name string | code string | asm string | file string |
|---|---|---|---|
llvm::Pass* llvm::callDefaultCtor<(anonymous namespace)::SILowerWWMCopies, true>() | Pass *callDefaultCtor() {
return new PassName();
} | pushq %rbx
subq $0x10, %rsp
movl $0x68, %edi
callq 0x7808d0
movq %rax, %rbx
xorl %eax, %eax
movq %rax, 0x8(%rbx)
leaq 0x4d55a95(%rip), %rcx # 0x5917d54
movq %rcx, 0x10(%rbx)
movl $0x2, 0x18(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rbx)
movq %rax, 0x30(%rbx)
leaq 0x4ba450c(%rip), %rax # 0x57667e8
movq %rax, (%rb... | /llvm/PassSupport.h |
copyRegOperand(llvm::MachineOperand&, llvm::MachineOperand const&) | static void copyRegOperand(MachineOperand &To, const MachineOperand &From) {
assert(To.isReg() && From.isReg());
To.setReg(From.getReg());
To.setSubReg(From.getSubReg());
To.setIsUndef(From.isUndef());
if (To.isUse()) {
To.setIsKill(From.isKill());
} else {
To.setIsDead(From.isDead());
}
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x4(%rsi), %esi
callq 0x1d531ce
movl $0xfff00, %ecx # imm = 0xFFF00
andl (%r14), %ecx
movl (%rbx), %edx
movl %edx, %eax
andl $0xfff000ff, %eax # imm = 0xFFF000FF
orl %ecx, %eax
movl %eax, (%rbx)
movl $0x10000000, %ecx # imm = 0x1... | /Target/AMDGPU/SIPeepholeSDWA.cpp |
getFlatScratchSpillOpcode(llvm::SIInstrInfo const*, unsigned int, unsigned int) | static unsigned getFlatScratchSpillOpcode(const SIInstrInfo *TII,
unsigned LoadStoreOp,
unsigned EltSize) {
bool IsStore = TII->get(LoadStoreOp).mayStore();
bool HasVAddr = AMDGPU::hasNamedOperand(LoadStoreOp, AMDGPU::OpName::vaddr)... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movl %edx, %r14d
movq 0x8(%rdi), %rax
movl %esi, %ecx
shlq $0x5, %rcx
negq %rcx
movq 0x10(%rax,%rcx), %r15
movzwl %si, %ebp
movl %ebp, %edi
movl $0x1, %esi
callq 0x19130e0
movl %eax, %ebx
cmpw $-0x1, %ax
je 0xbe98ae
xorl %eax, %eax
jmp 0xbe98c1
movl %ebp, %edi
movl... | /Target/AMDGPU/SIRegisterInfo.cpp |
void llvm::SmallVectorImpl<llvm::User*>::append<llvm::Value::user_iterator_impl<llvm::User>, void>(llvm::Value::user_iterator_impl<llvm::User>, llvm::Value::user_iterator_impl<llvm::User>) | void append(ItTy in_start, ItTy in_end) {
this->assertSafeToAddRange(in_start, in_end);
size_type NumInputs = std::distance(in_start, in_end);
this->reserve(this->size() + NumInputs);
this->uninitialized_copy(in_start, in_end, this->end());
this->set_size(this->size() + NumInputs);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
xorl %r12d, %r12d
cmpq %rdx, %rsi
je 0xbf991a
movq %r15, %rax
movq 0x8(%rax), %rax
incq %r12
cmpq %r14, %rax
jne 0xbf990e
movl 0x8(%rbx), %edx
movl 0xc(%rbx), %eax
addq %r12, %rdx
cmpq %rax, %rdx
jbe 0xbf9939
leaq 0x1... | /llvm/ADT/SmallVector.h |
buildMul(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&, llvm::Value*, llvm::Value*) | static Value *buildMul(IRBuilder<> &B, Value *LHS, Value *RHS) {
const ConstantInt *CI = dyn_cast<ConstantInt>(LHS);
return (CI && CI->isOne()) ? RHS : B.CreateMul(LHS, RHS);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x28, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
cmpb $0x11, (%rsi)
jne 0xbfdb59
leaq 0x18(%r14), %rdi
movl 0x20(%r14), %ebp
cmpl $0x40, %ebp
ja 0xbfdb49
cmpq $0x1, (%rdi)
jmp 0xbfdb52
callq 0x2b1284c
decl %ebp
cmpl %ebp, %eax
sete %al
testb %al, %al
jne 0xbfd... | /Target/AMDGPU/AMDGPUAtomicOptimizer.cpp |
llvm::AACallEdges& llvm::Attributor::registerAA<llvm::AACallEdges>(llvm::AACallEdges&) | AAType ®isterAA(AAType &AA) {
static_assert(std::is_base_of<AbstractAttribute, AAType>::value,
"Cannot register an attribute with a type not derived from "
"'AbstractAttribute'!");
// Put the attribute in the lookup map structure and the container we use to
// keep tra... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rsi, %rbx
movq %rdi, %r14
addq $0x68, %rdi
leaq 0x4351bae(%rip), %rax # 0x4f52c04
movq %rsp, %rsi
movq %rax, (%rsi)
movups 0x40(%rbx), %xmm0
movups %xmm0, 0x8(%rsi)
callq 0xc011ea
movq %rbx, 0x18(%rax)
cmpl $0x1, 0xd78(%r14)
ja 0xc0108c
addq $0xb0, %r14
movq %rsp, %rsi
mov... | /llvm/Transforms/IPO/Attributor.h |
bool llvm::function_ref<bool (llvm::Instruction&)>::callback_fn<(anonymous namespace)::AAAMDGPUNoAGPR::updateImpl(llvm::Attributor&)::'lambda'(llvm::Instruction&)>(long, llvm::Instruction&) | Ret operator()(Params ...params) const {
return callback(callable, std::forward<Params>(params)...);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movq -0x20(%rsi), %rax
movb (%rax), %bpl
testb %bpl, %bpl
je 0xc038eb
cmpb $0x19, %bpl
jne 0xc0393a
movq 0x38(%rax), %rsi
movq 0x40(%rax), %rdx
movq %rsp, %rbx
movq %rbx, %rdi
callq 0x2a4fb72
movq (%rbx), %rax
movq 0x8(%rbx), %rcx
cmpq %rcx, %rax
je 0xc0392f
... | /llvm/ADT/STLFunctionalExtras.h |
(anonymous namespace)::AMDGPUOutgoingArgHandler::getStackAddress(unsigned long, long, llvm::MachinePointerInfo&, llvm::ISD::ArgFlagsTy) | Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) override {
MachineFunction &MF = MIRBuilder.getMF();
const LLT PtrTy = LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32);
const LLT S32 = LLT::scalar(32);
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rcx, %rbx
movq %rdx, %r15
movq %rdi, %r12
movq 0x8(%rdi), %rdi
movq 0x8(%rdi), %r14
cmpb $0x1, 0x38(%r12)
jne 0xc0b0d5
movslq 0x30(%r12), %rdx
addq %r15, %rdx
movq 0x38(%r14), %rdi
movl $0x1, %ecx
xorl %r8d, %r8d
callq 0x1d32a60
mo... | /Target/AMDGPU/AMDGPUCallLowering.cpp |
llvm::IRBuilderBase::CreateSExtOrTrunc(llvm::Value*, llvm::Type*, llvm::Twine const&) | Value *CreateSExtOrTrunc(Value *V, Type *DestTy,
const Twine &Name = "") {
assert(V->getType()->isIntOrIntVectorTy() &&
DestTy->isIntOrIntVectorTy() &&
"Can only sign extend/truncate integers!");
Type *VTy = V->getType();
if (VTy->getScalarSizeInBits() < Dest... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq 0x8(%rsi), %rdi
callq 0x2a9a8f4
movl %eax, %ebp
movq %r14, %rdi
callq 0x2a9a8f4
cmpl %eax, %ebp
jae 0xc1034d
movq %r12, %rdi
movl $0x28, %esi
movq %r15, %rdx
movq %r14, %rcx
movq %rbx, %r8
popq %r... | /llvm/IR/IRBuilder.h |
(anonymous namespace)::AMDGPUCodeGenPrepareImpl::emitRcpIEEE1ULP(llvm::IRBuilder<llvm::ConstantFolder, llvm::IRBuilderDefaultInserter>&, llvm::Value*, bool) const | Value *AMDGPUCodeGenPrepareImpl::emitRcpIEEE1ULP(IRBuilder<> &Builder,
Value *Src,
bool IsNegative) const {
// Same as for 1.0, but expand the sign out of the constant.
// -1.0 / x -> rcp (fneg x)
if (IsNegative)
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rsi, %rbx
movq %rdi, %r14
testl %ecx, %ecx
je 0xc10ff8
leaq 0x10(%rsp), %rax
movw $0x101, 0x20(%rax) # imm = 0x101
movq %rbx, %rdi
movq %rdx, %rsi
movq %rax, %rdx
xorl %ecx, %ecx
callq 0xc10d50
movq %rax, %rdx
movq %r14, %rdi
... | /Target/AMDGPU/AMDGPUCodeGenPrepare.cpp |
llvm::IRBuilderBase::SetInsertPoint(llvm::ilist_iterator_w_bits<llvm::ilist_detail::node_options<llvm::Instruction, false, false, void, true, llvm::BasicBlock>, false, false>) | void SetInsertPoint(BasicBlock::iterator IP) {
BB = IP->getParent();
InsertPt = IP;
SetCurrentDebugLocation(IP->getStableDebugLoc());
} | pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq -0x18(%rsi), %rdi
testq %rsi, %rsi
cmoveq %rsi, %rdi
movq 0x28(%rdi), %rax
movq %rax, 0x30(%rbx)
movq %rsi, 0x38(%rbx)
movw %dx, 0x40(%rbx)
callq 0x2a5311a
movq (%rax), %rsi
movq %rsi, 0x8(%rsp)
testq %rsi, %rsi
je 0xc114b8
leaq 0x8(%rsp), %rdi
movl $0x1, %edx
callq 0x2a... | /llvm/IR/IRBuilder.h |
(anonymous namespace)::AMDGPUGlobalISelDivergenceLowering::AMDGPUGlobalISelDivergenceLowering() | AMDGPUGlobalISelDivergenceLowering() : MachineFunctionPass(ID) {
initializeAMDGPUGlobalISelDivergenceLoweringPass(
*PassRegistry::getPassRegistry());
} | pushq %rax
xorl %eax, %eax
movq %rax, 0x8(%rdi)
leaq 0x4d043c4(%rip), %rcx # 0x59191e8
movq %rcx, 0x10(%rdi)
movl $0x2, 0x18(%rdi)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rdi)
movq %rax, 0x30(%rdi)
leaq 0x4b6ac3f(%rip), %rax # 0x577fa80
movq %rax, (%rdi)
callq 0x2a9031c
movq %rsp, %rdx
movq %rax, (%rdx)
leaq 0x4d043... | /Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp |
llvm::Incoming& llvm::SmallVectorTemplateBase<llvm::Incoming, true>::growAndEmplaceBack<llvm::Register, llvm::MachineBasicBlock*, llvm::Register>(llvm::Register&&, llvm::MachineBasicBlock*&&, llvm::Register&&) | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Use push_back with a copy in case Args has an internal reference,
// side-stepping reference invalidation problems without losing the realloc
// optimization.
push_back(T(std::forward<ArgTypes>(Args)...));
return this->back();
} | pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movl (%rsi), %eax
movq (%rdx), %rdx
movl (%rcx), %ecx
leaq 0x8(%rsp), %rsi
movl %eax, (%rsi)
movq %rdx, 0x8(%rsi)
movl %ecx, 0x10(%rsi)
movl $0x1, %edx
callq 0xbc0d7c
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
movq 0x10(%rax), %rsi
movq %rsi, 0x10(%rcx,%r... | /llvm/ADT/SmallVector.h |
void llvm::SmallVectorImpl<llvm::Value*>::append<llvm::Use*, void>(llvm::Use*, llvm::Use*) | void append(ItTy in_start, ItTy in_end) {
this->assertSafeToAddRange(in_start, in_end);
size_type NumInputs = std::distance(in_start, in_end);
this->reserve(this->size() + NumInputs);
this->uninitialized_copy(in_start, in_end, this->end());
this->set_size(this->size() + NumInputs);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq %rdx, %r12
subq %rsi, %r12
sarq $0x5, %r12
movl 0x8(%rdi), %edx
movl 0xc(%rdi), %eax
addq %r12, %rdx
cmpq %rax, %rdx
jbe 0xc1b404
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
callq 0x2b4ed86
movl 0x8(%rb... | /llvm/ADT/SmallVector.h |
llvm::AMDGPUInstructionSelector::selectSWMMACIndex16(llvm::MachineOperand&) const | InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectSWMMACIndex16(MachineOperand &Root) const {
Register Src =
getDefIgnoringCopies(Root.getReg(), *MRI)->getOperand(0).getReg();
unsigned Key = 0;
Register ShiftSrc;
std::optional<ValueAndVReg> ShiftAmt;
if (mi_match(Src, *MRI, m_GL... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movq %rsi, %r14
movq %rdi, %rbx
movl 0x4(%rdx), %edi
movq 0x48(%rsi), %rsi
callq 0x15e5c06
movq 0x20(%rax), %rax
movl 0x4(%rax), %ebp
leaq 0x4(%rsp), %rax
movl $0x0, (%rax)
leaq 0x8(%rsp), %r15
movb $0x0, 0x18(%r15)
movq 0x48(%r14), ... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectGlobalLoadLds(llvm::MachineInstr&) const | bool AMDGPUInstructionSelector::selectGlobalLoadLds(MachineInstr &MI) const{
unsigned Opc;
unsigned Size = MI.getOperand(3).getImm();
switch (Size) {
default:
return false;
case 1:
Opc = AMDGPU::GLOBAL_LOAD_LDS_UBYTE;
break;
case 2:
Opc = AMDGPU::GLOBAL_LOAD_LDS_USHORT;
break;
case 4:... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movq 0x20(%rsi), %rax
movq 0x70(%rax), %r13
cmpl $0x1, %r13d
je 0xc30005
cmpl $0x4, %r13d
je 0xc2fffb
cmpl $0x2, %r13d
jne 0xc30148
movl $0xdcc, 0x30(%rsp) # imm = 0xDCC
jmp 0xc3000d
movl $0xdc4, 0x30... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectG_SELECT(llvm::MachineInstr&) const | bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
if (selectImpl(I, *CoverageInfo))
return true;
MachineBasicBlock *BB = I.getParent();
const DebugLoc &DL = I.getDebugLoc();
Register DstReg = I.getOperand(0).getReg();
unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI);
assert(S... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x8(%rdi), %rdx
callq 0xc22914
movb $0x1, %bpl
testb %al, %al
jne 0xc31518
movq 0x18(%rbx), %rax
movq %rax, (%rsp)
movq 0x20(%rbx), %rax
movl 0x4(%rax), %r13d
movq 0x68(%r14), %rdi
movq 0x48(%r14), %r... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectG_BRCOND(llvm::MachineInstr&) const | bool AMDGPUInstructionSelector::selectG_BRCOND(MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
MachineOperand &CondOp = I.getOperand(0);
Register CondReg = CondOp.getReg();
const DebugLoc &DL = I.getDebugLoc();
unsigned BrOpcode;
Register CondPhysReg;
const TargetRegisterClass *ConstrainR... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %rsi, %rbx
movq %rdi, %r15
movq 0x18(%rsi), %r12
movq 0x20(%rsi), %rax
movl 0x4(%rax), %r13d
movq 0x48(%rdi), %rdx
movl %r13d, %esi
callq 0xc270e2
movq 0x48(%r15), %rsi
testb %al, %al
je 0xc34d21
movl %r13d, %edi
callq 0xc35113
test... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
isVCmpResult(llvm::Register, llvm::MachineRegisterInfo&) | static bool isVCmpResult(Register Reg, MachineRegisterInfo &MRI) {
if (Reg.isPhysical())
return false;
MachineInstr &MI = *MRI.getUniqueVRegDef(Reg);
const unsigned Opcode = MI.getOpcode();
if (Opcode == AMDGPU::COPY)
return isVCmpResult(MI.getOperand(1).getReg(), MRI);
if (Opcode == AMDGPU::G_AND ... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movl %edi, %esi
leal -0x1(%rsi), %eax
cmpl $0x3fffffff, %eax # imm = 0x3FFFFFFF
jb 0xc3516b
movq %rbx, %rdi
callq 0x1d835be
movq %rax, %r14
movzwl 0x44(%rax), %r15d
leal -0x3c(%r15), %eax
cmpl $0x3, %eax
jae 0xc3515c
movq 0x20(%r14), %rax
movl 0x24(%rax), %edi
movq... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::selectStackRestore(llvm::MachineInstr&) const | bool AMDGPUInstructionSelector::selectStackRestore(MachineInstr &MI) const {
Register SrcReg = MI.getOperand(0).getReg();
if (!RBI.constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, *MRI))
return false;
MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
Register SP =
Subtarget->getTargetLowering()... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %rsi, %rbx
movq %rdi, %r15
movq 0x20(%rsi), %rax
movl 0x4(%rax), %r12d
movq 0x48(%rdi), %rdx
leaq 0x4b30d6f(%rip), %rsi # 0x57681c0
movl %r12d, %edi
callq 0x1e296b2
movq %rax, %r13
testq %rax, %rax
je 0xc376d8
movq 0x48(%r15), %rd... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
buildRegSequence(llvm::SmallVectorImpl<llvm::Register>&, llvm::MachineInstr*, llvm::MachineRegisterInfo&) | static Register buildRegSequence(SmallVectorImpl<Register> &Elts,
MachineInstr *InsertPt,
MachineRegisterInfo &MRI) {
const TargetRegisterClass *DstRegClass;
switch (Elts.size()) {
case 8:
DstRegClass = &AMDGPU::VReg_256RegClass;
break;
c... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rdx, %r12
movq %rdi, %rbx
movslq 0x8(%rdi), %rax
leaq 0x4b47d38(%rip), %rcx # 0x577fcb8
movq -0x10(%rcx,%rax,8), %r13
leaq 0x20(%rsp), %r14
movq %r14, %rdi
callq 0x94cecc
movq %r14, %rdi
movl $0x12, %esi
callq 0x15dd5c4
movq %r14... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::getPtrBaseWithConstantOffset(llvm::Register, llvm::MachineRegisterInfo const&) const | std::pair<Register, int64_t>
AMDGPUInstructionSelector::getPtrBaseWithConstantOffset(
Register Root, const MachineRegisterInfo &MRI) const {
MachineInstr *RootI = getDefIgnoringCopies(Root, MRI);
if (RootI->getOpcode() != TargetOpcode::G_PTR_ADD)
return {Root, 0};
MachineOperand &RHS = RootI->getOperand(2)... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, %r15
movl %esi, %ebx
movl %esi, %edi
movq %rdx, %rsi
callq 0x15e5c06
cmpw $0xd4, 0x44(%rax)
jne 0xc38556
movq %rax, %r14
movq 0x20(%rax), %rax
movl 0x44(%rax), %esi
leaq 0x8(%rsp), %r12
movq %r12, %rdi
movq %r15, %rdx
movl $0x1, %ecx
callq 0x15e51f... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
llvm::AMDGPUInstructionSelector::isFlatScratchBaseLegalSV(llvm::Register) const | bool AMDGPUInstructionSelector::isFlatScratchBaseLegalSV(Register Addr) const {
MachineInstr *AddrMI = getDefIgnoringCopies(Addr, *MRI);
if (isNoUnsignedWrap(AddrMI))
return true;
// Starting with GFX12, VADDR and SADDR fields in VSCRATCH can use negative
// values.
if (STI.hasSignedScratchOffsets())
... | pushq %rbp
pushq %rbx
pushq %rax
movl %esi, %eax
movq %rdi, %rbx
movq 0x48(%rdi), %rsi
movl %eax, %edi
callq 0x15e5c06
movq %rax, %rcx
movzwl 0x44(%rax), %edx
movb $0x1, %al
cmpl $0x3d, %edx
je 0xc38a56
cmpl $0xd4, %edx
jne 0xc38a1f
testb $0x8, 0x2d(%rcx)
jne 0xc38a56
movq 0x78(%rbx), %rdx
cmpl $0xa, 0x1f8(%rdx)
jg 0xc... | /Target/AMDGPU/AMDGPUInstructionSelector.cpp |
bool llvm::MIPatternMatch::BinaryOp_match<llvm::MIPatternMatch::bind_ty<llvm::Register>, llvm::MIPatternMatch::Or<llvm::MIPatternMatch::ConstantMatch<long>, llvm::MIPatternMatch::UnaryOp_match<llvm::MIPatternMatch::ConstantMatch<long>, 19u>>, 212u, false>::match<llvm::Register&>(llvm::MachineRegisterInfo const&, llvm::... | bool match(const MachineRegisterInfo &MRI, OpTy &&Op) {
MachineInstr *TmpMI;
if (mi_match(Op, MRI, m_MInstr(TmpMI))) {
if (TmpMI->getOpcode() == Opcode && TmpMI->getNumOperands() == 3) {
return (L.match(MRI, TmpMI->getOperand(1).getReg()) &&
R.match(MRI, TmpMI->getOperand(2).getReg... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movl (%rdx), %esi
movq %rbx, %rdi
callq 0x1d835a8
testq %rax, %rax
je 0xc3c5ea
cmpw $0xd4, 0x44(%rax)
jne 0xc3c5ea
movzwl 0x28(%rax), %ecx
movzbl 0x2a(%rax), %edx
shll $0x10, %edx
orl %ecx, %edx
cmpl $0x3, %edx
jne 0xc3c5ea
movq 0x20(%rax), %rax
movl 0x24... | /llvm/CodeGen/GlobalISel/MIPatternMatch.h |
AMDGPUDAGToDAGISel::getHi16Elt(llvm::SDValue) const | SDValue AMDGPUDAGToDAGISel::getHi16Elt(SDValue In) const {
if (In.isUndef())
return CurDAG->getUNDEF(MVT::i32);
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(In)) {
SDLoc SL(In);
return CurDAG->getConstant(C->getZExtValue() << 16, SL, MVT::i32);
}
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSD... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movl 0x18(%rsi), %eax
cmpl $0xb, %eax
je 0xc3d7b5
cmpl $0x23, %eax
je 0xc3d7b5
cmpl $0x33, %eax
jne 0xc3d7ba
movq 0x38(%r14), %rdi
movl $0x7, %esi
xorl %edx, %edx
callq 0x9fbc02
movq %rax, %r12
movl %edx, ... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectMAD_64_32(llvm::SDNode*) | void AMDGPUDAGToDAGISel::SelectMAD_64_32(SDNode *N) {
SDLoc SL(N);
bool Signed = N->getOpcode() == AMDGPUISD::MAD_I64_I32;
unsigned Opc;
if (Subtarget->hasMADIntraFwdBug())
Opc = Signed ? AMDGPU::V_MAD_I64_I32_gfx11_e64
: AMDGPU::V_MAD_U64_U32_gfx11_e64;
else
Opc = Signed ? AMDGPU::V_... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x78, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x10(%rsp)
testq %rsi, %rsi
je 0xc3fcaf
leaq 0x10(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbx), %eax
leaq 0x10(%rsp), %r15
movl %eax, 0x8(%r15)
cmpl $0x22d, 0x18(%rbx) # imm ... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectS_BFE(llvm::SDNode*) | void AMDGPUDAGToDAGISel::SelectS_BFE(SDNode *N) {
switch (N->getOpcode()) {
case ISD::AND:
if (N->getOperand(0).getOpcode() == ISD::SRL) {
// "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
// Predicate: isMask(mask)
const SDValue &Srl = N->getOperand(0);
ConstantSDNode *Shift = d... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movl 0x18(%rsi), %eax
cmpl $0xbe, %eax
jg 0xc40073
cmpl $0xb9, %eax
je 0xc400f4
cmpl $0xbe, %eax
jne 0xc40363
movq 0x28(%rbx), %rax
movq (%rax), %rax
cmpl $0xbd, 0x18(%rax)
je 0xc401cd
jmp 0xc40363
cmpl $0... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectScratchSVAddr(llvm::SDNode*, llvm::SDValue, llvm::SDValue&, llvm::SDValue&, llvm::SDValue&) const | bool AMDGPUDAGToDAGISel::SelectScratchSVAddr(SDNode *N, SDValue Addr,
SDValue &VAddr, SDValue &SAddr,
SDValue &Offset) const {
int64_t ImmOffset = 0;
SDValue LHS, RHS;
SDValue OrigAddr = Addr;
if (isBaseWithConstantOffse... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %r9, %rbp
movq %r8, 0x68(%rsp)
movl %ecx, %r14d
movq %rdx, %r12
movq %rsi, 0x38(%rsp)
movq 0xd0(%rsp), %r15
xorl %ebx, %ebx
leaq 0x50(%rsp), %r13
movq %rbx, (%r13)
movl %ebx, 0x8(%r13)
leaq 0x40(%rsp), %r8
movq %rbx, (%r8)
movl %ebx... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectMOVRELOffset(llvm::SDValue, llvm::SDValue&, llvm::SDValue&) const | bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
SDValue &Base,
SDValue &Offset) const {
SDLoc DL(Index);
if (CurDAG->isBaseWithConstantOffset(Index)) {
SDValue N0 = Index.getOperand(0);
SDValue N1 = Index.get... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r8, 0x20(%rsp)
movq %rcx, %r14
movl %edx, %ebp
movq %rsi, %r12
movq %rdi, %r15
movq 0x48(%rsi), %rsi
movq %rsi, 0x10(%rsp)
testq %rsi, %rsi
je 0xc45433
leaq 0x10(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r12), %eax
mov... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
buildRegSequence16(llvm::SmallVectorImpl<llvm::SDValue>&, llvm::SelectionDAG*, llvm::SDLoc const&) | static MachineSDNode *buildRegSequence16(SmallVectorImpl<SDValue> &Elts,
llvm::SelectionDAG *CurDAG,
const SDLoc &DL) {
SmallVector<SDValue, 8> PackedElts;
assert("unhandled Reg sequence size" &&
(Elts.size() == 8 || Elts.siz... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x108, %rsp # imm = 0x108
movq %rdx, 0x20(%rsp)
movq %rsi, 0x18(%rsp)
leaq 0x88(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, -0x8(%rcx)
cmpl $0x0, 0x8(%rdi)
je 0xc47557
movq %rdi, %r15... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
AMDGPUDAGToDAGISel::SelectWMMAModsF32NegAbs(llvm::SDValue, llvm::SDValue&, llvm::SDValue&) const | bool AMDGPUDAGToDAGISel::SelectWMMAModsF32NegAbs(SDValue In, SDValue &Src,
SDValue &SrcMods) const {
Src = In;
unsigned Mods = SISrcMods::OP_SEL_1;
SmallVector<SDValue, 8> EltsF32;
if (auto *BV = dyn_cast<BuildVectorSDNode>(stripBitcast(In))) {
assert(BV->ge... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %r8, 0x30(%rsp)
movq %rsi, %rbx
movq %rdi, %r15
movq %rsi, (%rcx)
movl %edx, 0x8(%rcx)
movl $0x8, 0xc(%rsp)
leaq 0x48(%rsp), %r13
movq %r13, -0x10(%r13)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, -0x8(%r13)
cmpl ... | /Target/AMDGPU/AMDGPUISelDAGToDAG.cpp |
llvm::AMDGPUTargetLowering::LowerOperation(llvm::SDValue, llvm::SelectionDAG&) const | SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) {
default:
Op->print(errs(), &DAG);
llvm_unreachable("Custom lowering code for this "
"instruction is not implemented yet!");
brea... | pushq %r14
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rsi, %r14
movl 0x18(%rsi), %eax
cmpl $0xd7, %eax
jle 0xc4faa3
leal -0x101(%rax), %ecx
cmpl $0x22, %ecx
ja 0xc4faf6
leaq 0x2b498c8(%rip), %rax # 0x3799350
movslq (%rax,%rcx,4), %rcx
addq %rax, %rcx
jmpq *%rcx
movq %r14, %rsi
movq %rbx, %rcx
addq $0x8, %rsp
popq %r... | /Target/AMDGPU/AMDGPUISelLowering.cpp |
llvm::SmallPtrSetImpl<llvm::Value*>::insert(llvm::Value*) | std::pair<iterator, bool> insert(PtrType Ptr) {
auto p = insert_imp(PtrTraits::getAsVoidPointer(Ptr));
return std::make_pair(makeIterator(p.first), p.second);
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq %rsi, %rdi
movq %rdx, %rsi
callq 0x91dbe2
movq 0x8(%r14), %rcx
xorl %esi, %esi
cmpq (%r14), %rcx
sete %sil
movl 0x10(%r14,%rsi,4), %esi
leaq (%rcx,%rsi,8), %rcx
cmpq %rax, %rcx
je 0xc688cb
cmpq $-0x2, (%rax)
jb 0xc688cb
addq $0x8, %rax
cmpq %rcx, %ra... | /llvm/ADT/SmallPtrSet.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value*>>, llvm::Value const*, llvm::Value*, llvm::DenseMapInfo<llvm::Value const*, void>, llvm::detail::DenseMapPair<llvm::Value const*, llvm::Value... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0xc68a0d
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movq (%rdi,%rbx), %rbx
cmpq %rbx, (%rsi)
jne... | /llvm/ADT/DenseMap.h |
llvm::AMDGPULegalizerInfo::legalizeFlog2(llvm::MachineInstr&, llvm::MachineIRBuilder&) const | bool AMDGPULegalizerInfo::legalizeFlog2(MachineInstr &MI,
MachineIRBuilder &B) const {
// v_log_f32 is good enough for OpenCL, except it doesn't handle denormals.
// If we have to handle denormals, scale up the input and adjust the result.
// scaled = x * (is_denormal ? 0x... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %rdx, %rdi
movq %rsi, %rbx
movq 0x20(%rsi), %rax
movl 0x4(%rax), %esi
testl %esi, %esi
jns 0xc74301
movq 0x18(%rdi), %rcx
movl %esi, %edx
andl $0x7fffffff, %edx # imm = 0x7FFFFFFF
cmpl %edx, 0x1d0(%rcx)
jbe 0xc74301
movq 0x1c8... | /Target/AMDGPU/AMDGPULegalizerInfo.cpp |
llvm::AMDGPULibCalls::fold(llvm::CallInst*) | bool AMDGPULibCalls::fold(CallInst *CI) {
Function *Callee = CI->getCalledFunction();
// Ignore indirect calls.
if (!Callee || Callee->isIntrinsic() || CI->isNoBuiltin())
return false;
FuncInfo FInfo;
if (!parseFunctionName(Callee->getName(), FInfo))
return false;
// Further check the number of ar... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xf8, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq -0x20(%rsi), %rax
xorl %r12d, %r12d
testq %rax, %rax
je 0xc8a2e4
cmpb $0x0, (%rax)
cmoveq %rax, %r12
testq %r12, %r12
je 0xc8a2f4
movq 0x18(%r12), %rax
cmpq 0x50(%rbx), %rax
je 0xc8a2f7
xorl %r12d, %r... | /Target/AMDGPU/AMDGPULibCalls.cpp |
(anonymous namespace)::AMDGPUMachineCFGStructurizer::initFallthroughMap(llvm::MachineFunction&) | void AMDGPUMachineCFGStructurizer::initFallthroughMap(MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "Fallthrough Map:\n");
for (auto &MBBI : MF) {
MachineBasicBlock *MBB = MBBI.getFallThrough();
if (MBB != nullptr) {
LLVM_DEBUG(dbgs() << "Fallthrough: " << MBBI.getNumber() << " -> "
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq 0x148(%rsi), %r15
addq $0x140, %rbx # imm = 0x140
cmpq %rbx, %r15
je 0xca310f
movq %rdi, %r14
addq $0x88, %r14
leaq 0x8(%rsp), %r12
movq %r15, %rdi
movl $0x1, %esi
callq 0x1cfd2e4
movq %rax, %r13
movq %r15, 0x8(%rsp)... | /Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp |
llvm::DenseMapBase<llvm::DenseMap<std::pair<unsigned int, llvm::MachineBasicBlock*>, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<std::pair<unsigned int, llvm::MachineBasicBlock*>, void>, llvm::detail::DenseSetPair<std::pair<unsigned int, llvm::MachineBasicBlock*>>>, std::pair<unsigned int, llvm::MachineBasicBlock*>... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %eax
testq %rax, %rax
je 0xca7c3c
movq (%r15), %rcx
shlq $0x4, %rax
addq %rcx, %rax
movl $0xffffffff, (%rcx) # imm = 0xFFFFFFFF
movq $-0x1000, 0x8(%rcx) # imm = 0xF000
add... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<std::pair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>, llvm::detail::DenseSetEmpty, llvm::DenseMapInfo<std::pair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>, void>, llvm::detail::DenseSetPair<std::pair<llvm::MachineBasicBlock*, llvm::MachineBasicBlock*>>>, std::pair<llv... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %eax
testq %rax, %rax
je 0xca97a3
movq (%r15), %rcx
shlq $0x4, %rax
addq %rcx, %rax
movq $-0x1000, %rdx # imm = 0xF000
movq %rdx, (%rcx)
movq %rdx, ... | /llvm/ADT/DenseMap.h |
(anonymous namespace)::SchedGroup::canAddMI(llvm::MachineInstr const&) const | bool PipelineSolver::checkOptimal() {
if (static_cast<size_t>(CurrSyncGroupIdx) == PipelineInstrs.size()) {
if (BestCost == -1 || CurrCost < BestCost) {
BestPipeline = CurrPipeline;
BestCost = CurrCost;
LLVM_DEBUG(dbgs() << "Found Fit with cost " << BestCost << "\n");
}
assert(BestCost >... | pushq %r14
pushq %rbx
pushq %rax
movq 0x10(%rsi), %rdx
testb $0x10, 0x10(%rdx)
jne 0xcac679
movq %rsi, %rbx
movq %rdi, %r14
movl (%rdi), %ecx
testb $0x1, %cl
jne 0xcac683
testb $0x2, %cl
je 0xcac528
movq 0x18(%rdx), %rsi
testb $0x2, %sil
jne 0xcac6c6
testb $0x4, %cl
je 0xcac539
movb $0x1, %al
testb $0x1, 0x18(%rdx)
jne... | /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::MFMASmallGemmSingleWaveOpt::EnablesInitialMFMA::~EnablesInitialMFMA() | bool apply(const SUnit *SU, const ArrayRef<SUnit *> Collection,
SmallVectorImpl<SchedGroup> &SyncPipe) override {
if (!SyncPipe.size())
return false;
int MFMAsFound = 0;
if (!Cache->size()) {
for (auto &Elt : SyncPipe[0].DAG->SUnits) {
if (TII->isMFMAorWMMA(*El... | pushq %rbx
movq %rdi, %rbx
leaq 0x4ad1c8f(%rip), %rax # 0x5781f40
movq %rax, (%rdi)
cmpb $0x1, 0x48(%rdi)
jne 0xcb02d0
movb $0x0, 0x48(%rbx)
movq 0x18(%rbx), %rdi
leaq 0x28(%rbx), %rax
cmpq %rax, %rdi
je 0xcb02d0
callq 0x780910
movl $0x50, %esi
movq %rbx, %rdi
popq %rbx
jmp 0x7800d0
| /Target/AMDGPU/AMDGPUIGroupLP.cpp |
(anonymous namespace)::AMDGPUOpenCLEnqueuedBlockLowering::runOnModule(llvm::Module&) | bool AMDGPUOpenCLEnqueuedBlockLowering::runOnModule(Module &M) {
DenseSet<Function *> Callers;
auto &C = M.getContext();
bool Changed = false;
// ptr kernel_object, i32 private_segment_size, i32 group_segment_size
StructType *HandleTy = nullptr;
for (auto &F : M.functions()) {
if (F.hasFnAttribute("en... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq 0x20(%rsi), %rbx
leaq 0x18(%rsi), %r13
cmpq %r13, %rbx
je 0xcb9d84
movq (%rsi), %rax
movq %rax, 0x8(%rsp)
movq %rsi, 0x20(%rsp)
leaq 0x120(%rsi), %rax
movq %rax, 0x10(%rsp)
xorl %r14d, %r14d
leaq 0x28(%rsp), %rbp
xorl %r15d, %r15d
m... | /Target/AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Function const*, llvm::AMDGPUPerfHintAnalysis::FuncInfo, llvm::ValueMapConfig<llvm::Function const*, llvm::sys::SmartMutex<false>>>, llvm::AMDGPUPerfHintAnalysis::FuncInfo, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Function const*, llvm::AMDGPUPer... | void erase(iterator I) {
BucketT *TheBucket = &*I;
TheBucket->getSecond().~ValueT();
TheBucket->getFirst() = getTombstoneKey();
decrementNumEntries();
incrementNumTombstones();
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %r15
movq %rdi, %rbx
leaq 0x8(%rsp), %r14
movq $0x2, (%r14)
xorl %eax, %eax
movq %rax, 0x8(%r14)
movq $-0x2000, %r12 # imm = 0xE000
movq %r12, 0x10(%r14)
leaq 0x4ac77b7(%rip), %rcx # 0x5782928
movq %rcx, -0x8(%r14)
movq %rax, 0x18(%r14)
... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::BasicBlock*, llvm::SmallDenseSet<llvm::Instruction*, 4u, llvm::DenseMapInfo<llvm::Instruction*, void>>, llvm::DenseMapInfo<llvm::BasicBlock*, void>, llvm::detail::DenseMapPair<llvm::BasicBlock*, llvm::SmallDenseSet<llvm::Instruction*, 4u, llvm::DenseMapInfo<llvm::Instruction*, vo... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %eax
testq %rax, %rax
je 0xcd1f7c
movq (%r15), %rcx
leaq (%rax,%rax,2), %rax
shlq $0x4, %rax
addq $-0x30, %rax
movabsq $-0x5555555555555555, %rdx # imm = 0xAAAAAA... | /llvm/ADT/DenseMap.h |
llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(llvm::MachineIRBuilder&, llvm::iterator_range<llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>>, llvm::SmallSet<llvm::Register, 4u, std::less<llvm::Register>>&) const | bool AMDGPURegisterBankInfo::executeInWaterfallLoop(
MachineIRBuilder &B, iterator_range<MachineBasicBlock::iterator> Range,
SmallSet<Register, 4> &SGPROperandRegs) const {
// Track use registers which have already been expanded with a readfirstlane
// sequence. This may have multiple uses if moving a seque... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1e8, %rsp # imm = 0x1E8
movq %r8, 0x100(%rsp)
movq %rcx, 0x78(%rsp)
movq %rdx, 0x60(%rsp)
movq %rsi, %r12
xorps %xmm0, %xmm0
movaps %xmm0, 0x110(%rsp)
movl $0x0, 0x120(%rsp)
movq 0x38(%rsi), %rax
movq %rax, 0xa0(%rsp)
movq 0xa0(%rdi), ... | /Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
substituteSimpleCopyRegs(llvm::RegisterBankInfo::OperandsMapper const&, unsigned int) | static bool substituteSimpleCopyRegs(
const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper, unsigned OpIdx) {
SmallVector<unsigned, 1> SrcReg(OpdMapper.getVRegs(OpIdx));
if (!SrcReg.empty()) {
assert(SrcReg.size() == 1);
OpdMapper.getMI().getOperand(OpIdx).setReg(SrcReg[0]);
return true;
}
ret... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x20, %rsp
movl %esi, %ebx
movq %rdi, %r14
xorl %edx, %edx
callq 0x1e2a2f8
leaq 0x18(%rsp), %r12
movq %r12, -0x10(%r12)
movabsq $0x100000000, %rcx # imm = 0x100000000
movq %rcx, -0x8(%r12)
leaq 0x8(%rsp), %r15
movq %r15, %rdi
movq %rax, %rsi
callq 0xceb3... | /Target/AMDGPU/AMDGPURegisterBankInfo.cpp |
HazardFnResult llvm::function_ref<HazardFnResult (llvm::GCNHazardRecognizer::fixVALUPartialForwardingHazard(llvm::MachineInstr*)::StateType&, llvm::MachineInstr const&)>::callback_fn<llvm::GCNHazardRecognizer::fixVALUPartialForwardingHazard(llvm::MachineInstr*)::$_0>(long, llvm::GCNHazardRecognizer::fixVALUPartialForwa... | static Ret callback_fn(intptr_t callable, Params ...params) {
return (*reinterpret_cast<Callable*>(callable))(
std::forward<Params>(params)...);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl $0x1, %ebp
cmpl $0x8, 0x2c(%rsi)
jg 0xcff539
movq %rdx, %r14
movq 0x10(%rdx), %rax
movzwl 0x1a(%rax), %eax
testl $0x3f6, %eax # imm = 0x3F6
je 0xcff54a
movl %ebp, %eax
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %... | /llvm/ADT/STLFunctionalExtras.h |
llvm::R600SchedStrategy::LoadAlu() | void R600SchedStrategy::LoadAlu() {
std::vector<SUnit *> &QSrc = Pending[IDAlu];
for (SUnit *SU : QSrc) {
AluKind AK = getAluKind(SU);
AvailableAlus[AK].push_back(SU);
}
QSrc.clear();
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
movq 0x70(%rdi), %r15
movq 0x78(%rdi), %r12
cmpq %r12, %r15
je 0xd03cf2
leaq 0xb8(%rbx), %r13
leaq 0x8(%rsp), %r14
movq (%r15), %rsi
movq %rsi, 0x8(%rsp)
movq %rbx, %rdi
callq 0xd037f8
movl %eax, %eax
leaq (%rax,%rax,2), %rax
leaq (... | /Target/AMDGPU/R600MachineScheduler.cpp |
llvm::ARMConstantPoolMBB::print(llvm::raw_ostream&) const | void ARMConstantPoolMBB::print(raw_ostream &O) const {
O << printMBBReference(*MBB);
ARMConstantPoolValue::print(O);
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rdi), %rsi
movq %rsp, %r15
movq %r15, %rdi
callq 0x1cfab69
cmpq $0x0, 0x10(%r15)
je 0xd2aef3
movq %rsp, %r15
movq %r15, %rdi
movq %rbx, %rsi
callq *0x18(%r15)
movq 0x10(%r15), %rax
testq %rax, %rax
je 0xd2aede
movq %rsp, %rdi
m... | /Target/ARM/ARMConstantPoolValue.cpp |
llvm::ARMTTIImpl::getShuffleCost(llvm::TargetTransformInfo::ShuffleKind, llvm::VectorType*, llvm::ArrayRef<int>, llvm::TargetTransformInfo::TargetCostKind, int, llvm::VectorType*, llvm::ArrayRef<llvm::Value const*>, llvm::Instruction const*) | InstructionCost ARMTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
VectorType *Tp, ArrayRef<int> Mask,
TTI::TargetCostKind CostKind,
int Index, VectorType *SubTp,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movl %r9d, 0x5c(%rsp)
movq %rdx, %r12
movq %rdi, %r13
leaq 0xc8(%rsp), %rax
movq %rax, (%rsp)
leaq 0xc0(%rsp), %r9
movq %rcx, 0x38(%rsp)
movq %rcx, %rdx
movq %r8, 0x30(%rsp)
movq %r8, %rcx
movq %r12, %r8
callq 0xd4ed3e
cmpl $0x5, %eax
mo... | /Target/ARM/ARMTargetTransformInfo.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::Value*, llvm::SCEVWrapPredicate::IncrementWrapFlags, llvm::ValueMapConfig<llvm::Value*, llvm::sys::SmartMutex<false>>>, llvm::SCEVWrapPredicate::IncrementWrapFlags, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Value*, llvm::SCEVWrapPredicate::Increme... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %eax
testq %rax, %rax
je 0xd54ecf
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
leaq 0x38(%rsp), %rbx
movl $0x2, %ecx
movq %rcx, (%rbx)
xorl %r15d, %r15d
movq %r15, 0x8(%rbx)
movq $-0x1000, 0x10(%rbx) # imm = 0xF000
leaq 0x4a35e73(%rip), %rdx # 0x578ac90
movq %... | /llvm/ADT/DenseMap.h |
void llvm::cl::apply<llvm::cl::opt<llvm::TailPredication::Mode, false, llvm::cl::parser<llvm::TailPredication::Mode>>, char [17], llvm::cl::desc, llvm::cl::initializer<llvm::TailPredication::Mode>, llvm::cl::ValuesClass>(llvm::cl::opt<llvm::TailPredication::Mode, false, llvm::cl::parser<llvm::TailPredication::Mode>>*, ... | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movq %rsi, %rdi
callq 0x7802c0
movq %r13, %rdi
movq %r12, %rsi
movq %rax, %rdx
callq 0x2b1f336
movups (%r15), %xmm0
movups %xmm0, 0x20(%r13)
movq (%r14), %rax
movl (%rax), %ecx
movl %ecx... | /llvm/Support/CommandLine.h |
LowerEXTRACT_SUBVECTOR(llvm::SDValue, llvm::SelectionDAG&, llvm::ARMSubtarget const*) | static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *ST) {
SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1);
SDLoc dl(Op);
EVT VT = Op.getValueType();
EVT Op1VT = V1.getValueType();
unsigned NumElts = VT.getVectorNumElemen... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1b8, %rsp # imm = 0x1B8
movq %rdx, 0x40(%rsp)
movl %esi, %ebx
movq %rdi, %r12
movq 0x28(%rdi), %rax
movq (%rax), %r14
movl 0x8(%rax), %r15d
movq 0x28(%rax), %r13
movq 0x48(%rdi), %rsi
movq %rsi, 0x30(%rsp)
testq %rsi, %rsi
je 0xde7ac1
... | /Target/ARM/ARMISelLowering.cpp |
PerformVMOVrhCombine(llvm::SDNode*, llvm::SelectionDAG&) | static SDValue PerformVMOVrhCombine(SDNode *N, SelectionDAG &DAG) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
// fold (VMOVrh (fpconst x)) -> const x
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N0)) {
APFloat V = C->getValueAPF();
return DAG.getConstant(V.bitcastToAPInt().get... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rdi), %rax
movq 0x30(%rdi), %rdx
movq (%rax), %r12
movl 0x18(%r12), %ecx
cmpl $0x24, %ecx
je 0xe06ade
cmpl $0xc, %ecx
jne 0xe06ae3
movq %r12, %rsi
jmp 0xe06ae5
xorl %esi, %esi
movb (%rdx), %bpl
... | /Target/ARM/ARMISelLowering.cpp |
(anonymous namespace)::HexagonBitSimplify::replaceRegWithSub(llvm::Register, llvm::Register, unsigned int, llvm::MachineRegisterInfo&) | bool HexagonBitSimplify::replaceRegWithSub(Register OldR, Register NewR,
unsigned NewSR,
MachineRegisterInfo &MRI) {
if (!OldR.isVirtual() || !NewR.isVirtual())
return false;
if (hasTiedUse(OldR, MRI, NewSR))
return false;... | testl %esi, %edi
jns 0xeda59f
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r14
movl %edx, %ebx
movl %esi, %ebp
movl %edi, %r15d
movq %rcx, %rsi
callq 0xed9552
testb %al, %al
je 0xeda5a2
xorl %eax, %eax
jmp 0xeda5fa
xorl %eax, %eax
retq
movq %r14, %rdi
movl %r15d, %esi
callq 0... | /Target/Hexagon/HexagonBitSimplify.cpp |
llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
SDLoc dl(Op);
ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %rcx, %r14
movl %edx, %ebx
movq %rsi, %r15
movq %rdi, %r12
movq 0x28(%rsi), %rax
movups (%rax), %xmm0
movaps %xmm0, 0x60(%rsp)
movups 0x28(%rax), %xmm0
movaps %xmm0, 0x50(%rsp)
movq 0x50(%rax), %r13
movq 0x48(%rsi), %rsi
movq %rsi, ... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::getTargetNodeName(unsigned int) const | const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((HexagonISD::NodeType)Opcode) {
case HexagonISD::ADDC: return "HexagonISD::ADDC";
case HexagonISD::SUBC: return "HexagonISD::SUBC";
case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
case HexagonI... | addl $0xfffffe1b, %esi # imm = 0xFFFFFE1B
cmpl $0x32, %esi
ja 0xf41bb4
movl %esi, %eax
leaq 0x2b5cc68(%rip), %rcx # 0x3a9e814
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
retq
xorl %eax, %eax
retq
nop
| /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::isExtractSubvectorCheap(llvm::EVT, llvm::EVT, unsigned int) const | bool HexagonTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
unsigned Index) const {
assert(ResVT.getVectorElementType() == SrcVT.getVectorElementType());
if (!ResVT.isSimple() || !SrcVT.isSimple())
return false;
MVT ResTy = ResVT.getSimpleVT(), SrcTy = SrcVT.getSimpleVT();
if (ResTy.get... | pushq %rbx
movl %ecx, %ebx
testb %sil, %sil
setne %al
testb %bl, %bl
setne %cl
andb %al, %cl
cmpb $0x1, %cl
jne 0xf42257
movzbl %sil, %ecx
leaq 0x228d81a(%rip), %rdx # 0x31cfa40
movb $0x1, %al
cmpb $0x2, -0x1(%rcx,%rdx)
jne 0xf42259
leal 0x77(%rbx), %eax
cmpb $0x34, %al
ja 0xf42242
leaq 0x245954d(%rip), %rdi # 0x33... | /Target/Hexagon/HexagonISelLowering.cpp |
llvm::HexagonTargetLowering::LowerHvxFpToInt(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
HexagonTargetLowering::LowerHvxFpToInt(SDValue Op, SelectionDAG &DAG) const {
// Catch invalid conversion ops (just in case).
assert(Op.getOpcode() == ISD::FP_TO_SINT ||
Op.getOpcode() == ISD::FP_TO_UINT);
MVT ResTy = ty(Op);
MVT FpTy = ty(Op.getOperand(0)).getVectorElementType();
MVT IntTy ... | pushq %rax
movq %rsi, %rax
movq 0x28(%rsi), %rsi
movq 0x30(%rax), %r8
movl %edx, %r9d
shlq $0x4, %r9
movzbl (%r8,%r9), %r9d
movq (%rsi), %r8
movl 0x8(%rsi), %esi
movq 0x30(%r8), %r8
shlq $0x4, %rsi
movzbl (%r8,%rsi), %esi
leaq 0x227ab8e(%rip), %r10 # 0x31cfa40
movb -0x1(%rsi,%r10), %r8b
movzbl -0x1(%r9,%r10), %esi
mo... | /Target/Hexagon/HexagonISelLoweringHVX.cpp |
llvm::SDValue lowerVectorBitRevImm<3u>(llvm::SDNode*, llvm::SelectionDAG&) | static SDValue lowerVectorBitRevImm(SDNode *Node, SelectionDAG &DAG) {
SDLoc DL(Node);
EVT ResTy = Node->getValueType(0);
auto *CImm = cast<ConstantSDNode>(Node->getOperand(2));
// Check the unsigned ImmArg.
if (!isUInt<N>(CImm->getZExtValue())) {
DAG.getContext()->emitError(Node->getOperationName(0) +
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0xc0, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x48(%rdi), %rsi
movq %rsi, 0x38(%rsp)
testq %rsi, %rsi
je 0xfdf84d
leaq 0x38(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r14), %eax
movl %eax, 0x40(%rsp)
movq 0x30(%r14), %rax
movb (%rax), %cl
movq 0... | /Target/LoongArch/LoongArchISelLowering.cpp |
llvm::MipsAsmPrinter::runOnMachineFunction(llvm::MachineFunction&) | bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<MipsSubtarget>();
MipsFI = MF.getInfo<MipsFunctionInfo>();
if (Subtarget->inMips16Mode())
for (const auto &I : MipsFI->StubsNeeded) {
const char *Symbol = I.first;
const Mips16HardFloatInfo::FuncSignatur... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rsi, %r14
movq %rdi, %rbx
movq 0x10(%rsi), %rax
movq %rax, 0x358(%rdi)
movq 0x30(%rsi), %rbp
movq %rbp, 0x360(%rdi)
cmpb $0x1, 0x13d(%rax)
jne 0xfe091a
movq 0x20(%rbp), %r15
addq $0x10, %rbp
cmpq %rbp, %r15
je 0xfe091a
leaq 0x328(%... | /Target/Mips/MipsAsmPrinter.cpp |
llvm::MipsAsmPrinter::isLongBranchPseudo(int) const | bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
return (Opcode == Mips::LONG_BRANCH_LUi
|| Opcode == Mips::LONG_BRANCH_LUi2Op
|| Opcode == Mips::LONG_BRANCH_LUi2Op_64
|| Opcode == Mips::LONG_BRANCH_ADDiu
|| Opcode == Mips::LONG_BRANCH_ADDiu2Op
|| Opcode ==... | addl $0xfffffdf8, %esi # imm = 0xFFFFFDF8
cmpl $0x7, %esi
setb %al
retq
nop
| /Target/Mips/MipsAsmPrinter.cpp |
llvm::MipsAsmPrinter::PrintAsmMemoryOperand(llvm::MachineInstr const*, unsigned int, char const*, llvm::raw_ostream&) | bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNum,
const char *ExtraCode,
raw_ostream &O) {
assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands... | pushq %r15
pushq %r14
pushq %rbx
movq 0x20(%rsi), %r14
leal 0x1(%rdx), %eax
shlq $0x5, %rax
movq 0x10(%r14,%rax), %rsi
testq %rcx, %rcx
je 0xfe2c0e
movzbl (%rcx), %ecx
cmpl $0x4d, %ecx
je 0xfe2bf8
cmpl $0x4c, %ecx
je 0xfe2be0
movb $0x1, %al
cmpl $0x44, %ecx
jne 0xfe2c62
addq $0x4, %rsi
jmp 0xfe2c0e
movq 0x358(%rdi), %r... | /Target/Mips/MipsAsmPrinter.cpp |
llvm::MipsAsmPrinter::EmitJal(llvm::MCSubtargetInfo const&, llvm::MCSymbol*) | void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
MCInst I;
I.setOpcode(Mips::JAL);
I.addOperand(
MCOperand::createExpr(MCSymbolRefExpr::create(Symbol, OutContext)));
OutStreamer->emitInstruction(I, STI);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rdx, %rax
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x10(%rsp), %r15
leaq 0x20(%rsp), %r12
xorps %xmm0, %xmm0
movaps %xmm0, -0x20(%r12)
movq %r12, -0x10(%r12)
movabsq $0x600000000, %rcx # imm = 0x600000000
movq %rcx, -0x8(%r12)
movl $0x71a, -0x20(%r12) ... | /Target/Mips/MipsAsmPrinter.cpp |
llvm::MipsRegisterInfo::getFrameRegister(llvm::MachineFunction const&) const | Register MipsRegisterInfo::
getFrameRegister(const MachineFunction &MF) const {
const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>();
const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
bool IsN64 =
static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI().IsN64();
if (Subta... | pushq %rbp
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq 0x10(%rsi), %r14
movq (%r14), %rax
movq %r14, %rdi
callq *0x88(%rax)
cmpb $0x1, 0x13d(%r14)
jne 0xfe5b37
movq (%rax), %rcx
movq %rax, %rdi
movq %rbx, %rsi
callq *0xc8(%rcx)
testb %al, %al
movl $0x146, %eax # imm = 0x146
movl $0x14, %ecx
cmovnel %eax, %ecx... | /Target/Mips/MipsRegisterInfo.cpp |
void llvm::StringMapEntry<std::unique_ptr<llvm::MipsSubtarget, std::default_delete<llvm::MipsSubtarget>>>::Destroy<llvm::MallocAllocator>(llvm::MallocAllocator&) | void Destroy(AllocatorTy &allocator) {
// Free memory referenced by the item.
size_t AllocSize = sizeof(StringMapEntry) + this->getKeyLength() + 1;
this->~StringMapEntry();
allocator.Deallocate(static_cast<void *>(this), AllocSize,
alignof(StringMapEntry));
} | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq (%rdi), %r14
movq 0x8(%rdi), %rdi
testq %rdi, %rdi
je 0xfe8317
movq (%rdi), %rax
callq *0x8(%rax)
addq $0x11, %r14
movq $0x0, 0x8(%rbx)
movl $0x8, %edx
movq %rbx, %rdi
movq %r14, %rsi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x2b410f1
| /llvm/ADT/StringMapEntry.h |
(anonymous namespace)::MipsIncomingValueHandler::getStackAddress(unsigned long, long, llvm::MachinePointerInfo&, llvm::ISD::ArgFlagsTy) | Register MipsIncomingValueHandler::getStackAddress(uint64_t Size,
int64_t Offset,
MachinePointerInfo &MPO,
ISD::ArgFlagsTy Flags) {
MachineFunction &MF = MIRBuilder... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movq %rdi, %r14
movq 0x8(%rdi), %rax
movq 0x8(%rax), %rax
movq 0x38(%rax), %rdi
movl $0x1, %ecx
xorl %r8d, %r8d
callq 0x1d32a60
movl %eax, %ebp
movq 0x8(%r14), %rax
movq 0x8(%rax), %rsi
movq %rsp, %r15
movq %r15, %rdi
movl %ebp, %edx
xorl %ecx... | /Target/Mips/MipsCallLowering.cpp |
llvm::MipsTargetLowering::lowerSETCC(llvm::SDValue, llvm::SelectionDAG&) const | SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
SDValue Cond = createFPCmp(DAG, Op);
assert(Cond.getOpcode() == MipsISD::FPCmp &&
"Floating point operand expected.");
SDLoc DL(Op);
SDValue True = DAG.getCon... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rcx, %rbx
movq %rsi, %r15
leaq 0x38(%rsp), %rsi
movq %r15, (%rsi)
movl %edx, 0x8(%rsi)
movq %rcx, %rdi
callq 0x1021268
movq %rax, 0x10(%rsp)
movl %edx, %ebp
movq 0x48(%r15), %rsi
movq %rsi, 0x18(%rsp)
testq %rsi, %rsi
je 0x10166db
... | /Target/Mips/MipsISelLowering.cpp |
llvm::SDValue llvm::MipsTargetLowering::getAddrNonPICSym64<llvm::ExternalSymbolSDNode>(llvm::ExternalSymbolSDNode*, llvm::SDLoc const&, llvm::EVT, llvm::SelectionDAG&) const | SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
SelectionDAG &DAG) const {
SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
SDValue Highest =
DAG.getNode(MipsISD::Highest, DL, Ty,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x128, %rsp # imm = 0x128
movq %r9, %r14
movq %r8, %rbx
movl %ecx, %ebp
movq %rdx, %r15
movq %rdx, 0x30(%rsp)
movq %rsi, %r12
movq 0x58(%rsi), %rsi
movq %r9, %rdi
movl %ecx, %edx
movq %r8, %rcx
movl $0x4, %r8d
callq 0x1766cc2
movq %rax, ... | /Target/Mips/MipsISelLowering.h |
llvm::DenseMap<llvm::PointerUnion<llvm::Value const*, llvm::PseudoSourceValue const*>, llvm::ScopedHashTableVal<llvm::PointerUnion<llvm::Value const*, llvm::PseudoSourceValue const*>, std::pair<unsigned int, unsigned int>>*, llvm::DenseMapInfo<llvm::PointerUnion<llvm::Value const*, llvm::PseudoSourceValue const*>, void... | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, llvm::MipsRegisterBankInfo::InstType, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, llvm::MipsRegisterBankInfo::InstType>>, llvm::MachineInstr const*, llvm::MipsRegisterBankInfo::InstType, llvm::Den... | unsigned getNumEntries() const {
return NumEntries;
} | movl 0x8(%rdi), %eax
testl %eax, %eax
jne 0x103aa37
cmpl $0x0, 0xc(%rdi)
je 0x103ab10
shll $0x2, %eax
movl 0x10(%rdi), %ecx
cmpl %ecx, %eax
setae %al
cmpl $0x41, %ecx
setb %dl
orb %al, %dl
je 0x103e34a
testq %rcx, %rcx
je 0x103ab08
movq (%rdi), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, ... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, llvm::SmallVector<llvm::MachineInstr const*, 2u>, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, llvm::SmallVector<llvm::MachineInstr const*, 2u>>>, llvm::MachineInstr const*, llvm::SmallVector<llvm:... | bool erase(const KeyT &Val) {
BucketT *TheBucket;
if (!LookupBucketFor(Val, TheBucket))
return false; // not in map.
TheBucket->getSecond().~ValueT();
TheBucket->getFirst() = getTombstoneKey();
decrementNumEntries();
incrementNumTombstones();
return true;
} | pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0x8(%rsp), %rdx
callq 0x103bdd4
movl %eax, %ebp
testb %al, %al
je 0x103c5f3
movq 0x8(%rsp), %r14
movq 0x8(%r14), %rdi
leaq 0x18(%r14), %rax
cmpq %rax, %rdi
je 0x103c5da
callq 0x780910
movq $-0x2000, (%r14) # imm = 0xE000
movq 0x8(%rbx), %xmm0... | /llvm/ADT/DenseMap.h |
llvm::MipsSEDAGToDAGISel::getMSACtrlReg(llvm::SDValue) const | uint64_t getZExtValue() const { return Value->getZExtValue(); } | movq 0x58(%rsi), %rax
cmpl $0x41, 0x20(%rax)
jb 0x10467cc
movq 0x18(%rax), %rax
jmp 0x10467d0
addq $0x18, %rax
movl (%rax), %eax
leaq 0x475cdd7(%rip), %rcx # 0x57a35b0
movq (%rcx), %rcx
movq (%rcx), %rcx
movzwl (%rcx,%rax,2), %eax
retq
| /llvm/CodeGen/SelectionDAGNodes.h |
llvm::Mips16InstrInfo::storeRegToStack(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::Register, bool, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*, long) const | void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
Register SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movl %r9d, %ebx
movl %r8d, 0x10(%rsp)
movl %ecx, 0x14(%rsp)
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
movq 0xa0(%rsp), %r15
movq $0x0, 0x8(%rsp)
leaq 0x30(%rsi), %rax
cmpq %rdx, %rax
je 0x105be1c
leaq 0x38(%r12), %rsi
leaq 0x8(%rsp... | /Target/Mips/Mips16InstrInfo.cpp |
llvm::Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned int, long, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>) const | void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
if (Amount == 0)
return;
if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16>
BuildA... | testq %rdx, %rdx
je 0x105cc6b
movq %rcx, %rsi
movq %rdx, %rcx
movq %r8, %rdx
jmp 0x105c588
retq
| /Target/Mips/Mips16InstrInfo.cpp |
(anonymous namespace)::MSP430DAGToDAGISel::Select(llvm::SDNode*) | void MSP430DAGToDAGISel::Select(SDNode *Node) {
SDLoc dl(Node);
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
Node->setNodeId(-1);
return;
}
// Few custom selection stuff.
switch (Node->get... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, 0x8(%rsp)
testq %rsi, %rsi
je 0x106f1b8
leaq 0x8(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbx), %eax
movl %eax, 0x10(%rsp)
movl 0x18(%rbx), %eax
testl %eax, %... | /Target/MSP430/MSP430ISelDAGToDAG.cpp |
void llvm::cl::parser<llvm::MSP430Subtarget::HWMultEnum>::addLiteralOption<int>(llvm::StringRef, int const&, llvm::StringRef) | void addLiteralOption(StringRef Name, const DT &V, StringRef HelpStr) {
#ifndef NDEBUG
if (findOption(Name) != Values.size())
report_fatal_error("Option '" + Name + "' already exists!");
#endif
OptionInfo X(Name, static_cast<DataType>(V), HelpStr);
Values.push_back(X);
AddLiteralOption(Owner, Name... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x30, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl (%rcx), %eax
movq %rsp, %rsi
movq %r14, (%rsi)
movq %rdx, 0x8(%rsi)
movq %r8, 0x10(%rsi)
movq %r9, 0x18(%rsi)
leaq 0x473c207(%rip), %r12 # 0x57ae270
leaq 0x473c1e0(%rip), %r13 # 0x57ae250
mov... | /llvm/Support/CommandLine.h |
llvm::MSP430TargetLowering::LowerRETURNADDR(llvm::SDValue, llvm::SelectionDAG&) const | SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
SelectionDAG &DAG) const {
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
MFI.setReturnAddressIsTaken(true);
if (verifyReturnAddressArgumentIsConstant(Op, DAG))
return SDValue();
unsig... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movq 0x28(%rcx), %rax
movq 0x38(%rax), %rax
movb $0x1, 0x26(%rax)
callq 0x17d3a3a
testb %al, %al
je 0x1073327
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp... | /Target/MSP430/MSP430ISelLowering.cpp |
llvm::NVPTXAsmPrinter::printFPConstant(llvm::ConstantFP const*, llvm::raw_ostream&) | void NVPTXAsmPrinter::printFPConstant(const ConstantFP *Fp, raw_ostream &O) {
APFloat APF = APFloat(Fp->getValueAPF()); // make a copy
bool ignored;
unsigned int numHex;
const char *lead;
if (Fp->getType()->getTypeID() == Type::FloatTyID) {
numHex = 8;
lead = "0f";
APF.convert(APFloat::IEEEsingle... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rdx, %r14
movq %rsi, %r15
leaq 0x28(%rsp), %rbx
addq $0x20, %rsi
movq %rbx, %rdi
callq 0x81e6da
movq 0x8(%r15), %rax
cmpb $0x2, 0x8(%rax)
jne 0x107f326
leaq 0x3f0b092(%rip), %r15 # 0x4f8a3ac
movl $0x8, %ebp
callq 0x2b061ee
jmp 0x... | /Target/NVPTX/NVPTXAsmPrinter.cpp |
llvm::NVPTXTargetLowering::NVPTXTargetLowering(llvm::NVPTXTargetMachine const&, llvm::NVPTXSubtarget const&) | NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
const NVPTXSubtarget &STI)
: TargetLowering(TM), nvTM(&TM), STI(STI) {
// always lower memset, memcpy, and memmove intrinsics to load/store
// instructions, rather
// then generating calls to memset... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r12
callq 0x17b1abc
leaq 0x472e153(%rip), %rax # 0x57af620
movq %rax, (%r12)
movq %r15, 0x4e0f8(%r12)
movq %rbx, 0x4e100(%r12)
movq $-0x1, 0x4e0e8(%r12)
pcmpeqd %xmm0, %xmm0
movdqu %xmm0, 0x4... | /Target/NVPTX/NVPTXISelLowering.cpp |
PromoteScalarIntegerPTX(llvm::EVT const&, llvm::MVT*) | static bool PromoteScalarIntegerPTX(const EVT &VT, MVT *PromotedVT) {
if (VT.isScalarInteger()) {
switch (PowerOf2Ceil(VT.getFixedSizeInBits())) {
default:
llvm_unreachable(
"Promotion is not suitable for scalars of size larger than 64-bits");
case 1:
*PromotedVT = MVT::i1;
bre... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %r14
movq %rdi, %rbx
movzbl (%rdi), %r15d
testq %r15, %r15
je 0x1086bbc
leal -0x2(%r15), %eax
cmpb $0x8, %al
setb %al
jmp 0x1086bc4
movq %rbx, %rdi
callq 0x1e89dd2
testb %al, %al
je 0x1086bdf
testq %r15, %r15
je 0x1086be3
shll $0x4, %r15d
leaq 0x2148168(%rip), %rax # 0x31ce... | /Target/NVPTX/NVPTXISelLowering.cpp |
llvm::cl::opt<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>, false, llvm::cl::parser<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char>>>>::opt<char [32], llvm::cl::desc, llvm::cl::initializer<char [1]>, llvm::cl::OptionHidden>(char const (&) [32], llvm::cl::d... | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %ebp, %ebp
xorl %esi, %esi
xorl %edx, %edx
callq 0x7fca88
leaq 0x90(%r14), %rax
movq %rax, 0x80(%r14)
movq %rbp, 0x88(%r14)
movb %bpl, 0x90(%r14)
leaq 0xb8(%r1... | /llvm/Support/CommandLine.h |
llvm::NVPTXAAResult::getModRefInfoMask(llvm::MemoryLocation const&, llvm::AAQueryInfo&, bool) | ModRefInfo NVPTXAAResult::getModRefInfoMask(const MemoryLocation &Loc,
AAQueryInfo &AAQI,
bool IgnoreLocals) {
if (isConstOrParam(Loc.Ptr->getType()->getPointerAddressSpace()))
return ModRefInfo::NoModRef;
const Value *Base... | movq (%rsi), %rdi
movq 0x8(%rdi), %rax
movl $0xfe, %ecx
andl 0x8(%rax), %ecx
cmpl $0x12, %ecx
jne 0x10a2d57
movq 0x10(%rax), %rax
movq (%rax), %rax
movl 0x8(%rax), %ecx
shrl $0x8, %ecx
xorl %eax, %eax
cmpl $0x4, %ecx
je 0x10a2da9
cmpl $0x65, %ecx
je 0x10a2da9
pushq %rax
movl $0x6, %esi
callq 0x26fbb24
movq 0x8(%rax), %... | /Target/NVPTX/NVPTXAliasAnalysis.cpp |
(anonymous namespace)::GenericToNVVMLegacyPass::runOnModule(llvm::Module&) | bool GenericToNVVMLegacyPass::runOnModule(Module &M) {
return GenericToNVVM().runOnModule(M);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x80, %rsp
movq %rsi, %r15
xorps %xmm0, %xmm0
leaq 0x40(%rsp), %r14
movaps %xmm0, -0x30(%r14)
movaps %xmm0, 0x30(%r14)
movaps %xmm0, 0x20(%r14)
movaps %xmm0, 0x10(%r14)
movaps %xmm0, (%r14)
movaps %xmm0, -0x10(%r14)
movaps %xmm0, -0x20(%r14)
movaps %xmm0, -0x... | /Target/NVPTX/NVPTXGenericToNVVM.cpp |
std::pair<llvm::DenseMapIterator<llvm::ValueMapCallbackVH<llvm::GlobalVariable*, llvm::GlobalVariable*, llvm::ValueMapConfig<llvm::GlobalVariable*, llvm::sys::SmartMutex<false>>>, llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::GlobalVariable*, llvm::GlobalVariable*, llvm::ValueMapConfig<llvm::... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x8(%rsp), %r15
movq %rsi, %rdi
movq %rdx, %rsi
movq %r15, %rdx
callq 0x10a469a
movq (%r15), %r15
testb %al, %al
je 0x10a49e7
xorl %eax, %eax
jmp 0x10a4a1a
movq %r14, %rdi
movq %r... | /llvm/ADT/DenseMap.h |
llvm::DenseMap<llvm::ValueMapCallbackVH<llvm::GlobalVariable*, llvm::GlobalVariable*, llvm::ValueMapConfig<llvm::GlobalVariable*, llvm::sys::SmartMutex<false>>>, llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::GlobalVariable*, llvm::GlobalVariable*, llvm::ValueMapConfig<llvm::GlobalVariable*, l... | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %rbx
movl 0x10(%rdi), %r15d
decl %esi
movl %esi, %eax
shrl %eax
orl %esi, %eax
movl %eax, %ecx
shrl $0x2, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x4, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x8, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x10, %eax
orl %ecx, %eax
incl %ea... | /llvm/ADT/DenseMap.h |
std::pair<llvm::DenseMapIterator<llvm::ValueMapCallbackVH<llvm::Constant*, llvm::Value*, llvm::ValueMapConfig<llvm::Constant*, llvm::sys::SmartMutex<false>>>, llvm::Value*, llvm::DenseMapInfo<llvm::ValueMapCallbackVH<llvm::Constant*, llvm::Value*, llvm::ValueMapConfig<llvm::Constant*, llvm::sys::SmartMutex<false>>>, vo... | std::pair<iterator, bool> try_emplace(KeyT &&Key, Ts &&... Args) {
BucketT *TheBucket;
if (LookupBucketFor(Key, TheBucket))
return std::make_pair(makeIterator(TheBucket,
shouldReverseIterate<KeyT>()
? getBuckets()
... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x8(%rsp), %r15
movq %rsi, %rdi
movq %rdx, %rsi
movq %r15, %rdx
callq 0x10a4f9c
movq (%r15), %r15
testb %al, %al
je 0x10a5265
xorl %eax, %eax
jmp 0x10a5298
movq %r14, %rdi
movq %r... | /llvm/ADT/DenseMap.h |
llvm::NVPTXDAGToDAGISel::tryStoreRetval(llvm::SDNode*) | bool NVPTXDAGToDAGISel::tryStoreRetval(SDNode *N) {
SDLoc DL(N);
SDValue Chain = N->getOperand(0);
SDValue Offset = N->getOperand(1);
unsigned OffsetVal = Offset->getAsZExtVal();
MemSDNode *Mem = cast<MemSDNode>(N);
// How many elements do we have?
unsigned NumElts = 1;
switch (N->getOpcode()) {
defa... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rsi, %rbx
movq %rdi, %r13
movq 0x48(%rsi), %rsi
movq %rsi, 0x20(%rsp)
testq %rsi, %rsi
je 0x10aa4d4
leaq 0x20(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbx), %eax
movl %eax, 0x28(%rsp)
movq 0x28(%rbx), %rax
movq 0x28(%... | /Target/NVPTX/NVPTXISelDAGToDAG.cpp |
llvm::NVPTXInstrInfo::copyPhysReg(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, llvm::MCRegister, llvm::MCRegister, bool) const | void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
MCRegister SrcReg, bool KillSrc) const {
const MachineRegisterInfo &MRI = MBB.getParent()->... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rsi, %r14
movq %rdi, %r12
movq 0x20(%rsi), %rax
movq 0x28(%rax), %rax
movl $0x7fffffff, %r10d # imm = 0x7FFFFFFF
movl %r8d, %esi
andl %r10d, %esi
movq 0x38(%rax), %rdi
shlq $0x4, %rsi
movq (%rdi,%rsi), %rax
andq $-0x8, %rax
an... | /Target/NVPTX/NVPTXInstrInfo.cpp |
(anonymous namespace)::NVPTXLowerArgs::handleByValParam(llvm::NVPTXTargetMachine const&, llvm::Argument*) | void NVPTXLowerArgs::handleByValParam(const NVPTXTargetMachine &TM,
Argument *Arg) {
bool IsGridConstant = isParamGridConstant(*Arg);
Function *Func = Arg->getParent();
BasicBlock::iterator FirstInst = Func->getEntryBlock().begin();
Type *StructType = Arg->getParamByValType... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x378, %rsp # imm = 0x378
movq %rsi, %r14
movq %rdi, 0xe8(%rsp)
movq %rsi, %rdi
callq 0x109ea7a
movl %eax, %ebx
movq 0x18(%r14), %rax
movq %rax, 0x38(%rsp)
movq 0x50(%rax), %rax
leaq -0x18(%rax), %rcx
testq %rax, %rax
cmoveq %rax, %rcx
m... | /Target/NVPTX/NVPTXLowerArgs.cpp |
llvm::Value** llvm::SmallVectorImpl<llvm::Value*>::insert<llvm::Value::user_iterator_impl<llvm::User>, void>(llvm::Value**, llvm::Value::user_iterator_impl<llvm::User>, llvm::Value::user_iterator_impl<llvm::User>) | iterator insert(iterator I, ItTy From, ItTy To) {
// Convert iterator to elt# to avoid invalidating iterator when we reserve()
size_t InsertElt = I - this->begin();
if (I == this->end()) { // Important special case for empty vector.
append(From, To);
return this->begin()+InsertElt;
}
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r14
movq %rdi, %r13
movq (%rdi), %rax
movq %rsi, %rbp
subq %rax, %rbp
movl 0x8(%rdi), %edx
leaq (%rax,%rdx,8), %rax
cmpq %rsi, %rax
je 0x10b06bb
xorl %r15d, %r15d
cmpq %rbx, %r14
je 0x10b0604
movq %r14, %rax
movq 0x... | /llvm/ADT/SmallVector.h |
llvm::PPCInstrInfo::foldImmediate(llvm::MachineInstr&, llvm::MachineInstr&, llvm::Register, llvm::MachineRegisterInfo*) const | bool PPCInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
Register Reg, MachineRegisterInfo *MRI) const {
bool Changed = onlyFoldImmediate(UseMI, DefMI, Reg);
if (MRI->use_nodbg_empty(Reg))
DefMI.eraseFromParent();
return Changed;
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %r8, %r14
movl %ecx, %r15d
movq %rdx, %rbx
callq 0x1108268
movl %eax, %ebp
movq %r14, %rdi
movl %r15d, %esi
callq 0x96036a
testq %rax, %rax
jne 0x11083a1
movq %rbx, %rdi
callq 0x1d3deba
movl %ebp, %eax
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
re... | /Target/PowerPC/PPCInstrInfo.cpp |
(anonymous namespace)::PPCDAGToDAGISel::tryAsSingleRLDICR(llvm::SDNode*) | bool PPCDAGToDAGISel::tryAsSingleRLDICR(SDNode *N) {
assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
uint64_t Imm64;
if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) ||
!isMask_64(~Imm64))
return false;
// If this is a negated 64-bit zero-extension mask,
// i.e. the immedi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movq 0x28(%rax), %rax
cmpl $0xb, 0x18(%rax)
jne 0x111cc31
movq 0x30(%rax), %rcx
cmpb $0x8, (%rcx)
jne 0x111cc31
movq 0x58(%rax), %rax
cmpl $0x41, 0x20(%rax)
jb 0x111cc35
movq 0x18(%ra... | /Target/PowerPC/PPCISelDAGToDAG.cpp |
llvm::APSInt::operator>=(long) const | bool operator>=(int64_t RHS) const {
return compareValues(*this, get(RHS)) >= 0;
} | pushq %r14
pushq %rbx
subq $0x18, %rsp
leaq 0x8(%rsp), %r14
movl $0x40, 0x8(%r14)
movq %rsi, (%r14)
movb $0x0, 0xc(%r14)
movq %r14, %rsi
callq 0x112a9f4
movl %eax, %ebx
cmpl $0x41, 0x8(%r14)
jb 0x112a9e6
movq 0x8(%rsp), %rdi
testq %rdi, %rdi
je 0x112a9e6
callq 0x7802b0
testl %ebx, %ebx
setns %al
addq $0x18, %rsp
popq %... | /llvm/ADT/APSInt.h |
llvm::PPCTargetLowering::shouldExpandAtomicCmpXchgInIR(llvm::AtomicCmpXchgInst*) const | TargetLowering::AtomicExpansionKind
PPCTargetLowering::shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
unsigned Size = AI->getNewValOperand()->getType()->getPrimitiveSizeInBits();
if (shouldInlineQuadwordAtomics() && Size == 128)
return AtomicExpansionKind::MaskedIntrinsic;
return TargetLowering:... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movq -0x20(%rsi), %rax
movq 0x8(%rax), %rdi
callq 0x2a9a7de
leaq 0x8(%rsp), %rdi
movq %rax, (%rdi)
movb %dl, 0x8(%rdi)
callq 0x2b60e74
movq %rax, %r14
movq 0x4e0f8(%rbx), %rdi
callq 0x10d80c0
movl %eax, %ecx
xorl %eax, %eax
movl $0x0, %edx
testb %cl, %cl
je 0x116e7... | /Target/PowerPC/PPCISelLowering.cpp |
llvm::SmallVectorTemplateBase<(anonymous namespace)::BucketElement, true>::push_back((anonymous namespace)::BucketElement) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0x117e854
movq (%r14), %rax
movl 0x8(%r14), %ecx
shlq $0x4, %rcx
movq %r15, (%rax,%rcx)
movq %rbx, 0x8(%rax,%rcx)
incl 0x8(%r14)
popq %rbx
popq %r14
popq %r15
retq
incq %rdx
leaq 0x10(%r14), %r... | /llvm/ADT/SmallVector.h |
llvm::RISCVInstrInfo::mulImm(llvm::MachineFunction&, llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, llvm::Register, unsigned int, llvm::MachineInstr::MIFlag) const | void RISCVInstrInfo::mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator II, const DebugLoc &DL,
Register DestReg, uint32_t Amount,
MachineInstr::MIFlag Flag) const {
MachineRegisterInfo &MRI = MF.getRegInf... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movl %r9d, 0x4(%rsp)
movq %r8, 0x28(%rsp)
movq %rcx, %r13
movq %rdx, %r12
movl 0x118(%rsp), %ebp
movl 0x110(%rsp), %r14d
leal -0x1(%r14), %r15d
movl %r14d, %eax
xorl %r15d, %eax
cmpl %r15d, %eax
movq %rdi, 0x30(%rsp)
jbe 0x1198afb
testl ... | /Target/RISCV/RISCVInstrInfo.cpp |
llvm::RISCVELFTargetObjectFile::SelectSectionForGlobal(llvm::GlobalObject const*, llvm::SectionKind, llvm::TargetMachine const&) const | MCSection *RISCVELFTargetObjectFile::SelectSectionForGlobal(
const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
// Handle Small Section classification here.
if (Kind.isBSS() && isGlobalInSmallSection(GO, TM))
return SmallBSSSection;
if (Kind.isData() && isGlobalInSmallSection(GO, T... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movl %edx, %r14d
movq %rsi, %r12
movq %rdi, %r15
leal -0xf(%r14), %eax
cmpb $0x2, %al
ja 0x11a5640
movq %r15, %rdi
movq %r12, %rsi
callq 0x11a5510
testb %al, %al
je 0x11a5640
movq 0x498(%r15), %rax
jmp 0x11a565c
cmpb $0x13, %r14b
jne 0x11a5668
movq ... | /Target/RISCV/RISCVTargetObjectFile.cpp |
llvm::APInt::isShiftedMask() const | bool isShiftedMask() const {
if (isSingleWord())
return isShiftedMask_64(U.VAL);
unsigned Ones = countPopulationSlowCase();
unsigned LeadZ = countLeadingZerosSlowCase();
return (Ones + LeadZ + countr_zero()) == BitWidth;
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movl 0x8(%rdi), %r15d
cmpl $0x40, %r15d
ja 0x11b6cee
movq (%rbx), %rax
testq %rax, %rax
je 0x11b6d22
leaq -0x1(%rax), %rcx
orq %rax, %rcx
leaq 0x1(%rcx), %rax
testq %rcx, %rax
jmp 0x11b6d14
movq %rbx, %rdi
callq 0x2b12a20
movl %eax, %ebp
movq %rbx, ... | /llvm/ADT/APInt.h |
(anonymous namespace)::RISCVInstructionSelector::renderImm(llvm::MachineInstrBuilder&, llvm::MachineInstr const&, int) const | const MachineOperand& getOperand(unsigned i) const {
assert(i < getNumOperands() && "getOperand() out of range!");
return Operands[i];
} | movq 0x20(%rdx), %rax
movq 0x30(%rax), %rcx
movl 0x20(%rcx), %eax
cmpl $0x40, %eax
ja 0x11b7b0e
movq 0x18(%rcx), %rdx
movl %eax, %ecx
negb %cl
shlq %cl, %rdx
sarq %cl, %rdx
xorl %ecx, %ecx
testl %eax, %eax
cmovneq %rdx, %rcx
jmp 0x11b7b15
movq 0x18(%rcx), %rax
movq (%rax), %rcx
subq $0x28, %rsp
movq (%rsi), %rax
movq 0... | /llvm/CodeGen/MachineInstr.h |
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