name string | code string | asm string | file string |
|---|---|---|---|
bool llvm::DenseMapBase<llvm::SmallDenseMap<llvm::DILocalVariable const*, llvm::DbgVariable*, 4u, llvm::DenseMapInfo<llvm::DILocalVariable const*, void>, llvm::detail::DenseMapPair<llvm::DILocalVariable const*, llvm::DbgVariable*>>, llvm::DILocalVariable const*, llvm::DbgVariable*, llvm::DenseMapInfo<llvm::DILocalVaria... | const BucketT *getBuckets() const {
return Small ? getInlineBuckets() : getLargeRep()->Buckets;
} | leaq 0x8(%rdi), %rcx
testb $0x1, (%rdi)
cmoveq 0x8(%rdi), %rcx
movl $0x4, %r8d
cmovel 0x10(%rdi), %r8d
testl %r8d, %r8d
je 0x16711b1
pushq %rbx
movl (%rsi), %edi
movl %edi, %eax
shrl $0x4, %eax
shrl $0x9, %edi
xorl %eax, %edi
decl %r8d
andl %r8d, %edi
movl $0x1, %r10d
xorl %r9d, %r9d
movl %edi, %ebx
shlq $0x4, %rbx
lea... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorImpl<llvm::DbgVariable*>::operator=(llvm::SmallVectorImpl<llvm::DbgVariable*> const&) | SmallVectorImpl<T> &SmallVectorImpl<T>::
operator=(const SmallVectorImpl<T> &RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (C... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
cmpq %rsi, %rdi
je 0x167218c
movq %rsi, %r15
movl 0x8(%rsi), %r14d
movl 0x8(%rbx), %r12d
cmpl %r14d, %r12d
jae 0x167212f
cmpl %r14d, 0xc(%rbx)
jae 0x1672149
movl $0x0, 0x8(%rbx)
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
movq %r14, %rdx
c... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::DAGCombiner::visitTokenFactor(llvm::SDNode*) | SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
// If N has two operands, where one has an input chain equal to the other,
// the 'other' chain is redundant.
if (N->getNumOperands() == 2) {
if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
return N->getOperand(0);
if (getI... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x3d8, %rsp # imm = 0x3D8
movq %rsi, %rcx
movq %rdi, 0x8(%rsp)
movzwl 0x40(%rsi), %ebp
cmpl $0x2, %ebp
jne 0x16752c3
movq %rcx, %r13
movq 0x28(%rcx), %r14
movq (%r14), %rbx
movq %rbx, %rdi
callq 0x16c19e0
movq 0x28(%r14), %r12
cmpq %r12,... | /CodeGen/SelectionDAG/DAGCombiner.cpp |
(anonymous namespace)::DAGCombiner::visitATOMIC_STORE(llvm::SDNode*) | SDValue DAGCombiner::visitATOMIC_STORE(SDNode *N) {
AtomicSDNode *ST = cast<AtomicSDNode>(N);
SDValue Val = ST->getVal();
EVT VT = Val.getValueType();
EVT MemVT = ST->getMemoryVT();
if (MemVT.bitsLT(VT)) { // Is truncating store
APInt TruncDemandedBits = APInt::getLowBitsSet(VT.getScalarSizeInBits(),
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rsi, %rbx
cmpl $0x14a, 0x18(%rsi) # imm = 0x14A
movq %rdi, %rbp
movq 0x28(%rsi), %rax
movl $0x28, %ecx
movl $0x50, %edx
cmoveq %rcx, %rdx
movq (%rax,%rdx), %r15
movl 0x8(%rax,%rdx), %r12d
movq 0x30(%r15), %rax
movq %r12, %rdx
... | /CodeGen/SelectionDAG/DAGCombiner.cpp |
llvm::SDPatternMatch::BinaryOpc_match<llvm::SDPatternMatch::BinaryOpc_match<llvm::SDPatternMatch::SpecificInt_match, llvm::SDPatternMatch::Value_bind, false, false>, llvm::SDPatternMatch::Value_bind, false, false>::BinaryOpc_match(unsigned int, llvm::SDPatternMatch::BinaryOpc_match<llvm::SDPatternMatch::SpecificInt_mat... | BinaryOpc_match(unsigned Opc, const LHS_P &L, const RHS_P &R)
: Opcode(Opc), LHS(L), RHS(R) {} | pushq %r15
pushq %r14
pushq %rbx
movq %rcx, %rbx
movq %rdx, %r15
movq %rdi, %r14
movl %esi, (%rdi)
movl (%rdx), %eax
movl %eax, 0x8(%rdi)
addq $0x10, %rdi
leaq 0x8(%rdx), %rsi
movl 0x10(%rdx), %eax
movl %eax, 0x18(%r14)
cmpl $0x40, %eax
ja 0x16c868f
movq (%rsi), %rax
movq %rax, (%rdi)
jmp 0x16c8694
callq 0x2b11114
movq... | /llvm/CodeGen/SDPatternMatch.h |
(anonymous namespace)::DAGCombiner::MatchBSwapHWordLow(llvm::SDNode*, llvm::SDValue, llvm::SDValue, bool) | SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
bool DemandHighBits) {
if (!LegalOperations)
return SDValue();
EVT VT = N->getValueType(0);
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
return SDValue();
if (!TLI.isOperationLe... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
cmpb $0x1, 0x21(%rdi)
jne 0x16d2359
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %r14
movq 0x30(%rsi), %rcx
movb (%rcx), %al
movq 0x8(%rcx), %rcx
movb %al, 0x60(%rsp)
movq %rcx, 0x68(%rsp)
leal -0x9(%rax), %edx
cmpb $-0x3, %dl
jae 0x16d237... | /CodeGen/SelectionDAG/DAGCombiner.cpp |
(anonymous namespace)::DAGCombiner::MatchRotate(llvm::SDValue, llvm::SDValue, llvm::SDLoc const&) | SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
EVT VT = LHS.getValueType();
// The target must have at least one rotate/funnel flavor.
// We still try to match rotate by constant pre-legalization.
// TODO: Support pre-legalization funnel-shift by constant.
bool HasROTL = hasOpe... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x248, %rsp # imm = 0x248
movq %r9, %r15
movl %r8d, 0x64(%rsp)
movq %rcx, 0x78(%rsp)
movq %rsi, %rbp
movq %rdi, %r14
movq 0x30(%rsi), %rax
movl %edx, 0x60(%rsp)
movl %edx, %r13d
shlq $0x4, %r13
movl (%rax,%r13), %edx
movq 0x8(%rax,%r13),... | /CodeGen/SelectionDAG/DAGCombiner.cpp |
combineMinNumMaxNumImpl(llvm::SDLoc const&, llvm::EVT, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::ISD::CondCode, llvm::TargetLowering const&, llvm::SelectionDAG&) | static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
SDValue RHS, SDValue True, SDValue False,
ISD::CondCode CC,
const TargetLowering &TLI,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movl %r9d, %ebp
movl %r8d, 0x2c(%rsp)
movq %rcx, %r15
movq %rdx, %rbx
movl %esi, %r14d
movq %rdi, %r12
movq 0xe8(%rsp), %rax
movq 0xe0(%rsp), %rdi
movq 0x40(%rax), %rsi
movq (%rdi), %rax
movl %r14d, %edx
movq %rbx, %rcx
callq *0x240(%rax... | /CodeGen/SelectionDAG/DAGCombiner.cpp |
std::pair<int, llvm::SDValue>& llvm::SmallVectorTemplateBase<std::pair<int, llvm::SDValue>, true>::growAndEmplaceBack<int, llvm::SDValue&>(int&&, llvm::SDValue&) | T &growAndEmplaceBack(ArgTypes &&... Args) {
// Use push_back with a copy in case Args has an internal reference,
// side-stepping reference invalidation problems without losing the realloc
// optimization.
push_back(T(std::forward<ArgTypes>(Args)...));
return this->back();
} | pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movl (%rsi), %eax
leaq 0x8(%rsp), %rsi
movl %eax, (%rsi)
movups (%rdx), %xmm0
movups %xmm0, 0x8(%rsi)
movl $0x1, %edx
callq 0x16f5672
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
movq 0x10(%rax), %rsi
movq %rsi, 0x10(%rcx,%rdx,8)
movups (%rax), %xmm0
movups... | /llvm/ADT/SmallVector.h |
int* llvm::SmallVectorImpl<int>::insert<int*, void>(int*, int*, int*) | iterator insert(iterator I, ItTy From, ItTy To) {
// Convert iterator to elt# to avoid invalidating iterator when we reserve()
size_t InsertElt = I - this->begin();
if (I == this->end()) { // Important special case for empty vector.
append(From, To);
return this->begin()+InsertElt;
}
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, %rbx
movq %rdi, %r13
movq (%rdi), %rax
movq %rsi, %r12
subq %rax, %r12
movl 0x8(%rdi), %edx
leaq (%rax,%rdx,4), %rax
cmpq %rsi, %rax
je 0x16f847b
movq %rcx, 0x8(%rsp)
movq %rcx, %rbp
subq %rbx, %rbp
movq %rbp, 0x10(%rsp)
sarq ... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::SelectionDAGLegalize::ReplaceNode(llvm::SDNode*, llvm::SDNode*) | void ReplaceNode(SDNode *Old, SDNode *New) {
LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
dbgs() << " with: "; New->dump(&DAG));
assert(Old->getNumValues() == New->getNumValues() &&
"Replacing one node with another that produces a different number "
"o... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq %rdx, (%rsp)
movq 0x10(%rdi), %rdi
callq 0x176215a
movq 0x20(%r14), %rdi
testq %rdi, %rdi
je 0x170d61e
movq %rsp, %rsi
callq 0x1673b14
movq %r14, %rdi
movq %rbx, %rsi
callq 0x1719604
addq $0x8, %rsp
popq %rbx
popq %r14
retq
nop
| /CodeGen/SelectionDAG/LegalizeDAG.cpp |
llvm::SelectionDAGBuilder::visitCallBrLandingPad(llvm::CallInst const&) | void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) {
SmallVector<EVT, 8> ResultVTs;
SmallVector<SDValue, 8> ResultValues;
const auto *CBR =
cast<CallBrInst>(I.getParent()->getUniquePredecessor()->getTerminator());
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
const TargetRegi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x308, %rsp # imm = 0x308
movq %rdi, %rbx
leaq 0x288(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, -0x8(%rcx)
leaq 0x1f8(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movq %rax, -0x8(%rcx)
movq %r... | /CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
getF32Constant(llvm::SelectionDAG&, unsigned int, llvm::SDLoc const&) | static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
const SDLoc &dl) {
return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
MVT::f32);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x30, %rsp
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
callq 0x2b061ee
movl %ebp, %ecx
movq %rsp, %r15
movl $0x20, 0x8(%r15)
movq %rcx, (%r15)
leaq 0x18(%rsp), %r12
movq %r12, %rdi
movq %rax, %rsi
movq %r15, %rdx
callq 0x816006
leaq 0x10(%rsp), %rsi
movq ... | /CodeGen/SelectionDAG/SelectionDAGBuilder.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::MCSymbol*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>>, llvm::MCSymbol*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>>::LookupBucketF... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x175aac3
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movq (%rdi,%rbx), %rbx
cmpq %rbx, (%rsi)
jn... | /llvm/ADT/DenseMap.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MCSymbol*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>>, llvm::MCSymbol*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>>::moveFromOldBuckets... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0x175ad65
movq (%r15), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x1, %ecx
ne... | /llvm/ADT/DenseMap.h |
llvm::ISD::isConstantSplatVectorAllOnes(llvm::SDNode const*, bool) | bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) {
// Look through a bit convert.
while (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0).getNode();
if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) {
APInt SplatVal;
return isConstantSplatVector(N, SplatVal... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movl 0x18(%rdi), %eax
cmpl $0xe6, %eax
jne 0x1760401
movq 0x28(%rbx), %rax
movq (%rax), %rbx
movl 0x18(%rbx), %eax
jmp 0x17603ee
cmpl $0xa7, %eax
setne %cl
orb %sil, %cl
je 0x17604b0
cmpl $0x9b, %eax
jne 0x17605a7
movzwl ... | /CodeGen/SelectionDAG/SelectionDAG.cpp |
llvm::ISD::getExtForLoadExtType(bool, llvm::ISD::LoadExtType) | ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) {
switch (ExtType) {
case ISD::EXTLOAD:
return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND;
case ISD::SEXTLOAD:
return ISD::SIGN_EXTEND;
case ISD::ZEXTLOAD:
return ISD::ZERO_EXTEND;
default:
break;
}
llvm_unreachable... | cmpl $0x3, %esi
je 0x1761593
movl $0xd4, %eax
cmpl $0x2, %esi
je 0x1761598
testb %dil, %dil
movl $0xe5, %ecx
movl $0xd6, %eax
cmovnel %ecx, %eax
retq
movl $0xd5, %eax
retq
| /CodeGen/SelectionDAG/SelectionDAG.cpp |
llvm::SelectionDAG::FindModifiedNodeSlot(llvm::SDNode*, llvm::ArrayRef<llvm::SDValue>, void*&) | SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, ArrayRef<SDValue> Ops,
void *&InsertPos) {
if (doNotCSE(N))
return nullptr;
FoldingSetNodeID ID;
AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
AddNodeIDCustom(ID, N);
SDNode *Node = FindNodeOrInsert... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %r8, %r14
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, %r15
movq %rsi, %rdi
callq 0x1762103
testb %al, %al
je 0x1762a66
xorl %r14d, %r14d
jmp 0x1762b1b
leaq 0x28(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x2000000000... | /CodeGen/SelectionDAG/SelectionDAG.cpp |
llvm::SelectionDAG::getVPZeroExtendInReg(llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDLoc const&, llvm::EVT) | SDValue SelectionDAG::getVPZeroExtendInReg(SDValue Op, SDValue Mask,
SDValue EVL, const SDLoc &DL,
EVT VT) {
EVT OpVT = Op.getValueType();
assert(VT.isInteger() && OpVT.isInteger() &&
"Cannot getVPZeroExtendInReg FP types... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %r9, %r13
movl %edx, %ebp
movq %rsi, %r14
leaq 0xf0(%rsp), %rbx
movq 0x30(%rsi), %rax
movl %edx, %edx
shlq $0x4, %rdx
movb (%rax,%rdx), %sil
movq 0x8(%rax,%rdx), %rax
movb %sil, 0x30(%rsp)
movq %rax, 0x38(%rsp)
cmpb (%rbx), %sil
jne... | /CodeGen/SelectionDAG/SelectionDAG.cpp |
llvm::JumpTableSDNode* llvm::SelectionDAG::newSDNode<llvm::JumpTableSDNode, int&, llvm::SDVTList&, bool&, unsigned int&>(int&, llvm::SDVTList&, bool&, unsigned int&) | SDNodeT *newSDNode(ArgTypes &&... Args) {
return new (NodeAllocator.template Allocate<SDNodeT>())
SDNodeT(std::forward<ArgTypes>(Args)...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r13
movq 0x160(%rdi), %r12
testq %r12, %r12
je 0x176607e
movq (%r12), %rax
movq %rax, 0x160(%rdi)
jmp 0x1766097
addq $0x168, %rdi # imm = 0x168
movl $0x70, %esi
movl $0x3, %edx
callq 0x8f284c
mov... | /llvm/CodeGen/SelectionDAG.h |
llvm::isBitwiseNot(llvm::SDValue, bool) | bool llvm::isBitwiseNot(SDValue V, bool AllowUndefs) {
if (V.getOpcode() != ISD::XOR)
return false;
V = peekThroughBitcasts(V.getOperand(1));
unsigned NumBits = V.getScalarValueSizeInBits();
ConstantSDNode *C =
isConstOrConstSplat(V, AllowUndefs, /*AllowTruncation*/ true);
return C && (C->getAPIntVa... | pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdi, (%rsp)
movl %esi, 0x8(%rsp)
cmpl $0xbb, 0x18(%rdi)
jne 0x1778965
movl %edx, %ebp
movq 0x28(%rdi), %rcx
movq 0x28(%rcx), %rax
cmpl $0xe6, 0x18(%rax)
jne 0x1778913
movq 0x28(%rax), %rcx
movq (%rcx), %rax
cmpl $0xe6, 0x18(%rax)
je 0x17788fd
addq $0x8, %rcx
jmp 0... | /CodeGen/SelectionDAG/SelectionDAG.cpp |
llvm::APIntOps::abdu(llvm::APInt const&, llvm::APInt const&) | inline const APInt abdu(const APInt &A, const APInt &B) {
return A.uge(B) ? (A - B) : (B - A);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x20, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq %rsi, %rdi
movq %rdx, %rsi
callq 0x2b11ae2
movl %eax, %ebp
testl %eax, %eax
js 0x1796231
movl 0x8(%r15), %eax
movl %eax, 0x18(%rsp)
cmpl $0x40, %eax
ja 0x1796247
movq (%r15), %rax
movq %rax, 0x10... | /llvm/ADT/APInt.h |
llvm::DenseMap<llvm::SDNode const*, llvm::SelectionDAG::NodeExtraInfo, llvm::DenseMapInfo<llvm::SDNode const*, void>, llvm::detail::DenseMapPair<llvm::SDNode const*, llvm::SelectionDAG::NodeExtraInfo>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0x1797a22
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ec... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorTemplateBase<(anonymous namespace)::MatchScope, false>::grow(unsigned long) | void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %rsi
movl $0x88, %r13d
leaq 0x10(%rsp), %r8
movl $0x88, %ecx
movq %rsi, 0x8(%rsp)
callq 0x2b4ec3c
movq %rax, (%rsp)
movl 0x8(%rbx), %eax
testq %rax, %rax
je 0x17ac563
movq (%rbx), %r12
mov... | /llvm/ADT/SmallVector.h |
llvm::StatepointLoweringState::getLocation(llvm::SDValue) | SDValue getLocation(SDValue Val) {
auto I = Locations.find(Val);
if (I == Locations.end())
return SDValue();
return I->second;
} | pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
movq %rsp, %rax
movq %rsi, (%rax)
movl %edx, 0x8(%rax)
movq %rax, %rsi
callq 0x17b06ca
movl 0x10(%rbx), %ecx
shlq $0x5, %rcx
addq (%rbx), %rcx
cmpq %rcx, %rax
je 0x17ae47f
movq 0x10(%rax), %rcx
movl 0x18(%rax), %edx
jmp 0x17ae483
xorl %edx, %edx
xorl %ecx, %ecx
movq %rcx, %ra... | /CodeGen/SelectionDAG/StatepointLowering.h |
llvm::TargetLowering::getConstraintPreferences(llvm::TargetLowering::AsmOperandInfo&) const | TargetLowering::ConstraintGroup TargetLowering::getConstraintPreferences(
TargetLowering::AsmOperandInfo &OpInfo) const {
ConstraintGroup Ret;
Ret.reserve(OpInfo.Codes.size());
for (StringRef Code : OpInfo.Codes) {
TargetLowering::ConstraintType CType = getConstraintType(Code);
// Indirect 'other' o... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 0x10(%rdi), %rsi
movq %rsi, (%rdi)
movabsq $0x200000000, %rax # imm = 0x200000000
movq %rax, 0x8(%rdi)
movq 0x18(%rdx), %rdx
subq 0x10(%r14), %rdx
sarq $0x5, %rdx
cmpq $0x3, %rdx
... | /CodeGen/SelectionDAG/TargetLowering.cpp |
llvm::DAGTypeLegalizer::SetPromotedInteger(llvm::SDValue, llvm::SDValue) | void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
assert(Result.getValueType() ==
TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
"Invalid type for promoted integer");
AnalyzeNewValue(Result);
auto &OpIdEntry = PromotedIntegers[getTableId(Op)];
assert((... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leaq 0x8(%rsp), %r12
movq %rcx, (%r12)
movl %r8d, 0x8(%r12)
movq %r12, %rsi
callq 0x17f86d0
leaq 0x270(%r15), %r13
movq %r15, %rdi
movq %r14, %rsi
movl %ebx, %edx
callq 0x17f875c
leaq 0x4(%... | /CodeGen/SelectionDAG/LegalizeTypes.cpp |
llvm::DenseMapBase<llvm::SmallDenseMap<unsigned int, llvm::SDValue, 8u, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::SDValue>>, unsigned int, llvm::SDValue, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::SDValue>>::find(unsigned int const... | iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*thi... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdx
callq 0x17fa20e
testb $0x1, (%rbx)
leaq 0x8(%rbx), %rcx
cmoveq 0x8(%rbx), %rcx
movl $0x8, %edx
cmovel 0x10(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
leaq (%rcx,%rdx,8), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x8, %rsp
pop... | /llvm/ADT/DenseMap.h |
llvm::DAGTypeLegalizer::ScalarizeVecRes_ExpOp(llvm::SDNode*) | SDValue DAGTypeLegalizer::ScalarizeVecRes_ExpOp(SDNode *N) {
SDValue Op = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op,
N->getOperand(1));
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movq (%rax), %rsi
movl 0x8(%rax), %edx
callq 0x180aea0
movq %rax, %r15
movl %edx, %r12d
movq 0x8(%r14), %r14
movl 0x18(%rbx), %ebp
movq 0x48(%rbx), %rsi
movq %rsi, 0x28(%rsp)
testq %r... | /CodeGen/SelectionDAG/LegalizeVectorTypes.cpp |
llvm::DAGTypeLegalizer::ScalarizeVecRes_VSELECT(llvm::SDNode*) | SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
SDValue Cond = N->getOperand(0);
EVT OpVT = Cond.getValueType();
SDLoc DL(N);
// The vselect result and true/value operands needs scalarizing, but it's
// not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
// See the similar ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x128, %rsp # imm = 0x128
movq %rsi, %r14
movq %rdi, %rbx
movq 0x28(%rsi), %rax
movq (%rax), %r12
movl 0x8(%rax), %r15d
movl 0xc(%rax), %eax
movl %eax, 0x34(%rsp)
movq 0x30(%r12), %rax
movq %r15, %rcx
shlq $0x4, %rcx
movb (%rax,%rcx), %d... | /CodeGen/SelectionDAG/LegalizeVectorTypes.cpp |
llvm::DAGTypeLegalizer::WidenVecRes_VECTOR_COMPRESS(llvm::SDNode*) | SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_COMPRESS(SDNode *N) {
SDValue Vec = N->getOperand(0);
SDValue Mask = N->getOperand(1);
SDValue Passthru = N->getOperand(2);
EVT WideVecVT =
TLI.getTypeToTransformTo(*DAG.getContext(), Vec.getValueType());
EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rdi, %r14
movq %rsi, 0x80(%rsp)
movq 0x28(%rsi), %rax
movq (%rax), %r15
movl 0x8(%rax), %edx
movq 0x28(%rax), %rbx
movl 0x30(%rax), %r13d
movq 0x50(%rax), %rcx
movq %rcx, 0x78(%rsp)
movl 0x58(%rax), %eax
movl %eax, 0x44(%rsp)
movq ... | /CodeGen/SelectionDAG/LegalizeVectorTypes.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::SDNode*, llvm::SDNode*, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseMapPair<llvm::SDNode*, llvm::SDNode*>>, llvm::SDNode*, llvm::SDNode*, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseMapPair<llvm::SDNode*, llvm::SDNode*>>::LookupBucketFor<llvm:... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x1832061
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movq (%rdi,%rbx), %rbx
cmpq %rbx, (%rsi)
jn... | /llvm/ADT/DenseMap.h |
hasOnlyLiveOutUses(llvm::SUnit const*) | size_t size() const { return Size; } | movl 0x80(%rdi), %ecx
testq %rcx, %rcx
sete %al
je 0x18377aa
movq 0x78(%rdi), %rdx
shlq $0x4, %rcx
xorl %esi, %esi
movl $0x1, %r8d
xorl %edi, %edi
movq (%rdx,%rsi), %r10
movb $0x1, %r9b
testb $0x6, %r10b
jne 0x1837794
andq $-0x8, %r10
movq (%r10), %r9
testq %r9, %r9
je 0x1837791
cmpl $0x31, 0x18(%r9)
jne 0x1837791
movq... | /llvm/ADT/SmallVector.h |
llvm::ScheduleDAGSDNodes::RegDefIter::Advance() | void ScheduleDAGSDNodes::RegDefIter::Advance() {
for (;Node;) { // Visit all glued nodes.
for (;DefIdx < NodeNumDefs; ++DefIdx) {
if (!Node->hasAnyUseOfValue(DefIdx))
continue;
ValueType = Node->getSimpleValueType(DefIdx);
++DefIdx;
return; // Found a normal regdef.
}
Node ... | cmpq $0x0, 0x8(%rdi)
je 0x183a527
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
xorl %r14d, %r14d
movl 0x10(%rbx), %esi
cmpl 0x14(%rbx), %esi
jae 0x183a4b8
movq 0x8(%rbx), %rdi
callq 0x1790dee
testb %al, %al
jne 0x183a505
movl 0x10(%rbx), %esi
incl %esi
movl %esi, 0x10(%rbx)
jmp 0x183a49c
movq 0x8(%rbx), %rcx
movzwl... | /CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp |
llvm::detail::DenseMapPair<llvm::MachineInstr const*, llvm::MachineFunction::CallSiteInfo>* llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, llvm::MachineFunction::CallSiteInfo, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, llvm::MachineFunction::... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0x183ba8b
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0... | /llvm/ADT/DenseMap.h |
llvm::DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(llvm::SDNode*) | SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
bool IsStrict = N->isStrictFPOpcode();
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDValue Op = N->getOperand(IsStrict ? 1 : 0);
SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
RTLIB::Libcall LC = RTLIB::get... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %rdi
callq 0x9f0c7a
movl %eax, %r15d
movq (%r14), %rdi
movq 0x8(%r14), %rax
movq 0x40(%rax), %rsi
movq 0x30(%rbx), %rax
movq 0x8(%rax), %rcx
movq (%rdi), %r8
movl (%rax... | /CodeGen/SelectionDAG/LegalizeFloatTypes.cpp |
llvm::DAGTypeLegalizer::SoftenFloatOp_LLROUND(llvm::SDNode*) | SDValue DAGTypeLegalizer::SoftenFloatOp_LLROUND(SDNode *N) {
EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
RTLIB::LLROUND_F32,
RTLIB::LLROUND_F64,
... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %rdi
callq 0x9f0c7a
movq 0x28(%rbx), %rcx
movzbl %al, %eax
leaq (%rax,%rax,4), %rax
movq (%rcx,%rax,8), %rdx
movl 0x8(%rcx,%rax,8), %eax
movq 0x30(%rdx), %rcx
shlq $0x4, %rax
movb (%rcx,%rax), %al
leal -0xc(%rax), %ecx
cmpb $0x10, %al
movl $0x1... | /CodeGen/SelectionDAG/LegalizeFloatTypes.cpp |
llvm::DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(llvm::SDNode*) | SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
EVT VT = NewLHS.getValueType();
NewLHS = GetSoftenedFloat(NewLHS);
NewRHS = GetSoftenedFloat(NewRHS);
TLI.soften... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movups (%rax), %xmm0
movaps %xmm0, 0x50(%rsp)
movups 0x28(%rax), %xmm0
movaps %xmm0, 0x40(%rsp)
movq 0xa0(%rax), %rax
movl 0x58(%rax), %eax
movl %eax, 0x3c(%rsp)
movq 0x50(%rsp), %rsi... | /CodeGen/SelectionDAG/LegalizeFloatTypes.cpp |
llvm::DAGTypeLegalizer::PromoteFloatOperand(llvm::SDNode*, unsigned int) | bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
LLVM_DEBUG(dbgs() << "Promote float operand " << OpNo << ": "; N->dump(&DAG));
SDValue R = SDValue();
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
r... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movl %edx, %ecx
leaq (%rcx,%rcx,4), %rcx
movq (%rax,%rcx,8), %rdx
movl 0x8(%rax,%rcx,8), %eax
movq 0x30(%rdx), %rdx
shlq $0x4, %rax
movq 0x8(%rdx,%rax), %rcx
movl (%rdx,%rax), %edx
xorl %r8d, %r8d
callq 0x17f9466
testb %al, %al
jne 0... | /CodeGen/SelectionDAG/LegalizeFloatTypes.cpp |
llvm::DAGTypeLegalizer::PromoteFloatOp_STORE(llvm::SDNode*, unsigned int) | SDValue DAGTypeLegalizer::PromoteFloatOp_STORE(SDNode *N, unsigned OpNo) {
StoreSDNode *ST = cast<StoreSDNode>(N);
SDValue Val = ST->getValue();
SDLoc DL(N);
SDValue Promoted = GetPromotedFloat(Val);
EVT VT = ST->getOperand(1).getValueType();
EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x60, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movq 0x28(%rax), %r15
movl 0x30(%rax), %ebp
movq 0x48(%rsi), %rsi
movq %rsi, 0x20(%rsp)
testq %rsi, %rsi
je 0x184dfe4
leaq 0x20(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbx), %eax
... | /CodeGen/SelectionDAG/LegalizeFloatTypes.cpp |
llvm::DAGTypeLegalizer::PromoteIntRes_SRL(llvm::SDNode*) | SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
SDValue RHS = N->getOperand(1);
if (N->getOpcode() != ISD::VP_SRL) {
// The input value must be properly zero extended.
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteIntege... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movq %rsi, %r15
movq %rdi, %r12
movq 0x28(%rsi), %rax
movq 0x28(%rax), %r14
movl 0x30(%rax), %ebx
movl 0x34(%rax), %ecx
movl %ecx, 0x44(%rsp)
cmpl $0x180, 0x18(%rsi) # imm = 0x180
jne 0x1856f1b
movq %rbx, %rbp
movq 0x50(%rax), %rbx
... | /CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp |
llvm::DAGTypeLegalizer::ExpandShiftWithKnownAmountBit(llvm::SDNode*, llvm::SDValue&, llvm::SDValue&) | bool DAGTypeLegalizer::
ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
unsigned Opc = N->getOpcode();
SDValue In = N->getOperand(0);
SDValue Amt = N->getOperand(1);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
EVT ShTy = Amt.getValueType();
unsigned ShBits... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x248, %rsp # imm = 0x248
movq %rcx, 0xa8(%rsp)
movq %rdx, %r12
movq %rsi, %r14
movq %rdi, %r15
movl 0x18(%rsi), %eax
movl %eax, 0x34(%rsp)
movq 0x28(%rsi), %rax
movq (%rax), %rcx
movq %rcx, 0x60(%rsp)
movl 0x8(%rax), %ecx
movl %ecx, 0x3... | /CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp |
llvm::DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(llvm::SDNode*) | SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
SDValue Lo, Hi;
GetExpandedOp(N->getOperand(0), Lo, Hi);
return N->getConstantOperandVal(1) ? Hi : Lo;
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %r15
xorl %ebp, %ebp
leaq 0x20(%rsp), %r12
movq %rbp, -0x8(%r12)
movl %ebp, (%r12)
leaq 0x10(%rsp), %r13
movq %rbp, -0x8(%r13)
movl %ebp, (%r13)
movq 0x28(%rsi), %rax
movq (%rax), %rsi
movl 0x8(%rax), %edx
leaq 0x18(%rsp), %r1... | /CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp |
llvm::detail::DenseMapPair<llvm::MCRegister, int>* llvm::DenseMapBase<llvm::DenseMap<llvm::MCRegister, int, llvm::DenseMapInfo<llvm::MCRegister, void>, llvm::detail::DenseMapPair<llvm::MCRegister, int>>, llvm::MCRegister, int, llvm::DenseMapInfo<llvm::MCRegister, void>, llvm::detail::DenseMapPair<llvm::MCRegister, int>... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0x18930a1
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0... | /llvm/ADT/DenseMap.h |
llvm::AMDGPUInstPrinter::printImmediateF16(unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) | void AMDGPUInstPrinter::printImmediateF16(uint32_t Imm,
const MCSubtargetInfo &STI,
raw_ostream &O) {
int16_t SImm = static_cast<int16_t>(Imm);
if (isInlinableIntLiteral(SImm)) {
O << SImm;
return;
}
uint16_t HImm = sta... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movswq %si, %rax
addq $0x10, %rax
cmpq $0x50, %rax
ja 0x18b656b
movswq %si, %rsi
movq %rbx, %rdi
addq $0x18, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
jmp 0x2b7d122
movq %rdi, %r14
movzwl %si, %ebp
movl %ebp, %edi
movq %rdx, %rsi
movq %rbx,... | /Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp |
(anonymous namespace)::R600MCCodeEmitter::encodeInstruction(llvm::MCInst const&, llvm::SmallVectorImpl<char>&, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const | void R600MCCodeEmitter::encodeInstruction(const MCInst &MI,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCInstrDesc &Desc = MCII.get(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, %r15
movq %rdx, %rbx
movq %rsi, %r14
movl (%rsi), %eax
cmpl $0x15c, %eax # imm = 0x15C
jle 0x18bfc09
cmpl $0x15d, %eax # imm = 0x15D
je 0x18bfd80
cmpl $0x164, %eax # imm = 0x164
je 0x18bfd80
cmp... | /Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp |
llvm::AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(llvm::Triple const&, llvm::MCTargetOptions const&) | AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
const MCTargetOptions &Options) {
CodePointerSize = (TT.getArch() == Triple::amdgcn) ? 8 : 4;
StackGrowsUp = true;
HasSingleParameterDotFile = false;
//===------------------------------------------------------------------===//
... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
callq 0x28caab8
leaq 0x3f5f9be(%rip), %rax # 0x5821ce0
movq %rax, (%rbx)
xorl %eax, %eax
cmpl $0x1a, 0x20(%r14)
sete %al
leal 0x4(,%rax,4), %ecx
movl %ecx, 0x8(%rbx)
movb $0x1, %cl
movb %cl, 0x11(%rbx)
xorl %edx, %edx
movb %dl, 0x16c(%rbx)
movl $0x4, 0x... | /Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp |
llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode(unsigned int) | unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc) {
const WMMAOpcodeMappingInfo *Info = getWMMAMappingInfoFrom2AddrOpcode(Opc);
return Info ? Info->Opcode3Addr : ~0u;
} | movl $0x22, %ecx
leaq 0x2e0cb5c(%rip), %rax # 0x4722b40
movq %rcx, %rdx
shrq %rdx
movq %rdx, %rsi
notq %rsi
addq %rcx, %rsi
leaq (%rax,%rdx,8), %rcx
addq $0x8, %rcx
cmpl %edi, -0x8(%rcx)
cmovaeq %rdx, %rsi
cmovbq %rcx, %rax
movq %rsi, %rcx
testq %rsi, %rsi
jg 0x1915fe4
leaq 0x2e0cc3b(%rip), %rcx # 0x4722c50
cmpq %r... | /Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp |
llvm::AMDGPU::getIntegerPairAttribute(llvm::Function const&, llvm::StringRef, std::pair<unsigned int, unsigned int>, bool) | std::pair<unsigned, unsigned>
getIntegerPairAttribute(const Function &F, StringRef Name,
std::pair<unsigned, unsigned> Default,
bool OnlyFirstRequired) {
Attribute A = F.getFnAttribute(Name);
if (!A.isStringAttribute())
return Default;
LLVMContext &Ctx = F.getC... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movl %r8d, %ebx
movq %rcx, %rbp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
callq 0x2a40aac
leaq 0x18(%rsp), %rdi
movq %rax, (%rdi)
callq 0x29a8f12
testb %al, %al
je 0x19176fe
movl %ebx, 0xc(%rsp)
movq %r12, %rdi
callq 0x2a3b1a0
movq... | /Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp |
llvm::AMDGPU::decodeStorecntDscnt(llvm::AMDGPU::IsaVersion const&, unsigned int) | Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt) {
Waitcnt Decoded;
Decoded.StoreCnt =
unpackBits(StorecntDscnt, getLoadcntStorecntBitShift(Version.Major),
getStorecntBitWidth(Version.Major));
Decoded.DsCnt = unpackBits(StorecntDscnt, getDscntBitShift(Version.M... | movq %rdi, %rax
pcmpeqd %xmm0, %xmm0
movdqu %xmm0, 0xc(%rdi)
movdqu %xmm0, (%rdi)
movl (%rsi), %ecx
xorl %esi, %esi
cmpl $0xa, %ecx
movl $0x3f, %edi
movl $0x0, %r8d
cmovael %edi, %r8d
cmpl $0xc, %ecx
setae %cl
cmovael %edi, %esi
shlb $0x3, %cl
andl %edx, %esi
shrl %cl, %edx
andl %r8d, %edx
movl %edx, 0xc(%rax)
movl %es... | /Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp |
llvm::AMDGPU::SendMsg::msgRequiresOp(long, llvm::MCSubtargetInfo const&) | bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI) {
return MsgId == ID_SYSMSG ||
(!isGFX11Plus(STI) &&
(MsgId == ID_GS_PreGFX11 || MsgId == ID_GS_DONE_PreGFX11));
} | movb $0x1, %al
cmpq $0xf, %rdi
je 0x1918ae4
testb $0x28, 0xe2(%rsi)
je 0x1918ae5
xorl %eax, %eax
retq
andq $-0x2, %rdi
cmpq $0x2, %rdi
sete %al
retq
| /Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp |
llvm::AMDGPU::getNSAMaxSize(llvm::MCSubtargetInfo const&, bool) | unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler) {
auto Version = getIsaVersion(STI.getCPU());
if (Version.Major == 10)
return Version.Minor >= 3 ? 13 : 5;
if (Version.Major == 11)
return 5;
if (Version.Major >= 12)
return HasSampler ? 4 : 5;
return 0;
} | pushq %rbx
movl %esi, %ebx
movq 0x40(%rdi), %rax
movq 0x48(%rdi), %rsi
movq %rax, %rdi
callq 0x2afdb5f
cmpl $0xb, %eax
je 0x1918d89
cmpl $0xa, %eax
jne 0x1918d90
shrq $0x20, %rax
xorl %ecx, %ecx
cmpl $0x3, %eax
setae %cl
leal 0x5(,%rcx,8), %ecx
jmp 0x1918d9e
movl $0x5, %ecx
jmp 0x1918d9e
movzbl %bl, %edx
xorl $0x5, %ed... | /Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp |
llvm::AMDGPU::eliminateConstantExprUsesOfLDSFromAllInstructions(llvm::Module&) | bool eliminateConstantExprUsesOfLDSFromAllInstructions(Module &M) {
// Constants are uniqued within LLVM. A ConstantExpr referring to a LDS
// global may have uses from multiple different functions as a result.
// This pass specialises LDS variables with respect to the kernel that
// allocates them.
// This ... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x40, %rsp
movq %rdi, %rbx
leaq 0x10(%rsp), %r12
movq %r12, -0x10(%r12)
movabsq $0x600000000, %rax # imm = 0x600000000
movq %rax, -0x8(%r12)
movq 0x10(%rdi), %r13
addq $0x8, %rbx
cmpq %rbx, %r13
je 0x191a9d5
movq %rsp, %r14
leaq -0x38(%r13), %r15
testq %... | /Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp |
bool llvm::set_union<llvm::DenseSet<llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>>, llvm::DenseSet<llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>>>(llvm::DenseSet<llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>>&, llvm::DenseSet<llvm::GlobalVariabl... | bool set_union(S1Ty &S1, const S2Ty &S2) {
bool Changed = false;
for (const auto &E : S2)
if (S1.insert(E).second)
Changed = true;
return Changed;
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq 0xc9f43a
movl 0x10(%r13), %r12d
shlq $0x3, %r12
addq (%r13), %r12
cmpq %r12, %rax
je 0x191b46a
movq %rax, %r14
movq %rdx, %r15
xorl %ebp, %ebp
movl $0x1000, %r13d # imm = 0x1... | /llvm/ADT/SetOperations.h |
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::MCExpr const*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MCExpr const*>>, unsigned int, llvm::MCExpr const*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MCExpr const*>>::clear() | unsigned getNumEntries() const {
return NumEntries;
} | movl 0x8(%rdi), %eax
testl %eax, %eax
jne 0x191db61
cmpl $0x0, 0xc(%rdi)
je 0x191dc99
shll $0x2, %eax
movl 0x10(%rdi), %ecx
cmpl %ecx, %eax
setae %al
cmpl $0x41, %ecx
setb %dl
orb %al, %dl
je 0x191e696
testq %rcx, %rcx
je 0x191dc91
movq (%rdi), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, ... | /llvm/ADT/DenseMap.h |
llvm::AMDGPUPALMetadata::refComputeRegister(llvm::StringRef) | msgpack::DocNode *AMDGPUPALMetadata::refComputeRegister(StringRef field) {
auto M = getComputeRegisters();
auto I = M.find(field);
return I == M.end() ? nullptr : &I->second;
} | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %rsi
leaq 0x8(%rsp), %r15
movq %r15, %rdi
callq 0x191d86e
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq 0x2ae0bc4
movq 0x8(%r15), %rdx
addq $0x8, %rdx
leaq 0x38(%rax), %rsi
xorl %ecx, %ecx
cmpq %rdx, %rax
cmovneq %rsi, ... | /Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp |
bool llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::MCExpr const*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MCExpr const*>>, unsigned int, llvm::MCExpr const*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MCExpr const*>>::Loo... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x191e2ae
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %esi
leal (%rsi,%rsi,8), %eax
leal (%rsi,%rax,4), %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movl (%rdi,%rbx), %ebx
cmpl %ebx, %esi
jne 0x191e279
movq... | /llvm/ADT/DenseMap.h |
llvm::AMDGPU::AMDGPUMCKernelCodeT::EmitKernelCodeT(llvm::raw_ostream&, llvm::MCContext&) | void AMDGPUMCKernelCodeT::EmitKernelCodeT(raw_ostream &OS, MCContext &Ctx) {
const int Size = hasMCExprVersionTable().size();
for (int i = 0; i < Size; ++i) {
OS << "\t\t";
if (hasMCExprVersionTable()[i]) {
OS << get_amd_kernel_code_t_FldNames()[i + 1] << " = ";
int64_t Val;
const MCExpr *... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, (%rsp)
movq %rsi, %r14
movq %rdi, 0x8(%rsp)
xorl %r12d, %r12d
leaq 0x36371e5(%rip), %rbp # 0x4f55e87
leaq 0x2e083b7(%rip), %rbx # 0x4727060
xorl %r13d, %r13d
movl $0x2, %edx
movq %r14, %rdi
movq %rbp, %rsi
callq 0x7f9ba8
c... | /Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp |
llvm::ARMInstPrinter::printT2AddrModeSoRegOperand(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) | void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
const MCOperand &MO1 = MI->getOperand(OpNu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r8, %rbx
movl %edx, %r15d
movq %rdi, %r14
movl %edx, %ebp
movq 0x10(%rsi), %r12
leal 0x1(%r15), %r13d
addl $0x2, %r15d
leaq 0x8(%rsp), %rdi
movq %r14, %rsi
movq %r8, %rdx
movl $0x3, %ecx
callq 0x28e4bf6
leaq 0x2fd3af9(%rip), %rsi ... | /Target/ARM/MCTargetDesc/ARMInstPrinter.cpp |
llvm::ARMInstPrinter::printFBits32(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) | void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O) {
markup(O, Markup::Immediate) << "#" << 32 - MI->getOperand(OpNum).getImm();
} | pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %rsi
movq %rsp, %rbx
movq %rbx, %rdi
movq %r8, %rdx
xorl %ecx, %ecx
callq 0x28e4bf6
movq (%rbx), %rdi
leaq 0x2e9e43e(%rip), %rsi # 0x47c8290
movl $0x1, %edx
callq 0x7f9ba8
movl %ebp, %eax
movq 0x10(%r14), %rcx
shlq $0x4, %rax... | /Target/ARM/MCTargetDesc/ARMInstPrinter.cpp |
llvm::ARMInstPrinter::printT2AddrModeImm8OffsetOperand(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) | void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(
const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
raw_ostream &O) {
const MCOperand &MO1 = MI->getOperand(OpNum);
int32_t OffImm = (int32_t)MO1.getImm();
O << ", ";
WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
if (OffImm == ... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %r8, %r14
movq %rdi, %r15
movl %edx, %eax
movq 0x10(%rsi), %rcx
shlq $0x4, %rax
movq 0x8(%rcx,%rax), %rbx
leaq 0x265671e(%rip), %rsi # 0x3f805cd
movl $0x2, %edx
movq %r8, %rdi
callq 0x7f9ba8
movq %rsp, %rdi
movq %r15, %rsi
movq %r14, %rdx
xorl %ecx, %ecx
callq 0x... | /Target/ARM/MCTargetDesc/ARMInstPrinter.cpp |
llvm::ARMInstPrinter::printMveSaturateOp(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&) | void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
uint32_t Val = MI->getOperand(OpNum).getImm();
assert(Val <= 1 && "Invalid MVE saturate operand");
O << "#" << (Va... | pushq %rbx
movq %r8, %rdi
movl %edx, %eax
movq 0x10(%rsi), %rcx
shlq $0x4, %rax
movl 0x8(%rcx,%rax), %ebx
leaq 0x2e9d12d(%rip), %rsi # 0x47c8290
movl $0x1, %edx
callq 0x7f9ba8
xorl %esi, %esi
cmpl $0x1, %ebx
setne %sil
shll $0x4, %esi
addq $0x30, %rsi
movq %rax, %rdi
popq %rbx
jmp 0x2b7d122
| /Target/ARM/MCTargetDesc/ARMInstPrinter.cpp |
printRegImmShift(llvm::raw_ostream&, llvm::ARM_AM::ShiftOpc, unsigned int, llvm::ARMInstPrinter const&) | static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
unsigned ShImm, const ARMInstPrinter &printer) {
if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
return;
O << ", ";
assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
O << ge... | testl %esi, %esi
je 0x192c415
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x10, %rsp
movl %edx, %ebx
movl %esi, %ebp
movl %esi, %eax
xorl $0x2, %eax
orl %edx, %eax
je 0x192c409
movq %rcx, %r14
movq %rdi, %r15
leaq 0x265424d(%rip), %rsi # 0x3f805cd
movl $0x2, %edx
callq 0x7f9ba8
movslq %ebp, %rax
leaq... | /Target/ARM/MCTargetDesc/ARMInstPrinter.cpp |
llvm::createARMWinCOFFStreamer(llvm::MCContext&, std::unique_ptr<llvm::MCAsmBackend, std::default_delete<llvm::MCAsmBackend>>&&, std::unique_ptr<llvm::MCObjectWriter, std::default_delete<llvm::MCObjectWriter>>&&, std::unique_ptr<llvm::MCCodeEmitter, std::default_delete<llvm::MCCodeEmitter>>&&) | MCStreamer *
llvm::createARMWinCOFFStreamer(MCContext &Context,
std::unique_ptr<MCAsmBackend> &&MAB,
std::unique_ptr<MCObjectWriter> &&OW,
std::unique_ptr<MCCodeEmitter> &&Emitter) {
return new ARMWinCOFFStreamer(Context, std... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x20, %rsp
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movl $0x1b8, %edi # imm = 0x1B8
callq 0x7808d0
movq %rax, %rbx
movq (%r12), %rax
xorl %ecx, %ecx
movq %rcx, (%r12)
movq (%r14), %rsi
movq %rcx, (%r14)
movq (%r15), %rdi
movq... | /Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp |
(anonymous namespace)::ARMTargetWinCOFFStreamer::emitARMWinCFIPrologEnd(bool) | void ARMTargetWinCOFFStreamer::emitARMWinCFIPrologEnd(bool Fragment) {
auto &S = getStreamer();
WinEH::FrameInfo *CurFrame = S.EnsureValidWinFrameInfo(SMLoc());
if (!CurFrame)
return;
MCSymbol *Label = S.emitCFILabel();
CurFrame->PrologEnd = Label;
WinEH::Instruction Inst =
WinEH::Instruction(Win... | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movl %esi, %ebx
movq 0x8(%rdi), %r15
movq %r15, %rdi
xorl %esi, %esi
callq 0x28f78a0
testq %rax, %rax
je 0x19304cb
movq %rax, %r14
movq (%r15), %rax
movq %r15, %rdi
callq *0x58(%rax)
movq %rax, 0x28(%r14)
leaq 0x8(%rsp), %rdx
movq $0x0, (%rdx)
movabsq $-0x100000000, %ra... | /Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp |
llvm::createARMTargetAsmStreamer(llvm::MCStreamer&, llvm::formatted_raw_ostream&, llvm::MCInstPrinter*) | MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &OS,
MCInstPrinter *InstPrint) {
return new ARMTargetAsmStreamer(S, OS, *InstPrint);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl $0x30, %edi
callq 0x7808d0
movq %rax, %r12
movq %rax, %rdi
movq %r15, %rsi
callq 0x192f834
leaq 0x3f034f0(%rip), %rax # 0x5837718
movq %rax, (%r12)
movq %r14, 0x18(%r12)
movq %rbx, 0x20(%r12)
movq (%r15), %rax
... | /Target/ARM/MCTargetDesc/ARMELFStreamer.cpp |
(anonymous namespace)::ARMTargetAsmStreamer::emitSetFP(unsigned int, unsigned int, long) | void ARMTargetAsmStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
int64_t Offset) {
OS << "\t.setfp\t";
InstPrinter.printRegName(OS, FpReg);
OS << ", ";
InstPrinter.printRegName(OS, SpReg);
if (Offset)
OS << ", #" << Offset;
OS << '\n';
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rcx, %r14
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %rbx
movq 0x18(%rdi), %rdi
leaq 0x2e93c97(%rip), %rsi # 0x47c8278
movl $0x8, %edx
callq 0x7f9ba8
movq 0x18(%rbx), %rsi
movq 0x20(%rbx), %rdi
movq (%rdi), %rax
movl %r15d, %edx
callq *0x28(%rax)
movq 0x18... | /Target/ARM/MCTargetDesc/ARMELFStreamer.cpp |
(anonymous namespace)::ARMTargetAsmStreamer::emitARMWinCFISaveRegMask(unsigned int, bool) | void ARMTargetAsmStreamer::emitARMWinCFISaveRegMask(unsigned Mask, bool Wide) {
if (Wide)
OS << "\t.seh_save_regs_w\t";
else
OS << "\t.seh_save_regs\t";
ListSeparator LS;
int First = -1;
OS << "{";
for (int I = 0; I <= 12; I++) {
if (Mask & (1 << I)) {
if (First < 0)
First = I;
... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movl %esi, %ebp
movq %rdi, %rbx
movq 0x18(%rdi), %rdi
testl %edx, %edx
je 0x1934f2f
leaq 0x2e93413(%rip), %rsi # 0x47c833b
movl $0x12, %edx
jmp 0x1934f3b
leaq 0x2e93418(%rip), %rsi # 0x47c834e
movl $0x10, %edx
callq 0x7f9ba8
movq %rsp, %r14
movb $0x1, (%r... | /Target/ARM/MCTargetDesc/ARMELFStreamer.cpp |
(anonymous namespace)::ARMELFStreamer::SwitchToEHSection(llvm::StringRef, unsigned int, unsigned int, llvm::SectionKind, llvm::MCSymbol const&) | inline void ARMELFStreamer::SwitchToEHSection(StringRef Prefix,
unsigned Type,
unsigned Flags,
SectionKind Kind,
const MCSymbol &Fn) {
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %r8d, (%rsp)
movl %ecx, 0x4(%rsp)
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %rbx
movq %r9, %rdi
movl $0x1, %esi
callq 0x858016
movq 0x8(%rax), %r14
movq 0x80(%r14), %r15
movq 0x88(%r14), %r12
addq %rbp, %r13
leaq 0x20(%rsp), %rcx
m... | /Target/ARM/MCTargetDesc/ARMELFStreamer.cpp |
(anonymous namespace)::ARMELFStreamer::changeSection(llvm::MCSection*, unsigned int) | void changeSection(MCSection *Section, uint32_t Subsection) override {
LastMappingSymbols[getCurrentSection().first] = std::move(LastEMSInfo);
MCELFStreamer::changeSection(Section, Subsection);
auto LastMappingSymbol = LastMappingSymbols.find(Section);
if (LastMappingSymbol != LastMappingSymbols.end()) ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %rbx
leaq 0x19d0(%rdi), %r14
movl 0x80(%rdi), %eax
testq %rax, %rax
je 0x19371cb
movq 0x78(%rbx), %rcx
shlq $0x5, %rax
movq -0x20(%rcx,%rax), %r13
jmp 0x19371ce
xorl %r13d, %r13d
leaq 0x10(%rsp)... | /Target/ARM/MCTargetDesc/ARMELFStreamer.cpp |
llvm::UnwindOpcodeAssembler::EmitInt16(unsigned int) | void EmitInt16(unsigned Opcode) {
Ops.push_back((Opcode >> 8) & 0xff);
Ops.push_back(Opcode & 0xff);
OpBegins.push_back(OpBegins.back() + 2);
} | pushq %rbp
pushq %r14
pushq %rbx
movl %esi, %ebx
movq %rdi, %r14
shrl $0x8, %esi
movl $0xff, %ebp
andl %ebp, %esi
callq 0x88863a
andl %ebp, %ebx
movq %r14, %rdi
movl %ebx, %esi
callq 0x88863a
leaq 0x38(%r14), %rdi
movq 0x38(%r14), %rax
movl 0x40(%r14), %ecx
movl -0x4(%rax,%rcx,4), %esi
addl $0x2, %esi
popq %rbx
popq %r... | /Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h |
llvm::AVRMCExpr::getKindByName(llvm::StringRef) | AVRMCExpr::VariantKind AVRMCExpr::getKindByName(StringRef Name) {
const auto &Modifier =
llvm::find_if(ModifierNames, [&Name](ModifierEntry const &Mod) {
return Mod.Spelling == Name;
});
if (Modifier != std::end(ModifierNames)) {
return Modifier->VariantKind;
}
return VK_AVR_None;
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x20, %rsp
leaq 0x10(%rsp), %rax
movq %rdi, (%rax)
movq %rsi, 0x8(%rax)
leaq 0x8(%rsp), %rbx
movq %rax, (%rbx)
leaq 0x3ef1960(%rip), %r14 # 0x5839a90
movl $0x4, %r13d
leaq 0x3ef1a13(%rip), %r12 # 0x5839b50
movq %rbx, %rdi
movq %r14, %rsi
callq 0x19481cc
t... | /Target/AVR/MCTargetDesc/AVRMCExpr.cpp |
(anonymous namespace)::BPFAsmBackend::getFixupKindInfo(llvm::MCFixupKind) const | const MCFixupKindInfo &
BPFAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[BPF::NumTargetFixupKinds] = {
{ "FK_BPF_PCRel_4", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
};
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
assert(unsigne... | cmpl $0x7f, %esi
jg 0x194b12c
jmp 0x28c9cec
addl $-0x80, %esi
leaq (%rsi,%rsi,2), %rax
leaq 0x3ef7956(%rip), %rcx # 0x5842a90
leaq (%rcx,%rax,8), %rax
retq
nop
| /Target/BPF/MCTargetDesc/BPFAsmBackend.cpp |
llvm::BPFInstPrinter::printBrTargetOperand(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) | void BPFInstPrinter::printBrTargetOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isImm()) {
if (MI->getOpcode() == BPF::JMPL) {
int32_t Imm = Op.getImm();
O << ((Imm >= 0) ? "+" : "") << formatImm(I... | pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movl %edx, %eax
movq 0x10(%rsi), %rdx
shlq $0x4, %rax
leaq (%rdx,%rax), %rdi
movzbl (%rdx,%rax), %eax
cmpl $0x5, %eax
je 0x194bc4d
cmpl $0x2, %eax
jne 0x194bc62
cmpl $0x154, (%rsi) # imm = 0x154
movq 0x8(%rdi), %r15
jne 0x194bc75
testl %r15d, %r... | /Target/BPF/MCTargetDesc/BPFInstPrinter.cpp |
llvm::SmallVectorTemplateBase<llvm::MCInst const*, true>::push_back(llvm::MCInst const*) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0x1958cb7
movq (%rbx), %rax
movl 0x8(%rbx), %ecx
movq %r14, (%rax,%rcx,8)
incl 0x8(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
incq %rdx
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
callq 0x2b4ed86... | /llvm/ADT/SmallVector.h |
llvm::HexagonMCELFStreamer::HexagonMCELFStreamer(llvm::MCContext&, std::unique_ptr<llvm::MCAsmBackend, std::default_delete<llvm::MCAsmBackend>>, std::unique_ptr<llvm::MCObjectWriter, std::default_delete<llvm::MCObjectWriter>>, std::unique_ptr<llvm::MCCodeEmitter, std::default_delete<llvm::MCCodeEmitter>>, llvm::MCAssem... | HexagonMCELFStreamer::HexagonMCELFStreamer(
MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
std::unique_ptr<MCObjectWriter> OW, std::unique_ptr<MCCodeEmitter> Emitter,
MCAssembler *Assembler)
: MCELFStreamer(Context, std::move(TAB), std::move(OW), std::move(Emitter)),
MCII(createHexagonMCIn... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movq (%rdx), %rdi
leaq 0x8(%rsp), %rax
movq %rdi, (%rax)
xorl %edi, %edi
movq %rdi, (%rdx)
movq (%rcx), %rdx
movq %rsp, %r9
movq %rdx, (%r9)
movq %rdi, (%rcx)
movq (%r8), %rcx
leaq 0x10(%rsp), %r14
movq %rcx, (%r14)
movq %rdi, (%r8)
movq %rbx, %rdi
movq %rax, %rdx
... | /Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp |
createHexagonMCAsmInfo(llvm::MCRegisterInfo const&, llvm::Triple const&, llvm::MCTargetOptions const&) | static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT,
const MCTargetOptions &Options) {
MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
// VirtualFP = (R30 + #0).
MCCFIInstruction Inst = MCCFIInstruction:... | pushq %r15
pushq %r14
pushq %rbx
subq $0x70, %rsp
movq %rsi, %r14
movq %rdi, %r15
movl $0x1e8, %edi # imm = 0x1E8
callq 0x7808d0
movq %rax, %rbx
movq %rax, %rdi
movq %r14, %rsi
callq 0x196439a
movq %r15, %rdi
movl $0x94, %esi
movl $0x1, %edx
callq 0x28f28d0
xorl %ecx, %ecx
leaq 0x60(%rsp), %r15
movq %rcx, -0... | /Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp |
llvm::HexagonShuffler::permitNonSlot() | size_t size() const { return Size; } | movl 0x8(%rdi), %eax
testq %rax, %rax
je 0x195f65e
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq (%rdi), %r14
shlq $0x3, %rax
leaq (%rax,%rax,4), %r15
xorl %r12d, %r12d
movq 0x140(%rbx), %rdi
movq (%r14,%r12), %rsi
callq 0x195b8f5
testb %al, %al
jne 0x195f64a
movq $0xf, 0x10(%r14,%r12)
add... | /llvm/ADT/SmallVector.h |
llvm::SmallVectorTemplateBase<CVIUnits, true>::push_back(CVIUnits) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0x196035f
movq (%rbx), %rax
movl 0x8(%rbx), %ecx
movq %r14, (%rax,%rcx,8)
incl 0x8(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
incq %rdx
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
callq 0x2b4ed86... | /llvm/ADT/SmallVector.h |
llvm::HexagonMCInstrInfo::deriveSubInst(llvm::MCInst const&) | MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
MCInst Result;
Result.setLoc(Inst.getLoc());
bool Absolute;
int64_t Value;
switch (Inst.getOpcode()) {
default:
// dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
llvm_unreachable("Unimplemented subinstruction \n");
break;
case H... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x20(%rdi), %rax
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq %rax, 0x10(%rdi)
movabsq $0x600000000, %rax # imm = 0x600000000
movq %rax, 0x18(%rdi)
movq 0x8(%rsi), %rax
movq %rax, 0x8(%rdi)
movl (%rsi), %eax
cmpl $0x5fa, %eax ... | /Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp |
llvm::LanaiInstPrinter::printHi16ImmOperand(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) | void LanaiInstPrinter::printHi16ImmOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &OS) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isImm()) {
OS << formatHex(Op.getImm() << 16);
} else {
// Symbolic operand will be lowered to immediate value by lin... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movq %rdi, %rax
movl %edx, %edx
movq 0x10(%rsi), %rsi
shlq $0x4, %rdx
leaq (%rsi,%rdx), %rcx
cmpb $0x2, (%rsi,%rdx)
jne 0x196cf6a
movq 0x8(%rcx), %rdx
shlq $0x10, %rdx
movq %rsp, %r14
movq %r14, %rdi
movq %rax, %rsi
callq 0x28e4a56
movq %rbx, %rdi
movq %r14, %rsi
c... | /Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp |
llvm::LanaiInstPrinter::printMemoryStoreIncrement(llvm::MCInst const*, llvm::raw_ostream&, llvm::StringRef, int) | bool LanaiInstPrinter::printMemoryStoreIncrement(const MCInst *MI,
raw_ostream &OS,
StringRef Opcode,
int AddOffset) {
if (isPreIncrementForm(MI, AddOffset)) {
OS << "... | pushq %r15
pushq %r14
pushq %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %rdi
movq %rsi, %rbx
movq 0x10(%rsi), %rax
movq 0x38(%rax), %rcx
movl %ecx, %edx
andl $0x47, %edx
cmpl $0x40, %edx
jne 0x196d64c
movq 0x28(%rax), %rdx
movslq %r9d, %rsi
cmpq %rsi, %rdx
je 0x196d584
movl %r9d, %esi
negl %esi
movslq %esi, %rsi
cmp... | /Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp |
(anonymous namespace)::LanaiELFObjectWriter::getRelocType(llvm::MCContext&, llvm::MCValue const&, llvm::MCFixup const&, bool) const | MCFixupKind getKind() const { return Kind; } | movl 0xc(%rcx), %eax
addl $-0x80, %eax
cmpl $0x6, %eax
ja 0x196e204
leaq 0x2eef3d0(%rip), %rcx # 0x485d5c8
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
xorl %eax, %eax
retq
movl $0x4, %eax
retq
movl $0x3, %eax
retq
movl $0x1, %eax
retq
movl $0x2, %eax
retq
movl $0x5, %eax
retq
movl $0x6, %eax
retq
| /llvm/MC/MCFixup.h |
llvm::LoongArchMCExpr::printImpl(llvm::raw_ostream&, llvm::MCAsmInfo const*) const | void LoongArchMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
VariantKind Kind = getKind();
bool HasVariant =
((Kind != VK_LoongArch_None) && (Kind != VK_LoongArch_CALL));
if (HasVariant)
OS << '%' << getVariantKindName(getKind()) << '(';
Expr->print(OS, MAI);
if (HasVariant)
O... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r14
movq %rsi, %rbx
movq %rdi, %r15
cmpl $0x2, 0x20(%rdi)
jb 0x196f4d1
movq 0x20(%rbx), %rax
cmpq 0x18(%rbx), %rax
jae 0x196f4ed
leaq 0x1(%rax), %rcx
movq %rcx, 0x20(%rbx)
movb $0x25, (%rax)
movq %rbx, %r12
jmp 0x196f4fd
movq 0x18(%r15), %rdi
movq %rbx,... | /Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp |
(anonymous namespace)::LoongArchMCInstrAnalysis::evaluateBranch(llvm::MCInst const&, unsigned long, unsigned long, unsigned long&) const | bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const override {
unsigned NumOps = Inst.getNumOperands();
if ((isBranch(Inst) && !isIndirectBranch(Inst)) ||
Inst.getOpcode() == LoongArch::BL) {
Target = Addr + Inst.getOperand(NumOps - 1... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl 0x18(%rsi), %r13d
movq (%rdi), %rax
callq *0x20(%rax)
testb %al, %al
je 0x19706a8
movq (%r12), %rax
movq %r12, %rdi
movq %r15, %rsi
callq *0x38(%rax)
testb %al, %al
je 0x19706b5
cmpl $0x1f0, (%r15)... | /Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp |
llvm::LoongArchAsmBackend::shouldInsertExtraNopBytesForCodeAlign(llvm::MCAlignFragment const&, unsigned int&) | const MCSubtargetInfo *getSubtargetInfo() const { return STI; } | movq 0x30(%rsi), %rcx
xorl %eax, %eax
testb $0x2, 0xd9(%rcx)
je 0x1971eaa
cmpl $0x4, 0x2c(%rsi)
jb 0x1971eaa
movb 0x1e(%rsi), %cl
movl $0x1, %eax
shlq %cl, %rax
addl $-0x4, %eax
movl %eax, (%rdx)
cmpb $0x3, 0x1e(%rsi)
setae %al
retq
nop
| /llvm/MC/MCFragment.h |
fixELFSymbolsInTLSFixupsImpl(llvm::MCExpr const*, llvm::MCAssembler&) | static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {
switch (Expr->getKind()) {
case MCExpr::Target:
fixELFSymbolsInTLSFixupsImpl(cast<MipsMCExpr>(Expr)->getSubExpr(), Asm);
break;
case MCExpr::Constant:
break;
case MCExpr::Binary: {
const MCBinaryExpr *BE = cast<MCBi... | pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
leaq 0x2f1c07d(%rip), %r14 # 0x4893c80
movzbl (%rbx), %eax
cmpq $0x4, %rax
ja 0x1977c3f
movslq (%r14,%rax,4), %rax
addq %r14, %rax
jmpq *%rax
movq 0x10(%rbx), %rdi
callq 0x1977bf5
movq 0x18(%rbx), %rbx
jmp 0x1977c03
movq 0x10(%rbx), %rbx
jmp 0x1977c03
movq 0x10(%rbx), ... | /Target/Mips/MCTargetDesc/MipsMCExpr.cpp |
llvm::isBasePlusOffsetMemoryAccess(unsigned int, unsigned int*, bool*) | bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
bool *IsStore) {
if (IsStore)
*IsStore = false;
switch (Opcode) {
default:
return false;
// Load instructions with base address register in position 1.
case Mips::LB:
case Mips::LBu:
case Mips... | testq %rdx, %rdx
je 0x1978418
movb $0x0, (%rdx)
xorl %eax, %eax
cmpl $0x996, %edi # imm = 0x996
jg 0x1978461
leal -0x743(%rdi), %ecx
cmpl $0x38, %ecx
ja 0x197843d
movabsq $0x102020000010401, %rdx # imm = 0x102020000010401
btq %rcx, %rdx
jb 0x1978458
addl $0xfffff87c, %edi # imm = 0xFFFFF87C
cmpl $0x24,... | /Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp |
llvm::MipsTargetStreamer::emitLoadWithImmOffset(unsigned int, unsigned int, unsigned int, long, unsigned int, llvm::SMLoc, llvm::MCSubtargetInfo const*) | void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
unsigned BaseReg, int64_t Offset,
unsigned TmpReg, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
if... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, %r14
movl %ecx, %r13d
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %r12
movswq %r14w, %rax
cmpq %r8, %rax
jne 0x197928e
movl %r13d, %ebx
jmp 0x19792fe
movl %r9d, %ebx
movq 0x58(%rsp), %rax
movq 0x50(%rsp), %r9
movl %r14d, %r8d
s... | /Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp |
llvm::MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned int, int, llvm::MCSymbol const&, bool) | void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
int RegOrOffset,
const MCSymbol &Sym,
bool IsReg) {
OS << "\t.cpsetup\t$"
<< StringRef(MipsInstPrinte... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %r8d, %r15d
movq %rcx, %r14
movl %edx, %ebp
movl %esi, %r13d
movq %rdi, %rbx
movq 0x68(%rdi), %rdi
leaq 0x2f4ec12(%rip), %rsi # 0x48c8cb5
movl $0xb, %edx
callq 0x7f9ba8
movq %rax, %r12
movl %r13d, %edi
callq 0x1976e58
movq %rax, 0... | /Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp |
llvm::operator<<(llvm::MCStreamer&, llvm::MipsABIFlagsSection&) | MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) {
// Write out a Elf_Internal_ABIFlags_v0 struct
OS.emitIntValue(ABIFlagsSection.getVersionValue(), 2); // version
OS.emitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level
OS.emitIntValue(ABIFlagsSection.getISARevi... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movzwl (%rsi), %esi
movq (%rdi), %rax
movl $0x2, %edx
callq *0x208(%rax)
movzbl 0x2(%r14), %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x1, %edx
callq *0x208(%rax)
movzbl 0x3(%r14), %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x1, %edx
callq *0x208(%rax... | /Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp |
llvm::MipsAsmBackend::MipsAsmBackend(llvm::Target const&, llvm::MCRegisterInfo const&, llvm::Triple const&, llvm::StringRef, bool) | MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
StringRef CPU, bool N32)
: MCAsmBackend(TT.isLittleEndian() ? llvm::endianness::little
: llvm::endianness::big),
TheTriple(TT), IsN32(N32) {} | pushq %rbp
pushq %r14
pushq %rbx
movq %rcx, %r14
movq %rdi, %rbx
movb 0x20(%rsp), %bpl
movq %rcx, %rdi
callq 0x2b0584a
movzbl %al, %esi
movq %rbx, %rdi
movl $0x528, %edx # imm = 0x528
callq 0x28c990c
leaq 0x3ecee94(%rip), %rax # 0x584afa0
movq %rax, (%rbx)
leaq 0x10(%rbx), %rdi
leaq 0x20(%rbx), %rax
movq %... | /Target/Mips/MCTargetDesc/MipsAsmBackend.h |
llvm::MipsMCCodeEmitter::getBranchTargetOpValueMMR6(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const | unsigned MipsMCCodeEmitter::
getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 2.
if (M... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movl %edx, %ecx
movq 0x10(%rsi), %rdx
shlq $0x4, %rcx
leaq (%rdx,%rcx), %rax
cmpb $0x2, (%rdx,%rcx)
jne 0x1981383
movq 0x8(%rax), %r14
shrq %r14
jmp 0x1981401
movq %rdi, %r15
movq 0x8(%rax), %r12
movq 0x10(%rdi), %rsi
xorl %r14d, %r14d
movq $-... | /Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp |
llvm::MipsMCCodeEmitter::getBranchTarget21OpValueMM(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const | unsigned MipsMCCodeEmitter::
getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 4.
if (M... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movl %edx, %ecx
movq 0x10(%rsi), %rdx
shlq $0x4, %rcx
leaq (%rdx,%rcx), %rax
cmpb $0x2, (%rdx,%rcx)
jne 0x198172a
movq 0x8(%rax), %r14
shrq $0x2, %r14
jmp 0x19817a8
movq %rdi, %r15
movq 0x8(%rax), %r12
movq 0x10(%rdi), %rsi
xorl %r14d, %r14d
m... | /Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp |
llvm::MipsMCCodeEmitter::getBranchTarget26OpValue(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const | unsigned MipsMCCodeEmitter::
getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 4.
if (MO.isIm... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movl %edx, %ecx
movq 0x10(%rsi), %rdx
shlq $0x4, %rcx
leaq (%rdx,%rcx), %rax
cmpb $0x2, (%rdx,%rcx)
jne 0x19817e4
movq 0x8(%rax), %r14
shrq $0x2, %r14
jmp 0x1981862
movq %rdi, %r15
movq 0x8(%rax), %r12
movq 0x10(%rdi), %rsi
xorl %r14d, %r14d
m... | /Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp |
llvm::MipsRegInfoRecord::EmitMipsOptionRecord() | void MipsRegInfoRecord::EmitMipsOptionRecord() {
MipsTargetStreamer *MTS =
static_cast<MipsTargetStreamer *>(Streamer->getTargetStreamer());
Streamer->pushSection();
// We need to distinguish between N64 and the rest because at the moment
// we don't emit .Mips.options for other ELFs other than N64.
/... | pushq %r14
pushq %rbx
subq $0x58, %rsp
movq %rdi, %rbx
movq 0x8(%rdi), %rdi
movq 0x10(%rdi), %r14
callq 0xac0e72
cmpl $0x3, 0x10(%r14)
movq 0x10(%rbx), %rdi
jne 0x1982818
leaq 0x2f50113(%rip), %rax # 0x48d27f0
leaq 0x8(%rsp), %rsi
movq %rax, (%rsi)
movw $0x103, 0x20(%rsi) # imm = 0x103
leaq 0x30(%rsp), %r9
movw ... | /Target/Mips/MCTargetDesc/MipsOptionRecord.cpp |
llvm::MSP430TargetELFStreamer::MSP430TargetELFStreamer(llvm::MCStreamer&, llvm::MCSubtargetInfo const&) | MSP430TargetELFStreamer::MSP430TargetELFStreamer(MCStreamer &S,
const MCSubtargetInfo &STI)
: MCTargetStreamer(S) {
// Emit build attributes section according to
// MSP430 EABI (slaa534.pdf, part 13).
MCSection *AttributeSection = getStreamer().getContext().get... | pushq %r14
pushq %rbx
subq $0x58, %rsp
movq %rdx, %r14
movq %rdi, %rbx
callq 0x28f5928
leaq 0x3ec8137(%rip), %rax # 0x584bc60
movq %rax, (%rbx)
movq 0x8(%rbx), %rax
movq 0x8(%rax), %rdi
leaq 0x2f581b5(%rip), %rax # 0x48dbcf0
leaq 0x8(%rsp), %rsi
movq %rax, (%rsi)
movw $0x103, 0x20(%rsi) # imm = 0x103
leaq 0x30... | /Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp |
LLVMInitializeNVPTXTargetMC | LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTargetMC() {
for (Target *T : {&getTheNVPTXTarget32(), &getTheNVPTXTarget64()}) {
// Register the MC asm info.
RegisterMCAsmInfo<NVPTXMCAsmInfo> X(*T);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createNVPTXMCInstrInfo)... | subq $0x18, %rsp
callq 0x19f4438
movq %rax, 0x8(%rsp)
callq 0x19f4456
movq %rax, 0x10(%rsp)
xorl %eax, %eax
leaq 0x321(%rip), %rcx # 0x1992846
leaq 0x5c(%rip), %rdx # 0x1992588
leaq 0x9b(%rip), %rsi # 0x19925ce
leaq 0x16b(%rip), %rdi # 0x19926a5
leaq 0x24d(%rip), %r8 # 0x199278e
leaq 0x... | /Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp |
createNVPTXMCInstrInfo() | static MCInstrInfo *createNVPTXMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitNVPTXMCInstrInfo(X);
return X;
} | pushq %rax
movl $0x30, %edi
callq 0x7808d0
xorps %xmm0, %xmm0
movaps %xmm0, (%rax)
movaps %xmm0, 0x10(%rax)
movaps %xmm0, 0x20(%rax)
leaq 0x2fad088(%rip), %rcx # 0x493f630
movq %rcx, (%rax)
leaq 0x2fd99ae(%rip), %rcx # 0x496bf60
movq %rcx, 0x8(%rax)
leaq 0x2fb52c3(%rip), %rcx # 0x4947880
movq %rcx, 0x10(%rax)
mov... | /Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp |
llvm::NVPTXMCAsmInfo::NVPTXMCAsmInfo(llvm::Triple const&, llvm::MCTargetOptions const&) | NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple,
const MCTargetOptions &Options) {
if (TheTriple.getArch() == Triple::nvptx64) {
CodePointerSize = CalleeSaveStackSlotSize = 8;
}
CommentString = "//";
HasSingleParameterDotFile = false;
InlineAsmStart = " begin inlin... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
callq 0x28c9ea0
leaq 0x3eba6f8(%rip), %rax # 0x584d488
movq %rax, (%rbx)
cmpl $0x2a, 0x20(%r14)
jne 0x1992da8
movabsq $0x800000008, %rax # imm = 0x800000008
movq %rax, 0x8(%rbx)
leaq 0x273c814(%rip), %rax # 0x40cf5c3
movq %rax, 0x30(%rbx)
movq $0... | /Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp |
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