name
string | code
string | asm
string | file
string |
|---|---|---|---|
bool llvm::DenseMapBase<llvm::SmallDenseMap<llvm::DILocalVariable const*, llvm::DbgVariable*, 4u, llvm::DenseMapInfo<llvm::DILocalVariable const*, void>, llvm::detail::DenseMapPair<llvm::DILocalVariable const*, llvm::DbgVariable*>>, llvm::DILocalVariable const*, llvm::DbgVariable*, llvm::DenseMapInfo<llvm::DILocalVariable const*, void>, llvm::detail::DenseMapPair<llvm::DILocalVariable const*, llvm::DbgVariable*>>::LookupBucketFor<llvm::DILocalVariable const*>(llvm::DILocalVariable const* const&, llvm::detail::DenseMapPair<llvm::DILocalVariable const*, llvm::DbgVariable*> const*&) const
|
const BucketT *getBuckets() const {
return Small ? getInlineBuckets() : getLargeRep()->Buckets;
}
|
leaq 0x8(%rdi), %rcx
testb $0x1, (%rdi)
cmoveq 0x8(%rdi), %rcx
movl $0x4, %r8d
cmovel 0x10(%rdi), %r8d
testl %r8d, %r8d
je 0x16711b1
pushq %rbx
movl (%rsi), %edi
movl %edi, %eax
shrl $0x4, %eax
shrl $0x9, %edi
xorl %eax, %edi
decl %r8d
andl %r8d, %edi
movl $0x1, %r10d
xorl %r9d, %r9d
movl %edi, %ebx
shlq $0x4, %rbx
leaq (%rcx,%rbx), %r11
movq (%rcx,%rbx), %rbx
cmpq %rbx, (%rsi)
jne 0x1671178
movq %r11, (%rdx)
movb $0x1, %al
xorl %r11d, %r11d
testb %r11b, %r11b
jne 0x1671156
jmp 0x16711ae
cmpq $-0x1000, %rbx # imm = 0xF000
jne 0x1671192
testq %r9, %r9
cmovneq %r9, %r11
movq %r11, (%rdx)
xorl %r11d, %r11d
xorl %eax, %eax
jmp 0x1671171
xorq $-0x2000, %rbx # imm = 0xE000
orq %r9, %rbx
cmoveq %r11, %r9
addl %r10d, %edi
incl %r10d
andl %r8d, %edi
movb $0x1, %r11b
jmp 0x1671171
popq %rbx
jmp 0x16711ba
movq $0x0, (%rdx)
xorl %eax, %eax
andb $0x1, %al
retq
nop
|
/llvm/ADT/DenseMap.h
|
llvm::SmallVectorImpl<llvm::DbgVariable*>::operator=(llvm::SmallVectorImpl<llvm::DbgVariable*> const&)
|
SmallVectorImpl<T> &SmallVectorImpl<T>::
operator=(const SmallVectorImpl<T> &RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (CurSize >= RHSSize) {
// Assign common elements.
iterator NewEnd;
if (RHSSize)
NewEnd = std::copy(RHS.begin(), RHS.begin()+RHSSize, this->begin());
else
NewEnd = this->begin();
// Destroy excess elements.
this->destroy_range(NewEnd, this->end());
// Trim.
this->set_size(RHSSize);
return *this;
}
// If we have to grow to have enough elements, destroy the current elements.
// This allows us to avoid copying them during the grow.
// FIXME: don't do this if they're efficiently moveable.
if (this->capacity() < RHSSize) {
// Destroy current elements.
this->clear();
CurSize = 0;
this->grow(RHSSize);
} else if (CurSize) {
// Otherwise, use assignment for the already-constructed elements.
std::copy(RHS.begin(), RHS.begin()+CurSize, this->begin());
}
// Copy construct the new elements in place.
this->uninitialized_copy(RHS.begin()+CurSize, RHS.end(),
this->begin()+CurSize);
// Set end.
this->set_size(RHSSize);
return *this;
}
|
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
cmpq %rsi, %rdi
je 0x167218c
movq %rsi, %r15
movl 0x8(%rsi), %r14d
movl 0x8(%rbx), %r12d
cmpl %r14d, %r12d
jae 0x167212f
cmpl %r14d, 0xc(%rbx)
jae 0x1672149
movl $0x0, 0x8(%rbx)
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
movq %r14, %rdx
callq 0x2b4ed86
jmp 0x1672163
testl %r14d, %r14d
je 0x1672188
movq (%r15), %rsi
leaq (,%r14,8), %rdx
movq (%rbx), %rdi
callq 0x780120
jmp 0x1672188
testq %r12, %r12
je 0x1672163
movq (%r15), %rsi
leaq (,%r12,8), %rdx
movq (%rbx), %rdi
callq 0x780120
jmp 0x1672166
xorl %r12d, %r12d
movl 0x8(%r15), %edx
subq %r12, %rdx
je 0x1672188
shlq $0x3, %r12
movq (%r15), %rsi
addq %r12, %rsi
addq (%rbx), %r12
shlq $0x3, %rdx
movq %r12, %rdi
callq 0x780890
movl %r14d, 0x8(%rbx)
movq %rbx, %rax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
nop
|
/llvm/ADT/SmallVector.h
|
(anonymous namespace)::DAGCombiner::visitTokenFactor(llvm::SDNode*)
|
SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
// If N has two operands, where one has an input chain equal to the other,
// the 'other' chain is redundant.
if (N->getNumOperands() == 2) {
if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
return N->getOperand(0);
if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
return N->getOperand(1);
}
// Don't simplify token factors if optnone.
if (OptLevel == CodeGenOptLevel::None)
return SDValue();
// Don't simplify the token factor if the node itself has too many operands.
if (N->getNumOperands() > TokenFactorInlineLimit)
return SDValue();
// If the sole user is a token factor, we should make sure we have a
// chance to merge them together. This prevents TF chains from inhibiting
// optimizations.
if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
AddToWorklist(*(N->use_begin()));
SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
SmallPtrSet<SDNode*, 16> SeenOps;
bool Changed = false; // If we should replace this token factor.
// Start out with this token factor.
TFs.push_back(N);
// Iterate through token factors. The TFs grows when new token factors are
// encountered.
for (unsigned i = 0; i < TFs.size(); ++i) {
// Limit number of nodes to inline, to avoid quadratic compile times.
// We have to add the outstanding Token Factors to Ops, otherwise we might
// drop Ops from the resulting Token Factors.
if (Ops.size() > TokenFactorInlineLimit) {
for (unsigned j = i; j < TFs.size(); j++)
Ops.emplace_back(TFs[j], 0);
// Drop unprocessed Token Factors from TFs, so we do not add them to the
// combiner worklist later.
TFs.resize(i);
break;
}
SDNode *TF = TFs[i];
// Check each of the operands.
for (const SDValue &Op : TF->op_values()) {
switch (Op.getOpcode()) {
case ISD::EntryToken:
// Entry tokens don't need to be added to the list. They are
// redundant.
Changed = true;
break;
case ISD::TokenFactor:
if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) {
// Queue up for processing.
TFs.push_back(Op.getNode());
Changed = true;
break;
}
[[fallthrough]];
default:
// Only add if it isn't already in the list.
if (SeenOps.insert(Op.getNode()).second)
Ops.push_back(Op);
else
Changed = true;
break;
}
}
}
// Re-visit inlined Token Factors, to clean them up in case they have been
// removed. Skip the first Token Factor, as this is the current node.
for (unsigned i = 1, e = TFs.size(); i < e; i++)
AddToWorklist(TFs[i]);
// Remove Nodes that are chained to another node in the list. Do so
// by walking up chains breath-first stopping when we've seen
// another operand. In general we must climb to the EntryNode, but we can exit
// early if we find all remaining work is associated with just one operand as
// no further pruning is possible.
// List of nodes to search through and original Ops from which they originate.
SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;
SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.
SmallPtrSet<SDNode *, 16> SeenChains;
bool DidPruneOps = false;
unsigned NumLeftToConsider = 0;
for (const SDValue &Op : Ops) {
Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++));
OpWorkCount.push_back(1);
}
auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {
// If this is an Op, we can remove the op from the list. Remark any
// search associated with it as from the current OpNumber.
if (SeenOps.contains(Op)) {
Changed = true;
DidPruneOps = true;
unsigned OrigOpNumber = 0;
while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op)
OrigOpNumber++;
assert((OrigOpNumber != Ops.size()) &&
"expected to find TokenFactor Operand");
// Re-mark worklist from OrigOpNumber to OpNumber
for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {
if (Worklist[i].second == OrigOpNumber) {
Worklist[i].second = OpNumber;
}
}
OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];
OpWorkCount[OrigOpNumber] = 0;
NumLeftToConsider--;
}
// Add if it's a new chain
if (SeenChains.insert(Op).second) {
OpWorkCount[OpNumber]++;
Worklist.push_back(std::make_pair(Op, OpNumber));
}
};
for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {
// We need at least be consider at least 2 Ops to prune.
if (NumLeftToConsider <= 1)
break;
auto CurNode = Worklist[i].first;
auto CurOpNumber = Worklist[i].second;
assert((OpWorkCount[CurOpNumber] > 0) &&
"Node should not appear in worklist");
switch (CurNode->getOpcode()) {
case ISD::EntryToken:
// Hitting EntryToken is the only way for the search to terminate without
// hitting
// another operand's search. Prevent us from marking this operand
// considered.
NumLeftToConsider++;
break;
case ISD::TokenFactor:
for (const SDValue &Op : CurNode->op_values())
AddToWorklist(i, Op.getNode(), CurOpNumber);
break;
case ISD::LIFETIME_START:
case ISD::LIFETIME_END:
case ISD::CopyFromReg:
case ISD::CopyToReg:
AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber);
break;
default:
if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))
AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);
break;
}
OpWorkCount[CurOpNumber]--;
if (OpWorkCount[CurOpNumber] == 0)
NumLeftToConsider--;
}
// If we've changed things around then replace token factor.
if (Changed) {
SDValue Result;
if (Ops.empty()) {
// The entry token is the only possible outcome.
Result = DAG.getEntryNode();
} else {
if (DidPruneOps) {
SmallVector<SDValue, 8> PrunedOps;
//
for (const SDValue &Op : Ops) {
if (SeenChains.count(Op.getNode()) == 0)
PrunedOps.push_back(Op);
}
Result = DAG.getTokenFactor(SDLoc(N), PrunedOps);
} else {
Result = DAG.getTokenFactor(SDLoc(N), Ops);
}
}
return Result;
}
return SDValue();
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x3d8, %rsp # imm = 0x3D8
movq %rsi, %rcx
movq %rdi, 0x8(%rsp)
movzwl 0x40(%rsi), %ebp
cmpl $0x2, %ebp
jne 0x16752c3
movq %rcx, %r13
movq 0x28(%rcx), %r14
movq (%r14), %rbx
movq %rbx, %rdi
callq 0x16c19e0
movq 0x28(%r14), %r12
cmpq %r12, %rax
sete %al
movl 0x30(%r14), %r15d
cmpl %r15d, %edx
sete %cl
andb %al, %cl
cmpb $0x1, %cl
jne 0x16752a9
movl 0x8(%r14), %r15d
movq %rbx, %r12
jmp 0x167592d
movq %r12, %rdi
callq 0x16c19e0
cmpq %rbx, %rax
movq %r13, %rcx
jne 0x16752c3
cmpl 0x8(%r14), %edx
je 0x167592d
xorl %r15d, %r15d
movq 0x8(%rsp), %rax
cmpl $0x0, 0x1c(%rax)
je 0x1675492
movl $0x0, %r12d
cmpl %ebp, 0x42c08df(%rip) # 0x5935bc0
jb 0x167592d
movq 0x38(%rcx), %rax
testq %rax, %rax
je 0x1675318
cmpq $0x0, 0x20(%rax)
jne 0x1675318
movq 0x10(%rax), %rsi
cmpl $0x2, 0x18(%rsi)
jne 0x1675318
movq 0x8(%rsp), %rdi
movl $0x1, %edx
movq %rcx, %rbx
xorl %ecx, %ecx
callq 0x1672ada
movq %rbx, %rcx
leaq 0x38(%rsp), %rax
movq %rax, -0x10(%rax)
movabsq $0x800000000, %rdx # imm = 0x800000000
movq %rdx, -0x8(%rax)
leaq 0xf8(%rsp), %rax
movq %rax, -0x10(%rax)
movq %rdx, -0x8(%rax)
leaq 0x358(%rsp), %rax
movq %rax, -0x20(%rax)
movq %rax, -0x18(%rax)
movq $0x10, -0x10(%rax)
movl $0x0, -0x8(%rax)
movb $0x0, 0x2(%rsp)
leaq 0x28(%rsp), %rbx
movq %rbx, %rdi
movq %rcx, 0x10(%rsp)
movq %rcx, %rsi
callq 0xa300a2
cmpl $0x0, 0x8(%rbx)
je 0x16754eb
xorl %r14d, %r14d
leaq 0x178(%rsp), %r12
xorl %r15d, %r15d
movl 0xf0(%rsp), %eax
cmpl 0x42c0823(%rip), %eax # 0x5935bc0
ja 0x167549a
movq 0x28(%rsp), %rax
movq (%rax,%r15,8), %rcx
movzwl 0x40(%rcx), %eax
testq %rax, %rax
je 0x167547e
movq 0x28(%rcx), %r13
shll $0x3, %eax
leaq (%rax,%rax,4), %rbx
xorl %ebp, %ebp
movq (%r13,%rbp), %rdi
movl 0x18(%rdi), %eax
cmpl $0x2, %eax
je 0x16753de
cmpl $0x1, %eax
je 0x167546c
jmp 0x1675425
movl 0x8(%r13,%rbp), %edx
movl $0x1, %esi
callq 0x179219e
testb %al, %al
je 0x1675425
movq (%r13,%rbp), %rax
movq %rax, 0x178(%rsp)
movq 0x28(%rsp), %rdi
movl 0x30(%rsp), %eax
leaq (%rdi,%rax,8), %rsi
movq %r12, %rdx
callq 0x1673792
movl 0x30(%rsp), %ecx
shlq $0x3, %rcx
addq 0x28(%rsp), %rcx
cmpq %rcx, %rax
je 0x167545d
movq (%r13,%rbp), %rdx
movq %r12, %rdi
leaq 0x338(%rsp), %rsi
callq 0xdce8e0
cmpb $0x1, 0x188(%rsp)
jne 0x167546c
movq (%r13,%rbp), %rsi
movl 0x8(%r13,%rbp), %edx
leaq 0xe8(%rsp), %rdi
callq 0x9e21b4
jmp 0x1675471
movq (%r13,%rbp), %rsi
leaq 0x28(%rsp), %rdi
callq 0xa300a2
movb $0x1, 0x2(%rsp)
addq $0x28, %rbp
cmpq %rbp, %rbx
jne 0x16753c6
incl %r15d
addq $0x8, %r14
cmpl %r15d, 0x30(%rsp)
ja 0x1675390
jmp 0x16754eb
xorl %r12d, %r12d
jmp 0x167592d
cmpl %r15d, 0x30(%rsp)
jbe 0x16754de
leaq 0xe8(%rsp), %rbx
leaq 0x178(%rsp), %r12
movl %r15d, %ebp
movq 0x28(%rsp), %rsi
addq %r14, %rsi
movl $0x0, 0x178(%rsp)
movq %rbx, %rdi
movq %r12, %rdx
callq 0x16c1a80
incl %ebp
addq $0x8, %r14
cmpl %ebp, 0x30(%rsp)
ja 0x16754b4
leaq 0x28(%rsp), %rdi
movq %r15, %rsi
callq 0x16c1c2a
movl 0x30(%rsp), %ebx
cmpq $0x2, %rbx
movq 0x8(%rsp), %r15
jb 0x1675520
movl $0x1, %r14d
movq 0x28(%rsp), %rax
movq (%rax,%r14,8), %rsi
movq %r15, %rdi
movl $0x1, %edx
xorl %ecx, %ecx
callq 0x1672ada
incq %r14
cmpq %r14, %rbx
jne 0x1675500
leaq 0x228(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, -0x8(%rcx)
leaq 0x88(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movq %rax, -0x8(%rcx)
leaq 0x198(%rsp), %rax
movq %rax, -0x20(%rax)
movq %rax, -0x18(%rax)
movq $0x10, -0x10(%rax)
xorl %ecx, %ecx
movl %ecx, -0x8(%rax)
movb $0x0, 0x3(%rsp)
movl %ecx, 0x4(%rsp)
movl 0xf0(%rsp), %r14d
testq %r14, %r14
je 0x16755c6
movq 0xe8(%rsp), %r12
shlq $0x4, %r14
xorl %r13d, %r13d
leaq 0x218(%rsp), %rbx
leaq 0x78(%rsp), %r15
movq (%r12,%r13), %rsi
movl 0x4(%rsp), %edx
leal 0x1(%rdx), %eax
movl %eax, 0x4(%rsp)
movq %rbx, %rdi
callq 0x16c1acc
movq %r15, %rdi
movl $0x1, %esi
callq 0x81fb4c
addq $0x10, %r13
cmpq %r13, %r14
jne 0x1675599
leaq 0x338(%rsp), %rax
movq %rax, 0xa8(%rsp)
leaq 0x2(%rsp), %rax
movq %rax, 0xb0(%rsp)
leaq 0x3(%rsp), %rax
movq %rax, 0xb8(%rsp)
leaq 0xe8(%rsp), %rax
movq %rax, 0xc0(%rsp)
leaq 0x218(%rsp), %rax
movq %rax, 0xc8(%rsp)
leaq 0x78(%rsp), %rcx
movq %rcx, 0xd0(%rsp)
leaq 0x4(%rsp), %rcx
movq %rcx, 0xd8(%rsp)
leaq 0x178(%rsp), %rdx
movq %rdx, 0xe0(%rsp)
cmpl $0x0, 0x8(%rax)
sete %dl
movl (%rcx), %eax
cmpl $0x2, %eax
setb %cl
orb %dl, %cl
je 0x1675795
xorl %r15d, %r15d
cmpb $0x1, 0x2(%rsp)
movq 0x10(%rsp), %rax
jne 0x167588d
movl 0xf0(%rsp), %r14d
testq %r14, %r14
je 0x1675892
cmpb $0x1, 0x3(%rsp)
jne 0x1675945
leaq 0x2b8(%rsp), %rbp
movq %rbp, -0x10(%rbp)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, -0x8(%rbp)
movq 0xe8(%rsp), %r12
shlq $0x4, %r14
xorl %r13d, %r13d
leaq 0x178(%rsp), %rbx
leaq 0x2a8(%rsp), %r15
movq (%r12,%r13), %rsi
movq %rbx, %rdi
callq 0x90b7be
movq 0x180(%rsp), %rcx
xorl %edx, %edx
cmpq 0x178(%rsp), %rcx
sete %dl
movl 0x188(%rsp,%rdx,4), %edx
leaq (%rcx,%rdx,8), %rcx
cmpq %rcx, %rax
jne 0x16756fb
movq (%r12,%r13), %rsi
movl 0x8(%r12,%r13), %edx
movq %r15, %rdi
callq 0x9e21b4
addq $0x10, %r13
cmpq %r13, %r14
jne 0x16756b9
movq 0x8(%rsp), %rax
movq (%rax), %rbx
movq 0x10(%rsp), %rax
movq 0x48(%rax), %rsi
movq %rsi, 0x18(%rsp)
testq %rsi, %rsi
je 0x1675733
leaq 0x18(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movq 0x10(%rsp), %rax
movl 0x44(%rax), %eax
leaq 0x18(%rsp), %r14
movl %eax, 0x8(%r14)
leaq 0x2a8(%rsp), %rdx
movq %rbx, %rdi
movq %r14, %rsi
callq 0x17951f2
movq %rax, %r12
movl %edx, %r15d
movq (%r14), %rsi
testq %rsi, %rsi
leaq 0x88(%rsp), %r13
je 0x1675772
leaq 0x18(%rsp), %rdi
callq 0x2a758fc
movq 0x2a8(%rsp), %rdi
cmpq %rbp, %rdi
leaq 0x228(%rsp), %rbx
je 0x16758b0
callq 0x780910
jmp 0x16758b0
xorl %r15d, %r15d
leaq 0xa8(%rsp), %r12
movq 0x218(%rsp), %rcx
movq %r15, %rdx
shlq $0x4, %rdx
movq (%rcx,%rdx), %r13
movl 0x8(%rcx,%rdx), %ebx
movl 0x18(%r13), %ecx
cmpl $0x162, %ecx # imm = 0x162
jg 0x1675810
leal -0x31(%rcx), %edx
cmpl $0x2, %edx
jb 0x167581b
cmpl $0x1, %ecx
je 0x1675885
cmpl $0x2, %ecx
jne 0x167586f
movzwl 0x40(%r13), %eax
testq %rax, %rax
je 0x167582f
movq 0x28(%r13), %r14
shll $0x3, %eax
leaq (%rax,%rax,4), %r13
xorl %ebp, %ebp
movq (%r14,%rbp), %rdx
movq %r12, %rdi
movl %r15d, %esi
movl %ebx, %ecx
callq 0x16c1b14
addq $0x28, %rbp
cmpq %rbp, %r13
jne 0x16757f4
jmp 0x167582f
addl $0xfffffe9d, %ecx # imm = 0xFFFFFE9D
cmpl $0x2, %ecx
jae 0x167586f
movq 0x28(%r13), %rax
movq (%rax), %rdx
movq %r12, %rdi
movl %r15d, %esi
movl %ebx, %ecx
callq 0x16c1b14
movq 0x78(%rsp), %rax
decl (%rax,%rbx,4)
jne 0x167583d
decl 0x4(%rsp)
cmpq $0x3fe, %r15 # imm = 0x3FE
ja 0x1675651
incq %r15
movl 0x220(%rsp), %eax
cmpq %rax, %r15
jae 0x1675651
movl 0x4(%rsp), %eax
cmpl $0x1, %eax
ja 0x16757a0
jmp 0x1675651
movq %r13, %rdi
callq 0x9e2a16
xorb $0x1, %al
testq %r13, %r13
sete %cl
orb %al, %cl
je 0x167581b
jmp 0x167582f
incl %eax
movl %eax, 0x4(%rsp)
jmp 0x167582f
xorl %r12d, %r12d
jmp 0x16758a0
movl $0xe8, %r12d
movq 0x8(%rsp), %rax
addq (%rax), %r12
leaq 0x228(%rsp), %rbx
leaq 0x88(%rsp), %r13
movq 0x180(%rsp), %rdi
cmpq 0x178(%rsp), %rdi
je 0x16758c7
callq 0x780910
movq 0x78(%rsp), %rdi
cmpq %r13, %rdi
je 0x16758d6
callq 0x780910
movq 0x218(%rsp), %rdi
cmpq %rbx, %rdi
je 0x16758e8
callq 0x780910
movq 0x340(%rsp), %rdi
cmpq 0x338(%rsp), %rdi
je 0x16758ff
callq 0x780910
movq 0xe8(%rsp), %rdi
leaq 0xf8(%rsp), %rax
cmpq %rax, %rdi
je 0x1675919
callq 0x780910
movq 0x28(%rsp), %rdi
leaq 0x38(%rsp), %rax
cmpq %rax, %rdi
je 0x167592d
callq 0x780910
movq %r12, %rax
movl %r15d, %edx
addq $0x3d8, %rsp # imm = 0x3D8
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movq 0x8(%rsp), %rcx
movq (%rcx), %rbx
movq 0x48(%rax), %rsi
movq %rsi, 0x2a8(%rsp)
testq %rsi, %rsi
leaq 0x88(%rsp), %r13
je 0x167597d
leaq 0x2a8(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movq 0x10(%rsp), %rax
movl 0x44(%rax), %eax
leaq 0x2a8(%rsp), %r14
movl %eax, 0x8(%r14)
leaq 0xe8(%rsp), %rdx
movq %rbx, %rdi
movq %r14, %rsi
callq 0x17951f2
movq %rax, %r12
movl %edx, %r15d
movq (%r14), %rsi
testq %rsi, %rsi
je 0x16759ba
leaq 0x2a8(%rsp), %rdi
callq 0x2a758fc
leaq 0x228(%rsp), %rbx
jmp 0x16758b0
nop
|
/CodeGen/SelectionDAG/DAGCombiner.cpp
|
(anonymous namespace)::DAGCombiner::visitATOMIC_STORE(llvm::SDNode*)
|
SDValue DAGCombiner::visitATOMIC_STORE(SDNode *N) {
AtomicSDNode *ST = cast<AtomicSDNode>(N);
SDValue Val = ST->getVal();
EVT VT = Val.getValueType();
EVT MemVT = ST->getMemoryVT();
if (MemVT.bitsLT(VT)) { // Is truncating store
APInt TruncDemandedBits = APInt::getLowBitsSet(VT.getScalarSizeInBits(),
MemVT.getScalarSizeInBits());
// See if we can simplify the operation with SimplifyDemandedBits, which
// only works if the value has a single use.
if (SimplifyDemandedBits(Val, TruncDemandedBits))
return SDValue(N, 0);
}
return SDValue();
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rsi, %rbx
cmpl $0x14a, 0x18(%rsi) # imm = 0x14A
movq %rdi, %rbp
movq 0x28(%rsi), %rax
movl $0x28, %ecx
movl $0x50, %edx
cmoveq %rcx, %rdx
movq (%rax,%rdx), %r15
movl 0x8(%rax,%rdx), %r12d
movq 0x30(%r15), %rax
movq %r12, %rdx
shlq $0x4, %rdx
movb (%rax,%rdx), %cl
movq 0x8(%rax,%rdx), %rdx
movb %cl, 0x28(%rsp)
movq %rdx, 0x30(%rsp)
movb 0x58(%rsi), %dil
movq 0x60(%rsi), %rsi
movb %dil, 0x8(%rsp)
movq %rsi, 0x10(%rsp)
cmpb %cl, %dil
jne 0x16a83c1
xorl %eax, %eax
testb %dil, %dil
jne 0x16a845b
cmpq %rdx, %rsi
je 0x16a845b
movzbl %cl, %esi
leaq 0x8(%rsp), %rdi
callq 0xa5000c
testb %al, %al
je 0x16a8459
leaq 0x28(%rsp), %rdi
callq 0x9254d2
movq %rax, %r13
leaq 0x8(%rsp), %rdi
callq 0x9254d2
movq %rax, (%rsp)
leaq 0x18(%rsp), %r14
movq %r14, %rdi
movl %r13d, %esi
xorl %edx, %edx
xorl %ecx, %ecx
callq 0x91d2c6
movq %r14, %rdi
xorl %esi, %esi
movq (%rsp), %rdx
callq 0x95b8c2
movq %rbp, %rdi
movq %r15, %rsi
movl %r12d, %edx
movq %r14, %rcx
callq 0x16c7fe4
movl 0x8(%r14), %ecx
testb %al, %al
je 0x16a8445
cmpl $0x41, %ecx
jb 0x16a8440
movq 0x18(%rsp), %rdi
testq %rdi, %rdi
je 0x16a8440
callq 0x7802b0
movq %rbx, %rax
jmp 0x16a845b
cmpl $0x41, %ecx
jb 0x16a8459
movq 0x18(%rsp), %rdi
testq %rdi, %rdi
je 0x16a8459
callq 0x7802b0
xorl %eax, %eax
xorl %edx, %edx
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/CodeGen/SelectionDAG/DAGCombiner.cpp
|
llvm::SDPatternMatch::BinaryOpc_match<llvm::SDPatternMatch::BinaryOpc_match<llvm::SDPatternMatch::SpecificInt_match, llvm::SDPatternMatch::Value_bind, false, false>, llvm::SDPatternMatch::Value_bind, false, false>::BinaryOpc_match(unsigned int, llvm::SDPatternMatch::BinaryOpc_match<llvm::SDPatternMatch::SpecificInt_match, llvm::SDPatternMatch::Value_bind, false, false> const&, llvm::SDPatternMatch::Value_bind const&)
|
BinaryOpc_match(unsigned Opc, const LHS_P &L, const RHS_P &R)
: Opcode(Opc), LHS(L), RHS(R) {}
|
pushq %r15
pushq %r14
pushq %rbx
movq %rcx, %rbx
movq %rdx, %r15
movq %rdi, %r14
movl %esi, (%rdi)
movl (%rdx), %eax
movl %eax, 0x8(%rdi)
addq $0x10, %rdi
leaq 0x8(%rdx), %rsi
movl 0x10(%rdx), %eax
movl %eax, 0x18(%r14)
cmpl $0x40, %eax
ja 0x16c868f
movq (%rsi), %rax
movq %rax, (%rdi)
jmp 0x16c8694
callq 0x2b11114
movq 0x18(%r15), %rax
movq %rax, 0x20(%r14)
movq (%rbx), %rax
movq %rax, 0x28(%r14)
popq %rbx
popq %r14
popq %r15
retq
nop
|
/llvm/CodeGen/SDPatternMatch.h
|
(anonymous namespace)::DAGCombiner::MatchBSwapHWordLow(llvm::SDNode*, llvm::SDValue, llvm::SDValue, bool)
|
SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
bool DemandHighBits) {
if (!LegalOperations)
return SDValue();
EVT VT = N->getValueType(0);
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
return SDValue();
if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
return SDValue();
// Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff)
bool LookPassAnd0 = false;
bool LookPassAnd1 = false;
if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
std::swap(N0, N1);
if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
std::swap(N0, N1);
if (N0.getOpcode() == ISD::AND) {
if (!N0->hasOneUse())
return SDValue();
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
// Also handle 0xffff since the LHS is guaranteed to have zeros there.
// This is needed for X86.
if (!N01C || (N01C->getZExtValue() != 0xFF00 &&
N01C->getZExtValue() != 0xFFFF))
return SDValue();
N0 = N0.getOperand(0);
LookPassAnd0 = true;
}
if (N1.getOpcode() == ISD::AND) {
if (!N1->hasOneUse())
return SDValue();
ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
if (!N11C || N11C->getZExtValue() != 0xFF)
return SDValue();
N1 = N1.getOperand(0);
LookPassAnd1 = true;
}
if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
std::swap(N0, N1);
if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
return SDValue();
if (!N0->hasOneUse() || !N1->hasOneUse())
return SDValue();
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
if (!N01C || !N11C)
return SDValue();
if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
return SDValue();
// Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
SDValue N00 = N0->getOperand(0);
if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
if (!N00->hasOneUse())
return SDValue();
ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
if (!N001C || N001C->getZExtValue() != 0xFF)
return SDValue();
N00 = N00.getOperand(0);
LookPassAnd0 = true;
}
SDValue N10 = N1->getOperand(0);
if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
if (!N10->hasOneUse())
return SDValue();
ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
// Also allow 0xFFFF since the bits will be shifted out. This is needed
// for X86.
if (!N101C || (N101C->getZExtValue() != 0xFF00 &&
N101C->getZExtValue() != 0xFFFF))
return SDValue();
N10 = N10.getOperand(0);
LookPassAnd1 = true;
}
if (N00 != N10)
return SDValue();
// Make sure everything beyond the low halfword gets set to zero since the SRL
// 16 will clear the top bits.
unsigned OpSizeInBits = VT.getSizeInBits();
if (OpSizeInBits > 16) {
// If the left-shift isn't masked out then the only way this is a bswap is
// if all bits beyond the low 8 are 0. In that case the entire pattern
// reduces to a left shift anyway: leave it for other parts of the combiner.
if (DemandHighBits && !LookPassAnd0)
return SDValue();
// However, if the right shift isn't masked out then it might be because
// it's not needed. See if we can spot that too. If the high bits aren't
// demanded, we only need bits 23:16 to be zero. Otherwise, we need all
// upper bits to be zero.
if (!LookPassAnd1) {
unsigned HighBit = DemandHighBits ? OpSizeInBits : 24;
if (!DAG.MaskedValueIsZero(N10,
APInt::getBitsSet(OpSizeInBits, 16, HighBit)))
return SDValue();
}
}
SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
if (OpSizeInBits > 16) {
SDLoc DL(N);
Res = DAG.getNode(ISD::SRL, DL, VT, Res,
DAG.getShiftAmountConstant(OpSizeInBits - 16, VT, DL));
}
return Res;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
cmpb $0x1, 0x21(%rdi)
jne 0x16d2359
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %r14
movq 0x30(%rsi), %rcx
movb (%rcx), %al
movq 0x8(%rcx), %rcx
movb %al, 0x60(%rsp)
movq %rcx, 0x68(%rsp)
leal -0x9(%rax), %edx
cmpb $-0x3, %dl
jae 0x16d2377
xorl %r15d, %r15d
xorl %r13d, %r13d
movq %r13, %rax
movl %r15d, %edx
addq $0xa8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
movl %r8d, %ebp
movq %rdi, %rbx
movq 0x8(%rdi), %rdi
movzbl %al, %edx
xorl %r15d, %r15d
movl $0xc4, %esi
xorl %r8d, %r8d
callq 0x92126e
testb %al, %al
je 0x16d235c
cmpl $0xb9, 0x18(%r13)
jne 0x16d23be
movq 0x28(%r13), %rax
movq (%rax), %rax
cmpl $0xbf, 0x18(%rax)
movq %r12, %rax
cmoveq %r13, %rax
cmoveq %r12, %r13
movq %rax, %r12
cmpl $0xb9, 0x18(%r12)
jne 0x16d23e6
movq 0x28(%r12), %rax
movq (%rax), %rax
cmpl $0xbd, 0x18(%rax)
movq %r12, %rax
cmoveq %r13, %rax
cmoveq %r12, %r13
movq %rax, %r12
xorl %r15d, %r15d
cmpl $0xb9, 0x18(%r13)
jne 0x16d2445
movq 0x38(%r13), %rax
testq %rax, %rax
je 0x16d235c
cmpq $0x0, 0x20(%rax)
jne 0x16d2359
movq 0x28(%r13), %rax
movq 0x28(%rax), %rcx
movl 0x18(%rcx), %edx
cmpl $0x23, %edx
je 0x16d2422
cmpl $0xb, %edx
je 0x16d2422
xorl %ecx, %ecx
xorl %r15d, %r15d
testq %rcx, %rcx
je 0x16d2576
movq 0x58(%rcx), %rcx
cmpl $0x41, 0x20(%rcx)
jb 0x16d257d
movq 0x18(%rcx), %rcx
jmp 0x16d2581
xorl %r8d, %r8d
xorl %r15d, %r15d
cmpl $0xb9, 0x18(%r12)
jne 0x16d24aa
movq 0x38(%r12), %rax
testq %rax, %rax
je 0x16d235c
cmpq $0x0, 0x20(%rax)
jne 0x16d2359
movq 0x28(%r12), %rax
movq 0x28(%rax), %rcx
movl 0x18(%rcx), %edx
cmpl $0x23, %edx
je 0x16d2487
cmpl $0xb, %edx
je 0x16d2487
xorl %ecx, %ecx
xorl %r15d, %r15d
testq %rcx, %rcx
je 0x16d25b3
movq 0x58(%rcx), %rcx
cmpl $0x41, 0x20(%rcx)
jb 0x16d25ba
movq 0x18(%rcx), %rcx
jmp 0x16d25be
xorl %r9d, %r9d
cmpl $0xbf, 0x18(%r13)
jne 0x16d24ce
cmpl $0xbd, 0x18(%r12)
movq %r12, %rax
cmoveq %r13, %rax
cmoveq %r12, %r13
movq %rax, %r12
cmpl $0xbd, 0x18(%r13)
jne 0x16d2359
cmpl $0xbf, 0x18(%r12)
jne 0x16d2359
movq 0x38(%r13), %rax
testq %rax, %rax
je 0x16d2359
cmpq $0x0, 0x20(%rax)
jne 0x16d2359
movq 0x38(%r12), %rax
testq %rax, %rax
je 0x16d2359
cmpq $0x0, 0x20(%rax)
jne 0x16d2359
movq 0x28(%r13), %rcx
movq 0x28(%rcx), %rdx
movl 0x18(%rdx), %eax
cmpl $0x23, %eax
je 0x16d2533
cmpl $0xb, %eax
je 0x16d2533
xorl %edx, %edx
movq 0x28(%r12), %rax
movq 0x28(%rax), %rsi
movl 0x18(%rsi), %edi
cmpl $0x23, %edi
je 0x16d254b
cmpl $0xb, %edi
je 0x16d254b
xorl %esi, %esi
xorl %r15d, %r15d
testq %rdx, %rdx
je 0x16d235c
movl $0x0, %r13d
testq %rsi, %rsi
je 0x16d235f
movq 0x58(%rdx), %rdx
cmpl $0x41, 0x20(%rdx)
jb 0x16d25e4
movq 0x18(%rdx), %rdx
jmp 0x16d25e8
xorl %r8d, %r8d
xorl %edx, %edx
jmp 0x16d25a6
addq $0x18, %rcx
movq (%rcx), %rcx
cmpq $0xffff, %rcx # imm = 0xFFFF
je 0x16d259e
xorl %r8d, %r8d
movl $0x0, %edx
cmpq $0xff00, %rcx # imm = 0xFF00
jne 0x16d25a6
movq (%rax), %r13
movb $0x1, %r8b
movb $0x1, %dl
testb %dl, %dl
je 0x16d235c
jmp 0x16d2448
xorl %r9d, %r9d
xorl %ecx, %ecx
jmp 0x16d25d7
addq $0x18, %rcx
xorl %r9d, %r9d
cmpq $0xff, (%rcx)
movl $0x0, %ecx
jne 0x16d25d7
movq (%rax), %r12
movb $0x1, %r9b
movb $0x1, %cl
testb %cl, %cl
je 0x16d235c
jmp 0x16d24ad
addq $0x18, %rdx
cmpq $0x8, (%rdx)
jne 0x16d2359
movq 0x58(%rsi), %rdx
cmpl $0x41, 0x20(%rdx)
jb 0x16d2602
movq 0x18(%rdx), %rdx
jmp 0x16d2606
addq $0x18, %rdx
cmpq $0x8, (%rdx)
jne 0x16d2359
movq %r9, 0x50(%rsp)
movq (%rcx), %rdx
movq %rdx, 0x30(%rsp)
movl 0x8(%rcx), %edx
movl %edx, 0x2c(%rsp)
movl 0xc(%rcx), %ecx
movl %ecx, 0x5c(%rsp)
movq %r8, 0x70(%rsp)
testb %r8b, %r8b
jne 0x16d26cd
movq 0x30(%rsp), %rcx
cmpl $0xb9, 0x18(%rcx)
jne 0x16d26cd
movq 0x30(%rsp), %rcx
movq 0x38(%rcx), %rcx
testq %rcx, %rcx
je 0x16d2359
cmpq $0x0, 0x20(%rcx)
jne 0x16d2359
movq 0x30(%rsp), %rcx
movq 0x28(%rcx), %rcx
movq 0x28(%rcx), %rdx
movl 0x18(%rdx), %esi
cmpl $0x23, %esi
je 0x16d2684
cmpl $0xb, %esi
je 0x16d2684
xorl %edx, %edx
xorl %r15d, %r15d
testq %rdx, %rdx
je 0x16d26c3
movq 0x58(%rdx), %rdx
cmpl $0x41, 0x20(%rdx)
jb 0x16d269c
movq 0x18(%rdx), %rdx
jmp 0x16d26a0
addq $0x18, %rdx
cmpq $0xff, (%rdx)
jne 0x16d26c3
movq (%rcx), %rdx
movq %rdx, 0x30(%rsp)
movl 0x8(%rcx), %ecx
movl %ecx, 0x2c(%rsp)
movb $0x1, %cl
movq %rcx, 0x70(%rsp)
movb $0x1, %cl
jmp 0x16d26c5
xorl %ecx, %ecx
testb %cl, %cl
je 0x16d235c
movq (%rax), %r12
movl 0x8(%rax), %eax
movl %eax, 0x28(%rsp)
cmpb $0x0, 0x50(%rsp)
jne 0x16d2772
cmpl $0xb9, 0x18(%r12)
jne 0x16d2772
movq 0x38(%r12), %rax
testq %rax, %rax
je 0x16d2359
cmpq $0x0, 0x20(%rax)
jne 0x16d2359
movq 0x28(%r12), %rax
movq 0x28(%rax), %rcx
movl 0x18(%rcx), %edx
cmpl $0x23, %edx
je 0x16d2722
cmpl $0xb, %edx
je 0x16d2722
xorl %ecx, %ecx
xorl %r15d, %r15d
testq %rcx, %rcx
je 0x16d2768
movq 0x58(%rcx), %rcx
cmpl $0x41, 0x20(%rcx)
jb 0x16d273a
movq 0x18(%rcx), %rcx
jmp 0x16d273e
addq $0x18, %rcx
movq (%rcx), %rcx
cmpq $0xffff, %rcx # imm = 0xFFFF
je 0x16d2753
cmpq $0xff00, %rcx # imm = 0xFF00
jne 0x16d2768
movq (%rax), %r12
movl 0x8(%rax), %eax
movl %eax, 0x28(%rsp)
movb $0x1, %al
movq %rax, 0x50(%rsp)
movb $0x1, %al
jmp 0x16d276a
xorl %eax, %eax
testb %al, %al
je 0x16d235c
xorl %r15d, %r15d
cmpq %r12, 0x30(%rsp)
jne 0x16d235c
movl $0x0, %r13d
movl 0x28(%rsp), %eax
cmpl %eax, 0x2c(%rsp)
jne 0x16d235f
leaq 0x60(%rsp), %rdi
callq 0x9ebda0
leaq 0x38(%rsp), %rdi
movq %rax, (%rdi)
movb %dl, 0x8(%rdi)
callq 0x2b60e74
movq %rax, 0x48(%rsp)
cmpl $0x11, %eax
jb 0x16d2831
testb %bpl, %bpl
je 0x16d27c8
cmpb $0x0, 0x70(%rsp)
je 0x16d2359
cmpb $0x0, 0x50(%rsp)
jne 0x16d2831
testb %bpl, %bpl
movl $0x18, %ecx
movq 0x48(%rsp), %rsi
cmovnel %esi, %ecx
movq (%rbx), %r13
leaq 0x38(%rsp), %rdi
movq %rdi, %rbp
movl $0x10, %edx
callq 0xc642b2
xorl %r15d, %r15d
movq %r13, %rdi
movq %r12, %rsi
movl 0x28(%rsp), %edx
movq %rbp, %r12
movq %rbp, %rcx
xorl %r8d, %r8d
callq 0x176a1ba
movl %eax, %ebp
cmpl $0x41, 0x8(%r12)
jb 0x16d2828
movq 0x38(%rsp), %rdi
testq %rdi, %rdi
je 0x16d2828
callq 0x7802b0
testb %bpl, %bpl
je 0x16d235c
movq (%rbx), %r15
movq 0x48(%r14), %rsi
movq %rsi, 0x38(%rsp)
testq %rsi, %rsi
je 0x16d2851
leaq 0x38(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r14), %eax
leaq 0x38(%rsp), %r12
movl %eax, 0x8(%r12)
movq 0x68(%rsp), %r8
movq 0x30(%rsp), %rax
movq %rax, 0x88(%rsp)
movl 0x2c(%rsp), %eax
movl %eax, 0x90(%rsp)
movl 0x5c(%rsp), %eax
movl %eax, 0x94(%rsp)
movl 0x60(%rsp), %ecx
movups 0x88(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r15, %rdi
movl $0xc4, %esi
movq %r12, %rdx
callq 0x176388a
movq %rax, %r13
movl %edx, %r15d
movq (%r12), %rsi
testq %rsi, %rsi
je 0x16d28c0
leaq 0x38(%rsp), %rdi
callq 0x2a758fc
cmpl $0x11, 0x48(%rsp)
jb 0x16d235f
movq 0x48(%r14), %rsi
movq %rsi, 0x38(%rsp)
testq %rsi, %rsi
je 0x16d28e8
leaq 0x38(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r14), %eax
leaq 0x38(%rsp), %r14
movl %eax, 0x8(%r14)
movq (%rbx), %r12
movq 0x68(%rsp), %rbx
movq %r13, 0x78(%rsp)
movl %r15d, 0x80(%rsp)
movl $0x0, 0x84(%rsp)
movq 0x48(%rsp), %rsi
addl $-0x10, %esi
movl 0x60(%rsp), %ebp
movq %r12, %rdi
movl %ebp, %edx
movq %rbx, %rcx
movq %r14, %r8
callq 0x17655ec
movq %rax, 0x98(%rsp)
movl %edx, 0xa0(%rsp)
movups 0x98(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x78(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r12, %rdi
movl $0xbf, %esi
movq %r14, %rdx
movl %ebp, %ecx
movq %rbx, %r8
callq 0x17638a8
movq %rax, %r13
movl %edx, %r15d
movq (%r14), %rsi
testq %rsi, %rsi
je 0x16d235f
leaq 0x38(%rsp), %rdi
callq 0x2a758fc
jmp 0x16d235f
|
/CodeGen/SelectionDAG/DAGCombiner.cpp
|
(anonymous namespace)::DAGCombiner::MatchRotate(llvm::SDValue, llvm::SDValue, llvm::SDLoc const&)
|
SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
EVT VT = LHS.getValueType();
// The target must have at least one rotate/funnel flavor.
// We still try to match rotate by constant pre-legalization.
// TODO: Support pre-legalization funnel-shift by constant.
bool HasROTL = hasOperation(ISD::ROTL, VT);
bool HasROTR = hasOperation(ISD::ROTR, VT);
bool HasFSHL = hasOperation(ISD::FSHL, VT);
bool HasFSHR = hasOperation(ISD::FSHR, VT);
// If the type is going to be promoted and the target has enabled custom
// lowering for rotate, allow matching rotate by non-constants. Only allow
// this for scalar types.
if (VT.isScalarInteger() && TLI.getTypeAction(*DAG.getContext(), VT) ==
TargetLowering::TypePromoteInteger) {
HasROTL |= TLI.getOperationAction(ISD::ROTL, VT) == TargetLowering::Custom;
HasROTR |= TLI.getOperationAction(ISD::ROTR, VT) == TargetLowering::Custom;
}
if (LegalOperations && !HasROTL && !HasROTR && !HasFSHL && !HasFSHR)
return SDValue();
// Check for truncated rotate.
if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE &&
LHS.getOperand(0).getValueType() == RHS.getOperand(0).getValueType()) {
assert(LHS.getValueType() == RHS.getValueType());
if (SDValue Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) {
return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(), Rot);
}
}
// Match "(X shl/srl V1) & V2" where V2 may not be present.
SDValue LHSShift; // The shift.
SDValue LHSMask; // AND value if any.
matchRotateHalf(DAG, LHS, LHSShift, LHSMask);
SDValue RHSShift; // The shift.
SDValue RHSMask; // AND value if any.
matchRotateHalf(DAG, RHS, RHSShift, RHSMask);
// If neither side matched a rotate half, bail
if (!LHSShift && !RHSShift)
return SDValue();
// InstCombine may have combined a constant shl, srl, mul, or udiv with one
// side of the rotate, so try to handle that here. In all cases we need to
// pass the matched shift from the opposite side to compute the opcode and
// needed shift amount to extract. We still want to do this if both sides
// matched a rotate half because one half may be a potential overshift that
// can be broken down (ie if InstCombine merged two shl or srl ops into a
// single one).
// Have LHS side of the rotate, try to extract the needed shift from the RHS.
if (LHSShift)
if (SDValue NewRHSShift =
extractShiftForRotate(DAG, LHSShift, RHS, RHSMask, DL))
RHSShift = NewRHSShift;
// Have RHS side of the rotate, try to extract the needed shift from the LHS.
if (RHSShift)
if (SDValue NewLHSShift =
extractShiftForRotate(DAG, RHSShift, LHS, LHSMask, DL))
LHSShift = NewLHSShift;
// If a side is still missing, nothing else we can do.
if (!RHSShift || !LHSShift)
return SDValue();
// At this point we've matched or extracted a shift op on each side.
if (LHSShift.getOpcode() == RHSShift.getOpcode())
return SDValue(); // Shifts must disagree.
// Canonicalize shl to left side in a shl/srl pair.
if (RHSShift.getOpcode() == ISD::SHL) {
std::swap(LHS, RHS);
std::swap(LHSShift, RHSShift);
std::swap(LHSMask, RHSMask);
}
// Something has gone wrong - we've lost the shl/srl pair - bail.
if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL)
return SDValue();
unsigned EltSizeInBits = VT.getScalarSizeInBits();
SDValue LHSShiftArg = LHSShift.getOperand(0);
SDValue LHSShiftAmt = LHSShift.getOperand(1);
SDValue RHSShiftArg = RHSShift.getOperand(0);
SDValue RHSShiftAmt = RHSShift.getOperand(1);
auto MatchRotateSum = [EltSizeInBits](ConstantSDNode *LHS,
ConstantSDNode *RHS) {
return (LHS->getAPIntValue() + RHS->getAPIntValue()) == EltSizeInBits;
};
auto ApplyMasks = [&](SDValue Res) {
// If there is an AND of either shifted operand, apply it to the result.
if (LHSMask.getNode() || RHSMask.getNode()) {
SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
SDValue Mask = AllOnes;
if (LHSMask.getNode()) {
SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt);
Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
DAG.getNode(ISD::OR, DL, VT, LHSMask, RHSBits));
}
if (RHSMask.getNode()) {
SDValue LHSBits = DAG.getNode(ISD::SHL, DL, VT, AllOnes, LHSShiftAmt);
Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
DAG.getNode(ISD::OR, DL, VT, RHSMask, LHSBits));
}
Res = DAG.getNode(ISD::AND, DL, VT, Res, Mask);
}
return Res;
};
// TODO: Support pre-legalization funnel-shift by constant.
bool IsRotate = LHSShiftArg == RHSShiftArg;
if (!IsRotate && !(HasFSHL || HasFSHR)) {
if (TLI.isTypeLegal(VT) && LHS.hasOneUse() && RHS.hasOneUse() &&
ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) {
// Look for a disguised rotate by constant.
// The common shifted operand X may be hidden inside another 'or'.
SDValue X, Y;
auto matchOr = [&X, &Y](SDValue Or, SDValue CommonOp) {
if (!Or.hasOneUse() || Or.getOpcode() != ISD::OR)
return false;
if (CommonOp == Or.getOperand(0)) {
X = CommonOp;
Y = Or.getOperand(1);
return true;
}
if (CommonOp == Or.getOperand(1)) {
X = CommonOp;
Y = Or.getOperand(0);
return true;
}
return false;
};
SDValue Res;
if (matchOr(LHSShiftArg, RHSShiftArg)) {
// (shl (X | Y), C1) | (srl X, C2) --> (rotl X, C1) | (shl Y, C1)
SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt);
SDValue ShlY = DAG.getNode(ISD::SHL, DL, VT, Y, LHSShiftAmt);
Res = DAG.getNode(ISD::OR, DL, VT, RotX, ShlY);
} else if (matchOr(RHSShiftArg, LHSShiftArg)) {
// (shl X, C1) | (srl (X | Y), C2) --> (rotl X, C1) | (srl Y, C2)
SDValue RotX = DAG.getNode(ISD::ROTL, DL, VT, X, LHSShiftAmt);
SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt);
Res = DAG.getNode(ISD::OR, DL, VT, RotX, SrlY);
} else {
return SDValue();
}
return ApplyMasks(Res);
}
return SDValue(); // Requires funnel shift support.
}
// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
// fold (or (shl x, C1), (srl y, C2)) -> (fshl x, y, C1)
// fold (or (shl x, C1), (srl y, C2)) -> (fshr x, y, C2)
// iff C1+C2 == EltSizeInBits
if (ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) {
SDValue Res;
if (IsRotate && (HasROTL || HasROTR || !(HasFSHL || HasFSHR))) {
bool UseROTL = !LegalOperations || HasROTL;
Res = DAG.getNode(UseROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg,
UseROTL ? LHSShiftAmt : RHSShiftAmt);
} else {
bool UseFSHL = !LegalOperations || HasFSHL;
Res = DAG.getNode(UseFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg,
RHSShiftArg, UseFSHL ? LHSShiftAmt : RHSShiftAmt);
}
return ApplyMasks(Res);
}
// Even pre-legalization, we can't easily rotate/funnel-shift by a variable
// shift.
if (!HasROTL && !HasROTR && !HasFSHL && !HasFSHR)
return SDValue();
// If there is a mask here, and we have a variable shift, we can't be sure
// that we're masking out the right stuff.
if (LHSMask.getNode() || RHSMask.getNode())
return SDValue();
// If the shift amount is sign/zext/any-extended just peel it off.
SDValue LExtOp0 = LHSShiftAmt;
SDValue RExtOp0 = RHSShiftAmt;
if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
(RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
LExtOp0 = LHSShiftAmt.getOperand(0);
RExtOp0 = RHSShiftAmt.getOperand(0);
}
if (IsRotate && (HasROTL || HasROTR)) {
SDValue TryL =
MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt, LExtOp0,
RExtOp0, HasROTL, ISD::ROTL, ISD::ROTR, DL);
if (TryL)
return TryL;
SDValue TryR =
MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt, RExtOp0,
LExtOp0, HasROTR, ISD::ROTR, ISD::ROTL, DL);
if (TryR)
return TryR;
}
SDValue TryL =
MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, LHSShiftAmt, RHSShiftAmt,
LExtOp0, RExtOp0, HasFSHL, ISD::FSHL, ISD::FSHR, DL);
if (TryL)
return TryL;
SDValue TryR =
MatchFunnelPosNeg(LHSShiftArg, RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
RExtOp0, LExtOp0, HasFSHR, ISD::FSHR, ISD::FSHL, DL);
if (TryR)
return TryR;
return SDValue();
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x248, %rsp # imm = 0x248
movq %r9, %r15
movl %r8d, 0x64(%rsp)
movq %rcx, 0x78(%rsp)
movq %rsi, %rbp
movq %rdi, %r14
movq 0x30(%rsi), %rax
movl %edx, 0x60(%rsp)
movl %edx, %r13d
shlq $0x4, %r13
movl (%rax,%r13), %edx
movq 0x8(%rax,%r13), %rcx
movb %dl, 0x68(%rsp)
movq %rcx, 0x70(%rsp)
movq 0x8(%rdi), %rdi
movzbl 0x21(%r14), %r8d
movl $0xc0, %esi
callq 0x92126e
movb %al, 0x88(%rsp)
movq 0x70(%rsp), %rcx
movq 0x8(%r14), %rdi
movzbl 0x21(%r14), %r8d
movl 0x68(%rsp), %edx
movl $0xc1, %esi
callq 0x92126e
movb %al, 0x5d(%rsp)
movq 0x70(%rsp), %rcx
movq 0x8(%r14), %rdi
movzbl 0x21(%r14), %r8d
movl 0x68(%rsp), %edx
movl $0xc2, %esi
callq 0x92126e
movl %eax, %r12d
movq 0x70(%rsp), %rcx
movq 0x8(%r14), %rdi
movzbl 0x21(%r14), %r8d
movl 0x68(%rsp), %edx
movl $0xc3, %esi
callq 0x92126e
movb %al, 0x5f(%rsp)
movb 0x68(%rsp), %bl
testb %bl, %bl
je 0x16d6a14
leal -0x2(%rbx), %eax
cmpb $0x8, %al
setb %al
jmp 0x16d6a1e
leaq 0x68(%rsp), %rdi
callq 0x1e89dd2
testb %al, %al
je 0x16d6a99
movq (%r14), %rax
movq 0x8(%r14), %rsi
movq 0x40(%rax), %rdx
movq 0x70(%rsp), %r8
movzbl %bl, %ecx
leaq 0x100(%rsp), %rbx
movq %rbx, %rdi
callq 0x1e6d32e
cmpb $0x1, (%rbx)
jne 0x16d6a99
movzbl 0x68(%rsp), %ecx
movl $0x10ea, %edx # imm = 0x10EA
addq 0x8(%r14), %rdx
testq %rcx, %rcx
je 0x16d6a71
imulq $0x1e5, %rcx, %rax # imm = 0x1E5
cmpb $0x4, 0xc0(%rdx,%rax)
sete %al
jmp 0x16d6a73
xorl %eax, %eax
testq %rcx, %rcx
je 0x16d6a8c
imulq $0x1e5, %rcx, %rcx # imm = 0x1E5
cmpb $0x4, 0xc1(%rdx,%rcx)
sete %cl
jmp 0x16d6a8e
xorl %ecx, %ecx
orb %al, 0x88(%rsp)
orb %cl, 0x5d(%rsp)
movb 0x21(%r14), %al
xorb $0x1, %al
orb 0x5d(%rsp), %al
orb %r12b, %al
orb 0x5f(%rsp), %al
orb 0x88(%rsp), %al
cmpb $0x1, %al
jne 0x16d7490
movq %r15, 0x80(%rsp)
cmpl $0xd7, 0x18(%rbp)
jne 0x16d6bea
movq 0x78(%rsp), %rax
cmpl $0xd7, 0x18(%rax)
jne 0x16d6bea
movq 0x28(%rbp), %rax
movq (%rax), %rsi
movl 0x8(%rax), %edx
movq 0x30(%rsi), %rax
movq %rdx, %rdi
shlq $0x4, %rdi
movb (%rax,%rdi), %r11b
movq 0x78(%rsp), %rcx
movq 0x28(%rcx), %r8
movq (%r8), %rcx
movl 0x8(%r8), %r8d
movq 0x30(%rcx), %r9
movq %r8, %r10
shlq $0x4, %r10
cmpb (%r9,%r10), %r11b
jne 0x16d6bea
testb %r11b, %r11b
jne 0x16d6b37
addq %rdi, %rax
addq %r10, %r9
movq 0x8(%r9), %rdi
cmpq %rdi, 0x8(%rax)
jne 0x16d6bea
movq %r14, %rdi
movq 0x80(%rsp), %r9
callq 0x16d6944
testq %rax, %rax
je 0x16d6bea
movq %rax, %rbx
movl %edx, %r15d
movq (%r14), %r14
movq 0x48(%rbp), %rsi
movq %rsi, 0x100(%rsp)
testq %rsi, %rsi
je 0x16d6b7c
leaq 0x100(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbp), %eax
leaq 0x100(%rsp), %r12
movl %eax, 0x8(%r12)
movq 0x30(%rbp), %rax
movq 0x8(%rax,%r13), %r8
movl (%rax,%r13), %ecx
movq %rbx, 0x1e0(%rsp)
movl %r15d, 0x1e8(%rsp)
movups 0x1e0(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r14, %rdi
movl $0xd7, %esi
movq %r12, %rdx
callq 0x176388a
movq %rax, %rbx
movl %edx, %r15d
movq (%r12), %rsi
testq %rsi, %rsi
je 0x16d7495
leaq 0x100(%rsp), %rdi
callq 0x2a758fc
jmp 0x16d7495
leaq 0xf0(%rsp), %rcx
movq $0x0, (%rcx)
movl $0x0, 0x8(%rcx)
movq (%r14), %rdi
movq %rbp, %rsi
movl 0x60(%rsp), %edx
callq 0x16d9bc6
movq %rax, %r13
movl 0x18(%rax), %eax
orl $0x2, %eax
cmpl $0xbf, %eax
movb %r12b, 0x5e(%rsp)
je 0x16d6c27
xorl %r13d, %r13d
leaq 0xc0(%rsp), %rcx
movq $0x0, (%rcx)
movl $0x0, 0x8(%rcx)
movq (%r14), %rdi
movq 0x78(%rsp), %rsi
movl 0x64(%rsp), %edx
callq 0x16d9bc6
movq %rax, %r12
movl 0x18(%rax), %eax
xorl %r15d, %r15d
orl $0x2, %eax
cmpl $0xbf, %eax
je 0x16d6c64
xorl %r12d, %r12d
movq %r13, %rax
orq %r12, %rax
je 0x16d7493
testq %r13, %r13
je 0x16d6ca5
movq (%r14), %rdi
leaq 0xc0(%rsp), %r8
movq %r13, %rsi
movq 0x78(%rsp), %rdx
movl 0x64(%rsp), %ecx
movq 0x80(%rsp), %rbx
movq %rbx, %r9
callq 0x16d8994
testq %rax, %rax
cmovneq %rax, %r12
jmp 0x16d6cad
movq 0x80(%rsp), %rbx
testq %r12, %r12
je 0x16d6cd6
movq (%r14), %rdi
leaq 0xf0(%rsp), %r8
movq %r12, %rsi
movq %rbp, %rdx
movl 0x60(%rsp), %ecx
movq %rbx, %r9
callq 0x16d8994
testq %rax, %rax
cmovneq %rax, %r13
xorl %r15d, %r15d
testq %r12, %r12
je 0x16d7493
movl $0x0, %ebx
testq %r13, %r13
je 0x16d7495
movl 0x18(%r12), %eax
cmpl %eax, 0x18(%r13)
je 0x16d7490
cmpl $0xbd, %eax
jne 0x16d6d5f
movups 0xf0(%rsp), %xmm0
movaps %xmm0, 0x100(%rsp)
movl 0xc8(%rsp), %eax
movl %eax, 0xf8(%rsp)
movq 0xc0(%rsp), %rax
movq %rax, 0xf0(%rsp)
movq 0x100(%rsp), %rax
movq %rax, 0xc0(%rsp)
movl 0x108(%rsp), %eax
movl %eax, 0xc8(%rsp)
movq %r13, %rbx
movq %rbp, %rcx
movl 0x60(%rsp), %r15d
jmp 0x16d6d7c
movq %r12, %rbx
movq %r13, %r12
movq 0x78(%rsp), %rcx
movl 0x64(%rsp), %r15d
movq %rbp, 0x78(%rsp)
movl 0x60(%rsp), %eax
movl %eax, 0x64(%rsp)
cmpl $0xbd, 0x18(%r12)
jne 0x16d7490
cmpl $0xbf, 0x18(%rbx)
jne 0x16d7490
movq %rcx, 0x140(%rsp)
leaq 0x68(%rsp), %rbp
movq %rbp, %rdi
callq 0x9254d2
movq %rax, %r9
movq 0x28(%r12), %rax
movq (%rax), %rdx
movl 0x8(%rax), %ecx
movl 0xc(%rax), %r8d
movups 0x28(%rax), %xmm0
leaq 0x90(%rsp), %rdi
movaps %xmm0, (%rdi)
movq 0x28(%rbx), %rax
movq (%rax), %rbx
movq 0x8(%rax), %xmm1
movd %xmm1, %esi
movups 0x28(%rax), %xmm0
leaq 0xb0(%rsp), %r12
movaps %xmm0, (%r12)
leaq 0xf0(%rsp), %rax
movq %rax, 0x100(%rsp)
leaq 0xc0(%rsp), %rax
movq %rax, 0x108(%rsp)
movq %r14, 0x110(%rsp)
movq 0x80(%rsp), %rax
movq %rax, 0x118(%rsp)
movq %rbp, 0x120(%rsp)
movq %r12, 0x128(%rsp)
movq %rdi, 0x130(%rsp)
movq %rdx, 0xa8(%rsp)
cmpq %rbx, %rdx
sete %al
movl %ecx, 0x60(%rsp)
movl %esi, 0xa4(%rsp)
cmpl %esi, %ecx
sete %bpl
andb %al, %bpl
movb 0x5f(%rsp), %r13b
orb 0x5e(%rsp), %r13b
movl %r13d, %eax
orb %bpl, %al
je 0x16d6fd5
movdqa %xmm1, 0x140(%rsp)
movl %r8d, 0x64(%rsp)
movq %rbx, 0x78(%rsp)
movq 0x90(%rsp), %rdi
movl 0x98(%rsp), %esi
movq 0xb0(%rsp), %rdx
movl 0xb8(%rsp), %ecx
xorps %xmm0, %xmm0
leaq 0x220(%rsp), %r15
movaps %xmm0, (%r15)
movaps %xmm0, 0x10(%r15)
movl %r9d, (%r15)
leaq 0x2e18(%rip), %rax # 0x16d9cde
movq %rax, 0x18(%r15)
leaq 0x2ed7(%rip), %rax # 0x16d9da8
movq %rax, 0x10(%r15)
movl $0x0, (%rsp)
movq %r15, %r8
xorl %r9d, %r9d
callq 0x1760fa3
movl %eax, %ebx
movq 0x10(%r15), %rax
testq %rax, %rax
je 0x16d6f04
leaq 0x220(%rsp), %rdi
movq %rdi, %rsi
movl $0x3, %edx
callq *%rax
testb %bl, %bl
movq 0x80(%rsp), %rdx
je 0x16d70ad
testb %bpl, %bpl
movq 0x78(%rsp), %r9
je 0x16d6f39
cmpb $0x1, %r13b
jne 0x16d7588
movb 0x88(%rsp), %al
orb %al, 0x5d(%rsp)
jne 0x16d7588
movb 0x21(%r14), %al
xorb $0x1, %al
movb 0x5e(%rsp), %cl
orb %al, %cl
movq (%r14), %rdi
movzbl %cl, %eax
movl %eax, %esi
xorl $0xc3, %esi
movq 0x70(%rsp), %r8
movq 0xa8(%rsp), %rcx
movq %rcx, 0x150(%rsp)
movl 0x60(%rsp), %ecx
movl %ecx, 0x158(%rsp)
movl 0x64(%rsp), %ecx
movl %ecx, 0x15c(%rsp)
movq %r9, 0x170(%rsp)
movaps 0x140(%rsp), %xmm0
movlps %xmm0, 0x178(%rsp)
testb %al, %al
leaq 0x90(%rsp), %rax
cmovneq %rax, %r12
movl 0x68(%rsp), %ecx
movups 0x170(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x150(%rsp), %xmm0
movups %xmm0, (%rsp)
movups (%r12), %xmm0
movups %xmm0, 0x20(%rsp)
callq 0x1764b02
jmp 0x16d75fd
movzbl 0x68(%rsp), %eax
testq %rax, %rax
je 0x16d734a
movq 0x8(%r14), %rcx
cmpq $0x0, 0x68(%rcx,%rax,8)
movl 0x60(%rsp), %ebp
movq 0xa8(%rsp), %r12
je 0x16d7341
movq %r9, 0x88(%rsp)
movq 0x78(%rsp), %rdi
movl $0x1, %esi
movl 0x64(%rsp), %edx
callq 0x179219e
testb %al, %al
je 0x16d7341
movq %rbx, %r13
movq 0x140(%rsp), %rdi
movl $0x1, %esi
movl %r15d, %edx
callq 0x179219e
testb %al, %al
je 0x16d7344
movq 0x90(%rsp), %rdi
movl 0x98(%rsp), %esi
movq 0xb0(%rsp), %rdx
movl 0xb8(%rsp), %ecx
xorps %xmm0, %xmm0
leaq 0x200(%rsp), %r8
movaps %xmm0, (%r8)
movaps %xmm0, 0x10(%r8)
movq 0x88(%rsp), %rax
movl %eax, (%r8)
leaq 0x2c58(%rip), %rax # 0x16d9cde
movq %rax, 0x18(%r8)
leaq 0x2d17(%rip), %rax # 0x16d9da8
movq %rax, 0x10(%r8)
movl $0x0, (%rsp)
xorl %r9d, %r9d
callq 0x1760fa3
movl %eax, %ebx
movb $0x1, %al
jmp 0x16d735d
movb 0x5d(%rsp), %al
orb 0x88(%rsp), %al
orb %al, %r13b
cmpb $0x1, %r13b
jne 0x16d7490
movq 0xc0(%rsp), %rcx
orq 0xf0(%rsp), %rcx
jne 0x16d7490
movaps 0x90(%rsp), %xmm0
movaps %xmm0, 0xe0(%rsp)
movaps 0xb0(%rsp), %xmm0
movaps %xmm0, 0xd0(%rsp)
movq 0x90(%rsp), %rcx
movl 0x18(%rcx), %edx
andl $-0x4, %edx
cmpl $0xd4, %edx
jne 0x16d7159
movq 0xb0(%rsp), %rdx
movl 0x18(%rdx), %esi
andl $-0x4, %esi
cmpl $0xd4, %esi
jne 0x16d7159
movq 0x28(%rcx), %rsi
movl 0x8(%rsi), %edi
movl %edi, 0xe8(%rsp)
movq (%rsi), %rsi
movq %rsi, 0xe0(%rsp)
movq 0x28(%rdx), %rdx
movl 0x8(%rdx), %esi
movl %esi, 0xd8(%rsp)
movq (%rdx), %rdx
movq %rdx, 0xd0(%rsp)
andb %bpl, %al
cmpb $0x1, %al
movl 0x60(%rsp), %ebp
movq 0xa8(%rsp), %r13
jne 0x16d7248
movl 0x98(%rsp), %r8d
movaps 0xd0(%rsp), %xmm0
movups %xmm0, 0x20(%rsp)
movaps 0xe0(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movaps 0xb0(%rsp), %xmm0
movups %xmm0, (%rsp)
movq 0x80(%rsp), %r12
movq %r12, 0x40(%rsp)
movl $0xc1, 0x38(%rsp)
movl $0xc0, 0x30(%rsp)
movzbl 0x88(%rsp), %r9d
movq %r14, %rdi
movq %r13, %rsi
movl %ebp, %edx
callq 0x16d94a0
testq %rax, %rax
jne 0x16d760d
movq 0xb0(%rsp), %rcx
movl 0xb8(%rsp), %r8d
movaps 0xe0(%rsp), %xmm0
movups %xmm0, 0x20(%rsp)
movaps 0xd0(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movaps 0x90(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r12, 0x40(%rsp)
movl $0xc0, 0x38(%rsp)
movl $0xc1, 0x30(%rsp)
movzbl 0x5d(%rsp), %r9d
movq %r14, %rdi
movq 0x78(%rsp), %rsi
movl 0xa4(%rsp), %edx
callq 0x16d94a0
testq %rax, %rax
jne 0x16d760d
movaps 0xd0(%rsp), %xmm0
movups %xmm0, 0x30(%rsp)
movaps 0xe0(%rsp), %xmm0
movups %xmm0, 0x20(%rsp)
movaps 0xb0(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movaps 0x90(%rsp), %xmm0
movups %xmm0, (%rsp)
movq 0x80(%rsp), %r12
movq %r12, 0x50(%rsp)
movl $0xc3, 0x48(%rsp)
movl $0xc2, 0x40(%rsp)
movzbl 0x5e(%rsp), %r9d
movq %r14, %rdi
movq %r13, %rsi
movl %ebp, %edx
movq 0x78(%rsp), %rbp
movq %rbp, %rcx
movl 0xa4(%rsp), %r13d
movl %r13d, %r8d
callq 0x16d959c
testq %rax, %rax
jne 0x16d760d
movaps 0xe0(%rsp), %xmm0
movups %xmm0, 0x30(%rsp)
movaps 0xd0(%rsp), %xmm0
movups %xmm0, 0x20(%rsp)
movaps 0x90(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movaps 0xb0(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r12, 0x50(%rsp)
movl $0xc2, 0x48(%rsp)
movl $0xc3, 0x40(%rsp)
movzbl 0x5f(%rsp), %r9d
movq %r14, %rdi
movq 0xa8(%rsp), %rsi
movl 0x60(%rsp), %edx
movq %rbp, %rcx
movl %r13d, %r8d
callq 0x16d959c
movq %rax, %rbx
xorl %r15d, %r15d
testq %rax, %rax
cmovnel %edx, %r15d
jmp 0x16d7495
movq %rbx, %r13
xorl %eax, %eax
xorl %ebx, %ebx
jmp 0x16d735d
movq %rbx, %r13
xorl %eax, %eax
xorl %ebx, %ebx
movl 0x60(%rsp), %ebp
movq 0xa8(%rsp), %r12
testb %al, %al
je 0x16d7380
movq 0x210(%rsp), %rax
testq %rax, %rax
je 0x16d7380
leaq 0x200(%rsp), %rdi
movq %rdi, %rsi
movl $0x3, %edx
callq *%rax
testb %bl, %bl
je 0x16d7490
xorl %r15d, %r15d
leaq 0x1d0(%rsp), %rax
movq %r15, (%rax)
movl %r15d, 0x8(%rax)
leaq 0x1c0(%rsp), %rcx
movq %r15, (%rcx)
movl %r15d, 0x8(%rcx)
leaq 0x1f0(%rsp), %rdi
movq %rax, (%rdi)
movq %rcx, 0x8(%rdi)
movq %r12, %rsi
movl %ebp, %edx
movq %r13, %rbx
movq %r13, %rcx
movl 0xa4(%rsp), %r13d
movl %r13d, %r8d
callq 0x16d915a
testb %al, %al
je 0x16d74ad
movq (%r14), %rdi
movq 0x70(%rsp), %r8
movl 0x68(%rsp), %ecx
movaps 0x90(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x1d0(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0xc0, %esi
movq 0x80(%rsp), %r15
movq %r15, %rdx
callq 0x17638a8
movq %rax, %rbx
movl %edx, %ebp
movq (%r14), %rdi
movq 0x70(%rsp), %r8
movl 0x68(%rsp), %ecx
movaps 0x90(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x1c0(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0xbd, %esi
movq %r15, %rdx
callq 0x17638a8
movq (%r14), %rdi
movq 0x70(%rsp), %r8
movq %rbx, 0x1b0(%rsp)
movl %ebp, 0x1b8(%rsp)
movq %rax, 0x1a0(%rsp)
movl %edx, 0x1a8(%rsp)
movl 0x68(%rsp), %ecx
movups 0x1a0(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x1b0(%rsp), %xmm0
jmp 0x16d757a
xorl %r15d, %r15d
xorl %ebx, %ebx
movq %rbx, %rax
movl %r15d, %edx
addq $0x248, %rsp # imm = 0x248
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
leaq 0x1f0(%rsp), %rdi
movq %rbx, %rsi
movl %r13d, %edx
movq %r12, %rcx
movl %ebp, %r8d
callq 0x16d915a
testb %al, %al
je 0x16d7493
movq (%r14), %rdi
movq 0x70(%rsp), %r8
movl 0x68(%rsp), %ecx
movaps 0x90(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x1d0(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0xc0, %esi
movq 0x80(%rsp), %r15
movq %r15, %rdx
callq 0x17638a8
movq %rax, %rbx
movl %edx, %ebp
movq (%r14), %rdi
movq 0x70(%rsp), %r8
movl 0x68(%rsp), %ecx
movaps 0xb0(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x1c0(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0xbf, %esi
movq %r15, %rdx
callq 0x17638a8
movq (%r14), %rdi
movq 0x70(%rsp), %r8
movq %rbx, 0x190(%rsp)
movl %ebp, 0x198(%rsp)
movq %rax, 0x180(%rsp)
movl %edx, 0x188(%rsp)
movl 0x68(%rsp), %ecx
movups 0x180(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x190(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0xba, %esi
movq %r15, %rdx
jmp 0x16d75f8
movb 0x21(%r14), %al
xorb $0x1, %al
movb 0x88(%rsp), %cl
orb %al, %cl
movq (%r14), %rdi
movzbl %cl, %eax
movl %eax, %esi
xorl $0xc1, %esi
movq 0x70(%rsp), %r8
movq 0xa8(%rsp), %rcx
movq %rcx, 0x160(%rsp)
movl 0x60(%rsp), %ecx
movl %ecx, 0x168(%rsp)
movl 0x64(%rsp), %ecx
movl %ecx, 0x16c(%rsp)
testb %al, %al
leaq 0x90(%rsp), %rax
cmovneq %rax, %r12
movl 0x68(%rsp), %ecx
movups 0x160(%rsp), %xmm0
movups %xmm0, (%rsp)
movups (%r12), %xmm0
movups %xmm0, 0x10(%rsp)
callq 0x17638a8
leaq 0x100(%rsp), %rdi
movq %rax, %rsi
callq 0x16d91e4
movq %rax, %rbx
movl %edx, %r15d
jmp 0x16d7495
|
/CodeGen/SelectionDAG/DAGCombiner.cpp
|
combineMinNumMaxNumImpl(llvm::SDLoc const&, llvm::EVT, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::ISD::CondCode, llvm::TargetLowering const&, llvm::SelectionDAG&)
|
static SDValue combineMinNumMaxNumImpl(const SDLoc &DL, EVT VT, SDValue LHS,
SDValue RHS, SDValue True, SDValue False,
ISD::CondCode CC,
const TargetLowering &TLI,
SelectionDAG &DAG) {
EVT TransformVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
switch (CC) {
case ISD::SETOLT:
case ISD::SETOLE:
case ISD::SETLT:
case ISD::SETLE:
case ISD::SETULT:
case ISD::SETULE: {
// Since it's known never nan to get here already, either fminnum or
// fminnum_ieee are OK. Try the ieee version first, since it's fminnum is
// expanded in terms of it.
unsigned IEEEOpcode = (LHS == True) ? ISD::FMINNUM_IEEE : ISD::FMAXNUM_IEEE;
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
return SDValue();
}
case ISD::SETOGT:
case ISD::SETOGE:
case ISD::SETGT:
case ISD::SETGE:
case ISD::SETUGT:
case ISD::SETUGE: {
unsigned IEEEOpcode = (LHS == True) ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
if (TLI.isOperationLegalOrCustom(IEEEOpcode, VT))
return DAG.getNode(IEEEOpcode, DL, VT, LHS, RHS);
unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
if (TLI.isOperationLegalOrCustom(Opcode, TransformVT))
return DAG.getNode(Opcode, DL, VT, LHS, RHS);
return SDValue();
}
default:
return SDValue();
}
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movl %r9d, %ebp
movl %r8d, 0x2c(%rsp)
movq %rcx, %r15
movq %rdx, %rbx
movl %esi, %r14d
movq %rdi, %r12
movq 0xe8(%rsp), %rax
movq 0xe0(%rsp), %rdi
movq 0x40(%rax), %rsi
movq (%rdi), %rax
movl %r14d, %edx
movq %rbx, %rcx
callq *0x240(%rax)
movl %eax, %edi
xorl %r13d, %r13d
xorl %eax, %eax
cmpl $0x15, %ebp
ja 0x16deef1
movq %rdx, %rsi
leaq 0xd0(%rsp), %rcx
movl $0xc0c0c, %edx # imm = 0xC0C0C
btl %ebp, %edx
movq %r12, 0x38(%rsp)
movq %rsi, 0x40(%rsp)
movb %dil, 0x2b(%rsp)
jb 0x16ded92
movl $0x303030, %edx # imm = 0x303030
btl %ebp, %edx
movl 0x2c(%rsp), %r8d
movq 0xe0(%rsp), %rdx
jae 0x16deef1
cmpq %r15, (%rcx)
sete %al
cmpl %r8d, 0x8(%rcx)
sete %cl
andb %al, %cl
movzbl %cl, %r12d
movl %r12d, %ebp
xorl $0x115, %ebp # imm = 0x115
movzbl %r14b, %r14d
xorl %r13d, %r13d
movq %rdx, %rdi
movl %ebp, %esi
movl %r14d, %edx
movq %rbx, %rcx
movq %rbx, 0x30(%rsp)
movl %r8d, %ebx
xorl %r8d, %r8d
callq 0x92126e
testb %al, %al
je 0x16dee7a
movq %r15, 0x78(%rsp)
movl %ebx, 0x80(%rsp)
leaq 0xc0(%rsp), %rax
movups (%rax), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x78(%rsp), %xmm0
movups %xmm0, (%rsp)
movq 0xe8(%rsp), %rdi
movl %ebp, %esi
movq 0x38(%rsp), %rdx
movl %r14d, %ecx
movq 0x30(%rsp), %r8
jmp 0x16deee5
cmpq %r15, (%rcx)
sete %al
movq %r15, 0x30(%rsp)
movq %rbx, %r15
movl 0x2c(%rsp), %ebx
cmpl %ebx, 0x8(%rcx)
sete %cl
andb %al, %cl
movzbl %cl, %ebp
leal 0x114(%rbp), %r12d
movzbl %r14b, %r14d
xorl %r13d, %r13d
movq 0xe0(%rsp), %rdi
movl %r12d, %esi
movl %r14d, %edx
movq %r15, %rcx
xorl %r8d, %r8d
callq 0x92126e
testb %al, %al
je 0x16dee0e
movq 0x30(%rsp), %rax
movq %rax, 0x58(%rsp)
movl %ebx, 0x60(%rsp)
leaq 0xc0(%rsp), %rax
movups (%rax), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x58(%rsp), %xmm0
movups %xmm0, (%rsp)
movq 0xe8(%rsp), %rdi
movl %r12d, %esi
jmp 0x16dee6d
movq 0x30(%rsp), %rbx
orl $0x112, %ebp # imm = 0x112
movzbl 0x2b(%rsp), %edx
movq 0xe0(%rsp), %rdi
movl %ebp, %esi
movq 0x40(%rsp), %rcx
xorl %r8d, %r8d
callq 0x92126e
testb %al, %al
je 0x16deeef
movq %rbx, 0x48(%rsp)
movl 0x2c(%rsp), %eax
movl %eax, 0x50(%rsp)
leaq 0xc0(%rsp), %rax
movups (%rax), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x48(%rsp), %xmm0
movups %xmm0, (%rsp)
movq 0xe8(%rsp), %rdi
movl %ebp, %esi
movq 0x38(%rsp), %rdx
movl %r14d, %ecx
movq %r15, %r8
jmp 0x16deee5
movl %r14d, %ebx
movq 0x30(%rsp), %r14
xorl $0x113, %r12d # imm = 0x113
movzbl 0x2b(%rsp), %edx
movq 0xe0(%rsp), %rdi
movl %r12d, %esi
movq 0x40(%rsp), %rcx
xorl %r8d, %r8d
callq 0x92126e
testb %al, %al
je 0x16deeef
movq %r15, 0x68(%rsp)
movl 0x2c(%rsp), %eax
movl %eax, 0x70(%rsp)
leaq 0xc0(%rsp), %rax
movups (%rax), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x68(%rsp), %xmm0
movups %xmm0, (%rsp)
movq 0xe8(%rsp), %rdi
movl %r12d, %esi
movq 0x38(%rsp), %rdx
movl %ebx, %ecx
movq %r14, %r8
callq 0x17638a8
movl %edx, %r13d
jmp 0x16deef1
xorl %eax, %eax
movl %r13d, %edx
addq $0x88, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/CodeGen/SelectionDAG/DAGCombiner.cpp
|
std::pair<int, llvm::SDValue>& llvm::SmallVectorTemplateBase<std::pair<int, llvm::SDValue>, true>::growAndEmplaceBack<int, llvm::SDValue&>(int&&, llvm::SDValue&)
|
T &growAndEmplaceBack(ArgTypes &&... Args) {
// Use push_back with a copy in case Args has an internal reference,
// side-stepping reference invalidation problems without losing the realloc
// optimization.
push_back(T(std::forward<ArgTypes>(Args)...));
return this->back();
}
|
pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movl (%rsi), %eax
leaq 0x8(%rsp), %rsi
movl %eax, (%rsi)
movups (%rdx), %xmm0
movups %xmm0, 0x8(%rsi)
movl $0x1, %edx
callq 0x16f5672
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
movq 0x10(%rax), %rsi
movq %rsi, 0x10(%rcx,%rdx,8)
movups (%rax), %xmm0
movups %xmm0, (%rcx,%rdx,8)
movl 0x8(%rbx), %eax
incl %eax
movl %eax, 0x8(%rbx)
movq (%rbx), %rcx
leaq (%rax,%rax,2), %rax
leaq (%rcx,%rax,8), %rax
addq $-0x18, %rax
addq $0x20, %rsp
popq %rbx
retq
nop
|
/llvm/ADT/SmallVector.h
|
int* llvm::SmallVectorImpl<int>::insert<int*, void>(int*, int*, int*)
|
iterator insert(iterator I, ItTy From, ItTy To) {
// Convert iterator to elt# to avoid invalidating iterator when we reserve()
size_t InsertElt = I - this->begin();
if (I == this->end()) { // Important special case for empty vector.
append(From, To);
return this->begin()+InsertElt;
}
assert(this->isReferenceToStorage(I) && "Insertion iterator is out of bounds.");
// Check that the reserve that follows doesn't invalidate the iterators.
this->assertSafeToAddRange(From, To);
size_t NumToInsert = std::distance(From, To);
// Ensure there is enough space.
reserve(this->size() + NumToInsert);
// Uninvalidate the iterator.
I = this->begin()+InsertElt;
// If there are more elements between the insertion point and the end of the
// range than there are being inserted, we can use a simple approach to
// insertion. Since we already reserved space, we know that this won't
// reallocate the vector.
if (size_t(this->end()-I) >= NumToInsert) {
T *OldEnd = this->end();
append(std::move_iterator<iterator>(this->end() - NumToInsert),
std::move_iterator<iterator>(this->end()));
// Copy the existing elements that get replaced.
std::move_backward(I, OldEnd-NumToInsert, OldEnd);
std::copy(From, To, I);
return I;
}
// Otherwise, we're inserting more elements than exist already, and we're
// not inserting at the end.
// Move over the elements that we're about to overwrite.
T *OldEnd = this->end();
this->set_size(this->size() + NumToInsert);
size_t NumOverwritten = OldEnd-I;
this->uninitialized_move(I, OldEnd, this->end()-NumOverwritten);
// Replace the overwritten part.
for (T *J = I; NumOverwritten > 0; --NumOverwritten) {
*J = *From;
++J; ++From;
}
// Insert the non-overwritten middle part.
this->uninitialized_copy(From, To, OldEnd);
return I;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, %rbx
movq %rdi, %r13
movq (%rdi), %rax
movq %rsi, %r12
subq %rax, %r12
movl 0x8(%rdi), %edx
leaq (%rax,%rdx,4), %rax
cmpq %rsi, %rax
je 0x16f847b
movq %rcx, 0x8(%rsp)
movq %rcx, %rbp
subq %rbx, %rbp
movq %rbp, 0x10(%rsp)
sarq $0x2, %rbp
addq %rbp, %rdx
movl 0xc(%r13), %eax
cmpq %rax, %rdx
jbe 0x16f83e4
leaq 0x10(%r13), %rsi
movl $0x4, %ecx
movq %r13, %rdi
callq 0x2b4ed86
movq (%r13), %rax
leaq (%rax,%r12), %r15
movl 0x8(%r13), %ecx
leaq (,%rcx,4), %rsi
leaq (%rax,%rcx,4), %r8
movq %rsi, %rdx
subq %r12, %rdx
movq %rdx, %r14
sarq $0x2, %r14
cmpq %rbp, %r14
jae 0x16f8492
addl %ecx, %ebp
movl %ebp, 0x8(%r13)
cmpq %r12, %rsi
je 0x16f8442
movl %ebp, %ecx
leaq (%rax,%rcx,4), %rdi
leaq (,%r14,4), %rax
subq %rax, %rdi
movq %rsi, %rbp
movq %r15, %rsi
movq %r8, %r13
callq 0x780890
movq %rbp, %rsi
movq %r13, %r8
cmpq %r12, %rsi
je 0x16f8461
xorl %eax, %eax
xorl %ecx, %ecx
movl (%rbx,%rcx,4), %edx
movl %edx, (%r15,%rcx,4)
incq %rcx
addq $-0x4, %rax
cmpq %rcx, %r14
jne 0x16f844b
subq %rax, %rbx
movq 0x8(%rsp), %rdx
cmpq %rdx, %rbx
je 0x16f84e8
subq %rbx, %rdx
movq %r8, %rdi
movq %rbx, %rsi
callq 0x780890
jmp 0x16f84e8
movq %r13, %rdi
movq %rbx, %rsi
movq %rcx, %rdx
callq 0x14be0cc
addq (%r13), %r12
movq %r12, %r15
jmp 0x16f84e8
shlq $0x2, %rbp
movq %r8, %r12
subq %rbp, %r12
movq %r13, %rdi
movq %r12, %rsi
movq %r8, %rdx
movq %r8, %r14
callq 0x16f8320
subq %r15, %r12
je 0x16f84c3
subq %r12, %r14
movq %r14, %rdi
movq %r15, %rsi
movq %r12, %rdx
callq 0x780120
cmpq %rbx, 0x8(%rsp)
je 0x16f84e8
movq %r15, %rdi
movq %rbx, %rsi
movq 0x10(%rsp), %rdx
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x780120
movq %r15, %rax
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/llvm/ADT/SmallVector.h
|
(anonymous namespace)::SelectionDAGLegalize::ReplaceNode(llvm::SDNode*, llvm::SDNode*)
|
void ReplaceNode(SDNode *Old, SDNode *New) {
LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
dbgs() << " with: "; New->dump(&DAG));
assert(Old->getNumValues() == New->getNumValues() &&
"Replacing one node with another that produces a different number "
"of values!");
DAG.ReplaceAllUsesWith(Old, New);
if (UpdatedNodes)
UpdatedNodes->insert(New);
ReplacedNode(Old);
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq %rdx, (%rsp)
movq 0x10(%rdi), %rdi
callq 0x176215a
movq 0x20(%r14), %rdi
testq %rdi, %rdi
je 0x170d61e
movq %rsp, %rsi
callq 0x1673b14
movq %r14, %rdi
movq %rbx, %rsi
callq 0x1719604
addq $0x8, %rsp
popq %rbx
popq %r14
retq
nop
|
/CodeGen/SelectionDAG/LegalizeDAG.cpp
|
llvm::SelectionDAGBuilder::visitCallBrLandingPad(llvm::CallInst const&)
|
void SelectionDAGBuilder::visitCallBrLandingPad(const CallInst &I) {
SmallVector<EVT, 8> ResultVTs;
SmallVector<SDValue, 8> ResultValues;
const auto *CBR =
cast<CallBrInst>(I.getParent()->getUniquePredecessor()->getTerminator());
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
unsigned InitialDef = FuncInfo.ValueMap[CBR];
SDValue Chain = DAG.getRoot();
// Re-parse the asm constraints string.
TargetLowering::AsmOperandInfoVector TargetConstraints =
TLI.ParseConstraints(DAG.getDataLayout(), TRI, *CBR);
for (auto &T : TargetConstraints) {
SDISelAsmOperandInfo OpInfo(T);
if (OpInfo.Type != InlineAsm::isOutput)
continue;
// Pencil in OpInfo.ConstraintType and OpInfo.ConstraintVT based on the
// individual constraint.
TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
switch (OpInfo.ConstraintType) {
case TargetLowering::C_Register:
case TargetLowering::C_RegisterClass: {
// Fill in OpInfo.AssignedRegs.Regs.
getRegistersForValue(DAG, getCurSDLoc(), OpInfo, OpInfo);
// getRegistersForValue may produce 1 to many registers based on whether
// the OpInfo.ConstraintVT is legal on the target or not.
for (unsigned &Reg : OpInfo.AssignedRegs.Regs) {
Register OriginalDef = FollowCopyChain(MRI, InitialDef++);
if (Register::isPhysicalRegister(OriginalDef))
FuncInfo.MBB->addLiveIn(OriginalDef);
// Update the assigned registers to use the original defs.
Reg = OriginalDef;
}
SDValue V = OpInfo.AssignedRegs.getCopyFromRegs(
DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, CBR);
ResultValues.push_back(V);
ResultVTs.push_back(OpInfo.ConstraintVT);
break;
}
case TargetLowering::C_Other: {
SDValue Flag;
SDValue V = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(),
OpInfo, DAG);
++InitialDef;
ResultValues.push_back(V);
ResultVTs.push_back(OpInfo.ConstraintVT);
break;
}
default:
break;
}
}
SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
DAG.getVTList(ResultVTs), ResultValues);
setValue(&I, V);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x308, %rsp # imm = 0x308
movq %rdi, %rbx
leaq 0x288(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x800000000, %rax # imm = 0x800000000
movq %rax, -0x8(%rcx)
leaq 0x1f8(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movq %rax, -0x8(%rcx)
movq %rsi, 0x40(%rsp)
movq 0x28(%rsi), %rdi
callq 0x29ca4a2
movq 0x30(%rax), %rcx
addq $0x30, %rax
cmpq %rax, %rcx
je 0x1750db0
leaq -0x18(%rcx), %rax
testq %rcx, %rcx
cmoveq %rcx, %rax
movzbl (%rax), %ecx
addl $-0x1e, %ecx
xorl %r15d, %r15d
cmpl $0xb, %ecx
cmovbq %rax, %r15
jmp 0x1750db3
xorl %r15d, %r15d
movq 0x340(%rbx), %rax
movq 0x10(%rax), %r12
movq %r12, 0x30(%rsp)
movq 0x28(%rax), %rax
movq 0x10(%rax), %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, %r14
movq 0x340(%rbx), %rax
movq 0x398(%rbx), %rdi
movq 0x28(%rax), %rax
movq 0x28(%rax), %r13
addq $0x50, %rdi
leaq 0x80(%rsp), %rsi
movq %r15, (%rsi)
callq 0x1176360
movl 0x8(%rax), %ebp
movq 0x340(%rbx), %rax
movups 0x140(%rax), %xmm0
movaps %xmm0, 0x60(%rsp)
movq 0x28(%rax), %rdi
callq 0x1d33c98
movq (%r12), %r9
movq %r15, %r8
leaq 0x1d0(%rsp), %r15
movq %r15, %rdi
movq %r12, %rsi
movq %rax, %rdx
movq %r14, %rcx
movq %r8, 0x48(%rsp)
callq *0x940(%r9)
movq (%r15), %r12
movq 0x8(%r15), %r15
cmpq %r15, %r12
je 0x17511b6
leaq 0x80(%rsp), %r14
movq %r15, 0x28(%rsp)
movq %rbx, 0x38(%rsp)
movq %r14, %rdi
movq %r12, %rsi
callq 0x1755168
cmpl $0x1, 0x80(%rsp)
jne 0x17510f7
movq 0x108(%rsp), %rdx
movl 0x110(%rsp), %ecx
movq 0x340(%rbx), %r8
movq 0x30(%rsp), %rdi
movq (%rdi), %rax
movq %r14, %rsi
callq *0x958(%rax)
movl 0xf0(%rsp), %eax
cmpl $0x2, %eax
jae 0x175103b
movq 0x340(%rbx), %r15
movq (%rbx), %rsi
movl 0x330(%rbx), %eax
movq $0x0, 0x10(%rsp)
movl %eax, 0x18(%rsp)
testq %rsi, %rsi
leaq 0x10(%rsp), %r14
je 0x1750eec
addq $0x30, %rsi
movq %r14, %rdi
callq 0x91058c
movq %r12, 0x20(%rsp)
movq %r15, %rdi
movq %r14, %rsi
leaq 0x80(%rsp), %rcx
movq %rcx, %rdx
callq 0x17553f9
movq 0x10(%rsp), %rsi
testq %rsi, %rsi
je 0x1750f19
movq %r14, %rdi
callq 0x2a758fc
movl 0x190(%rsp), %r12d
testq %r12, %r12
je 0x1750fb4
movq 0x188(%rsp), %rbx
shlq $0x2, %r12
xorl %r14d, %r14d
movq %r13, %rdi
movl %ebp, %esi
callq 0x961680
movq 0x8(%rax), %rax
movq 0x20(%rax), %rax
movl 0x24(%rax), %r15d
movq %r13, %rdi
movl %r15d, %esi
callq 0x961680
movq 0x8(%rax), %rax
cmpw $0x13, 0x44(%rax)
jne 0x1750f78
movq 0x20(%rax), %rax
movl 0x24(%rax), %r15d
movq %r13, %rdi
movl %r15d, %esi
callq 0x961680
leal -0x1(%r15), %eax
cmpl $0x3ffffffe, %eax # imm = 0x3FFFFFFE
ja 0x1750fa5
movq 0x38(%rsp), %rax
movq 0x398(%rax), %rax
movq 0x280(%rax), %rdi
movl %r15d, %esi
movq $-0x1, %rdx
callq 0x944102
movl %r15d, (%rbx,%r14)
addq $0x4, %r14
incl %ebp
cmpq %r14, %r12
jne 0x1750f39
movq 0x38(%rsp), %rbx
movq 0x340(%rbx), %r15
movq 0x398(%rbx), %r12
movq (%rbx), %rsi
movl 0x330(%rbx), %eax
movq $0x0, 0x10(%rsp)
movl %eax, 0x18(%rsp)
testq %rsi, %rsi
leaq 0x10(%rsp), %r14
je 0x1750ff3
addq $0x30, %rsi
movq %r14, %rdi
callq 0x91058c
movq 0x48(%rsp), %rax
movq %rax, (%rsp)
leaq 0x118(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r14, %rcx
leaq 0x60(%rsp), %r8
xorl %r9d, %r9d
callq 0x1723bd0
movq %rax, %r15
movl %edx, %r12d
movq 0x10(%rsp), %rsi
testq %rsi, %rsi
je 0x17510c4
movq %r14, %rdi
callq 0x2a758fc
jmp 0x17510c4
cmpl $0x5, %eax
jne 0x17510f7
movq %r12, 0x20(%rsp)
xorl %ecx, %ecx
movq %rcx, 0x10(%rsp)
movl $0x0, 0x18(%rsp)
movq (%rbx), %rsi
movl 0x330(%rbx), %eax
movq %rcx, 0x50(%rsp)
movl %eax, 0x58(%rsp)
testq %rsi, %rsi
leaq 0x50(%rsp), %r14
je 0x1751080
addq $0x30, %rsi
movq %r14, %rdi
callq 0x91058c
movq 0x340(%rbx), %r9
movq 0x30(%rsp), %rdi
movq (%rdi), %rax
leaq 0x60(%rsp), %rsi
leaq 0x10(%rsp), %rdx
movq %r14, %rcx
leaq 0x80(%rsp), %r8
callq *0x988(%rax)
movq %rax, %r15
movl %edx, %r12d
movq 0x50(%rsp), %rsi
testq %rsi, %rsi
je 0x17510c2
movq %r14, %rdi
callq 0x2a758fc
incl %ebp
leaq 0x1e8(%rsp), %rdi
movq %r15, %rsi
movl %r12d, %edx
callq 0x9e21b4
movl 0x100(%rsp), %esi
leaq 0x278(%rsp), %rdi
xorl %edx, %edx
callq 0x92dc10
movq 0x20(%rsp), %r12
movq 0x28(%rsp), %r15
movq 0x1a8(%rsp), %rdi
leaq 0x1b8(%rsp), %rax
cmpq %rax, %rdi
je 0x1751111
callq 0x780910
movq 0x188(%rsp), %rdi
leaq 0x198(%rsp), %rax
cmpq %rax, %rdi
je 0x175112b
callq 0x780910
movq 0x168(%rsp), %rdi
leaq 0x180(%rsp), %rax
cmpq %rax, %rdi
je 0x1751145
callq 0x780910
movq 0x118(%rsp), %rdi
leaq 0x128(%rsp), %rax
cmpq %rax, %rdi
je 0x175115f
callq 0x780910
movq 0xd0(%rsp), %rdi
leaq 0xe0(%rsp), %rax
cmpq %rax, %rdi
je 0x1751184
movq 0xe0(%rsp), %rsi
incq %rsi
callq 0x7800d0
leaq 0xb0(%rsp), %rdi
callq 0xafa2e2
leaq 0x90(%rsp), %rdi
callq 0x7fb2c8
addq $0x88, %r12
cmpq %r15, %r12
leaq 0x80(%rsp), %r14
jne 0x1750e69
movq 0x340(%rbx), %r14
movq (%rbx), %rsi
movl 0x330(%rbx), %eax
movq $0x0, 0x80(%rsp)
movl %eax, 0x88(%rsp)
testq %rsi, %rsi
je 0x17511ef
addq $0x30, %rsi
leaq 0x80(%rsp), %rdi
callq 0x91058c
movq 0x340(%rbx), %rdi
movq 0x278(%rsp), %rsi
movl 0x280(%rsp), %edx
callq 0x17859b6
movl %edx, %r8d
movq 0x1e8(%rsp), %rcx
movq %rcx, 0x70(%rsp)
movl 0x1f0(%rsp), %ecx
movq %rcx, 0x78(%rsp)
movups 0x70(%rsp), %xmm0
movups %xmm0, (%rsp)
leaq 0x80(%rsp), %r15
movq %r14, %rdi
movl $0x37, %esi
movq %r15, %rdx
movq %rax, %rcx
callq 0x1785998
movq %rax, %r14
movl %edx, %ebp
movq (%r15), %rsi
testq %rsi, %rsi
je 0x1751264
leaq 0x80(%rsp), %rdi
callq 0x2a758fc
leaq 0x80(%rsp), %rsi
movq 0x40(%rsp), %rax
movq %rax, (%rsi)
addq $0x8, %rbx
movq %rbx, %rdi
callq 0x175b93e
movq %r14, 0x8(%rax)
movl %ebp, 0x10(%rax)
leaq 0x1d0(%rsp), %rdi
callq 0xaf6798
movq 0x1e8(%rsp), %rdi
leaq 0x1f8(%rsp), %rax
cmpq %rax, %rdi
je 0x17512ae
callq 0x780910
movq 0x278(%rsp), %rdi
leaq 0x288(%rsp), %rax
cmpq %rax, %rdi
je 0x17512c8
callq 0x780910
addq $0x308, %rsp # imm = 0x308
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
|
getF32Constant(llvm::SelectionDAG&, unsigned int, llvm::SDLoc const&)
|
static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt,
const SDLoc &dl) {
return DAG.getConstantFP(APFloat(APFloat::IEEEsingle(), APInt(32, Flt)), dl,
MVT::f32);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x30, %rsp
movq %rdx, %rbx
movl %esi, %ebp
movq %rdi, %r14
callq 0x2b061ee
movl %ebp, %ecx
movq %rsp, %r15
movl $0x20, 0x8(%r15)
movq %rcx, (%r15)
leaq 0x18(%rsp), %r12
movq %r12, %rdi
movq %rax, %rsi
movq %r15, %rdx
callq 0x816006
leaq 0x10(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $0xc, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq 0x17656c0
movq %rax, %rbx
movl %edx, %ebp
movq %r12, %rdi
callq 0x81603c
cmpl $0x41, 0x8(%r15)
jb 0x1759cfa
movq (%rsp), %rdi
testq %rdi, %rdi
je 0x1759cfa
callq 0x7802b0
movq %rbx, %rax
movl %ebp, %edx
addq $0x30, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
retq
|
/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
|
bool llvm::DenseMapBase<llvm::DenseMap<llvm::MCSymbol*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>>, llvm::MCSymbol*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>>::LookupBucketFor<llvm::MCSymbol*>(llvm::MCSymbol* const&, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int> const*&) const
|
unsigned getNumBuckets() const {
return NumBuckets;
}
|
movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x175aac3
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movq (%rdi,%rbx), %rbx
cmpq %rbx, (%rsi)
jne 0x175aa8a
movq %r11, (%rdx)
movb $0x1, %al
xorl %r11d, %r11d
testb %r11b, %r11b
jne 0x175aa67
jmp 0x175aac0
cmpq $-0x1000, %rbx # imm = 0xF000
jne 0x175aaa4
testq %r9, %r9
cmovneq %r9, %r11
movq %r11, (%rdx)
xorl %r11d, %r11d
xorl %eax, %eax
jmp 0x175aa83
xorq $-0x2000, %rbx # imm = 0xE000
orq %r9, %rbx
cmoveq %r11, %r9
addl %r10d, %r8d
incl %r10d
andl %ecx, %r8d
movb $0x1, %r11b
jmp 0x175aa83
popq %rbx
jmp 0x175aacc
movq $0x0, (%rdx)
xorl %eax, %eax
andb $0x1, %al
retq
nop
|
/llvm/ADT/DenseMap.h
|
llvm::DenseMapBase<llvm::DenseMap<llvm::MCSymbol*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>>, llvm::MCSymbol*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>>::moveFromOldBuckets(llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>*, llvm::detail::DenseMapPair<llvm::MCSymbol*, unsigned int>*)
|
void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqual(B->getFirst(), EmptyKey) &&
!KeyInfoT::isEqual(B->getFirst(), TombstoneKey)) {
// Insert the key/value into the new table.
BucketT *DestBucket;
bool FoundVal = LookupBucketFor(B->getFirst(), DestBucket);
(void)FoundVal; // silence warning.
assert(!FoundVal && "Key already in new map?");
DestBucket->getFirst() = std::move(B->getFirst());
::new (&DestBucket->getSecond()) ValueT(std::move(B->getSecond()));
incrementNumEntries();
// Free the value.
B->getSecond().~ValueT();
}
B->getFirst().~KeyT();
}
}
|
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0x175ad65
movq (%r15), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x1, %ecx
negq %rcx
addq %rdx, %rcx
addq $0x2, %rcx
movq %rdx, %xmm0
pshufd $0x44, %xmm0, %xmm0 # xmm0 = xmm0[0,1,0,1]
addq $0x10, %rax
xorl %edx, %edx
movdqa 0x145a332(%rip), %xmm1 # 0x2bb5020
movdqa 0x145a33a(%rip), %xmm2 # 0x2bb5030
pxor %xmm2, %xmm0
pcmpeqd %xmm3, %xmm3
movq %rdx, %xmm4
pshufd $0x44, %xmm4, %xmm4 # xmm4 = xmm4[0,1,0,1]
por %xmm1, %xmm4
pxor %xmm2, %xmm4
movdqa %xmm4, %xmm5
pcmpgtd %xmm0, %xmm5
pcmpeqd %xmm0, %xmm4
pshufd $0xf5, %xmm4, %xmm6 # xmm6 = xmm4[1,1,3,3]
pand %xmm5, %xmm6
pshufd $0xf5, %xmm5, %xmm4 # xmm4 = xmm5[1,1,3,3]
por %xmm6, %xmm4
movd %xmm4, %esi
notl %esi
testb $0x1, %sil
je 0x175ad42
movq $-0x1000, -0x10(%rax) # imm = 0xF000
pxor %xmm3, %xmm4
pextrw $0x4, %xmm4, %esi
testb $0x1, %sil
je 0x175ad58
movq $-0x1000, (%rax) # imm = 0xF000
addq $0x2, %rdx
addq $0x20, %rax
cmpq %rdx, %rcx
jne 0x175acfe
cmpq %rbx, %r14
je 0x175adb0
movl $0x1000, %r13d # imm = 0x1000
leaq 0x8(%rsp), %r12
movq (%r14), %rax
orq %r13, %rax
cmpq $-0x1000, %rax # imm = 0xF000
je 0x175ada7
movq %r15, %rdi
movq %r14, %rsi
movq %r12, %rdx
callq 0x175aa3e
movq 0x8(%rsp), %rax
movq (%r14), %rcx
movq %rcx, (%rax)
movl 0x8(%r14), %ecx
movl %ecx, 0x8(%rax)
incl 0x8(%r15)
addq $0x10, %r14
cmpq %rbx, %r14
jne 0x175ad75
addq $0x10, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
retq
|
/llvm/ADT/DenseMap.h
|
llvm::ISD::isConstantSplatVectorAllOnes(llvm::SDNode const*, bool)
|
bool ISD::isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly) {
// Look through a bit convert.
while (N->getOpcode() == ISD::BITCAST)
N = N->getOperand(0).getNode();
if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) {
APInt SplatVal;
return isConstantSplatVector(N, SplatVal) && SplatVal.isAllOnes();
}
if (N->getOpcode() != ISD::BUILD_VECTOR) return false;
unsigned i = 0, e = N->getNumOperands();
// Skip over all of the undef values.
while (i != e && N->getOperand(i).isUndef())
++i;
// Do not accept an all-undef vector.
if (i == e) return false;
// Do not accept build_vectors that aren't all constants or which have non-~0
// elements. We have to be a bit careful here, as the type of the constant
// may not be the same as the type of the vector elements due to type
// legalization (the elements are promoted to a legal type for the target and
// a vector of a type may be legal when the base element type is not).
// We only want to check enough bits to cover the vector elements, because
// we care if the resultant vector is all ones, not whether the individual
// constants are.
SDValue NotZero = N->getOperand(i);
unsigned EltSize = N->getValueType(0).getScalarSizeInBits();
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(NotZero)) {
if (CN->getAPIntValue().countr_one() < EltSize)
return false;
} else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(NotZero)) {
if (CFPN->getValueAPF().bitcastToAPInt().countr_one() < EltSize)
return false;
} else
return false;
// Okay, we have at least one ~0 value, check to see if the rest match or are
// undefs. Even with the above element type twiddling, this should be OK, as
// the same type legalization should have applied to all the elements.
for (++i; i != e; ++i)
if (N->getOperand(i) != NotZero && !N->getOperand(i).isUndef())
return false;
return true;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movl 0x18(%rdi), %eax
cmpl $0xe6, %eax
jne 0x1760401
movq 0x28(%rbx), %rax
movq (%rax), %rbx
movl 0x18(%rbx), %eax
jmp 0x17603ee
cmpl $0xa7, %eax
setne %cl
orb %sil, %cl
je 0x17604b0
cmpl $0x9b, %eax
jne 0x17605a7
movzwl 0x40(%rbx), %r12d
xorl %r13d, %r13d
testl %r12d, %r12d
sete %cl
je 0x17605a7
movq 0x28(%rbx), %rax
movq (%rax), %rdx
cmpl $0x33, 0x18(%rdx)
jne 0x1760466
addq $0x28, %rax
leal -0x1(%r12), %edx
xorl %r13d, %r13d
cmpl %r13d, %edx
sete %cl
je 0x17605a7
movq (%rax), %rsi
addq $0x28, %rax
incl %r13d
cmpl $0x33, 0x18(%rsi)
je 0x176044a
testb %cl, %cl
jne 0x17605a7
movq 0x28(%rbx), %rax
movl %r13d, %ecx
leaq (%rcx,%rcx,4), %rcx
movq (%rax,%rcx,8), %r15
movl 0x8(%rax,%rcx,8), %r14d
movq 0x30(%rbx), %rax
movb (%rax), %cl
movq 0x8(%rax), %rax
movq %rsp, %rdi
movb %cl, (%rdi)
movq %rax, 0x8(%rdi)
callq 0x9254d2
movq %rax, %rbp
movl 0x18(%r15), %eax
cmpl $0x23, %eax
je 0x17604ab
cmpl $0xb, %eax
jne 0x17604fd
movq %r15, %rcx
jmp 0x17604ff
movq %rsp, %rsi
movl $0x1, 0x8(%rsi)
movq $0x0, (%rsi)
movq %rbx, %rdi
callq 0x175fa88
testb %al, %al
je 0x17604d9
movq %rsp, %rdi
callq 0x9e1c5c
movl %eax, %ebp
jmp 0x17604db
xorl %ebp, %ebp
cmpl $0x41, 0x8(%rsp)
jb 0x17605a9
movq (%rsp), %rdi
testq %rdi, %rdi
je 0x17605a9
callq 0x7802b0
jmp 0x17605a9
xorl %ecx, %ecx
testq %rcx, %rcx
je 0x1760521
movq 0x58(%rcx), %rax
leaq 0x18(%rax), %rdi
cmpl $0x40, 0x20(%rax)
ja 0x1760530
movq (%rdi), %rax
xorq $-0x1, %rax
je 0x176056e
bsfq %rax, %rax
jmp 0x1760573
cmpl $0x24, %eax
je 0x176052b
cmpl $0xc, %eax
jne 0x1760537
movq %r15, %rax
jmp 0x1760539
callq 0x2b129ac
jmp 0x1760573
xorl %eax, %eax
testq %rax, %rax
je 0x17605a7
movq %rbp, 0x10(%rsp)
movq 0x58(%rax), %rsi
addq $0x18, %rsi
movq %rsp, %rbp
movq %rbp, %rdi
callq 0x815f90
movl 0x8(%rbp), %ebp
cmpl $0x40, %ebp
ja 0x1760579
movq (%rsp), %rax
xorq $-0x1, %rax
je 0x1760583
bsfq %rax, %rax
jmp 0x1760588
movl $0x40, %eax
cmpl %ebp, %eax
jb 0x17605a7
jmp 0x17605ba
movq %rsp, %rdi
callq 0x2b129ac
jmp 0x1760588
movl $0x40, %eax
cmpl $0x41, %ebp
jb 0x17605a1
movq (%rsp), %rdi
testq %rdi, %rdi
je 0x17605a1
movq %rax, %rbp
callq 0x7802b0
movq %rbp, %rax
cmpl 0x10(%rsp), %eax
jae 0x17605ba
xorl %ebp, %ebp
movl %ebp, %eax
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
incl %r13d
movb $0x1, %bpl
cmpl %r12d, %r13d
je 0x17605a9
movq 0x28(%rbx), %rax
movl %r13d, %ecx
leaq (%rcx,%rcx,4), %rdx
movq (%rax,%rdx,8), %rcx
cmpq %r15, %rcx
jne 0x17605e0
cmpl %r14d, 0x8(%rax,%rdx,8)
je 0x17605e6
cmpl $0x33, 0x18(%rcx)
jne 0x17605a7
incl %r13d
cmpl %r13d, %r12d
jne 0x17605c9
jmp 0x17605a9
|
/CodeGen/SelectionDAG/SelectionDAG.cpp
|
llvm::ISD::getExtForLoadExtType(bool, llvm::ISD::LoadExtType)
|
ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) {
switch (ExtType) {
case ISD::EXTLOAD:
return IsFP ? ISD::FP_EXTEND : ISD::ANY_EXTEND;
case ISD::SEXTLOAD:
return ISD::SIGN_EXTEND;
case ISD::ZEXTLOAD:
return ISD::ZERO_EXTEND;
default:
break;
}
llvm_unreachable("Invalid LoadExtType");
}
|
cmpl $0x3, %esi
je 0x1761593
movl $0xd4, %eax
cmpl $0x2, %esi
je 0x1761598
testb %dil, %dil
movl $0xe5, %ecx
movl $0xd6, %eax
cmovnel %ecx, %eax
retq
movl $0xd5, %eax
retq
|
/CodeGen/SelectionDAG/SelectionDAG.cpp
|
llvm::SelectionDAG::FindModifiedNodeSlot(llvm::SDNode*, llvm::ArrayRef<llvm::SDValue>, void*&)
|
SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N, ArrayRef<SDValue> Ops,
void *&InsertPos) {
if (doNotCSE(N))
return nullptr;
FoldingSetNodeID ID;
AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops);
AddNodeIDCustom(ID, N);
SDNode *Node = FindNodeOrInsertPos(ID, SDLoc(N), InsertPos);
if (Node)
Node->intersectFlagsWith(N->getFlags());
return Node;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %r8, %r14
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %rbx
movq %rdi, %r15
movq %rsi, %rdi
callq 0x1762103
testb %al, %al
je 0x1762a66
xorl %r14d, %r14d
jmp 0x1762b1b
leaq 0x28(%rsp), %rcx
movq %rcx, -0x10(%rcx)
movabsq $0x2000000000, %rax # imm = 0x2000000000
movq %rax, -0x8(%rcx)
movl 0x18(%rbx), %esi
movq 0x30(%rbx), %rdx
leaq 0x18(%rsp), %rbp
movq %rbp, %rdi
movq %r13, %rcx
movq %r12, %r8
callq 0x1762410
movq %rbp, %rdi
movq %rbx, %rsi
callq 0x176248d
movq 0x48(%rbx), %rsi
movq %rsi, 0x8(%rsp)
testq %rsi, %rsi
je 0x1762abf
leaq 0x8(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbx), %eax
leaq 0x8(%rsp), %r12
movl %eax, 0x8(%r12)
leaq 0x18(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movq %r14, %rcx
callq 0x176285c
movq %rax, %r14
movq (%r12), %rsi
testq %rsi, %rsi
je 0x1762af5
leaq 0x8(%rsp), %rdi
callq 0x2a758fc
testq %r14, %r14
je 0x1762b07
movl $0xc000, %eax # imm = 0xC000
orl 0x1c(%rbx), %eax
andw %ax, 0x1c(%r14)
movq 0x18(%rsp), %rdi
leaq 0x28(%rsp), %rax
cmpq %rax, %rdi
je 0x1762b1b
callq 0x780910
movq %r14, %rax
addq $0xa8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/CodeGen/SelectionDAG/SelectionDAG.cpp
|
llvm::SelectionDAG::getVPZeroExtendInReg(llvm::SDValue, llvm::SDValue, llvm::SDValue, llvm::SDLoc const&, llvm::EVT)
|
SDValue SelectionDAG::getVPZeroExtendInReg(SDValue Op, SDValue Mask,
SDValue EVL, const SDLoc &DL,
EVT VT) {
EVT OpVT = Op.getValueType();
assert(VT.isInteger() && OpVT.isInteger() &&
"Cannot getVPZeroExtendInReg FP types");
assert(VT.isVector() && OpVT.isVector() &&
"getVPZeroExtendInReg type and operand type should be vector!");
assert(VT.getVectorElementCount() == OpVT.getVectorElementCount() &&
"Vector element counts must match in getZeroExtendInReg");
assert(VT.bitsLE(OpVT) && "Not extending!");
if (OpVT == VT)
return Op;
APInt Imm = APInt::getLowBitsSet(OpVT.getScalarSizeInBits(),
VT.getScalarSizeInBits());
return getNode(ISD::VP_AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT), Mask,
EVL);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %r9, %r13
movl %edx, %ebp
movq %rsi, %r14
leaq 0xf0(%rsp), %rbx
movq 0x30(%rsi), %rax
movl %edx, %edx
shlq $0x4, %rdx
movb (%rax,%rdx), %sil
movq 0x8(%rax,%rdx), %rax
movb %sil, 0x30(%rsp)
movq %rax, 0x38(%rsp)
cmpb (%rbx), %sil
jne 0x1764384
testb %sil, %sil
jne 0x17644a1
cmpq 0x8(%rbx), %rax
je 0x17644a1
leaq 0x30(%rsp), %rax
movq %rdi, %r15
movq %rax, %rdi
movl %r8d, 0x1c(%rsp)
movq %rcx, 0x20(%rsp)
callq 0x9254d2
movq %rax, %r12
movq %rbx, %rdi
callq 0x9254d2
movq %rax, %rbx
movq %r13, 0x28(%rsp)
leaq 0x40(%rsp), %r13
movq %r13, %rdi
movl %r12d, %esi
xorl %edx, %edx
xorl %ecx, %ecx
callq 0x91d2c6
movq %r13, %rdi
xorl %esi, %esi
movl %ebx, %edx
callq 0x95b8c2
leaq 0x30(%rsp), %rax
movb (%rax), %bl
movq 0x8(%rax), %r12
movq 0x40(%r15), %rdi
movq %r13, %rsi
movq 0x28(%rsp), %r13
callq 0x29e1b4c
movl $0x0, (%rsp)
movzbl %bl, %ebx
movq %r15, %rdi
movq %rax, %rsi
movq %r13, %rdx
movl %ebx, %ecx
movq %r12, %r8
xorl %r9d, %r9d
callq 0x1764b20
leaq 0x60(%rsp), %rcx
movq %r14, (%rcx)
movl %ebp, 0x8(%rcx)
movq %rax, 0x10(%rcx)
movl %edx, 0x18(%rcx)
movq 0x20(%rsp), %rax
movq %rax, 0x20(%rcx)
movl 0x1c(%rsp), %eax
movl %eax, 0x28(%rcx)
leaq 0xe0(%rsp), %rdx
movq (%rdx), %rax
movq %rax, 0x30(%rcx)
movl 0x8(%rdx), %eax
movl %eax, 0x38(%rcx)
movq %rcx, 0x50(%rsp)
movq $0x4, 0x58(%rsp)
movq 0x378(%r15), %rax
testq %rax, %rax
je 0x1764465
movzwl 0x8(%rax), %r9d
jmp 0x1764468
xorl %r9d, %r9d
movups 0x50(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r15, %rdi
movl $0x17e, %esi # imm = 0x17E
movq %r13, %rdx
movl %ebx, %ecx
movq %r12, %r8
callq 0x177d0f6
movq %rax, %r14
movl %edx, %ebp
cmpl $0x41, 0x48(%rsp)
jb 0x17644a1
movq 0x40(%rsp), %rdi
testq %rdi, %rdi
je 0x17644a1
callq 0x7802b0
movq %r14, %rax
movl %ebp, %edx
addq $0xa8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/CodeGen/SelectionDAG/SelectionDAG.cpp
|
llvm::JumpTableSDNode* llvm::SelectionDAG::newSDNode<llvm::JumpTableSDNode, int&, llvm::SDVTList&, bool&, unsigned int&>(int&, llvm::SDVTList&, bool&, unsigned int&)
|
SDNodeT *newSDNode(ArgTypes &&... Args) {
return new (NodeAllocator.template Allocate<SDNodeT>())
SDNodeT(std::forward<ArgTypes>(Args)...);
}
|
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r13
movq 0x160(%rdi), %r12
testq %r12, %r12
je 0x176607e
movq (%r12), %rax
movq %rax, 0x160(%rdi)
jmp 0x1766097
addq $0x168, %rdi # imm = 0x168
movl $0x70, %esi
movl $0x3, %edx
callq 0x8f284c
movq %rax, %r12
movl (%r13), %esi
movq (%r15), %rdx
movl 0x8(%r15), %ecx
movzbl (%r14), %r8d
movl (%rbx), %r9d
movq %r12, %rdi
callq 0x179808e
movq %r12, %rax
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
retq
|
/llvm/CodeGen/SelectionDAG.h
|
llvm::isBitwiseNot(llvm::SDValue, bool)
|
bool llvm::isBitwiseNot(SDValue V, bool AllowUndefs) {
if (V.getOpcode() != ISD::XOR)
return false;
V = peekThroughBitcasts(V.getOperand(1));
unsigned NumBits = V.getScalarValueSizeInBits();
ConstantSDNode *C =
isConstOrConstSplat(V, AllowUndefs, /*AllowTruncation*/ true);
return C && (C->getAPIntValue().countr_one() >= NumBits);
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rdi, (%rsp)
movl %esi, 0x8(%rsp)
cmpl $0xbb, 0x18(%rdi)
jne 0x1778965
movl %edx, %ebp
movq 0x28(%rdi), %rcx
movq 0x28(%rcx), %rax
cmpl $0xe6, 0x18(%rax)
jne 0x1778913
movq 0x28(%rax), %rcx
movq (%rcx), %rax
cmpl $0xe6, 0x18(%rax)
je 0x17788fd
addq $0x8, %rcx
jmp 0x1778917
addq $0x30, %rcx
movl (%rcx), %ecx
movq %rsp, %r14
movq %rax, (%r14)
movl %ecx, 0x8(%r14)
movq %r14, %rdi
callq 0x9e1bc2
movq %rax, %rbx
movq (%r14), %rdi
movl 0x8(%r14), %esi
movzbl %bpl, %edx
movl $0x1, %ecx
callq 0x1776f70
testq %rax, %rax
je 0x1778965
movq 0x58(%rax), %rax
leaq 0x18(%rax), %rdi
cmpl $0x40, 0x20(%rax)
ja 0x1778969
movq (%rdi), %rax
xorq $-0x1, %rax
je 0x1778970
bsfq %rax, %rax
jmp 0x1778975
xorl %eax, %eax
jmp 0x177897a
callq 0x2b129ac
jmp 0x1778975
movl $0x40, %eax
cmpl %ebx, %eax
setae %al
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
|
/CodeGen/SelectionDAG/SelectionDAG.cpp
|
llvm::APIntOps::abdu(llvm::APInt const&, llvm::APInt const&)
|
inline const APInt abdu(const APInt &A, const APInt &B) {
return A.uge(B) ? (A - B) : (B - A);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x20, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq %rsi, %rdi
movq %rdx, %rsi
callq 0x2b11ae2
movl %eax, %ebp
testl %eax, %eax
js 0x1796231
movl 0x8(%r15), %eax
movl %eax, 0x18(%rsp)
cmpl $0x40, %eax
ja 0x1796247
movq (%r15), %rax
movq %rax, 0x10(%rsp)
jmp 0x1796254
movl 0x8(%r14), %eax
movl %eax, 0x8(%rsp)
cmpl $0x40, %eax
ja 0x1796261
movq (%r14), %rax
movq %rax, (%rsp)
jmp 0x179626c
leaq 0x10(%rsp), %rdi
movq %r15, %rsi
callq 0x2b11114
leaq 0x10(%rsp), %r12
movq %r12, %rdi
movq %r14, %rsi
jmp 0x1796275
movq %rsp, %rdi
movq %r14, %rsi
callq 0x2b11114
movq %rsp, %r12
movq %r12, %rdi
movq %r15, %rsi
callq 0x2b11694
movl 0x8(%r12), %eax
movl %eax, 0x8(%rbx)
movq (%r12), %rax
movq %rax, (%rbx)
movl $0x0, 0x8(%r12)
testl %ebp, %ebp
js 0x17962a5
cmpl $0x41, 0x18(%rsp)
setb %al
movq 0x10(%rsp), %rdi
jmp 0x17962b1
cmpl $0x41, 0x8(%rsp)
setb %al
movq (%rsp), %rdi
testq %rdi, %rdi
sete %cl
orb %al, %cl
jne 0x17962c0
callq 0x7802b0
movq %rbx, %rax
addq $0x20, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
retq
|
/llvm/ADT/APInt.h
|
llvm::DenseMap<llvm::SDNode const*, llvm::SelectionDAG::NodeExtraInfo, llvm::DenseMapInfo<llvm::SDNode const*, void>, llvm::detail::DenseMapPair<llvm::SDNode const*, llvm::SelectionDAG::NodeExtraInfo>>::init(unsigned int)
|
void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
}
|
pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0x1797a22
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ebp
shrl $0x10, %ebp
orl %eax, %ebp
incl %ebp
jmp 0x1797a24
xorl %ebp, %ebp
movl %ebp, 0x10(%rbx)
testl %ebp, %ebp
je 0x1797a3d
movl %ebp, %edi
shlq $0x6, %rdi
movl $0x8, %esi
callq 0x2b410ec
jmp 0x1797a3f
xorl %eax, %eax
movq %rax, (%rbx)
movq $0x0, 0x8(%rbx)
testl %ebp, %ebp
je 0x1797b0a
movl 0x10(%rbx), %ecx
testq %rcx, %rcx
je 0x1797b0a
movabsq $0x3ffffffffffffff, %rdx # imm = 0x3FFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x1, %ecx
negq %rcx
addq %rdx, %rcx
addq $0x2, %rcx
movq %rdx, %xmm0
pshufd $0x44, %xmm0, %xmm0 # xmm0 = xmm0[0,1,0,1]
addq $0x40, %rax
xorl %edx, %edx
movdqa 0x141d58d(%rip), %xmm1 # 0x2bb5020
movdqa 0x141d595(%rip), %xmm2 # 0x2bb5030
pxor %xmm2, %xmm0
pcmpeqd %xmm3, %xmm3
movq %rdx, %xmm4
pshufd $0x44, %xmm4, %xmm4 # xmm4 = xmm4[0,1,0,1]
por %xmm1, %xmm4
pxor %xmm2, %xmm4
movdqa %xmm4, %xmm5
pcmpgtd %xmm0, %xmm5
pcmpeqd %xmm0, %xmm4
pshufd $0xf5, %xmm4, %xmm6 # xmm6 = xmm4[1,1,3,3]
pand %xmm5, %xmm6
pshufd $0xf5, %xmm5, %xmm4 # xmm4 = xmm5[1,1,3,3]
por %xmm6, %xmm4
movd %xmm4, %esi
notl %esi
testb $0x1, %sil
je 0x1797ae7
movq $-0x1000, -0x40(%rax) # imm = 0xF000
pxor %xmm3, %xmm4
pextrw $0x4, %xmm4, %esi
testb $0x1, %sil
je 0x1797afd
movq $-0x1000, (%rax) # imm = 0xF000
addq $0x2, %rdx
subq $-0x80, %rax
cmpq %rdx, %rcx
jne 0x1797aa3
addq $0x8, %rsp
popq %rbx
popq %rbp
retq
nop
|
/llvm/ADT/DenseMap.h
|
llvm::SmallVectorTemplateBase<(anonymous namespace)::MatchScope, false>::grow(unsigned long)
|
void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %rsi
movl $0x88, %r13d
leaq 0x10(%rsp), %r8
movl $0x88, %ecx
movq %rsi, 0x8(%rsp)
callq 0x2b4ec3c
movq %rax, (%rsp)
movl 0x8(%rbx), %eax
testq %rax, %rax
je 0x17ac563
movq (%rbx), %r12
movq %rax, %rcx
shlq $0x7, %rcx
leaq (%rcx,%rax,8), %rbp
addq %r12, %rbp
addq $0x8, %r12
movabsq $0x400000000, %r15 # imm = 0x400000000
movq (%rsp), %r14
movl -0x8(%r12), %eax
movl %eax, (%r14)
leaq 0x18(%r14), %rax
movq %rax, 0x8(%r14)
movq %r15, 0x10(%r14)
cmpl $0x0, 0x8(%r12)
je 0x17ac535
leaq 0x8(%r14), %rdi
movq %r12, %rsi
callq 0x16f7800
leaq -0x8(%r12), %rax
movups 0x58(%rax), %xmm0
movups 0x68(%rax), %xmm1
movups 0x71(%rax), %xmm2
movups %xmm2, 0x71(%r14)
movups %xmm1, 0x68(%r14)
movups %xmm0, 0x58(%r14)
addq %r13, %r14
addq %r13, %r12
addq %r13, %rax
cmpq %rbp, %rax
jne 0x17ac50d
movl 0x8(%rbx), %eax
testq %rax, %rax
je 0x17ac599
movq (%rbx), %r14
leaq -0x70(%r14), %r15
movq %rax, %rcx
shlq $0x7, %rcx
leaq (%rcx,%rax,8), %r12
movq -0x80(%r14,%r12), %rdi
leaq (%r15,%r12), %rax
cmpq %rdi, %rax
je 0x17ac590
callq 0x780910
addq $-0x88, %r12
jne 0x17ac57d
movq 0x10(%rsp), %r14
movq (%rbx), %rdi
cmpq 0x8(%rsp), %rdi
je 0x17ac5ad
callq 0x780910
movq (%rsp), %rax
movq %rax, (%rbx)
movl %r14d, 0xc(%rbx)
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/llvm/ADT/SmallVector.h
|
llvm::StatepointLoweringState::getLocation(llvm::SDValue)
|
SDValue getLocation(SDValue Val) {
auto I = Locations.find(Val);
if (I == Locations.end())
return SDValue();
return I->second;
}
|
pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
movq %rsp, %rax
movq %rsi, (%rax)
movl %edx, 0x8(%rax)
movq %rax, %rsi
callq 0x17b06ca
movl 0x10(%rbx), %ecx
shlq $0x5, %rcx
addq (%rbx), %rcx
cmpq %rcx, %rax
je 0x17ae47f
movq 0x10(%rax), %rcx
movl 0x18(%rax), %edx
jmp 0x17ae483
xorl %edx, %edx
xorl %ecx, %ecx
movq %rcx, %rax
addq $0x10, %rsp
popq %rbx
retq
|
/CodeGen/SelectionDAG/StatepointLowering.h
|
llvm::TargetLowering::getConstraintPreferences(llvm::TargetLowering::AsmOperandInfo&) const
|
TargetLowering::ConstraintGroup TargetLowering::getConstraintPreferences(
TargetLowering::AsmOperandInfo &OpInfo) const {
ConstraintGroup Ret;
Ret.reserve(OpInfo.Codes.size());
for (StringRef Code : OpInfo.Codes) {
TargetLowering::ConstraintType CType = getConstraintType(Code);
// Indirect 'other' or 'immediate' constraints are not allowed.
if (OpInfo.isIndirect && !(CType == TargetLowering::C_Memory ||
CType == TargetLowering::C_Register ||
CType == TargetLowering::C_RegisterClass))
continue;
// Things with matching constraints can only be registers, per gcc
// documentation. This mainly affects "g" constraints.
if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
continue;
Ret.emplace_back(Code, CType);
}
std::stable_sort(
Ret.begin(), Ret.end(), [](ConstraintPair a, ConstraintPair b) {
return getConstraintPiority(a.second) > getConstraintPiority(b.second);
});
return Ret;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
leaq 0x10(%rdi), %rsi
movq %rsi, (%rdi)
movabsq $0x200000000, %rax # imm = 0x200000000
movq %rax, 0x8(%rdi)
movq 0x18(%rdx), %rdx
subq 0x10(%r14), %rdx
sarq $0x5, %rdx
cmpq $0x3, %rdx
jb 0x17ce9f7
movl $0x18, %ecx
movq %rbx, %rdi
callq 0x2b4ed86
movq 0x10(%r14), %rbp
movq 0x18(%r14), %r12
cmpq %r12, %rbp
je 0x17cea5c
leaq 0xc(%rsp), %r13
movq (%rbp), %rsi
movq %rsi, 0x10(%rsp)
movq 0x8(%rbp), %rdx
movq %rdx, 0x18(%rsp)
movq (%r15), %rax
movq %r15, %rdi
callq *0x960(%rax)
movl %eax, 0xc(%rsp)
cmpl $0x3, %eax
jb 0x17cea37
cmpb $0x0, 0xd(%r14)
jne 0x17cea53
cmpl $0x2, %eax
jne 0x17cea43
cmpl $-0x1, 0x8(%r14)
jne 0x17cea53
movq %rbx, %rdi
leaq 0x10(%rsp), %rsi
movq %r13, %rdx
callq 0x17cead6
addq $0x20, %rbp
cmpq %r12, %rbp
jne 0x17cea09
movl 0x8(%rbx), %edx
testq %rdx, %rdx
je 0x17ceac3
movq (%rbx), %r14
leaq (%rdx,%rdx,2), %rax
leaq (%r14,%rax,8), %r15
incq %rdx
shrq %rdx
leaq 0x10(%rsp), %r12
movq %r12, %rdi
movq %r14, %rsi
callq 0x17f5816
movq 0x10(%r12), %rdx
testq %rdx, %rdx
je 0x17ceaa1
movq 0x18(%rsp), %rcx
movq %r14, %rdi
movq %r15, %rsi
callq 0x17f5929
jmp 0x17ceaac
movq %r14, %rdi
movq %r15, %rsi
callq 0x17f589c
movq 0x18(%rsp), %rax
movq 0x20(%rsp), %rdi
shlq $0x3, %rax
leaq (%rax,%rax,2), %rsi
callq 0x7800d0
movq %rbx, %rax
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/CodeGen/SelectionDAG/TargetLowering.cpp
|
llvm::DAGTypeLegalizer::SetPromotedInteger(llvm::SDValue, llvm::SDValue)
|
void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
assert(Result.getValueType() ==
TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
"Invalid type for promoted integer");
AnalyzeNewValue(Result);
auto &OpIdEntry = PromotedIntegers[getTableId(Op)];
assert((OpIdEntry == 0) && "Node is already promoted!");
OpIdEntry = getTableId(Result);
DAG.transferDbgValues(Op, Result);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leaq 0x8(%rsp), %r12
movq %rcx, (%r12)
movl %r8d, 0x8(%r12)
movq %r12, %rsi
callq 0x17f86d0
leaq 0x270(%r15), %r13
movq %r15, %rdi
movq %r14, %rsi
movl %ebx, %edx
callq 0x17f875c
leaq 0x4(%rsp), %rsi
movl %eax, (%rsi)
movq %r13, %rdi
callq 0x17fb5ec
movq %rax, %r13
movq (%r12), %rbp
movl 0x8(%r12), %r12d
movq %r15, %rdi
movq %rbp, %rsi
movl %r12d, %edx
callq 0x17f875c
movl %eax, 0x4(%r13)
movq 0x8(%r15), %rdi
movq %r14, %rsi
movl %ebx, %edx
movq %rbp, %rcx
movl %r12d, %r8d
xorl %r9d, %r9d
pushq $0x1
pushq $0x0
callq 0x177badc
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/CodeGen/SelectionDAG/LegalizeTypes.cpp
|
llvm::DenseMapBase<llvm::SmallDenseMap<unsigned int, llvm::SDValue, 8u, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::SDValue>>, unsigned int, llvm::SDValue, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::SDValue>>::find(unsigned int const&)
|
iterator find(const_arg_type_t<KeyT> Val) {
BucketT *TheBucket;
if (LookupBucketFor(Val, TheBucket))
return makeIterator(TheBucket,
shouldReverseIterate<KeyT>() ? getBuckets()
: getBucketsEnd(),
*this, true);
return end();
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq %rsp, %r14
movq %r14, %rdx
callq 0x17fa20e
testb $0x1, (%rbx)
leaq 0x8(%rbx), %rcx
cmoveq 0x8(%rbx), %rcx
movl $0x8, %edx
cmovel 0x10(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
leaq (%rcx,%rdx,8), %rdx
testb %al, %al
movq (%r14), %rax
cmoveq %rdx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
|
/llvm/ADT/DenseMap.h
|
llvm::DAGTypeLegalizer::ScalarizeVecRes_ExpOp(llvm::SDNode*)
|
SDValue DAGTypeLegalizer::ScalarizeVecRes_ExpOp(SDNode *N) {
SDValue Op = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op,
N->getOperand(1));
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movq (%rax), %rsi
movl 0x8(%rax), %edx
callq 0x180aea0
movq %rax, %r15
movl %edx, %r12d
movq 0x8(%r14), %r14
movl 0x18(%rbx), %ebp
movq 0x48(%rbx), %rsi
movq %rsi, 0x28(%rsp)
testq %rsi, %rsi
je 0x18081d5
leaq 0x28(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbx), %eax
leaq 0x28(%rsp), %r13
movl %eax, 0x8(%r13)
movq 0x30(%r15), %rax
movl %r12d, %ecx
shlq $0x4, %rcx
movq 0x8(%rax,%rcx), %r8
movl (%rax,%rcx), %ecx
movq %r15, 0x38(%rsp)
movl %r12d, 0x40(%rsp)
movq 0x28(%rbx), %rax
movups 0x28(%rax), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x38(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r14, %rdi
movl %ebp, %esi
movq %r13, %rdx
callq 0x17638a8
movq %rax, %rbx
movl %edx, %ebp
movq (%r13), %rsi
testq %rsi, %rsi
je 0x1808239
leaq 0x28(%rsp), %rdi
callq 0x2a758fc
movq %rbx, %rax
movl %ebp, %edx
addq $0x48, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
|
llvm::DAGTypeLegalizer::ScalarizeVecRes_VSELECT(llvm::SDNode*)
|
SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
SDValue Cond = N->getOperand(0);
EVT OpVT = Cond.getValueType();
SDLoc DL(N);
// The vselect result and true/value operands needs scalarizing, but it's
// not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
// See the similar logic in ScalarizeVecRes_SETCC
if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
Cond = GetScalarizedVector(Cond);
} else {
EVT VT = OpVT.getVectorElementType();
Cond = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond,
DAG.getVectorIdxConstant(0, DL));
}
SDValue LHS = GetScalarizedVector(N->getOperand(1));
TargetLowering::BooleanContent ScalarBool =
TLI.getBooleanContents(false, false);
TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
// If integer and float booleans have different contents then we can't
// reliably optimize in all cases. There is a full explanation for this in
// DAGCombiner::visitSELECT() where the same issue affects folding
// (select C, 0, 1) to (xor C, 1).
if (TLI.getBooleanContents(false, false) !=
TLI.getBooleanContents(false, true)) {
// At least try the common case where the boolean is generated by a
// comparison.
if (Cond->getOpcode() == ISD::SETCC) {
EVT OpVT = Cond->getOperand(0).getValueType();
ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
VecBool = TLI.getBooleanContents(OpVT);
} else
ScalarBool = TargetLowering::UndefinedBooleanContent;
}
EVT CondVT = Cond.getValueType();
if (ScalarBool != VecBool) {
switch (ScalarBool) {
case TargetLowering::UndefinedBooleanContent:
break;
case TargetLowering::ZeroOrOneBooleanContent:
assert(VecBool == TargetLowering::UndefinedBooleanContent ||
VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
// Vector read from all ones, scalar expects a single 1 so mask.
Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
Cond, DAG.getConstant(1, SDLoc(N), CondVT));
break;
case TargetLowering::ZeroOrNegativeOneBooleanContent:
assert(VecBool == TargetLowering::UndefinedBooleanContent ||
VecBool == TargetLowering::ZeroOrOneBooleanContent);
// Vector reads from a one, scalar from all ones so sign extend.
Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
Cond, DAG.getValueType(MVT::i1));
break;
}
}
// Truncate the condition if needed
auto BoolVT = getSetCCResultType(CondVT);
if (BoolVT.bitsLT(CondVT))
Cond = DAG.getNode(ISD::TRUNCATE, SDLoc(N), BoolVT, Cond);
return DAG.getSelect(SDLoc(N),
LHS.getValueType(), Cond, LHS,
GetScalarizedVector(N->getOperand(2)));
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x128, %rsp # imm = 0x128
movq %rsi, %r14
movq %rdi, %rbx
movq 0x28(%rsi), %rax
movq (%rax), %r12
movl 0x8(%rax), %r15d
movl 0xc(%rax), %eax
movl %eax, 0x34(%rsp)
movq 0x30(%r12), %rax
movq %r15, %rcx
shlq $0x4, %rcx
movb (%rax,%rcx), %dl
movq 0x8(%rax,%rcx), %rax
movb %dl, 0x80(%rsp)
movq %rax, 0x88(%rsp)
movq 0x48(%rsi), %rsi
movq %rsi, 0x70(%rsp)
testq %rsi, %rsi
je 0x180888f
leaq 0x70(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r14), %eax
movl %eax, 0x78(%rsp)
movq 0x88(%rsp), %r8
movq (%rbx), %rsi
movq 0x8(%rbx), %rax
movq 0x40(%rax), %rdx
movl 0x80(%rsp), %ecx
leaq 0x48(%rsp), %r13
movq %r13, %rdi
callq 0x1e6d32e
cmpb $0x5, (%r13)
jne 0x18088d8
movq %rbx, %rdi
movq %r12, %rsi
movl %r15d, %edx
callq 0x180aea0
jmp 0x1808984
movzbl 0x80(%rsp), %eax
testq %rax, %rax
je 0x18088fc
leaq 0x19c7154(%rip), %rcx # 0x31cfa40
movb -0x1(%rax,%rcx), %bpl
movq $0x0, 0x28(%rsp)
jmp 0x1808910
leaq 0x80(%rsp), %rdi
callq 0x1e89fc8
movl %eax, %ebp
movq %rdx, 0x28(%rsp)
movq 0x8(%rbx), %r13
movq %r12, 0xc8(%rsp)
movl %r15d, 0xd0(%rsp)
movl 0x34(%rsp), %eax
movl %eax, 0xd4(%rsp)
leaq 0x70(%rsp), %r15
movq %r13, %rdi
xorl %esi, %esi
movq %r15, %rdx
xorl %ecx, %ecx
callq 0x1765662
movq %rax, 0x118(%rsp)
movl %edx, 0x120(%rsp)
movups 0x118(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xc8(%rsp), %xmm0
movups %xmm0, (%rsp)
movzbl %bpl, %ecx
movq %r13, %rdi
movl $0x9d, %esi
movq %r15, %rdx
movq 0x28(%rsp), %r8
callq 0x17638a8
movq %rax, %rbp
movl %edx, 0x28(%rsp)
movq 0x28(%r14), %rax
movq 0x28(%rax), %rsi
movl 0x30(%rax), %edx
movq %rbx, %rdi
callq 0x180aea0
movq %rax, 0x90(%rsp)
movl %edx, 0x6c(%rsp)
movq (%rbx), %r15
movl 0x34(%r15), %r13d
movl 0x3c(%r15), %eax
cmpl 0x38(%r15), %r13d
movq %rbp, %r12
je 0x1808a18
xorl %r13d, %r13d
cmpl $0xcf, 0x18(%rbp)
jne 0x1808a18
movq 0x28(%rbp), %rax
movq (%rax), %rcx
movl 0x8(%rax), %eax
movq 0x30(%rcx), %rcx
shlq $0x4, %rax
movb (%rcx,%rax), %dl
movq 0x8(%rcx,%rax), %rax
leaq 0x48(%rsp), %rbp
movb %dl, (%rbp)
movq %rax, 0x8(%rbp)
movq %rbp, %rdi
callq 0x931436
movzbl %al, %esi
movq %r15, %rdi
callq 0x1472d4c
movl %eax, %r13d
movq (%rbx), %rdi
movq 0x8(%rbp), %rdx
movl (%rbp), %esi
movq %r12, %rbp
callq 0x1472d4c
movq 0x30(%rbp), %rcx
movl 0x28(%rsp), %edx
shlq $0x4, %rdx
movb (%rcx,%rdx), %sil
movq 0x8(%rcx,%rdx), %r15
movzbl %sil, %ebp
cmpl %eax, %r13d
je 0x1808c06
cmpl $0x2, %r13d
je 0x1808b4c
cmpl $0x1, %r13d
jne 0x1808c06
movq 0x8(%rbx), %rax
movq %rax, 0x60(%rsp)
movq 0x48(%r14), %rsi
movq %rsi, 0x48(%rsp)
testq %rsi, %rsi
je 0x1808a74
leaq 0x48(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r14), %eax
movl %eax, 0x50(%rsp)
movq %r12, 0xb8(%rsp)
movl 0x28(%rsp), %eax
movl %eax, 0xc0(%rsp)
movl 0x34(%rsp), %eax
movl %eax, 0xc4(%rsp)
movq 0x8(%rbx), %r12
movq 0x48(%r14), %rsi
movq %rsi, 0x38(%rsp)
testq %rsi, %rsi
je 0x1808abb
leaq 0x38(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r14), %eax
leaq 0x38(%rsp), %r13
movl %eax, 0x8(%r13)
movl $0x0, (%rsp)
movl $0x1, %esi
movq %r12, %rdi
movq %r13, %rdx
movl %ebp, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq 0x17645fe
movq %rax, 0x108(%rsp)
movl %edx, 0x110(%rsp)
movups 0x108(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xb8(%rsp), %xmm0
movups %xmm0, (%rsp)
leaq 0x48(%rsp), %rdx
movq 0x60(%rsp), %rdi
movl $0xb9, %esi
movl %ebp, %ecx
movq %r15, %r8
callq 0x17638a8
movq %rax, %r12
movl %edx, 0x28(%rsp)
movq (%r13), %rsi
testq %rsi, %rsi
je 0x1808b42
leaq 0x38(%rsp), %rdi
callq 0x2a758fc
movq 0x48(%rsp), %rsi
jmp 0x1808bf7
movq 0x8(%rbx), %rax
movq %rax, 0x60(%rsp)
movq 0x48(%r14), %rsi
movq %rsi, 0x48(%rsp)
testq %rsi, %rsi
je 0x1808b72
leaq 0x48(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r14), %eax
leaq 0x48(%rsp), %r13
movl %eax, 0x8(%r13)
movq %r12, 0xa8(%rsp)
movl 0x28(%rsp), %eax
movl %eax, 0xb0(%rsp)
movl 0x34(%rsp), %eax
movl %eax, 0xb4(%rsp)
movq 0x8(%rbx), %rdi
movl $0x2, %esi
xorl %edx, %edx
callq 0x1766848
movq %rax, 0xf8(%rsp)
movl %edx, 0x100(%rsp)
movups 0xf8(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xa8(%rsp), %xmm0
movups %xmm0, (%rsp)
movq 0x60(%rsp), %rdi
movl $0xda, %esi
movq %r13, %rdx
movl %ebp, %ecx
movq %r15, %r8
callq 0x17638a8
movq %rax, %r12
movl %edx, 0x28(%rsp)
movq (%r13), %rsi
testq %rsi, %rsi
je 0x1808c06
leaq 0x48(%rsp), %rdi
callq 0x2a758fc
movq (%rbx), %r13
movq 0x8(%rbx), %rax
movq 0x28(%rax), %rdi
callq 0x1d33c98
movq 0x8(%rbx), %rcx
movq 0x40(%rcx), %rdx
movq (%r13), %r9
movq %r13, %rdi
movq %rax, %rsi
movl %ebp, %ecx
movq %r15, %r8
callq *0x200(%r9)
movb %al, 0x48(%rsp)
movq %rdx, 0x50(%rsp)
cmpb %bpl, %al
jne 0x1808c53
testb %al, %al
jne 0x1808cfa
cmpq %r15, %rdx
je 0x1808cfa
leaq 0x48(%rsp), %rdi
movl %ebp, %esi
movq %r15, %rdx
callq 0xa5000c
testb %al, %al
je 0x1808cfa
movq 0x8(%rbx), %r15
movq 0x48(%r14), %rsi
movq %rsi, 0x38(%rsp)
testq %rsi, %rsi
je 0x1808c8b
leaq 0x38(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movq %r14, %rbp
movl 0x44(%r14), %eax
leaq 0x38(%rsp), %r13
movl %eax, 0x8(%r13)
movq 0x50(%rsp), %r8
movq %r12, 0x98(%rsp)
movl 0x28(%rsp), %eax
movl %eax, 0xa0(%rsp)
movl 0x34(%rsp), %eax
movl %eax, 0xa4(%rsp)
movl 0x48(%rsp), %ecx
movups 0x98(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r15, %rdi
movl $0xd7, %esi
movq %r13, %rdx
callq 0x176388a
movq %rax, %r14
movl %edx, 0x28(%rsp)
movq (%r13), %rsi
testq %rsi, %rsi
je 0x1808d00
leaq 0x38(%rsp), %rdi
callq 0x2a758fc
jmp 0x1808d00
movq %r14, %rbp
movq %r12, %r14
movq 0x8(%rbx), %r15
movq 0x48(%rbp), %rsi
movq %rsi, 0x38(%rsp)
testq %rsi, %rsi
je 0x1808d21
leaq 0x38(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movq %rbp, %rdi
movl 0x44(%rbp), %eax
leaq 0x38(%rsp), %r13
movl %eax, 0x8(%r13)
movq 0x90(%rsp), %rdx
movq 0x30(%rdx), %rax
movl 0x6c(%rsp), %esi
movl %esi, %ecx
shlq $0x4, %rcx
movq 0x8(%rax,%rcx), %rbp
movl (%rax,%rcx), %r12d
movq %rdx, 0xe8(%rsp)
movl %esi, 0xf0(%rsp)
movq 0x28(%rdi), %rax
movq 0x50(%rax), %rsi
movl 0x58(%rax), %edx
movq %rbx, %rdi
callq 0x180aea0
movq %rax, 0xd8(%rsp)
movl %edx, 0xe0(%rsp)
movups 0xd8(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xe8(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0x0, 0x20(%rsp)
movq %r15, %rdi
movq %r13, %rsi
movl %r12d, %edx
movq %rbp, %rcx
movq %r14, %r8
movl 0x28(%rsp), %r9d
callq 0x9f1108
movq %rax, %rbx
movl %edx, %ebp
movq (%r13), %rsi
testq %rsi, %rsi
je 0x1808dd2
leaq 0x38(%rsp), %rdi
callq 0x2a758fc
movq 0x70(%rsp), %rsi
testq %rsi, %rsi
je 0x1808de6
leaq 0x70(%rsp), %rdi
callq 0x2a758fc
movq %rbx, %rax
movl %ebp, %edx
addq $0x128, %rsp # imm = 0x128
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
|
llvm::DAGTypeLegalizer::WidenVecRes_VECTOR_COMPRESS(llvm::SDNode*)
|
SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_COMPRESS(SDNode *N) {
SDValue Vec = N->getOperand(0);
SDValue Mask = N->getOperand(1);
SDValue Passthru = N->getOperand(2);
EVT WideVecVT =
TLI.getTypeToTransformTo(*DAG.getContext(), Vec.getValueType());
EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
Mask.getValueType().getVectorElementType(),
WideVecVT.getVectorNumElements());
SDValue WideVec = ModifyToType(Vec, WideVecVT);
SDValue WideMask = ModifyToType(Mask, WideMaskVT, /*FillWithZeroes=*/true);
SDValue WidePassthru = ModifyToType(Passthru, WideVecVT);
return DAG.getNode(ISD::VECTOR_COMPRESS, SDLoc(N), WideVecVT, WideVec,
WideMask, WidePassthru);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rdi, %r14
movq %rsi, 0x80(%rsp)
movq 0x28(%rsi), %rax
movq (%rax), %r15
movl 0x8(%rax), %edx
movq 0x28(%rax), %rbx
movl 0x30(%rax), %r13d
movq 0x50(%rax), %rcx
movq %rcx, 0x78(%rsp)
movl 0x58(%rax), %eax
movl %eax, 0x44(%rsp)
movq (%rdi), %rdi
movq 0x8(%r14), %rax
movq 0x40(%rax), %rsi
movq 0x30(%r15), %rax
movq %rdx, 0x38(%rsp)
shlq $0x4, %rdx
movq 0x8(%rax,%rdx), %rcx
movq (%rdi), %r8
movl (%rax,%rdx), %edx
callq *0x240(%r8)
movb %al, 0x58(%rsp)
movq %rdx, 0x60(%rsp)
movq 0x8(%r14), %rax
movq 0x40(%rax), %r12
movq %rbx, 0x70(%rsp)
movq 0x30(%rbx), %rcx
movq %r13, 0x68(%rsp)
movq %r13, %rdx
shlq $0x4, %rdx
movzbl (%rcx,%rdx), %eax
movq 0x8(%rcx,%rdx), %rcx
movb %al, 0x48(%rsp)
movq %rcx, 0x50(%rsp)
testq %rax, %rax
je 0x182062a
leaq 0x19af420(%rip), %rcx # 0x31cfa40
movb -0x1(%rax,%rcx), %bpl
xorl %r13d, %r13d
jmp 0x1820639
leaq 0x48(%rsp), %rdi
callq 0x1e89fc8
movl %eax, %ebp
movq %rdx, %r13
leaq 0x58(%rsp), %rbx
movq %rbx, %rdi
callq 0x92c1fe
movzbl %bpl, %esi
movq %r12, %rdi
movq %r13, %rdx
movl %eax, %ecx
xorl %r8d, %r8d
callq 0x92dc58
movl %eax, %ebp
movq %rdx, %r12
movq 0x8(%rbx), %r8
movl (%rbx), %ecx
movq %r14, %rdi
movq %r15, %rsi
movq 0x38(%rsp), %rdx
xorl %r9d, %r9d
callq 0x1825d2e
movq %rax, 0x38(%rsp)
movl %edx, 0x40(%rsp)
movzbl %bpl, %ecx
movq %r14, %rdi
movq 0x70(%rsp), %rsi
movq 0x68(%rsp), %rdx
movq %r12, %r8
movl $0x1, %r9d
callq 0x1825d2e
movq %rax, %r12
movl %edx, %r13d
movq 0x8(%rbx), %r8
movl (%rbx), %ecx
movq %r14, %rdi
movq 0x78(%rsp), %rsi
movl 0x44(%rsp), %edx
xorl %r9d, %r9d
callq 0x1825d2e
movq %rax, %r15
movl %edx, %ebp
movq 0x8(%r14), %rbx
movq 0x80(%rsp), %r14
movq 0x48(%r14), %rsi
movq %rsi, 0x48(%rsp)
testq %rsi, %rsi
je 0x18206ee
leaq 0x48(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r14), %eax
leaq 0x48(%rsp), %r14
movl %eax, 0x8(%r14)
movq 0x60(%rsp), %r8
movq 0x38(%rsp), %rax
movq %rax, 0xa8(%rsp)
movl 0x40(%rsp), %eax
movl %eax, 0xb0(%rsp)
movq %r12, 0x98(%rsp)
movl %r13d, 0xa0(%rsp)
movq %r15, 0x88(%rsp)
movl %ebp, 0x90(%rsp)
movl 0x58(%rsp), %ecx
movups 0x88(%rsp), %xmm0
movups %xmm0, 0x20(%rsp)
movups 0x98(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xa8(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %rbx, %rdi
movl $0xaa, %esi
movq %r14, %rdx
callq 0x1764b02
movq %rax, %rbx
movl %edx, %ebp
movq (%r14), %rsi
testq %rsi, %rsi
je 0x1820788
leaq 0x48(%rsp), %rdi
callq 0x2a758fc
movq %rbx, %rax
movl %ebp, %edx
addq $0xb8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
|
bool llvm::DenseMapBase<llvm::DenseMap<llvm::SDNode*, llvm::SDNode*, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseMapPair<llvm::SDNode*, llvm::SDNode*>>, llvm::SDNode*, llvm::SDNode*, llvm::DenseMapInfo<llvm::SDNode*, void>, llvm::detail::DenseMapPair<llvm::SDNode*, llvm::SDNode*>>::LookupBucketFor<llvm::SDNode*>(llvm::SDNode* const&, llvm::detail::DenseMapPair<llvm::SDNode*, llvm::SDNode*> const*&) const
|
unsigned getNumBuckets() const {
return NumBuckets;
}
|
movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x1832061
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movq (%rdi,%rbx), %rbx
cmpq %rbx, (%rsi)
jne 0x1832028
movq %r11, (%rdx)
movb $0x1, %al
xorl %r11d, %r11d
testb %r11b, %r11b
jne 0x1832005
jmp 0x183205e
cmpq $-0x1000, %rbx # imm = 0xF000
jne 0x1832042
testq %r9, %r9
cmovneq %r9, %r11
movq %r11, (%rdx)
xorl %r11d, %r11d
xorl %eax, %eax
jmp 0x1832021
xorq $-0x2000, %rbx # imm = 0xE000
orq %r9, %rbx
cmoveq %r11, %r9
addl %r10d, %r8d
incl %r10d
andl %ecx, %r8d
movb $0x1, %r11b
jmp 0x1832021
popq %rbx
jmp 0x183206a
movq $0x0, (%rdx)
xorl %eax, %eax
andb $0x1, %al
retq
nop
|
/llvm/ADT/DenseMap.h
|
hasOnlyLiveOutUses(llvm::SUnit const*)
|
size_t size() const { return Size; }
|
movl 0x80(%rdi), %ecx
testq %rcx, %rcx
sete %al
je 0x18377aa
movq 0x78(%rdi), %rdx
shlq $0x4, %rcx
xorl %esi, %esi
movl $0x1, %r8d
xorl %edi, %edi
movq (%rdx,%rsi), %r10
movb $0x1, %r9b
testb $0x6, %r10b
jne 0x1837794
andq $-0x8, %r10
movq (%r10), %r9
testq %r9, %r9
je 0x1837791
cmpl $0x31, 0x18(%r9)
jne 0x1837791
movq 0x28(%r9), %r9
movq 0x28(%r9), %r9
movl 0x58(%r9), %r10d
movl %r10d, %r9d
shrl $0x1f, %r9d
testl %r10d, %r10d
movzbl %dil, %edi
cmovsl %r8d, %edi
jmp 0x1837794
xorl %r9d, %r9d
testb %r9b, %r9b
je 0x18377a5
addq $0x10, %rsi
cmpq %rsi, %rcx
sete %al
jne 0x1837751
andb %dil, %al
jmp 0x18377ac
xorl %eax, %eax
andb $0x1, %al
retq
|
/llvm/ADT/SmallVector.h
|
llvm::ScheduleDAGSDNodes::RegDefIter::Advance()
|
void ScheduleDAGSDNodes::RegDefIter::Advance() {
for (;Node;) { // Visit all glued nodes.
for (;DefIdx < NodeNumDefs; ++DefIdx) {
if (!Node->hasAnyUseOfValue(DefIdx))
continue;
ValueType = Node->getSimpleValueType(DefIdx);
++DefIdx;
return; // Found a normal regdef.
}
Node = Node->getGluedNode();
if (!Node) {
return; // No values left to visit.
}
InitNodeNumDefs();
}
}
|
cmpq $0x0, 0x8(%rdi)
je 0x183a527
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
xorl %r14d, %r14d
movl 0x10(%rbx), %esi
cmpl 0x14(%rbx), %esi
jae 0x183a4b8
movq 0x8(%rbx), %rdi
callq 0x1790dee
testb %al, %al
jne 0x183a505
movl 0x10(%rbx), %esi
incl %esi
movl %esi, 0x10(%rbx)
jmp 0x183a49c
movq 0x8(%rbx), %rcx
movzwl 0x40(%rcx), %eax
testq %rax, %rax
je 0x183a4e9
decl %eax
movq 0x28(%rcx), %rcx
leaq (%rax,%rax,4), %rdx
movq (%rcx,%rdx,8), %rax
movl 0x8(%rcx,%rdx,8), %ecx
movq 0x30(%rax), %rdx
shlq $0x4, %rcx
cmpb $-0x41, (%rdx,%rcx)
cmovneq %r14, %rax
jmp 0x183a4eb
xorl %eax, %eax
movq %rax, 0x8(%rbx)
testq %rax, %rax
je 0x183a520
movq %rbx, %rdi
callq 0x183a3f4
cmpq $0x0, 0x8(%rbx)
jne 0x183a499
jmp 0x183a520
movq 0x8(%rbx), %rax
movl 0x10(%rbx), %ecx
movq 0x30(%rax), %rax
leal 0x1(%rcx), %edx
shlq $0x4, %rcx
movb (%rax,%rcx), %al
movb %al, 0x18(%rbx)
movl %edx, 0x10(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
|
/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
|
llvm::detail::DenseMapPair<llvm::MachineInstr const*, llvm::MachineFunction::CallSiteInfo>* llvm::DenseMapBase<llvm::DenseMap<llvm::MachineInstr const*, llvm::MachineFunction::CallSiteInfo, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, llvm::MachineFunction::CallSiteInfo>>, llvm::MachineInstr const*, llvm::MachineFunction::CallSiteInfo, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, llvm::MachineFunction::CallSiteInfo>>::InsertIntoBucketImpl<llvm::MachineInstr const*>(llvm::MachineInstr const* const&, llvm::MachineInstr const* const&, llvm::detail::DenseMapPair<llvm::MachineInstr const*, llvm::MachineFunction::CallSiteInfo>*)
|
BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow the table.
//
// The later case is tricky. For example, if we had one empty bucket with
// tons of tombstones, failing lookups (e.g. for insertion) would have to
// probe almost the entire table until it found the empty bucket. If the
// table completely filled with tombstones, no lookup would ever succeed,
// causing infinite loops in lookup.
unsigned NewNumEntries = getNumEntries() + 1;
unsigned NumBuckets = getNumBuckets();
if (LLVM_UNLIKELY(NewNumEntries * 4 >= NumBuckets * 3)) {
this->grow(NumBuckets * 2);
LookupBucketFor(Lookup, TheBucket);
NumBuckets = getNumBuckets();
} else if (LLVM_UNLIKELY(NumBuckets-(NewNumEntries+getNumTombstones()) <=
NumBuckets/8)) {
this->grow(NumBuckets);
LookupBucketFor(Lookup, TheBucket);
}
assert(TheBucket);
// Only update the state after we've grown our bucket space appropriately
// so that when growing buckets we have self-consistent entry count.
incrementNumEntries();
// If we are writing over a tombstone, remember this.
const KeyT EmptyKey = getEmptyKey();
if (!KeyInfoT::isEqual(TheBucket->getFirst(), EmptyKey))
decrementNumTombstones();
return TheBucket;
}
|
pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0x183ba8b
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x183ba8d
incl 0x8(%rbx)
cmpq $-0x1000, (%rax) # imm = 0xF000
je 0x183ba81
decl 0xc(%rbx)
addq $0x10, %rsp
popq %rbx
popq %r14
popq %r15
retq
addl %esi, %esi
movq %rbx, %rdi
callq 0x183baae
leaq 0x8(%rsp), %r15
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq 0x162cd7c
movq (%r15), %rax
jmp 0x183ba72
nop
|
/llvm/ADT/DenseMap.h
|
llvm::DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(llvm::SDNode*)
|
SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
bool IsStrict = N->isStrictFPOpcode();
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDValue Op = N->getOperand(IsStrict ? 1 : 0);
SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), N->getValueType(0));
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
TargetLowering::MakeLibCallOptions CallOptions;
EVT OpVT = N->getOperand(IsStrict ? 1 : 0).getValueType();
CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Op,
CallOptions, SDLoc(N),
Chain);
if (IsStrict)
ReplaceValueWith(SDValue(N, 1), Tmp.second);
return Tmp.first;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %rdi
callq 0x9f0c7a
movl %eax, %r15d
movq (%r14), %rdi
movq 0x8(%r14), %rax
movq 0x40(%rax), %rsi
movq 0x30(%rbx), %rax
movq 0x8(%rax), %rcx
movq (%rdi), %r8
movl (%rax), %edx
callq *0x240(%r8)
movb %al, 0x57(%rsp)
movq %rdx, 0x60(%rsp)
movq 0x28(%rbx), %rax
movzbl %r15b, %ebp
leaq (,%rbp,4), %r15
addq %rbp, %r15
movups (%rax,%r15,8), %xmm0
movaps %xmm0, 0xf0(%rsp)
testb %bpl, %bpl
je 0x1845bf2
movq (%rax), %rcx
movq %rcx, 0x58(%rsp)
movsd 0x8(%rax), %xmm0
movaps %xmm0, 0xa0(%rsp)
jmp 0x1845c06
xorps %xmm0, %xmm0
movaps %xmm0, 0xa0(%rsp)
movq $0x0, 0x58(%rsp)
leaq 0xf0(%rsp), %r12
movq (%r12), %rax
movl 0x8(%r12), %edx
movq 0x30(%rax), %rax
shlq $0x4, %rdx
movq 0x8(%rax,%rdx), %rsi
movq 0x30(%rbx), %r8
movq 0x8(%r8), %rcx
movl (%rax,%rdx), %edi
movl (%r8), %edx
callq 0x1e6c27e
movl %eax, %r9d
movq 0x28(%rbx), %rax
movq (%rax,%r15,8), %rcx
movl 0x8(%rax,%r15,8), %eax
movq 0x30(%rcx), %rcx
shlq $0x4, %rax
movb (%rcx,%rax), %dl
movq 0x8(%rcx,%rax), %rax
leaq 0x108(%rsp), %rcx
movb %dl, (%rcx)
movq %rax, 0x8(%rcx)
movq 0x30(%rbx), %rax
movb (%rax), %dl
movq 0x8(%rax), %rax
movq (%r14), %r13
movq 0x8(%r14), %r15
movq %r12, 0xc0(%rsp)
movl $0x1, %esi
movq %rsi, 0xc8(%rsp)
movq %rcx, 0x78(%rsp)
movq %rsi, 0x80(%rsp)
movb %dl, 0x88(%rsp)
movq %rax, 0x90(%rsp)
movb $0x14, 0x98(%rsp)
movq 0x48(%rbx), %rsi
movq %rsi, 0x68(%rsp)
testq %rsi, %rsi
je 0x1845cd2
leaq 0x68(%rsp), %rdi
movl $0x1, %edx
movl %r9d, %r12d
callq 0x2a757d8
movl %r12d, %r9d
movl 0x44(%rbx), %eax
leaq 0x68(%rsp), %r12
movl %eax, 0x8(%r12)
movq 0x58(%rsp), %rax
movq %rax, 0xb0(%rsp)
movaps 0xa0(%rsp), %xmm0
movlps %xmm0, 0xb8(%rsp)
movups 0xb0(%rsp), %xmm0
movups %xmm0, 0x40(%rsp)
movq 0x98(%rsp), %rax
movq %rax, 0x30(%rsp)
movups 0x78(%rsp), %xmm0
movups 0x88(%rsp), %xmm1
movups %xmm1, 0x20(%rsp)
movups %xmm0, 0x10(%rsp)
movups 0xc0(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r12, 0x38(%rsp)
movzbl 0x57(%rsp), %r8d
leaq 0xd0(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl %r9d, %ecx
movq 0x60(%rsp), %r9
callq 0x17b1f40
movq (%r12), %rsi
testq %rsi, %rsi
je 0x1845d72
leaq 0x68(%rsp), %rdi
callq 0x2a758fc
testq %rbp, %rbp
je 0x1845d97
movq 0xe0(%rsp), %rcx
movl 0xe8(%rsp), %r8d
movq %r14, %rdi
movq %rbx, %rsi
movl $0x1, %edx
callq 0x17f8436
movq 0xd0(%rsp), %rax
movl 0xd8(%rsp), %edx
addq $0x118, %rsp # imm = 0x118
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
|
llvm::DAGTypeLegalizer::SoftenFloatOp_LLROUND(llvm::SDNode*)
|
SDValue DAGTypeLegalizer::SoftenFloatOp_LLROUND(SDNode *N) {
EVT OpVT = N->getOperand(N->isStrictFPOpcode() ? 1 : 0).getValueType();
return SoftenFloatOp_Unary(N, GetFPLibCall(OpVT,
RTLIB::LLROUND_F32,
RTLIB::LLROUND_F64,
RTLIB::LLROUND_F80,
RTLIB::LLROUND_F128,
RTLIB::LLROUND_PPCF128));
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %rdi
callq 0x9f0c7a
movq 0x28(%rbx), %rcx
movzbl %al, %eax
leaq (%rax,%rax,4), %rax
movq (%rcx,%rax,8), %rdx
movl 0x8(%rcx,%rax,8), %eax
movq 0x30(%rdx), %rcx
shlq $0x4, %rax
movb (%rcx,%rax), %al
leal -0xc(%rax), %ecx
cmpb $0x10, %al
movl $0x114, %eax # imm = 0x114
movl $0x2b2, %esi # imm = 0x2B2
cmovel %eax, %esi
movzbl %cl, %eax
leal 0x110(%rax), %edx
cmpb $0x4, %al
cmovael %esi, %edx
movq %r14, %rdi
movq %rbx, %rsi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x18496c0
|
/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
|
llvm::DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(llvm::SDNode*)
|
SDValue DAGTypeLegalizer::SoftenFloatOp_SELECT_CC(SDNode *N) {
SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
EVT VT = NewLHS.getValueType();
NewLHS = GetSoftenedFloat(NewLHS);
NewRHS = GetSoftenedFloat(NewRHS);
TLI.softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, SDLoc(N),
N->getOperand(0), N->getOperand(1));
// If softenSetCCOperands returned a scalar, we need to compare the result
// against zero to select between true and false values.
if (!NewRHS.getNode()) {
NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
CCCode = ISD::SETNE;
}
// Update N to have the operands specified.
return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
N->getOperand(2), N->getOperand(3),
DAG.getCondCode(CCCode)),
0);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movups (%rax), %xmm0
movaps %xmm0, 0x50(%rsp)
movups 0x28(%rax), %xmm0
movaps %xmm0, 0x40(%rsp)
movq 0xa0(%rax), %rax
movl 0x58(%rax), %eax
movl %eax, 0x3c(%rsp)
movq 0x50(%rsp), %rsi
movl 0x58(%rsp), %edx
movq 0x30(%rsi), %rax
movq %rdx, %rcx
shlq $0x4, %rcx
movb (%rax,%rcx), %bpl
movq 0x8(%rax,%rcx), %rax
movq %rax, 0x78(%rsp)
callq 0x1847bb8
movq %rax, 0x50(%rsp)
movl %edx, 0x58(%rsp)
movq 0x40(%rsp), %rsi
movl 0x48(%rsp), %edx
movq %r14, %rdi
callq 0x1847bb8
movq %rax, 0x40(%rsp)
movl %edx, 0x48(%rsp)
movq (%r14), %r12
movq 0x8(%r14), %r13
movq 0x48(%rbx), %rsi
movq %rsi, 0x68(%rsp)
testq %rsi, %rsi
je 0x1848abe
leaq 0x68(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbx), %eax
leaq 0x68(%rsp), %r15
movl %eax, 0x8(%r15)
movq 0x28(%rbx), %rax
movups (%rax), %xmm0
movups 0x28(%rax), %xmm1
movups %xmm1, 0x20(%rsp)
movups %xmm0, 0x10(%rsp)
movq %r15, 0x8(%rsp)
leaq 0x3c(%rsp), %rax
movq %rax, (%rsp)
movzbl %bpl, %edx
leaq 0x50(%rsp), %r8
leaq 0x40(%rsp), %r9
movq %r12, %rdi
movq %r13, %rsi
movq 0x78(%rsp), %rcx
callq 0x17b282a
movq (%r15), %rsi
testq %rsi, %rsi
je 0x1848b1d
leaq 0x68(%rsp), %rdi
callq 0x2a758fc
cmpq $0x0, 0x40(%rsp)
jne 0x1848bab
movq 0x8(%r14), %r15
movq 0x48(%rbx), %rsi
movq %rsi, 0x68(%rsp)
testq %rsi, %rsi
je 0x1848b4a
leaq 0x68(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbx), %eax
leaq 0x68(%rsp), %r12
movl %eax, 0x8(%r12)
movq 0x50(%rsp), %rax
movl 0x58(%rsp), %ecx
movq 0x30(%rax), %rax
shlq $0x4, %rcx
movq 0x8(%rax,%rcx), %r8
movl (%rax,%rcx), %ecx
movl $0x0, (%rsp)
movq %r15, %rdi
xorl %esi, %esi
movq %r12, %rdx
xorl %r9d, %r9d
callq 0x17645fe
movq %rax, 0x40(%rsp)
movl %edx, 0x48(%rsp)
movq (%r12), %rsi
testq %rsi, %rsi
je 0x1848ba3
leaq 0x68(%rsp), %rdi
callq 0x2a758fc
movl $0x16, 0x3c(%rsp)
movq 0x8(%r14), %r14
movq 0x50(%rsp), %r15
movl 0x58(%rsp), %ebp
movq 0x40(%rsp), %r12
movl 0x48(%rsp), %r13d
movq 0x28(%rbx), %rax
movups 0x50(%rax), %xmm0
movaps %xmm0, 0xa0(%rsp)
movups 0x78(%rax), %xmm0
movaps %xmm0, 0x90(%rsp)
movl 0x3c(%rsp), %esi
movq %r14, %rdi
callq 0x1766ed6
movq %rax, 0x80(%rsp)
movl %edx, 0x88(%rsp)
movups 0x80(%rsp), %xmm0
movups %xmm0, 0x20(%rsp)
movaps 0x90(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movaps 0xa0(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r14, %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl %ebp, %ecx
movq %r12, %r8
movl %r13d, %r9d
callq 0x178e67a
xorl %edx, %edx
addq $0xb8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
|
llvm::DAGTypeLegalizer::PromoteFloatOperand(llvm::SDNode*, unsigned int)
|
bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
LLVM_DEBUG(dbgs() << "Promote float operand " << OpNo << ": "; N->dump(&DAG));
SDValue R = SDValue();
if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n");
return false;
}
// Nodes that use a promotion-requiring floating point operand, but doesn't
// produce a promotion-requiring floating point result, need to be legalized
// to use the promoted float operand. Nodes that produce at least one
// promotion-requiring floating point result have their operands legalized as
// a part of PromoteFloatResult.
// clang-format off
switch (N->getOpcode()) {
default:
#ifndef NDEBUG
dbgs() << "PromoteFloatOperand Op #" << OpNo << ": ";
N->dump(&DAG); dbgs() << "\n";
#endif
report_fatal_error("Do not know how to promote this operator's operand!");
case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break;
case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::LRINT:
case ISD::LLRINT: R = PromoteFloatOp_UnaryOp(N, OpNo); break;
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
R = PromoteFloatOp_FP_TO_XINT_SAT(N, OpNo); break;
case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break;
case ISD::STRICT_FP_EXTEND:
R = PromoteFloatOp_STRICT_FP_EXTEND(N, OpNo);
break;
case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break;
case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;
case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo); break;
case ISD::ATOMIC_STORE: R = PromoteFloatOp_ATOMIC_STORE(N, OpNo); break;
}
// clang-format on
if (R.getNode())
ReplaceValueWith(SDValue(N, 0), R);
return false;
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movl %edx, %ecx
leaq (%rcx,%rcx,4), %rcx
movq (%rax,%rcx,8), %rdx
movl 0x8(%rax,%rcx,8), %eax
movq 0x30(%rdx), %rdx
shlq $0x4, %rax
movq 0x8(%rdx,%rax), %rcx
movl (%rdx,%rax), %edx
xorl %r8d, %r8d
callq 0x17f9466
testb %al, %al
jne 0x184d7ef
movl 0x18(%rbx), %eax
cmpl $0x10f, %eax # imm = 0x10F
jg 0x184d724
cmpl $0xce, %eax
jle 0x184d751
leal -0xde(%rax), %ecx
cmpl $0x8, %ecx
ja 0x184d7ab
leaq 0x271d8d1(%rip), %rax # 0x3f6afdc
movslq (%rax,%rcx,4), %rcx
addq %rax, %rcx
jmpq *%rcx
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184db00
jmp 0x184d7d7
leal -0x110(%rax), %ecx
cmpl $0x2, %ecx
jb 0x184d777
cmpl $0x122, %eax # imm = 0x122
je 0x184d79e
cmpl $0x14a, %eax # imm = 0x14A
jne 0x184d7f9
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184e132
jmp 0x184d7d7
cmpl $0x91, %eax
je 0x184d784
cmpl $0x97, %eax
je 0x184d791
cmpl $0xce, %eax
jne 0x184d7f9
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184dd9e
jmp 0x184d7d7
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184da50
jmp 0x184d7d7
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184dc86
jmp 0x184d7d7
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184d98a
jmp 0x184d7d7
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184dfaa
jmp 0x184d7d7
cmpl $0xcf, %eax
jne 0x184d7f9
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184dea8
jmp 0x184d7d7
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184d80a
jmp 0x184d7d7
movq %r14, %rdi
movq %rbx, %rsi
callq 0x184dbbc
movl %edx, %r8d
testq %rax, %rax
je 0x184d7ef
movq %r14, %rdi
movq %rbx, %rsi
xorl %edx, %edx
movq %rax, %rcx
callq 0x17f8436
xorl %eax, %eax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
leaq 0x271dc99(%rip), %rdi # 0x3f6b499
movl $0x1, %esi
callq 0x2b31b17
|
/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
|
llvm::DAGTypeLegalizer::PromoteFloatOp_STORE(llvm::SDNode*, unsigned int)
|
SDValue DAGTypeLegalizer::PromoteFloatOp_STORE(SDNode *N, unsigned OpNo) {
StoreSDNode *ST = cast<StoreSDNode>(N);
SDValue Val = ST->getValue();
SDLoc DL(N);
SDValue Promoted = GetPromotedFloat(Val);
EVT VT = ST->getOperand(1).getValueType();
EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
SDValue NewVal;
NewVal = DAG.getNode(GetPromotionOpcode(Promoted.getValueType(), VT), DL,
IVT, Promoted);
return DAG.getStore(ST->getChain(), DL, NewVal, ST->getBasePtr(),
ST->getMemOperand());
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x60, %rsp
movq %rsi, %rbx
movq %rdi, %r14
movq 0x28(%rsi), %rax
movq 0x28(%rax), %r15
movl 0x30(%rax), %ebp
movq 0x48(%rsi), %rsi
movq %rsi, 0x20(%rsp)
testq %rsi, %rsi
je 0x184dfe4
leaq 0x20(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%rbx), %eax
movl %eax, 0x28(%rsp)
movq %r14, %rdi
movq %r15, %rsi
movl %ebp, %edx
callq 0x1847ebe
movq %rax, %r15
movl %edx, %ebp
movq 0x28(%rbx), %rax
movq 0x28(%rax), %rcx
movl 0x30(%rax), %eax
movq 0x30(%rcx), %rdx
shlq $0x4, %rax
movzbl (%rdx,%rax), %ecx
movq 0x8(%rdx,%rax), %rax
movb %cl, 0x30(%rsp)
movq %rax, 0x38(%rsp)
movq 0x8(%r14), %rax
movq 0x40(%rax), %r12
testq %rcx, %rcx
je 0x184e044
shll $0x4, %ecx
leaq 0x1980d07(%rip), %rdx # 0x31ced40
movq -0x10(%rcx,%rdx), %rax
movb -0x8(%rcx,%rdx), %dl
jmp 0x184e04e
leaq 0x30(%rsp), %rdi
callq 0x1e89e20
leaq 0x50(%rsp), %rdi
movq %rax, (%rdi)
movb %dl, 0x8(%rdi)
callq 0x2b60e74
movq %r12, %rdi
movl %eax, %esi
callq 0x921640
movq %rdx, %r8
movq 0x8(%r14), %rdi
movq 0x30(%r15), %rcx
movl %ebp, %edx
shlq $0x4, %rdx
movb (%rcx,%rdx), %cl
movl $0xe8, %esi
cmpb $0xb, %cl
je 0x184e0a8
movb 0x30(%rsp), %dl
movl $0xe9, %esi
cmpb $0xb, %dl
je 0x184e0a8
movl $0xec, %esi
cmpb $0xa, %cl
je 0x184e0a8
movl $0xed, %esi
cmpb $0xa, %dl
jne 0x184e120
movq %r15, 0x40(%rsp)
movl %ebp, 0x48(%rsp)
movups 0x40(%rsp), %xmm0
movups %xmm0, (%rsp)
movzbl %al, %ecx
leaq 0x20(%rsp), %r15
movq %r15, %rdx
callq 0x176388a
movl %edx, %r9d
movq 0x8(%r14), %rdi
movq 0x28(%rbx), %rcx
movq 0x68(%rbx), %r8
movq (%rcx), %rsi
movl 0x8(%rcx), %edx
movups 0x50(%rcx), %xmm0
movups %xmm0, (%rsp)
movq %r8, 0x10(%rsp)
movq %r15, %rcx
movq %rax, %r8
callq 0x1787346
movq %rax, %rbx
movl %edx, %ebp
movq (%r15), %rsi
testq %rsi, %rsi
je 0x184e10e
leaq 0x20(%rsp), %rdi
callq 0x2a758fc
movq %rbx, %rax
movl %ebp, %edx
addq $0x60, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
retq
leaq 0x271d44a(%rip), %rdi # 0x3f6b571
movl $0x1, %esi
callq 0x2b31b17
nop
|
/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
|
llvm::DAGTypeLegalizer::PromoteIntRes_SRL(llvm::SDNode*)
|
SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
SDValue RHS = N->getOperand(1);
if (N->getOpcode() != ISD::VP_SRL) {
// The input value must be properly zero extended.
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = ZExtPromotedInteger(RHS);
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS);
}
SDValue Mask = N->getOperand(2);
SDValue EVL = N->getOperand(3);
// The input value must be properly zero extended.
SDValue LHS = VPZExtPromotedInteger(N->getOperand(0), Mask, EVL);
if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
RHS = VPZExtPromotedInteger(RHS, Mask, EVL);
return DAG.getNode(N->getOpcode(), SDLoc(N), LHS.getValueType(), LHS, RHS,
Mask, EVL);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xe8, %rsp
movq %rsi, %r15
movq %rdi, %r12
movq 0x28(%rsi), %rax
movq 0x28(%rax), %r14
movl 0x30(%rax), %ebx
movl 0x34(%rax), %ecx
movl %ecx, 0x44(%rsp)
cmpl $0x180, 0x18(%rsi) # imm = 0x180
jne 0x1856f1b
movq %rbx, %rbp
movq 0x50(%rax), %rbx
movq 0x58(%rax), %r13
movups 0x78(%rax), %xmm0
movaps %xmm0, 0xa0(%rsp)
movq (%rax), %rsi
movl 0x8(%rax), %edx
movups 0x78(%rax), %xmm0
movups %xmm0, (%rsp)
movq %r12, %rdi
movq %rbx, %rcx
movl %r13d, %r8d
callq 0x185e970
movq %rax, 0x48(%rsp)
movl %edx, 0x54(%rsp)
movq 0x30(%r14), %rax
movq %rbp, 0x70(%rsp)
movq %rbp, %rcx
shlq $0x4, %rcx
movq 0x8(%rax,%rcx), %r8
movq (%r12), %rsi
movq 0x8(%r12), %rdx
movq 0x40(%rdx), %rdx
movl (%rax,%rcx), %ecx
leaq 0x58(%rsp), %rbp
movq %rbp, %rdi
callq 0x1e6d32e
cmpb $0x1, (%rbp)
jne 0x1857015
movaps 0xa0(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r12, %rdi
movq %r14, %rsi
movq 0x70(%rsp), %rdx
movq %rbx, %rcx
movl %r13d, %r8d
callq 0x185e970
movq %rax, %rbp
movl %edx, %r14d
jmp 0x185701d
movq (%rax), %rsi
movl 0x8(%rax), %edx
movq %r12, %rdi
callq 0x1825c8a
movq %rax, 0x48(%rsp)
movl %edx, %ebp
movq 0x30(%r14), %rax
movq %rbx, %rcx
shlq $0x4, %rcx
movq 0x8(%rax,%rcx), %r8
movq (%r12), %rsi
movq 0x8(%r12), %rdx
movq 0x40(%rdx), %rdx
movl (%rax,%rcx), %ecx
leaq 0x58(%rsp), %r13
movq %r13, %rdi
callq 0x1e6d32e
cmpb $0x1, (%r13)
jne 0x1856f76
movq %r12, %rdi
movq %r14, %rsi
movl %ebx, %edx
callq 0x1825c8a
movq %rax, %r14
movl %edx, %ebx
movq 0x8(%r12), %r12
movl 0x18(%r15), %r13d
movq 0x48(%r15), %rsi
movq %rsi, 0x58(%rsp)
testq %rsi, %rsi
je 0x1856f9c
leaq 0x58(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r15), %eax
leaq 0x58(%rsp), %r15
movl %eax, 0x8(%r15)
movq 0x48(%rsp), %rdx
movq 0x30(%rdx), %rax
movl %ebp, %ecx
shlq $0x4, %rcx
movq 0x8(%rax,%rcx), %r8
movl (%rax,%rcx), %ecx
movq %rdx, 0xd8(%rsp)
movl %ebp, 0xe0(%rsp)
movq %r14, 0x90(%rsp)
movl %ebx, 0x98(%rsp)
movl 0x44(%rsp), %eax
movl %eax, 0x9c(%rsp)
movups 0x90(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xd8(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r12, %rdi
movl %r13d, %esi
movq %r15, %rdx
callq 0x17638a8
jmp 0x18570f8
movq %r14, %rbp
movq 0x70(%rsp), %r14
movq %r13, %xmm0
movq 0x8(%r12), %r12
movl 0x18(%r15), %r13d
movq 0x48(%r15), %rsi
movq %rsi, 0x58(%rsp)
testq %rsi, %rsi
je 0x1857054
leaq 0x58(%rsp), %rdi
movl $0x1, %edx
movdqa %xmm0, 0x70(%rsp)
callq 0x2a757d8
movdqa 0x70(%rsp), %xmm0
movl 0x44(%r15), %eax
leaq 0x58(%rsp), %r15
movl %eax, 0x8(%r15)
movq 0x48(%rsp), %rdx
movq 0x30(%rdx), %rax
movl 0x54(%rsp), %esi
movl %esi, %ecx
shlq $0x4, %rcx
movq 0x8(%rax,%rcx), %r8
movl (%rax,%rcx), %ecx
movq %rdx, 0xc8(%rsp)
movl %esi, 0xd0(%rsp)
movq %rbp, 0x80(%rsp)
movl %r14d, 0x88(%rsp)
movl 0x44(%rsp), %eax
movl %eax, 0x8c(%rsp)
movq %rbx, 0xb8(%rsp)
movq %xmm0, 0xc0(%rsp)
movaps 0xa0(%rsp), %xmm0
movups %xmm0, 0x30(%rsp)
movups 0xb8(%rsp), %xmm0
movups %xmm0, 0x20(%rsp)
movups 0x80(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xc8(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r12, %rdi
movl %r13d, %esi
movq %r15, %rdx
callq 0x17644b8
movq %rax, %rbx
movl %edx, %ebp
movq (%r15), %rsi
testq %rsi, %rsi
je 0x185710f
leaq 0x58(%rsp), %rdi
callq 0x2a758fc
movq %rbx, %rax
movl %ebp, %edx
addq $0xe8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
|
llvm::DAGTypeLegalizer::ExpandShiftWithKnownAmountBit(llvm::SDNode*, llvm::SDValue&, llvm::SDValue&)
|
bool DAGTypeLegalizer::
ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
unsigned Opc = N->getOpcode();
SDValue In = N->getOperand(0);
SDValue Amt = N->getOperand(1);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
EVT ShTy = Amt.getValueType();
unsigned ShBits = ShTy.getScalarSizeInBits();
unsigned NVTBits = NVT.getScalarSizeInBits();
assert(isPowerOf2_32(NVTBits) &&
"Expanded integer type size not a power of two!");
SDLoc dl(N);
APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
KnownBits Known = DAG.computeKnownBits(Amt);
// If we don't know anything about the high bits, exit.
if (((Known.Zero | Known.One) & HighBitMask) == 0)
return false;
// Get the incoming operand to be shifted.
SDValue InL, InH;
GetExpandedInteger(In, InL, InH);
// If we know that any of the high bits of the shift amount are one, then we
// can do this as a couple of simple shifts.
if (Known.One.intersects(HighBitMask)) {
// Mask out the high bit, which we know is set.
Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
DAG.getConstant(~HighBitMask, dl, ShTy));
switch (Opc) {
default: llvm_unreachable("Unknown shift");
case ISD::SHL:
Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
return true;
case ISD::SRL:
Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
return true;
case ISD::SRA:
Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
DAG.getConstant(NVTBits - 1, dl, ShTy));
Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
return true;
}
}
// If we know that all of the high bits of the shift amount are zero, then we
// can do this as a couple of simple shifts.
if (HighBitMask.isSubsetOf(Known.Zero)) {
// Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
// shift if x is zero. We can use XOR here because x is known to be smaller
// than 32.
SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
DAG.getConstant(NVTBits - 1, dl, ShTy));
unsigned Op1, Op2;
switch (Opc) {
default: llvm_unreachable("Unknown shift");
case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
case ISD::SRL:
case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
}
// When shifting right the arithmetic for Lo and Hi is swapped.
if (Opc != ISD::SHL)
std::swap(InL, InH);
// Use a little trick to get the bits that move from Lo to Hi. First
// shift by one bit.
SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
// Then compute the remaining shift with amount-1.
SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
Lo = DAG.getNode(Opc, dl, NVT, InL, Amt);
Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
if (Opc != ISD::SHL)
std::swap(Hi, Lo);
return true;
}
return false;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x248, %rsp # imm = 0x248
movq %rcx, 0xa8(%rsp)
movq %rdx, %r12
movq %rsi, %r14
movq %rdi, %r15
movl 0x18(%rsi), %eax
movl %eax, 0x34(%rsp)
movq 0x28(%rsi), %rax
movq (%rax), %rcx
movq %rcx, 0x60(%rsp)
movl 0x8(%rax), %ecx
movl %ecx, 0x30(%rsp)
movq 0x28(%rax), %r13
movl 0x30(%rax), %ebp
movl 0x34(%rax), %eax
movl %eax, 0x2c(%rsp)
movq (%rdi), %rdi
movq 0x8(%r15), %rax
movq 0x40(%rax), %rsi
movq 0x30(%r14), %rax
movq 0x8(%rax), %rcx
movq (%rdi), %r8
movl (%rax), %edx
callq *0x240(%r8)
leaq 0x40(%rsp), %rbx
movb %al, (%rbx)
movq %rdx, 0x8(%rbx)
movq 0x30(%r13), %rax
movq %rbp, 0x38(%rsp)
movq %rbp, %rcx
shlq $0x4, %rcx
movb (%rax,%rcx), %dl
movq 0x8(%rax,%rcx), %rax
leaq 0x98(%rsp), %rdi
movb %dl, (%rdi)
movq %rax, 0x8(%rdi)
callq 0x9254d2
movq %rax, %rbp
movq %rbx, %rdi
callq 0x9254d2
movq %rax, %rbx
movq 0x48(%r14), %rsi
movq %rsi, 0x78(%rsp)
testq %rsi, %rsi
je 0x187031c
leaq 0x78(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movq %r12, 0xb0(%rsp)
movl 0x44(%r14), %eax
movl %eax, 0x80(%rsp)
testl %ebx, %ebx
je 0x187033d
bsrl %ebx, %r12d
xorl $0x1f, %r12d
jmp 0x1870343
movl $0x20, %r12d
leaq 0x68(%rsp), %r14
movq %r14, %rdi
movl %ebp, %esi
xorl %edx, %edx
xorl %ecx, %ecx
callq 0x91d2c6
movl 0x8(%r14), %edx
addl %ebp, %r12d
negl %r12d
leal (%rdx,%r12), %esi
addl $0x1f, %esi
movq %r14, %rdi
callq 0x95b8c2
movq 0x8(%r15), %rsi
leaq 0xf0(%rsp), %r14
movq %r14, %rdi
movq %r13, %rdx
movq 0x38(%rsp), %rcx
xorl %r8d, %r8d
callq 0x176a228
movl 0x8(%r14), %eax
movl %eax, 0x90(%rsp)
cmpl $0x40, %eax
ja 0x18703b0
movq 0xf0(%rsp), %rax
movq %rax, 0x88(%rsp)
jmp 0x18703c5
leaq 0x88(%rsp), %rdi
leaq 0xf0(%rsp), %rsi
callq 0x2b11114
leaq 0x100(%rsp), %rsi
cmpl $0x40, 0x90(%rsp)
ja 0x18703ec
movq %rsi, %r12
movq 0x100(%rsp), %rax
orq %rax, 0x88(%rsp)
jmp 0x18703fc
leaq 0x88(%rsp), %rdi
movq %rsi, %r12
callq 0x2b118b8
movl 0x90(%rsp), %ecx
movl %ecx, 0xe0(%rsp)
movq 0x88(%rsp), %rax
movq %rax, 0xd8(%rsp)
movl $0x0, 0x90(%rsp)
cmpl $0x40, %ecx
ja 0x1870439
andq 0x68(%rsp), %rax
movq %rax, 0xd8(%rsp)
jmp 0x187044b
leaq 0xd8(%rsp), %rdi
leaq 0x68(%rsp), %rsi
callq 0x2b1188e
movl 0xe0(%rsp), %r14d
movl %r14d, 0x58(%rsp)
movq 0xd8(%rsp), %rax
movq %rax, 0x50(%rsp)
movl $0x0, 0xe0(%rsp)
cmpl $0x41, %r14d
jb 0x187048a
leaq 0x50(%rsp), %rdi
callq 0x2b1284c
movl %r14d, %ecx
subl %eax, %ecx
cmpl $0x40, %ecx
ja 0x18704a6
cmpl $0x41, %r14d
jb 0x1870497
movq 0x50(%rsp), %rax
jmp 0x187049c
leaq 0x50(%rsp), %rax
cmpq $0x0, (%rax)
sete %bpl
jmp 0x18704a8
xorl %ebp, %ebp
cmpl $0x41, %r14d
jb 0x18704bd
movq 0x50(%rsp), %rdi
testq %rdi, %rdi
je 0x18704bd
callq 0x7802b0
cmpl $0x41, 0xe0(%rsp)
jb 0x18704d9
movq 0xd8(%rsp), %rdi
testq %rdi, %rdi
je 0x18704d9
callq 0x7802b0
cmpl $0x41, 0x90(%rsp)
jb 0x18704f5
movq 0x88(%rsp), %rdi
testq %rdi, %rdi
je 0x18704f5
callq 0x7802b0
xorl %r14d, %r14d
testb %bpl, %bpl
jne 0x1870c90
leaq 0xc8(%rsp), %rcx
movq %r14, (%rcx)
movl %r14d, 0x8(%rcx)
leaq 0xb8(%rsp), %r8
movq %r14, (%r8)
movl %r14d, 0x8(%r8)
movq %r15, %rdi
movq 0x60(%rsp), %rsi
movl 0x30(%rsp), %edx
callq 0x17f8b02
cmpl $0x40, 0x108(%rsp)
ja 0x187054c
movq 0x68(%rsp), %rax
testq %rax, 0x100(%rsp)
setne %al
jmp 0x1870559
leaq 0x68(%rsp), %rsi
movq %r12, %rdi
callq 0x2b12aa4
testb %al, %al
je 0x18705b4
movq 0x8(%r15), %rbp
movb 0x98(%rsp), %r14b
movq 0xa0(%rsp), %rax
movq %rax, 0x60(%rsp)
movq %r13, 0x1a0(%rsp)
movq 0x38(%rsp), %rax
movl %eax, 0x1a8(%rsp)
movl 0x2c(%rsp), %eax
movl %eax, 0x1ac(%rsp)
movl 0x70(%rsp), %eax
movl %eax, 0x118(%rsp)
cmpl $0x40, %eax
ja 0x18705d7
movq 0x68(%rsp), %rax
movq %rax, 0x110(%rsp)
jmp 0x18705e9
cmpl $0x40, 0x70(%rsp)
ja 0x18707be
movq 0xf0(%rsp), %rax
notq %rax
testq %rax, 0x68(%rsp)
sete %al
jmp 0x18707d0
leaq 0x110(%rsp), %rdi
leaq 0x68(%rsp), %rsi
callq 0x2b11114
leaq 0x110(%rsp), %r13
movq %r13, %rdi
callq 0x90c61a
movl 0x8(%r13), %eax
leaq 0x50(%rsp), %r12
movl %eax, 0x8(%r12)
movq (%r13), %rax
movq %rax, (%r12)
xorl %eax, %eax
movl %eax, 0x8(%r13)
movq 0xa0(%rsp), %r8
movl 0x98(%rsp), %ecx
movl %eax, (%rsp)
leaq 0x78(%rsp), %r13
movq %rbp, %rdi
movq %r12, %rsi
movq %r13, %rdx
xorl %r9d, %r9d
callq 0x17642f0
movq %rax, 0x220(%rsp)
movl %edx, 0x228(%rsp)
movups 0x220(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x1a0(%rsp), %xmm0
movups %xmm0, (%rsp)
movzbl %r14b, %ecx
movq %rbp, %rdi
movl $0xb9, %esi
movq %r13, %rdx
movq 0x60(%rsp), %r8
callq 0x17638a8
movq %rax, %r14
movl %edx, 0x38(%rsp)
cmpl $0x41, 0x8(%r12)
jb 0x187069c
movq 0x50(%rsp), %rdi
testq %rdi, %rdi
je 0x187069c
callq 0x7802b0
cmpl $0x41, 0x118(%rsp)
jb 0x18706b8
movq 0x110(%rsp), %rdi
testq %rdi, %rdi
je 0x18706b8
callq 0x7802b0
movq 0x8(%r15), %r13
movb 0x40(%rsp), %bpl
movq 0x48(%rsp), %r12
movl 0x34(%rsp), %eax
cmpl $0xbd, %eax
je 0x1870b6e
cmpl $0xbe, %eax
jne 0x1870bfd
movups 0xb8(%rsp), %xmm0
movaps %xmm0, 0x230(%rsp)
movl $0xffffffff, %eax # imm = 0xFFFFFFFF
addl %eax, %ebx
movq 0xa0(%rsp), %r8
movl 0x98(%rsp), %ecx
movl $0x0, (%rsp)
leaq 0x78(%rsp), %rdx
movq %r13, %rdi
movq %rbx, %rsi
movq %rdx, %rbx
xorl %r9d, %r9d
callq 0x17645fe
movq %rax, 0x210(%rsp)
movl %edx, 0x218(%rsp)
movups 0x210(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movaps 0x230(%rsp), %xmm0
movups %xmm0, (%rsp)
movzbl %bpl, %ecx
movq %r13, %rdi
movl $0xbe, %esi
movq %rbx, %rdx
movq %r12, %r8
callq 0x17638a8
movq 0xa8(%rsp), %rcx
movq %rax, (%rcx)
movl %edx, 0x8(%rcx)
movq 0x8(%r15), %rdi
movq 0x48(%rsp), %r8
movq %r14, 0x170(%rsp)
movl 0x38(%rsp), %eax
movl %eax, 0x178(%rsp)
movl 0x2c(%rsp), %eax
movl %eax, 0x17c(%rsp)
movl 0x40(%rsp), %ecx
movups 0x170(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xb8(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0xbe, %esi
jmp 0x1870c77
leaq 0x68(%rsp), %rdi
leaq 0xf0(%rsp), %rsi
callq 0x2b12ae4
testb %al, %al
je 0x1870b66
movq 0x8(%r15), %rbp
movq 0xa0(%rsp), %r12
movq %r13, 0x160(%rsp)
movq 0x38(%rsp), %rax
movl %eax, 0x168(%rsp)
movl 0x2c(%rsp), %eax
movl %eax, 0x16c(%rsp)
movl $0xffffffff, %eax # imm = 0xFFFFFFFF
addl %eax, %ebx
movl 0x98(%rsp), %r14d
movl $0x0, (%rsp)
leaq 0x78(%rsp), %rdx
movq %rbp, %rdi
movq %rbx, %rsi
movq %rdx, %rbx
movl %r14d, %ecx
movq %r12, %r8
xorl %r9d, %r9d
callq 0x17645fe
movq %rax, 0x200(%rsp)
movl %edx, 0x208(%rsp)
movups 0x200(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x160(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %rbp, %rdi
movl $0xbb, %esi
movq %rbx, %rdx
movl %r14d, %ecx
movq %r12, %r8
callq 0x17638a8
movq %rax, 0x60(%rsp)
movl %edx, 0x30(%rsp)
movl $0xbd, %eax
xorl %ebx, %ebx
xorl %ebp, %ebp
movl 0x34(%rsp), %ecx
cmpl %eax, %ecx
setne %bl
sete %bpl
addl %ebp, %ebp
orl %eax, %ebp
addl %ebx, %ebx
orl %eax, %ebx
cmpl %eax, %ecx
je 0x18708e1
movups 0xc8(%rsp), %xmm0
movaps %xmm0, 0x50(%rsp)
movl 0xc0(%rsp), %eax
movl %eax, 0xd0(%rsp)
movq 0xb8(%rsp), %rax
movq %rax, 0xc8(%rsp)
movq 0x50(%rsp), %rax
movq %rax, 0xb8(%rsp)
movl 0x58(%rsp), %eax
movl %eax, 0xc0(%rsp)
movq 0x8(%r15), %r14
movq 0x48(%rsp), %rax
movq %rax, 0x138(%rsp)
movq 0xc8(%rsp), %rax
movq %rax, 0x120(%rsp)
movl 0xd0(%rsp), %eax
movl %eax, 0x128(%rsp)
movl 0xd4(%rsp), %eax
movl %eax, 0x12c(%rsp)
movq 0xa0(%rsp), %r8
movl 0x98(%rsp), %ecx
movl 0x40(%rsp), %eax
movl %eax, 0xec(%rsp)
movl $0x0, (%rsp)
leaq 0x78(%rsp), %r12
movl $0x1, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %r9d, %r9d
callq 0x17645fe
movq %rax, 0x1f0(%rsp)
movl %edx, 0x1f8(%rsp)
movups 0x1f0(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movaps 0x120(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r14, %rdi
movl %ebp, %esi
movq %r12, %rdx
movq %r12, %r14
movl 0xec(%rsp), %ecx
movq 0x138(%rsp), %r8
callq 0x17638a8
movq 0x8(%r15), %rdi
movq 0x48(%rsp), %r8
movq %rax, 0x1e0(%rsp)
movl %edx, 0x1e8(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x1d0(%rsp)
movl 0x30(%rsp), %eax
movl %eax, 0x1d8(%rsp)
movl 0x40(%rsp), %ecx
movups 0x1d0(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x1e0(%rsp), %xmm0
movups %xmm0, (%rsp)
movl %ebp, %esi
movq %r12, %rdx
callq 0x17638a8
movq %rax, 0x60(%rsp)
movl %edx, 0x30(%rsp)
movq 0x8(%r15), %rdi
movq 0x48(%rsp), %r8
movq %r13, 0x150(%rsp)
movq 0x38(%rsp), %r12
movl %r12d, 0x158(%rsp)
movl 0x2c(%rsp), %ebp
movl %ebp, 0x15c(%rsp)
movl 0x40(%rsp), %ecx
movups 0x150(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xc8(%rsp), %xmm0
movups %xmm0, (%rsp)
movl 0x34(%rsp), %esi
movq %r14, %rdx
callq 0x17638a8
movq 0xb0(%rsp), %rcx
movq %rax, (%rcx)
movl %edx, 0x8(%rcx)
movq 0x8(%r15), %r14
movq 0x48(%rsp), %r15
movq %r13, 0x140(%rsp)
movl %r12d, 0x148(%rsp)
movl %ebp, 0x14c(%rsp)
movq %rcx, %r13
movl 0x40(%rsp), %r12d
movups 0x140(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xb8(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r14, %rdi
movl %ebx, %esi
leaq 0x78(%rsp), %rbx
movq %rbx, %rdx
movl %r12d, %ecx
movq %r15, %r8
callq 0x17638a8
movq %rax, 0x1c0(%rsp)
movl %edx, 0x1c8(%rsp)
movq 0x60(%rsp), %rax
movq %rax, 0x1b0(%rsp)
movl 0x30(%rsp), %eax
movl %eax, 0x1b8(%rsp)
movups 0x1b0(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0x1c0(%rsp), %xmm0
movups %xmm0, (%rsp)
movq %r14, %rdi
movl $0xba, %esi
movq %rbx, %rdx
movl %r12d, %ecx
movq %r15, %r8
callq 0x17638a8
movq 0xa8(%rsp), %rcx
movq %rax, (%rcx)
movl %edx, 0x8(%rcx)
movb $0x1, %r14b
cmpl $0xbd, 0x34(%rsp)
je 0x1870c90
movq (%rcx), %rax
movq %rax, 0x50(%rsp)
movl 0x8(%rcx), %eax
movl %eax, 0x58(%rsp)
movl 0xc(%rcx), %eax
movl %eax, 0x5c(%rsp)
movl 0x8(%r13), %eax
movl %eax, 0x8(%rcx)
movq (%r13), %rax
movq %rax, (%rcx)
movq 0x50(%rsp), %rax
movq %rax, (%r13)
movl 0x58(%rsp), %eax
movl %eax, 0x8(%r13)
jmp 0x1870c90
xorl %r14d, %r14d
jmp 0x1870c90
movl $0x0, (%rsp)
movzbl %bpl, %ecx
leaq 0x78(%rsp), %rbx
movq %r13, %rdi
xorl %esi, %esi
movq %rbx, %rdx
movq %r12, %r8
xorl %r9d, %r9d
callq 0x17645fe
movq 0xb0(%rsp), %rcx
movq %rax, (%rcx)
movl %edx, 0x8(%rcx)
movq 0x8(%r15), %rdi
movq 0x48(%rsp), %r8
movq %r14, 0x190(%rsp)
movl 0x38(%rsp), %eax
movl %eax, 0x198(%rsp)
movl 0x2c(%rsp), %eax
movl %eax, 0x19c(%rsp)
movl 0x40(%rsp), %ecx
movups 0x190(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xc8(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0xbd, %esi
movq %rbx, %rdx
callq 0x17638a8
movq 0xa8(%rsp), %rcx
jmp 0x1870c87
movl $0x0, (%rsp)
movzbl %bpl, %ecx
leaq 0x78(%rsp), %rbx
movq %r13, %rdi
xorl %esi, %esi
movq %rbx, %rdx
movq %r12, %r8
xorl %r9d, %r9d
callq 0x17645fe
movq 0xa8(%rsp), %rcx
movq %rax, (%rcx)
movl %edx, 0x8(%rcx)
movq 0x8(%r15), %rdi
movq 0x48(%rsp), %r8
movq %r14, 0x180(%rsp)
movl 0x38(%rsp), %eax
movl %eax, 0x188(%rsp)
movl 0x2c(%rsp), %eax
movl %eax, 0x18c(%rsp)
movl 0x40(%rsp), %ecx
movups 0x180(%rsp), %xmm0
movups %xmm0, 0x10(%rsp)
movups 0xb8(%rsp), %xmm0
movups %xmm0, (%rsp)
movl $0xbf, %esi
movq %rbx, %rdx
callq 0x17638a8
movq 0xb0(%rsp), %rcx
movq %rax, (%rcx)
movl %edx, 0x8(%rcx)
movb $0x1, %r14b
cmpl $0x41, 0x108(%rsp)
jb 0x1870cac
movq 0x100(%rsp), %rdi
testq %rdi, %rdi
je 0x1870cac
callq 0x7802b0
cmpl $0x41, 0xf8(%rsp)
jb 0x1870cc8
movq 0xf0(%rsp), %rdi
testq %rdi, %rdi
je 0x1870cc8
callq 0x7802b0
cmpl $0x41, 0x70(%rsp)
jb 0x1870cde
movq 0x68(%rsp), %rdi
testq %rdi, %rdi
je 0x1870cde
callq 0x7802b0
movq 0x78(%rsp), %rsi
testq %rsi, %rsi
je 0x1870cf2
leaq 0x78(%rsp), %rdi
callq 0x2a758fc
movl %r14d, %eax
addq $0x248, %rsp # imm = 0x248
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
|
llvm::DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(llvm::SDNode*)
|
SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
SDValue Lo, Hi;
GetExpandedOp(N->getOperand(0), Lo, Hi);
return N->getConstantOperandVal(1) ? Hi : Lo;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %r15
xorl %ebp, %ebp
leaq 0x20(%rsp), %r12
movq %rbp, -0x8(%r12)
movl %ebp, (%r12)
leaq 0x10(%rsp), %r13
movq %rbp, -0x8(%r13)
movl %ebp, (%r13)
movq 0x28(%rsi), %rax
movq (%rax), %rsi
movl 0x8(%rax), %edx
leaq 0x18(%rsp), %r14
leaq 0x8(%rsp), %rbx
movq %r14, %rcx
movq %rbx, %r8
callq 0x181583e
movq 0x28(%r15), %rax
movq 0x28(%rax), %rax
movq 0x58(%rax), %rax
cmpl $0x41, 0x20(%rax)
jb 0x1876c0f
movq 0x18(%rax), %rax
jmp 0x1876c13
addq $0x18, %rax
cmpq %rbp, (%rax)
cmoveq %r14, %rbx
cmoveq %r12, %r13
movq (%rbx), %rax
movl (%r13), %edx
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
|
llvm::detail::DenseMapPair<llvm::MCRegister, int>* llvm::DenseMapBase<llvm::DenseMap<llvm::MCRegister, int, llvm::DenseMapInfo<llvm::MCRegister, void>, llvm::detail::DenseMapPair<llvm::MCRegister, int>>, llvm::MCRegister, int, llvm::DenseMapInfo<llvm::MCRegister, void>, llvm::detail::DenseMapPair<llvm::MCRegister, int>>::InsertIntoBucketImpl<llvm::MCRegister>(llvm::MCRegister const&, llvm::MCRegister const&, llvm::detail::DenseMapPair<llvm::MCRegister, int>*)
|
BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow the table.
//
// The later case is tricky. For example, if we had one empty bucket with
// tons of tombstones, failing lookups (e.g. for insertion) would have to
// probe almost the entire table until it found the empty bucket. If the
// table completely filled with tombstones, no lookup would ever succeed,
// causing infinite loops in lookup.
unsigned NewNumEntries = getNumEntries() + 1;
unsigned NumBuckets = getNumBuckets();
if (LLVM_UNLIKELY(NewNumEntries * 4 >= NumBuckets * 3)) {
this->grow(NumBuckets * 2);
LookupBucketFor(Lookup, TheBucket);
NumBuckets = getNumBuckets();
} else if (LLVM_UNLIKELY(NumBuckets-(NewNumEntries+getNumTombstones()) <=
NumBuckets/8)) {
this->grow(NumBuckets);
LookupBucketFor(Lookup, TheBucket);
}
assert(TheBucket);
// Only update the state after we've grown our bucket space appropriately
// so that when growing buckets we have self-consistent entry count.
incrementNumEntries();
// If we are writing over a tombstone, remember this.
const KeyT EmptyKey = getEmptyKey();
if (!KeyInfoT::isEqual(TheBucket->getFirst(), EmptyKey))
decrementNumTombstones();
return TheBucket;
}
|
pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0x18930a1
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0x18930a3
incl 0x8(%rbx)
cmpl $-0x1, (%rax)
je 0x1893097
decl 0xc(%rbx)
addq $0x10, %rsp
popq %rbx
popq %r14
popq %r15
retq
addl %esi, %esi
movq %rbx, %rdi
callq 0x18930c4
leaq 0x8(%rsp), %r15
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq 0x1892fd6
movq (%r15), %rax
jmp 0x189308c
nop
|
/llvm/ADT/DenseMap.h
|
llvm::AMDGPUInstPrinter::printImmediateF16(unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
|
void AMDGPUInstPrinter::printImmediateF16(uint32_t Imm,
const MCSubtargetInfo &STI,
raw_ostream &O) {
int16_t SImm = static_cast<int16_t>(Imm);
if (isInlinableIntLiteral(SImm)) {
O << SImm;
return;
}
uint16_t HImm = static_cast<uint16_t>(Imm);
if (printImmediateFP16(HImm, STI, O))
return;
uint64_t Imm16 = static_cast<uint16_t>(Imm);
O << formatHex(Imm16);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movswq %si, %rax
addq $0x10, %rax
cmpq $0x50, %rax
ja 0x18b656b
movswq %si, %rsi
movq %rbx, %rdi
addq $0x18, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
jmp 0x2b7d122
movq %rdi, %r14
movzwl %si, %ebp
movl %ebp, %edi
movq %rdx, %rsi
movq %rbx, %rdx
callq 0x18b65a8
testb %al, %al
jne 0x18b659d
movl %ebp, %edx
movq %rsp, %r15
movq %r15, %rdi
movq %r14, %rsi
callq 0x28e4b7a
movq %rbx, %rdi
movq %r15, %rsi
callq 0x2b7d21a
addq $0x18, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
|
/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
|
(anonymous namespace)::R600MCCodeEmitter::encodeInstruction(llvm::MCInst const&, llvm::SmallVectorImpl<char>&, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
|
void R600MCCodeEmitter::encodeInstruction(const MCInst &MI,
SmallVectorImpl<char> &CB,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
if (MI.getOpcode() == R600::RETURN ||
MI.getOpcode() == R600::FETCH_CLAUSE ||
MI.getOpcode() == R600::ALU_CLAUSE ||
MI.getOpcode() == R600::BUNDLE ||
MI.getOpcode() == R600::KILL) {
return;
}
if (IS_VTX(Desc)) {
uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
if (!(STI.hasFeature(R600::FeatureCaymanISA))) {
InstWord2 |= 1 << 19; // Mega-Fetch bit
}
emit(InstWord01, CB);
emit(InstWord2, CB);
emit((uint32_t)0, CB);
} else if (IS_TEX(Desc)) {
int64_t Sampler = MI.getOperand(14).getImm();
int64_t SrcSelect[4] = {
MI.getOperand(2).getImm(), MI.getOperand(3).getImm(),
MI.getOperand(4).getImm(), MI.getOperand(5).getImm()};
int64_t Offsets[3] = {MI.getOperand(6).getImm() & 0x1F,
MI.getOperand(7).getImm() & 0x1F,
MI.getOperand(8).getImm() & 0x1F};
uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 |
Offsets[1] << 5 | Offsets[2] << 10;
emit(Word01, CB);
emit(Word2, CB);
emit((uint32_t)0, CB);
} else {
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
if ((STI.hasFeature(R600::FeatureR600ALUInst)) &&
((Desc.TSFlags & R600_InstFlag::OP1) ||
Desc.TSFlags & R600_InstFlag::OP2)) {
uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
Inst &= ~(0x3FFULL << 39);
Inst |= ISAOpCode << 1;
}
emit(Inst, CB);
}
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, %r15
movq %rdx, %rbx
movq %rsi, %r14
movl (%rsi), %eax
cmpl $0x15c, %eax # imm = 0x15C
jle 0x18bfc09
cmpl $0x15d, %eax # imm = 0x15D
je 0x18bfd80
cmpl $0x164, %eax # imm = 0x164
je 0x18bfd80
cmpl $0x19e, %eax # imm = 0x19E
je 0x18bfd80
jmp 0x18bfc1b
cmpl $0x7, %eax
je 0x18bfd80
cmpl $0x14, %eax
je 0x18bfd80
movq 0x10(%rdi), %rdx
movq (%rdx), %r12
shlq $0x5, %rax
subq %rax, %r12
movq 0x18(%r12), %rax
btl $0xc, %eax
jb 0x18bfc8c
btl $0xd, %eax
jb 0x18bfcb6
movq %r14, %rsi
movq %rcx, %rdx
callq 0x18bfd90
testb $0x10, 0xd9(%r15)
je 0x18bfc7e
addq $0x18, %r12
testb $0xc, 0x1(%r12)
je 0x18bfc7e
movabsq $-0x1ff8000000001, %rcx # imm = 0xFFFE007FFFFFFFFF
andq %rax, %rcx
addq %rax, %rax
movabsq $0x3ff0000000000, %rdx # imm = 0x3FF0000000000
andq %rax, %rdx
orq %rcx, %rdx
movq %rdx, %rax
leaq 0x8(%rsp), %rdx
movq %rax, -0x8(%rdx)
jmp 0x18bfd75
movq %r14, %rsi
movq %rcx, %rdx
callq 0x18bfd90
movq 0x10(%r14), %rcx
movl 0x28(%rcx), %ecx
movl %ecx, %ebp
orl $0x80000, %ebp # imm = 0x80000
testb $0x2, 0xd8(%r15)
cmovnel %ecx, %ebp
jmp 0x18bfd3c
movq 0x10(%r14), %rax
movl 0xe8(%rax), %edx
movl %edx, 0x8(%rsp)
movl 0x28(%rax), %ebp
movl 0x38(%rax), %edx
movl %edx, 0xc(%rsp)
movl 0x48(%rax), %r13d
movl 0x58(%rax), %r12d
movl 0x68(%rax), %edx
andl $0x1f, %edx
movl %edx, 0x10(%rsp)
movl 0x78(%rax), %r15d
movl 0x88(%rax), %eax
movl %eax, 0x14(%rsp)
movq %r14, %rsi
movq %rcx, %rdx
callq 0x18bfd90
movl 0x8(%rsp), %ecx
shll $0xf, %ecx
shll $0x14, %ebp
orl %ecx, %ebp
movl 0xc(%rsp), %ecx
shll $0x17, %ecx
shll $0x1a, %r13d
orl %ecx, %r13d
orl %ebp, %r13d
shll $0x1d, %r12d
orl %r13d, %r12d
addl 0x10(%rsp), %r12d
andl $0x1f, %r15d
shll $0x5, %r15d
orl %r12d, %r15d
movl 0x14(%rsp), %ecx
andl $0x1f, %ecx
shll $0xa, %ecx
orl %r15d, %ecx
movl %ecx, %ebp
leaq 0x8(%rsp), %rdx
movq %rax, -0x8(%rdx)
movq %rsp, %r14
movq %rbx, %rdi
movq %r14, %rsi
callq 0x89893e
movl %ebp, (%r14)
leaq 0x4(%rsp), %rdx
movq %rsp, %r14
movq %rbx, %rdi
movq %r14, %rsi
callq 0x89893e
movl $0x0, (%r14)
leaq 0x4(%rsp), %rdx
movq %rsp, %rsi
movq %rbx, %rdi
callq 0x89893e
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
|
llvm::AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(llvm::Triple const&, llvm::MCTargetOptions const&)
|
AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
const MCTargetOptions &Options) {
CodePointerSize = (TT.getArch() == Triple::amdgcn) ? 8 : 4;
StackGrowsUp = true;
HasSingleParameterDotFile = false;
//===------------------------------------------------------------------===//
MinInstAlignment = 4;
// This is the maximum instruction encoded size for gfx10. With a known
// subtarget, it can be reduced to 8 bytes.
MaxInstLength = (TT.getArch() == Triple::amdgcn) ? 20 : 16;
SeparatorString = "\n";
CommentString = ";";
InlineAsmStart = ";#ASMSTART";
InlineAsmEnd = ";#ASMEND";
//===--- Data Emission Directives -------------------------------------===//
UsesELFSectionDirectiveForBSS = true;
//===--- Global Variable Emission Directives --------------------------===//
HasAggressiveSymbolFolding = true;
COMMDirectiveAlignmentIsInBytes = false;
HasNoDeadStrip = true;
//===--- Dwarf Emission Directives -----------------------------------===//
SupportsDebugInformation = true;
UsesCFIWithoutEH = true;
DwarfRegNumForCFI = true;
UseIntegratedAssembler = false;
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
callq 0x28caab8
leaq 0x3f5f9be(%rip), %rax # 0x5821ce0
movq %rax, (%rbx)
xorl %eax, %eax
cmpl $0x1a, 0x20(%r14)
sete %al
leal 0x4(,%rax,4), %ecx
movl %ecx, 0x8(%rbx)
movb $0x1, %cl
movb %cl, 0x11(%rbx)
xorl %edx, %edx
movb %dl, 0x16c(%rbx)
movl $0x4, 0x1c(%rbx)
leal 0x10(,%rax,4), %eax
movl %eax, 0x18(%rbx)
leaq 0x3646eef(%rip), %rax # 0x4f0924d
movq %rax, 0x28(%rbx)
leaq 0x3676fd3(%rip), %rax # 0x4f3933c
movq %rax, 0x30(%rbx)
movq $0x1, 0x38(%rbx)
leaq 0x2cd7006(%rip), %rax # 0x4599382
movq %rax, 0x88(%rbx)
leaq 0x2cd7003(%rip), %rax # 0x459938d
movq %rax, 0x90(%rbx)
movb %cl, 0x151(%rbx)
movw $0x1, 0x161(%rbx)
movb %cl, 0x16f(%rbx)
movb %cl, 0x1a0(%rbx)
movb %cl, 0x1a8(%rbx)
movb %cl, 0x1b5(%rbx)
movb %dl, 0x1e0(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
|
/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
|
llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode(unsigned int)
|
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc) {
const WMMAOpcodeMappingInfo *Info = getWMMAMappingInfoFrom2AddrOpcode(Opc);
return Info ? Info->Opcode3Addr : ~0u;
}
|
movl $0x22, %ecx
leaq 0x2e0cb5c(%rip), %rax # 0x4722b40
movq %rcx, %rdx
shrq %rdx
movq %rdx, %rsi
notq %rsi
addq %rcx, %rsi
leaq (%rax,%rdx,8), %rcx
addq $0x8, %rcx
cmpl %edi, -0x8(%rcx)
cmovaeq %rdx, %rsi
cmovbq %rcx, %rax
movq %rsi, %rcx
testq %rsi, %rsi
jg 0x1915fe4
leaq 0x2e0cc3b(%rip), %rcx # 0x4722c50
cmpq %rcx, %rax
je 0x1916024
xorl %ecx, %ecx
cmpl %edi, (%rax)
cmoveq %rax, %rcx
jmp 0x1916026
xorl %ecx, %ecx
testq %rcx, %rcx
je 0x191602f
movl 0x4(%rcx), %eax
retq
movl $0xffffffff, %eax # imm = 0xFFFFFFFF
retq
|
/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
|
llvm::AMDGPU::getIntegerPairAttribute(llvm::Function const&, llvm::StringRef, std::pair<unsigned int, unsigned int>, bool)
|
std::pair<unsigned, unsigned>
getIntegerPairAttribute(const Function &F, StringRef Name,
std::pair<unsigned, unsigned> Default,
bool OnlyFirstRequired) {
Attribute A = F.getFnAttribute(Name);
if (!A.isStringAttribute())
return Default;
LLVMContext &Ctx = F.getContext();
std::pair<unsigned, unsigned> Ints = Default;
std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
if (Strs.first.trim().getAsInteger(0, Ints.first)) {
Ctx.emitError("can't parse first integer attribute " + Name);
return Default;
}
if (Strs.second.trim().getAsInteger(0, Ints.second)) {
if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
Ctx.emitError("can't parse second integer attribute " + Name);
return Default;
}
}
return Ints;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x68, %rsp
movl %r8d, %ebx
movq %rcx, %rbp
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
callq 0x2a40aac
leaq 0x18(%rsp), %rdi
movq %rax, (%rdi)
callq 0x29a8f12
testb %al, %al
je 0x19176fe
movl %ebx, 0xc(%rsp)
movq %r12, %rdi
callq 0x2a3b1a0
movq %rax, %rbx
leaq 0x18(%rsp), %rdi
callq 0x29a900e
leaq 0x20(%rsp), %rsi
movq %rax, (%rsi)
movq %rdx, 0x8(%rsi)
leaq 0xb(%rsp), %rdx
movb $0x2c, (%rdx)
leaq 0x48(%rsp), %r13
movl $0x1, %ecx
movq %r13, %rdi
callq 0x8215a0
leaq 0x12a5e4a(%rip), %rsi # 0x2bbd443
movl $0x6, %edx
movq %r13, %rdi
callq 0x821166
leaq 0x20(%rsp), %r13
movq %rax, %rdi
movq %rdx, %rsi
xorl %edx, %edx
movq %r13, %rcx
callq 0x2b575d8
movq (%r13), %r12
movq %r12, %rcx
shrq $0x20, %rcx
setne %cl
orb %al, %cl
cmovneq %rbp, %r12
cmpb $0x1, %cl
jne 0x1917659
leaq 0x20(%rsp), %rsi
movw $0x503, 0x20(%rsi) # imm = 0x503
leaq 0x2db0445(%rip), %rax # 0x46c7a8b
movq %rax, (%rsi)
movq %r15, 0x10(%rsi)
movq %r14, 0x18(%rsi)
movq %rbx, %rdi
jmp 0x19176ed
movq %rbx, 0x10(%rsp)
movq %rbp, %rbx
shrq $0x20, %rbx
leaq 0x58(%rsp), %rdi
leaq 0x12a5dd2(%rip), %rsi # 0x2bbd443
movl $0x6, %edx
callq 0x821166
leaq 0x20(%rsp), %r13
movq %rax, %rdi
movq %rdx, %rsi
xorl %edx, %edx
movq %r13, %rcx
callq 0x2b575d8
movq (%r13), %rcx
movq %rcx, %rdx
shrq $0x20, %rdx
setne %dl
orb %al, %dl
cmoveq %rcx, %rbx
cmpb $0x1, %dl
jne 0x19176f4
cmpb $0x0, 0xc(%rsp)
je 0x19176cb
leaq 0x12a5d8c(%rip), %rsi # 0x2bbd443
movl $0x6, %edx
leaq 0x58(%rsp), %rdi
callq 0x821166
testq %rdx, %rdx
je 0x19176f4
leaq 0x20(%rsp), %rsi
movw $0x503, 0x20(%rsi) # imm = 0x503
leaq 0x2db03d3(%rip), %rax # 0x46c7ab0
movq %rax, (%rsi)
movq %r15, 0x10(%rsi)
movq %r14, 0x18(%rsi)
movq 0x10(%rsp), %rdi
callq 0x2a603f6
jmp 0x19176fe
shlq $0x20, %rbx
movl %r12d, %ebp
orq %rbx, %rbp
movq %rbp, %rax
addq $0x68, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
|
llvm::AMDGPU::decodeStorecntDscnt(llvm::AMDGPU::IsaVersion const&, unsigned int)
|
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt) {
Waitcnt Decoded;
Decoded.StoreCnt =
unpackBits(StorecntDscnt, getLoadcntStorecntBitShift(Version.Major),
getStorecntBitWidth(Version.Major));
Decoded.DsCnt = unpackBits(StorecntDscnt, getDscntBitShift(Version.Major),
getDscntBitWidth(Version.Major));
return Decoded;
}
|
movq %rdi, %rax
pcmpeqd %xmm0, %xmm0
movdqu %xmm0, 0xc(%rdi)
movdqu %xmm0, (%rdi)
movl (%rsi), %ecx
xorl %esi, %esi
cmpl $0xa, %ecx
movl $0x3f, %edi
movl $0x0, %r8d
cmovael %edi, %r8d
cmpl $0xc, %ecx
setae %cl
cmovael %edi, %esi
shlb $0x3, %cl
andl %edx, %esi
shrl %cl, %edx
andl %r8d, %edx
movl %edx, 0xc(%rax)
movl %esi, 0x8(%rax)
retq
|
/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
|
llvm::AMDGPU::SendMsg::msgRequiresOp(long, llvm::MCSubtargetInfo const&)
|
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI) {
return MsgId == ID_SYSMSG ||
(!isGFX11Plus(STI) &&
(MsgId == ID_GS_PreGFX11 || MsgId == ID_GS_DONE_PreGFX11));
}
|
movb $0x1, %al
cmpq $0xf, %rdi
je 0x1918ae4
testb $0x28, 0xe2(%rsi)
je 0x1918ae5
xorl %eax, %eax
retq
andq $-0x2, %rdi
cmpq $0x2, %rdi
sete %al
retq
|
/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
|
llvm::AMDGPU::getNSAMaxSize(llvm::MCSubtargetInfo const&, bool)
|
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler) {
auto Version = getIsaVersion(STI.getCPU());
if (Version.Major == 10)
return Version.Minor >= 3 ? 13 : 5;
if (Version.Major == 11)
return 5;
if (Version.Major >= 12)
return HasSampler ? 4 : 5;
return 0;
}
|
pushq %rbx
movl %esi, %ebx
movq 0x40(%rdi), %rax
movq 0x48(%rdi), %rsi
movq %rax, %rdi
callq 0x2afdb5f
cmpl $0xb, %eax
je 0x1918d89
cmpl $0xa, %eax
jne 0x1918d90
shrq $0x20, %rax
xorl %ecx, %ecx
cmpl $0x3, %eax
setae %cl
leal 0x5(,%rcx,8), %ecx
jmp 0x1918d9e
movl $0x5, %ecx
jmp 0x1918d9e
movzbl %bl, %edx
xorl $0x5, %edx
xorl %ecx, %ecx
cmpl $0xc, %eax
cmovael %edx, %ecx
movl %ecx, %eax
popq %rbx
retq
|
/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
|
llvm::AMDGPU::eliminateConstantExprUsesOfLDSFromAllInstructions(llvm::Module&)
|
bool eliminateConstantExprUsesOfLDSFromAllInstructions(Module &M) {
// Constants are uniqued within LLVM. A ConstantExpr referring to a LDS
// global may have uses from multiple different functions as a result.
// This pass specialises LDS variables with respect to the kernel that
// allocates them.
// This is semantically equivalent to (the unimplemented as slow):
// for (auto &F : M.functions())
// for (auto &BB : F)
// for (auto &I : BB)
// for (Use &Op : I.operands())
// if (constantExprUsesLDS(Op))
// replaceConstantExprInFunction(I, Op);
SmallVector<Constant *> LDSGlobals;
for (auto &GV : M.globals())
if (AMDGPU::isLDSVariableToLower(GV))
LDSGlobals.push_back(&GV);
return convertUsersOfConstantsToInstructions(LDSGlobals);
}
|
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x40, %rsp
movq %rdi, %rbx
leaq 0x10(%rsp), %r12
movq %r12, -0x10(%r12)
movabsq $0x600000000, %rax # imm = 0x600000000
movq %rax, -0x8(%r12)
movq 0x10(%rdi), %r13
addq $0x8, %rbx
cmpq %rbx, %r13
je 0x191a9d5
movq %rsp, %r14
leaq -0x38(%r13), %r15
testq %r13, %r13
cmoveq %r13, %r15
movq %r15, %rdi
callq 0x191a909
testb %al, %al
je 0x191a9cc
movq %r14, %rdi
movq %r15, %rsi
callq 0x93160c
movq 0x8(%r13), %r13
cmpq %rbx, %r13
jne 0x191a9aa
movq (%rsp), %rdi
movl 0x8(%rsp), %esi
xorl %edx, %edx
movl $0x1, %ecx
xorl %r8d, %r8d
callq 0x2a9920c
movl %eax, %ebx
movq (%rsp), %rdi
cmpq %r12, %rdi
je 0x191a9fc
callq 0x780910
movl %ebx, %eax
addq $0x40, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
retq
|
/Target/AMDGPU/Utils/AMDGPUMemoryUtils.cpp
|
bool llvm::set_union<llvm::DenseSet<llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>>, llvm::DenseSet<llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>>>(llvm::DenseSet<llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>>&, llvm::DenseSet<llvm::GlobalVariable*, llvm::DenseMapInfo<llvm::GlobalVariable*, void>> const&)
|
bool set_union(S1Ty &S1, const S2Ty &S2) {
bool Changed = false;
for (const auto &E : S2)
if (S1.insert(E).second)
Changed = true;
return Changed;
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq 0xc9f43a
movl 0x10(%r13), %r12d
shlq $0x3, %r12
addq (%r13), %r12
cmpq %r12, %rax
je 0x191b46a
movq %rax, %r14
movq %rdx, %r15
xorl %ebp, %ebp
movl $0x1000, %r13d # imm = 0x1000
leaq 0x10(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
leaq 0xf(%rsp), %rcx
callq 0xca0996
cmpb $0x0, 0x20(%rsp)
movzbl %bpl, %ebp
movl $0x1, %eax
cmovnel %eax, %ebp
addq $0x8, %r14
cmpq %r15, %r14
je 0x191b463
movq (%r14), %rax
orq %r13, %rax
cmpq $-0x1000, %rax # imm = 0xF000
je 0x191b44c
cmpq %r12, %r14
jne 0x191b426
jmp 0x191b46c
xorl %ebp, %ebp
andb $0x1, %bpl
movl %ebp, %eax
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/llvm/ADT/SetOperations.h
|
llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::MCExpr const*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MCExpr const*>>, unsigned int, llvm::MCExpr const*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MCExpr const*>>::clear()
|
unsigned getNumEntries() const {
return NumEntries;
}
|
movl 0x8(%rdi), %eax
testl %eax, %eax
jne 0x191db61
cmpl $0x0, 0xc(%rdi)
je 0x191dc99
shll $0x2, %eax
movl 0x10(%rdi), %ecx
cmpl %ecx, %eax
setae %al
cmpl $0x41, %ecx
setb %dl
orb %al, %dl
je 0x191e696
testq %rcx, %rcx
je 0x191dc91
movq (%rdi), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, %rcx
andq %rcx, %rdx
andl $0x3, %ecx
negq %rcx
addq %rdx, %rcx
addq $0x4, %rcx
movq %rdx, %xmm0
pshufd $0x44, %xmm0, %xmm0 # xmm0 = xmm0[0,1,0,1]
addq $0x30, %rax
xorl %edx, %edx
movdqa 0x1a7bbc5(%rip), %xmm1 # 0x3399780
movdqa 0x129745d(%rip), %xmm2 # 0x2bb5020
movdqa 0x1297465(%rip), %xmm3 # 0x2bb5030
pxor %xmm3, %xmm0
pcmpeqd %xmm4, %xmm4
movq %rdx, %xmm5
pshufd $0x44, %xmm5, %xmm5 # xmm5 = xmm5[0,1,0,1]
movdqa %xmm5, %xmm6
por %xmm2, %xmm6
pxor %xmm3, %xmm6
movdqa %xmm6, %xmm7
pcmpgtd %xmm0, %xmm7
pcmpeqd %xmm0, %xmm6
pshufd $0xf5, %xmm6, %xmm8 # xmm8 = xmm6[1,1,3,3]
pand %xmm7, %xmm8
pshufd $0xf5, %xmm7, %xmm6 # xmm6 = xmm7[1,1,3,3]
por %xmm8, %xmm6
movd %xmm6, %esi
notl %esi
testb $0x1, %sil
je 0x191dc1d
movl $0xffffffff, -0x30(%rax) # imm = 0xFFFFFFFF
pxor %xmm4, %xmm6
pextrw $0x4, %xmm6, %esi
testb $0x1, %sil
je 0x191dc33
movl $0xffffffff, -0x20(%rax) # imm = 0xFFFFFFFF
por %xmm1, %xmm5
pxor %xmm3, %xmm5
movdqa %xmm5, %xmm6
pcmpgtd %xmm0, %xmm6
pcmpeqd %xmm0, %xmm5
pshufd $0xf5, %xmm5, %xmm7 # xmm7 = xmm5[1,1,3,3]
pand %xmm6, %xmm7
pshufd $0xf5, %xmm6, %xmm5 # xmm5 = xmm6[1,1,3,3]
por %xmm7, %xmm5
pxor %xmm4, %xmm5
pextrw $0x0, %xmm5, %esi
testb $0x1, %sil
je 0x191dc6f
movl $0xffffffff, -0x10(%rax) # imm = 0xFFFFFFFF
pextrw $0x4, %xmm5, %esi
testb $0x1, %sil
je 0x191dc80
movl $0xffffffff, (%rax) # imm = 0xFFFFFFFF
addq $0x4, %rdx
addq $0x40, %rax
cmpq %rdx, %rcx
jne 0x191dbd3
movq $0x0, 0x8(%rdi)
retq
|
/llvm/ADT/DenseMap.h
|
llvm::AMDGPUPALMetadata::refComputeRegister(llvm::StringRef)
|
msgpack::DocNode *AMDGPUPALMetadata::refComputeRegister(StringRef field) {
auto M = getComputeRegisters();
auto I = M.find(field);
return I == M.end() ? nullptr : &I->second;
}
|
pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %rsi
leaq 0x8(%rsp), %r15
movq %r15, %rdi
callq 0x191d86e
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq 0x2ae0bc4
movq 0x8(%r15), %rdx
addq $0x8, %rdx
leaq 0x38(%rax), %rsi
xorl %ecx, %ecx
cmpq %rdx, %rax
cmovneq %rsi, %rcx
movq %rcx, %rax
addq $0x20, %rsp
popq %rbx
popq %r14
popq %r15
retq
nop
|
/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp
|
bool llvm::DenseMapBase<llvm::DenseMap<unsigned int, llvm::MCExpr const*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MCExpr const*>>, unsigned int, llvm::MCExpr const*, llvm::DenseMapInfo<unsigned int, void>, llvm::detail::DenseMapPair<unsigned int, llvm::MCExpr const*>>::LookupBucketFor<unsigned int>(unsigned int const&, llvm::detail::DenseMapPair<unsigned int, llvm::MCExpr const*> const*&) const
|
unsigned getNumBuckets() const {
return NumBuckets;
}
|
movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x191e2ae
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %esi
leal (%rsi,%rsi,8), %eax
leal (%rsi,%rax,4), %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %ebx
shlq $0x4, %rbx
leaq (%rdi,%rbx), %r11
movl (%rdi,%rbx), %ebx
cmpl %ebx, %esi
jne 0x191e279
movq %r11, (%rdx)
movb $0x1, %al
xorl %r11d, %r11d
testb %r11b, %r11b
jne 0x191e258
jmp 0x191e2ab
cmpl $-0x1, %ebx
jne 0x191e28f
testq %r9, %r9
cmovneq %r9, %r11
movq %r11, (%rdx)
xorl %r11d, %r11d
xorl %eax, %eax
jmp 0x191e272
testq %r9, %r9
cmovneq %r9, %r11
cmpl $-0x2, %ebx
cmoveq %r11, %r9
addl %r10d, %r8d
incl %r10d
andl %ecx, %r8d
movb $0x1, %r11b
jmp 0x191e272
popq %rbx
jmp 0x191e2b7
movq $0x0, (%rdx)
xorl %eax, %eax
andb $0x1, %al
retq
|
/llvm/ADT/DenseMap.h
|
llvm::AMDGPU::AMDGPUMCKernelCodeT::EmitKernelCodeT(llvm::raw_ostream&, llvm::MCContext&)
|
void AMDGPUMCKernelCodeT::EmitKernelCodeT(raw_ostream &OS, MCContext &Ctx) {
const int Size = hasMCExprVersionTable().size();
for (int i = 0; i < Size; ++i) {
OS << "\t\t";
if (hasMCExprVersionTable()[i]) {
OS << get_amd_kernel_code_t_FldNames()[i + 1] << " = ";
int64_t Val;
const MCExpr *Value = getMCExprForIndex(i);
if (Value->evaluateAsAbsolute(Val))
OS << Val;
else
Value->print(OS, Ctx.getAsmInfo());
} else {
printAmdKernelCodeField(*this, i, OS, Ctx);
}
OS << '\n';
}
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rdx, (%rsp)
movq %rsi, %r14
movq %rdi, 0x8(%rsp)
xorl %r12d, %r12d
leaq 0x36371e5(%rip), %rbp # 0x4f55e87
leaq 0x2e083b7(%rip), %rbx # 0x4727060
xorl %r13d, %r13d
movl $0x2, %edx
movq %r14, %rdi
movq %rbp, %rsi
callq 0x7f9ba8
cmpb $0x1, (%r13,%rbx)
jne 0x191ed24
movq %rbp, %r15
leaq 0x3f067b2(%rip), %rax # 0x5825480
movq 0x10(%rax,%r12,2), %rsi
movq 0x18(%rax,%r12,2), %rdx
movq %r14, %rdi
callq 0x7f9ba8
movl $0x3, %edx
movq %rax, %rdi
leaq 0x2ed320e(%rip), %rsi # 0x47f1efd
callq 0x7f9ba8
movq 0x8(%rsp), %rdi
movl %r13d, %esi
callq 0x191eb00
movq (%rax), %rbp
movq %rbp, %rdi
leaq 0x10(%rsp), %rsi
callq 0x28e340e
testb %al, %al
je 0x191ed55
movq 0x10(%rsp), %rsi
movq %r14, %rdi
callq 0x2b7d122
jmp 0x191ed6d
leaq 0x3f06b85(%rip), %rax # 0x58258b0
movq (%r12,%rax), %rax
testq %rax, %rax
je 0x191ed70
leaq 0x3f06745(%rip), %rcx # 0x5825480
movq 0x10(%rcx,%r12,2), %rdi
movq 0x18(%rcx,%r12,2), %rsi
movq 0x8(%rsp), %rdx
movq %r14, %rcx
movq (%rsp), %r8
callq *%rax
jmp 0x191ed70
movq (%rsp), %rax
movq 0x98(%rax), %rdx
movq %rbp, %rdi
movq %r14, %rsi
xorl %ecx, %ecx
callq 0x28e14a4
movq %r15, %rbp
movq 0x20(%r14), %rax
cmpq 0x18(%r14), %rax
jae 0x191ed87
leaq 0x1(%rax), %rcx
movq %rcx, 0x20(%r14)
movb $0xa, (%rax)
jmp 0x191ed94
movq %r14, %rdi
movl $0xa, %esi
callq 0x2b7d68e
incq %r13
addq $0x8, %r12
cmpq $0x42, %r13
jne 0x191ecac
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
|
llvm::ARMInstPrinter::printT2AddrModeSoRegOperand(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
|
void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
const MCOperand &MO1 = MI->getOperand(OpNum);
const MCOperand &MO2 = MI->getOperand(OpNum + 1);
const MCOperand &MO3 = MI->getOperand(OpNum + 2);
WithMarkup ScopedMarkup = markup(O, Markup::Memory);
O << "[";
printRegName(O, MO1.getReg());
assert(MO2.getReg() && "Invalid so_reg load / store address!");
O << ", ";
printRegName(O, MO2.getReg());
unsigned ShAmt = MO3.getImm();
if (ShAmt) {
assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
O << ", lsl ";
markup(O, Markup::Immediate) << "#" << ShAmt;
}
O << "]";
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r8, %rbx
movl %edx, %r15d
movq %rdi, %r14
movl %edx, %ebp
movq 0x10(%rsi), %r12
leal 0x1(%r15), %r13d
addl $0x2, %r15d
leaq 0x8(%rsp), %rdi
movq %r14, %rsi
movq %r8, %rdx
movl $0x3, %ecx
callq 0x28e4bf6
leaq 0x2fd3af9(%rip), %rsi # 0x48fd1fc
movl $0x1, %edx
movq %rbx, %rdi
callq 0x7f9ba8
shlq $0x4, %rbp
movl 0x8(%r12,%rbp), %edx
movq (%r14), %rax
movq %r14, %rdi
movq %rbx, %rsi
callq *0x28(%rax)
leaq 0x2656ea1(%rip), %rsi # 0x3f805cd
movl $0x2, %edx
movq %rbx, %rdi
callq 0x7f9ba8
shlq $0x4, %r13
movl 0x8(%r12,%r13), %edx
movq (%r14), %rax
movq %r14, %rdi
movq %rbx, %rsi
callq *0x28(%rax)
shlq $0x4, %r15
movl 0x8(%r12,%r15), %r15d
testq %r15, %r15
je 0x19297ae
leaq 0x2657092(%rip), %rsi # 0x3f807f5
movl $0x6, %edx
movq %rbx, %rdi
callq 0x7f9ba8
leaq 0x18(%rsp), %r12
movq %r12, %rdi
movq %r14, %rsi
movq %rbx, %rdx
xorl %ecx, %ecx
callq 0x28e4bf6
movq (%r12), %rdi
leaq 0x2e9eb00(%rip), %rsi # 0x47c8290
movl $0x1, %edx
callq 0x7f9ba8
movq (%r12), %rdi
movq %r15, %rsi
callq 0x2b7d110
movq %r12, %rdi
callq 0x28e4cbc
leaq 0x36a0235(%rip), %rsi # 0x4fc99ea
movl $0x1, %edx
movq %rbx, %rdi
callq 0x7f9ba8
leaq 0x8(%rsp), %rdi
callq 0x28e4cbc
addq $0x28, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
nop
|
/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
|
llvm::ARMInstPrinter::printFBits32(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
|
void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI, raw_ostream &O) {
markup(O, Markup::Immediate) << "#" << 32 - MI->getOperand(OpNum).getImm();
}
|
pushq %rbp
pushq %r14
pushq %rbx
subq $0x10, %rsp
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %rsi
movq %rsp, %rbx
movq %rbx, %rdi
movq %r8, %rdx
xorl %ecx, %ecx
callq 0x28e4bf6
movq (%rbx), %rdi
leaq 0x2e9e43e(%rip), %rsi # 0x47c8290
movl $0x1, %edx
callq 0x7f9ba8
movl %ebp, %eax
movq 0x10(%r14), %rcx
shlq $0x4, %rax
movl $0x20, %esi
subq 0x8(%rcx,%rax), %rsi
movq (%rbx), %rdi
callq 0x2b7d122
movq %rbx, %rdi
callq 0x28e4cbc
addq $0x10, %rsp
popq %rbx
popq %r14
popq %rbp
retq
nop
|
/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
|
llvm::ARMInstPrinter::printT2AddrModeImm8OffsetOperand(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
|
void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(
const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
raw_ostream &O) {
const MCOperand &MO1 = MI->getOperand(OpNum);
int32_t OffImm = (int32_t)MO1.getImm();
O << ", ";
WithMarkup ScopedMarkup = markup(O, Markup::Immediate);
if (OffImm == INT32_MIN)
O << "#-0";
else if (OffImm < 0)
O << "#-" << -OffImm;
else
O << "#" << OffImm;
}
|
pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %r8, %r14
movq %rdi, %r15
movl %edx, %eax
movq 0x10(%rsi), %rcx
shlq $0x4, %rax
movq 0x8(%rcx,%rax), %rbx
leaq 0x265671e(%rip), %rsi # 0x3f805cd
movl $0x2, %edx
movq %r8, %rdi
callq 0x7f9ba8
movq %rsp, %rdi
movq %r15, %rsi
movq %r14, %rdx
xorl %ecx, %ecx
callq 0x28e4bf6
movl %ebx, %eax
negl %eax
jno 0x1929ee8
leaq 0x2e07e57(%rip), %rsi # 0x4731d30
movl $0x3, %edx
movq %r14, %rdi
callq 0x7f9ba8
jmp 0x1929f29
testl %ebx, %ebx
js 0x1929f08
leaq 0x2e9e39d(%rip), %rsi # 0x47c8290
movl $0x1, %edx
movq %r14, %rdi
callq 0x7f9ba8
andl $0x7fffffff, %ebx # imm = 0x7FFFFFFF
jmp 0x1929f1e
leaq 0x2e07e06(%rip), %rsi # 0x4731d15
movl $0x2, %edx
movq %r14, %rdi
callq 0x7f9ba8
negl %ebx
movq %rax, %rdi
movq %rbx, %rsi
callq 0x2b7d122
movq %rsp, %rdi
callq 0x28e4cbc
addq $0x10, %rsp
popq %rbx
popq %r14
popq %r15
retq
nop
|
/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
|
llvm::ARMInstPrinter::printMveSaturateOp(llvm::MCInst const*, unsigned int, llvm::MCSubtargetInfo const&, llvm::raw_ostream&)
|
void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum,
const MCSubtargetInfo &STI,
raw_ostream &O) {
uint32_t Val = MI->getOperand(OpNum).getImm();
assert(Val <= 1 && "Invalid MVE saturate operand");
O << "#" << (Val == 1 ? 48 : 64);
}
|
pushq %rbx
movq %r8, %rdi
movl %edx, %eax
movq 0x10(%rsi), %rcx
shlq $0x4, %rax
movl 0x8(%rcx,%rax), %ebx
leaq 0x2e9d12d(%rip), %rsi # 0x47c8290
movl $0x1, %edx
callq 0x7f9ba8
xorl %esi, %esi
cmpl $0x1, %ebx
setne %sil
shll $0x4, %esi
addq $0x30, %rsi
movq %rax, %rdi
popq %rbx
jmp 0x2b7d122
|
/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
|
printRegImmShift(llvm::raw_ostream&, llvm::ARM_AM::ShiftOpc, unsigned int, llvm::ARMInstPrinter const&)
|
static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
unsigned ShImm, const ARMInstPrinter &printer) {
if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
return;
O << ", ";
assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
O << getShiftOpcStr(ShOpc);
if (ShOpc != ARM_AM::rrx) {
O << " ";
printer.markup(O, llvm::MCInstPrinter::Markup::Immediate)
<< "#" << translateShiftImm(ShImm);
}
}
|
testl %esi, %esi
je 0x192c415
pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x10, %rsp
movl %edx, %ebx
movl %esi, %ebp
movl %esi, %eax
xorl $0x2, %eax
orl %edx, %eax
je 0x192c409
movq %rcx, %r14
movq %rdi, %r15
leaq 0x265424d(%rip), %rsi # 0x3f805cd
movl $0x2, %edx
callq 0x7f9ba8
movslq %ebp, %rax
leaq 0x2e07614(%rip), %rcx # 0x47339a8
movq -0x8(%rcx,%rax,8), %rdx
leaq 0x3ef9770(%rip), %rcx # 0x5825b10
movq -0x8(%rcx,%rax,8), %rsi
movq %r15, %rdi
callq 0x7f9ba8
cmpl $0x5, %ebp
je 0x192c409
leaq 0x2f637a9(%rip), %rsi # 0x488fb62
movl $0x1, %edx
movq %r15, %rdi
callq 0x7f9ba8
movq %rsp, %r12
movq %r12, %rdi
movq %r14, %rsi
movq %r15, %rdx
xorl %ecx, %ecx
callq 0x28e4bf6
movq (%r12), %rdi
leaq 0x2e9beac(%rip), %rsi # 0x47c8290
movl $0x1, %edx
callq 0x7f9ba8
testl %ebx, %ebx
movl $0x20, %esi
cmovnel %ebx, %esi
movq (%r12), %rdi
callq 0x2b7d110
movq %r12, %rdi
callq 0x28e4cbc
addq $0x10, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
popq %rbp
retq
|
/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp
|
llvm::createARMWinCOFFStreamer(llvm::MCContext&, std::unique_ptr<llvm::MCAsmBackend, std::default_delete<llvm::MCAsmBackend>>&&, std::unique_ptr<llvm::MCObjectWriter, std::default_delete<llvm::MCObjectWriter>>&&, std::unique_ptr<llvm::MCCodeEmitter, std::default_delete<llvm::MCCodeEmitter>>&&)
|
MCStreamer *
llvm::createARMWinCOFFStreamer(MCContext &Context,
std::unique_ptr<MCAsmBackend> &&MAB,
std::unique_ptr<MCObjectWriter> &&OW,
std::unique_ptr<MCCodeEmitter> &&Emitter) {
return new ARMWinCOFFStreamer(Context, std::move(MAB), std::move(Emitter),
std::move(OW));
}
|
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x20, %rsp
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movl $0x1b8, %edi # imm = 0x1B8
callq 0x7808d0
movq %rax, %rbx
movq (%r12), %rax
xorl %ecx, %ecx
movq %rcx, (%r12)
movq (%r14), %rsi
movq %rcx, (%r14)
movq (%r15), %rdi
movq %rcx, (%r15)
leaq 0x10(%rsp), %rdx
movq %rax, (%rdx)
leaq 0x8(%rsp), %rcx
movq %rsi, (%rcx)
leaq 0x18(%rsp), %r14
movq %rdi, (%r14)
movq %rbx, %rdi
movq %r13, %rsi
movq %r14, %r8
callq 0x2901c8c
movq (%r14), %rdi
testq %rdi, %rdi
je 0x1930138
movq (%rdi), %rax
callq *0x8(%rax)
movq $0x0, 0x18(%rsp)
movq 0x8(%rsp), %rdi
testq %rdi, %rdi
je 0x1930151
movq (%rdi), %rax
callq *0x8(%rax)
movq $0x0, 0x8(%rsp)
movq 0x10(%rsp), %rdi
testq %rdi, %rdi
je 0x193016a
movq (%rdi), %rax
callq *0x8(%rax)
movq $0x0, 0x10(%rsp)
leaq 0x3f062f6(%rip), %rax # 0x5836470
movq %rax, (%rbx)
leaq 0x3f8d7dc(%rip), %rax # 0x58bd960
addq $0x10, %rax
movq %rax, 0x1b0(%rbx)
movq %rbx, %rax
addq $0x20, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
retq
|
/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
|
(anonymous namespace)::ARMTargetWinCOFFStreamer::emitARMWinCFIPrologEnd(bool)
|
void ARMTargetWinCOFFStreamer::emitARMWinCFIPrologEnd(bool Fragment) {
auto &S = getStreamer();
WinEH::FrameInfo *CurFrame = S.EnsureValidWinFrameInfo(SMLoc());
if (!CurFrame)
return;
MCSymbol *Label = S.emitCFILabel();
CurFrame->PrologEnd = Label;
WinEH::Instruction Inst =
WinEH::Instruction(Win64EH::UOP_End, /*Label=*/nullptr, -1, 0);
auto it = CurFrame->Instructions.begin();
CurFrame->Instructions.insert(it, Inst);
CurFrame->Fragment = Fragment;
}
|
pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movl %esi, %ebx
movq 0x8(%rdi), %r15
movq %r15, %rdi
xorl %esi, %esi
callq 0x28f78a0
testq %rax, %rax
je 0x19304cb
movq %rax, %r14
movq (%r15), %rax
movq %r15, %rdi
callq *0x58(%rax)
movq %rax, 0x28(%r14)
leaq 0x8(%rsp), %rdx
movq $0x0, (%rdx)
movabsq $-0x100000000, %rax # imm = 0xFFFFFFFF00000000
movq %rax, 0x8(%rdx)
movl $0x1b, 0x10(%rdx)
movq %r14, %rdi
addq $0x58, %rdi
movq 0x58(%r14), %rsi
callq 0x18944dc
movb %bl, 0x4b(%r14)
addq $0x20, %rsp
popq %rbx
popq %r14
popq %r15
retq
nop
|
/Target/ARM/MCTargetDesc/ARMWinCOFFStreamer.cpp
|
llvm::createARMTargetAsmStreamer(llvm::MCStreamer&, llvm::formatted_raw_ostream&, llvm::MCInstPrinter*)
|
MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
formatted_raw_ostream &OS,
MCInstPrinter *InstPrint) {
return new ARMTargetAsmStreamer(S, OS, *InstPrint);
}
|
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl $0x30, %edi
callq 0x7808d0
movq %rax, %r12
movq %rax, %rdi
movq %r15, %rsi
callq 0x192f834
leaq 0x3f034f0(%rip), %rax # 0x5837718
movq %rax, (%r12)
movq %r14, 0x18(%r12)
movq %rbx, 0x20(%r12)
movq (%r15), %rax
movq %r15, %rdi
callq *0x60(%rax)
movb %al, 0x28(%r12)
movq %r12, %rax
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
|
/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
|
(anonymous namespace)::ARMTargetAsmStreamer::emitSetFP(unsigned int, unsigned int, long)
|
void ARMTargetAsmStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
int64_t Offset) {
OS << "\t.setfp\t";
InstPrinter.printRegName(OS, FpReg);
OS << ", ";
InstPrinter.printRegName(OS, SpReg);
if (Offset)
OS << ", #" << Offset;
OS << '\n';
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rcx, %r14
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %rbx
movq 0x18(%rdi), %rdi
leaq 0x2e93c97(%rip), %rsi # 0x47c8278
movl $0x8, %edx
callq 0x7f9ba8
movq 0x18(%rbx), %rsi
movq 0x20(%rbx), %rdi
movq (%rdi), %rax
movl %r15d, %edx
callq *0x28(%rax)
movq 0x18(%rbx), %rdi
leaq 0x264bfc6(%rip), %rsi # 0x3f805cd
movl $0x2, %edx
callq 0x7f9ba8
movq 0x18(%rbx), %rsi
movq 0x20(%rbx), %rdi
movq (%rdi), %rax
movl %ebp, %edx
callq *0x28(%rax)
testq %r14, %r14
je 0x1934646
movq 0x18(%rbx), %rdi
leaq 0x18aad30(%rip), %rsi # 0x31df361
movl $0x3, %edx
callq 0x7f9ba8
movq %rax, %rdi
movq %r14, %rsi
callq 0x2b7d122
movq 0x18(%rbx), %rdi
movq 0x20(%rdi), %rax
cmpq 0x18(%rdi), %rax
jae 0x193466a
leaq 0x1(%rax), %rcx
movq %rcx, 0x20(%rdi)
movb $0xa, (%rax)
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
movl $0xa, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
jmp 0x2b7d68e
|
/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
|
(anonymous namespace)::ARMTargetAsmStreamer::emitARMWinCFISaveRegMask(unsigned int, bool)
|
void ARMTargetAsmStreamer::emitARMWinCFISaveRegMask(unsigned Mask, bool Wide) {
if (Wide)
OS << "\t.seh_save_regs_w\t";
else
OS << "\t.seh_save_regs\t";
ListSeparator LS;
int First = -1;
OS << "{";
for (int I = 0; I <= 12; I++) {
if (Mask & (1 << I)) {
if (First < 0)
First = I;
} else {
if (First >= 0) {
printRegs(OS, LS, First, I - 1);
First = -1;
}
}
}
if (First >= 0)
printRegs(OS, LS, First, 12);
if (Mask & (1 << 14))
OS << LS << "lr";
OS << "}\n";
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movl %esi, %ebp
movq %rdi, %rbx
movq 0x18(%rdi), %rdi
testl %edx, %edx
je 0x1934f2f
leaq 0x2e93413(%rip), %rsi # 0x47c833b
movl $0x12, %edx
jmp 0x1934f3b
leaq 0x2e93418(%rip), %rsi # 0x47c834e
movl $0x10, %edx
callq 0x7f9ba8
movq %rsp, %r14
movb $0x1, (%r14)
leaq 0x264b67f(%rip), %rax # 0x3f805cd
movq %rax, 0x8(%r14)
movq $0x2, 0x10(%r14)
movq 0x18(%rbx), %rdi
leaq 0x2fc832c(%rip), %rsi # 0x48fd291
movl $0x1, %edx
callq 0x7f9ba8
movl $0xffffffff, %r15d # imm = 0xFFFFFFFF
movl $0xffffffff, %edx # imm = 0xFFFFFFFF
movl %r15d, %ecx
leal 0x1(%rcx), %r15d
btl %r15d, %ebp
jae 0x1934f8f
testl %edx, %edx
cmovsl %r15d, %edx
jmp 0x1934fa4
testl %edx, %edx
js 0x1934fa4
movq 0x18(%rbx), %rdi
movq %r14, %rsi
callq 0x1935277
movl $0xffffffff, %edx # imm = 0xFFFFFFFF
cmpl $0xc, %r15d
jne 0x1934f7a
testl %edx, %edx
js 0x1934fbf
movq 0x18(%rbx), %rdi
movq %rsp, %rsi
movl $0xc, %ecx
callq 0x1935277
btl $0xe, %ebp
jae 0x1934ffc
movq 0x18(%rbx), %rdi
cmpb $0x1, (%rsp)
jne 0x1934fd9
movb $0x0, (%rsp)
xorl %esi, %esi
xorl %edx, %edx
jmp 0x1934fe3
movq 0x8(%rsp), %rsi
movq 0x10(%rsp), %rdx
callq 0x7f9ba8
leaq 0x2dfca2f(%rip), %rsi # 0x4731a1e
movl $0x2, %edx
movq %rax, %rdi
callq 0x7f9ba8
movq 0x18(%rbx), %rdi
leaq 0x3040418(%rip), %rsi # 0x497541f
movl $0x2, %edx
addq $0x18, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
jmp 0x7f9ba8
nop
|
/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
|
(anonymous namespace)::ARMELFStreamer::SwitchToEHSection(llvm::StringRef, unsigned int, unsigned int, llvm::SectionKind, llvm::MCSymbol const&)
|
inline void ARMELFStreamer::SwitchToEHSection(StringRef Prefix,
unsigned Type,
unsigned Flags,
SectionKind Kind,
const MCSymbol &Fn) {
const MCSectionELF &FnSection =
static_cast<const MCSectionELF &>(Fn.getSection());
// Create the name for new section
StringRef FnSecName(FnSection.getName());
SmallString<128> EHSecName(Prefix);
if (FnSecName != ".text") {
EHSecName += FnSecName;
}
// Get .ARM.extab or .ARM.exidx section
const MCSymbolELF *Group = FnSection.getGroup();
if (Group)
Flags |= ELF::SHF_GROUP;
MCSectionELF *EHSection = getContext().getELFSection(
EHSecName, Type, Flags, 0, Group, /*IsComdat=*/true,
FnSection.getUniqueID(),
static_cast<const MCSymbolELF *>(FnSection.getBeginSymbol()));
assert(EHSection && "Failed to get the required EH section");
// Switch to .ARM.extab or .ARM.exidx section
switchSection(EHSection);
emitValueToAlignment(Align(4), 0, 1, 0);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %r8d, (%rsp)
movl %ecx, 0x4(%rsp)
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %rbx
movq %r9, %rdi
movl $0x1, %esi
callq 0x858016
movq 0x8(%rax), %r14
movq 0x80(%r14), %r15
movq 0x88(%r14), %r12
addq %rbp, %r13
leaq 0x20(%rsp), %rcx
movq %rcx, -0x18(%rcx)
movq $0x0, -0x10(%rcx)
movl $0x80, %eax
movq %rax, -0x8(%rcx)
leaq 0x8(%rsp), %rdi
movq %rbp, %rsi
movq %r13, %rdx
callq 0x89893e
cmpq $0x5, %r12
jne 0x1936270
leaq 0x18eb5d5(%rip), %rsi # 0x3221836
movq %r15, %rdi
movq %r12, %rdx
callq 0x780c70
testl %eax, %eax
je 0x1936283
addq %r15, %r12
leaq 0x8(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
callq 0x89893e
movq 0xa8(%r14), %r9
movl (%rsp), %eax
movl %eax, %ecx
orl $0x200, %ecx # imm = 0x200
andq $-0x8, %r9
cmovel %eax, %ecx
movq 0x8(%rbx), %rdi
leaq 0xa0(%rsp), %rsi
movw $0x105, 0x20(%rsi) # imm = 0x105
movups 0x8(%rsp), %xmm0
movups %xmm0, (%rsi)
movl 0x9c(%r14), %eax
subq $0x8, %rsp
movl 0xc(%rsp), %edx
xorl %r8d, %r8d
pushq 0x10(%r14)
pushq %rax
pushq $0x1
callq 0x28d398e
addq $0x20, %rsp
movq (%rbx), %rcx
movq %rbx, %rdi
movq %rax, %rsi
xorl %edx, %edx
callq *0xa8(%rcx)
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x2, %esi
xorl %edx, %edx
movl $0x1, %ecx
xorl %r8d, %r8d
callq *0x280(%rax)
movq 0x8(%rsp), %rdi
leaq 0x20(%rsp), %rax
cmpq %rax, %rdi
je 0x1936318
callq 0x780910
addq $0xc8, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
|
(anonymous namespace)::ARMELFStreamer::changeSection(llvm::MCSection*, unsigned int)
|
void changeSection(MCSection *Section, uint32_t Subsection) override {
LastMappingSymbols[getCurrentSection().first] = std::move(LastEMSInfo);
MCELFStreamer::changeSection(Section, Subsection);
auto LastMappingSymbol = LastMappingSymbols.find(Section);
if (LastMappingSymbol != LastMappingSymbols.end()) {
LastEMSInfo = std::move(LastMappingSymbol->second);
return;
}
LastEMSInfo.reset(new ElfMappingSymbolInfo);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movl %edx, %ebp
movq %rsi, %r15
movq %rdi, %rbx
leaq 0x19d0(%rdi), %r14
movl 0x80(%rdi), %eax
testq %rax, %rax
je 0x19371cb
movq 0x78(%rbx), %rcx
shlq $0x5, %rax
movq -0x20(%rcx,%rax), %r13
jmp 0x19371ce
xorl %r13d, %r13d
leaq 0x10(%rsp), %rsi
movq %r13, (%rsi)
leaq 0x8(%rsp), %r12
movq %r14, %rdi
movq %r12, %rdx
callq 0x1937964
movq (%r12), %rcx
testb %al, %al
jne 0x193724b
movq %rcx, (%rsp)
movl 0x19d8(%rbx), %eax
movl 0x19e0(%rbx), %esi
leal 0x4(,%rax,4), %ecx
leal (%rsi,%rsi,2), %edx
cmpl %edx, %ecx
jae 0x1937333
notl %eax
addl %esi, %eax
subl 0x19dc(%rbx), %eax
movl %esi, %ecx
shrl $0x3, %ecx
cmpl %ecx, %eax
jbe 0x1937335
incl 0x19d8(%rbx)
movq (%rsp), %rcx
cmpq $-0x1000, (%rcx) # imm = 0xF000
je 0x1937240
decl 0x19dc(%rbx)
movq %r13, (%rcx)
movq $0x0, 0x8(%rcx)
movq 0x19e8(%rbx), %rax
movq $0x0, 0x19e8(%rbx)
movq 0x8(%rcx), %rdi
movq %rax, 0x8(%rcx)
testq %rdi, %rdi
je 0x1937274
movl $0x18, %esi
callq 0x7800d0
movq %rbx, %rdi
movq %r15, %rsi
movl %ebp, %edx
callq 0x28dfd04
movq %rsp, %rsi
movq %r15, (%rsi)
leaq 0x8(%rsp), %rdx
movq %r14, %rdi
callq 0x1937964
testb %al, %al
je 0x193729f
movq 0x8(%rsp), %rax
jmp 0x19372b0
movl 0x19e0(%rbx), %eax
shlq $0x4, %rax
addq 0x19d0(%rbx), %rax
movl 0x19e0(%rbx), %ecx
shlq $0x4, %rcx
addq 0x19d0(%rbx), %rcx
cmpq %rcx, %rax
je 0x19372e2
movq 0x8(%rax), %rcx
movq $0x0, 0x8(%rax)
movq 0x19e8(%rbx), %rdi
movq %rcx, 0x19e8(%rbx)
jmp 0x1937307
movl $0x18, %edi
callq 0x7808d0
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movl $0x0, 0x10(%rax)
movq 0x19e8(%rbx), %rdi
movq %rax, 0x19e8(%rbx)
testq %rdi, %rdi
je 0x1937324
movl $0x18, %esi
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x7800d0
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
addl %esi, %esi
movq %r14, %rdi
callq 0x19379fe
leaq 0x10(%rsp), %rsi
movq %rsp, %rdx
movq %r14, %rdi
callq 0x1937964
jmp 0x1937227
|
/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
|
llvm::UnwindOpcodeAssembler::EmitInt16(unsigned int)
|
void EmitInt16(unsigned Opcode) {
Ops.push_back((Opcode >> 8) & 0xff);
Ops.push_back(Opcode & 0xff);
OpBegins.push_back(OpBegins.back() + 2);
}
|
pushq %rbp
pushq %r14
pushq %rbx
movl %esi, %ebx
movq %rdi, %r14
shrl $0x8, %esi
movl $0xff, %ebp
andl %ebp, %esi
callq 0x88863a
andl %ebp, %ebx
movq %r14, %rdi
movl %ebx, %esi
callq 0x88863a
leaq 0x38(%r14), %rdi
movq 0x38(%r14), %rax
movl 0x40(%r14), %ecx
movl -0x4(%rax,%rcx,4), %esi
addl $0x2, %esi
popq %rbx
popq %r14
popq %rbp
jmp 0x81fb4c
|
/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h
|
llvm::AVRMCExpr::getKindByName(llvm::StringRef)
|
AVRMCExpr::VariantKind AVRMCExpr::getKindByName(StringRef Name) {
const auto &Modifier =
llvm::find_if(ModifierNames, [&Name](ModifierEntry const &Mod) {
return Mod.Spelling == Name;
});
if (Modifier != std::end(ModifierNames)) {
return Modifier->VariantKind;
}
return VK_AVR_None;
}
|
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x20, %rsp
leaq 0x10(%rsp), %rax
movq %rdi, (%rax)
movq %rsi, 0x8(%rax)
leaq 0x8(%rsp), %rbx
movq %rax, (%rbx)
leaq 0x3ef1960(%rip), %r14 # 0x5839a90
movl $0x4, %r13d
leaq 0x3ef1a13(%rip), %r12 # 0x5839b50
movq %rbx, %rdi
movq %r14, %rsi
callq 0x19481cc
testb %al, %al
jne 0x1948197
leaq 0x10(%r14), %r15
movq %rbx, %rdi
movq %r15, %rsi
callq 0x19481cc
testb %al, %al
jne 0x194819a
leaq 0x20(%r14), %r15
movq %rbx, %rdi
movq %r15, %rsi
callq 0x19481cc
testb %al, %al
jne 0x194819a
leaq 0x30(%r14), %r15
movq %rbx, %rdi
movq %r15, %rsi
callq 0x19481cc
testb %al, %al
jne 0x194819a
addq $0x40, %r14
decq %r13
cmpq $0x1, %r13
ja 0x194813d
movq %r12, %r15
jmp 0x194819a
movq %r14, %r15
cmpq %r12, %r15
je 0x19481a5
movl 0x8(%r15), %eax
jmp 0x19481a7
xorl %eax, %eax
addq $0x20, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
retq
nop
|
/Target/AVR/MCTargetDesc/AVRMCExpr.cpp
|
(anonymous namespace)::BPFAsmBackend::getFixupKindInfo(llvm::MCFixupKind) const
|
const MCFixupKindInfo &
BPFAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[BPF::NumTargetFixupKinds] = {
{ "FK_BPF_PCRel_4", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
};
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
return Infos[Kind - FirstTargetFixupKind];
}
|
cmpl $0x7f, %esi
jg 0x194b12c
jmp 0x28c9cec
addl $-0x80, %esi
leaq (%rsi,%rsi,2), %rax
leaq 0x3ef7956(%rip), %rcx # 0x5842a90
leaq (%rcx,%rax,8), %rax
retq
nop
|
/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
|
llvm::BPFInstPrinter::printBrTargetOperand(llvm::MCInst const*, unsigned int, llvm::raw_ostream&)
|
void BPFInstPrinter::printBrTargetOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isImm()) {
if (MI->getOpcode() == BPF::JMPL) {
int32_t Imm = Op.getImm();
O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
} else {
int16_t Imm = Op.getImm();
O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
}
} else if (Op.isExpr()) {
printExpr(Op.getExpr(), O);
} else {
O << Op;
}
}
|
pushq %r15
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rdi, %rbx
movl %edx, %eax
movq 0x10(%rsi), %rdx
shlq $0x4, %rax
leaq (%rdx,%rax), %rdi
movzbl (%rdx,%rax), %eax
cmpl $0x5, %eax
je 0x194bc4d
cmpl $0x2, %eax
jne 0x194bc62
cmpl $0x154, (%rsi) # imm = 0x154
movq 0x8(%rdi), %r15
jne 0x194bc75
testl %r15d, %r15d
leaq 0x1e5e23d(%rip), %rax # 0x37a9e65
leaq 0x260f889(%rip), %rsi # 0x3f5b4b8
cmovnsq %rax, %rsi
movl %r15d, %edx
shrl $0x1f, %edx
xorq $0x1, %rdx
movq %rcx, %rdi
callq 0x7f9ba8
movq %rax, %r14
movslq %r15d, %rdx
jmp 0x194bca6
movq 0x8(%rdi), %rdi
movq %rcx, %rsi
addq $0x20, %rsp
popq %rbx
popq %r14
popq %r15
jmp 0x194bd90
movq %rcx, %rsi
xorl %edx, %edx
addq $0x20, %rsp
popq %rbx
popq %r14
popq %r15
jmp 0x28e4238
movl %r15d, %edx
andl $0x8000, %edx # imm = 0x8000
leaq 0x1e5e1e0(%rip), %rax # 0x37a9e65
leaq 0x260f82c(%rip), %rsi # 0x3f5b4b8
cmoveq %rax, %rsi
shrl $0xf, %edx
xorq $0x1, %rdx
movq %rcx, %rdi
callq 0x7f9ba8
movq %rax, %r14
movswq %r15w, %rdx
leaq 0x8(%rsp), %r15
movq %r15, %rdi
movq %rbx, %rsi
callq 0x188cd0a
movq %r14, %rdi
movq %r15, %rsi
callq 0x2b7d21a
addq $0x20, %rsp
popq %rbx
popq %r14
popq %r15
retq
nop
|
/Target/BPF/MCTargetDesc/BPFInstPrinter.cpp
|
llvm::SmallVectorTemplateBase<llvm::MCInst const*, true>::push_back(llvm::MCInst const*)
|
void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0x1958cb7
movq (%rbx), %rax
movl 0x8(%rbx), %ecx
movq %r14, (%rax,%rcx,8)
incl 0x8(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
incq %rdx
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
callq 0x2b4ed86
jmp 0x1958ca2
nop
|
/llvm/ADT/SmallVector.h
|
llvm::HexagonMCELFStreamer::HexagonMCELFStreamer(llvm::MCContext&, std::unique_ptr<llvm::MCAsmBackend, std::default_delete<llvm::MCAsmBackend>>, std::unique_ptr<llvm::MCObjectWriter, std::default_delete<llvm::MCObjectWriter>>, std::unique_ptr<llvm::MCCodeEmitter, std::default_delete<llvm::MCCodeEmitter>>, llvm::MCAssembler*)
|
HexagonMCELFStreamer::HexagonMCELFStreamer(
MCContext &Context, std::unique_ptr<MCAsmBackend> TAB,
std::unique_ptr<MCObjectWriter> OW, std::unique_ptr<MCCodeEmitter> Emitter,
MCAssembler *Assembler)
: MCELFStreamer(Context, std::move(TAB), std::move(OW), std::move(Emitter)),
MCII(createHexagonMCInstrInfo()) {}
|
pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %rbx
movq (%rdx), %rdi
leaq 0x8(%rsp), %rax
movq %rdi, (%rax)
xorl %edi, %edi
movq %rdi, (%rdx)
movq (%rcx), %rdx
movq %rsp, %r9
movq %rdx, (%r9)
movq %rdi, (%rcx)
movq (%r8), %rcx
leaq 0x10(%rsp), %r14
movq %rcx, (%r14)
movq %rdi, (%r8)
movq %rbx, %rdi
movq %rax, %rdx
movq %r9, %rcx
movq %r14, %r8
callq 0x28dfacc
movq (%r14), %rdi
testq %rdi, %rdi
je 0x1959c35
movq (%rdi), %rax
callq *0x8(%rax)
movq $0x0, 0x10(%rsp)
movq (%rsp), %rdi
testq %rdi, %rdi
je 0x1959c4d
movq (%rdi), %rax
callq *0x8(%rax)
movq $0x0, (%rsp)
movq 0x8(%rsp), %rdi
testq %rdi, %rdi
je 0x1959c65
movq (%rdi), %rax
callq *0x8(%rax)
movq $0x0, 0x8(%rsp)
leaq 0x3ee8f43(%rip), %rax # 0x5842bb8
movq %rax, (%rbx)
callq 0x195ca5f
movq %rax, 0x19d0(%rbx)
addq $0x18, %rsp
popq %rbx
popq %r14
retq
|
/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp
|
createHexagonMCAsmInfo(llvm::MCRegisterInfo const&, llvm::Triple const&, llvm::MCTargetOptions const&)
|
static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT,
const MCTargetOptions &Options) {
MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
// VirtualFP = (R30 + #0).
MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
MAI->addInitialFrameState(Inst);
return MAI;
}
|
pushq %r15
pushq %r14
pushq %rbx
subq $0x70, %rsp
movq %rsi, %r14
movq %rdi, %r15
movl $0x1e8, %edi # imm = 0x1E8
callq 0x7808d0
movq %rax, %rbx
movq %rax, %rdi
movq %r14, %rsi
callq 0x196439a
movq %r15, %rdi
movl $0x94, %esi
movl $0x1, %edx
callq 0x28f28d0
xorl %ecx, %ecx
leaq 0x60(%rsp), %r15
movq %rcx, -0x58(%r15)
movb $0x7, -0x38(%r15)
xorps %xmm0, %xmm0
movups %xmm0, -0x30(%r15)
movups %xmm0, -0x20(%r15)
movq %r15, -0x10(%r15)
movq %rcx, -0x8(%r15)
movb $0x0, (%r15)
movl %eax, -0x50(%r15)
movq %rcx, -0x48(%r15)
leaq 0x8(%rsp), %r14
movq %rbx, %rdi
movq %r14, %rsi
callq 0x28ca1a4
movq 0x48(%r14), %rdi
cmpq %r15, %rdi
je 0x195da0b
movq 0x60(%rsp), %rsi
incq %rsi
callq 0x7800d0
movq 0x38(%rsp), %rdi
testq %rdi, %rdi
je 0x195da22
movq 0x48(%rsp), %rsi
subq %rdi, %rsi
callq 0x7800d0
movq %rbx, %rax
addq $0x70, %rsp
popq %rbx
popq %r14
popq %r15
retq
|
/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
|
llvm::HexagonShuffler::permitNonSlot()
|
size_t size() const { return Size; }
|
movl 0x8(%rdi), %eax
testq %rax, %rax
je 0x195f65e
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
movq (%rdi), %r14
shlq $0x3, %rax
leaq (%rax,%rax,4), %r15
xorl %r12d, %r12d
movq 0x140(%rbx), %rdi
movq (%r14,%r12), %rsi
callq 0x195b8f5
testb %al, %al
jne 0x195f64a
movq $0xf, 0x10(%r14,%r12)
addq $0x28, %r12
cmpq %r12, %r15
jne 0x195f62d
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
nop
|
/llvm/ADT/SmallVector.h
|
llvm::SmallVectorTemplateBase<CVIUnits, true>::push_back(CVIUnits)
|
void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0x196035f
movq (%rbx), %rax
movl 0x8(%rbx), %ecx
movq %r14, (%rax,%rcx,8)
incl 0x8(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
incq %rdx
leaq 0x10(%rbx), %rsi
movl $0x8, %ecx
movq %rbx, %rdi
callq 0x2b4ed86
jmp 0x196034a
|
/llvm/ADT/SmallVector.h
|
llvm::HexagonMCInstrInfo::deriveSubInst(llvm::MCInst const&)
|
MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
MCInst Result;
Result.setLoc(Inst.getLoc());
bool Absolute;
int64_t Value;
switch (Inst.getOpcode()) {
default:
// dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
llvm_unreachable("Unimplemented subinstruction \n");
break;
case Hexagon::A2_addi:
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
if (Absolute) {
if (Value == 1) {
Result.setOpcode(Hexagon::SA1_inc);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break;
} // 1,2 SUBInst $Rd = add($Rs, #1)
if (Value == -1) {
Result.setOpcode(Hexagon::SA1_dec);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break;
} // 1,2 SUBInst $Rd = add($Rs,#-1)
if (Inst.getOperand(1).getReg() == Hexagon::R29) {
Result.setOpcode(Hexagon::SA1_addsp);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break;
} // 1,3 SUBInst $Rd = add(r29, #$u6_2)
}
Result.setOpcode(Hexagon::SA1_addi);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rx = add($Rx, #$s7)
case Hexagon::A2_add:
Result.setOpcode(Hexagon::SA1_addrx);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rx = add($_src_, $Rs)
case Hexagon::S2_allocframe:
Result.setOpcode(Hexagon::SS2_allocframe);
addOps(Result, Inst, 2);
break; // 1 SUBInst allocframe(#$u5_3)
case Hexagon::A2_andir:
if (minConstant(Inst, 2) == 255) {
Result.setOpcode(Hexagon::SA1_zxtb);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 $Rd = and($Rs, #255)
} else {
Result.setOpcode(Hexagon::SA1_and1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = and($Rs, #1)
}
case Hexagon::C2_cmpeqi:
Result.setOpcode(Hexagon::SA1_cmpeqi);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 2,3 SUBInst p0 = cmp.eq($Rs, #$u2)
case Hexagon::A4_combineii:
case Hexagon::A2_combineii:
Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 1) {
Result.setOpcode(Hexagon::SA1_combine1i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#1, #$u2)
}
if (Value == 3) {
Result.setOpcode(Hexagon::SA1_combine3i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#3, #$u2)
}
if (Value == 0) {
Result.setOpcode(Hexagon::SA1_combine0i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#0, #$u2)
}
if (Value == 2) {
Result.setOpcode(Hexagon::SA1_combine2i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#2, #$u2)
}
break;
case Hexagon::A4_combineir:
Result.setOpcode(Hexagon::SA1_combinezr);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#0, $Rs)
case Hexagon::A4_combineri:
Result.setOpcode(Hexagon::SA1_combinerz);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rdd = combine($Rs, #0)
case Hexagon::L4_return_tnew_pnt:
case Hexagon::L4_return_tnew_pt:
Result.setOpcode(Hexagon::SL2_return_tnew);
break; // none SUBInst if (p0.new) dealloc_return:nt
case Hexagon::L4_return_fnew_pnt:
case Hexagon::L4_return_fnew_pt:
Result.setOpcode(Hexagon::SL2_return_fnew);
break; // none SUBInst if (!p0.new) dealloc_return:nt
case Hexagon::L4_return_f:
Result.setOpcode(Hexagon::SL2_return_f);
break; // none SUBInst if (!p0) dealloc_return
case Hexagon::L4_return_t:
Result.setOpcode(Hexagon::SL2_return_t);
break; // none SUBInst if (p0) dealloc_return
case Hexagon::L4_return:
Result.setOpcode(Hexagon::SL2_return);
break; // none SUBInst dealloc_return
case Hexagon::L2_deallocframe:
Result.setOpcode(Hexagon::SL2_deallocframe);
break; // none SUBInst deallocframe
case Hexagon::EH_RETURN_JMPR:
case Hexagon::J2_jumpr:
case Hexagon::PS_jmpret:
Result.setOpcode(Hexagon::SL2_jumpr31);
break; // none SUBInst jumpr r31
case Hexagon::J2_jumprf:
case Hexagon::PS_jmpretf:
Result.setOpcode(Hexagon::SL2_jumpr31_f);
break; // none SUBInst if (!p0) jumpr r31
case Hexagon::J2_jumprfnew:
case Hexagon::PS_jmpretfnewpt:
case Hexagon::PS_jmpretfnew:
Result.setOpcode(Hexagon::SL2_jumpr31_fnew);
break; // none SUBInst if (!p0.new) jumpr:nt r31
case Hexagon::J2_jumprt:
case Hexagon::PS_jmprett:
Result.setOpcode(Hexagon::SL2_jumpr31_t);
break; // none SUBInst if (p0) jumpr r31
case Hexagon::J2_jumprtnew:
case Hexagon::PS_jmprettnewpt:
case Hexagon::PS_jmprettnew:
Result.setOpcode(Hexagon::SL2_jumpr31_tnew);
break; // none SUBInst if (p0.new) jumpr:nt r31
case Hexagon::L2_loadrb_io:
Result.setOpcode(Hexagon::SL2_loadrb_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memb($Rs + #$u3_0)
case Hexagon::L2_loadrd_io:
Result.setOpcode(Hexagon::SL2_loadrd_sp);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = memd(r29 + #$u5_3)
case Hexagon::L2_loadrh_io:
Result.setOpcode(Hexagon::SL2_loadrh_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memh($Rs + #$u3_1)
case Hexagon::L2_loadrub_io:
Result.setOpcode(Hexagon::SL1_loadrub_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memub($Rs + #$u4_0)
case Hexagon::L2_loadruh_io:
Result.setOpcode(Hexagon::SL2_loadruh_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memuh($Rs + #$u3_1)
case Hexagon::L2_loadri_io:
if (Inst.getOperand(1).getReg() == Hexagon::R29) {
Result.setOpcode(Hexagon::SL2_loadri_sp);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 2 1,3 SUBInst $Rd = memw(r29 + #$u5_2)
} else {
Result.setOpcode(Hexagon::SL1_loadri_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memw($Rs + #$u4_2)
}
case Hexagon::S4_storeirb_io:
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 0) {
Result.setOpcode(Hexagon::SS2_storebi0);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst memb($Rs + #$u4_0)=#0
} else if (Value == 1) {
Result.setOpcode(Hexagon::SS2_storebi1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 1,2 SUBInst memb($Rs + #$u4_0)=#1
}
break;
case Hexagon::S2_storerb_io:
Result.setOpcode(Hexagon::SS1_storeb_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
case Hexagon::S2_storerd_io:
Result.setOpcode(Hexagon::SS2_stored_sp);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 2,3 SUBInst memd(r29 + #$s6_3) = $Rtt
case Hexagon::S2_storerh_io:
Result.setOpcode(Hexagon::SS2_storeh_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
case Hexagon::S4_storeiri_io:
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 0) {
Result.setOpcode(Hexagon::SS2_storewi0);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#0
} else if (Value == 1) {
Result.setOpcode(Hexagon::SS2_storewi1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#1
} else if (Inst.getOperand(0).getReg() == Hexagon::R29) {
Result.setOpcode(Hexagon::SS2_storew_sp);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1 2,3 SUBInst memw(r29 + #$u5_2) = $Rt
}
break;
case Hexagon::S2_storeri_io:
if (Inst.getOperand(0).getReg() == Hexagon::R29) {
Result.setOpcode(Hexagon::SS2_storew_sp);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2); // 1,2,3 SUBInst memw(sp + #$u5_2) = $Rt
} else {
Result.setOpcode(Hexagon::SS1_storew_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2); // 1,2,3 SUBInst memw($Rs + #$u4_2) = $Rt
}
break;
case Hexagon::A2_sxtb:
Result.setOpcode(Hexagon::SA1_sxtb);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = sxtb($Rs)
case Hexagon::A2_sxth:
Result.setOpcode(Hexagon::SA1_sxth);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = sxth($Rs)
case Hexagon::A2_tfr:
Result.setOpcode(Hexagon::SA1_tfr);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = $Rs
case Hexagon::C2_cmovenewif:
Result.setOpcode(Hexagon::SA1_clrfnew);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (!p0.new) $Rd = #0
case Hexagon::C2_cmovenewit:
Result.setOpcode(Hexagon::SA1_clrtnew);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (p0.new) $Rd = #0
case Hexagon::C2_cmoveif:
Result.setOpcode(Hexagon::SA1_clrf);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (!p0) $Rd = #0
case Hexagon::C2_cmoveit:
Result.setOpcode(Hexagon::SA1_clrt);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (p0) $Rd = #0
case Hexagon::A2_tfrsi:
Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
if (Absolute && Value == -1) {
Result.setOpcode(Hexagon::SA1_setin1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 1 SUBInst $Rd = #-1
} else {
Result.setOpcode(Hexagon::SA1_seti);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = #$u6
}
case Hexagon::A2_zxtb:
Result.setOpcode(Hexagon::SA1_zxtb);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 $Rd = and($Rs, #255)
case Hexagon::A2_zxth:
Result.setOpcode(Hexagon::SA1_zxth);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = zxth($Rs)
}
return Result;
}
|
pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x20(%rdi), %rax
xorps %xmm0, %xmm0
movups %xmm0, (%rdi)
movq %rax, 0x10(%rdi)
movabsq $0x600000000, %rax # imm = 0x600000000
movq %rax, 0x18(%rdi)
movq 0x8(%rsi), %rax
movq %rax, 0x8(%rdi)
movl (%rsi), %eax
cmpl $0x5fa, %eax # imm = 0x5FA
jg 0x196bdae
cmpl $0x49c, %eax # imm = 0x49C
jg 0x196bdd5
cmpl $0x3ed, %eax # imm = 0x3ED
jle 0x196be96
cmpl $0x435, %eax # imm = 0x435
jg 0x196befc
addl $0xfffffc12, %eax # imm = 0xFFFFFC12
leaq 0x2eeb016(%rip), %rcx # 0x4856db0
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl $0xa0d, (%rbx) # imm = 0xA0D
jmp 0x196c220
cmpl $0x813, %eax # imm = 0x813
jle 0x196be0c
cmpl $0x834, %eax # imm = 0x834
jg 0x196be41
addl $0xfffff7ec, %eax # imm = 0xFFFFF7EC
leaq 0x2eeb03c(%rip), %rcx # 0x4856e08
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
cmpl $0x52e, %eax # imm = 0x52E
jle 0x196be6d
cmpl $0x53a, %eax # imm = 0x53A
jle 0x196bf24
cmpl $0x5ce, %eax # imm = 0x5CE
jg 0x196bf8a
cmpl $0x53b, %eax # imm = 0x53B
jne 0x196bf19
movl $0xa20, (%rbx) # imm = 0xA20
jmp 0x196c29f
cmpl $0x60f, %eax # imm = 0x60F
jle 0x196bedb
leal -0x6b6(%rax), %ecx
cmpl $0x6, %ecx
ja 0x196c066
leaq 0x2eeafbf(%rip), %rax # 0x4856dec
movslq (%rax,%rcx,4), %rcx
addq %rax, %rcx
jmpq *%rcx
movl $0xa29, (%rbx) # imm = 0xA29
jmp 0x196c29f
cmpl $0x908, %eax # imm = 0x908
jle 0x196bf48
cmpl $0x9b4, %eax # imm = 0x9B4
jg 0x196bfa0
cmpl $0x909, %eax # imm = 0x909
jne 0x196c122
movl $0xa32, (%rbx) # imm = 0xA32
jmp 0x196c272
addl $0xfffffb63, %eax # imm = 0xFFFFFB63
cmpl $0x5, %eax
ja 0x196bf69
leaq 0x2eeaf52(%rip), %rcx # 0x4856dd4
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl $0x9fe, (%rbx) # imm = 0x9FE
jmp 0x196c220
cmpl $0x395, %eax # imm = 0x395
jle 0x196c01e
cmpl $0x396, %eax # imm = 0x396
je 0x196c092
cmpl $0x39d, %eax # imm = 0x39D
jne 0x196bfe1
movl $0x2, %esi
movq %r14, %rdi
callq 0x195b66e
cmpq $0xff, %rax
je 0x196c029
movl $0x9fd, (%rbx) # imm = 0x9FD
jmp 0x196c220
cmpl $0x5fb, %eax # imm = 0x5FB
je 0x196c034
cmpl $0x602, %eax # imm = 0x602
jne 0x196c03f
movl $0xa24, (%rbx) # imm = 0xA24
jmp 0x196c272
cmpl $0x44a, %eax # imm = 0x44A
jg 0x196bf74
cmpl $0x436, %eax # imm = 0x436
jne 0x196bfe1
movl $0xa11, (%rbx) # imm = 0xA11
jmp 0x196c220
movl $0xa21, (%rbx) # imm = 0xA21
jmp 0x196c29f
cmpl $0x52f, %eax # imm = 0x52F
je 0x196bf69
cmpl $0x530, %eax # imm = 0x530
jne 0x196bf3d
movl $0xa1e, (%rbx) # imm = 0xA1E
jmp 0x196c29f
movl $0xa1f, (%rbx) # imm = 0xA1F
jmp 0x196c29f
cmpl $0x835, %eax # imm = 0x835
je 0x196c07c
cmpl $0x8ed, %eax # imm = 0x8ED
jne 0x196c117
movl $0xa2c, (%rbx) # imm = 0xA2C
jmp 0x196c272
movl $0xa1d, (%rbx) # imm = 0xA1D
jmp 0x196c29f
cmpl $0x44b, %eax # imm = 0x44B
jne 0x196c101
movl $0xa08, (%rbx) # imm = 0xA08
jmp 0x196c208
cmpl $0x5cf, %eax # imm = 0x5CF
jne 0x196c13e
movl $0xa1c, (%rbx) # imm = 0xA1C
jmp 0x196c29f
cmpl $0x9b5, %eax # imm = 0x9B5
jne 0x196c149
movq 0x10(%r14), %rax
movq 0x28(%rax), %rdi
leaq 0x8(%rsp), %r15
movq %r15, %rsi
callq 0x28e340e
movq (%r15), %rax
cmpq $0x1, %rax
je 0x196c212
testq %rax, %rax
jne 0x196c29f
movl $0xa2f, (%rbx) # imm = 0xA2F
jmp 0x196c220
movq 0x10(%r14), %rax
movq 0x18(%rax), %rdi
leaq 0x8(%rsp), %r15
movq %r15, %rsi
callq 0x28e340e
movq (%r15), %rax
cmpq $0x3, %rax
ja 0x196c29f
leaq 0x2eeae1a(%rip), %rcx # 0x4856e24
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl $0xa03, (%rbx) # imm = 0xA03
jmp 0x196c208
cmpl $0x137, %eax # imm = 0x137
jne 0x196c195
movl $0xa10, (%rbx) # imm = 0xA10
jmp 0x196c220
movl $0xa23, (%rbx) # imm = 0xA23
jmp 0x196c208
movq 0x10(%r14), %rax
cmpl $0x93, 0x18(%rax)
jne 0x196c1b3
movl $0xa25, (%rbx) # imm = 0xA25
jmp 0x196c208
movl $0xa2b, (%rbx) # imm = 0xA2B
jmp 0x196c29f
cmpl $0x610, %eax # imm = 0x610
jne 0x196c1d4
movl $0xa1b, (%rbx) # imm = 0xA1B
jmp 0x196c272
movl $0xa2e, (%rbx) # imm = 0xA2E
jmp 0x196c28f
movl $0xa01, (%rbx) # imm = 0xA01
jmp 0x196c220
movq 0x10(%r14), %rax
movq 0x28(%rax), %rdi
leaq 0x8(%rsp), %rsi
callq 0x28e340e
testb %al, %al
je 0x196c26c
movq 0x8(%rsp), %rax
cmpq $-0x1, %rax
je 0x196c24f
cmpq $0x1, %rax
jne 0x196c257
movl $0xa0a, (%rbx) # imm = 0xA0A
jmp 0x196c220
movq 0x10(%r14), %rax
movq 0x18(%rax), %rdi
leaq 0x8(%rsp), %rsi
callq 0x28e340e
testb %al, %al
je 0x196c1ea
cmpq $-0x1, 0x8(%rsp)
jne 0x196c1ea
movl $0xa0c, (%rbx) # imm = 0xA0C
jmp 0x196c220
movl $0xa07, (%rbx) # imm = 0xA07
jmp 0x196c220
movl $0xa00, (%rbx) # imm = 0xA00
jmp 0x196c220
movl $0xa31, (%rbx) # imm = 0xA31
jmp 0x196c27f
movq 0x10(%r14), %rax
cmpl $0x93, 0x8(%rax)
je 0x196c247
movl $0xa2d, (%rbx) # imm = 0xA2D
jmp 0x196c272
movl $0xa22, (%rbx) # imm = 0xA22
jmp 0x196c272
movq 0x10(%r14), %rax
movq 0x28(%rax), %rdi
leaq 0x8(%rsp), %r15
movq %r15, %rsi
callq 0x28e340e
movq (%r15), %rax
cmpq $0x1, %rax
je 0x196c21a
testq %rax, %rax
jne 0x196c23a
movl $0xa34, (%rbx) # imm = 0xA34
jmp 0x196c220
movl $0xa0e, (%rbx) # imm = 0xA0E
jmp 0x196c220
movl $0x9ff, (%rbx) # imm = 0x9FF
jmp 0x196c220
movl $0x9fb, (%rbx) # imm = 0x9FB
jmp 0x196c272
movl $0xa0f, (%rbx) # imm = 0xA0F
jmp 0x196c220
movl $0xa02, (%rbx) # imm = 0xA02
jmp 0x196c27f
movl $0xa1a, (%rbx) # imm = 0xA1A
jmp 0x196c272
movl $0xa27, (%rbx) # imm = 0xA27
jmp 0x196c29f
movl $0xa28, (%rbx) # imm = 0xA28
jmp 0x196c29f
movl $0xa26, (%rbx) # imm = 0xA26
jmp 0x196c272
movl $0xa2a, (%rbx) # imm = 0xA2A
jmp 0x196c29f
movl $0xa0b, (%rbx) # imm = 0xA0B
jmp 0x196c220
movl $0xa05, (%rbx) # imm = 0xA05
jmp 0x196c208
movl $0xa06, (%rbx) # imm = 0xA06
jmp 0x196c208
movl $0xa04, (%rbx) # imm = 0xA04
movq %rbx, %rdi
movq %r14, %rsi
xorl %edx, %edx
jmp 0x196c28a
movl $0xa30, (%rbx) # imm = 0xA30
jmp 0x196c220
movl $0xa35, (%rbx) # imm = 0xA35
movq %rbx, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq 0x196c2e5
movq %rbx, %rdi
movq %r14, %rsi
movl $0x1, %edx
jmp 0x196c29a
movq 0x10(%r14), %rax
cmpl $0x93, 0x8(%rax)
jne 0x196c29f
movl $0xa33, (%rbx) # imm = 0xA33
jmp 0x196c27f
movl $0xa09, (%rbx) # imm = 0xA09
jmp 0x196c272
movq 0x10(%r14), %rax
cmpl $0x93, 0x18(%rax)
jne 0x196c26c
movl $0x9fc, (%rbx) # imm = 0x9FC
jmp 0x196c208
movl $0x9fa, (%rbx) # imm = 0x9FA
movq %rbx, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq 0x196c2e5
movq %rbx, %rdi
movq %r14, %rsi
movl $0x1, %edx
callq 0x196c2e5
movq %rbx, %rdi
movq %r14, %rsi
movl $0x2, %edx
callq 0x196c2e5
movq %rbx, %rax
addq $0x10, %rsp
popq %rbx
popq %r14
popq %r15
retq
|
/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
|
llvm::LanaiInstPrinter::printHi16ImmOperand(llvm::MCInst const*, unsigned int, llvm::raw_ostream&)
|
void LanaiInstPrinter::printHi16ImmOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &OS) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isImm()) {
OS << formatHex(Op.getImm() << 16);
} else {
// Symbolic operand will be lowered to immediate value by linker
assert(Op.isExpr() && "Expected an expression");
Op.getExpr()->print(OS, &MAI);
}
}
|
pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movq %rdi, %rax
movl %edx, %edx
movq 0x10(%rsi), %rsi
shlq $0x4, %rdx
leaq (%rsi,%rdx), %rcx
cmpb $0x2, (%rsi,%rdx)
jne 0x196cf6a
movq 0x8(%rcx), %rdx
shlq $0x10, %rdx
movq %rsp, %r14
movq %r14, %rdi
movq %rax, %rsi
callq 0x28e4a56
movq %rbx, %rdi
movq %r14, %rsi
callq 0x2b7d21a
addq $0x18, %rsp
popq %rbx
popq %r14
retq
movq 0x8(%rcx), %rdi
movq 0x10(%rax), %rdx
movq %rbx, %rsi
xorl %ecx, %ecx
addq $0x18, %rsp
popq %rbx
popq %r14
jmp 0x28e14a4
nop
|
/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp
|
llvm::LanaiInstPrinter::printMemoryStoreIncrement(llvm::MCInst const*, llvm::raw_ostream&, llvm::StringRef, int)
|
bool LanaiInstPrinter::printMemoryStoreIncrement(const MCInst *MI,
raw_ostream &OS,
StringRef Opcode,
int AddOffset) {
if (isPreIncrementForm(MI, AddOffset)) {
OS << "\t" << Opcode << "\t%" << getRegisterName(MI->getOperand(0).getReg())
<< ", [" << decIncOperator(MI) << "%"
<< getRegisterName(MI->getOperand(1).getReg()) << "]";
return true;
}
if (isPostIncrementForm(MI, AddOffset)) {
OS << "\t" << Opcode << "\t%" << getRegisterName(MI->getOperand(0).getReg())
<< ", [%" << getRegisterName(MI->getOperand(1).getReg())
<< decIncOperator(MI) << "]";
return true;
}
return false;
}
|
pushq %r15
pushq %r14
pushq %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %rdi
movq %rsi, %rbx
movq 0x10(%rsi), %rax
movq 0x38(%rax), %rcx
movl %ecx, %edx
andl $0x47, %edx
cmpl $0x40, %edx
jne 0x196d64c
movq 0x28(%rax), %rdx
movslq %r9d, %rsi
cmpq %rsi, %rdx
je 0x196d584
movl %r9d, %esi
negl %esi
movslq %esi, %rsi
cmpq %rsi, %rdx
jne 0x196d64c
leaq 0x35e88fd(%rip), %rsi # 0x4f55e88
movl $0x1, %edx
callq 0x7f9ba8
movq %rax, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq 0x7f9ba8
leaq 0x2eea273(%rip), %rsi # 0x485781d
movl $0x2, %edx
movq %rax, %rdi
callq 0x7f9ba8
movq 0x10(%rbx), %rcx
movl 0x8(%rcx), %ecx
decl %ecx
leaq 0x2eea309(%rip), %r14 # 0x48578d0
movzbl (%rcx,%r14), %esi
leaq 0x2eea26d(%rip), %r15 # 0x4857840
addq %r15, %rsi
movq %rax, %rdi
callq 0x7f9b78
leaq 0x2612fe2(%rip), %rsi # 0x3f805c7
movl $0x3, %edx
movq %rax, %rdi
callq 0x7f9ba8
movq 0x10(%rbx), %rcx
cmpq $0x0, 0x28(%rcx)
leaq 0x35a5ad5(%rip), %rcx # 0x4f130d7
leaq 0x372fd01(%rip), %rsi # 0x509d30a
cmovsq %rcx, %rsi
movl $0x2, %edx
movq %rax, %rdi
callq 0x7f9ba8
leaq 0x2eea1fd(%rip), %rsi # 0x485781e
movl $0x1, %edx
movq %rax, %rdi
callq 0x7f9ba8
movq 0x10(%rbx), %rcx
movl 0x18(%rcx), %ecx
decl %ecx
movzbl (%rcx,%r14), %esi
addq %r15, %rsi
movq %rax, %rdi
callq 0x7f9b78
jmp 0x196d728
andl $0x87, %ecx
cmpl $0x80, %ecx
jne 0x196d740
movq 0x28(%rax), %rax
movslq %r9d, %rcx
cmpq %rcx, %rax
je 0x196d679
negl %r9d
movslq %r9d, %rcx
cmpq %rcx, %rax
jne 0x196d740
leaq 0x35e8808(%rip), %rsi # 0x4f55e88
movl $0x1, %edx
callq 0x7f9ba8
movq %rax, %rdi
movq %r15, %rsi
movq %r14, %rdx
callq 0x7f9ba8
leaq 0x2eea17e(%rip), %rsi # 0x485781d
movl $0x2, %edx
movq %rax, %rdi
callq 0x7f9ba8
movq 0x10(%rbx), %rcx
movl 0x8(%rcx), %ecx
decl %ecx
leaq 0x2eea214(%rip), %r14 # 0x48578d0
movzbl (%rcx,%r14), %esi
leaq 0x2eea178(%rip), %r15 # 0x4857840
addq %r15, %rsi
movq %rax, %rdi
callq 0x7f9b78
leaq 0x2eea146(%rip), %rsi # 0x4857820
movl $0x4, %edx
movq %rax, %rdi
callq 0x7f9ba8
movq 0x10(%rbx), %rcx
movl 0x18(%rcx), %ecx
decl %ecx
movzbl (%rcx,%r14), %esi
addq %r15, %rsi
movq %rax, %rdi
callq 0x7f9b78
movq 0x10(%rbx), %rcx
cmpq $0x0, 0x28(%rcx)
leaq 0x35a59c7(%rip), %rcx # 0x4f130d7
leaq 0x372fbf3(%rip), %rsi # 0x509d30a
cmovsq %rcx, %rsi
movl $0x2, %edx
movq %rax, %rdi
callq 0x7f9ba8
leaq 0x365c2bb(%rip), %rsi # 0x4fc99ea
movl $0x1, %edx
movq %rax, %rdi
callq 0x7f9ba8
movb $0x1, %al
jmp 0x196d742
xorl %eax, %eax
popq %rbx
popq %r14
popq %r15
retq
|
/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp
|
(anonymous namespace)::LanaiELFObjectWriter::getRelocType(llvm::MCContext&, llvm::MCValue const&, llvm::MCFixup const&, bool) const
|
MCFixupKind getKind() const { return Kind; }
|
movl 0xc(%rcx), %eax
addl $-0x80, %eax
cmpl $0x6, %eax
ja 0x196e204
leaq 0x2eef3d0(%rip), %rcx # 0x485d5c8
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
xorl %eax, %eax
retq
movl $0x4, %eax
retq
movl $0x3, %eax
retq
movl $0x1, %eax
retq
movl $0x2, %eax
retq
movl $0x5, %eax
retq
movl $0x6, %eax
retq
|
/llvm/MC/MCFixup.h
|
llvm::LoongArchMCExpr::printImpl(llvm::raw_ostream&, llvm::MCAsmInfo const*) const
|
void LoongArchMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
VariantKind Kind = getKind();
bool HasVariant =
((Kind != VK_LoongArch_None) && (Kind != VK_LoongArch_CALL));
if (HasVariant)
OS << '%' << getVariantKindName(getKind()) << '(';
Expr->print(OS, MAI);
if (HasVariant)
OS << ')';
}
|
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r14
movq %rsi, %rbx
movq %rdi, %r15
cmpl $0x2, 0x20(%rdi)
jb 0x196f4d1
movq 0x20(%rbx), %rax
cmpq 0x18(%rbx), %rax
jae 0x196f4ed
leaq 0x1(%rax), %rcx
movq %rcx, 0x20(%rbx)
movb $0x25, (%rax)
movq %rbx, %r12
jmp 0x196f4fd
movq 0x18(%r15), %rdi
movq %rbx, %rsi
movq %r14, %rdx
xorl %ecx, %ecx
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
jmp 0x28e14a4
movq %rbx, %rdi
movl $0x25, %esi
callq 0x2b7d68e
movq %rax, %r12
movl 0x20(%r15), %edi
callq 0x196f580
movq %r12, %rdi
movq %rax, %rsi
callq 0x7f9ba8
movq 0x20(%rax), %rcx
cmpq 0x18(%rax), %rcx
jae 0x196f528
leaq 0x1(%rcx), %rdx
movq %rdx, 0x20(%rax)
movb $0x28, (%rcx)
jmp 0x196f535
movq %rax, %rdi
movl $0x28, %esi
callq 0x2b7d68e
movq 0x18(%r15), %rdi
movq %rbx, %rsi
movq %r14, %rdx
xorl %ecx, %ecx
callq 0x28e14a4
movq 0x20(%rbx), %rax
cmpq 0x18(%rbx), %rax
jae 0x196f567
leaq 0x1(%rax), %rcx
movq %rcx, 0x20(%rbx)
movb $0x29, (%rax)
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
movq %rbx, %rdi
movl $0x29, %esi
addq $0x8, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
jmp 0x2b7d68e
nop
|
/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
|
(anonymous namespace)::LoongArchMCInstrAnalysis::evaluateBranch(llvm::MCInst const&, unsigned long, unsigned long, unsigned long&) const
|
bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const override {
unsigned NumOps = Inst.getNumOperands();
if ((isBranch(Inst) && !isIndirectBranch(Inst)) ||
Inst.getOpcode() == LoongArch::BL) {
Target = Addr + Inst.getOperand(NumOps - 1).getImm();
return true;
}
return false;
}
|
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl 0x18(%rsi), %r13d
movq (%rdi), %rax
callq *0x20(%rax)
testb %al, %al
je 0x19706a8
movq (%r12), %rax
movq %r12, %rdi
movq %r15, %rsi
callq *0x38(%rax)
testb %al, %al
je 0x19706b5
cmpl $0x1f0, (%r15) # imm = 0x1F0
je 0x19706b5
xorl %eax, %eax
jmp 0x19706ca
decl %r13d
movq 0x10(%r15), %rax
shlq $0x4, %r13
addq 0x8(%rax,%r13), %r14
movq %r14, (%rbx)
movb $0x1, %al
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
retq
|
/Target/LoongArch/MCTargetDesc/LoongArchMCTargetDesc.cpp
|
llvm::LoongArchAsmBackend::shouldInsertExtraNopBytesForCodeAlign(llvm::MCAlignFragment const&, unsigned int&)
|
const MCSubtargetInfo *getSubtargetInfo() const { return STI; }
|
movq 0x30(%rsi), %rcx
xorl %eax, %eax
testb $0x2, 0xd9(%rcx)
je 0x1971eaa
cmpl $0x4, 0x2c(%rsi)
jb 0x1971eaa
movb 0x1e(%rsi), %cl
movl $0x1, %eax
shlq %cl, %rax
addl $-0x4, %eax
movl %eax, (%rdx)
cmpb $0x3, 0x1e(%rsi)
setae %al
retq
nop
|
/llvm/MC/MCFragment.h
|
fixELFSymbolsInTLSFixupsImpl(llvm::MCExpr const*, llvm::MCAssembler&)
|
static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {
switch (Expr->getKind()) {
case MCExpr::Target:
fixELFSymbolsInTLSFixupsImpl(cast<MipsMCExpr>(Expr)->getSubExpr(), Asm);
break;
case MCExpr::Constant:
break;
case MCExpr::Binary: {
const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
fixELFSymbolsInTLSFixupsImpl(BE->getLHS(), Asm);
fixELFSymbolsInTLSFixupsImpl(BE->getRHS(), Asm);
break;
}
case MCExpr::SymbolRef: {
// We're known to be under a TLS fixup, so any symbol should be
// modified. There should be only one.
const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
cast<MCSymbolELF>(SymRef.getSymbol()).setType(ELF::STT_TLS);
break;
}
case MCExpr::Unary:
fixELFSymbolsInTLSFixupsImpl(cast<MCUnaryExpr>(Expr)->getSubExpr(), Asm);
break;
}
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rdi, %rbx
leaq 0x2f1c07d(%rip), %r14 # 0x4893c80
movzbl (%rbx), %eax
cmpq $0x4, %rax
ja 0x1977c3f
movslq (%r14,%rax,4), %rax
addq %r14, %rax
jmpq *%rax
movq 0x10(%rbx), %rdi
callq 0x1977bf5
movq 0x18(%rbx), %rbx
jmp 0x1977c03
movq 0x10(%rbx), %rbx
jmp 0x1977c03
movq 0x10(%rbx), %rdi
movl $0x6, %esi
addq $0x8, %rsp
popq %rbx
popq %r14
jmp 0x28fb0f8
addq $0x8, %rsp
popq %rbx
popq %r14
retq
nop
|
/Target/Mips/MCTargetDesc/MipsMCExpr.cpp
|
llvm::isBasePlusOffsetMemoryAccess(unsigned int, unsigned int*, bool*)
|
bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
bool *IsStore) {
if (IsStore)
*IsStore = false;
switch (Opcode) {
default:
return false;
// Load instructions with base address register in position 1.
case Mips::LB:
case Mips::LBu:
case Mips::LH:
case Mips::LHu:
case Mips::LW:
case Mips::LWC1:
case Mips::LDC1:
case Mips::LL:
case Mips::LL_R6:
case Mips::LWL:
case Mips::LWR:
*AddrIdx = 1;
return true;
// Store instructions with base address register in position 1.
case Mips::SB:
case Mips::SH:
case Mips::SW:
case Mips::SWC1:
case Mips::SDC1:
case Mips::SWL:
case Mips::SWR:
*AddrIdx = 1;
if (IsStore)
*IsStore = true;
return true;
// Store instructions with base address register in position 2.
case Mips::SC:
case Mips::SC_R6:
*AddrIdx = 2;
if (IsStore)
*IsStore = true;
return true;
}
}
|
testq %rdx, %rdx
je 0x1978418
movb $0x0, (%rdx)
xorl %eax, %eax
cmpl $0x996, %edi # imm = 0x996
jg 0x1978461
leal -0x743(%rdi), %ecx
cmpl $0x38, %ecx
ja 0x197843d
movabsq $0x102020000010401, %rdx # imm = 0x102020000010401
btq %rcx, %rdx
jb 0x1978458
addl $0xfffff87c, %edi # imm = 0xFFFFF87C
cmpl $0x24, %edi
ja 0x1978460
movabsq $0x1002004801, %rcx # imm = 0x1002004801
btq %rdi, %rcx
jae 0x1978460
movl $0x1, (%rsi)
movb $0x1, %al
retq
cmpl $0x9af, %edi # imm = 0x9AF
jg 0x1978489
cmpl $0x997, %edi # imm = 0x997
je 0x19784a0
cmpl $0x99f, %edi # imm = 0x99F
je 0x1978481
cmpl $0x9a8, %edi # imm = 0x9A8
jne 0x1978460
movl $0x2, (%rsi)
jmp 0x19784a6
leal -0xab3(%rdi), %ecx
cmpl $0x17, %ecx
ja 0x19784b1
movl $0x804011, %r8d # imm = 0x804011
btl %ecx, %r8d
jae 0x19784b1
movl $0x1, (%rsi)
movb $0x1, %al
testq %rdx, %rdx
je 0x1978460
movb $0x1, (%rdx)
retq
cmpl $0x9b0, %edi # imm = 0x9B0
je 0x19784a0
cmpl $0x9d9, %edi # imm = 0x9D9
je 0x19784a0
jmp 0x1978460
|
/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
|
llvm::MipsTargetStreamer::emitLoadWithImmOffset(unsigned int, unsigned int, unsigned int, long, unsigned int, llvm::SMLoc, llvm::MCSubtargetInfo const*)
|
void MipsTargetStreamer::emitLoadWithImmOffset(unsigned Opcode, unsigned DstReg,
unsigned BaseReg, int64_t Offset,
unsigned TmpReg, SMLoc IDLoc,
const MCSubtargetInfo *STI) {
if (isInt<16>(Offset)) {
emitRRI(Opcode, DstReg, BaseReg, Offset, IDLoc, STI);
return;
}
// 1) lw $8, offset($9) => lui $8, %hi(offset)
// add $8, $8, $9
// lw $8, %lo(offset)($9)
// 2) lw $8, offset($8) => lui $at, %hi(offset)
// add $at, $at, $8
// lw $8, %lo(offset)($at)
unsigned LoOffset = Offset & 0x0000ffff;
unsigned HiOffset = (Offset & 0xffff0000) >> 16;
// If msb of LoOffset is 1(negative number) we must increment HiOffset
// to account for the sign-extension of the low part.
if (LoOffset & 0x8000)
HiOffset++;
// Generate the base address in TmpReg.
emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI);
if (BaseReg != Mips::ZERO)
emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
// Emit the load with the adjusted base and offset.
emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI);
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, %r14
movl %ecx, %r13d
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %r12
movswq %r14w, %rax
cmpq %r8, %rax
jne 0x197928e
movl %r13d, %ebx
jmp 0x19792fe
movl %r9d, %ebx
movq 0x58(%rsp), %rax
movq 0x50(%rsp), %r9
movl %r14d, %r8d
shrl $0x10, %r8d
btl $0xf, %r14d
adcl $0x0, %r8d
subq $0x8, %rsp
movq %r12, %rdi
movl $0x78c, %esi # imm = 0x78C
movl %ebx, %edx
movl $0x2, %ecx
movq %r9, 0x18(%rsp)
movq %rax, 0x10(%rsp)
pushq %rax
callq 0x1978cca
addq $0x10, %rsp
cmpl $0x15, %r13d
je 0x19792fe
movl %r13d, %r9d
movq %r12, %rdi
movl $0x340, %esi # imm = 0x340
movl %ebx, %edx
movl %ebx, %ecx
movl $0x1, %r8d
pushq 0x8(%rsp)
pushq 0x18(%rsp)
callq 0x1978e40
addq $0x10, %rsp
movswq %r14w, %r9
movq %r12, %rdi
movl %r15d, %esi
movl %ebp, %edx
movl %ebx, %ecx
movl $0x2, %r8d
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
jmp 0x1978e40
nop
|
/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
|
llvm::MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned int, int, llvm::MCSymbol const&, bool)
|
void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
int RegOrOffset,
const MCSymbol &Sym,
bool IsReg) {
OS << "\t.cpsetup\t$"
<< StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
if (IsReg)
OS << "$"
<< StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
else
OS << RegOrOffset;
OS << ", ";
OS << Sym.getName();
forbidModuleDirective();
}
|
pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movl %r8d, %r15d
movq %rcx, %r14
movl %edx, %ebp
movl %esi, %r13d
movq %rdi, %rbx
movq 0x68(%rdi), %rdi
leaq 0x2f4ec12(%rip), %rsi # 0x48c8cb5
movl $0xb, %edx
callq 0x7f9ba8
movq %rax, %r12
movl %r13d, %edi
callq 0x1976e58
movq %rax, 0x8(%rsp)
testq %rax, %rax
je 0x197a0cc
movq %rax, %rdi
callq 0x7802c0
jmp 0x197a0ce
xorl %eax, %eax
leaq 0x8(%rsp), %rsi
movq %rax, 0x8(%rsi)
leaq 0x18(%rsp), %r13
movq %r13, %rdi
callq 0x2b56b9e
movq (%r13), %rsi
movq 0x8(%r13), %rdx
movq %r12, %rdi
callq 0x2b7d704
leaq 0x26064d2(%rip), %rsi # 0x3f805cd
movl $0x2, %edx
movq %rax, %rdi
callq 0x7f9ba8
movq (%r13), %rdi
leaq 0x28(%rsp), %r13
cmpq %r13, %rdi
je 0x197a123
movq 0x28(%rsp), %rsi
incq %rsi
callq 0x7800d0
movq 0x68(%rbx), %rdi
testb %r15b, %r15b
je 0x197a15b
leaq 0x2f4eb67(%rip), %rsi # 0x48c8c9a
movl $0x1, %edx
callq 0x7f9ba8
movq %rax, %r15
movl %ebp, %edi
callq 0x1976e58
movq %rax, 0x8(%rsp)
testq %rax, %rax
je 0x197a165
movq %rax, %rdi
callq 0x7802c0
jmp 0x197a167
movslq %ebp, %rsi
callq 0x2b7d122
jmp 0x197a1a4
xorl %eax, %eax
leaq 0x8(%rsp), %rsi
movq %rax, 0x8(%rsi)
leaq 0x18(%rsp), %r12
movq %r12, %rdi
callq 0x2b56b9e
movq (%r12), %rsi
movq 0x8(%r12), %rdx
movq %r15, %rdi
callq 0x2b7d704
movq (%r12), %rdi
cmpq %r13, %rdi
je 0x197a1a4
movq 0x28(%rsp), %rsi
incq %rsi
callq 0x7800d0
movq 0x68(%rbx), %rdi
leaq 0x260641e(%rip), %rsi # 0x3f805cd
movl $0x2, %edx
callq 0x7f9ba8
movq 0x68(%rbx), %rdi
xorl %esi, %esi
testb $0x1, 0x8(%r14)
movl $0x0, %edx
je 0x197a1d6
movq -0x8(%r14), %rsi
movq (%rsi), %rdx
addq $0x18, %rsi
callq 0x7f9ba8
movb $0x0, 0x64(%rbx)
addq $0x38, %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
retq
|
/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
|
llvm::operator<<(llvm::MCStreamer&, llvm::MipsABIFlagsSection&)
|
MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) {
// Write out a Elf_Internal_ABIFlags_v0 struct
OS.emitIntValue(ABIFlagsSection.getVersionValue(), 2); // version
OS.emitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level
OS.emitIntValue(ABIFlagsSection.getISARevisionValue(), 1); // isa_rev
OS.emitIntValue(ABIFlagsSection.getGPRSizeValue(), 1); // gpr_size
OS.emitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1); // cpr1_size
OS.emitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1); // cpr2_size
OS.emitIntValue(ABIFlagsSection.getFpABIValue(), 1); // fp_abi
OS.emitIntValue(ABIFlagsSection.getISAExtensionValue(), 4); // isa_ext
OS.emitIntValue(ABIFlagsSection.getASESetValue(), 4); // ases
OS.emitIntValue(ABIFlagsSection.getFlags1Value(), 4); // flags1
OS.emitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2
return OS;
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movzwl (%rsi), %esi
movq (%rdi), %rax
movl $0x2, %edx
callq *0x208(%rax)
movzbl 0x2(%r14), %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x1, %edx
callq *0x208(%rax)
movzbl 0x3(%r14), %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x1, %edx
callq *0x208(%rax)
movzbl 0x4(%r14), %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x1, %edx
callq *0x208(%rax)
movl 0x1c(%r14), %eax
cmpl $0x1, %eax
movzbl 0x8(%r14), %esi
cmovel %eax, %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x1, %edx
callq *0x208(%rax)
movzbl 0xc(%r14), %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x1, %edx
callq *0x208(%rax)
movl 0x1c(%r14), %esi
leaq 0x2f4db20(%rip), %rax # 0x48c8dcc
movslq (%rax,%rsi,4), %rcx
addq %rax, %rcx
jmpq *%rcx
movl $0x5, %esi
jmp 0x197b2df
movl $0x3, %esi
jmp 0x197b2df
movl $0x1, %esi
jmp 0x197b2df
movl $0x1, %esi
cmpb $0x1, 0x19(%r14)
jne 0x197b2df
movzbl 0x18(%r14), %esi
xorq $0x7, %rsi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x1, %edx
callq *0x208(%rax)
movl 0x10(%r14), %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x4, %edx
callq *0x208(%rax)
movl 0x14(%r14), %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x4, %edx
callq *0x208(%rax)
movzbl 0x18(%r14), %esi
movq (%rbx), %rax
movq %rbx, %rdi
movl $0x4, %edx
callq *0x208(%rax)
movq (%rbx), %rax
movq %rbx, %rdi
xorl %esi, %esi
movl $0x4, %edx
callq *0x208(%rax)
movq %rbx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
retq
nop
|
/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp
|
llvm::MipsAsmBackend::MipsAsmBackend(llvm::Target const&, llvm::MCRegisterInfo const&, llvm::Triple const&, llvm::StringRef, bool)
|
MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
StringRef CPU, bool N32)
: MCAsmBackend(TT.isLittleEndian() ? llvm::endianness::little
: llvm::endianness::big),
TheTriple(TT), IsN32(N32) {}
|
pushq %rbp
pushq %r14
pushq %rbx
movq %rcx, %r14
movq %rdi, %rbx
movb 0x20(%rsp), %bpl
movq %rcx, %rdi
callq 0x2b0584a
movzbl %al, %esi
movq %rbx, %rdi
movl $0x528, %edx # imm = 0x528
callq 0x28c990c
leaq 0x3ecee94(%rip), %rax # 0x584afa0
movq %rax, (%rbx)
leaq 0x10(%rbx), %rdi
leaq 0x20(%rbx), %rax
movq %rax, 0x10(%rbx)
movq (%r14), %rsi
movq 0x8(%r14), %rdx
addq %rsi, %rdx
callq 0x7fc9f8
movq 0x30(%r14), %rax
movq %rax, 0x40(%rbx)
movups 0x20(%r14), %xmm0
movups %xmm0, 0x30(%rbx)
movb %bpl, 0x48(%rbx)
popq %rbx
popq %r14
popq %rbp
retq
|
/Target/Mips/MCTargetDesc/MipsAsmBackend.h
|
llvm::MipsMCCodeEmitter::getBranchTargetOpValueMMR6(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
|
unsigned MipsMCCodeEmitter::
getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 2.
if (MO.isImm())
return MO.getImm() >> 1;
assert(MO.isExpr() &&
"getBranchTargetOpValueMMR6 expects only expressions or immediates");
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
Fixups.push_back(MCFixup::create(0, FixupExpression,
MCFixupKind(Mips::fixup_Mips_PC16)));
return 0;
}
|
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movl %edx, %ecx
movq 0x10(%rsi), %rdx
shlq $0x4, %rcx
leaq (%rdx,%rcx), %rax
cmpb $0x2, (%rdx,%rcx)
jne 0x1981383
movq 0x8(%rax), %r14
shrq %r14
jmp 0x1981401
movq %rdi, %r15
movq 0x8(%rax), %r12
movq 0x10(%rdi), %rsi
xorl %r14d, %r14d
movq $-0x2, %rdi
xorl %edx, %edx
xorl %ecx, %ecx
callq 0x28e1cba
movq 0x10(%r15), %rcx
xorl %edi, %edi
movq %r12, %rsi
movq %rax, %rdx
xorl %r8d, %r8d
callq 0x28e1c22
xorps %xmm0, %xmm0
movq %rsp, %rsi
movaps %xmm0, (%rsi)
movq $0x0, 0x10(%rsi)
movq %rax, (%rsi)
movabsq $0x8900000000, %rax # imm = 0x8900000000
movq %rax, 0x8(%rsi)
movl $0x1, %edx
movq %rbx, %rdi
callq 0x18a7ff6
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
movq 0x10(%rax), %rsi
movq %rsi, 0x10(%rcx,%rdx,8)
movups (%rax), %xmm0
movups %xmm0, (%rcx,%rdx,8)
incl 0x8(%rbx)
movl %r14d, %eax
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
|
/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
|
llvm::MipsMCCodeEmitter::getBranchTarget21OpValueMM(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
|
unsigned MipsMCCodeEmitter::
getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 4.
if (MO.isImm()) return MO.getImm() >> 2;
assert(MO.isExpr() &&
"getBranchTarget21OpValueMM expects only expressions or immediates");
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
Fixups.push_back(MCFixup::create(0, FixupExpression,
MCFixupKind(Mips::fixup_MICROMIPS_PC21_S1)));
return 0;
}
|
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movl %edx, %ecx
movq 0x10(%rsi), %rdx
shlq $0x4, %rcx
leaq (%rdx,%rcx), %rax
cmpb $0x2, (%rdx,%rcx)
jne 0x198172a
movq 0x8(%rax), %r14
shrq $0x2, %r14
jmp 0x19817a8
movq %rdi, %r15
movq 0x8(%rax), %r12
movq 0x10(%rdi), %rsi
xorl %r14d, %r14d
movq $-0x4, %rdi
xorl %edx, %edx
xorl %ecx, %ecx
callq 0x28e1cba
movq 0x10(%r15), %rcx
xorl %edi, %edi
movq %r12, %rsi
movq %rax, %rdx
xorl %r8d, %r8d
callq 0x28e1c22
xorps %xmm0, %xmm0
movq %rsp, %rsi
movaps %xmm0, (%rsi)
movq $0x0, 0x10(%rsi)
movq %rax, (%rsi)
movabsq $0xb600000000, %rax # imm = 0xB600000000
movq %rax, 0x8(%rsi)
movl $0x1, %edx
movq %rbx, %rdi
callq 0x18a7ff6
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
movq 0x10(%rax), %rsi
movq %rsi, 0x10(%rcx,%rdx,8)
movups (%rax), %xmm0
movups %xmm0, (%rcx,%rdx,8)
incl 0x8(%rbx)
movl %r14d, %eax
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
nop
|
/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
|
llvm::MipsMCCodeEmitter::getBranchTarget26OpValue(llvm::MCInst const&, unsigned int, llvm::SmallVectorImpl<llvm::MCFixup>&, llvm::MCSubtargetInfo const&) const
|
unsigned MipsMCCodeEmitter::
getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
// If the destination is an immediate, divide by 4.
if (MO.isImm()) return MO.getImm() >> 2;
assert(MO.isExpr() &&
"getBranchTarget26OpValue expects only expressions or immediates");
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
Fixups.push_back(MCFixup::create(0, FixupExpression,
MCFixupKind(Mips::fixup_MIPS_PC26_S2)));
return 0;
}
|
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %rcx, %rbx
movl %edx, %ecx
movq 0x10(%rsi), %rdx
shlq $0x4, %rcx
leaq (%rdx,%rcx), %rax
cmpb $0x2, (%rdx,%rcx)
jne 0x19817e4
movq 0x8(%rax), %r14
shrq $0x2, %r14
jmp 0x1981862
movq %rdi, %r15
movq 0x8(%rax), %r12
movq 0x10(%rdi), %rsi
xorl %r14d, %r14d
movq $-0x4, %rdi
xorl %edx, %edx
xorl %ecx, %ecx
callq 0x28e1cba
movq 0x10(%r15), %rcx
xorl %edi, %edi
movq %r12, %rsi
movq %rax, %rdx
xorl %r8d, %r8d
callq 0x28e1c22
xorps %xmm0, %xmm0
movq %rsp, %rsi
movaps %xmm0, (%rsi)
movq $0x0, 0x10(%rsi)
movq %rax, (%rsi)
movabsq $0xa900000000, %rax # imm = 0xA900000000
movq %rax, 0x8(%rsi)
movl $0x1, %edx
movq %rbx, %rdi
callq 0x18a7ff6
movq (%rbx), %rcx
movl 0x8(%rbx), %edx
leaq (%rdx,%rdx,2), %rdx
movq 0x10(%rax), %rsi
movq %rsi, 0x10(%rcx,%rdx,8)
movups (%rax), %xmm0
movups %xmm0, (%rcx,%rdx,8)
incl 0x8(%rbx)
movl %r14d, %eax
addq $0x18, %rsp
popq %rbx
popq %r12
popq %r14
popq %r15
retq
nop
|
/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
|
llvm::MipsRegInfoRecord::EmitMipsOptionRecord()
|
void MipsRegInfoRecord::EmitMipsOptionRecord() {
MipsTargetStreamer *MTS =
static_cast<MipsTargetStreamer *>(Streamer->getTargetStreamer());
Streamer->pushSection();
// We need to distinguish between N64 and the rest because at the moment
// we don't emit .Mips.options for other ELFs other than N64.
// Since .reginfo has the same information as .Mips.options (ODK_REGINFO),
// we can use the same abstraction (MipsRegInfoRecord class) to handle both.
if (MTS->getABI().IsN64()) {
// The EntrySize value of 1 seems strange since the records are neither
// 1-byte long nor fixed length but it matches the value GAS emits.
MCSectionELF *Sec =
Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS,
ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP, 1);
Sec->setAlignment(Align(8));
Streamer->switchSection(Sec);
Streamer->emitInt8(ELF::ODK_REGINFO); // kind
Streamer->emitInt8(40); // size
Streamer->emitInt16(0); // section
Streamer->emitInt32(0); // info
Streamer->emitInt32(ri_gprmask);
Streamer->emitInt32(0); // pad
Streamer->emitInt32(ri_cprmask[0]);
Streamer->emitInt32(ri_cprmask[1]);
Streamer->emitInt32(ri_cprmask[2]);
Streamer->emitInt32(ri_cprmask[3]);
Streamer->emitIntValue(ri_gp_value, 8);
} else {
MCSectionELF *Sec = Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO,
ELF::SHF_ALLOC, 24);
Sec->setAlignment(MTS->getABI().IsN32() ? Align(8) : Align(4));
Streamer->switchSection(Sec);
Streamer->emitInt32(ri_gprmask);
Streamer->emitInt32(ri_cprmask[0]);
Streamer->emitInt32(ri_cprmask[1]);
Streamer->emitInt32(ri_cprmask[2]);
Streamer->emitInt32(ri_cprmask[3]);
assert((ri_gp_value & 0xffffffff) == ri_gp_value);
Streamer->emitInt32(ri_gp_value);
}
Streamer->popSection();
}
|
pushq %r14
pushq %rbx
subq $0x58, %rsp
movq %rdi, %rbx
movq 0x8(%rdi), %rdi
movq 0x10(%rdi), %r14
callq 0xac0e72
cmpl $0x3, 0x10(%r14)
movq 0x10(%rbx), %rdi
jne 0x1982818
leaq 0x2f50113(%rip), %rax # 0x48d27f0
leaq 0x8(%rsp), %rsi
movq %rax, (%rsi)
movw $0x103, 0x20(%rsi) # imm = 0x103
leaq 0x30(%rsp), %r9
movw $0x101, 0x20(%r9) # imm = 0x101
subq $0x8, %rsp
movl $0x7000000d, %edx # imm = 0x7000000D
movl $0x8000002, %ecx # imm = 0x8000002
movl $0x1, %r8d
pushq $0x0
pushq $-0x1
pushq $0x0
callq 0x28d38c0
addq $0x20, %rsp
movb $0x3, 0x20(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rcx
movq %rax, %rsi
xorl %edx, %edx
callq *0xa8(%rcx)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x1, %esi
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x28, %esi
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
xorl %esi, %esi
movl $0x2, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
xorl %esi, %esi
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movl 0x60(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
xorl %esi, %esi
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movl 0x64(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movl 0x68(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movl 0x6c(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movl 0x70(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq 0x78(%rbx), %rsi
movq (%rdi), %rax
movl $0x8, %edx
jmp 0x19828f5
leaq 0x2f4ffdf(%rip), %rax # 0x48d27fe
leaq 0x8(%rsp), %rsi
movq %rax, (%rsi)
movw $0x103, 0x20(%rsi) # imm = 0x103
leaq 0x30(%rsp), %r9
movw $0x101, 0x20(%r9) # imm = 0x101
subq $0x8, %rsp
movl $0x70000006, %edx # imm = 0x70000006
movl $0x2, %ecx
movl $0x18, %r8d
pushq $0x0
pushq $-0x1
pushq $0x0
callq 0x28d38c0
addq $0x20, %rsp
cmpl $0x2, 0x10(%r14)
sete %cl
orb $0x2, %cl
movb %cl, 0x20(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rcx
movq %rax, %rsi
xorl %edx, %edx
callq *0xa8(%rcx)
movq 0x8(%rbx), %rdi
movl 0x60(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movl 0x64(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movl 0x68(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movl 0x6c(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movl 0x70(%rbx), %esi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq 0x78(%rbx), %rsi
movq (%rdi), %rax
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
callq 0x28f8a44
addq $0x58, %rsp
popq %rbx
popq %r14
retq
|
/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
|
llvm::MSP430TargetELFStreamer::MSP430TargetELFStreamer(llvm::MCStreamer&, llvm::MCSubtargetInfo const&)
|
MSP430TargetELFStreamer::MSP430TargetELFStreamer(MCStreamer &S,
const MCSubtargetInfo &STI)
: MCTargetStreamer(S) {
// Emit build attributes section according to
// MSP430 EABI (slaa534.pdf, part 13).
MCSection *AttributeSection = getStreamer().getContext().getELFSection(
".MSP430.attributes", ELF::SHT_MSP430_ATTRIBUTES, 0);
Streamer.switchSection(AttributeSection);
// Format version.
Streamer.emitInt8(0x41);
// Subsection length.
Streamer.emitInt32(22);
// Vendor name string, zero-terminated.
Streamer.emitBytes("mspabi");
Streamer.emitInt8(0);
// Attribute vector scope tag. 1 stands for the entire file.
Streamer.emitInt8(1);
// Attribute vector length.
Streamer.emitInt32(11);
Streamer.emitInt8(TagISA);
Streamer.emitInt8(STI.hasFeature(MSP430::FeatureX) ? ISAMSP430X : ISAMSP430);
Streamer.emitInt8(TagCodeModel);
Streamer.emitInt8(CMSmall);
Streamer.emitInt8(TagDataModel);
Streamer.emitInt8(DMSmall);
// Don't emit TagEnumSize, for full GCC compatibility.
}
|
pushq %r14
pushq %rbx
subq $0x58, %rsp
movq %rdx, %r14
movq %rdi, %rbx
callq 0x28f5928
leaq 0x3ec8137(%rip), %rax # 0x584bc60
movq %rax, (%rbx)
movq 0x8(%rbx), %rax
movq 0x8(%rax), %rdi
leaq 0x2f581b5(%rip), %rax # 0x48dbcf0
leaq 0x8(%rsp), %rsi
movq %rax, (%rsi)
movw $0x103, 0x20(%rsi) # imm = 0x103
leaq 0x30(%rsp), %r9
movw $0x101, 0x20(%r9) # imm = 0x101
subq $0x8, %rsp
movl $0x70000003, %edx # imm = 0x70000003
xorl %ecx, %ecx
xorl %r8d, %r8d
pushq $0x0
pushq $-0x1
pushq $0x0
callq 0x28d38c0
addq $0x20, %rsp
movq 0x8(%rbx), %rdi
movq (%rdi), %rcx
movq %rax, %rsi
xorl %edx, %edx
callq *0xa8(%rcx)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x41, %esi
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x16, %esi
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
leaq 0x2f58143(%rip), %rsi # 0x48dbd03
movl $0x6, %edx
callq *0x1f0(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
xorl %esi, %esi
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x1, %esi
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0xb, %esi
movl $0x4, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x4, %esi
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq 0xd8(%r14), %rax
andl $0x8, %eax
cmpq $0x1, %rax
movl $0x2, %esi
sbbq $0x0, %rsi
movq (%rdi), %rax
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x6, %esi
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x1, %esi
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x8, %esi
movl $0x1, %edx
callq *0x208(%rax)
movq 0x8(%rbx), %rdi
movq (%rdi), %rax
movl $0x1, %esi
movl $0x1, %edx
callq *0x208(%rax)
addq $0x58, %rsp
popq %rbx
popq %r14
retq
nop
|
/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp
|
LLVMInitializeNVPTXTargetMC
|
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTargetMC() {
for (Target *T : {&getTheNVPTXTarget32(), &getTheNVPTXTarget64()}) {
// Register the MC asm info.
RegisterMCAsmInfo<NVPTXMCAsmInfo> X(*T);
// Register the MC instruction info.
TargetRegistry::RegisterMCInstrInfo(*T, createNVPTXMCInstrInfo);
// Register the MC register info.
TargetRegistry::RegisterMCRegInfo(*T, createNVPTXMCRegisterInfo);
// Register the MC subtarget info.
TargetRegistry::RegisterMCSubtargetInfo(*T, createNVPTXMCSubtargetInfo);
// Register the MCInstPrinter.
TargetRegistry::RegisterMCInstPrinter(*T, createNVPTXMCInstPrinter);
// Register the MCTargetStreamer.
TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer);
// Register the MCTargetStreamer.
TargetRegistry::RegisterNullTargetStreamer(*T, createNullTargetStreamer);
}
}
|
subq $0x18, %rsp
callq 0x19f4438
movq %rax, 0x8(%rsp)
callq 0x19f4456
movq %rax, 0x10(%rsp)
xorl %eax, %eax
leaq 0x321(%rip), %rcx # 0x1992846
leaq 0x5c(%rip), %rdx # 0x1992588
leaq 0x9b(%rip), %rsi # 0x19925ce
leaq 0x16b(%rip), %rdi # 0x19926a5
leaq 0x24d(%rip), %r8 # 0x199278e
leaq 0x28d(%rip), %r9 # 0x19927d5
leaq 0x2b0(%rip), %r10 # 0x19927ff
movq 0x8(%rsp,%rax), %r11
movq %rcx, 0x30(%r11)
movq %rdx, 0x40(%r11)
movq %rsi, 0x50(%r11)
movq %rdi, 0x58(%r11)
movq %r8, 0x88(%r11)
movq %r9, 0xc0(%r11)
movq %r10, 0xb8(%r11)
addq $0x8, %rax
cmpq $0x10, %rax
jne 0x199254f
addq $0x18, %rsp
retq
|
/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
|
createNVPTXMCInstrInfo()
|
static MCInstrInfo *createNVPTXMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitNVPTXMCInstrInfo(X);
return X;
}
|
pushq %rax
movl $0x30, %edi
callq 0x7808d0
xorps %xmm0, %xmm0
movaps %xmm0, (%rax)
movaps %xmm0, 0x10(%rax)
movaps %xmm0, 0x20(%rax)
leaq 0x2fad088(%rip), %rcx # 0x493f630
movq %rcx, (%rax)
leaq 0x2fd99ae(%rip), %rcx # 0x496bf60
movq %rcx, 0x8(%rax)
leaq 0x2fb52c3(%rip), %rcx # 0x4947880
movq %rcx, 0x10(%rax)
movups %xmm0, 0x18(%rax)
movl $0x1fea, 0x28(%rax) # imm = 0x1FEA
popq %rcx
retq
|
/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp
|
llvm::NVPTXMCAsmInfo::NVPTXMCAsmInfo(llvm::Triple const&, llvm::MCTargetOptions const&)
|
NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple,
const MCTargetOptions &Options) {
if (TheTriple.getArch() == Triple::nvptx64) {
CodePointerSize = CalleeSaveStackSlotSize = 8;
}
CommentString = "//";
HasSingleParameterDotFile = false;
InlineAsmStart = " begin inline asm";
InlineAsmEnd = " end inline asm";
SupportsDebugInformation = true;
// PTX does not allow .align on functions.
HasFunctionAlignment = false;
HasDotTypeDotSizeDirective = false;
// PTX does not allow .hidden or .protected
HiddenDeclarationVisibilityAttr = HiddenVisibilityAttr = MCSA_Invalid;
ProtectedVisibilityAttr = MCSA_Invalid;
Data8bitsDirective = ".b8 ";
Data16bitsDirective = nullptr; // not supported
Data32bitsDirective = ".b32 ";
Data64bitsDirective = ".b64 ";
ZeroDirective = ".b8";
AsciiDirective = nullptr; // not supported
AscizDirective = nullptr; // not supported
SupportsQuotedNames = false;
SupportsExtendedDwarfLocDirective = false;
SupportsSignedData = false;
PrivateGlobalPrefix = "$L__";
PrivateLabelPrefix = PrivateGlobalPrefix;
// @TODO: Can we just disable this?
WeakDirective = "\t// .weak\t";
GlobalDirective = "\t// .globl\t";
UseIntegratedAssembler = false;
// Avoid using parens for identifiers starting with $ - ptxas does
// not expect them.
UseParensForDollarSignNames = false;
// ptxas does not support DWARF `.file fileno directory filename'
// syntax as of v11.X.
EnableDwarfFileDirectoryDefault = false;
}
|
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
callq 0x28c9ea0
leaq 0x3eba6f8(%rip), %rax # 0x584d488
movq %rax, (%rbx)
cmpl $0x2a, 0x20(%r14)
jne 0x1992da8
movabsq $0x800000008, %rax # imm = 0x800000008
movq %rax, 0x8(%rbx)
leaq 0x273c814(%rip), %rax # 0x40cf5c3
movq %rax, 0x30(%rbx)
movq $0x2, 0x38(%rbx)
xorl %eax, %eax
movb %al, 0x16c(%rbx)
leaq 0x2fe2662(%rip), %rcx # 0x497542c
movq %rcx, 0x88(%rbx)
leaq 0x2fe2666(%rip), %rcx # 0x497543e
movq %rcx, 0x90(%rbx)
movb $0x1, 0x1a0(%rbx)
movw $0x0, 0x16a(%rbx)
movl $0x0, 0x18c(%rbx)
movq %rax, 0x194(%rbx)
leaq 0x2178a15(%rip), %rcx # 0x3b0b81c
movq %rcx, 0xf8(%rbx)
movq %rax, 0x100(%rbx)
leaq 0x2fe2632(%rip), %rcx # 0x497544e
movq %rcx, 0x108(%rbx)
leaq 0x2fe262a(%rip), %rcx # 0x4975454
movq %rcx, 0x110(%rbx)
leaq 0x2fe2622(%rip), %rcx # 0x497545a
movq %rcx, 0xc0(%rbx)
movb %al, 0xb9(%rbx)
movb %al, 0x1b8(%rbx)
movb %al, 0x118(%rbx)
xorps %xmm0, %xmm0
movups %xmm0, 0xd0(%rbx)
leaq 0x2fe25fc(%rip), %rcx # 0x497545e
movq %rcx, 0x58(%rbx)
movq $0x4, 0x60(%rbx)
movq 0x58(%rbx), %rcx
movq %rcx, 0x68(%rbx)
movq 0x60(%rbx), %rcx
movq %rcx, 0x70(%rbx)
leaq 0x2fe25de(%rip), %rcx # 0x4975463
movq %rcx, 0x178(%rbx)
leaq 0x2fe25db(%rip), %rcx # 0x497546e
movq %rcx, 0x158(%rbx)
movb %al, 0x1e0(%rbx)
movb %al, 0x1b7(%rbx)
movb %al, 0x1b3(%rbx)
addq $0x8, %rsp
popq %rbx
popq %r14
retq
|
/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp
|
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