name string | code string | asm string | file string |
|---|---|---|---|
(anonymous namespace)::RISCVInstructionSelector::replacePtrWithInt(llvm::MachineOperand&, llvm::MachineIRBuilder&, llvm::MachineRegisterInfo&) | bool RISCVInstructionSelector::replacePtrWithInt(MachineOperand &Op,
MachineIRBuilder &MIB,
MachineRegisterInfo &MRI) {
Register PtrReg = Op.getReg();
assert(MRI.getType(PtrReg).isPointer() && "Operand is not a pointer... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rcx, %r15
movq %rdx, %rax
movq %rsi, %r14
movq %rdi, %rbx
movl 0x4(%rsi), %ecx
movq 0x48(%rdi), %rdx
movzbl 0x1d7(%rdx), %esi
shll $0x8, %esi
addq $0x101, %rsi # imm = 0x101
leaq 0x10(%rsp), %rdx
movq %rsi, (%rdx)
xorl %esi, %esi
movl %esi, 0... | /Target/RISCV/GISel/RISCVInstructionSelector.cpp |
llvm::RISCVLegalizerInfo::legalizeIntrinsic(llvm::LegalizerHelper&, llvm::MachineInstr&) const | bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
switch (IntrinsicID) {
default:
return false;
case Intrinsic::vacopy: {
// vacopy arguments must be ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdx, %rdi
callq 0x1d3dfae
movq 0x20(%rbx), %rcx
movl %eax, %eax
shlq $0x5, %rax
movl 0x10(%rcx,%rax), %eax
cmpl $0x169, %eax # imm = 0x169
jne 0x11c0662
movl %eax, 0x34(%rsp)
movq (%r14), ... | /Target/RISCV/GISel/RISCVLegalizerInfo.cpp |
llvm::Pass* llvm::callDefaultCtor<(anonymous namespace)::RISCVMakeCompressibleOpt, true>() | Pass *callDefaultCtor() {
return new PassName();
} | pushq %rax
movl $0x38, %edi
callq 0x7808d0
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x475a624(%rip), %rdx # 0x592f924
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x45eb433(%rip), %rcx # 0x57c0750
movq %rcx, (%rax)
popq %rcx
retq
| /llvm/PassSupport.h |
llvm::createRISCVPreRAExpandPseudoPass() | FunctionPass *createRISCVPreRAExpandPseudoPass() { return new RISCVPreRAExpandPseudo(); } | pushq %rax
movl $0x48, %edi
callq 0x7808d0
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x4755ec7(%rip), %rdx # 0x592f939
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x45e6f01(%rip), %rcx # 0x57c0990
movq %rcx, (%rax)
popq %rcx
retq
| /Target/RISCV/RISCVExpandPseudoInsts.cpp |
(anonymous namespace)::RISCVExpandPseudo::expandVMSET_VMCLR(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, unsigned int) | bool RISCVExpandPseudo::expandVMSET_VMCLR(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned Opcode) {
DebugLoc DL = MBBI->getDebugLoc();
Register DstReg = MBBI->getOperand(0).getReg();
const MCInstrDesc &Desc = TI... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movl %ecx, %r12d
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq 0x38(%rdx), %rsi
movq %rsi, 0x10(%rsp)
testq %rsi, %rsi
je 0x11daf6f
leaq 0x10(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movq 0x20(%rbx), %rax
movl 0x4(%rax), %ebp
m... | /Target/RISCV/RISCVExpandPseudoInsts.cpp |
llvm::RISCVFrameLowering::canUseAsEpilogue(llvm::MachineBasicBlock const&) const | bool RISCVFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
const MachineFunction *MF = MBB.getParent();
MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
if (!RVFI->useSaveRestoreLibCalls(*MF))
return true;
... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq 0x20(%rsi), %rsi
movq 0x30(%rsi), %rdi
callq 0x11dfe0e
movb $0x1, %bl
testb %al, %al
je 0x11e0af5
movq 0x58(%r14), %rax
movq 0x60(%r14), %rcx
movq %rcx, %rdx
subq %rax, %rdx
movabsq $0x7fffffff0, %rsi # imm = 0x7FFFFFFF0
testq %rsi, %rdx
je 0x11e0aff
xorl %ebx,... | /Target/RISCV/RISCVFrameLowering.cpp |
llvm::detail::DenseMapPair<llvm::GetElementPtrInst*, std::pair<llvm::Value*, llvm::Value*>>* llvm::DenseMapBase<llvm::DenseMap<llvm::GetElementPtrInst*, std::pair<llvm::Value*, llvm::Value*>, llvm::DenseMapInfo<llvm::GetElementPtrInst*, void>, llvm::detail::DenseMapPair<llvm::GetElementPtrInst*, std::pair<llvm::Value*,... | BucketT *InsertIntoBucketImpl(const KeyT &Key, const LookupKeyT &Lookup,
BucketT *TheBucket) {
incrementEpoch();
// If the load of the hash table is more than 3/4, or if fewer than 1/8 of
// the buckets are empty (meaning that many are filled with tombstones),
// grow th... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movq %rcx, %rax
movq %rdx, %r14
movq %rdi, %rbx
movl 0x8(%rdi), %ecx
movl 0x10(%rdi), %esi
leal 0x4(,%rcx,4), %edx
leal (%rsi,%rsi,2), %edi
cmpl %edi, %edx
jae 0x11e2f73
notl %ecx
addl %esi, %ecx
subl 0xc(%rbx), %ecx
movl %esi, %edx
shrl $0x3, %edx
cmpl %edx, %ecx
jbe 0... | /llvm/ADT/DenseMap.h |
llvm::RISCVDAGToDAGISel::selectSHXADDOp(llvm::SDValue, unsigned int, llvm::SDValue&) | bool RISCVDAGToDAGISel::selectSHXADDOp(SDValue N, unsigned ShAmt,
SDValue &Val) {
if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
SDValue N0 = N.getOperand(0);
bool LeftShift = N0.getOpcode() == ISD::SHL;
if ((LeftShift || N0.getOpcode() == ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movl %ecx, %r12d
movl %edx, %r9d
movq %rsi, %r15
movq %rdi, %r14
cmpl $0xb9, 0x18(%rsi)
jne 0x11f379d
movq 0x28(%r15), %rax
movq 0x28(%rax), %rcx
movl 0x18(%rcx), %edx
cmpl $0x23, %edx
je 0x11f36c3
cmpl $0xb, %edx
jne 0x11f379d
movq (%ra... | /Target/RISCV/RISCVISelDAGToDAG.cpp |
llvm::RISCVDAGToDAGISel::selectSimm5Shl2(llvm::SDValue, llvm::SDValue&, llvm::SDValue&) | bool RISCVDAGToDAGISel::selectSimm5Shl2(SDValue N, SDValue &Simm5,
SDValue &Shl2) {
if (auto *C = dyn_cast<ConstantSDNode>(N)) {
int64_t Offset = C->getSExtValue();
int64_t Shift;
for (Shift = 0; Shift < 4; Shift++)
if (isInt<5>(Offset >> Shift) && ((Offset % ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rcx, %r9
movq %rsi, %r14
movl 0x18(%rsi), %eax
cmpl $0x23, %eax
je 0x11f43f3
cmpl $0xb, %eax
jne 0x11f43f8
movq %r14, %rbx
jmp 0x11f43fa
xorl %ebx, %ebx
testq %rbx, %rbx
je 0x11f4423
movq 0x58(%rbx), %rcx
movl 0x20(%rcx), %eax
cmpl... | /Target/RISCV/RISCVISelDAGToDAG.cpp |
llvm::cl::opt<int, false, llvm::cl::parser<int>>::opt<char [23], llvm::cl::OptionHidden, llvm::cl::desc, llvm::cl::initializer<int>>(char const (&) [23], llvm::cl::OptionHidden const&, llvm::cl::desc const&, llvm::cl::initializer<int> const&) | explicit opt(const Mods &... Ms)
: Option(llvm::cl::Optional, NotHidden), Parser(*this) {
apply(this, Ms...);
done();
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %rbx
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %r14
xorl %esi, %esi
xorl %edx, %edx
callq 0x7fca88
movl $0x0, 0x80(%r14)
xorps %xmm0, %xmm0
movups %xmm0, 0x88(%r14)
movb $0x0, 0x94(%r14)
leaq 0x455d6e8(%rip), %rax # 0x5757040
movq %rax,... | /llvm/Support/CommandLine.h |
llvm::RISCVTargetLowering::isLegalICmpImmediate(long) const | constexpr bool isInt(int64_t x) {
if constexpr (N == 0)
return 0 == x;
if constexpr (N == 8)
return static_cast<int8_t>(x) == x;
if constexpr (N == 16)
return static_cast<int16_t>(x) == x;
if constexpr (N == 32)
return static_cast<int32_t>(x) == x;
if constexpr (N < 64)
return -(INT64_C(1)... | addq $0x800, %rsi # imm = 0x800
cmpq $0x1000, %rsi # imm = 0x1000
setb %al
retq
| /llvm/Support/MathExtras.h |
lowerConstant(llvm::SDValue, llvm::SelectionDAG&, llvm::RISCVSubtarget const&) | static SDValue lowerConstant(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
assert(Op.getValueType() == MVT::i64 && "Unexpected VT");
int64_t Imm = cast<ConstantSDNode>(Op)->getSExtValue();
// All simm32 constants should be handled by isel.
// NOTE: The getMaxBu... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xa8, %rsp
movq %rcx, %r15
movq %rdx, %r12
movl %esi, %ebx
movq %rdi, %r14
movq 0x58(%rdi), %rcx
movl 0x20(%rcx), %eax
cmpl $0x40, %eax
ja 0x1206a21
movq 0x18(%rcx), %rdx
movl %eax, %ecx
negb %cl
shlq %cl, %rdx
sarq %cl, %rdx
xorl %r13d, %r13d
test... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::lowerVectorMaskExt(llvm::SDValue, llvm::SelectionDAG&, long) const | SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
int64_t ExtTrueVal) const {
SDLoc DL(Op);
MVT VecVT = Op.getSimpleValueType();
SDValue Src = Op.getOperand(0);
// Only custom-lower extensions from mask types
assert(Src.getValueType(... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x178, %rsp # imm = 0x178
movq %r8, 0x60(%rsp)
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r14
movq %rdi, %r15
movq 0x48(%rsi), %rsi
movq %rsi, 0x68(%rsp)
testq %rsi, %rsi
je 0x120ca2a
leaq 0x68(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVTargetLowering::lowerStrictFPExtendOrRoundLike(llvm::SDValue, llvm::SelectionDAG&) const | SDValue
RISCVTargetLowering::lowerStrictFPExtendOrRoundLike(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
SDValue Chain = Op.getOperand(0);
SDValue Src = Op.getOperand(1);
MVT VT = Op.getSimpleValueType();
MVT SrcVT = Src.getSimpleValueType();
MVT C... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x118, %rsp # imm = 0x118
movq %rcx, 0x58(%rsp)
movl %edx, %r14d
movq %rsi, %r12
movq 0x48(%rsi), %rsi
movq %rsi, 0x70(%rsp)
testq %rsi, %rsi
movq %rdi, 0x80(%rsp)
je 0x12103b9
leaq 0x70(%rsp), %rdi
movl $0x1, %edx
callq 0x2a757d8
movq 0... | /Target/RISCV/RISCVISelLowering.cpp |
(anonymous namespace)::NodeExtensionHelper::getMaskAndVL(llvm::SDNode const*, llvm::SelectionDAG&, llvm::RISCVSubtarget const&) | static std::pair<SDValue, SDValue>
getMaskAndVL(const SDNode *Root, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
assert(isSupportedRoot(Root, Subtarget) && "Unexpected root");
switch (Root->getOpcode()) {
case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
case ISD::OR:
ca... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %rbx
movl 0x18(%rsi), %eax
leal -0x38(%rax), %ecx
cmpl $0x3, %ecx
jb 0x1252d52
cmpl $0xbd, %eax
je 0x1252d52
cmpl $0xba, %eax
jne 0x1252da4
movq 0x48(%r12), %rsi
movq %rsi, (%rsp)
testq %rs... | /Target/RISCV/RISCVISelLowering.cpp |
tryFoldSelectIntoOp(llvm::SDNode*, llvm::SelectionDAG&, llvm::SDValue, llvm::SDValue, bool) | static SDValue tryFoldSelectIntoOp(SDNode *N, SelectionDAG &DAG,
SDValue TrueVal, SDValue FalseVal,
bool Swapped) {
bool Commutative = true;
unsigned Opc = TrueVal.getOpcode();
switch (Opc) {
default:
return SDValue();
case ISD::SHL:
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movl %r9d, 0x34(%rsp)
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, 0x38(%rsp)
movl 0x18(%rdx), %r13d
xorl %ebp, %ebp
xorl %ebx, %ebx
cmpl $0xbc, %r13d
jg 0x1253f14
movb $0x1, %r12b
leal -0xba(%r13), %eax
cmpl $0x2, %eax
jb 0x1253f27
cmpl $... | /Target/RISCV/RISCVISelLowering.cpp |
void llvm::RVVArgDispatcher::constructArgInfos<llvm::ISD::InputArg>(llvm::ArrayRef<llvm::ISD::InputArg>) | void RVVArgDispatcher::constructArgInfos(ArrayRef<Arg> ArgList) {
// This lambda determines whether an array of types are constructed by
// homogeneous vector types.
auto isHomogeneousScalableVectorType = [](ArrayRef<Arg> ArgList) {
// First, extract the first element in the argument type.
auto It = ArgLi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
imulq $0x38, %rdx, %r15
testq %rdx, %rdx
je 0x12558f7
testb $0x1, 0x1(%r14)
jne 0x12558f7
cmpq $0x1, %rdx
je 0x12558f7
movzbl 0x10(%r14), %eax
leal 0x77(%rax), %ecx
cmpb $0x34, %cl
ja 0x12558f7
leaq -0x38(%r15),... | /Target/RISCV/RISCVISelLowering.cpp |
llvm::RISCVMachineFunctionInfo::isSExt32Register(llvm::Register) const | bool RISCVMachineFunctionInfo::isSExt32Register(Register Reg) const {
return is_contained(SExt32Registers, Reg);
} | pushq %rbx
subq $0x10, %rsp
movq %rdi, %rbx
leaq 0xc(%rsp), %rdx
movl %esi, (%rdx)
movq 0x40(%rdi), %rdi
movl 0x48(%rbx), %eax
leaq (%rdi,%rax,4), %rsi
callq 0xbe0938
movl 0x48(%rbx), %ecx
shlq $0x2, %rcx
addq 0x40(%rbx), %rcx
cmpq %rcx, %rax
setne %al
addq $0x10, %rsp
popq %rbx
retq
| /Target/RISCV/RISCVMachineFunctionInfo.cpp |
llvm::DenseMap<llvm::MachineInstr const*, llvm::SmallVector<unsigned int, 12u>, llvm::DenseMapInfo<llvm::MachineInstr const*, void>, llvm::detail::DenseMapPair<llvm::MachineInstr const*, llvm::SmallVector<unsigned int, 12u>>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %rbx
movl 0x10(%rdi), %r15d
decl %esi
movl %esi, %eax
shrl %eax
orl %esi, %eax
movl %eax, %ecx
shrl $0x2, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x4, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x8, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x10, %eax
orl %ecx, %eax
incl %ea... | /llvm/ADT/DenseMap.h |
llvm::SparcRegisterInfo::isReservedReg(llvm::MachineFunction const&, llvm::MCRegister) const | bool SparcRegisterInfo::isReservedReg(const MachineFunction &MF,
MCRegister Reg) const {
return getReservedRegs(MF)[Reg];
} | pushq %r14
pushq %rbx
subq $0x48, %rsp
movl %edx, %ebx
movq %rsi, %rdx
movq %rdi, %rsi
movq (%rdi), %rax
movq %rsp, %r14
movq %r14, %rdi
callq *0x60(%rax)
movq (%r14), %rdi
movl %ebx, %eax
shrl $0x6, %eax
movq (%rdi,%rax,8), %r14
leaq 0x10(%rsp), %rax
cmpq %rax, %rdi
je 0x125b4a8
callq 0x780910
btq %rbx, %r14
setb %al
... | /Target/Sparc/SparcRegisterInfo.cpp |
llvm::StringMap<std::unique_ptr<llvm::SparcSubtarget, std::default_delete<llvm::SparcSubtarget>>, llvm::MallocAllocator>::~StringMap() | ~StringMap() {
// Delete all the elements in the map, but don't reset the elements
// to default values. This is a copy of clear(), but avoids unnecessary
// work not required in the destructor.
if (!empty()) {
for (unsigned I = 0, E = NumBuckets; I != E; ++I) {
StringMapEntryBase *Bucket... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %rbx
cmpl $0x0, 0xc(%rdi)
je 0x125c31e
movl 0x8(%rbx), %r14d
testq %r14, %r14
je 0x125c31e
xorl %r15d, %r15d
movq (%rbx), %rax
movq (%rax,%r15,8), %rdi
cmpq $-0x8, %rdi
je 0x125c316
testq %rdi, %rdi
je 0x125c316
movq %rbx, %rsi
callq 0x125cbe2
incq %r15
cmpq %r15, %r14
jne 0x... | /llvm/ADT/StringMap.h |
llvm::SystemZAsmPrinter::PrintAsmMemoryOperand(llvm::MachineInstr const*, unsigned int, char const*, llvm::raw_ostream&) | bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
unsigned OpNo,
const char *ExtraCode,
raw_ostream &OS) {
if (ExtraCode && ExtraCode[0] && !ExtraCode[1]) {
... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %r8, %rbx
testq %rcx, %rcx
je 0x1275c83
movzbl (%rcx), %eax
testl %eax, %eax
je 0x1275c83
cmpb $0x0, 0x1(%rcx)
je 0x1275d21
movq 0x40(%rdi), %r14
movq 0x20(%rsi), %rax
movl %edx, %ecx
shlq $0x5, %rcx
movl 0x4(%rax,%rcx), %ebp
leal 0x1(%rdx), %ecx
shlq $0... | /Target/SystemZ/SystemZAsmPrinter.cpp |
llvm::SystemZAsmPrinter::emitPPA2(llvm::Module&) | void SystemZAsmPrinter::emitPPA2(Module &M) {
OutStreamer->pushSection();
OutStreamer->switchSection(getObjFileLowering().getPPA2Section());
MCContext &OutContext = OutStreamer->getContext();
// Make CELQSTRT symbol.
const char *StartSymbolName = "CELQSTRT";
MCSymbol *CELQSTRT = OutContext.getOrCreateSymbol... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1a8, %rsp # imm = 0x1A8
movq %rsi, %r12
movq %rdi, %rbx
movq 0x50(%rdi), %rdi
callq 0xac0e72
movq 0x50(%rbx), %r14
movq %rbx, %rdi
callq 0x1606e3a
movq 0x2f0(%rax), %rsi
movq (%r14), %rax
movq %r14, %rdi
xorl %edx, %edx
callq *0xa8(%ra... | /Target/SystemZ/SystemZAsmPrinter.cpp |
llvm::SystemZAsmPrinter::~SystemZAsmPrinter() | class LLVM_LIBRARY_VISIBILITY SystemZAsmPrinter : public AsmPrinter {
private:
MCSymbol *CurrentFnPPA1Sym; // PPA1 Symbol.
MCSymbol *CurrentFnEPMarkerSym; // Entry Point Marker.
MCSymbol *PPA2Sym;
SystemZTargetStreamer *getTargetStreamer() {
MCTargetStreamer *TS = OutStreamer->getTargetStreamer();
... | pushq %rbx
movq %rdi, %rbx
leaq 0x454da5d(%rip), %rax # 0x57c6428
movq %rax, (%rdi)
movq 0x350(%rdi), %rdi
leaq 0x360(%rbx), %rax
cmpq %rax, %rdi
je 0x12789e6
callq 0x780910
movq 0x338(%rbx), %rdi
movl 0x348(%rbx), %eax
shlq $0x3, %rax
leaq (%rax,%rax,2), %rsi
movl $0x8, %edx
callq 0x2b410f1
movq %rbx, %rdi
callq 0x1... | /Target/SystemZ/SystemZAsmPrinter.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::MCSymbol const*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol const*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol const*, unsigned int>>, llvm::MCSymbol const*, unsigned int, llvm::DenseMapInfo<llvm::MCSymbol const*, void>, llvm::detail::DenseMapPair<llvm::MCSymbol const*... | unsigned getNumEntries() const {
return NumEntries;
} | movl 0x8(%rdi), %eax
testl %eax, %eax
jne 0x1278eb3
cmpl $0x0, 0xc(%rdi)
je 0x1278f8c
shll $0x2, %eax
movl 0x10(%rdi), %ecx
cmpl %ecx, %eax
setae %al
cmpl $0x41, %ecx
setb %dl
orb %al, %dl
je 0x1278f8e
testq %rcx, %rcx
je 0x1278f84
movq (%rdi), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, ... | /llvm/ADT/DenseMap.h |
llvm::SystemZInstrInfo::expandRXYPseudo(llvm::MachineInstr&, unsigned int, unsigned int) const | void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
unsigned HighOpcode) const {
Register Reg = MI.getOperand(0).getReg();
unsigned Opcode = getOpcodeForOffset(
SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode,
MI.getOperand(2).getImm());
... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movq 0x20(%rsi), %rax
movl 0x4(%rax), %esi
leal -0x1(%rsi), %edi
cmpl $0x3ffffffe, %edi # imm = 0x3FFFFFFE
ja 0x127a70f
leaq 0x454cc67(%rip), %rdi # 0x57c7350
movq (%rdi), %rdi
movl %esi, %r8d
shrl $0x3, %r8d
movzwl 0x16(%rdi), %r9d
cmpl %r9d, %r8... | /Target/SystemZ/SystemZInstrInfo.cpp |
llvm::SystemZInstrInfo::getLoadAndTest(unsigned int) const | unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
switch (Opcode) {
case SystemZ::L: return SystemZ::LT;
case SystemZ::LY: return SystemZ::LT;
case SystemZ::LG: return SystemZ::LTG;
case SystemZ::LGF: return SystemZ::LTGF;
case SystemZ::LR: return SystemZ::LTR;
case Sy... | movl $0x702, %eax # imm = 0x702
cmpl $0x610, %esi # imm = 0x610
jg 0x1280add
cmpl $0x5d8, %esi # imm = 0x5D8
jle 0x1280b0b
cmpl $0x5df, %esi # imm = 0x5DF
jg 0x1280b4b
cmpl $0x5d9, %esi # imm = 0x5D9
je 0x1280b77
cmpl $0x5de, %esi # imm = 0x5DE
jne 0x128... | /Target/SystemZ/SystemZInstrInfo.cpp |
llvm::SystemZ::splitBlockAfter(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::MachineBasicBlock*) | MachineBasicBlock *SystemZ::splitBlockAfter(MachineBasicBlock::iterator MI,
MachineBasicBlock *MBB) {
MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
NewMBB->splice(NewMBB->begin(), MBB,
std::next(MachineBasicBlock::iterator(MI)), MBB->end());
NewMBB->... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
movq %rdi, %r15
movq %rsi, %rdi
callq 0x1280f13
movq %rax, %r14
testq %r15, %r15
je 0x1280f87
testb $0x4, (%r15)
je 0x1280f87
jmp 0x1280f8e
movq 0x8(%r15), %r15
testb $0x8, 0x2c(%r15)
jne 0x1280f83
movq 0x8(%r15), %rcx
leaq 0x30(%rbx), %r8
cmpq %r8, %rcx
je 0x1280faf
mov... | /Target/SystemZ/SystemZInstrInfo.cpp |
llvm::VR32BitGetRawAllocationOrder(llvm::MachineFunction const&) | iterator begin() const { return RegsBegin; } | leaq 0x45e9681(%rip), %rax # 0x586ac70
movq 0x20(%rax), %rcx
movzwl 0x34(%rax), %eax
movq %rcx, -0x28(%rsp)
movq %rax, -0x20(%rsp)
leaq 0x2bb1e58(%rip), %rax # 0x3e33460
movq %rax, -0x18(%rsp)
movq $0x20, -0x10(%rsp)
movq 0x10(%rdi), %rax
movl 0x17c(%rax), %ecx
movl 0x184(%rax), %eax
xorl $0x4, %eax
xorl $0xf, %ecx... | /llvm/MC/MCRegisterInfo.h |
llvm::SystemZELFRegisters::getCallPreservedMask(llvm::MachineFunction const&, unsigned int) const | const uint32_t *
SystemZELFRegisters::getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID CC) const {
const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
if (CC == CallingConv::GHC)
return CSR_SystemZ_NoRegs_RegMask;
if (CC == CallingC... | cmpl $0xa, %edx
je 0x1282a3b
pushq %rbx
subq $0x10, %rsp
movq %rsi, %rbx
movq 0x10(%rsi), %rdi
cmpl $0xd, %edx
jne 0x1282a43
leaq 0x2bb07c9(%rip), %rcx # 0x3e331f0
leaq 0x2bb07a2(%rip), %rax # 0x3e331d0
cmpb $0x0, 0x146(%rdi)
cmovneq %rcx, %rax
jmp 0x1282a8b
leaq 0x2bb07ee(%rip), %rax # 0x3e33230
retq
movq (%rdi)... | /Target/SystemZ/SystemZRegisterInfo.cpp |
llvm::BasicTTIImplBase<llvm::SystemZTTIImpl>::isTypeLegal(llvm::Type*) | bool isTypeLegal(Type *Ty) {
EVT VT = getTLI()->getValueType(DL, Ty, /*AllowUnknown=*/true);
return getTLI()->isTypeLegal(VT);
} | pushq %rbx
movq %rsi, %rdx
movq %rdi, %rbx
movq 0x8(%rdi), %rsi
movq 0x18(%rdi), %rdi
movl $0x1, %ecx
callq 0x920138
testb %al, %al
je 0x128679b
movq 0x18(%rbx), %rcx
movzbl %al, %eax
cmpq $0x0, 0x68(%rcx,%rax,8)
setne %al
jmp 0x128679d
xorl %eax, %eax
popq %rbx
retq
nop
| /llvm/CodeGen/BasicTTIImpl.h |
llvm::SystemZTTIImpl::getMinPrefetchStride(unsigned int, unsigned int, unsigned int, bool) const | unsigned SystemZTTIImpl::getMinPrefetchStride(unsigned NumMemAccesses,
unsigned NumStridedMemAccesses,
unsigned NumPrefetches,
bool HasCall) const {
// Don't prefetch a loop with m... | movl $0xffffffff, %eax # imm = 0xFFFFFFFF
cmpl $0x10, %ecx
ja 0x128bbd3
cmpl $0x21, %edx
setb %al
orb %r8b, %al
jne 0x128bbbb
subl %edx, %esi
shll $0x5, %esi
movl $0x1, %eax
cmpl %edx, %esi
jbe 0x128bbd3
movq 0x10(%rdi), %rax
cmpb $0x0, 0x13b(%rax)
movl $0x2000, %ecx # imm = 0x2000
movl $0x800, %eax ... | /Target/SystemZ/SystemZTargetTransformInfo.cpp |
(anonymous namespace)::SystemZDAGToDAGISel::storeLoadIsAligned(llvm::SDNode*) const | bool SystemZDAGToDAGISel::storeLoadIsAligned(SDNode *N) const {
auto *MemAccess = cast<MemSDNode>(N);
auto *LdSt = dyn_cast<LSBaseSDNode>(MemAccess);
TypeSize StoreSize = MemAccess->getMemoryVT().getStoreSize();
SDValue BasePtr = MemAccess->getBasePtr();
MachineMemOperand *MMO = MemAccess->getMemOperand();
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %rdi, %r14
movl $0xfffffedf, %eax # imm = 0xFFFFFEDF
addl 0x18(%rdi), %eax
xorl %ebx, %ebx
cmpl $0x2, %eax
movl $0x0, %r13d
cmovbq %rdi, %r13
movb 0x58(%rdi), %al
movq 0x60(%rdi), %rcx
leaq 0x18(%rsp), %rdi
movb %al, (%rdi)
mo... | /Target/SystemZ/SystemZISelDAGToDAG.cpp |
llvm::getNodeAVL(llvm::SDValue) | SDValue getNodeAVL(SDValue Op) {
auto PosOpt = getAVLPos(Op->getOpcode());
return PosOpt ? Op->getOperand(*PosOpt) : SDValue();
} | pushq %rbx
movq %rdi, %rbx
movl 0x18(%rdi), %edi
callq 0x12f4039
btq $0x20, %rax
jb 0x12f466e
xorl %edx, %edx
xorl %eax, %eax
jmp 0x12f4680
movq 0x28(%rbx), %rcx
movl %eax, %eax
leaq (%rax,%rax,4), %rdx
movq (%rcx,%rdx,8), %rax
movl 0x8(%rcx,%rdx,8), %edx
popq %rbx
retq
| /Target/VE/VECustomDAG.cpp |
llvm::SmallVectorTemplateBase<std::pair<llvm::StringRef, llvm::SmallVector<llvm::MCSymbol*, 4u>>, false>::grow(unsigned long) | void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %r12
movl $0x40, %ecx
movq %r15, %rsi
movq %r12, %r8
callq 0x2b4ec3c
movq %rax, %r14
movq %rbx, %rdi
movq %rax, %rsi
callq 0x12f83b6
movq (%r12), %r12
movq (%rbx), %rdi
cmpq %r15, %rdi
je 0x12f83a2
ca... | /llvm/ADT/SmallVector.h |
llvm::computeLegalValueVTs(llvm::WebAssemblyTargetLowering const&, llvm::LLVMContext&, llvm::DataLayout const&, llvm::Type*, llvm::SmallVectorImpl<llvm::MVT>&) | void llvm::computeLegalValueVTs(const WebAssemblyTargetLowering &TLI,
LLVMContext &Ctx, const DataLayout &DL,
Type *Ty, SmallVectorImpl<MVT> &ValueVTs) {
SmallVector<EVT, 4> VTs;
ComputeValueVTs(TLI, DL, Ty, VTs);
for (EVT VT : VTs) {
unsigned N... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %r8, %rbx
movq %rsi, 0x28(%rsp)
leaq 0x58(%rsp), %rsi
movq %rsi, -0x10(%rsi)
movabsq $0x400000000, %rax # imm = 0x400000000
movq %rax, -0x8(%rsi)
movq $0x0, 0x38(%rsp)
movb $0x0, 0x40(%rsp)
movups 0x38(%rsp), %xmm0
movups %xmm0... | /Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp |
void llvm::cl::apply<llvm::cl::opt<bool, false, llvm::cl::parser<bool>>, char [47], llvm::cl::OptionHidden, llvm::cl::desc, llvm::cl::initializer<bool>>(llvm::cl::opt<bool, false, llvm::cl::parser<bool>>*, char const (&) [47], llvm::cl::OptionHidden const&, llvm::cl::desc const&, llvm::cl::initializer<bool> const&) | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq %rsi, %rdi
callq 0x7802c0
movq %rbx, %rdi
movq %r13, %rsi
movq %rax, %rdx
callq 0x2b1f336
movl (%r12), %eax
movzwl 0xa(%rbx), %ecx
shll $0x5, %eax
andl $0x60, %eax
andl $-0x61, %ecx... | /llvm/Support/CommandLine.h |
llvm::SmallVectorTemplateBase<std::unique_ptr<llvm::WebAssemblyException, std::default_delete<llvm::WebAssemblyException>>, false>::grow(unsigned long) | void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %r12
movl $0x8, %ecx
movq %r15, %rsi
movq %r12, %r8
callq 0x2b4ec3c
movq %rax, %r14
movq %rbx, %rdi
movq %rax, %rsi
callq 0x1313036
movq (%r12), %r12
movq (%rbx), %rdi
cmpq %r15, %rdi
je 0x1313022
cal... | /llvm/ADT/SmallVector.h |
(anonymous namespace)::WebAssemblyFixIrreducibleControlFlow::runOnMachineFunction(llvm::MachineFunction&) | bool WebAssemblyFixIrreducibleControlFlow::runOnMachineFunction(
MachineFunction &MF) {
LLVM_DEBUG(dbgs() << "********** Fixing Irreducible Control Flow **********\n"
"********** Function: "
<< MF.getName() << '\n');
// Start the recursive process on the entire functi... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x58, %rsp
movq %rsi, %rbx
leaq 0x20(%rsp), %rax
movq %rax, -0x20(%rax)
movq %rax, -0x18(%rax)
movq $0x4, -0x10(%rax)
movl $0x0, -0x8(%rax)
leaq 0x140(%rsi), %r13
movq 0x148(%rsi), %r14
cmpq %r13, %r14
je 0x13150f7
leaq 0x40(%rsp), %r15
movq %rsp, ... | /Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp |
bool llvm::PatternMatch::Shuffle_match<llvm::PatternMatch::ThreeOps_match<llvm::PatternMatch::class_match<llvm::Value>, llvm::PatternMatch::class_match<llvm::Value>, llvm::PatternMatch::cstval_pred_ty<llvm::PatternMatch::is_zero_int, llvm::ConstantInt, true>, 62u>, llvm::PatternMatch::class_match<llvm::Value>, llvm::Pa... | bool isValue(const APInt &C) { return C.isMaxSignedValue(); } | pushq %rbp
pushq %rbx
pushq %rax
movb (%rsi), %bpl
xorl %ebx, %ebx
cmpb $0x5c, %bpl
cmoveq %rsi, %rbx
jne 0x133811a
movq -0x40(%rbx), %rsi
callq 0x133812a
testb %al, %al
je 0x1338118
movq 0x48(%rbx), %rdi
movl 0x50(%rbx), %eax
leaq (%rdi,%rax,4), %rbx
movq %rbx, %rsi
callq 0xe1fff0
cmpq %rbx, %rax
sete %cl
jmp 0x133811... | /llvm/IR/PatternMatch.h |
(anonymous namespace)::WebAssemblyFastISel::getLegalType(llvm::MVT::SimpleValueType) | MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
switch (VT) {
case MVT::i1:
case MVT::i8:
case MVT::i16:
return MVT::i32;
case MVT::i32:
case MVT::i64:
case MVT::f32:
case MVT::f64:
return VT;
case MVT::funcref:
case MVT::externref:
if (Subtarget->h... | movl %esi, %eax
cmpl $0x4d, %esi
jg 0x133cd0e
cmpl $0x3c, %esi
ja 0x133cd33
movl %esi, %ecx
movl $0x3180, %edx # imm = 0x3180
btq %rcx, %rdx
jb 0x133cd0d
movabsq $0x1004008000000000, %rdx # imm = 0x1004008000000000
btq %rcx, %rdx
jb 0x133cd54
cmpq $0xb, %rcx
jne 0x133cd33
movb $0xc, %al
retq
leal -0x4e(%rsi),... | /Target/WebAssembly/WebAssemblyFastISel.cpp |
llvm::X86Subtarget::swiftAsyncContextIsDynamicallySet() const | bool swiftAsyncContextIsDynamicallySet() const {
// Older OS versions (particularly system unwinders) are confused by the
// Swift extended frame, so when building code that might be run on them we
// must dynamically query the concurrency library to determine whether
// extended frames should be flagge... | pushq %rbx
movq %rdi, %rbx
addq $0x1f0, %rdi # imm = 0x1F0
callq 0x2b04486
movq %rax, %rcx
movl 0x21c(%rbx), %edx
xorl %eax, %eax
cmpl $0x8, %edx
jle 0x13aca55
cmpl $0x9, %edx
je 0x13aca64
cmpl $0x1b, %edx
je 0x13aca69
cmpl $0x1a, %edx
je 0x13aca5f
jmp 0x13aca6f
cmpl $0x1, %edx
je 0x13aca64
cmpl $0x5, %edx
j... | /Target/X86/X86Subtarget.h |
LowerAndToBT(llvm::SDValue, llvm::ISD::CondCode, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::X86::CondCode&) | static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC, const SDLoc &dl,
SelectionDAG &DAG, X86::CondCode &X86CC) {
assert(And.getOpcode() == ISD::AND && "Expected AND node!");
SDValue Op0 = And.getOperand(0);
SDValue Op1 = And.getOperand(1);
if (Op0.getOpcode() == ISD::TRUNCATE)
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x78, %rsp
movq %r9, %r15
movq %r8, %rbx
movq %rcx, 0x38(%rsp)
movq %rdi, 0x68(%rsp)
movl %esi, 0x70(%rsp)
movq 0x28(%rdi), %rax
movups (%rax), %xmm0
movaps %xmm0, 0x10(%rsp)
movq 0x28(%rax), %r13
movq 0x10(%rsp), %rcx
cmpl $0xd7, 0x18(%rcx)
jne 0x... | /Target/X86/X86ISelLowering.cpp |
llvm::X86TargetLowering::shouldExpandAtomicLoadInIR(llvm::LoadInst*) const | TargetLowering::AtomicExpansionKind
X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
Type *MemType = LI->getType();
if (!LI->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
!Subtarget.useSoftFloat()) {
// If this a 64 bit atomic load on a 32-bit target and SSE2 is enabled,... | pushq %r14
pushq %rbx
subq $0x18, %rsp
movq %rdi, %r14
movq 0x8(%rsi), %rbx
movq %rsi, %rdi
callq 0x2a51280
movq %rax, %rdi
movl $0x1c, %esi
callq 0x2a40a66
testb %al, %al
jne 0x1401ea4
movq 0x4e0f8(%r14), %rax
cmpb $0x0, 0x1e6(%rax)
jne 0x1401ea4
movq %rbx, %rdi
callq 0x2a9a7de
leaq 0x8(%rsp), %rdi
movq %rax, (%rdi)
m... | /Target/X86/X86ISelLowering.cpp |
LowerFCOPYSIGN(llvm::SDValue, llvm::SelectionDAG&) | static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
SDValue Mag = Op.getOperand(0);
SDValue Sign = Op.getOperand(1);
SDLoc dl(Op);
// If the sign operand is smaller, extend it first.
MVT VT = Op.getSimpleValueType();
if (Sign.getSimpleValueType().bitsLT(VT))
Sign = DAG.getNode(ISD::FP_EXTEND... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x188, %rsp # imm = 0x188
movq %rdx, %r12
movl %esi, %ebx
movq %rdi, %r14
movq 0x28(%rdi), %rax
movq (%rax), %rcx
movq %rcx, 0x78(%rsp)
movl 0x8(%rax), %ecx
movl %ecx, 0x64(%rsp)
movl 0xc(%rax), %ecx
movl %ecx, 0x58(%rsp)
movq 0x28(%rax)... | /Target/X86/X86ISelLowering.cpp |
isRepeatedShuffleMask(unsigned int, llvm::MVT, llvm::ArrayRef<int>, llvm::SmallVectorImpl<int>&) | static bool isRepeatedShuffleMask(unsigned LaneSizeInBits, MVT VT,
ArrayRef<int> Mask,
SmallVectorImpl<int> &RepeatedMask) {
auto LaneSize = LaneSizeInBits / VT.getScalarSizeInBits();
RepeatedMask.assign(LaneSize, -1);
int Size = Mask.size();
f... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
movq %r8, %r12
movq %rcx, %rbx
movq %rdx, %r14
movl %edi, %eax
leal -0x11(%rsi), %ecx
cmpb $-0x54, %cl
ja 0x1488563
movzbl %sil, %ecx
leaq 0x1d474e2(%rip), %rdx # 0x31cfa40
movb -0x1(%rcx,%rdx), %sil
movzbl %sil, %ecx
shll $0x4, %ecx
leaq 0x1d467cf(%rip), %rsi ... | /Target/X86/X86ISelLowering.cpp |
lowerV4I64Shuffle(llvm::SDLoc const&, llvm::ArrayRef<int>, llvm::APInt const&, llvm::SDValue, llvm::SDValue, llvm::X86Subtarget const&, llvm::SelectionDAG&) | static SDValue lowerV4I64Shuffle(const SDLoc &DL, ArrayRef<int> Mask,
const APInt &Zeroable, SDValue V1, SDValue V2,
const X86Subtarget &Subtarget,
SelectionDAG &DAG) {
assert(V1.getSimpleValueType() == MVT::v4i64 && "B... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x1b8, %rsp # imm = 0x1B8
movl %r9d, %ebp
movq %r8, %r15
movq %rcx, %r13
movq %rsi, %r12
movq 0x208(%rsp), %rcx
movq 0x200(%rsp), %rax
movq %r8, 0x80(%rsp)
movl %r9d, 0x88(%rsp)
movq 0x1f0(%rsp), %r14
movl 0x1f8(%rsp), %ebx
movq %rsi, 0x... | /Target/X86/X86ISelLowering.cpp |
llvm::createX86OptimizeLEAs() | FunctionPass *llvm::createX86OptimizeLEAs() { return new X86OptimizeLEAPass(); } | pushq %rax
movl $0x68, %edi
callq 0x7808d0
xorl %ecx, %ecx
movq %rcx, 0x8(%rax)
leaq 0x4428f0c(%rip), %rdx # 0x5932c5c
movq %rdx, 0x10(%rax)
movl $0x2, 0x18(%rax)
xorps %xmm0, %xmm0
movups %xmm0, 0x20(%rax)
movq %rcx, 0x30(%rax)
leaq 0x42d540b(%rip), %rdx # 0x57df178
movq %rdx, (%rax)
movups %xmm0, 0x38(%rax)
movl ... | /Target/X86/X86OptimizeLEAs.cpp |
(anonymous namespace)::X86SpeculativeLoadHardeningPass::saveEFLAGS(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&) | unsigned X86SpeculativeLoadHardeningPass::saveEFLAGS(
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertPt,
const DebugLoc &Loc) {
// FIXME: Hard coding this to a 32-bit register class seems weird, but matches
// what instruction selection does.
Register Reg = MRI->createVirtualRegister(&X86::GR32... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x40, %rsp
movq %rcx, %r13
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movq 0x40(%rdi), %rdi
leaq 0x42bfee2(%rip), %rsi # 0x57d5ad0
leaq 0x2a458c3(%rip), %rdx # 0x3f5b4b8
xorl %ecx, %ecx
callq 0x1d82fd6
movl %eax, %ebx
movq (%r13), %rsi
movq %rsi, (%r... | /Target/X86/X86SpeculativeLoadHardening.cpp |
(anonymous namespace)::X86OutgoingValueAssigner::assignArg(unsigned int, llvm::EVT, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::CallLowering::ArgInfo const&, llvm::ISD::ArgFlagsTy, llvm::CCState&) | bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
CCValAssign::LocInfo LocInfo,
const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
CCState &State) override {
bool Res = AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
StackSize = Stat... | pushq %r15
pushq %r14
pushq %rbx
subq $0x10, %rsp
movl %r9d, %edx
movl %r8d, %eax
movq %rdi, %rbx
movq 0x50(%rsp), %r14
movq 0x38(%rsp), %r15
movl 0x30(%rsp), %ecx
movq 0x40(%rsp), %r8
movq 0x48(%rsp), %r9
movq %r14, (%rsp)
movl %esi, %edi
movl %eax, %esi
callq *0x8(%rbx)
movq 0x30(%r14), %rcx
movq %rcx, 0x28(%rbx)
cmp... | /Target/X86/GISel/X86CallLowering.cpp |
llvm::GISelCSEInfo::insertInstr(llvm::MachineInstr*, void*) | void GISelCSEInfo::insertInstr(MachineInstr *MI, void *InsertPos) {
assert(MI);
// If it exists in temporary insts, remove it.
TemporaryInsts.remove(MI);
auto *Node = getUniqueInstrForMI(MI);
insertNode(Node, InsertPos);
} | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
addq $0xe8, %rdi
callq 0x155e44a
leaq 0x48(%r15), %rdi
movl $0x10, %esi
movl $0x4, %edx
callq 0x8f284c
movq $0x0, (%rax)
movq %r14, 0x8(%rax)
movq %r15, %rdi
movq %rax, %rsi
movq %rbx, %rdx
popq %rbx
popq %r14
popq %r15
jmp 0x155e31a
nop
| /CodeGen/GlobalISel/CSEInfo.cpp |
llvm::CallBase::countOperandBundlesOfType(unsigned int) const | unsigned countOperandBundlesOfType(uint32_t ID) const {
unsigned Count = 0;
for (unsigned i = 0, e = getNumOperandBundles(); i != e; ++i)
if (getOperandBundleAt(i).getTagID() == ID)
Count++;
return Count;
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movl %esi, %ebx
movq %rdi, %r14
callq 0x91f95a
testl %eax, %eax
je 0x1565727
movl %eax, %r15d
shlq $0x4, %r15
xorl %r12d, %r12d
xorl %ebp, %ebp
movq %r14, %rdi
callq 0x2a9ec18
movq (%rax,%r12), %rax
xorl %ecx, %ecx
cmpl %ebx, 0x8(%rax)
sete %cl
addl %ecx, %ebp
addq... | /llvm/IR/InstrTypes.h |
llvm::SmallVectorTemplateBase<std::function<void ()>, false>::moveElementsForGrow(std::function<void ()>*) | size_t size() const { return Size; } | pushq %r14
pushq %rbx
pushq %rax
movl 0x8(%rdi), %eax
testq %rax, %rax
je 0x156a58f
movq (%rdi), %rcx
shlq $0x5, %rax
addq $0x18, %rcx
xorl %edx, %edx
xorps %xmm0, %xmm0
movups %xmm0, (%rsi,%rdx)
movq $0x0, 0x10(%rsi,%rdx)
movq (%rcx,%rdx), %r8
movq %r8, 0x18(%rsi,%rdx)
cmpq $0x0, -0x8(%rcx,%rdx)
je 0x156a586
leaq (%rs... | /llvm/ADT/SmallVector.h |
llvm::CombinerHelper::applyFunnelShiftToRotate(llvm::MachineInstr&) | void CombinerHelper::applyFunnelShiftToRotate(MachineInstr &MI) {
unsigned Opc = MI.getOpcode();
assert(Opc == TargetOpcode::G_FSHL || Opc == TargetOpcode::G_FSHR);
bool IsFSHL = Opc == TargetOpcode::G_FSHL;
Observer.changingInstr(MI);
MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL
... | pushq %r15
pushq %r14
pushq %rbx
movq %rsi, %rbx
xorl %r14d, %r14d
cmpw $0x89, 0x44(%rsi)
movq %rdi, %r15
setne %r14b
movq 0x10(%rdi), %rdi
movq (%rdi), %rax
callq *0x20(%rax)
movq (%r15), %rax
movq 0x10(%rax), %rax
shll $0x5, %r14d
orq $-0x1180, %r14 # imm = 0xEE80
addq 0x8(%rax), %r14
movq %rbx, %rdi
movq %r... | /CodeGen/GlobalISel/CombinerHelper.cpp |
llvm::CombinerHelper::applyUDivByConst(llvm::MachineInstr&) | void CombinerHelper::applyUDivByConst(MachineInstr &MI) {
auto *NewMI = buildUDivUsingMul(MI);
replaceSingleDefInstWithReg(MI, NewMI->getOperand(0).getReg());
} | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
callq 0x1579fac
movq 0x20(%rax), %rax
movl 0x4(%rax), %ebp
movq 0x20(%rbx), %rax
movl 0x4(%rax), %r15d
movq %rbx, %rdi
callq 0x1d3deba
movq 0x8(%r14), %rsi
movq %r14, %rdi
movl %r15d, %edx
movl %ebp, %ecx
addq $0x8, %rsp
popq %rbx
po... | /CodeGen/GlobalISel/CombinerHelper.cpp |
llvm::CombinerHelper::matchTruncLshrBuildVectorFold(llvm::MachineInstr&, llvm::Register&) | bool CombinerHelper::matchTruncLshrBuildVectorFold(MachineInstr &MI,
Register &MatchInfo) {
// Replace (G_TRUNC (G_LSHR (G_BITCAST (G_BUILD_VECTOR x, y)), K)) with
// y if K == size of vector element type
std::optional<ValueAndVReg> ShiftAmt;
if (!mi_match(M... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rdx, %r15
movq %rsi, %r14
movq %rdi, %rbx
leaq 0x10(%rsp), %r12
movb $0x0, 0x18(%r12)
movq 0x20(%rsi), %rax
movl 0x24(%rax), %eax
movq 0x8(%rdi), %rsi
leaq 0x30(%rsp), %rdi
movq %rdx, 0x8(%rdi)
movq %r12, 0x10(%rdi)
leaq 0x8(%rsp), %rdx
movl %eax, (%rdx... | /CodeGen/GlobalISel/CombinerHelper.cpp |
llvm::DenseMapBase<llvm::SmallDenseMap<long, long, 8u, llvm::DenseMapInfo<long, void>, llvm::detail::DenseMapPair<long, long>>, long, long, llvm::DenseMapInfo<long, void>, llvm::detail::DenseMapPair<long, long>>::moveFromOldBuckets(llvm::detail::DenseMapPair<long, long>*, llvm::detail::DenseMapPair<long, long>*) | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x10, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movabsq $0x7fffffffffffffff, %r13 # imm = 0x7FFFFFFFFFFFFFFF
leaq 0x8(%rdi), %rax
andl $0x1, (%rdi)
movl $0x0, 0x4(%rdi)
cmoveq 0x8(%rdi), %rax
movl $0x8, %ecx
cmovel 0x10(%rdi), %ecx
testl %ecx, %ecx... | /llvm/ADT/DenseMap.h |
llvm::CombinerHelper::matchSubOfVScale(llvm::MachineOperand const&, std::function<void (llvm::MachineIRBuilder&)>&) | bool CombinerHelper::matchSubOfVScale(const MachineOperand &MO,
BuildFnTy &MatchInfo) {
GSub *Sub = cast<GSub>(MRI.getVRegDef(MO.getReg()));
GVScale *RHSVScale = cast<GVScale>(MRI.getVRegDef(Sub->getRHSReg()));
Register Dst = MO.getReg();
LLT DstTy = MRI.getType(Dst);
i... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x50, %rsp
movq %rdx, %rbx
movq %rsi, %r13
movq %rdi, %r12
movq 0x8(%rdi), %rdi
movl 0x4(%rsi), %esi
callq 0x1d835a8
movq %rax, %r14
movq 0x8(%r12), %rdi
movq 0x20(%rax), %rax
movl 0x44(%rax), %esi
callq 0x1d835a8
movq %rax, %r15
movl 0x4(%r13), %r13d
movq 0x... | /CodeGen/GlobalISel/CombinerHelperVectorOps.cpp |
llvm::IRTranslator::findUnwindDestinations(llvm::BasicBlock const*, llvm::BranchProbability, llvm::SmallVectorImpl<std::pair<llvm::MachineBasicBlock*, llvm::BranchProbability>>&) | bool IRTranslator::findUnwindDestinations(
const BasicBlock *EHPadBB,
BranchProbability Prob,
SmallVectorImpl<std::pair<MachineBasicBlock *, BranchProbability>>
&UnwindDests) {
EHPersonality Personality = classifyEHPersonality(
EHPadBB->getParent()->getFunction().getPersonalityFn());
bool ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rcx, %rbx
movq %rsi, %r12
movq %rdi, %r14
movl %edx, 0xc(%rsp)
movq 0x48(%rsi), %rdi
callq 0x2a40ed6
movq %rax, %rdi
callq 0x2a39a54
movq %rax, 0x28(%rsp)
cmpl $0xc, %eax
je 0x159a978
movq 0x28(%rsp), %rax
leal -0x7(%rax), %ecx
mov... | /CodeGen/GlobalISel/IRTranslator.cpp |
llvm::MachineFunction::VariableDbgInfo& llvm::SmallVectorImpl<llvm::MachineFunction::VariableDbgInfo>::emplace_back<llvm::DILocalVariable const*&, llvm::DIExpression const*&, int&, llvm::DILocation const*&>(llvm::DILocalVariable const*&, llvm::DIExpression const*&, int&, llvm::DILocation const*&) | size_t size() const { return Size; } | movl 0x8(%rdi), %eax
cmpl 0xc(%rdi), %eax
jae 0x15a0390
movq (%rdi), %r9
movq %rax, %r10
shlq $0x5, %r10
movq (%rsi), %rsi
movq (%rdx), %rdx
movl (%rcx), %ecx
movq (%r8), %r8
movl %ecx, (%r9,%r10)
movb $0x0, 0x4(%r9,%r10)
movq %rsi, 0x8(%r9,%r10)
movq %rdx, 0x10(%r9,%r10)
movq %r8, 0x18(%r9,%r10)
incl %eax
movl %eax, 0... | /llvm/ADT/SmallVector.h |
llvm::SrcOp const* llvm::SmallVectorTemplateCommon<llvm::SrcOp, void>::reserveForParamAndGetAddressImpl<llvm::SmallVectorTemplateBase<llvm::SrcOp, true>>(llvm::SmallVectorTemplateBase<llvm::SrcOp, true>*, llvm::SrcOp const&, unsigned long) | static const T *reserveForParamAndGetAddressImpl(U *This, const T &Elt,
size_t N) {
size_t NewSize = This->size() + N;
if (LLVM_LIKELY(NewSize <= This->capacity()))
return &Elt;
bool ReferencesStorage = false;
int64_t Index = -1;
if (!U::Take... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %rbx
movl 0x8(%rdi), %ecx
movl 0xc(%rdi), %eax
addq %rcx, %rdx
cmpq %rax, %rdx
ja 0x15a2488
movq %rbx, %rax
addq $0x8, %rsp
popq %rbx
popq %r14
popq %r15
popq %rbp
retq
movq %rdi, %r14
movq (%rdi), %rax
leaq (%rcx,%rcx,2), %rcx
cmpq %rbx, %rax
setbe %sil... | /llvm/ADT/SmallVector.h |
llvm::SmallVectorImpl<llvm::LegalityPredicates::TypePairAndMemDesc>::operator=(llvm::SmallVectorImpl<llvm::LegalityPredicates::TypePairAndMemDesc> const&) | SmallVectorImpl<T> &SmallVectorImpl<T>::
operator=(const SmallVectorImpl<T> &RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;
// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (C... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdi, %rbx
cmpq %rsi, %rdi
je 0x15a6d12
movq %rsi, %r15
movl 0x8(%rsi), %r14d
movl 0x8(%rbx), %r12d
cmpl %r14d, %r12d
jae 0x15a6cb7
cmpl %r14d, 0xc(%rbx)
jae 0x15a6cd0
movl $0x0, 0x8(%rbx)
leaq 0x10(%rbx), %rsi
movl $0x20, %ecx
movq %rbx, %rdi
movq %r14, %rdx
... | /llvm/ADT/SmallVector.h |
llvm::LegalizerHelper::lowerSADDO_SSUBO(llvm::MachineInstr&) | LegalizerHelper::LegalizeResult
LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
auto [Dst0, Dst0Ty, Dst1, Dst1Ty, LHS, LHSTy, RHS, RHSTy] =
MI.getFirst4RegLLTs();
const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
LLT Ty = Dst0Ty;
LLT BoolTy = Dst1Ty;
Register NewDst0 = MRI.cloneVirtual... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xd8, %rsp
movq %rsi, %rbx
movq %rdi, %r14
leaq 0x98(%rsp), %r15
movq %r15, %rdi
callq 0x1d436ac
movq %rbx, 0x38(%rsp)
movzwl 0x44(%rbx), %ebp
movq 0x20(%r15), %rax
movq %rax, 0x30(%rsp)
movq 0x30(%r15), %rbx
movq 0x10(%r14), %rdi
movl 0x38(%r15), ... | /CodeGen/GlobalISel/LegalizerHelper.cpp |
llvm::LegalizerHelper::lowerSMULH_UMULH(llvm::MachineInstr&) | LegalizerHelper::LegalizeResult
LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) {
bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH;
unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
Register Result = MI.getOperand(0).getReg();
LLT OrigTy = MRI.getType(Result);
auto SizeInBits... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x88, %rsp
movq %rdi, %r14
movq %rsi, %rbx
movq 0x20(%rsi), %rax
movl 0x4(%rax), %edx
testl %edx, %edx
jns 0x15be127
movq 0x10(%r14), %rax
movl %edx, %ecx
andl $0x7fffffff, %ecx # imm = 0x7FFFFFFF
cmpl %ecx, 0x1d0(%rax)
jbe 0x15be127
movq 0x1... | /CodeGen/GlobalISel/LegalizerHelper.cpp |
getTruncStoreByteOffset(llvm::GStore&, llvm::Register&, llvm::MachineRegisterInfo&) | static std::optional<int64_t>
getTruncStoreByteOffset(GStore &Store, Register &SrcVal,
MachineRegisterInfo &MRI) {
Register TruncVal;
if (!mi_match(Store.getValueReg(), MRI, m_GTrunc(m_Reg(TruncVal))))
return std::nullopt;
// The shift amount must be a constant multiple of the narrow ... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
leaq 0x4(%rsp), %rax
movl $0x0, (%rax)
movq 0x20(%rdi), %rcx
movl 0x4(%rcx), %ecx
leaq 0x18(%rsp), %rdi
movq %rax, (%rdi)
leaq 0x8(%rsp), %r12
movl %ecx, (%r12)
movq %rdx, %rsi
movq %r12, %rdx
callq 0x97e174
tes... | /CodeGen/GlobalISel/LoadStoreOpt.cpp |
llvm::MachineIRBuilder::buildUnmerge(llvm::LLT, llvm::SrcOp const&) | MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
const SrcOp &Op) {
unsigned NumReg = Op.getLLTTy(*getMRI()).getSizeInBits() / Res.getSizeInBits();
SmallVector<DstOp, 8> TmpVec(NumReg, Res);
return buildInstr(TargetOpcode::G_UNMERGE_VALUES, TmpVec, Op)... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
subq $0xb8, %rsp
movq %rdx, %rbx
movq %rdi, %r14
leaq 0x10(%rsp), %r15
movq %rsi, (%r15)
movq 0x18(%rdi), %rsi
movq %rdx, %rdi
callq 0x1563f02
leaq 0x8(%rsp), %rdi
movq %rax, (%rdi)
callq 0x94022c
leaq 0x28(%rsp), %rdi
movq %rax, (%rdi)
movb %dl, 0x8(%rdi)
callq 0x2b60e74
mov... | /CodeGen/GlobalISel/MachineIRBuilder.cpp |
llvm::MachineIRBuilder::buildConstant(llvm::DstOp const&, llvm::ConstantInt const&) | MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
const ConstantInt &Val) {
LLT Ty = Res.getLLTTy(*getMRI());
LLT EltTy = Ty.getScalarType();
assert(EltTy.getScalarSizeInBits() == Val.getBitWidth() &&
"creating constant with the wron... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x48, %rsp
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl 0x8(%rsi), %eax
cmpl $0x2, %eax
je 0x15de87b
cmpl $0x1, %eax
jne 0x15de880
movl (%r14), %eax
testl %eax, %eax
jns 0x15de87b
movq 0x18(%r15), %rcx
andl $0x7fffffff, %eax # imm = 0... | /CodeGen/GlobalISel/MachineIRBuilder.cpp |
llvm::MachineIRBuilder::buildPrefetch(llvm::SrcOp const&, unsigned int, unsigned int, unsigned int, llvm::MachineMemOperand&) | MachineInstrBuilder MachineIRBuilder::buildPrefetch(const SrcOp &Addr,
unsigned RW,
unsigned Locality,
unsigned CacheType,
... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %r9, (%rsp)
movl %r8d, %ebp
movl %ecx, %r15d
movl %edx, %r12d
movq %rsi, %r13
movq %rdi, %r14
movl $0x75, %esi
callq 0x15dd5c4
movq %r14, %rdi
movq %rax, %rsi
callq 0x15dd6ec
leaq 0x28(%rsp), %r14
movq %rax, (%r14)
movq %rdx, 0x8(%r... | /CodeGen/GlobalISel/MachineIRBuilder.cpp |
llvm::RegBankSelect::init(llvm::MachineFunction&) | void RegBankSelect::init(MachineFunction &MF) {
RBI = MF.getSubtarget().getRegBankInfo();
assert(RBI && "Cannot work without RegisterBankInfo");
MRI = &MF.getRegInfo();
TRI = MF.getSubtarget().getRegisterInfo();
TPC = &getAnalysis<TargetPassConfig>();
if (OptMode != Mode::Fast) {
MBFI = &getAnalysis<Mac... | pushq %r14
pushq %rbx
pushq %rax
movq %rsi, %r14
movq %rdi, %rbx
movq 0x10(%rsi), %rdi
movq (%rdi), %rax
callq *0xd0(%rax)
movq %rax, 0x38(%rbx)
movq 0x28(%r14), %rax
movq %rax, 0x40(%rbx)
movq 0x10(%r14), %rdi
movq (%rdi), %rax
callq *0xc8(%rax)
movq %rax, 0x48(%rbx)
movq 0x8(%rbx), %rax
movq (%rax), %rdx
movq 0x8(%ra... | /CodeGen/GlobalISel/RegBankSelect.cpp |
(anonymous namespace)::XCoreAsmPrinter::printOperand(llvm::MachineInstr const*, int, llvm::raw_ostream&) | void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
raw_ostream &O) {
const DataLayout &DL = getDataLayout();
const MachineOperand &MO = MI->getOperand(opNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
O << XCoreInstPrinter::getRegisterNam... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %r14
movl %edx, %ebx
movq %rsi, %r12
movq %rdi, %r15
callq 0x1606e44
movq 0x20(%r12), %rcx
movl %ebx, %edx
shlq $0x5, %rdx
leaq (%rcx,%rdx), %rbx
movzbl (%rcx,%rdx), %ecx
leaq 0x296ecee(%rip), %rdx # 0x3f59dd0
movslq (%rdx,%rcx,4), %rcx
addq %rdx, %rcx... | /Target/XCore/XCoreAsmPrinter.cpp |
(anonymous namespace)::XCoreLowerThreadLocal::XCoreLowerThreadLocal() | XCoreLowerThreadLocal() : ModulePass(ID) {
initializeXCoreLowerThreadLocalPass(*PassRegistry::getPassRegistry());
} | pushq %rax
movq $0x0, 0x8(%rdi)
leaq 0x433c694(%rip), %rax # 0x5933e94
movq %rax, 0x10(%rdi)
movl $0x4, 0x18(%rdi)
leaq 0x41eaff6(%rip), %rax # 0x57e2808
movq %rax, (%rdi)
callq 0x2a9031c
movq %rsp, %rdx
movq %rax, (%rdx)
leaq 0x433c669(%rip), %rdi # 0x5933e90
leaq -0xdf(%rip), %rsi # 0x15f774f
callq 0x9390... | /Target/XCore/XCoreLowerThreadLocal.cpp |
llvm::XCoreRegisterInfo::getReservedRegs(llvm::MachineFunction const&) const | BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
const XCoreFrameLowering *TFI = getFrameLowering(MF);
Reserved.set(XCore::CP);
Reserved.set(XCore::DP);
Reserved.set(XCore::SP);
Reserved.set(XCore::LR);
if (TFI->hasFP(MF)) {
Reserved.se... | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %r14
movq %rdi, %rbx
movl 0x10(%rsi), %r15d
leal 0x3f(%r15), %esi
shrl $0x6, %esi
leaq 0x10(%rdi), %rax
movq %rax, (%rdi)
movabsq $0x600000000, %rax # imm = 0x600000000
movq %rax, 0x8(%rdi)
xorl %edx, %edx
callq 0x7fa254
movl %r15d, 0x40(%rbx)
movq 0x10(%r14), %rdi
movq ... | /Target/XCore/XCoreRegisterInfo.cpp |
llvm::XCoreFrameLowering::emitPrologue(llvm::MachineFunction&, llvm::MachineBasicBlock&) const | void XCoreFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo &MFI = MF.getFrameInfo();
const MCRegisterInfo *MR... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x148, %rsp # imm = 0x148
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movq 0x38(%rdx), %r13
movq 0x38(%rsi), %rbp
movq 0x10(%rsi), %rdi
movq 0x18(%rsi), %rax
movq 0xa0(%rax), %rax
movq %rax, 0x38(%rsp)
movq (%rdi), %rax
callq *0x80(%... | /Target/XCore/XCoreFrameLowering.cpp |
EmitDefCfaOffset(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, llvm::DebugLoc const&, llvm::TargetInstrInfo const&, int) | static void EmitDefCfaOffset(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
const DebugLoc &dl, const TargetInstrInfo &TII,
int Offset) {
MachineFunction &MF = *MBB.getParent();
unsigned CFIIndex =
MF.addFrameIns... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x98, %rsp
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, 0x10(%rsp)
movq %rdi, %r14
movq 0x20(%rdi), %r13
movslq %r8d, %rdx
leaq 0x30(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
xorl %ecx, %ecx
callq 0x9ba8be
movq %r13, %rdi
movq %rbx, %rsi
callq 0x1d... | /Target/XCore/XCoreFrameLowering.cpp |
llvm::XCoreTargetLowering::LowerConstantPool(llvm::SDValue, llvm::SelectionDAG&) const | SDValue XCoreTargetLowering::
LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
{
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
// FIXME there isn't really debug info here
SDLoc dl(CP);
EVT PtrVT = Op.getValueType();
SDValue Res;
if (CP->isMachineConstantPoolEntry()) {
Res = DAG.getTargetC... | pushq %rbp
pushq %r14
pushq %rbx
subq $0x20, %rsp
movq %rcx, %rbx
movl %edx, %ebp
movq %rsi, %r14
movq 0x48(%rsi), %rsi
movq %rsi, (%rsp)
testq %rsi, %rsi
je 0x15fddf4
movq %rsp, %rdi
movl $0x1, %edx
callq 0x2a757d8
movl 0x44(%r14), %eax
movl %eax, 0x8(%rsp)
movl %ebp, %ecx
shlq $0x4, %rcx
movq 0x30(%r14), %rdx
movq 0x... | /Target/XCore/XCoreISelLowering.cpp |
llvm::DIELabel::sizeOf(llvm::dwarf::FormParams const&, llvm::dwarf::Form) const | unsigned DIELabel::sizeOf(const dwarf::FormParams &FormParams,
dwarf::Form Form) const {
switch (Form) {
case dwarf::DW_FORM_data4:
return 4;
case dwarf::DW_FORM_data8:
return 8;
case dwarf::DW_FORM_sec_offset:
case dwarf::DW_FORM_strp:
return FormParams.getDwarfOffsetByt... | cmpl $0x6, %edx
jle 0x161e281
cmpl $0x17, %edx
je 0x161e273
cmpl $0xe, %edx
jne 0x161e28d
cmpb $0x0, 0x3(%rsi)
setne %al
shlb $0x2, %al
addb $0x4, %al
jmp 0x161e28f
movb $0x4, %al
cmpl $0x1, %edx
jne 0x161e28f
movb 0x2(%rsi), %al
jmp 0x161e28f
movb $0x8, %al
movzbl %al, %eax
retq
nop
| /CodeGen/AsmPrinter/DIE.cpp |
llvm::DIEBlock::sizeOf(llvm::dwarf::FormParams const&, llvm::dwarf::Form) const | unsigned DIEBlock::sizeOf(const dwarf::FormParams &, dwarf::Form Form) const {
switch (Form) {
case dwarf::DW_FORM_block1: return Size + sizeof(int8_t);
case dwarf::DW_FORM_block2: return Size + sizeof(int16_t);
case dwarf::DW_FORM_block4: return Size + sizeof(int32_t);
case dwarf::DW_FORM_exprloc:
case dwa... | leal -0x3(%rdx), %eax
cmpl $0x7, %eax
ja 0x161e335
leaq 0x293e50b(%rip), %rcx # 0x3f5c830
movslq (%rcx,%rax,4), %rax
addq %rcx, %rax
jmpq *%rax
movl 0x8(%rdi), %eax
addl $0x2, %eax
retq
movl $0x10, %eax
cmpl $0x18, %edx
jne 0x161e35b
pushq %rbx
movl 0x8(%rdi), %ebx
movq %rbx, %rdi
callq 0x2b40dd4
addl %ebx, %eax
popq... | /CodeGen/AsmPrinter/DIE.cpp |
llvm::SmallVectorTemplateBase<llvm::DbgValueLoc, false>::push_back(llvm::DbgValueLoc const&) | void push_back(const T &Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
::new ((void *)this->end()) T(*EltPtr);
this->set_size(this->size() + 1);
} | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %rbx
movl $0x1, %edx
callq 0x16349f6
movq %rax, %r14
movq (%rbx), %rax
movl 0x8(%rbx), %ecx
leaq (%rcx,%rcx,4), %rcx
shlq $0x4, %rcx
leaq (%rax,%rcx), %r15
movq (%r14), %rdx
leaq (%rax,%rcx), %rsi
addq $0x18, %rsi
movq %rdx, -0x18(%rsi)
movq %rsi, -0x10(%rsi)
movabsq $0x20000... | /llvm/ADT/SmallVector.h |
llvm::DwarfDebug::recordSourceLine(unsigned int, unsigned int, llvm::MDNode const*, unsigned int) | void DwarfDebug::recordSourceLine(unsigned Line, unsigned Col, const MDNode *S,
unsigned Flags) {
::recordSourceLine(*Asm, Line, Col, S, Flags,
Asm->OutStreamer->getContext().getDwarfCompileUnitID(),
getDwarfVersion(), getUnits());
} | subq $0x28, %rsp
movq 0x8(%rdi), %rax
movq 0x50(%rax), %r9
movq 0x8(%r9), %r10
movl 0x760(%r10), %r9d
movzwl 0x758(%r10), %r10d
movq 0xbf8(%rdi), %r11
movq %r11, 0x18(%rsp)
movl 0xc00(%rdi), %edi
movq %rdi, 0x20(%rsp)
movups 0x18(%rsp), %xmm0
movups %xmm0, 0x8(%rsp)
movl %r10d, (%rsp)
movq %rax, %rdi
callq 0x1626f9e
ad... | /CodeGen/AsmPrinter/DwarfDebug.cpp |
llvm::DwarfDebug::initSkeletonUnit(llvm::DwarfUnit const&, llvm::DIE&, std::unique_ptr<llvm::DwarfCompileUnit, std::default_delete<llvm::DwarfCompileUnit>>) | void DwarfDebug::initSkeletonUnit(const DwarfUnit &U, DIE &Die,
std::unique_ptr<DwarfCompileUnit> NewU) {
if (!CompilationDir.empty())
NewU->addString(Die, dwarf::DW_AT_comp_dir, CompilationDir);
addGnuPubAttributes(*NewU, Die);
SkeletonHolder.addUnit(std::move(NewU));
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rcx, %rbx
movq %rdx, %r15
movq %rdi, %r14
cmpq $0x0, 0xb58(%rdi)
je 0x162a5ed
movq (%rbx), %rdi
movq 0xb50(%r14), %rcx
movq 0xb58(%r14), %r8
movq %r15, %rsi
movl $0x1b, %edx
callq 0x163cf34
movq (%rbx), %r12
movq %r12, %rdi
callq 0x16702a2
testb %al, %al
je 0... | /CodeGen/AsmPrinter/DwarfDebug.cpp |
void llvm::cl::apply<llvm::cl::opt<llvm::AccelTableKind, false, llvm::cl::parser<llvm::AccelTableKind>>, char [13], llvm::cl::OptionHidden, llvm::cl::desc, llvm::cl::ValuesClass, llvm::cl::initializer<llvm::AccelTableKind>>(llvm::cl::opt<llvm::AccelTableKind, false, llvm::cl::parser<llvm::AccelTableKind>>*, char const ... | void apply(Opt *O, const Mod &M, const Mods &... Ms) {
applicator<Mod>::opt(M, *O);
apply(O, Ms...);
} | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
pushq %rax
movq %r9, %r14
movq %r8, %r15
movq %rcx, %r12
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %rbx
movq %rsi, %rdi
callq 0x7802c0
movq %rbx, %rdi
movq %rbp, %rsi
movq %rax, %rdx
callq 0x2b1f336
movl (%r13), %eax
movzwl 0xa(%rbx), %ecx
shll $0x5, %e... | /llvm/Support/CommandLine.h |
llvm::SmallVectorTemplateBase<std::pair<llvm::MDNode const*, llvm::DwarfCompileUnit*>, true>::push_back(std::pair<llvm::MDNode const*, llvm::DwarfCompileUnit*>) | void push_back(ValueParamT Elt) {
const T *EltPtr = reserveForParamAndGetAddress(Elt);
memcpy(reinterpret_cast<void *>(this->end()), EltPtr, sizeof(T));
this->set_size(this->size() + 1);
} | pushq %r15
pushq %r14
pushq %rbx
movq %rdx, %rbx
movq %rsi, %r15
movq %rdi, %r14
movl 0x8(%rdi), %edx
cmpl 0xc(%rdi), %edx
jae 0x1632e50
movq (%r14), %rax
movl 0x8(%r14), %ecx
shlq $0x4, %rcx
movq %r15, (%rax,%rcx)
movq %rbx, 0x8(%rax,%rcx)
incl 0x8(%r14)
popq %rbx
popq %r14
popq %r15
retq
incq %rdx
leaq 0x10(%r14), %r... | /llvm/ADT/SmallVector.h |
llvm::DenseMap<llvm::DIE const*, llvm::DwarfCompileUnit*, llvm::DenseMapInfo<llvm::DIE const*, void>, llvm::detail::DenseMapPair<llvm::DIE const*, llvm::DwarfCompileUnit*>>::grow(unsigned int) | void grow(unsigned AtLeast) {
unsigned OldNumBuckets = NumBuckets;
BucketT *OldBuckets = Buckets;
allocateBuckets(std::max<unsigned>(64, static_cast<unsigned>(NextPowerOf2(AtLeast-1))));
assert(Buckets);
if (!OldBuckets) {
this->BaseT::initEmpty();
return;
}
this->moveFromOldBu... | pushq %r15
pushq %r14
pushq %rbx
movq %rdi, %r15
movl 0x10(%rdi), %ebx
movq (%rdi), %r14
leal -0x1(%rsi), %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x8, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x10,... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorImpl<std::pair<unsigned long, llvm::DbgValueLoc>>::erase(std::pair<unsigned long, llvm::DbgValueLoc> const*, std::pair<unsigned long, llvm::DbgValueLoc> const*) | iterator erase(const_iterator CS, const_iterator CE) {
// Just cast away constness because this is a non-const member function.
iterator S = const_cast<iterator>(CS);
iterator E = const_cast<iterator>(CE);
assert(this->isRangeInStorage(S, E) && "Range to erase is out of bounds.");
iterator N = S;
... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rbx
movq %rdi, %r14
movl 0x8(%rdi), %eax
imulq $0x58, %rax, %rsi
addq (%rdi), %rsi
movq %rdx, %rdi
movq %rbx, %rdx
callq 0x16347f4
movq %rax, %r15
movl 0x8(%r14), %eax
imulq $0x58, %rax, %r12
addq (%r14), %r12
cmpq %r15, %r12
je 0x16347d0
movq -0x48(%r1... | /llvm/ADT/SmallVector.h |
void llvm::SmallVectorImpl<llvm::DbgValueLoc>::append<llvm::DbgValueLoc const*, void>(llvm::DbgValueLoc const*, llvm::DbgValueLoc const*) | void append(ItTy in_start, ItTy in_end) {
this->assertSafeToAddRange(in_start, in_end);
size_type NumInputs = std::distance(in_start, in_end);
this->reserve(this->size() + NumInputs);
this->uninitialized_copy(in_start, in_end, this->end());
this->set_size(this->size() + NumInputs);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %rbx
movq %rdx, %rax
subq %rsi, %rax
sarq $0x4, %rax
movabsq $-0x3333333333333333, %r12 # imm = 0xCCCCCCCCCCCCCCCD
imulq %rax, %r12
movl 0x8(%rdi), %esi
movl 0xc(%rdi), %eax
addq %r12, %rsi
cmpq %rax, %rsi
jbe 0x1635007
mo... | /llvm/ADT/SmallVector.h |
bool llvm::DenseMapBase<llvm::DenseMap<llvm::LexicalScope*, llvm::SmallVector<llvm::DbgLabel*, 4u>, llvm::DenseMapInfo<llvm::LexicalScope*, void>, llvm::detail::DenseMapPair<llvm::LexicalScope*, llvm::SmallVector<llvm::DbgLabel*, 4u>>>, llvm::LexicalScope*, llvm::SmallVector<llvm::DbgLabel*, 4u>, llvm::DenseMapInfo<llv... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x163b8a3
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %r8d
movl %r8d, %eax
shrl $0x4, %eax
shrl $0x9, %r8d
xorl %eax, %r8d
decl %ecx
andl %ecx, %r8d
movl $0x1, %r10d
xorl %r9d, %r9d
movl %r8d, %r11d
imulq $0x38, %r11, %rbx
leaq (%rdi,%rbx), %r11
movq (%rdi,%rbx), %rbx
cmpq %rbx, ... | /llvm/ADT/DenseMap.h |
llvm::DwarfUnit::addConstantValue(llvm::DIE&, llvm::APInt const&, bool) | void DwarfUnit::addConstantValue(DIE &Die, const APInt &Val, bool Unsigned) {
unsigned CIBitWidth = Val.getBitWidth();
if (CIBitWidth <= 64) {
addConstantValue(Die, Unsigned,
Unsigned ? Val.getZExtValue() : Val.getSExtValue());
return;
}
DIEBlock *Block = new (DIEValueAllocator) DI... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rdx, %r12
movq %rdi, %rbx
movl 0x8(%rdx), %edx
cmpl $0x40, %edx
ja 0x163de79
movl %ecx, %eax
movq (%r12), %r8
movl $0x1000f, %ecx # imm = 0x1000F
testb %al, %al
jne 0x163de5a
movl %edx, %ecx
negb %cl
shlq %cl, %r8
sarq %cl... | /CodeGen/AsmPrinter/DwarfUnit.cpp |
llvm::CodeViewDebug::emitInlinedCallSite(llvm::CodeViewDebug::FunctionInfo const&, llvm::DILocation const*, llvm::CodeViewDebug::InlineSite const&) | void CodeViewDebug::emitInlinedCallSite(const FunctionInfo &FI,
const DILocation *InlinedAt,
const InlineSite &Site) {
assert(TypeIndices.count({Site.Inlinee, nullptr}));
TypeIndex InlineeIdx = TypeIndices[{Site.Inlinee, nullptr}];
/... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x38, %rsp
movq %rcx, %r15
movq %rsi, %r14
movq %rdi, %rbx
addq $0x450, %rdi # imm = 0x450
movq 0x78(%rcx), %rax
leaq 0x10(%rsp), %rbp
movq %rax, (%rbp)
movq $0x0, 0x8(%rbp)
movq %rbp, %rsi
callq 0x165a1e4
movl 0x10(%rax), %r13d
movq %rb... | /CodeGen/AsmPrinter/CodeViewDebug.cpp |
llvm::CodeViewDebug::getCompleteTypeIndex(llvm::DIType const*) | TypeIndex CodeViewDebug::getCompleteTypeIndex(const DIType *Ty) {
// The null DIType is the void type. Don't try to hash it.
if (!Ty)
return TypeIndex::Void();
// Look through typedefs when getting the complete type index. Call
// getTypeIndex on the typdef to ensure that any UDTs are accumulated and are
... | pushq %rbp
pushq %r15
pushq %r14
pushq %rbx
subq $0x38, %rsp
testq %rsi, %rsi
je 0x164fe04
movq %rsi, %r14
movq %rdi, %rbx
movq %rsi, %rdi
callq 0x2a08d12
cmpw $0x16, %ax
jne 0x164fd2c
movq %rbx, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq 0x164b402
jmp 0x164fd2c
movq -0x10(%r14), %rax
testb $0x2, %al
jne 0x164fd24
addq... | /CodeGen/AsmPrinter/CodeViewDebug.cpp |
llvm::MachineInstr::getHeapAllocMarker() const | [[nodiscard]] inline To bit_cast(const From &from) noexcept {
#if __has_builtin(__builtin_bit_cast)
return __builtin_bit_cast(To, from);
#else
To to;
std::memcpy(&to, &from, sizeof(To));
return to;
#endif
} | movq 0x30(%rdi), %rax
cmpq $0x8, %rax
jb 0x16510f1
movl %eax, %ecx
andl $0x7, %ecx
cmpl $0x3, %ecx
setne %cl
andq $-0x8, %rax
sete %dl
orb %cl, %dl
jne 0x16510f1
cmpb $0x1, 0x6(%rax)
jne 0x16510f1
movslq (%rax), %rcx
leaq (%rax,%rcx,8), %rcx
movzbl 0x4(%rax), %edx
movzbl 0x5(%rax), %eax
addl %edx, %eax
movq 0x10(%rcx,%... | /llvm/ADT/bit.h |
llvm::SmallVectorTemplateBase<llvm::CodeViewDebug::LocalVariable, false>::grow(unsigned long) | void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
size_t NewCapacity;
T *NewElts = mallocForGrow(MinSize, NewCapacity);
moveElementsForGrow(NewElts);
takeAllocationForGrow(NewElts, NewCapacity);
} | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rsi, %rdx
movq %rdi, %rbx
leaq 0x10(%rdi), %r15
movq %rsp, %r12
movl $0x50, %ecx
movq %r15, %rsi
movq %r12, %r8
callq 0x2b4ec3c
movq %rax, %r14
movq %rbx, %rdi
movq %rax, %rsi
callq 0x16566dc
movq (%r12), %r12
movq (%rbx), %rdi
cmpq %r15, %rdi
je 0x1656334
ca... | /llvm/ADT/SmallVector.h |
llvm::DenseMap<std::pair<llvm::DINode const*, llvm::DIType const*>, llvm::codeview::TypeIndex, llvm::DenseMapInfo<std::pair<llvm::DINode const*, llvm::DIType const*>, void>, llvm::detail::DenseMapPair<std::pair<llvm::DINode const*, llvm::DIType const*>, llvm::codeview::TypeIndex>>::init(unsigned int) | void init(unsigned InitNumEntries) {
auto InitBuckets = BaseT::getMinBucketToReserveForEntries(InitNumEntries);
if (allocateBuckets(InitBuckets)) {
this->BaseT::initEmpty();
} else {
NumEntries = 0;
NumTombstones = 0;
}
} | pushq %rbp
pushq %rbx
pushq %rax
movq %rdi, %rbx
testl %esi, %esi
je 0x16590c4
shll $0x2, %esi
movl $0xaaaaaaab, %eax # imm = 0xAAAAAAAB
imulq %rsi, %rax
shrq $0x21, %rax
incl %eax
movl %eax, %ecx
shrl %ecx
orl %eax, %ecx
movl %ecx, %eax
shrl $0x2, %eax
orl %ecx, %eax
movl %eax, %ecx
shrl $0x4, %ecx
orl %eax, %ec... | /llvm/ADT/DenseMap.h |
llvm::SmallVectorImpl<llvm::codeview::VFTableSlotKind>::assign(unsigned long, llvm::codeview::VFTableSlotKind) | void assign(size_type NumElts, ValueParamT Elt) {
// Note that Elt could be an internal reference.
if (NumElts > this->capacity()) {
this->growAndAssign(NumElts, Elt);
return;
}
// Assign over existing elements.
std::fill_n(this->begin(), std::min(NumElts, this->size()), Elt);
if (N... | pushq %rbp
pushq %r15
pushq %r14
pushq %r12
pushq %rbx
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
cmpq %rsi, 0x10(%rdi)
jae 0x165b950
leaq 0x8(%r14), %r15
movq $0x0, 0x8(%r14)
leaq 0x18(%r14), %rsi
movl $0x1, %ecx
movq %r14, %rdi
movq %rbx, %rdx
callq 0x2b4efce
movq (%r14), %rdi
movzbl %bpl, %esi
movq %rbx, %rdx
c... | /llvm/ADT/SmallVector.h |
llvm::WasmException::computeCallSiteTable(llvm::SmallVectorImpl<llvm::EHStreamer::CallSiteEntry>&, llvm::SmallVectorImpl<llvm::EHStreamer::CallSiteRange>&, llvm::SmallVectorImpl<llvm::LandingPadInfo const*> const&, llvm::SmallVectorImpl<unsigned int> const&) | void WasmException::computeCallSiteTable(
SmallVectorImpl<CallSiteEntry> &CallSites,
SmallVectorImpl<CallSiteRange> &CallSiteRanges,
const SmallVectorImpl<const LandingPadInfo *> &LandingPads,
const SmallVectorImpl<unsigned> &FirstActions) {
MachineFunction &MF = *Asm->MF;
for (unsigned I = 0, N = L... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x28, %rsp
movq %r8, 0x20(%rsp)
movq %rsi, (%rsp)
movl 0x8(%rcx), %r15d
testq %r15, %r15
je 0x165f441
movq %rcx, %r14
movq 0x8(%rdi), %rax
movl $0x1e0, %r12d # imm = 0x1E0
addq 0x58(%rax), %r12
xorl %r13d, %r13d
movq %r15, 0x18(%rsp)
movq... | /CodeGen/AsmPrinter/WasmException.cpp |
char* llvm::hashing::detail::hash_combine_recursive_helper::combine_data<bool>(unsigned long&, char*, char*, bool) | char *combine_data(size_t &length, char *buffer_ptr, char *buffer_end, T data) {
if (!store_and_advance(buffer_ptr, buffer_end, data)) {
// Check for skew which prevents the buffer from being packed, and do
// a partial store into the buffer to fill it. This is only a concern
// with the variadic ... | pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x40, %rsp
movq %rcx, %r14
movq %rdx, %r13
movq %rsi, %r15
movq %rdi, %rbx
movb %r8b, 0x7(%rsp)
leaq 0x1(%rdx), %rax
cmpq %rcx, %rax
ja 0x1661c54
movb 0x7(%rsp), %cl
movb %cl, (%r13)
movq %rax, %r13
cmpq %r14, %rax
jbe 0x1661cf3
movq %r14, %r12
subq %r13, %r1... | /llvm/ADT/Hashing.h |
llvm::DenseMapBase<llvm::DenseMap<llvm::OffsetAndUnitID, llvm::MCSymbol*, llvm::DenseMapInfo<llvm::OffsetAndUnitID, void>, llvm::detail::DenseMapPair<llvm::OffsetAndUnitID, llvm::MCSymbol*>>, llvm::OffsetAndUnitID, llvm::MCSymbol*, llvm::DenseMapInfo<llvm::OffsetAndUnitID, void>, llvm::detail::DenseMapPair<llvm::Offset... | void moveFromOldBuckets(BucketT *OldBucketsBegin, BucketT *OldBucketsEnd) {
initEmpty();
// Insert all the old elements.
const KeyT EmptyKey = getEmptyKey();
const KeyT TombstoneKey = getTombstoneKey();
for (BucketT *B = OldBucketsBegin, *E = OldBucketsEnd; B != E; ++B) {
if (!KeyInfoT::isEqu... | pushq %r15
pushq %r14
pushq %r12
pushq %rbx
pushq %rax
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movq $0x0, 0x8(%rdi)
movl 0x10(%rdi), %ecx
testq %rcx, %rcx
je 0x16624f1
movq (%r15), %rax
leaq (%rcx,%rcx,2), %rcx
leaq (%rax,%rcx,8), %rcx
movq $-0x1, (%rax)
movb $0x0, 0xc(%rax)
movl $0xffffffff, 0x8(%rax) # imm =... | /llvm/ADT/DenseMap.h |
bool llvm::DenseMapBase<llvm::DenseMap<std::pair<llvm::DINode const*, llvm::DILocation const*>, unsigned int, llvm::DenseMapInfo<std::pair<llvm::DINode const*, llvm::DILocation const*>, void>, llvm::detail::DenseMapPair<std::pair<llvm::DINode const*, llvm::DILocation const*>, unsigned int>>, std::pair<llvm::DINode cons... | unsigned getNumBuckets() const {
return NumBuckets;
} | movl 0x10(%rdi), %ecx
testl %ecx, %ecx
je 0x16680b2
pushq %r15
pushq %r14
pushq %rbx
movq (%rdi), %rdi
movl (%rsi), %eax
movl 0x8(%rsi), %r8d
movl %eax, %r9d
shrl $0x4, %r9d
shrl $0x9, %eax
xorl %r9d, %eax
movl %r8d, %r9d
shrl $0x4, %r9d
shrl $0x9, %r8d
xorl %r9d, %r8d
shlq $0x20, %rax
orq %rax, %r8
movabsq $-0x40a7b89... | /llvm/ADT/DenseMap.h |
llvm::DIEHash::hashShallowTypeReference(llvm::dwarf::Attribute, llvm::DIE const&, llvm::StringRef) | void DIEHash::hashShallowTypeReference(dwarf::Attribute Attribute,
const DIE &Entry, StringRef Name) {
// append the letter 'N'
addULEB128('N');
// the DWARF attribute code (DW_AT_type or DW_AT_friend),
addULEB128(Attribute);
// the context of the tag,
if (const DIE ... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0x18, %rsp
movq %r8, 0x10(%rsp)
movq %rcx, %r15
movq %rdx, %r12
movl %esi, %ebp
movq %rdi, %rbx
leaq 0xd(%rsp), %rsi
movb $0x4e, (%rsi)
movl $0x1, %edx
callq 0x2b42f66
movl %ebp, %r14d
leaq 0xc(%rsp), %r13
movq %r14, %rbp
movl %r14d, %eax
andb $0x7... | /CodeGen/AsmPrinter/DIEHash.cpp |
llvm::DenseMapBase<llvm::DenseMap<llvm::DIE const*, unsigned int, llvm::DenseMapInfo<llvm::DIE const*, void>, llvm::detail::DenseMapPair<llvm::DIE const*, unsigned int>>, llvm::DIE const*, unsigned int, llvm::DenseMapInfo<llvm::DIE const*, void>, llvm::detail::DenseMapPair<llvm::DIE const*, unsigned int>>::clear() | unsigned getNumEntries() const {
return NumEntries;
} | movl 0x8(%rdi), %eax
testl %eax, %eax
jne 0x166a9eb
cmpl $0x0, 0xc(%rdi)
je 0x166aac4
shll $0x2, %eax
movl 0x10(%rdi), %ecx
cmpl %ecx, %eax
setae %al
cmpl $0x41, %ecx
setb %dl
orb %al, %dl
je 0x166af8e
testq %rcx, %rcx
je 0x166aabc
movq (%rdi), %rax
movabsq $0xfffffffffffffff, %rdx # imm = 0xFFFFFFFFFFFFFFF
addq %rdx, ... | /llvm/ADT/DenseMap.h |
llvm::DwarfCompileUnit::getOrCreateSourceID(llvm::DIFile const*) | unsigned DwarfCompileUnit::getOrCreateSourceID(const DIFile *File) {
// If we print assembly, we can't separate .file entries according to
// compile units. Thus all files will belong to the default compile unit.
// FIXME: add a better feature test than hasRawTextSupport. Even better,
// extend .file to suppor... | pushq %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $0xc8, %rsp
movq %rsi, %r13
movq %rdi, %rbx
movq 0xb8(%rdi), %rax
movq 0x50(%rax), %rdi
movq (%rdi), %rax
callq *0x68(%rax)
xorl %ebp, %ebp
testb %al, %al
jne 0x166b729
movl 0x48(%rbx), %ebp
testq %r13, %r13
je 0x166b7ba
cmpq %r13, 0x290(%rbx)
je 0x... | /CodeGen/AsmPrinter/DwarfCompileUnit.cpp |
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