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----[ 2.1 VIA C3 ALTINST Instructions
The VIA C3 processor has a unique instruction called ALTINST[9] (encoded as
0F 3F), which serves as an entry point to an undocumented alternate
instruction set. While the C3 technical manual acknowledges the existence
of this instruction set, it provides no further details. The manual
says: "This alternate instruction set is intended for testing, debugging,
and specialized applications. As such, it is not documented for general
use. If access to these instructions is required, contact your VIA
representative." However, research[10] and patents[11][12][13][14] suggest
that the VIA C3's ALTINST opcode unlocks an undocumented RISC-like
microcode ISA that bypasses x86 privilege enforcement, allowing ring 3 code
to execute ring 0 operations and circumvent memory protection checks.
To enable the alternate instruction set, the ALTINST bit must first be set
to 1 in the Feature Control Register (FCR) via WRMSR. If disabled
(ALTINST=0), executing the 0F 3F opcode triggers an Invalid Instruction
(#UD) exception. Once enabled, executing 0F 3F performs a near branch to
CS:EAX while simultaneously switching the processor into an internal mode,
interpreting subsequent instructions as the microcode and bypassing
standard privilege checks.
After executing the 0x0F3F gateway instruction, the processor expects
alternate instructions to be encoded within an LEA [EAX+EAX+disp32] opcode
sequence (0x8D8400XXXXXXXX), where the 32-bit displacement field (XXXXXXXX)
contains the actual micro-operation. The CPU internally extracts and
executes this payload while discarding the x86 LEA wrapper. This encoding
scheme is clever, because disassemblers typically interpret 0x0F3F as a NOP
instruction. The following bytes are then processed as a standard x86 LEA
operation, effectively concealing the alternate instruction stream within
what appears to be normal x86 code.
----[ 2.2 AMD Secret Password 0x9C5A203A
Model-Specific Registers (MSRs) are specialized control registers in the
x86 architecture, designed for tasks such as debugging, execution tracing,
performance monitoring, and enabling or disabling specific CPU features.
Access to these registers is performed using the RDMSR and WRMSR
instructions, which reference the target MSR via a 32-bit index.
Although most MSRs are documented, certain processors, particularly AMD's
Opteron (K8 microarchitecture), have undocumented MSRs that require
password to access. For example, on those processors, the password
0x9C5A203A unlocks hidden debugging functionality. According to internet
user Czernobyl[15], these undocumented MSRs are primarily used for
low-level debugging. To activate this feature, the password must first be
loaded into the EDI register. Failure to do so triggers a General
Protection Fault (GPF) exception.
An AMD white paper titled "Live Migration with AMD-V Extended Migration
Technology"[4] references password-protected MSRs. The document includes a
code example (shown below) demonstrating how a hypervisor or operating
system can disable reporting of the RDTSCP instruction on Second-Generation
AMD Opteron processors:
/*
* Example 3: Use MSR C001_1005 to clear bit 27 (RDTSCP) reported in
* EDX after CPUID Function 8000_0001
*/
/*
Read current value of the CPUID Override MSR C001_1005.
After RDMSR completes, EDX:EAX contains the 64bit MSR value.
EDX is loaded with the high 32 bits of the MSR and EAX is loaded
with the low 32 bits. The low 32 bits of this MSR are returned in
EDX after CPUID Function 8000_0001
*/
/*
Write the new EDX:EAX value into CPUID override MSR.
Second-Generation AMD Opteron Processors require a
32 bit password in EDI. Contact AMD to get the password.
*/
MOV EDI, <PASSWORD>
MOV CX, 0xC0011005h
RDMSR
/*
Clear bit 27 (RDTSCP) of EAX register
*/
ANDL EAX, 0xF7FFFFFFh
WRMSR
According to the white paper, the password (0x9C5A203A) is only necessary
for writing a specific bit in MSR c0011005h — a register that enables
access to additional undocumented features. While the document mentions
that the password must be obtained directly from AMD, it was accidentally
revealed in another whitepaper[34].
----[ 2.3 Candidate Backdoor Instructions