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recognizing predefined hash values, but the username transmitted in
cleartext can still serve as an alternative trigger.
A microcode-based prototype was also implemented on an Intel Pentium N4200
CPU (Goldmont microarchitecture) to validate the concept on commercial
hardware.
This paper is structured in three main sections. We begin by discussing
existing CPU backdoors to establish necessary background knowledge. Next,
we introduce and demonstrate our novel CPU backdoor design. Finally, we
discuss and conclude with our insights.
--[ 2. Known CPU "Backdoors"
When discussing CPU "backdoors," hidden instructions are a common concern.
For example, a single malicious instruction might grant the highest system
privileges. While CPU manufacturers document most instructions,
undocumented instructions do exist [5][6][7][8]. Actually, since all
instructions must comply the processor's encoding rules, it is not
difficult to enumerate all undocumented opcodes. These could either be
valid but undocumented instructions or simply reserved opcode space for
future use.
However, variable-length instruction sets (like x86) add complexity.
Undocumented extension bytes could exist, expanding the available encoding
space and potentially concealing more hidden opcodes.
The following is a portion of Intel's 2-byte opcode map for instructions
that start with the escape code 0F. The second byte is determined by its
row and column position in the map. For example, the INVD instruction
corresponds to 0F08, while WBINVD is encoded as 0F09. Some instructions
also require a prefix. VMOVAPD, for instance, is represented as 660F28,
where 66 is the prefix, 0F is the escape code, and 28 is the second byte
derived from the opcode map.
+--------------------------------------------- -------------------+
| |pfx| 8 | 9 | A | B | | E | F |
|--+---+--------+-------+----------+--------+- +--------+---------|
| 0| |INVD |WBINVD | |2-byte | | | |
| | | | | |illegal | ... | | |
| | | | | |opcodes | | | |
| | | | | | UD2 | | | |
|--+---+--------+-------+----------+---------- +--------+---------|
| 1| |Prefetch| |NOP /0 Ev|
| | |(Grp 16)| | |
|--+---+--------+-------+----------+---------- +--------+---------|
| | |vmovaps |vmovaps| cvtpi2ps |vmovntps| |vucomiss| vcomiss |
| | |Vps,Wps |Wps,Vps| Vps,Qpi |Mps,Vps | |Vss,Wss | Vss,Wss |
| |---+--------+-------+----------+--------+- ... +--------+---------|
| | 66|vmovapd |vmovapd| cvtpi2pd |vmovntpd| |vucomisd| vcomisd |
| | |Vpd,Wpd |Wpd,Vpd| Vpd,Qpi |Mpd,Vpd | |Vsd,Wsd | Vsd,Wsd |
| 2|---+--------+-------+----------+--------+- +--------+---------|
| | F3| | |vcvtsi2ss | | | | |
| | | | |Vss,Hss,Ey| | | | |
| |---+--------+-------+----------+--------+- +--------+---------|
| | F2| | |vcvtsi2sd | | | | |
| | | | |Vsd,Hsd,Ey| | ... | | |
|--+---+--------+-------+----------+--------+- +--------+---------|
| 3| | 3-byte | | 3-byte | | | | |
| | | escape | | escape | | | | |
|--+---+--------+-------+----------+--------+- +--------+---------|
| ... |
The opcode map includes several unassigned entries, such as 0F 0A, which
may indicate either undocumented or invalid instructions. Another example
is 0F 3F in the bottom-right corner, also left blank in Intel's
documentation. However, this particular opcode holds significance in VIA's
x86 CPUs, where it encodes the ALTINST (Alternate Instruction). While VIA's
manuals confirm the existence of ALTINST, they provide minimal technical
details, leaving the alternate instruction set largely undisclosed.
The seventh row of the map includes entries labeled "3-byte escape," which
denote instructions starting with the escape sequences 0F 38 or 0F 3A. To
enumerate these instructions, the corresponding 3-byte opcode map is
needed.
Although Intel's documentation suggests that 3-byte opcodes is the current
maximum length, nothing prevents additional escape codes in further bytes.
Notably, the gap between 0F 38 and 0F 3A, which is the unassigned 0F 39
raises intriguing questions: Is this an undocumented instruction, or could
it be an undocumented escape prefix? Similar question arise with other
blank entries in the map.
Some CPU instructions have hidden functionalities that are unlocked only
when specific values are set in registers. While the base instruction is
documented, its full capabilities may remain undisclosed unless the right
"key" (a particular register value) is provided.
For example, the CPUID instruction retrieves CPU information based on
register inputs, behaving like a standard feature. However, what if certain
register values could unlock deeper, undocumented functions? AMD CPUs
already use this method for some debugging features.
This approach has advantages. The instruction behaves normally without the
correct register value, its hidden functionality remains undetectable
unless the precise activation code is provided. Additionally, the risk of
accidental execution is minimal, especially on 64-bit systems, where the
chances of randomly entering the correct 64-bit "key" are very low.