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3.4.3 CMPS Backdoor Implementation
3.4.4 Installing Microcode Backdoors via Coreboot
3.4.5 The 0x0 Bytes Left Club
3.4.6 CRBUS, LDAT and Memory Arrays
4. Miscellaneous
4.1 X86 SSE/AVX Instruction Sets
4.2 Other Thoughts
5. Conclusion
6. Acknowledgements
7. References
8. Appendix: Code
--[ 1. Introduction
The concept of CPU backdoors is both fascinating and controversial. While
their existence is often debated, it's hard to believe that the major CPU
vendors (like Intel, AMD, ARM and IBM) or certain agencies have never
considered them. An effective CPU backdoor must be undetectable and
lethal, reserved only for breaching the most secure systems as a last
resort.
Current discussions often focus on undocumented instructions. The problem
is, those still require the attacker to already have some foothold in the
system. Instead, what if a backdoor embedded deep within the processor's
microarchitecture, could grant access to a system without requiring any
prior compromise?
Certainly, components like the Baseboard Management Controller (BMC) and
Intel's Management Engine (ME), along with their underlying controlling
bus, can fully control a system at the deepest level. However, these
features are at least partially documented and typically fall under the
broader category of Reliability, Availability, and Serviceability (RAS).
Customers should already be well aware of the risks when their devices are
marketed as remotely manageable.
The goal of this project is to implant a CPU backdoor by altering
instruction implementations. It is not meant to make a destructive
"halt-and-catch-fire" instruction. This backdoor is designed to subtly
manipulate critical instructions such as "CMP" that are involved in password
authentication, to bypass system security checks.
Imagine an attacker sitting down at a secured machine he's never touched
before, or connecting remotely. By entering one secret master password, he
can gain access to any account on the system.
Years ago, a security researcher demonstrated an attack on an ATM running
Windows XP by exploiting an exposed FireWire port. This port allowed direct
memory access from the connected peer machine, bypassing Windows XP's login
mechanism.
This is how the Windows password authentication works: when Windows system
received a password input, it would pad the string and generate a 16-byte
NTLM hash, which the system compared against stored credentials in the SAM
database via the MsvpPasswordValidate() function within msv1_0.dll.
By accessing the system's memory through the FireWire interface, the
attacker could patch the validation function to always return "true"
(rendering all passwords valid) or embed a predetermined hash to accept a
specific master password. This memory-level manipulation completely
circumvented Windows XP's security measures, granting unrestricted access
to any system account.
Surprisingly, the hash used is unsalted. Even Windows 10 still relies on
unsalted hashes (I haven't tested Windows 11 yet, as none of my machines or
VMs meet its requirements, but I suspect the situation remains unchanged).
A CPU password backdoor would be especially convenient due to the
predictability of unsalted hashing.
One challenge for hardware-level backdoors is that CPU cores operate at a
lower abstraction layer, stripping away OS-level context during instruction
execution. However, it is notable that operating system authentication
module has remained largely unchanged for years (all NT-based Windows
systems use the same authentication mechanism and libraries as just
described above, at least from Windows XP to Windows 10), whether by
deliberate design or simply due to the robustness of their implementation.
For the backdoor design, malicious circuitry is embedded into the CPU's
Arithmetic Logic Unit (ALU). When a specific hash value is compared, the
malicious circuitry manipulates the ALU to produce a false result, forcing
it to return a match regardless of the actual comparison. This manipulation
is triggered when the ALU operation originates from a CMP instruction
executed by the password authentication module (64-bit hashes derived from
the secret master key prevent false triggers). As a result, the master key
will be accepted as valid for any stored credentials, bypassing
authentication checks.
To validate this concept, I employed QEMU with TCG (Tiny Code Generator) to
demonstrate the backdoor on a virtual x86 machine running Windows.
To further verify the backdoor's feasibility on commercial hardware, I
implemented it in Verilog RTL for the OpenSPARC T1 (Sun Microsystems'
open-source UltraSPARC T1 variant) and deployed it on a Xilinx ML505
(Virtex-5 LX110T) FPGA board. This FPGA implementation enabled
cycle-accurate verification of the backdoor on actual CPU hardware.
Since Windows does not support SPARC-based systems, I installed a Linux
distribution instead and made adjustments to the backdoor. In Linux and
other Unix-like systems, the use of salted password hashes complicates
backdoor implementation. The salt prevents the CPU from directly