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output [7:0] exu_mmu_early_va_e;
output alu_ecl_add_n64_e;
output alu_ecl_add_n32_e;
output alu_ecl_log_n64_e;
output alu_ecl_log_n32_e;
output alu_ecl_zhigh_e;
output alu_ecl_zlow_e;
output exu_ifu_regz_e; // rs1_data == 0
output exu_ifu_regn_e;
output alu_ecl_adderin2_63_e;
output alu_ecl_adderin2_31_e;
output alu_ecl_adder_out_63_e;
output alu_ecl_cout32_e; // To ecl of sparc_exu_ecl.v
output alu_ecl_cout64_e_l; // To ecl of sparc_exu_ecl.v
output alu_ecl_mem_addr_invalid_e_l;
wire clk;
wire [63:0] logic_out; // result of logic block
wire [63:0] adder_out; // result of adder
wire [63:0] spr_out; // result of sum predict
wire [63:0] zcomp_in; // result going to zcompare
wire [63:0] va_e; // complete va
wire [63:0] byp_alu_rs2_data_e;
wire invert_e;
wire ecl_alu_out_sel_sum_e;
wire ecl_alu_out_sel_rs3_e;
wire ecl_alu_out_sel_shift_e;
wire ecl_alu_out_sel_logic_e;
assign clk = rclk;
assign byp_alu_rs2_data_e[63:0] = ~byp_alu_rs2_data_e_l[63:0];
assign ecl_alu_out_sel_sum_e = ~ecl_alu_out_sel_sum_e_l;
assign ecl_alu_out_sel_rs3_e = ~ecl_alu_out_sel_rs3_e_l;
assign ecl_alu_out_sel_shift_e = ~ecl_alu_out_sel_shift_e_l;
assign ecl_alu_out_sel_logic_e = ~ecl_alu_out_sel_logic_e_l;
// Zero comparison for exu_ifu_regz_e
sparc_exu_aluzcmp64 regzcmp(.in(byp_alu_rcc_data_e[63:0]),
.zero64(exu_ifu_regz_e));
assign exu_ifu_regn_e = byp_alu_rcc_data_e[63];
// mux between adder output and rs1 (for casa) for lsu va
dp_mux2es #(64) lsu_va_mux(.dout(va_e[63:0]),
.in0(adder_out[63:0]),
.in1(byp_alu_rs1_data_e[63:0]),
.sel(ifu_lsu_casa_e));
assign exu_lsu_ldst_va_e[47:0] = va_e[47:0];
// for bits 10:4 we have a separate bus that is not used for cas
assign exu_lsu_early_va_e[10:3] = adder_out[10:3];
// mmu needs bits 7:0
assign exu_mmu_early_va_e[7:0] = adder_out[7:0];
// Adder
assign exu_ifu_brpc_e[47:0] = adder_out[47:0];
assign alu_ecl_adder_out_63_e = adder_out[63];
sparc_exu_aluaddsub addsub(.adder_out(adder_out[63:0]),
/*AUTOINST*/
// Outputs
.spr_out (spr_out[63:0]),
.alu_ecl_cout64_e_l(alu_ecl_cout64_e_l),
.alu_ecl_cout32_e(alu_ecl_cout32_e),
.alu_ecl_adderin2_63_e(alu_ecl_adderin2_63_e),
.alu_ecl_adderin2_31_e(alu_ecl_adderin2_31_e),
// Inputs
.clk (clk),
.se (se),
.byp_alu_rs1_data_e(byp_alu_rs1_data_e[63:0]),
.byp_alu_rs2_data_e(byp_alu_rs2_data_e[63:0]),
.ecl_alu_cin_e(ecl_alu_cin_e),
.ecl_alu_rd_e(ecl_alu_rd_e), // uty: test
.ifu_exu_invert_d(ifu_exu_invert_d));
// Logic/pass rs2_data
dff_s invert_d2e(.din(ifu_exu_invert_d), .clk(clk), .q(invert_e),
.se(se), .si(), .so());
sparc_exu_alulogic logic(.rs1_data(byp_alu_rs1_data_e[63:0]),
.rs2_data(byp_alu_rs2_data_e[63:0]),
.isand(ecl_alu_log_sel_and_e),
.isor(ecl_alu_log_sel_or_e),
.isxor(ecl_alu_log_sel_xor_e),
.pass_rs2_data(ecl_alu_log_sel_move_e),
.inv_logic(invert_e), .logic_out(logic_out[63:0]),
.ifu_exu_sethi_inst_e(ecl_alu_sethi_inst_e));
// Mux between sum predict and logic outputs for zcc
dp_mux2es #(64) zcompmux(.dout(zcomp_in[63:0]),
.in0(logic_out[63:0]),
.in1(spr_out[63:0]),
.sel(ecl_alu_out_sel_sum_e));
// Zero comparison for zero cc
// sparc_exu_aluzcmp64 zcccmp(.in(zcomp_in[63:0]),
// .zero64(alu_ecl_z64_e),
// .zero32(alu_ecl_z32_e));
assign alu_ecl_zlow_e = ~(|zcomp_in[31:0]);
assign alu_ecl_zhigh_e = ~(|zcomp_in[63:32]);
// Get Negative ccs
assign alu_ecl_add_n64_e = adder_out[63];
assign alu_ecl_add_n32_e = adder_out[31];