text stringlengths 0 1.99k |
|---|
08: 1 0x01d6 0x7c6a |
09: 1 0x2e44 0x7cbe |
10: 1 0x70fa 0x7c9e |
11: 1 0x13c2 0x7cea |
12: 1 0x67a0 0x7c6e |
13: 1 0x0cd2 0x7c82 |
14: 1 0x209c 0x28d8 |
15: 1 0x141e 0x7c96 |
16: 1 0x24bc 0x7c8a |
17: 1 0x623a 0x7d16 |
18: 0 0x0000 0x0000 |
19: 0 0x0000 0x0000 |
20: 0 0x0000 0x0000 |
21: 0 0x0000 0x0000 |
22: 0 0x0000 0x0000 |
23: 0 0x0000 0x0000 |
24: 0 0x0000 0x0000 |
25: 0 0x0000 0x0000 |
26: 0 0x0000 0x0000 |
27: 0 0x0000 0x0000 |
28: 0 0x0000 0x0000 |
29: 0 0x0000 0x0000 |
30: 0 0x0000 0x0000 |
31: 0 0x0000 0x0000 |
--[ 3.4.6 CRBUS, LDAT and Memory Arrays |
An important aspect need to be covered is how data is read from MSROM and |
written to MSRAM. These operations rely on two critical components: CRBUS |
and LDAT. Since I'm still learning about these systems myself, I'll explain |
them to the best of my understanding. |
It makes sense for a processor to have an internal bus capable of |
monitoring the status of all its components. Such a bus would be essential |
for tasks like resetting hardware to predefined states, enabling or |
disabling specific features, and reading diagnostic data. While not |
documented in public specifications, these internal buses appear to exist |
across major architectures, such as Intel CRBUS (Configuration Register |
Bus) and IBM PIB (Pervasive Interconnect Bus). |
The CRBUS can be accessed through multiple interfaces[31]. One method is |
via the TAP (Test Access Port) which is a logic block responsible for |
executing tests and managing data flow along the boundary cells. In |
practice, this is commonly referred to as JTAG access. |
The following CRBUS read/write implementation is extracted from the TXE-POC |
project [23]: |
def crbus_read(addr): |
glm0 = ipc.devs.glm_module0 |
crbus_val = (0x3 << 79) | (addr << 65) |
ipc.irdrscan(glm0, 0xa8, 83, None, crbus_val, False) |
val = ipc.irdrscan(glm0, 0xa9, 83) |
data = (val & ((1 << 0x41) - 1)) >> 1 |
return data |
def crbus_write(addr, val): |
glm0 = ipc.devs.glm_module0 |
crbus_val = (0x1 << 80) | (addr << 65) | ((val &((1 << 64 ) -1)) << 1) |
ipc.irdrscan(glm0, 0xa8, 83, None, crbus_val, False) |
The implementation utilizes ipccli lib's irdrscan function (from Intel |
System Studio) which performs combined IR/DR scan operations through the |
JTAG interface. |
irdrscan(device, instruction, bitCount, data=None, writeData=None, |
returnData=True) |
Perform a combined IR/DR scan to the specified device, passing in the |
specified instruction for the IR scan and the specified bit count for |
the DR scan. |
Parameters |
device (int) – the did or alias of the device (not needed if using |
from a node object). |
instruction (int) – The instruction to scan into the device. |
bitCount (int) – The number of bits to scan from the data register of |
the designated device as selected by the current |
instruction register handle. |
data (int) – can specify this or writeData with a number or BitData |
object to write to the device (see note about backwards |
compatibility). |
writeData (int) – a number or BitData object to write to the device. |
returnData (bool) – whether to return the data from the scan that was |
done. |
Returns |
A BitData object containing the bits that were read back. |
The second parameter specifies the instruction to be scanned into the |
device. While the exact meaning of the "0xa8" used in the Python code above |
seems to be undocumented, it may correspond to "CRBUS" instruction as |
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