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referenced in a Intel patent[31]."
According to the patent, the CRBUS consists of one 32-bit CR DATA BUS and
10-bit CR ADDRESS & W/R BUS. Two different TAP instructions, "CRBUS" and
"CRBUSNOGO", have been designed to perform the necessary accessing of
control registers. The CRBUS command instructs the TAP to access the
appropriate location and if it is a "write", to write the data to the
accessed register. If the operation is a "read," then the CRBUS command
instructs data to be read from the accessed register. The CRBUSNOGO
instruction is used (along with the CRBUS instruction) only for a read
operation, to shift the data out as a serial TDO signal.
The referenced patent dates back to 2000, and modern implementations may
differ significantly. For instance, the MSROM includes numerous control
registers with addresses exceeding 10 bits. For current analysis, we can
just treat CRBUS as an interconnect for accessing control registers
distributed across the chip.
An alternative method for accessing CRBUS is via the undocumented
instructions UDBGRD and UDBGWR, as disclosed by researchers Mark Ermolov,
Dmitry Sklyarov, and Maxim Goryachy and implemented in lib-micro. The
relevant code snippet is provided below.
__attribute__((always_inline))
u_result_t static inline udbgrd(uint64_t type, uint64_t addr) {
lmfence();
u_result_t res;
asm volatile(
".byte 0x0F, 0x0E\n\t"
: "=d" (res.value)
, "=b" (res.status)
: "a" (addr)
, "c" (type)
);
lmfence();
return res;
}
__attribute__((always_inline))
u_result_t static inline udbgwr(uint64_t type, uint64_t addr,
uint64_t value) {
uint32_t value_low = (uint32_t)(value & 0xFFFFFFFF);
uint32_t value_high = (uint32_t)(value >> 32);
u_result_t res;
lmfence();
asm volatile(
".byte 0x0F, 0x0F\n\t"
: "=d" (res.value)
, "=b" (res.status)
: "a" (addr)
, "c" (type)
, "d" (value_low)
, "b" (value_high)
);
lmfence();
return res;
}
The opcodes for UDBGRD and UDBGWR are 0F0E and 0F0F, respectively.
Referring back to the opcode map in Section 2, the last two cells of the
first row are unassigned, indeed, these correspond to undocumented
instructions.
The RCX register specifies the target device to access. A value of 0x0
corresponds to the CRBUS, while 0x10 indicates URAM, which is a private
memory region exclusive to a single CPU core and not shared with others.
For CRBUS read or write operations, the RAX register holds the address of
the target control register.
For MSROM reads or MSRAM writes, the relevant control registers belong to
LDAT (Large Data Array Testing[29] or Local Direct Access Test[30]). As the
name suggests, the LDAT engine manages large data arrays.
The engine has four registers: SDAT, PDAT, DATIN, and DATOUT[29][32]. By
configuring SDAT/PDAT with address, array, bank, and other parameters,
specific memory arrays can be read or written. It is unclear to me how this
was reverse-engineered, whether through direct analysis or by referencing
some XML files containing register address definitions. Previous
research[30][32][27][33] provides these definitions, which I include here
for easy reference.
SDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+-----------+---+-------+-------+-------+-------+
| Port |Mod| DWord |ArrySel| |BankSel|
+-----------+---+-------+-------+-------+-------+
PDAT Bitfield:
3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+---------------+---+-----------+-------------------------------+
| | A1| | FastAddr |
+---------------+---+-----------+-------------------------------+
A1 Command fields:
| Encoding | Name |
+----------+--------+