id stringlengths 22 129 | text stringlengths 60 19.5k | arch stringclasses 9
values | syntax stringclasses 5
values | kind stringclasses 4
values | repo stringclasses 32
values | path stringlengths 7 108 | license stringclasses 10
values | commit stringlengths 40 40 | source_host stringclasses 1
value | category stringclasses 15
values | source_url stringlengths 85 192 | line_start int64 1 5.48k | line_end int64 4 5.5k |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
zephyrproject-rtos/zephyr:arch/arc/core/fast_irq.S:5 | /* restore interrupted context' sp */
pop sp
/*
* Keeping this code block close to those that use it allows using brxx
* instruction instead of a pair of cmp and bxx
*/
#if CONFIG_RGF_NUM_BANKS == 1
_pop_irq_stack_frame
#endif
rtie
.align 4
_firq_switch:
/* restore interrupted context' sp */
pop sp
#if CO... | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/fast_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fast_irq.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arc/core/fast_irq.S:6 | * if firq comes out in kernel mode, the following micro ops will be executed:
* sp<-reg bank'sp
* so, sw needs to do necessary handling to set up the correct sp
*/
lr r0, [_ARC_V2_AUX_IRQ_ACT]
bbit0 r0, 31, _firq_from_kernel
aex sp, [_ARC_V2_USER_SP]
lr r0, [_ARC_V2_STATUS32]
and r0, r0, ~_ARC_V2_STATUS32_... | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/fast_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fast_irq.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arc/core/fast_irq.S:7 | st _CAUSE_FIRQ, [r2, _thread_offset_to_relinquish_cause]
_irq_store_old_thread_callee_regs
/* mov new thread (r0) to r2 */
mov r2, r0
_load_new_thread_callee_regs
breq r3, _CAUSE_RIRQ, _firq_switch_from_rirq
nop_s
breq r3, _CAUSE_FIRQ, _firq_switch_from_firq
nop_s
/* fall through */
.align 4
_firq_switch... | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/fast_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fast_irq.S | 241 | 298 |
zephyrproject-rtos/zephyr:arch/arc/core/fast_irq.S:8 | _set_misc_regs_irq_switch_from_irq
_pop_irq_stack_frame
ld ilink, [sp, -4] /* status32 into ilink */
sr ilink, [_ARC_V2_STATUS32_P0]
ld ilink, [sp, -8] /* pc into ilink */
#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
push_s blink
bl z_thread_mark_switched_in
pop_s blink
#endif
/* LP registers are already rest... | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/fast_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fast_irq.S | 281 | 298 |
zephyrproject-rtos/zephyr:arch/arc/core/fault_s.S:1 | /*
* Copyright (c) 2014 Wind River Systems, Inc.
* Copyright (c) 2018 Synopsys.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Fault handlers for ARCv2
*
* Fault handlers for ARCv2 processors.
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/fault_s.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fault_s.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arc/core/fault_s.S:2 | lr r0,[_ARC_V2_ERSEC_STAT]
st_s r0, [sp, ___isf_t_sec_stat_OFFSET]
#endif
LRR r0, [_ARC_V2_ERET]
STR r0, sp, ___isf_t_pc_OFFSET
LRR r0, [_ARC_V2_ERSTATUS]
STR r0, sp, ___isf_t_status32_OFFSET
.endm
/*
* The exception handling will use top part of interrupt stack to
* get smaller memory footprint, because except... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/fault_s.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fault_s.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arc/core/fault_s.S:3 | * stack. If this top part is used by interrupt handling,
* and exception is raised, then here it's guaranteed that
* exception handling has necessary stack to use
*/
MOVR ilink, sp
_get_curr_cpu_irq_stack sp
SUBR sp, sp, (CONFIG_ISR_STACK_SIZE - CONFIG_ARC_EXCEPTION_STACK_SIZE)
/*
* save caller saved regis... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/fault_s.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fault_s.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arc/core/fault_s.S:4 | /* Save old thread into switch handle which is required by z_sched_switch_spin which
* will be called during old thread abort.
*/
STR r2, r2, ___thread_t_switch_handle_OFFSET
MOVR r2, r0
#ifdef CONFIG_ARC_SECURE_FIRMWARE
/*
* sync up the ERSEC_STAT.ERM and SEC_STAT.IRM.
* use a fake interrupt return to sim... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/fault_s.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fault_s.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arc/core/fault_s.S:5 | #ifdef CONFIG_ARC_SECURE_FIRMWARE
mov_s r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
#else
MOVR r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
#endif
#ifdef CONFIG_ARC_NORMAL_FIRMWARE
push_s r2
mov_s r0, _ARC_V2_AUX_IRQ_ACT
mov_s r1, r3
mov_s r6, ARC_S_CALL_AUX_WRITE
sjli SJLI_CALL_ARC_SECURE
pop_s r2
#else
SRR r3, [_... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/fault_s.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fault_s.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arc/core/fault_s.S:6 | #ifdef CONFIG_USERSPACE
cmp ilink, _TRAP_S_CALL_SYSTEM_CALL
bne _do_non_syscall_trap
/* do sys_call */
mov ilink, K_SYSCALL_LIMIT
cmp r6, ilink
blo valid_syscall_id
mov_s r0, r6
mov_s r6, K_SYSCALL_BAD
valid_syscall_id:
/* create a sys call frame
* caller regs (r0 - 12) are saved in _create_irq_stack_frame... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/fault_s.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/fault_s.S | 201 | 236 |
zephyrproject-rtos/zephyr:arch/arc/core/isr_wrapper.S:1 | /*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Wrapper around ISRs with logic for context switching
*
*
* Wrapper installed in vector table for handling dynamic interrupts that accept
* a parameter.
*/
#include <offsets_short.h>
#includ... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/isr_wrapper.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arc/core/isr_wrapper.S:2 | Context switch explanation:
The context switch code is spread in these files:
isr_wrapper.s, switch.s, swap_macros.h, fast_irq.s, regular_irq.s
IRQ stack frame layout:
high address
status32
pc
lp_count
lp_start
lp_end
blink
r13
...
sp -> r0
low address
The context switch code adopts this standa... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/isr_wrapper.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arc/core/isr_wrapper.S:3 | CONFIG_RGF_NUM_BANKS==1 case:
Scratch registers are pushed onto the current stack just as they are with
RIRQ. See the above frame layout. Unlike RIRQ, the status32_p0 and ilink
registers are where status32 and the program counter are located, so these
need to be pushed.
CONFIG_RGF_NUM_BANKS!=1 case:
The FIRQ handler h... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/isr_wrapper.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arc/core/isr_wrapper.S:4 | needed in order to have code to save other registers. r0 is saved
first in the stack and restored later
CONFIG_RGF_NUM_BANKS!=1 case:
During early initialization, the sp in the 2nd register bank is made to
refer to _firq_stack. This allows for the FIRQ handler to use its own
stack. GPRs are banked, loop registers... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/isr_wrapper.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arc/core/isr_wrapper.S:5 | From FIRQ:
When CONFIG_RGF_NUM_BANKS==1, context switch is done as it is for RIRQ.
When CONFIG_RGF_NUM_BANKS!=1, the processor is put back to using bank0,
not bank1 anymore, because it had to save the outgoing context from
bank0, and now has to load the incoming one into bank0.
o to coop
The address of the ret... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/isr_wrapper.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arc/core/isr_wrapper.S:6 | interrupt.
*/
SECTION_FUNC(TEXT, _isr_wrapper)
#ifdef CONFIG_ARC_FIRQ
#if CONFIG_RGF_NUM_BANKS == 1
/* free r0 here, use r0 to check whether irq is firq.
* for rirq, as sp will not change and r0 already saved, this action
* in fact is useless
* for firq, r0 will be restored later
*/
push r0
#endif
lr r0, [_AR... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/isr_wrapper.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arc/core/isr_wrapper.S:7 | #else
MOVR r3, _rirq_exit
MOVR r2, _rirq_enter
j_s [r2]
#endif
/* r0, r1, and r3 will be used in exit_tickless_idle macro */
.macro exit_tickless_idle
#if defined(CONFIG_PM)
clri r0 /* do not interrupt exiting tickless idle operations */
MOVR r1, _kernel
breq r3, 0, _skip_pm_save_idle_exit
st 0, [r1, _kernel_o... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/isr_wrapper.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arc/core/isr_wrapper.S:8 | bl z_sched_usage_stop
#endif
#ifdef CONFIG_TRACING_ISR
bl sys_trace_isr_enter
#endif
/* cannot be done before this point because we must be able to run C */
exit_tickless_idle
lr r0, [_ARC_V2_ICAUSE]
/* handle software triggered interrupt */
lr r3, [_ARC_V2_AUX_IRQ_HINT]
brne r3, r0, irq_hint_handled
sr 0, [_... | arm64 | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/isr_wrapper.S | 281 | 327 |
zephyrproject-rtos/zephyr:arch/arc/core/regular_irq.S:1 | /*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Handling of transitions to-and-from regular IRQs (RIRQ)
*
* This module implements the code for handling entry to and exit from regular
* IRQs.
*
* See isr_wrapper.S for details.
*/
#include <z... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/regular_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/regular_irq.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arc/core/regular_irq.S:2 | - Explicitly yielding
- Bumping into locked sync primitive etc
What (3) means is before passing control to another thread our thread
in question:
a. Stashed all precious caller-saved registers on its stack
b. Pushed return address to the top of the stack as well
That's how thread's stack looks like right befor... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/regular_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/regular_irq.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arc/core/regular_irq.S:3 | | \- FP
| ...
--------------------------------------
| Return address; PC (Program Counter)
--------------------------------------
| STATUS32 value
--------------------------------------
| Caller-saved registers: some of R0-R12
-----------------... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/regular_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/regular_irq.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arc/core/regular_irq.S:4 | will happen. So if we do nothing special we'll end-up with that:
----------------------------->8---------------------------------
lower_addr, let's say: 0x1000
--------------------------------------
# | Return address; PC (Program Counter)
| --------------------------------------
| | ST... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/regular_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/regular_irq.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arc/core/regular_irq.S:5 | | --------------------------------------
# | STATUS32 value
--------------------------------------
| Caller-saved registers: R0-R12
--------------------------------------
|...
| < Some data on thread's stack>
|...
higher_addr, let's say: 0x2000
--------... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/regular_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/regular_irq.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arc/core/regular_irq.S:6 | SECTION_FUNC(TEXT, _rirq_enter)
/* the ISR will be handled in separate interrupt stack,
* so stack checking must be diabled, or exception will
* be caused
*/
_disable_stack_checking r2
clri
/* check whether irq stack is used, if
* not switch to isr stack
*/
_check_and_inc_int_nest_counter r0, r1
bne.d ri... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/regular_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/regular_irq.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arc/core/regular_irq.S:7 | /* sp is struct k_thread **old of z_arc_switch_in_isr which is a wrapper of
* z_get_next_switch_handle. r0 contains the 1st thread in ready queue. If it isn't NULL,
* then do switch to this thread.
*/
_get_next_switch_handle
CMPR r0, 0
beq _rirq_no_switch
#ifdef CONFIG_ARC_SECURE_FIRMWARE
/* here need to re... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/regular_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/regular_irq.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arc/core/regular_irq.S:8 | _rirq_switch_from_coop:
/* for a cooperative switch, it's not in irq, so
* need to set some regs for irq return
*/
_set_misc_regs_irq_switch_from_coop
/*
* See verbose explanation of
* RETURN FROM INTERRUPT TO COOPERATIVE THREAD above
*/
/* carve fake stack */
SUBR sp, sp, ___isf_t_pc_OFFSET
#ifdef ... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/regular_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/regular_irq.S | 281 | 335 |
zephyrproject-rtos/zephyr:arch/arc/core/regular_irq.S:9 | .align 4
_rirq_switch_from_firq:
_rirq_switch_from_rirq:
_set_misc_regs_irq_switch_from_irq
#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
PUSHR blink
bl z_thread_mark_switched_in
POPR blink
#endif
_rirq_no_switch:
rtie | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/regular_irq.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/regular_irq.S | 321 | 335 |
zephyrproject-rtos/zephyr:arch/arc/core/reset.S:2 | * Locking interrupts prevents anything from interrupting the CPU.
*
* When these steps are completed, jump to z_prep_c(), which will finish setting
* up the system for running C code.
*/
SECTION_SUBSEC_FUNC(TEXT,_reset_and__start,__reset)
SECTION_SUBSEC_FUNC(TEXT,_reset_and__start,__start)
/* lock interrupts: wil... | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/reset.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arc/core/reset.S:3 | lr r0, [_ARC_V2_STATUS32]
bset r0, r0, _ARC_V2_STATUS32_US_BIT
kflag r0
#endif
#ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS
lr r0, [_ARC_V2_STATUS32]
bset r0, r0, _ARC_V2_STATUS32_AD_BIT
kflag r0
#endif
/* Invalidate icache */
lr r0, [_ARC_V2_I_CACHE_BUILD]
and.f r0, r0, 0xff
bz.nd done_icache_invalidate
mov_... | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/reset.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arc/core/reset.S:4 | /*
* Init ARC internal architecture state
* Force to initialize internal architecture state to reset values
* For scenarios where board hardware is not re-initialized between tests,
* some settings need to be restored to its default initial states as a
* substitution of normal hardware reset sequence.
*/
#ifdef C... | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/reset.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arc/core/reset.S:5 | hw_pf_setup_done:
#endif
#if defined(CONFIG_SMP) || CONFIG_MP_MAX_NUM_CPUS > 1
_get_cpu_id r0
breq r0, 0, _primary_core_startup
/*
* Non-primary cores wait for primary core (core 0) to boot enough
*/
_secondary_core_wait:
#if CONFIG_MP_MAX_NUM_CPUS == 1
kflag 1
#endif
ld r1, [arc_cpu_wake_flag]
brne r0, r1, _... | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/reset.S | 161 | 215 |
zephyrproject-rtos/zephyr:arch/arc/core/reset.S:6 | mov_s r0, z_interrupt_stacks
mov_s r1, 0xaa
mov_s r2, CONFIG_ISR_STACK_SIZE
jl memset
#endif /* CONFIG_INIT_STACKS */
mov_s sp, INIT_STACK
add sp, sp, INIT_STACK_SIZE
#if defined(CONFIG_ARC_FIRQ_STACK)
jl z_arc_firq_stack_set
#endif
j z_prep_c | arm64 | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/reset.S | 201 | 215 |
zephyrproject-rtos/zephyr:arch/arc/core/secureshield/arc_secure.S:1 | /*
* Copyright (c) 2018 Synopsys.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
.macro clear_scratch_regs
mov r1, 0
mov r2, 0
mov r3, 0
mov r4, 0
mov r5, 0
mov r6, 0
mov r7, 0
mov r8, 0
mov r9, 0
mov r10, 0
mov r... | arm64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/secureshield/arc_secure.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/secureshield/arc_secure.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arc/core/secureshield/arc_secure.S:2 | GTEXT(arc_go_to_normal)
GTEXT(_arc_do_secure_call)
GDATA(arc_s_call_table)
SECTION_FUNC(TEXT, _arc_do_secure_call)
/* r0-r5: arg1-arg6, r6 is call id */
/* the call id should be checked */
/* disable normal interrupt happened when processor in secure mode ? */
/* seti (0x30 | (ARC_N_IRQ_START_LEVEL-1)) */
breq r... | arm64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/secureshield/arc_secure.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/secureshield/arc_secure.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arc/core/secureshield/arc_secure.S:3 | lr r0, [_ARC_V2_STATUS32]
and r0, r0, 0x1e
asr r0, r0
or r0, r0, 0x30
mov r6, (0x30 | (ARC_N_IRQ_START_LEVEL-1))
j.d [blink]
seti r6
_s_seti:
btst r0, 4
jnz __seti_0
mov r0, (CONFIG_NUM_IRQ_PRIO_LEVELS - 1)
lr r6, [_ARC_V2_STATUS32]
and r6, r6, 0x1e
asr r6, r6
cmp r0, r6
mov.hs r0, r6
__seti_0:
and r0,... | arm64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/secureshield/arc_secure.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/secureshield/arc_secure.S | 81 | 121 |
zephyrproject-rtos/zephyr:arch/arc/core/switch.S:2 | * of a cooperative call to arch_switch() has to be recorded via the
* _CAUSE_COOP code in the relinquish_cause of the thread's k_thread structure.
* The _rirq_exit()/_firq_exit() code will take care of doing the right thing
* to restore the thread status.
*
* When arch_switch() is invoked, we know the decision to ... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/switch.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arc/core/switch.S:3 | #endif
push_s r3
#endif
PUSHR blink
_store_old_thread_callee_regs
/* disable stack checking here, as sp will be changed to target
* thread'sp
*/
_disable_stack_checking r3
MOVR r2, r0
_load_new_thread_callee_regs
breq r3, _CAUSE_RIRQ, _switch_return_from_rirq
nop_s
breq r3, _CAUSE_FIRQ, _switch_return_... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/switch.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arc/core/switch.S:4 | bl z_thread_mark_switched_in
POPR blink
#endif
j_s [blink]
.align 4
_switch_return_from_rirq:
_switch_return_from_firq:
_set_misc_regs_irq_switch_from_irq
/* use lowest interrupt priority to simulate
* a interrupt return to load left regs of new
* thread
*/
LRR r3, [_ARC_V2_AUX_IRQ_ACT]
#ifdef CONFIG_A... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/switch.S | 121 | 161 |
zephyrproject-rtos/zephyr:arch/arc/core/thread_entry_wrapper.S:1 | /*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Wrapper for z_thread_entry
*
* Wrapper for z_thread_entry routine when called from the initial context.
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <v2/irq.h... | arm64 | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arc/core/thread_entry_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/thread_entry_wrapper.S | 1 | 58 |
zephyrproject-rtos/zephyr:arch/arc/core/userspace.S:1 | /*
* Copyright (c) 2018 Synopsys.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <offsets_short.h>
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/kernel_structs.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/syscall.h>
#include <swap_macros.h>
#include <v2/irq.h>
.macro ... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/userspace.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arc/core/userspace.S:2 | mov_s r16, 0
mov_s r15, 0
mov_s r14, 0
mov_s r13, 0
.endm
GTEXT(z_arc_userspace_enter)
GTEXT(_arc_do_syscall)
GTEXT(z_user_thread_entry_wrapper)
GTEXT(arch_user_string_nlen)
GTEXT(z_arc_user_string_nlen_fault_start)
GTEXT(z_arc_user_string_nlen_fault_end)
GTEXT(z_arc_user_string_nlen_fixup)
/**
* @brief Wrapper ... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/userspace.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arc/core/userspace.S:3 | j _arc_go_to_user_space
/**
*
* User space entry function
*
* This function is the entry point to user mode from privileged execution.
* The conversion is one way, and threads which transition to user mode do
* not transition back later, unless they are doing system calls.
*
*/
SECTION_FUNC(TEXT, z_arc_userspa... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/userspace.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arc/core/userspace.S:4 | #endif
_clear_user_stack:
st.ab r0, [r4, 4]
cmp r4, r5
jlt _clear_user_stack
/* reload the stack checking regs as the original kernel stack
* becomes user stack
*/
#ifdef CONFIG_ARC_STACK_CHECKING
/* current thread in r6, SMP case is also considered */
mov r2, r6
_load_stack_check_regs
_enable_stack_checking... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/userspace.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arc/core/userspace.S:5 | lr r0, [_ARC_V2_SEC_STAT]
/* the mode returns from exception return is secure mode */
bset r0, r0, 31
sr r0, [_ARC_V2_ERSEC_STAT]
sr r5, [_ARC_V2_SEC_U_SP]
#else
sr r5, [_ARC_V2_USER_SP]
#endif
mov_s sp, blink
mov_s r0, 0
clear_callee_regs
clear_scratch_regs
mov fp, 0
mov r29, 0
mov r30, 0
mov blink, 0... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/userspace.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arc/core/userspace.S:6 | * optimized.
*/
ld_s r0, [sp, ___isf_t_r0_OFFSET]
ld_s r1, [sp, ___isf_t_r1_OFFSET]
ld_s r2, [sp, ___isf_t_r2_OFFSET]
mov r7, sp
mov_s blink, _k_syscall_table
ld.as r6, [blink, r6]
jl [r6]
/* save return value */
st_s r0, [sp, ___isf_t_r0_OFFSET]
mov r29, 0
mov r30, 0
/* through fake exception retur... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/userspace.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arc/core/userspace.S:7 | * size_t arch_user_string_nlen(const char *s, size_t maxsize, int *err_arg)
*/
SECTION_FUNC(TEXT, arch_user_string_nlen)
/* int err; */
sub_s sp,sp,0x4
/* Initial error value (-1 failure), store at [sp,0] */
mov_s r3, -1
st_s r3, [sp, 0]
/* Loop setup.
* r12 (position locator) = s - 1
* r0 (length counter ... | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/userspace.S | 241 | 290 |
zephyrproject-rtos/zephyr:arch/arc/core/userspace.S:8 | not_null:
/* check if we've hit the maximum, if so we're done. */
brne.d.nt lp_count, 0x1, inc_len
sub lp_count, lp_count, 0x1
b_s strlen_done
inc_len:
/* increment length measurement, loop again */
add_s r0, r0, 1
b_s strlen_loop | x86_64 | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arc/core/userspace.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arc/core/userspace.S | 281 | 290 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/__aeabi_read_tp.S:1 | /*
* Copyright (c) 2020 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
_ASM_FILE_PROLOGUE
GTEXT(__aeabi_read_tp)
SECTION_FUNC(text, __aeabi_read_tp)
/*
* TPIDRURW will be used as a base pointer point to TLS aera.
*/
mrc p15, 0, r0, c13, c0, 2
bx lr | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/__aeabi_read_tp.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/__aeabi_read_tp.S | 1 | 18 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/cpu_idle.S:1 | /*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-A and Cortex-R power management
*
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
#include <soc_cpu_idle.h>
#endif
_A... | arm | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/cpu_idle.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/cpu_idle.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/cpu_idle.S:2 | #if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
/* Inline the macro provided by SoC-specific code */
SOC_ON_EXIT_CPU_IDLE
#endif /* CONFIG_ARM_ON_EXIT_CPU_IDLE */
#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
_skip_\@:
pop {r0, lr}
#endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */
.endm
#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_I... | arm | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/cpu_idle.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/cpu_idle.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/cpu_idle.S:3 | /*
* Lock PRIMASK while sleeping: wfe will still get interrupted by
* incoming interrupts but the CPU will not service them right away.
*/
cpsid i
/* r0: interrupt mask from caller */
/* No BASEPRI, call wfe directly
*/
_sleep_if_allowed wfe
cmp r0, #0
bne _irq_disabled
cpsie i
_irq_disabled:
bx lr
... | arm | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/cpu_idle.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/cpu_idle.S | 81 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc.S:1 | /*
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Exception handlers for ARM Cortex-A and Cortex-R
*
* This file implements the exception handlers (undefined instruction, prefetch
* abort and data abort) for ARM Cortex-A and Cortex-... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc.S:2 | GTEXT(z_arm_undef_instruction)
GTEXT(z_arm_prefetch_abort)
GTEXT(z_arm_data_abort)
#ifndef CONFIG_USE_SWITCH
.macro exception_entry mode
/*
* Store r0-r3, r12, lr, lr_und and spsr_und into the stack to
* construct an exception stack frame.
*/
srsdb sp!, #\mode
stmfd sp, {r0-r3, r12, lr}^
sub sp, #24
#if de... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc.S:3 | cps #MODE_SYS
stm r1, {r4-r11, sp}
cps #\mode
mov r0, sp
mov sp, r1
#else
mov r0, sp
#endif
/* Increment exception nesting count */
get_cpu r2
ldr r1, [r2, #___cpu_t_nested_OFFSET]
add r1, r1, #1
str r1, [r2, #___cpu_t_nested_OFFSET]
.endm
.macro exception_exit
/* Exit exception */
#if defined(CONFIG_EXTR... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc.S:4 | subeq lr, #4 /* ARM (!T_BIT) */
subne lr, #2 /* Thumb (T_BIT) */
pop {r0}
/*
* Store r0-r3, r12, lr, lr_und and spsr_und into the stack to
* construct an exception stack frame.
*/
srsdb sp!, #MODE_UND
stmfd sp, {r0-r3, r12, lr}^
sub sp, #24
/* Increment exception nesting count */
get_cpu r2
ldr r1, [... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc.S:5 | sub sp, #___extra_esf_info_t_SIZEOF
mov r0, #0
str r0, [sp, #4]
str r0, [sp, #8]
sub r1, sp, #___callee_saved_t_SIZEOF
str r1, [sp]
cps #MODE_SYS
stm r1, {r4-r11, sp}
cps #MODE_UND
mov r0, sp
mov sp, r1
#else
mov r0, sp
#endif
bl z_arm_fault_undef_instruction
exception_exit
b z_arm_exc_exit
/**
* @b... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc.S:6 | #if defined(CONFIG_FPU_SHARING)
#define FPU_SF_SIZE ___fpu_t_SIZEOF
#else
#define FPU_SF_SIZE 0
#endif
/**
* @brief Data abort exception handler
*
* A data abort (DABT) exception is generated when an error occurs on a data
* memory access. This exception can be either synchronous or asynchronous,
* depending on t... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc.S:7 | GTEXT(z_arm_cortex_ar_exit_exc)
SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc)
/* Note:
* This function is expected to be *always* called with
* processor mode set to MODE_SYS.
*/
/* decrement exception depth */
get_cpu r2
ldrb r1, [r2, #_cpu_offset_to_exc_depth]
sub r1, r1, #1
strb... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc.S:8 | z_arm_cortex_ar_enter_exc
bl z_arm_fault_undef_instruction
b z_arm_cortex_ar_exit_exc
/**
* @brief Prefetch abort exception handler
*
* A prefetch abort (PABT) exception is generated when the processor marks the
* prefetched instruction as invalid and the instruction is executed.
*/
SECTION_SUBSEC_FUNC(TEXT, __... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc.S | 281 | 315 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc_exit.S:1 | /*
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
* Copyright (c) 2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-A and Cortex-R exception/interrupt exit API
*
* Provides functions for performing kernel handling when exiting exceptions,
*... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc_exit.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc_exit.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc_exit.S:2 | * svc stack since we cannot trust the usr stack.
*/
cps #MODE_SYS
pop {r0-r1}
cps #MODE_SVC
str r0, [sp, #8]
str r1, [sp, #12]
/* Only switch the stacks if returning to a user thread */
and r1, #MODE_MASK
cmp r1, #MODE_USR
bne system_thread_exit\@
/* Restore user stack pointer */
get_cpu r0
ldr r0, [r0... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc_exit.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc_exit.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc_exit.S:3 | cmp r0, #0
moveq r1, #0
streq r1, [r2, #___cpu_t_fp_ctx_OFFSET]
b vfp_exit\@
vfp_restore\@:
add r3, sp, #___fpu_sf_t_fpscr_OFFSET
ldm r3, {r1, r2}
tst r2, #FPEXC_EN
beq vfp_exit\@
vmsr fpexc, r2
vmsr fpscr, r1
mov r3, sp
vldmia r3!, {s0-s15}
#ifdef CONFIG_VFP_FEATURE_REGS_S64_D32
vldmia r3!, {d16-d31}
#en... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc_exit.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc_exit.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc_exit.S:4 | *
* e.g.
*
* void myISR(void)
* {
* printk("in %s\n", __FUNCTION__);
* doStuff();
* z_arm_int_exit();
* }
*/
SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_int_exit)
#ifdef CONFIG_STACK_SENTINEL
bl z_check_stack_sentinel
#endif /* CONFIG_STACK_SENTINEL */
/* Disable nested interrupts while exiting, t... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc_exit.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc_exit.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc_exit.S:5 | str r0, [r2, #___cpu_t_nested_OFFSET]
/* Restore previous stack pointer */
pop {r2, r3}
add sp, sp, r3
/*
* Restore lr_svc stored into the SVC mode stack by the mode entry
* function. This ensures that the return address of the interrupted
* context is preserved in case of interrupt nesting.
*/
pop {lr}
... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc_exit.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc_exit.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc_exit.S:6 | * If exiting a non-nested fatal exception, the exit routine, assuming that the
* current faulting thread is aborted, discards the saved exception stack
* frame containing the aborted thread context and switches to the next
* scheduled thread.
*
* void z_arm_exc_exit(bool fatal)
*
* @param fatal True if exiting f... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc_exit.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc_exit.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/exc_exit.S:7 | bl z_arm_do_swap
/* Decrement exception nesting count */
get_cpu r3
ldr r0, [r3, #___cpu_t_nested_OFFSET]
sub r0, r0, #1
str r0, [r3, #___cpu_t_nested_OFFSET]
/* Return to the switched thread */
cps #MODE_SYS
#if defined(CONFIG_FPU_SHARING)
fpu_exc_exit
#endif
pop {r0-r3, r12, lr}
userspace_exc_exit
rfeia ... | arm | intel-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/exc_exit.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/exc_exit.S | 241 | 273 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:1 | /*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-A and Cortex-R wrapper for ISRs with parameter
*
* Wrapper installed in vector table for handling dynamic interrupts tha... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:2 | * using the running interrupt number as the index, and invokes the registered
* ISR with its corresponding argument. When returning from the ISR, it
* determines if a context switch needs to happen (see documentation for
* z_arm_pendsv()) and pends the PendSV exception if so: the latter will
* perform the context s... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:3 | * and spsr_irq since we may swap processes and return to a different
* thread.
*/
sub lr, lr, #4
srsdb #MODE_SYS!
cps #MODE_SYS
push {r0-r3, r12, lr}
#if defined(CONFIG_FPU_SHARING)
sub sp, sp, #___fpu_t_SIZEOF
/*
* Note that this handler was entered with the VFP unit enabled.
* The undefined instructio... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:4 | * in the SYS/USR mode stack (i.e. interrupted thread stack) leaves the
* ISR stack usage at the mercy of the interrupted thread and this can
* be prone to stack overflows if any of the ISRs and/or preemptible
* threads have high stack usage.
*
* When userspace is enabled, this also prevents leaking privileged... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:5 | */
/* is this a wakeup from idle ? */
ldr r2, =_kernel
/* requested idle duration, in ticks */
ldr r0, [r2, #_kernel_offset_to_idle]
cmp r0, #0
beq _idle_state_cleared
movs r1, #0
/* clear kernel idle state */
str r1, [r2, #_kernel_offset_to_idle]
bl pm_system_resume
_idle_state_cleared:
#endif /* CONFIG_P... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:6 | */
mov r1, #CONFIG_NUM_IRQS
lsl r1, r1, #3
cmp r0, r1
bge spurious_continue
ldr r1, =_sw_isr_table
add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
* in thumb mode */
ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
blx r3 /* call ISR */
spurious_continue:
/* Signal end-of-interrupt */
po... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:7 | * determines if a context switch needs to happen and invoke the arch_switch
* function if so.
*
*/
SECTION_FUNC(TEXT, _isr_wrapper)
sub lr, #4
z_arm_cortex_ar_enter_exc
/* Increment interrupt nesting count */
get_cpu r2
ldr r0, [r2, #___cpu_t_nested_OFFSET]
add r0, #1
str r0, [r2, #___cpu_t_nested_OFFSET]
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:8 | beq _idle_state_cleared
movs r1, #0
/* clear kernel idle state */
str r1, [r2, #_kernel_offset_to_idle]
bl pm_system_resume
_idle_state_cleared:
#endif /* CONFIG_PM */
/* Get active IRQ number from the interrupt controller */
#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
bl arm_gic_get_active
#else
bl z_... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:9 | /* Signal end-of-interrupt */
pop {r0, r1}
#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
bl arm_gic_eoi
#else
bl z_soc_irq_eoi
#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
#ifdef CONFIG_TRACING_ISR
bl sys_trace_isr_exit
#endif
GTEXT(z_arm_cortex_ar_irq_done)
z_arm_cortex_ar_irq_done:
/* Decrement ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/isr_wrapper.S:10 | bl z_get_next_switch_handle
pop {r1}
cmp r0, #0
beq __EXIT_INT
/*
* Switch thread
* r0: new thread
* r1: old thread
*/
bl z_arm_context_switch
__EXIT_INT:
#ifdef CONFIG_STACK_SENTINEL
bl z_check_stack_sentinel
#endif /* CONFIG_STACK_SENTINEL */
b z_arm_cortex_ar_exit_exc
#endif | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/isr_wrapper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/isr_wrapper.S | 361 | 382 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/macro_priv.inc:1 | /*
* Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MACRO_PRIV_INC_
#define _MACRO_PRIV_INC_
#include <zephyr/arch/arm/cortex_a_r/tpidruro.h>
/*
* Get CPU id
*/
.macro get_cpu_id rreg0
/* Read MPIDR register */
mrc p15, 0, \rreg0, c0... | arm | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/macro_priv.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/macro_priv.inc | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/macro_priv.inc:2 | .macro get_cpu rreg0
/*
* Get CPU pointer.
*/
mrc p15, 0, \rreg0, c13, c0, 3
and \rreg0, #TPIDRURO_CURR_CPU
.endm
.macro z_arm_cortex_ar_enter_exc
/*
* Store r0-r3, r12, lr into the stack to construct an exception
* stack frame.
*/
srsdb sp!, #MODE_SYS
cps #MODE_SYS
push {r0-r3, r12, lr}... | arm | gas-like | macro-heavy | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/macro_priv.inc | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/macro_priv.inc | 41 | 69 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:2 | *
* Ran when the system comes out of reset. The processor is in Supervisor mode
* and interrupts are disabled. The processor architectural registers are in
* an indeterminate state.
*
* When these steps are completed, jump to z_prep_c(), which will finish
* setting up the system for running C code.
*
*/
#if def... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/reset.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:3 | */
/* Init HACTLR: Enable EL1 access to all IMP DEF registers */
ldr r0, =HACTLR_INIT
mcr p15, 4, r0, c1, c0, 1
/* Go to SVC mode */
mrs r0, cpsr
bic r0, #MODE_MASK
orr r0, #MODE_SVC
msr spsr_cxsf, r0
ldr r0, =EL1_Reset_Handler
msr elr_hyp, r0
dsb
isb
eret
EL1_Rese... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/reset.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:4 | mov r10, #0
mov r11, #0
mov r12, #0
mov r13, #0 /* r13_svc */
mov r14, #0 /* r14_svc */
mrs r0, cpsr
msr spsr_cxsf, r0 /* spsr_svc */
/* FIQ mode registers */
cps #MODE_FIQ
mov r8, #0 /* r8_fiq */
mov r9, #0 /* r9_fiq */
mov r10, #0 ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/reset.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:5 | /* SYS mode registers */
cps #MODE_SYS
mov r13, #0 /* r13_sys */
mov r14, #0 /* r14_sys */
#if defined(CONFIG_FPU) && defined(CONFIG_CPU_HAS_VFP)
/*
* Initialise FPU registers to a defined state.
*/
/* Allow VFP coprocessor access */
mrc p15, 0, r0, c1, c0, 2
orr ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/reset.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:6 | fmdrr d18, r1, r1
fmdrr d19, r1, r1
fmdrr d20, r1, r1
fmdrr d21, r1, r1
fmdrr d22, r1, r1
fmdrr d23, r1, r1
fmdrr d24, r1, r1
fmdrr d25, r1, r1
fmdrr d26, r1, r1
fmdrr d27, r1, r1
fmdrr d28, r1, r1
fmdrr d29, r1, r1
fmdrr d30, r1, r1
fmdrr d31, r1, r1
#endif /* CONFIG... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/reset.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:7 | add r4, r0, #BOOT_PARAM_VOTING_OFFSET
/* signal our desire to vote */
mov r5, #1
strb r5, [r4, r2]
mov r7, #0
ldr r3, [r0, #BOOT_PARAM_MPID_OFFSET]
cmn r3, #1
beq 1f
/* some core already won, release */
strb r7, [r4, r2]
b _secondary_core
/* suggest current core then relea... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/reset.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:8 | ldr r2, [r0, #BOOT_PARAM_MPID_OFFSET]
cmp r1, r2
bne _secondary_core
/* we can now load our stack pointer values and move on */
ldr r4, =arch_secondary_cpu_init
ldr r5, [r0, #BOOT_PARAM_FIQ_SP_OFFSET]
ldr r6, [r0, #BOOT_PARAM_IRQ_SP_OFFSET]
ldr r7, [r0, #BOOT_PARAM_ABT_SP_OFFSET]
ldr r8... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/reset.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:9 | mov sp, r7
/* UND mode stack */
msr CPSR_c, #(MODE_UND | I_BIT | F_BIT)
mov sp, r8
/* SVC mode stack */
msr CPSR_c, #(MODE_SVC | I_BIT | F_BIT)
mov sp, r9
/* SYS mode stack */
msr CPSR_c, #(MODE_SYS | I_BIT | F_BIT)
mov sp, r10
#if defined(CONFIG_SOC_RESET_HOOK)
/* Execute pl... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/reset.S | 321 | 351 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:1 | /*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Reset handler
*
* Reset handler that prepares the ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/reset.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:2 | *
* Ran when the system comes out of reset. The processor is in Supervisor mode
* and interrupts are disabled. The processor architectural registers are in
* an indeterminate state.
*
* When these steps are completed, jump to z_prep_c(), which will finish
* setting up the system for running C code.
*
*/
SECTION... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/reset.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:3 | EL1_Reset_Handler:
#endif
#if defined(CONFIG_DCLS)
/*
* Initialise CPU registers to a defined state if the processor is
* configured as Dual-redundant Core Lock-step (DCLS). This is required
* for state convergence of the two parallel executing cores.
*/
/* Common and SVC mode registers *... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/reset.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:4 | mrs r0, cpsr
msr spsr_cxsf, r0 /* spsr_fiq */
/* IRQ mode registers */
cps #MODE_IRQ
mov r13, #0 /* r13_irq */
mov r14, #0 /* r14_irq */
mrs r0, cpsr
msr spsr_cxsf, r0 /* spsr_irq */
/* ABT mode registers */
cps #MODE_ABT
mov r13, #0 /* r13_abt */
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/reset.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:5 | mov r0, #FPEXC_EN
vmsr fpexc, r0
/* Initialise VFP registers */
fmdrr d0, r1, r1
fmdrr d1, r1, r1
fmdrr d2, r1, r1
fmdrr d3, r1, r1
fmdrr d4, r1, r1
fmdrr d5, r1, r1
fmdrr d6, r1, r1
fmdrr d7, r1, r1
fmdrr d8, r1, r1
fmdrr d9, r1, r1
fmdrr d10, r1, r1
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/reset.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:6 | vmsr fpexc, r1
#endif /* CONFIG_FPU && CONFIG_CPU_HAS_VFP */
#endif /* CONFIG_DCLS */
#if defined(CONFIG_CPU_CORTEX_R52_CACHE_SEGREGATION)
ldr r0, =IMP_CSCTLR(CONFIG_CPU_CORTEX_R52_ICACHE_FLASH_WAY,
CONFIG_CPU_CORTEX_R52_DCACHE_FLASH_WAY)
mcr p15, 1, r0, c9, c1, 0
#endif
ldr r0, =... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/reset.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:7 | strb r7, [r4, r2]
dmb
/* then wait until every core else is done voting */
mov r5, #0
2: ldrb r3, [r4, r5]
tst r3, #255
/* wait */
bne 2b
add r5, r5, #1
cmp r5, #CONFIG_MP_MAX_NUM_CPUS
bne 2b
/* check if current core won */
dmb
ldr r3, [r0, #BOOT_PARAM_MPID_OFFSET]
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/reset.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:8 | ldr r4, =z_prep_c
ldr r5, =(z_arm_fiq_stack + CONFIG_ARMV7_FIQ_STACK_SIZE)
ldr r6, =(z_interrupt_stacks + CONFIG_ISR_STACK_SIZE)
ldr r7, =(z_arm_abort_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)
ldr r8, =(z_arm_undef_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)
ldr r9, =(z_arm_svc_stack + CONFIG_ARMV7_... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/reset.S | 281 | 334 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/reset.S:9 | #endif
#if defined(CONFIG_WDOG_INIT)
/* board-specific watchdog initialization is necessary */
bl z_arm_watchdog_init
#endif
#if defined(CONFIG_DISABLE_TCM_ECC)
bl z_arm_tcm_disable_ecc
#endif
bl z_arm_relocate_vector_table
bx r4 | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/reset.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/reset.S | 321 | 334 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:1 | /*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2017-2019 Nordic Semiconductor ASA.
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Thread context switching for ARM Cortex-A and Cortex-R
*
* This module impleme... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:2 | * in case of preemption, or z_arm_svc in case of cooperative switching.
*/
SECTION_FUNC(TEXT, z_arm_do_swap)
#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
/* Register the context switch */
push {r0, lr}
bl z_thread_mark_switched_out
pop {r0, lr}
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */
/* loa... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:3 | * used since this thread has used it. Consequently, the caller-saved
* float registers have not been saved away, so write them to the
* exception stack frame.
*/
ldr r0, [r1, #___cpu_t_fp_ctx_OFFSET]
cmp r0, #0
beq out_store_thread_context
vstmia r0!, {s0-s15}
#ifdef CONFIG_VFP_FEATURE_... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:4 | ldr r4, =_thread_offset_to_tls
adds r4, r2, r4
ldr r0, [r4]
/* Store TLS pointer in the "Process ID" register.
* TPIDRURW is used as a base pointer to all
* thread variables with offsets added by toolchain.
*/
mcr p15, 0, r0, c13, c0, 2
#endif
#if defined(CONFIG_ARM_STORE_EXC_RETURN)
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:5 | /* Restore s16-s31 from thread context */
add r0, r2, #_thread_offset_to_preempt_float
vldmia r0, {s16-s31}
mov r3, #0
vmsr fpexc, r3
in_fp_inactive:
#endif /* CONFIG_FPU_SHARING */
#if defined (CONFIG_ARM_MPU)
/* r2 contains k_thread */
mov r0, r2
/* Re-program dynamic memory map */
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 161 | 220 |
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