id stringlengths 22 129 | text stringlengths 60 19.5k | arch stringclasses 9
values | syntax stringclasses 5
values | kind stringclasses 4
values | repo stringclasses 32
values | path stringlengths 7 108 | license stringclasses 10
values | commit stringlengths 40 40 | source_host stringclasses 1
value | category stringclasses 15
values | source_url stringlengths 85 192 | line_start int64 1 5.48k | line_end int64 4 5.5k |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:6 | *
* The service call (svc) is used in the following occasions:
* - Cooperative context switching
* - IRQ offloading
* - Kernel run-time exceptions
*
*/
SECTION_FUNC(TEXT, z_arm_svc)
#if defined(CONFIG_USERSPACE)
/* Determine if incoming thread was in user context */
push {r0}
mrs r0, spsr
and r0, ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:7 | #if defined(CONFIG_FPU_SHARING)
sub sp, sp, #___fpu_t_SIZEOF
/*
* Note that this handler was entered with the VFP unit enabled.
* The undefined instruction handler uses this to know that it
* needs to save the current floating context.
*/
vmrs r0, fpexc
str r0, [sp, #___fpu_t_SIZEOF... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:8 | /* Align stack at double-word boundary */
/* TODO: Question, why push {r2, r3} here */
and r3, sp, #4
sub sp, sp, r3
push {r2, r3}
/* Increment interrupt nesting count */
get_cpu r2
ldr r0, [r2, #___cpu_t_nested_OFFSET]
add r0, r0, #1
str r0, [r2, #___cpu_t_nested_OFFSET]
/* Ge... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:9 | cmp r1, #_SVC_CALL_RUNTIME_EXCEPT
beq _oops
#if CONFIG_IRQ_OFFLOAD
blx z_irq_do_offload /* call C routine which executes the offload */
/* exception return is done in z_arm_int_exit() */
b z_arm_int_exit
#endif
_context_switch:
/* handler mode exit, to PendSV */
bl z_arm_do_swap
b z_arm... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:10 | *
* Registers look like:
* r0 - arg1
* r1 - arg2
* r2 - arg3
* r3 - arg4
* r4 - arg5
* r5 - arg6
* r6 - call_id
* r8 - saved link register
*/
_do_syscall:
/* grab address of LR from stack frame */
ldr r8, [ip, #(FPU_SF_SIZE + ___basic_sf_t_pc_OFFSET)]
/* Ma... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:11 | str r6, [sp]
cps #MODE_SVC
ldr r6, =K_SYSCALL_BAD
valid_syscall_id:
get_cpu r0
ldr r0, [r0, #___cpu_t_current_OFFSET]
ldr r1, [r0, #_thread_offset_to_mode]
bic r1, #1
/* Store (privileged) mode in thread's mode state variable */
str r1, [r0, #_thread_offset_to_mode]
dsb
/* ISB ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/swap_helper.S | 401 | 431 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:2 | * in case of preemption, or z_arm_svc in case of cooperative switching.
*/
SECTION_FUNC(TEXT, z_arm_do_swap)
#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
/* Register the context switch */
push {r0, lr}
bl z_thread_mark_switched_out
pop {r0, lr}
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */
/* loa... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/swap_helper.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/swap_helper.S:4 | ldr r4, =_thread_offset_to_tls
adds r4, r2, r4
ldr r0, [r4]
/* Store TLS pointer in the "Process ID" register.
* TPIDRURW is used as a base pointer to all
* thread variables with offsets added by toolchain.
*/
mcr p15, 0, r0, c13, c0, 2
#endif
#if defined(CONFIG_ARM_STORE_EXC_RETURN)
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/swap_helper.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_a_r/swap_helper.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/switch.S:1 | /*
* Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Thread context switching for ARM Cortex-A and Cortex-R (AArch32)
*
* This module implements the routines necessary for thread context switching
* on ARM Cortex-A and Corte... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/switch.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/switch.S:2 | stm r2, {r4-r11, sp, lr}
/* save current thread's exception depth */
get_cpu r2
ldrb r3, [r2, #_cpu_offset_to_exc_depth]
strb r3, [r1, #_thread_offset_to_exception_depth]
/* retrieve next thread's exception depth */
ldrb r3, [r0, #_thread_offset_to_exception_depth]
strb r3, [r2, #_cpu_offset_to_exc_depth]
/*... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/switch.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/switch.S:3 | #endif
#ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
push {lr}
bl z_thread_mark_switched_in
pop {lr}
#endif
bx lr
/**
*
* @brief Service call handler
*
* The service call (svc) is used in the following occasions:
* - Cooperative context switching
* - IRQ offloading
* - Kernel run-time exceptions
*
*/
SECTIO... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/switch.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/switch.S:4 | */
demux:
cps #MODE_SYS
cmp r1, #_SVC_CALL_RUNTIME_EXCEPT
beq _oops
#ifdef CONFIG_IRQ_OFFLOAD
cmp r1, #_SVC_CALL_IRQ_OFFLOAD
beq offload
b inv
offload:
get_cpu r2
ldr r3, [r2, #___cpu_t_nested_OFFSET]
add r3, r3, #1
str r3, [r2, #___cpu_t_nested_OFFSET]
/* If not nested: s... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/switch.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/switch.S | 121 | 167 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_a_r/vector_table.S:1 | /*
* Copyright (c) 2018 Marvell
* Copyright (c) 2018 Lexmark International, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Populated vector table in ROM
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include "vector_table.h"
#include "offsets_short.h"
#include "mac... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_a_r/vector_table.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_a_r/vector_table.S | 1 | 37 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/__aeabi_read_tp.S:1 | /*
* Copyright (c) 2020 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
_ASM_FILE_PROLOGUE
GTEXT(__aeabi_read_tp)
GDATA(z_arm_tls_ptr)
/* Grab the TLS pointer and store in R0.
* According to the Run-Time ABI for the Arm® Architectu... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/__aeabi_read_tp.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/__aeabi_read_tp.S | 1 | 26 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/__aeabi_read_tp.S:1 | /*
* Copyright (c) 2020 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
_ASM_FILE_PROLOGUE
GTEXT(__aeabi_read_tp)
GDATA(z_arm_tls_ptr)
/* Grab the TLS pointer and store in R0.
* According to the Run-Time ABI for the Arm® Architecture section 5.3.5, this
* function m... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/__aeabi_read_tp.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_m/__aeabi_read_tp.S | 1 | 25 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/fault_s.S:2 | *
* Entry point for the HardFault, MemManageFault, BusFault, UsageFault,
* SecureFault and Debug Monitor exceptions.
*
* The function supplies the values of
* - the MSP
* - the PSP
* - the EXC_RETURN value
* - callee saved register state (r4-r11, psp)
* as parameters to the z_arm_fault() C function that will p... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/fault_s.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/fault_s.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/fault_s.S:3 | mrs r1, PSP
push {r0, lr}
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
/* Build _callee_saved_t. To match the struct
* definition we push the psp & then r11-r4
*/
push { r1, r2 }
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
mov r3, r11
mov r2, r10
push {r2, r3}
mov r3, r9
mov r2, r8
push {r2, r3}
push {r... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/fault_s.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/fault_s.S | 81 | 113 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/fault_s.S:2 | *
* Entry point for the HardFault, MemManageFault, BusFault, UsageFault,
* SecureFault and Debug Monitor exceptions.
*
* The function supplies the values of
* - the MSP
* - the PSP
* - the EXC_RETURN value
* - callee saved register state (r4-r11, psp)
* as parameters to the z_arm_fault() C function that will p... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/fault_s.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_m/fault_s.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/irq_relay.S:1 | /*
* Copyright (c) 2018 Ding Tao <miyatsu@qq.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file irq_relay.S
*
* @brief IRQ relay vector table and relay handler for Cortex-M0 or
* Armv8-M baseline SoCs
*
* In certain ARMv6-M and Armv8-M baseline cores the vector table address can
* not be cha... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/irq_relay.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/irq_relay.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/irq_relay.S:2 | /**
* The size of IRQ vector is 4 bytes, the offset within vector table
* is the IRQ number times 4 (aka r0 << 2). As know as the r1 stored
* the offset of real vector table, thus the (r1 = r1 + r0 << 2) will
* be the real irq handle vector.
* */
bx r1;
GTEXT(__vector_relay_handler)
SECTION_FUNC(vector_re... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/irq_relay.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/irq_relay.S | 41 | 77 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:2 | /*
* The following macros could be written as assembler macros, but C is used
* for portability (assembler macro syntax may differ between toolchains).
*/
/*
* Pushes registers r4~r12 and lr on the stack.
* r0 is unmodified but other GPRs may be overwritten.
*/
#if !defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* `p... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/pm_s2ram.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:3 | mov r11, r4; \
mov r10, r3; \
mov r9, r2; \
mov r8, r1; \
pop {r4-r7}
#else
/* `pop` on ARMv7-M and ARMv8-M Mainline: no limitation */
#define POP_GPRS \
pop {r4-r12, lr}
#endif /* !CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* Registers presen... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/pm_s2ram.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:4 | #endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */
/*
* Saves the CPU's special registers in the `struct __cpu_context`
* pointed to by the `cpu_ctx` register.
* The `tmp_reg` register is overwritten as part of this process.
*/
#define SAVE_SPECIAL_REGISTERS(cpu_ctx, tmp_reg) \
SAVE_SPECIAL_REG(msp, cpu_ctx, tmp_reg) ... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/pm_s2ram.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:5 | GDATA(_cpu_context)
SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
/*
* Save the CPU context
*
* r0: address of the system_off function
*/
PUSH_GPRS
/* Move system_off to protected register. */
mov r4, r0
/* Store CPU context */
ldr r1, =_cpu_context
SAVE_SPECIAL_REGISTERS(/* ctx: */ r1, /* tmp: */ r2)
... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/pm_s2ram.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:6 | bl pm_s2ram_mark_check_and_clear
/* Move the stored return value of system_off back to r0,
* setting it as return value for this function.
*/
mov r0, r4
POP_GPRS
bx lr
GTEXT(arch_pm_s2ram_resume)
SECTION_FUNC(TEXT, arch_pm_s2ram_resume)
/*
* Check if reset occurred after suspending to RAM.
* Store LR t... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/pm_s2ram.S | 201 | 245 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:2 | /*
* The following macros could be written as assembler macros, but C is used
* for portability (assembler macro syntax may differ between toolchains).
*/
/*
* Pushes registers r4~r12 and lr on the stack.
* r0 is unmodified but other GPRs may be overwritten.
*/
#if !defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* `p... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_m/pm_s2ram.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:3 | mov r10, r3; \
mov r9, r2; \
mov r8, r1; \
pop {r4-r7}
#else
/* `pop` on ARMv7-M and ARMv8-M Mainline: no limitation */
#define POP_GPRS \
pop {r4-r12, lr}
#endif /* !CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* Registers present only on ARMv7-M and ... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_m/pm_s2ram.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:4 | /*
* Saves the CPU's special registers in the `struct __cpu_context`
* pointed to by the `cpu_ctx` register.
* The `tmp_reg` register is overwritten as part of this process.
*/
#define SAVE_SPECIAL_REGISTERS(cpu_ctx, tmp_reg) \
SAVE_SPECIAL_REG(msp, cpu_ctx, tmp_reg) \
SAVE_SPECIAL_REG(psp, cpu_ctx, tmp_reg)... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_m/pm_s2ram.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:5 | SECTION_FUNC(TEXT, arch_pm_s2ram_suspend)
/*
* Save the CPU context
*
* r0: address of the system_off function
*/
PUSH_GPRS
/* Move system_off to protected register. */
mov r4, r0
/* Store CPU context */
ldr r1, =_cpu_context
SAVE_SPECIAL_REGISTERS(/* ctx: */ r1, /* tmp: */ r2)
/*
* Mark entering... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_m/pm_s2ram.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/pm_s2ram.S:6 | /* Move the stored return value of system_off back to r0,
* setting it as return value for this function.
*/
mov r0, r4
POP_GPRS
bx lr
GTEXT(arch_pm_s2ram_resume)
SECTION_FUNC(TEXT, arch_pm_s2ram_resume)
/*
* Check if reset occurred after suspending to RAM.
* Store LR to ensure we can continue boot when ... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/pm_s2ram.S | Apache-2.0 | 94ed533c31ee1dde8117e995630e27373927a17c | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/94ed533c31ee1dde8117e995630e27373927a17c/arch/arm/core/cortex_m/pm_s2ram.S | 201 | 244 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:1 | /*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2017-2019 Nordic Semiconductor ASA.
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
* Copyright 2026 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:2 | *
*/
SECTION_FUNC(TEXT, z_arm_svc)
/* Use EXC_RETURN state to find out if stack frame is on the
* MSP or PSP
*/
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
movs r0, #_EXC_RETURN_SPSEL_Msk
mov r1, lr
tst r1, r0
beq .L_stack_frame_msp
mrs r0, PSP
bne .L_stack_frame_endif
.L_stack_frame_msp:
mrs r0... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:3 | * 1: irq_offload (if configured)
* 2: kernel panic or oops (software generated fatal exception)
* 3: System call (if user mode supported)
*/
#if defined(CONFIG_USERSPACE)
mrs r2, CONTROL
cmp r1, #3
beq .L_do_syscall
/*
* check that we are privileged before invoking other SVCs
* o... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:4 | * switch correctly (which... isn't tested?)
*/
push {r0, lr}
bl arm_m_legacy_exit
pop {r0, lr}
bx lr
#else
ldr r0, =z_arm_int_exit
bx r0
#endif
#endif
.L_oops:
push {r0, lr}
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
/* Build _callee_saved_t. To match the struct
* definition we... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:7 | * | | | | | |
* | | | 0 | address that |z_arm_do_syscall expects |
* | | | | z_arm_do_syscall should |the original pre-svc sp at|
* | | ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:8 | #else
mov r8, #_EXC_HW_SAVED_BASIC_SF_SIZE
#endif
sub ip, #8 /* z_arm_do_syscall will use this to get original sp and pc */
sub ip, r8 /* 32 for basic sf + 72 for the optional esf */
#endif
/*
* At this point:
* r0 has PSP i.e. top of user stack
* ip has top of privilege stack
* r8 ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:9 | /* r0-r3, r12, LR from user stack sf are copied to sf of priv stack */
mov r1, r0
mov r2, r3
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
ldmia r1!, {r4-r5}
stmia r2!, {r4-r5}
/* Store the svc return address at the offset expected by z_arm_do_syscall,
* as detailed in the table above.
*/... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:10 | str r1,[ip, #_EXC_HW_SAVED_BASIC_SF_XPSR_OFFSET] /* priv sf get user sf xPSR with bit9 reset */
/* r0-r3, r12, LR from user stack sf are copied to sf of priv stack */
mov r1, r0
mov r2, ip
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
ldmia r1!, {r4-r5}
stmia r2!, {r4-r5}
/* Store the svc retu... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:11 | #endif
pop {r2} /* restore CONTROL value */
pop {r4-r7}
/* Point PSP to privilege stack,
* note that r0 still has the old PSP
*/
msr PSP, ip
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
ldr r3, =K_SYSCALL_LIMIT
cmp r6, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* validate... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:12 | mov r2, ip
dsb
/* set mode to privileged, r2 still contains value from CONTROL */
movs r3, #1
bics r2, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
ldr r1, [r0, #_thread_offset_to_mode]
bic r1, #1
/* Store (privileged) mode in thread's mode state variable */
str r1, [r0, #_thread_of... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/svc.S | 441 | 483 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:1 | /*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2017-2019 Nordic Semiconductor ASA.
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief SVC exception handling for ARM Cortex-M
*
* This module implements the z_arm_s... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 1 | 60 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:2 | */
SECTION_FUNC(TEXT, z_arm_svc)
/* Use EXC_RETURN state to find out if stack frame is on the
* MSP or PSP
*/
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
movs r0, #_EXC_RETURN_SPSEL_Msk
mov r1, lr
tst r1, r0
beq .L_stack_frame_msp
mrs r0, PSP
bne .L_stack_frame_endif
.L_stack_frame_msp:
mrs r0, M... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:3 | * 2: kernel panic or oops (software generated fatal exception)
* 3: System call (if user mode supported)
*/
#if defined(CONFIG_USERSPACE)
mrs r2, CONTROL
cmp r1, #3
beq .L_do_syscall
/*
* check that we are privileged before invoking other SVCs
* oops if we are unprivileged
*/
#i... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:4 | */
push {r0, lr}
bl arm_m_legacy_exit
pop {r0, lr}
bx lr
#else
ldr r0, =z_arm_int_exit
bx r0
#endif
#endif
.L_oops:
push {r0, lr}
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
/* Build _callee_saved_t. To match the struct
* definition we push the psp & then r11-r4
*/
mrs r1, P... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:7 | * | | | 0 | address that |z_arm_do_syscall expects |
* | | | | z_arm_do_syscall should |the original pre-svc sp at|
* | | | | set as PSP before |0th offset i.e. new sp[0] |
* | | ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:8 | mov r8, #_EXC_HW_SAVED_BASIC_SF_SIZE
#endif
sub ip, #8 /* z_arm_do_syscall will use this to get original sp and pc */
sub ip, r8 /* 32 for basic sf + 72 for the optional esf */
#endif
/*
* At this point:
* r0 has PSP i.e. top of user stack
* ip has top of privilege stack
* r8 has hardwa... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:9 | /* r0-r3, r12, LR from user stack sf are copied to sf of priv stack */
mov r1, r0
mov r2, r3
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
ldmia r1!, {r4-r5}
stmia r2!, {r4-r5}
/* Store the svc return address at the offset expected by z_arm_do_syscall,
* as detailed in the table above.
*/... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:10 | /* r0-r3, r12, LR from user stack sf are copied to sf of priv stack */
mov r1, r0
mov r2, ip
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
ldmia r1!, {r4-r5}
stmia r2!, {r4-r5}
/* Store the svc return address at the offset expected by z_arm_do_syscall,
* as detailed in the table above.
*/... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:11 | #endif
pop {r2} /* restore CONTROL value */
pop {r4-r7}
/* Point PSP to privilege stack,
* note that r0 still has the old PSP
*/
msr PSP, ip
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
ldr r3, =K_SYSCALL_LIMIT
cmp r6, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* validate... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:12 | dsb
/* set mode to privileged, r2 still contains value from CONTROL */
movs r3, #1
bics r2, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
ldr r1, [r0, #_thread_offset_to_mode]
bic r1, #1
/* Store (privileged) mode in thread's mode state variable */
str r1, [r0, #_thread_offset_to_mode]
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 70e87c5d1dceb2fab50dcf073db44cf3729bbe39 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/70e87c5d1dceb2fab50dcf073db44cf3729bbe39/arch/arm/core/cortex_m/svc.S | 441 | 480 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/svc.S:12 | dsb
/* set mode to privileged, r2 still contains value from CONTROL */
movs r3, #1
bics r2, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
ldr r1, [r0, #_thread_offset_to_mode]
bic r1, #1
/* Store (privileged) mode in thread's mode state variable */
str r1, [r0, #_thread_offset_to_mode]
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/svc.S | Apache-2.0 | 89296edf30860745c8005c999c701fd2bbdb7cfc | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/89296edf30860745c8005c999c701fd2bbdb7cfc/arch/arm/core/cortex_m/svc.S | 441 | 472 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:2 | * When PendSV is pended, the decision that a context switch must happen has
* already been taken. In other words, when z_arm_pendsv() runs, we *know* we
* have to swap *something*.
*
* For Cortex-M, z_arm_pendsv() is invoked with no arguments.
*/
SECTION_FUNC(TEXT, z_arm_pendsv)
#ifdef CONFIG_INSTRUMENT_THREAD_S... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/swap_helper.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:3 | mrs ip, PSP
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
/* Store current r4-r7 */
stmea r0!, {r4-r7}
/* copy r8-r12 into r3-r7 */
mov r3, r8
mov r4, r9
mov r5, r10
mov r6, r11
mov r7, ip
/* store r8-12 */
stmea r0!, {r3-r7}
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
stm... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/swap_helper.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:4 | #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI_MAX, r0
isb /* Make the effect of disabling interrupts be realized immediately */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
/*
* Prepare to clear PendSV with interr... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/swap_helper.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:5 | str r6, [r7, #0]
#if defined(CONFIG_THREAD_LOCAL_STORAGE)
/* Grab the TLS pointer */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
ldr r4, =_thread_offset_to_tls
adds r4, r2, r4
ldr r0, [r4]
#else
ldr r0, [r2, #_thread_offset_to_tls]
#endif
/* For Cortex-M, store TLS pointer in a global variabl... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/swap_helper.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:6 | ldr r0, [r2, #_thread_offset_to_basepri]
movs r3, #0
str r3, [r2, #_thread_offset_to_basepri]
#endif
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
/* BASEPRI not available, previous interrupt disable state
* maps to PRIMASK.
*
* Only enable interrupts if value is 0, meaning interrupts
* ... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/swap_helper.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:7 | */
isb
#endif
ldr r4, =_thread_offset_to_callee_saved
adds r0, r2, r4
/* restore r4-r12 for new thread */
/* first restore r8-r12 located after r4-r7 (4*4bytes) */
adds r0, #16
ldmia r0!, {r3-r7}
/* move to correct registers */
mov r8, r3
mov r9, r4
mov r10, r5
mov r11... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/swap_helper.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:8 | * - clear EXC_RETURN.F_Type
* - FPSCR and caller-saved registers will be restored automatically
* - restore callee-saved FP registers
*/
add r0, r2, #_thread_offset_to_preempt_float
vldmia r0, {s16-s31}
.L_in_fp_endif:
/* Clear CONTROL.FPCA that may have been set by FP instructions */
mrs... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/swap_helper.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:9 | * Note: There is no way to know the _current thread mode after the thread creation since
* `_current->arch.mode` for the userspace thread is set in z_arm_userspace_enter() which
* runs after z_arm_pendsv is done. So for now, while switching to an unprivileged thread
* the same PAC keys are set in both pr... | arm | gas-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 5e802fe73d979b1e0aa9d675429be303a0d2e7b2 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/5e802fe73d979b1e0aa9d675429be303a0d2e7b2/arch/arm/core/cortex_m/swap_helper.S | 321 | 369 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:2 | /**
*
* @brief PendSV exception handler, handling context switches
*
* The PendSV exception is the only execution context in the system that can
* perform context switching. When an execution context finds out it has to
* switch contexts, it pends the PendSV exception.
*
* When PendSV is pended, the decision th... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:3 | strb lr, [r2, #_thread_offset_to_mode_exc_return]
#endif
/* addr of callee-saved regs in thread in r0 */
ldr r0, =_thread_offset_to_callee_saved
add r0, r2
/* save callee-saved + psp in thread */
mrs ip, PSP
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
/* Store current r4-r7 */
stmea r0!,... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:4 | #endif /* CONFIG_FPU_SHARING */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
/* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
movs.n r0, #_EXC_IRQ_DEFA... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:5 | * decides, with the new kernel state based on the new thread
* being context-switched in, that it needs to reschedule, it
* will take, but that previously pended PendSVs do not take,
* since they were based on the previous kernel state and this
* has been handled.
*/
/* _SCS_ICSR is still ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:6 | */
ldr r4, =_thread_offset_to_basepri
adds r4, r2, r4
ldr r0, [r4]
movs.n r3, #0
str r3, [r4]
#else
ldr r0, [r2, #_thread_offset_to_basepri]
movs r3, #0
str r3, [r2, #_thread_offset_to_basepri]
#endif
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
/* BASEPRI not available, previous i... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:7 | movs.n r1, #1
bics r3, r1
orrs r3, r0
msr CONTROL, r3
/* ISB is not strictly necessary here (stack pointer is not being
* touched), but it's recommended to avoid executing pre-fetched
* instructions with the previous privilege.
*/
isb
#endif
ldr r4, =_thread_offset_to_callee_sa... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:8 | * from pendSV)
*/
movs.n r3, #0
vmsr fpscr, r3
b .L_in_fp_endif
.L_in_fp_active:
/* FP context active:
* - clear EXC_RETURN.F_Type
* - FPSCR and caller-saved registers will be restored automatically
* - restore callee-saved FP registers
*/
add r0, r2, #_thread_offset_to_p... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:9 | * instructions with the previous privilege.
*/
isb
#endif
#ifdef CONFIG_ARM_PAC_PER_THREAD
/* Read thread's dedicated PAC key and write them in the privileged PAC key registers.
* Note: There is no way to know the _current thread mode after the thread creation since
* `_current->arch.mode` for ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:10 | #ifdef CONFIG_INSTRUMENT_THREAD_SWITCHING
/* Register the context switch */
push {r0, lr}
bl z_thread_mark_switched_in
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
pop {r0, r1}
mov lr, r1
#else
pop {r0, lr}
#endif
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */
/*
* Cortex-M: return fr... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:11 | mrs r0, MSP
.L_stack_frame_endif:
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
tst lr, #_EXC_RETURN_SPSEL_Msk /* did we come from thread mode ? */
ite eq /* if zero (equal), came from handler mode */
mrseq r0, MSP /* handler mode, stack frame is on MSP */
mrsne r0, PSP /* thread mode, sta... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:12 | #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
movs r3, #0x1
tst r2, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
tst r2, #0x1
#endif
bne .L_oops
#endif /* CONFIG_USERSPACE */
cmp r1, #2
beq .L_oops
#if defined(CONFIG_IRQ_OFFLOAD)
push {r0, lr}
bl z_irq_do_offload /* call C routin... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:13 | push {r0, lr}
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
/* Build _callee_saved_t. To match the struct
* definition we push the psp & then r11-r4
*/
mrs r1, PSP
push {r1, r2} /* r2 for padding */
#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
push {r4-r11}
#elif defined(CONFIG_ARMV6_M_ARMV8_M_BASE... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 481 | 540 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:16 | * Note that the "FP regs + FPSCR" are only present if CONFIG_FPU_SHARING=y, and the optional pad
* is only present if PSP was not 8-byte aligned when SVC was executed.
* Also note that FPU cannot be present in ARMv6-M or ARMv8-M Baseline implementations
* (i.e., it may only be present when CONFIG_ARMV7_M_ARMV8_M_MAI... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:17 | push {r2}
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
mov r2, r0 /* safe to use r2 since it is saved on MSP */
/* Check for padding in the sf */
ldr r1, [r0, #_EXC_HW_SAVED_BASIC_SF_XPSR_OFFSET] /* grab xPSR from sf which has the pad bit */
movs r3, #1
/* Check if pad bit 9 is set */
lsls r3... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:18 | ldr r1, =z_arm_do_syscall
str r1, [r3, #_EXC_HW_SAVED_BASIC_SF_RETADDR_OFFSET] /* Execution return to z_arm_do_syscall */
ldr r1, [r0, #_EXC_HW_SAVED_BASIC_SF_RETADDR_OFFSET] /* grab address of PC from stack frame */
/* Store the svc return address (i.e. next instr to svc) in r8 as expected by z_arm_do_sysc... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:19 | str r5, [ip, r8]
ldr r1, =z_arm_do_syscall
str r1, [ip, #_EXC_HW_SAVED_BASIC_SF_RETADDR_OFFSET] /* Execution return to z_arm_do_syscall */
ldr r1, [r0, #_EXC_HW_SAVED_BASIC_SF_RETADDR_OFFSET] /* grab address of PC from stack frame */
/* Store the svc return address (i.e. next instr to svc) in r8 as exp... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:20 | /* validate syscall limit */
ldr ip, =K_SYSCALL_LIMIT
cmp r6, ip
#endif
/* The supplied syscall_id must be lower than the limit
* (Requires unsigned integer comparison)
*/
blo .L_valid_syscall_id
/* bad syscall id. Set arg1 to bad id and set call_id to SYSCALL_BAD */
str r6, [r0]
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 761 | 819 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:21 | msr CONTROL, r2
/* ISB is not strictly necessary here (stack pointer is not being
* touched), but it's recommended to avoid executing pre-fetched
* instructions with the previous privilege.
*/
isb
#if defined(CONFIG_BUILTIN_STACK_GUARD)
/* Set stack pointer limit (needed in privileged mode)... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | e2e5542d14adb0f97a425243ee9b009bb71757d8 | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/e2e5542d14adb0f97a425243ee9b009bb71757d8/arch/arm/core/cortex_m/swap_helper.S | 801 | 819 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:12 | #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
movs r3, #0x1
tst r2, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
tst r2, #0x1
#endif
bne .L_oops
#endif /* CONFIG_USERSPACE */
cmp r1, #2
beq .L_oops
#if defined(CONFIG_IRQ_OFFLOAD)
push {r0, lr}
bl z_irq_do_offload /* call C routin... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | a8422253cf41b2c6388fee933acad577a32a671b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a8422253cf41b2c6388fee933acad577a32a671b/arch/arm/core/cortex_m/swap_helper.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:15 | * | | | | |On returning to |
* | | | | |z_arm_do_syscall, the |
* | | | | |above sf has already been |
* | | ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | a8422253cf41b2c6388fee933acad577a32a671b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a8422253cf41b2c6388fee933acad577a32a671b/arch/arm/core/cortex_m/swap_helper.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:16 | #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
ldr ip, =_kernel
ldr ip, [ip, #_kernel_offset_to_current]
ldr ip, [ip, #_thread_offset_to_priv_stack_start] /* bottom of priv stack */
add ip, #CONFIG_PRIVILEGED_STACK_SIZE
#ifdef CONFIG_FPU_SHARING
/* Assess whether svc calling thread had been using th... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | a8422253cf41b2c6388fee933acad577a32a671b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a8422253cf41b2c6388fee933acad577a32a671b/arch/arm/core/cortex_m/swap_helper.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:17 | /* Calculate original pre-svc user sp which is psp + sf size (+4B if pad bit was set) */
adds r2, #_EXC_HW_SAVED_BASIC_SF_SIZE
mov r3, ip
str r2,[r3, #0]
/* Store the pre-SVC user SP at the offset expected by z_arm_do_syscall,
* as detailed in the table above.
*/
str r2,[r3, #_EXC_HW_SAV... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | a8422253cf41b2c6388fee933acad577a32a671b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a8422253cf41b2c6388fee933acad577a32a671b/arch/arm/core/cortex_m/swap_helper.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:18 | tst r1, #(1<<9) /* Check if pad bit 9 is set */
beq .L_no_padding
bics r1, #(1<<9) /* clear the pad bit (priv stack is aligned and doesn't need it) */
/* Calculate original pre-svc user sp with pad */
add r2, #4
.L_no_padding:
str r2,[ip, #0]
/* Store the pre-SVC user SP at the offset expected ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | a8422253cf41b2c6388fee933acad577a32a671b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a8422253cf41b2c6388fee933acad577a32a671b/arch/arm/core/cortex_m/swap_helper.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:19 | add r1, r0, #32
add r2, ip, #32
vldmia r1!, {s0-s15}
vstmia r2!, {s0-s15}
/* copy FPSCR + reserved (8 bytes) */
ldmia r1!, {r4, r5}
stmia r2!, {r4, r5}
.L_skip_fp_copy:
#endif
#endif
pop {r2} /* restore CONTROL value */
pop {r4-r7}
/* Point PSP to privilege stack,
* note... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | a8422253cf41b2c6388fee933acad577a32a671b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a8422253cf41b2c6388fee933acad577a32a671b/arch/arm/core/cortex_m/swap_helper.S | 721 | 780 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:20 | .L_valid_syscall_id:
ldr r0, =_kernel
ldr r0, [r0, #_kernel_offset_to_current]
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
mov ip, r2
ldr r1, =_thread_offset_to_mode
ldr r3, [r0, r1]
movs r2, #1
bics r3, r2
/* Store (privileged) mode in thread's mode state variable */
str r3, [r0, r... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | a8422253cf41b2c6388fee933acad577a32a671b | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/a8422253cf41b2c6388fee933acad577a32a671b/arch/arm/core/cortex_m/swap_helper.S | 761 | 804 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:2 | /**
*
* @brief PendSV exception handler, handling context switches
*
* The PendSV exception is the only execution context in the system that can
* perform context switching. When an execution context finds out it has to
* switch contexts, it pends the PendSV exception.
*
* When PendSV is pended, the decision th... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 41 | 100 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:3 | add r0, r2
/* save callee-saved + psp in thread */
mrs ip, PSP
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
/* Store current r4-r7 */
stmea r0!, {r4-r7}
/* copy r8-r12 into r3-r7 */
mov r3, r8
mov r4, r9
mov r5, r10
mov r6, r11
mov r7, ip
/* store r8-12 */
stmea r0!, {r... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 81 | 140 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:4 | /* Protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
cpsid i
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI_MAX, r0
isb /* Make the effect of disabling interrupts be realized immediately */
#else
#er... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 121 | 180 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:5 | #if defined(CONFIG_THREAD_LOCAL_STORAGE)
/* Grab the TLS pointer */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
ldr r4, =_thread_offset_to_tls
adds r4, r2, r4
ldr r0, [r4]
#else
ldr r0, [r2, #_thread_offset_to_tls]
#endif
/* For Cortex-M, store TLS pointer in a global variable,
* as it la... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 161 | 220 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:6 | str r3, [r2, #_thread_offset_to_basepri]
#endif
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
/* BASEPRI not available, previous interrupt disable state
* maps to PRIMASK.
*
* Only enable interrupts if value is 0, meaning interrupts
* were enabled before irq_lock was called.
*/
cmp r0, ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 201 | 260 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:7 | #endif
ldr r4, =_thread_offset_to_callee_saved
adds r0, r2, r4
/* restore r4-r12 for new thread */
/* first restore r8-r12 located after r4-r7 (4*4bytes) */
adds r0, #16
ldmia r0!, {r3-r7}
/* move to correct registers */
mov r8, r3
mov r9, r4
mov r10, r5
mov r11, r6
mov... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 241 | 300 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:8 | * - restore callee-saved FP registers
*/
add r0, r2, #_thread_offset_to_preempt_float
vldmia r0, {s16-s31}
.L_in_fp_endif:
/* Clear CONTROL.FPCA that may have been set by FP instructions */
mrs r3, CONTROL
bic r3, #_CONTROL_FPCA_Msk
msr CONTROL, r3
isb
#endif
#if defined(CONFIG_MPU_STA... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 281 | 340 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:9 | * runs after z_arm_pendsv is done. So for now, while switching to an unprivileged thread
* the same PAC keys are set in both privileged and unprivileged PAC key registers.
* TODO: find a way to not set privileged PAC keys if the thread being switched into is an
* unprivileged thread.
*/
add r0, ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 321 | 380 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:10 | #endif
#endif /* CONFIG_INSTRUMENT_THREAD_SWITCHING */
/*
* Cortex-M: return from PendSV exception
*/
bx lr
/**
*
* @brief Service call handler
*
* The service call (svc) is used in the following occasions:
* - IRQ offloading
* - Kernel run-time exceptions
* - System Calls (User mode)
*
*/
... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 361 | 420 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:11 | /* Figure out what SVC call number was invoked */
ldr r1, [r0, #24] /* grab address of PC from stack frame */
/* SVC is a two-byte instruction, point to it and read the
* SVC number (lower byte of SCV instruction)
*/
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
subs r1, r1, #2
ldrb r1, [r1]... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 401 | 460 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:12 | cmp r1, #2
beq .L_oops
#if defined(CONFIG_IRQ_OFFLOAD)
push {r0, lr}
bl z_irq_do_offload /* call C routine which executes the offload */
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
pop {r0, r3}
mov lr, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
pop {r0, lr}
#endif
/* exception ret... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 441 | 500 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:15 | * | | | | |to be set in r8. |
* | | | | | |
* | | | 0 | address that |z_arm_do_syscall expects |
* | | ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 561 | 620 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:16 | movne r8, #_EXC_HW_SAVED_BASIC_SF_SIZE
#else
mov r8, #_EXC_HW_SAVED_BASIC_SF_SIZE
#endif
sub ip, #8 /* z_arm_do_syscall will use this to get original sp and pc */
sub ip, r8 /* 32 for basic sf + 72 for the optional esf */
#endif
/*
* At this point:
* r0 has PSP i.e. top of user stack
* i... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 601 | 660 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:17 | str r1,[r3, #_EXC_HW_SAVED_BASIC_SF_XPSR_OFFSET]
/* r0-r3, r12, LR from user stack sf are copied to sf of priv stack */
mov r1, r0
mov r2, r3
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
ldmia r1!, {r4-r5}
stmia r2!, {r4-r5}
/* Store the svc return address at the offset expected by z_arm_do_s... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 641 | 700 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:18 | str r2,[ip, r8]
str r1,[ip, #_EXC_HW_SAVED_BASIC_SF_XPSR_OFFSET] /* priv sf get user sf xPSR with bit9 reset */
/* r0-r3, r12, LR from user stack sf are copied to sf of priv stack */
mov r1, r0
mov r2, ip
ldmia r1!, {r4-r7}
stmia r2!, {r4-r7}
ldmia r1!, {r4-r5}
stmia r2!, {r4-r5}
/... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 681 | 740 |
zephyrproject-rtos/zephyr:arch/arm/core/cortex_m/swap_helper.S:19 | #endif
#endif
pop {r2} /* restore CONTROL value */
pop {r4-r7}
/* Point PSP to privilege stack,
* note that r0 still has the old PSP
*/
msr PSP, ip
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
ldr r3, =K_SYSCALL_LIMIT
cmp r6, r3
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* ... | arm | intel-like | handwritten | zephyrproject-rtos/zephyr | arch/arm/core/cortex_m/swap_helper.S | Apache-2.0 | 8558b935b147f33958153822478e2bf9ab9806cf | github | rtos | https://github.com/zephyrproject-rtos/zephyr/blob/8558b935b147f33958153822478e2bf9ab9806cf/arch/arm/core/cortex_m/swap_helper.S | 721 | 780 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.