code
stringlengths 1
2.01M
| repo_name
stringlengths 3
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| path
stringlengths 1
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| language
stringclasses 231
values | license
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/*
* ATI PCI IDs from XFree86, kept here to make sync'ing with
* XFree much simpler. Currently, this list is only used by
* radeonfb
*/
#define PCI_CHIP_RV380_3150 0x3150
#define PCI_CHIP_RV380_3151 0x3151
#define PCI_CHIP_RV380_3152 0x3152
#define PCI_CHIP_RV380_3153 0x3153
#define PCI_CHIP_RV380_3154 0x3154
#define PCI_CHIP_RV380_3156 0x3156
#define PCI_CHIP_RV380_3E50 0x3E50
#define PCI_CHIP_RV380_3E51 0x3E51
#define PCI_CHIP_RV380_3E52 0x3E52
#define PCI_CHIP_RV380_3E53 0x3E53
#define PCI_CHIP_RV380_3E54 0x3E54
#define PCI_CHIP_RV380_3E56 0x3E56
#define PCI_CHIP_RS100_4136 0x4136
#define PCI_CHIP_RS200_4137 0x4137
#define PCI_CHIP_R300_AD 0x4144
#define PCI_CHIP_R300_AE 0x4145
#define PCI_CHIP_R300_AF 0x4146
#define PCI_CHIP_R300_AG 0x4147
#define PCI_CHIP_R350_AH 0x4148
#define PCI_CHIP_R350_AI 0x4149
#define PCI_CHIP_R350_AJ 0x414A
#define PCI_CHIP_R350_AK 0x414B
#define PCI_CHIP_RV350_AP 0x4150
#define PCI_CHIP_RV350_AQ 0x4151
#define PCI_CHIP_RV360_AR 0x4152
#define PCI_CHIP_RV350_AS 0x4153
#define PCI_CHIP_RV350_AT 0x4154
#define PCI_CHIP_RV350_AV 0x4156
#define PCI_CHIP_MACH32 0x4158
#define PCI_CHIP_RS250_4237 0x4237
#define PCI_CHIP_R200_BB 0x4242
#define PCI_CHIP_R200_BC 0x4243
#define PCI_CHIP_RS100_4336 0x4336
#define PCI_CHIP_RS200_4337 0x4337
#define PCI_CHIP_MACH64CT 0x4354
#define PCI_CHIP_MACH64CX 0x4358
#define PCI_CHIP_RS250_4437 0x4437
#define PCI_CHIP_MACH64ET 0x4554
#define PCI_CHIP_MACH64GB 0x4742
#define PCI_CHIP_MACH64GD 0x4744
#define PCI_CHIP_MACH64GI 0x4749
#define PCI_CHIP_MACH64GL 0x474C
#define PCI_CHIP_MACH64GM 0x474D
#define PCI_CHIP_MACH64GN 0x474E
#define PCI_CHIP_MACH64GO 0x474F
#define PCI_CHIP_MACH64GP 0x4750
#define PCI_CHIP_MACH64GQ 0x4751
#define PCI_CHIP_MACH64GR 0x4752
#define PCI_CHIP_MACH64GS 0x4753
#define PCI_CHIP_MACH64GT 0x4754
#define PCI_CHIP_MACH64GU 0x4755
#define PCI_CHIP_MACH64GV 0x4756
#define PCI_CHIP_MACH64GW 0x4757
#define PCI_CHIP_MACH64GX 0x4758
#define PCI_CHIP_MACH64GY 0x4759
#define PCI_CHIP_MACH64GZ 0x475A
#define PCI_CHIP_RV250_Id 0x4964
#define PCI_CHIP_RV250_Ie 0x4965
#define PCI_CHIP_RV250_If 0x4966
#define PCI_CHIP_RV250_Ig 0x4967
#define PCI_CHIP_R420_JH 0x4A48
#define PCI_CHIP_R420_JI 0x4A49
#define PCI_CHIP_R420_JJ 0x4A4A
#define PCI_CHIP_R420_JK 0x4A4B
#define PCI_CHIP_R420_JL 0x4A4C
#define PCI_CHIP_R420_JM 0x4A4D
#define PCI_CHIP_R420_JN 0x4A4E
#define PCI_CHIP_R420_JP 0x4A50
#define PCI_CHIP_MACH64LB 0x4C42
#define PCI_CHIP_MACH64LD 0x4C44
#define PCI_CHIP_RAGE128LE 0x4C45
#define PCI_CHIP_RAGE128LF 0x4C46
#define PCI_CHIP_MACH64LG 0x4C47
#define PCI_CHIP_MACH64LI 0x4C49
#define PCI_CHIP_MACH64LM 0x4C4D
#define PCI_CHIP_MACH64LN 0x4C4E
#define PCI_CHIP_MACH64LP 0x4C50
#define PCI_CHIP_MACH64LQ 0x4C51
#define PCI_CHIP_MACH64LR 0x4C52
#define PCI_CHIP_MACH64LS 0x4C53
#define PCI_CHIP_MACH64LT 0x4C54
#define PCI_CHIP_RADEON_LW 0x4C57
#define PCI_CHIP_RADEON_LX 0x4C58
#define PCI_CHIP_RADEON_LY 0x4C59
#define PCI_CHIP_RADEON_LZ 0x4C5A
#define PCI_CHIP_RV250_Ld 0x4C64
#define PCI_CHIP_RV250_Le 0x4C65
#define PCI_CHIP_RV250_Lf 0x4C66
#define PCI_CHIP_RV250_Lg 0x4C67
#define PCI_CHIP_RV250_Ln 0x4C6E
#define PCI_CHIP_RAGE128MF 0x4D46
#define PCI_CHIP_RAGE128ML 0x4D4C
#define PCI_CHIP_R300_ND 0x4E44
#define PCI_CHIP_R300_NE 0x4E45
#define PCI_CHIP_R300_NF 0x4E46
#define PCI_CHIP_R300_NG 0x4E47
#define PCI_CHIP_R350_NH 0x4E48
#define PCI_CHIP_R350_NI 0x4E49
#define PCI_CHIP_R360_NJ 0x4E4A
#define PCI_CHIP_R350_NK 0x4E4B
#define PCI_CHIP_RV350_NP 0x4E50
#define PCI_CHIP_RV350_NQ 0x4E51
#define PCI_CHIP_RV350_NR 0x4E52
#define PCI_CHIP_RV350_NS 0x4E53
#define PCI_CHIP_RV350_NT 0x4E54
#define PCI_CHIP_RV350_NV 0x4E56
#define PCI_CHIP_RAGE128PA 0x5041
#define PCI_CHIP_RAGE128PB 0x5042
#define PCI_CHIP_RAGE128PC 0x5043
#define PCI_CHIP_RAGE128PD 0x5044
#define PCI_CHIP_RAGE128PE 0x5045
#define PCI_CHIP_RAGE128PF 0x5046
#define PCI_CHIP_RAGE128PG 0x5047
#define PCI_CHIP_RAGE128PH 0x5048
#define PCI_CHIP_RAGE128PI 0x5049
#define PCI_CHIP_RAGE128PJ 0x504A
#define PCI_CHIP_RAGE128PK 0x504B
#define PCI_CHIP_RAGE128PL 0x504C
#define PCI_CHIP_RAGE128PM 0x504D
#define PCI_CHIP_RAGE128PN 0x504E
#define PCI_CHIP_RAGE128PO 0x504F
#define PCI_CHIP_RAGE128PP 0x5050
#define PCI_CHIP_RAGE128PQ 0x5051
#define PCI_CHIP_RAGE128PR 0x5052
#define PCI_CHIP_RAGE128PS 0x5053
#define PCI_CHIP_RAGE128PT 0x5054
#define PCI_CHIP_RAGE128PU 0x5055
#define PCI_CHIP_RAGE128PV 0x5056
#define PCI_CHIP_RAGE128PW 0x5057
#define PCI_CHIP_RAGE128PX 0x5058
#define PCI_CHIP_RADEON_QD 0x5144
#define PCI_CHIP_RADEON_QE 0x5145
#define PCI_CHIP_RADEON_QF 0x5146
#define PCI_CHIP_RADEON_QG 0x5147
#define PCI_CHIP_R200_QH 0x5148
#define PCI_CHIP_R200_QI 0x5149
#define PCI_CHIP_R200_QJ 0x514A
#define PCI_CHIP_R200_QK 0x514B
#define PCI_CHIP_R200_QL 0x514C
#define PCI_CHIP_R200_QM 0x514D
#define PCI_CHIP_R200_QN 0x514E
#define PCI_CHIP_R200_QO 0x514F
#define PCI_CHIP_RV200_QW 0x5157
#define PCI_CHIP_RV200_QX 0x5158
#define PCI_CHIP_RV100_QY 0x5159
#define PCI_CHIP_RV100_QZ 0x515A
#define PCI_CHIP_RN50 0x515E
#define PCI_CHIP_RAGE128RE 0x5245
#define PCI_CHIP_RAGE128RF 0x5246
#define PCI_CHIP_RAGE128RG 0x5247
#define PCI_CHIP_RAGE128RK 0x524B
#define PCI_CHIP_RAGE128RL 0x524C
#define PCI_CHIP_RAGE128SE 0x5345
#define PCI_CHIP_RAGE128SF 0x5346
#define PCI_CHIP_RAGE128SG 0x5347
#define PCI_CHIP_RAGE128SH 0x5348
#define PCI_CHIP_RAGE128SK 0x534B
#define PCI_CHIP_RAGE128SL 0x534C
#define PCI_CHIP_RAGE128SM 0x534D
#define PCI_CHIP_RAGE128SN 0x534E
#define PCI_CHIP_RAGE128TF 0x5446
#define PCI_CHIP_RAGE128TL 0x544C
#define PCI_CHIP_RAGE128TR 0x5452
#define PCI_CHIP_RAGE128TS 0x5453
#define PCI_CHIP_RAGE128TT 0x5454
#define PCI_CHIP_RAGE128TU 0x5455
#define PCI_CHIP_RV370_5460 0x5460
#define PCI_CHIP_RV370_5461 0x5461
#define PCI_CHIP_RV370_5462 0x5462
#define PCI_CHIP_RV370_5463 0x5463
#define PCI_CHIP_RV370_5464 0x5464
#define PCI_CHIP_RV370_5465 0x5465
#define PCI_CHIP_RV370_5466 0x5466
#define PCI_CHIP_RV370_5467 0x5467
#define PCI_CHIP_R423_UH 0x5548
#define PCI_CHIP_R423_UI 0x5549
#define PCI_CHIP_R423_UJ 0x554A
#define PCI_CHIP_R423_UK 0x554B
#define PCI_CHIP_R423_UQ 0x5551
#define PCI_CHIP_R423_UR 0x5552
#define PCI_CHIP_R423_UT 0x5554
#define PCI_CHIP_MACH64VT 0x5654
#define PCI_CHIP_MACH64VU 0x5655
#define PCI_CHIP_MACH64VV 0x5656
#define PCI_CHIP_RS300_5834 0x5834
#define PCI_CHIP_RS300_5835 0x5835
#define PCI_CHIP_RS300_5836 0x5836
#define PCI_CHIP_RS300_5837 0x5837
#define PCI_CHIP_RV370_5B60 0x5B60
#define PCI_CHIP_RV370_5B61 0x5B61
#define PCI_CHIP_RV370_5B62 0x5B62
#define PCI_CHIP_RV370_5B63 0x5B63
#define PCI_CHIP_RV370_5B64 0x5B64
#define PCI_CHIP_RV370_5B65 0x5B65
#define PCI_CHIP_RV370_5B66 0x5B66
#define PCI_CHIP_RV370_5B67 0x5B67
#define PCI_CHIP_RV280_5960 0x5960
#define PCI_CHIP_RV280_5961 0x5961
#define PCI_CHIP_RV280_5962 0x5962
#define PCI_CHIP_RV280_5964 0x5964
#define PCI_CHIP_RV280_5C61 0x5C61
#define PCI_CHIP_RV280_5C63 0x5C63
#define PCI_CHIP_R423_5D57 0x5D57
#define PCI_CHIP_RS350_7834 0x7834
#define PCI_CHIP_RS350_7835 0x7835
|
1001-study-uboot
|
drivers/video/ati_ids.h
|
C
|
gpl3
| 8,033
|
/*
* (C) Copyright 2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* cfb_console.c
*
* Color Framebuffer Console driver for 8/15/16/24/32 bits per pixel.
*
* At the moment only the 8x16 font is tested and the font fore- and
* background color is limited to black/white/gray colors. The Linux
* logo can be placed in the upper left corner and additional board
* information strings (that normally goes to serial port) can be drawn.
*
* The console driver can use the standard PC keyboard interface (i8042)
* for character input. Character output goes to a memory mapped video
* framebuffer with little or big-endian organisation.
* With environment setting 'console=serial' the console i/o can be
* forced to serial port.
*
* The driver uses graphic specific defines/parameters/functions:
*
* (for SMI LynxE graphic chip)
*
* CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810
* VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian
* VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill
* VIDEO_HW_BITBLT - graphic driver supports hardware bit blt
*
* Console Parameters are set by graphic drivers global struct:
*
* VIDEO_VISIBLE_COLS - x resolution
* VIDEO_VISIBLE_ROWS - y resolution
* VIDEO_PIXEL_SIZE - storage size in byte per pixel
* VIDEO_DATA_FORMAT - graphical data format GDF
* VIDEO_FB_ADRS - start of video memory
*
* CONFIG_I8042_KBD - AT Keyboard driver for i8042
* VIDEO_KBD_INIT_FCT - init function for keyboard
* VIDEO_TSTC_FCT - keyboard_tstc function
* VIDEO_GETC_FCT - keyboard_getc function
*
* CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with
* delay loop in VIDEO_TSTC_FCT (i8042)
*
* CONFIG_SYS_CONSOLE_BLINK_COUNT - value for delay loop - blink rate
* CONFIG_CONSOLE_TIME - display time/date in upper right
* corner, needs CONFIG_CMD_DATE and
* CONFIG_CONSOLE_CURSOR
* CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner
* CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo
* CONFIG_CONSOLE_EXTRA_INFO - display additional board information
* strings that normaly goes to serial
* port. This define requires a board
* specific function:
* video_drawstring (VIDEO_INFO_X,
* VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT,
* info);
* that fills a info buffer at i=row.
* s.a: board/eltec/bab7xx.
* CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be
* initialized as an output only device.
* The Keyboard driver will not be
* set-up. This may be used, if you have
* no or more than one Keyboard devices
* (USB Keyboard, AT Keyboard).
*
* CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last
* character. No blinking is provided.
* Uses the macros CURSOR_SET and
* CURSOR_OFF.
*
* CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability
* of the graphic chip. Uses the macro
* CURSOR_SET. ATTENTION: If booting an
* OS, the display driver must disable
* the hardware register of the graphic
* chip. Otherwise a blinking field is
* displayed.
*/
#include <common.h>
#include <version.h>
#include <malloc.h>
#include <linux/compiler.h>
/*
* Console device defines with SMI graphic
* Any other graphic must change this section
*/
#ifdef CONFIG_VIDEO_SMI_LYNXEM
#define VIDEO_FB_LITTLE_ENDIAN
#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT
#endif
/*
* Defines for the CT69000 driver
*/
#ifdef CONFIG_VIDEO_CT69000
#define VIDEO_FB_LITTLE_ENDIAN
#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT
#endif
/*
* Defines for the SED13806 driver
*/
#ifdef CONFIG_VIDEO_SED13806
#ifndef CONFIG_TOTAL5200
#define VIDEO_FB_LITTLE_ENDIAN
#endif
#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT
#endif
/*
* Defines for the SED13806 driver
*/
#ifdef CONFIG_VIDEO_SM501
#ifdef CONFIG_HH405
#define VIDEO_FB_LITTLE_ENDIAN
#endif
#endif
/*
* Defines for the MB862xx driver
*/
#ifdef CONFIG_VIDEO_MB862xx
#ifdef CONFIG_VIDEO_CORALP
#define VIDEO_FB_LITTLE_ENDIAN
#endif
#ifdef CONFIG_VIDEO_MB862xx_ACCEL
#define VIDEO_HW_RECTFILL
#define VIDEO_HW_BITBLT
#endif
#endif
/*
* Defines for the i.MX31 driver (mx3fb.c)
*/
#if defined(CONFIG_VIDEO_MX3) || defined(CONFIG_VIDEO_MX5)
#define VIDEO_FB_16BPP_WORD_SWAP
#endif
/*
* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc.
*/
#include <video_fb.h>
/*
* some Macros
*/
#define VIDEO_VISIBLE_COLS (pGD->winSizeX)
#define VIDEO_VISIBLE_ROWS (pGD->winSizeY)
#define VIDEO_PIXEL_SIZE (pGD->gdfBytesPP)
#define VIDEO_DATA_FORMAT (pGD->gdfIndex)
#define VIDEO_FB_ADRS (pGD->frameAdrs)
/*
* Console device defines with i8042 keyboard controller
* Any other keyboard controller must change this section
*/
#ifdef CONFIG_I8042_KBD
#include <i8042.h>
#define VIDEO_KBD_INIT_FCT i8042_kbd_init()
#define VIDEO_TSTC_FCT i8042_tstc
#define VIDEO_GETC_FCT i8042_getc
#endif
/*
* Console device
*/
#include <version.h>
#include <linux/types.h>
#include <stdio_dev.h>
#include <video_font.h>
#include <video_font_data.h>
#if defined(CONFIG_CMD_DATE)
#include <rtc.h>
#endif
#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
#include <watchdog.h>
#include <bmp_layout.h>
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
#define BMP_ALIGN_CENTER 0x7FFF
#endif
#endif
/*
* Cursor definition:
* CONFIG_CONSOLE_CURSOR: Uses a timer function (see drivers/input/i8042.c)
* to let the cursor blink. Uses the macros
* CURSOR_OFF and CURSOR_ON.
* CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No
* blinking is provided. Uses the macros CURSOR_SET
* and CURSOR_OFF.
* CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the
* graphic chip. Uses the macro CURSOR_SET.
* ATTENTION: If booting an OS, the display driver
* must disable the hardware register of the graphic
* chip. Otherwise a blinking field is displayed
*/
#if !defined(CONFIG_CONSOLE_CURSOR) && \
!defined(CONFIG_VIDEO_SW_CURSOR) && \
!defined(CONFIG_VIDEO_HW_CURSOR)
/* no Cursor defined */
#define CURSOR_ON
#define CURSOR_OFF
#define CURSOR_SET
#endif
#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR)
#if defined(CURSOR_ON) || \
(defined(CONFIG_CONSOLE_CURSOR) && defined(CONFIG_VIDEO_SW_CURSOR))
#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
or CONFIG_VIDEO_HW_CURSOR can be defined
#endif
void console_cursor(int state);
#define CURSOR_ON console_cursor(1)
#define CURSOR_OFF console_cursor(0)
#define CURSOR_SET video_set_cursor()
#endif /* CONFIG_CONSOLE_CURSOR || CONFIG_VIDEO_SW_CURSOR */
#ifdef CONFIG_CONSOLE_CURSOR
#ifndef CONFIG_CONSOLE_TIME
#error CONFIG_CONSOLE_CURSOR must be defined for CONFIG_CONSOLE_TIME
#endif
#ifndef CONFIG_I8042_KBD
#warning Cursor drawing on/off needs timer function s.a. drivers/input/i8042.c
#endif
#endif /* CONFIG_CONSOLE_CURSOR */
#ifdef CONFIG_VIDEO_HW_CURSOR
#ifdef CURSOR_ON
#error only one of CONFIG_CONSOLE_CURSOR, CONFIG_VIDEO_SW_CURSOR, \
or CONFIG_VIDEO_HW_CURSOR can be defined
#endif
#define CURSOR_ON
#define CURSOR_OFF
#define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \
(console_row * VIDEO_FONT_HEIGHT) + video_logo_height)
#endif /* CONFIG_VIDEO_HW_CURSOR */
#ifdef CONFIG_VIDEO_LOGO
#ifdef CONFIG_VIDEO_BMP_LOGO
#include <bmp_logo.h>
#include <bmp_logo_data.h>
#define VIDEO_LOGO_WIDTH BMP_LOGO_WIDTH
#define VIDEO_LOGO_HEIGHT BMP_LOGO_HEIGHT
#define VIDEO_LOGO_LUT_OFFSET BMP_LOGO_OFFSET
#define VIDEO_LOGO_COLORS BMP_LOGO_COLORS
#else /* CONFIG_VIDEO_BMP_LOGO */
#define LINUX_LOGO_WIDTH 80
#define LINUX_LOGO_HEIGHT 80
#define LINUX_LOGO_COLORS 214
#define LINUX_LOGO_LUT_OFFSET 0x20
#define __initdata
#include <linux_logo.h>
#define VIDEO_LOGO_WIDTH LINUX_LOGO_WIDTH
#define VIDEO_LOGO_HEIGHT LINUX_LOGO_HEIGHT
#define VIDEO_LOGO_LUT_OFFSET LINUX_LOGO_LUT_OFFSET
#define VIDEO_LOGO_COLORS LINUX_LOGO_COLORS
#endif /* CONFIG_VIDEO_BMP_LOGO */
#define VIDEO_INFO_X (VIDEO_LOGO_WIDTH)
#define VIDEO_INFO_Y (VIDEO_FONT_HEIGHT/2)
#else /* CONFIG_VIDEO_LOGO */
#define VIDEO_LOGO_WIDTH 0
#define VIDEO_LOGO_HEIGHT 0
#endif /* CONFIG_VIDEO_LOGO */
#define VIDEO_COLS VIDEO_VISIBLE_COLS
#define VIDEO_ROWS VIDEO_VISIBLE_ROWS
#define VIDEO_SIZE (VIDEO_ROWS*VIDEO_COLS*VIDEO_PIXEL_SIZE)
#define VIDEO_PIX_BLOCKS (VIDEO_SIZE >> 2)
#define VIDEO_LINE_LEN (VIDEO_COLS*VIDEO_PIXEL_SIZE)
#define VIDEO_BURST_LEN (VIDEO_COLS/8)
#ifdef CONFIG_VIDEO_LOGO
#define CONSOLE_ROWS ((VIDEO_ROWS - video_logo_height) / VIDEO_FONT_HEIGHT)
#else
#define CONSOLE_ROWS (VIDEO_ROWS / VIDEO_FONT_HEIGHT)
#endif
#define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH)
#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN)
#define CONSOLE_ROW_FIRST (video_console_address)
#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE)
#define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE)
#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS)
#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE)
/* Macros */
#ifdef VIDEO_FB_LITTLE_ENDIAN
#define SWAP16(x) ((((x) & 0x00ff) << 8) | \
((x) >> 8) \
)
#define SWAP32(x) ((((x) & 0x000000ff) << 24) | \
(((x) & 0x0000ff00) << 8) | \
(((x) & 0x00ff0000) >> 8) | \
(((x) & 0xff000000) >> 24) \
)
#define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | \
(((x) & 0x0000ff00) >> 8) | \
(((x) & 0x00ff0000) << 8) | \
(((x) & 0xff000000) >> 8) \
)
#else
#define SWAP16(x) (x)
#define SWAP32(x) (x)
#if defined(VIDEO_FB_16BPP_WORD_SWAP)
#define SHORTSWAP32(x) (((x) >> 16) | ((x) << 16))
#else
#define SHORTSWAP32(x) (x)
#endif
#endif
#ifdef CONFIG_CONSOLE_EXTRA_INFO
/*
* setup a board string: type, speed, etc.
*
* line_number: location to place info string beside logo
* info: buffer for info string
*/
extern void video_get_info_str(int line_number, char *info);
#endif
/* Locals */
static GraphicDevice *pGD; /* Pointer to Graphic array */
static void *video_fb_address; /* frame buffer address */
static void *video_console_address; /* console buffer start address */
static int video_logo_height = VIDEO_LOGO_HEIGHT;
static int __maybe_unused cursor_state;
static int __maybe_unused old_col;
static int __maybe_unused old_row;
static int console_col; /* cursor col */
static int console_row; /* cursor row */
static u32 eorx, fgx, bgx; /* color pats */
static const int video_font_draw_table8[] = {
0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
};
static const int video_font_draw_table15[] = {
0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff
};
static const int video_font_draw_table16[] = {
0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff
};
static const int video_font_draw_table24[16][3] = {
{0x00000000, 0x00000000, 0x00000000},
{0x00000000, 0x00000000, 0x00ffffff},
{0x00000000, 0x0000ffff, 0xff000000},
{0x00000000, 0x0000ffff, 0xffffffff},
{0x000000ff, 0xffff0000, 0x00000000},
{0x000000ff, 0xffff0000, 0x00ffffff},
{0x000000ff, 0xffffffff, 0xff000000},
{0x000000ff, 0xffffffff, 0xffffffff},
{0xffffff00, 0x00000000, 0x00000000},
{0xffffff00, 0x00000000, 0x00ffffff},
{0xffffff00, 0x0000ffff, 0xff000000},
{0xffffff00, 0x0000ffff, 0xffffffff},
{0xffffffff, 0xffff0000, 0x00000000},
{0xffffffff, 0xffff0000, 0x00ffffff},
{0xffffffff, 0xffffffff, 0xff000000},
{0xffffffff, 0xffffffff, 0xffffffff}
};
static const int video_font_draw_table32[16][4] = {
{0x00000000, 0x00000000, 0x00000000, 0x00000000},
{0x00000000, 0x00000000, 0x00000000, 0x00ffffff},
{0x00000000, 0x00000000, 0x00ffffff, 0x00000000},
{0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff},
{0x00000000, 0x00ffffff, 0x00000000, 0x00000000},
{0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff},
{0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000},
{0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff},
{0x00ffffff, 0x00000000, 0x00000000, 0x00000000},
{0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff},
{0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000},
{0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff},
{0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000},
{0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff},
{0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000},
{0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff}
};
static void video_drawchars(int xx, int yy, unsigned char *s, int count)
{
u8 *cdat, *dest, *dest0;
int rows, offset, c;
offset = yy * VIDEO_LINE_LEN + xx * VIDEO_PIXEL_SIZE;
dest0 = video_fb_address + offset;
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
case GDF__8BIT_332RGB:
while (count--) {
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
((u32 *) dest)[0] =
(video_font_draw_table8[bits >> 4] &
eorx) ^ bgx;
((u32 *) dest)[1] =
(video_font_draw_table8[bits & 15] &
eorx) ^ bgx;
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
}
break;
case GDF_15BIT_555RGB:
while (count--) {
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
((u32 *) dest)[0] =
SHORTSWAP32((video_font_draw_table15
[bits >> 6] & eorx) ^
bgx);
((u32 *) dest)[1] =
SHORTSWAP32((video_font_draw_table15
[bits >> 4 & 3] & eorx) ^
bgx);
((u32 *) dest)[2] =
SHORTSWAP32((video_font_draw_table15
[bits >> 2 & 3] & eorx) ^
bgx);
((u32 *) dest)[3] =
SHORTSWAP32((video_font_draw_table15
[bits & 3] & eorx) ^
bgx);
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
}
break;
case GDF_16BIT_565RGB:
while (count--) {
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
((u32 *) dest)[0] =
SHORTSWAP32((video_font_draw_table16
[bits >> 6] & eorx) ^
bgx);
((u32 *) dest)[1] =
SHORTSWAP32((video_font_draw_table16
[bits >> 4 & 3] & eorx) ^
bgx);
((u32 *) dest)[2] =
SHORTSWAP32((video_font_draw_table16
[bits >> 2 & 3] & eorx) ^
bgx);
((u32 *) dest)[3] =
SHORTSWAP32((video_font_draw_table16
[bits & 3] & eorx) ^
bgx);
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
}
break;
case GDF_32BIT_X888RGB:
while (count--) {
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
((u32 *) dest)[0] =
SWAP32((video_font_draw_table32
[bits >> 4][0] & eorx) ^ bgx);
((u32 *) dest)[1] =
SWAP32((video_font_draw_table32
[bits >> 4][1] & eorx) ^ bgx);
((u32 *) dest)[2] =
SWAP32((video_font_draw_table32
[bits >> 4][2] & eorx) ^ bgx);
((u32 *) dest)[3] =
SWAP32((video_font_draw_table32
[bits >> 4][3] & eorx) ^ bgx);
((u32 *) dest)[4] =
SWAP32((video_font_draw_table32
[bits & 15][0] & eorx) ^ bgx);
((u32 *) dest)[5] =
SWAP32((video_font_draw_table32
[bits & 15][1] & eorx) ^ bgx);
((u32 *) dest)[6] =
SWAP32((video_font_draw_table32
[bits & 15][2] & eorx) ^ bgx);
((u32 *) dest)[7] =
SWAP32((video_font_draw_table32
[bits & 15][3] & eorx) ^ bgx);
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
}
break;
case GDF_24BIT_888RGB:
while (count--) {
c = *s;
cdat = video_fontdata + c * VIDEO_FONT_HEIGHT;
for (rows = VIDEO_FONT_HEIGHT, dest = dest0;
rows--; dest += VIDEO_LINE_LEN) {
u8 bits = *cdat++;
((u32 *) dest)[0] =
(video_font_draw_table24[bits >> 4][0]
& eorx) ^ bgx;
((u32 *) dest)[1] =
(video_font_draw_table24[bits >> 4][1]
& eorx) ^ bgx;
((u32 *) dest)[2] =
(video_font_draw_table24[bits >> 4][2]
& eorx) ^ bgx;
((u32 *) dest)[3] =
(video_font_draw_table24[bits & 15][0]
& eorx) ^ bgx;
((u32 *) dest)[4] =
(video_font_draw_table24[bits & 15][1]
& eorx) ^ bgx;
((u32 *) dest)[5] =
(video_font_draw_table24[bits & 15][2]
& eorx) ^ bgx;
}
dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE;
s++;
}
break;
}
}
static inline void video_drawstring(int xx, int yy, unsigned char *s)
{
video_drawchars(xx, yy, s, strlen((char *) s));
}
static void video_putchar(int xx, int yy, unsigned char c)
{
video_drawchars(xx, yy + video_logo_height, &c, 1);
}
#if defined(CONFIG_CONSOLE_CURSOR) || defined(CONFIG_VIDEO_SW_CURSOR)
static void video_set_cursor(void)
{
if (cursor_state)
console_cursor(0);
console_cursor(1);
}
static void video_invertchar(int xx, int yy)
{
int firstx = xx * VIDEO_PIXEL_SIZE;
int lastx = (xx + VIDEO_FONT_WIDTH) * VIDEO_PIXEL_SIZE;
int firsty = yy * VIDEO_LINE_LEN;
int lasty = (yy + VIDEO_FONT_HEIGHT) * VIDEO_LINE_LEN;
int x, y;
for (y = firsty; y < lasty; y += VIDEO_LINE_LEN) {
for (x = firstx; x < lastx; x++) {
u8 *dest = (u8 *)(video_fb_address) + x + y;
*dest = ~*dest;
}
}
}
void console_cursor(int state)
{
#ifdef CONFIG_CONSOLE_TIME
struct rtc_time tm;
char info[16];
/* time update only if cursor is on (faster scroll) */
if (state) {
rtc_get(&tm);
sprintf(info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min,
tm.tm_sec);
video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
VIDEO_INFO_Y, (uchar *) info);
sprintf(info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon,
tm.tm_year);
video_drawstring(VIDEO_VISIBLE_COLS - 10 * VIDEO_FONT_WIDTH,
VIDEO_INFO_Y + 1 * VIDEO_FONT_HEIGHT,
(uchar *) info);
}
#endif
if (cursor_state != state) {
if (cursor_state) {
/* turn off the cursor */
video_invertchar(old_col * VIDEO_FONT_WIDTH,
old_row * VIDEO_FONT_HEIGHT +
video_logo_height);
} else {
/* turn off the cursor and record where it is */
video_invertchar(console_col * VIDEO_FONT_WIDTH,
console_row * VIDEO_FONT_HEIGHT +
video_logo_height);
old_col = console_col;
old_row = console_row;
}
cursor_state = state;
}
}
#endif
#ifndef VIDEO_HW_RECTFILL
static void memsetl(int *p, int c, int v)
{
while (c--)
*(p++) = v;
}
#endif
#ifndef VIDEO_HW_BITBLT
static void memcpyl(int *d, int *s, int c)
{
while (c--)
*(d++) = *(s++);
}
#endif
static void console_scrollup(void)
{
/* copy up rows ignoring the first one */
#ifdef VIDEO_HW_BITBLT
video_hw_bitblt(VIDEO_PIXEL_SIZE, /* bytes per pixel */
0, /* source pos x */
video_logo_height +
VIDEO_FONT_HEIGHT, /* source pos y */
0, /* dest pos x */
video_logo_height, /* dest pos y */
VIDEO_VISIBLE_COLS, /* frame width */
VIDEO_VISIBLE_ROWS
- video_logo_height
- VIDEO_FONT_HEIGHT /* frame height */
);
#else
memcpyl(CONSOLE_ROW_FIRST, CONSOLE_ROW_SECOND,
CONSOLE_SCROLL_SIZE >> 2);
#endif
/* clear the last one */
#ifdef VIDEO_HW_RECTFILL
video_hw_rectfill(VIDEO_PIXEL_SIZE, /* bytes per pixel */
0, /* dest pos x */
VIDEO_VISIBLE_ROWS
- VIDEO_FONT_HEIGHT, /* dest pos y */
VIDEO_VISIBLE_COLS, /* frame width */
VIDEO_FONT_HEIGHT, /* frame height */
CONSOLE_BG_COL /* fill color */
);
#else
memsetl(CONSOLE_ROW_LAST, CONSOLE_ROW_SIZE >> 2, CONSOLE_BG_COL);
#endif
}
static void console_back(void)
{
CURSOR_OFF;
console_col--;
if (console_col < 0) {
console_col = CONSOLE_COLS - 1;
console_row--;
if (console_row < 0)
console_row = 0;
}
CURSOR_SET;
}
static void console_newline(void)
{
console_row++;
console_col = 0;
/* Check if we need to scroll the terminal */
if (console_row >= CONSOLE_ROWS) {
/* Scroll everything up */
console_scrollup();
/* Decrement row number */
console_row--;
}
}
static void console_cr(void)
{
console_col = 0;
}
void video_putc(const char c)
{
static int nl = 1;
CURSOR_OFF;
switch (c) {
case 13: /* back to first column */
console_cr();
break;
case '\n': /* next line */
if (console_col || (!console_col && nl))
console_newline();
nl = 1;
break;
case 9: /* tab 8 */
console_col |= 0x0008;
console_col &= ~0x0007;
if (console_col >= CONSOLE_COLS)
console_newline();
break;
case 8: /* backspace */
console_back();
break;
default: /* draw the char */
video_putchar(console_col * VIDEO_FONT_WIDTH,
console_row * VIDEO_FONT_HEIGHT, c);
console_col++;
/* check for newline */
if (console_col >= CONSOLE_COLS) {
console_newline();
nl = 0;
}
}
CURSOR_SET;
}
void video_puts(const char *s)
{
int count = strlen(s);
while (count--)
video_putc(*s++);
}
/*
* Do not enforce drivers (or board code) to provide empty
* video_set_lut() if they do not support 8 bpp format.
* Implement weak default function instead.
*/
void __video_set_lut(unsigned int index, unsigned char r,
unsigned char g, unsigned char b)
{
}
void video_set_lut(unsigned int, unsigned char, unsigned char, unsigned char)
__attribute__ ((weak, alias("__video_set_lut")));
#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
#define FILL_8BIT_332RGB(r,g,b) { \
*fb = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6); \
fb ++; \
}
#define FILL_15BIT_555RGB(r,g,b) { \
*(unsigned short *)fb = \
SWAP16((unsigned short)(((r>>3)<<10) | \
((g>>3)<<5) | \
(b>>3))); \
fb += 2; \
}
#define FILL_16BIT_565RGB(r,g,b) { \
*(unsigned short *)fb = \
SWAP16((unsigned short)((((r)>>3)<<11)| \
(((g)>>2)<<5) | \
((b)>>3))); \
fb += 2; \
}
#define FILL_32BIT_X888RGB(r,g,b) { \
*(unsigned long *)fb = \
SWAP32((unsigned long)(((r<<16) | \
(g<<8) | \
b))); \
fb += 4; \
}
#ifdef VIDEO_FB_LITTLE_ENDIAN
#define FILL_24BIT_888RGB(r,g,b) { \
fb[0] = b; \
fb[1] = g; \
fb[2] = r; \
fb += 3; \
}
#else
#define FILL_24BIT_888RGB(r,g,b) { \
fb[0] = r; \
fb[1] = g; \
fb[2] = b; \
fb += 3; \
}
#endif
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
static inline void fill_555rgb_pswap(uchar *fb, int x, u8 r, u8 g, u8 b)
{
ushort *dst = (ushort *) fb;
ushort color = (ushort) (((r >> 3) << 10) |
((g >> 3) << 5) |
(b >> 3));
if (x & 1)
*(--dst) = color;
else
*(++dst) = color;
}
#endif
/*
* RLE8 bitmap support
*/
#ifdef CONFIG_VIDEO_BMP_RLE8
/* Pre-calculated color table entry */
struct palette {
union {
unsigned short w; /* word */
unsigned int dw; /* double word */
} ce; /* color entry */
};
/*
* Helper to draw encoded/unencoded run.
*/
static void draw_bitmap(uchar **fb, uchar *bm, struct palette *p,
int cnt, int enc)
{
ulong addr = (ulong) *fb;
int *off;
int enc_off = 1;
int i;
/*
* Setup offset of the color index in the bitmap.
* Color index of encoded run is at offset 1.
*/
off = enc ? &enc_off : &i;
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
for (i = 0; i < cnt; i++)
*(unsigned char *) addr++ = bm[*off];
break;
case GDF_15BIT_555RGB:
case GDF_16BIT_565RGB:
/* differences handled while pre-calculating palette */
for (i = 0; i < cnt; i++) {
*(unsigned short *) addr = p[bm[*off]].ce.w;
addr += 2;
}
break;
case GDF_32BIT_X888RGB:
for (i = 0; i < cnt; i++) {
*(unsigned long *) addr = p[bm[*off]].ce.dw;
addr += 4;
}
break;
}
*fb = (uchar *) addr; /* return modified address */
}
static int display_rle8_bitmap(bmp_image_t *img, int xoff, int yoff,
int width, int height)
{
unsigned char *bm;
unsigned char *fbp;
unsigned int cnt, runlen;
int decode = 1;
int x, y, bpp, i, ncolors;
struct palette p[256];
bmp_color_table_entry_t cte;
int green_shift, red_off;
int limit = VIDEO_COLS * VIDEO_ROWS;
int pixels = 0;
x = 0;
y = __le32_to_cpu(img->header.height) - 1;
ncolors = __le32_to_cpu(img->header.colors_used);
bpp = VIDEO_PIXEL_SIZE;
fbp = (unsigned char *) ((unsigned int) video_fb_address +
(((y + yoff) * VIDEO_COLS) + xoff) * bpp);
bm = (uchar *) img + __le32_to_cpu(img->header.data_offset);
/* pre-calculate and setup palette */
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
for (i = 0; i < ncolors; i++) {
cte = img->color_table[i];
video_set_lut(i, cte.red, cte.green, cte.blue);
}
break;
case GDF_15BIT_555RGB:
case GDF_16BIT_565RGB:
if (VIDEO_DATA_FORMAT == GDF_15BIT_555RGB) {
green_shift = 3;
red_off = 10;
} else {
green_shift = 2;
red_off = 11;
}
for (i = 0; i < ncolors; i++) {
cte = img->color_table[i];
p[i].ce.w = SWAP16((unsigned short)
(((cte.red >> 3) << red_off) |
((cte.green >> green_shift) << 5) |
cte.blue >> 3));
}
break;
case GDF_32BIT_X888RGB:
for (i = 0; i < ncolors; i++) {
cte = img->color_table[i];
p[i].ce.dw = SWAP32((cte.red << 16) |
(cte.green << 8) |
cte.blue);
}
break;
default:
printf("RLE Bitmap unsupported in video mode 0x%x\n",
VIDEO_DATA_FORMAT);
return -1;
}
while (decode) {
switch (bm[0]) {
case 0:
switch (bm[1]) {
case 0:
/* scan line end marker */
bm += 2;
x = 0;
y--;
fbp = (unsigned char *)
((unsigned int) video_fb_address +
(((y + yoff) * VIDEO_COLS) +
xoff) * bpp);
continue;
case 1:
/* end of bitmap data marker */
decode = 0;
break;
case 2:
/* run offset marker */
x += bm[2];
y -= bm[3];
fbp = (unsigned char *)
((unsigned int) video_fb_address +
(((y + yoff) * VIDEO_COLS) +
x + xoff) * bpp);
bm += 4;
break;
default:
/* unencoded run */
cnt = bm[1];
runlen = cnt;
pixels += cnt;
if (pixels > limit)
goto error;
bm += 2;
if (y < height) {
if (x >= width) {
x += runlen;
goto next_run;
}
if (x + runlen > width)
cnt = width - x;
draw_bitmap(&fbp, bm, p, cnt, 0);
x += runlen;
}
next_run:
bm += runlen;
if (runlen & 1)
bm++; /* 0 padding if length is odd */
}
break;
default:
/* encoded run */
cnt = bm[0];
runlen = cnt;
pixels += cnt;
if (pixels > limit)
goto error;
if (y < height) { /* only draw into visible area */
if (x >= width) {
x += runlen;
bm += 2;
continue;
}
if (x + runlen > width)
cnt = width - x;
draw_bitmap(&fbp, bm, p, cnt, 1);
x += runlen;
}
bm += 2;
break;
}
}
return 0;
error:
printf("Error: Too much encoded pixel data, validate your bitmap\n");
return -1;
}
#endif
/*
* Display the BMP file located at address bmp_image.
*/
int video_display_bitmap(ulong bmp_image, int x, int y)
{
ushort xcount, ycount;
uchar *fb;
bmp_image_t *bmp = (bmp_image_t *) bmp_image;
uchar *bmap;
ushort padded_line;
unsigned long width, height, bpp;
unsigned colors;
unsigned long compression;
bmp_color_table_entry_t cte;
#ifdef CONFIG_VIDEO_BMP_GZIP
unsigned char *dst = NULL;
ulong len;
#endif
WATCHDOG_RESET();
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
#ifdef CONFIG_VIDEO_BMP_GZIP
/*
* Could be a gzipped bmp image, try to decrompress...
*/
len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
if (dst == NULL) {
printf("Error: malloc in gunzip failed!\n");
return 1;
}
if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
(uchar *) bmp_image,
&len) != 0) {
printf("Error: no valid bmp or bmp.gz image at %lx\n",
bmp_image);
free(dst);
return 1;
}
if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
printf("Image could be truncated "
"(increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
}
/*
* Set addr to decompressed image
*/
bmp = (bmp_image_t *) dst;
if (!((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M'))) {
printf("Error: no valid bmp.gz image at %lx\n",
bmp_image);
free(dst);
return 1;
}
#else
printf("Error: no valid bmp image at %lx\n", bmp_image);
return 1;
#endif /* CONFIG_VIDEO_BMP_GZIP */
}
width = le32_to_cpu(bmp->header.width);
height = le32_to_cpu(bmp->header.height);
bpp = le16_to_cpu(bmp->header.bit_count);
colors = le32_to_cpu(bmp->header.colors_used);
compression = le32_to_cpu(bmp->header.compression);
debug("Display-bmp: %ld x %ld with %d colors\n",
width, height, colors);
if (compression != BMP_BI_RGB
#ifdef CONFIG_VIDEO_BMP_RLE8
&& compression != BMP_BI_RLE8
#endif
) {
printf("Error: compression type %ld not supported\n",
compression);
#ifdef CONFIG_VIDEO_BMP_GZIP
if (dst)
free(dst);
#endif
return 1;
}
padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3;
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
if (x == BMP_ALIGN_CENTER)
x = max(0, (VIDEO_VISIBLE_COLS - width) / 2);
else if (x < 0)
x = max(0, VIDEO_VISIBLE_COLS - width + x + 1);
if (y == BMP_ALIGN_CENTER)
y = max(0, (VIDEO_VISIBLE_ROWS - height) / 2);
else if (y < 0)
y = max(0, VIDEO_VISIBLE_ROWS - height + y + 1);
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
if ((x + width) > VIDEO_VISIBLE_COLS)
width = VIDEO_VISIBLE_COLS - x;
if ((y + height) > VIDEO_VISIBLE_ROWS)
height = VIDEO_VISIBLE_ROWS - y;
bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset);
fb = (uchar *) (video_fb_address +
((y + height - 1) * VIDEO_COLS * VIDEO_PIXEL_SIZE) +
x * VIDEO_PIXEL_SIZE);
#ifdef CONFIG_VIDEO_BMP_RLE8
if (compression == BMP_BI_RLE8) {
return display_rle8_bitmap(bmp, x, y, width, height);
}
#endif
/* We handle only 4, 8, or 24 bpp bitmaps */
switch (le16_to_cpu(bmp->header.bit_count)) {
case 4:
padded_line -= width / 2;
ycount = height;
switch (VIDEO_DATA_FORMAT) {
case GDF_32BIT_X888RGB:
while (ycount--) {
WATCHDOG_RESET();
/*
* Don't assume that 'width' is an
* even number
*/
for (xcount = 0; xcount < width; xcount++) {
uchar idx;
if (xcount & 1) {
idx = *bmap & 0xF;
bmap++;
} else
idx = *bmap >> 4;
cte = bmp->color_table[idx];
FILL_32BIT_X888RGB(cte.red, cte.green,
cte.blue);
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
default:
puts("4bpp bitmap unsupported with current "
"video mode\n");
break;
}
break;
case 8:
padded_line -= width;
if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) {
/* Copy colormap */
for (xcount = 0; xcount < colors; ++xcount) {
cte = bmp->color_table[xcount];
video_set_lut(xcount, cte.red, cte.green,
cte.blue);
}
}
ycount = height;
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
while (ycount--) {
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
*fb++ = *bmap++;
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
case GDF__8BIT_332RGB:
while (ycount--) {
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
FILL_8BIT_332RGB(cte.red, cte.green,
cte.blue);
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
case GDF_15BIT_555RGB:
while (ycount--) {
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
fill_555rgb_pswap(fb, xpos++, cte.red,
cte.green,
cte.blue);
fb += 2;
#else
FILL_15BIT_555RGB(cte.red, cte.green,
cte.blue);
#endif
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
case GDF_16BIT_565RGB:
while (ycount--) {
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
FILL_16BIT_565RGB(cte.red, cte.green,
cte.blue);
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
case GDF_32BIT_X888RGB:
while (ycount--) {
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
FILL_32BIT_X888RGB(cte.red, cte.green,
cte.blue);
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
case GDF_24BIT_888RGB:
while (ycount--) {
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
cte = bmp->color_table[*bmap++];
FILL_24BIT_888RGB(cte.red, cte.green,
cte.blue);
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
}
break;
case 24:
padded_line -= 3 * width;
ycount = height;
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_332RGB:
while (ycount--) {
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
FILL_8BIT_332RGB(bmap[2], bmap[1],
bmap[0]);
bmap += 3;
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
case GDF_15BIT_555RGB:
while (ycount--) {
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
fill_555rgb_pswap(fb, xpos++, bmap[2],
bmap[1], bmap[0]);
fb += 2;
#else
FILL_15BIT_555RGB(bmap[2], bmap[1],
bmap[0]);
#endif
bmap += 3;
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
case GDF_16BIT_565RGB:
while (ycount--) {
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
FILL_16BIT_565RGB(bmap[2], bmap[1],
bmap[0]);
bmap += 3;
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
case GDF_32BIT_X888RGB:
while (ycount--) {
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
FILL_32BIT_X888RGB(bmap[2], bmap[1],
bmap[0]);
bmap += 3;
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
case GDF_24BIT_888RGB:
while (ycount--) {
WATCHDOG_RESET();
xcount = width;
while (xcount--) {
FILL_24BIT_888RGB(bmap[2], bmap[1],
bmap[0]);
bmap += 3;
}
bmap += padded_line;
fb -= (VIDEO_VISIBLE_COLS + width) *
VIDEO_PIXEL_SIZE;
}
break;
default:
printf("Error: 24 bits/pixel bitmap incompatible "
"with current video mode\n");
break;
}
break;
default:
printf("Error: %d bit/pixel bitmaps not supported by U-Boot\n",
le16_to_cpu(bmp->header.bit_count));
break;
}
#ifdef CONFIG_VIDEO_BMP_GZIP
if (dst) {
free(dst);
}
#endif
return (0);
}
#endif
#ifdef CONFIG_VIDEO_LOGO
void logo_plot(void *screen, int width, int x, int y)
{
int xcount, i;
int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE;
int ycount = video_logo_height;
unsigned char r, g, b, *logo_red, *logo_blue, *logo_green;
unsigned char *source;
unsigned char *dest = (unsigned char *) screen +
((y * width * VIDEO_PIXEL_SIZE) + x * VIDEO_PIXEL_SIZE);
#ifdef CONFIG_VIDEO_BMP_LOGO
source = bmp_logo_bitmap;
/* Allocate temporary space for computing colormap */
logo_red = malloc(BMP_LOGO_COLORS);
logo_green = malloc(BMP_LOGO_COLORS);
logo_blue = malloc(BMP_LOGO_COLORS);
/* Compute color map */
for (i = 0; i < VIDEO_LOGO_COLORS; i++) {
logo_red[i] = (bmp_logo_palette[i] & 0x0f00) >> 4;
logo_green[i] = (bmp_logo_palette[i] & 0x00f0);
logo_blue[i] = (bmp_logo_palette[i] & 0x000f) << 4;
}
#else
source = linux_logo;
logo_red = linux_logo_red;
logo_green = linux_logo_green;
logo_blue = linux_logo_blue;
#endif
if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) {
for (i = 0; i < VIDEO_LOGO_COLORS; i++) {
video_set_lut(i + VIDEO_LOGO_LUT_OFFSET,
logo_red[i], logo_green[i],
logo_blue[i]);
}
}
while (ycount--) {
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
int xpos = x;
#endif
xcount = VIDEO_LOGO_WIDTH;
while (xcount--) {
r = logo_red[*source - VIDEO_LOGO_LUT_OFFSET];
g = logo_green[*source - VIDEO_LOGO_LUT_OFFSET];
b = logo_blue[*source - VIDEO_LOGO_LUT_OFFSET];
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
*dest = *source;
break;
case GDF__8BIT_332RGB:
*dest = ((r >> 5) << 5) |
((g >> 5) << 2) |
(b >> 6);
break;
case GDF_15BIT_555RGB:
#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
fill_555rgb_pswap(dest, xpos++, r, g, b);
#else
*(unsigned short *) dest =
SWAP16((unsigned short) (
((r >> 3) << 10) |
((g >> 3) << 5) |
(b >> 3)));
#endif
break;
case GDF_16BIT_565RGB:
*(unsigned short *) dest =
SWAP16((unsigned short) (
((r >> 3) << 11) |
((g >> 2) << 5) |
(b >> 3)));
break;
case GDF_32BIT_X888RGB:
*(unsigned long *) dest =
SWAP32((unsigned long) (
(r << 16) |
(g << 8) |
b));
break;
case GDF_24BIT_888RGB:
#ifdef VIDEO_FB_LITTLE_ENDIAN
dest[0] = b;
dest[1] = g;
dest[2] = r;
#else
dest[0] = r;
dest[1] = g;
dest[2] = b;
#endif
break;
}
source++;
dest += VIDEO_PIXEL_SIZE;
}
dest += skip;
}
#ifdef CONFIG_VIDEO_BMP_LOGO
free(logo_red);
free(logo_green);
free(logo_blue);
#endif
}
static void *video_logo(void)
{
char info[128];
int space, len;
__maybe_unused int y_off = 0;
#ifdef CONFIG_SPLASH_SCREEN
char *s;
ulong addr;
s = getenv("splashimage");
if (s != NULL) {
int x = 0, y = 0;
addr = simple_strtoul(s, NULL, 16);
#ifdef CONFIG_SPLASH_SCREEN_ALIGN
s = getenv("splashpos");
if (s != NULL) {
if (s[0] == 'm')
x = BMP_ALIGN_CENTER;
else
x = simple_strtol(s, NULL, 0);
s = strchr(s + 1, ',');
if (s != NULL) {
if (s[1] == 'm')
y = BMP_ALIGN_CENTER;
else
y = simple_strtol(s + 1, NULL, 0);
}
}
#endif /* CONFIG_SPLASH_SCREEN_ALIGN */
if (video_display_bitmap(addr, x, y) == 0) {
video_logo_height = 0;
return ((void *) (video_fb_address));
}
}
#endif /* CONFIG_SPLASH_SCREEN */
logo_plot(video_fb_address, VIDEO_COLS, 0, 0);
sprintf(info, " %s", version_string);
space = (VIDEO_LINE_LEN / 2 - VIDEO_INFO_X) / VIDEO_FONT_WIDTH;
len = strlen(info);
if (len > space) {
video_drawchars(VIDEO_INFO_X, VIDEO_INFO_Y,
(uchar *) info, space);
video_drawchars(VIDEO_INFO_X + VIDEO_FONT_WIDTH,
VIDEO_INFO_Y + VIDEO_FONT_HEIGHT,
(uchar *) info + space, len - space);
y_off = 1;
} else
video_drawstring(VIDEO_INFO_X, VIDEO_INFO_Y, (uchar *) info);
#ifdef CONFIG_CONSOLE_EXTRA_INFO
{
int i, n =
((video_logo_height -
VIDEO_FONT_HEIGHT) / VIDEO_FONT_HEIGHT);
for (i = 1; i < n; i++) {
video_get_info_str(i, info);
if (!*info)
continue;
len = strlen(info);
if (len > space) {
video_drawchars(VIDEO_INFO_X,
VIDEO_INFO_Y +
(i + y_off) *
VIDEO_FONT_HEIGHT,
(uchar *) info, space);
y_off++;
video_drawchars(VIDEO_INFO_X +
VIDEO_FONT_WIDTH,
VIDEO_INFO_Y +
(i + y_off) *
VIDEO_FONT_HEIGHT,
(uchar *) info + space,
len - space);
} else {
video_drawstring(VIDEO_INFO_X,
VIDEO_INFO_Y +
(i + y_off) *
VIDEO_FONT_HEIGHT,
(uchar *) info);
}
}
}
#endif
return (video_fb_address + video_logo_height * VIDEO_LINE_LEN);
}
#endif
static int video_init(void)
{
unsigned char color8;
pGD = video_hw_init();
if (pGD == NULL)
return -1;
video_fb_address = (void *) VIDEO_FB_ADRS;
#ifdef CONFIG_VIDEO_HW_CURSOR
video_init_hw_cursor(VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT);
#endif
/* Init drawing pats */
switch (VIDEO_DATA_FORMAT) {
case GDF__8BIT_INDEX:
video_set_lut(0x01, CONSOLE_FG_COL, CONSOLE_FG_COL,
CONSOLE_FG_COL);
video_set_lut(0x00, CONSOLE_BG_COL, CONSOLE_BG_COL,
CONSOLE_BG_COL);
fgx = 0x01010101;
bgx = 0x00000000;
break;
case GDF__8BIT_332RGB:
color8 = ((CONSOLE_FG_COL & 0xe0) |
((CONSOLE_FG_COL >> 3) & 0x1c) |
CONSOLE_FG_COL >> 6);
fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) |
color8;
color8 = ((CONSOLE_BG_COL & 0xe0) |
((CONSOLE_BG_COL >> 3) & 0x1c) |
CONSOLE_BG_COL >> 6);
bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) |
color8;
break;
case GDF_15BIT_555RGB:
fgx = (((CONSOLE_FG_COL >> 3) << 26) |
((CONSOLE_FG_COL >> 3) << 21) |
((CONSOLE_FG_COL >> 3) << 16) |
((CONSOLE_FG_COL >> 3) << 10) |
((CONSOLE_FG_COL >> 3) << 5) |
(CONSOLE_FG_COL >> 3));
bgx = (((CONSOLE_BG_COL >> 3) << 26) |
((CONSOLE_BG_COL >> 3) << 21) |
((CONSOLE_BG_COL >> 3) << 16) |
((CONSOLE_BG_COL >> 3) << 10) |
((CONSOLE_BG_COL >> 3) << 5) |
(CONSOLE_BG_COL >> 3));
break;
case GDF_16BIT_565RGB:
fgx = (((CONSOLE_FG_COL >> 3) << 27) |
((CONSOLE_FG_COL >> 2) << 21) |
((CONSOLE_FG_COL >> 3) << 16) |
((CONSOLE_FG_COL >> 3) << 11) |
((CONSOLE_FG_COL >> 2) << 5) |
(CONSOLE_FG_COL >> 3));
bgx = (((CONSOLE_BG_COL >> 3) << 27) |
((CONSOLE_BG_COL >> 2) << 21) |
((CONSOLE_BG_COL >> 3) << 16) |
((CONSOLE_BG_COL >> 3) << 11) |
((CONSOLE_BG_COL >> 2) << 5) |
(CONSOLE_BG_COL >> 3));
break;
case GDF_32BIT_X888RGB:
fgx = (CONSOLE_FG_COL << 16) |
(CONSOLE_FG_COL << 8) |
CONSOLE_FG_COL;
bgx = (CONSOLE_BG_COL << 16) |
(CONSOLE_BG_COL << 8) |
CONSOLE_BG_COL;
break;
case GDF_24BIT_888RGB:
fgx = (CONSOLE_FG_COL << 24) |
(CONSOLE_FG_COL << 16) |
(CONSOLE_FG_COL << 8) |
CONSOLE_FG_COL;
bgx = (CONSOLE_BG_COL << 24) |
(CONSOLE_BG_COL << 16) |
(CONSOLE_BG_COL << 8) |
CONSOLE_BG_COL;
break;
}
eorx = fgx ^ bgx;
#ifdef CONFIG_VIDEO_LOGO
/* Plot the logo and get start point of console */
debug("Video: Drawing the logo ...\n");
video_console_address = video_logo();
#else
video_console_address = video_fb_address;
#endif
/* Initialize the console */
console_col = 0;
console_row = 0;
return 0;
}
/*
* Implement a weak default function for boards that optionally
* need to skip the video initialization.
*/
int __board_video_skip(void)
{
/* As default, don't skip test */
return 0;
}
int board_video_skip(void)
__attribute__ ((weak, alias("__board_video_skip")));
int drv_video_init(void)
{
int skip_dev_init;
struct stdio_dev console_dev;
/* Check if video initialization should be skipped */
if (board_video_skip())
return 0;
/* Init video chip - returns with framebuffer cleared */
skip_dev_init = (video_init() == -1);
#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
debug("KBD: Keyboard init ...\n");
skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1);
#endif
if (skip_dev_init)
return 0;
/* Init vga device */
memset(&console_dev, 0, sizeof(console_dev));
strcpy(console_dev.name, "vga");
console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */
console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
console_dev.putc = video_putc; /* 'putc' function */
console_dev.puts = video_puts; /* 'puts' function */
console_dev.tstc = NULL; /* 'tstc' function */
console_dev.getc = NULL; /* 'getc' function */
#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE)
/* Also init console device */
console_dev.flags |= DEV_FLAGS_INPUT;
console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */
console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */
#endif /* CONFIG_VGA_AS_SINGLE_DEVICE */
if (stdio_register(&console_dev) != 0)
return 0;
/* Return success */
return 1;
}
|
1001-study-uboot
|
drivers/video/cfb_console.c
|
C
|
gpl3
| 44,912
|
/*
* Driver for AMBA PrimeCell CLCD
*
* Copyright (C) 2009 Alessandro Rubini
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <lcd.h>
#include <amba_clcd.h>
/* These variables are required by lcd.c -- although it sets them by itself */
int lcd_line_length;
int lcd_color_fg;
int lcd_color_bg;
void *lcd_base;
void *lcd_console_address;
short console_col;
short console_row;
/*
* To use this driver you need to provide the following in board files:
* a panel_info definition
* an lcd_enable function (can't define a weak default with current code)
*/
/* There is nothing to do with color registers, we use true color */
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
{
return;
}
/* Low level initialization of the logic cell: depends on panel_info */
void lcd_ctrl_init(void *lcdbase)
{
struct clcd_config *config;
struct clcd_registers *regs;
u32 cntl;
config = panel_info.priv;
regs = config->address;
cntl = config->cntl & ~CNTL_LCDEN;
/* Lazily, just copy the registers over: first control with disable */
writel(cntl, ®s->cntl);
writel(config->tim0, ®s->tim0);
writel(config->tim1, ®s->tim1);
writel(config->tim2, ®s->tim2);
writel(config->tim3, ®s->tim3);
writel((u32)lcdbase, ®s->ubas);
/* finally, enable */
writel(cntl | CNTL_LCDEN, ®s->cntl);
}
/* This is trivial, and copied from atmel_lcdfb.c */
ulong calc_fbsize(void)
{
return ((panel_info.vl_col * panel_info.vl_row *
NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
}
|
1001-study-uboot
|
drivers/video/amba.c
|
C
|
gpl3
| 2,309
|
/*
* Driver for AT91/AT32 LCD Controller
*
* Copyright (C) 2007 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
#include <atmel_lcdc.h>
int lcd_line_length;
int lcd_color_fg;
int lcd_color_bg;
void *lcd_base; /* Start of framebuffer memory */
void *lcd_console_address; /* Start of console buffer */
short console_col;
short console_row;
/* configurable parameters */
#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
#define ATMEL_LCDC_DMA_BURST_LEN 8
#ifndef ATMEL_LCDC_GUARD_TIME
#define ATMEL_LCDC_GUARD_TIME 1
#endif
#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9)
#define ATMEL_LCDC_FIFO_SIZE 2048
#else
#define ATMEL_LCDC_FIFO_SIZE 512
#endif
#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
{
#if defined(CONFIG_ATMEL_LCD_BGR555)
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
(red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
#else
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
(blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
#endif
}
void lcd_ctrl_init(void *lcdbase)
{
unsigned long value;
/* Turn off the LCD controller and the DMA controller */
lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
/* Wait for the LCDC core to become idle */
while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
udelay(10);
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
/* Reset LCDC DMA */
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
/* ...set frame size and burst length = 8 words (?) */
value = (panel_info.vl_col * panel_info.vl_row *
NBITS(panel_info.vl_bpix)) / 32;
value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
/* Set pixel clock */
value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
value++;
value = (value / 2) - 1;
if (!value) {
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
} else
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
value << ATMEL_LCDC_CLKVAL_OFFSET);
/* Initialize control register 2 */
#ifdef CONFIG_AVR32
value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
#else
value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
#endif
if (panel_info.vl_tft)
value |= ATMEL_LCDC_DISTYPE_TFT;
value |= panel_info.vl_sync;
value |= (panel_info.vl_bpix << 5);
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
/* Vertical timing */
value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
value |= panel_info.vl_lower_margin;
lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
/* Horizontal timing */
value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
value |= (panel_info.vl_left_margin - 1);
lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
/* Display size */
value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
value |= panel_info.vl_row - 1;
lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
/* FIFO Threshold: Use formula from data sheet */
value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
/* Toggle LCD_MODE every frame */
lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
/* Disable all interrupts */
lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
/* Set contrast */
value = ATMEL_LCDC_PS_DIV8 |
ATMEL_LCDC_ENA_PWMENABLE;
if (!panel_info.vl_cont_pol_low)
value |= ATMEL_LCDC_POL_POSITIVE;
lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
/* Set framebuffer DMA base address and pixel offset */
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
(ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
}
ulong calc_fbsize(void)
{
return ((panel_info.vl_col * panel_info.vl_row *
NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
}
|
1001-study-uboot
|
drivers/video/atmel_lcdfb.c
|
C
|
gpl3
| 5,323
|
/*
* Porting to u-boot:
*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* Linux IPU driver for MX51:
*
* (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IPU_REGS_INCLUDED__
#define __IPU_REGS_INCLUDED__
#define IPU_DISP0_BASE 0x00000000
#define IPU_MCU_T_DEFAULT 8
#define IPU_DISP1_BASE (IPU_MCU_T_DEFAULT << 25)
#define IPU_CM_REG_BASE 0x1E000000
#define IPU_STAT_REG_BASE 0x1E000200
#define IPU_IDMAC_REG_BASE 0x1E008000
#define IPU_ISP_REG_BASE 0x1E010000
#define IPU_DP_REG_BASE 0x1E018000
#define IPU_IC_REG_BASE 0x1E020000
#define IPU_IRT_REG_BASE 0x1E028000
#define IPU_CSI0_REG_BASE 0x1E030000
#define IPU_CSI1_REG_BASE 0x1E038000
#define IPU_DI0_REG_BASE 0x1E040000
#define IPU_DI1_REG_BASE 0x1E048000
#define IPU_SMFC_REG_BASE 0x1E050000
#define IPU_DC_REG_BASE 0x1E058000
#define IPU_DMFC_REG_BASE 0x1E060000
#define IPU_CPMEM_REG_BASE 0x1F000000
#define IPU_LUT_REG_BASE 0x1F020000
#define IPU_SRM_REG_BASE 0x1F040000
#define IPU_TPM_REG_BASE 0x1F060000
#define IPU_DC_TMPL_REG_BASE 0x1F080000
#define IPU_ISP_TBPR_REG_BASE 0x1F0C0000
#define IPU_VDI_REG_BASE 0x1E068000
extern u32 *ipu_dc_tmpl_reg;
#define DC_EVT_NF 0
#define DC_EVT_NL 1
#define DC_EVT_EOF 2
#define DC_EVT_NFIELD 3
#define DC_EVT_EOL 4
#define DC_EVT_EOFIELD 5
#define DC_EVT_NEW_ADDR 6
#define DC_EVT_NEW_CHAN 7
#define DC_EVT_NEW_DATA 8
#define DC_EVT_NEW_ADDR_W_0 0
#define DC_EVT_NEW_ADDR_W_1 1
#define DC_EVT_NEW_CHAN_W_0 2
#define DC_EVT_NEW_CHAN_W_1 3
#define DC_EVT_NEW_DATA_W_0 4
#define DC_EVT_NEW_DATA_W_1 5
#define DC_EVT_NEW_ADDR_R_0 6
#define DC_EVT_NEW_ADDR_R_1 7
#define DC_EVT_NEW_CHAN_R_0 8
#define DC_EVT_NEW_CHAN_R_1 9
#define DC_EVT_NEW_DATA_R_0 10
#define DC_EVT_NEW_DATA_R_1 11
/* Software reset for ipu */
#define SW_IPU_RST 8
enum {
IPU_CONF_DP_EN = 0x00000020,
IPU_CONF_DI0_EN = 0x00000040,
IPU_CONF_DI1_EN = 0x00000080,
IPU_CONF_DMFC_EN = 0x00000400,
IPU_CONF_DC_EN = 0x00000200,
DI0_COUNTER_RELEASE = 0x01000000,
DI1_COUNTER_RELEASE = 0x02000000,
DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
DI_GEN_DI_CLK_EXT = 0x100000,
DI_GEN_POLARITY_1 = 0x00000001,
DI_GEN_POLARITY_2 = 0x00000002,
DI_GEN_POLARITY_3 = 0x00000004,
DI_GEN_POLARITY_4 = 0x00000008,
DI_GEN_POLARITY_5 = 0x00000010,
DI_GEN_POLARITY_6 = 0x00000020,
DI_GEN_POLARITY_7 = 0x00000040,
DI_GEN_POLARITY_8 = 0x00000080,
DI_GEN_POL_CLK = 0x20000,
DI_POL_DRDY_DATA_POLARITY = 0x00000080,
DI_POL_DRDY_POLARITY_15 = 0x00000010,
DI_VSYNC_SEL_OFFSET = 13,
DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
DP_COM_CONF_FG_EN = 0x00000001,
DP_COM_CONF_GWSEL = 0x00000002,
DP_COM_CONF_GWAM = 0x00000004,
DP_COM_CONF_GWCKE = 0x00000008,
DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
DP_COM_CONF_CSC_DEF_OFFSET = 8,
DP_COM_CONF_CSC_DEF_FG = 0x00000300,
DP_COM_CONF_CSC_DEF_BG = 0x00000200,
DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
DP_COM_CONF_GAMMA_EN = 0x00001000,
DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
};
enum di_pins {
DI_PIN11 = 0,
DI_PIN12 = 1,
DI_PIN13 = 2,
DI_PIN14 = 3,
DI_PIN15 = 4,
DI_PIN16 = 5,
DI_PIN17 = 6,
DI_PIN_CS = 7,
DI_PIN_SER_CLK = 0,
DI_PIN_SER_RS = 1,
};
enum di_sync_wave {
DI_SYNC_NONE = -1,
DI_SYNC_CLK = 0,
DI_SYNC_INT_HSYNC = 1,
DI_SYNC_HSYNC = 2,
DI_SYNC_VSYNC = 3,
DI_SYNC_DE = 5,
};
struct ipu_cm {
u32 conf;
u32 sisg_ctrl0;
u32 sisg_ctrl1;
u32 sisg_set[6];
u32 sisg_clear[6];
u32 int_ctrl[15];
u32 sdma_event[10];
u32 srm_pri1;
u32 srm_pri2;
u32 fs_proc_flow[3];
u32 fs_disp_flow[2];
u32 skip;
u32 disp_alt_conf;
u32 disp_gen;
u32 disp_alt[4];
u32 snoop;
u32 mem_rst;
u32 pm;
u32 gpr;
u32 reserved0[26];
u32 ch_db_mode_sel[2];
u32 reserved1[16];
u32 alt_ch_db_mode_sel[2];
u32 reserved2[2];
u32 ch_trb_mode_sel[2];
};
struct ipu_idmac {
u32 conf;
u32 ch_en[2];
u32 sep_alpha;
u32 alt_sep_alpha;
u32 ch_pri[2];
u32 wm_en[2];
u32 lock_en[2];
u32 sub_addr[5];
u32 bndm_en[2];
u32 sc_cord[2];
u32 reserved[45];
u32 ch_busy[2];
};
struct ipu_com_async {
u32 com_conf_async;
u32 graph_wind_ctrl_async;
u32 fg_pos_async;
u32 cur_pos_async;
u32 cur_map_async;
u32 gamma_c_async[8];
u32 gamma_s_async[4];
u32 dp_csca_async[4];
u32 dp_csc_async[2];
};
struct ipu_dp {
u32 com_conf_sync;
u32 graph_wind_ctrl_sync;
u32 fg_pos_sync;
u32 cur_pos_sync;
u32 cur_map_sync;
u32 gamma_c_sync[8];
u32 gamma_s_sync[4];
u32 csca_sync[4];
u32 csc_sync[2];
u32 cur_pos_alt;
struct ipu_com_async async[2];
};
struct ipu_di {
u32 general;
u32 bs_clkgen0;
u32 bs_clkgen1;
u32 sw_gen0[9];
u32 sw_gen1[9];
u32 sync_as;
u32 dw_gen[12];
u32 dw_set[48];
u32 stp_rep[4];
u32 stp_rep9;
u32 ser_conf;
u32 ssc;
u32 pol;
u32 aw0;
u32 aw1;
u32 scr_conf;
u32 stat;
};
struct ipu_stat {
u32 int_stat[15];
u32 cur_buf[2];
u32 alt_cur_buf_0;
u32 alt_cur_buf_1;
u32 srm_stat;
u32 proc_task_stat;
u32 disp_task_stat;
u32 triple_cur_buf[4];
u32 ch_buf0_rdy[2];
u32 ch_buf1_rdy[2];
u32 alt_ch_buf0_rdy[2];
u32 alt_ch_buf1_rdy[2];
u32 ch_buf2_rdy[2];
};
struct ipu_dc_ch {
u32 wr_ch_conf;
u32 wr_ch_addr;
u32 rl[5];
};
struct ipu_dc {
struct ipu_dc_ch dc_ch0_1_2[3];
u32 cmd_ch_conf_3;
u32 cmd_ch_conf_4;
struct ipu_dc_ch dc_ch5_6[2];
struct ipu_dc_ch dc_ch8;
u32 rl6_ch_8;
struct ipu_dc_ch dc_ch9;
u32 rl6_ch_9;
u32 gen;
u32 disp_conf1[4];
u32 disp_conf2[4];
u32 di0_conf[2];
u32 di1_conf[2];
u32 dc_map_ptr[15];
u32 dc_map_val[12];
u32 udge[16];
u32 lla[2];
u32 r_lla[2];
u32 wr_ch_addr_5_alt;
u32 stat;
};
struct ipu_dmfc {
u32 rd_chan;
u32 wr_chan;
u32 wr_chan_def;
u32 dp_chan;
u32 dp_chan_def;
u32 general[2];
u32 ic_ctrl;
u32 wr_chan_alt;
u32 wr_chan_def_alt;
u32 general1_alt;
u32 stat;
};
#define IPU_CM_REG ((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
IPU_CM_REG_BASE))
#define IPU_CONF (&IPU_CM_REG->conf)
#define IPU_SRM_PRI1 (&IPU_CM_REG->srm_pri1)
#define IPU_SRM_PRI2 (&IPU_CM_REG->srm_pri2)
#define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])
#define IPU_FS_PROC_FLOW2 (&IPU_CM_REG->fs_proc_flow[1])
#define IPU_FS_PROC_FLOW3 (&IPU_CM_REG->fs_proc_flow[2])
#define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
#define IPU_DISP_GEN (&IPU_CM_REG->disp_gen)
#define IPU_MEM_RST (&IPU_CM_REG->mem_rst)
#define IPU_GPR (&IPU_CM_REG->gpr)
#define IPU_CHA_DB_MODE_SEL(ch) (&IPU_CM_REG->ch_db_mode_sel[ch / 32])
#define IPU_STAT ((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
IPU_STAT_REG_BASE))
#define IPU_CHA_CUR_BUF(ch) (&IPU_STAT->cur_buf[ch / 32])
#define IPU_CHA_BUF0_RDY(ch) (&IPU_STAT->ch_buf0_rdy[ch / 32])
#define IPU_CHA_BUF1_RDY(ch) (&IPU_STAT->ch_buf1_rdy[ch / 32])
#define IPU_INT_CTRL(n) (&IPU_CM_REG->int_ctrl[(n) - 1])
#define IDMAC_REG ((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
IPU_IDMAC_REG_BASE))
#define IDMAC_CONF (&IDMAC_REG->conf)
#define IDMAC_CHA_EN(ch) (&IDMAC_REG->ch_en[ch / 32])
#define IDMAC_CHA_PRI(ch) (&IDMAC_REG->ch_pri[ch / 32])
#define DI_REG(di) ((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
((di == 1) ? IPU_DI1_REG_BASE : \
IPU_DI0_REG_BASE)))
#define DI_GENERAL(di) (&DI_REG(di)->general)
#define DI_BS_CLKGEN0(di) (&DI_REG(di)->bs_clkgen0)
#define DI_BS_CLKGEN1(di) (&DI_REG(di)->bs_clkgen1)
#define DI_SW_GEN0(di, gen) (&DI_REG(di)->sw_gen0[gen - 1])
#define DI_SW_GEN1(di, gen) (&DI_REG(di)->sw_gen1[gen - 1])
#define DI_STP_REP(di, gen) (&DI_REG(di)->stp_rep[(gen - 1) / 2])
#define DI_SYNC_AS_GEN(di) (&DI_REG(di)->sync_as)
#define DI_DW_GEN(di, gen) (&DI_REG(di)->dw_gen[gen])
#define DI_DW_SET(di, gen, set) (&DI_REG(di)->dw_set[gen + 12 * set])
#define DI_POL(di) (&DI_REG(di)->pol)
#define DI_SCR_CONF(di) (&DI_REG(di)->scr_conf)
#define DMFC_REG ((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
IPU_DMFC_REG_BASE))
#define DMFC_WR_CHAN (&DMFC_REG->wr_chan)
#define DMFC_WR_CHAN_DEF (&DMFC_REG->wr_chan_def)
#define DMFC_DP_CHAN (&DMFC_REG->dp_chan)
#define DMFC_DP_CHAN_DEF (&DMFC_REG->dp_chan_def)
#define DMFC_GENERAL1 (&DMFC_REG->general[0])
#define DMFC_IC_CTRL (&DMFC_REG->ic_ctrl)
#define DC_REG ((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
IPU_DC_REG_BASE))
#define DC_MAP_CONF_PTR(n) (&DC_REG->dc_map_ptr[n / 2])
#define DC_MAP_CONF_VAL(n) (&DC_REG->dc_map_val[n / 2])
static inline struct ipu_dc_ch *dc_ch_offset(int ch)
{
switch (ch) {
case 0:
case 1:
case 2:
return &DC_REG->dc_ch0_1_2[ch];
case 5:
case 6:
return &DC_REG->dc_ch5_6[ch - 5];
case 8:
return &DC_REG->dc_ch8;
case 9:
return &DC_REG->dc_ch9;
default:
printf("%s: invalid channel %d\n", __func__, ch);
return NULL;
}
}
#define DC_RL_CH(ch, evt) (&dc_ch_offset(ch)->rl[evt / 2])
#define DC_WR_CH_CONF(ch) (&dc_ch_offset(ch)->wr_ch_conf)
#define DC_WR_CH_ADDR(ch) (&dc_ch_offset(ch)->wr_ch_addr)
#define DC_WR_CH_CONF_1 DC_WR_CH_CONF(1)
#define DC_WR_CH_CONF_5 DC_WR_CH_CONF(5)
#define DC_GEN (&DC_REG->gen)
#define DC_DISP_CONF2(disp) (&DC_REG->disp_conf2[disp])
#define DC_STAT (&DC_REG->stat)
#define DP_SYNC 0
#define DP_ASYNC0 0x60
#define DP_ASYNC1 0xBC
#define DP_REG ((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
IPU_DP_REG_BASE))
#define DP_COM_CONF() (&DP_REG->com_conf_sync)
#define DP_GRAPH_WIND_CTRL() (&DP_REG->graph_wind_ctrl_sync)
#define DP_CSC_A_0() (&DP_REG->csca_sync[0])
#define DP_CSC_A_1() (&DP_REG->csca_sync[1])
#define DP_CSC_A_2() (&DP_REG->csca_sync[2])
#define DP_CSC_A_3() (&DP_REG->csca_sync[3])
#define DP_CSC_0() (&DP_REG->csc_sync[0])
#define DP_CSC_1() (&DP_REG->csc_sync[1])
/* DC template opcodes */
#define WROD(lf) (0x18 | (lf << 1))
#endif
|
1001-study-uboot
|
drivers/video/ipu_regs.h
|
C
|
gpl3
| 10,545
|
/*
* (C) Copyright 2004
* Pierre Aubert, Staubli Faverges , <p.aubert@staubli.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef CONFIG_SYS_DEFAULT_VIDEO_MODE
#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x301
#endif
/* Some mode definitions */
#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
#define FB_SYNC_EXT 4 /* external sync */
#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
/* vtotal = 144d/288n/576i => PAL */
/* vtotal = 121d/242n/484i => NTSC */
#define FB_SYNC_ON_GREEN 32 /* sync on green */
#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
#define FB_VMODE_INTERLACED 1 /* interlaced */
#define FB_VMODE_DOUBLE 2 /* double scan */
#define FB_VMODE_MASK 255
#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
/******************************************************************
* Resolution Struct
******************************************************************/
struct ctfb_res_modes {
int xres; /* visible resolution */
int yres;
/* Timing: All values in pixclocks, except pixclock (of course) */
int pixclock; /* pixel clock in ps (pico seconds) */
int left_margin; /* time from sync to picture */
int right_margin; /* time from picture to sync */
int upper_margin; /* time from sync to picture */
int lower_margin;
int hsync_len; /* length of horizontal sync */
int vsync_len; /* length of vertical sync */
int sync; /* see FB_SYNC_* */
int vmode; /* see FB_VMODE_* */
};
/******************************************************************
* Vesa Mode Struct
******************************************************************/
struct ctfb_vesa_modes {
int vesanr; /* Vesa number as in LILO (VESA Nr + 0x200} */
int resindex; /* index to resolution struct */
int bits_per_pixel; /* bpp */
};
#define RES_MODE_640x480 0
#define RES_MODE_800x600 1
#define RES_MODE_1024x768 2
#define RES_MODE_960_720 3
#define RES_MODE_1152x864 4
#define RES_MODE_1280x1024 5
#define RES_MODES_COUNT 6
#define VESA_MODES_COUNT 19
extern const struct ctfb_vesa_modes vesa_modes[];
extern const struct ctfb_res_modes res_mode_init[];
int video_get_params (struct ctfb_res_modes *pPar, char *penv);
int video_get_video_mode(unsigned int *xres, unsigned int *yres,
unsigned int *depth, unsigned int *freq, const char **options);
|
1001-study-uboot
|
drivers/video/videomodes.h
|
C
|
gpl3
| 3,349
|
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libvideo.o
COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
COBJS-$(CONFIG_SED156X) += sed156x.o
COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o videomodes.o
COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/video/Makefile
|
Makefile
|
gpl3
| 2,226
|
/*
* Porting to u-boot:
*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* Linux IPU driver for MX51:
*
* (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_IPU_H__
#define __ASM_ARCH_IPU_H__
#include <linux/types.h>
#include <ipu_pixfmt.h>
#define IDMA_CHAN_INVALID 0xFF
#define HIGH_RESOLUTION_WIDTH 1024
struct clk {
const char *name;
int id;
/* Source clock this clk depends on */
struct clk *parent;
/* Secondary clock to enable/disable with this clock */
struct clk *secondary;
/* Current clock rate */
unsigned long rate;
/* Reference count of clock enable/disable */
__s8 usecount;
/* Register bit position for clock's enable/disable control. */
u8 enable_shift;
/* Register address for clock's enable/disable control. */
void *enable_reg;
u32 flags;
/*
* Function ptr to recalculate the clock's rate based on parent
* clock's rate
*/
void (*recalc) (struct clk *);
/*
* Function ptr to set the clock to a new rate. The rate must match a
* supported rate returned from round_rate. Leave blank if clock is not
* programmable
*/
int (*set_rate) (struct clk *, unsigned long);
/*
* Function ptr to round the requested clock rate to the nearest
* supported rate that is less than or equal to the requested rate.
*/
unsigned long (*round_rate) (struct clk *, unsigned long);
/*
* Function ptr to enable the clock. Leave blank if clock can not
* be gated.
*/
int (*enable) (struct clk *);
/*
* Function ptr to disable the clock. Leave blank if clock can not
* be gated.
*/
void (*disable) (struct clk *);
/* Function ptr to set the parent clock of the clock. */
int (*set_parent) (struct clk *, struct clk *);
};
/*
* Enumeration of Synchronous (Memory-less) panel types
*/
typedef enum {
IPU_PANEL_SHARP_TFT,
IPU_PANEL_TFT,
} ipu_panel_t;
/*
* IPU Driver channels definitions.
* Note these are different from IDMA channels
*/
#define IPU_MAX_CH 32
#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
#define IPU_CHAN_ID(ch) (ch >> 24)
#define IPU_CHAN_ALT(ch) (ch & 0x02000000)
#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
#define NO_DMA 0x3F
#define ALT 1
/*
* Enumeration of IPU logical channels. An IPU logical channel is defined as a
* combination of an input (memory to IPU), output (IPU to memory), and/or
* secondary input IDMA channels and in some cases an Image Converter task.
* Some channels consist of only an input or output.
*/
typedef enum {
CHAN_NONE = -1,
MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
} ipu_channel_t;
/*
* Enumeration of types of buffers for a logical channel.
*/
typedef enum {
IPU_OUTPUT_BUFFER = 0, /*< Buffer for output from IPU */
IPU_ALPHA_IN_BUFFER = 1, /*< Buffer for input to IPU */
IPU_GRAPH_IN_BUFFER = 2, /*< Buffer for input to IPU */
IPU_VIDEO_IN_BUFFER = 3, /*< Buffer for input to IPU */
IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
} ipu_buffer_t;
#define IPU_PANEL_SERIAL 1
#define IPU_PANEL_PARALLEL 2
struct ipu_channel {
u8 video_in_dma;
u8 alpha_in_dma;
u8 graph_in_dma;
u8 out_dma;
};
enum ipu_dmfc_type {
DMFC_NORMAL = 0,
DMFC_HIGH_RESOLUTION_DC,
DMFC_HIGH_RESOLUTION_DP,
DMFC_HIGH_RESOLUTION_ONLY_DP,
};
/*
* Union of initialization parameters for a logical channel.
*/
typedef union {
struct {
uint32_t di;
unsigned char interlaced;
} mem_dc_sync;
struct {
uint32_t temp;
} mem_sdc_fg;
struct {
uint32_t di;
unsigned char interlaced;
uint32_t in_pixel_fmt;
uint32_t out_pixel_fmt;
unsigned char alpha_chan_en;
} mem_dp_bg_sync;
struct {
uint32_t temp;
} mem_sdc_bg;
struct {
uint32_t di;
unsigned char interlaced;
uint32_t in_pixel_fmt;
uint32_t out_pixel_fmt;
unsigned char alpha_chan_en;
} mem_dp_fg_sync;
} ipu_channel_params_t;
/*
* Bitfield of Display Interface signal polarities.
*/
typedef struct {
unsigned datamask_en:1;
unsigned ext_clk:1;
unsigned interlaced:1;
unsigned odd_field_first:1;
unsigned clksel_en:1;
unsigned clkidle_en:1;
unsigned data_pol:1; /* true = inverted */
unsigned clk_pol:1; /* true = rising edge */
unsigned enable_pol:1;
unsigned Hsync_pol:1; /* true = active high */
unsigned Vsync_pol:1;
} ipu_di_signal_cfg_t;
typedef enum {
RGB,
YCbCr,
YUV
} ipu_color_space_t;
/* Common IPU API */
int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params);
void ipu_uninit_channel(ipu_channel_t channel);
int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
uint32_t pixel_fmt,
uint16_t width, uint16_t height,
uint32_t stride,
dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
uint32_t u_offset, uint32_t v_offset);
int32_t ipu_update_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
uint32_t bufNum, dma_addr_t phyaddr);
int32_t ipu_is_channel_busy(ipu_channel_t channel);
void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
uint32_t bufNum);
int32_t ipu_enable_channel(ipu_channel_t channel);
int32_t ipu_disable_channel(ipu_channel_t channel);
int32_t ipu_init_sync_panel(int disp,
uint32_t pixel_clk,
uint16_t width, uint16_t height,
uint32_t pixel_fmt,
uint16_t h_start_width, uint16_t h_sync_width,
uint16_t h_end_width, uint16_t v_start_width,
uint16_t v_sync_width, uint16_t v_end_width,
uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
uint8_t alpha);
int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
uint32_t colorKey);
uint32_t bytes_per_pixel(uint32_t fmt);
void clk_enable(struct clk *clk);
void clk_disable(struct clk *clk);
u32 clk_get_rate(struct clk *clk);
int clk_set_rate(struct clk *clk, unsigned long rate);
long clk_round_rate(struct clk *clk, unsigned long rate);
int clk_set_parent(struct clk *clk, struct clk *parent);
int clk_get_usecount(struct clk *clk);
struct clk *clk_get_parent(struct clk *clk);
void ipu_dump_registers(void);
int ipu_probe(void);
void ipu_dmfc_init(int dmfc_type, int first);
void ipu_init_dc_mappings(void);
void ipu_dmfc_set_wait4eot(int dma_chan, int width);
void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
void ipu_dc_uninit(int dc_chan);
void ipu_dp_dc_enable(ipu_channel_t channel);
int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
uint32_t out_pixel_fmt);
void ipu_dp_uninit(ipu_channel_t channel);
void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
ipu_color_space_t format_to_colorspace(uint32_t fmt);
#endif
|
1001-study-uboot
|
drivers/video/ipu.h
|
C
|
gpl3
| 8,286
|
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* Referred to Linux Kernel DSS driver files for OMAP3 by
* Tomi Valkeinen from drivers/video/omap2/dss/
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 and any
* later version the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/dss.h>
/*
* Configure VENC for a given Mode (NTSC / PAL)
*/
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
u32 height, u32 width)
{
struct venc_regs *venc = (struct venc_regs *) OMAP3_VENC_BASE;
struct dss_regs *dss = (struct dss_regs *) OMAP3_DSS_BASE;
struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
writel(venc_cfg->status, &venc->status);
writel(venc_cfg->f_control, &venc->f_control);
writel(venc_cfg->vidout_ctrl, &venc->vidout_ctrl);
writel(venc_cfg->sync_ctrl, &venc->sync_ctrl);
writel(venc_cfg->llen, &venc->llen);
writel(venc_cfg->flens, &venc->flens);
writel(venc_cfg->hfltr_ctrl, &venc->hfltr_ctrl);
writel(venc_cfg->cc_carr_wss_carr, &venc->cc_carr_wss_carr);
writel(venc_cfg->c_phase, &venc->c_phase);
writel(venc_cfg->gain_u, &venc->gain_u);
writel(venc_cfg->gain_v, &venc->gain_v);
writel(venc_cfg->gain_y, &venc->gain_y);
writel(venc_cfg->black_level, &venc->black_level);
writel(venc_cfg->blank_level, &venc->blank_level);
writel(venc_cfg->x_color, &venc->x_color);
writel(venc_cfg->m_control, &venc->m_control);
writel(venc_cfg->bstamp_wss_data, &venc->bstamp_wss_data);
writel(venc_cfg->s_carr, &venc->s_carr);
writel(venc_cfg->line21, &venc->line21);
writel(venc_cfg->ln_sel, &venc->ln_sel);
writel(venc_cfg->l21__wc_ctl, &venc->l21__wc_ctl);
writel(venc_cfg->htrigger_vtrigger, &venc->htrigger_vtrigger);
writel(venc_cfg->savid__eavid, &venc->savid__eavid);
writel(venc_cfg->flen__fal, &venc->flen__fal);
writel(venc_cfg->lal__phase_reset, &venc->lal__phase_reset);
writel(venc_cfg->hs_int_start_stop_x,
&venc->hs_int_start_stop_x);
writel(venc_cfg->hs_ext_start_stop_x,
&venc->hs_ext_start_stop_x);
writel(venc_cfg->vs_int_start_x, &venc->vs_int_start_x);
writel(venc_cfg->vs_int_stop_x__vs_int_start_y,
&venc->vs_int_stop_x__vs_int_start_y);
writel(venc_cfg->vs_int_stop_y__vs_ext_start_x,
&venc->vs_int_stop_y__vs_ext_start_x);
writel(venc_cfg->vs_ext_stop_x__vs_ext_start_y,
&venc->vs_ext_stop_x__vs_ext_start_y);
writel(venc_cfg->vs_ext_stop_y, &venc->vs_ext_stop_y);
writel(venc_cfg->avid_start_stop_x, &venc->avid_start_stop_x);
writel(venc_cfg->avid_start_stop_y, &venc->avid_start_stop_y);
writel(venc_cfg->fid_int_start_x__fid_int_start_y,
&venc->fid_int_start_x__fid_int_start_y);
writel(venc_cfg->fid_int_offset_y__fid_ext_start_x,
&venc->fid_int_offset_y__fid_ext_start_x);
writel(venc_cfg->fid_ext_start_y__fid_ext_offset_y,
&venc->fid_ext_start_y__fid_ext_offset_y);
writel(venc_cfg->tvdetgp_int_start_stop_x,
&venc->tvdetgp_int_start_stop_x);
writel(venc_cfg->tvdetgp_int_start_stop_y,
&venc->tvdetgp_int_start_stop_y);
writel(venc_cfg->gen_ctrl, &venc->gen_ctrl);
writel(venc_cfg->output_control, &venc->output_control);
writel(venc_cfg->dac_b__dac_c, &venc->dac_b__dac_c);
/* Configure DSS for VENC Settings */
writel(VENC_DSS_CONFIG, &dss->control);
/* Configure height and width for Digital out */
writel(((height << DIG_LPP_SHIFT) | width), &dispc->size_dig);
}
/*
* Configure Panel Specific Parameters
*/
void omap3_dss_panel_config(const struct panel_config *panel_cfg)
{
struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
writel(panel_cfg->timing_h, &dispc->timing_h);
writel(panel_cfg->timing_v, &dispc->timing_v);
writel(panel_cfg->pol_freq, &dispc->pol_freq);
writel(panel_cfg->divisor, &dispc->divisor);
writel(panel_cfg->lcd_size, &dispc->size_lcd);
writel((panel_cfg->load_mode << FRAME_MODE_SHIFT), &dispc->config);
writel(((panel_cfg->panel_type << TFTSTN_SHIFT) |
(panel_cfg->data_lines << DATALINES_SHIFT)), &dispc->control);
writel(panel_cfg->panel_color, &dispc->default_color0);
}
/*
* Enable LCD and DIGITAL OUT in DSS
*/
void omap3_dss_enable(void)
{
struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
u32 l = 0;
l = readl(&dispc->control);
l |= DISPC_ENABLE;
writel(l, &dispc->control);
}
|
1001-study-uboot
|
drivers/video/omap3_dss.c
|
C
|
gpl3
| 4,979
|
/*
* (C) Copyright 2005-2009
* Jens Scharsig @ BuS Elektronik GmbH & Co. KG, <esw@bus-elektronik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <bmp_layout.h>
#include <asm/io.h>
vu_char *vcxk_bws = ((vu_char *) (CONFIG_SYS_VCXK_BASE));
vu_short *vcxk_bws_word = ((vu_short *)(CONFIG_SYS_VCXK_BASE));
vu_long *vcxk_bws_long = ((vu_long *) (CONFIG_SYS_VCXK_BASE));
#ifdef CONFIG_AT91RM9200
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#ifndef VCBITMASK
#define VCBITMASK(bitno) (0x0001 << (bitno % 16))
#endif
#ifndef CONFIG_AT91_LEGACY
at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
do { \
writel(PIN, &pio->PORT.per); \
writel(PIN, &pio->PORT.DDR); \
writel(PIN, &pio->PORT.mddr); \
if (!I0O1) \
writel(PIN, &pio->PORT.puer); \
} while (0);
#define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr);
#define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr);
#define VCXK_ACKNOWLEDGE \
(!(readl(&pio->CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT.pdsr) & \
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
#else
#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
((AT91PS_PIO) PORT)->PIO_PER = PIN; \
((AT91PS_PIO) PORT)->DDR = PIN; \
((AT91PS_PIO) PORT)->PIO_MDDR = PIN; \
if (!I0O1) ((AT91PS_PIO) PORT)->PIO_PPUER = PIN;
#define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN;
#define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN;
#define VCXK_ACKNOWLEDGE \
(!(((AT91PS_PIO) CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT)->\
PIO_PDSR & CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
#endif
#elif defined(CONFIG_MCF52x2)
#include <asm/m5282.h>
#ifndef VCBITMASK
#define VCBITMASK(bitno) (0x8000 >> (bitno % 16))
#endif
#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
if (I0O1) DDR |= PIN; else DDR &= ~PIN;
#define VCXK_SET_PIN(PORT, PIN) PORT |= PIN;
#define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN;
#define VCXK_ACKNOWLEDGE \
(!(CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT & \
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
#else
#error no vcxk support for selected ARCH
#endif
#define VCXK_DISABLE\
VCXK_SET_PIN(CONFIG_SYS_VCXK_ENABLE_PORT, CONFIG_SYS_VCXK_ENABLE_PIN)
#define VCXK_ENABLE\
VCXK_CLR_PIN(CONFIG_SYS_VCXK_ENABLE_PORT, CONFIG_SYS_VCXK_ENABLE_PIN)
#ifndef CONFIG_SYS_VCXK_DOUBLEBUFFERED
#define VCXK_BWS(x, data) vcxk_bws[x] = data;
#define VCXK_BWS_WORD_SET(x, mask) vcxk_bws_word[x] |= mask;
#define VCXK_BWS_WORD_CLEAR(x, mask) vcxk_bws_word[x] &= ~mask;
#define VCXK_BWS_LONG(x, data) vcxk_bws_long[x] = data;
#else
u_char double_bws[16384];
u_short *double_bws_word;
u_long *double_bws_long;
#define VCXK_BWS(x,data) \
double_bws[x] = data; vcxk_bws[x] = data;
#define VCXK_BWS_WORD_SET(x,mask) \
double_bws_word[x] |= mask; \
vcxk_bws_word[x] = double_bws_word[x];
#define VCXK_BWS_WORD_CLEAR(x,mask) \
double_bws_word[x] &= ~mask; \
vcxk_bws_word[x] = double_bws_word[x];
#define VCXK_BWS_LONG(x,data) \
double_bws_long[x] = data; vcxk_bws_long[x] = data;
#endif
#define VC4K16_Bright1 vcxk_bws_word[0x20004 / 2]
#define VC4K16_Bright2 vcxk_bws_word[0x20006 / 2]
#define VC2K_Bright vcxk_bws[0x8000]
#define VC8K_BrightH vcxk_bws[0xC000]
#define VC8K_BrightL vcxk_bws[0xC001]
vu_char VC4K16;
u_long display_width;
u_long display_height;
u_long display_bwidth;
ulong search_vcxk_driver(void);
void vcxk_cls(void);
void vcxk_setbrightness(unsigned int side, short brightness);
int vcxk_request(void);
int vcxk_acknowledge_wait(void);
void vcxk_clear(void);
/*
****f* bus_vcxk/vcxk_init
* FUNCTION
* initialalize Video Controller
* PARAMETERS
* width visible display width in pixel
* height visible display height in pixel
***
*/
int vcxk_init(unsigned long width, unsigned long height)
{
#ifdef CONFIG_SYS_VCXK_RESET_PORT
VCXK_INIT_PIN(CONFIG_SYS_VCXK_RESET_PORT,
CONFIG_SYS_VCXK_RESET_PIN, CONFIG_SYS_VCXK_RESET_DDR, 1)
VCXK_SET_PIN(CONFIG_SYS_VCXK_RESET_PORT, CONFIG_SYS_VCXK_RESET_PIN);
#endif
#ifdef CONFIG_SYS_VCXK_DOUBLEBUFFERED
double_bws_word = (u_short *)double_bws;
double_bws_long = (u_long *)double_bws;
debug("%lx %lx %lx \n", double_bws, double_bws_word, double_bws_long);
#endif
display_width = width;
display_height = height;
#if (CONFIG_SYS_VCXK_DEFAULT_LINEALIGN == 4)
display_bwidth = ((width + 31) / 8) & ~0x3;
#elif (CONFIG_SYS_VCXK_DEFAULT_LINEALIGN == 2)
display_bwidth = ((width + 15) / 8) & ~0x1;
#else
#error CONFIG_SYS_VCXK_DEFAULT_LINEALIGN is invalid
#endif
debug("linesize ((%ld + 15) / 8 & ~0x1) = %ld\n",
display_width, display_bwidth);
#ifdef CONFIG_SYS_VCXK_AUTODETECT
VC4K16 = 0;
vcxk_bws_long[1] = 0x0;
vcxk_bws_long[1] = 0x55AAAA55;
vcxk_bws_long[5] = 0x0;
if (vcxk_bws_long[1] == 0x55AAAA55)
VC4K16 = 1;
#else
VC4K16 = 1;
debug("No autodetect: use vc4k\n");
#endif
VCXK_INIT_PIN(CONFIG_SYS_VCXK_INVERT_PORT,
CONFIG_SYS_VCXK_INVERT_PIN, CONFIG_SYS_VCXK_INVERT_DDR, 1)
VCXK_SET_PIN(CONFIG_SYS_VCXK_INVERT_PORT, CONFIG_SYS_VCXK_INVERT_PIN)
VCXK_SET_PIN(CONFIG_SYS_VCXK_REQUEST_PORT, CONFIG_SYS_VCXK_REQUEST_PIN);
VCXK_INIT_PIN(CONFIG_SYS_VCXK_REQUEST_PORT,
CONFIG_SYS_VCXK_REQUEST_PIN, CONFIG_SYS_VCXK_REQUEST_DDR, 1)
VCXK_INIT_PIN(CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT,
CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN,
CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR, 0)
VCXK_DISABLE;
VCXK_INIT_PIN(CONFIG_SYS_VCXK_ENABLE_PORT,
CONFIG_SYS_VCXK_ENABLE_PIN, CONFIG_SYS_VCXK_ENABLE_DDR, 1)
vcxk_cls();
vcxk_cls(); /* clear second/hidden page */
vcxk_setbrightness(3, 1000);
VCXK_ENABLE;
return 1;
}
/*
****f* bus_vcxk/vcxk_setpixel
* FUNCTION
* set the pixel[x,y] with the given color
* PARAMETER
* x pixel colum
* y pixel row
* color <0x40 off/black
* >0x40 on
***
*/
void vcxk_setpixel(int x, int y, unsigned long color)
{
vu_short dataptr;
if ((x < display_width) && (y < display_height)) {
dataptr = ((x / 16)) + (y * (display_bwidth >> 1));
color = ((color >> 16) & 0xFF) |
((color >> 8) & 0xFF) | (color & 0xFF);
if (color > 0x40) {
VCXK_BWS_WORD_SET(dataptr, VCBITMASK(x));
} else {
VCXK_BWS_WORD_CLEAR(dataptr, VCBITMASK(x));
}
}
}
/*
****f* bus_vcxk/vcxk_loadimage
* FUNCTION
* copies a binary image to display memory
***
*/
void vcxk_loadimage(ulong source)
{
int cnt;
vcxk_acknowledge_wait();
if (VC4K16) {
for (cnt = 0; cnt < (16384 / 4); cnt++) {
VCXK_BWS_LONG(cnt, (*(ulong *) source));
source = source + 4;
}
} else {
for (cnt = 0; cnt < 16384; cnt++) {
VCXK_BWS_LONG(cnt*2, (*(vu_char *) source));
source++;
}
}
vcxk_request();
}
/*
****f* bus_vcxk/vcxk_cls
* FUNCTION
* clear the display
***
*/
void vcxk_cls(void)
{
vcxk_acknowledge_wait();
vcxk_clear();
vcxk_request();
}
/*
****f* bus_vcxk/vcxk_clear(void)
* FUNCTION
* clear the display memory
***
*/
void vcxk_clear(void)
{
int cnt;
for (cnt = 0; cnt < (16384 / 4); cnt++) {
VCXK_BWS_LONG(cnt, 0)
}
}
/*
****f* bus_vcxk/vcxk_setbrightness
* FUNCTION
* set the display brightness
* PARAMETER
* side 1 set front side brightness
* 2 set back side brightness
* 3 set brightness for both sides
* brightness 0..1000
***
*/
void vcxk_setbrightness(unsigned int side, short brightness)
{
if (VC4K16) {
if ((side == 0) || (side & 0x1))
VC4K16_Bright1 = brightness + 23;
if ((side == 0) || (side & 0x2))
VC4K16_Bright2 = brightness + 23;
} else {
VC2K_Bright = (brightness >> 4) + 2;
VC8K_BrightH = (brightness + 23) >> 8;
VC8K_BrightL = (brightness + 23) & 0xFF;
}
}
/*
****f* bus_vcxk/vcxk_request
* FUNCTION
* requests viewing of display memory
***
*/
int vcxk_request(void)
{
VCXK_CLR_PIN(CONFIG_SYS_VCXK_REQUEST_PORT,
CONFIG_SYS_VCXK_REQUEST_PIN)
VCXK_SET_PIN(CONFIG_SYS_VCXK_REQUEST_PORT,
CONFIG_SYS_VCXK_REQUEST_PIN);
return 1;
}
/*
****f* bus_vcxk/vcxk_acknowledge_wait
* FUNCTION
* wait for acknowledge viewing requests
***
*/
int vcxk_acknowledge_wait(void)
{
while (VCXK_ACKNOWLEDGE)
;
return 1;
}
/*
****f* bus_vcxk/vcxk_draw_mono
* FUNCTION
* copies a monochrom bitmap (BMP-Format) from given memory
* PARAMETER
* dataptr pointer to bitmap
* x output bitmap @ columne
* y output bitmap @ row
***
*/
void vcxk_draw_mono(unsigned char *dataptr, unsigned long linewidth,
unsigned long cp_width, unsigned long cp_height)
{
unsigned char *lineptr;
unsigned long xcnt, ycnt;
for (ycnt = cp_height; ycnt > 0; ycnt--) {
lineptr = dataptr;
for (xcnt = 0; xcnt < cp_width; xcnt++) {
if ((*lineptr << (xcnt % 8)) & 0x80)
vcxk_setpixel(xcnt, ycnt - 1, 0xFFFFFF);
else
vcxk_setpixel(xcnt, ycnt-1, 0);
if ((xcnt % 8) == 7)
lineptr++;
} /* endfor xcnt */
dataptr = dataptr + linewidth;
} /* endfor ycnt */
}
/*
****f* bus_vcxk/vcxk_display_bitmap
* FUNCTION
* copies a bitmap (BMP-Format) to the given position
* PARAMETER
* addr pointer to bitmap
* x output bitmap @ columne
* y output bitmap @ row
***
*/
int vcxk_display_bitmap(ulong addr, int x, int y)
{
bmp_image_t *bmp;
unsigned long width;
unsigned long height;
unsigned long bpp;
unsigned long lw;
unsigned long c_width;
unsigned long c_height;
unsigned char *dataptr;
bmp = (bmp_image_t *) addr;
if ((bmp->header.signature[0] == 'B') &&
(bmp->header.signature[1] == 'M')) {
width = le32_to_cpu(bmp->header.width);
height = le32_to_cpu(bmp->header.height);
bpp = le16_to_cpu(bmp->header.bit_count);
dataptr = (unsigned char *) bmp +
le32_to_cpu(bmp->header.data_offset);
if (display_width < (width + x))
c_width = display_width - x;
else
c_width = width;
if (display_height < (height + y))
c_height = display_height - y;
else
c_height = height;
lw = (((width + 7) / 8) + 3) & ~0x3;
if (c_height < height)
dataptr = dataptr + lw * (height - c_height);
switch (bpp) {
case 1:
vcxk_draw_mono(dataptr, lw, c_width, c_height);
break;
default:
printf("Error: %ld bit per pixel "
"not supported by VCxK\n", bpp);
return 0;
}
} else {
printf("Error: no valid bmp at %lx\n", (ulong) bmp);
return 0;
}
return 1;
}
/*
****f* bus_vcxk/video_display_bitmap
***
*/
int video_display_bitmap(ulong addr, int x, int y)
{
vcxk_acknowledge_wait();
if (vcxk_display_bitmap(addr, x, y)) {
vcxk_request();
return 0;
}
return 1;
}
/* EOF */
|
1001-study-uboot
|
drivers/video/bus_vcxk.c
|
C
|
gpl3
| 11,089
|
/*
* Porting to u-boot:
*
* (C) Copyright 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2008-2009 MontaVista Software Inc.
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* Based on the LCD driver for TI Avalanche processors written by
* Ajay Singh and Shalom Hai.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option)any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <video_fb.h>
#include <linux/list.h>
#include <linux/fb.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include "videomodes.h"
#include <asm/arch/da8xx-fb.h>
#define DRIVER_NAME "da8xx_lcdc"
/* LCD Status Register */
#define LCD_END_OF_FRAME1 (1 << 9)
#define LCD_END_OF_FRAME0 (1 << 8)
#define LCD_PL_LOAD_DONE (1 << 6)
#define LCD_FIFO_UNDERFLOW (1 << 5)
#define LCD_SYNC_LOST (1 << 2)
/* LCD DMA Control Register */
#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
#define LCD_DMA_BURST_1 0x0
#define LCD_DMA_BURST_2 0x1
#define LCD_DMA_BURST_4 0x2
#define LCD_DMA_BURST_8 0x3
#define LCD_DMA_BURST_16 0x4
#define LCD_END_OF_FRAME_INT_ENA (1 << 2)
#define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
/* LCD Control Register */
#define LCD_CLK_DIVISOR(x) ((x) << 8)
#define LCD_RASTER_MODE 0x01
/* LCD Raster Control Register */
#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
#define PALETTE_AND_DATA 0x00
#define PALETTE_ONLY 0x01
#define DATA_ONLY 0x02
#define LCD_MONO_8BIT_MODE (1 << 9)
#define LCD_RASTER_ORDER (1 << 8)
#define LCD_TFT_MODE (1 << 7)
#define LCD_UNDERFLOW_INT_ENA (1 << 6)
#define LCD_PL_ENABLE (1 << 4)
#define LCD_MONOCHROME_MODE (1 << 1)
#define LCD_RASTER_ENABLE (1 << 0)
#define LCD_TFT_ALT_ENABLE (1 << 23)
#define LCD_STN_565_ENABLE (1 << 24)
/* LCD Raster Timing 2 Register */
#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
#define LCD_SYNC_CTRL (1 << 25)
#define LCD_SYNC_EDGE (1 << 24)
#define LCD_INVERT_PIXEL_CLOCK (1 << 22)
#define LCD_INVERT_LINE_CLOCK (1 << 21)
#define LCD_INVERT_FRAME_CLOCK (1 << 20)
/* LCD Block */
struct da8xx_lcd_regs {
u32 revid;
u32 ctrl;
u32 stat;
u32 lidd_ctrl;
u32 lidd_cs0_conf;
u32 lidd_cs0_addr;
u32 lidd_cs0_data;
u32 lidd_cs1_conf;
u32 lidd_cs1_addr;
u32 lidd_cs1_data;
u32 raster_ctrl;
u32 raster_timing_0;
u32 raster_timing_1;
u32 raster_timing_2;
u32 raster_subpanel;
u32 reserved;
u32 dma_ctrl;
u32 dma_frm_buf_base_addr_0;
u32 dma_frm_buf_ceiling_addr_0;
u32 dma_frm_buf_base_addr_1;
u32 dma_frm_buf_ceiling_addr_1;
};
#define LCD_NUM_BUFFERS 1
#define WSI_TIMEOUT 50
#define PALETTE_SIZE 256
#define LEFT_MARGIN 64
#define RIGHT_MARGIN 64
#define UPPER_MARGIN 32
#define LOWER_MARGIN 32
#define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
static struct da8xx_lcd_regs *da8xx_fb_reg_base;
DECLARE_GLOBAL_DATA_PTR;
/* graphics setup */
static GraphicDevice gpanel;
static const struct da8xx_panel *lcd_panel;
static struct fb_info *da8xx_fb_info;
static int bits_x_pixel;
static inline unsigned int lcdc_read(u32 *addr)
{
return (unsigned int)readl(addr);
}
static inline void lcdc_write(unsigned int val, u32 *addr)
{
writel(val, addr);
}
struct da8xx_fb_par {
u32 p_palette_base;
unsigned char *v_palette_base;
dma_addr_t vram_phys;
unsigned long vram_size;
void *vram_virt;
unsigned int dma_start;
unsigned int dma_end;
struct clk *lcdc_clk;
int irq;
unsigned short pseudo_palette[16];
unsigned int palette_sz;
unsigned int pxl_clk;
int blank;
int vsync_flag;
int vsync_timeout;
};
/* Variable Screen Information */
static struct fb_var_screeninfo da8xx_fb_var = {
.xoffset = 0,
.yoffset = 0,
.transp = {0, 0, 0},
.nonstd = 0,
.activate = 0,
.height = -1,
.width = -1,
.pixclock = 46666, /* 46us - AUO display */
.accel_flags = 0,
.left_margin = LEFT_MARGIN,
.right_margin = RIGHT_MARGIN,
.upper_margin = UPPER_MARGIN,
.lower_margin = LOWER_MARGIN,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_fix_screeninfo da8xx_fb_fix = {
.id = "DA8xx FB Drv",
.type = FB_TYPE_PACKED_PIXELS,
.type_aux = 0,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 0,
.ypanstep = 1,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE
};
static const struct display_panel disp_panel = {
QVGA,
16,
16,
COLOR_ACTIVE,
};
static const struct lcd_ctrl_config lcd_cfg = {
&disp_panel,
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 16,
.fdd = 255,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
};
/* Enable the Raster Engine of the LCD Controller */
static inline void lcd_enable_raster(void)
{
u32 reg;
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
if (!(reg & LCD_RASTER_ENABLE))
lcdc_write(reg | LCD_RASTER_ENABLE,
&da8xx_fb_reg_base->raster_ctrl);
}
/* Disable the Raster Engine of the LCD Controller */
static inline void lcd_disable_raster(void)
{
u32 reg;
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
if (reg & LCD_RASTER_ENABLE)
lcdc_write(reg & ~LCD_RASTER_ENABLE,
&da8xx_fb_reg_base->raster_ctrl);
}
static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
{
u32 start;
u32 end;
u32 reg_ras;
u32 reg_dma;
/* init reg to clear PLM (loading mode) fields */
reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
reg_ras &= ~(3 << 20);
reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
if (load_mode == LOAD_DATA) {
start = par->dma_start;
end = par->dma_end;
reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
reg_dma |= LCD_END_OF_FRAME_INT_ENA;
#if (LCD_NUM_BUFFERS == 2)
reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
#else
reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
#endif
} else if (load_mode == LOAD_PALETTE) {
start = par->p_palette_base;
end = start + par->palette_sz - 1;
reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
reg_ras |= LCD_PL_ENABLE;
lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
}
lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
/*
* The Raster enable bit must be set after all other control fields are
* set.
*/
lcd_enable_raster();
}
/* Configure the Burst Size of DMA */
static int lcd_cfg_dma(int burst_size)
{
u32 reg;
reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
switch (burst_size) {
case 1:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
break;
case 2:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
break;
case 4:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
break;
case 8:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
break;
case 16:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
break;
default:
return -EINVAL;
}
lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
return 0;
}
static void lcd_cfg_ac_bias(int period, int transitions_per_int)
{
u32 reg;
/* Set the AC Bias Period and Number of Transisitons per Interrupt */
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
reg |= LCD_AC_BIAS_FREQUENCY(period) |
LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
}
static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
int front_porch)
{
u32 reg;
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
reg |= ((back_porch & 0xff) << 24)
| ((front_porch & 0xff) << 16)
| ((pulse_width & 0x3f) << 10);
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
}
static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
int front_porch)
{
u32 reg;
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
reg |= ((back_porch & 0xff) << 24)
| ((front_porch & 0xff) << 16)
| ((pulse_width & 0x3f) << 10);
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
}
static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
{
u32 reg;
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
LCD_MONO_8BIT_MODE |
LCD_MONOCHROME_MODE);
switch (cfg->p_disp_panel->panel_shade) {
case MONOCHROME:
reg |= LCD_MONOCHROME_MODE;
if (cfg->mono_8bit_mode)
reg |= LCD_MONO_8BIT_MODE;
break;
case COLOR_ACTIVE:
reg |= LCD_TFT_MODE;
if (cfg->tft_alt_mode)
reg |= LCD_TFT_ALT_ENABLE;
break;
case COLOR_PASSIVE:
if (cfg->stn_565_mode)
reg |= LCD_STN_565_ENABLE;
break;
default:
return -EINVAL;
}
/* enable additional interrupts here */
reg |= LCD_UNDERFLOW_INT_ENA;
lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
if (cfg->sync_ctrl)
reg |= LCD_SYNC_CTRL;
else
reg &= ~LCD_SYNC_CTRL;
if (cfg->sync_edge)
reg |= LCD_SYNC_EDGE;
else
reg &= ~LCD_SYNC_EDGE;
if (cfg->invert_line_clock)
reg |= LCD_INVERT_LINE_CLOCK;
else
reg &= ~LCD_INVERT_LINE_CLOCK;
if (cfg->invert_frm_clock)
reg |= LCD_INVERT_FRAME_CLOCK;
else
reg &= ~LCD_INVERT_FRAME_CLOCK;
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
return 0;
}
static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
u32 bpp, u32 raster_order)
{
u32 reg;
/* Set the Panel Width */
/* Pixels per line = (PPL + 1)*16 */
/*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
width &= 0x3f0;
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
reg &= 0xfffffc00;
reg |= ((width >> 4) - 1) << 4;
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
/* Set the Panel Height */
reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
/* Set the Raster Order of the Frame Buffer */
reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
if (raster_order)
reg |= LCD_RASTER_ORDER;
lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
switch (bpp) {
case 1:
case 2:
case 4:
case 16:
par->palette_sz = 16 * 2;
break;
case 8:
par->palette_sz = 256 * 2;
break;
default:
return -EINVAL;
}
return 0;
}
static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct da8xx_fb_par *par = info->par;
unsigned short *palette = (unsigned short *) par->v_palette_base;
u_short pal;
int update_hw = 0;
if (regno > 255)
return 1;
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
return 1;
if (info->var.bits_per_pixel == 8) {
red >>= 4;
green >>= 8;
blue >>= 12;
pal = (red & 0x0f00);
pal |= (green & 0x00f0);
pal |= (blue & 0x000f);
if (palette[regno] != pal) {
update_hw = 1;
palette[regno] = pal;
}
} else if ((info->var.bits_per_pixel == 16) && regno < 16) {
red >>= (16 - info->var.red.length);
red <<= info->var.red.offset;
green >>= (16 - info->var.green.length);
green <<= info->var.green.offset;
blue >>= (16 - info->var.blue.length);
blue <<= info->var.blue.offset;
par->pseudo_palette[regno] = red | green | blue;
if (palette[0] != 0x4000) {
update_hw = 1;
palette[0] = 0x4000;
}
}
/* Update the palette in the h/w as needed. */
if (update_hw)
lcd_blit(LOAD_PALETTE, par);
return 0;
}
static void lcd_reset(struct da8xx_fb_par *par)
{
/* Disable the Raster if previously Enabled */
lcd_disable_raster();
/* DMA has to be disabled */
lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
}
static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
{
unsigned int lcd_clk, div;
/* Get clock from sysclk2 */
lcd_clk = clk_get(2);
div = lcd_clk / par->pxl_clk;
debug("LCD Clock: 0x%x Divider: 0x%x PixClk: 0x%x\n",
lcd_clk, div, par->pxl_clk);
/* Configure the LCD clock divisor. */
lcdc_write(LCD_CLK_DIVISOR(div) |
(LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
}
static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
const struct da8xx_panel *panel)
{
u32 bpp;
int ret = 0;
lcd_reset(par);
/* Calculate the divider */
lcd_calc_clk_divider(par);
if (panel->invert_pxl_clk)
lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
LCD_INVERT_PIXEL_CLOCK),
&da8xx_fb_reg_base->raster_timing_2);
else
lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
~LCD_INVERT_PIXEL_CLOCK),
&da8xx_fb_reg_base->raster_timing_2);
/* Configure the DMA burst size. */
ret = lcd_cfg_dma(cfg->dma_burst_sz);
if (ret < 0)
return ret;
/* Configure the AC bias properties. */
lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
/* Configure the vertical and horizontal sync properties. */
lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
/* Configure for disply */
ret = lcd_cfg_display(cfg);
if (ret < 0)
return ret;
if (QVGA != cfg->p_disp_panel->panel_type)
return -EINVAL;
if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
cfg->bpp >= cfg->p_disp_panel->min_bpp)
bpp = cfg->bpp;
else
bpp = cfg->p_disp_panel->max_bpp;
if (bpp == 12)
bpp = 16;
ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
(unsigned int)panel->height, bpp,
cfg->raster_order);
if (ret < 0)
return ret;
/* Configure FDD */
lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
(cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
return 0;
}
static void lcdc_dma_start(void)
{
struct da8xx_fb_par *par = da8xx_fb_info->par;
lcdc_write(par->dma_start,
&da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
lcdc_write(par->dma_end,
&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
lcdc_write(0,
&da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
lcdc_write(0,
&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
}
static u32 lcdc_irq_handler(void)
{
struct da8xx_fb_par *par = da8xx_fb_info->par;
u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
u32 reg_ras;
if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
debug("LCD_SYNC_LOST\n");
lcd_disable_raster();
lcdc_write(stat, &da8xx_fb_reg_base->stat);
lcd_enable_raster();
return LCD_SYNC_LOST;
} else if (stat & LCD_PL_LOAD_DONE) {
debug("LCD_PL_LOAD_DONE\n");
/*
* Must disable raster before changing state of any control bit.
* And also must be disabled before clearing the PL loading
* interrupt via the following write to the status register. If
* this is done after then one gets multiple PL done interrupts.
*/
lcd_disable_raster();
lcdc_write(stat, &da8xx_fb_reg_base->stat);
/* Disable PL completion inerrupt */
reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
reg_ras &= ~LCD_PL_ENABLE;
lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
/* Setup and start data loading mode */
lcd_blit(LOAD_DATA, par);
return LCD_PL_LOAD_DONE;
} else {
lcdc_write(stat, &da8xx_fb_reg_base->stat);
if (stat & LCD_END_OF_FRAME0)
debug("LCD_END_OF_FRAME0\n");
lcdc_write(par->dma_start,
&da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
lcdc_write(par->dma_end,
&da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
par->vsync_flag = 1;
return LCD_END_OF_FRAME0;
}
return stat;
}
static u32 wait_for_event(u32 event)
{
u32 timeout = 50000;
u32 ret;
do {
ret = lcdc_irq_handler();
udelay(1000);
} while (!(ret & event));
if (timeout <= 0) {
printf("%s: event %d not hit\n", __func__, event);
return -1;
}
return 0;
}
void *video_hw_init(void)
{
struct da8xx_fb_par *par;
u32 size;
char *p;
if (!lcd_panel) {
printf("Display not initialized\n");
return NULL;
}
gpanel.winSizeX = lcd_panel->width;
gpanel.winSizeY = lcd_panel->height;
gpanel.plnSizeX = lcd_panel->width;
gpanel.plnSizeY = lcd_panel->height;
switch (bits_x_pixel) {
case 24:
gpanel.gdfBytesPP = 4;
gpanel.gdfIndex = GDF_32BIT_X888RGB;
break;
case 16:
gpanel.gdfBytesPP = 2;
gpanel.gdfIndex = GDF_16BIT_565RGB;
break;
default:
gpanel.gdfBytesPP = 1;
gpanel.gdfIndex = GDF__8BIT_INDEX;
break;
}
da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DAVINCI_LCD_CNTL_BASE;
debug("Resolution: %dx%d %x\n",
gpanel.winSizeX,
gpanel.winSizeY,
lcd_cfg.bpp);
size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
da8xx_fb_info = malloc(size);
debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
if (!da8xx_fb_info) {
printf("Memory allocation failed for fb_info\n");
return NULL;
}
memset(da8xx_fb_info, 0, size);
p = (char *)da8xx_fb_info;
da8xx_fb_info->par = p + sizeof(struct fb_info);
debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
par = da8xx_fb_info->par;
par->pxl_clk = lcd_panel->pxl_clk;
if (lcd_init(par, &lcd_cfg, lcd_panel) < 0) {
printf("lcd_init failed\n");
goto err_release_fb;
}
/* allocate frame buffer */
par->vram_size = lcd_panel->width * lcd_panel->height * lcd_cfg.bpp;
par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
par->vram_virt = malloc(par->vram_size);
par->vram_phys = (dma_addr_t) par->vram_virt;
debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
(unsigned int)par->vram_size,
(unsigned int)par->vram_virt);
if (!par->vram_virt) {
printf("GLCD: malloc for frame buffer failed\n");
goto err_release_fb;
}
gpanel.frameAdrs = (unsigned int)par->vram_virt;
da8xx_fb_info->screen_base = (char *) par->vram_virt;
da8xx_fb_fix.smem_start = gpanel.frameAdrs;
da8xx_fb_fix.smem_len = par->vram_size;
da8xx_fb_fix.line_length = (lcd_panel->width * lcd_cfg.bpp) / 8;
par->dma_start = par->vram_phys;
par->dma_end = par->dma_start + lcd_panel->height *
da8xx_fb_fix.line_length - 1;
/* allocate palette buffer */
par->v_palette_base = malloc(PALETTE_SIZE);
if (!par->v_palette_base) {
printf("GLCD: malloc for palette buffer failed\n");
goto err_release_fb_mem;
}
memset(par->v_palette_base, 0, PALETTE_SIZE);
par->p_palette_base = (unsigned int)par->v_palette_base;
/* Initialize par */
da8xx_fb_info->var.bits_per_pixel = lcd_cfg.bpp;
da8xx_fb_var.xres = lcd_panel->width;
da8xx_fb_var.xres_virtual = lcd_panel->width;
da8xx_fb_var.yres = lcd_panel->height;
da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
da8xx_fb_var.grayscale =
lcd_cfg.p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
da8xx_fb_var.bits_per_pixel = lcd_cfg.bpp;
da8xx_fb_var.hsync_len = lcd_panel->hsw;
da8xx_fb_var.vsync_len = lcd_panel->vsw;
/* Initialize fbinfo */
da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
da8xx_fb_info->fix = da8xx_fb_fix;
da8xx_fb_info->var = da8xx_fb_var;
da8xx_fb_info->pseudo_palette = par->pseudo_palette;
da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
/* Clear interrupt */
memset((void *)par->vram_virt, 0, par->vram_size);
lcd_disable_raster();
lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
debug("Palette at 0x%x size %d\n", par->p_palette_base,
par->palette_sz);
lcdc_dma_start();
/* Load a default palette */
fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
/* Check that the palette is loaded */
wait_for_event(LCD_PL_LOAD_DONE);
/* Wait until DMA is working */
wait_for_event(LCD_END_OF_FRAME0);
return (void *)&gpanel;
err_release_fb_mem:
free(par->vram_virt);
err_release_fb:
free(da8xx_fb_info);
return NULL;
}
void video_set_lut(unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
)
{
return;
}
void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel)
{
lcd_panel = panel;
bits_x_pixel = bits_pixel;
}
|
1001-study-uboot
|
drivers/video/da8xx-fb.c
|
C
|
gpl3
| 21,023
|
/*
* (C) Copyright 2010
* Matthias Weisser <weisserm@arcor.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic
* controller.
*/
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <video_fb.h>
#include "videomodes.h"
/*
* 4MB (at the end of system RAM)
*/
#define VIDEO_MEM_SIZE 0x400000
#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */
/*
* Graphic Device
*/
static GraphicDevice mb86r0x;
static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr,
u32 *videomem)
{
struct ctfb_res_modes var_mode;
u32 dcm1, dcm2, dcm3;
u16 htp, hdp, hdb, hsp, vtr, vsp, vdp;
u8 hsw, vsw;
u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1;
u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh;
unsigned long div;
int bpp;
bpp = video_get_params(&var_mode, modestr);
if (bpp == 0) {
var_mode.xres = 640;
var_mode.yres = 480;
var_mode.pixclock = 39721; /* 25MHz */
var_mode.left_margin = 48;
var_mode.right_margin = 16;
var_mode.upper_margin = 33;
var_mode.lower_margin = 10;
var_mode.hsync_len = 96;
var_mode.vsync_len = 2;
var_mode.sync = 0;
var_mode.vmode = 0;
bpp = 15;
}
/* Fill memory with white */
memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2);
mb86r0x.winSizeX = var_mode.xres;
mb86r0x.winSizeY = var_mode.yres;
/* LCD base clock is ~ 660MHZ. We do calculations in kHz */
div = 660000 / (1000000000L / var_mode.pixclock);
if (div > 64)
div = 64;
if (0 == div)
div = 1;
dcm1 = (div - 1) << 8;
dcm2 = 0x00000000;
if (var_mode.sync & FB_SYNC_CLK_INV)
dcm3 = 0x00000100;
else
dcm3 = 0x00000000;
htp = var_mode.left_margin + var_mode.xres +
var_mode.hsync_len + var_mode.right_margin;
hdp = var_mode.xres;
hdb = var_mode.xres;
hsp = var_mode.xres + var_mode.right_margin;
hsw = var_mode.hsync_len;
vsw = var_mode.vsync_len;
vtr = var_mode.upper_margin + var_mode.yres +
var_mode.vsync_len + var_mode.lower_margin;
vsp = var_mode.yres + var_mode.lower_margin;
vdp = var_mode.yres;
l2m = ((var_mode.yres - 1) << (0)) |
(((var_mode.xres * 2) / 64) << (16)) |
((1) << (31));
l2em = (1 << 0) | (1 << 1);
l2oa0 = mb86r0x.frameAdrs;
l2da0 = mb86r0x.frameAdrs;
l2oa1 = mb86r0x.frameAdrs;
l2da1 = mb86r0x.frameAdrs;
l2dx = 0;
l2dy = 0;
l2wx = 0;
l2wy = 0;
l2ww = var_mode.xres;
l2wh = var_mode.yres - 1;
writel(dcm1, &dsp->dcm1);
writel(dcm2, &dsp->dcm2);
writel(dcm3, &dsp->dcm3);
writew(htp, &dsp->htp);
writew(hdp, &dsp->hdp);
writew(hdb, &dsp->hdb);
writew(hsp, &dsp->hsp);
writeb(hsw, &dsp->hsw);
writeb(vsw, &dsp->vsw);
writew(vtr, &dsp->vtr);
writew(vsp, &dsp->vsp);
writew(vdp, &dsp->vdp);
writel(l2m, &dsp->l2m);
writel(l2em, &dsp->l2em);
writel(l2oa0, &dsp->l2oa0);
writel(l2da0, &dsp->l2da0);
writel(l2oa1, &dsp->l2oa1);
writel(l2da1, &dsp->l2da1);
writew(l2dx, &dsp->l2dx);
writew(l2dy, &dsp->l2dy);
writew(l2wx, &dsp->l2wx);
writew(l2wy, &dsp->l2wy);
writew(l2ww, &dsp->l2ww);
writew(l2wh, &dsp->l2wh);
writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1);
}
void *video_hw_init(void)
{
struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE;
GraphicDevice *pGD = &mb86r0x;
char *s;
u32 *vid;
memset(pGD, 0, sizeof(GraphicDevice));
pGD->gdfIndex = GDF_15BIT_555RGB;
pGD->gdfBytesPP = 2;
pGD->memSize = VIDEO_MEM_SIZE;
pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
vid = (u32 *)pGD->frameAdrs;
s = getenv("videomode");
if (s != NULL)
dsp_init(&gdc->dsp0, s, vid);
s = getenv("videomode1");
if (s != NULL)
dsp_init(&gdc->dsp1, s, vid);
return pGD;
}
|
1001-study-uboot
|
drivers/video/mb86r0xgdc.c
|
C
|
gpl3
| 4,414
|
/*
* (C) Copyright 2002
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
*
* (C) Copyright 2005
* Martin Krause TQ-Systems GmbH martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Basic video support for SMI SM501 "Voyager" graphic controller
*/
#include <common.h>
#include <asm/io.h>
#include <video_fb.h>
#include <sm501.h>
#define read8(ptrReg) \
*(volatile unsigned char *)(sm501.isaBase + ptrReg)
#define write8(ptrReg,value) \
*(volatile unsigned char *)(sm501.isaBase + ptrReg) = value
#define read16(ptrReg) \
(*(volatile unsigned short *)(sm501.isaBase + ptrReg))
#define write16(ptrReg,value) \
(*(volatile unsigned short *)(sm501.isaBase + ptrReg) = value)
#define read32(ptrReg) \
(*(volatile unsigned int *)(sm501.isaBase + ptrReg))
#define write32(ptrReg, value) \
(*(volatile unsigned int *)(sm501.isaBase + ptrReg) = value)
GraphicDevice sm501;
void write_be32(int off, unsigned int val)
{
out_be32((unsigned __iomem *)(sm501.isaBase + off), val);
}
void write_le32(int off, unsigned int val)
{
out_le32((unsigned __iomem *)(sm501.isaBase + off), val);
}
void (*write_reg32)(int off, unsigned int val) = write_be32;
/*-----------------------------------------------------------------------------
* SmiSetRegs --
*-----------------------------------------------------------------------------
*/
static void SmiSetRegs (void)
{
/*
* The content of the chipset register depends on the board (clocks,
* ...)
*/
const SMI_REGS *preg = board_get_regs ();
while (preg->Index) {
write_reg32 (preg->Index, preg->Value);
/*
* Insert a delay between
*/
udelay (1000);
preg ++;
}
}
#ifdef CONFIG_VIDEO_SM501_PCI
static struct pci_device_id sm501_pci_tbl[] = {
{ PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_501 },
{}
};
#endif
/*
* We do not enforce board code to provide empty/unused
* functions for this driver and define weak default
* functions here.
*/
unsigned int __board_video_init (void)
{
return 0;
}
unsigned int board_video_init (void)
__attribute__((weak, alias("__board_video_init")));
unsigned int __board_video_get_fb (void)
{
return 0;
}
unsigned int board_video_get_fb (void)
__attribute__((weak, alias("__board_video_get_fb")));
void __board_validate_screen (unsigned int base)
{
}
void board_validate_screen (unsigned int base)
__attribute__((weak, alias("__board_validate_screen")));
/*-----------------------------------------------------------------------------
* video_hw_init --
*-----------------------------------------------------------------------------
*/
void *video_hw_init (void)
{
#ifdef CONFIG_VIDEO_SM501_PCI
unsigned int pci_mem_base, pci_mmio_base;
unsigned int id;
unsigned short device_id;
pci_dev_t devbusfn;
int mem;
#endif
unsigned int *vm, i;
memset (&sm501, 0, sizeof (GraphicDevice));
#ifdef CONFIG_VIDEO_SM501_PCI
printf("Video: ");
/* Look for SM501/SM502 chips */
devbusfn = pci_find_devices(sm501_pci_tbl, 0);
if (devbusfn < 0) {
printf ("PCI Controller not found.\n");
goto not_pci;
}
/* Setup */
pci_write_config_dword (devbusfn, PCI_COMMAND,
(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
pci_read_config_dword (devbusfn, PCI_REVISION_ID, &id);
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_1, &pci_mmio_base);
sm501.frameAdrs = pci_mem_to_phys (devbusfn, pci_mem_base);
sm501.isaBase = pci_mem_to_phys (devbusfn, pci_mmio_base);
if (sm501.isaBase)
write_reg32 = write_le32;
mem = in_le32 ((unsigned __iomem *)(sm501.isaBase + 0x10));
mem = (mem & 0x0000e000) >> 13;
switch (mem) {
case 1:
mem = 8;
break;
case 2:
mem = 16;
break;
case 3:
mem = 32;
break;
case 4:
mem = 64;
break;
case 5:
mem = 2;
break;
case 0:
default:
mem = 4;
}
printf ("PCI SM50%d %d MB\n", ((id & 0xff) == 0xC0) ? 2 : 1, mem);
not_pci:
#endif
/*
* Initialization of the access to the graphic chipset Retreive base
* address of the chipset (see board/RPXClassic/eccx.c)
*/
if (!sm501.isaBase) {
sm501.isaBase = board_video_init ();
if (!sm501.isaBase)
return NULL;
}
if (!sm501.frameAdrs) {
sm501.frameAdrs = board_video_get_fb ();
if (!sm501.frameAdrs)
return NULL;
}
sm501.winSizeX = board_get_width ();
sm501.winSizeY = board_get_height ();
#if defined(CONFIG_VIDEO_SM501_8BPP)
sm501.gdfIndex = GDF__8BIT_INDEX;
sm501.gdfBytesPP = 1;
#elif defined(CONFIG_VIDEO_SM501_16BPP)
sm501.gdfIndex = GDF_16BIT_565RGB;
sm501.gdfBytesPP = 2;
#elif defined(CONFIG_VIDEO_SM501_32BPP)
sm501.gdfIndex = GDF_32BIT_X888RGB;
sm501.gdfBytesPP = 4;
#else
#error Unsupported SM501 BPP
#endif
sm501.memSize = sm501.winSizeX * sm501.winSizeY * sm501.gdfBytesPP;
/* Load Smi registers */
SmiSetRegs ();
/* (see board/RPXClassic/RPXClassic.c) */
board_validate_screen (sm501.isaBase);
/* Clear video memory */
i = sm501.memSize/4;
vm = (unsigned int *)sm501.frameAdrs;
while(i--)
*vm++ = 0;
return (&sm501);
}
|
1001-study-uboot
|
drivers/video/sm501.c
|
C
|
gpl3
| 5,882
|
/*
* Porting to u-boot:
*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* Linux IPU driver for MX51:
*
* (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* #define DEBUG */
#include <common.h>
#include <linux/types.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include "ipu.h"
#include "ipu_regs.h"
enum csc_type_t {
RGB2YUV = 0,
YUV2RGB,
RGB2RGB,
YUV2YUV,
CSC_NONE,
CSC_NUM
};
struct dp_csc_param_t {
int mode;
void *coeff;
};
#define SYNC_WAVE 0
/* DC display ID assignments */
#define DC_DISP_ID_SYNC(di) (di)
#define DC_DISP_ID_SERIAL 2
#define DC_DISP_ID_ASYNC 3
int dmfc_type_setup;
static int dmfc_size_28, dmfc_size_29, dmfc_size_24, dmfc_size_27, dmfc_size_23;
int g_di1_tvout;
extern struct clk *g_ipu_clk;
extern struct clk *g_di_clk[2];
extern struct clk *g_pixel_clk[2];
extern unsigned char g_ipu_clk_enabled;
extern unsigned char g_dc_di_assignment[];
void ipu_dmfc_init(int dmfc_type, int first)
{
u32 dmfc_wr_chan, dmfc_dp_chan;
if (first) {
if (dmfc_type_setup > dmfc_type)
dmfc_type = dmfc_type_setup;
else
dmfc_type_setup = dmfc_type;
/* disable DMFC-IC channel*/
__raw_writel(0x2, DMFC_IC_CTRL);
} else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
printf("DMFC high resolution has set, will not change\n");
return;
} else
dmfc_type_setup = dmfc_type;
if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
/* 1 - segment 0~3;
* 5B - segement 4, 5;
* 5F - segement 6, 7;
* 1C, 2C and 6B, 6F unused;
*/
debug("IPU DMFC DC HIGH RES: 1(0~3), 5B(4,5), 5F(6,7)\n");
dmfc_wr_chan = 0x00000088;
dmfc_dp_chan = 0x00009694;
dmfc_size_28 = 256 * 4;
dmfc_size_29 = 0;
dmfc_size_24 = 0;
dmfc_size_27 = 128 * 4;
dmfc_size_23 = 128 * 4;
} else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
/* 1 - segment 0, 1;
* 5B - segement 2~5;
* 5F - segement 6,7;
* 1C, 2C and 6B, 6F unused;
*/
debug("IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)\n");
dmfc_wr_chan = 0x00000090;
dmfc_dp_chan = 0x0000968a;
dmfc_size_28 = 128 * 4;
dmfc_size_29 = 0;
dmfc_size_24 = 0;
dmfc_size_27 = 128 * 4;
dmfc_size_23 = 256 * 4;
} else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
/* 5B - segement 0~3;
* 5F - segement 4~7;
* 1, 1C, 2C and 6B, 6F unused;
*/
debug("IPU DMFC ONLY-DP HIGH RES: 5B(0~3), 5F(4~7)\n");
dmfc_wr_chan = 0x00000000;
dmfc_dp_chan = 0x00008c88;
dmfc_size_28 = 0;
dmfc_size_29 = 0;
dmfc_size_24 = 0;
dmfc_size_27 = 256 * 4;
dmfc_size_23 = 256 * 4;
} else {
/* 1 - segment 0, 1;
* 5B - segement 4, 5;
* 5F - segement 6, 7;
* 1C, 2C and 6B, 6F unused;
*/
debug("IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
dmfc_wr_chan = 0x00000090;
dmfc_dp_chan = 0x00009694;
dmfc_size_28 = 128 * 4;
dmfc_size_29 = 0;
dmfc_size_24 = 0;
dmfc_size_27 = 128 * 4;
dmfc_size_23 = 128 * 4;
}
__raw_writel(dmfc_wr_chan, DMFC_WR_CHAN);
__raw_writel(0x202020F6, DMFC_WR_CHAN_DEF);
__raw_writel(dmfc_dp_chan, DMFC_DP_CHAN);
/* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
__raw_writel(0x2020F6F6, DMFC_DP_CHAN_DEF);
}
void ipu_dmfc_set_wait4eot(int dma_chan, int width)
{
u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1);
if (width >= HIGH_RESOLUTION_WIDTH) {
if (dma_chan == 23)
ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DP, 0);
else if (dma_chan == 28)
ipu_dmfc_init(DMFC_HIGH_RESOLUTION_DC, 0);
}
if (dma_chan == 23) { /*5B*/
if (dmfc_size_23 / width > 3)
dmfc_gen1 |= 1UL << 20;
else
dmfc_gen1 &= ~(1UL << 20);
} else if (dma_chan == 24) { /*6B*/
if (dmfc_size_24 / width > 1)
dmfc_gen1 |= 1UL << 22;
else
dmfc_gen1 &= ~(1UL << 22);
} else if (dma_chan == 27) { /*5F*/
if (dmfc_size_27 / width > 2)
dmfc_gen1 |= 1UL << 21;
else
dmfc_gen1 &= ~(1UL << 21);
} else if (dma_chan == 28) { /*1*/
if (dmfc_size_28 / width > 2)
dmfc_gen1 |= 1UL << 16;
else
dmfc_gen1 &= ~(1UL << 16);
} else if (dma_chan == 29) { /*6F*/
if (dmfc_size_29 / width > 1)
dmfc_gen1 |= 1UL << 23;
else
dmfc_gen1 &= ~(1UL << 23);
}
__raw_writel(dmfc_gen1, DMFC_GENERAL1);
}
static void ipu_di_data_wave_config(int di,
int wave_gen,
int access_size, int component_size)
{
u32 reg;
reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
(component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
__raw_writel(reg, DI_DW_GEN(di, wave_gen));
}
static void ipu_di_data_pin_config(int di, int wave_gen, int di_pin, int set,
int up, int down)
{
u32 reg;
reg = __raw_readl(DI_DW_GEN(di, wave_gen));
reg &= ~(0x3 << (di_pin * 2));
reg |= set << (di_pin * 2);
__raw_writel(reg, DI_DW_GEN(di, wave_gen));
__raw_writel((down << 16) | up, DI_DW_SET(di, wave_gen, set));
}
static void ipu_di_sync_config(int di, int wave_gen,
int run_count, int run_src,
int offset_count, int offset_src,
int repeat_count, int cnt_clr_src,
int cnt_polarity_gen_en,
int cnt_polarity_clr_src,
int cnt_polarity_trigger_src,
int cnt_up, int cnt_down)
{
u32 reg;
if ((run_count >= 0x1000) || (offset_count >= 0x1000) ||
(repeat_count >= 0x1000) ||
(cnt_up >= 0x400) || (cnt_down >= 0x400)) {
printf("DI%d counters out of range.\n", di);
return;
}
reg = (run_count << 19) | (++run_src << 16) |
(offset_count << 3) | ++offset_src;
__raw_writel(reg, DI_SW_GEN0(di, wave_gen));
reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
(++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
reg |= (cnt_down << 16) | cnt_up;
if (repeat_count == 0) {
/* Enable auto reload */
reg |= 0x10000000;
}
__raw_writel(reg, DI_SW_GEN1(di, wave_gen));
reg = __raw_readl(DI_STP_REP(di, wave_gen));
reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
__raw_writel(reg, DI_STP_REP(di, wave_gen));
}
static void ipu_dc_map_config(int map, int byte_num, int offset, int mask)
{
int ptr = map * 3 + byte_num;
u32 reg;
reg = __raw_readl(DC_MAP_CONF_VAL(ptr));
reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
__raw_writel(reg, DC_MAP_CONF_VAL(ptr));
reg = __raw_readl(DC_MAP_CONF_PTR(map));
reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
__raw_writel(reg, DC_MAP_CONF_PTR(map));
}
static void ipu_dc_map_clear(int map)
{
u32 reg = __raw_readl(DC_MAP_CONF_PTR(map));
__raw_writel(reg & ~(0xFFFF << (16 * (map & 0x1))),
DC_MAP_CONF_PTR(map));
}
static void ipu_dc_write_tmpl(int word, u32 opcode, u32 operand, int map,
int wave, int glue, int sync)
{
u32 reg;
int stop = 1;
reg = sync;
reg |= (glue << 4);
reg |= (++wave << 11);
reg |= (++map << 15);
reg |= (operand << 20) & 0xFFF00000;
__raw_writel(reg, ipu_dc_tmpl_reg + word * 2);
reg = (operand >> 12);
reg |= opcode << 4;
reg |= (stop << 9);
__raw_writel(reg, ipu_dc_tmpl_reg + word * 2 + 1);
}
static void ipu_dc_link_event(int chan, int event, int addr, int priority)
{
u32 reg;
reg = __raw_readl(DC_RL_CH(chan, event));
reg &= ~(0xFFFF << (16 * (event & 0x1)));
reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
__raw_writel(reg, DC_RL_CH(chan, event));
}
/* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;
* U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
* V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;
*/
static const int rgb2ycbcr_coeff[5][3] = {
{0x4D, 0x96, 0x1D},
{0x3D5, 0x3AB, 0x80},
{0x80, 0x395, 0x3EB},
{0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */
{0x2, 0x2, 0x2}, /* S0, S1, S2 */
};
/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
* G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
* B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
*/
static const int ycbcr2rgb_coeff[5][3] = {
{0x095, 0x000, 0x0CC},
{0x095, 0x3CE, 0x398},
{0x095, 0x0FF, 0x000},
{0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */
{0x1, 0x1, 0x1}, /*S0,S1,S2 */
};
#define mask_a(a) ((u32)(a) & 0x3FF)
#define mask_b(b) ((u32)(b) & 0x3FFF)
/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
static int rgb_to_yuv(int n, int red, int green, int blue)
{
int c;
c = red * rgb2ycbcr_coeff[n][0];
c += green * rgb2ycbcr_coeff[n][1];
c += blue * rgb2ycbcr_coeff[n][2];
c /= 16;
c += rgb2ycbcr_coeff[3][n] * 4;
c += 8;
c /= 16;
if (c < 0)
c = 0;
if (c > 255)
c = 255;
return c;
}
/*
* Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
* Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
*/
static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
{
{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff},
{0, 0},
{0, 0},
{DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff},
{DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}
},
{
{0, 0},
{DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff},
{DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff},
{0, 0},
{DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}
},
{
{0, 0},
{DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
{0, 0},
{0, 0},
{0, 0}
},
{
{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
{0, 0},
{0, 0},
{0, 0},
{0, 0}
},
{
{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff},
{DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff},
{0, 0},
{0, 0},
{0, 0}
}
};
static enum csc_type_t fg_csc_type = CSC_NONE, bg_csc_type = CSC_NONE;
static int color_key_4rgb = 1;
void ipu_dp_csc_setup(int dp, struct dp_csc_param_t dp_csc_param,
unsigned char srm_mode_update)
{
u32 reg;
const int (*coeff)[5][3];
if (dp_csc_param.mode >= 0) {
reg = __raw_readl(DP_COM_CONF());
reg &= ~DP_COM_CONF_CSC_DEF_MASK;
reg |= dp_csc_param.mode;
__raw_writel(reg, DP_COM_CONF());
}
coeff = dp_csc_param.coeff;
if (coeff) {
__raw_writel(mask_a((*coeff)[0][0]) |
(mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0());
__raw_writel(mask_a((*coeff)[0][2]) |
(mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1());
__raw_writel(mask_a((*coeff)[1][1]) |
(mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2());
__raw_writel(mask_a((*coeff)[2][0]) |
(mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3());
__raw_writel(mask_a((*coeff)[2][2]) |
(mask_b((*coeff)[3][0]) << 16) |
((*coeff)[4][0] << 30), DP_CSC_0());
__raw_writel(mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
(mask_b((*coeff)[3][2]) << 16) |
((*coeff)[4][2] << 30), DP_CSC_1());
}
if (srm_mode_update) {
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
}
}
int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
uint32_t out_pixel_fmt)
{
int in_fmt, out_fmt;
int dp;
int partial = 0;
uint32_t reg;
if (channel == MEM_FG_SYNC) {
dp = DP_SYNC;
partial = 1;
} else if (channel == MEM_BG_SYNC) {
dp = DP_SYNC;
partial = 0;
} else if (channel == MEM_BG_ASYNC0) {
dp = DP_ASYNC0;
partial = 0;
} else {
return -EINVAL;
}
in_fmt = format_to_colorspace(in_pixel_fmt);
out_fmt = format_to_colorspace(out_pixel_fmt);
if (partial) {
if (in_fmt == RGB) {
if (out_fmt == RGB)
fg_csc_type = RGB2RGB;
else
fg_csc_type = RGB2YUV;
} else {
if (out_fmt == RGB)
fg_csc_type = YUV2RGB;
else
fg_csc_type = YUV2YUV;
}
} else {
if (in_fmt == RGB) {
if (out_fmt == RGB)
bg_csc_type = RGB2RGB;
else
bg_csc_type = RGB2YUV;
} else {
if (out_fmt == RGB)
bg_csc_type = YUV2RGB;
else
bg_csc_type = YUV2YUV;
}
}
/* Transform color key from rgb to yuv if CSC is enabled */
reg = __raw_readl(DP_COM_CONF());
if (color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
(((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
int red, green, blue;
int y, u, v;
uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
0xFFFFFFL;
debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
color_key);
red = (color_key >> 16) & 0xFF;
green = (color_key >> 8) & 0xFF;
blue = color_key & 0xFF;
y = rgb_to_yuv(0, red, green, blue);
u = rgb_to_yuv(1, red, green, blue);
v = rgb_to_yuv(2, red, green, blue);
color_key = (y << 16) | (u << 8) | v;
reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
__raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
color_key_4rgb = 0;
debug("_ipu_dp_init color key change to yuv fmt 0x%x!\n",
color_key);
}
ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 1);
return 0;
}
void ipu_dp_uninit(ipu_channel_t channel)
{
int dp;
int partial = 0;
if (channel == MEM_FG_SYNC) {
dp = DP_SYNC;
partial = 1;
} else if (channel == MEM_BG_SYNC) {
dp = DP_SYNC;
partial = 0;
} else if (channel == MEM_BG_ASYNC0) {
dp = DP_ASYNC0;
partial = 0;
} else {
return;
}
if (partial)
fg_csc_type = CSC_NONE;
else
bg_csc_type = CSC_NONE;
ipu_dp_csc_setup(dp, dp_csc_array[bg_csc_type][fg_csc_type], 0);
}
void ipu_dc_init(int dc_chan, int di, unsigned char interlaced)
{
u32 reg = 0;
if ((dc_chan == 1) || (dc_chan == 5)) {
if (interlaced) {
ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 3);
ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 2);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 1);
} else {
if (di) {
ipu_dc_link_event(dc_chan, DC_EVT_NL, 2, 3);
ipu_dc_link_event(dc_chan, DC_EVT_EOL, 3, 2);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
4, 1);
} else {
ipu_dc_link_event(dc_chan, DC_EVT_NL, 5, 3);
ipu_dc_link_event(dc_chan, DC_EVT_EOL, 6, 2);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA,
7, 1);
}
}
ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
reg = 0x2;
reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
reg |= di << 2;
if (interlaced)
reg |= DC_WR_CH_CONF_FIELD_MODE;
} else if ((dc_chan == 8) || (dc_chan == 9)) {
/* async channels */
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
reg = 0x3;
reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
}
__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
__raw_writel(0x00000000, DC_WR_CH_ADDR(dc_chan));
__raw_writel(0x00000084, DC_GEN);
}
void ipu_dc_uninit(int dc_chan)
{
if ((dc_chan == 1) || (dc_chan == 5)) {
ipu_dc_link_event(dc_chan, DC_EVT_NL, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_EOL, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NF, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NFIELD, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_EOF, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_EOFIELD, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR, 0, 0);
} else if ((dc_chan == 8) || (dc_chan == 9)) {
ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
ipu_dc_link_event(dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
}
}
int ipu_chan_is_interlaced(ipu_channel_t channel)
{
if (channel == MEM_DC_SYNC)
return !!(__raw_readl(DC_WR_CH_CONF_1) &
DC_WR_CH_CONF_FIELD_MODE);
else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
return !!(__raw_readl(DC_WR_CH_CONF_5) &
DC_WR_CH_CONF_FIELD_MODE);
return 0;
}
void ipu_dp_dc_enable(ipu_channel_t channel)
{
int di;
uint32_t reg;
uint32_t dc_chan;
if (channel == MEM_FG_SYNC)
dc_chan = 5;
if (channel == MEM_DC_SYNC)
dc_chan = 1;
else if (channel == MEM_BG_SYNC)
dc_chan = 5;
else
return;
if (channel == MEM_FG_SYNC) {
/* Enable FG channel */
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg | DP_COM_CONF_FG_EN, DP_COM_CONF());
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
return;
}
di = g_dc_di_assignment[dc_chan];
/* Make sure other DC sync channel is not assigned same DI */
reg = __raw_readl(DC_WR_CH_CONF(6 - dc_chan));
if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
__raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
}
reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
clk_enable(g_pixel_clk[di]);
}
static unsigned char dc_swap;
void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
{
uint32_t reg;
uint32_t csc;
uint32_t dc_chan = 0;
int timeout = 50;
dc_swap = swap;
if (channel == MEM_DC_SYNC) {
dc_chan = 1;
} else if (channel == MEM_BG_SYNC) {
dc_chan = 5;
} else if (channel == MEM_FG_SYNC) {
/* Disable FG channel */
dc_chan = 5;
reg = __raw_readl(DP_COM_CONF());
csc = reg & DP_COM_CONF_CSC_DEF_MASK;
if (csc == DP_COM_CONF_CSC_DEF_FG)
reg &= ~DP_COM_CONF_CSC_DEF_MASK;
reg &= ~DP_COM_CONF_FG_EN;
__raw_writel(reg, DP_COM_CONF());
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
timeout = 50;
/*
* Wait for DC triple buffer to empty,
* this check is useful for tv overlay.
*/
if (g_dc_di_assignment[dc_chan] == 0)
while ((__raw_readl(DC_STAT) & 0x00000002)
!= 0x00000002) {
udelay(2000);
timeout -= 2;
if (timeout <= 0)
break;
}
else if (g_dc_di_assignment[dc_chan] == 1)
while ((__raw_readl(DC_STAT) & 0x00000020)
!= 0x00000020) {
udelay(2000);
timeout -= 2;
if (timeout <= 0)
break;
}
return;
} else {
return;
}
if (dc_swap) {
/* Swap DC channel 1 and 5 settings, and disable old dc chan */
reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
__raw_writel(reg, DC_WR_CH_CONF(6 - dc_chan));
reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
reg ^= DC_WR_CH_CONF_PROG_DI_ID;
__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
} else {
timeout = 50;
/* Wait for DC triple buffer to empty */
if (g_dc_di_assignment[dc_chan] == 0)
while ((__raw_readl(DC_STAT) & 0x00000002)
!= 0x00000002) {
udelay(2000);
timeout -= 2;
if (timeout <= 0)
break;
}
else if (g_dc_di_assignment[dc_chan] == 1)
while ((__raw_readl(DC_STAT) & 0x00000020)
!= 0x00000020) {
udelay(2000);
timeout -= 2;
if (timeout <= 0)
break;
}
reg = __raw_readl(DC_WR_CH_CONF(dc_chan));
reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
__raw_writel(reg, DC_WR_CH_CONF(dc_chan));
reg = __raw_readl(IPU_DISP_GEN);
if (g_dc_di_assignment[dc_chan])
reg &= ~DI1_COUNTER_RELEASE;
else
reg &= ~DI0_COUNTER_RELEASE;
__raw_writel(reg, IPU_DISP_GEN);
/* Clock is already off because it must be done quickly, but
we need to fix the ref count */
clk_disable(g_pixel_clk[g_dc_di_assignment[dc_chan]]);
}
}
void ipu_init_dc_mappings(void)
{
/* IPU_PIX_FMT_RGB24 */
ipu_dc_map_clear(0);
ipu_dc_map_config(0, 0, 7, 0xFF);
ipu_dc_map_config(0, 1, 15, 0xFF);
ipu_dc_map_config(0, 2, 23, 0xFF);
/* IPU_PIX_FMT_RGB666 */
ipu_dc_map_clear(1);
ipu_dc_map_config(1, 0, 5, 0xFC);
ipu_dc_map_config(1, 1, 11, 0xFC);
ipu_dc_map_config(1, 2, 17, 0xFC);
/* IPU_PIX_FMT_YUV444 */
ipu_dc_map_clear(2);
ipu_dc_map_config(2, 0, 15, 0xFF);
ipu_dc_map_config(2, 1, 23, 0xFF);
ipu_dc_map_config(2, 2, 7, 0xFF);
/* IPU_PIX_FMT_RGB565 */
ipu_dc_map_clear(3);
ipu_dc_map_config(3, 0, 4, 0xF8);
ipu_dc_map_config(3, 1, 10, 0xFC);
ipu_dc_map_config(3, 2, 15, 0xF8);
/* IPU_PIX_FMT_LVDS666 */
ipu_dc_map_clear(4);
ipu_dc_map_config(4, 0, 5, 0xFC);
ipu_dc_map_config(4, 1, 13, 0xFC);
ipu_dc_map_config(4, 2, 21, 0xFC);
}
int ipu_pixfmt_to_map(uint32_t fmt)
{
switch (fmt) {
case IPU_PIX_FMT_GENERIC:
case IPU_PIX_FMT_RGB24:
return 0;
case IPU_PIX_FMT_RGB666:
return 1;
case IPU_PIX_FMT_YUV444:
return 2;
case IPU_PIX_FMT_RGB565:
return 3;
case IPU_PIX_FMT_LVDS666:
return 4;
}
return -1;
}
/*
* This function is called to adapt synchronous LCD panel to IPU restriction.
*/
void adapt_panel_to_ipu_restricitions(uint32_t *pixel_clk,
uint16_t width, uint16_t height,
uint16_t h_start_width,
uint16_t h_end_width,
uint16_t v_start_width,
uint16_t *v_end_width)
{
if (*v_end_width < 2) {
uint16_t total_width = width + h_start_width + h_end_width;
uint16_t total_height_old = height + v_start_width +
(*v_end_width);
uint16_t total_height_new = height + v_start_width + 2;
*v_end_width = 2;
*pixel_clk = (*pixel_clk) * total_width * total_height_new /
(total_width * total_height_old);
printf("WARNING: adapt panel end blank lines\n");
}
}
/*
* This function is called to initialize a synchronous LCD panel.
*
* @param disp The DI the panel is attached to.
*
* @param pixel_clk Desired pixel clock frequency in Hz.
*
* @param pixel_fmt Input parameter for pixel format of buffer.
* Pixel format is a FOURCC ASCII code.
*
* @param width The width of panel in pixels.
*
* @param height The height of panel in pixels.
*
* @param hStartWidth The number of pixel clocks between the HSYNC
* signal pulse and the start of valid data.
*
* @param hSyncWidth The width of the HSYNC signal in units of pixel
* clocks.
*
* @param hEndWidth The number of pixel clocks between the end of
* valid data and the HSYNC signal for next line.
*
* @param vStartWidth The number of lines between the VSYNC
* signal pulse and the start of valid data.
*
* @param vSyncWidth The width of the VSYNC signal in units of lines
*
* @param vEndWidth The number of lines between the end of valid
* data and the VSYNC signal for next frame.
*
* @param sig Bitfield of signal polarities for LCD interface.
*
* @return This function returns 0 on success or negative error code on
* fail.
*/
int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
uint16_t width, uint16_t height,
uint32_t pixel_fmt,
uint16_t h_start_width, uint16_t h_sync_width,
uint16_t h_end_width, uint16_t v_start_width,
uint16_t v_sync_width, uint16_t v_end_width,
uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
{
uint32_t reg;
uint32_t di_gen, vsync_cnt;
uint32_t div, rounded_pixel_clk;
uint32_t h_total, v_total;
int map;
struct clk *di_parent;
debug("panel size = %d x %d\n", width, height);
if ((v_sync_width == 0) || (h_sync_width == 0))
return EINVAL;
adapt_panel_to_ipu_restricitions(&pixel_clk, width, height,
h_start_width, h_end_width,
v_start_width, &v_end_width);
h_total = width + h_sync_width + h_start_width + h_end_width;
v_total = height + v_sync_width + v_start_width + v_end_width;
/* Init clocking */
debug("pixel clk = %d\n", pixel_clk);
if (sig.ext_clk) {
if (!(g_di1_tvout && (disp == 1))) { /*not round div for tvout*/
/*
* Set the PLL to be an even multiple
* of the pixel clock.
*/
if ((clk_get_usecount(g_pixel_clk[0]) == 0) &&
(clk_get_usecount(g_pixel_clk[1]) == 0)) {
di_parent = clk_get_parent(g_di_clk[disp]);
rounded_pixel_clk =
clk_round_rate(g_pixel_clk[disp],
pixel_clk);
div = clk_get_rate(di_parent) /
rounded_pixel_clk;
if (div % 2)
div++;
if (clk_get_rate(di_parent) != div *
rounded_pixel_clk)
clk_set_rate(di_parent,
div * rounded_pixel_clk);
udelay(10000);
clk_set_rate(g_di_clk[disp],
2 * rounded_pixel_clk);
udelay(10000);
}
}
clk_set_parent(g_pixel_clk[disp], g_di_clk[disp]);
} else {
if (clk_get_usecount(g_pixel_clk[disp]) != 0)
clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
}
rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
udelay(5000);
/* Get integer portion of divider */
div = clk_get_rate(clk_get_parent(g_pixel_clk[disp])) /
rounded_pixel_clk;
ipu_di_data_wave_config(disp, SYNC_WAVE, div - 1, div - 1);
ipu_di_data_pin_config(disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
map = ipu_pixfmt_to_map(pixel_fmt);
if (map < 0) {
debug("IPU_DISP: No MAP\n");
return -EINVAL;
}
di_gen = __raw_readl(DI_GENERAL(disp));
if (sig.interlaced) {
/* Setup internal HSYNC waveform */
ipu_di_sync_config(
disp, /* display */
1, /* counter */
h_total / 2 - 1,/* run count */
DI_SYNC_CLK, /* run_resolution */
0, /* offset */
DI_SYNC_NONE, /* offset resolution */
0, /* repeat count */
DI_SYNC_NONE, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
0 /* COUNT DOWN */
);
/* Field 1 VSYNC waveform */
ipu_di_sync_config(
disp, /* display */
2, /* counter */
h_total - 1, /* run count */
DI_SYNC_CLK, /* run_resolution */
0, /* offset */
DI_SYNC_NONE, /* offset resolution */
0, /* repeat count */
DI_SYNC_NONE, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
4 /* COUNT DOWN */
);
/* Setup internal HSYNC waveform */
ipu_di_sync_config(
disp, /* display */
3, /* counter */
v_total * 2 - 1,/* run count */
DI_SYNC_INT_HSYNC, /* run_resolution */
1, /* offset */
DI_SYNC_INT_HSYNC, /* offset resolution */
0, /* repeat count */
DI_SYNC_NONE, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
4 /* COUNT DOWN */
);
/* Active Field ? */
ipu_di_sync_config(
disp, /* display */
4, /* counter */
v_total / 2 - 1,/* run count */
DI_SYNC_HSYNC, /* run_resolution */
v_start_width, /* offset */
DI_SYNC_HSYNC, /* offset resolution */
2, /* repeat count */
DI_SYNC_VSYNC, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
0 /* COUNT DOWN */
);
/* Active Line */
ipu_di_sync_config(
disp, /* display */
5, /* counter */
0, /* run count */
DI_SYNC_HSYNC, /* run_resolution */
0, /* offset */
DI_SYNC_NONE, /* offset resolution */
height / 2, /* repeat count */
4, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
0 /* COUNT DOWN */
);
/* Field 0 VSYNC waveform */
ipu_di_sync_config(
disp, /* display */
6, /* counter */
v_total - 1, /* run count */
DI_SYNC_HSYNC, /* run_resolution */
0, /* offset */
DI_SYNC_NONE, /* offset resolution */
0, /* repeat count */
DI_SYNC_NONE, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
0 /* COUNT DOWN */
);
/* DC VSYNC waveform */
vsync_cnt = 7;
ipu_di_sync_config(
disp, /* display */
7, /* counter */
v_total / 2 - 1,/* run count */
DI_SYNC_HSYNC, /* run_resolution */
9, /* offset */
DI_SYNC_HSYNC, /* offset resolution */
2, /* repeat count */
DI_SYNC_VSYNC, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
0 /* COUNT DOWN */
);
/* active pixel waveform */
ipu_di_sync_config(
disp, /* display */
8, /* counter */
0, /* run count */
DI_SYNC_CLK, /* run_resolution */
h_start_width, /* offset */
DI_SYNC_CLK, /* offset resolution */
width, /* repeat count */
5, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
0 /* COUNT DOWN */
);
ipu_di_sync_config(
disp, /* display */
9, /* counter */
v_total - 1, /* run count */
DI_SYNC_INT_HSYNC,/* run_resolution */
v_total / 2, /* offset */
DI_SYNC_INT_HSYNC,/* offset resolution */
0, /* repeat count */
DI_SYNC_HSYNC, /* CNT_CLR_SEL */
0, /* CNT_POLARITY_GEN_EN */
DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
0, /* COUNT UP */
4 /* COUNT DOWN */
);
/* set gentime select and tag sel */
reg = __raw_readl(DI_SW_GEN1(disp, 9));
reg &= 0x1FFFFFFF;
reg |= (3 - 1)<<29 | 0x00008000;
__raw_writel(reg, DI_SW_GEN1(disp, 9));
__raw_writel(v_total / 2 - 1, DI_SCR_CONF(disp));
/* set y_sel = 1 */
di_gen |= 0x10000000;
di_gen |= DI_GEN_POLARITY_5;
di_gen |= DI_GEN_POLARITY_8;
} else {
/* Setup internal HSYNC waveform */
ipu_di_sync_config(disp, 1, h_total - 1, DI_SYNC_CLK,
0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
0, DI_SYNC_NONE,
DI_SYNC_NONE, 0, 0);
/* Setup external (delayed) HSYNC waveform */
ipu_di_sync_config(disp, DI_SYNC_HSYNC, h_total - 1,
DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
DI_SYNC_CLK, 0, h_sync_width * 2);
/* Setup VSYNC waveform */
vsync_cnt = DI_SYNC_VSYNC;
ipu_di_sync_config(disp, DI_SYNC_VSYNC, v_total - 1,
DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
DI_SYNC_NONE, 1, DI_SYNC_NONE,
DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
__raw_writel(v_total - 1, DI_SCR_CONF(disp));
/* Setup active data waveform to sync with DC */
ipu_di_sync_config(disp, 4, 0, DI_SYNC_HSYNC,
v_sync_width + v_start_width, DI_SYNC_HSYNC,
height,
DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
DI_SYNC_NONE, 0, 0);
ipu_di_sync_config(disp, 5, 0, DI_SYNC_CLK,
h_sync_width + h_start_width, DI_SYNC_CLK,
width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
0);
/* reset all unused counters */
__raw_writel(0, DI_SW_GEN0(disp, 6));
__raw_writel(0, DI_SW_GEN1(disp, 6));
__raw_writel(0, DI_SW_GEN0(disp, 7));
__raw_writel(0, DI_SW_GEN1(disp, 7));
__raw_writel(0, DI_SW_GEN0(disp, 8));
__raw_writel(0, DI_SW_GEN1(disp, 8));
__raw_writel(0, DI_SW_GEN0(disp, 9));
__raw_writel(0, DI_SW_GEN1(disp, 9));
reg = __raw_readl(DI_STP_REP(disp, 6));
reg &= 0x0000FFFF;
__raw_writel(reg, DI_STP_REP(disp, 6));
__raw_writel(0, DI_STP_REP(disp, 7));
__raw_writel(0, DI_STP_REP(disp, 9));
/* Init template microcode */
if (disp) {
ipu_dc_write_tmpl(2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
ipu_dc_write_tmpl(3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
ipu_dc_write_tmpl(4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
} else {
ipu_dc_write_tmpl(5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
ipu_dc_write_tmpl(6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
ipu_dc_write_tmpl(7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
}
if (sig.Hsync_pol)
di_gen |= DI_GEN_POLARITY_2;
if (sig.Vsync_pol)
di_gen |= DI_GEN_POLARITY_3;
if (sig.clk_pol)
di_gen |= DI_GEN_POL_CLK;
}
__raw_writel(di_gen, DI_GENERAL(disp));
__raw_writel((--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
0x00000002, DI_SYNC_AS_GEN(disp));
reg = __raw_readl(DI_POL(disp));
reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
if (sig.enable_pol)
reg |= DI_POL_DRDY_POLARITY_15;
if (sig.data_pol)
reg |= DI_POL_DRDY_DATA_POLARITY;
__raw_writel(reg, DI_POL(disp));
__raw_writel(width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
return 0;
}
/*
* This function sets the foreground and background plane global alpha blending
* modes. This function also sets the DP graphic plane according to the
* parameter of IPUv3 DP channel.
*
* @param channel IPUv3 DP channel
*
* @param enable Boolean to enable or disable global alpha
* blending. If disabled, local blending is used.
*
* @param alpha Global alpha value.
*
* @return Returns 0 on success or negative error code on fail
*/
int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
uint8_t alpha)
{
uint32_t reg;
unsigned char bg_chan;
if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
(channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
(channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
return -EINVAL;
if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
channel == MEM_BG_ASYNC1)
bg_chan = 1;
else
bg_chan = 0;
if (!g_ipu_clk_enabled)
clk_enable(g_ipu_clk);
if (bg_chan) {
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF());
} else {
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg | DP_COM_CONF_GWSEL, DP_COM_CONF());
}
if (enable) {
reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
__raw_writel(reg | ((uint32_t) alpha << 24),
DP_GRAPH_WIND_CTRL());
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
} else {
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg & ~DP_COM_CONF_GWAM, DP_COM_CONF());
}
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
if (!g_ipu_clk_enabled)
clk_disable(g_ipu_clk);
return 0;
}
/*
* This function sets the transparent color key for SDC graphic plane.
*
* @param channel Input parameter for the logical channel ID.
*
* @param enable Boolean to enable or disable color key
*
* @param colorKey 24-bit RGB color for transparent color key.
*
* @return Returns 0 on success or negative error code on fail
*/
int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
uint32_t color_key)
{
uint32_t reg;
int y, u, v;
int red, green, blue;
if (!((channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) ||
(channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0) ||
(channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)))
return -EINVAL;
if (!g_ipu_clk_enabled)
clk_enable(g_ipu_clk);
color_key_4rgb = 1;
/* Transform color key from rgb to yuv if CSC is enabled */
if (((fg_csc_type == RGB2YUV) && (bg_csc_type == YUV2YUV)) ||
((fg_csc_type == YUV2YUV) && (bg_csc_type == RGB2YUV)) ||
((fg_csc_type == YUV2YUV) && (bg_csc_type == YUV2YUV)) ||
((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB))) {
debug("color key 0x%x need change to yuv fmt\n", color_key);
red = (color_key >> 16) & 0xFF;
green = (color_key >> 8) & 0xFF;
blue = color_key & 0xFF;
y = rgb_to_yuv(0, red, green, blue);
u = rgb_to_yuv(1, red, green, blue);
v = rgb_to_yuv(2, red, green, blue);
color_key = (y << 16) | (u << 8) | v;
color_key_4rgb = 0;
debug("color key change to yuv fmt 0x%x\n", color_key);
}
if (enable) {
reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFF000000L;
__raw_writel(reg | color_key, DP_GRAPH_WIND_CTRL());
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg | DP_COM_CONF_GWCKE, DP_COM_CONF());
} else {
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF());
}
reg = __raw_readl(IPU_SRM_PRI2) | 0x8;
__raw_writel(reg, IPU_SRM_PRI2);
if (!g_ipu_clk_enabled)
clk_disable(g_ipu_clk);
return 0;
}
|
1001-study-uboot
|
drivers/video/ipu_disp.c
|
C
|
gpl3
| 37,056
|
/*
* Porting to u-boot:
*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* Linux IPU driver for MX51:
*
* (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MXCFB_H__
#define __ASM_ARCH_MXCFB_H__
#define FB_SYNC_OE_LOW_ACT 0x80000000
#define FB_SYNC_CLK_LAT_FALL 0x40000000
#define FB_SYNC_DATA_INVERT 0x20000000
#define FB_SYNC_CLK_IDLE_EN 0x10000000
#define FB_SYNC_SHARP_MODE 0x08000000
#define FB_SYNC_SWAP_RGB 0x04000000
struct mxcfb_gbl_alpha {
int enable;
int alpha;
};
struct mxcfb_loc_alpha {
int enable;
int alpha_in_pixel;
unsigned long alpha_phy_addr0;
unsigned long alpha_phy_addr1;
};
struct mxcfb_color_key {
int enable;
__u32 color_key;
};
struct mxcfb_pos {
__u16 x;
__u16 y;
};
struct mxcfb_gamma {
int enable;
int constk[16];
int slopek[16];
};
#endif
|
1001-study-uboot
|
drivers/video/mxcfb.h
|
C
|
gpl3
| 1,656
|
/*
* (C) Copyright 1997-2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* smiLynxEM.c
*
* Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
*
* modification history
* --------------------
* 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
*
* 18-03-2004 - Unify videomodes handling with the ct69000
* - The video output can be set via the variable "videoout"
* in the environment.
* videoout=1 output on LCD
* videoout=2 output on CRT (default value)
* <p.aubert@staubli.com>
*/
#include <common.h>
#include <pci.h>
#include <video_fb.h>
#include "videomodes.h"
/*
* Export Graphic Device
*/
GraphicDevice smi;
/*
* SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external
*/
#define VIDEO_MEM_SIZE 0x400000
/*
* ISA mapped regs
*/
#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */
#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */
#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */
#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */
#define SMI_ISR1 (pGD->isaBase + 0x03ca)
#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */
#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */
#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */
#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */
#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */
#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */
#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/
#define SMI_INDX_ATTR (pGD->isaBase + 0x03c0) /* attributes index reg */
/*
* Video processor control
*/
typedef struct {
unsigned int control;
unsigned int colorKey;
unsigned int colorKeyMask;
unsigned int start;
unsigned short offset;
unsigned short width;
unsigned int fifoPrio;
unsigned int fifoERL;
unsigned int YUVtoRGB;
} SmiVideoProc;
/*
* Video window control
*/
typedef struct {
unsigned short top;
unsigned short left;
unsigned short bottom;
unsigned short right;
unsigned int srcStart;
unsigned short width;
unsigned short offset;
unsigned char hStretch;
unsigned char vStretch;
} SmiVideoWin;
/*
* Capture port control
*/
typedef struct {
unsigned int control;
unsigned short topClip;
unsigned short leftClip;
unsigned short srcHeight;
unsigned short srcWidth;
unsigned int srcBufStart1;
unsigned int srcBufStart2;
unsigned short srcOffset;
unsigned short fifoControl;
} SmiCapturePort;
/*
* Register values for common video modes
*/
static char SMI_SCR[] = {
/* all modes */
0x10, 0xff, 0x11, 0xff, 0x12, 0xff, 0x13, 0xff, 0x15, 0x90,
0x17, 0x20, 0x18, 0xb1, 0x19, 0x00,
};
static char SMI_EXT_CRT[] = {
0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00,
0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00,
};
static char SMI_ATTR [] = {
0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05,
0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0b,
0x0c, 0x0c, 0x0d, 0x0d, 0x0e, 0x0e, 0x0f, 0x0f, 0x10, 0x41, 0x11, 0x00,
0x12, 0x0f, 0x13, 0x00, 0x14, 0x00,
};
static char SMI_GCR[18] = {
0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x40,
0x06, 0x05, 0x07, 0x0f, 0x08, 0xff,
};
static char SMI_SEQR[] = {
0x00, 0x00, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e, 0x00, 0x03,
};
static char SMI_PCR [] = {
0x20, 0x04, 0x21, 0x30, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00,
};
static char SMI_MCR[] = {
0x60, 0x01, 0x61, 0x00,
#ifdef CONFIG_HMI1001
0x62, 0x74, /* Memory type is not configured by pins on HMI1001 */
#endif
};
static char SMI_HCR[] = {
0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00,
0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00,
};
/*******************************************************************************
*
* Write SMI ISA register
*/
static void smiWrite (unsigned short index, char reg, char val)
{
register GraphicDevice *pGD = (GraphicDevice *)&smi;
out8 ((pGD->isaBase + index), reg);
out8 ((pGD->isaBase + index + 1), val);
}
/*******************************************************************************
*
* Write a table of SMI ISA register
*/
static void smiLoadRegs (
unsigned int iReg,
unsigned int dReg,
char *regTab,
unsigned int tabSize
)
{
register GraphicDevice *pGD = (GraphicDevice *)&smi;
register int i;
for (i=0; i<tabSize; i+=2) {
if (iReg == SMI_INDX_ATTR) {
/* Reset the Flip Flop */
in8 (SMI_ISR1);
out8 (iReg, regTab[i]);
out8 (iReg, regTab[i+1]);
} else {
out8 (iReg, regTab[i]);
out8 (dReg, regTab[i+1]);
}
}
}
/*******************************************************************************
*
* Init capture port registers
*/
static void smiInitCapturePort (void)
{
SmiCapturePort smiCP = { 0x01400600, 0x30, 0x40, 480, 640, 0, 0, 2560, 6 };
register GraphicDevice *pGD = (GraphicDevice *)&smi;
register SmiCapturePort *pCP = (SmiCapturePort *)&smiCP;
out32r ((pGD->cprBase + 0x0004), ((pCP->topClip<<16) | pCP->leftClip));
out32r ((pGD->cprBase + 0x0008), ((pCP->srcHeight<<16) | pCP->srcWidth));
out32r ((pGD->cprBase + 0x000c), pCP->srcBufStart1/8);
out32r ((pGD->cprBase + 0x0010), pCP->srcBufStart2/8);
out32r ((pGD->cprBase + 0x0014), pCP->srcOffset/8);
out32r ((pGD->cprBase + 0x0018), pCP->fifoControl);
out32r ((pGD->cprBase + 0x0000), pCP->control);
}
/*******************************************************************************
*
* Init video processor registers
*/
static void smiInitVideoProcessor (void)
{
SmiVideoProc smiVP = { 0x100000, 0, 0, 0, 0, 1600, 0x1200543, 4, 0xededed };
SmiVideoWin smiVW = { 0, 0, 599, 799, 0, 1600, 0, 0, 0 };
register GraphicDevice *pGD = (GraphicDevice *)&smi;
register SmiVideoProc *pVP = (SmiVideoProc *)&smiVP;
register SmiVideoWin *pVWin = (SmiVideoWin *)&smiVW;
pVP->width = pGD->plnSizeX * pGD->gdfBytesPP;
pVP->control |= pGD->gdfIndex << 16;
pVWin->bottom = pGD->winSizeY - 1;
pVWin->right = pGD->winSizeX - 1;
pVWin->width = pVP->width;
/* color key */
out32r ((pGD->vprBase + 0x0004), pVP->colorKey);
/* color key mask */
out32r ((pGD->vprBase + 0x0008), pVP->colorKeyMask);
/* data src start adrs */
out32r ((pGD->vprBase + 0x000c), pVP->start / 8);
/* data width and offset */
out32r ((pGD->vprBase + 0x0010),
((pVP->offset / 8 * pGD->gdfBytesPP) << 16) |
(pGD->plnSizeX / 8 * pGD->gdfBytesPP));
/* video window 1 */
out32r ((pGD->vprBase + 0x0014),
((pVWin->top << 16) | pVWin->left));
out32r ((pGD->vprBase + 0x0018),
((pVWin->bottom << 16) | pVWin->right));
out32r ((pGD->vprBase + 0x001c), pVWin->srcStart / 8);
out32r ((pGD->vprBase + 0x0020),
(((pVWin->offset / 8) << 16) | (pVWin->width / 8)));
out32r ((pGD->vprBase + 0x0024),
(((pVWin->hStretch) << 8) | pVWin->vStretch));
/* video window 2 */
out32r ((pGD->vprBase + 0x0028),
((pVWin->top << 16) | pVWin->left));
out32r ((pGD->vprBase + 0x002c),
((pVWin->bottom << 16) | pVWin->right));
out32r ((pGD->vprBase + 0x0030),
pVWin->srcStart / 8);
out32r ((pGD->vprBase + 0x0034),
(((pVWin->offset / 8) << 16) | (pVWin->width / 8)));
out32r ((pGD->vprBase + 0x0038),
(((pVWin->hStretch) << 8) | pVWin->vStretch));
/* fifo prio control */
out32r ((pGD->vprBase + 0x0054), pVP->fifoPrio);
/* fifo empty request levell */
out32r ((pGD->vprBase + 0x0058), pVP->fifoERL);
/* conversion constant */
out32r ((pGD->vprBase + 0x005c), pVP->YUVtoRGB);
/* vpr control word */
out32r ((pGD->vprBase + 0x0000), pVP->control);
}
/******************************************************************************
*
* Init drawing engine registers
*/
static void smiInitDrawingEngine (void)
{
GraphicDevice *pGD = (GraphicDevice *)&smi;
unsigned int val;
/* don't start now */
out32r ((pGD->dprBase + 0x000c), 0x000f0000);
/* set rop2 to copypen */
val = 0xffff3ff0 & in32r ((pGD->dprBase + 0x000c));
out32r ((pGD->dprBase + 0x000c), (val | 0x8000 | 0x0c));
/* set clip rect */
out32r ((pGD->dprBase + 0x002c), 0);
out32r ((pGD->dprBase + 0x0030),
((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP ));
/* src row pitch */
val = 0xffff0000 & (in32r ((pGD->dprBase + 0x0010)));
out32r ((pGD->dprBase + 0x0010),
(val | pGD->plnSizeX * pGD->gdfBytesPP));
/* dst row pitch */
val = 0x0000ffff & (in32r ((pGD->dprBase + 0x0010)));
out32r ((pGD->dprBase + 0x0010),
(((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val));
/* window width src/dst */
out32r ((pGD->dprBase + 0x003c),
(((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) |
(pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)));
out16r ((pGD->dprBase + 0x001e), 0x0000);
/* src base adrs */
out32r ((pGD->dprBase + 0x0040),
(((pGD->frameAdrs/8) & 0x000fffff)));
/* dst base adrs */
out32r ((pGD->dprBase + 0x0044),
(((pGD->frameAdrs/8) & 0x000fffff)));
/* foreground color */
out32r ((pGD->dprBase + 0x0014), pGD->fg);
/* background color */
out32r ((pGD->dprBase + 0x0018), pGD->bg);
/* xcolor */
out32r ((pGD->dprBase + 0x0020), 0x00ffffff);
/* xcolor mask */
out32r ((pGD->dprBase + 0x0024), 0x00ffffff);
/* bit mask */
out32r ((pGD->dprBase + 0x0028), 0x00ffffff);
/* load mono pattern */
out32r ((pGD->dprBase + 0x0034), 0);
out32r ((pGD->dprBase + 0x0038), 0);
}
static struct pci_device_id supported[] = {
{ PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_710 },
{ PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_712 },
{ PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_810 },
{ }
};
/*****************************************************************************/
static void smiLoadMsr (struct ctfb_res_modes *mode)
{
unsigned char h_synch_high, v_synch_high;
register GraphicDevice *pGD = (GraphicDevice *)&smi;
h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */
v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */
out8 (SMI_MISC_REG, (h_synch_high | v_synch_high | 0x29));
/* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
* Selects the upper 64KB page.Bit5=1
* CLK2 (left reserved in standard VGA) Bit3|2=1|0
* Disables CPU access to frame buffer. Bit1=0
* Sets the I/O address decode for ST01, FCR, and all CR registers
* to the 3Dx I/O address range (CGA emulation). Bit0=1
*/
}
/*****************************************************************************/
static void smiLoadCrt (struct ctfb_res_modes *var, int bits_per_pixel)
{
unsigned char cr[0x7a];
int i;
unsigned int hd, hs, he, ht, hbs, hbe; /* Horizontal. */
unsigned int vd, vs, ve, vt, vbs, vbe; /* vertical */
unsigned int bpp, wd, dblscan, interlaced;
const int LineCompare = 0x3ff;
unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */
register GraphicDevice *pGD = (GraphicDevice *)&smi;
/* Horizontal */
hd = (var->xres) / 8; /* HDisp. */
hs = (var->xres + var->right_margin) / 8; /* HsStrt */
he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */
ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */
/* Blank */
hbs = hd;
hbe = 0; /* Blank end at 0 */
/* Vertical */
vd = var->yres; /* VDisplay */
vs = var->yres + var->lower_margin; /* VSyncStart */
ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */
vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */
vbs = vd;
vbe = 0;
bpp = bits_per_pixel;
dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0;
interlaced = var->vmode & FB_VMODE_INTERLACED;
if (bpp == 15)
bpp = 16;
wd = var->xres * bpp / 64; /* double words per line */
if (interlaced) { /* we divide all vertical timings, exept vd */
vs >>= 1;
vbs >>= 1;
ve >>= 1;
vt >>= 1;
}
memset (cr, 0, sizeof (cr));
cr[0x00] = ht - 5;
cr[0x01] = hd - 1;
cr[0x02] = hbs - 1;
cr[0x03] = (hbe & 0x1F);
cr[0x04] = hs;
cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
cr[0x06] = (vt - 2) & 0xFF;
cr[0x07] = (((vt - 2) & 0x100) >> 8)
| (((vd - 1) & 0x100) >> 7)
| ((vs & 0x100) >> 6)
| (((vbs - 1) & 0x100) >> 5)
| ((LineCompare & 0x100) >> 4)
| (((vt - 2) & 0x200) >> 4)
| (((vd - 1) & 0x200) >> 3)
| ((vs & 0x200) >> 2);
cr[0x30] = ((vt - 2) & 0x400) >> 7
| (((vd - 1) & 0x400) >> 8)
| (((vbs - 1) & 0x400) >> 9)
| ((vs & 0x400) >> 10)
| (interlaced) ? 0x80 : 0;
cr[0x08] = 0x00;
cr[0x09] = (dblscan << 7)
| ((LineCompare & 0x200) >> 3)
| (((vbs - 1) & 0x200) >> 4)
| (TextScanLines - 1);
cr[0x10] = vs & 0xff; /* VSyncPulseStart */
cr[0x11] = (ve & 0x0f);
cr[0x12] = (vd - 1) & 0xff; /* LineCount */
cr[0x13] = wd & 0xff;
cr[0x14] = 0x40;
cr[0x15] = (vbs - 1) & 0xff;
cr[0x16] = vbe & 0xff;
cr[0x17] = 0xe3; /* but it does not work */
cr[0x18] = 0xff & LineCompare;
cr[0x22] = 0x00; /* todo? */
/* now set the registers */
for (i = 0; i <= 0x18; i++) { /*CR00 .. CR18 */
smiWrite (SMI_INDX_D4, i, cr[i]);
}
i = 0x22; /*CR22 */
smiWrite (SMI_INDX_D4, i, cr[i]);
i = 0x30; /*CR30 */
smiWrite (SMI_INDX_D4, i, cr[i]);
}
/*****************************************************************************/
#define REF_FREQ 14318180
#define PMIN 1
#define PMAX 255
#define QMIN 1
#define QMAX 63
static unsigned int FindPQ (unsigned int freq, unsigned int *pp, unsigned int *pq)
{
unsigned int n = QMIN, m = 0;
long long int L = 0, P = freq, Q = REF_FREQ, H = P >> 1;
long long int D = 0x7ffffffffffffffLL;
for (n = QMIN; n <= QMAX; n++) {
m = PMIN; /* p/q ~ freq/ref -> p*ref-freq*q ~ 0 */
L = P * n - m * Q;
while (L > 0 && m < PMAX) {
L -= REF_FREQ; /* difference is greater as 0 subtract fref */
m++; /* and increment m */
}
/* difference is less or equal than 0 or m > maximum */
if (m > PMAX)
break; /* no solution: if we increase n we get the same situation */
/* L is <= 0 now */
if (-L > H && m > PMIN) { /* if difference > the half fref */
L += REF_FREQ; /* we take the situation before */
m--; /* because its closer to 0 */
}
L = (L < 0) ? -L : +L; /* absolute value */
if (D < L) /* if last difference was better take next n */
continue;
D = L;
*pp = m;
*pq = n; /* keep improved data */
if (D == 0)
break; /* best result we can get */
}
return (unsigned int) (0xffffffff & D);
}
/*****************************************************************************/
static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id)
{
unsigned int p = 0;
unsigned int q = 0;
long long freq;
register GraphicDevice *pGD = (GraphicDevice *)&smi;
smiWrite (SMI_INDX_C4, 0x65, 0);
smiWrite (SMI_INDX_C4, 0x66, 0);
smiWrite (SMI_INDX_C4, 0x68, 0x50);
if (device_id == PCI_DEVICE_ID_SMI_810) {
smiWrite (SMI_INDX_C4, 0x69, 0x3);
} else {
smiWrite (SMI_INDX_C4, 0x69, 0x0);
}
/* Memory clock */
switch (device_id) {
case PCI_DEVICE_ID_SMI_710 :
smiWrite (SMI_INDX_C4, 0x6a, 0x75);
break;
case PCI_DEVICE_ID_SMI_712 :
smiWrite (SMI_INDX_C4, 0x6a, 0x80);
break;
default :
smiWrite (SMI_INDX_C4, 0x6a, 0x53);
break;
}
smiWrite (SMI_INDX_C4, 0x6b, 0x15);
/* VCLK */
freq = 1000000000000LL / var -> pixclock;
FindPQ ((unsigned int)freq, &p, &q);
smiWrite (SMI_INDX_C4, 0x6c, p);
smiWrite (SMI_INDX_C4, 0x6d, q);
}
/*******************************************************************************
*
* Init video chip with common Linux graphic modes (lilo)
*/
void *video_hw_init (void)
{
GraphicDevice *pGD = (GraphicDevice *)&smi;
unsigned short device_id;
pci_dev_t devbusfn;
int videomode;
unsigned long t1, hsynch, vsynch;
unsigned int pci_mem_base, *vm;
char *penv;
int tmp, i, bits_per_pixel;
struct ctfb_res_modes *res_mode;
struct ctfb_res_modes var_mode;
unsigned char videoout;
/* Search for video chip */
printf("Video: ");
if ((devbusfn = pci_find_devices(supported, 0)) < 0)
{
printf ("Controller not found !\n");
return (NULL);
}
/* PCI setup */
pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
tmp = 0;
videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
/* get video mode via environment */
if ((penv = getenv ("videomode")) != NULL) {
/* deceide if it is a string */
if (penv[0] <= '9') {
videomode = (int) simple_strtoul (penv, NULL, 16);
tmp = 1;
}
} else {
tmp = 1;
}
if (tmp) {
/* parameter are vesa modes */
/* search params */
for (i = 0; i < VESA_MODES_COUNT; i++) {
if (vesa_modes[i].vesanr == videomode)
break;
}
if (i == VESA_MODES_COUNT) {
printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE);
i = 0;
}
res_mode =
(struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].
resindex];
bits_per_pixel = vesa_modes[i].bits_per_pixel;
} else {
res_mode = (struct ctfb_res_modes *) &var_mode;
bits_per_pixel = video_get_params (res_mode, penv);
}
/* calculate hsynch and vsynch freq (info only) */
t1 = (res_mode->left_margin + res_mode->xres +
res_mode->right_margin + res_mode->hsync_len) / 8;
t1 *= 8;
t1 *= res_mode->pixclock;
t1 /= 1000;
hsynch = 1000000000L / t1;
t1 *=
(res_mode->upper_margin + res_mode->yres +
res_mode->lower_margin + res_mode->vsync_len);
t1 /= 1000;
vsynch = 1000000000L / t1;
/* fill in Graphic device struct */
sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
res_mode->yres, bits_per_pixel, (hsynch / 1000),
(vsynch / 1000));
printf ("%s\n", pGD->modeIdent);
pGD->winSizeX = res_mode->xres;
pGD->winSizeY = res_mode->yres;
pGD->plnSizeX = res_mode->xres;
pGD->plnSizeY = res_mode->yres;
switch (bits_per_pixel) {
case 8:
pGD->gdfBytesPP = 1;
pGD->gdfIndex = GDF__8BIT_INDEX;
break;
case 15:
pGD->gdfBytesPP = 2;
pGD->gdfIndex = GDF_15BIT_555RGB;
break;
case 16:
pGD->gdfBytesPP = 2;
pGD->gdfIndex = GDF_16BIT_565RGB;
break;
case 24:
pGD->gdfBytesPP = 3;
pGD->gdfIndex = GDF_24BIT_888RGB;
break;
}
pGD->isaBase = CONFIG_SYS_ISA_IO;
pGD->pciBase = pci_mem_base;
pGD->dprBase = (pci_mem_base + 0x400000 + 0x8000);
pGD->vprBase = (pci_mem_base + 0x400000 + 0xc000);
pGD->cprBase = (pci_mem_base + 0x400000 + 0xe000);
pGD->frameAdrs = pci_mem_base;
pGD->memSize = VIDEO_MEM_SIZE;
/* Set up hardware : select color mode,
set Register base to isa 3dx for 3?x regs*/
out8 (SMI_MISC_REG, 0x01);
/* Turn off display */
smiWrite (SMI_INDX_C4, 0x01, 0x20);
/* Unlock ext. crt regs */
out8 (SMI_LOCK_REG, 0x40);
/* Unlock crt regs 0-7 */
smiWrite (SMI_INDX_D4, 0x11, 0x0e);
/* Sytem Control Register */
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SCR, sizeof(SMI_SCR));
/* extented CRT Register */
smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, SMI_EXT_CRT, sizeof(SMI_EXT_CRT));
/* Attributes controller registers */
smiLoadRegs (SMI_INDX_ATTR, SMI_INDX_ATTR, SMI_ATTR, sizeof(SMI_ATTR));
/* Graphics Controller Register */
smiLoadRegs (SMI_INDX_CE, SMI_DATA_CF, SMI_GCR, sizeof(SMI_GCR));
/* Sequencer Register */
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SEQR, sizeof(SMI_SEQR));
/* Power Control Register */
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_PCR, sizeof(SMI_PCR));
/* Memory Control Register */
/* Register MSR62 is a power on configurable register. We don't */
/* modify it */
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_MCR, sizeof(SMI_MCR));
/* Set misc output register */
smiLoadMsr (res_mode);
/* Set CRT and Clock control registers */
smiLoadCrt (res_mode, bits_per_pixel);
smiLoadCcr (res_mode, device_id);
/* Hardware Cusor Register */
smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_HCR, sizeof(SMI_HCR));
/* Enable Display */
videoout = 2; /* Default output is CRT */
if ((penv = getenv ("videoout")) != NULL) {
/* deceide if it is a string */
videoout = (int) simple_strtoul (penv, NULL, 16);
}
smiWrite (SMI_INDX_C4, 0x31, videoout);
/* Video processor default setup */
smiInitVideoProcessor ();
/* Capture port default setup */
smiInitCapturePort ();
/* Drawing engine default setup */
smiInitDrawingEngine ();
/* Turn on display */
smiWrite (0x3c4, 0x01, 0x01);
/* Clear video memory */
i = pGD->memSize/4;
vm = (unsigned int *)pGD->pciBase;
while(i--)
*vm++ = 0;
return ((void*)&smi);
}
/*******************************************************************************
*
* Drawing engine fill on screen region
*/
void video_hw_rectfill (
unsigned int bpp, /* bytes per pixel */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y, /* frame height */
unsigned int color /* fill color */
)
{
register GraphicDevice *pGD = (GraphicDevice *)&smi;
register unsigned int control;
dim_x *= bpp;
out32r ((pGD->dprBase + 0x0014), color);
out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y));
out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y));
control = 0x0000ffff & in32r ((pGD->dprBase + 0x000c));
control |= 0x80010000;
out32r ((pGD->dprBase + 0x000c), control);
/* Wait for drawing processor */
do
{
out8 ((pGD->isaBase + 0x3c4), 0x16);
} while (in8 (pGD->isaBase + 0x3c5) & 0x08);
}
/*******************************************************************************
*
* Drawing engine bitblt with screen region
*/
void video_hw_bitblt (
unsigned int bpp, /* bytes per pixel */
unsigned int src_x, /* source pos x */
unsigned int src_y, /* source pos y */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y /* frame height */
)
{
register GraphicDevice *pGD = (GraphicDevice *)&smi;
register unsigned int control;
dim_x *= bpp;
if ((src_y<dst_y) || ((src_y==dst_y) && (src_x<dst_x)))
{
out32r ((pGD->dprBase + 0x0000), (((src_x+dim_x-1)<<16) | (src_y+dim_y-1)));
out32r ((pGD->dprBase + 0x0004), (((dst_x+dim_x-1)<<16) | (dst_y+dim_y-1)));
control = 0x88000000;
} else {
out32r ((pGD->dprBase + 0x0000), ((src_x<<16) | src_y));
out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y));
control = 0x80000000;
}
out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y));
control |= (0x0000ffff & in32r ((pGD->dprBase + 0x000c)));
out32r ((pGD->dprBase + 0x000c), control);
/* Wait for drawing processor */
do
{
out8 ((pGD->isaBase + 0x3c4), 0x16);
} while (in8 (pGD->isaBase + 0x3c5) & 0x08);
}
/*******************************************************************************
*
* Set a RGB color in the LUT (8 bit index)
*/
void video_set_lut (
unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
)
{
register GraphicDevice *pGD = (GraphicDevice *)&smi;
out8 (SMI_LUT_MASK, 0xff);
out8 (SMI_LUT_START, (char)index);
out8 (SMI_LUT_RGB, r>>2); /* red */
udelay (10);
out8 (SMI_LUT_RGB, g>>2); /* green */
udelay (10);
out8 (SMI_LUT_RGB, b>>2); /* blue */
udelay (10);
}
|
1001-study-uboot
|
drivers/video/smiLynxEM.c
|
C
|
gpl3
| 24,232
|
/*
* (C) Copyright 2003
*
* Pantelis Antoniou <panto@intracom.gr>
* Intracom S.A.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <sed156x.h>
/* configure according to the selected display */
#if defined(CONFIG_SED156X_PG12864Q)
#define LCD_WIDTH 128
#define LCD_HEIGHT 64
#define LCD_LINES 64
#define LCD_PAGES 9
#define LCD_COLUMNS 132
#else
#error Unsupported SED156x configuration
#endif
/* include the font data */
#include <video_font.h>
#include <video_font_data.h>
#if VIDEO_FONT_WIDTH != 8 || VIDEO_FONT_HEIGHT != 16
#error Expecting VIDEO_FONT_WIDTH == 8 && VIDEO_FONT_HEIGHT == 16
#endif
#define LCD_BYTE_WIDTH (LCD_WIDTH / 8)
#define VIDEO_FONT_BYTE_WIDTH (VIDEO_FONT_WIDTH / 8)
#define LCD_TEXT_WIDTH (LCD_WIDTH / VIDEO_FONT_WIDTH)
#define LCD_TEXT_HEIGHT (LCD_HEIGHT / VIDEO_FONT_HEIGHT)
#define LCD_BYTE_LINESZ (LCD_BYTE_WIDTH * VIDEO_FONT_HEIGHT)
const int sed156x_text_width = LCD_TEXT_WIDTH;
const int sed156x_text_height = LCD_TEXT_HEIGHT;
/**************************************************************************************/
#define SED156X_SPI_RXD() (SED156X_SPI_RXD_PORT & SED156X_SPI_RXD_MASK)
#define SED156X_SPI_TXD(x) \
do { \
if (x) \
SED156X_SPI_TXD_PORT |= SED156X_SPI_TXD_MASK; \
else \
SED156X_SPI_TXD_PORT &= ~SED156X_SPI_TXD_MASK; \
} while(0)
#define SED156X_SPI_CLK(x) \
do { \
if (x) \
SED156X_SPI_CLK_PORT |= SED156X_SPI_CLK_MASK; \
else \
SED156X_SPI_CLK_PORT &= ~SED156X_SPI_CLK_MASK; \
} while(0)
#define SED156X_SPI_CLK_TOGGLE() (SED156X_SPI_CLK_PORT ^= SED156X_SPI_CLK_MASK)
#define SED156X_SPI_BIT_DELAY() /* no delay */
#define SED156X_CS(x) \
do { \
if (x) \
SED156X_CS_PORT |= SED156X_CS_MASK; \
else \
SED156X_CS_PORT &= ~SED156X_CS_MASK; \
} while(0)
#define SED156X_A0(x) \
do { \
if (x) \
SED156X_A0_PORT |= SED156X_A0_MASK; \
else \
SED156X_A0_PORT &= ~SED156X_A0_MASK; \
} while(0)
/**************************************************************************************/
/*** LCD Commands ***/
#define LCD_ON 0xAF /* Display ON */
#define LCD_OFF 0xAE /* Display OFF */
#define LCD_LADDR 0x40 /* Display start line set + (6-bit) address */
#define LCD_PADDR 0xB0 /* Page address set + (4-bit) page */
#define LCD_CADRH 0x10 /* Column address set upper + (4-bit) column hi */
#define LCD_CADRL 0x00 /* Column address set lower + (4-bit) column lo */
#define LCD_ADC_NRM 0xA0 /* ADC select Normal */
#define LCD_ADC_REV 0xA1 /* ADC select Reverse */
#define LCD_DSP_NRM 0xA6 /* LCD display Normal */
#define LCD_DSP_REV 0xA7 /* LCD display Reverse */
#define LCD_DPT_NRM 0xA4 /* Display all points Normal */
#define LCD_DPT_ALL 0xA5 /* Display all points ON */
#define LCD_BIAS9 0xA2 /* LCD bias set 1/9 */
#define LCD_BIAS7 0xA3 /* LCD bias set 1/7 */
#define LCD_CAINC 0xE0 /* Read/modify/write */
#define LCD_CAEND 0xEE /* End */
#define LCD_RESET 0xE2 /* Reset */
#define LCD_C_NRM 0xC0 /* Common output mode select Normal direction */
#define LCD_C_RVS 0xC8 /* Common output mode select Reverse direction */
#define LCD_PWRMD 0x28 /* Power control set + (3-bit) mode */
#define LCD_RESRT 0x20 /* V5 v. reg. int. resistor ratio set + (3-bit) ratio */
#define LCD_EVSET 0x81 /* Electronic volume mode set + byte = (6-bit) volume */
#define LCD_SIOFF 0xAC /* Static indicator OFF */
#define LCD_SION 0xAD /* Static indicator ON + byte = (2-bit) mode */
#define LCD_NOP 0xE3 /* NOP */
#define LCD_TEST 0xF0 /* Test/Test mode reset (Note: *DO NOT USE*) */
/*-------------------------------------------------------------------------------
Compound commands
-------------------------------------------------------------------------------
Command Description Commands
---------- ------------------------ -------------------------------------
POWS_ON POWER SAVER ON command LCD_OFF, LCD_D_ALL
POWS_OFF POWER SAVER OFF command LCD_D_NRM
SLEEPON SLEEP mode LCD_SIOFF, POWS_ON
SLEEPOFF SLEEP mode cancel LCD_D_NRM, LCD_SION, LCD_SIS_???
STDBYON STAND BY mode LCD_SION, POWS_ON
STDBYOFF STAND BY mode cancel LCD_D_NRM
-------------------------------------------------------------------------------*/
/*** LCD various parameters ***/
#define LCD_PPB 8 /* Pixels per byte (display is B/W, 1 bit per pixel) */
/*** LCD Status byte masks ***/
#define LCD_S_BUSY 0x80 /* Status Read - BUSY mask */
#define LCD_S_ADC 0x40 /* Status Read - ADC mask */
#define LCD_S_ONOFF 0x20 /* Status Read - ON/OFF mask */
#define LCD_S_RESET 0x10 /* Status Read - RESET mask */
/*** LCD commands parameter masks ***/
#define LCD_M_LADDR 0x3F /* Display start line (6-bit) address mask */
#define LCD_M_PADDR 0x0F /* Page address (4-bit) page mask */
#define LCD_M_CADRH 0x0F /* Column address upper (4-bit) column hi mask */
#define LCD_M_CADRL 0x0F /* Column address lower (4-bit) column lo mask */
#define LCD_M_PWRMD 0x07 /* Power control (3-bit) mode mask */
#define LCD_M_RESRT 0x07 /* V5 v. reg. int. resistor ratio (3-bit) ratio mask */
#define LCD_M_EVSET 0x3F /* Electronic volume mode byte (6-bit) volume mask */
#define LCD_M_SION 0x03 /* Static indicator ON (2-bit) mode mask */
/*** LCD Power control cirquits control masks ***/
#define LCD_PWRBSTR 0x04 /* Power control mode - Booster cirquit ON */
#define LCD_PWRVREG 0x02 /* Power control mode - Voltage regulator cirquit ON */
#define LCD_PWRVFOL 0x01 /* Power control mode - Voltage follower cirquit ON */
/*** LCD Static indicator states ***/
#define LCD_SIS_OFF 0x00 /* Static indicator register set - OFF state */
#define LCD_SIS_BL 0x01 /* Static indicator register set - 1s blink state */
#define LCD_SIS_RBL 0x02 /* Static indicator register set - .5s rapid blink state */
#define LCD_SIS_ON 0x03 /* Static indicator register set - constantly on state */
/*** LCD functions special parameters (commands) ***/
#define LCD_PREVP 0x80 /* Page number for moving to previous */
#define LCD_NEXTP 0x81 /* or next page */
#define LCD_ERR_P 0xFF /* Error in page number */
/*** LCD initialization settings ***/
#define LCD_BIAS LCD_BIAS9 /* Bias: 1/9 */
#define LCD_ADCMODE LCD_ADC_NRM /* ADC mode: normal */
#define LCD_COMDIR LCD_C_NRM /* Common output mode: normal */
#define LCD_RRATIO 0 /* Resistor ratio: 0 */
#define LCD_CNTRST 0x1C /* electronic volume: 1Ch */
#define LCD_POWERM (LCD_PWRBSTR | LCD_PWRVREG | LCD_PWRVFOL) /* Power mode: All on */
/**************************************************************************************/
static inline unsigned int sed156x_transfer(unsigned int val)
{
unsigned int rx;
int b;
rx = 0; b = 8;
while (--b >= 0) {
SED156X_SPI_TXD(val & 0x80);
val <<= 1;
SED156X_SPI_CLK_TOGGLE();
SED156X_SPI_BIT_DELAY();
rx <<= 1;
if (SED156X_SPI_RXD())
rx |= 1;
SED156X_SPI_CLK_TOGGLE();
SED156X_SPI_BIT_DELAY();
}
return rx;
}
unsigned int sed156x_data_transfer(unsigned int val)
{
unsigned int rx;
SED156X_SPI_CLK(1);
SED156X_CS(0);
SED156X_A0(1);
rx = sed156x_transfer(val);
SED156X_CS(1);
return rx;
}
void sed156x_data_block_transfer(const u8 *p, int size)
{
SED156X_SPI_CLK(1);
SED156X_CS(0);
SED156X_A0(1);
while (--size >= 0)
sed156x_transfer(*p++);
SED156X_CS(1);
}
unsigned int sed156x_cmd_transfer(unsigned int val)
{
unsigned int rx;
SED156X_SPI_CLK(1);
SED156X_CS(0);
SED156X_A0(0);
rx = sed156x_transfer(val);
SED156X_CS(1);
SED156X_A0(1);
return rx;
}
/******************************************************************************/
static u8 hw_screen[LCD_PAGES][LCD_COLUMNS];
static u8 last_hw_screen[LCD_PAGES][LCD_COLUMNS];
static u8 sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT];
void sed156x_sync(void)
{
int i, j, last_page;
u8 *d;
const u8 *s, *e, *b, *r;
u8 v0, v1, v2, v3, v4, v5, v6, v7;
/* copy and rotate sw_screen to hw_screen */
for (i = 0; i < LCD_HEIGHT / 8; i++) {
d = &hw_screen[i][0];
s = &sw_screen[LCD_BYTE_WIDTH * 8 * i + LCD_BYTE_WIDTH - 1];
for (j = 0; j < LCD_WIDTH / 8; j++) {
v0 = s[0 * LCD_BYTE_WIDTH];
v1 = s[1 * LCD_BYTE_WIDTH];
v2 = s[2 * LCD_BYTE_WIDTH];
v3 = s[3 * LCD_BYTE_WIDTH];
v4 = s[4 * LCD_BYTE_WIDTH];
v5 = s[5 * LCD_BYTE_WIDTH];
v6 = s[6 * LCD_BYTE_WIDTH];
v7 = s[7 * LCD_BYTE_WIDTH];
d[0] = ((v7 & 0x01) << 7) |
((v6 & 0x01) << 6) |
((v5 & 0x01) << 5) |
((v4 & 0x01) << 4) |
((v3 & 0x01) << 3) |
((v2 & 0x01) << 2) |
((v1 & 0x01) << 1) |
(v0 & 0x01) ;
d[1] = ((v7 & 0x02) << 6) |
((v6 & 0x02) << 5) |
((v5 & 0x02) << 4) |
((v4 & 0x02) << 3) |
((v3 & 0x02) << 2) |
((v2 & 0x02) << 1) |
((v1 & 0x02) << 0) |
((v0 & 0x02) >> 1) ;
d[2] = ((v7 & 0x04) << 5) |
((v6 & 0x04) << 4) |
((v5 & 0x04) << 3) |
((v4 & 0x04) << 2) |
((v3 & 0x04) << 1) |
(v2 & 0x04) |
((v1 & 0x04) >> 1) |
((v0 & 0x04) >> 2) ;
d[3] = ((v7 & 0x08) << 4) |
((v6 & 0x08) << 3) |
((v5 & 0x08) << 2) |
((v4 & 0x08) << 1) |
(v3 & 0x08) |
((v2 & 0x08) >> 1) |
((v1 & 0x08) >> 2) |
((v0 & 0x08) >> 3) ;
d[4] = ((v7 & 0x10) << 3) |
((v6 & 0x10) << 2) |
((v5 & 0x10) << 1) |
(v4 & 0x10) |
((v3 & 0x10) >> 1) |
((v2 & 0x10) >> 2) |
((v1 & 0x10) >> 3) |
((v0 & 0x10) >> 4) ;
d[5] = ((v7 & 0x20) << 2) |
((v6 & 0x20) << 1) |
(v5 & 0x20) |
((v4 & 0x20) >> 1) |
((v3 & 0x20) >> 2) |
((v2 & 0x20) >> 3) |
((v1 & 0x20) >> 4) |
((v0 & 0x20) >> 5) ;
d[6] = ((v7 & 0x40) << 1) |
(v6 & 0x40) |
((v5 & 0x40) >> 1) |
((v4 & 0x40) >> 2) |
((v3 & 0x40) >> 3) |
((v2 & 0x40) >> 4) |
((v1 & 0x40) >> 5) |
((v0 & 0x40) >> 6) ;
d[7] = (v7 & 0x80) |
((v6 & 0x80) >> 1) |
((v5 & 0x80) >> 2) |
((v4 & 0x80) >> 3) |
((v3 & 0x80) >> 4) |
((v2 & 0x80) >> 5) |
((v1 & 0x80) >> 6) |
((v0 & 0x80) >> 7) ;
d += 8;
s--;
}
}
/* and now output only the differences */
for (i = 0; i < LCD_PAGES; i++) {
b = &hw_screen[i][0];
e = &hw_screen[i][LCD_COLUMNS];
d = &last_hw_screen[i][0];
s = b;
last_page = -1;
/* update only the differences */
do {
while (s < e && *s == *d) {
s++;
d++;
}
if (s == e)
break;
r = s;
while (s < e && *s != *d)
*d++ = *s++;
j = r - b;
if (i != last_page) {
sed156x_cmd_transfer(LCD_PADDR | i);
last_page = i;
}
sed156x_cmd_transfer(LCD_CADRH | ((j >> 4) & 0x0F));
sed156x_cmd_transfer(LCD_CADRL | (j & 0x0F));
sed156x_data_block_transfer(r, s - r);
} while (s < e);
}
/********
for (i = 0; i < LCD_PAGES; i++) {
sed156x_cmd_transfer(LCD_PADDR | i);
sed156x_cmd_transfer(LCD_CADRH | 0);
sed156x_cmd_transfer(LCD_CADRL | 0);
sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS);
}
memcpy(last_hw_screen, hw_screen, sizeof(last_hw_screen));
********/
}
void sed156x_clear(void)
{
memset(sw_screen, 0, sizeof(sw_screen));
}
void sed156x_output_at(int x, int y, const char *str, int size)
{
int i, j;
u8 *p;
const u8 *s;
if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH)
return;
p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH];
while (--size >= 0) {
s = &video_fontdata[((int)*str++ & 0xff) * VIDEO_FONT_BYTE_WIDTH * VIDEO_FONT_HEIGHT];
for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++)
*p++ = *s++;
p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH;
}
p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH);
if (x >= LCD_TEXT_WIDTH)
break;
x++;
}
}
void sed156x_reverse_at(int x, int y, int size)
{
int i, j;
u8 *p;
if ((unsigned int)y >= LCD_TEXT_HEIGHT || (unsigned int)x >= LCD_TEXT_WIDTH)
return;
p = &sw_screen[y * VIDEO_FONT_HEIGHT * LCD_BYTE_WIDTH + x * VIDEO_FONT_BYTE_WIDTH];
while (--size >= 0) {
for (i = 0; i < VIDEO_FONT_HEIGHT; i++) {
for (j = 0; j < VIDEO_FONT_BYTE_WIDTH; j++, p++)
*p = ~*p;
p += LCD_BYTE_WIDTH - VIDEO_FONT_BYTE_WIDTH;
}
p -= (LCD_BYTE_LINESZ - VIDEO_FONT_BYTE_WIDTH);
if (x >= LCD_TEXT_WIDTH)
break;
x++;
}
}
void sed156x_scroll_line(void)
{
memmove(&sw_screen[0],
&sw_screen[LCD_BYTE_LINESZ],
LCD_BYTE_WIDTH * (LCD_HEIGHT - VIDEO_FONT_HEIGHT));
}
void sed156x_scroll(int dx, int dy)
{
u8 *p1 = NULL, *p2 = NULL, *p3 = NULL; /* pacify gcc */
int adx, ady, i, sz;
adx = dx > 0 ? dx : -dx;
ady = dy > 0 ? dy : -dy;
/* overscroll? erase everything */
if (adx >= LCD_TEXT_WIDTH || ady >= LCD_TEXT_HEIGHT) {
memset(sw_screen, 0, sizeof(sw_screen));
return;
}
sz = LCD_BYTE_LINESZ * ady;
if (dy > 0) {
p1 = &sw_screen[0];
p2 = &sw_screen[sz];
p3 = &sw_screen[LCD_BYTE_WIDTH * LCD_HEIGHT - sz];
} else if (dy < 0) {
p1 = &sw_screen[sz];
p2 = &sw_screen[0];
p3 = &sw_screen[0];
}
if (ady > 0) {
memmove(p1, p2, LCD_BYTE_WIDTH * LCD_HEIGHT - sz);
memset(p3, 0, sz);
}
sz = VIDEO_FONT_BYTE_WIDTH * adx;
if (dx > 0) {
p1 = &sw_screen[0];
p2 = &sw_screen[0] + sz;
p3 = &sw_screen[0] + LCD_BYTE_WIDTH - sz;
} else if (dx < 0) {
p1 = &sw_screen[0] + sz;
p2 = &sw_screen[0];
p3 = &sw_screen[0];
}
/* xscroll */
if (adx > 0) {
for (i = 0; i < LCD_HEIGHT; i++) {
memmove(p1, p2, LCD_BYTE_WIDTH - sz);
memset(p3, 0, sz);
p1 += LCD_BYTE_WIDTH;
p2 += LCD_BYTE_WIDTH;
p3 += LCD_BYTE_WIDTH;
}
}
}
void sed156x_init(void)
{
int i;
SED156X_CS(1);
SED156X_A0(1);
/* Send initialization commands to the LCD */
sed156x_cmd_transfer(LCD_OFF); /* Turn display OFF */
sed156x_cmd_transfer(LCD_BIAS); /* set the LCD Bias, */
sed156x_cmd_transfer(LCD_ADCMODE); /* ADC mode, */
sed156x_cmd_transfer(LCD_COMDIR); /* common output mode, */
sed156x_cmd_transfer(LCD_RESRT | LCD_RRATIO); /* resistor ratio, */
sed156x_cmd_transfer(LCD_EVSET); /* electronic volume, */
sed156x_cmd_transfer(LCD_CNTRST);
sed156x_cmd_transfer(LCD_PWRMD | LCD_POWERM); /* and power mode */
sed156x_cmd_transfer(LCD_PADDR | 0); /* cursor home */
sed156x_cmd_transfer(LCD_CADRH | 0);
sed156x_cmd_transfer(LCD_CADRL | 0);
sed156x_cmd_transfer(LCD_LADDR | 0); /* and display start line */
sed156x_cmd_transfer(LCD_DSP_NRM); /* LCD display Normal */
/* clear everything */
memset(sw_screen, 0, sizeof(sw_screen));
memset(hw_screen, 0, sizeof(hw_screen));
memset(last_hw_screen, 0, sizeof(last_hw_screen));
for (i = 0; i < LCD_PAGES; i++) {
sed156x_cmd_transfer(LCD_PADDR | i);
sed156x_cmd_transfer(LCD_CADRH | 0);
sed156x_cmd_transfer(LCD_CADRL | 0);
sed156x_data_block_transfer(&hw_screen[i][0], LCD_COLUMNS);
}
sed156x_clear();
sed156x_sync();
sed156x_cmd_transfer(LCD_ON); /* Turn display ON */
}
|
1001-study-uboot
|
drivers/video/sed156x.c
|
C
|
gpl3
| 15,722
|
/*
* (C) Copyright 2002
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Video support for Epson SED13806 chipset */
#include <common.h>
#include <video_fb.h>
#include <sed13806.h>
#define readByte(ptrReg) \
*(volatile unsigned char *)(sed13806.isaBase + ptrReg)
#define writeByte(ptrReg,value) \
*(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value
#ifdef CONFIG_TOTAL5200
#define writeWord(ptrReg,value) \
(*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = value)
#else
#define writeWord(ptrReg,value) \
(*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00))
#endif
GraphicDevice sed13806;
/*-----------------------------------------------------------------------------
* EpsonSetRegs --
*-----------------------------------------------------------------------------
*/
static void EpsonSetRegs (void)
{
/* the content of the chipset register depends on the board (clocks, ...)*/
const S1D_REGS *preg = board_get_regs ();
while (preg -> Index) {
writeByte (preg -> Index, preg -> Value);
preg ++;
}
}
/*-----------------------------------------------------------------------------
* video_hw_init --
*-----------------------------------------------------------------------------
*/
void *video_hw_init (void)
{
unsigned int *vm, i;
memset (&sed13806, 0, sizeof (GraphicDevice));
/* Initialization of the access to the graphic chipset
Retreive base address of the chipset
(see board/RPXClassic/eccx.c) */
if ((sed13806.isaBase = board_video_init ()) == 0) {
return (NULL);
}
sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET;
sed13806.winSizeX = board_get_width ();
sed13806.winSizeY = board_get_height ();
#if defined(CONFIG_VIDEO_SED13806_8BPP)
sed13806.gdfIndex = GDF__8BIT_INDEX;
sed13806.gdfBytesPP = 1;
#elif defined(CONFIG_VIDEO_SED13806_16BPP)
sed13806.gdfIndex = GDF_16BIT_565RGB;
sed13806.gdfBytesPP = 2;
#else
#error Unsupported SED13806 BPP
#endif
sed13806.memSize = sed13806.winSizeX * sed13806.winSizeY * sed13806.gdfBytesPP;
/* Load SED registers */
EpsonSetRegs ();
/* (see board/RPXClassic/RPXClassic.c) */
board_validate_screen (sed13806.isaBase);
/* Clear video memory */
i = sed13806.memSize/4;
vm = (unsigned int *)sed13806.frameAdrs;
while(i--)
*vm++ = 0;
return (&sed13806);
}
/*-----------------------------------------------------------------------------
* Epson_wait_idle -- Wait for hardware to become idle
*-----------------------------------------------------------------------------
*/
static void Epson_wait_idle (void)
{
while (readByte (BLT_CTRL0) & 0x80);
/* Read a word in the BitBLT memory area to shutdown the BitBLT engine */
*(volatile unsigned short *)(sed13806.isaBase + BLT_REG);
}
/*-----------------------------------------------------------------------------
* video_hw_bitblt --
*-----------------------------------------------------------------------------
*/
void video_hw_bitblt (
unsigned int bpp, /* bytes per pixel */
unsigned int src_x, /* source pos x */
unsigned int src_y, /* source pos y */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y /* frame height */
)
{
register GraphicDevice *pGD = (GraphicDevice *)&sed13806;
unsigned long srcAddr, dstAddr;
unsigned int stride = bpp * pGD -> winSizeX;
srcAddr = (src_y * stride) + (src_x * bpp);
dstAddr = (dst_y * stride) + (dst_x * bpp);
Epson_wait_idle ();
writeByte(BLT_ROP,0x0C); /* source */
writeByte(BLT_OP,0x02);/* move blit in positive direction with ROP */
writeWord(BLT_MEM_OFF0, stride / 2);
if (pGD -> gdfIndex == GDF__8BIT_INDEX) {
writeByte(BLT_CTRL1,0x00);
}
else {
writeByte(BLT_CTRL1,0x01);
}
writeWord(BLT_WIDTH0,(dim_x - 1));
writeWord(BLT_HEIGHT0,(dim_y - 1));
/* set up blit registers */
writeByte(BLT_SRC_ADDR0,srcAddr);
writeByte(BLT_SRC_ADDR1,srcAddr>>8);
writeByte(BLT_SRC_ADDR2,srcAddr>>16);
writeByte(BLT_DST_ADDR0,dstAddr);
writeByte(BLT_DST_ADDR1,dstAddr>>8);
writeByte(BLT_DST_ADDR2,dstAddr>>16);
/* Engage the blt engine */
/* rectangular region for src and dst */
writeByte(BLT_CTRL0,0x80);
/* wait untill current blits finished */
Epson_wait_idle ();
}
/*-----------------------------------------------------------------------------
* video_hw_rectfill --
*-----------------------------------------------------------------------------
*/
void video_hw_rectfill (
unsigned int bpp, /* bytes per pixel */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y, /* frame height */
unsigned int color /* fill color */
)
{
register GraphicDevice *pGD = (GraphicDevice *)&sed13806;
unsigned long dstAddr;
unsigned int stride = bpp * pGD -> winSizeX;
dstAddr = (dst_y * stride) + (dst_x * bpp);
Epson_wait_idle ();
/* set up blit registers */
writeByte(BLT_DST_ADDR0,dstAddr);
writeByte(BLT_DST_ADDR1,dstAddr>>8);
writeByte(BLT_DST_ADDR2,dstAddr>>16);
writeWord(BLT_WIDTH0,(dim_x - 1));
writeWord(BLT_HEIGHT0,(dim_y - 1));
writeWord(BLT_FGCOLOR0,color);
writeByte(BLT_OP,0x0C); /* solid fill */
writeWord(BLT_MEM_OFF0,stride / 2);
if (pGD -> gdfIndex == GDF__8BIT_INDEX) {
writeByte(BLT_CTRL1,0x00);
}
else {
writeByte(BLT_CTRL1,0x01);
}
/* Engage the blt engine */
/* rectangular region for src and dst */
writeByte(BLT_CTRL0,0x80);
/* wait untill current blits finished */
Epson_wait_idle ();
}
/*-----------------------------------------------------------------------------
* video_set_lut --
*-----------------------------------------------------------------------------
*/
void video_set_lut (
unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
)
{
writeByte(REG_LUT_ADDR, index );
writeByte(REG_LUT_DATA, r);
writeByte(REG_LUT_DATA, g);
writeByte(REG_LUT_DATA, b);
}
#ifdef CONFIG_VIDEO_HW_CURSOR
/*-----------------------------------------------------------------------------
* video_set_hw_cursor --
*-----------------------------------------------------------------------------
*/
void video_set_hw_cursor (int x, int y)
{
writeByte (LCD_CURSOR_XL, (x & 0xff));
writeByte (LCD_CURSOR_XM, (x >> 8));
writeByte (LCD_CURSOR_YL, (y & 0xff));
writeByte (LCD_CURSOR_YM, (y >> 8));
}
/*-----------------------------------------------------------------------------
* video_init_hw_cursor --
*-----------------------------------------------------------------------------
*/
void video_init_hw_cursor (int font_width, int font_height)
{
volatile unsigned char *ptr;
unsigned char pattern;
int i;
/* Init cursor content
Cursor size is 64x64 pixels
Start of the cursor memory depends on panel type (dual panel ...) */
if ((i = readByte (LCD_CURSOR_START)) == 0) {
ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE);
}
else {
ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192));
}
/* Fill the first line and the first empty line after cursor */
for (i = 0, pattern = 0; i < 64; i++) {
if (i < font_width) {
/* Invert background */
pattern |= 0x3;
}
else {
/* Background */
pattern |= 0x2;
}
if ((i & 3) == 3) {
*ptr = pattern;
*(ptr + font_height * 16) = 0xaa;
ptr ++;
pattern = 0;
}
pattern <<= 2;
}
/* Duplicate this line */
for (i = 1; i < font_height; i++) {
memcpy ((void *)ptr, (void *)(ptr - 16), 16);
ptr += 16;
}
for (; i < 64; i++) {
memcpy ((void *)(ptr + 16), (void *)ptr, 16);
ptr += 16;
}
/* Select cursor mode */
writeByte (LCD_CURSOR_CNTL, 1);
}
#endif
|
1001-study-uboot
|
drivers/video/sed13806.c
|
C
|
gpl3
| 9,928
|
/*
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
* Authors: York Sun <yorksun@freescale.com>
* Timur Tabi <timur@freescale.com>
*
* FSL DIU Framebuffer driver
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include "videomodes.h"
#include <video_fb.h>
#include <fsl_diu_fb.h>
#include <linux/list.h>
#include <linux/fb.h>
/* This setting is used for the ifm pdm360ng with PRIMEVIEW PM070WL3 */
static struct fb_videomode fsl_diu_mode_800_480 = {
.name = "800x480-60",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 31250,
.left_margin = 86,
.right_margin = 42,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 128,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
/* For the SHARP LQ084S3LG01, used on the P1022DS board */
static struct fb_videomode fsl_diu_mode_800_600 = {
.name = "800x600-60",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000,
.left_margin = 88,
.right_margin = 40,
.upper_margin = 23,
.lower_margin = 1,
.hsync_len = 128,
.vsync_len = 4,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* These parameters give default parameters
* for video output 1024x768,
* FIXME - change timing to proper amounts
* hsync 31.5kHz, vsync 60Hz
*/
static struct fb_videomode fsl_diu_mode_1024_768 = {
.name = "1024x768-60",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 160,
.right_margin = 24,
.upper_margin = 29,
.lower_margin = 3,
.hsync_len = 136,
.vsync_len = 6,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_videomode fsl_diu_mode_1280_1024 = {
.name = "1280x1024-60",
.refresh = 60,
.xres = 1280,
.yres = 1024,
.pixclock = 9375,
.left_margin = 38,
.right_margin = 128,
.upper_margin = 2,
.lower_margin = 7,
.hsync_len = 216,
.vsync_len = 37,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_videomode fsl_diu_mode_1280_720 = {
.name = "1280x720-60",
.refresh = 60,
.xres = 1280,
.yres = 720,
.pixclock = 13426,
.left_margin = 192,
.right_margin = 64,
.upper_margin = 22,
.lower_margin = 1,
.hsync_len = 136,
.vsync_len = 3,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_videomode fsl_diu_mode_1920_1080 = {
.name = "1920x1080-60",
.refresh = 60,
.xres = 1920,
.yres = 1080,
.pixclock = 5787,
.left_margin = 328,
.right_margin = 120,
.upper_margin = 34,
.lower_margin = 1,
.hsync_len = 208,
.vsync_len = 3,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* These are the fields of area descriptor(in DDR memory) for every plane
*/
struct diu_ad {
/* Word 0(32-bit) in DDR memory */
__le32 pix_fmt; /* hard coding pixel format */
/* Word 1(32-bit) in DDR memory */
__le32 addr;
/* Word 2(32-bit) in DDR memory */
__le32 src_size_g_alpha;
/* Word 3(32-bit) in DDR memory */
__le32 aoi_size;
/* Word 4(32-bit) in DDR memory */
__le32 offset_xyi;
/* Word 5(32-bit) in DDR memory */
__le32 offset_xyd;
/* Word 6(32-bit) in DDR memory */
__le32 ckmax_r:8;
__le32 ckmax_g:8;
__le32 ckmax_b:8;
__le32 res9:8;
/* Word 7(32-bit) in DDR memory */
__le32 ckmin_r:8;
__le32 ckmin_g:8;
__le32 ckmin_b:8;
__le32 res10:8;
/* Word 8(32-bit) in DDR memory */
__le32 next_ad;
/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
__le32 res[3];
} __attribute__ ((packed));
/*
* DIU register map
*/
struct diu {
__be32 desc[3];
__be32 gamma;
__be32 pallete;
__be32 cursor;
__be32 curs_pos;
__be32 diu_mode;
__be32 bgnd;
__be32 bgnd_wb;
__be32 disp_size;
__be32 wb_size;
__be32 wb_mem_addr;
__be32 hsyn_para;
__be32 vsyn_para;
__be32 syn_pol;
__be32 thresholds;
__be32 int_status;
__be32 int_mask;
__be32 colorbar[8];
__be32 filling;
__be32 plut;
} __attribute__ ((packed));
struct diu_addr {
void *vaddr; /* Virtual address */
u32 paddr; /* 32-bit physical address */
unsigned int offset; /* Alignment offset */
};
static struct fb_info info;
/*
* Align to 64-bit(8-byte), 32-byte, etc.
*/
static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
{
u32 offset, ssize;
u32 mask;
ssize = size + bytes_align;
buf->vaddr = malloc(ssize);
if (!buf->vaddr)
return -1;
memset(buf->vaddr, 0, ssize);
mask = bytes_align - 1;
offset = (u32)buf->vaddr & mask;
if (offset) {
buf->offset = bytes_align - offset;
buf->vaddr += offset;
} else
buf->offset = 0;
buf->paddr = virt_to_phys(buf->vaddr);
return 0;
}
/*
* Allocate a framebuffer and an Area Descriptor that points to it. Both
* are created in the same memory block. The Area Descriptor is updated to
* point to the framebuffer memory. Memory is aligned as needed.
*/
static struct diu_ad *allocate_fb(unsigned int xres, unsigned int yres,
unsigned int depth, char **fb)
{
unsigned long size = xres * yres * depth;
struct diu_addr addr;
struct diu_ad *ad;
size_t ad_size = roundup(sizeof(struct diu_ad), 32);
/*
* Allocate a memory block that holds the Area Descriptor and the
* frame buffer right behind it. To keep the code simple, everything
* is aligned on a 32-byte address.
*/
if (allocate_buf(&addr, ad_size + size, 32) < 0)
return NULL;
ad = addr.vaddr;
ad->addr = cpu_to_le32(addr.paddr + ad_size);
ad->aoi_size = cpu_to_le32((yres << 16) | xres);
ad->src_size_g_alpha = cpu_to_le32((yres << 12) | xres);
ad->offset_xyi = 0;
ad->offset_xyd = 0;
if (fb)
*fb = addr.vaddr + ad_size;
return ad;
}
int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix)
{
struct fb_videomode *fsl_diu_mode_db;
struct diu_ad *ad;
struct diu *hw = (struct diu *)CONFIG_SYS_DIU_ADDR;
u8 *gamma_table_base;
unsigned int i, j;
struct diu_ad *dummy_ad;
struct diu_addr gamma;
struct diu_addr cursor;
/* Convert the X,Y resolution pair into a single number */
#define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
switch (RESOLUTION(xres, yres)) {
case RESOLUTION(800, 480):
fsl_diu_mode_db = &fsl_diu_mode_800_480;
break;
case RESOLUTION(800, 600):
fsl_diu_mode_db = &fsl_diu_mode_800_600;
break;
case RESOLUTION(1024, 768):
fsl_diu_mode_db = &fsl_diu_mode_1024_768;
break;
case RESOLUTION(1280, 1024):
fsl_diu_mode_db = &fsl_diu_mode_1280_1024;
break;
case RESOLUTION(1280, 720):
fsl_diu_mode_db = &fsl_diu_mode_1280_720;
break;
case RESOLUTION(1920, 1080):
fsl_diu_mode_db = &fsl_diu_mode_1920_1080;
break;
default:
printf("DIU: Unsupported resolution %ux%u\n", xres, yres);
return -1;
}
/* The AD struct for the dummy framebuffer and the FB itself */
dummy_ad = allocate_fb(2, 4, 4, NULL);
if (!dummy_ad) {
printf("DIU: Out of memory\n");
return -1;
}
dummy_ad->pix_fmt = 0x88883316;
/* read mode info */
info.var.xres = fsl_diu_mode_db->xres;
info.var.yres = fsl_diu_mode_db->yres;
info.var.bits_per_pixel = 32;
info.var.pixclock = fsl_diu_mode_db->pixclock;
info.var.left_margin = fsl_diu_mode_db->left_margin;
info.var.right_margin = fsl_diu_mode_db->right_margin;
info.var.upper_margin = fsl_diu_mode_db->upper_margin;
info.var.lower_margin = fsl_diu_mode_db->lower_margin;
info.var.hsync_len = fsl_diu_mode_db->hsync_len;
info.var.vsync_len = fsl_diu_mode_db->vsync_len;
info.var.sync = fsl_diu_mode_db->sync;
info.var.vmode = fsl_diu_mode_db->vmode;
info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8;
/* Memory allocation for framebuffer */
info.screen_size =
info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
ad = allocate_fb(info.var.xres, info.var.yres,
info.var.bits_per_pixel / 8, &info.screen_base);
if (!ad) {
printf("DIU: Out of memory\n");
return -1;
}
ad->pix_fmt = pixel_format;
/* Disable chroma keying function */
ad->ckmax_r = 0;
ad->ckmax_g = 0;
ad->ckmax_b = 0;
ad->ckmin_r = 255;
ad->ckmin_g = 255;
ad->ckmin_b = 255;
/* Initialize the gamma table */
if (allocate_buf(&gamma, 256 * 3, 32) < 0) {
printf("DIU: Out of memory\n");
return -1;
}
gamma_table_base = gamma.vaddr;
for (i = 0; i <= 2; i++)
for (j = 0; j < 256; j++)
*gamma_table_base++ = j;
if (gamma_fix == 1) { /* fix the gamma */
gamma_table_base = gamma.vaddr;
for (i = 0; i < 256 * 3; i++) {
gamma_table_base[i] = (gamma_table_base[i] << 2)
| ((gamma_table_base[i] >> 6) & 0x03);
}
}
/* Initialize the cursor */
if (allocate_buf(&cursor, 32 * 32 * 2, 32) < 0) {
printf("DIU: Can't alloc cursor data\n");
return -1;
}
/* Program DIU registers */
out_be32(&hw->diu_mode, 0); /* Temporarily disable the DIU */
out_be32(&hw->gamma, gamma.paddr);
out_be32(&hw->cursor, cursor.paddr);
out_be32(&hw->bgnd, 0x007F7F7F);
out_be32(&hw->bgnd_wb, 0);
out_be32(&hw->disp_size, info.var.yres << 16 | info.var.xres);
out_be32(&hw->wb_size, 0);
out_be32(&hw->wb_mem_addr, 0);
out_be32(&hw->hsyn_para, info.var.left_margin << 22 |
info.var.hsync_len << 11 |
info.var.right_margin);
out_be32(&hw->vsyn_para, info.var.upper_margin << 22 |
info.var.vsync_len << 11 |
info.var.lower_margin);
out_be32(&hw->syn_pol, 0);
out_be32(&hw->thresholds, 0x00037800);
out_be32(&hw->int_status, 0);
out_be32(&hw->int_mask, 0);
out_be32(&hw->plut, 0x01F5F666);
/* Pixel Clock configuration */
diu_set_pixel_clock(info.var.pixclock);
/* Set the frame buffers */
out_be32(&hw->desc[0], virt_to_phys(ad));
out_be32(&hw->desc[1], virt_to_phys(dummy_ad));
out_be32(&hw->desc[2], virt_to_phys(dummy_ad));
/* Enable the DIU, set display to all three planes */
out_be32(&hw->diu_mode, 1);
return 0;
}
void *video_hw_init(void)
{
static GraphicDevice ctfb;
const char *options;
unsigned int depth = 0, freq = 0;
if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq,
&options))
return NULL;
/* Find the monitor port, which is a required option */
if (!options)
return NULL;
if (strncmp(options, "monitor=", 8) != 0)
return NULL;
if (platform_diu_init(ctfb.winSizeX, ctfb.winSizeY, options + 8) < 0)
return NULL;
/* fill in Graphic device struct */
sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz",
ctfb.winSizeX, ctfb.winSizeY, depth, 64, freq);
ctfb.frameAdrs = (unsigned int)info.screen_base;
ctfb.plnSizeX = ctfb.winSizeX;
ctfb.plnSizeY = ctfb.winSizeY;
ctfb.gdfBytesPP = 4;
ctfb.gdfIndex = GDF_32BIT_X888RGB;
ctfb.isaBase = 0;
ctfb.pciBase = 0;
ctfb.memSize = info.screen_size;
/* Cursor Start Address */
ctfb.dprBase = 0;
ctfb.vprBase = 0;
ctfb.cprBase = 0;
return &ctfb;
}
|
1001-study-uboot
|
drivers/video/fsl_diu_fb.c
|
C
|
gpl3
| 11,483
|
/*
* Copyright (C) 2009
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <spi.h>
#include <s6e63d6.h>
/*
* Each transfer is performed as:
* 1. chip-select active
* 2. send 8-bit start code
* 3. send 16-bit data
* 4. chip-select inactive
*/
static int send_word(struct s6e63d6 *data, u8 rs, u16 word)
{
/*
* The start byte looks like (binary):
* 01110<ID><RS><R/W>
* RS is 0 for index or 1 for data, and R/W is 0 for write.
*/
u32 buf8 = 0x70 | data->id | (rs & 2);
u32 buf16 = cpu_to_le16(word);
u32 buf_in;
int err;
err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
if (err)
return err;
return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END);
}
/* Index and param differ in Register Select bit */
int s6e63d6_index(struct s6e63d6 *data, u8 idx)
{
return send_word(data, 0, idx);
}
int s6e63d6_param(struct s6e63d6 *data, u16 param)
{
return send_word(data, 2, param);
}
int s6e63d6_init(struct s6e63d6 *data)
{
if (data->id != 0 && data->id != 4) {
printf("s6e63d6: invalid ID %u\n", data->id);
return 1;
}
data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
if (!data->slave)
return 1;
return 0;
}
|
1001-study-uboot
|
drivers/video/s6e63d6.c
|
C
|
gpl3
| 2,034
|
/*
* Copyright (C) 2009
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
* Copyright (C) 2011
* HALE electronic GmbH, <helmut.raiger@hale.at>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <video_fb.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/errno.h>
#include <asm/io.h>
#include "videomodes.h"
/* this might need panel specific set-up as-well */
#define IF_CONF 0
/* -------------- controller specific stuff -------------- */
/* IPU DMA Controller channel definitions. */
enum ipu_channel {
IDMAC_IC_0 = 0, /* IC (encoding task) to memory */
IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */
IDMAC_ADC_0 = 1,
IDMAC_IC_2 = 2,
IDMAC_ADC_1 = 2,
IDMAC_IC_3 = 3,
IDMAC_IC_4 = 4,
IDMAC_IC_5 = 5,
IDMAC_IC_6 = 6,
IDMAC_IC_7 = 7, /* IC (sensor data) to memory */
IDMAC_IC_8 = 8,
IDMAC_IC_9 = 9,
IDMAC_IC_10 = 10,
IDMAC_IC_11 = 11,
IDMAC_IC_12 = 12,
IDMAC_IC_13 = 13,
IDMAC_SDC_0 = 14, /* Background synchronous display data */
IDMAC_SDC_1 = 15, /* Foreground data (overlay) */
IDMAC_SDC_2 = 16,
IDMAC_SDC_3 = 17,
IDMAC_ADC_2 = 18,
IDMAC_ADC_3 = 19,
IDMAC_ADC_4 = 20,
IDMAC_ADC_5 = 21,
IDMAC_ADC_6 = 22,
IDMAC_ADC_7 = 23,
IDMAC_PF_0 = 24,
IDMAC_PF_1 = 25,
IDMAC_PF_2 = 26,
IDMAC_PF_3 = 27,
IDMAC_PF_4 = 28,
IDMAC_PF_5 = 29,
IDMAC_PF_6 = 30,
IDMAC_PF_7 = 31,
};
/* More formats can be copied from the Linux driver if needed */
enum pixel_fmt {
/* 2 bytes */
IPU_PIX_FMT_RGB565,
IPU_PIX_FMT_RGB666,
IPU_PIX_FMT_BGR666,
/* 3 bytes */
IPU_PIX_FMT_RGB24,
};
struct pixel_fmt_cfg {
u32 b0;
u32 b1;
u32 b2;
u32 acc;
};
static struct pixel_fmt_cfg fmt_cfg[] = {
[IPU_PIX_FMT_RGB24] = {
0x1600AAAA, 0x00E05555, 0x00070000, 3,
},
[IPU_PIX_FMT_RGB666] = {
0x0005000F, 0x000B000F, 0x0011000F, 1,
},
[IPU_PIX_FMT_BGR666] = {
0x0011000F, 0x000B000F, 0x0005000F, 1,
},
[IPU_PIX_FMT_RGB565] = {
0x0004003F, 0x000A000F, 0x000F003F, 1,
}
};
enum ipu_panel {
IPU_PANEL_SHARP_TFT,
IPU_PANEL_TFT,
};
/* IPU Common registers */
/* IPU_CONF and its bits already defined in imx-regs.h */
#define IPU_CHA_BUF0_RDY (0x04 + IPU_BASE)
#define IPU_CHA_BUF1_RDY (0x08 + IPU_BASE)
#define IPU_CHA_DB_MODE_SEL (0x0C + IPU_BASE)
#define IPU_CHA_CUR_BUF (0x10 + IPU_BASE)
#define IPU_FS_PROC_FLOW (0x14 + IPU_BASE)
#define IPU_FS_DISP_FLOW (0x18 + IPU_BASE)
#define IPU_TASKS_STAT (0x1C + IPU_BASE)
#define IPU_IMA_ADDR (0x20 + IPU_BASE)
#define IPU_IMA_DATA (0x24 + IPU_BASE)
#define IPU_INT_CTRL_1 (0x28 + IPU_BASE)
#define IPU_INT_CTRL_2 (0x2C + IPU_BASE)
#define IPU_INT_CTRL_3 (0x30 + IPU_BASE)
#define IPU_INT_CTRL_4 (0x34 + IPU_BASE)
#define IPU_INT_CTRL_5 (0x38 + IPU_BASE)
#define IPU_INT_STAT_1 (0x3C + IPU_BASE)
#define IPU_INT_STAT_2 (0x40 + IPU_BASE)
#define IPU_INT_STAT_3 (0x44 + IPU_BASE)
#define IPU_INT_STAT_4 (0x48 + IPU_BASE)
#define IPU_INT_STAT_5 (0x4C + IPU_BASE)
#define IPU_BRK_CTRL_1 (0x50 + IPU_BASE)
#define IPU_BRK_CTRL_2 (0x54 + IPU_BASE)
#define IPU_BRK_STAT (0x58 + IPU_BASE)
#define IPU_DIAGB_CTRL (0x5C + IPU_BASE)
/* Image Converter Registers */
#define IC_CONF (0x88 + IPU_BASE)
#define IC_PRP_ENC_RSC (0x8C + IPU_BASE)
#define IC_PRP_VF_RSC (0x90 + IPU_BASE)
#define IC_PP_RSC (0x94 + IPU_BASE)
#define IC_CMBP_1 (0x98 + IPU_BASE)
#define IC_CMBP_2 (0x9C + IPU_BASE)
#define PF_CONF (0xA0 + IPU_BASE)
#define IDMAC_CONF (0xA4 + IPU_BASE)
#define IDMAC_CHA_EN (0xA8 + IPU_BASE)
#define IDMAC_CHA_PRI (0xAC + IPU_BASE)
#define IDMAC_CHA_BUSY (0xB0 + IPU_BASE)
/* Image Converter Register bits */
#define IC_CONF_PRPENC_EN 0x00000001
#define IC_CONF_PRPENC_CSC1 0x00000002
#define IC_CONF_PRPENC_ROT_EN 0x00000004
#define IC_CONF_PRPVF_EN 0x00000100
#define IC_CONF_PRPVF_CSC1 0x00000200
#define IC_CONF_PRPVF_CSC2 0x00000400
#define IC_CONF_PRPVF_CMB 0x00000800
#define IC_CONF_PRPVF_ROT_EN 0x00001000
#define IC_CONF_PP_EN 0x00010000
#define IC_CONF_PP_CSC1 0x00020000
#define IC_CONF_PP_CSC2 0x00040000
#define IC_CONF_PP_CMB 0x00080000
#define IC_CONF_PP_ROT_EN 0x00100000
#define IC_CONF_IC_GLB_LOC_A 0x10000000
#define IC_CONF_KEY_COLOR_EN 0x20000000
#define IC_CONF_RWS_EN 0x40000000
#define IC_CONF_CSI_MEM_WR_EN 0x80000000
/* SDC Registers */
#define SDC_COM_CONF (0xB4 + IPU_BASE)
#define SDC_GW_CTRL (0xB8 + IPU_BASE)
#define SDC_FG_POS (0xBC + IPU_BASE)
#define SDC_BG_POS (0xC0 + IPU_BASE)
#define SDC_CUR_POS (0xC4 + IPU_BASE)
#define SDC_PWM_CTRL (0xC8 + IPU_BASE)
#define SDC_CUR_MAP (0xCC + IPU_BASE)
#define SDC_HOR_CONF (0xD0 + IPU_BASE)
#define SDC_VER_CONF (0xD4 + IPU_BASE)
#define SDC_SHARP_CONF_1 (0xD8 + IPU_BASE)
#define SDC_SHARP_CONF_2 (0xDC + IPU_BASE)
/* Register bits */
#define SDC_COM_TFT_COLOR 0x00000001UL
#define SDC_COM_FG_EN 0x00000010UL
#define SDC_COM_GWSEL 0x00000020UL
#define SDC_COM_GLB_A 0x00000040UL
#define SDC_COM_KEY_COLOR_G 0x00000080UL
#define SDC_COM_BG_EN 0x00000200UL
#define SDC_COM_SHARP 0x00001000UL
#define SDC_V_SYNC_WIDTH_L 0x00000001UL
/* Display Interface registers */
#define DI_DISP_IF_CONF (0x0124 + IPU_BASE)
#define DI_DISP_SIG_POL (0x0128 + IPU_BASE)
#define DI_SER_DISP1_CONF (0x012C + IPU_BASE)
#define DI_SER_DISP2_CONF (0x0130 + IPU_BASE)
#define DI_HSP_CLK_PER (0x0134 + IPU_BASE)
#define DI_DISP0_TIME_CONF_1 (0x0138 + IPU_BASE)
#define DI_DISP0_TIME_CONF_2 (0x013C + IPU_BASE)
#define DI_DISP0_TIME_CONF_3 (0x0140 + IPU_BASE)
#define DI_DISP1_TIME_CONF_1 (0x0144 + IPU_BASE)
#define DI_DISP1_TIME_CONF_2 (0x0148 + IPU_BASE)
#define DI_DISP1_TIME_CONF_3 (0x014C + IPU_BASE)
#define DI_DISP2_TIME_CONF_1 (0x0150 + IPU_BASE)
#define DI_DISP2_TIME_CONF_2 (0x0154 + IPU_BASE)
#define DI_DISP2_TIME_CONF_3 (0x0158 + IPU_BASE)
#define DI_DISP3_TIME_CONF (0x015C + IPU_BASE)
#define DI_DISP0_DB0_MAP (0x0160 + IPU_BASE)
#define DI_DISP0_DB1_MAP (0x0164 + IPU_BASE)
#define DI_DISP0_DB2_MAP (0x0168 + IPU_BASE)
#define DI_DISP0_CB0_MAP (0x016C + IPU_BASE)
#define DI_DISP0_CB1_MAP (0x0170 + IPU_BASE)
#define DI_DISP0_CB2_MAP (0x0174 + IPU_BASE)
#define DI_DISP1_DB0_MAP (0x0178 + IPU_BASE)
#define DI_DISP1_DB1_MAP (0x017C + IPU_BASE)
#define DI_DISP1_DB2_MAP (0x0180 + IPU_BASE)
#define DI_DISP1_CB0_MAP (0x0184 + IPU_BASE)
#define DI_DISP1_CB1_MAP (0x0188 + IPU_BASE)
#define DI_DISP1_CB2_MAP (0x018C + IPU_BASE)
#define DI_DISP2_DB0_MAP (0x0190 + IPU_BASE)
#define DI_DISP2_DB1_MAP (0x0194 + IPU_BASE)
#define DI_DISP2_DB2_MAP (0x0198 + IPU_BASE)
#define DI_DISP2_CB0_MAP (0x019C + IPU_BASE)
#define DI_DISP2_CB1_MAP (0x01A0 + IPU_BASE)
#define DI_DISP2_CB2_MAP (0x01A4 + IPU_BASE)
#define DI_DISP3_B0_MAP (0x01A8 + IPU_BASE)
#define DI_DISP3_B1_MAP (0x01AC + IPU_BASE)
#define DI_DISP3_B2_MAP (0x01B0 + IPU_BASE)
#define DI_DISP_ACC_CC (0x01B4 + IPU_BASE)
#define DI_DISP_LLA_CONF (0x01B8 + IPU_BASE)
#define DI_DISP_LLA_DATA (0x01BC + IPU_BASE)
/* DI_DISP_SIG_POL bits */
#define DI_D3_VSYNC_POL (1 << 28)
#define DI_D3_HSYNC_POL (1 << 27)
#define DI_D3_DRDY_SHARP_POL (1 << 26)
#define DI_D3_CLK_POL (1 << 25)
#define DI_D3_DATA_POL (1 << 24)
/* DI_DISP_IF_CONF bits */
#define DI_D3_CLK_IDLE (1 << 26)
#define DI_D3_CLK_SEL (1 << 25)
#define DI_D3_DATAMSK (1 << 24)
#define IOMUX_PADNUM_MASK 0x1ff
#define IOMUX_GPIONUM_SHIFT 9
#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
struct chan_param_mem_planar {
/* Word 0 */
u32 xv:10;
u32 yv:10;
u32 xb:12;
u32 yb:12;
u32 res1:2;
u32 nsb:1;
u32 lnpb:6;
u32 ubo_l:11;
u32 ubo_h:15;
u32 vbo_l:17;
u32 vbo_h:9;
u32 res2:3;
u32 fw:12;
u32 fh_l:8;
u32 fh_h:4;
u32 res3:28;
/* Word 1 */
u32 eba0;
u32 eba1;
u32 bpp:3;
u32 sl:14;
u32 pfs:3;
u32 bam:3;
u32 res4:2;
u32 npb:6;
u32 res5:1;
u32 sat:2;
u32 res6:30;
} __attribute__ ((packed));
struct chan_param_mem_interleaved {
/* Word 0 */
u32 xv:10;
u32 yv:10;
u32 xb:12;
u32 yb:12;
u32 sce:1;
u32 res1:1;
u32 nsb:1;
u32 lnpb:6;
u32 sx:10;
u32 sy_l:1;
u32 sy_h:9;
u32 ns:10;
u32 sm:10;
u32 sdx_l:3;
u32 sdx_h:2;
u32 sdy:5;
u32 sdrx:1;
u32 sdry:1;
u32 sdr1:1;
u32 res2:2;
u32 fw:12;
u32 fh_l:8;
u32 fh_h:4;
u32 res3:28;
/* Word 1 */
u32 eba0;
u32 eba1;
u32 bpp:3;
u32 sl:14;
u32 pfs:3;
u32 bam:3;
u32 res4:2;
u32 npb:6;
u32 res5:1;
u32 sat:2;
u32 scc:1;
u32 ofs0:5;
u32 ofs1:5;
u32 ofs2:5;
u32 ofs3:5;
u32 wid0:3;
u32 wid1:3;
u32 wid2:3;
u32 wid3:3;
u32 dec_sel:1;
u32 res6:28;
} __attribute__ ((packed));
union chan_param_mem {
struct chan_param_mem_planar pp;
struct chan_param_mem_interleaved ip;
};
DECLARE_GLOBAL_DATA_PTR;
/* graphics setup */
static GraphicDevice panel;
static struct ctfb_res_modes *mode;
static struct ctfb_res_modes var_mode;
/*
* sdc_init_panel() - initialize a synchronous LCD panel.
* @width: width of panel in pixels.
* @height: height of panel in pixels.
* @di_setup: pixel format of the frame buffer
* @di_panel: either SHARP or normal TFT
* @return: 0 on success or negative error code on failure.
*/
static int sdc_init_panel(u16 width, u16 height,
enum pixel_fmt di_setup, enum ipu_panel di_panel)
{
u32 reg, div;
uint32_t old_conf;
int clock;
debug("%s(width=%d, height=%d)\n", __func__, width, height);
/* Init clocking, the IPU receives its clock from the hsp divder */
clock = mxc_get_clock(MXC_IPU_CLK);
if (clock < 0)
return -EACCES;
/* Init panel size and blanking periods */
reg = width + mode->left_margin + mode->right_margin - 1;
if (reg > 1023) {
printf("mx3fb: Display width too large, coerced to 1023!");
reg = 1023;
}
reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
writel(reg, SDC_HOR_CONF);
reg = height + mode->upper_margin + mode->lower_margin - 1;
if (reg > 1023) {
printf("mx3fb: Display height too large, coerced to 1023!");
reg = 1023;
}
reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
writel(reg, SDC_VER_CONF);
switch (di_panel) {
case IPU_PANEL_SHARP_TFT:
writel(0x00FD0102L, SDC_SHARP_CONF_1);
writel(0x00F500F4L, SDC_SHARP_CONF_2);
writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
/* TODO: probably IF_CONF must be adapted (see below)! */
break;
case IPU_PANEL_TFT:
writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
break;
default:
return -EINVAL;
}
/*
* Calculate divider: The fractional part is 4 bits so simply
* multiple by 2^4 to get it.
*
* Opposed to the kernel driver mode->pixclock is the time of one
* pixel in pico seconds, so:
* pixel_clk = 1e12 / mode->pixclock
* div = ipu_clk * 16 / pixel_clk
* leads to:
* div = ipu_clk * 16 / (1e12 / mode->pixclock)
* or:
* div = ipu_clk * 16 * mode->pixclock / 1e12
*
* To avoid integer overflows this is split into 2 shifts and
* one divide with sufficient accuracy:
* 16*1024*128*476837 = 0.9999996682e12
*/
div = ((clock/1024) * (mode->pixclock/128)) / 476837;
debug("hsp_clk is %d, div=%d\n", clock, div);
/* coerce to not less than 4.0, not more than 255.9375 */
if (div < 0x40)
div = 0x40;
else if (div > 0xFFF)
div = 0xFFF;
/* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
* fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
* based on timing debug DISP3_IF_CLK_UP_WR is 0
*/
writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
/* DI settings for display 3: clock idle (bit 26) during vsync */
old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
writel(old_conf | IF_CONF, DI_DISP_IF_CONF);
/* only set display 3 polarity bits */
old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
writel(old_conf | mode->sync, DI_DISP_SIG_POL);
writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
writel(readl(DI_DISP_ACC_CC) |
((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
debug("DI_DISP_IF_CONF = 0x%08X\n", readl(DI_DISP_IF_CONF));
debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL));
debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF));
debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF));
debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF));
return 0;
}
static void ipu_ch_param_set_size(union chan_param_mem *params,
uint pixelfmt, uint16_t width,
uint16_t height, uint16_t stride)
{
debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
__func__, pixelfmt, width, height, stride);
params->pp.fw = width - 1;
params->pp.fh_l = height - 1;
params->pp.fh_h = (height - 1) >> 8;
params->pp.sl = stride - 1;
/* See above, for further formats see the Linux driver */
switch (pixelfmt) {
case GDF_16BIT_565RGB:
params->ip.bpp = 2;
params->ip.pfs = 4;
params->ip.npb = 7;
params->ip.sat = 2; /* SAT = 32-bit access */
params->ip.ofs0 = 0; /* Red bit offset */
params->ip.ofs1 = 5; /* Green bit offset */
params->ip.ofs2 = 11; /* Blue bit offset */
params->ip.ofs3 = 16; /* Alpha bit offset */
params->ip.wid0 = 4; /* Red bit width - 1 */
params->ip.wid1 = 5; /* Green bit width - 1 */
params->ip.wid2 = 4; /* Blue bit width - 1 */
break;
case GDF_32BIT_X888RGB:
params->ip.bpp = 1; /* 24 BPP & RGB PFS */
params->ip.pfs = 4;
params->ip.npb = 7;
params->ip.sat = 2; /* SAT = 32-bit access */
params->ip.ofs0 = 16; /* Red bit offset */
params->ip.ofs1 = 8; /* Green bit offset */
params->ip.ofs2 = 0; /* Blue bit offset */
params->ip.ofs3 = 24; /* Alpha bit offset */
params->ip.wid0 = 7; /* Red bit width - 1 */
params->ip.wid1 = 7; /* Green bit width - 1 */
params->ip.wid2 = 7; /* Blue bit width - 1 */
break;
default:
printf("mx3fb: Pixel format not supported!\n");
break;
}
params->pp.nsb = 1;
}
static void ipu_ch_param_set_buffer(union chan_param_mem *params,
void *buf0, void *buf1)
{
params->pp.eba0 = (u32)buf0;
params->pp.eba1 = (u32)buf1;
}
static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
uint32_t num_words)
{
for (; num_words > 0; num_words--) {
writel(addr, IPU_IMA_ADDR);
writel(*data++, IPU_IMA_DATA);
addr++;
if ((addr & 0x7) == 5) {
addr &= ~0x7; /* set to word 0 */
addr += 8; /* increment to next row */
}
}
}
static uint32_t dma_param_addr(enum ipu_channel channel)
{
/* Channel Parameter Memory */
return 0x10000 | (channel << 4);
}
static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
{
union chan_param_mem params = {};
uint32_t reg;
uint32_t stride_bytes;
stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem);
/* Build parameter memory data for DMA channel */
ipu_ch_param_set_size(¶ms, panel.gdfIndex,
panel.plnSizeX, panel.plnSizeY, stride_bytes);
ipu_ch_param_set_buffer(¶ms, fbmem, NULL);
params.pp.bam = 0;
/* Some channels (rotation) have restriction on burst length */
switch (channel) {
case IDMAC_SDC_0:
/* In original code only IPU_PIX_FMT_RGB565 was setting burst */
params.pp.npb = 16 - 1;
break;
default:
break;
}
ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)¶ms, 10);
/* Disable double-buffering */
reg = readl(IPU_CHA_DB_MODE_SEL);
reg &= ~(1UL << channel);
writel(reg, IPU_CHA_DB_MODE_SEL);
}
static void ipu_channel_set_priority(enum ipu_channel channel,
int prio)
{
u32 reg = readl(IDMAC_CHA_PRI);
if (prio)
reg |= 1UL << channel;
else
reg &= ~(1UL << channel);
writel(reg, IDMAC_CHA_PRI);
}
/*
* ipu_enable_channel() - enable an IPU channel.
* @channel: channel ID.
* @return: 0 on success or negative error code on failure.
*/
static int ipu_enable_channel(enum ipu_channel channel)
{
uint32_t reg;
/* Reset to buffer 0 */
writel(1UL << channel, IPU_CHA_CUR_BUF);
switch (channel) {
case IDMAC_SDC_0:
ipu_channel_set_priority(channel, 1);
break;
default:
break;
}
reg = readl(IDMAC_CHA_EN);
writel(reg | (1UL << channel), IDMAC_CHA_EN);
return 0;
}
static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
{
uint32_t reg;
reg = readl(IPU_CHA_BUF0_RDY);
if (reg & (1UL << channel))
return -EACCES;
/* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
writel((u32)buf, IPU_IMA_DATA);
return 0;
}
static int idmac_tx_submit(enum ipu_channel channel, void *buf)
{
int ret;
ipu_init_channel_buffer(channel, buf);
/* ipu_idmac.c::ipu_submit_channel_buffers() */
ret = ipu_update_channel_buffer(channel, buf);
if (ret < 0)
return ret;
/* ipu_idmac.c::ipu_select_buffer() */
/* Mark buffer 0 as ready. */
writel(1UL << channel, IPU_CHA_BUF0_RDY);
ret = ipu_enable_channel(channel);
return ret;
}
static void sdc_enable_channel(void *fbmem)
{
int ret;
u32 reg;
ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
/* mx3fb.c::sdc_fb_init() */
if (ret >= 0) {
reg = readl(SDC_COM_CONF);
writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
}
/*
* Attention! Without this msleep the channel keeps generating
* interrupts. Next sdc_set_brightness() is going to be called
* from mx3fb_blank().
*/
udelay(2000);
}
/*
* mx3fb_set_par() - set framebuffer parameters and change the operating mode.
* @return: 0 on success or negative error code on failure.
* TODO: currently only 666 and TFT as DI setup supported
*/
static int mx3fb_set_par(void)
{
int ret;
ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
if (ret < 0)
return ret;
writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
return 0;
}
static void ll_disp3_enable(void *base)
{
u32 reg;
debug("%s(base=0x%x)\n", __func__, (u32) base);
/* pcm037.c::mxc_board_init() */
/* Display Interface #3 */
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
/* ipu_idmac.c::ipu_probe() */
/* Start the clock */
__REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
/* ipu_idmac.c::ipu_idmac_init() */
/* Service request counter to maximum - shouldn't be needed */
writel(0x00000070, IDMAC_CONF);
/* ipu_idmac.c::ipu_init_channel() */
/* Enable IPU sub modules */
reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
writel(reg, IPU_CONF);
/* mx3fb.c::init_fb_chan() */
/* set Display Interface clock period */
writel(0x00100010L, DI_HSP_CLK_PER);
/* Might need to trigger HSP clock change - see 44.3.3.8.5 */
/* mx3fb.c::sdc_set_brightness() */
/* This might be board-specific */
writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
/* mx3fb.c::sdc_set_global_alpha() */
/* Use global - not per-pixel - Alpha-blending */
reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL;
writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
reg = readl(SDC_COM_CONF);
writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
/* mx3fb.c::sdc_set_color_key() */
/* Disable colour-keying for background */
reg = readl(SDC_COM_CONF) &
~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
writel(reg, SDC_COM_CONF);
mx3fb_set_par();
sdc_enable_channel(base);
/*
* Linux driver calls sdc_set_brightness() here again,
* once is enough for us
*/
debug("%s() done\n", __func__);
}
/* ------------------------ public part ------------------- */
ulong calc_fbsize(void)
{
return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
}
/*
* The current implementation is only tested for GDF_16BIT_565RGB!
* It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
* because the lcd code seemed loaded with color table stuff, that
* does not relate to most modern TFTs. cfb_console.c looks more
* straight forward.
* This is the environment setting for the original setup
* "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
* up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
* "videomode=unknown"
*
* Settings for VBEST VGG322403 display:
* "videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000,
* "le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0"
*
* Settings for COM57H5M10XRC display:
* "videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,
* "le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0"
*/
void *video_hw_init(void)
{
char *penv;
u32 memsize;
unsigned long t1, hsynch, vsynch;
int bits_per_pixel, i, tmp, videomode;
tmp = 0;
puts("Video: ");
videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
/* get video mode via environment */
penv = getenv("videomode");
if (penv) {
/* decide if it is a string */
if (penv[0] <= '9') {
videomode = (int) simple_strtoul(penv, NULL, 16);
tmp = 1;
}
} else {
tmp = 1;
}
if (tmp) {
/* parameter are vesa modes */
/* search params */
for (i = 0; i < VESA_MODES_COUNT; i++) {
if (vesa_modes[i].vesanr == videomode)
break;
}
if (i == VESA_MODES_COUNT) {
printf("No VESA Mode found, switching to mode 0x%x ",
CONFIG_SYS_DEFAULT_VIDEO_MODE);
i = 0;
}
mode = (struct ctfb_res_modes *)
&res_mode_init[vesa_modes[i].resindex];
bits_per_pixel = vesa_modes[i].bits_per_pixel;
} else {
mode = (struct ctfb_res_modes *) &var_mode;
bits_per_pixel = video_get_params(mode, penv);
}
/* calculate hsynch and vsynch freq (info only) */
t1 = (mode->left_margin + mode->xres +
mode->right_margin + mode->hsync_len) / 8;
t1 *= 8;
t1 *= mode->pixclock;
t1 /= 1000;
hsynch = 1000000000L / t1;
t1 *= (mode->upper_margin + mode->yres +
mode->lower_margin + mode->vsync_len);
t1 /= 1000;
vsynch = 1000000000L / t1;
/* fill in Graphic device struct */
sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
mode->xres, mode->yres,
bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
printf("%s\n", panel.modeIdent);
panel.winSizeX = mode->xres;
panel.winSizeY = mode->yres;
panel.plnSizeX = mode->xres;
panel.plnSizeY = mode->yres;
switch (bits_per_pixel) {
case 24:
panel.gdfBytesPP = 4;
panel.gdfIndex = GDF_32BIT_X888RGB;
break;
case 16:
panel.gdfBytesPP = 2;
panel.gdfIndex = GDF_16BIT_565RGB;
break;
default:
panel.gdfBytesPP = 1;
panel.gdfIndex = GDF__8BIT_INDEX;
break;
}
/* set up Hardware */
memsize = calc_fbsize();
debug("%s() allocating %d bytes\n", __func__, memsize);
/* fill in missing Graphic device struct */
panel.frameAdrs = (u32) malloc(memsize);
if (panel.frameAdrs == 0) {
printf("%s() malloc(%d) failed\n", __func__, memsize);
return 0;
}
panel.memSize = memsize;
ll_disp3_enable((void *) panel.frameAdrs);
memset((void *) panel.frameAdrs, 0, memsize);
debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
__func__, panel.frameAdrs, memsize);
return (void *) &panel;
}
void video_set_lut(unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
)
{
return;
}
|
1001-study-uboot
|
drivers/video/mx3fb.c
|
C
|
gpl3
| 25,069
|
/*
* (C) Copyright 2007
* DENX Software Engineering, Anatolij Gustschin, agust@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
* PCI and video mode code was derived from smiLynxEM driver.
*/
#include <common.h>
#include <asm/io.h>
#include <pci.h>
#include <video_fb.h>
#include "videomodes.h"
#include <mb862xx.h>
#if defined(CONFIG_POST)
#include <post.h>
#endif
/*
* Graphic Device
*/
GraphicDevice mb862xx;
/*
* 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
*/
#define VIDEO_MEM_SIZE 0x01FC0000
#if defined(CONFIG_PCI)
#if defined(CONFIG_VIDEO_CORALP)
static struct pci_device_id supported[] = {
{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
{ PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
{ }
};
/* Internal clock frequency divider table, index is mode number */
unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
#endif
#endif
#if defined(CONFIG_VIDEO_CORALP)
#define rd_io in32r
#define wr_io out32r
#else
#define rd_io(addr) in_be32((volatile unsigned *)(addr))
#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
#endif
#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
(val))
#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
(val))
#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
#if defined(CONFIG_VIDEO_CORALP)
#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
#else
#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
#endif
#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
(GC_DISP_BASE | GC_L0PAL0) + \
((idx) << 2)), (val))
#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
static void gdc_sw_reset (void)
{
GraphicDevice *dev = &mb862xx;
HOST_WR_REG (GC_SRST, 0x1);
udelay (500);
video_hw_init ();
}
static void de_wait (void)
{
GraphicDevice *dev = &mb862xx;
int lc = 0x10000;
/*
* Sync with software writes to framebuffer,
* try to reset if engine locked
*/
while (DE_RD_REG (GC_CTR) & 0x00000131)
if (lc-- < 0) {
gdc_sw_reset ();
puts ("gdc reset done after drawing engine lock.\n");
break;
}
}
static void de_wait_slots (int slots)
{
GraphicDevice *dev = &mb862xx;
int lc = 0x10000;
/* Wait for free fifo slots */
while (DE_RD_REG (GC_IFCNT) < slots)
if (lc-- < 0) {
gdc_sw_reset ();
puts ("gdc reset done after drawing engine lock.\n");
break;
}
}
#endif
#if !defined(CONFIG_VIDEO_CORALP)
static void board_disp_init (void)
{
GraphicDevice *dev = &mb862xx;
const gdc_regs *regs = board_get_regs ();
while (regs->index) {
DISP_WR_REG (regs->index, regs->value);
regs++;
}
}
#endif
/*
* Init drawing engine if accel enabled.
* Also clears visible framebuffer.
*/
static void de_init (void)
{
GraphicDevice *dev = &mb862xx;
#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
/* Setup mode and fbbase, xres, fg, bg */
de_wait_slots (2);
DE_WR_FIFO (0xf1010108);
DE_WR_FIFO (cf | 0x0300);
DE_WR_REG (GC_FBR, 0x0);
DE_WR_REG (GC_XRES, dev->winSizeX);
DE_WR_REG (GC_FC, 0x0);
DE_WR_REG (GC_BC, 0x0);
/* Reset clipping */
DE_WR_REG (GC_CXMIN, 0x0);
DE_WR_REG (GC_CXMAX, dev->winSizeX);
DE_WR_REG (GC_CYMIN, 0x0);
DE_WR_REG (GC_CYMAX, dev->winSizeY);
/* Clear framebuffer using drawing engine */
de_wait_slots (3);
DE_WR_FIFO (0x09410000);
DE_WR_FIFO (0x00000000);
DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
/* sync with SW access to framebuffer */
de_wait ();
#else
unsigned int i, *p;
i = dev->winSizeX * dev->winSizeY;
p = (unsigned int *)dev->frameAdrs;
while (i--)
*p++ = 0;
#endif
}
#if defined(CONFIG_VIDEO_CORALP)
/* use CCF and MMR parameters for Coral-P Eval. Board as default */
#ifndef CONFIG_SYS_MB862xx_CCF
#define CONFIG_SYS_MB862xx_CCF 0x00090000
#endif
#ifndef CONFIG_SYS_MB862xx_MMR
#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
#endif
unsigned int pci_video_init (void)
{
GraphicDevice *dev = &mb862xx;
pci_dev_t devbusfn;
u16 device;
if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
puts("controller not present\n");
return 0;
}
/* PCI setup */
pci_write_config_dword (devbusfn, PCI_COMMAND,
(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
if (dev->frameAdrs == 0) {
puts ("PCI config: failed to get base address\n");
return 0;
}
dev->pciBase = dev->frameAdrs;
puts("Coral-");
pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
switch (device) {
case PCI_DEVICE_ID_CORAL_P:
puts("P\n");
break;
case PCI_DEVICE_ID_CORAL_PA:
puts("PA\n");
break;
default:
puts("Unknown\n");
return 0;
}
/* Setup clocks and memory mode for Coral-P(A) */
HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
udelay (200);
HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
udelay (100);
return dev->frameAdrs;
}
unsigned int card_init (void)
{
GraphicDevice *dev = &mb862xx;
unsigned int cf, videomode, div = 0;
unsigned long t1, hsync, vsync;
char *penv;
int tmp, i, bpp;
struct ctfb_res_modes *res_mode;
struct ctfb_res_modes var_mode;
memset (dev, 0, sizeof (GraphicDevice));
if (!pci_video_init ())
return 0;
tmp = 0;
videomode = 0x310;
/* get video mode via environment */
if ((penv = getenv ("videomode")) != NULL) {
/* decide if it is a string */
if (penv[0] <= '9') {
videomode = (int) simple_strtoul (penv, NULL, 16);
tmp = 1;
}
} else {
tmp = 1;
}
if (tmp) {
/* parameter are vesa modes, search params */
for (i = 0; i < VESA_MODES_COUNT; i++) {
if (vesa_modes[i].vesanr == videomode)
break;
}
if (i == VESA_MODES_COUNT) {
printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
videomode);
i = 0;
}
res_mode = (struct ctfb_res_modes *)
&res_mode_init[vesa_modes[i].resindex];
if (vesa_modes[i].resindex > 2) {
puts ("\tUnsupported resolution, using default\n");
bpp = vesa_modes[1].bits_per_pixel;
div = fr_div[1];
}
bpp = vesa_modes[i].bits_per_pixel;
div = fr_div[vesa_modes[i].resindex];
} else {
res_mode = (struct ctfb_res_modes *) &var_mode;
bpp = video_get_params (res_mode, penv);
}
/* calculate hsync and vsync freq (info only) */
t1 = (res_mode->left_margin + res_mode->xres +
res_mode->right_margin + res_mode->hsync_len) / 8;
t1 *= 8;
t1 *= res_mode->pixclock;
t1 /= 1000;
hsync = 1000000000L / t1;
t1 *= (res_mode->upper_margin + res_mode->yres +
res_mode->lower_margin + res_mode->vsync_len);
t1 /= 1000;
vsync = 1000000000L / t1;
/* fill in Graphic device struct */
sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
printf ("\t%s\n", dev->modeIdent);
dev->winSizeX = res_mode->xres;
dev->winSizeY = res_mode->yres;
dev->memSize = VIDEO_MEM_SIZE;
switch (bpp) {
case 8:
dev->gdfIndex = GDF__8BIT_INDEX;
dev->gdfBytesPP = 1;
break;
case 15:
case 16:
dev->gdfIndex = GDF_15BIT_555RGB;
dev->gdfBytesPP = 2;
break;
default:
printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
bpp);
puts ("\tfallback to 15bpp\n");
dev->gdfIndex = GDF_15BIT_555RGB;
dev->gdfBytesPP = 2;
}
/* Setup dot clock (internal pll, division rate) */
DISP_WR_REG (GC_DCM1, div);
/* L0 init */
cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
(dev->winSizeY - 1) | cf);
DISP_WR_REG (GC_L0OA0, 0x0);
DISP_WR_REG (GC_L0DA0, 0x0);
DISP_WR_REG (GC_L0DY_L0DX, 0x0);
DISP_WR_REG (GC_L0EM, 0x0);
DISP_WR_REG (GC_L0WY_L0WX, 0x0);
DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
/* Display timing init */
DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
res_mode->left_margin +
res_mode->right_margin +
res_mode->hsync_len - 1) << 16);
DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
(dev->winSizeX - 1));
DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
(res_mode->hsync_len - 1) << 16 |
(dev->winSizeX +
res_mode->right_margin - 1));
DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
res_mode->upper_margin +
res_mode->vsync_len - 1) << 16);
DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
(dev->winSizeY +
res_mode->lower_margin - 1));
DISP_WR_REG (GC_WY_WX, 0x0);
DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
/* Display enable, L0 layer */
DISP_WR_REG (GC_DCM1, 0x80010000 | div);
return dev->frameAdrs;
}
#endif
#if !defined(CONFIG_VIDEO_CORALP)
int mb862xx_probe(unsigned int addr)
{
GraphicDevice *dev = &mb862xx;
unsigned int reg;
dev->frameAdrs = addr;
dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
/* Try to access GDC ID/Revision registers */
reg = HOST_RD_REG (GC_CID);
reg = HOST_RD_REG (GC_CID);
if (reg == 0x303) {
reg = DE_RD_REG(GC_REV);
reg = DE_RD_REG(GC_REV);
if ((reg & ~0xff) == 0x20050100)
return MB862XX_TYPE_LIME;
}
return 0;
}
#endif
void *video_hw_init (void)
{
GraphicDevice *dev = &mb862xx;
puts ("Video: Fujitsu ");
memset (dev, 0, sizeof (GraphicDevice));
#if defined(CONFIG_VIDEO_CORALP)
if (card_init () == 0)
return NULL;
#else
/*
* Preliminary init of the onboard graphic controller,
* retrieve base address
*/
if ((dev->frameAdrs = board_video_init ()) == 0) {
puts ("Controller not found!\n");
return NULL;
} else {
puts ("Lime\n");
/* Set Change of Clock Frequency Register */
HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
/* Delay required */
udelay(300);
/* Set Memory I/F Mode Register) */
HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
}
#endif
de_init ();
#if !defined(CONFIG_VIDEO_CORALP)
board_disp_init ();
#endif
#if (defined(CONFIG_LWMON5) || \
defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
/* Lamp on */
board_backlight_switch (1);
#endif
return dev;
}
/*
* Set a RGB color in the LUT
*/
void video_set_lut (unsigned int index, unsigned char r,
unsigned char g, unsigned char b)
{
GraphicDevice *dev = &mb862xx;
L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
}
#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
/*
* Drawing engine Fill and BitBlt screen region
*/
void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
unsigned int dst_y, unsigned int dim_x,
unsigned int dim_y, unsigned int color)
{
GraphicDevice *dev = &mb862xx;
de_wait_slots (3);
DE_WR_REG (GC_FC, color);
DE_WR_FIFO (0x09410000);
DE_WR_FIFO ((dst_y << 16) | dst_x);
DE_WR_FIFO ((dim_y << 16) | dim_x);
de_wait ();
}
void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
unsigned int src_y, unsigned int dst_x,
unsigned int dst_y, unsigned int width,
unsigned int height)
{
GraphicDevice *dev = &mb862xx;
unsigned int ctrl = 0x0d000000L;
if (src_x >= dst_x && src_y >= dst_y)
ctrl |= 0x00440000L;
else if (src_x >= dst_x && src_y <= dst_y)
ctrl |= 0x00460000L;
else if (src_x <= dst_x && src_y >= dst_y)
ctrl |= 0x00450000L;
else
ctrl |= 0x00470000L;
de_wait_slots (4);
DE_WR_FIFO (ctrl);
DE_WR_FIFO ((src_y << 16) | src_x);
DE_WR_FIFO ((dst_y << 16) | dst_x);
DE_WR_FIFO ((height << 16) | width);
de_wait (); /* sync */
}
#endif
|
1001-study-uboot
|
drivers/video/mb862xx.c
|
C
|
gpl3
| 12,412
|
#ifndef __ATI_RADEON_FB_H
#define __ATI_RADEON_FB_H
/***************************************************************
* Most of the definitions here are adapted right from XFree86 *
***************************************************************/
/*
* Chip families. Must fit in the low 16 bits of a long word
*/
enum radeon_family {
CHIP_FAMILY_UNKNOW,
CHIP_FAMILY_LEGACY,
CHIP_FAMILY_RADEON,
CHIP_FAMILY_RV100,
CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
CHIP_FAMILY_RV200,
CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
RS250 (IGP 7000) */
CHIP_FAMILY_R200,
CHIP_FAMILY_RV250,
CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
CHIP_FAMILY_RV280,
CHIP_FAMILY_R300,
CHIP_FAMILY_R350,
CHIP_FAMILY_RV350,
CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
CHIP_FAMILY_R420, /* R420/R423/M18 */
CHIP_FAMILY_LAST,
};
#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
((rinfo)->family == CHIP_FAMILY_RV200) || \
((rinfo)->family == CHIP_FAMILY_RS100) || \
((rinfo)->family == CHIP_FAMILY_RS200) || \
((rinfo)->family == CHIP_FAMILY_RV250) || \
((rinfo)->family == CHIP_FAMILY_RV280) || \
((rinfo)->family == CHIP_FAMILY_RS300))
#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
((rinfo)->family == CHIP_FAMILY_RV350) || \
((rinfo)->family == CHIP_FAMILY_R350) || \
((rinfo)->family == CHIP_FAMILY_RV380) || \
((rinfo)->family == CHIP_FAMILY_R420))
struct radeonfb_info {
char name[20];
struct pci_device_id pdev;
u16 family;
u32 fb_base_bus;
u32 mmio_base_bus;
void *mmio_base;
void *fb_base;
u32 video_ram;
u32 mapped_vram;
int vram_width;
int vram_ddr;
u32 fb_local_base;
};
#define INREG8(addr) readb((rinfo->mmio_base)+addr)
#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
#define INREG16(addr) readw((rinfo->mmio_base)+addr)
#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
#define INREG(addr) readl((rinfo->mmio_base)+addr)
#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
u32 val, u32 mask)
{
unsigned int tmp;
tmp = INREG(addr);
tmp &= (mask);
tmp |= (val);
OUTREG(addr, tmp);
}
#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask)
/*
* 2D Engine helper routines
*/
static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
{
int i;
/* initiate flush */
OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
~RB2D_DC_FLUSH_ALL);
for (i=0; i < 2000000; i++) {
if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
return;
udelay(1);
}
printf("radeonfb: Flush Timeout !\n");
}
static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
{
int i;
for (i=0; i<2000000; i++) {
if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
return;
udelay(1);
}
printf("radeonfb: FIFO Timeout !\n");
}
static inline void _radeon_engine_idle(struct radeonfb_info *rinfo)
{
int i;
/* ensure FIFO is empty before waiting for idle */
_radeon_fifo_wait (rinfo, 64);
for (i=0; i<2000000; i++) {
if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
radeon_engine_flush (rinfo);
return;
}
udelay(1);
}
printf("radeonfb: Idle Timeout !\n");
}
#define radeon_engine_idle() _radeon_engine_idle(rinfo)
#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
/*
* This structure contains the various registers manipulated by this
* driver for setting or restoring a mode. It's mostly copied from
* XFree's RADEONSaveRec structure. A few chip settings might still be
* tweaked without beeing reflected or saved in these registers though
*/
struct radeon_regs {
/* Common registers */
u32 ovr_clr;
u32 ovr_wid_left_right;
u32 ovr_wid_top_bottom;
u32 ov0_scale_cntl;
u32 mpp_tb_config;
u32 mpp_gp_config;
u32 subpic_cntl;
u32 viph_control;
u32 i2c_cntl_1;
u32 gen_int_cntl;
u32 cap0_trig_cntl;
u32 cap1_trig_cntl;
u32 bus_cntl;
u32 surface_cntl;
u32 bios_5_scratch;
/* Other registers to save for VT switches or driver load/unload */
u32 dp_datatype;
u32 rbbm_soft_reset;
u32 clock_cntl_index;
u32 amcgpio_en_reg;
u32 amcgpio_mask;
/* Surface/tiling registers */
u32 surf_lower_bound[8];
u32 surf_upper_bound[8];
u32 surf_info[8];
/* CRTC registers */
u32 crtc_gen_cntl;
u32 crtc_ext_cntl;
u32 dac_cntl;
u32 crtc_h_total_disp;
u32 crtc_h_sync_strt_wid;
u32 crtc_v_total_disp;
u32 crtc_v_sync_strt_wid;
u32 crtc_offset;
u32 crtc_offset_cntl;
u32 crtc_pitch;
u32 disp_merge_cntl;
u32 grph_buffer_cntl;
u32 crtc_more_cntl;
/* CRTC2 registers */
u32 crtc2_gen_cntl;
u32 dac2_cntl;
u32 disp_output_cntl;
u32 disp_hw_debug;
u32 disp2_merge_cntl;
u32 grph2_buffer_cntl;
u32 crtc2_h_total_disp;
u32 crtc2_h_sync_strt_wid;
u32 crtc2_v_total_disp;
u32 crtc2_v_sync_strt_wid;
u32 crtc2_offset;
u32 crtc2_offset_cntl;
u32 crtc2_pitch;
/* Flat panel regs */
u32 fp_crtc_h_total_disp;
u32 fp_crtc_v_total_disp;
u32 fp_gen_cntl;
u32 fp2_gen_cntl;
u32 fp_h_sync_strt_wid;
u32 fp2_h_sync_strt_wid;
u32 fp_horz_stretch;
u32 fp_panel_cntl;
u32 fp_v_sync_strt_wid;
u32 fp2_v_sync_strt_wid;
u32 fp_vert_stretch;
u32 lvds_gen_cntl;
u32 lvds_pll_cntl;
u32 tmds_crc;
u32 tmds_transmitter_cntl;
/* Computed values for PLL */
u32 dot_clock_freq;
int feedback_div;
int post_div;
/* PLL registers */
u32 ppll_div_3;
u32 ppll_ref_div;
u32 vclk_ecp_cntl;
u32 clk_cntl_index;
/* Computed values for PLL2 */
u32 dot_clock_freq_2;
int feedback_div_2;
int post_div_2;
/* PLL2 registers */
u32 p2pll_ref_div;
u32 p2pll_div_0;
u32 htotal_cntl2;
/* Palette */
int palette_valid;
};
static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
{
u32 data;
OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
/* radeon_pll_errata_after_index(rinfo); */
data = INREG(CLOCK_CNTL_DATA);
/* radeon_pll_errata_after_data(rinfo); */
return data;
}
static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
u32 val)
{
OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
/* radeon_pll_errata_after_index(rinfo); */
OUTREG(CLOCK_CNTL_DATA, val);
/* radeon_pll_errata_after_data(rinfo); */
}
static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
u32 val, u32 mask)
{
unsigned int tmp;
tmp = __INPLL(rinfo, index);
tmp &= (mask);
tmp |= (val);
__OUTPLL(rinfo, index, tmp);
}
#define INPLL(addr) __INPLL(rinfo, addr)
#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
#endif
|
1001-study-uboot
|
drivers/video/ati_radeon_fb.h
|
C
|
gpl3
| 6,830
|
/* ported from ctfb.c (linux kernel):
* Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
*
* Ported to U-Boot:
* (C) Copyright 2002 Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#ifdef CONFIG_VIDEO
#include <pci.h>
#include <video_fb.h>
#include "videomodes.h"
/* debug */
#undef VGA_DEBUG
#undef VGA_DUMP_REG
#ifdef VGA_DEBUG
#undef _DEBUG
#define _DEBUG 1
#else
#undef _DEBUG
#define _DEBUG 0
#endif
/* Macros */
#ifndef min
#define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
#endif
#ifndef max
#define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b )
#endif
#ifdef minmax
#error "term minmax already used."
#endif
#define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) )
#define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) )
/* CT Register Offsets */
#define CT_AR_O 0x3c0 /* Index and Data write port of the attribute Registers */
#define CT_GR_O 0x3ce /* Index port of the Graphic Controller Registers */
#define CT_SR_O 0x3c4 /* Index port of the Sequencer Controller */
#define CT_CR_O 0x3d4 /* Index port of the CRT Controller */
#define CT_XR_O 0x3d6 /* Extended Register index */
#define CT_MSR_W_O 0x3c2 /* Misc. Output Register (write only) */
#define CT_LUT_MASK_O 0x3c6 /* Color Palette Mask */
#define CT_LUT_START_O 0x3c8 /* Color Palette Write Mode Index */
#define CT_LUT_RGB_O 0x3c9 /* Color Palette Data Port */
#define CT_STATUS_REG0_O 0x3c2 /* Status Register 0 (read only) */
#define CT_STATUS_REG1_O 0x3da /* Input Status Register 1 (read only) */
#define CT_FP_O 0x3d0 /* Index port of the Flat panel Registers */
#define CT_MR_O 0x3d2 /* Index Port of the Multimedia Extension */
/* defines for the memory mapped registers */
#define BR00_o 0x400000 /* Source and Destination Span Register */
#define BR01_o 0x400004 /* Pattern/Source Expansion Background Color & Transparency Key Register */
#define BR02_o 0x400008 /* Pattern/Source Expansion Foreground Color Register */
#define BR03_o 0x40000C /* Monochrome Source Control Register */
#define BR04_o 0x400010 /* BitBLT Control Register */
#define BR05_o 0x400014 /* Pattern Address Registe */
#define BR06_o 0x400018 /* Source Address Register */
#define BR07_o 0x40001C /* Destination Address Register */
#define BR08_o 0x400020 /* Destination Width & Height Register */
#define BR09_o 0x400024 /* Source Expansion Background Color & Transparency Key Register */
#define BR0A_o 0x400028 /* Source Expansion Foreground Color Register */
#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
/* Some Mode definitions */
#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
#define FB_SYNC_EXT 4 /* external sync */
#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
/* vtotal = 144d/288n/576i => PAL */
/* vtotal = 121d/242n/484i => NTSC */
#define FB_SYNC_ON_GREEN 32 /* sync on green */
#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
#define FB_VMODE_INTERLACED 1 /* interlaced */
#define FB_VMODE_DOUBLE 2 /* double scan */
#define FB_VMODE_MASK 255
#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
#define text 0
#define fntwidth 8
/* table for VGA Initialization */
typedef struct {
const unsigned char reg;
const unsigned char val;
} CT_CFG_TABLE;
/* this table provides some basic initialisations such as Memory Clock etc */
static CT_CFG_TABLE xreg[] = {
{0x09, 0x01}, /* CRT Controller Extensions Enable */
{0x0A, 0x02}, /* Frame Buffer Mapping */
{0x0B, 0x01}, /* PCI Write Burst support */
{0x20, 0x00}, /* BitBLT Configuration */
{0x40, 0x03}, /* Memory Access Control */
{0x60, 0x00}, /* Video Pin Control */
{0x61, 0x00}, /* DPMS Synch control */
{0x62, 0x00}, /* GPIO Pin Control */
{0x63, 0xBD}, /* GPIO Pin Data */
{0x67, 0x00}, /* Pin Tri-State */
{0x80, 0x80}, /* Pixel Pipeline Config 0 register */
{0xA0, 0x00}, /* Cursor 1 Control Reg */
{0xA1, 0x00}, /* Cursor 1 Vertical Extension Reg */
{0xA2, 0x00}, /* Cursor 1 Base Address Low */
{0xA3, 0x00}, /* Cursor 1 Base Address High */
{0xA4, 0x00}, /* Cursor 1 X-Position Low */
{0xA5, 0x00}, /* Cursor 1 X-Position High */
{0xA6, 0x00}, /* Cursor 1 Y-Position Low */
{0xA7, 0x00}, /* Cursor 1 Y-Position High */
{0xA8, 0x00}, /* Cursor 2 Control Reg */
{0xA9, 0x00}, /* Cursor 2 Vertical Extension Reg */
{0xAA, 0x00}, /* Cursor 2 Base Address Low */
{0xAB, 0x00}, /* Cursor 2 Base Address High */
{0xAC, 0x00}, /* Cursor 2 X-Position Low */
{0xAD, 0x00}, /* Cursor 2 X-Position High */
{0xAE, 0x00}, /* Cursor 2 Y-Position Low */
{0xAF, 0x00}, /* Cursor 2 Y-Position High */
{0xC0, 0x7D}, /* Dot Clock 0 VCO M-Divisor */
{0xC1, 0x07}, /* Dot Clock 0 VCO N-Divisor */
{0xC3, 0x34}, /* Dot Clock 0 Divisor select */
{0xC4, 0x55}, /* Dot Clock 1 VCO M-Divisor */
{0xC5, 0x09}, /* Dot Clock 1 VCO N-Divisor */
{0xC7, 0x24}, /* Dot Clock 1 Divisor select */
{0xC8, 0x7D}, /* Dot Clock 2 VCO M-Divisor */
{0xC9, 0x07}, /* Dot Clock 2 VCO N-Divisor */
{0xCB, 0x34}, /* Dot Clock 2 Divisor select */
{0xCC, 0x38}, /* Memory Clock 0 VCO M-Divisor */
{0xCD, 0x03}, /* Memory Clock 0 VCO N-Divisor */
{0xCE, 0x90}, /* Memory Clock 0 Divisor select */
{0xCF, 0x06}, /* Clock Config */
{0xD0, 0x0F}, /* Power Down */
{0xD1, 0x01}, /* Power Down BitBLT */
{0xFF, 0xFF} /* end of table */
};
/* Clock Config:
* =============
*
* PD Registers:
* -------------
* Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor.
* They are encoded as follows:
*
* +---+--------------+
* | 2 | Loop Divisor |
* +---+--------------+
* | 1 | 1 |
* +---+--------------+
* | 0 | 4 |
* +---+--------------+
* Note: The Memory Clock does not have a Loop Divisor.
* +---+---+---+--------------+
* | 6 | 5 | 4 | Post Divisor |
* +---+---+---+--------------+
* | 0 | 0 | 0 | 1 |
* +---+---+---+--------------+
* | 0 | 0 | 1 | 2 |
* +---+---+---+--------------+
* | 0 | 1 | 0 | 4 |
* +---+---+---+--------------+
* | 0 | 1 | 1 | 8 |
* +---+---+---+--------------+
* | 1 | 0 | 0 | 16 |
* +---+---+---+--------------+
* | 1 | 0 | 1 | 32 |
* +---+---+---+--------------+
* | 1 | 1 | X | reserved |
* +---+---+---+--------------+
*
* All other bits are reserved in these registers.
*
* Clock VCO M Registers:
* ----------------------
* These Registers contain the M Value -2.
*
* Clock VCO N Registers:
* ----------------------
* These Registers contain the N Value -2.
*
* Formulas:
* ---------
* Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz
* Fout = Fvco / Post Divisor
*
* Dot Clk0 (default 25MHz):
* -------------------------
* Fvco = 14.318 * 127 / 9 = 202.045MHz
* Fout = 202.045MHz / 8 = 25.25MHz
* Post Divisor = 8
* Loop Divisor = 1
* XRC0 = (M - 2) = 125 = 0x7D
* XRC1 = (N - 2) = 7 = 0x07
* XRC3 = 0x34
*
* Dot Clk1 (default 28MHz):
* -------------------------
* Fvco = 14.318 * 87 / 11 = 113.24MHz
* Fout = 113.24MHz / 4 = 28.31MHz
* Post Divisor = 4
* Loop Divisor = 1
* XRC4 = (M - 2) = 85 = 0x55
* XRC5 = (N - 2) = 9 = 0x09
* XRC7 = 0x24
*
* Dot Clk2 (variable for extended modes set to 25MHz):
* ----------------------------------------------------
* Fvco = 14.318 * 127 / 9 = 202.045MHz
* Fout = 202.045MHz / 8 = 25.25MHz
* Post Divisor = 8
* Loop Divisor = 1
* XRC8 = (M - 2) = 125 = 0x7D
* XRC9 = (N - 2) = 7 = 0x07
* XRCB = 0x34
*
* Memory Clk for most modes >50MHz:
* ----------------------------------
* Fvco = 14.318 * 58 / 5 = 166MHz
* Fout = 166MHz / 2 = 83MHz
* Post Divisor = 2
* XRCC = (M - 2) = 57 = 0x38
* XRCD = (N - 2) = 3 = 0x03
* XRCE = 0x90
*
* Note Bit7 enables the clock source from the VCO
*
*/
/*******************************************************************
* Chips struct
*******************************************************************/
struct ctfb_chips_properties {
int device_id; /* PCI Device ID */
unsigned long max_mem; /* memory for frame buffer */
int vld_set; /* value of VLD if bit2 in clock control is set */
int vld_not_set; /* value of VLD if bit2 in clock control is set */
int mn_diff; /* difference between M/N Value + mn_diff = M/N Register */
int mn_min; /* min value of M/N Value */
int mn_max; /* max value of M/N Value */
int vco_min; /* VCO Min in MHz */
int vco_max; /* VCO Max in MHz */
};
static const struct ctfb_chips_properties chips[] = {
{PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
#ifdef CONFIG_USE_CPCIDVI
{PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220},
#endif
{PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
{0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
};
/*
* The Graphic Device
*/
GraphicDevice ctfb;
/*******************************************************************************
*
* Low Level Routines
*/
/*******************************************************************************
*
* Read CT ISA register
*/
#ifdef VGA_DEBUG
static unsigned char
ctRead (unsigned short index)
{
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
if (index == CT_AR_O)
/* synch the Flip Flop */
in8 (pGD->isaBase + CT_STATUS_REG1_O);
return (in8 (pGD->isaBase + index));
}
#endif
/*******************************************************************************
*
* Write CT ISA register
*/
static void
ctWrite (unsigned short index, unsigned char val)
{
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
out8 ((pGD->isaBase + index), val);
}
/*******************************************************************************
*
* Read CT ISA register indexed
*/
static unsigned char
ctRead_i (unsigned short index, char reg)
{
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
if (index == CT_AR_O)
/* synch the Flip Flop */
in8 (pGD->isaBase + CT_STATUS_REG1_O);
out8 ((pGD->isaBase + index), reg);
return (in8 (pGD->isaBase + index + 1));
}
/*******************************************************************************
*
* Write CT ISA register indexed
*/
static void
ctWrite_i (unsigned short index, char reg, char val)
{
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
if (index == CT_AR_O) {
/* synch the Flip Flop */
in8 (pGD->isaBase + CT_STATUS_REG1_O);
out8 ((pGD->isaBase + index), reg);
out8 ((pGD->isaBase + index), val);
} else {
out8 ((pGD->isaBase + index), reg);
out8 ((pGD->isaBase + index + 1), val);
}
}
/*******************************************************************************
*
* Write a table of CT ISA register
*/
static void
ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab)
{
while (regTab->reg != 0xFF) {
ctWrite_i (index, regTab->reg, regTab->val);
regTab++;
}
}
/*****************************************************************************/
static void
SetArRegs (void)
{
int i, tmp;
for (i = 0; i < 0x10; i++)
ctWrite_i (CT_AR_O, i, i);
if (text)
tmp = 0x04;
else
tmp = 0x41;
ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */
ctWrite_i (CT_AR_O, 0x11, 0x00); /* Overscan Color Register */
ctWrite_i (CT_AR_O, 0x12, 0x0f); /* Memory Plane Enable Register */
if (fntwidth == 9)
tmp = 0x08;
else
tmp = 0x00;
ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */
ctWrite_i (CT_AR_O, 0x14, 0x00); /* Color Select Register */
ctWrite (CT_AR_O, 0x20); /* enable video */
}
/*****************************************************************************/
static void
SetGrRegs (void)
{ /* Set Graphics Mode */
int i;
for (i = 0; i < 0x05; i++)
ctWrite_i (CT_GR_O, i, 0);
if (text) {
ctWrite_i (CT_GR_O, 0x05, 0x10);
ctWrite_i (CT_GR_O, 0x06, 0x02);
} else {
ctWrite_i (CT_GR_O, 0x05, 0x40);
ctWrite_i (CT_GR_O, 0x06, 0x05);
}
ctWrite_i (CT_GR_O, 0x07, 0x0f);
ctWrite_i (CT_GR_O, 0x08, 0xff);
}
/*****************************************************************************/
static void
SetSrRegs (void)
{
int tmp = 0;
ctWrite_i (CT_SR_O, 0x00, 0x00); /* reset */
/*rr( sr, 0x01, tmp );
if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01;
wr( sr, 0x01, tmp ); */
if (fntwidth == 8)
ctWrite_i (CT_SR_O, 0x01, 0x01); /* Clocking Mode Register */
else
ctWrite_i (CT_SR_O, 0x01, 0x00); /* Clocking Mode Register */
ctWrite_i (CT_SR_O, 0x02, 0x0f); /* Enable CPU wr access to given memory plane */
ctWrite_i (CT_SR_O, 0x03, 0x00); /* Character Map Select Register */
if (text)
tmp = 0x02;
else
tmp = 0x0e;
ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB
total VGA memory beyond the first 64KB and set
fb mapping mode. */
ctWrite_i (CT_SR_O, 0x00, 0x03); /* enable */
}
/*****************************************************************************/
static void
SetBitsPerPixelIntoXrRegs (int bpp)
{
unsigned int n = (bpp >> 3), tmp; /* only for 15, 8, 16, 24 bpp */
static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */
static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 }; /* mask */
static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */
if (bpp == 15)
n = 0;
tmp = ctRead_i (CT_XR_O, 0x20);
tmp &= off[n];
tmp |= on[n];
ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
ctWrite_i (CT_XR_O, 0x81, md[n]);
}
/*****************************************************************************/
static void
SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel)
{ /* he -le- ht|0 hd -ri- hs -h- he */
unsigned char cr[0x7a];
int i, tmp;
unsigned int hd, hs, he, ht, hbe; /* Horizontal. */
unsigned int vd, vs, ve, vt; /* vertical */
unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine;
unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay;
unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl;
unsigned int HorizontalEqualizationPulses;
unsigned int HorizontalSerration1Start, HorizontalSerration2Start;
const int LineCompare = 0x3ff;
unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */
unsigned int RAMDAC_BlankPedestalEnable = 0; /* 1=en-, 0=disable, see XR82 */
hd = (var->xres) / 8; /* HDisp. */
hs = (var->xres + var->right_margin) / 8; /* HsStrt */
he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */
ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */
hbe = ht - 1; /* HBlankEnable todo docu wants ht here, but it does not work */
/* ve -up- vt|0 vd -lo- vs -v- ve */
vd = var->yres; /* VDisplay */
vs = var->yres + var->lower_margin; /* VSyncStart */
ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */
vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */
bpp = bits_per_pixel;
dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0;
interlaced = var->vmode & FB_VMODE_INTERLACED;
bcast = var->sync & FB_SYNC_BROADCAST;
CrtHalfLine = bcast ? (hd >> 1) : 0;
BlDelayCtrl = bcast ? 1 : 0;
CompSyncCharClkDelay = 0; /* 2 bit */
CompSyncPixelClkDelay = 0; /* 3 bit */
if (bcast) {
NTSC_PAL_HorizontalPulseWidth = 7; /*( var->hsync_len >> 1 ) + 1 */
HorizontalEqualizationPulses = 0; /* inverse value */
HorizontalSerration1Start = 31; /* ( ht >> 1 ) */
HorizontalSerration2Start = 89; /* ( ht >> 1 ) */
} else {
NTSC_PAL_HorizontalPulseWidth = 0;
/* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] )
* / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */
HorizontalEqualizationPulses = 1; /* inverse value */
HorizontalSerration1Start = 0; /* ( ht >> 1 ) */
HorizontalSerration2Start = 0; /* ( ht >> 1 ) */
}
if (bpp == 15)
bpp = 16;
wd = var->xres * bpp / 64; /* double words per line */
if (interlaced) { /* we divide all vertical timings, exept vd */
vs >>= 1;
ve >>= 1;
vt >>= 1;
}
memset (cr, 0, sizeof (cr));
cr[0x00] = 0xff & (ht - 5);
cr[0x01] = hd - 1; /* soll:4f ist 59 */
cr[0x02] = hd;
cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd */
cr[0x04] = hs;
cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
cr[0x06] = (vt - 2) & 0xFF;
cr[0x30] = (vt - 2) >> 8;
cr[0x07] = ((vt & 0x100) >> 8)
| ((vd & 0x100) >> 7)
| ((vs & 0x100) >> 6)
| ((vs & 0x100) >> 5)
| ((LineCompare & 0x100) >> 4)
| ((vt & 0x200) >> 4)
| ((vd & 0x200) >> 3)
| ((vs & 0x200) >> 2);
cr[0x08] = 0x00;
cr[0x09] = (dblscan << 7)
| ((LineCompare & 0x200) >> 3)
| ((vs & 0x200) >> 4)
| (TextScanLines - 1);
cr[0x10] = vs & 0xff; /* VSyncPulseStart */
cr[0x32] = (vs & 0xf00) >> 8; /* VSyncPulseStart */
cr[0x11] = (ve & 0x0f); /* | 0x20; */
cr[0x12] = (vd - 1) & 0xff; /* LineCount */
cr[0x31] = ((vd - 1) & 0xf00) >> 8; /* LineCount */
cr[0x13] = wd & 0xff;
cr[0x41] = (wd & 0xf00) >> 8;
cr[0x15] = vs & 0xff;
cr[0x33] = (vs & 0xf00) >> 8;
cr[0x38] = (0x100 & (ht - 5)) >> 8;
cr[0x3C] = 0xc0 & hbe;
cr[0x16] = (vt - 1) & 0xff; /* vbe - docu wants vt here, */
cr[0x17] = 0xe3; /* but it does not work */
cr[0x18] = 0xff & LineCompare;
cr[0x22] = 0xff; /* todo? */
cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00; /* check:0xa6 */
cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6)
| (BlDelayCtrl << 5)
| ((0x03 & CompSyncCharClkDelay) << 3)
| (0x07 & CompSyncPixelClkDelay); /* todo: see XR82 */
cr[0x72] = HorizontalSerration1Start;
cr[0x73] = HorizontalSerration2Start;
cr[0x74] = (HorizontalEqualizationPulses << 5)
| NTSC_PAL_HorizontalPulseWidth;
/* todo: ct69000 has also 0x75-79 */
/* now set the registers */
for (i = 0; i <= 0x0d; i++) { /*CR00 .. CR0D */
ctWrite_i (CT_CR_O, i, cr[i]);
}
for (i = 0x10; i <= 0x18; i++) { /*CR10 .. CR18 */
ctWrite_i (CT_CR_O, i, cr[i]);
}
i = 0x22; /*CR22 */
ctWrite_i (CT_CR_O, i, cr[i]);
for (i = 0x30; i <= 0x33; i++) { /*CR30 .. CR33 */
ctWrite_i (CT_CR_O, i, cr[i]);
}
i = 0x38; /*CR38 */
ctWrite_i (CT_CR_O, i, cr[i]);
i = 0x3C; /*CR3C */
ctWrite_i (CT_CR_O, i, cr[i]);
for (i = 0x40; i <= 0x41; i++) { /*CR40 .. CR41 */
ctWrite_i (CT_CR_O, i, cr[i]);
}
for (i = 0x70; i <= 0x74; i++) { /*CR70 .. CR74 */
ctWrite_i (CT_CR_O, i, cr[i]);
}
tmp = ctRead_i (CT_CR_O, 0x40);
tmp &= 0x0f;
tmp |= 0x80;
ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */
}
/* pixelclock control */
/*****************************************************************************
We have a rational number p/q and need an m/n which is very close to p/q
but has m and n within mnmin and mnmax. We have no floating point in the
kernel. We can use long long without divide. And we have time to compute...
******************************************************************************/
static unsigned int
FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin,
unsigned int mnmax, unsigned int *pm, unsigned int *pn)
{
/* this code is not for general purpose usable but good for our number ranges */
unsigned int n = mnmin, m = 0;
long long int L = 0, P = p, Q = q, H = P >> 1;
long long int D = 0x7ffffffffffffffLL;
for (n = mnmin; n <= mnmax; n++) {
m = mnmin; /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */
L = P * n - m * Q; /* n * vco - m * fref should be near 0 */
while (L > 0 && m < mnmax) {
L -= q; /* difference is greater as 0 subtract fref */
m++; /* and increment m */
}
/* difference is less or equal than 0 or m > maximum */
if (m > mnmax)
break; /* no solution: if we increase n we get the same situation */
/* L is <= 0 now */
if (-L > H && m > mnmin) { /* if difference > the half fref */
L += q; /* we take the situation before */
m--; /* because its closer to 0 */
}
L = (L < 0) ? -L : +L; /* absolute value */
if (D < L) /* if last difference was better take next n */
continue;
D = L;
*pm = m;
*pn = n; /* keep improved data */
if (D == 0)
break; /* best result we can get */
}
return (unsigned int) (0xffffffff & D);
}
/* that is the hardware < 69000 we have to manage
+---------+ +-------------------+ +----------------------+ +--+
| REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
| 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | |
+---------+ +-------------------+ +----------------------+ +--+ |
___________________________________________________________________|
|
| fvco fout
| +--------+ +------------+ +-----+ +-------------------+ +----+
+-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
+-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
| +--------+ +------------+ +-----+ | +-------------------+ +----+
| |
| +--+ +---------------+ |
|____|÷M|___|VCO Loop Divide|__________|
| | |(VLD)(÷4, ÷16) |
+--+ +---------------+
****************************************************************************
that is the hardware >= 69000 we have to manage
+---------+ +--+
| REFCLK |__|÷N|__
| 14.3MHz | | | |
+---------+ +--+ |
__________________|
|
| fvco fout
| +--------+ +------------+ +-----+ +-------------------+ +----+
+-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
+-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
| +--------+ +------------+ +-----+ | +-------------------+ +----+
| |
| +--+ +---------------+ |
|____|÷M|___|VCO Loop Divide|__________|
| | |(VLD)(÷1, ÷4) |
+--+ +---------------+
*/
#define VIDEO_FREF 14318180; /* Hz */
/*****************************************************************************/
static int
ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param)
{
unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock;
i = 0;
pixclock = -1;
fref = VIDEO_FREF;
m = ctRead_i (CT_XR_O, 0xc8);
n = ctRead_i (CT_XR_O, 0xc9);
m -= param->mn_diff;
n -= param->mn_diff;
xr_cb = ctRead_i (CT_XR_O, 0xcb);
PD = (0x70 & xr_cb) >> 4;
pd = 1;
for (i = 0; i < PD; i++) {
pd *= 2;
}
vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set;
if (n * vld * m) {
unsigned long long p = 1000000000000LL * pd * n;
unsigned long long q = (long long) fref * vld * m;
while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) {
p >>= 1; /* can't divide with long long so we scale down */
q >>= 1;
}
pixclock = (unsigned) p / (unsigned) q;
} else
printf ("Invalid data in xr regs.\n");
return pixclock;
}
/*****************************************************************************/
static void
FindAndSetPllParamIntoXrRegs (unsigned int pixelclock,
struct ctfb_chips_properties *param)
{
unsigned int m, n, vld, pd, PD, fref, xr_cb;
unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk;
unsigned int pfreq, fvco, new_pixclock;
unsigned int D,nback,mback;
fref = VIDEO_FREF;
pd = 1;
PD = 0;
fvcomin = param->vco_min;
fvcomax = param->vco_max; /* MHz */
pclckmin = 1000000 / fvcomax + 1; /* 4546 */
pclckmax = 32000000 / fvcomin - 1; /* 666665 */
pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */
pfreq = 250 * (4000000000U / pclk);
fvco = pfreq; /* Hz */
new_pixclock = 0;
while (fvco < fvcomin * 1000000) {
/* double VCO starting with the pixelclock frequency
* as long as it is lower than the minimal VCO frequency */
fvco *= 2;
pd *= 2;
PD++;
}
/* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */
/* first try */
vld = param->vld_set;
D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */
mback=m;
nback=n;
/* second try */
vld = param->vld_not_set;
if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) { /* rds = 1 */
/* first try was better */
m=mback;
n=nback;
vld = param->vld_set;
}
m += param->mn_diff;
n += param->mn_diff;
debug("VCO %d, pd %d, m %d n %d vld %d\n", fvco, pd, m, n, vld);
xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
/* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
* written, and in order from XRC8 to XRCB, before the hardware will
* update the synthesizer s settings.
*/
ctWrite_i (CT_XR_O, 0xc8, m);
ctWrite_i (CT_XR_O, 0xc9, n); /* xrca does not exist in CT69000 and CT69030 */
ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */
ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */
new_pixclock = ReadPixClckFromXrRegsBack (param);
debug("pixelclock.set = %d, pixelclock.real = %d\n",
pixelclock, new_pixclock);
}
/*****************************************************************************/
static void
SetMsrRegs (struct ctfb_res_modes *mode)
{
unsigned char h_synch_high, v_synch_high;
h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */
v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */
ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29));
/* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
* Selects the upper 64KB page.Bit5=1
* CLK2 (left reserved in standard VGA) Bit3|2=1|0
* Disables CPU access to frame buffer. Bit1=0
* Sets the I/O address decode for ST01, FCR, and all CR registers
* to the 3Dx I/O address range (CGA emulation). Bit0=1
*/
}
/************************************************************************************/
#ifdef VGA_DUMP_REG
static void
ctDispRegs (unsigned short index, int from, int to)
{
unsigned char status;
int i;
for (i = from; i < to; i++) {
status = ctRead_i (index, i);
printf ("%02X: is %02X\n", i, status);
}
}
void
video_dump_reg (void)
{
int i;
printf ("Extended Regs:\n");
ctDispRegs (CT_XR_O, 0, 0xC);
ctDispRegs (CT_XR_O, 0xe, 0xf);
ctDispRegs (CT_XR_O, 0x20, 0x21);
ctDispRegs (CT_XR_O, 0x40, 0x50);
ctDispRegs (CT_XR_O, 0x60, 0x64);
ctDispRegs (CT_XR_O, 0x67, 0x68);
ctDispRegs (CT_XR_O, 0x70, 0x72);
ctDispRegs (CT_XR_O, 0x80, 0x83);
ctDispRegs (CT_XR_O, 0xA0, 0xB0);
ctDispRegs (CT_XR_O, 0xC0, 0xD3);
printf ("Sequencer Regs:\n");
ctDispRegs (CT_SR_O, 0, 0x8);
printf ("Graphic Regs:\n");
ctDispRegs (CT_GR_O, 0, 0x9);
printf ("CRT Regs:\n");
ctDispRegs (CT_CR_O, 0, 0x19);
ctDispRegs (CT_CR_O, 0x22, 0x23);
ctDispRegs (CT_CR_O, 0x30, 0x34);
ctDispRegs (CT_CR_O, 0x38, 0x39);
ctDispRegs (CT_CR_O, 0x3C, 0x3D);
ctDispRegs (CT_CR_O, 0x40, 0x42);
ctDispRegs (CT_CR_O, 0x70, 0x80);
/* don't display the attributes */
}
#endif
#ifdef CONFIG_VIDEO_HW_CURSOR
/***************************************************************
* Set Hardware Cursor in Pixel
*/
void
video_set_hw_cursor (int x, int y)
{
int sig_x = 0, sig_y = 0;
if (x < 0) {
x *= -1;
sig_x = 1;
}
if (y < 0) {
y *= -1;
sig_y = 1;
}
ctWrite_i (CT_XR_O, 0xa4, x & 0xff);
ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7);
ctWrite_i (CT_XR_O, 0xa6, y & 0xff);
ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7);
}
/***************************************************************
* Init Hardware Cursor. To know the size of the Cursor,
* we have to know the Font size.
*/
void
video_init_hw_cursor (int font_width, int font_height)
{
unsigned char xr_80;
unsigned long *curs, pattern;
int i;
int cursor_start;
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
cursor_start = pGD->dprBase;
xr_80 = ctRead_i (CT_XR_O, 0x80);
/* set start address */
ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0);
ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f);
/* set cursor shape */
curs = (unsigned long *) cursor_start;
i = 0;
while (i < 0x400) {
curs[i++] = 0xffffffff; /* AND mask */
curs[i++] = 0xffffffff; /* AND mask */
curs[i++] = 0; /* XOR mask */
curs[i++] = 0; /* XOR mask */
/* Transparent */
}
pattern = 0xffffffff >> font_width;
i = 0;
while (i < (font_height * 2)) {
curs[i++] = pattern; /* AND mask */
curs[i++] = pattern; /* AND mask */
curs[i++] = 0; /* XOR mask */
curs[i++] = 0; /* XOR mask */
/* Cursor Color 0 */
}
/* set blink rate */
ctWrite_i (CT_FP_O, 0x19, 0xf);
/* set cursors colors */
xr_80 = ctRead_i (CT_XR_O, 0x80);
xr_80 |= 0x1; /* alternate palette select */
ctWrite_i (CT_XR_O, 0x80, xr_80);
video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL);
/* position 4 is color 0 cursor 0 */
xr_80 &= 0xfe; /* normal palette select */
ctWrite_i (CT_XR_O, 0x80, xr_80);
/* cursor enable */
ctWrite_i (CT_XR_O, 0xa0, 0x91);
xr_80 |= 0x10; /* enable hwcursor */
ctWrite_i (CT_XR_O, 0x80, xr_80);
video_set_hw_cursor (0, 0);
}
#endif /* CONFIG_VIDEO_HW_CURSOR */
/***************************************************************
* Wait for BitBlt ready
*/
static int
video_wait_bitblt (unsigned long addr)
{
unsigned long br04;
int i = 0;
br04 = in32r (addr);
while (br04 & 0x80000000) {
udelay (1);
br04 = in32r (addr);
if (i++ > 1000000) {
printf ("ERROR Timeout %lx\n", br04);
return 1;
}
}
return 0;
}
/***************************************************************
* Set up BitBlt Registrs
*/
static void
SetDrawingEngine (int bits_per_pixel)
{
unsigned long br04, br00;
unsigned char tmp;
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */
tmp |= 0x02; /* reset BitBLT */
ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
udelay (10);
tmp &= 0xfd; /* release reset BitBLT */
ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
video_wait_bitblt (pGD->pciBase + BR04_o);
/* set pattern Address */
out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8);
br04 = 0;
if (bits_per_pixel == 1) {
br04 |= 0x00040000; /* monochome Pattern */
br04 |= 0x00001000; /* monochome source */
}
br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP); /* bytes per scanline */
out32r (pGD->pciBase + BR00_o, br00); /* */
out32r (pGD->pciBase + BR08_o, (10 << 16) + 10); /* dummy */
out32r (pGD->pciBase + BR04_o, br04); /* write all 0 */
out32r (pGD->pciBase + BR07_o, 0); /* destination */
video_wait_bitblt (pGD->pciBase + BR04_o);
}
/****************************************************************************
* supported Video Chips
*/
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
#ifdef CONFIG_USE_CPCIDVI
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030},
#endif
{}
};
/*******************************************************************************
*
* Init video chip
*/
void *
video_hw_init (void)
{
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
unsigned short device_id;
pci_dev_t devbusfn;
int videomode;
unsigned long t1, hsynch, vsynch;
unsigned int pci_mem_base, *vm;
int tmp, i, bits_per_pixel;
char *penv;
struct ctfb_res_modes *res_mode;
struct ctfb_res_modes var_mode;
struct ctfb_chips_properties *chips_param;
/* Search for video chip */
if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
#ifdef CONFIG_VIDEO_ONBOARD
printf ("Video: Controller not found !\n");
#endif
return (NULL);
}
/* PCI setup */
pci_write_config_dword (devbusfn, PCI_COMMAND,
(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
/* get chips params */
for (chips_param = (struct ctfb_chips_properties *) &chips[0];
chips_param->device_id != 0; chips_param++) {
if (chips_param->device_id == device_id)
break;
}
if (chips_param->device_id == 0) {
#ifdef CONFIG_VIDEO_ONBOARD
printf ("Video: controller 0x%X not supported\n", device_id);
#endif
return NULL;
}
/* supported Video controller found */
printf ("Video: ");
tmp = 0;
videomode = 0x301;
/* get video mode via environment */
if ((penv = getenv ("videomode")) != NULL) {
/* deceide if it is a string */
if (penv[0] <= '9') {
videomode = (int) simple_strtoul (penv, NULL, 16);
tmp = 1;
}
} else {
tmp = 1;
}
if (tmp) {
/* parameter are vesa modes */
/* search params */
for (i = 0; i < VESA_MODES_COUNT; i++) {
if (vesa_modes[i].vesanr == videomode)
break;
}
if (i == VESA_MODES_COUNT) {
printf ("no VESA Mode found, switching to mode 0x301 ");
i = 0;
}
res_mode =
(struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].
resindex];
bits_per_pixel = vesa_modes[i].bits_per_pixel;
} else {
res_mode = (struct ctfb_res_modes *) &var_mode;
bits_per_pixel = video_get_params (res_mode, penv);
}
/* calculate available color depth for controller memory */
if (bits_per_pixel == 15)
tmp = 2;
else
tmp = bits_per_pixel >> 3; /* /8 */
if (((chips_param->max_mem -
ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) {
tmp =
((chips_param->max_mem -
ACCELMEMORY) / (res_mode->xres * res_mode->yres));
if (tmp == 0) {
printf
("No matching videomode found .-> reduce resolution\n");
return NULL;
} else {
printf ("Switching back to %d Bits per Pixel ",
tmp << 3);
bits_per_pixel = tmp << 3;
}
}
/* calculate hsynch and vsynch freq (info only) */
t1 = (res_mode->left_margin + res_mode->xres +
res_mode->right_margin + res_mode->hsync_len) / 8;
t1 *= 8;
t1 *= res_mode->pixclock;
t1 /= 1000;
hsynch = 1000000000L / t1;
t1 *=
(res_mode->upper_margin + res_mode->yres +
res_mode->lower_margin + res_mode->vsync_len);
t1 /= 1000;
vsynch = 1000000000L / t1;
/* fill in Graphic device struct */
sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
res_mode->yres, bits_per_pixel, (hsynch / 1000),
(vsynch / 1000));
printf ("%s\n", pGD->modeIdent);
pGD->winSizeX = res_mode->xres;
pGD->winSizeY = res_mode->yres;
pGD->plnSizeX = res_mode->xres;
pGD->plnSizeY = res_mode->yres;
switch (bits_per_pixel) {
case 8:
pGD->gdfBytesPP = 1;
pGD->gdfIndex = GDF__8BIT_INDEX;
break;
case 15:
pGD->gdfBytesPP = 2;
pGD->gdfIndex = GDF_15BIT_555RGB;
break;
case 16:
pGD->gdfBytesPP = 2;
pGD->gdfIndex = GDF_16BIT_565RGB;
break;
case 24:
pGD->gdfBytesPP = 3;
pGD->gdfIndex = GDF_24BIT_888RGB;
break;
}
pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
pGD->pciBase = pci_mem_base;
pGD->frameAdrs = pci_mem_base;
pGD->memSize = chips_param->max_mem;
/* Cursor Start Address */
pGD->dprBase =
(pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base;
if ((pGD->dprBase & 0x0fff) != 0) {
/* allign it */
pGD->dprBase &= 0xfffff000;
pGD->dprBase += 0x00001000;
}
debug("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
PATTERN_ADR);
pGD->vprBase = pci_mem_base; /* Dummy */
pGD->cprBase = pci_mem_base; /* Dummy */
/* set up Hardware */
#ifdef CONFIG_USE_CPCIDVI
if (device_id == PCI_DEVICE_ID_CT_69030) {
ctWrite (CT_MSR_W_O, 0x0b);
ctWrite (0x3cd, 0x13);
ctWrite_i (CT_FP_O, 0x02, 0x00);
ctWrite_i (CT_FP_O, 0x05, 0x00);
ctWrite_i (CT_FP_O, 0x06, 0x00);
ctWrite (0x3c2, 0x0b);
ctWrite_i (CT_FP_O, 0x02, 0x10);
ctWrite_i (CT_FP_O, 0x01, 0x09);
} else {
ctWrite (CT_MSR_W_O, 0x01);
}
#else
ctWrite (CT_MSR_W_O, 0x01);
#endif
/* set the extended Registers */
ctLoadRegs (CT_XR_O, xreg);
/* set atribute registers */
SetArRegs ();
/* set Graphics register */
SetGrRegs ();
/* set sequencer */
SetSrRegs ();
/* set msr */
SetMsrRegs (res_mode);
/* set CRT Registers */
SetCrRegs (res_mode, bits_per_pixel);
/* set color mode */
SetBitsPerPixelIntoXrRegs (bits_per_pixel);
/* set PLL */
FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param);
ctWrite_i (CT_SR_O, 0, 0x03); /* clear synchronous reset */
/* Clear video memory */
i = pGD->memSize / 4;
vm = (unsigned int *) pGD->pciBase;
while (i--)
*vm++ = 0;
SetDrawingEngine (bits_per_pixel);
#ifdef VGA_DUMP_REG
video_dump_reg ();
#endif
return ((void *) &ctfb);
}
/*******************************************************************************
*
* Set a RGB color in the LUT (8 bit index)
*/
void
video_set_lut (unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
)
{
ctWrite (CT_LUT_MASK_O, 0xff);
ctWrite (CT_LUT_START_O, (char) index);
ctWrite (CT_LUT_RGB_O, r); /* red */
ctWrite (CT_LUT_RGB_O, g); /* green */
ctWrite (CT_LUT_RGB_O, b); /* blue */
udelay (1);
ctWrite (CT_LUT_MASK_O, 0xff);
}
/*******************************************************************************
*
* Drawing engine fill on screen region
*/
void
video_hw_rectfill (unsigned int bpp, /* bytes per pixel */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y, /* frame height */
unsigned int color /* fill color */
)
{
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
unsigned long *p, br04;
video_wait_bitblt (pGD->pciBase + BR04_o);
p = (unsigned long *) PATTERN_ADR;
dim_x *= bpp;
if (bpp == 3)
bpp++; /* 24Bit needs a 32bit pattern */
memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8)); /* 8 x 8 pattern data */
out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00;
br04 |= 0xF0; /* write Pattern P -> D */
out32r (pGD->pciBase + BR04_o, br04); /* */
out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* starts the BITBlt */
video_wait_bitblt (pGD->pciBase + BR04_o);
}
/*******************************************************************************
*
* Drawing engine bitblt with screen region
*/
void
video_hw_bitblt (unsigned int bpp, /* bytes per pixel */
unsigned int src_x, /* source pos x */
unsigned int src_y, /* source pos y */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y /* frame height */
)
{
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
unsigned long br04;
br04 = in32r (pGD->pciBase + BR04_o);
/* to prevent data corruption due to overlap, we have to
* find out if, and how the frames overlaps */
if (src_x < dst_x) {
/* src is more left than dest
* the frame may overlap -> start from right to left */
br04 |= 0x00000100; /* set bit 8 */
src_x += dim_x;
dst_x += dim_x;
} else {
br04 &= 0xfffffeff; /* clear bit 8 left to right */
}
if (src_y < dst_y) {
/* src is higher than dst
* the frame may overlap => start from bottom */
br04 |= 0x00000200; /* set bit 9 */
src_y += dim_y;
dst_y += dim_y;
} else {
br04 &= 0xfffffdff; /* clear bit 9 top to bottom */
}
dim_x *= bpp;
out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP); /* source */
out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
br04 &= 0xffffff00;
br04 |= 0x000000CC; /* S -> D */
out32r (pGD->pciBase + BR04_o, br04); /* */
out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* start the BITBlt */
video_wait_bitblt (pGD->pciBase + BR04_o);
}
#endif /* CONFIG_VIDEO */
|
1001-study-uboot
|
drivers/video/ct69000.c
|
C
|
gpl3
| 40,786
|
/*
* (C) Copyright 2004
* Pierre Aubert, Staubli Faverges , <p.aubert@staubli.com>
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************************************
Get Parameters for the video mode:
The default video mode can be defined in CONFIG_SYS_DEFAULT_VIDEO_MODE.
If undefined, default video mode is set to 0x301
Parameters can be set via the variable "videomode" in the environment.
2 diferent ways are possible:
"videomode=301" - 301 is a hexadecimal number describing the VESA
mode. Following modes are implemented:
Colors 640x480 800x600 1024x768 1152x864 1280x1024
--------+---------------------------------------------
8 bits | 0x301 0x303 0x305 0x161 0x307
15 bits | 0x310 0x313 0x316 0x162 0x319
16 bits | 0x311 0x314 0x317 0x163 0x31A
24 bits | 0x312 0x315 0x318 ? 0x31B
--------+---------------------------------------------
"videomode=bootargs"
- the parameters are parsed from the bootargs.
The format is "NAME:VALUE,NAME:VALUE" etc.
Ex.:
"bootargs=video=ctfb:x:800,y:600,depth:16,pclk:25000"
Parameters not included in the list will be taken from
the default mode, which is one of the following:
mode:0 640x480x24
mode:1 800x600x16
mode:2 1024x768x8
mode:3 960x720x24
mode:4 1152x864x16
mode:5 1280x1024x8
if "mode" is not provided within the parameter list,
mode:0 is assumed.
Following parameters are supported:
x xres = visible resolution horizontal
y yres = visible resolution vertical
pclk pixelclocks in pico sec
le left_marging time from sync to picture in pixelclocks
ri right_marging time from picture to sync in pixelclocks
up upper_margin time from sync to picture
lo lower_margin
hs hsync_len length of horizontal sync
vs vsync_len length of vertical sync
sync see FB_SYNC_*
vmode see FB_VMODE_*
depth Color depth in bits per pixel
All other parameters in the variable bootargs are ignored.
It is also possible to set the parameters direct in the
variable "videomode", or in another variable i.e.
"myvideo" and setting the variable "videomode=myvideo"..
****************************************************************************/
#include <common.h>
#include <linux/ctype.h>
#include "videomodes.h"
const struct ctfb_vesa_modes vesa_modes[VESA_MODES_COUNT] = {
{0x301, RES_MODE_640x480, 8},
{0x310, RES_MODE_640x480, 15},
{0x311, RES_MODE_640x480, 16},
{0x312, RES_MODE_640x480, 24},
{0x303, RES_MODE_800x600, 8},
{0x313, RES_MODE_800x600, 15},
{0x314, RES_MODE_800x600, 16},
{0x315, RES_MODE_800x600, 24},
{0x305, RES_MODE_1024x768, 8},
{0x316, RES_MODE_1024x768, 15},
{0x317, RES_MODE_1024x768, 16},
{0x318, RES_MODE_1024x768, 24},
{0x161, RES_MODE_1152x864, 8},
{0x162, RES_MODE_1152x864, 15},
{0x163, RES_MODE_1152x864, 16},
{0x307, RES_MODE_1280x1024, 8},
{0x319, RES_MODE_1280x1024, 15},
{0x31A, RES_MODE_1280x1024, 16},
{0x31B, RES_MODE_1280x1024, 24},
};
const struct ctfb_res_modes res_mode_init[RES_MODES_COUNT] = {
/* x y pixclk le ri up lo hs vs s vmode */
{640, 480, 39721, 40, 24, 32, 11, 96, 2, 0, FB_VMODE_NONINTERLACED},
{800, 600, 27778, 64, 24, 22, 1, 72, 2, 0, FB_VMODE_NONINTERLACED},
{1024, 768, 15384, 168, 8, 29, 3, 144, 4, 0, FB_VMODE_NONINTERLACED},
{960, 720, 13100, 160, 40, 32, 8, 80, 4, 0, FB_VMODE_NONINTERLACED},
{1152, 864, 12004, 200, 64, 32, 16, 80, 4, 0, FB_VMODE_NONINTERLACED},
{1280, 1024, 9090, 200, 48, 26, 1, 184, 3, 0, FB_VMODE_NONINTERLACED},
};
/************************************************************************
* Get Parameters for the video mode:
*/
/*********************************************************************
* returns the length to the next seperator
*/
static int
video_get_param_len (char *start, char sep)
{
int i = 0;
while ((*start != 0) && (*start != sep)) {
start++;
i++;
}
return i;
}
static int
video_search_param (char *start, char *param)
{
int len, totallen, i;
char *p = start;
len = strlen (param);
totallen = len + strlen (start);
for (i = 0; i < totallen; i++) {
if (strncmp (p++, param, len) == 0)
return (i);
}
return -1;
}
/***************************************************************
* Get parameter via the environment as it is done for the
* linux kernel i.e:
* video=ctfb:x:800,xv:1280,y:600,yv:1024,depth:16,mode:0,pclk:25000,
* le:56,ri:48,up:26,lo:5,hs:152,vs:2,sync:0,vmode:0,accel:0
*
* penv is a pointer to the environment, containing the string, or the name of
* another environment variable. It could even be the term "bootargs"
*/
#define GET_OPTION(name,var) \
if(strncmp(p,name,strlen(name))==0) { \
val_s=p+strlen(name); \
var=simple_strtoul(val_s, NULL, 10); \
}
int video_get_params (struct ctfb_res_modes *pPar, char *penv)
{
char *p, *s, *val_s;
int i = 0;
int bpp;
int mode;
/* first search for the environment containing the real param string */
s = penv;
if ((p = getenv (s)) != NULL)
s = p;
/*
* in case of the bootargs line, we have to start
* after "video=ctfb:"
*/
i = video_search_param (s, "video=ctfb:");
if (i >= 0) {
s += i;
s += strlen ("video=ctfb:");
}
/* search for mode as a default value */
p = s;
mode = 0; /* default */
while ((i = video_get_param_len (p, ',')) != 0) {
GET_OPTION ("mode:", mode)
p += i;
if (*p != 0)
p++; /* skip ',' */
}
if (mode >= RES_MODES_COUNT)
mode = 0;
*pPar = res_mode_init[mode]; /* copy default values */
bpp = 24 - ((mode % 3) * 8);
p = s; /* restart */
while ((i = video_get_param_len (p, ',')) != 0) {
GET_OPTION ("x:", pPar->xres)
GET_OPTION ("y:", pPar->yres)
GET_OPTION ("le:", pPar->left_margin)
GET_OPTION ("ri:", pPar->right_margin)
GET_OPTION ("up:", pPar->upper_margin)
GET_OPTION ("lo:", pPar->lower_margin)
GET_OPTION ("hs:", pPar->hsync_len)
GET_OPTION ("vs:", pPar->vsync_len)
GET_OPTION ("sync:", pPar->sync)
GET_OPTION ("vmode:", pPar->vmode)
GET_OPTION ("pclk:", pPar->pixclock)
GET_OPTION ("depth:", bpp)
p += i;
if (*p != 0)
p++; /* skip ',' */
}
return bpp;
}
/*
* Parse the 'video-mode' environment variable
*
* Example: "video-mode=fslfb:1280x1024-32@60,monitor=dvi". See
* doc/README.video for more information on how to set the variable.
*
* @xres: returned value of X-resolution
* @yres: returned value of Y-resolution
* @depth: returned value of color depth
* @freq: returned value of monitor frequency
* @options: pointer to any remaining options, or NULL
*
* Returns 1 if valid values were found, 0 otherwise
*/
int video_get_video_mode(unsigned int *xres, unsigned int *yres,
unsigned int *depth, unsigned int *freq, const char **options)
{
char *p = getenv("video-mode");
if (!p)
return 0;
/* Skip over the driver name, which we don't care about. */
p = strchr(p, ':');
if (!p)
return 0;
/* Get the X-resolution*/
while (*p && !isdigit(*p))
p++;
*xres = simple_strtoul(p, &p, 10);
if (!*xres)
return 0;
/* Get the Y-resolution */
while (*p && !isdigit(*p))
p++;
*yres = simple_strtoul(p, &p, 10);
if (!*yres)
return 0;
/* Get the depth */
while (*p && !isdigit(*p))
p++;
*depth = simple_strtoul(p, &p, 10);
if (!*depth)
return 0;
/* Get the frequency */
while (*p && !isdigit(*p))
p++;
*freq = simple_strtoul(p, &p, 10);
if (!*freq)
return 0;
/* Find the extra options, if any */
p = strchr(p, ',');
*options = p ? p + 1 : NULL;
return 1;
}
|
1001-study-uboot
|
drivers/video/videomodes.c
|
C
|
gpl3
| 8,572
|
/*
* ATI Radeon Video card Framebuffer driver.
*
* Copyright 2007 Freescale Semiconductor, Inc.
* Zhang Wei <wei.zhang@freescale.com>
* Jason Jin <jason.jin@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Some codes of this file is partly ported from Linux kernel
* ATI video framebuffer driver.
*
* Now the driver is tested on below ATI chips:
* 9200
* X300
* X700
*
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <video_fb.h>
#include "videomodes.h"
#include <radeon.h>
#include "ati_ids.h"
#include "ati_radeon_fb.h"
#undef DEBUG
#ifdef DEBUG
#define DPRINT(x...) printf(x)
#else
#define DPRINT(x...) do{}while(0)
#endif
#ifndef min_t
#define min_t(type,x,y) \
({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
#endif
#define MAX_MAPPED_VRAM (2048*2048*4)
#define MIN_MAPPED_VRAM (1024*768*1)
#define RADEON_BUFFER_ALIGN 0x00000fff
#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \
& ~RADEON_BUFFER_ALIGN) - 1)
#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \
((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \
(((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16))
#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \
(((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16))
#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \
((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16))
#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \
((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16))
/*#define PCI_VENDOR_ID_ATI*/
#define PCI_CHIP_RV280_5960 0x5960
#define PCI_CHIP_RV280_5961 0x5961
#define PCI_CHIP_RV280_5962 0x5962
#define PCI_CHIP_RV280_5964 0x5964
#define PCI_CHIP_RV280_5C63 0x5C63
#define PCI_CHIP_RV370_5B60 0x5B60
#define PCI_CHIP_RV380_5657 0x5657
#define PCI_CHIP_R420_554d 0x554d
static struct pci_device_id ati_radeon_pci_ids[] = {
{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960},
{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961},
{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962},
{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964},
{PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63},
{PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60},
{PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657},
{PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d},
{0, 0}
};
static u16 ati_radeon_id_family_table[][2] = {
{PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280},
{PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280},
{PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280},
{PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280},
{PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280},
{PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380},
{PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380},
{PCI_CHIP_R420_554d, CHIP_FAMILY_R420},
{0, 0}
};
u16 get_radeon_id_family(u16 device)
{
int i;
for (i=0; ati_radeon_id_family_table[0][i]; i+=2)
if (ati_radeon_id_family_table[0][i] == device)
return ati_radeon_id_family_table[0][i + 1];
return 0;
}
struct radeonfb_info *rinfo;
static void radeon_identify_vram(struct radeonfb_info *rinfo)
{
u32 tmp;
/* framebuffer size */
if ((rinfo->family == CHIP_FAMILY_RS100) ||
(rinfo->family == CHIP_FAMILY_RS200) ||
(rinfo->family == CHIP_FAMILY_RS300)) {
u32 tom = INREG(NB_TOM);
tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
radeon_fifo_wait(6);
OUTREG(MC_FB_LOCATION, tom);
OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
/* This is supposed to fix the crtc2 noise problem. */
OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
if ((rinfo->family == CHIP_FAMILY_RS100) ||
(rinfo->family == CHIP_FAMILY_RS200)) {
/* This is to workaround the asic bug for RMX, some versions
of BIOS dosen't have this register initialized correctly.
*/
OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
~CRTC_H_CUTOFF_ACTIVE_EN);
}
} else {
tmp = INREG(CONFIG_MEMSIZE);
}
/* mem size is bits [28:0], mask off the rest */
rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
/*
* Hack to get around some busted production M6's
* reporting no ram
*/
if (rinfo->video_ram == 0) {
switch (rinfo->pdev.device) {
case PCI_CHIP_RADEON_LY:
case PCI_CHIP_RADEON_LZ:
rinfo->video_ram = 8192 * 1024;
break;
default:
break;
}
}
/*
* Now try to identify VRAM type
*/
if ((rinfo->family >= CHIP_FAMILY_R300) ||
(INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
rinfo->vram_ddr = 1;
else
rinfo->vram_ddr = 0;
tmp = INREG(MEM_CNTL);
if (IS_R300_VARIANT(rinfo)) {
tmp &= R300_MEM_NUM_CHANNELS_MASK;
switch (tmp) {
case 0: rinfo->vram_width = 64; break;
case 1: rinfo->vram_width = 128; break;
case 2: rinfo->vram_width = 256; break;
default: rinfo->vram_width = 128; break;
}
} else if ((rinfo->family == CHIP_FAMILY_RV100) ||
(rinfo->family == CHIP_FAMILY_RS100) ||
(rinfo->family == CHIP_FAMILY_RS200)){
if (tmp & RV100_MEM_HALF_MODE)
rinfo->vram_width = 32;
else
rinfo->vram_width = 64;
} else {
if (tmp & MEM_NUM_CHANNELS_MASK)
rinfo->vram_width = 128;
else
rinfo->vram_width = 64;
}
/* This may not be correct, as some cards can have half of channel disabled
* ToDo: identify these cases
*/
DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n",
rinfo->video_ram / 1024,
rinfo->vram_ddr ? "DDR" : "SDRAM",
rinfo->vram_width);
}
static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
{
int i;
radeon_fifo_wait(20);
#if 0
/* Workaround from XFree */
if (rinfo->is_mobility) {
/* A temporal workaround for the occational blanking on certain laptop
* panels. This appears to related to the PLL divider registers
* (fail to lock?). It occurs even when all dividers are the same
* with their old settings. In this case we really don't need to
* fiddle with PLL registers. By doing this we can avoid the blanking
* problem with some panels.
*/
if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
(mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
(PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
/* We still have to force a switch to selected PPLL div thanks to
* an XFree86 driver bug which will switch it away in some cases
* even when using UseFDev */
OUTREGP(CLOCK_CNTL_INDEX,
mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
~PPLL_DIV_SEL_MASK);
radeon_pll_errata_after_index(rinfo);
radeon_pll_errata_after_data(rinfo);
return;
}
}
#endif
if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return;
/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
/* Reset PPLL & enable atomic update */
OUTPLLP(PPLL_CNTL,
PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
/* Switch to selected PPLL divider */
OUTREGP(CLOCK_CNTL_INDEX,
mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
~PPLL_DIV_SEL_MASK);
/* Set PPLL ref. div */
if (rinfo->family == CHIP_FAMILY_R300 ||
rinfo->family == CHIP_FAMILY_RS300 ||
rinfo->family == CHIP_FAMILY_R350 ||
rinfo->family == CHIP_FAMILY_RV350) {
if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
/* When restoring console mode, use saved PPLL_REF_DIV
* setting.
*/
OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
} else {
/* R300 uses ref_div_acc field as real ref divider */
OUTPLLP(PPLL_REF_DIV,
(mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
~R300_PPLL_REF_DIV_ACC_MASK);
}
} else
OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
/* Set PPLL divider 3 & post divider*/
OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
/* Write update */
while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
;
OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
/* Wait read update complete */
/* FIXME: Certain revisions of R300 can't recover here. Not sure of
the cause yet, but this workaround will mask the problem for now.
Other chips usually will pass at the very first test, so the
workaround shouldn't have any effect on them. */
for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
;
OUTPLL(HTOTAL_CNTL, 0);
/* Clear reset & atomic update */
OUTPLLP(PPLL_CNTL, 0,
~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
/* We may want some locking ... oh well */
udelay(5000);
/* Switch back VCLK source to PPLL */
OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
}
typedef struct {
u16 reg;
u32 val;
} reg_val;
#if 0 /* unused ? -> scheduled for removal */
/* these common regs are cleared before mode setting so they do not
* interfere with anything
*/
static reg_val common_regs[] = {
{ OVR_CLR, 0 },
{ OVR_WID_LEFT_RIGHT, 0 },
{ OVR_WID_TOP_BOTTOM, 0 },
{ OV0_SCALE_CNTL, 0 },
{ SUBPIC_CNTL, 0 },
{ VIPH_CONTROL, 0 },
{ I2C_CNTL_1, 0 },
{ GEN_INT_CNTL, 0 },
{ CAP0_TRIG_CNTL, 0 },
{ CAP1_TRIG_CNTL, 0 },
};
#endif /* 0 */
void radeon_setmode(void)
{
struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
mode->crtc_gen_cntl = 0x03000200;
mode->crtc_ext_cntl = 0x00008048;
mode->dac_cntl = 0xff002100;
mode->crtc_h_total_disp = 0x4f0063;
mode->crtc_h_sync_strt_wid = 0x8c02a2;
mode->crtc_v_total_disp = 0x01df020c;
mode->crtc_v_sync_strt_wid = 0x8201ea;
mode->crtc_pitch = 0x00500050;
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
OUTREG(CRTC_OFFSET, 0);
OUTREG(CRTC_OFFSET_CNTL, 0);
OUTREG(CRTC_PITCH, mode->crtc_pitch);
mode->clk_cntl_index = 0x300;
mode->ppll_ref_div = 0xc;
mode->ppll_div_3 = 0x00030059;
radeon_write_pll_regs(rinfo, mode);
}
static void set_pal(void)
{
int idx, val = 0;
for (idx = 0; idx < 256; idx++) {
OUTREG8(PALETTE_INDEX, idx);
OUTREG(PALETTE_DATA, val);
val += 0x00010101;
}
}
void radeon_setmode_9200(int vesa_idx, int bpp)
{
struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN;
mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN;
mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN;
switch (bpp) {
case 24:
mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */
#if defined(__BIG_ENDIAN)
mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
#endif
break;
case 16:
mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */
#if defined(__BIG_ENDIAN)
mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
#endif
break;
default:
mode->crtc_gen_cntl |= 0x2 << 8; /* palette */
mode->surface_cntl = 0x00000000;
break;
}
switch (vesa_idx) {
case RES_MODE_1280x1024:
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280);
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024);
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3);
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18);
mode->ppll_div_3 = 0x00010078;
#else /* default @ 60 Hz */
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14);
mode->ppll_div_3 = 0x00010060;
#endif
/*
* for this mode pitch expands to the same value for 32, 16 and 8 bpp,
* so we set it here once only.
*/
mode->crtc_pitch = RADEON_CRT_PITCH(1280,32);
switch (bpp) {
case 24:
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32);
break;
case 16:
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16);
break;
default: /* 8 bpp */
mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8);
break;
}
break;
case RES_MODE_1024x768:
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024);
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12);
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768);
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3);
mode->ppll_div_3 = 0x0002008c;
#else /* @ 60 Hz */
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024);
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL;
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768);
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL;
mode->ppll_div_3 = 0x00020074;
#endif
/* also same pitch value for 32, 16 and 8 bpp */
mode->crtc_pitch = RADEON_CRT_PITCH(1024,32);
switch (bpp) {
case 24:
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32);
break;
case 16:
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16);
break;
default: /* 8 bpp */
mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8);
break;
}
break;
case RES_MODE_800x600:
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800);
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10);
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600);
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3);
mode->ppll_div_3 = 0x000300b0;
#else /* @ 60 Hz */
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16);
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600);
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4);
mode->ppll_div_3 = 0x0003008e;
#endif
switch (bpp) {
case 24:
mode->crtc_pitch = RADEON_CRT_PITCH(832,32);
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32);
break;
case 16:
mode->crtc_pitch = RADEON_CRT_PITCH(896,16);
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16);
break;
default: /* 8 bpp */
mode->crtc_pitch = RADEON_CRT_PITCH(1024,8);
mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8);
break;
}
break;
default: /* RES_MODE_640x480 */
#if defined(CONFIG_RADEON_VREFRESH_75HZ)
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640);
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL;
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480);
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL;
mode->ppll_div_3 = 0x00030070;
#else /* @ 60 Hz */
mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640);
mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL;
mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480);
mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL;
mode->ppll_div_3 = 0x00030059;
#endif
/* also same pitch value for 32, 16 and 8 bpp */
mode->crtc_pitch = RADEON_CRT_PITCH(640,32);
switch (bpp) {
case 24:
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32);
break;
case 16:
mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16);
mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16);
break;
default: /* 8 bpp */
mode->crtc_offset_cntl = 0x00000000;
break;
}
break;
}
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
OUTREG(CRTC_OFFSET, 0);
OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl);
OUTREG(CRTC_PITCH, mode->crtc_pitch);
OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
mode->clk_cntl_index = 0x300;
mode->ppll_ref_div = 0xc;
radeon_write_pll_regs(rinfo, mode);
OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
OUTREG(SURFACE0_INFO, mode->surf_info[0]);
OUTREG(SURFACE0_LOWER_BOUND, 0);
OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]);
OUTREG(SURFACE_CNTL, mode->surface_cntl);
if (bpp > 8)
set_pal();
free(mode);
}
#include "../bios_emulator/include/biosemu.h"
extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
int radeon_probe(struct radeonfb_info *rinfo)
{
pci_dev_t pdev;
u16 did;
pdev = pci_find_devices(ati_radeon_pci_ids, 0);
if (pdev != -1) {
pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n",
PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff,
(pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
strcpy(rinfo->name, "ATI Radeon");
rinfo->pdev.vendor = PCI_VENDOR_ID_ATI;
rinfo->pdev.device = did;
rinfo->family = get_radeon_id_family(rinfo->pdev.device);
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
&rinfo->fb_base_bus);
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2,
&rinfo->mmio_base_bus);
rinfo->fb_base_bus &= 0xfffff000;
rinfo->mmio_base_bus &= ~0x04;
rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus,
PCI_REGION_MEM, 0, MAP_NOCACHE);
DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n",
rinfo->mmio_base, rinfo->mmio_base_bus);
rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base);
/* PostBIOS with x86 emulater */
if (!BootVideoCardBIOS(pdev, NULL, 0))
return -1;
/*
* Check for errata
* (These will be added in the future for the chipfamily
* R300, RV200, RS200, RV100, RS100.)
*/
/* Get VRAM size and type */
radeon_identify_vram(rinfo);
rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM,
rinfo->video_ram);
rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus,
PCI_REGION_MEM, 0, MAP_NOCACHE);
DPRINT("Radeon: framebuffer base address 0x%08x, "
"bus address 0x%08x\n"
"MMIO base address 0x%08x, bus address 0x%08x, "
"framebuffer local base 0x%08x.\n ",
(u32)rinfo->fb_base, rinfo->fb_base_bus,
(u32)rinfo->mmio_base, rinfo->mmio_base_bus,
rinfo->fb_local_base);
return 0;
}
return -1;
}
/*
* The Graphic Device
*/
GraphicDevice ctfb;
#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
void *video_hw_init(void)
{
GraphicDevice *pGD = (GraphicDevice *) & ctfb;
u32 *vm;
char *penv;
unsigned long t1, hsynch, vsynch;
int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
struct ctfb_res_modes *res_mode;
struct ctfb_res_modes var_mode;
rinfo = malloc(sizeof(struct radeonfb_info));
printf("Video: ");
if(radeon_probe(rinfo)) {
printf("No radeon video card found!\n");
return NULL;
}
tmp = 0;
videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
/* get video mode via environment */
if ((penv = getenv ("videomode")) != NULL) {
/* deceide if it is a string */
if (penv[0] <= '9') {
videomode = (int) simple_strtoul (penv, NULL, 16);
tmp = 1;
}
} else {
tmp = 1;
}
if (tmp) {
/* parameter are vesa modes */
/* search params */
for (i = 0; i < VESA_MODES_COUNT; i++) {
if (vesa_modes[i].vesanr == videomode)
break;
}
if (i == VESA_MODES_COUNT) {
printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE);
i = 0;
}
res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
bits_per_pixel = vesa_modes[i].bits_per_pixel;
vesa_idx = vesa_modes[i].resindex;
} else {
res_mode = (struct ctfb_res_modes *) &var_mode;
bits_per_pixel = video_get_params (res_mode, penv);
}
/* calculate hsynch and vsynch freq (info only) */
t1 = (res_mode->left_margin + res_mode->xres +
res_mode->right_margin + res_mode->hsync_len) / 8;
t1 *= 8;
t1 *= res_mode->pixclock;
t1 /= 1000;
hsynch = 1000000000L / t1;
t1 *= (res_mode->upper_margin + res_mode->yres +
res_mode->lower_margin + res_mode->vsync_len);
t1 /= 1000;
vsynch = 1000000000L / t1;
/* fill in Graphic device struct */
sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
res_mode->yres, bits_per_pixel, (hsynch / 1000),
(vsynch / 1000));
printf ("%s\n", pGD->modeIdent);
pGD->winSizeX = res_mode->xres;
pGD->winSizeY = res_mode->yres;
pGD->plnSizeX = res_mode->xres;
pGD->plnSizeY = res_mode->yres;
switch (bits_per_pixel) {
case 24:
pGD->gdfBytesPP = 4;
pGD->gdfIndex = GDF_32BIT_X888RGB;
if (res_mode->xres == 800) {
pGD->winSizeX = 832;
pGD->plnSizeX = 832;
}
break;
case 16:
pGD->gdfBytesPP = 2;
pGD->gdfIndex = GDF_16BIT_565RGB;
if (res_mode->xres == 800) {
pGD->winSizeX = 896;
pGD->plnSizeX = 896;
}
break;
default:
if (res_mode->xres == 800) {
pGD->winSizeX = 1024;
pGD->plnSizeX = 1024;
}
pGD->gdfBytesPP = 1;
pGD->gdfIndex = GDF__8BIT_INDEX;
break;
}
pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
pGD->pciBase = (unsigned int)rinfo->fb_base;
pGD->frameAdrs = (unsigned int)rinfo->fb_base;
pGD->memSize = 64 * 1024 * 1024;
/* Cursor Start Address */
pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) +
(unsigned int)rinfo->fb_base;
if ((pGD->dprBase & 0x0fff) != 0) {
/* allign it */
pGD->dprBase &= 0xfffff000;
pGD->dprBase += 0x00001000;
}
DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
PATTERN_ADR);
pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */
pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */
/* set up Hardware */
/* Clear video memory (only visible screen area) */
i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
vm = (unsigned int *) pGD->pciBase;
while (i--)
*vm++ = 0;
/*SetDrawingEngine (bits_per_pixel);*/
if (rinfo->family == CHIP_FAMILY_RV280)
radeon_setmode_9200(vesa_idx, bits_per_pixel);
else
radeon_setmode();
return ((void *) pGD);
}
void video_set_lut (unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
)
{
OUTREG(PALETTE_INDEX, index);
OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b);
}
|
1001-study-uboot
|
drivers/video/ati_radeon_fb.c
|
C
|
gpl3
| 24,475
|
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* Author: Priyanka Jain <Priyanka.Jain@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file provides Date & Time support (no alarms) for PT7C4338 chip.
*
* This file is based on drivers/rtc/ds1337.c
*
* PT7C4338 chip is manufactured by Pericom Technology Inc.
* It is a serial real-time clock which provides
* 1)Low-power clock/calendar.
* 2)Programmable square-wave output.
* It has 56 bytes of nonvolatile RAM.
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
/* RTC register addresses */
#define RTC_SEC_REG_ADDR 0x0
#define RTC_MIN_REG_ADDR 0x1
#define RTC_HR_REG_ADDR 0x2
#define RTC_DAY_REG_ADDR 0x3
#define RTC_DATE_REG_ADDR 0x4
#define RTC_MON_REG_ADDR 0x5
#define RTC_YR_REG_ADDR 0x6
#define RTC_CTL_STAT_REG_ADDR 0x7
/* RTC second register address bit */
#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
/* RTC control and status register bits */
#define RTC_CTL_STAT_BIT_RS0 0x1 /* Rate select 0 */
#define RTC_CTL_STAT_BIT_RS1 0x2 /* Rate select 1 */
#define RTC_CTL_STAT_BIT_SQWE 0x10 /* Square Wave Enable */
#define RTC_CTL_STAT_BIT_OSF 0x20 /* Oscillator Stop Flag */
#define RTC_CTL_STAT_BIT_OUT 0x80 /* Output Level Control */
/* RTC reset value */
#define RTC_PT7C4338_RESET_VAL \
(RTC_CTL_STAT_BIT_RS0 | RTC_CTL_STAT_BIT_RS1 | RTC_CTL_STAT_BIT_OUT)
/****** Helper functions ****************************************/
static u8 rtc_read(u8 reg)
{
return i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, reg);
}
static void rtc_write(u8 reg, u8 val)
{
i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
/****************************************************************/
/* Get the current time from the RTC */
int rtc_get(struct rtc_time *tmp)
{
int ret = 0;
u8 sec, min, hour, mday, wday, mon, year, ctl_stat;
ctl_stat = rtc_read(RTC_CTL_STAT_REG_ADDR);
sec = rtc_read(RTC_SEC_REG_ADDR);
min = rtc_read(RTC_MIN_REG_ADDR);
hour = rtc_read(RTC_HR_REG_ADDR);
wday = rtc_read(RTC_DAY_REG_ADDR);
mday = rtc_read(RTC_DATE_REG_ADDR);
mon = rtc_read(RTC_MON_REG_ADDR);
year = rtc_read(RTC_YR_REG_ADDR);
debug("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x control_status: %02x\n",
year, mon, mday, wday, hour, min, sec, ctl_stat);
if (ctl_stat & RTC_CTL_STAT_BIT_OSF) {
printf("### Warning: RTC oscillator has stopped\n");
/* clear the OSF flag */
rtc_write(RTC_CTL_STAT_REG_ADDR,
rtc_read(RTC_CTL_STAT_REG_ADDR)\
& ~RTC_CTL_STAT_BIT_OSF);
ret = -1;
}
tmp->tm_sec = bcd2bin(sec & 0x7F);
tmp->tm_min = bcd2bin(min & 0x7F);
tmp->tm_hour = bcd2bin(hour & 0x3F);
tmp->tm_mday = bcd2bin(mday & 0x3F);
tmp->tm_mon = bcd2bin(mon & 0x1F);
tmp->tm_year = bcd2bin(year) + 2000;
tmp->tm_wday = bcd2bin((wday - 1) & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return ret;
}
/* Set the RTC */
int rtc_set(struct rtc_time *tmp)
{
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write(RTC_YR_REG_ADDR, bin2bcd(tmp->tm_year % 100));
rtc_write(RTC_MON_REG_ADDR, bin2bcd(tmp->tm_mon));
rtc_write(RTC_DAY_REG_ADDR, bin2bcd(tmp->tm_wday + 1));
rtc_write(RTC_DATE_REG_ADDR, bin2bcd(tmp->tm_mday));
rtc_write(RTC_HR_REG_ADDR, bin2bcd(tmp->tm_hour));
rtc_write(RTC_MIN_REG_ADDR, bin2bcd(tmp->tm_min));
rtc_write(RTC_SEC_REG_ADDR, bin2bcd(tmp->tm_sec));
return 0;
}
/* Reset the RTC */
void rtc_reset(void)
{
rtc_write(RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
rtc_write(RTC_CTL_STAT_REG_ADDR, RTC_PT7C4338_RESET_VAL);
}
|
1001-study-uboot
|
drivers/rtc/pt7c4338.c
|
C
|
gpl3
| 4,651
|
/*
* (C) Copyright 2010
* Reinhard Meyer, reinhard.meyer@emk-elektronik.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the internal Real-time Timer
* of AT91SAM9260 and compatibles.
* Compatible with the LinuX rtc driver workaround:
* The RTT cannot be written to, but only reset.
* The actual time is the sum of RTT and one of
* the four GPBR registers.
*
* The at91sam9260 has 4 GPBR (0-3).
* For their typical use see at91_gpbr.h !
*
* make sure u-boot and kernel use the same GPBR !
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_rtt.h>
#include <asm/arch/at91_gpbr.h>
#if defined(CONFIG_CMD_DATE)
int rtc_get (struct rtc_time *tmp)
{
at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
ulong tim;
ulong tim2;
ulong off;
do {
tim = readl(&rtt->vr);
tim2 = readl(&rtt->vr);
} while (tim!=tim2);
off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
/* off==0 means time is invalid, but we ignore that */
to_tm (tim+off, tmp);
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
ulong tim;
tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
/* clear alarm, set prescaler to 32768, clear counter */
writel(32768+AT91_RTT_RTTRST, &rtt->mr);
writel(~0, &rtt->ar);
writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
/* wait for counter clear to happen, takes less than a 1/32768th second */
while (readl(&rtt->vr) != 0)
;
return 0;
}
void rtc_reset (void)
{
at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT;
at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR;
/* clear alarm, set prescaler to 32768, clear counter */
writel(32768+AT91_RTT_RTTRST, &rtt->mr);
writel(~0, &rtt->ar);
writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]);
/* wait for counter clear to happen, takes less than a 1/32768th second */
while (readl(&rtt->vr) != 0)
;
}
#endif
|
1001-study-uboot
|
drivers/rtc/at91sam9_rtt.c
|
C
|
gpl3
| 2,897
|
/*
* (C) Copyright 2004
* DAVE Srl
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* S3C44B0 CPU specific code
*/
#include <common.h>
#include <command.h>
#include <asm/hardware.h>
#include <rtc.h>
int rtc_get (struct rtc_time* tm)
{
RTCCON |= 1;
tm->tm_year = bcd2bin(BCDYEAR);
tm->tm_mon = bcd2bin(BCDMON);
tm->tm_wday = bcd2bin(BCDDATE);
tm->tm_mday = bcd2bin(BCDDAY);
tm->tm_hour = bcd2bin(BCDHOUR);
tm->tm_min = bcd2bin(BCDMIN);
tm->tm_sec = bcd2bin(BCDSEC);
if (tm->tm_sec==0) {
/* we have to re-read the rtc data because of the "one second deviation" problem */
/* see RTC datasheet for more info about it */
tm->tm_year = bcd2bin(BCDYEAR);
tm->tm_mon = bcd2bin(BCDMON);
tm->tm_mday = bcd2bin(BCDDAY);
tm->tm_wday = bcd2bin(BCDDATE);
tm->tm_hour = bcd2bin(BCDHOUR);
tm->tm_min = bcd2bin(BCDMIN);
tm->tm_sec = bcd2bin(BCDSEC);
}
RTCCON &= ~1;
if(tm->tm_year >= 70)
tm->tm_year += 1900;
else
tm->tm_year += 2000;
return 0;
}
int rtc_set (struct rtc_time* tm)
{
if(tm->tm_year < 2000)
tm->tm_year -= 1900;
else
tm->tm_year -= 2000;
RTCCON |= 1;
BCDYEAR = bin2bcd(tm->tm_year);
BCDMON = bin2bcd(tm->tm_mon);
BCDDAY = bin2bcd(tm->tm_mday);
BCDDATE = bin2bcd(tm->tm_wday);
BCDHOUR = bin2bcd(tm->tm_hour);
BCDMIN = bin2bcd(tm->tm_min);
BCDSEC = bin2bcd(tm->tm_sec);
RTCCON &= 1;
return 0;
}
void rtc_reset (void)
{
RTCCON |= 1;
BCDYEAR = 0;
BCDMON = 0;
BCDDAY = 0;
BCDDATE = 0;
BCDHOUR = 0;
BCDMIN = 0;
BCDSEC = 0;
RTCCON &= 1;
}
|
1001-study-uboot
|
drivers/rtc/s3c44b0_rtc.c
|
C
|
gpl3
| 2,358
|
/*
* (C) Copyright 2011 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#if defined(CONFIG_CMD_DATE)
int rtc_get(struct rtc_time *tmp)
{
struct davinci_rtc *rtc = davinci_rtc_base;
unsigned long sec, min, hour, mday, wday, mon_cent, year;
unsigned long status;
status = readl(&rtc->status);
if ((status & RTC_STATE_RUN) != RTC_STATE_RUN) {
printf("RTC doesn't run\n");
return -1;
}
if ((status & RTC_STATE_BUSY) == RTC_STATE_BUSY)
udelay(20);
sec = readl(&rtc->second);
min = readl(&rtc->minutes);
hour = readl(&rtc->hours);
mday = readl(&rtc->day);
wday = readl(&rtc->dotw);
mon_cent = readl(&rtc->month);
year = readl(&rtc->year);
debug("Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
"hr: %02lx min: %02lx sec: %02lx\n",
year, mon_cent, mday, wday,
hour, min, sec);
tmp->tm_sec = bcd2bin(sec & 0x7F);
tmp->tm_min = bcd2bin(min & 0x7F);
tmp->tm_hour = bcd2bin(hour & 0x3F);
tmp->tm_mday = bcd2bin(mday & 0x3F);
tmp->tm_mon = bcd2bin(mon_cent & 0x1F);
tmp->tm_year = bcd2bin(year) + 2000;
tmp->tm_wday = bcd2bin(wday & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
int rtc_set(struct rtc_time *tmp)
{
struct davinci_rtc *rtc = davinci_rtc_base;
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
writel(bin2bcd(tmp->tm_year % 100), &rtc->year);
writel(bin2bcd(tmp->tm_mon), &rtc->month);
writel(bin2bcd(tmp->tm_wday), &rtc->dotw);
writel(bin2bcd(tmp->tm_mday), &rtc->day);
writel(bin2bcd(tmp->tm_hour), &rtc->hours);
writel(bin2bcd(tmp->tm_min), &rtc->minutes);
writel(bin2bcd(tmp->tm_sec), &rtc->second);
return 0;
}
void rtc_reset(void)
{
struct davinci_rtc *rtc = davinci_rtc_base;
/* run RTC counter */
writel(0x01, &rtc->ctrl);
}
#endif
|
1001-study-uboot
|
drivers/rtc/davinci.c
|
C
|
gpl3
| 2,940
|
/*
* (C) Copyright 2008
* Tor Krill, Excito Elektronik i Skåne , tor@excito.com
*
* Modelled after the ds1337 driver
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support (no alarms) for Intersil
* ISL1208 Real Time Clock (RTC).
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
/*---------------------------------------------------------------------*/
#ifdef DEBUG_RTC
#define DEBUGR(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGR(fmt,args...)
#endif
/*---------------------------------------------------------------------*/
/*
* RTC register addresses
*/
#define RTC_SEC_REG_ADDR 0x0
#define RTC_MIN_REG_ADDR 0x1
#define RTC_HR_REG_ADDR 0x2
#define RTC_DATE_REG_ADDR 0x3
#define RTC_MON_REG_ADDR 0x4
#define RTC_YR_REG_ADDR 0x5
#define RTC_DAY_REG_ADDR 0x6
#define RTC_STAT_REG_ADDR 0x7
/*
* RTC control register bits
*/
/*
* RTC status register bits
*/
#define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */
#define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */
#define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */
#define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */
#define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */
#define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
/*
* Get the current time from the RTC
*/
int rtc_get (struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year, status;
status = rtc_read (RTC_STAT_REG_ADDR);
sec = rtc_read (RTC_SEC_REG_ADDR);
min = rtc_read (RTC_MIN_REG_ADDR);
hour = rtc_read (RTC_HR_REG_ADDR);
wday = rtc_read (RTC_DAY_REG_ADDR);
mday = rtc_read (RTC_DATE_REG_ADDR);
mon = rtc_read (RTC_MON_REG_ADDR);
year = rtc_read (RTC_YR_REG_ADDR);
DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x status: %02x\n",
year, mon, mday, wday, hour, min, sec, status);
if (status & RTC_STAT_BIT_RTCF) {
printf ("### Warning: RTC oscillator has stopped\n");
rtc_write(RTC_STAT_REG_ADDR,
rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF));
rel = -1;
}
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year)+2000;
tmp->tm_wday = bcd2bin (wday & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return rel;
}
/*
* Set the RTC
*/
int rtc_set (struct rtc_time *tmp)
{
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
/* enable write */
rtc_write(RTC_STAT_REG_ADDR,
rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC);
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
/* disable write */
rtc_write(RTC_STAT_REG_ADDR,
rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC);
return 0;
}
void rtc_reset (void)
{
}
/*
* Helper functions
*/
static uchar rtc_read (uchar reg)
{
return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
|
1001-study-uboot
|
drivers/rtc/isl1208.c
|
C
|
gpl3
| 4,457
|
/*
* rs5c372.c
*
* Device driver for Ricoh's Real Time Controller RS5C372A.
*
* Copyright (C) 2004 Gary Jennejohn garyj@denx.de
*
* Based in part in ds1307.c -
* (C) Copyright 2001, 2002, 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Keith Outwater, keith_outwater@mvis.com`
* Steven Scholz, steven.scholz@imc-berlin.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
/*
* Reads are always done starting with register 15, which requires some
* jumping-through-hoops to access the data correctly.
*
* Writes are always done starting with register 0.
*/
#define DEBUG 0
#if DEBUG
static unsigned int rtc_debug = DEBUG;
#else
#define rtc_debug 0 /* gcc will remove all the debug code for us */
#endif
#ifndef CONFIG_SYS_I2C_RTC_ADDR
#define CONFIG_SYS_I2C_RTC_ADDR 0x32
#endif
#define RS5C372_RAM_SIZE 0x10
#define RATE_32000HZ 0x80 /* Rate Select 32.000KHz */
#define RATE_32768HZ 0x00 /* Rate Select 32.768KHz */
#define STATUS_XPT 0x10 /* data invalid because voltage was 0 */
#define USE_24HOUR_MODE 0x20
#define TWELVE_HOUR_MODE(n) ((((n) >> 5) & 1) == 0)
#define HOURS_AP(n) (((n) >> 5) & 1)
#define HOURS_12(n) bcd2bin((n) & 0x1F)
#define HOURS_24(n) bcd2bin((n) & 0x3F)
static int setup_done = 0;
static int
rs5c372_readram(unsigned char *buf, int len)
{
int ret;
ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, len);
if (ret != 0) {
printf("%s: failed to read\n", __FUNCTION__);
return ret;
}
if (buf[0] & STATUS_XPT)
printf("### Warning: RTC lost power\n");
return ret;
}
static void
rs5c372_enable(void)
{
unsigned char buf[RS5C372_RAM_SIZE + 1];
int ret;
/* note that this returns reg. 15 in buf[1] */
ret = rs5c372_readram(&buf[1], RS5C372_RAM_SIZE);
if (ret != 0) {
printf("%s: failed\n", __FUNCTION__);
return;
}
buf[0] = 0;
/* we want to start writing at register 0 so we have to copy the */
/* register contents up one slot */
for (ret = 2; ret < 9; ret++)
buf[ret - 1] = buf[ret];
/* registers 0 to 6 (time values) are not touched */
buf[8] = RATE_32768HZ; /* reg. 7 */
buf[9] = 0; /* reg. 8 */
buf[10] = 0; /* reg. 9 */
buf[11] = 0; /* reg. 10 */
buf[12] = 0; /* reg. 11 */
buf[13] = 0; /* reg. 12 */
buf[14] = 0; /* reg. 13 */
buf[15] = 0; /* reg. 14 */
buf[16] = USE_24HOUR_MODE; /* reg. 15 */
ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1);
if (ret != 0) {
printf("%s: failed\n", __FUNCTION__);
return;
}
setup_done = 1;
return;
}
static void
rs5c372_convert_to_time(struct rtc_time *dt, unsigned char *buf)
{
/* buf[0] is register 15 */
dt->tm_sec = bcd2bin(buf[1]);
dt->tm_min = bcd2bin(buf[2]);
if (TWELVE_HOUR_MODE(buf[0])) {
dt->tm_hour = HOURS_12(buf[3]);
if (HOURS_AP(buf[3])) /* PM */
dt->tm_hour += 12;
} else /* 24-hour-mode */
dt->tm_hour = HOURS_24(buf[3]);
dt->tm_mday = bcd2bin(buf[5]);
dt->tm_mon = bcd2bin(buf[6]);
dt->tm_year = bcd2bin(buf[7]);
if (dt->tm_year >= 70)
dt->tm_year += 1900;
else
dt->tm_year += 2000;
/* 0 is Sunday */
dt->tm_wday = bcd2bin(buf[4] & 0x07);
dt->tm_yday = 0;
dt->tm_isdst= 0;
if(rtc_debug > 2) {
printf("rs5c372_convert_to_time: year = %d\n", dt->tm_year);
printf("rs5c372_convert_to_time: mon = %d\n", dt->tm_mon);
printf("rs5c372_convert_to_time: mday = %d\n", dt->tm_mday);
printf("rs5c372_convert_to_time: hour = %d\n", dt->tm_hour);
printf("rs5c372_convert_to_time: min = %d\n", dt->tm_min);
printf("rs5c372_convert_to_time: sec = %d\n", dt->tm_sec);
}
}
/*
* Get the current time from the RTC
*/
int
rtc_get (struct rtc_time *tmp)
{
unsigned char buf[RS5C372_RAM_SIZE];
int ret;
if (!setup_done)
rs5c372_enable();
if (!setup_done)
return -1;
memset(buf, 0, sizeof(buf));
/* note that this returns reg. 15 in buf[0] */
ret = rs5c372_readram(buf, RS5C372_RAM_SIZE);
if (ret != 0) {
printf("%s: failed\n", __FUNCTION__);
return -1;
}
rs5c372_convert_to_time(tmp, buf);
return 0;
}
/*
* Set the RTC
*/
int rtc_set (struct rtc_time *tmp)
{
unsigned char buf[8], reg15;
int ret;
if (!setup_done)
rs5c372_enable();
if (!setup_done)
return -1;
if(rtc_debug > 2) {
printf("rtc_set: tm_year = %d\n", tmp->tm_year);
printf("rtc_set: tm_mon = %d\n", tmp->tm_mon);
printf("rtc_set: tm_mday = %d\n", tmp->tm_mday);
printf("rtc_set: tm_hour = %d\n", tmp->tm_hour);
printf("rtc_set: tm_min = %d\n", tmp->tm_min);
printf("rtc_set: tm_sec = %d\n", tmp->tm_sec);
}
memset(buf, 0, sizeof(buf));
/* only read register 15 */
ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1);
if (ret == 0) {
/* need to save register 15 */
reg15 = buf[0];
buf[0] = 0; /* register address on RS5C372 */
buf[1] = bin2bcd(tmp->tm_sec);
buf[2] = bin2bcd(tmp->tm_min);
/* need to handle 12 hour mode */
if (TWELVE_HOUR_MODE(reg15)) {
if (tmp->tm_hour >= 12) { /* PM */
/* 12 PM is a special case */
if (tmp->tm_hour == 12)
buf[3] = bin2bcd(tmp->tm_hour);
else
buf[3] = bin2bcd(tmp->tm_hour - 12);
buf[3] |= 0x20;
}
} else {
buf[3] = bin2bcd(tmp->tm_hour);
}
buf[4] = bin2bcd(tmp->tm_wday);
buf[5] = bin2bcd(tmp->tm_mday);
buf[6] = bin2bcd(tmp->tm_mon);
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
buf[7] = bin2bcd(tmp->tm_year % 100);
ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8);
if (ret != 0) {
printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret);
return -1;
}
} else {
return -1;
}
return 0;
}
/*
* Reset the RTC. We set the date back to 1970-01-01.
*/
void
rtc_reset (void)
{
struct rtc_time tmp;
if (!setup_done)
rs5c372_enable();
if (!setup_done)
return;
tmp.tm_year = 1970;
tmp.tm_mon = 1;
/* Jan. 1, 1970 was a Thursday */
tmp.tm_wday= 4;
tmp.tm_mday= 1;
tmp.tm_hour = 0;
tmp.tm_min = 0;
tmp.tm_sec = 0;
rtc_set(&tmp);
printf ("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
return;
}
#endif
|
1001-study-uboot
|
drivers/rtc/rs5c372.c
|
C
|
gpl3
| 6,845
|
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for MAXIM MAX6900 RTC
*/
/* #define DEBUG */
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
#ifndef CONFIG_SYS_I2C_RTC_ADDR
#define CONFIG_SYS_I2C_RTC_ADDR 0x50
#endif
/* ------------------------------------------------------------------------- */
static uchar rtc_read (uchar reg)
{
return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
udelay(2500);
}
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
{
uchar sec, min, hour, mday, wday, mon, cent, year;
int retry = 1;
do {
sec = rtc_read (0x80);
min = rtc_read (0x82);
hour = rtc_read (0x84);
mday = rtc_read (0x86);
mon = rtc_read (0x88);
wday = rtc_read (0x8a);
year = rtc_read (0x8c);
cent = rtc_read (0x92);
/*
* Check for seconds rollover
*/
if ((sec != 59) || (rtc_read(0x80) == sec)){
retry = 0;
}
} while (retry);
debug ( "Get RTC year: %02x mon: %02x cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, cent, mday, wday,
hour, min, sec );
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year) + bcd2bin(cent) * 100;
tmp->tm_wday = bcd2bin (wday & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (0x9E, 0x00);
rtc_write (0x80, 0); /* Clear seconds to ensure no rollover */
rtc_write (0x92, bin2bcd(tmp->tm_year / 100));
rtc_write (0x8c, bin2bcd(tmp->tm_year % 100));
rtc_write (0x8a, bin2bcd(tmp->tm_wday));
rtc_write (0x88, bin2bcd(tmp->tm_mon));
rtc_write (0x86, bin2bcd(tmp->tm_mday));
rtc_write (0x84, bin2bcd(tmp->tm_hour));
rtc_write (0x82, bin2bcd(tmp->tm_min ));
rtc_write (0x80, bin2bcd(tmp->tm_sec ));
return 0;
}
void rtc_reset (void)
{
}
#endif
|
1001-study-uboot
|
drivers/rtc/max6900.c
|
C
|
gpl3
| 3,321
|
/*
* Driver for ST M41T94 SPI RTC
*
* Taken from the Linux kernel drivier:
* Copyright (C) 2008 Kim B. Heino
*
* Adaptation for U-Boot:
* Copyright (C) 2009
* Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <rtc.h>
#include <spi.h>
static struct spi_slave *slave;
#define M41T94_REG_SECONDS 0x01
#define M41T94_REG_MINUTES 0x02
#define M41T94_REG_HOURS 0x03
#define M41T94_REG_WDAY 0x04
#define M41T94_REG_DAY 0x05
#define M41T94_REG_MONTH 0x06
#define M41T94_REG_YEAR 0x07
#define M41T94_REG_HT 0x0c
#define M41T94_BIT_HALT 0x40
#define M41T94_BIT_STOP 0x80
#define M41T94_BIT_CB 0x40
#define M41T94_BIT_CEB 0x80
int rtc_set(struct rtc_time *tm)
{
u8 buf[8]; /* write cmd + 7 registers */
int ret;
if (!slave) {
slave = spi_setup_slave(CONFIG_M41T94_SPI_BUS,
CONFIG_M41T94_SPI_CS, 1000000,
SPI_MODE_3);
if (!slave)
return -1;
}
spi_claim_bus(slave);
buf[0] = 0x80 | M41T94_REG_SECONDS; /* write time + date */
buf[M41T94_REG_SECONDS] = bin2bcd(tm->tm_sec);
buf[M41T94_REG_MINUTES] = bin2bcd(tm->tm_min);
buf[M41T94_REG_HOURS] = bin2bcd(tm->tm_hour);
buf[M41T94_REG_WDAY] = bin2bcd(tm->tm_wday + 1);
buf[M41T94_REG_DAY] = bin2bcd(tm->tm_mday);
buf[M41T94_REG_MONTH] = bin2bcd(tm->tm_mon + 1);
buf[M41T94_REG_HOURS] |= M41T94_BIT_CEB;
if (tm->tm_year >= 100)
buf[M41T94_REG_HOURS] |= M41T94_BIT_CB;
buf[M41T94_REG_YEAR] = bin2bcd(tm->tm_year % 100);
ret = spi_xfer(slave, 64, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
spi_release_bus(slave);
return ret;
}
int rtc_get(struct rtc_time *tm)
{
u8 buf[2];
int ret, hour;
if (!slave) {
slave = spi_setup_slave(CONFIG_M41T94_SPI_BUS,
CONFIG_M41T94_SPI_CS, 1000000,
SPI_MODE_3);
if (!slave)
return -1;
}
spi_claim_bus(slave);
/* clear halt update bit */
ret = spi_w8r8(slave, M41T94_REG_HT);
if (ret < 0)
return ret;
if (ret & M41T94_BIT_HALT) {
buf[0] = 0x80 | M41T94_REG_HT;
buf[1] = ret & ~M41T94_BIT_HALT;
spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
}
/* clear stop bit */
ret = spi_w8r8(slave, M41T94_REG_SECONDS);
if (ret < 0)
return ret;
if (ret & M41T94_BIT_STOP) {
buf[0] = 0x80 | M41T94_REG_SECONDS;
buf[1] = ret & ~M41T94_BIT_STOP;
spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
}
tm->tm_sec = bcd2bin(spi_w8r8(slave, M41T94_REG_SECONDS));
tm->tm_min = bcd2bin(spi_w8r8(slave, M41T94_REG_MINUTES));
hour = spi_w8r8(slave, M41T94_REG_HOURS);
tm->tm_hour = bcd2bin(hour & 0x3f);
tm->tm_wday = bcd2bin(spi_w8r8(slave, M41T94_REG_WDAY)) - 1;
tm->tm_mday = bcd2bin(spi_w8r8(slave, M41T94_REG_DAY));
tm->tm_mon = bcd2bin(spi_w8r8(slave, M41T94_REG_MONTH)) - 1;
tm->tm_year = bcd2bin(spi_w8r8(slave, M41T94_REG_YEAR));
if ((hour & M41T94_BIT_CB) || !(hour & M41T94_BIT_CEB))
tm->tm_year += 100;
spi_release_bus(slave);
return 0;
}
void rtc_reset(void)
{
/*
* Could not be tested as the reset pin is not wired on
* the sbc35-ag20 board
*/
}
|
1001-study-uboot
|
drivers/rtc/m41t94.c
|
C
|
gpl3
| 3,215
|
/*
* (C) Copyright 2008
* Gururaja Hebbar gururajakr@sanyo.co.in
*
* reference linux-2.6.20.6/drivers/rtc/rtc-pl031.c
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
#ifndef CONFIG_SYS_RTC_PL031_BASE
#error CONFIG_SYS_RTC_PL031_BASE is not defined!
#endif
/*
* Register definitions
*/
#define RTC_DR 0x00 /* Data read register */
#define RTC_MR 0x04 /* Match register */
#define RTC_LR 0x08 /* Data load register */
#define RTC_CR 0x0c /* Control register */
#define RTC_IMSC 0x10 /* Interrupt mask and set register */
#define RTC_RIS 0x14 /* Raw interrupt status register */
#define RTC_MIS 0x18 /* Masked interrupt status register */
#define RTC_ICR 0x1c /* Interrupt clear register */
#define RTC_CR_START (1 << 0)
#define RTC_WRITE_REG(addr, val) \
(*(volatile unsigned int *)(CONFIG_SYS_RTC_PL031_BASE + (addr)) = (val))
#define RTC_READ_REG(addr) \
(*(volatile unsigned int *)(CONFIG_SYS_RTC_PL031_BASE + (addr)))
static int pl031_initted = 0;
/* Enable RTC Start in Control register*/
void rtc_init(void)
{
RTC_WRITE_REG(RTC_CR, RTC_CR_START);
pl031_initted = 1;
}
/*
* Reset the RTC. We set the date back to 1970-01-01.
*/
void rtc_reset(void)
{
RTC_WRITE_REG(RTC_LR, 0x00);
if(!pl031_initted)
rtc_init();
}
/*
* Set the RTC
*/
int rtc_set(struct rtc_time *tmp)
{
unsigned long tim;
if(!pl031_initted)
rtc_init();
if (tmp == NULL) {
puts("Error setting the date/time\n");
return -1;
}
/* Calculate number of seconds this incoming time represents */
tim = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
RTC_WRITE_REG(RTC_LR, tim);
return -1;
}
/*
* Get the current time from the RTC
*/
int rtc_get(struct rtc_time *tmp)
{
ulong tim;
if(!pl031_initted)
rtc_init();
if (tmp == NULL) {
puts("Error getting the date/time\n");
return -1;
}
tim = RTC_READ_REG(RTC_DR);
to_tm (tim, tmp);
debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
#endif
|
1001-study-uboot
|
drivers/rtc/pl031.c
|
C
|
gpl3
| 2,954
|
/*
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* based on a the Linux rtc-m41t80.c driver which is:
* Alexander Bigga <ab@mycable.de>, 2006 (c) mycable GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for STMicroelectronics M41T62
*/
/* #define DEBUG */
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
#define M41T62_REG_SSEC 0
#define M41T62_REG_SEC 1
#define M41T62_REG_MIN 2
#define M41T62_REG_HOUR 3
#define M41T62_REG_WDAY 4
#define M41T62_REG_DAY 5
#define M41T62_REG_MON 6
#define M41T62_REG_YEAR 7
#define M41T62_REG_ALARM_MON 0xa
#define M41T62_REG_ALARM_DAY 0xb
#define M41T62_REG_ALARM_HOUR 0xc
#define M41T62_REG_ALARM_MIN 0xd
#define M41T62_REG_ALARM_SEC 0xe
#define M41T62_REG_FLAGS 0xf
#define M41T62_DATETIME_REG_SIZE (M41T62_REG_YEAR + 1)
#define M41T62_ALARM_REG_SIZE \
(M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON)
#define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */
#define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */
#define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */
#define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
#define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */
#define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */
#define M41T62_FEATURE_HT (1 << 0)
#define M41T62_FEATURE_BL (1 << 1)
int rtc_get(struct rtc_time *tm)
{
u8 buf[M41T62_DATETIME_REG_SIZE];
i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
__FUNCTION__,
buf[0], buf[1], buf[2], buf[3],
buf[4], buf[5], buf[6], buf[7]);
tm->tm_sec = bcd2bin(buf[M41T62_REG_SEC] & 0x7f);
tm->tm_min = bcd2bin(buf[M41T62_REG_MIN] & 0x7f);
tm->tm_hour = bcd2bin(buf[M41T62_REG_HOUR] & 0x3f);
tm->tm_mday = bcd2bin(buf[M41T62_REG_DAY] & 0x3f);
tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07;
tm->tm_mon = bcd2bin(buf[M41T62_REG_MON] & 0x1f);
/* assume 20YY not 19YY, and ignore the Century Bit */
/* U-Boot needs to add 1900 here */
tm->tm_year = bcd2bin(buf[M41T62_REG_YEAR]) + 100 + 1900;
debug("%s: tm is secs=%d, mins=%d, hours=%d, "
"mday=%d, mon=%d, year=%d, wday=%d\n",
__FUNCTION__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
return 0;
}
int rtc_set(struct rtc_time *tm)
{
u8 buf[M41T62_DATETIME_REG_SIZE];
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
/* Merge time-data and register flags into buf[0..7] */
buf[M41T62_REG_SSEC] = 0;
buf[M41T62_REG_SEC] =
bin2bcd(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f);
buf[M41T62_REG_MIN] =
bin2bcd(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f);
buf[M41T62_REG_HOUR] =
bin2bcd(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ;
buf[M41T62_REG_WDAY] =
(tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07);
buf[M41T62_REG_DAY] =
bin2bcd(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f);
buf[M41T62_REG_MON] =
bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);
/* assume 20YY not 19YY */
buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100);
if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE)) {
printf("I2C write failed in %s()\n", __func__);
return -1;
}
return 0;
}
void rtc_reset(void)
{
/*
* Nothing to do
*/
}
#endif
|
1001-study-uboot
|
drivers/rtc/m41t62.c
|
C
|
gpl3
| 4,311
|
/*
* (C) Copyright 2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <rtc.h>
#define RTC_RV3029_CTRL1 0x00
#define RTC_RV3029_CTRL1_EERE (1 << 3)
#define RTC_RV3029_CTRL_STATUS 0x03
#define RTC_RV3029_CTRLS_EEBUSY (1 << 7)
#define RTC_RV3029_CTRL_RESET 0x04
#define RTC_RV3029_CTRL_SYS_R (1 << 4)
#define RTC_RV3029_CLOCK_PAGE 0x08
#define RTC_RV3029_PAGE_LEN 7
#define RV3029C2_W_SECONDS 0x00
#define RV3029C2_W_MINUTES 0x01
#define RV3029C2_W_HOURS 0x02
#define RV3029C2_W_DATE 0x03
#define RV3029C2_W_DAYS 0x04
#define RV3029C2_W_MONTHS 0x05
#define RV3029C2_W_YEARS 0x06
#define RV3029C2_REG_HR_12_24 (1 << 6) /* 24h/12h mode */
#define RV3029C2_REG_HR_PM (1 << 5) /* PM/AM bit in 12h mode */
#define RTC_RV3029_EEPROM_CTRL 0x30
#define RTC_RV3029_TRICKLE_1K (1 << 4)
#define RTC_RV3029_TRICKLE_5K (1 << 5)
#define RTC_RV3029_TRICKLE_20K (1 << 6)
#define RTC_RV3029_TRICKLE_80K (1 << 7)
int rtc_get( struct rtc_time *tmp )
{
int ret;
unsigned char buf[RTC_RV3029_PAGE_LEN];
ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CLOCK_PAGE, 1, buf, \
RTC_RV3029_PAGE_LEN);
if (ret) {
printf("%s: error reading RTC: %x\n", __func__, ret);
return -1;
}
tmp->tm_sec = bcd2bin( buf[RV3029C2_W_SECONDS] & 0x7f);
tmp->tm_min = bcd2bin( buf[RV3029C2_W_MINUTES] & 0x7f);
if (buf[RV3029C2_W_HOURS] & RV3029C2_REG_HR_12_24) {
/* 12h format */
tmp->tm_hour = bcd2bin(buf[RV3029C2_W_HOURS] & 0x1f);
if (buf[RV3029C2_W_HOURS] & RV3029C2_REG_HR_PM)
/* PM flag set */
tmp->tm_hour += 12;
} else
tmp->tm_hour = bcd2bin(buf[RV3029C2_W_HOURS] & 0x3f);
tmp->tm_mday = bcd2bin( buf[RV3029C2_W_DATE] & 0x3F );
tmp->tm_mon = bcd2bin( buf[RV3029C2_W_MONTHS] & 0x1F );
tmp->tm_wday = bcd2bin( buf[RV3029C2_W_DAYS] & 0x07 );
/* RTC supports only years > 1999 */
tmp->tm_year = bcd2bin( buf[RV3029C2_W_YEARS]) + 2000;
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
debug( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
return 0;
}
int rtc_set( struct rtc_time *tmp )
{
int ret;
unsigned char buf[RTC_RV3029_PAGE_LEN];
debug( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
if (tmp->tm_year < 2000) {
printf("RTC: year %d < 2000 not possible\n", tmp->tm_year);
return -1;
}
buf[RV3029C2_W_SECONDS] = bin2bcd(tmp->tm_sec);
buf[RV3029C2_W_MINUTES] = bin2bcd(tmp->tm_min);
buf[RV3029C2_W_HOURS] = bin2bcd(tmp->tm_hour);
/* set 24h format */
buf[RV3029C2_W_HOURS] &= ~RV3029C2_REG_HR_12_24;
buf[RV3029C2_W_DATE] = bin2bcd(tmp->tm_mday);
buf[RV3029C2_W_DAYS] = bin2bcd(tmp->tm_wday);
buf[RV3029C2_W_MONTHS] = bin2bcd(tmp->tm_mon);
tmp->tm_year -= 2000;
buf[RV3029C2_W_YEARS] = bin2bcd(tmp->tm_year);
ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CLOCK_PAGE, 1,
buf, RTC_RV3029_PAGE_LEN);
/* give the RTC some time to update */
udelay(1000);
return ret;
}
/* sets EERE-Bit (automatic EEPROM refresh) */
static void set_eere_bit(int state)
{
unsigned char reg_ctrl1;
(void)i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1,
®_ctrl1, 1);
if (state)
reg_ctrl1 |= RTC_RV3029_CTRL1_EERE;
else
reg_ctrl1 &= (~RTC_RV3029_CTRL1_EERE);
(void)i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL1, 1,
®_ctrl1, 1);
}
/* waits until EEPROM page is no longer busy (times out after 10ms*loops) */
static int wait_eebusy(int loops)
{
int i;
unsigned char ctrl_status;
for (i = 0; i < loops; i++) {
(void)i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_STATUS,
1, &ctrl_status, 1);
if ((ctrl_status & RTC_RV3029_CTRLS_EEBUSY) == 0)
break;
udelay(10000);
}
return i;
}
void rtc_reset (void)
{
unsigned char buf[RTC_RV3029_PAGE_LEN];
buf[0] = RTC_RV3029_CTRL_SYS_R;
(void)i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_CTRL_RESET, 1,
buf, 1);
#if defined(CONFIG_SYS_RV3029_TCR)
/*
* because EEPROM_CTRL register is in EEPROM page it is necessary to
* disable automatic EEPROM refresh and check if EEPROM is busy
* before EEPORM_CTRL register may be accessed
*/
set_eere_bit(0);
wait_eebusy(100);
/* read current trickle charger setting */
(void)i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_RV3029_EEPROM_CTRL,
1, buf, 1);
/* enable automatic EEPROM refresh again */
set_eere_bit(1);
/*
* to minimize EEPROM access write trickle charger setting only if it
* differs from current value
*/
if ((buf[0] & 0xF0) != CONFIG_SYS_RV3029_TCR) {
buf[0] = (buf[0] & 0x0F) | CONFIG_SYS_RV3029_TCR;
/*
* write trickle charger setting (disable autom. EEPROM
* refresh and wait until EEPROM is idle)
*/
set_eere_bit(0);
wait_eebusy(100);
(void)i2c_write(CONFIG_SYS_I2C_RTC_ADDR,
RTC_RV3029_EEPROM_CTRL, 1, buf, 1);
/*
* it is necessary to wait 10ms before EEBUSY-Bit may be read
* (this is not documented in the data sheet yet, but the
* manufacturer recommends it)
*/
udelay(10000);
/* wait until EEPROM write access is finished */
wait_eebusy(100);
set_eere_bit(1);
}
#endif
}
|
1001-study-uboot
|
drivers/rtc/rv3029.c
|
C
|
gpl3
| 6,045
|
/*
* (C) Copyright 2001
* ARIO Data Networks, Inc. dchiu@ariodata.com
*
* Based on MontaVista DS1743 code and U-Boot mc146818 code
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the DS174x RTC
*/
/*#define DEBUG*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
static uchar rtc_read( unsigned int addr );
static void rtc_write( unsigned int addr, uchar val);
#define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR )
#define RTC_YEAR ( RTC_BASE + 7 )
#define RTC_MONTH ( RTC_BASE + 6 )
#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 )
#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 )
#define RTC_HOURS ( RTC_BASE + 3 )
#define RTC_MINUTES ( RTC_BASE + 2 )
#define RTC_SECONDS ( RTC_BASE + 1 )
#define RTC_CENTURY ( RTC_BASE + 0 )
#define RTC_CONTROLA RTC_CENTURY
#define RTC_CONTROLB RTC_SECONDS
#define RTC_CONTROLC RTC_DAY_OF_WEEK
#define RTC_CA_WRITE 0x80
#define RTC_CA_READ 0x40
#define RTC_CB_OSC_DISABLE 0x80
#define RTC_CC_BATTERY_FLAG 0x80
#define RTC_CC_FREQ_TEST 0x40
/* ------------------------------------------------------------------------- */
int rtc_get( struct rtc_time *tmp )
{
uchar sec, min, hour;
uchar mday, wday, mon, year;
int century;
uchar reg_a;
reg_a = rtc_read( RTC_CONTROLA );
/* lock clock registers for read */
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
sec = rtc_read( RTC_SECONDS );
min = rtc_read( RTC_MINUTES );
hour = rtc_read( RTC_HOURS );
mday = rtc_read( RTC_DAY_OF_MONTH );
wday = rtc_read( RTC_DAY_OF_WEEK );
mon = rtc_read( RTC_MONTH );
year = rtc_read( RTC_YEAR );
century = rtc_read( RTC_CENTURY );
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
#ifdef RTC_DEBUG
printf( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon_cent, mday, wday,
hour, min, sec );
#endif
tmp->tm_sec = bcd2bin( sec & 0x7F );
tmp->tm_min = bcd2bin( min & 0x7F );
tmp->tm_hour = bcd2bin( hour & 0x3F );
tmp->tm_mday = bcd2bin( mday & 0x3F );
tmp->tm_mon = bcd2bin( mon & 0x1F );
tmp->tm_wday = bcd2bin( wday & 0x07 );
/* glue year from century and year in century */
tmp->tm_year = bcd2bin( year ) +
( bcd2bin( century & 0x3F ) * 100 );
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
#ifdef RTC_DEBUG
printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
#endif
return 0;
}
int rtc_set( struct rtc_time *tmp )
{
uchar reg_a;
#ifdef RTC_DEBUG
printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
/* lock clock registers for write */
reg_a = rtc_read( RTC_CONTROLA );
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
/* break year up into century and year in century */
rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
return 0;
}
void rtc_reset (void)
{
uchar reg_a, reg_b, reg_c;
reg_a = rtc_read( RTC_CONTROLA );
reg_b = rtc_read( RTC_CONTROLB );
if ( reg_b & RTC_CB_OSC_DISABLE )
{
printf( "real-time-clock was stopped. Now starting...\n" );
reg_a |= RTC_CA_WRITE;
reg_b &= ~RTC_CB_OSC_DISABLE;
rtc_write( RTC_CONTROLA, reg_a );
rtc_write( RTC_CONTROLB, reg_b );
}
/* make sure read/write clock register bits are cleared */
reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
rtc_write( RTC_CONTROLA, reg_a );
reg_c = rtc_read( RTC_CONTROLC );
if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
printf( "RTC battery low. Clock setting may not be reliable.\n" );
}
/* ------------------------------------------------------------------------- */
static uchar rtc_read( unsigned int addr )
{
uchar val = in8( addr );
#ifdef RTC_DEBUG
printf( "rtc_read: %x:%x\n", addr, val );
#endif
return( val );
}
static void rtc_write( unsigned int addr, uchar val )
{
#ifdef RTC_DEBUG
printf( "rtc_write: %x:%x\n", addr, val );
#endif
out8( addr, val );
}
#endif
|
1001-study-uboot
|
drivers/rtc/ds174x.c
|
C
|
gpl3
| 5,332
|
/*
* (C) Copyright 2002 SIXNET, dge@sixnetio.com.
*
* (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for DS1306 RTC using SPI:
*
* - SXNI855T: it uses its own soft SPI here in this file
* - all other: use the external spi_xfer() function
* (see include/spi.h)
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <spi.h>
#if defined(CONFIG_CMD_DATE)
#define RTC_SECONDS 0x00
#define RTC_MINUTES 0x01
#define RTC_HOURS 0x02
#define RTC_DAY_OF_WEEK 0x03
#define RTC_DATE_OF_MONTH 0x04
#define RTC_MONTH 0x05
#define RTC_YEAR 0x06
#define RTC_SECONDS_ALARM0 0x07
#define RTC_MINUTES_ALARM0 0x08
#define RTC_HOURS_ALARM0 0x09
#define RTC_DAY_OF_WEEK_ALARM0 0x0a
#define RTC_SECONDS_ALARM1 0x0b
#define RTC_MINUTES_ALARM1 0x0c
#define RTC_HOURS_ALARM1 0x0d
#define RTC_DAY_OF_WEEK_ALARM1 0x0e
#define RTC_CONTROL 0x0f
#define RTC_STATUS 0x10
#define RTC_TRICKLE_CHARGER 0x11
#define RTC_USER_RAM_BASE 0x20
/* ************************************************************************* */
#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */
static void soft_spi_send (unsigned char n);
static unsigned char soft_spi_read (void);
static void init_spi (void);
/*-----------------------------------------------------------------------
* Definitions
*/
#define PB_SPISCK 0x00000002 /* PB 30 */
#define PB_SPIMOSI 0x00000004 /* PB 29 */
#define PB_SPIMISO 0x00000008 /* PB 28 */
#define PB_SPI_CE 0x00010000 /* PB 15 */
/* ------------------------------------------------------------------------- */
/* read clock time from DS1306 and return it in *tmp */
int rtc_get (struct rtc_time *tmp)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
unsigned char spi_byte; /* Data Byte */
init_spi (); /* set port B for software SPI */
/* Now we can enable the DS1306 RTC */
immap->im_cpm.cp_pbdat |= PB_SPI_CE;
udelay (10);
/* Shift out the address (0) of the time in the Clock Chip */
soft_spi_send (0);
/* Put the clock readings into the rtc_time structure */
tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */
tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */
/* Hours are trickier */
spi_byte = soft_spi_read (); /* Read Hours into temporary value */
if (spi_byte & 0x40) {
/* 12 hour mode bit is set (time is in 1-12 format) */
if (spi_byte & 0x20) {
/* since PM we add 11 to get 0-23 for hours */
tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
} else {
/* since AM we subtract 1 to get 0-23 for hours */
tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
}
} else {
/* Otherwise, 0-23 hour format */
tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
}
soft_spi_read (); /* Read and discard Day of week */
tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */
tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */
/* Read Year and convert to this century */
tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;
/* Now we can disable the DS1306 RTC */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
udelay (10);
GregorianDay (tmp); /* Determine the day of week */
debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
/* ------------------------------------------------------------------------- */
/* set clock time in DS1306 RTC and in MPC8xx RTC */
int rtc_set (struct rtc_time *tmp)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
init_spi (); /* set port B for software SPI */
/* Now we can enable the DS1306 RTC */
immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
udelay (10);
/* First disable write protect in the clock chip control register */
soft_spi_send (0x8F); /* send address of the control register */
soft_spi_send (0x00); /* send control register contents */
/* Now disable the DS1306 to terminate the write */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
udelay (10);
/* Now enable the DS1306 to initiate a new write */
immap->im_cpm.cp_pbdat |= PB_SPI_CE;
udelay (10);
/* Next, send the address of the clock time write registers */
soft_spi_send (0x80); /* send address of the first time register */
/* Use Burst Mode to send all of the time data to the clock */
bin2bcd (tmp->tm_sec);
soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */
soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */
soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */
soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */
soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */
soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */
soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */
/* Now we can disable the Clock chip to terminate the burst write */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
udelay (10);
/* Now we can enable the Clock chip to initiate a new write */
immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
udelay (10);
/* First we Enable write protect in the clock chip control register */
soft_spi_send (0x8F); /* send address of the control register */
soft_spi_send (0x40); /* send out Control Register contents */
/* Now disable the DS1306 */
immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
udelay (10);
/* Set standard MPC8xx clock to the same time so Linux will
* see the time even if it doesn't have a DS1306 clock driver.
* This helps with experimenting with standard kernels.
*/
{
ulong tim;
tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
immap->im_sitk.sitk_rtck = KAPWR_KEY;
immap->im_sit.sit_rtc = tim;
}
debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
/* ------------------------------------------------------------------------- */
/* Initialize Port B for software SPI */
static void init_spi (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
/* Force output pins to begin at logic 0 */
immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);
/* Set these 3 signals as outputs */
immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */
udelay (10);
}
/* ------------------------------------------------------------------------- */
/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
static void soft_spi_send (unsigned char n)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
unsigned char bitpos; /* bit position to receive */
unsigned char i; /* Loop Control */
/* bit position to send, start with most significant bit */
bitpos = 0x80;
/* Send 8 bits to software SPI */
for (i = 0; i < 8; i++) { /* Loop for 8 bits */
immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
if (n & bitpos)
immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */
else
immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */
udelay (10);
immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
udelay (10);
bitpos >>= 1; /* Shift for next bit position */
}
}
/* ------------------------------------------------------------------------- */
/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
static unsigned char soft_spi_read (void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
unsigned char spi_byte = 0; /* Return value, assume success */
unsigned char bitpos; /* bit position to receive */
unsigned char i; /* Loop Control */
/* bit position to receive, start with most significant bit */
bitpos = 0x80;
/* Read 8 bits here */
for (i = 0; i < 8; i++) { /* Do 8 bits in loop */
immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
udelay (10);
if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */
spi_byte |= bitpos; /* Set data accordingly */
immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
udelay (10);
bitpos >>= 1; /* Shift for next bit position */
}
return spi_byte; /* Return the byte read */
}
/* ------------------------------------------------------------------------- */
void rtc_reset (void)
{
return; /* nothing to do */
}
#else /* not CONFIG_SXNI855T */
/* ************************************************************************* */
static unsigned char rtc_read (unsigned char reg);
static void rtc_write (unsigned char reg, unsigned char val);
static struct spi_slave *slave;
/* read clock time from DS1306 and return it in *tmp */
int rtc_get (struct rtc_time *tmp)
{
unsigned char sec, min, hour, mday, wday, mon, year;
/*
* Assuming Vcc = 2.0V (lowest speed)
*
* REVISIT: If we add an rtc_init() function we can do this
* step just once.
*/
if (!slave) {
slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
sec = rtc_read (RTC_SECONDS);
min = rtc_read (RTC_MINUTES);
hour = rtc_read (RTC_HOURS);
mday = rtc_read (RTC_DATE_OF_MONTH);
wday = rtc_read (RTC_DAY_OF_WEEK);
mon = rtc_read (RTC_MONTH);
year = rtc_read (RTC_YEAR);
spi_release_bus(slave);
debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday, hour, min, sec);
debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
rtc_read (RTC_DAY_OF_WEEK_ALARM0),
rtc_read (RTC_HOURS_ALARM0),
rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
rtc_read (RTC_DAY_OF_WEEK_ALARM1),
rtc_read (RTC_HOURS_ALARM1),
rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));
tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */
tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */
/* convert Hours */
tmp->tm_hour = (hour & 0x40)
? ((hour & 0x20) /* 12 hour mode */
? bcd2bin (hour & 0x1F) + 11 /* PM */
: bcd2bin (hour & 0x1F) - 1 /* AM */
)
: bcd2bin (hour & 0x3F); /* 24 hour mode */
tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */
tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */
tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */
tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
/* ------------------------------------------------------------------------- */
/* set clock time from *tmp in DS1306 RTC */
int rtc_set (struct rtc_time *tmp)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
spi_release_bus(slave);
}
/* ------------------------------------------------------------------------- */
/* reset the DS1306 */
void rtc_reset (void)
{
/* Assuming Vcc = 2.0V (lowest speed) */
if (!slave) {
slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
SPI_MODE_3 | SPI_CS_HIGH);
if (!slave)
return;
}
if (spi_claim_bus(slave))
return;
/* clear the control register */
rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
/* reset all alarms */
rtc_write (RTC_SECONDS_ALARM0, 0x00);
rtc_write (RTC_SECONDS_ALARM1, 0x00);
rtc_write (RTC_MINUTES_ALARM0, 0x00);
rtc_write (RTC_MINUTES_ALARM1, 0x00);
rtc_write (RTC_HOURS_ALARM0, 0x00);
rtc_write (RTC_HOURS_ALARM1, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
spi_release_bus(slave);
}
/* ------------------------------------------------------------------------- */
static unsigned char rtc_read (unsigned char reg)
{
int ret;
ret = spi_w8r8(slave, reg);
return ret < 0 ? 0 : ret;
}
/* ------------------------------------------------------------------------- */
static void rtc_write (unsigned char reg, unsigned char val)
{
unsigned char dout[2]; /* SPI Output Data Bytes */
unsigned char din[2]; /* SPI Input Data Bytes */
dout[0] = 0x80 | reg;
dout[1] = val;
spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
}
#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */
#endif
|
1001-study-uboot
|
drivers/rtc/ds1306.c
|
C
|
gpl3
| 14,161
|
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for internal RTC of MPC8xx
*/
/*#define DEBUG*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
ulong tim;
tim = immr->im_sit.sit_rtc;
to_tm (tim, tmp);
debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
ulong tim;
debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
immr->im_sitk.sitk_rtck = KAPWR_KEY;
immr->im_sit.sit_rtc = tim;
return 0;
}
void rtc_reset (void)
{
return; /* nothing to do */
}
#endif
|
1001-study-uboot
|
drivers/rtc/mpc8xx.c
|
C
|
gpl3
| 1,992
|
/*
* Copyright (C) 2011
* Jason Cooper <u-boot@lakedaemon.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for Marvell Integrated RTC
*/
#ifndef _MVRTC_H_
#define _MVRTC_H_
#include <asm/arch/kirkwood.h>
#include <compiler.h>
/* RTC registers */
struct mvrtc_registers {
u32 time;
u32 date;
};
/* time register */
#define MVRTC_SEC_SFT 0
#define MVRTC_SEC_MSK 0x7f
#define MVRTC_MIN_SFT 8
#define MVRTC_MIN_MSK 0x7f
#define MVRTC_HOUR_SFT 16
#define MVRTC_HOUR_MSK 0x3f
#define MVRTC_DAY_SFT 24
#define MVRTC_DAY_MSK 0x7
/*
* Hour format bit
* 1 = 12 hour clock
* 0 = 24 hour clock
*/
#define MVRTC_HRFMT_MSK 0x00400000
/* date register */
#define MVRTC_DATE_SFT 0
#define MVRTC_DATE_MSK 0x3f
#define MVRTC_MON_SFT 8
#define MVRTC_MON_MSK 0x1f
#define MVRTC_YEAR_SFT 16
#define MVRTC_YEAR_MSK 0xff
#endif
|
1001-study-uboot
|
drivers/rtc/mvrtc.h
|
C
|
gpl3
| 1,622
|
/*
* Faraday FTRTC010 Real Time Clock
*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
#include <common.h>
#include <rtc.h>
#include <asm/io.h>
struct ftrtc010 {
unsigned int sec; /* 0x00 */
unsigned int min; /* 0x04 */
unsigned int hour; /* 0x08 */
unsigned int day; /* 0x0c */
unsigned int alarm_sec; /* 0x10 */
unsigned int alarm_min; /* 0x14 */
unsigned int alarm_hour; /* 0x18 */
unsigned int record; /* 0x1c */
unsigned int cr; /* 0x20 */
unsigned int wsec; /* 0x24 */
unsigned int wmin; /* 0x28 */
unsigned int whour; /* 0x2c */
unsigned int wday; /* 0x30 */
unsigned int intr; /* 0x34 */
unsigned int div; /* 0x38 */
unsigned int rev; /* 0x3c */
};
/*
* RTC Control Register
*/
#define FTRTC010_CR_ENABLE (1 << 0)
#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */
#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */
#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */
#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */
static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE;
static void ftrtc010_enable(void)
{
writel(FTRTC010_CR_ENABLE, &rtc->cr);
}
/*
* return current time in seconds
*/
static unsigned long ftrtc010_time(void)
{
unsigned long day;
unsigned long hour;
unsigned long minute;
unsigned long second;
unsigned long second2;
do {
second = readl(&rtc->sec);
day = readl(&rtc->day);
hour = readl(&rtc->hour);
minute = readl(&rtc->min);
second2 = readl(&rtc->sec);
} while (second != second2);
return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second;
}
/*
* Get the current time from the RTC
*/
int rtc_get(struct rtc_time *tmp)
{
unsigned long now;
debug("%s(): record register: %x\n",
__func__, readl(&rtc->record));
#ifdef CONFIG_FTRTC010_PCLK
now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT;
#else /* CONFIG_FTRTC010_EXTCLK */
now = ftrtc010_time() + readl(&rtc->record);
#endif
to_tm(now, tmp);
return 0;
}
/*
* Set the RTC
*/
int rtc_set(struct rtc_time *tmp)
{
unsigned long new;
unsigned long now;
debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
__func__,
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
new = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour,
tmp->tm_min, tmp->tm_sec);
now = ftrtc010_time();
debug("%s(): write %lx to record register\n", __func__, new - now);
writel(new - now, &rtc->record);
return 0;
}
void rtc_reset(void)
{
debug("%s()\n", __func__);
ftrtc010_enable();
}
|
1001-study-uboot
|
drivers/rtc/ftrtc010.c
|
C
|
gpl3
| 3,385
|
/*
* (C) Copyright 2002
* ARIO Data Networks, Inc. dchiu@ariodata.com
*
* modified for DS1556:
* Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
*
* Based on MontaVista DS1743 code and U-Boot mc146818 code
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the DS1556 RTC
*/
/*#define RTC_DEBUG */
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
static uchar rtc_read( unsigned int addr );
static void rtc_write( unsigned int addr, uchar val);
#define RTC_BASE ( CONFIG_SYS_NVRAM_SIZE + CONFIG_SYS_NVRAM_BASE_ADDR )
#define RTC_YEAR ( RTC_BASE + 0xf )
#define RTC_MONTH ( RTC_BASE + 0xe )
#define RTC_DAY_OF_MONTH ( RTC_BASE + 0xd )
#define RTC_DAY_OF_WEEK ( RTC_BASE + 0xc )
#define RTC_HOURS ( RTC_BASE + 0xb )
#define RTC_MINUTES ( RTC_BASE + 0xa )
#define RTC_SECONDS ( RTC_BASE + 0x9 )
#define RTC_CENTURY ( RTC_BASE + 0x8 )
#define RTC_CONTROLA RTC_CENTURY
#define RTC_CONTROLB RTC_SECONDS
#define RTC_CONTROLC RTC_BASE
#define RTC_CA_WRITE 0x80
#define RTC_CA_READ 0x40
#define RTC_CB_OSC_DISABLE 0x80
#define RTC_CC_BATTERY_FLAG 0x10
#define RTC_CC_FREQ_TEST 0x40
/* ------------------------------------------------------------------------- */
int rtc_get( struct rtc_time *tmp )
{
uchar sec, min, hour;
uchar mday, wday, mon, year;
int century;
uchar reg_a;
reg_a = rtc_read( RTC_CONTROLA );
/* lock clock registers for read */
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
sec = rtc_read( RTC_SECONDS );
min = rtc_read( RTC_MINUTES );
hour = rtc_read( RTC_HOURS );
mday = rtc_read( RTC_DAY_OF_MONTH );
wday = rtc_read( RTC_DAY_OF_WEEK );
mon = rtc_read( RTC_MONTH );
year = rtc_read( RTC_YEAR );
century = rtc_read( RTC_CENTURY );
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
#ifdef RTC_DEBUG
printf( "Get RTC year: %02x mon/cent: %02x mon: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, century, mon, mday, wday,
hour, min, sec );
#endif
tmp->tm_sec = bcd2bin( sec & 0x7F );
tmp->tm_min = bcd2bin( min & 0x7F );
tmp->tm_hour = bcd2bin( hour & 0x3F );
tmp->tm_mday = bcd2bin( mday & 0x3F );
tmp->tm_mon = bcd2bin( mon & 0x1F );
tmp->tm_wday = bcd2bin( wday & 0x07 );
/* glue year from century and year in century */
tmp->tm_year = bcd2bin( year ) +
( bcd2bin( century & 0x3F ) * 100 );
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
#ifdef RTC_DEBUG
printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
#endif
return 0;
}
int rtc_set( struct rtc_time *tmp )
{
uchar reg_a;
#ifdef RTC_DEBUG
printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
/* lock clock registers for write */
reg_a = rtc_read( RTC_CONTROLA );
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
/* break year up into century and year in century */
rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
return 0;
}
void rtc_reset (void)
{
uchar reg_a, reg_b, reg_c;
reg_a = rtc_read( RTC_CONTROLA );
reg_b = rtc_read( RTC_CONTROLB );
if ( reg_b & RTC_CB_OSC_DISABLE )
{
printf( "real-time-clock was stopped. Now starting...\n" );
reg_a |= RTC_CA_WRITE;
reg_b &= ~RTC_CB_OSC_DISABLE;
rtc_write( RTC_CONTROLA, reg_a );
rtc_write( RTC_CONTROLB, reg_b );
}
/* make sure read/write clock register bits are cleared */
reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
rtc_write( RTC_CONTROLA, reg_a );
reg_c = rtc_read( RTC_CONTROLC );
if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
printf( "RTC battery low. Clock setting may not be reliable.\n" );
}
/* ------------------------------------------------------------------------- */
static uchar rtc_read( unsigned int addr )
{
uchar val = *(volatile unsigned char*)(addr);
#ifdef RTC_DEBUG
printf( "rtc_read: %x:%x\n", addr, val );
#endif
return( val );
}
static void rtc_write( unsigned int addr, uchar val )
{
#ifdef RTC_DEBUG
printf( "rtc_write: %x:%x\n", addr, val );
#endif
*(volatile unsigned char*)(addr) = val;
}
#endif
|
1001-study-uboot
|
drivers/rtc/ds1556.c
|
C
|
gpl3
| 5,492
|
/*
* Freescale i.MX28 RTC Driver
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <rtc.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#define MXS_RTC_MAX_TIMEOUT 1000000
/* Set time in seconds since 1970-01-01 */
int mxs_rtc_set_time(uint32_t secs)
{
struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
int ret;
writel(secs, &rtc_regs->hw_rtc_seconds);
/*
* The 0x80 here means seconds were copied to analog. This information
* is taken from the linux kernel driver for the STMP37xx RTC since
* documentation doesn't mention it.
*/
ret = mx28_wait_mask_clr(&rtc_regs->hw_rtc_stat_reg,
0x80 << RTC_STAT_STALE_REGS_OFFSET, MXS_RTC_MAX_TIMEOUT);
if (ret)
printf("MXS RTC: Timeout waiting for update\n");
return ret;
}
int rtc_get(struct rtc_time *time)
{
struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
uint32_t secs;
secs = readl(&rtc_regs->hw_rtc_seconds);
to_tm(secs, time);
return 0;
}
int rtc_set(struct rtc_time *time)
{
uint32_t secs;
secs = mktime(time->tm_year, time->tm_mon, time->tm_mday,
time->tm_hour, time->tm_min, time->tm_sec);
return mxs_rtc_set_time(secs);
}
void rtc_reset(void)
{
struct mx28_rtc_regs *rtc_regs = (struct mx28_rtc_regs *)MXS_RTC_BASE;
int ret;
/* Set time to 1970-01-01 */
mxs_rtc_set_time(0);
/* Reset the RTC block */
ret = mx28_reset_block(&rtc_regs->hw_rtc_ctrl_reg);
if (ret)
printf("MXS RTC: Block reset timeout\n");
}
|
1001-study-uboot
|
drivers/rtc/mxsrtc.c
|
C
|
gpl3
| 2,304
|
/*
* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <rtc.h>
#include <spi.h>
#include <pmic.h>
#include <fsl_pmic.h>
int rtc_get(struct rtc_time *rtc)
{
u32 day1, day2, time;
int tim, i = 0;
struct pmic *p = get_pmic();
int ret;
do {
ret = pmic_reg_read(p, REG_RTC_DAY, &day1);
if (ret < 0)
return -1;
ret = pmic_reg_read(p, REG_RTC_TIME, &time);
if (ret < 0)
return -1;
ret = pmic_reg_read(p, REG_RTC_DAY, &day2);
if (ret < 0)
return -1;
} while (day1 != day2 && i++ < 3);
tim = day1 * 86400 + time;
to_tm(tim, rtc);
rtc->tm_yday = 0;
rtc->tm_isdst = 0;
return 0;
}
int rtc_set(struct rtc_time *rtc)
{
u32 time, day;
struct pmic *p = get_pmic();
time = mktime(rtc->tm_year, rtc->tm_mon, rtc->tm_mday,
rtc->tm_hour, rtc->tm_min, rtc->tm_sec);
day = time / 86400;
time %= 86400;
pmic_reg_write(p, REG_RTC_DAY, day);
pmic_reg_write(p, REG_RTC_TIME, time);
return 0;
}
void rtc_reset(void)
{
}
|
1001-study-uboot
|
drivers/rtc/mc13xxx-rtc.c
|
C
|
gpl3
| 1,791
|
/*
* (C) Copyright 2001
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for ST Electronics M48T35Ax RTC
*/
/*#define DEBUG */
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <config.h>
#if defined(CONFIG_CMD_DATE)
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
{
uchar sec, min, hour, cent_day, date, month, year;
uchar ccr; /* Clock control register */
/* Lock RTC for read using clock control register */
ccr = rtc_read(0);
ccr = ccr | 0x40;
rtc_write(0, ccr);
sec = rtc_read (0x1);
min = rtc_read (0x2);
hour = rtc_read (0x3);
cent_day= rtc_read (0x4);
date = rtc_read (0x5);
month = rtc_read (0x6);
year = rtc_read (0x7);
/* UNLock RTC */
ccr = rtc_read(0);
ccr = ccr & 0xBF;
rtc_write(0, ccr);
debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, month, date, cent_day,
hour, min, sec );
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (date & 0x3F);
tmp->tm_mon = bcd2bin (month & 0x1F);
tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900);
tmp->tm_wday = bcd2bin (cent_day & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
uchar ccr; /* Clock control register */
uchar century;
debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
/* Lock RTC for write using clock control register */
ccr = rtc_read(0);
ccr = ccr | 0x80;
rtc_write(0, ccr);
rtc_write (0x07, bin2bcd(tmp->tm_year % 100));
rtc_write (0x06, bin2bcd(tmp->tm_mon));
rtc_write (0x05, bin2bcd(tmp->tm_mday));
century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20;
rtc_write (0x04, bin2bcd(tmp->tm_wday) | century);
rtc_write (0x03, bin2bcd(tmp->tm_hour));
rtc_write (0x02, bin2bcd(tmp->tm_min ));
rtc_write (0x01, bin2bcd(tmp->tm_sec ));
/* UNLock RTC */
ccr = rtc_read(0);
ccr = ccr & 0x7F;
rtc_write(0, ccr);
return 0;
}
void rtc_reset (void)
{
uchar val;
/* Clear all clock control registers */
rtc_write (0x0, 0x80); /* No Read Lock or calibration */
/* Clear stop bit */
val = rtc_read (0x1);
val &= 0x7f;
rtc_write(0x1, val);
/* Enable century / disable frequency test */
val = rtc_read (0x4);
val = (val & 0xBF) | 0x20;
rtc_write(0x4, val);
/* Clear write lock */
rtc_write(0x0, 0);
}
/* ------------------------------------------------------------------------- */
static uchar rtc_read (uchar reg)
{
uchar val;
val = *(unsigned char *)
((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg);
return val;
}
static void rtc_write (uchar reg, uchar val)
{
*(unsigned char *)
((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val;
}
#endif
|
1001-study-uboot
|
drivers/rtc/m48t35ax.c
|
C
|
gpl3
| 4,051
|
/*
* (C) Copyright 2007
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Epson RX8025 RTC driver.
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
#ifdef DEBUG_RTC
#define DEBUGR(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGR(fmt,args...)
#endif
/*---------------------------------------------------------------------*/
#ifndef CONFIG_SYS_I2C_RTC_ADDR
# define CONFIG_SYS_I2C_RTC_ADDR 0x32
#endif
/*
* RTC register addresses
*/
#define RTC_SEC_REG_ADDR 0x00
#define RTC_MIN_REG_ADDR 0x01
#define RTC_HR_REG_ADDR 0x02
#define RTC_DAY_REG_ADDR 0x03
#define RTC_DATE_REG_ADDR 0x04
#define RTC_MON_REG_ADDR 0x05
#define RTC_YR_REG_ADDR 0x06
#define RTC_CTL1_REG_ADDR 0x0e
#define RTC_CTL2_REG_ADDR 0x0f
/*
* Control register 1 bits
*/
#define RTC_CTL1_BIT_2412 0x20
/*
* Control register 2 bits
*/
#define RTC_CTL2_BIT_PON 0x10
#define RTC_CTL2_BIT_VDET 0x40
#define RTC_CTL2_BIT_XST 0x20
#define RTC_CTL2_BIT_VDSL 0x80
/*
* Note: the RX8025 I2C RTC requires register
* reads and write to consist of a single bus
* cycle. It is not allowed to write the register
* address in a first cycle that is terminated by
* a STOP condition. The chips needs a 'restart'
* sequence (start sequence without a prior stop).
* This driver has been written for a 4xx board.
* U-Boot's 4xx i2c driver is currently not capable
* to generate such cycles to some work arounds
* are used.
*/
/* static uchar rtc_read (uchar reg); */
#define rtc_read(reg) buf[((reg) + 1) & 0xf]
static void rtc_write (uchar reg, uchar val);
/*
* Get the current time from the RTC
*/
int rtc_get (struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year, ctl2;
uchar buf[16];
if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
printf("Error reading from RTC\n");
sec = rtc_read(RTC_SEC_REG_ADDR);
min = rtc_read(RTC_MIN_REG_ADDR);
hour = rtc_read(RTC_HR_REG_ADDR);
wday = rtc_read(RTC_DAY_REG_ADDR);
mday = rtc_read(RTC_DATE_REG_ADDR);
mon = rtc_read(RTC_MON_REG_ADDR);
year = rtc_read(RTC_YR_REG_ADDR);
DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday, hour, min, sec);
/* dump status */
ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
if (ctl2 & RTC_CTL2_BIT_PON) {
printf("RTC: power-on detected\n");
rel = -1;
}
if (ctl2 & RTC_CTL2_BIT_VDET) {
printf("RTC: voltage drop detected\n");
rel = -1;
}
if (!(ctl2 & RTC_CTL2_BIT_XST)) {
printf("RTC: oscillator stop detected\n");
rel = -1;
}
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
if (rtc_read(RTC_CTL1_REG_ADDR) & RTC_CTL1_BIT_2412)
tmp->tm_hour = bcd2bin (hour & 0x3F);
else
tmp->tm_hour = bcd2bin (hour & 0x1F) % 12 +
((hour & 0x20) ? 12 : 0);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
tmp->tm_wday = bcd2bin (wday & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return rel;
}
/*
* Set the RTC
*/
int rtc_set (struct rtc_time *tmp)
{
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
rtc_write (RTC_CTL1_REG_ADDR, RTC_CTL1_BIT_2412);
return 0;
}
/*
* Reset the RTC. We setting the date back to 1970-01-01.
*/
void rtc_reset (void)
{
struct rtc_time tmp;
uchar buf[16];
uchar ctl2;
if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 16))
printf("Error reading from RTC\n");
ctl2 = rtc_read(RTC_CTL2_REG_ADDR);
ctl2 &= ~(RTC_CTL2_BIT_PON | RTC_CTL2_BIT_VDET);
ctl2 |= RTC_CTL2_BIT_XST | RTC_CTL2_BIT_VDSL;
rtc_write (RTC_CTL2_REG_ADDR, ctl2);
tmp.tm_year = 1970;
tmp.tm_mon = 1;
tmp.tm_mday= 1;
tmp.tm_hour = 0;
tmp.tm_min = 0;
tmp.tm_sec = 0;
rtc_set(&tmp);
printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
return;
}
/*
* Helper functions
*/
static void rtc_write (uchar reg, uchar val)
{
uchar buf[2];
buf[0] = reg << 4;
buf[1] = val;
if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 0, buf, 2) != 0)
printf("Error writing to RTC\n");
}
#endif /* CONFIG_RTC_RX8025 && CONFIG_CMD_DATE */
|
1001-study-uboot
|
drivers/rtc/rx8025.c
|
C
|
gpl3
| 5,913
|
/*
* (C) Copyright 2008, 2009
* Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/io.h>
#include <common.h>
#include <command.h>
#include <config.h>
#include <rtc.h>
#include <tws.h>
#if defined(CONFIG_CMD_DATE)
/*
* Note: The acrobatics below is due to the hideously ingenius idea of
* the chip designers. As the chip does not allow register
* addressing, all values need to be read and written in one go. Sure
* enough, the 'wday' field (0-6) is transferred using the economic
* number of 4 bits right in the middle of the packet.....
*/
int rtc_get(struct rtc_time *tm)
{
int rel = 0;
uchar buffer[7];
memset(buffer, 0, 7);
/* Read 52 bits into our buffer */
tws_read(buffer, 52);
tm->tm_sec = bcd2bin( buffer[0] & 0x7F);
tm->tm_min = bcd2bin( buffer[1] & 0x7F);
tm->tm_hour = bcd2bin( buffer[2] & 0x3F);
tm->tm_wday = bcd2bin( buffer[3] & 0x07);
tm->tm_mday = bcd2bin((buffer[3] & 0xF0) >> 4 | (buffer[4] & 0x0F) << 4);
tm->tm_mon = bcd2bin((buffer[4] & 0x30) >> 4 | (buffer[5] & 0x0F) << 4);
tm->tm_year = bcd2bin((buffer[5] & 0xF0) >> 4 | (buffer[6] & 0x0F) << 4) + 2000;
tm->tm_yday = 0;
tm->tm_isdst = 0;
if (tm->tm_sec & 0x80) {
puts("### Warning: RTC Low Voltage - date/time not reliable\n");
rel = -1;
}
debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
return rel;
}
int rtc_set(struct rtc_time *tm)
{
uchar buffer[7];
uchar tmp;
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
memset(buffer, 0, 7);
buffer[0] = bin2bcd(tm->tm_sec);
buffer[1] = bin2bcd(tm->tm_min);
buffer[2] = bin2bcd(tm->tm_hour);
buffer[3] = bin2bcd(tm->tm_wday);
tmp = bin2bcd(tm->tm_mday);
buffer[3] |= (tmp & 0x0F) << 4;
buffer[4] = (tmp & 0xF0) >> 4;
tmp = bin2bcd(tm->tm_mon);
buffer[4] |= (tmp & 0x0F) << 4;
buffer[5] = (tmp & 0xF0) >> 4;
tmp = bin2bcd(tm->tm_year % 100);
buffer[5] |= (tmp & 0x0F) << 4;
buffer[6] = (tmp & 0xF0) >> 4;
/* Write the resulting 52 bits to device */
tws_write(buffer, 52);
return 0;
}
void rtc_reset(void)
{
struct rtc_time tmp;
tmp.tm_sec = 0;
tmp.tm_min = 0;
tmp.tm_hour = 0;
tmp.tm_wday = 4;
tmp.tm_mday = 1;
tmp.tm_mon = 1;
tmp.tm_year = 2000;
rtc_set(&tmp);
}
#endif
|
1001-study-uboot
|
drivers/rtc/rtc4543.c
|
C
|
gpl3
| 3,217
|
/*
* (C) Copyright 2004
* Reinhard Meyer, EMK Elektronik GmbH
* r.meyer@emk-elektronik.de
* www.emk-elektronik.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*****************************************************************************
* Date & Time support for internal RTC of MPC52xx
*****************************************************************************/
/*#define DEBUG*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
/*****************************************************************************
* this structure should be defined in mpc5200.h ...
*****************************************************************************/
typedef struct rtc5200 {
volatile ulong tsr; /* MBAR+0x800: time set register */
volatile ulong dsr; /* MBAR+0x804: data set register */
volatile ulong nysr; /* MBAR+0x808: new year and stopwatch register */
volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */
volatile ulong ctr; /* MBAR+0x810: current time register */
volatile ulong cdr; /* MBAR+0x814: current data register */
volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interrupt register */
volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */
volatile ulong trdr; /* MBAR+0x820: test register/divides register */
} RTC5200;
#define RTC_SET 0x02000000
#define RTC_PAUSE 0x01000000
/*****************************************************************************
* get time
*****************************************************************************/
int rtc_get (struct rtc_time *tmp)
{
RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800);
ulong time, date, time2;
/* read twice to avoid getting a funny time when the second is just changing */
do {
time = rtc->ctr;
date = rtc->cdr;
time2 = rtc->ctr;
} while (time != time2);
tmp->tm_year = date & 0xfff;
tmp->tm_mon = (date >> 24) & 0xf;
tmp->tm_mday = (date >> 16) & 0x1f;
tmp->tm_wday = (date >> 21) & 7;
/* sunday is 7 in 5200 but 0 in rtc_time */
if (tmp->tm_wday == 7)
tmp->tm_wday = 0;
tmp->tm_hour = (time >> 16) & 0x1f;
tmp->tm_min = (time >> 8) & 0x3f;
tmp->tm_sec = time & 0x3f;
debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
/*****************************************************************************
* set time
*****************************************************************************/
int rtc_set (struct rtc_time *tmp)
{
RTC5200 *rtc = (RTC5200 *) (CONFIG_SYS_MBAR+0x800);
ulong time, date, year;
debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
time = (tmp->tm_hour << 16) | (tmp->tm_min << 8) | tmp->tm_sec;
date = (tmp->tm_mon << 16) | tmp->tm_mday;
if (tmp->tm_wday == 0)
date |= (7 << 8);
else
date |= (tmp->tm_wday << 8);
year = tmp->tm_year;
/* mask unwanted bits that might show up when rtc_time is corrupt */
time &= 0x001f3f3f;
date &= 0x001f071f;
year &= 0x00000fff;
/* pause and set the RTC */
rtc->nysr = year;
rtc->dsr = date | RTC_PAUSE;
udelay (1000);
rtc->dsr = date | RTC_PAUSE | RTC_SET;
udelay (1000);
rtc->dsr = date | RTC_PAUSE;
udelay (1000);
rtc->dsr = date;
udelay (1000);
rtc->tsr = time | RTC_PAUSE;
udelay (1000);
rtc->tsr = time | RTC_PAUSE | RTC_SET;
udelay (1000);
rtc->tsr = time | RTC_PAUSE;
udelay (1000);
rtc->tsr = time;
udelay (1000);
return 0;
}
/*****************************************************************************
* reset rtc circuit
*****************************************************************************/
void rtc_reset (void)
{
return; /* nothing to do */
}
#endif
|
1001-study-uboot
|
drivers/rtc/mpc5xxx.c
|
C
|
gpl3
| 4,608
|
/*
* Copyright (C) 2011
* Jason Cooper <u-boot@lakedaemon.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for Marvell Integrated RTC
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <asm/io.h>
#include "mvrtc.h"
/* This RTC does not support century, so we assume 20 */
#define CENTURY 20
int rtc_get(struct rtc_time *t)
{
u32 time;
u32 date;
struct mvrtc_registers *mvrtc_regs;
mvrtc_regs = (struct mvrtc_registers *)KW_RTC_BASE;
/* read the time register */
time = readl(&mvrtc_regs->time);
/* read the date register */
date = readl(&mvrtc_regs->date);
/* test for 12 hour clock (can't tell if it's am/pm) */
if (time & MVRTC_HRFMT_MSK) {
printf("Error: RTC in 12 hour mode, can't determine AM/PM.\n");
return -1;
}
/* time */
t->tm_sec = bcd2bin((time >> MVRTC_SEC_SFT) & MVRTC_SEC_MSK);
t->tm_min = bcd2bin((time >> MVRTC_MIN_SFT) & MVRTC_MIN_MSK);
t->tm_hour = bcd2bin((time >> MVRTC_HOUR_SFT) & MVRTC_HOUR_MSK);
t->tm_wday = bcd2bin((time >> MVRTC_DAY_SFT) & MVRTC_DAY_MSK);
t->tm_wday--;
/* date */
t->tm_mday = bcd2bin((date >> MVRTC_DATE_SFT) & MVRTC_DATE_MSK);
t->tm_mon = bcd2bin((date >> MVRTC_MON_SFT) & MVRTC_MON_MSK);
t->tm_year = bcd2bin((date >> MVRTC_YEAR_SFT) & MVRTC_YEAR_MSK);
t->tm_year += CENTURY * 100;
/* not supported in this RTC */
t->tm_yday = 0;
t->tm_isdst = 0;
return 0;
}
int rtc_set(struct rtc_time *t)
{
u32 time = 0; /* sets hour format bit to zero, 24hr format. */
u32 date = 0;
struct mvrtc_registers *mvrtc_regs;
mvrtc_regs = (struct mvrtc_registers *)KW_RTC_BASE;
/* check that this code isn't 80+ years old ;-) */
if ((t->tm_year / 100) != CENTURY)
printf("Warning: Only century %d supported.\n", CENTURY);
/* time */
time |= (bin2bcd(t->tm_sec) & MVRTC_SEC_MSK) << MVRTC_SEC_SFT;
time |= (bin2bcd(t->tm_min) & MVRTC_MIN_MSK) << MVRTC_MIN_SFT;
time |= (bin2bcd(t->tm_hour) & MVRTC_HOUR_MSK) << MVRTC_HOUR_SFT;
time |= (bin2bcd(t->tm_wday + 1) & MVRTC_DAY_MSK) << MVRTC_DAY_SFT;
/* date */
date |= (bin2bcd(t->tm_mday) & MVRTC_DATE_MSK) << MVRTC_DATE_SFT;
date |= (bin2bcd(t->tm_mon) & MVRTC_MON_MSK) << MVRTC_MON_SFT;
date |= (bin2bcd(t->tm_year % 100) & MVRTC_YEAR_MSK) << MVRTC_YEAR_SFT;
/* write the time register */
writel(time, &mvrtc_regs->time);
/* write the date register */
writel(date, &mvrtc_regs->date);
return 0;
}
void rtc_reset(void)
{
u32 time;
u32 sec;
struct mvrtc_registers *mvrtc_regs;
mvrtc_regs = (struct mvrtc_registers *)KW_RTC_BASE;
/* no init routine for this RTC needed, just check that it's working */
time = readl(&mvrtc_regs->time);
sec = bcd2bin((time >> MVRTC_SEC_SFT) & MVRTC_SEC_MSK);
udelay(1000000);
time = readl(&mvrtc_regs->time);
if (sec == bcd2bin((time >> MVRTC_SEC_SFT) & MVRTC_SEC_MSK))
printf("Error: RTC did not increment.\n");
}
|
1001-study-uboot
|
drivers/rtc/mvrtc.c
|
C
|
gpl3
| 3,648
|
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
#CFLAGS += -DDEBUG
LIB = $(obj)librtc.o
COBJS-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o
COBJS-$(CONFIG_RTC_BFIN) += bfin_rtc.o
COBJS-y += date.o
COBJS-$(CONFIG_RTC_DAVINCI) += davinci.o
COBJS-$(CONFIG_RTC_DS12887) += ds12887.o
COBJS-$(CONFIG_RTC_DS1302) += ds1302.o
COBJS-$(CONFIG_RTC_DS1306) += ds1306.o
COBJS-$(CONFIG_RTC_DS1307) += ds1307.o
COBJS-$(CONFIG_RTC_DS1338) += ds1307.o
COBJS-$(CONFIG_RTC_DS1337) += ds1337.o
COBJS-$(CONFIG_RTC_DS1374) += ds1374.o
COBJS-$(CONFIG_RTC_DS1556) += ds1556.o
COBJS-$(CONFIG_RTC_DS164x) += ds164x.o
COBJS-$(CONFIG_RTC_DS174x) += ds174x.o
COBJS-$(CONFIG_RTC_DS3231) += ds3231.o
COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o
COBJS-$(CONFIG_RTC_M41T11) += m41t11.o
COBJS-$(CONFIG_RTC_M41T60) += m41t60.o
COBJS-$(CONFIG_RTC_M41T62) += m41t62.o
COBJS-$(CONFIG_RTC_M41T94) += m41t94.o
COBJS-$(CONFIG_RTC_M48T35A) += m48t35ax.o
COBJS-$(CONFIG_RTC_MAX6900) += max6900.o
COBJS-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o
COBJS-$(CONFIG_RTC_MC146818) += mc146818.o
COBJS-$(CONFIG_MCFRTC) += mcfrtc.o
COBJS-$(CONFIG_RTC_MK48T59) += mk48t59.o
COBJS-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
COBJS-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
COBJS-$(CONFIG_RTC_MV) += mvrtc.o
COBJS-$(CONFIG_RTC_MXS) += mxsrtc.o
COBJS-$(CONFIG_RTC_PCF8563) += pcf8563.o
COBJS-$(CONFIG_RTC_PL031) += pl031.o
COBJS-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
COBJS-$(CONFIG_RTC_RS5C372A) += rs5c372.o
COBJS-$(CONFIG_RTC_RTC4543) += rtc4543.o
COBJS-$(CONFIG_RTC_RV3029) += rv3029.o
COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
COBJS-$(CONFIG_RTC_S3C44B0) += s3c44b0_rtc.o
COBJS-$(CONFIG_RTC_X1205) += x1205.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/rtc/Makefile
|
Makefile
|
gpl3
| 2,964
|
/*
* ds1302.c - Support for the Dallas Semiconductor DS1302 Timekeeping Chip
*
* Rex G. Feany <rfeany@zumanetworks.com>
*
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
/* GPP Pins */
#define DATA 0x200
#define SCLK 0x400
#define RST 0x800
/* Happy Fun Defines(tm) */
#define RESET rtc_go_low(RST), rtc_go_low(SCLK)
#define N_RESET rtc_go_high(RST), rtc_go_low(SCLK)
#define CLOCK_HIGH rtc_go_high(SCLK)
#define CLOCK_LOW rtc_go_low(SCLK)
#define DATA_HIGH rtc_go_high(DATA)
#define DATA_LOW rtc_go_low(DATA)
#define DATA_READ (GTREGREAD(GPP_VALUE) & DATA)
#undef RTC_DEBUG
#ifdef RTC_DEBUG
# define DPRINTF(x,args...) printf("ds1302: " x , ##args)
static inline void DUMP(const char *ptr, int num)
{
while (num--) printf("%x ", *ptr++);
printf("]\n");
}
#else
# define DPRINTF(x,args...)
# define DUMP(ptr, num)
#endif
/* time data format for DS1302 */
struct ds1302_st
{
unsigned char CH:1; /* clock halt 1=stop 0=start */
unsigned char sec10:3;
unsigned char sec:4;
unsigned char zero0:1;
unsigned char min10:3;
unsigned char min:4;
unsigned char fmt:1; /* 1=12 hour 0=24 hour */
unsigned char zero1:1;
unsigned char hr10:2; /* 10 (0-2) or am/pm (am/pm, 0-1) */
unsigned char hr:4;
unsigned char zero2:2;
unsigned char date10:2;
unsigned char date:4;
unsigned char zero3:3;
unsigned char month10:1;
unsigned char month:4;
unsigned char zero4:5;
unsigned char day:3; /* day of week */
unsigned char year10:4;
unsigned char year:4;
unsigned char WP:1; /* write protect 1=protect 0=unprot */
unsigned char zero5:7;
};
static int ds1302_initted=0;
/* Pin control */
static inline void
rtc_go_high(unsigned int mask)
{
unsigned int f = GTREGREAD(GPP_VALUE) | mask;
GT_REG_WRITE(GPP_VALUE, f);
}
static inline void
rtc_go_low(unsigned int mask)
{
unsigned int f = GTREGREAD(GPP_VALUE) & ~mask;
GT_REG_WRITE(GPP_VALUE, f);
}
static inline void
rtc_go_input(unsigned int mask)
{
unsigned int f = GTREGREAD(GPP_IO_CONTROL) & ~mask;
GT_REG_WRITE(GPP_IO_CONTROL, f);
}
static inline void
rtc_go_output(unsigned int mask)
{
unsigned int f = GTREGREAD(GPP_IO_CONTROL) | mask;
GT_REG_WRITE(GPP_IO_CONTROL, f);
}
/* Access data in RTC */
static void
write_byte(unsigned char b)
{
int i;
unsigned char mask=1;
for(i=0;i<8;i++) {
CLOCK_LOW; /* Lower clock */
(b&mask)?DATA_HIGH:DATA_LOW; /* set data */
udelay(1);
CLOCK_HIGH; /* latch data with rising clock */
udelay(1);
mask=mask<<1;
}
}
static unsigned char
read_byte(void)
{
int i;
unsigned char mask=1;
unsigned char b=0;
for(i=0;i<8;i++) {
CLOCK_LOW;
udelay(1);
if (DATA_READ) b|=mask; /* if this bit is high, set in b */
CLOCK_HIGH; /* clock out next bit */
udelay(1);
mask=mask<<1;
}
return b;
}
static void
read_ser_drv(unsigned char addr, unsigned char *buf, int count)
{
int i;
#ifdef RTC_DEBUG
char *foo = buf;
#endif
DPRINTF("READ 0x%x bytes @ 0x%x [ ", count, addr);
addr|=1; /* READ */
N_RESET;
udelay(4);
write_byte(addr);
rtc_go_input(DATA); /* Put gpp pin into input mode */
udelay(1);
for(i=0;i<count;i++) *(buf++)=read_byte();
RESET;
rtc_go_output(DATA);/* Reset gpp for output */
udelay(4);
DUMP(foo, count);
}
static void
write_ser_drv(unsigned char addr, unsigned char *buf, int count)
{
int i;
DPRINTF("WRITE 0x%x bytes @ 0x%x [ ", count, addr);
DUMP(buf, count);
addr&=~1; /* WRITE */
N_RESET;
udelay(4);
write_byte(addr);
for(i=0;i<count;i++) write_byte(*(buf++));
RESET;
udelay(4);
}
void
rtc_init(void)
{
struct ds1302_st bbclk;
unsigned char b;
int mod;
DPRINTF("init\n");
rtc_go_output(DATA|SCLK|RST);
/* disable write protect */
b = 0;
write_ser_drv(0x8e,&b,1);
/* enable trickle */
b = 0xa5; /* 1010.0101 */
write_ser_drv(0x90,&b,1);
/* read burst */
read_ser_drv(0xbe, (unsigned char *)&bbclk, 8);
/* Sanity checks */
mod = 0;
if (bbclk.CH) {
printf("ds1302: Clock was halted, starting clock\n");
bbclk.CH=0;
mod=1;
}
if (bbclk.fmt) {
printf("ds1302: Clock was in 12 hour mode, fixing\n");
bbclk.fmt=0;
mod=1;
}
if (bbclk.year>9) {
printf("ds1302: Year was corrupted, fixing\n");
bbclk.year10=100/10; /* 2000 - why not? ;) */
bbclk.year=0;
mod=1;
}
/* Write out the changes if needed */
if (mod) {
/* enable write protect */
bbclk.WP = 1;
write_ser_drv(0xbe,(unsigned char *)&bbclk,8);
} else {
/* Else just turn write protect on */
b = 0x80;
write_ser_drv(0x8e,&b,1);
}
DPRINTF("init done\n");
ds1302_initted=1;
}
void
rtc_reset(void)
{
if(!ds1302_initted) rtc_init();
/* TODO */
}
int
rtc_get(struct rtc_time *tmp)
{
int rel = 0;
struct ds1302_st bbclk;
if(!ds1302_initted) rtc_init();
read_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* read burst */
if (bbclk.CH) {
printf("ds1302: rtc_get: Clock was halted, clock probably "
"corrupt\n");
rel = -1;
}
tmp->tm_sec=10*bbclk.sec10+bbclk.sec;
tmp->tm_min=10*bbclk.min10+bbclk.min;
tmp->tm_hour=10*bbclk.hr10+bbclk.hr;
tmp->tm_wday=bbclk.day;
tmp->tm_mday=10*bbclk.date10+bbclk.date;
tmp->tm_mon=10*bbclk.month10+bbclk.month;
tmp->tm_year=10*bbclk.year10+bbclk.year + 1900;
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
DPRINTF("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
return rel;
}
int rtc_set(struct rtc_time *tmp)
{
struct ds1302_st bbclk;
unsigned char b=0;
if(!ds1302_initted) rtc_init();
DPRINTF("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
memset(&bbclk,0,sizeof(bbclk));
bbclk.CH=0; /* dont halt */
bbclk.WP=1; /* write protect when we're done */
bbclk.sec10=tmp->tm_sec/10;
bbclk.sec=tmp->tm_sec%10;
bbclk.min10=tmp->tm_min/10;
bbclk.min=tmp->tm_min%10;
bbclk.hr10=tmp->tm_hour/10;
bbclk.hr=tmp->tm_hour%10;
bbclk.day=tmp->tm_wday;
bbclk.date10=tmp->tm_mday/10;
bbclk.date=tmp->tm_mday%10;
bbclk.month10=tmp->tm_mon/10;
bbclk.month=tmp->tm_mon%10;
tmp->tm_year -= 1900;
bbclk.year10=tmp->tm_year/10;
bbclk.year=tmp->tm_year%10;
write_ser_drv(0x8e,&b,1); /* disable write protect */
write_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* write burst */
return 0;
}
#endif
|
1001-study-uboot
|
drivers/rtc/ds1302.c
|
C
|
gpl3
| 6,372
|
/*
* (C) Copyright 2002
* Andrew May, Viasat Inc, amay@viasat.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* M41T11 Serial Access Timekeeper(R) SRAM
* can you believe a trademark on that?
*/
/* #define DEBUG 1 */
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
/*
I Don't have an example config file but this
is what should be done.
#define CONFIG_RTC_M41T11 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#if 0
#define CONFIG_SYS_M41T11_EXT_CENTURY_DATA
#else
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
#endif
*/
#if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE)
/* ------------------------------------------------------------------------- */
/*
these are simple defines for the chip local to here so they aren't too
verbose
DAY/DATE aren't nice but that is how they are on the data sheet
*/
#define RTC_SEC_ADDR 0x0
#define RTC_MIN_ADDR 0x1
#define RTC_HOUR_ADDR 0x2
#define RTC_DAY_ADDR 0x3
#define RTC_DATE_ADDR 0x4
#define RTC_MONTH_ADDR 0x5
#define RTC_YEARS_ADDR 0x6
#define RTC_REG_CNT 7
#define RTC_CONTROL_ADDR 0x7
#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA
#define REG_CNT (RTC_REG_CNT+1)
/*
you only get 00-99 for the year we will asume you
want from the year 2000 if you don't set the config
*/
#ifndef CONFIG_SYS_M41T11_BASE_YEAR
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
#endif
#else
/* we will store extra year info in byte 9*/
#define M41T11_YEAR_DATA 0x8
#define M41T11_YEAR_SIZE 1
#define REG_CNT (RTC_REG_CNT+1+M41T11_YEAR_SIZE)
#endif
#define M41T11_STORAGE_SZ (64-REG_CNT)
int rtc_get (struct rtc_time *tmp)
{
int rel = 0;
uchar data[RTC_REG_CNT];
i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT);
if( data[RTC_SEC_ADDR] & 0x80 ){
printf( "m41t11 RTC Clock stopped!!!\n" );
rel = -1;
}
tmp->tm_sec = bcd2bin (data[RTC_SEC_ADDR] & 0x7F);
tmp->tm_min = bcd2bin (data[RTC_MIN_ADDR] & 0x7F);
tmp->tm_hour = bcd2bin (data[RTC_HOUR_ADDR] & 0x3F);
tmp->tm_mday = bcd2bin (data[RTC_DATE_ADDR] & 0x3F);
tmp->tm_mon = bcd2bin (data[RTC_MONTH_ADDR]& 0x1F);
#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA
tmp->tm_year = CONFIG_SYS_M41T11_BASE_YEAR
+ bcd2bin(data[RTC_YEARS_ADDR])
+ ((data[RTC_HOUR_ADDR]&0x40) ? 100 : 0);
#else
{
unsigned char cent;
i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE);
if( !(data[RTC_HOUR_ADDR] & 0x80) ){
printf( "m41t11 RTC: cann't keep track of years without CEB set\n" );
rel = -1;
}
if( (cent & 0x1) != ((data[RTC_HOUR_ADDR]&0x40)>>7) ){
/*century flip store off new year*/
cent += 1;
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE);
}
tmp->tm_year =((int)cent*100)+bcd2bin(data[RTC_YEARS_ADDR]);
}
#endif
tmp->tm_wday = bcd2bin (data[RTC_DAY_ADDR] & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return rel;
}
int rtc_set (struct rtc_time *tmp)
{
uchar data[RTC_REG_CNT];
debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
data[RTC_SEC_ADDR] = bin2bcd(tmp->tm_sec) & 0x7F;/*just in case*/
data[RTC_MIN_ADDR] = bin2bcd(tmp->tm_min);
data[RTC_HOUR_ADDR] = bin2bcd(tmp->tm_hour) & 0x3F;/*handle cent stuff later*/
data[RTC_DATE_ADDR] = bin2bcd(tmp->tm_mday) & 0x3F;
data[RTC_MONTH_ADDR] = bin2bcd(tmp->tm_mon);
data[RTC_DAY_ADDR] = bin2bcd(tmp->tm_wday) & 0x07;
data[RTC_HOUR_ADDR] |= 0x80;/*we will always use CEB*/
data[RTC_YEARS_ADDR] = bin2bcd(tmp->tm_year%100);/*same thing either way*/
#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA
if( ((tmp->tm_year - CONFIG_SYS_M41T11_BASE_YEAR) > 200) ||
(tmp->tm_year < CONFIG_SYS_M41T11_BASE_YEAR) ){
printf( "m41t11 RTC setting year out of range!!need recompile\n" );
}
data[RTC_HOUR_ADDR] |= (tmp->tm_year - CONFIG_SYS_M41T11_BASE_YEAR) > 100 ? 0x40 : 0;
#else
{
unsigned char cent;
cent = tmp->tm_year ? tmp->tm_year / 100 : 0;
data[RTC_HOUR_ADDR] |= (cent & 0x1) ? 0x40 : 0;
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE);
}
#endif
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT);
return 0;
}
void rtc_reset (void)
{
unsigned char val;
/* clear all control & status registers */
i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, 1);
val = val & 0x7F;/*make sure we are running*/
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, RTC_REG_CNT);
i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1);
val = val & 0x3F;/*turn off freq test keep calibration*/
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1);
}
#endif
|
1001-study-uboot
|
drivers/rtc/m41t11.c
|
C
|
gpl3
| 5,615
|
/*
* (C) Copyright 2001, 2002, 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Keith Outwater, keith_outwater@mvis.com`
* Steven Scholz, steven.scholz@imc-berlin.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
* DS1307 and DS1338 Real Time Clock (RTC).
*
* based on ds1337.c
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
#ifdef DEBUG_RTC
#define DEBUGR(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGR(fmt,args...)
#endif
/*---------------------------------------------------------------------*/
#ifndef CONFIG_SYS_I2C_RTC_ADDR
# define CONFIG_SYS_I2C_RTC_ADDR 0x68
#endif
#if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000)
# error The DS1307 is specified only up to 100kHz!
#endif
/*
* RTC register addresses
*/
#define RTC_SEC_REG_ADDR 0x00
#define RTC_MIN_REG_ADDR 0x01
#define RTC_HR_REG_ADDR 0x02
#define RTC_DAY_REG_ADDR 0x03
#define RTC_DATE_REG_ADDR 0x04
#define RTC_MON_REG_ADDR 0x05
#define RTC_YR_REG_ADDR 0x06
#define RTC_CTL_REG_ADDR 0x07
#define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */
#define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */
#define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */
#define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */
#define RTC_CTL_BIT_OUT 0x80 /* Output Control */
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
/*
* Get the current time from the RTC
*/
int rtc_get (struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon, year;
sec = rtc_read (RTC_SEC_REG_ADDR);
min = rtc_read (RTC_MIN_REG_ADDR);
hour = rtc_read (RTC_HR_REG_ADDR);
wday = rtc_read (RTC_DAY_REG_ADDR);
mday = rtc_read (RTC_DATE_REG_ADDR);
mon = rtc_read (RTC_MON_REG_ADDR);
year = rtc_read (RTC_YR_REG_ADDR);
DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday, hour, min, sec);
if (sec & RTC_SEC_BIT_CH) {
printf ("### Warning: RTC oscillator has stopped\n");
/* clear the CH flag */
rtc_write (RTC_SEC_REG_ADDR,
rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH);
rel = -1;
}
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000);
tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return rel;
}
/*
* Set the RTC
*/
int rtc_set (struct rtc_time *tmp)
{
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
return 0;
}
/*
* Reset the RTC. We setting the date back to 1970-01-01.
* We also enable the oscillator output on the SQW/OUT pin and program
* it for 32,768 Hz output. Note that according to the datasheet, turning
* on the square wave output increases the current drain on the backup
* battery to something between 480nA and 800nA.
*/
void rtc_reset (void)
{
struct rtc_time tmp;
rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */
rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0);
tmp.tm_year = 1970;
tmp.tm_mon = 1;
tmp.tm_mday= 1;
tmp.tm_hour = 0;
tmp.tm_min = 0;
tmp.tm_sec = 0;
rtc_set(&tmp);
printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
return;
}
/*
* Helper functions
*/
static
uchar rtc_read (uchar reg)
{
return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
#endif
|
1001-study-uboot
|
drivers/rtc/ds1307.c
|
C
|
gpl3
| 5,462
|
/*
* (C) Copyright 2002
* ARIO Data Networks, Inc. dchiu@ariodata.com
*
* modified for DS164x:
* The LEOX team <team@leox.org>, http://www.leox.org
*
* Based on MontaVista DS1743 code and U-Boot mc146818 code
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the DS164x RTC
*/
/* #define RTC_DEBUG */
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
static uchar rtc_read(unsigned int addr );
static void rtc_write(unsigned int addr, uchar val);
#define RTC_EPOCH 2000 /* century */
/*
* DS164x registers layout
*/
#define RTC_BASE ( CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE )
#define RTC_YEAR ( RTC_BASE + 0x07 )
#define RTC_MONTH ( RTC_BASE + 0x06 )
#define RTC_DAY_OF_MONTH ( RTC_BASE + 0x05 )
#define RTC_DAY_OF_WEEK ( RTC_BASE + 0x04 )
#define RTC_HOURS ( RTC_BASE + 0x03 )
#define RTC_MINUTES ( RTC_BASE + 0x02 )
#define RTC_SECONDS ( RTC_BASE + 0x01 )
#define RTC_CONTROL ( RTC_BASE + 0x00 )
#define RTC_CONTROLA RTC_CONTROL /* W=bit6, R=bit5 */
#define RTC_CA_WRITE 0x80
#define RTC_CA_READ 0x40
#define RTC_CONTROLB RTC_SECONDS /* OSC=bit7 */
#define RTC_CB_OSC_DISABLE 0x80
#define RTC_CONTROLC RTC_DAY_OF_WEEK /* FT=bit6 */
#define RTC_CC_FREQ_TEST 0x40
/* ------------------------------------------------------------------------- */
int rtc_get( struct rtc_time *tmp )
{
uchar sec, min, hour;
uchar mday, wday, mon, year;
uchar reg_a;
reg_a = rtc_read( RTC_CONTROLA );
/* lock clock registers for read */
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
sec = rtc_read( RTC_SECONDS );
min = rtc_read( RTC_MINUTES );
hour = rtc_read( RTC_HOURS );
mday = rtc_read( RTC_DAY_OF_MONTH );
wday = rtc_read( RTC_DAY_OF_WEEK );
mon = rtc_read( RTC_MONTH );
year = rtc_read( RTC_YEAR );
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
#ifdef RTC_DEBUG
printf( "Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday,
hour, min, sec );
#endif
tmp->tm_sec = bcd2bin( sec & 0x7F );
tmp->tm_min = bcd2bin( min & 0x7F );
tmp->tm_hour = bcd2bin( hour & 0x3F );
tmp->tm_mday = bcd2bin( mday & 0x3F );
tmp->tm_mon = bcd2bin( mon & 0x1F );
tmp->tm_wday = bcd2bin( wday & 0x07 );
/* glue year in century (2000) */
tmp->tm_year = bcd2bin( year ) + RTC_EPOCH;
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
#ifdef RTC_DEBUG
printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
#endif
return 0;
}
int rtc_set( struct rtc_time *tmp )
{
uchar reg_a;
#ifdef RTC_DEBUG
printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
/* lock clock registers for write */
reg_a = rtc_read( RTC_CONTROLA );
rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
/* break year in century */
rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
/* unlock clock registers after read */
rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
return 0;
}
void rtc_reset (void)
{
uchar reg_a, reg_b;
reg_a = rtc_read( RTC_CONTROLA );
reg_b = rtc_read( RTC_CONTROLB );
if ( reg_b & RTC_CB_OSC_DISABLE )
{
printf( "real-time-clock was stopped. Now starting...\n" );
reg_a |= RTC_CA_WRITE;
reg_b &= ~RTC_CB_OSC_DISABLE;
rtc_write( RTC_CONTROLA, reg_a );
rtc_write( RTC_CONTROLB, reg_b );
}
/* make sure read/write clock register bits are cleared */
reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
rtc_write( RTC_CONTROLA, reg_a );
}
/* ------------------------------------------------------------------------- */
static uchar rtc_read( unsigned int addr )
{
uchar val = *(volatile unsigned char*)(addr);
#ifdef RTC_DEBUG
printf( "rtc_read: %x:%x\n", addr, val );
#endif
return( val );
}
static void rtc_write( unsigned int addr, uchar val )
{
#ifdef RTC_DEBUG
printf( "rtc_write: %x:%x\n", addr, val );
#endif
*(volatile unsigned char*)(addr) = val;
}
#endif
|
1001-study-uboot
|
drivers/rtc/ds164x.c
|
C
|
gpl3
| 5,283
|
/*
* (C) Copyright 2003
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the DS12887 RTC
*/
#undef RTC_DEBUG
#include <common.h>
#include <command.h>
#include <config.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
#define RTC_SECONDS 0x00
#define RTC_SECONDS_ALARM 0x01
#define RTC_MINUTES 0x02
#define RTC_MINUTES_ALARM 0x03
#define RTC_HOURS 0x04
#define RTC_HOURS_ALARM 0x05
#define RTC_DAY_OF_WEEK 0x06
#define RTC_DATE_OF_MONTH 0x07
#define RTC_MONTH 0x08
#define RTC_YEAR 0x09
#define RTC_CONTROL_A 0x0A
#define RTC_CONTROL_B 0x0B
#define RTC_CONTROL_C 0x0C
#define RTC_CONTROL_D 0x0D
#define RTC_CA_UIP 0x80
#define RTC_CB_DM 0x04
#define RTC_CB_24_12 0x02
#define RTC_CB_SET 0x80
#if defined(CONFIG_ATC)
static uchar rtc_read (uchar reg)
{
uchar val;
*(volatile unsigned char*)(RTC_PORT_ADDR) = reg;
__asm__ __volatile__ ("sync");
val = *(volatile unsigned char*)(RTC_PORT_DATA);
return (val);
}
static void rtc_write (uchar reg, uchar val)
{
*(volatile unsigned char*)(RTC_PORT_ADDR) = reg;
__asm__ __volatile__ ("sync");
*(volatile unsigned char*)(RTC_PORT_DATA) = val;
__asm__ __volatile__ ("sync");
}
#else
# error Board specific rtc access functions should be supplied
#endif
int rtc_get (struct rtc_time *tmp)
{
uchar sec, min, hour, mday, wday, mon, year;
/* check if rtc is available for access */
while( rtc_read(RTC_CONTROL_A) & RTC_CA_UIP)
;
sec = rtc_read(RTC_SECONDS);
min = rtc_read(RTC_MINUTES);
hour = rtc_read(RTC_HOURS);
mday = rtc_read(RTC_DATE_OF_MONTH);
wday = rtc_read(RTC_DAY_OF_WEEK);
mon = rtc_read(RTC_MONTH);
year = rtc_read(RTC_YEAR);
#ifdef RTC_DEBUG
printf( "Get RTC year: %d; mon: %d; mday: %d; wday: %d; "
"hr: %d; min: %d; sec: %d\n",
year, mon, mday, wday, hour, min, sec );
printf ( "Alarms: hour: %02x min: %02x sec: %02x\n",
rtc_read (RTC_HOURS_ALARM),
rtc_read (RTC_MINUTES_ALARM),
rtc_read (RTC_SECONDS_ALARM) );
#endif
if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM))
{ /* Information is in BCD format */
printf(" Get: Convert BSD to BIN\n");
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year);
tmp->tm_wday = bcd2bin (wday & 0x07);
}
else
{
tmp->tm_sec = sec & 0x7F;
tmp->tm_min = min & 0x7F;
tmp->tm_hour = hour & 0x3F;
tmp->tm_mday = mday & 0x3F;
tmp->tm_mon = mon & 0x1F;
tmp->tm_year = year;
tmp->tm_wday = wday & 0x07;
}
if(tmp->tm_year<70)
tmp->tm_year+=2000;
else
tmp->tm_year+=1900;
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
#ifdef RTC_DEBUG
printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
uchar save_ctrl_b;
uchar sec, min, hour, mday, wday, mon, year;
#ifdef RTC_DEBUG
printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
if( !(rtc_read(RTC_CONTROL_B) & RTC_CB_DM))
{ /* Information is in BCD format */
year = bin2bcd(tmp->tm_year % 100);
mon = bin2bcd(tmp->tm_mon);
wday = bin2bcd(tmp->tm_wday);
mday = bin2bcd(tmp->tm_mday);
hour = bin2bcd(tmp->tm_hour);
min = bin2bcd(tmp->tm_min);
sec = bin2bcd(tmp->tm_sec);
}
else
{
year = tmp->tm_year % 100;
mon = tmp->tm_mon;
wday = tmp->tm_wday;
mday = tmp->tm_mday;
hour = tmp->tm_hour;
min = tmp->tm_min;
sec = tmp->tm_sec;
}
/* disables the RTC to update the regs */
save_ctrl_b = rtc_read(RTC_CONTROL_B);
save_ctrl_b |= RTC_CB_SET;
rtc_write(RTC_CONTROL_B, save_ctrl_b);
rtc_write (RTC_YEAR, year);
rtc_write (RTC_MONTH, mon);
rtc_write (RTC_DAY_OF_WEEK, wday);
rtc_write (RTC_DATE_OF_MONTH, mday);
rtc_write (RTC_HOURS, hour);
rtc_write (RTC_MINUTES, min);
rtc_write (RTC_SECONDS, sec);
/* enables the RTC to update the regs */
save_ctrl_b &= ~RTC_CB_SET;
rtc_write(RTC_CONTROL_B, save_ctrl_b);
return 0;
}
void rtc_reset (void)
{
struct rtc_time tmp;
uchar ctrl_rg;
ctrl_rg = RTC_CB_SET;
rtc_write(RTC_CONTROL_B,ctrl_rg);
tmp.tm_year = 1970 % 100;
tmp.tm_mon = 1;
tmp.tm_mday= 1;
tmp.tm_hour = 0;
tmp.tm_min = 0;
tmp.tm_sec = 0;
#ifdef RTC_DEBUG
printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
#endif
ctrl_rg = RTC_CB_SET | RTC_CB_24_12 | RTC_CB_DM;
rtc_write(RTC_CONTROL_B,ctrl_rg);
rtc_set(&tmp);
rtc_write(RTC_HOURS_ALARM, 0),
rtc_write(RTC_MINUTES_ALARM, 0),
rtc_write(RTC_SECONDS_ALARM, 0);
ctrl_rg = RTC_CB_24_12 | RTC_CB_DM;
rtc_write(RTC_CONTROL_B,ctrl_rg);
}
#endif
|
1001-study-uboot
|
drivers/rtc/ds12887.c
|
C
|
gpl3
| 5,582
|
/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the MK48T59 RTC
*/
#undef RTC_DEBUG
#include <common.h>
#include <command.h>
#include <config.h>
#include <rtc.h>
#include <mk48t59.h>
#if defined(CONFIG_BAB7xx)
static uchar rtc_read (short reg)
{
out8(RTC_PORT_ADDR0, reg & 0xFF);
out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF);
return in8(RTC_PORT_DATA);
}
static void rtc_write (short reg, uchar val)
{
out8(RTC_PORT_ADDR0, reg & 0xFF);
out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF);
out8(RTC_PORT_DATA, val);
}
#elif defined(CONFIG_PCIPPC2)
#include "../board/pcippc2/pcippc2.h"
static uchar rtc_read (short reg)
{
return in8(RTC(reg));
}
static void rtc_write (short reg, uchar val)
{
out8(RTC(reg),val);
}
#elif defined(CONFIG_EVAL5200)
static uchar rtc_read (short reg)
{
return in8(RTC(reg));
}
static void rtc_write (short reg, uchar val)
{
out8(RTC(reg),val);
}
#else
# error Board specific rtc access functions should be supplied
#endif
/* ------------------------------------------------------------------------- */
void *nvram_read(void *dest, const short src, size_t count)
{
uchar *d = (uchar *) dest;
short s = src;
while (count--)
*d++ = rtc_read(s++);
return dest;
}
void nvram_write(short dest, const void *src, size_t count)
{
short d = dest;
uchar *s = (uchar *) src;
while (count--)
rtc_write(d++, *s++);
}
#if defined(CONFIG_CMD_DATE)
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
{
uchar save_ctrl_a;
uchar sec, min, hour, mday, wday, mon, year;
/* Simple: freeze the clock, read it and allow updates again */
save_ctrl_a = rtc_read(RTC_CONTROLA);
/* Set the register to read the value. */
save_ctrl_a |= RTC_CA_READ;
rtc_write(RTC_CONTROLA, save_ctrl_a);
sec = rtc_read (RTC_SECONDS);
min = rtc_read (RTC_MINUTES);
hour = rtc_read (RTC_HOURS);
mday = rtc_read (RTC_DAY_OF_MONTH);
wday = rtc_read (RTC_DAY_OF_WEEK);
mon = rtc_read (RTC_MONTH);
year = rtc_read (RTC_YEAR);
/* re-enable update */
save_ctrl_a &= ~RTC_CA_READ;
rtc_write(RTC_CONTROLA, save_ctrl_a);
#ifdef RTC_DEBUG
printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday,
hour, min, sec );
#endif
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year);
tmp->tm_wday = bcd2bin (wday & 0x07);
if(tmp->tm_year<70)
tmp->tm_year+=2000;
else
tmp->tm_year+=1900;
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
#ifdef RTC_DEBUG
printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
uchar save_ctrl_a;
#ifdef RTC_DEBUG
printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
save_ctrl_a = rtc_read(RTC_CONTROLA);
save_ctrl_a |= RTC_CA_WRITE;
rtc_write(RTC_CONTROLA, save_ctrl_a); /* disables the RTC to update the regs */
rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100));
rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon));
rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
rtc_write (RTC_DAY_OF_MONTH, bin2bcd(tmp->tm_mday));
rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour));
rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min ));
rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec ));
save_ctrl_a &= ~RTC_CA_WRITE;
rtc_write(RTC_CONTROLA, save_ctrl_a); /* enables the RTC to update the regs */
return 0;
}
void rtc_reset (void)
{
uchar control_b;
/*
* Start oscillator here.
*/
control_b = rtc_read(RTC_CONTROLB);
control_b &= ~RTC_CB_STOP;
rtc_write(RTC_CONTROLB, control_b);
}
void rtc_set_watchdog(short multi, short res)
{
uchar wd_value;
wd_value = RTC_WDS | ((multi & 0x1F) << 2) | (res & 0x3);
rtc_write(RTC_WATCHDOG, wd_value);
}
#endif
|
1001-study-uboot
|
drivers/rtc/mk48t59.c
|
C
|
gpl3
| 4,993
|
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for Philips PCF8563 RTC
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE) || defined(CONFIG_TIMESTAMP)
#define FEBRUARY 2
#define STARTOFTIME 1970
#define SECDAY 86400L
#define SECYR (SECDAY * 365)
#define leapyear(year) ((year) % 4 == 0)
#define days_in_year(a) (leapyear(a) ? 366 : 365)
#define days_in_month(a) (month_days[(a) - 1])
static int month_days[12] = {
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
};
/*
* This only works for the Gregorian calendar - i.e. after 1752 (in the UK)
*/
void GregorianDay(struct rtc_time * tm)
{
int leapsToDate;
int lastYear;
int day;
int MonthOffset[] = { 0,31,59,90,120,151,181,212,243,273,304,334 };
lastYear=tm->tm_year-1;
/*
* Number of leap corrections to apply up to end of last year
*/
leapsToDate = lastYear/4 - lastYear/100 + lastYear/400;
/*
* This year is a leap year if it is divisible by 4 except when it is
* divisible by 100 unless it is divisible by 400
*
* e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 will be
*/
if((tm->tm_year%4==0) &&
((tm->tm_year%100!=0) || (tm->tm_year%400==0)) &&
(tm->tm_mon>2)) {
/*
* We are past Feb. 29 in a leap year
*/
day=1;
} else {
day=0;
}
day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] + tm->tm_mday;
tm->tm_wday=day%7;
}
void to_tm(int tim, struct rtc_time * tm)
{
register int i;
register long hms, day;
day = tim / SECDAY;
hms = tim % SECDAY;
/* Hours, minutes, seconds are easy */
tm->tm_hour = hms / 3600;
tm->tm_min = (hms % 3600) / 60;
tm->tm_sec = (hms % 3600) % 60;
/* Number of years in days */
for (i = STARTOFTIME; day >= days_in_year(i); i++) {
day -= days_in_year(i);
}
tm->tm_year = i;
/* Number of months in days left */
if (leapyear(tm->tm_year)) {
days_in_month(FEBRUARY) = 29;
}
for (i = 1; day >= days_in_month(i); i++) {
day -= days_in_month(i);
}
days_in_month(FEBRUARY) = 28;
tm->tm_mon = i;
/* Days are what is left over (+1) from all that. */
tm->tm_mday = day + 1;
/*
* Determine the day of week
*/
GregorianDay(tm);
}
/* Converts Gregorian date to seconds since 1970-01-01 00:00:00.
* Assumes input in normal date format, i.e. 1980-12-31 23:59:59
* => year=1980, mon=12, day=31, hour=23, min=59, sec=59.
*
* [For the Julian calendar (which was used in Russia before 1917,
* Britain & colonies before 1752, anywhere else before 1582,
* and is still in use by some communities) leave out the
* -year/100+year/400 terms, and add 10.]
*
* This algorithm was first published by Gauss (I think).
*
* WARNING: this function will overflow on 2106-02-07 06:28:16 on
* machines were long is 32-bit! (However, as time_t is signed, we
* will already get problems at other places on 2038-01-19 03:14:08)
*/
unsigned long
mktime (unsigned int year, unsigned int mon,
unsigned int day, unsigned int hour,
unsigned int min, unsigned int sec)
{
if (0 >= (int) (mon -= 2)) { /* 1..12 -> 11,12,1..10 */
mon += 12; /* Puts Feb last since it has leap day */
year -= 1;
}
return (((
(unsigned long) (year/4 - year/100 + year/400 + 367*mon/12 + day) +
year*365 - 719499
)*24 + hour /* now have hours */
)*60 + min /* now have minutes */
)*60 + sec; /* finally seconds */
}
#endif
|
1001-study-uboot
|
drivers/rtc/date.c
|
C
|
gpl3
| 4,213
|
/*
* (C) Copyright 2007
* Larry Johnson, lrj@acm.org
*
* based on rtc/m41t11.c which is ...
*
* (C) Copyright 2002
* Andrew May, Viasat Inc, amay@viasat.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* STMicroelectronics M41T60 serial access real-time clock
*/
/* #define DEBUG 1 */
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_SYS_I2C_RTC_ADDR) && defined(CONFIG_CMD_DATE)
/*
* Convert between century and "century bits" (CB1 and CB0). These routines
* assume years are in the range 1900 - 2299.
*/
static unsigned char year2cb(unsigned const year)
{
if (year < 1900 || year >= 2300)
printf("M41T60 RTC: year %d out of range\n", year);
return (year / 100) & 0x3;
}
static unsigned cb2year(unsigned const cb)
{
return 1900 + 100 * ((cb + 1) & 0x3);
}
/*
* These are simple defines for the chip local to here so they aren't too
* verbose. DAY/DATE aren't nice but that is how they are on the data sheet.
*/
#define RTC_SEC 0x0
#define RTC_MIN 0x1
#define RTC_HOUR 0x2
#define RTC_DAY 0x3
#define RTC_DATE 0x4
#define RTC_MONTH 0x5
#define RTC_YEAR 0x6
#define RTC_REG_CNT 7
#define RTC_CTRL 0x7
#if defined(DEBUG)
static void rtc_dump(char const *const label)
{
uchar data[8];
if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
printf("I2C read failed in rtc_dump()\n");
return;
}
printf("RTC dump %s: %02X-%02X-%02X-%02X-%02X-%02X-%02X-%02X\n",
label, data[0], data[1], data[2], data[3],
data[4], data[5], data[6], data[7]);
}
#else
#define rtc_dump(label)
#endif
static uchar *rtc_validate(void)
{
/*
* This routine uses the OUT bit and the validity of the time values to
* determine whether there has been an initial power-up since the last
* time the routine was run. It assumes that the OUT bit is not being
* used for any other purpose.
*/
static const uchar daysInMonth[0x13] = {
0x00, 0x31, 0x29, 0x31, 0x30, 0x31, 0x30, 0x31,
0x31, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x31, 0x30, 0x31
};
static uchar data[8];
uchar min, date, month, years;
rtc_dump("begin validate");
if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
printf("I2C read failed in rtc_validate()\n");
return 0;
}
/*
* If the OUT bit is "1", there has been a loss of power, so stop the
* oscillator so it can be "kick-started" as per data sheet.
*/
if (0x00 != (data[RTC_CTRL] & 0x80)) {
printf("M41T60 RTC clock lost power.\n");
data[RTC_SEC] = 0x80;
if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) {
printf("I2C write failed in rtc_validate()\n");
return 0;
}
}
/*
* If the oscillator is stopped or the date is invalid, then reset the
* OUT bit to "0", reset the date registers, and start the oscillator.
*/
min = data[RTC_MIN] & 0x7F;
date = data[RTC_DATE];
month = data[RTC_MONTH] & 0x3F;
years = data[RTC_YEAR];
if (0x59 < data[RTC_SEC] || 0x09 < (data[RTC_SEC] & 0x0F) ||
0x59 < min || 0x09 < (min & 0x0F) ||
0x23 < data[RTC_HOUR] || 0x09 < (data[RTC_HOUR] & 0x0F) ||
0x07 < data[RTC_DAY] || 0x00 == data[RTC_DAY] ||
0x12 < month ||
0x99 < years || 0x09 < (years & 0x0F) ||
daysInMonth[month] < date || 0x09 < (date & 0x0F) || 0x00 == date ||
(0x29 == date && 0x02 == month &&
((0x00 != (years & 0x03)) ||
(0x00 == years && 0x00 != (data[RTC_MONTH] & 0xC0))))) {
printf("Resetting M41T60 RTC clock.\n");
/*
* Set to 00:00:00 1900-01-01 (Monday)
*/
data[RTC_SEC] = 0x00;
data[RTC_MIN] &= 0x80; /* preserve OFIE bit */
data[RTC_HOUR] = 0x00;
data[RTC_DAY] = 0x02;
data[RTC_DATE] = 0x01;
data[RTC_MONTH] = 0xC1;
data[RTC_YEAR] = 0x00;
data[RTC_CTRL] &= 0x7F; /* reset OUT bit */
if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) {
printf("I2C write failed in rtc_validate()\n");
return 0;
}
}
return data;
}
int rtc_get(struct rtc_time *tmp)
{
uchar const *const data = rtc_validate();
if (!data)
return -1;
tmp->tm_sec = bcd2bin(data[RTC_SEC] & 0x7F);
tmp->tm_min = bcd2bin(data[RTC_MIN] & 0x7F);
tmp->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3F);
tmp->tm_mday = bcd2bin(data[RTC_DATE] & 0x3F);
tmp->tm_mon = bcd2bin(data[RTC_MONTH] & 0x1F);
tmp->tm_year = cb2year(data[RTC_MONTH] >> 6) + bcd2bin(data[RTC_YEAR]);
tmp->tm_wday = bcd2bin(data[RTC_DAY] & 0x07) - 1;
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return 0;
}
int rtc_set(struct rtc_time *tmp)
{
uchar *const data = rtc_validate();
if (!data)
return -1;
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
data[RTC_SEC] = (data[RTC_SEC] & 0x80) | (bin2bcd(tmp->tm_sec) & 0x7F);
data[RTC_MIN] = (data[RTC_MIN] & 0X80) | (bin2bcd(tmp->tm_min) & 0X7F);
data[RTC_HOUR] = bin2bcd(tmp->tm_hour) & 0x3F;
data[RTC_DATE] = bin2bcd(tmp->tm_mday) & 0x3F;
data[RTC_MONTH] = bin2bcd(tmp->tm_mon) & 0x1F;
data[RTC_YEAR] = bin2bcd(tmp->tm_year % 100);
data[RTC_MONTH] |= year2cb(tmp->tm_year) << 6;
data[RTC_DAY] = bin2bcd(tmp->tm_wday + 1) & 0x07;
if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) {
printf("I2C write failed in rtc_set()\n");
return -1;
}
return 0;
}
void rtc_reset(void)
{
uchar *const data = rtc_validate();
char const *const s = getenv("rtccal");
if (!data)
return;
rtc_dump("begin reset");
/*
* If environmental variable "rtccal" is present, it must be a hex value
* between 0x00 and 0x3F, inclusive. The five least-significan bits
* represent the calibration magnitude, and the sixth bit the sign bit.
* If these do not match the contents of the hardware register, that
* register is updated. The value 0x00 imples no correction. Consult
* the M41T60 documentation for further details.
*/
if (s) {
unsigned long const l = simple_strtoul(s, 0, 16);
if (l <= 0x3F) {
if ((data[RTC_CTRL] & 0x3F) != l) {
printf("Setting RTC calibration to 0x%02lX\n",
l);
data[RTC_CTRL] &= 0xC0;
data[RTC_CTRL] |= (uchar) l;
}
} else
printf("environment parameter \"rtccal\" not valid: "
"ignoring\n");
}
/*
* Turn off frequency test.
*/
data[RTC_CTRL] &= 0xBF;
if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) {
printf("I2C write failed in rtc_reset()\n");
return;
}
rtc_dump("end reset");
}
#endif /* CONFIG_RTC_M41T60 && CONFIG_SYS_I2C_RTC_ADDR && CONFIG_CMD_DATE */
|
1001-study-uboot
|
drivers/rtc/m41t60.c
|
C
|
gpl3
| 7,371
|
/*
* Copyright (c) 2004-2008 Analog Devices Inc.
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#if defined(CONFIG_CMD_DATE)
#include <asm/blackfin.h>
#include <asm/mach-common/bits/rtc.h>
#define pr_stamp() debug("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__)
#define MIN_TO_SECS(x) (60 * (x))
#define HRS_TO_SECS(x) (60 * MIN_TO_SECS(x))
#define DAYS_TO_SECS(x) (24 * HRS_TO_SECS(x))
#define NUM_SECS_IN_MIN MIN_TO_SECS(1)
#define NUM_SECS_IN_HR HRS_TO_SECS(1)
#define NUM_SECS_IN_DAY DAYS_TO_SECS(1)
/* Enable the RTC prescaler enable register */
static void rtc_init(void)
{
if (!(bfin_read_RTC_PREN() & 0x1))
bfin_write_RTC_PREN(0x1);
}
/* Our on-chip RTC has no notion of "reset" */
void rtc_reset(void)
{
rtc_init();
}
/* Wait for pending writes to complete */
static void wait_for_complete(void)
{
pr_stamp();
while (!(bfin_read_RTC_ISTAT() & WRITE_COMPLETE))
if (!(bfin_read_RTC_ISTAT() & WRITE_PENDING))
break;
bfin_write_RTC_ISTAT(WRITE_COMPLETE);
}
/* Set the time. Get the time_in_secs which is the number of seconds since Jan 1970 and set the RTC registers
* based on this value.
*/
int rtc_set(struct rtc_time *tmp)
{
unsigned long remain, days, hrs, mins, secs;
pr_stamp();
if (tmp == NULL) {
puts("Error setting the date/time\n");
return -1;
}
rtc_init();
wait_for_complete();
/* Calculate number of seconds this incoming time represents */
remain = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
/* Figure out how many days since epoch */
days = remain / NUM_SECS_IN_DAY;
/* From the remaining secs, compute the hrs(0-23), mins(0-59) and secs(0-59) */
remain = remain % NUM_SECS_IN_DAY;
hrs = remain / NUM_SECS_IN_HR;
remain = remain % NUM_SECS_IN_HR;
mins = remain / NUM_SECS_IN_MIN;
secs = remain % NUM_SECS_IN_MIN;
/* Encode these time values into our RTC_STAT register */
bfin_write_RTC_STAT(SET_ALARM(days, hrs, mins, secs));
return 0;
}
/* Read the time from the RTC_STAT. time_in_seconds is seconds since Jan 1970 */
int rtc_get(struct rtc_time *tmp)
{
uint32_t cur_rtc_stat;
int time_in_sec;
int tm_sec, tm_min, tm_hr, tm_day;
pr_stamp();
if (tmp == NULL) {
puts("Error getting the date/time\n");
return -1;
}
rtc_init();
wait_for_complete();
/* Read the RTC_STAT register */
cur_rtc_stat = bfin_read_RTC_STAT();
/* Convert our encoded format into actual time values */
tm_sec = (cur_rtc_stat & RTC_SEC) >> RTC_SEC_P;
tm_min = (cur_rtc_stat & RTC_MIN) >> RTC_MIN_P;
tm_hr = (cur_rtc_stat & RTC_HR ) >> RTC_HR_P;
tm_day = (cur_rtc_stat & RTC_DAY) >> RTC_DAY_P;
/* Calculate the total number of seconds since epoch */
time_in_sec = (tm_sec) + MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hr) + DAYS_TO_SECS(tm_day);
to_tm(time_in_sec, tmp);
return 0;
}
#endif
|
1001-study-uboot
|
drivers/rtc/bfin_rtc.c
|
C
|
gpl3
| 2,985
|
/*
* (C) Copyright 2003
* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the built-in Samsung S3C24X0 RTC
*/
#include <common.h>
#include <command.h>
#if (defined(CONFIG_CMD_DATE))
#include <asm/arch/s3c24x0_cpu.h>
#include <rtc.h>
#include <asm/io.h>
#include <linux/compiler.h>
typedef enum {
RTC_ENABLE,
RTC_DISABLE
} RTC_ACCESS;
static inline void SetRTC_Access(RTC_ACCESS a)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
switch (a) {
case RTC_ENABLE:
writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon);
break;
case RTC_DISABLE:
writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon);
break;
}
}
/* ------------------------------------------------------------------------- */
int rtc_get(struct rtc_time *tmp)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
uchar sec, min, hour, mday, wday, mon, year;
__maybe_unused uchar a_sec, a_min, a_hour, a_date,
a_mon, a_year, a_armed;
/* enable access to RTC registers */
SetRTC_Access(RTC_ENABLE);
/* read RTC registers */
do {
sec = readb(&rtc->bcdsec);
min = readb(&rtc->bcdmin);
hour = readb(&rtc->bcdhour);
mday = readb(&rtc->bcddate);
wday = readb(&rtc->bcdday);
mon = readb(&rtc->bcdmon);
year = readb(&rtc->bcdyear);
} while (sec != readb(&rtc->bcdsec));
/* read ALARM registers */
a_sec = readb(&rtc->almsec);
a_min = readb(&rtc->almmin);
a_hour = readb(&rtc->almhour);
a_date = readb(&rtc->almdate);
a_mon = readb(&rtc->almmon);
a_year = readb(&rtc->almyear);
a_armed = readb(&rtc->rtcalm);
/* disable access to RTC registers */
SetRTC_Access(RTC_DISABLE);
#ifdef RTC_DEBUG
printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday, hour, min, sec);
printf("Alarms: %02x: year: %02x month: %02x date: %02x hour: "
"%02x min: %02x sec: %02x\n",
a_armed, a_year, a_mon, a_date, a_hour, a_min, a_sec);
#endif
tmp->tm_sec = bcd2bin(sec & 0x7F);
tmp->tm_min = bcd2bin(min & 0x7F);
tmp->tm_hour = bcd2bin(hour & 0x3F);
tmp->tm_mday = bcd2bin(mday & 0x3F);
tmp->tm_mon = bcd2bin(mon & 0x1F);
tmp->tm_year = bcd2bin(year);
tmp->tm_wday = bcd2bin(wday & 0x07);
if (tmp->tm_year < 70)
tmp->tm_year += 2000;
else
tmp->tm_year += 1900;
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
#ifdef RTC_DEBUG
printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
int rtc_set(struct rtc_time *tmp)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
uchar sec, min, hour, mday, wday, mon, year;
#ifdef RTC_DEBUG
printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
year = bin2bcd(tmp->tm_year % 100);
mon = bin2bcd(tmp->tm_mon);
wday = bin2bcd(tmp->tm_wday);
mday = bin2bcd(tmp->tm_mday);
hour = bin2bcd(tmp->tm_hour);
min = bin2bcd(tmp->tm_min);
sec = bin2bcd(tmp->tm_sec);
/* enable access to RTC registers */
SetRTC_Access(RTC_ENABLE);
/* write RTC registers */
writeb(sec, &rtc->bcdsec);
writeb(min, &rtc->bcdmin);
writeb(hour, &rtc->bcdhour);
writeb(mday, &rtc->bcddate);
writeb(wday, &rtc->bcdday);
writeb(mon, &rtc->bcdmon);
writeb(year, &rtc->bcdyear);
/* disable access to RTC registers */
SetRTC_Access(RTC_DISABLE);
return 0;
}
void rtc_reset(void)
{
struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon);
writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon);
}
#endif
|
1001-study-uboot
|
drivers/rtc/s3c24x0_rtc.c
|
C
|
gpl3
| 4,531
|
/*
* (C) Copyright 2001-2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Keith Outwater, keith_outwater@mvis.com`
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
* DS1337 Real Time Clock (RTC).
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
/*
* RTC register addresses
*/
#define RTC_SEC_REG_ADDR 0x0
#define RTC_MIN_REG_ADDR 0x1
#define RTC_HR_REG_ADDR 0x2
#define RTC_DAY_REG_ADDR 0x3
#define RTC_DATE_REG_ADDR 0x4
#define RTC_MON_REG_ADDR 0x5
#define RTC_YR_REG_ADDR 0x6
#define RTC_CTL_REG_ADDR 0x0e
#define RTC_STAT_REG_ADDR 0x0f
#define RTC_TC_REG_ADDR 0x10
/*
* RTC control register bits
*/
#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
/*
* RTC status register bits
*/
#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
/*
* Get the current time from the RTC
*/
int rtc_get (struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
control = rtc_read (RTC_CTL_REG_ADDR);
status = rtc_read (RTC_STAT_REG_ADDR);
sec = rtc_read (RTC_SEC_REG_ADDR);
min = rtc_read (RTC_MIN_REG_ADDR);
hour = rtc_read (RTC_HR_REG_ADDR);
wday = rtc_read (RTC_DAY_REG_ADDR);
mday = rtc_read (RTC_DATE_REG_ADDR);
mon_cent = rtc_read (RTC_MON_REG_ADDR);
year = rtc_read (RTC_YR_REG_ADDR);
debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
year, mon_cent, mday, wday, hour, min, sec, control, status);
if (status & RTC_STAT_BIT_OSF) {
printf ("### Warning: RTC oscillator has stopped\n");
/* clear the OSF flag */
rtc_write (RTC_STAT_REG_ADDR,
rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
rel = -1;
}
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return rel;
}
/*
* Set the RTC
*/
int rtc_set (struct rtc_time *tmp)
{
uchar century;
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
century = (tmp->tm_year >= 2000) ? 0x80 : 0;
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
return 0;
}
/*
* Reset the RTC. We also enable the oscillator output on the
* SQW/INTB* pin and program it for 32,768 Hz output. Note that
* according to the datasheet, turning on the square wave output
* increases the current drain on the backup battery from about
* 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
* off the OSC output.
*/
#ifdef CONFIG_SYS_RTC_DS1337_NOOSC
#define RTC_DS1337_RESET_VAL \
(RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
#else
#define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
#endif
void rtc_reset (void)
{
rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
#ifdef CONFIG_SYS_DS1339_TCR_VAL
rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
#endif
}
/*
* Helper functions
*/
static
uchar rtc_read (uchar reg)
{
return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
#endif
|
1001-study-uboot
|
drivers/rtc/ds1337.c
|
C
|
gpl3
| 5,261
|
/*
* (C) Copyright 2006
* Markus Klotzbuecher, mk@denx.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
* Extremly Accurate DS3231 Real Time Clock (RTC).
*
* copied from ds1337.c
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
/*
* RTC register addresses
*/
#define RTC_SEC_REG_ADDR 0x0
#define RTC_MIN_REG_ADDR 0x1
#define RTC_HR_REG_ADDR 0x2
#define RTC_DAY_REG_ADDR 0x3
#define RTC_DATE_REG_ADDR 0x4
#define RTC_MON_REG_ADDR 0x5
#define RTC_YR_REG_ADDR 0x6
#define RTC_CTL_REG_ADDR 0x0e
#define RTC_STAT_REG_ADDR 0x0f
/*
* RTC control register bits
*/
#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
/*
* RTC status register bits
*/
#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
/*
* Get the current time from the RTC
*/
int rtc_get (struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
control = rtc_read (RTC_CTL_REG_ADDR);
status = rtc_read (RTC_STAT_REG_ADDR);
sec = rtc_read (RTC_SEC_REG_ADDR);
min = rtc_read (RTC_MIN_REG_ADDR);
hour = rtc_read (RTC_HR_REG_ADDR);
wday = rtc_read (RTC_DAY_REG_ADDR);
mday = rtc_read (RTC_DATE_REG_ADDR);
mon_cent = rtc_read (RTC_MON_REG_ADDR);
year = rtc_read (RTC_YR_REG_ADDR);
debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
year, mon_cent, mday, wday, hour, min, sec, control, status);
if (status & RTC_STAT_BIT_OSF) {
printf ("### Warning: RTC oscillator has stopped\n");
/* clear the OSF flag */
rtc_write (RTC_STAT_REG_ADDR,
rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
rel = -1;
}
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return rel;
}
/*
* Set the RTC
*/
int rtc_set (struct rtc_time *tmp)
{
uchar century;
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
century = (tmp->tm_year >= 2000) ? 0x80 : 0;
rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
return 0;
}
/*
* Reset the RTC. We also enable the oscillator output on the
* SQW/INTB* pin and program it for 32,768 Hz output. Note that
* according to the datasheet, turning on the square wave output
* increases the current drain on the backup battery from about
* 600 nA to 2uA.
*/
void rtc_reset (void)
{
rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
}
/*
* Helper functions
*/
static
uchar rtc_read (uchar reg)
{
return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
#endif
|
1001-study-uboot
|
drivers/rtc/ds3231.c
|
C
|
gpl3
| 4,932
|
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_CMD_DATE)
#include <command.h>
#include <rtc.h>
#include <asm/immap.h>
#include <asm/rtc.h>
#undef RTC_DEBUG
#ifndef CONFIG_SYS_MCFRTC_BASE
#error RTC_BASE is not defined!
#endif
#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)
#define STARTOFTIME 1970
int rtc_get(struct rtc_time *tmp)
{
volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
int rtc_days, rtc_hrs, rtc_mins;
int tim;
rtc_days = rtc->days;
rtc_hrs = rtc->hourmin >> 8;
rtc_mins = RTC_HOURMIN_MINUTES(rtc->hourmin);
tim = (rtc_days * 24) + rtc_hrs;
tim = (tim * 60) + rtc_mins;
tim = (tim * 60) + rtc->seconds;
to_tm(tim, tmp);
tmp->tm_yday = 0;
tmp->tm_isdst = 0;
#ifdef RTC_DEBUG
printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
int rtc_set(struct rtc_time *tmp)
{
volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
static int month_days[12] = {
31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
};
int days, i, months;
if (tmp->tm_year > 2037) {
printf("Unable to handle. Exceeding integer limitation!\n");
tmp->tm_year = 2027;
}
#ifdef RTC_DEBUG
printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
/* calculate days by years */
for (i = STARTOFTIME, days = 0; i < tmp->tm_year; i++) {
days += 365 + isleap(i);
}
/* calculate days by months */
months = tmp->tm_mon - 1;
for (i = 0; i < months; i++) {
days += month_days[i];
if (i == 1)
days += isleap(i);
}
days += tmp->tm_mday - 1;
rtc->days = days;
rtc->hourmin = (tmp->tm_hour << 8) | tmp->tm_min;
rtc->seconds = tmp->tm_sec;
return 0;
}
void rtc_reset(void)
{
volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
if ((rtc->cr & RTC_CR_EN) == 0) {
printf("real-time-clock was stopped. Now starting...\n");
rtc->cr |= RTC_CR_EN;
}
rtc->cr |= RTC_CR_SWR;
}
#endif /* CONFIG_MCFRTC && CONFIG_CMD_DATE */
|
1001-study-uboot
|
drivers/rtc/mcfrtc.c
|
C
|
gpl3
| 3,080
|
/*
* (C) Copyright 2001
* Denis Peter MPL AG Switzerland. d.peter@mpl.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the MC146818 (PIXX4) RTC
*/
/*#define DEBUG*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#ifdef __I386__
#include <asm/io.h>
#define in8(p) inb(p)
#define out8(p, v) outb(v, p)
#endif
#if defined(CONFIG_CMD_DATE)
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70
#define RTC_SECONDS 0x00
#define RTC_SECONDS_ALARM 0x01
#define RTC_MINUTES 0x02
#define RTC_MINUTES_ALARM 0x03
#define RTC_HOURS 0x04
#define RTC_HOURS_ALARM 0x05
#define RTC_DAY_OF_WEEK 0x06
#define RTC_DATE_OF_MONTH 0x07
#define RTC_MONTH 0x08
#define RTC_YEAR 0x09
#define RTC_CONFIG_A 0x0A
#define RTC_CONFIG_B 0x0B
#define RTC_CONFIG_C 0x0C
#define RTC_CONFIG_D 0x0D
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
{
uchar sec, min, hour, mday, wday, mon, year;
/* here check if rtc can be accessed */
while((rtc_read(RTC_CONFIG_A)&0x80)==0x80);
sec = rtc_read (RTC_SECONDS);
min = rtc_read (RTC_MINUTES);
hour = rtc_read (RTC_HOURS);
mday = rtc_read (RTC_DATE_OF_MONTH);
wday = rtc_read (RTC_DAY_OF_WEEK);
mon = rtc_read (RTC_MONTH);
year = rtc_read (RTC_YEAR);
#ifdef RTC_DEBUG
printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon, mday, wday,
hour, min, sec );
printf ( "Alarms: month: %02x hour: %02x min: %02x sec: %02x\n",
rtc_read (RTC_CONFIG_D) & 0x3F,
rtc_read (RTC_HOURS_ALARM),
rtc_read (RTC_MINUTES_ALARM),
rtc_read (RTC_SECONDS_ALARM) );
#endif
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon & 0x1F);
tmp->tm_year = bcd2bin (year);
tmp->tm_wday = bcd2bin (wday & 0x07);
if(tmp->tm_year<70)
tmp->tm_year+=2000;
else
tmp->tm_year+=1900;
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
#ifdef RTC_DEBUG
printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
int rtc_set (struct rtc_time *tmp)
{
#ifdef RTC_DEBUG
printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
rtc_write(RTC_CONFIG_B,0x82); /* disables the RTC to update the regs */
rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100));
rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon));
rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday));
rtc_write (RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday));
rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour));
rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min ));
rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec ));
rtc_write(RTC_CONFIG_B,0x02); /* enables the RTC to update the regs */
return 0;
}
void rtc_reset (void)
{
rtc_write(RTC_CONFIG_B,0x82); /* disables the RTC to update the regs */
rtc_write(RTC_CONFIG_A,0x20); /* Normal OP */
rtc_write(RTC_CONFIG_B,0x00);
rtc_write(RTC_CONFIG_B,0x00);
rtc_write(RTC_CONFIG_B,0x02); /* enables the RTC to update the regs */
}
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_SYS_RTC_REG_BASE_ADDR
/*
* use direct memory access
*/
static uchar rtc_read (uchar reg)
{
return(in8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg));
}
static void rtc_write (uchar reg, uchar val)
{
out8(CONFIG_SYS_RTC_REG_BASE_ADDR+reg, val);
}
#else
static uchar rtc_read (uchar reg)
{
out8(RTC_PORT_MC146818,reg);
return(in8(RTC_PORT_MC146818+1));
}
static void rtc_write (uchar reg, uchar val)
{
out8(RTC_PORT_MC146818,reg);
out8(RTC_PORT_MC146818+1,val);
}
#endif
#endif
|
1001-study-uboot
|
drivers/rtc/mc146818.c
|
C
|
gpl3
| 4,696
|
/*
* (C) Copyright 2001, 2002, 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Keith Outwater, keith_outwater@mvis.com`
* Steven Scholz, steven.scholz@imc-berlin.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
* DS1374 Real Time Clock (RTC).
*
* based on ds1337.c
*/
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
/*---------------------------------------------------------------------*/
#undef DEBUG_RTC
#define DEBUG_RTC
#ifdef DEBUG_RTC
#define DEBUGR(fmt,args...) printf(fmt ,##args)
#else
#define DEBUGR(fmt,args...)
#endif
/*---------------------------------------------------------------------*/
#ifndef CONFIG_SYS_I2C_RTC_ADDR
# define CONFIG_SYS_I2C_RTC_ADDR 0x68
#endif
#if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
# error The DS1374 is specified up to 400kHz in fast mode!
#endif
/*
* RTC register addresses
*/
#define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */
#define RTC_TOD_CNT_BYTE1_ADDR 0x01
#define RTC_TOD_CNT_BYTE2_ADDR 0x02
#define RTC_TOD_CNT_BYTE3_ADDR 0x03
#define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04
#define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05
#define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06
#define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
#define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
#define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
#define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
#define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
#define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
#define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */
#define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
#define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
#define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
#define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */
#define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
#define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
typedef unsigned char boolean_t;
#ifndef TRUE
#define TRUE ((boolean_t)(0==0))
#endif
#ifndef FALSE
#define FALSE (!TRUE)
#endif
const char RtcTodAddr[] = {
RTC_TOD_CNT_BYTE0_ADDR,
RTC_TOD_CNT_BYTE1_ADDR,
RTC_TOD_CNT_BYTE2_ADDR,
RTC_TOD_CNT_BYTE3_ADDR
};
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val, boolean_t set);
static void rtc_write_raw (uchar reg, uchar val);
/*
* Get the current time from the RTC
*/
int rtc_get (struct rtc_time *tm){
int rel = 0;
unsigned long time1, time2;
unsigned int limit;
unsigned char tmp;
unsigned int i;
/*
* Since the reads are being performed one byte at a time,
* there is a chance that a carry will occur during the read.
* To detect this, 2 reads are performed and compared.
*/
limit = 10;
do {
i = 4;
time1 = 0;
while (i--) {
tmp = rtc_read(RtcTodAddr[i]);
time1 = (time1 << 8) | (tmp & 0xff);
}
i = 4;
time2 = 0;
while (i--) {
tmp = rtc_read(RtcTodAddr[i]);
time2 = (time2 << 8) | (tmp & 0xff);
}
} while ((time1 != time2) && limit--);
if (time1 != time2) {
printf("can't get consistent time from rtc chip\n");
rel = -1;
}
DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1);
to_tm(time1, tm); /* To Gregorian Date */
if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) {
printf ("### Warning: RTC oscillator has stopped\n");
rel = -1;
}
DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
return rel;
}
/*
* Set the RTC
*/
int rtc_set (struct rtc_time *tmp){
unsigned long time;
unsigned i;
DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
printf("WARNING: year should be between 1970 and 2069!\n");
time = mktime(tmp->tm_year, tmp->tm_mon,
tmp->tm_mday, tmp->tm_hour,
tmp->tm_min, tmp->tm_sec);
DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time, time);
/* write to RTC_TOD_CNT_BYTEn_ADDR */
for (i = 0; i <= 3; i++) {
rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
time = time >> 8;
}
/* Start clock */
rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE);
return 0;
}
/*
* Reset the RTC. We setting the date back to 1970-01-01.
* We also enable the oscillator output on the SQW/OUT pin and program
* it for 32,768 Hz output. Note that according to the datasheet, turning
* on the square wave output increases the current drain on the backup
* battery to something between 480nA and 800nA.
*/
void rtc_reset (void){
struct rtc_time tmp;
/* clear status flags */
rtc_write (RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), FALSE); /* clearing OSF and AF */
/* Initialise DS1374 oriented to MPC8349E-ADS */
rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
|RTC_CTL_BIT_WACE
|RTC_CTL_BIT_AIE), FALSE);/* start osc, disable WACE, clear AIE
- set to 0 */
rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
|RTC_CTL_BIT_WDSTR
|RTC_CTL_BIT_RS1
|RTC_CTL_BIT_RS2
|RTC_CTL_BIT_BBSQW), TRUE);/* disable WD/ALM, WDSTR set to INT-pin,
set BBSQW and SQW to 32k
- set to 1 */
tmp.tm_year = 1970;
tmp.tm_mon = 1;
tmp.tm_mday= 1;
tmp.tm_hour = 0;
tmp.tm_min = 0;
tmp.tm_sec = 0;
rtc_set(&tmp);
printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAC, TRUE);
rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR,0xDE, TRUE);
rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAD, TRUE);
}
/*
* Helper functions
*/
static uchar rtc_read (uchar reg)
{
return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val, boolean_t set)
{
if (set == TRUE) {
val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
} else {
val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val;
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
}
static void rtc_write_raw (uchar reg, uchar val)
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
#endif
|
1001-study-uboot
|
drivers/rtc/ds1374.c
|
C
|
gpl3
| 7,221
|
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for Philips PCF8563 RTC
*/
/* #define DEBUG */
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
static uchar rtc_read (uchar reg);
static void rtc_write (uchar reg, uchar val);
/* ------------------------------------------------------------------------- */
int rtc_get (struct rtc_time *tmp)
{
int rel = 0;
uchar sec, min, hour, mday, wday, mon_cent, year;
sec = rtc_read (0x02);
min = rtc_read (0x03);
hour = rtc_read (0x04);
mday = rtc_read (0x05);
wday = rtc_read (0x06);
mon_cent= rtc_read (0x07);
year = rtc_read (0x08);
debug ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
"hr: %02x min: %02x sec: %02x\n",
year, mon_cent, mday, wday,
hour, min, sec );
debug ( "Alarms: wday: %02x day: %02x hour: %02x min: %02x\n",
rtc_read (0x0C),
rtc_read (0x0B),
rtc_read (0x0A),
rtc_read (0x09) );
if (sec & 0x80) {
puts ("### Warning: RTC Low Voltage - date/time not reliable\n");
rel = -1;
}
tmp->tm_sec = bcd2bin (sec & 0x7F);
tmp->tm_min = bcd2bin (min & 0x7F);
tmp->tm_hour = bcd2bin (hour & 0x3F);
tmp->tm_mday = bcd2bin (mday & 0x3F);
tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
tmp->tm_wday = bcd2bin (wday & 0x07);
tmp->tm_yday = 0;
tmp->tm_isdst= 0;
debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
return rel;
}
int rtc_set (struct rtc_time *tmp)
{
uchar century;
debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
rtc_write (0x08, bin2bcd(tmp->tm_year % 100));
century = (tmp->tm_year >= 2000) ? 0x80 : 0;
rtc_write (0x07, bin2bcd(tmp->tm_mon) | century);
rtc_write (0x06, bin2bcd(tmp->tm_wday));
rtc_write (0x05, bin2bcd(tmp->tm_mday));
rtc_write (0x04, bin2bcd(tmp->tm_hour));
rtc_write (0x03, bin2bcd(tmp->tm_min ));
rtc_write (0x02, bin2bcd(tmp->tm_sec ));
return 0;
}
void rtc_reset (void)
{
/* clear all control & status registers */
rtc_write (0x00, 0x00);
rtc_write (0x01, 0x00);
rtc_write (0x0D, 0x00);
/* clear Voltage Low bit */
rtc_write (0x02, rtc_read (0x02) & 0x7F);
/* reset all alarms */
rtc_write (0x09, 0x00);
rtc_write (0x0A, 0x00);
rtc_write (0x0B, 0x00);
rtc_write (0x0C, 0x00);
}
/* ------------------------------------------------------------------------- */
static uchar rtc_read (uchar reg)
{
return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
}
static void rtc_write (uchar reg, uchar val)
{
i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
}
#endif
|
1001-study-uboot
|
drivers/rtc/pcf8563.c
|
C
|
gpl3
| 3,664
|
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* based on a the Linux rtc-x1207.c driver which is:
* Copyright 2004 Karen Spearel
* Copyright 2005 Alessandro Zummo
*
* Information and datasheet:
* http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for Xicor/Intersil X1205 RTC
*/
/* #define DEBUG */
#include <common.h>
#include <command.h>
#include <rtc.h>
#include <i2c.h>
#if defined(CONFIG_CMD_DATE)
#define CCR_SEC 0
#define CCR_MIN 1
#define CCR_HOUR 2
#define CCR_MDAY 3
#define CCR_MONTH 4
#define CCR_YEAR 5
#define CCR_WDAY 6
#define CCR_Y2K 7
#define X1205_REG_SR 0x3F /* status register */
#define X1205_REG_Y2K 0x37
#define X1205_REG_DW 0x36
#define X1205_REG_YR 0x35
#define X1205_REG_MO 0x34
#define X1205_REG_DT 0x33
#define X1205_REG_HR 0x32
#define X1205_REG_MN 0x31
#define X1205_REG_SC 0x30
#define X1205_REG_DTR 0x13
#define X1205_REG_ATR 0x12
#define X1205_REG_INT 0x11
#define X1205_REG_0 0x10
#define X1205_REG_Y2K1 0x0F
#define X1205_REG_DWA1 0x0E
#define X1205_REG_YRA1 0x0D
#define X1205_REG_MOA1 0x0C
#define X1205_REG_DTA1 0x0B
#define X1205_REG_HRA1 0x0A
#define X1205_REG_MNA1 0x09
#define X1205_REG_SCA1 0x08
#define X1205_REG_Y2K0 0x07
#define X1205_REG_DWA0 0x06
#define X1205_REG_YRA0 0x05
#define X1205_REG_MOA0 0x04
#define X1205_REG_DTA0 0x03
#define X1205_REG_HRA0 0x02
#define X1205_REG_MNA0 0x01
#define X1205_REG_SCA0 0x00
#define X1205_CCR_BASE 0x30 /* Base address of CCR */
#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
#define X1205_SR_RTCF 0x01 /* Clock failure */
#define X1205_SR_WEL 0x02 /* Write Enable Latch */
#define X1205_SR_RWEL 0x04 /* Register Write Enable */
#define X1205_DTR_DTR0 0x01
#define X1205_DTR_DTR1 0x02
#define X1205_DTR_DTR2 0x04
#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
static void rtc_write(int reg, u8 val)
{
i2c_write(CONFIG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1);
}
/*
* In the routines that deal directly with the x1205 hardware, we use
* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
* Epoch is initialized as 2000. Time is set to UTC.
*/
int rtc_get(struct rtc_time *tm)
{
u8 buf[8];
i2c_read(CONFIG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8);
debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
__FUNCTION__,
buf[0], buf[1], buf[2], buf[3],
buf[4], buf[5], buf[6], buf[7]);
tm->tm_sec = bcd2bin(buf[CCR_SEC]);
tm->tm_min = bcd2bin(buf[CCR_MIN]);
tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */
tm->tm_year = bcd2bin(buf[CCR_YEAR])
+ (bcd2bin(buf[CCR_Y2K]) * 100);
tm->tm_wday = buf[CCR_WDAY];
debug("%s: tm is secs=%d, mins=%d, hours=%d, "
"mday=%d, mon=%d, year=%d, wday=%d\n",
__FUNCTION__,
tm->tm_sec, tm->tm_min, tm->tm_hour,
tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
return 0;
}
int rtc_set(struct rtc_time *tm)
{
int i;
u8 buf[8];
debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
tm->tm_hour, tm->tm_min, tm->tm_sec);
buf[CCR_SEC] = bin2bcd(tm->tm_sec);
buf[CCR_MIN] = bin2bcd(tm->tm_min);
/* set hour and 24hr bit */
buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;
buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
/* month, 1 - 12 */
buf[CCR_MONTH] = bin2bcd(tm->tm_mon);
/* year, since the rtc epoch*/
buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
buf[CCR_WDAY] = tm->tm_wday & 0x07;
buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100);
/* this sequence is required to unlock the chip */
rtc_write(X1205_REG_SR, X1205_SR_WEL);
rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL);
/* write register's data */
for (i = 0; i < 8; i++)
rtc_write(X1205_CCR_BASE + i, buf[i]);
rtc_write(X1205_REG_SR, 0);
return 0;
}
void rtc_reset(void)
{
/*
* Nothing to do
*/
}
#endif
|
1001-study-uboot
|
drivers/rtc/x1205.c
|
C
|
gpl3
| 4,907
|
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#ifdef CONFIG_TWL6030_POWER
#include <twl6030.h>
/* Functions to read and write from TWL6030 */
static inline int twl6030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
{
return i2c_write(chip_no, reg, 1, &val, 1);
}
static inline int twl6030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
{
return i2c_read(chip_no, reg, 1, val, 1);
}
static int twl6030_gpadc_read_channel(u8 channel_no)
{
u8 lsb = 0;
u8 msb = 0;
int ret = 0;
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &lsb,
GPCH0_LSB + channel_no * 2);
if (ret)
return ret;
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &msb,
GPCH0_MSB + channel_no * 2);
if (ret)
return ret;
return (msb << 8) | lsb;
}
static int twl6030_gpadc_sw2_trigger(void)
{
u8 val;
int ret = 0;
ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2_SP2, CTRL_P2);
if (ret)
return ret;
/* Waiting until the SW1 conversion ends*/
val = CTRL_P2_BUSY;
while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) {
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, &val, CTRL_P2);
if (ret)
return ret;
udelay(1000);
}
return 0;
}
void twl6030_stop_usb_charging(void)
{
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, 0, CONTROLLER_CTRL1);
return;
}
void twl6030_start_usb_charging(void)
{
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VICHRG_1500,
CHARGERUSB_VICHRG);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CIN_LIMIT_NONE,
CHARGERUSB_CINLIMIT);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MBAT_TEMP,
CONTROLLER_INT_MASK);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, MASK_MCHARGERUSB_THMREG,
CHARGERUSB_INT_MASK);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_VOREG_4P0,
CHARGERUSB_VOREG);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CHARGERUSB_CTRL2_VITERM_400,
CHARGERUSB_CTRL2);
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TERM, CHARGERUSB_CTRL1);
/* Enable USB charging */
twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, CONTROLLER_CTRL1_EN_CHARGER,
CONTROLLER_CTRL1);
return;
}
int twl6030_get_battery_current(void)
{
int battery_current = 0;
u8 msb = 0;
u8 lsb = 0;
twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &msb, FG_REG_11);
twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &lsb, FG_REG_10);
battery_current = ((msb << 8) | lsb);
/* convert 10 bit signed number to 16 bit signed number */
if (battery_current >= 0x2000)
battery_current = (battery_current - 0x4000);
battery_current = battery_current * 3000 / 4096;
printf("Battery Current: %d mA\n", battery_current);
return battery_current;
}
int twl6030_get_battery_voltage(void)
{
int battery_volt = 0;
int ret = 0;
/* Start GPADC SW conversion */
ret = twl6030_gpadc_sw2_trigger();
if (ret) {
printf("Failed to convert battery voltage\n");
return ret;
}
/* measure Vbat voltage */
battery_volt = twl6030_gpadc_read_channel(7);
if (battery_volt < 0) {
printf("Failed to read battery voltage\n");
return ret;
}
battery_volt = (battery_volt * 25 * 1000) >> (10 + 2);
printf("Battery Voltage: %d mV\n", battery_volt);
return battery_volt;
}
void twl6030_init_battery_charging(void)
{
u8 stat1 = 0;
int battery_volt = 0;
int ret = 0;
/* Enable VBAT measurement */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, VBAT_MEAS, MISC1);
/* Enable GPADC module */
ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, FGS | GPADCS, TOGGLE1);
if (ret) {
printf("Failed to enable GPADC\n");
return;
}
battery_volt = twl6030_get_battery_voltage();
if (battery_volt < 0)
return;
if (battery_volt < 3000)
printf("Main battery voltage too low!\n");
/* Check for the presence of USB charger */
twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, &stat1, CONTROLLER_STAT1);
/* check for battery presence indirectly via Fuel gauge */
if ((stat1 & VBUS_DET) && (battery_volt < 3300))
twl6030_start_usb_charging();
return;
}
void twl6030_power_mmc_init()
{
/* set voltage to 3.0 and turnon for APP */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x15, VMMC_CFG_VOLTATE);
twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VMMC_CFG_STATE);
}
void twl6030_usb_device_settings()
{
u8 data = 0;
/* Select APP Group and set state to ON */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, 0x21, VUSB_CFG_STATE);
twl6030_i2c_read_u8(TWL6030_CHIP_PM, &data, MISC2);
data |= 0x10;
/* Select the input supply for VBUS regulator */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, data, MISC2);
}
#endif
|
1001-study-uboot
|
drivers/power/twl6030.c
|
C
|
gpl3
| 5,272
|
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix at windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* twl4030_power_reset_init is derived from code on omapzoom,
* git://git.omapzoom.com/repo/u-boot.git
*
* Copyright (C) 2007-2009 Texas Instruments, Inc.
*
* twl4030_power_init is from cpu/omap3/common.c, power_init_r
*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*
* Author :
* Sunil Kumar <sunilsaini05 at gmail.com>
* Shashi Ranjan <shashiranjanmca05 at gmail.com>
*
* Derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2 at ti.com>
* Syed Mohammed Khasim <khasim at ti.com>
*
*/
#include <twl4030.h>
/*
* Power Reset
*/
void twl4030_power_reset_init(void)
{
u8 val = 0;
if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val,
TWL4030_PM_MASTER_P1_SW_EVENTS)) {
printf("Error:TWL4030: failed to read the power register\n");
printf("Could not initialize hardware reset\n");
} else {
val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON;
if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, val,
TWL4030_PM_MASTER_P1_SW_EVENTS)) {
printf("Error:TWL4030: failed to write the power register\n");
printf("Could not initialize hardware reset\n");
}
}
}
/*
* Set Device Group and Voltage
*/
void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
u8 dev_grp, u8 dev_grp_sel)
{
/* Select the Device Group */
twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
dev_grp);
/* Select the Voltage */
twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
vsel_reg);
}
void twl4030_power_init(void)
{
/* set VAUX3 to 2.8V */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED,
TWL4030_PM_RECEIVER_VAUX3_VSEL_28,
TWL4030_PM_RECEIVER_VAUX3_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
/* set VPLL2 to 1.8V */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VPLL2_DEDICATED,
TWL4030_PM_RECEIVER_VPLL2_VSEL_18,
TWL4030_PM_RECEIVER_VPLL2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_ALL);
/* set VDAC to 1.8V */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED,
TWL4030_PM_RECEIVER_VDAC_VSEL_18,
TWL4030_PM_RECEIVER_VDAC_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
void twl4030_power_mmc_init(void)
{
/* Set VMMC1 to 3.15 Volts */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
|
1001-study-uboot
|
drivers/power/twl4030.c
|
C
|
gpl3
| 3,165
|
#
# Copyright (c) 2009 Wind River Systems, Inc.
# Tom Rix <Tom.Rix at windriver.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libpower.o
COBJS-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o
COBJS-$(CONFIG_TWL6030_POWER) += twl6030.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
########################################################################
|
1001-study-uboot
|
drivers/power/Makefile
|
Makefile
|
gpl3
| 1,447
|
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* Copyright (C) 2010 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <asm/io.h>
#include <faraday/ftpmu010.h>
/* OSCC: OSC Control Register */
void ftpmu010_32768osc_enable(void)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int oscc;
/* enable the 32768Hz oscillator */
oscc = readl(&pmu->OSCC);
oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI);
writel(oscc, &pmu->OSCC);
/* wait until ready */
while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE))
;
/* select 32768Hz oscillator */
oscc = readl(&pmu->OSCC);
oscc |= FTPMU010_OSCC_OSCL_RTCLSEL;
writel(oscc, &pmu->OSCC);
}
/* MFPSR: Multi-Function Port Setting Register */
void ftpmu010_mfpsr_select_dev(unsigned int dev)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int mfpsr;
mfpsr = readl(&pmu->MFPSR);
mfpsr |= dev;
writel(mfpsr, &pmu->MFPSR);
}
void ftpmu010_mfpsr_diselect_dev(unsigned int dev)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int mfpsr;
mfpsr = readl(&pmu->MFPSR);
mfpsr &= ~dev;
writel(mfpsr, &pmu->MFPSR);
}
/* PDLLCR0: PLL/DLL Control Register 0 */
void ftpmu010_dlldis_disable(void)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
pdllcr0 |= FTPMU010_PDLLCR0_DLLDIS;
writel(pdllcr0, &pmu->PDLLCR0);
}
void ftpmu010_sdram_clk_disable(unsigned int cr0)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0);
writel(pdllcr0, &pmu->PDLLCR0);
}
/* SDRAMHTC: SDRAM Signal Hold Time Control */
void ftpmu010_sdramhtc_set(unsigned int val)
{
static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int sdramhtc;
sdramhtc = readl(&pmu->SDRAMHTC);
sdramhtc |= val;
writel(sdramhtc, &pmu->SDRAMHTC);
}
|
1001-study-uboot
|
drivers/power/ftpmu010.c
|
C
|
gpl3
| 2,905
|
/*
* Davinci MMC Controller Driver
*
* Copyright (C) 2010 Texas Instruments Incorporated
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/sdmmc_defs.h>
#define DAVINCI_MAX_BLOCKS (32)
#define WATCHDOG_COUNT (100000)
#define get_val(addr) REG(addr)
#define set_val(addr, val) REG(addr) = (val)
#define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
#define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
/* Set davinci clock prescalar value based on the required clock in HZ */
static void dmmc_set_clock(struct mmc *mmc, uint clock)
{
struct davinci_mmc *host = mmc->priv;
struct davinci_mmc_regs *regs = host->reg_base;
uint clkrt, sysclk2, act_clock;
if (clock < mmc->f_min)
clock = mmc->f_min;
if (clock > mmc->f_max)
clock = mmc->f_max;
set_val(®s->mmcclk, 0);
sysclk2 = host->input_clk;
clkrt = (sysclk2 / (2 * clock)) - 1;
/* Calculate the actual clock for the divider used */
act_clock = (sysclk2 / (2 * (clkrt + 1)));
/* Adjust divider if actual clock exceeds the required clock */
if (act_clock > clock)
clkrt++;
/* check clock divider boundary and correct it */
if (clkrt > 0xFF)
clkrt = 0xFF;
set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN));
}
/* Status bit wait loop for MMCST1 */
static int
dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
{
uint wdog = WATCHDOG_COUNT;
while (--wdog && ((get_val(®s->mmcst1) & status) != status))
udelay(10);
if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT))
udelay(100);
if (wdog == 0)
return COMM_ERR;
return 0;
}
/* Busy bit wait loop for MMCST1 */
static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
{
uint wdog = WATCHDOG_COUNT;
while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY))
udelay(10);
if (wdog == 0)
return COMM_ERR;
return 0;
}
/* Status bit wait loop for MMCST0 - Checks for error bits as well */
static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
uint *cur_st, uint st_ready, uint st_error)
{
uint wdog = WATCHDOG_COUNT;
uint mmcstatus = *cur_st;
while (wdog--) {
if (mmcstatus & st_ready) {
*cur_st = mmcstatus;
mmcstatus = get_val(®s->mmcst1);
return 0;
} else if (mmcstatus & st_error) {
if (mmcstatus & MMCST0_TOUTRS)
return TIMEOUT;
printf("[ ST0 ERROR %x]\n", mmcstatus);
/*
* Ignore CRC errors as some MMC cards fail to
* initialize on DM365-EVM on the SD1 slot
*/
if (mmcstatus & MMCST0_CRCRS)
return 0;
return COMM_ERR;
}
udelay(10);
mmcstatus = get_val(®s->mmcst0);
}
printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
get_val(®s->mmcst1));
return COMM_ERR;
}
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
*/
static int
dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
struct davinci_mmc *host = mmc->priv;
volatile struct davinci_mmc_regs *regs = host->reg_base;
uint mmcstatus, status_rdy, status_err;
uint i, cmddata, bytes_left = 0;
int fifo_words, fifo_bytes, err;
char *data_buf = NULL;
/* Clear status registers */
mmcstatus = get_val(®s->mmcst0);
fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8;
fifo_bytes = fifo_words << 2;
/* Wait for any previous busy signal to be cleared */
dmmc_busy_wait(regs);
cmddata = cmd->cmdidx;
cmddata |= MMCCMD_PPLEN;
/* Send init clock for CMD0 */
if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
cmddata |= MMCCMD_INITCK;
switch (cmd->resp_type) {
case MMC_RSP_R1b:
cmddata |= MMCCMD_BSYEXP;
/* Fall-through */
case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
cmddata |= MMCCMD_RSPFMT_R1567;
break;
case MMC_RSP_R2:
cmddata |= MMCCMD_RSPFMT_R2;
break;
case MMC_RSP_R3: /* R3, R4 */
cmddata |= MMCCMD_RSPFMT_R3;
break;
}
set_val(®s->mmcim, 0);
if (data) {
/* clear previous data transfer if any and set new one */
bytes_left = (data->blocksize * data->blocks);
/* Reset FIFO - Always use 32 byte fifo threshold */
set_val(®s->mmcfifoctl,
(MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
if (host->version == MMC_CTLR_VERSION_2)
cmddata |= MMCCMD_DMATRIG;
cmddata |= MMCCMD_WDATX;
if (data->flags == MMC_DATA_READ) {
set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
} else if (data->flags == MMC_DATA_WRITE) {
set_val(®s->mmcfifoctl,
(MMCFIFOCTL_FIFOLEV |
MMCFIFOCTL_FIFODIR));
cmddata |= MMCCMD_DTRW;
}
set_val(®s->mmctod, 0xFFFF);
set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
if (data->flags == MMC_DATA_WRITE) {
uint val;
data_buf = (char *)data->src;
/* For write, fill FIFO with data before issue of CMD */
for (i = 0; (i < fifo_words) && bytes_left; i++) {
memcpy((char *)&val, data_buf, 4);
set_val(®s->mmcdxr, val);
data_buf += 4;
bytes_left -= 4;
}
}
} else {
set_val(®s->mmcblen, 0);
set_val(®s->mmcnblk, 0);
}
set_val(®s->mmctor, 0x1FFF);
/* Send the command */
set_val(®s->mmcarghl, cmd->cmdarg);
set_val(®s->mmccmd, cmddata);
status_rdy = MMCST0_RSPDNE;
status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
MMCST0_CRCWR | MMCST0_CRCRD);
if (cmd->resp_type & MMC_RSP_CRC)
status_err |= MMCST0_CRCRS;
mmcstatus = get_val(®s->mmcst0);
err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
if (err)
return err;
/* For R1b wait for busy done */
if (cmd->resp_type == MMC_RSP_R1b)
dmmc_busy_wait(regs);
/* Collect response from controller for specific commands */
if (mmcstatus & MMCST0_RSPDNE) {
/* Copy the response to the response buffer */
if (cmd->resp_type & MMC_RSP_136) {
cmd->response[0] = get_val(®s->mmcrsp67);
cmd->response[1] = get_val(®s->mmcrsp45);
cmd->response[2] = get_val(®s->mmcrsp23);
cmd->response[3] = get_val(®s->mmcrsp01);
} else if (cmd->resp_type & MMC_RSP_PRESENT) {
cmd->response[0] = get_val(®s->mmcrsp67);
}
}
if (data == NULL)
return 0;
if (data->flags == MMC_DATA_READ) {
/* check for DATDNE along with DRRDY as the controller might
* set the DATDNE without DRRDY for smaller transfers with
* less than FIFO threshold bytes
*/
status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
data_buf = data->dest;
} else {
status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
status_err = MMCST0_CRCWR;
}
/* Wait until all of the blocks are transferred */
while (bytes_left) {
err = dmmc_check_status(regs, &mmcstatus, status_rdy,
status_err);
if (err)
return err;
if (data->flags == MMC_DATA_READ) {
/*
* MMC controller sets the Data receive ready bit
* (DRRDY) in MMCST0 even before the entire FIFO is
* full. This results in erratic behavior if we start
* reading the FIFO soon after DRRDY. Wait for the
* FIFO full bit in MMCST1 for proper FIFO clearing.
*/
if (bytes_left > fifo_bytes)
dmmc_wait_fifo_status(regs, 0x4a);
else if (bytes_left == fifo_bytes)
dmmc_wait_fifo_status(regs, 0x40);
for (i = 0; bytes_left && (i < fifo_words); i++) {
cmddata = get_val(®s->mmcdrr);
memcpy(data_buf, (char *)&cmddata, 4);
data_buf += 4;
bytes_left -= 4;
}
} else {
/*
* MMC controller sets the Data transmit ready bit
* (DXRDY) in MMCST0 even before the entire FIFO is
* empty. This results in erratic behavior if we start
* writing the FIFO soon after DXRDY. Wait for the
* FIFO empty bit in MMCST1 for proper FIFO clearing.
*/
dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
for (i = 0; bytes_left && (i < fifo_words); i++) {
memcpy((char *)&cmddata, data_buf, 4);
set_val(®s->mmcdxr, cmddata);
data_buf += 4;
bytes_left -= 4;
}
dmmc_busy_wait(regs);
}
}
err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
if (err)
return err;
return 0;
}
/* Initialize Davinci MMC controller */
static int dmmc_init(struct mmc *mmc)
{
struct davinci_mmc *host = mmc->priv;
struct davinci_mmc_regs *regs = host->reg_base;
/* Clear status registers explicitly - soft reset doesn't clear it
* If Uboot is invoked from UBL with SDMMC Support, the status
* registers can have uncleared bits
*/
get_val(®s->mmcst0);
get_val(®s->mmcst1);
/* Hold software reset */
set_bit(®s->mmcctl, MMCCTL_DATRST);
set_bit(®s->mmcctl, MMCCTL_CMDRST);
udelay(10);
set_val(®s->mmcclk, 0x0);
set_val(®s->mmctor, 0x1FFF);
set_val(®s->mmctod, 0xFFFF);
/* Clear software reset */
clear_bit(®s->mmcctl, MMCCTL_DATRST);
clear_bit(®s->mmcctl, MMCCTL_CMDRST);
udelay(10);
/* Reset FIFO - Always use the maximum fifo threshold */
set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
return 0;
}
/* Set buswidth or clock as indicated by the GENERIC_MMC framework */
static void dmmc_set_ios(struct mmc *mmc)
{
struct davinci_mmc *host = mmc->priv;
struct davinci_mmc_regs *regs = host->reg_base;
/* Set the bus width */
if (mmc->bus_width == 4)
set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
else
clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
/* Set clock speed */
if (mmc->clock)
dmmc_set_clock(mmc, mmc->clock);
}
/* Called from board_mmc_init during startup. Can be called multiple times
* depending on the number of slots available on board and controller
*/
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
{
struct mmc *mmc;
mmc = malloc(sizeof(struct mmc));
memset(mmc, 0, sizeof(struct mmc));
sprintf(mmc->name, "davinci");
mmc->priv = host;
mmc->send_cmd = dmmc_send_cmd;
mmc->set_ios = dmmc_set_ios;
mmc->init = dmmc_init;
mmc->f_min = 200000;
mmc->f_max = 25000000;
mmc->voltages = host->voltages;
mmc->host_caps = host->host_caps;
mmc->b_max = DAVINCI_MAX_BLOCKS;
mmc_register(mmc);
return 0;
}
|
1001-study-uboot
|
drivers/mmc/davinci_mmc.c
|
C
|
gpl3
| 10,790
|
/*
* Copyright (C) 2011 Andes Technology Corporation
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <faraday/ftsdc010.h>
/*
* supported mmc hosts
* setting the number CONFIG_FTSDC010_NUMBER in your configuration file.
*/
static struct mmc ftsdc010_dev[CONFIG_FTSDC010_NUMBER];
static struct mmc_host ftsdc010_host[CONFIG_FTSDC010_NUMBER];
static struct ftsdc010_mmc *ftsdc010_get_base_mmc(int dev_index)
{
return (struct ftsdc010_mmc *)CONFIG_FTSDC010_BASE + dev_index;
}
#ifdef DEBUG
static void ftsdc010_dump_reg(struct mmc_host *host)
{
debug("cmd: %08x\n", readl(&host->reg->cmd));
debug("argu: %08x\n", readl(&host->reg->argu));
debug("rsp0: %08x\n", readl(&host->reg->rsp0));
debug("rsp1: %08x\n", readl(&host->reg->rsp1));
debug("rsp2: %08x\n", readl(&host->reg->rsp2));
debug("rsp3: %08x\n", readl(&host->reg->rsp3));
debug("rsp_cmd: %08x\n", readl(&host->reg->rsp_cmd));
debug("dcr: %08x\n", readl(&host->reg->dcr));
debug("dtr: %08x\n", readl(&host->reg->dtr));
debug("dlr: %08x\n", readl(&host->reg->dlr));
debug("status: %08x\n", readl(&host->reg->status));
debug("clr: %08x\n", readl(&host->reg->clr));
debug("int_mask: %08x\n", readl(&host->reg->int_mask));
debug("pcr: %08x\n", readl(&host->reg->pcr));
debug("ccr: %08x\n", readl(&host->reg->ccr));
debug("bwr: %08x\n", readl(&host->reg->bwr));
debug("dwr: %08x\n", readl(&host->reg->dwr));
debug("feature: %08x\n", readl(&host->reg->feature));
debug("rev: %08x\n", readl(&host->reg->rev));
}
#endif
static unsigned int enable_imask(struct ftsdc010_mmc *reg, unsigned int imask)
{
unsigned int newmask;
newmask = readl(®->int_mask);
newmask |= imask;
writel(newmask, ®->int_mask);
return newmask;
}
static void ftsdc010_pio_read(struct mmc_host *host, char *buf, unsigned int size)
{
unsigned int fifo;
unsigned int fifo_words;
unsigned int *ptr;
unsigned int status;
unsigned int retry = 0;
/* get_data_buffer */
ptr = (unsigned int *)buf;
while (size) {
status = readl(&host->reg->status);
if (status & FTSDC010_STATUS_FIFO_ORUN) {
fifo = host->fifo_len > size ?
size : host->fifo_len;
size -= fifo;
fifo_words = fifo >> 2;
while (fifo_words--)
*ptr++ = readl(&host->reg->dwr);
/*
* for adding some delays for SD card to put
* data into FIFO again
*/
udelay(4*FTSDC010_DELAY_UNIT);
#ifdef CONFIG_FTSDC010_SDIO
/* sdio allow non-power-of-2 blksz */
if (fifo & 3) {
unsigned int n = fifo & 3;
unsigned int data = readl(&host->reg->dwr);
unsigned char *p = (unsigned char *)ptr;
while (n--) {
*p++ = data;
data >>= 8;
}
}
#endif
} else {
udelay(1);
if (++retry >= FTSDC010_PIO_RETRY) {
debug("%s: PIO_RETRY timeout\n", __func__);
return;
}
}
}
}
static void ftsdc010_pio_write(struct mmc_host *host, const char *buf,
unsigned int size)
{
unsigned int fifo;
unsigned int *ptr;
unsigned int status;
unsigned int retry = 0;
/* get data buffer */
ptr = (unsigned int *)buf;
while (size) {
status = readl(&host->reg->status);
if (status & FTSDC010_STATUS_FIFO_ORUN) {
fifo = host->fifo_len > size ?
size : host->fifo_len;
size -= fifo;
fifo = (fifo + 3) >> 2;
while (fifo--) {
writel(*ptr, &host->reg->dwr);
ptr++;
}
} else {
udelay(1);
if (++retry >= FTSDC010_PIO_RETRY) {
debug("%s: PIO_RETRY timeout\n", __func__);
return;
}
}
}
}
static int ftsdc010_pio_check_status(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct mmc_host *host = mmc->priv;
unsigned int sta, clear;
unsigned int i;
/* check response and hardware status */
clear = 0;
/* chech CMD_SEND */
for (i = 0; i < FTSDC010_CMD_RETRY; i++) {
sta = readl(&host->reg->status);
/* Command Complete */
if (sta & FTSDC010_STATUS_CMD_SEND) {
if (!data)
clear |= FTSDC010_CLR_CMD_SEND;
break;
}
}
if (i > FTSDC010_CMD_RETRY) {
printf("%s: send command timeout\n", __func__);
return TIMEOUT;
}
/* debug: print status register and command index*/
debug("sta: %08x cmd %d\n", sta, cmd->cmdidx);
/* handle data FIFO */
if ((sta & FTSDC010_STATUS_FIFO_ORUN) ||
(sta & FTSDC010_STATUS_FIFO_URUN)) {
/* Wrong DATA FIFO Flag */
if (data == NULL)
printf("%s, data fifo wrong: sta: %08x cmd %d\n",
__func__, sta, cmd->cmdidx);
if (sta & FTSDC010_STATUS_FIFO_ORUN)
clear |= FTSDC010_STATUS_FIFO_ORUN;
if (sta & FTSDC010_STATUS_FIFO_URUN)
clear |= FTSDC010_STATUS_FIFO_URUN;
}
/* check RSP TIMEOUT or FAIL */
if (sta & FTSDC010_STATUS_RSP_TIMEOUT) {
/* RSP TIMEOUT */
debug("%s: RSP timeout: sta: %08x cmd %d\n",
__func__, sta, cmd->cmdidx);
clear |= FTSDC010_CLR_RSP_TIMEOUT;
writel(clear, &host->reg->clr);
return TIMEOUT;
} else if (sta & FTSDC010_STATUS_RSP_CRC_FAIL) {
/* clear response fail bit */
debug("%s: RSP CRC FAIL: sta: %08x cmd %d\n",
__func__, sta, cmd->cmdidx);
clear |= FTSDC010_CLR_RSP_CRC_FAIL;
writel(clear, &host->reg->clr);
return 0;
} else if (sta & FTSDC010_STATUS_RSP_CRC_OK) {
/* clear response CRC OK bit */
clear |= FTSDC010_CLR_RSP_CRC_OK;
}
/* check DATA TIMEOUT or FAIL */
if (data) {
if (sta & FTSDC010_STATUS_DATA_TIMEOUT) {
/* DATA TIMEOUT */
debug("%s: DATA TIMEOUT: sta: %08x\n",
__func__, sta);
clear |= FTSDC010_STATUS_DATA_TIMEOUT;
writel(sta, &host->reg->clr);
return TIMEOUT;
} else if (sta & FTSDC010_STATUS_DATA_CRC_FAIL) {
/* Error Interrupt */
debug("%s: DATA CRC FAIL: sta: %08x\n",
__func__, sta);
clear |= FTSDC010_STATUS_DATA_CRC_FAIL;
writel(clear, &host->reg->clr);
return 0;
} else if (sta & FTSDC010_STATUS_DATA_END) {
/* Transfer Complete */
clear |= FTSDC010_STATUS_DATA_END;
}
}
/* transaction is success and clear status register */
writel(clear, &host->reg->clr);
return 0;
}
static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct mmc_host *host = mmc->priv;
#ifdef CONFIG_FTSDC010_SDIO
unsigned int scon;
#endif
unsigned int ccon;
unsigned int mask, tmpmask;
unsigned int ret;
if (data)
mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
else if (cmd->resp_type & MMC_RSP_PRESENT)
mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
else
mask = FTSDC010_INT_MASK_CMD_SEND;
/* write argu reg */
debug("%s: cmd->arg: %08x\n", __func__, cmd->cmdarg);
writel(cmd->cmdarg, &host->reg->argu);
/* setup cmd reg */
debug("cmd: %d\n", cmd->cmdidx);
debug("resp: %08x\n", cmd->resp_type);
/* setup commnad */
ccon = FTSDC010_CMD_IDX(cmd->cmdidx);
/* setup command flags */
ccon |= FTSDC010_CMD_CMD_EN;
/*
* This hardware didn't support specific commands for mapping
* MMC_RSP_BUSY and MMC_RSP_OPCODE. Hence we don't deal with it.
*/
if (cmd->resp_type & MMC_RSP_PRESENT) {
ccon |= FTSDC010_CMD_NEED_RSP;
mask |= FTSDC010_INT_MASK_RSP_CRC_OK |
FTSDC010_INT_MASK_RSP_CRC_FAIL;
}
if (cmd->resp_type & MMC_RSP_136)
ccon |= FTSDC010_CMD_LONG_RSP;
/* In Linux driver, MMC_CMD_APP_CMD is checked in last_opcode */
if (host->last_opcode == MMC_CMD_APP_CMD)
ccon |= FTSDC010_CMD_APP_CMD;
#ifdef CONFIG_FTSDC010_SDIO
scon = readl(&host->reg->sdio_ctrl1);
if (host->card_type == MMC_TYPE_SDIO)
scon |= FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
else
scon &= ~FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
writel(scon, &host->reg->sdio_ctrl1);
#endif
/* record last opcode for specifing the command type to hardware */
host->last_opcode = cmd->cmdidx;
/* write int_mask reg */
tmpmask = readl(&host->reg->int_mask);
tmpmask |= mask;
writel(tmpmask, &host->reg->int_mask);
/* write cmd reg */
debug("%s: ccon: %08x\n", __func__, ccon);
writel(ccon, &host->reg->cmd);
udelay(4*FTSDC010_DELAY_UNIT);
/* read/write data */
if (data && (data->flags & MMC_DATA_READ)) {
ftsdc010_pio_read(host, data->dest,
data->blocksize * data->blocks);
} else if (data && (data->flags & MMC_DATA_WRITE)) {
ftsdc010_pio_write(host, data->src,
data->blocksize * data->blocks);
}
/* pio check response status */
ret = ftsdc010_pio_check_status(mmc, cmd, data);
if (!ret) {
/* if it is long response */
if (ccon & FTSDC010_CMD_LONG_RSP) {
cmd->response[0] = readl(&host->reg->rsp3);
cmd->response[1] = readl(&host->reg->rsp2);
cmd->response[2] = readl(&host->reg->rsp1);
cmd->response[3] = readl(&host->reg->rsp0);
} else {
cmd->response[0] = readl(&host->reg->rsp0);
}
}
udelay(FTSDC010_DELAY_UNIT);
return ret;
}
static unsigned int cal_blksz(unsigned int blksz)
{
unsigned int blksztwo = 0;
while (blksz >>= 1)
blksztwo++;
return blksztwo;
}
static int ftsdc010_setup_data(struct mmc *mmc, struct mmc_data *data)
{
struct mmc_host *host = mmc->priv;
unsigned int dcon, newmask;
/* configure data transfer paramter */
if (!data)
return 0;
if (((data->blocksize - 1) & data->blocksize) != 0) {
printf("%s: can't do non-power-of 2 sized block transfers"
" (blksz %d)\n", __func__, data->blocksize);
return -1;
}
/*
* We cannot deal with unaligned blocks with more than
* one block being transfered.
*/
if ((data->blocksize <= 2) && (data->blocks > 1)) {
printf("%s: can't do non-word sized block transfers"
" (blksz %d)\n", __func__, data->blocksize);
return -1;
}
/* data length */
dcon = data->blocksize * data->blocks;
writel(dcon, &host->reg->dlr);
/* write data control */
dcon = cal_blksz(data->blocksize);
/* add to IMASK register */
newmask = (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT);
/*
* enable UNDERRUN will trigger interrupt immediatedly
* So setup it when rsp is received successfully
*/
if (data->flags & MMC_DATA_WRITE) {
dcon |= FTSDC010_DCR_DATA_WRITE;
} else {
dcon &= ~FTSDC010_DCR_DATA_WRITE;
newmask |= FTSDC010_STATUS_FIFO_ORUN;
}
enable_imask(host->reg, newmask);
#ifdef CONFIG_FTSDC010_SDIO
/* always reset fifo since last transfer may fail */
dcon |= FTSDC010_DCR_FIFO_RST;
/* handle sdio */
dcon = data->blocksize | data->blocks << 15;
if (data->blocks > 1)
dcon |= FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE;
#endif
/* enable data transfer which will be pended until cmd is send */
dcon |= FTSDC010_DCR_DATA_EN;
writel(dcon, &host->reg->dcr);
return 0;
}
static int ftsdc010_send_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
int ret;
if (data) {
ret = ftsdc010_setup_data(mmc, data);
if (ret) {
printf("%s: setup data error\n", __func__);
return -1;
}
if ((data->flags & MMC_DATA_BOTH_DIR) == MMC_DATA_BOTH_DIR) {
printf("%s: data is both direction\n", __func__);
return -1;
}
}
/* Send command */
ret = ftsdc010_send_cmd(mmc, cmd, data);
return ret;
}
static int ftsdc010_card_detect(struct mmc *mmc)
{
struct mmc_host *host = mmc->priv;
unsigned int sta;
sta = readl(&host->reg->status);
debug("%s: card status: %08x\n", __func__, sta);
return (sta & FTSDC010_STATUS_CARD_DETECT) ? 0 : 1;
}
static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
int ret;
if (ftsdc010_card_detect(mmc) == 0) {
printf("%s: no medium present\n", __func__);
return -1;
} else {
ret = ftsdc010_send_request(mmc, cmd, data);
return ret;
}
}
static void ftsdc010_set_clk(struct mmc *mmc)
{
struct mmc_host *host = mmc->priv;
unsigned char clk_div;
unsigned char real_rate;
unsigned int clock;
debug("%s: mmc_set_clock: %x\n", __func__, mmc->clock);
clock = readl(&host->reg->ccr);
if (mmc->clock == 0) {
real_rate = 0;
clock |= FTSDC010_CCR_CLK_DIS;
} else {
debug("%s, mmc->clock: %08x, origin clock: %08x\n",
__func__, mmc->clock, clock);
for (clk_div = 0; clk_div <= 127; clk_div++) {
real_rate = (CONFIG_SYS_CLK_FREQ / 2) /
(2 * (clk_div + 1));
if (real_rate <= mmc->clock)
break;
}
debug("%s: computed real_rete: %x, clk_div: %x\n",
__func__, real_rate, clk_div);
if (clk_div > 127)
debug("%s: no match clock rate, %x\n",
__func__, mmc->clock);
clock = (clock & ~FTSDC010_CCR_CLK_DIV(0x7f)) |
FTSDC010_CCR_CLK_DIV(clk_div);
clock &= ~FTSDC010_CCR_CLK_DIS;
}
debug("%s, set clock: %08x\n", __func__, clock);
writel(clock, &host->reg->ccr);
}
static void ftsdc010_set_ios(struct mmc *mmc)
{
struct mmc_host *host = mmc->priv;
unsigned int power;
unsigned long val;
unsigned int bus_width;
debug("%s: bus_width: %x, clock: %d\n",
__func__, mmc->bus_width, mmc->clock);
/* set pcr: power on */
power = readl(&host->reg->pcr);
power |= FTSDC010_PCR_POWER_ON;
writel(power, &host->reg->pcr);
if (mmc->clock)
ftsdc010_set_clk(mmc);
/* set bwr: bus width reg */
bus_width = readl(&host->reg->bwr);
bus_width &= ~(FTSDC010_BWR_WIDE_8_BUS | FTSDC010_BWR_WIDE_4_BUS |
FTSDC010_BWR_SINGLE_BUS);
if (mmc->bus_width == 8)
bus_width |= FTSDC010_BWR_WIDE_8_BUS;
else if (mmc->bus_width == 4)
bus_width |= FTSDC010_BWR_WIDE_4_BUS;
else
bus_width |= FTSDC010_BWR_SINGLE_BUS;
writel(bus_width, &host->reg->bwr);
/* set fifo depth */
val = readl(&host->reg->feature);
host->fifo_len = FTSDC010_FEATURE_FIFO_DEPTH(val) * 4; /* 4 bytes */
/* set data timeout register */
val = -1;
writel(val, &host->reg->dtr);
}
static void ftsdc010_reset(struct mmc_host *host)
{
unsigned int timeout;
/* Do SDC_RST: Software reset for all register */
writel(FTSDC010_CMD_SDC_RST, &host->reg->cmd);
host->clock = 0;
/* this hardware has no reset finish flag to read */
/* wait 100ms maximum */
timeout = 100;
/* hw clears the bit when it's done */
while (readl(&host->reg->dtr) != 0) {
if (timeout == 0) {
printf("%s: reset timeout error\n", __func__);
return;
}
timeout--;
udelay(10*FTSDC010_DELAY_UNIT);
}
}
static int ftsdc010_core_init(struct mmc *mmc)
{
struct mmc_host *host = mmc->priv;
unsigned int mask;
unsigned int major, minor, revision;
/* get hardware version */
host->version = readl(&host->reg->rev);
major = FTSDC010_REV_MAJOR(host->version);
minor = FTSDC010_REV_MINOR(host->version);
revision = FTSDC010_REV_REVISION(host->version);
printf("ftsdc010 hardware ver: %d_%d_r%d\n", major, minor, revision);
/* Interrupt MASK register init - mask all */
writel(0x0, &host->reg->int_mask);
mask = FTSDC010_INT_MASK_CMD_SEND |
FTSDC010_INT_MASK_DATA_END |
FTSDC010_INT_MASK_CARD_CHANGE;
#ifdef CONFIG_FTSDC010_SDIO
mask |= FTSDC010_INT_MASK_CP_READY |
FTSDC010_INT_MASK_CP_BUF_READY |
FTSDC010_INT_MASK_PLAIN_TEXT_READY |
FTSDC010_INT_MASK_SDIO_IRPT;
#endif
writel(mask, &host->reg->int_mask);
return 0;
}
int ftsdc010_mmc_init(int dev_index)
{
struct mmc *mmc;
struct mmc_host *host;
mmc = &ftsdc010_dev[dev_index];
sprintf(mmc->name, "FTSDC010 SD/MMC");
mmc->priv = &ftsdc010_host[dev_index];
mmc->send_cmd = ftsdc010_request;
mmc->set_ios = ftsdc010_set_ios;
mmc->init = ftsdc010_core_init;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = CONFIG_SYS_CLK_FREQ / 2 / (2*128);
mmc->f_max = CONFIG_SYS_CLK_FREQ / 2 / 2;
ftsdc010_host[dev_index].clock = 0;
ftsdc010_host[dev_index].reg = ftsdc010_get_base_mmc(dev_index);
mmc_register(mmc);
/* reset mmc */
host = (struct mmc_host *)mmc->priv;
ftsdc010_reset(host);
return 0;
}
|
1001-study-uboot
|
drivers/mmc/ftsdc010_esdhc.c
|
C
|
gpl3
| 16,261
|
/*
* (C) Copyright 2003
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <mmc.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <part.h>
#include <asm/io.h>
#include "pxa_mmc.h"
extern int fat_register_device(block_dev_desc_t * dev_desc, int part_no);
static block_dev_desc_t mmc_dev;
block_dev_desc_t *mmc_get_dev(int dev)
{
return ((block_dev_desc_t *) & mmc_dev);
}
/*
* FIXME needs to read cid and csd info to determine block size
* and other parameters
*/
static uchar mmc_buf[MMC_BLOCK_SIZE];
static uchar spec_ver;
static int mmc_ready = 0;
static int wide = 0;
static uint32_t *
/****************************************************/
mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
/****************************************************/
{
static uint32_t resp[4], a, b, c;
uint32_t status;
int i;
debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl,
cmdat | wide);
writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
writel(~MMC_I_MASK_CLK_IS_OFF, MMC_I_MASK);
while (!(readl(MMC_I_REG) & MMC_I_REG_CLK_IS_OFF))
;
writel(cmd, MMC_CMD);
writel(argh, MMC_ARGH);
writel(argl, MMC_ARGL);
writel(cmdat | wide, MMC_CMDAT);
writel(~MMC_I_MASK_END_CMD_RES, MMC_I_MASK);
writel(MMC_STRPCL_START_CLK, MMC_STRPCL);
while (!(readl(MMC_I_REG) & MMC_I_REG_END_CMD_RES))
;
status = readl(MMC_STAT);
debug("MMC status 0x%08x\n", status);
if (status & MMC_STAT_TIME_OUT_RESPONSE) {
return 0;
}
/* Linux says:
* Did I mention this is Sick. We always need to
* discard the upper 8 bits of the first 16-bit word.
*/
a = (readl(MMC_RES) & 0xffff);
for (i = 0; i < 4; i++) {
b = (readl(MMC_RES) & 0xffff);
c = (readl(MMC_RES) & 0xffff);
resp[i] = (a << 24) | (b << 8) | (c >> 8);
a = c;
debug("MMC resp[%d] = %#08x\n", i, resp[i]);
}
return resp;
}
int
/****************************************************/
mmc_block_read(uchar * dst, uint32_t src, int len)
/****************************************************/
{
ushort argh, argl;
ulong status;
if (len == 0) {
return 0;
}
debug("mmc_block_rd dst %p src %08x len %d\n", dst, src, len);
argh = len >> 16;
argl = len & 0xffff;
/* set block len */
mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
/* send read command */
argh = src >> 16;
argl = src & 0xffff;
writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
writel(0xffff, MMC_RDTO);
writel(1, MMC_NOB);
writel(len, MMC_BLKLEN);
mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl,
MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK |
MMC_CMDAT_DATA_EN);
writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK);
while (len) {
if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) {
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
int i;
for (i = min(len, 32); i; i--) {
*dst++ = readb(MMC_RXFIFO);
len--;
}
#else
*dst++ = readb(MMC_RXFIFO);
len--;
#endif
}
status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
}
}
writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
;
status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
}
return 0;
}
int
/****************************************************/
mmc_block_write(ulong dst, uchar * src, int len)
/****************************************************/
{
ushort argh, argl;
ulong status;
if (len == 0) {
return 0;
}
debug("mmc_block_wr dst %lx src %lx len %d\n", dst, (ulong) src, len);
argh = len >> 16;
argl = len & 0xffff;
/* set block len */
mmc_cmd(MMC_CMD_SET_BLOCKLEN, argh, argl, MMC_CMDAT_R1);
/* send write command */
argh = dst >> 16;
argl = dst & 0xffff;
writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL);
writel(1, MMC_NOB);
writel(len, MMC_BLKLEN);
mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl,
MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK |
MMC_CMDAT_DATA_EN);
writel(~MMC_I_MASK_TXFIFO_WR_REQ, MMC_I_MASK);
while (len) {
if (readl(MMC_I_REG) & MMC_I_REG_TXFIFO_WR_REQ) {
int i, bytes = min(32, len);
for (i = 0; i < bytes; i++) {
writel(*src++, MMC_TXFIFO);
}
if (bytes < 32) {
writel(MMC_PRTBUF_BUF_PART_FULL, MMC_PRTBUF);
}
len -= bytes;
}
status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
}
}
writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK);
while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE))
;
writel(~MMC_I_MASK_PRG_DONE, MMC_I_MASK);
while (!(readl(MMC_I_REG) & MMC_I_REG_PRG_DONE))
;
status = readl(MMC_STAT);
if (status & MMC_STAT_ERRORS) {
printf("MMC_STAT error %lx\n", status);
return -1;
}
return 0;
}
int
/****************************************************/
pxa_mmc_read(long src, uchar * dst, int size)
/****************************************************/
{
ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
ulong mmc_block_size, mmc_block_address;
if (size == 0) {
return 0;
}
if (!mmc_ready) {
printf("Please initial the MMC first\n");
return -1;
}
mmc_block_size = MMC_BLOCK_SIZE;
mmc_block_address = ~(mmc_block_size - 1);
src -= CONFIG_SYS_MMC_BASE;
end = src + size;
part_start = ~mmc_block_address & src;
part_end = ~mmc_block_address & end;
aligned_start = mmc_block_address & src;
aligned_end = mmc_block_address & end;
/* all block aligned accesses */
debug
("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong) dst, end, part_start, part_end, aligned_start,
aligned_end);
if (part_start) {
part_len = mmc_block_size - part_start;
debug
("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong) dst, end, part_start, part_end, aligned_start,
aligned_end);
if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) <
0) {
return -1;
}
memcpy(dst, mmc_buf + part_start, part_len);
dst += part_len;
src += part_len;
}
debug
("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong) dst, end, part_start, part_end, aligned_start,
aligned_end);
for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
debug
("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong) dst, end, part_start, part_end, aligned_start,
aligned_end);
if ((mmc_block_read((uchar *) (dst), src, mmc_block_size)) < 0) {
return -1;
}
}
debug
("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong) dst, end, part_start, part_end, aligned_start,
aligned_end);
if (part_end && src < end) {
debug
("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, (ulong) dst, end, part_start, part_end, aligned_start,
aligned_end);
if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
return -1;
}
memcpy(dst, mmc_buf, part_end);
}
return 0;
}
int
/****************************************************/
pxa_mmc_write(uchar * src, uint32_t dst, int size)
/****************************************************/
{
ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
ulong mmc_block_size, mmc_block_address;
if (size == 0) {
return 0;
}
if (!mmc_ready) {
printf("Please initial the MMC first\n");
return -1;
}
mmc_block_size = MMC_BLOCK_SIZE;
mmc_block_address = ~(mmc_block_size - 1);
dst -= CONFIG_SYS_MMC_BASE;
end = dst + size;
part_start = ~mmc_block_address & dst;
part_end = ~mmc_block_address & end;
aligned_start = mmc_block_address & dst;
aligned_end = mmc_block_address & end;
/* all block aligned accesses */
debug
("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if (part_start) {
part_len = mmc_block_size - part_start;
debug
("ps src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) <
0) {
return -1;
}
memcpy(mmc_buf + part_start, src, part_len);
if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) <
0) {
return -1;
}
dst += part_len;
src += part_len;
}
debug
("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, dst, end, part_start, part_end, aligned_start,
aligned_end);
for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
debug
("al src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if ((mmc_block_write(dst, (uchar *) src, mmc_block_size)) < 0) {
return -1;
}
}
debug
("src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if (part_end && dst < end) {
debug
("pe src %p dst %08x end %lx pstart %lx pend %lx astart %lx aend %lx\n",
src, dst, end, part_start, part_end, aligned_start,
aligned_end);
if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
return -1;
}
memcpy(mmc_buf, src, part_end);
if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
return -1;
}
}
return 0;
}
static ulong
/****************************************************/
mmc_bread(int dev_num, ulong blknr, lbaint_t blkcnt, void *dst)
/****************************************************/
{
int mmc_block_size = MMC_BLOCK_SIZE;
ulong src = blknr * mmc_block_size + CONFIG_SYS_MMC_BASE;
pxa_mmc_read(src, (uchar *) dst, blkcnt * mmc_block_size);
return blkcnt;
}
#ifdef __GNUC__
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#else
#define likely(x) (x)
#define unlikely(x) (x)
#endif
#define UNSTUFF_BITS(resp,start,size) \
({ \
const int __size = size; \
const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \
const int32_t __off = 3 - ((start) / 32); \
const int32_t __shft = (start) & 31; \
uint32_t __res; \
\
__res = resp[__off] >> __shft; \
if (__size + __shft > 32) \
__res |= resp[__off-1] << ((32 - __shft) % 32); \
__res & __mask; \
})
/*
* Given the decoded CSD structure, decode the raw CID to our CID structure.
*/
static void mmc_decode_cid(uint32_t * resp)
{
if (IF_TYPE_SD == mmc_dev.if_type) {
/*
* SD doesn't currently have a version field so we will
* have to assume we can parse this.
*/
sprintf((char *)mmc_dev.vendor,
"Man %02x OEM %c%c \"%c%c%c%c%c\" Date %02u/%04u",
UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp, 112, 8),
UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp, 96, 8),
UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp, 80, 8),
UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp, 64, 8),
UNSTUFF_BITS(resp, 8, 4), UNSTUFF_BITS(resp, 12,
8) + 2000);
sprintf((char *)mmc_dev.revision, "%d.%d",
UNSTUFF_BITS(resp, 60, 4), UNSTUFF_BITS(resp, 56, 4));
sprintf((char *)mmc_dev.product, "%u",
UNSTUFF_BITS(resp, 24, 32));
} else {
/*
* The selection of the format here is based upon published
* specs from sandisk and from what people have reported.
*/
switch (spec_ver) {
case 0: /* MMC v1.0 - v1.2 */
case 1: /* MMC v1.4 */
sprintf((char *)mmc_dev.vendor,
"Man %02x%02x%02x \"%c%c%c%c%c%c%c\" Date %02u/%04u",
UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp,
112,
8),
UNSTUFF_BITS(resp, 104, 8), UNSTUFF_BITS(resp,
96, 8),
UNSTUFF_BITS(resp, 88, 8), UNSTUFF_BITS(resp,
80, 8),
UNSTUFF_BITS(resp, 72, 8), UNSTUFF_BITS(resp,
64, 8),
UNSTUFF_BITS(resp, 56, 8), UNSTUFF_BITS(resp,
48, 8),
UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8,
4) +
1997);
sprintf((char *)mmc_dev.revision, "%d.%d",
UNSTUFF_BITS(resp, 44, 4), UNSTUFF_BITS(resp,
40, 4));
sprintf((char *)mmc_dev.product, "%u",
UNSTUFF_BITS(resp, 16, 24));
break;
case 2: /* MMC v2.0 - v2.2 */
case 3: /* MMC v3.1 - v3.3 */
case 4: /* MMC v4 */
sprintf((char *)mmc_dev.vendor,
"Man %02x OEM %04x \"%c%c%c%c%c%c\" Date %02u/%04u",
UNSTUFF_BITS(resp, 120, 8), UNSTUFF_BITS(resp,
104,
16),
UNSTUFF_BITS(resp, 96, 8), UNSTUFF_BITS(resp,
88, 8),
UNSTUFF_BITS(resp, 80, 8), UNSTUFF_BITS(resp,
72, 8),
UNSTUFF_BITS(resp, 64, 8), UNSTUFF_BITS(resp,
56, 8),
UNSTUFF_BITS(resp, 12, 4), UNSTUFF_BITS(resp, 8,
4) +
1997);
sprintf((char *)mmc_dev.product, "%u",
UNSTUFF_BITS(resp, 16, 32));
sprintf((char *)mmc_dev.revision, "N/A");
break;
default:
printf("MMC card has unknown MMCA version %d\n",
spec_ver);
break;
}
}
printf("%s card.\nVendor: %s\nProduct: %s\nRevision: %s\n",
(IF_TYPE_SD == mmc_dev.if_type) ? "SD" : "MMC", mmc_dev.vendor,
mmc_dev.product, mmc_dev.revision);
}
/*
* Given a 128-bit response, decode to our card CSD structure.
*/
static void mmc_decode_csd(uint32_t * resp)
{
unsigned int mult, csd_struct;
if (IF_TYPE_SD == mmc_dev.if_type) {
csd_struct = UNSTUFF_BITS(resp, 126, 2);
if (csd_struct != 0) {
printf("SD: unrecognised CSD structure version %d\n",
csd_struct);
return;
}
} else {
/*
* We only understand CSD structure v1.1 and v1.2.
* v1.2 has extra information in bits 15, 11 and 10.
*/
csd_struct = UNSTUFF_BITS(resp, 126, 2);
if (csd_struct != 1 && csd_struct != 2) {
printf("MMC: unrecognised CSD structure version %d\n",
csd_struct);
return;
}
spec_ver = UNSTUFF_BITS(resp, 122, 4);
mmc_dev.if_type = IF_TYPE_MMC;
}
mult = 1 << (UNSTUFF_BITS(resp, 47, 3) + 2);
mmc_dev.lba = (1 + UNSTUFF_BITS(resp, 62, 12)) * mult;
mmc_dev.blksz = 1 << UNSTUFF_BITS(resp, 80, 4);
/* FIXME: The following just makes assumes that's the partition type -- should really read it */
mmc_dev.part_type = PART_TYPE_DOS;
mmc_dev.dev = 0;
mmc_dev.lun = 0;
mmc_dev.type = DEV_TYPE_HARDDISK;
mmc_dev.removable = 0;
mmc_dev.block_read = mmc_bread;
printf("Detected: %lu blocks of %lu bytes (%luMB) ",
mmc_dev.lba,
mmc_dev.blksz,
mmc_dev.lba * mmc_dev.blksz / (1024 * 1024));
}
int
/****************************************************/
mmc_legacy_init(int verbose)
/****************************************************/
{
int retries, rc = -ENODEV;
uint32_t cid_resp[4];
uint32_t *resp;
uint16_t rca = 0;
/* Reset device interface type */
mmc_dev.if_type = IF_TYPE_UNKNOWN;
#ifdef CONFIG_CPU_MONAHANS /* pxa3xx */
writel(readl(CKENA) | CKENA_12_MMC0 | CKENA_13_MMC1, CKENA);
#else /* pxa2xx */
writel(readl(CKEN) | CKEN12_MMC, CKEN); /* enable MMC unit clock */
#endif
writel(MMC_CLKRT_0_3125MHZ, MMC_CLKRT);
writel(MMC_RES_TO_MAX, MMC_RESTO);
writel(MMC_SPI_DISABLE, MMC_SPI);
/* reset */
mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0);
udelay(200000);
retries = 3;
while (retries--) {
resp = mmc_cmd(MMC_CMD_APP_CMD, 0, 0, MMC_CMDAT_R1);
if (!(resp[0] & 0x00000020)) { /* Card does not support APP_CMD */
debug("Card does not support APP_CMD\n");
break;
}
/* Select 3.2-3.3V and 3.3-3.4V */
resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0030, 0x0000,
MMC_CMDAT_R3 | (retries < 2 ? 0
: MMC_CMDAT_INIT));
if (resp[0] & 0x80000000) {
mmc_dev.if_type = IF_TYPE_SD;
debug("Detected SD card\n");
break;
}
udelay(200000);
}
if (retries <= 0 || !(IF_TYPE_SD == mmc_dev.if_type)) {
debug("Failed to detect SD Card, trying MMC\n");
resp =
mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000, MMC_CMDAT_R3);
retries = 10;
while (retries-- && resp && !(resp[0] & 0x80000000)) {
udelay(200000);
resp =
mmc_cmd(MMC_CMD_SEND_OP_COND, 0x00ff, 0x8000,
MMC_CMDAT_R3);
}
}
/* try to get card id */
resp =
mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, 0, MMC_CMDAT_R2 | MMC_CMDAT_BUSY);
if (resp) {
memcpy(cid_resp, resp, sizeof(cid_resp));
/* MMC exists, get CSD too */
resp = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, 0, 0, MMC_CMDAT_R1);
if (IF_TYPE_SD == mmc_dev.if_type)
rca = ((resp[0] & 0xffff0000) >> 16);
resp = mmc_cmd(MMC_CMD_SEND_CSD, rca, 0, MMC_CMDAT_R2);
if (resp) {
mmc_decode_csd(resp);
rc = 0;
mmc_ready = 1;
}
mmc_decode_cid(cid_resp);
}
writel(0, MMC_CLKRT); /* 20 MHz */
resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
if (IF_TYPE_SD == mmc_dev.if_type) {
resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1);
resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1);
wide = MMC_CMDAT_SD_4DAT;
}
#endif
fat_register_device(&mmc_dev, 1); /* partitions start counting with 1 */
return rc;
}
|
1001-study-uboot
|
drivers/mmc/pxa_mmc.c
|
C
|
gpl3
| 17,934
|
/*
* Copyright (C) 2010
* Rob Emanuele <rob@emanuele.us>
* Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
*
* Original Driver:
* Copyright (C) 2004-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include "atmel_mci.h"
#ifndef CONFIG_SYS_MMC_CLK_OD
# define CONFIG_SYS_MMC_CLK_OD 150000
#endif
#define MMC_DEFAULT_BLKLEN 512
#if defined(CONFIG_ATMEL_MCI_PORTB)
# define MCI_BUS 1
#else
# define MCI_BUS 0
#endif
static int initialized = 0;
/*
* Print command and status:
*
* - always when DEBUG is defined
* - on command errors
*/
static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
{
printf("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
cmdr, cmdr&0x3F, arg, status, msg);
}
/* Setup for MCI Clock and Block Size */
static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
{
atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
u32 bus_hz = get_mci_clk_rate();
u32 clkdiv = 255;
debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
bus_hz, hz, blklen);
if (hz > 0) {
/* find lowest clkdiv yielding a rate <= than requested */
for (clkdiv=0; clkdiv<255; clkdiv++) {
if ((bus_hz / (clkdiv+1) / 2) <= hz)
break;
}
}
printf("mci: setting clock %u Hz, block size %u\n",
(bus_hz / (clkdiv+1)) / 2, blklen);
blklen &= 0xfffc;
/* On some platforms RDPROOF and WRPROOF are ignored */
writel((MMCI_BF(CLKDIV, clkdiv)
| MMCI_BF(BLKLEN, blklen)
| MMCI_BIT(RDPROOF)
| MMCI_BIT(WRPROOF)), &mci->mr);
initialized = 1;
}
/* Return the CMDR with flags for a given command and data packet */
static u32 mci_encode_cmd(
struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
{
u32 cmdr = 0;
/* Default Flags for Errors */
*error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
MMCI_BIT(RINDE) | MMCI_BIT(RTOE));
/* Default Flags for the Command */
cmdr |= MMCI_BIT(MAXLAT);
if (data) {
cmdr |= MMCI_BF(TRCMD, 1);
if (data->blocks > 1)
cmdr |= MMCI_BF(TRTYP, 1);
if (data->flags & MMC_DATA_READ)
cmdr |= MMCI_BIT(TRDIR);
}
if (cmd->resp_type & MMC_RSP_CRC)
*error_flags |= MMCI_BIT(RCRCE);
if (cmd->resp_type & MMC_RSP_136)
cmdr |= MMCI_BF(RSPTYP, 2);
else if (cmd->resp_type & MMC_RSP_BUSY)
cmdr |= MMCI_BF(RSPTYP, 3);
else if (cmd->resp_type & MMC_RSP_PRESENT)
cmdr |= MMCI_BF(RSPTYP, 1);
return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
}
/* Entered into function pointer in mci_send_cmd */
static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
{
u32 status;
do {
status = readl(&mci->sr);
if (status & (error_flags | MMCI_BIT(OVRE)))
goto io_fail;
} while (!(status & MMCI_BIT(RXRDY)));
if (status & MMCI_BIT(RXRDY)) {
*data = readl(&mci->rdr);
status = 0;
}
io_fail:
return status;
}
/* Entered into function pointer in mci_send_cmd */
static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
{
u32 status;
do {
status = readl(&mci->sr);
if (status & (error_flags | MMCI_BIT(UNRE)))
goto io_fail;
} while (!(status & MMCI_BIT(TXRDY)));
if (status & MMCI_BIT(TXRDY)) {
writel(*data, &mci->tdr);
status = 0;
}
io_fail:
return status;
}
/*
* Entered into mmc structure during driver init
*
* Sends a command out on the bus and deals with the block data.
* Takes the mmc pointer, a command pointer, and an optional data pointer.
*/
static int
mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
u32 cmdr;
u32 error_flags = 0;
u32 status;
if (!initialized) {
puts ("MCI not initialized!\n");
return COMM_ERR;
}
/* Figure out the transfer arguments */
cmdr = mci_encode_cmd(cmd, data, &error_flags);
/* Send the command */
writel(cmd->cmdarg, &mci->argr);
writel(cmdr, &mci->cmdr);
#ifdef DEBUG
dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
#endif
/* Wait for the command to complete */
while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
if (status & error_flags) {
dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
return COMM_ERR;
}
/* Copy the response to the response buffer */
if (cmd->resp_type & MMC_RSP_136) {
cmd->response[0] = readl(&mci->rspr);
cmd->response[1] = readl(&mci->rspr1);
cmd->response[2] = readl(&mci->rspr2);
cmd->response[3] = readl(&mci->rspr3);
} else
cmd->response[0] = readl(&mci->rspr);
/* transfer all of the blocks */
if (data) {
u32 word_count, block_count;
u32* ioptr;
u32 sys_blocksize, dummy, i;
u32 (*mci_data_op)
(atmel_mci_t *mci, u32* data, u32 error_flags);
if (data->flags & MMC_DATA_READ) {
mci_data_op = mci_data_read;
sys_blocksize = mmc->read_bl_len;
ioptr = (u32*)data->dest;
} else {
mci_data_op = mci_data_write;
sys_blocksize = mmc->write_bl_len;
ioptr = (u32*)data->src;
}
status = 0;
for (block_count = 0;
block_count < data->blocks && !status;
block_count++) {
word_count = 0;
do {
status = mci_data_op(mci, ioptr, error_flags);
word_count++;
ioptr++;
} while (!status && word_count < (data->blocksize/4));
#ifdef DEBUG
if (data->flags & MMC_DATA_READ)
{
printf("Read Data:\n");
print_buffer(0, data->dest, 1,
word_count*4, 0);
}
#endif
#ifdef DEBUG
if (!status && word_count < (sys_blocksize / 4))
printf("filling rest of block...\n");
#endif
/* fill the rest of a full block */
while (!status && word_count < (sys_blocksize / 4)) {
status = mci_data_op(mci, &dummy,
error_flags);
word_count++;
}
if (status) {
dump_cmd(cmdr, cmd->cmdarg, status,
"Data Transfer Failed");
return COMM_ERR;
}
}
/* Wait for Transfer End */
i = 0;
do {
status = readl(&mci->sr);
if (status & error_flags) {
dump_cmd(cmdr, cmd->cmdarg, status,
"DTIP Wait Failed");
return COMM_ERR;
}
i++;
} while ((status & MMCI_BIT(DTIP)) && i < 10000);
if (status & MMCI_BIT(DTIP)) {
dump_cmd(cmdr, cmd->cmdarg, status,
"XFER DTIP never unset, ignoring");
}
}
return 0;
}
/* Entered into mmc structure during driver init */
static void mci_set_ios(struct mmc *mmc)
{
atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
int busw = (mmc->bus_width == 4) ? 1 : 0;
/* Set the clock speed */
mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
/*
* set the bus width and select slot for this interface
* there is no capability for multiple slots on the same interface yet
* Bitfield SCDBUS needs to be expanded to 2 bits for 8-bit buses
*/
writel(MMCI_BF(SCDBUS, busw) | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
}
/* Entered into mmc structure during driver init */
static int mci_init(struct mmc *mmc)
{
atmel_mci_t *mci = (atmel_mci_t *)mmc->priv;
/* Initialize controller */
writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
/* Initial Time-outs */
writel(0x5f, &mci->dtor);
/* Disable Interrupts */
writel(~0UL, &mci->idr);
/* Set default clocks and blocklen */
mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
return 0;
}
/*
* This is the only exported function
*
* Call it with the MCI register base address
*/
int atmel_mci_init(void *regs)
{
struct mmc *mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -1;
strcpy(mmc->name, "mci");
mmc->priv = regs;
mmc->send_cmd = mci_send_cmd;
mmc->set_ios = mci_set_ios;
mmc->init = mci_init;
/* need to be able to pass these in on a board by board basis */
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT;
/*
* min and max frequencies determined by
* max and min of clock divider
*/
mmc->f_min = get_mci_clk_rate() / (2*256);
mmc->f_max = get_mci_clk_rate() / (2*1);
mmc->b_max = 0;
mmc_register(mmc);
return 0;
}
|
1001-study-uboot
|
drivers/mmc/gen_atmel_mci.c
|
C
|
gpl3
| 8,882
|
/*
* Copyright (C) 2005-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CPU_AT32AP_ATMEL_MCI_H__
#define __CPU_AT32AP_ATMEL_MCI_H__
#ifndef __ASSEMBLY__
/*
* Structure for struct SoC access.
* Names starting with '_' are fillers.
*/
typedef struct atmel_mci {
/* reg Offset */
u32 cr; /* 0x00 */
u32 mr; /* 0x04 */
u32 dtor; /* 0x08 */
u32 sdcr; /* 0x0c */
u32 argr; /* 0x10 */
u32 cmdr; /* 0x14 */
u32 _18; /* 0x18 */
u32 _1c; /* 0x1c */
u32 rspr; /* 0x20 */
u32 rspr1; /* 0x24 */
u32 rspr2; /* 0x28 */
u32 rspr3; /* 0x2c */
u32 rdr; /* 0x30 */
u32 tdr; /* 0x34 */
u32 _38; /* 0x38 */
u32 _3c; /* 0x3c */
u32 sr; /* 0x40 */
u32 ier; /* 0x44 */
u32 idr; /* 0x48 */
u32 imr; /* 0x4c */
} atmel_mci_t;
#endif /* __ASSEMBLY__ */
/*
* NOTICE: Use of registers offsets is depreciated.
* These defines will be removed once the old driver
* is taken out of commision.
*
* Atmel MultiMedia Card Interface (MCI) registers
*/
#define MMCI_CR 0x0000
#define MMCI_MR 0x0004
#define MMCI_DTOR 0x0008
#define MMCI_SDCR 0x000c
#define MMCI_ARGR 0x0010
#define MMCI_CMDR 0x0014
#define MMCI_RSPR 0x0020
#define MMCI_RSPR1 0x0024
#define MMCI_RSPR2 0x0028
#define MMCI_RSPR3 0x002c
#define MMCI_RDR 0x0030
#define MMCI_TDR 0x0034
#define MMCI_SR 0x0040
#define MMCI_IER 0x0044
#define MMCI_IDR 0x0048
#define MMCI_IMR 0x004c
/* Bitfields in CR */
#define MMCI_MCIEN_OFFSET 0
#define MMCI_MCIEN_SIZE 1
#define MMCI_MCIDIS_OFFSET 1
#define MMCI_MCIDIS_SIZE 1
#define MMCI_PWSEN_OFFSET 2
#define MMCI_PWSEN_SIZE 1
#define MMCI_PWSDIS_OFFSET 3
#define MMCI_PWSDIS_SIZE 1
#define MMCI_SWRST_OFFSET 7
#define MMCI_SWRST_SIZE 1
/* Bitfields in MR */
#define MMCI_CLKDIV_OFFSET 0
#define MMCI_CLKDIV_SIZE 8
#define MMCI_PWSDIV_OFFSET 8
#define MMCI_PWSDIV_SIZE 3
#define MMCI_RDPROOF_OFFSET 11
#define MMCI_RDPROOF_SIZE 1
#define MMCI_WRPROOF_OFFSET 12
#define MMCI_WRPROOF_SIZE 1
#define MMCI_PDCPADV_OFFSET 14
#define MMCI_PDCPADV_SIZE 1
#define MMCI_PDCMODE_OFFSET 15
#define MMCI_PDCMODE_SIZE 1
#define MMCI_BLKLEN_OFFSET 16
#define MMCI_BLKLEN_SIZE 16
/* Bitfields in DTOR */
#define MMCI_DTOCYC_OFFSET 0
#define MMCI_DTOCYC_SIZE 4
#define MMCI_DTOMUL_OFFSET 4
#define MMCI_DTOMUL_SIZE 3
/* Bitfields in SDCR */
#define MMCI_SCDSEL_OFFSET 0
#define MMCI_SCDSEL_SIZE 4
#define MMCI_SCDBUS_OFFSET 7
#define MMCI_SCDBUS_SIZE 1
/* Bitfields in ARGR */
#define MMCI_ARG_OFFSET 0
#define MMCI_ARG_SIZE 32
/* Bitfields in CMDR */
#define MMCI_CMDNB_OFFSET 0
#define MMCI_CMDNB_SIZE 6
#define MMCI_RSPTYP_OFFSET 6
#define MMCI_RSPTYP_SIZE 2
#define MMCI_SPCMD_OFFSET 8
#define MMCI_SPCMD_SIZE 3
#define MMCI_OPDCMD_OFFSET 11
#define MMCI_OPDCMD_SIZE 1
#define MMCI_MAXLAT_OFFSET 12
#define MMCI_MAXLAT_SIZE 1
#define MMCI_TRCMD_OFFSET 16
#define MMCI_TRCMD_SIZE 2
#define MMCI_TRDIR_OFFSET 18
#define MMCI_TRDIR_SIZE 1
#define MMCI_TRTYP_OFFSET 19
#define MMCI_TRTYP_SIZE 2
/* Bitfields in RSPRx */
#define MMCI_RSP_OFFSET 0
#define MMCI_RSP_SIZE 32
/* Bitfields in SR/IER/IDR/IMR */
#define MMCI_CMDRDY_OFFSET 0
#define MMCI_CMDRDY_SIZE 1
#define MMCI_RXRDY_OFFSET 1
#define MMCI_RXRDY_SIZE 1
#define MMCI_TXRDY_OFFSET 2
#define MMCI_TXRDY_SIZE 1
#define MMCI_BLKE_OFFSET 3
#define MMCI_BLKE_SIZE 1
#define MMCI_DTIP_OFFSET 4
#define MMCI_DTIP_SIZE 1
#define MMCI_NOTBUSY_OFFSET 5
#define MMCI_NOTBUSY_SIZE 1
#define MMCI_ENDRX_OFFSET 6
#define MMCI_ENDRX_SIZE 1
#define MMCI_ENDTX_OFFSET 7
#define MMCI_ENDTX_SIZE 1
#define MMCI_RXBUFF_OFFSET 14
#define MMCI_RXBUFF_SIZE 1
#define MMCI_TXBUFE_OFFSET 15
#define MMCI_TXBUFE_SIZE 1
#define MMCI_RINDE_OFFSET 16
#define MMCI_RINDE_SIZE 1
#define MMCI_RDIRE_OFFSET 17
#define MMCI_RDIRE_SIZE 1
#define MMCI_RCRCE_OFFSET 18
#define MMCI_RCRCE_SIZE 1
#define MMCI_RENDE_OFFSET 19
#define MMCI_RENDE_SIZE 1
#define MMCI_RTOE_OFFSET 20
#define MMCI_RTOE_SIZE 1
#define MMCI_DCRCE_OFFSET 21
#define MMCI_DCRCE_SIZE 1
#define MMCI_DTOE_OFFSET 22
#define MMCI_DTOE_SIZE 1
#define MMCI_OVRE_OFFSET 30
#define MMCI_OVRE_SIZE 1
#define MMCI_UNRE_OFFSET 31
#define MMCI_UNRE_SIZE 1
/* Constants for DTOMUL */
#define MMCI_DTOMUL_1_CYCLE 0
#define MMCI_DTOMUL_16_CYCLES 1
#define MMCI_DTOMUL_128_CYCLES 2
#define MMCI_DTOMUL_256_CYCLES 3
#define MMCI_DTOMUL_1024_CYCLES 4
#define MMCI_DTOMUL_4096_CYCLES 5
#define MMCI_DTOMUL_65536_CYCLES 6
#define MMCI_DTOMUL_1048576_CYCLES 7
/* Constants for RSPTYP */
#define MMCI_RSPTYP_NO_RESP 0
#define MMCI_RSPTYP_48_BIT_RESP 1
#define MMCI_RSPTYP_136_BIT_RESP 2
/* Constants for SPCMD */
#define MMCI_SPCMD_NO_SPEC_CMD 0
#define MMCI_SPCMD_INIT_CMD 1
#define MMCI_SPCMD_SYNC_CMD 2
#define MMCI_SPCMD_INT_CMD 4
#define MMCI_SPCMD_INT_RESP 5
/* Constants for TRCMD */
#define MMCI_TRCMD_NO_TRANS 0
#define MMCI_TRCMD_START_TRANS 1
#define MMCI_TRCMD_STOP_TRANS 2
/* Constants for TRTYP */
#define MMCI_TRTYP_BLOCK 0
#define MMCI_TRTYP_MULTI_BLOCK 1
#define MMCI_TRTYP_STREAM 2
/* Bit manipulation macros */
#define MMCI_BIT(name) \
(1 << MMCI_##name##_OFFSET)
#define MMCI_BF(name,value) \
(((value) & ((1 << MMCI_##name##_SIZE) - 1)) \
<< MMCI_##name##_OFFSET)
#define MMCI_BFEXT(name,value) \
(((value) >> MMCI_##name##_OFFSET)\
& ((1 << MMCI_##name##_SIZE) - 1))
#define MMCI_BFINS(name,value,old) \
(((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \
<< MMCI_##name##_OFFSET)) \
| MMCI_BF(name,value))
/*
* NOTICE: Use of registers offsets is depreciated.
* These defines will be removed once the old driver
* is taken out of commision.
*
* Register access macros
*/
#define mmci_readl(reg) \
readl((void *)ATMEL_BASE_MMCI + MMCI_##reg)
#define mmci_writel(reg,value) \
writel((value), (void *)ATMEL_BASE_MMCI + MMCI_##reg)
#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */
|
1001-study-uboot
|
drivers/mmc/atmel_mci.h
|
C
|
gpl3
| 6,788
|
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Jaehoon Chung <jh80.chung@samsung.com>
* Portions Copyright 2011 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <mmc.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include "tegra2_mmc.h"
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
struct mmc_host mmc_host[4];
/**
* Get the host address and peripheral ID for a device. Devices are numbered
* from 0 to 3.
*
* @param host Structure to fill in (base, reg, mmc_id)
* @param dev_index Device index (0-3)
*/
static void tegra2_get_setup(struct mmc_host *host, int dev_index)
{
debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
switch (dev_index) {
case 1:
host->base = TEGRA2_SDMMC3_BASE;
host->mmc_id = PERIPH_ID_SDMMC3;
break;
case 2:
host->base = TEGRA2_SDMMC2_BASE;
host->mmc_id = PERIPH_ID_SDMMC2;
break;
case 3:
host->base = TEGRA2_SDMMC1_BASE;
host->mmc_id = PERIPH_ID_SDMMC1;
break;
case 0:
default:
host->base = TEGRA2_SDMMC4_BASE;
host->mmc_id = PERIPH_ID_SDMMC4;
break;
}
host->reg = (struct tegra2_mmc *)host->base;
}
static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
{
unsigned char ctrl;
debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
(u32)data->dest, data->blocks, data->blocksize);
writel((u32)data->dest, &host->reg->sysad);
/*
* DMASEL[4:3]
* 00 = Selects SDMA
* 01 = Reserved
* 10 = Selects 32-bit Address ADMA2
* 11 = Selects 64-bit Address ADMA2
*/
ctrl = readb(&host->reg->hostctl);
ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
writeb(ctrl, &host->reg->hostctl);
/* We do not handle DMA boundaries, so set it to max (512 KiB) */
writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
writew(data->blocks, &host->reg->blkcnt);
}
static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
{
unsigned short mode;
debug(" mmc_set_transfer_mode called\n");
/*
* TRNMOD
* MUL1SIN0[5] : Multi/Single Block Select
* RD1WT0[4] : Data Transfer Direction Select
* 1 = read
* 0 = write
* ENACMD12[2] : Auto CMD12 Enable
* ENBLKCNT[1] : Block Count Enable
* ENDMA[0] : DMA Enable
*/
mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
if (data->blocks > 1)
mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
if (data->flags & MMC_DATA_READ)
mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
writew(mode, &host->reg->trnmod);
}
static int mmc_wait_inhibit(struct mmc_host *host,
struct mmc_cmd *cmd,
struct mmc_data *data,
unsigned int timeout)
{
/*
* PRNSTS
* CMDINHDAT[1] : Command Inhibit (DAT)
* CMDINHCMD[0] : Command Inhibit (CMD)
*/
unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
/*
* We shouldn't wait for data inhibit for stop commands, even
* though they might use busy signaling
*/
if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
while (readl(&host->reg->prnsts) & mask) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return -1;
}
timeout--;
udelay(1000);
}
return 0;
}
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
int flags, i;
int result;
unsigned int mask;
unsigned int retry = 0x100000;
debug(" mmc_send_cmd called\n");
result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
if (result < 0)
return result;
if (data)
mmc_prepare_data(host, data);
debug("cmd->arg: %08x\n", cmd->cmdarg);
writel(cmd->cmdarg, &host->reg->argument);
if (data)
mmc_set_transfer_mode(host, data);
if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
return -1;
/*
* CMDREG
* CMDIDX[13:8] : Command index
* DATAPRNT[5] : Data Present Select
* ENCMDIDX[4] : Command Index Check Enable
* ENCMDCRC[3] : Command CRC Check Enable
* RSPTYP[1:0]
* 00 = No Response
* 01 = Length 136
* 10 = Length 48
* 11 = Length 48 Check busy after response
*/
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
else if (cmd->resp_type & MMC_RSP_136)
flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
else if (cmd->resp_type & MMC_RSP_BUSY)
flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
else
flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
if (cmd->resp_type & MMC_RSP_CRC)
flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
if (data)
flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
debug("cmd: %d\n", cmd->cmdidx);
writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
for (i = 0; i < retry; i++) {
mask = readl(&host->reg->norintsts);
/* Command Complete */
if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
if (!data)
writel(mask, &host->reg->norintsts);
break;
}
}
if (i == retry) {
printf("%s: waiting for status update\n", __func__);
return TIMEOUT;
}
if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
/* Timeout Error */
debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
return TIMEOUT;
} else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
/* Error Interrupt */
debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
return -1;
}
if (cmd->resp_type & MMC_RSP_PRESENT) {
if (cmd->resp_type & MMC_RSP_136) {
/* CRC is stripped so we need to do some shifting. */
for (i = 0; i < 4; i++) {
unsigned int offset =
(unsigned int)(&host->reg->rspreg3 - i);
cmd->response[i] = readl(offset) << 8;
if (i != 3) {
cmd->response[i] |=
readb(offset - 1);
}
debug("cmd->resp[%d]: %08x\n",
i, cmd->response[i]);
}
} else if (cmd->resp_type & MMC_RSP_BUSY) {
for (i = 0; i < retry; i++) {
/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
if (readl(&host->reg->prnsts)
& (1 << 20)) /* DAT[0] */
break;
}
if (i == retry) {
printf("%s: card is still busy\n", __func__);
return TIMEOUT;
}
cmd->response[0] = readl(&host->reg->rspreg0);
debug("cmd->resp[0]: %08x\n", cmd->response[0]);
} else {
cmd->response[0] = readl(&host->reg->rspreg0);
debug("cmd->resp[0]: %08x\n", cmd->response[0]);
}
}
if (data) {
unsigned long start = get_timer(0);
while (1) {
mask = readl(&host->reg->norintsts);
if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
/* Error Interrupt */
writel(mask, &host->reg->norintsts);
printf("%s: error during transfer: 0x%08x\n",
__func__, mask);
return -1;
} else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
/*
* DMA Interrupt, restart the transfer where
* it was interrupted.
*/
unsigned int address = readl(&host->reg->sysad);
debug("DMA end\n");
writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
&host->reg->norintsts);
writel(address, &host->reg->sysad);
} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
/* Transfer Complete */
debug("r/w is done\n");
break;
} else if (get_timer(start) > 2000UL) {
writel(mask, &host->reg->norintsts);
printf("%s: MMC Timeout\n"
" Interrupt status 0x%08x\n"
" Interrupt status enable 0x%08x\n"
" Interrupt signal enable 0x%08x\n"
" Present status 0x%08x\n",
__func__, mask,
readl(&host->reg->norintstsen),
readl(&host->reg->norintsigen),
readl(&host->reg->prnsts));
return -1;
}
}
writel(mask, &host->reg->norintsts);
}
udelay(1000);
return 0;
}
static void mmc_change_clock(struct mmc_host *host, uint clock)
{
int div;
unsigned short clk;
unsigned long timeout;
debug(" mmc_change_clock called\n");
/*
* Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
* PLLP_OUT0
*/
if (clock == 0)
goto out;
clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
&div);
debug("div = %d\n", div);
writew(0, &host->reg->clkcon);
/*
* CLKCON
* SELFREQ[15:8] : base clock divided by value
* ENSDCLK[2] : SD Clock Enable
* STBLINTCLK[1] : Internal Clock Stable
* ENINTCLK[0] : Internal Clock Enable
*/
div >>= 1;
clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
writew(clk, &host->reg->clkcon);
/* Wait max 10 ms */
timeout = 10;
while (!(readw(&host->reg->clkcon) &
TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return;
}
timeout--;
udelay(1000);
}
clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
writew(clk, &host->reg->clkcon);
debug("mmc_change_clock: clkcon = %08X\n", clk);
out:
host->clock = clock;
}
static void mmc_set_ios(struct mmc *mmc)
{
struct mmc_host *host = mmc->priv;
unsigned char ctrl;
debug(" mmc_set_ios called\n");
debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
/* Change clock first */
mmc_change_clock(host, mmc->clock);
ctrl = readb(&host->reg->hostctl);
/*
* WIDE8[5]
* 0 = Depend on WIDE4
* 1 = 8-bit mode
* WIDE4[1]
* 1 = 4-bit mode
* 0 = 1-bit mode
*/
if (mmc->bus_width == 8)
ctrl |= (1 << 5);
else if (mmc->bus_width == 4)
ctrl |= (1 << 1);
else
ctrl &= ~(1 << 1);
writeb(ctrl, &host->reg->hostctl);
debug("mmc_set_ios: hostctl = %08X\n", ctrl);
}
static void mmc_reset(struct mmc_host *host)
{
unsigned int timeout;
debug(" mmc_reset called\n");
/*
* RSTALL[0] : Software reset for all
* 1 = reset
* 0 = work
*/
writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
host->clock = 0;
/* Wait max 100 ms */
timeout = 100;
/* hw clears the bit when it's done */
while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return;
}
timeout--;
udelay(1000);
}
}
static int mmc_core_init(struct mmc *mmc)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
unsigned int mask;
debug(" mmc_core_init called\n");
mmc_reset(host);
host->version = readw(&host->reg->hcver);
debug("host version = %x\n", host->version);
/* mask all */
writel(0xffffffff, &host->reg->norintstsen);
writel(0xffffffff, &host->reg->norintsigen);
writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
/*
* NORMAL Interrupt Status Enable Register init
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
* [3] ENSTADMAINT : DMA boundary interrupt
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
* [0] ENSTACMDCMPLT : Command Complete Status Enable
*/
mask = readl(&host->reg->norintstsen);
mask &= ~(0xffff);
mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
writel(mask, &host->reg->norintstsen);
/*
* NORMAL Interrupt Signal Enable Register init
* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
*/
mask = readl(&host->reg->norintsigen);
mask &= ~(0xffff);
mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
writel(mask, &host->reg->norintsigen);
return 0;
}
int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
{
struct mmc_host *host;
char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
struct mmc *mmc;
debug(" tegra2_mmc_init: index %d, bus width %d "
"pwr_gpio %d cd_gpio %d\n",
dev_index, bus_width, pwr_gpio, cd_gpio);
host = &mmc_host[dev_index];
host->clock = 0;
host->pwr_gpio = pwr_gpio;
host->cd_gpio = cd_gpio;
tegra2_get_setup(host, dev_index);
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
if (host->pwr_gpio >= 0) {
sprintf(gpusage, "SD/MMC%d PWR", dev_index);
gpio_request(host->pwr_gpio, gpusage);
gpio_direction_output(host->pwr_gpio, 1);
}
if (host->cd_gpio >= 0) {
sprintf(gpusage, "SD/MMC%d CD", dev_index);
gpio_request(host->cd_gpio, gpusage);
gpio_direction_input(host->cd_gpio);
}
mmc = &mmc_dev[dev_index];
sprintf(mmc->name, "Tegra2 SD/MMC");
mmc->priv = host;
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
if (bus_width == 8)
mmc->host_caps = MMC_MODE_8BIT;
else
mmc->host_caps = MMC_MODE_4BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
/*
* min freq is for card identification, and is the highest
* low-speed SDIO card frequency (actually 400KHz)
* max freq is highest HS eMMC clock as per the SD/MMC spec
* (actually 52MHz)
* Both of these are the closest equivalents w/216MHz source
* clock and Tegra2 SDMMC divisors.
*/
mmc->f_min = 375000;
mmc->f_max = 48000000;
mmc_register(mmc);
return 0;
}
/* this is a weak define that we are overriding */
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
debug("board_mmc_getcd called\n");
*cd = 1; /* Assume card is inserted, or eMMC */
if (IS_SD(mmc)) {
if (host->cd_gpio >= 0) {
if (gpio_get_value(host->cd_gpio))
*cd = 0;
}
}
return 0;
}
|
1001-study-uboot
|
drivers/mmc/tegra2_mmc.c
|
C
|
gpl3
| 14,141
|
/*
* Copyright 2008, Freescale Semiconductor, Inc
* Andy Fleming
*
* Based vaguely on the Linux code
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <linux/list.h>
#include <div64.h>
/* Set block count limit because of 16 bit register limit on some hardware*/
#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
#endif
static struct list_head mmc_devices;
static int cur_dev_num = -1;
int __board_mmc_getcd(u8 *cd, struct mmc *mmc) {
return -1;
}
int board_mmc_getcd(u8 *cd, struct mmc *mmc)__attribute__((weak,
alias("__board_mmc_getcd")));
int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
#ifdef CONFIG_MMC_TRACE
int ret;
int i;
u8 *ptr;
printf("CMD_SEND:%d\n", cmd->cmdidx);
printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
printf("\t\tFLAG\t\t\t %d\n", cmd->flags);
ret = mmc->send_cmd(mmc, cmd, data);
switch (cmd->resp_type) {
case MMC_RSP_NONE:
printf("\t\tMMC_RSP_NONE\n");
break;
case MMC_RSP_R1:
printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
cmd->response[0]);
break;
case MMC_RSP_R1b:
printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
cmd->response[0]);
break;
case MMC_RSP_R2:
printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
cmd->response[0]);
printf("\t\t \t\t 0x%08X \n",
cmd->response[1]);
printf("\t\t \t\t 0x%08X \n",
cmd->response[2]);
printf("\t\t \t\t 0x%08X \n",
cmd->response[3]);
printf("\n");
printf("\t\t\t\t\tDUMPING DATA\n");
for (i = 0; i < 4; i++) {
int j;
printf("\t\t\t\t\t%03d - ", i*4);
ptr = &cmd->response[i];
ptr += 3;
for (j = 0; j < 4; j++)
printf("%02X ", *ptr--);
printf("\n");
}
break;
case MMC_RSP_R3:
printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
cmd->response[0]);
break;
default:
printf("\t\tERROR MMC rsp not supported\n");
break;
}
return ret;
#else
return mmc->send_cmd(mmc, cmd, data);
#endif
}
int mmc_send_status(struct mmc *mmc, int timeout)
{
struct mmc_cmd cmd;
int err;
#ifdef CONFIG_MMC_TRACE
int status;
#endif
cmd.cmdidx = MMC_CMD_SEND_STATUS;
cmd.resp_type = MMC_RSP_R1;
if (!mmc_host_is_spi(mmc))
cmd.cmdarg = mmc->rca << 16;
cmd.flags = 0;
do {
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
else if (cmd.response[0] & MMC_STATUS_RDY_FOR_DATA)
break;
udelay(1000);
if (cmd.response[0] & MMC_STATUS_MASK) {
printf("Status Error: 0x%08X\n", cmd.response[0]);
return COMM_ERR;
}
} while (timeout--);
#ifdef CONFIG_MMC_TRACE
status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
printf("CURR STATE:%d\n", status);
#endif
if (!timeout) {
printf("Timeout waiting card ready\n");
return TIMEOUT;
}
return 0;
}
int mmc_set_blocklen(struct mmc *mmc, int len)
{
struct mmc_cmd cmd;
cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = len;
cmd.flags = 0;
return mmc_send_cmd(mmc, &cmd, NULL);
}
struct mmc *find_mmc_device(int dev_num)
{
struct mmc *m;
struct list_head *entry;
list_for_each(entry, &mmc_devices) {
m = list_entry(entry, struct mmc, link);
if (m->block_dev.dev == dev_num)
return m;
}
printf("MMC Device %d not found\n", dev_num);
return NULL;
}
static ulong mmc_erase_t(struct mmc *mmc, ulong start, lbaint_t blkcnt)
{
struct mmc_cmd cmd;
ulong end;
int err, start_cmd, end_cmd;
if (mmc->high_capacity)
end = start + blkcnt - 1;
else {
end = (start + blkcnt - 1) * mmc->write_bl_len;
start *= mmc->write_bl_len;
}
if (IS_SD(mmc)) {
start_cmd = SD_CMD_ERASE_WR_BLK_START;
end_cmd = SD_CMD_ERASE_WR_BLK_END;
} else {
start_cmd = MMC_CMD_ERASE_GROUP_START;
end_cmd = MMC_CMD_ERASE_GROUP_END;
}
cmd.cmdidx = start_cmd;
cmd.cmdarg = start;
cmd.resp_type = MMC_RSP_R1;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
goto err_out;
cmd.cmdidx = end_cmd;
cmd.cmdarg = end;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
goto err_out;
cmd.cmdidx = MMC_CMD_ERASE;
cmd.cmdarg = SECURE_ERASE;
cmd.resp_type = MMC_RSP_R1b;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
goto err_out;
return 0;
err_out:
puts("mmc erase failed\n");
return err;
}
static unsigned long
mmc_berase(int dev_num, unsigned long start, lbaint_t blkcnt)
{
int err = 0;
struct mmc *mmc = find_mmc_device(dev_num);
lbaint_t blk = 0, blk_r = 0;
if (!mmc)
return -1;
if ((start % mmc->erase_grp_size) || (blkcnt % mmc->erase_grp_size))
printf("\n\nCaution! Your devices Erase group is 0x%x\n"
"The erase range would be change to 0x%lx~0x%lx\n\n",
mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1),
((start + blkcnt + mmc->erase_grp_size)
& ~(mmc->erase_grp_size - 1)) - 1);
while (blk < blkcnt) {
blk_r = ((blkcnt - blk) > mmc->erase_grp_size) ?
mmc->erase_grp_size : (blkcnt - blk);
err = mmc_erase_t(mmc, start + blk, blk_r);
if (err)
break;
blk += blk_r;
}
return blk;
}
static ulong
mmc_write_blocks(struct mmc *mmc, ulong start, lbaint_t blkcnt, const void*src)
{
struct mmc_cmd cmd;
struct mmc_data data;
int timeout = 1000;
if ((start + blkcnt) > mmc->block_dev.lba) {
printf("MMC: block number 0x%lx exceeds max(0x%lx)\n",
start + blkcnt, mmc->block_dev.lba);
return 0;
}
if (blkcnt > 1)
cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK;
else
cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
if (mmc->high_capacity)
cmd.cmdarg = start;
else
cmd.cmdarg = start * mmc->write_bl_len;
cmd.resp_type = MMC_RSP_R1;
cmd.flags = 0;
data.src = src;
data.blocks = blkcnt;
data.blocksize = mmc->write_bl_len;
data.flags = MMC_DATA_WRITE;
if (mmc_send_cmd(mmc, &cmd, &data)) {
printf("mmc write failed\n");
return 0;
}
/* SPI multiblock writes terminate using a special
* token, not a STOP_TRANSMISSION request.
*/
if (!mmc_host_is_spi(mmc) && blkcnt > 1) {
cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_R1b;
cmd.flags = 0;
if (mmc_send_cmd(mmc, &cmd, NULL)) {
printf("mmc fail to send stop cmd\n");
return 0;
}
/* Waiting for the ready status */
mmc_send_status(mmc, timeout);
}
return blkcnt;
}
static ulong
mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src)
{
lbaint_t cur, blocks_todo = blkcnt;
struct mmc *mmc = find_mmc_device(dev_num);
if (!mmc)
return 0;
if (mmc_set_blocklen(mmc, mmc->write_bl_len))
return 0;
do {
cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo;
if(mmc_write_blocks(mmc, start, cur, src) != cur)
return 0;
blocks_todo -= cur;
start += cur;
src += cur * mmc->write_bl_len;
} while (blocks_todo > 0);
return blkcnt;
}
int mmc_read_blocks(struct mmc *mmc, void *dst, ulong start, lbaint_t blkcnt)
{
struct mmc_cmd cmd;
struct mmc_data data;
int timeout = 1000;
if (blkcnt > 1)
cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
else
cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
if (mmc->high_capacity)
cmd.cmdarg = start;
else
cmd.cmdarg = start * mmc->read_bl_len;
cmd.resp_type = MMC_RSP_R1;
cmd.flags = 0;
data.dest = dst;
data.blocks = blkcnt;
data.blocksize = mmc->read_bl_len;
data.flags = MMC_DATA_READ;
if (mmc_send_cmd(mmc, &cmd, &data))
return 0;
if (blkcnt > 1) {
cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_R1b;
cmd.flags = 0;
if (mmc_send_cmd(mmc, &cmd, NULL)) {
printf("mmc fail to send stop cmd\n");
return 0;
}
/* Waiting for the ready status */
mmc_send_status(mmc, timeout);
}
return blkcnt;
}
static ulong mmc_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst)
{
lbaint_t cur, blocks_todo = blkcnt;
if (blkcnt == 0)
return 0;
struct mmc *mmc = find_mmc_device(dev_num);
if (!mmc)
return 0;
if ((start + blkcnt) > mmc->block_dev.lba) {
printf("MMC: block number 0x%lx exceeds max(0x%lx)\n",
start + blkcnt, mmc->block_dev.lba);
return 0;
}
if (mmc_set_blocklen(mmc, mmc->read_bl_len))
return 0;
do {
cur = (blocks_todo > mmc->b_max) ? mmc->b_max : blocks_todo;
if(mmc_read_blocks(mmc, dst, start, cur) != cur)
return 0;
blocks_todo -= cur;
start += cur;
dst += cur * mmc->read_bl_len;
} while (blocks_todo > 0);
return blkcnt;
}
int mmc_go_idle(struct mmc* mmc)
{
struct mmc_cmd cmd;
int err;
udelay(1000);
cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_NONE;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
udelay(2000);
return 0;
}
int
sd_send_op_cond(struct mmc *mmc)
{
int timeout = 1000;
int err;
struct mmc_cmd cmd;
do {
cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
cmd.resp_type = MMC_RSP_R3;
/*
* Most cards do not answer if some reserved bits
* in the ocr are set. However, Some controller
* can set bit 7 (reserved for low voltages), but
* how to manage low voltages SD card is not yet
* specified.
*/
cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
(mmc->voltages & 0xff8000);
if (mmc->version == SD_VERSION_2)
cmd.cmdarg |= OCR_HCS;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
udelay(1000);
} while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
if (timeout <= 0)
return UNUSABLE_ERR;
if (mmc->version != SD_VERSION_2)
mmc->version = SD_VERSION_1_0;
if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
cmd.resp_type = MMC_RSP_R3;
cmd.cmdarg = 0;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
}
mmc->ocr = cmd.response[0];
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
mmc->rca = 0;
return 0;
}
int mmc_send_op_cond(struct mmc *mmc)
{
int timeout = 10000;
struct mmc_cmd cmd;
int err;
/* Some cards seem to need this */
mmc_go_idle(mmc);
/* Asking to the card its capabilities */
cmd.cmdidx = MMC_CMD_SEND_OP_COND;
cmd.resp_type = MMC_RSP_R3;
cmd.cmdarg = 0;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
udelay(1000);
do {
cmd.cmdidx = MMC_CMD_SEND_OP_COND;
cmd.resp_type = MMC_RSP_R3;
cmd.cmdarg = (mmc_host_is_spi(mmc) ? 0 :
(mmc->voltages &
(cmd.response[0] & OCR_VOLTAGE_MASK)) |
(cmd.response[0] & OCR_ACCESS_MODE));
if (mmc->host_caps & MMC_MODE_HC)
cmd.cmdarg |= OCR_HCS;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
udelay(1000);
} while (!(cmd.response[0] & OCR_BUSY) && timeout--);
if (timeout <= 0)
return UNUSABLE_ERR;
if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
cmd.resp_type = MMC_RSP_R3;
cmd.cmdarg = 0;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
}
mmc->version = MMC_VERSION_UNKNOWN;
mmc->ocr = cmd.response[0];
mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
mmc->rca = 0;
return 0;
}
int mmc_send_ext_csd(struct mmc *mmc, char *ext_csd)
{
struct mmc_cmd cmd;
struct mmc_data data;
int err;
/* Get the Card Status Register */
cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
cmd.flags = 0;
data.dest = ext_csd;
data.blocks = 1;
data.blocksize = 512;
data.flags = MMC_DATA_READ;
err = mmc_send_cmd(mmc, &cmd, &data);
return err;
}
int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
{
struct mmc_cmd cmd;
int timeout = 1000;
int ret;
cmd.cmdidx = MMC_CMD_SWITCH;
cmd.resp_type = MMC_RSP_R1b;
cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
(index << 16) |
(value << 8);
cmd.flags = 0;
ret = mmc_send_cmd(mmc, &cmd, NULL);
/* Waiting for the ready status */
mmc_send_status(mmc, timeout);
return ret;
}
int mmc_change_freq(struct mmc *mmc)
{
ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
char cardtype;
int err;
mmc->card_caps = 0;
if (mmc_host_is_spi(mmc))
return 0;
/* Only version 4 supports high-speed */
if (mmc->version < MMC_VERSION_4)
return 0;
err = mmc_send_ext_csd(mmc, ext_csd);
if (err)
return err;
cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
if (err)
return err;
/* Now check to see that it worked */
err = mmc_send_ext_csd(mmc, ext_csd);
if (err)
return err;
/* No high-speed support */
if (!ext_csd[EXT_CSD_HS_TIMING])
return 0;
/* High Speed is set, there are two types: 52MHz and 26MHz */
if (cardtype & MMC_HS_52MHZ)
mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
else
mmc->card_caps |= MMC_MODE_HS;
return 0;
}
int mmc_switch_part(int dev_num, unsigned int part_num)
{
struct mmc *mmc = find_mmc_device(dev_num);
if (!mmc)
return -1;
return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
(mmc->part_config & ~PART_ACCESS_MASK)
| (part_num & PART_ACCESS_MASK));
}
int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
{
struct mmc_cmd cmd;
struct mmc_data data;
/* Switch the frequency */
cmd.cmdidx = SD_CMD_SWITCH_FUNC;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = (mode << 31) | 0xffffff;
cmd.cmdarg &= ~(0xf << (group * 4));
cmd.cmdarg |= value << (group * 4);
cmd.flags = 0;
data.dest = (char *)resp;
data.blocksize = 64;
data.blocks = 1;
data.flags = MMC_DATA_READ;
return mmc_send_cmd(mmc, &cmd, &data);
}
int sd_change_freq(struct mmc *mmc)
{
int err;
struct mmc_cmd cmd;
ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
struct mmc_data data;
int timeout;
mmc->card_caps = 0;
if (mmc_host_is_spi(mmc))
return 0;
/* Read the SCR to find out if this card supports higher speeds */
cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = mmc->rca << 16;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
cmd.cmdidx = SD_CMD_APP_SEND_SCR;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 0;
cmd.flags = 0;
timeout = 3;
retry_scr:
data.dest = (char *)scr;
data.blocksize = 8;
data.blocks = 1;
data.flags = MMC_DATA_READ;
err = mmc_send_cmd(mmc, &cmd, &data);
if (err) {
if (timeout--)
goto retry_scr;
return err;
}
mmc->scr[0] = __be32_to_cpu(scr[0]);
mmc->scr[1] = __be32_to_cpu(scr[1]);
switch ((mmc->scr[0] >> 24) & 0xf) {
case 0:
mmc->version = SD_VERSION_1_0;
break;
case 1:
mmc->version = SD_VERSION_1_10;
break;
case 2:
mmc->version = SD_VERSION_2;
break;
default:
mmc->version = SD_VERSION_1_0;
break;
}
if (mmc->scr[0] & SD_DATA_4BIT)
mmc->card_caps |= MMC_MODE_4BIT;
/* Version 1.0 doesn't support switching */
if (mmc->version == SD_VERSION_1_0)
return 0;
timeout = 4;
while (timeout--) {
err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
(u8 *)switch_status);
if (err)
return err;
/* The high-speed function is busy. Try again */
if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
break;
}
/* If high-speed isn't supported, we return */
if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
return 0;
err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
if (err)
return err;
if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
mmc->card_caps |= MMC_MODE_HS;
return 0;
}
/* frequency bases */
/* divided by 10 to be nice to platforms without floating point */
static const int fbase[] = {
10000,
100000,
1000000,
10000000,
};
/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
* to platforms without floating point.
*/
static const int multipliers[] = {
0, /* reserved */
10,
12,
13,
15,
20,
25,
30,
35,
40,
45,
50,
55,
60,
70,
80,
};
void mmc_set_ios(struct mmc *mmc)
{
mmc->set_ios(mmc);
}
void mmc_set_clock(struct mmc *mmc, uint clock)
{
if (clock > mmc->f_max)
clock = mmc->f_max;
if (clock < mmc->f_min)
clock = mmc->f_min;
mmc->clock = clock;
mmc_set_ios(mmc);
}
void mmc_set_bus_width(struct mmc *mmc, uint width)
{
mmc->bus_width = width;
mmc_set_ios(mmc);
}
int mmc_startup(struct mmc *mmc)
{
int err, width;
uint mult, freq;
u64 cmult, csize, capacity;
struct mmc_cmd cmd;
ALLOC_CACHE_ALIGN_BUFFER(char, ext_csd, 512);
ALLOC_CACHE_ALIGN_BUFFER(char, test_csd, 512);
int timeout = 1000;
#ifdef CONFIG_MMC_SPI_CRC_ON
if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 1;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
}
#endif
/* Put the Card in Identify Mode */
cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
cmd.resp_type = MMC_RSP_R2;
cmd.cmdarg = 0;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
memcpy(mmc->cid, cmd.response, 16);
/*
* For MMC cards, set the Relative Address.
* For SD cards, get the Relatvie Address.
* This also puts the cards into Standby State
*/
if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
cmd.cmdarg = mmc->rca << 16;
cmd.resp_type = MMC_RSP_R6;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
if (IS_SD(mmc))
mmc->rca = (cmd.response[0] >> 16) & 0xffff;
}
/* Get the Card-Specific Data */
cmd.cmdidx = MMC_CMD_SEND_CSD;
cmd.resp_type = MMC_RSP_R2;
cmd.cmdarg = mmc->rca << 16;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
/* Waiting for the ready status */
mmc_send_status(mmc, timeout);
if (err)
return err;
mmc->csd[0] = cmd.response[0];
mmc->csd[1] = cmd.response[1];
mmc->csd[2] = cmd.response[2];
mmc->csd[3] = cmd.response[3];
if (mmc->version == MMC_VERSION_UNKNOWN) {
int version = (cmd.response[0] >> 26) & 0xf;
switch (version) {
case 0:
mmc->version = MMC_VERSION_1_2;
break;
case 1:
mmc->version = MMC_VERSION_1_4;
break;
case 2:
mmc->version = MMC_VERSION_2_2;
break;
case 3:
mmc->version = MMC_VERSION_3;
break;
case 4:
mmc->version = MMC_VERSION_4;
break;
default:
mmc->version = MMC_VERSION_1_2;
break;
}
}
/* divide frequency by 10, since the mults are 10x bigger */
freq = fbase[(cmd.response[0] & 0x7)];
mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
mmc->tran_speed = freq * mult;
mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
if (IS_SD(mmc))
mmc->write_bl_len = mmc->read_bl_len;
else
mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
if (mmc->high_capacity) {
csize = (mmc->csd[1] & 0x3f) << 16
| (mmc->csd[2] & 0xffff0000) >> 16;
cmult = 8;
} else {
csize = (mmc->csd[1] & 0x3ff) << 2
| (mmc->csd[2] & 0xc0000000) >> 30;
cmult = (mmc->csd[2] & 0x00038000) >> 15;
}
mmc->capacity = (csize + 1) << (cmult + 2);
mmc->capacity *= mmc->read_bl_len;
if (mmc->read_bl_len > 512)
mmc->read_bl_len = 512;
if (mmc->write_bl_len > 512)
mmc->write_bl_len = 512;
/* Select the card, and put it into Transfer Mode */
if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
cmd.cmdidx = MMC_CMD_SELECT_CARD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = mmc->rca << 16;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
}
/*
* For SD, its erase group is always one sector
*/
mmc->erase_grp_size = 1;
mmc->part_config = MMCPART_NOAVAILABLE;
if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
/* check ext_csd version and capacity */
err = mmc_send_ext_csd(mmc, ext_csd);
if (!err & (ext_csd[EXT_CSD_REV] >= 2)) {
/*
* According to the JEDEC Standard, the value of
* ext_csd's capacity is valid if the value is more
* than 2GB
*/
capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
| ext_csd[EXT_CSD_SEC_CNT + 1] << 8
| ext_csd[EXT_CSD_SEC_CNT + 2] << 16
| ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
capacity *= 512;
if ((capacity >> 20) > 2 * 1024)
mmc->capacity = capacity;
}
/*
* Check whether GROUP_DEF is set, if yes, read out
* group size from ext_csd directly, or calculate
* the group size from the csd value.
*/
if (ext_csd[EXT_CSD_ERASE_GROUP_DEF])
mmc->erase_grp_size =
ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 512 * 1024;
else {
int erase_gsz, erase_gmul;
erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
mmc->erase_grp_size = (erase_gsz + 1)
* (erase_gmul + 1);
}
/* store the partition info of emmc */
if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT)
mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
}
if (IS_SD(mmc))
err = sd_change_freq(mmc);
else
err = mmc_change_freq(mmc);
if (err)
return err;
/* Restrict card's capabilities by what the host can do */
mmc->card_caps &= mmc->host_caps;
if (IS_SD(mmc)) {
if (mmc->card_caps & MMC_MODE_4BIT) {
cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = mmc->rca << 16;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = 2;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
mmc_set_bus_width(mmc, 4);
}
if (mmc->card_caps & MMC_MODE_HS)
mmc_set_clock(mmc, 50000000);
else
mmc_set_clock(mmc, 25000000);
} else {
for (width = EXT_CSD_BUS_WIDTH_8; width >= 0; width--) {
/* Set the card to use 4 bit*/
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
EXT_CSD_BUS_WIDTH, width);
if (err)
continue;
if (!width) {
mmc_set_bus_width(mmc, 1);
break;
} else
mmc_set_bus_width(mmc, 4 * width);
err = mmc_send_ext_csd(mmc, test_csd);
if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
== test_csd[EXT_CSD_PARTITIONING_SUPPORT]
&& ext_csd[EXT_CSD_ERASE_GROUP_DEF] \
== test_csd[EXT_CSD_ERASE_GROUP_DEF] \
&& ext_csd[EXT_CSD_REV] \
== test_csd[EXT_CSD_REV]
&& ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
== test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
&& memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
&test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
mmc->card_caps |= width;
break;
}
}
if (mmc->card_caps & MMC_MODE_HS) {
if (mmc->card_caps & MMC_MODE_HS_52MHz)
mmc_set_clock(mmc, 52000000);
else
mmc_set_clock(mmc, 26000000);
} else
mmc_set_clock(mmc, 20000000);
}
/* fill in device description */
mmc->block_dev.lun = 0;
mmc->block_dev.type = 0;
mmc->block_dev.blksz = mmc->read_bl_len;
mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
sprintf(mmc->block_dev.vendor, "Man %06x Snr %08x", mmc->cid[0] >> 8,
(mmc->cid[2] << 8) | (mmc->cid[3] >> 24));
sprintf(mmc->block_dev.product, "%c%c%c%c%c", mmc->cid[0] & 0xff,
(mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
(mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff);
sprintf(mmc->block_dev.revision, "%d.%d", mmc->cid[2] >> 28,
(mmc->cid[2] >> 24) & 0xf);
init_part(&mmc->block_dev);
return 0;
}
int mmc_send_if_cond(struct mmc *mmc)
{
struct mmc_cmd cmd;
int err;
cmd.cmdidx = SD_CMD_SEND_IF_COND;
/* We set the bit if the host supports voltages between 2.7 and 3.6 V */
cmd.cmdarg = ((mmc->voltages & 0xff8000) != 0) << 8 | 0xaa;
cmd.resp_type = MMC_RSP_R7;
cmd.flags = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
if (err)
return err;
if ((cmd.response[0] & 0xff) != 0xaa)
return UNUSABLE_ERR;
else
mmc->version = SD_VERSION_2;
return 0;
}
int mmc_register(struct mmc *mmc)
{
/* Setup the universal parts of the block interface just once */
mmc->block_dev.if_type = IF_TYPE_MMC;
mmc->block_dev.dev = cur_dev_num++;
mmc->block_dev.removable = 1;
mmc->block_dev.block_read = mmc_bread;
mmc->block_dev.block_write = mmc_bwrite;
mmc->block_dev.block_erase = mmc_berase;
if (!mmc->b_max)
mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
INIT_LIST_HEAD (&mmc->link);
list_add_tail (&mmc->link, &mmc_devices);
return 0;
}
#ifdef CONFIG_PARTITIONS
block_dev_desc_t *mmc_get_dev(int dev)
{
struct mmc *mmc = find_mmc_device(dev);
return mmc ? &mmc->block_dev : NULL;
}
#endif
int mmc_init(struct mmc *mmc)
{
int err;
if (mmc->has_init)
return 0;
err = mmc->init(mmc);
if (err)
return err;
mmc_set_bus_width(mmc, 1);
mmc_set_clock(mmc, 1);
/* Reset the Card */
err = mmc_go_idle(mmc);
if (err)
return err;
/* The internal partition reset to user partition(0) at every CMD0*/
mmc->part_num = 0;
/* Test for SD version 2 */
err = mmc_send_if_cond(mmc);
/* Now try to get the SD card's operating condition */
err = sd_send_op_cond(mmc);
/* If the command timed out, we check for an MMC card */
if (err == TIMEOUT) {
err = mmc_send_op_cond(mmc);
if (err) {
printf("Card did not respond to voltage select!\n");
return UNUSABLE_ERR;
}
}
err = mmc_startup(mmc);
if (err)
mmc->has_init = 0;
else
mmc->has_init = 1;
return err;
}
/*
* CPU and board-specific MMC initializations. Aliased function
* signals caller to move on
*/
static int __def_mmc_init(bd_t *bis)
{
return -1;
}
int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
int board_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init")));
void print_mmc_devices(char separator)
{
struct mmc *m;
struct list_head *entry;
list_for_each(entry, &mmc_devices) {
m = list_entry(entry, struct mmc, link);
printf("%s: %d", m->name, m->block_dev.dev);
if (entry->next != &mmc_devices)
printf("%c ", separator);
}
printf("\n");
}
int get_mmc_num(void)
{
return cur_dev_num;
}
int mmc_initialize(bd_t *bis)
{
INIT_LIST_HEAD (&mmc_devices);
cur_dev_num = 0;
if (board_mmc_init(bis) < 0)
cpu_mmc_init(bis);
print_mmc_devices(',');
return 0;
}
|
1001-study-uboot
|
drivers/mmc/mmc.c
|
C
|
gpl3
| 26,840
|
/*
* linux/drivers/mmc/mmc_pxa.h
*
* Author: Vladimir Shebordaev, Igor Oblakov
* Copyright: MontaVista Software Inc.
*
* $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MMC_PXA_P_H__
#define __MMC_PXA_P_H__
/* PXA-250 MMC controller registers */
/* MMC_STRPCL */
#define MMC_STRPCL_STOP_CLK (0x0001UL)
#define MMC_STRPCL_START_CLK (0x0002UL)
/* MMC_STAT */
#define MMC_STAT_END_CMD_RES (0x0001UL << 13)
#define MMC_STAT_PRG_DONE (0x0001UL << 12)
#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11)
#define MMC_STAT_CLK_EN (0x0001UL << 8)
#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7)
#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6)
#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5)
#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4)
#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3)
#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2)
#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1)
#define MMC_STAT_READ_TIME_OUT (0x0001UL)
#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\
|MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\
|MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR)
/* MMC_CLKRT */
#define MMC_CLKRT_20MHZ (0x0000UL)
#define MMC_CLKRT_10MHZ (0x0001UL)
#define MMC_CLKRT_5MHZ (0x0002UL)
#define MMC_CLKRT_2_5MHZ (0x0003UL)
#define MMC_CLKRT_1_25MHZ (0x0004UL)
#define MMC_CLKRT_0_625MHZ (0x0005UL)
#define MMC_CLKRT_0_3125MHZ (0x0006UL)
/* MMC_SPI */
#define MMC_SPI_DISABLE (0x00UL)
#define MMC_SPI_EN (0x01UL)
#define MMC_SPI_CS_EN (0x01UL << 2)
#define MMC_SPI_CS_ADDRESS (0x01UL << 3)
#define MMC_SPI_CRC_ON (0x01UL << 1)
/* MMC_CMDAT */
#define MMC_CMDAT_SD_4DAT (0x0001UL << 8)
#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7)
#define MMC_CMDAT_INIT (0x0001UL << 6)
#define MMC_CMDAT_BUSY (0x0001UL << 5)
#define MMC_CMDAT_BCR (0x0003UL << 5)
#define MMC_CMDAT_STREAM (0x0001UL << 4)
#define MMC_CMDAT_BLOCK (0x0000UL << 4)
#define MMC_CMDAT_WRITE (0x0001UL << 3)
#define MMC_CMDAT_READ (0x0000UL << 3)
#define MMC_CMDAT_DATA_EN (0x0001UL << 2)
#define MMC_CMDAT_R0 (0)
#define MMC_CMDAT_R1 (0x0001UL)
#define MMC_CMDAT_R2 (0x0002UL)
#define MMC_CMDAT_R3 (0x0003UL)
/* MMC_RESTO */
#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */
/* MMC_RDTO */
#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */
/* MMC_BLKLEN */
#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */
/* MMC_PRTBUF */
#define MMC_PRTBUF_BUF_PART_FULL (0x01UL)
#define MMC_PRTBUF_BUF_FULL (0x00UL )
/* MMC_I_MASK */
#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6)
#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5)
#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4)
#define MMC_I_MASK_STOP_CMD (0x01UL << 3)
#define MMC_I_MASK_END_CMD_RES (0x01UL << 2)
#define MMC_I_MASK_PRG_DONE (0x01UL << 1)
#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL)
#define MMC_I_MASK_ALL (0x07fUL)
/* MMC_I_REG */
#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6)
#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5)
#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4)
#define MMC_I_REG_STOP_CMD (0x01UL << 3)
#define MMC_I_REG_END_CMD_RES (0x01UL << 2)
#define MMC_I_REG_PRG_DONE (0x01UL << 1)
#define MMC_I_REG_DATA_TRAN_DONE (0x01UL)
#define MMC_I_REG_ALL (0x007fUL)
/* MMC_CMD */
#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */
#define CMD(x) (x)
#define MMC_DEFAULT_RCA 1
#define MMC_BLOCK_SIZE 512
#define MMC_MAX_BLOCK_SIZE 512
#define MMC_R1_IDLE_STATE 0x01
#define MMC_R1_ERASE_STATE 0x02
#define MMC_R1_ILLEGAL_CMD 0x04
#define MMC_R1_COM_CRC_ERR 0x08
#define MMC_R1_ERASE_SEQ_ERR 0x01
#define MMC_R1_ADDR_ERR 0x02
#define MMC_R1_PARAM_ERR 0x04
#define MMC_R1B_WP_ERASE_SKIP 0x0002
#define MMC_R1B_ERR 0x0004
#define MMC_R1B_CC_ERR 0x0008
#define MMC_R1B_CARD_ECC_ERR 0x0010
#define MMC_R1B_WP_VIOLATION 0x0020
#define MMC_R1B_ERASE_PARAM 0x0040
#define MMC_R1B_OOR 0x0080
#define MMC_R1B_IDLE_STATE 0x0100
#define MMC_R1B_ERASE_RESET 0x0200
#define MMC_R1B_ILLEGAL_CMD 0x0400
#define MMC_R1B_COM_CRC_ERR 0x0800
#define MMC_R1B_ERASE_SEQ_ERR 0x1000
#define MMC_R1B_ADDR_ERR 0x2000
#define MMC_R1B_PARAM_ERR 0x4000
#endif /* __MMC_PXA_P_H__ */
|
1001-study-uboot
|
drivers/mmc/pxa_mmc.h
|
C
|
gpl3
| 4,359
|
/*
* ARM PrimeCell MultiMedia Card Interface - PL180
*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Ulf Hansson <ulf.hansson@stericsson.com>
* Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
* Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* #define DEBUG */
#include <asm/io.h>
#include "common.h"
#include <errno.h>
#include <mmc.h>
#include "arm_pl180_mmci.h"
#include <malloc.h>
struct mmc_host {
struct sdi_registers *base;
};
static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd)
{
u32 hoststatus, statusmask;
struct mmc_host *host = dev->priv;
statusmask = SDI_STA_CTIMEOUT | SDI_STA_CCRCFAIL;
if ((cmd->resp_type & MMC_RSP_PRESENT))
statusmask |= SDI_STA_CMDREND;
else
statusmask |= SDI_STA_CMDSENT;
do
hoststatus = readl(&host->base->status) & statusmask;
while (!hoststatus);
writel(statusmask, &host->base->status_clear);
if (hoststatus & SDI_STA_CTIMEOUT) {
printf("CMD%d time out\n", cmd->cmdidx);
return -ETIMEDOUT;
} else if ((hoststatus & SDI_STA_CCRCFAIL) &&
(cmd->flags & MMC_RSP_CRC)) {
printf("CMD%d CRC error\n", cmd->cmdidx);
return -EILSEQ;
}
if (cmd->resp_type & MMC_RSP_PRESENT) {
cmd->response[0] = readl(&host->base->response0);
cmd->response[1] = readl(&host->base->response1);
cmd->response[2] = readl(&host->base->response2);
cmd->response[3] = readl(&host->base->response3);
debug("CMD%d response[0]:0x%08X, response[1]:0x%08X, "
"response[2]:0x%08X, response[3]:0x%08X\n",
cmd->cmdidx, cmd->response[0], cmd->response[1],
cmd->response[2], cmd->response[3]);
}
return 0;
}
/* send command to the mmc card and wait for results */
static int do_command(struct mmc *dev, struct mmc_cmd *cmd)
{
int result;
u32 sdi_cmd = 0;
struct mmc_host *host = dev->priv;
sdi_cmd = ((cmd->cmdidx & SDI_CMD_CMDINDEX_MASK) | SDI_CMD_CPSMEN);
if (cmd->resp_type) {
sdi_cmd |= SDI_CMD_WAITRESP;
if (cmd->resp_type & MMC_RSP_136)
sdi_cmd |= SDI_CMD_LONGRESP;
}
writel((u32)cmd->cmdarg, &host->base->argument);
udelay(COMMAND_REG_DELAY);
writel(sdi_cmd, &host->base->command);
result = wait_for_command_end(dev, cmd);
/* After CMD2 set RCA to a none zero value. */
if ((result == 0) && (cmd->cmdidx == MMC_CMD_ALL_SEND_CID))
dev->rca = 10;
/* After CMD3 open drain is switched off and push pull is used. */
if ((result == 0) && (cmd->cmdidx == MMC_CMD_SET_RELATIVE_ADDR)) {
u32 sdi_pwr = readl(&host->base->power) & ~SDI_PWR_OPD;
writel(sdi_pwr, &host->base->power);
}
return result;
}
static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
{
u32 *tempbuff = dest;
u64 xfercount = blkcount * blksize;
struct mmc_host *host = dev->priv;
u32 status, status_err;
debug("read_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
status = readl(&host->base->status);
status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
SDI_STA_RXOVERR);
while ((!status_err) && (xfercount >= sizeof(u32))) {
if (status & SDI_STA_RXDAVL) {
*(tempbuff) = readl(&host->base->fifo);
tempbuff++;
xfercount -= sizeof(u32);
}
status = readl(&host->base->status);
status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
SDI_STA_RXOVERR);
}
status_err = status &
(SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
SDI_STA_RXOVERR);
while (!status_err) {
status = readl(&host->base->status);
status_err = status &
(SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND |
SDI_STA_RXOVERR);
}
if (status & SDI_STA_DTIMEOUT) {
printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
xfercount, status);
return -ETIMEDOUT;
} else if (status & SDI_STA_DCRCFAIL) {
printf("Read data bytes CRC error: 0x%x\n", status);
return -EILSEQ;
} else if (status & SDI_STA_RXOVERR) {
printf("Read data RX overflow error\n");
return -EIO;
}
writel(SDI_ICR_MASK, &host->base->status_clear);
if (xfercount) {
printf("Read data error, xfercount: %llu\n", xfercount);
return -ENOBUFS;
}
return 0;
}
static int write_bytes(struct mmc *dev, u32 *src, u32 blkcount, u32 blksize)
{
u32 *tempbuff = src;
int i;
u64 xfercount = blkcount * blksize;
struct mmc_host *host = dev->priv;
u32 status, status_err;
debug("write_bytes: blkcount=%u blksize=%u\n", blkcount, blksize);
status = readl(&host->base->status);
status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
while (!status_err && xfercount) {
if (status & SDI_STA_TXFIFOBW) {
if (xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32)) {
for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
writel(*(tempbuff + i),
&host->base->fifo);
tempbuff += SDI_FIFO_BURST_SIZE;
xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
} else {
while (xfercount >= sizeof(u32)) {
writel(*(tempbuff), &host->base->fifo);
tempbuff++;
xfercount -= sizeof(u32);
}
}
}
status = readl(&host->base->status);
status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT);
}
status_err = status &
(SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
while (!status_err) {
status = readl(&host->base->status);
status_err = status &
(SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_DBCKEND);
}
if (status & SDI_STA_DTIMEOUT) {
printf("Write data timed out, xfercount:%llu,status:0x%08X\n",
xfercount, status);
return -ETIMEDOUT;
} else if (status & SDI_STA_DCRCFAIL) {
printf("Write data CRC error\n");
return -EILSEQ;
}
writel(SDI_ICR_MASK, &host->base->status_clear);
if (xfercount) {
printf("Write data error, xfercount:%llu", xfercount);
return -ENOBUFS;
}
return 0;
}
static int do_data_transfer(struct mmc *dev,
struct mmc_cmd *cmd,
struct mmc_data *data)
{
int error = -ETIMEDOUT;
struct mmc_host *host = dev->priv;
u32 blksz = 0;
u32 data_ctrl = 0;
u32 data_len = (u32) (data->blocks * data->blocksize);
blksz = (ffs(data->blocksize) - 1);
data_ctrl |= ((blksz << 4) & SDI_DCTRL_DBLKSIZE_MASK);
data_ctrl |= SDI_DCTRL_DTEN;
writel(SDI_DTIMER_DEFAULT, &host->base->datatimer);
writel(data_len, &host->base->datalength);
udelay(DATA_REG_DELAY);
if (data->flags & MMC_DATA_READ) {
data_ctrl |= SDI_DCTRL_DTDIR_IN;
writel(data_ctrl, &host->base->datactrl);
error = do_command(dev, cmd);
if (error)
return error;
error = read_bytes(dev, (u32 *)data->dest, (u32)data->blocks,
(u32)data->blocksize);
} else if (data->flags & MMC_DATA_WRITE) {
error = do_command(dev, cmd);
if (error)
return error;
writel(data_ctrl, &host->base->datactrl);
error = write_bytes(dev, (u32 *)data->src, (u32)data->blocks,
(u32)data->blocksize);
}
return error;
}
static int host_request(struct mmc *dev,
struct mmc_cmd *cmd,
struct mmc_data *data)
{
int result;
if (data)
result = do_data_transfer(dev, cmd, data);
else
result = do_command(dev, cmd);
return result;
}
/* MMC uses open drain drivers in the enumeration phase */
static int mmc_host_reset(struct mmc *dev)
{
struct mmc_host *host = dev->priv;
u32 sdi_u32 = SDI_PWR_OPD | SDI_PWR_PWRCTRL_ON;
writel(sdi_u32, &host->base->power);
return 0;
}
static void host_set_ios(struct mmc *dev)
{
struct mmc_host *host = dev->priv;
u32 sdi_clkcr;
sdi_clkcr = readl(&host->base->clock);
/* Ramp up the clock rate */
if (dev->clock) {
u32 clkdiv = 0;
if (dev->clock >= dev->f_max)
dev->clock = dev->f_max;
clkdiv = ((ARM_MCLK / dev->clock) / 2) - 1;
if (clkdiv > SDI_CLKCR_CLKDIV_MASK)
clkdiv = SDI_CLKCR_CLKDIV_MASK;
sdi_clkcr &= ~(SDI_CLKCR_CLKDIV_MASK);
sdi_clkcr |= clkdiv;
}
/* Set the bus width */
if (dev->bus_width) {
u32 buswidth = 0;
switch (dev->bus_width) {
case 1:
buswidth |= SDI_CLKCR_WIDBUS_1;
break;
case 4:
buswidth |= SDI_CLKCR_WIDBUS_4;
break;
default:
printf("Invalid bus width\n");
break;
}
sdi_clkcr &= ~(SDI_CLKCR_WIDBUS_MASK);
sdi_clkcr |= buswidth;
}
writel(sdi_clkcr, &host->base->clock);
udelay(CLK_CHANGE_DELAY);
}
struct mmc *alloc_mmc_struct(void)
{
struct mmc_host *host = NULL;
struct mmc *mmc_device = NULL;
host = malloc(sizeof(struct mmc_host));
if (!host)
return NULL;
mmc_device = malloc(sizeof(struct mmc));
if (!mmc_device)
goto err;
mmc_device->priv = host;
return mmc_device;
err:
free(host);
return NULL;
}
/*
* mmc_host_init - initialize the mmc controller.
* Set initial clock and power for mmc slot.
* Initialize mmc struct and register with mmc framework.
*/
static int arm_pl180_mmci_host_init(struct mmc *dev)
{
struct mmc_host *host = dev->priv;
u32 sdi_u32;
host->base = (struct sdi_registers *)CONFIG_ARM_PL180_MMCI_BASE;
/* Initially set power-on, full voltage & MMCI read */
sdi_u32 = INIT_PWR;
writel(sdi_u32, &host->base->power);
/* setting clk freq 505KHz */
sdi_u32 = SDI_CLKCR_CLKDIV_INIT | SDI_CLKCR_CLKEN;
writel(sdi_u32, &host->base->clock);
udelay(CLK_CHANGE_DELAY);
/* Disable mmc interrupts */
sdi_u32 = readl(&host->base->mask0) & ~SDI_MASK0_MASK;
writel(sdi_u32, &host->base->mask0);
sprintf(dev->name, "MMC");
dev->clock = ARM_MCLK / (2 * (SDI_CLKCR_CLKDIV_INIT + 1));
dev->send_cmd = host_request;
dev->set_ios = host_set_ios;
dev->init = mmc_host_reset;
dev->host_caps = 0;
dev->voltages = VOLTAGE_WINDOW_MMC;
dev->f_min = dev->clock;
dev->f_max = CONFIG_ARM_PL180_MMCI_CLOCK_FREQ;
return 0;
}
int arm_pl180_mmci_init(void)
{
int error;
struct mmc *dev;
dev = alloc_mmc_struct();
if (!dev)
return -1;
error = arm_pl180_mmci_host_init(dev);
if (error) {
printf("mmci_host_init error - %d\n", error);
return -1;
}
dev->b_max = 0;
mmc_register(dev);
debug("registered mmc interface number is:%d\n", dev->block_dev.dev);
return 0;
}
|
1001-study-uboot
|
drivers/mmc/arm_pl180_mmci.c
|
C
|
gpl3
| 10,490
|
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libmmc.o
COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
COBJS-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
COBJS-$(CONFIG_MMC_SPI) += mmc_spi.o
COBJS-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
COBJS-$(CONFIG_MV_SDHCI) += mv_sdhci.o
COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o
COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o
COBJS-$(CONFIG_SDHCI) += sdhci.o
COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o
COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/mmc/Makefile
|
Makefile
|
gpl3
| 2,086
|
/*
* generic mmc spi driver
*
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <malloc.h>
#include <part.h>
#include <mmc.h>
#include <spi.h>
#include <crc.h>
#include <linux/crc7.h>
#include <linux/byteorder/swab.h>
/* MMC/SD in SPI mode reports R1 status always */
#define R1_SPI_IDLE (1 << 0)
#define R1_SPI_ERASE_RESET (1 << 1)
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
#define R1_SPI_COM_CRC (1 << 3)
#define R1_SPI_ERASE_SEQ (1 << 4)
#define R1_SPI_ADDRESS (1 << 5)
#define R1_SPI_PARAMETER (1 << 6)
/* R1 bit 7 is always zero, reuse this bit for error */
#define R1_SPI_ERROR (1 << 7)
/* Response tokens used to ack each block written: */
#define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
#define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
#define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
#define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
/* Read and write blocks start with these tokens and end with crc;
* on error, read tokens act like a subset of R2_SPI_* values.
*/
#define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
#define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
#define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
/* MMC SPI commands start with a start bit "0" and a transmit bit "1" */
#define MMC_SPI_CMD(x) (0x40 | (x & 0x3f))
/* bus capability */
#define MMC_SPI_VOLTAGE (MMC_VDD_32_33 | MMC_VDD_33_34)
#define MMC_SPI_MIN_CLOCK 400000 /* 400KHz to meet MMC spec */
/* timeout value */
#define CTOUT 8
#define RTOUT 3000000 /* 1 sec */
#define WTOUT 3000000 /* 1 sec */
static uint mmc_spi_sendcmd(struct mmc *mmc, ushort cmdidx, u32 cmdarg)
{
struct spi_slave *spi = mmc->priv;
u8 cmdo[7];
u8 r1;
int i;
cmdo[0] = 0xff;
cmdo[1] = MMC_SPI_CMD(cmdidx);
cmdo[2] = cmdarg >> 24;
cmdo[3] = cmdarg >> 16;
cmdo[4] = cmdarg >> 8;
cmdo[5] = cmdarg;
cmdo[6] = (crc7(0, &cmdo[1], 5) << 1) | 0x01;
spi_xfer(spi, sizeof(cmdo) * 8, cmdo, NULL, 0);
for (i = 0; i < CTOUT; i++) {
spi_xfer(spi, 1 * 8, NULL, &r1, 0);
if (i && (r1 & 0x80) == 0) /* r1 response */
break;
}
debug("%s:cmd%d resp%d %x\n", __func__, cmdidx, i, r1);
return r1;
}
static uint mmc_spi_readdata(struct mmc *mmc, void *xbuf,
u32 bcnt, u32 bsize)
{
struct spi_slave *spi = mmc->priv;
u8 *buf = xbuf;
u8 r1;
u16 crc;
int i;
while (bcnt--) {
for (i = 0; i < RTOUT; i++) {
spi_xfer(spi, 1 * 8, NULL, &r1, 0);
if (r1 != 0xff) /* data token */
break;
}
debug("%s:tok%d %x\n", __func__, i, r1);
if (r1 == SPI_TOKEN_SINGLE) {
spi_xfer(spi, bsize * 8, NULL, buf, 0);
spi_xfer(spi, 2 * 8, NULL, &crc, 0);
#ifdef CONFIG_MMC_SPI_CRC_ON
if (swab16(cyg_crc16(buf, bsize)) != crc) {
debug("%s: CRC error\n", mmc->name);
r1 = R1_SPI_COM_CRC;
break;
}
#endif
r1 = 0;
} else {
r1 = R1_SPI_ERROR;
break;
}
buf += bsize;
}
return r1;
}
static uint mmc_spi_writedata(struct mmc *mmc, const void *xbuf,
u32 bcnt, u32 bsize, int multi)
{
struct spi_slave *spi = mmc->priv;
const u8 *buf = xbuf;
u8 r1;
u16 crc;
u8 tok[2];
int i;
tok[0] = 0xff;
tok[1] = multi ? SPI_TOKEN_MULTI_WRITE : SPI_TOKEN_SINGLE;
while (bcnt--) {
#ifdef CONFIG_MMC_SPI_CRC_ON
crc = swab16(cyg_crc16((u8 *)buf, bsize));
#endif
spi_xfer(spi, 2 * 8, tok, NULL, 0);
spi_xfer(spi, bsize * 8, buf, NULL, 0);
spi_xfer(spi, 2 * 8, &crc, NULL, 0);
for (i = 0; i < CTOUT; i++) {
spi_xfer(spi, 1 * 8, NULL, &r1, 0);
if ((r1 & 0x10) == 0) /* response token */
break;
}
debug("%s:tok%d %x\n", __func__, i, r1);
if (SPI_MMC_RESPONSE_CODE(r1) == SPI_RESPONSE_ACCEPTED) {
for (i = 0; i < WTOUT; i++) { /* wait busy */
spi_xfer(spi, 1 * 8, NULL, &r1, 0);
if (i && r1 == 0xff) {
r1 = 0;
break;
}
}
if (i == WTOUT) {
debug("%s:wtout %x\n", __func__, r1);
r1 = R1_SPI_ERROR;
break;
}
} else {
debug("%s: err %x\n", __func__, r1);
r1 = R1_SPI_COM_CRC;
break;
}
buf += bsize;
}
if (multi && bcnt == -1) { /* stop multi write */
tok[1] = SPI_TOKEN_STOP_TRAN;
spi_xfer(spi, 2 * 8, tok, NULL, 0);
for (i = 0; i < WTOUT; i++) { /* wait busy */
spi_xfer(spi, 1 * 8, NULL, &r1, 0);
if (i && r1 == 0xff) {
r1 = 0;
break;
}
}
if (i == WTOUT) {
debug("%s:wstop %x\n", __func__, r1);
r1 = R1_SPI_ERROR;
}
}
return r1;
}
static int mmc_spi_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct spi_slave *spi = mmc->priv;
u8 r1;
int i;
int ret = 0;
debug("%s:cmd%d %x %x %x\n", __func__,
cmd->cmdidx, cmd->resp_type, cmd->cmdarg, cmd->flags);
spi_claim_bus(spi);
spi_cs_activate(spi);
r1 = mmc_spi_sendcmd(mmc, cmd->cmdidx, cmd->cmdarg);
if (r1 == 0xff) { /* no response */
ret = NO_CARD_ERR;
goto done;
} else if (r1 & R1_SPI_COM_CRC) {
ret = COMM_ERR;
goto done;
} else if (r1 & ~R1_SPI_IDLE) { /* other errors */
ret = TIMEOUT;
goto done;
} else if (cmd->resp_type == MMC_RSP_R2) {
r1 = mmc_spi_readdata(mmc, cmd->response, 1, 16);
for (i = 0; i < 4; i++)
cmd->response[i] = swab32(cmd->response[i]);
debug("r128 %x %x %x %x\n", cmd->response[0], cmd->response[1],
cmd->response[2], cmd->response[3]);
} else if (!data) {
switch (cmd->cmdidx) {
case SD_CMD_APP_SEND_OP_COND:
case MMC_CMD_SEND_OP_COND:
cmd->response[0] = (r1 & R1_SPI_IDLE) ? 0 : OCR_BUSY;
break;
case SD_CMD_SEND_IF_COND:
case MMC_CMD_SPI_READ_OCR:
spi_xfer(spi, 4 * 8, NULL, cmd->response, 0);
cmd->response[0] = swab32(cmd->response[0]);
debug("r32 %x\n", cmd->response[0]);
break;
case MMC_CMD_SEND_STATUS:
spi_xfer(spi, 1 * 8, NULL, cmd->response, 0);
cmd->response[0] = (cmd->response[0] & 0xff) ?
MMC_STATUS_ERROR : MMC_STATUS_RDY_FOR_DATA;
break;
}
} else {
debug("%s:data %x %x %x\n", __func__,
data->flags, data->blocks, data->blocksize);
if (data->flags == MMC_DATA_READ)
r1 = mmc_spi_readdata(mmc, data->dest,
data->blocks, data->blocksize);
else if (data->flags == MMC_DATA_WRITE)
r1 = mmc_spi_writedata(mmc, data->src,
data->blocks, data->blocksize,
(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK));
if (r1 & R1_SPI_COM_CRC)
ret = COMM_ERR;
else if (r1) /* other errors */
ret = TIMEOUT;
}
done:
spi_cs_deactivate(spi);
spi_release_bus(spi);
return ret;
}
static void mmc_spi_set_ios(struct mmc *mmc)
{
struct spi_slave *spi = mmc->priv;
debug("%s: clock %u\n", __func__, mmc->clock);
if (mmc->clock)
spi_set_speed(spi, mmc->clock);
}
static int mmc_spi_init_p(struct mmc *mmc)
{
struct spi_slave *spi = mmc->priv;
mmc->clock = 0;
spi_set_speed(spi, MMC_SPI_MIN_CLOCK);
spi_claim_bus(spi);
/* cs deactivated for 100+ clock */
spi_xfer(spi, 18 * 8, NULL, NULL, 0);
spi_release_bus(spi);
return 0;
}
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode)
{
struct mmc *mmc;
mmc = malloc(sizeof(*mmc));
if (!mmc)
return NULL;
memset(mmc, 0, sizeof(*mmc));
mmc->priv = spi_setup_slave(bus, cs, speed, mode);
if (!mmc->priv) {
free(mmc);
return NULL;
}
sprintf(mmc->name, "MMC_SPI");
mmc->send_cmd = mmc_spi_request;
mmc->set_ios = mmc_spi_set_ios;
mmc->init = mmc_spi_init_p;
mmc->host_caps = MMC_MODE_SPI;
mmc->voltages = MMC_SPI_VOLTAGE;
mmc->f_max = speed;
mmc->f_min = MMC_SPI_MIN_CLOCK;
mmc->block_dev.part_type = PART_TYPE_DOS;
mmc_register(mmc);
return mmc;
}
|
1001-study-uboot
|
drivers/mmc/mmc_spi.c
|
C
|
gpl3
| 7,413
|
/*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* Loosely based on the old code and Linux's PXA MMC driver
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/errno.h>
#include <asm/arch/hardware.h>
#include <asm/arch/regs-mmc.h>
#include <asm/io.h>
/* PXAMMC Generic default config for various CPUs */
#if defined(CONFIG_CPU_PXA25X)
#define PXAMMC_FIFO_SIZE 1
#define PXAMMC_MIN_SPEED 312500
#define PXAMMC_MAX_SPEED 20000000
#define PXAMMC_HOST_CAPS (0)
#elif defined(CONFIG_CPU_PXA27X)
#define PXAMMC_CRC_SKIP
#define PXAMMC_FIFO_SIZE 32
#define PXAMMC_MIN_SPEED 304000
#define PXAMMC_MAX_SPEED 19500000
#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT)
#elif defined(CONFIG_CPU_MONAHANS)
#define PXAMMC_FIFO_SIZE 32
#define PXAMMC_MIN_SPEED 304000
#define PXAMMC_MAX_SPEED 26000000
#define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS)
#else
#error "This CPU isn't supported by PXA MMC!"
#endif
#define MMC_STAT_ERRORS \
(MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN | \
MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE | \
MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)
/* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
#define PXA_MMC_TIMEOUT 100
struct pxa_mmc_priv {
struct pxa_mmc_regs *regs;
};
/* Wait for bit to be set */
static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
unsigned int timeout = PXA_MMC_TIMEOUT;
/* Wait for bit to be set */
while (--timeout) {
if (readl(®s->stat) & mask)
break;
udelay(10);
}
if (!timeout)
return -ETIMEDOUT;
return 0;
}
static int pxa_mmc_stop_clock(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
unsigned int timeout = PXA_MMC_TIMEOUT;
/* If the clock aren't running, exit */
if (!(readl(®s->stat) & MMC_STAT_CLK_EN))
return 0;
/* Tell the controller to turn off the clock */
writel(MMC_STRPCL_STOP_CLK, ®s->strpcl);
/* Wait until the clock are off */
while (--timeout) {
if (!(readl(®s->stat) & MMC_STAT_CLK_EN))
break;
udelay(10);
}
/* The clock refused to stop, scream and die a painful death */
if (!timeout)
return -ETIMEDOUT;
/* The clock stopped correctly */
return 0;
}
static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
uint32_t cmdat)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
int ret;
/* The card can send a "busy" response */
if (cmd->flags & MMC_RSP_BUSY)
cmdat |= MMC_CMDAT_BUSY;
/* Inform the controller about response type */
switch (cmd->resp_type) {
case MMC_RSP_R1:
case MMC_RSP_R1b:
cmdat |= MMC_CMDAT_R1;
break;
case MMC_RSP_R2:
cmdat |= MMC_CMDAT_R2;
break;
case MMC_RSP_R3:
cmdat |= MMC_CMDAT_R3;
break;
default:
break;
}
/* Load command and it's arguments into the controller */
writel(cmd->cmdidx, ®s->cmd);
writel(cmd->cmdarg >> 16, ®s->argh);
writel(cmd->cmdarg & 0xffff, ®s->argl);
writel(cmdat, ®s->cmdat);
/* Start the controller clock and wait until they are started */
writel(MMC_STRPCL_START_CLK, ®s->strpcl);
ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
if (ret)
return ret;
/* Correct and happy end */
return 0;
}
static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t a, b, c;
int i;
int stat;
/* Read the controller status */
stat = readl(®s->stat);
/*
* Linux says:
* Did I mention this is Sick. We always need to
* discard the upper 8 bits of the first 16-bit word.
*/
a = readl(®s->res) & 0xffff;
for (i = 0; i < 4; i++) {
b = readl(®s->res) & 0xffff;
c = readl(®s->res) & 0xffff;
cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
a = c;
}
/* The command response didn't arrive */
if (stat & MMC_STAT_TIME_OUT_RESPONSE)
return -ETIMEDOUT;
else if (stat & MMC_STAT_RES_CRC_ERROR && cmd->flags & MMC_RSP_CRC) {
#ifdef PXAMMC_CRC_SKIP
if (cmd->flags & MMC_RSP_136 && cmd->response[0] & (1 << 31))
printf("Ignoring CRC, this may be dangerous!\n");
else
#endif
return -EILSEQ;
}
/* The command response was successfully read */
return 0;
}
static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t len;
uint32_t *buf = (uint32_t *)data->dest;
int size;
int ret;
len = data->blocks * data->blocksize;
while (len) {
/* The controller has data ready */
if (readl(®s->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
size = min(len, PXAMMC_FIFO_SIZE);
len -= size;
size /= 4;
/* Read data into the buffer */
while (size--)
*buf++ = readl(®s->rxfifo);
}
if (readl(®s->stat) & MMC_STAT_ERRORS)
return -EIO;
}
/* Wait for the transmission-done interrupt */
ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
if (ret)
return ret;
return 0;
}
static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t len;
uint32_t *buf = (uint32_t *)data->src;
int size;
int ret;
len = data->blocks * data->blocksize;
while (len) {
/* The controller is ready to receive data */
if (readl(®s->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
size = min(len, PXAMMC_FIFO_SIZE);
len -= size;
size /= 4;
while (size--)
writel(*buf++, ®s->txfifo);
if (min(len, PXAMMC_FIFO_SIZE) < 32)
writel(MMC_PRTBUF_BUF_PART_FULL, ®s->prtbuf);
}
if (readl(®s->stat) & MMC_STAT_ERRORS)
return -EIO;
}
/* Wait for the transmission-done interrupt */
ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
if (ret)
return ret;
/* Wait until the data are really written to the card */
ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
if (ret)
return ret;
return 0;
}
static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t cmdat = 0;
int ret;
/* Stop the controller */
ret = pxa_mmc_stop_clock(mmc);
if (ret)
return ret;
/* If we're doing data transfer, configure the controller accordingly */
if (data) {
writel(data->blocks, ®s->nob);
writel(data->blocksize, ®s->blklen);
/* This delay can be optimized, but stick with max value */
writel(0xffff, ®s->rdto);
cmdat |= MMC_CMDAT_DATA_EN;
if (data->flags & MMC_DATA_WRITE)
cmdat |= MMC_CMDAT_WRITE;
}
/* Run in 4bit mode if the card can do it */
if (mmc->bus_width == 4)
cmdat |= MMC_CMDAT_SD_4DAT;
/* Execute the command */
ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
if (ret)
return ret;
/* Wait until the command completes */
ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
if (ret)
return ret;
/* Read back the result */
ret = pxa_mmc_cmd_done(mmc, cmd);
if (ret)
return ret;
/* In case there was a data transfer scheduled, do it */
if (data) {
if (data->flags & MMC_DATA_WRITE)
pxa_mmc_do_write_xfer(mmc, data);
else
pxa_mmc_do_read_xfer(mmc, data);
}
return 0;
}
static void pxa_mmc_set_ios(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
uint32_t tmp;
uint32_t pxa_mmc_clock;
if (!mmc->clock) {
pxa_mmc_stop_clock(mmc);
return;
}
/* PXA3xx can do 26MHz with special settings. */
if (mmc->clock == 26000000) {
writel(0x7, ®s->clkrt);
return;
}
/* Set clock to the card the usual way. */
pxa_mmc_clock = 0;
tmp = mmc->f_max / mmc->clock;
tmp += tmp % 2;
while (tmp > 1) {
pxa_mmc_clock++;
tmp >>= 1;
}
writel(pxa_mmc_clock, ®s->clkrt);
}
static int pxa_mmc_init(struct mmc *mmc)
{
struct pxa_mmc_priv *priv = (struct pxa_mmc_priv *)mmc->priv;
struct pxa_mmc_regs *regs = priv->regs;
/* Make sure the clock are stopped */
pxa_mmc_stop_clock(mmc);
/* Turn off SPI mode */
writel(0, ®s->spi);
/* Set up maximum timeout to wait for command response */
writel(MMC_RES_TO_MAX_MASK, ®s->resto);
/* Mask all interrupts */
writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
®s->i_mask);
return 0;
}
int pxa_mmc_register(int card_index)
{
struct mmc *mmc;
struct pxa_mmc_priv *priv;
uint32_t reg;
int ret = -ENOMEM;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
goto err0;
priv = malloc(sizeof(struct pxa_mmc_priv));
if (!priv)
goto err1;
switch (card_index) {
case 0:
priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
break;
case 1:
priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
break;
default:
printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
card_index);
goto err2;
}
mmc->priv = priv;
sprintf(mmc->name, "PXA MMC");
mmc->send_cmd = pxa_mmc_request;
mmc->set_ios = pxa_mmc_set_ios;
mmc->init = pxa_mmc_init;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->f_max = PXAMMC_MAX_SPEED;
mmc->f_min = PXAMMC_MIN_SPEED;
mmc->host_caps = PXAMMC_HOST_CAPS;
mmc->b_max = 0;
#ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
reg = readl(CKEN);
reg |= CKEN12_MMC;
writel(reg, CKEN);
#else /* PXA3xx */
reg = readl(CKENA);
reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
writel(reg, CKENA);
#endif
mmc_register(mmc);
return 0;
err2:
free(priv);
err1:
free(mmc);
err0:
return ret;
}
|
1001-study-uboot
|
drivers/mmc/pxa_mmc_gen.c
|
C
|
gpl3
| 10,345
|
/*
* Copyright (C) 2004-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <part.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include "atmel_mci.h"
#ifdef DEBUG
#define pr_debug(fmt, args...) printf(fmt, ##args)
#else
#define pr_debug(...) do { } while(0)
#endif
#ifndef CONFIG_SYS_MMC_CLK_OD
#define CONFIG_SYS_MMC_CLK_OD 150000
#endif
#ifndef CONFIG_SYS_MMC_CLK_PP
#define CONFIG_SYS_MMC_CLK_PP 5000000
#endif
#ifndef CONFIG_SYS_MMC_OP_COND
#define CONFIG_SYS_MMC_OP_COND 0x00100000
#endif
#define MMC_DEFAULT_BLKLEN 512
#define MMC_DEFAULT_RCA 1
static unsigned int mmc_rca;
static int mmc_card_is_sd;
static block_dev_desc_t mmc_blkdev;
block_dev_desc_t *mmc_get_dev(int dev)
{
return &mmc_blkdev;
}
static void mci_set_mode(unsigned long hz, unsigned long blklen)
{
unsigned long bus_hz;
unsigned long clkdiv;
bus_hz = get_mci_clk_rate();
clkdiv = (bus_hz / hz) / 2 - 1;
pr_debug("mmc: setting clock %lu Hz, block size %lu\n",
hz, blklen);
if (clkdiv & ~255UL) {
clkdiv = 255;
printf("mmc: clock %lu too low; setting CLKDIV to 255\n",
hz);
}
blklen &= 0xfffc;
mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv)
| MMCI_BF(BLKLEN, blklen)
| MMCI_BIT(RDPROOF)
| MMCI_BIT(WRPROOF)));
}
#define RESP_NO_CRC 1
#define R1 MMCI_BF(RSPTYP, 1)
#define R2 MMCI_BF(RSPTYP, 2)
#define R3 (R1 | RESP_NO_CRC)
#define R6 R1
#define NID MMCI_BF(MAXLAT, 0)
#define NCR MMCI_BF(MAXLAT, 1)
#define TRCMD_START MMCI_BF(TRCMD, 1)
#define TRDIR_READ MMCI_BF(TRDIR, 1)
#define TRTYP_BLOCK MMCI_BF(TRTYP, 0)
#define INIT_CMD MMCI_BF(SPCMD, 1)
#define OPEN_DRAIN MMCI_BF(OPDCMD, 1)
#define ERROR_FLAGS (MMCI_BIT(DTOE) \
| MMCI_BIT(RDIRE) \
| MMCI_BIT(RENDE) \
| MMCI_BIT(RINDE) \
| MMCI_BIT(RTOE))
static int
mmc_cmd(unsigned long cmd, unsigned long arg,
void *resp, unsigned long flags)
{
unsigned long *response = resp;
int i, response_words = 0;
unsigned long error_flags;
u32 status;
pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n",
cmd, arg, flags);
error_flags = ERROR_FLAGS;
if (!(flags & RESP_NO_CRC))
error_flags |= MMCI_BIT(RCRCE);
flags &= ~MMCI_BF(CMDNB, ~0UL);
if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP)
response_words = 1;
else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP)
response_words = 4;
mmci_writel(ARGR, arg);
mmci_writel(CMDR, cmd | flags);
do {
udelay(40);
status = mmci_readl(SR);
} while (!(status & MMCI_BIT(CMDRDY)));
pr_debug("mmc: status 0x%08x\n", status);
if (status & error_flags) {
printf("mmc: command %lu failed (status: 0x%08x)\n",
cmd, status);
return -EIO;
}
if (response_words)
pr_debug("mmc: response:");
for (i = 0; i < response_words; i++) {
response[i] = mmci_readl(RSPR);
pr_debug(" %08lx", response[i]);
}
pr_debug("\n");
return 0;
}
static int mmc_acmd(unsigned long cmd, unsigned long arg,
void *resp, unsigned long flags)
{
unsigned long aresp[4];
int ret;
/*
* Seems like the APP_CMD part of an ACMD has 64 cycles max
* latency even though the ACMD part doesn't. This isn't
* entirely clear in the SD Card spec, but some cards refuse
* to work if we attempt to use 5 cycles max latency here...
*/
ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp,
R1 | NCR | (flags & OPEN_DRAIN));
if (ret)
return ret;
if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD)
return -ENODEV;
ret = mmc_cmd(cmd, arg, resp, flags);
return ret;
}
static unsigned long
mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
void *buffer)
{
int ret, i = 0;
unsigned long resp[4];
unsigned long card_status, data;
unsigned long wordcount;
u32 *p = buffer;
u32 status;
if (blkcnt == 0)
return 0;
pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n",
dev, start, blkcnt);
/* Put the device into Transfer state */
ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
if (ret) goto out;
/* Set block length */
ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
if (ret) goto out;
pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
for (i = 0; i < blkcnt; i++, start++) {
ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK,
start * mmc_blkdev.blksz, resp,
(R1 | NCR | TRCMD_START | TRDIR_READ
| TRTYP_BLOCK));
if (ret) goto out;
ret = -EIO;
wordcount = 0;
do {
do {
status = mmci_readl(SR);
if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
goto read_error;
} while (!(status & MMCI_BIT(RXRDY)));
if (status & MMCI_BIT(RXRDY)) {
data = mmci_readl(RDR);
/* pr_debug("%x\n", data); */
*p++ = data;
wordcount++;
}
} while(wordcount < (mmc_blkdev.blksz / 4));
pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount);
do {
status = mmci_readl(SR);
} while (!(status & MMCI_BIT(BLKE)));
putc('.');
}
out:
/* Put the device back into Standby state */
mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
return i;
read_error:
mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
printf("mmc: bread failed, status = %08x, card status = %08lx\n",
status, card_status);
goto out;
}
static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp)
{
cid->mid = resp[0] >> 24;
cid->oid = (resp[0] >> 8) & 0xffff;
cid->pnm[0] = resp[0];
cid->pnm[1] = resp[1] >> 24;
cid->pnm[2] = resp[1] >> 16;
cid->pnm[3] = resp[1] >> 8;
cid->pnm[4] = resp[1];
cid->pnm[5] = resp[2] >> 24;
cid->pnm[6] = 0;
cid->prv = resp[2] >> 16;
cid->psn = (resp[2] << 16) | (resp[3] >> 16);
cid->mdt = resp[3] >> 8;
}
static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp)
{
cid->mid = resp[0] >> 24;
cid->oid = (resp[0] >> 8) & 0xffff;
cid->pnm[0] = resp[0];
cid->pnm[1] = resp[1] >> 24;
cid->pnm[2] = resp[1] >> 16;
cid->pnm[3] = resp[1] >> 8;
cid->pnm[4] = resp[1];
cid->pnm[5] = 0;
cid->pnm[6] = 0;
cid->prv = resp[2] >> 24;
cid->psn = (resp[2] << 8) | (resp[3] >> 24);
cid->mdt = (resp[3] >> 8) & 0x0fff;
}
static void mmc_dump_cid(const struct mmc_cid *cid)
{
printf("Manufacturer ID: %02X\n", cid->mid);
printf("OEM/Application ID: %04X\n", cid->oid);
printf("Product name: %s\n", cid->pnm);
printf("Product Revision: %u.%u\n",
cid->prv >> 4, cid->prv & 0x0f);
printf("Product Serial Number: %lu\n", cid->psn);
printf("Manufacturing Date: %02u/%02u\n",
cid->mdt >> 4, cid->mdt & 0x0f);
}
static void mmc_dump_csd(const struct mmc_csd *csd)
{
unsigned long *csd_raw = (unsigned long *)csd;
printf("CSD data: %08lx %08lx %08lx %08lx\n",
csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]);
printf("CSD structure version: 1.%u\n", csd->csd_structure);
printf("MMC System Spec version: %u\n", csd->spec_vers);
printf("Card command classes: %03x\n", csd->ccc);
printf("Read block length: %u\n", 1 << csd->read_bl_len);
if (csd->read_bl_partial)
puts("Supports partial reads\n");
else
puts("Does not support partial reads\n");
printf("Write block length: %u\n", 1 << csd->write_bl_len);
if (csd->write_bl_partial)
puts("Supports partial writes\n");
else
puts("Does not support partial writes\n");
if (csd->wp_grp_enable)
printf("Supports group WP: %u\n", csd->wp_grp_size + 1);
else
puts("Does not support group WP\n");
printf("Card capacity: %u bytes\n",
(csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) *
(1 << csd->read_bl_len));
printf("File format: %u/%u\n",
csd->file_format_grp, csd->file_format);
puts("Write protection: ");
if (csd->perm_write_protect)
puts(" permanent");
if (csd->tmp_write_protect)
puts(" temporary");
putc('\n');
}
static int mmc_idle_cards(void)
{
int ret;
/* Reset and initialize all cards */
ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
if (ret)
return ret;
/* Keep the bus idle for 74 clock cycles */
return mmc_cmd(0, 0, NULL, INIT_CMD);
}
static int sd_init_card(struct mmc_cid *cid, int verbose)
{
unsigned long resp[4];
int i, ret = 0;
mmc_idle_cards();
for (i = 0; i < 1000; i++) {
ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND,
resp, R3 | NID);
if (ret || (resp[0] & 0x80000000))
break;
ret = -ETIMEDOUT;
}
if (ret)
return ret;
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID);
if (ret)
return ret;
sd_parse_cid(cid, resp);
if (verbose)
mmc_dump_cid(cid);
/* Get RCA of the card that responded */
ret = mmc_cmd(SD_CMD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR);
if (ret)
return ret;
mmc_rca = resp[0] >> 16;
if (verbose)
printf("SD Card detected (RCA %u)\n", mmc_rca);
mmc_card_is_sd = 1;
return 0;
}
static int mmc_init_card(struct mmc_cid *cid, int verbose)
{
unsigned long resp[4];
int i, ret = 0;
mmc_idle_cards();
for (i = 0; i < 1000; i++) {
ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, resp,
R3 | NID | OPEN_DRAIN);
if (ret || (resp[0] & 0x80000000))
break;
ret = -ETIMEDOUT;
}
if (ret)
return ret;
/* Get CID of all cards. FIXME: Support more than one card */
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN);
if (ret)
return ret;
mmc_parse_cid(cid, resp);
if (verbose)
mmc_dump_cid(cid);
/* Set Relative Address of the card that responded */
ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp,
R1 | NCR | OPEN_DRAIN);
return ret;
}
static void mci_set_data_timeout(struct mmc_csd *csd)
{
static const unsigned int dtomul_to_shift[] = {
0, 4, 7, 8, 10, 12, 16, 20,
};
static const unsigned int taac_exp[] = {
1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
};
static const unsigned int taac_mant[] = {
0, 10, 12, 13, 15, 60, 25, 30,
35, 40, 45, 50, 55, 60, 70, 80,
};
unsigned int timeout_ns, timeout_clks;
unsigned int e, m;
unsigned int dtocyc, dtomul;
unsigned int shift;
u32 dtor;
e = csd->taac & 0x07;
m = (csd->taac >> 3) & 0x0f;
timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10;
timeout_clks = csd->nsac * 100;
timeout_clks += (((timeout_ns + 9) / 10)
* ((CONFIG_SYS_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000;
if (!mmc_card_is_sd)
timeout_clks *= 10;
else
timeout_clks *= 100;
dtocyc = timeout_clks;
dtomul = 0;
shift = 0;
while (dtocyc > 15 && dtomul < 8) {
dtomul++;
shift = dtomul_to_shift[dtomul];
dtocyc = (timeout_clks + (1 << shift) - 1) >> shift;
}
if (dtomul >= 8) {
dtomul = 7;
dtocyc = 15;
puts("Warning: Using maximum data timeout\n");
}
dtor = (MMCI_BF(DTOMUL, dtomul)
| MMCI_BF(DTOCYC, dtocyc));
mmci_writel(DTOR, dtor);
printf("mmc: Using %u cycles data timeout (DTOR=0x%x)\n",
dtocyc << shift, dtor);
}
int mmc_legacy_init(int verbose)
{
struct mmc_cid cid;
struct mmc_csd csd;
unsigned int max_blksz;
int ret;
/* Initialize controller */
mmci_writel(CR, MMCI_BIT(SWRST));
mmci_writel(CR, MMCI_BIT(MCIEN));
mmci_writel(DTOR, 0x5f);
mmci_writel(IDR, ~0UL);
mci_set_mode(CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
mmc_card_is_sd = 0;
ret = sd_init_card(&cid, verbose);
if (ret) {
mmc_rca = MMC_DEFAULT_RCA;
ret = mmc_init_card(&cid, verbose);
}
if (ret)
return ret;
/* Get CSD from the card */
ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR);
if (ret)
return ret;
if (verbose)
mmc_dump_csd(&csd);
mci_set_data_timeout(&csd);
/* Initialize the blockdev structure */
mmc_blkdev.if_type = IF_TYPE_MMC;
mmc_blkdev.part_type = PART_TYPE_DOS;
mmc_blkdev.block_read = mmc_bread;
sprintf((char *)mmc_blkdev.vendor,
"Man %02x%04x Snr %08lx",
cid.mid, cid.oid, cid.psn);
strncpy((char *)mmc_blkdev.product, cid.pnm,
sizeof(mmc_blkdev.product));
sprintf((char *)mmc_blkdev.revision, "%x %x",
cid.prv >> 4, cid.prv & 0x0f);
/*
* If we can't use 512 byte blocks, refuse to deal with the
* card. Tons of code elsewhere seems to depend on this.
*/
max_blksz = 1 << csd.read_bl_len;
if (max_blksz < 512 || (max_blksz > 512 && !csd.read_bl_partial)) {
printf("Card does not support 512 byte reads, aborting.\n");
return -ENODEV;
}
mmc_blkdev.blksz = 512;
mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2));
mci_set_mode(CONFIG_SYS_MMC_CLK_PP, mmc_blkdev.blksz);
#if 0
if (fat_register_device(&mmc_blkdev, 1))
printf("Could not register MMC fat device\n");
#else
init_part(&mmc_blkdev);
#endif
return 0;
}
|
1001-study-uboot
|
drivers/mmc/atmel_mci.c
|
C
|
gpl3
| 13,270
|
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Back ported to the 8xx platform (from the 8260 platform) by
* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
*/
#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <sdhci.h>
void *aligned_buffer;
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
unsigned long timeout;
/* Wait max 100 ms */
timeout = 100;
sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
if (timeout == 0) {
printf("Reset 0x%x never completed.\n", (int)mask);
return;
}
timeout--;
udelay(1000);
}
}
static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
{
int i;
if (cmd->resp_type & MMC_RSP_136) {
/* CRC is stripped so we need to do some shifting. */
for (i = 0; i < 4; i++) {
cmd->response[i] = sdhci_readl(host,
SDHCI_RESPONSE + (3-i)*4) << 8;
if (i != 3)
cmd->response[i] |= sdhci_readb(host,
SDHCI_RESPONSE + (3-i)*4-1);
}
} else {
cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
}
}
static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
{
int i;
char *offs;
for (i = 0; i < data->blocksize; i += 4) {
offs = data->dest + i;
if (data->flags == MMC_DATA_READ)
*(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
else
sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
}
}
static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
unsigned int start_addr)
{
unsigned int stat, rdy, mask, timeout, block = 0;
timeout = 10000;
rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR) {
printf("Error detected in status(0x%X)!\n", stat);
return -1;
}
if (stat & rdy) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
continue;
sdhci_writel(host, rdy, SDHCI_INT_STATUS);
sdhci_transfer_pio(host, data);
data->dest += data->blocksize;
if (++block >= data->blocks)
break;
}
#ifdef CONFIG_MMC_SDMA
if (stat & SDHCI_INT_DMA_END) {
sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
}
#endif
if (timeout-- > 0)
udelay(10);
else {
printf("Transfer data timeout\n");
return -1;
}
} while (!(stat & SDHCI_INT_DATA_END));
return 0;
}
int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
unsigned int stat = 0;
int ret = 0;
int trans_bytes = 0, is_aligned = 1;
u32 mask, flags, mode;
unsigned int timeout, start_addr = 0;
/* Wait max 10 ms */
timeout = 10;
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
/* We shouldn't wait for data inihibit for stop commands, even
though they might use busy signaling */
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
mask &= ~SDHCI_DATA_INHIBIT;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
if (timeout == 0) {
printf("Controller never released inhibit bit(s).\n");
return COMM_ERR;
}
timeout--;
udelay(1000);
}
mask = SDHCI_INT_RESPONSE;
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = SDHCI_CMD_RESP_NONE;
else if (cmd->resp_type & MMC_RSP_136)
flags = SDHCI_CMD_RESP_LONG;
else if (cmd->resp_type & MMC_RSP_BUSY) {
flags = SDHCI_CMD_RESP_SHORT_BUSY;
mask |= SDHCI_INT_DATA_END;
} else
flags = SDHCI_CMD_RESP_SHORT;
if (cmd->resp_type & MMC_RSP_CRC)
flags |= SDHCI_CMD_CRC;
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= SDHCI_CMD_INDEX;
if (data)
flags |= SDHCI_CMD_DATA;
/*Set Transfer mode regarding to data flag*/
if (data != 0) {
sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
mode = SDHCI_TRNS_BLK_CNT_EN;
trans_bytes = data->blocks * data->blocksize;
if (data->blocks > 1)
mode |= SDHCI_TRNS_MULTI;
if (data->flags == MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
#ifdef CONFIG_MMC_SDMA
if (data->flags == MMC_DATA_READ)
start_addr = (unsigned int)data->dest;
else
start_addr = (unsigned int)data->src;
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
(start_addr & 0x7) != 0x0) {
is_aligned = 0;
start_addr = (unsigned int)aligned_buffer;
if (data->flags != MMC_DATA_READ)
memcpy(aligned_buffer, data->src, trans_bytes);
}
sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
mode |= SDHCI_TRNS_DMA;
#endif
sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
data->blocksize),
SDHCI_BLOCK_SIZE);
sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
}
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
#ifdef CONFIG_MMC_SDMA
flush_cache(start_addr, trans_bytes);
#endif
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
do {
stat = sdhci_readl(host, SDHCI_INT_STATUS);
if (stat & SDHCI_INT_ERROR)
break;
} while ((stat & mask) != mask);
if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
sdhci_cmd_done(host, cmd);
sdhci_writel(host, mask, SDHCI_INT_STATUS);
} else
ret = -1;
if (!ret && data)
ret = sdhci_transfer_data(host, data, start_addr);
stat = sdhci_readl(host, SDHCI_INT_STATUS);
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
if (!ret) {
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
!is_aligned && (data->flags == MMC_DATA_READ))
memcpy(data->dest, aligned_buffer, trans_bytes);
return 0;
}
sdhci_reset(host, SDHCI_RESET_CMD);
sdhci_reset(host, SDHCI_RESET_DATA);
if (stat & SDHCI_INT_TIMEOUT)
return TIMEOUT;
else
return COMM_ERR;
}
static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
{
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
unsigned int div, clk, timeout;
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
if (clock == 0)
return 0;
if (host->version >= SDHCI_SPEC_300) {
/* Version 3.00 divisors must be a multiple of 2. */
if (mmc->f_max <= clock)
div = 1;
else {
for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
if ((mmc->f_max / div) <= clock)
break;
}
}
} else {
/* Version 2.00 divisors must be a power of 2. */
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
if ((mmc->f_max / div) <= clock)
break;
}
}
div >>= 1;
clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
clk |= SDHCI_CLOCK_INT_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
/* Wait max 20 ms */
timeout = 20;
while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
& SDHCI_CLOCK_INT_STABLE)) {
if (timeout == 0) {
printf("Internal clock never stabilised.\n");
return -1;
}
timeout--;
udelay(1000);
}
clk |= SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
return 0;
}
static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
{
u8 pwr = 0;
if (power != (unsigned short)-1) {
switch (1 << power) {
case MMC_VDD_165_195:
pwr = SDHCI_POWER_180;
break;
case MMC_VDD_29_30:
case MMC_VDD_30_31:
pwr = SDHCI_POWER_300;
break;
case MMC_VDD_32_33:
case MMC_VDD_33_34:
pwr = SDHCI_POWER_330;
break;
}
}
if (pwr == 0) {
sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
return;
}
pwr |= SDHCI_POWER_ON;
sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
}
void sdhci_set_ios(struct mmc *mmc)
{
u32 ctrl;
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
if (mmc->clock != host->clock)
sdhci_set_clock(mmc, mmc->clock);
/* Set bus width */
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
if (mmc->bus_width == 8) {
ctrl &= ~SDHCI_CTRL_4BITBUS;
if (host->version >= SDHCI_SPEC_300)
ctrl |= SDHCI_CTRL_8BITBUS;
} else {
if (host->version >= SDHCI_SPEC_300)
ctrl &= ~SDHCI_CTRL_8BITBUS;
if (mmc->bus_width == 4)
ctrl |= SDHCI_CTRL_4BITBUS;
else
ctrl &= ~SDHCI_CTRL_4BITBUS;
}
if (mmc->clock > 26000000)
ctrl |= SDHCI_CTRL_HISPD;
else
ctrl &= ~SDHCI_CTRL_HISPD;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
int sdhci_init(struct mmc *mmc)
{
struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
aligned_buffer = memalign(8, 512*1024);
if (!aligned_buffer) {
printf("Aligned buffer alloc failed!!!");
return -1;
}
}
/* Eable all state */
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE);
sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE);
sdhci_set_power(host, fls(mmc->voltages) - 1);
return 0;
}
int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
{
struct mmc *mmc;
unsigned int caps;
mmc = malloc(sizeof(struct mmc));
if (!mmc) {
printf("mmc malloc fail!\n");
return -1;
}
mmc->priv = host;
host->mmc = mmc;
sprintf(mmc->name, "%s", host->name);
mmc->send_cmd = sdhci_send_command;
mmc->set_ios = sdhci_set_ios;
mmc->init = sdhci_init;
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
#ifdef CONFIG_MMC_SDMA
if (!(caps & SDHCI_CAN_DO_SDMA)) {
printf("Your controller don't support sdma!!\n");
return -1;
}
#endif
if (max_clk)
mmc->f_max = max_clk;
else {
if (host->version >= SDHCI_SPEC_300)
mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
else
mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
mmc->f_max *= 1000000;
}
if (mmc->f_max == 0) {
printf("Hardware doesn't specify base clock frequency\n");
return -1;
}
if (min_clk)
mmc->f_min = min_clk;
else {
if (host->version >= SDHCI_SPEC_300)
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
else
mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
}
mmc->voltages = 0;
if (caps & SDHCI_CAN_VDD_330)
mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
if (caps & SDHCI_CAN_VDD_300)
mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
if (caps & SDHCI_CAN_VDD_180)
mmc->voltages |= MMC_VDD_165_195;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
if (caps & SDHCI_CAN_DO_8BIT)
mmc->host_caps |= MMC_MODE_8BIT;
sdhci_reset(host, SDHCI_RESET_ALL);
mmc_register(mmc);
return 0;
}
|
1001-study-uboot
|
drivers/mmc/sdhci.c
|
C
|
gpl3
| 11,217
|
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Jaehoon Chung <jh80.chung@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/mmc.h>
#include <asm/arch/clk.h>
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
struct mmc_host mmc_host[4];
static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index)
{
unsigned long offset = dev_index * sizeof(struct s5p_mmc);
return (struct s5p_mmc *)(samsung_get_base_mmc() + offset);
}
static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
{
unsigned char ctrl;
debug("data->dest: %08x\n", (u32)data->dest);
writel((u32)data->dest, &host->reg->sysad);
/*
* DMASEL[4:3]
* 00 = Selects SDMA
* 01 = Reserved
* 10 = Selects 32-bit Address ADMA2
* 11 = Selects 64-bit Address ADMA2
*/
ctrl = readb(&host->reg->hostctl);
ctrl &= ~(3 << 3);
writeb(ctrl, &host->reg->hostctl);
/* We do not handle DMA boundaries, so set it to max (512 KiB) */
writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
writew(data->blocks, &host->reg->blkcnt);
}
static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
{
unsigned short mode;
/*
* TRNMOD
* MUL1SIN0[5] : Multi/Single Block Select
* RD1WT0[4] : Data Transfer Direction Select
* 1 = read
* 0 = write
* ENACMD12[2] : Auto CMD12 Enable
* ENBLKCNT[1] : Block Count Enable
* ENDMA[0] : DMA Enable
*/
mode = (1 << 1) | (1 << 0);
if (data->blocks > 1)
mode |= (1 << 5);
if (data->flags & MMC_DATA_READ)
mode |= (1 << 4);
writew(mode, &host->reg->trnmod);
}
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
int flags, i;
unsigned int timeout;
unsigned int mask;
unsigned int retry = 0x100000;
/* Wait max 10 ms */
timeout = 10;
/*
* PRNSTS
* CMDINHDAT[1] : Command Inhibit (DAT)
* CMDINHCMD[0] : Command Inhibit (CMD)
*/
mask = (1 << 0);
if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
mask |= (1 << 1);
/*
* We shouldn't wait for data inihibit for stop commands, even
* though they might use busy signaling
*/
if (data)
mask &= ~(1 << 1);
while (readl(&host->reg->prnsts) & mask) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return -1;
}
timeout--;
udelay(1000);
}
if (data)
mmc_prepare_data(host, data);
debug("cmd->arg: %08x\n", cmd->cmdarg);
writel(cmd->cmdarg, &host->reg->argument);
if (data)
mmc_set_transfer_mode(host, data);
if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
return -1;
/*
* CMDREG
* CMDIDX[13:8] : Command index
* DATAPRNT[5] : Data Present Select
* ENCMDIDX[4] : Command Index Check Enable
* ENCMDCRC[3] : Command CRC Check Enable
* RSPTYP[1:0]
* 00 = No Response
* 01 = Length 136
* 10 = Length 48
* 11 = Length 48 Check busy after response
*/
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = 0;
else if (cmd->resp_type & MMC_RSP_136)
flags = (1 << 0);
else if (cmd->resp_type & MMC_RSP_BUSY)
flags = (3 << 0);
else
flags = (2 << 0);
if (cmd->resp_type & MMC_RSP_CRC)
flags |= (1 << 3);
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= (1 << 4);
if (data)
flags |= (1 << 5);
debug("cmd: %d\n", cmd->cmdidx);
writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
for (i = 0; i < retry; i++) {
mask = readl(&host->reg->norintsts);
/* Command Complete */
if (mask & (1 << 0)) {
if (!data)
writel(mask, &host->reg->norintsts);
break;
}
}
if (i == retry) {
printf("%s: waiting for status update\n", __func__);
return TIMEOUT;
}
if (mask & (1 << 16)) {
/* Timeout Error */
debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
return TIMEOUT;
} else if (mask & (1 << 15)) {
/* Error Interrupt */
debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
return -1;
}
if (cmd->resp_type & MMC_RSP_PRESENT) {
if (cmd->resp_type & MMC_RSP_136) {
/* CRC is stripped so we need to do some shifting. */
for (i = 0; i < 4; i++) {
unsigned int offset =
(unsigned int)(&host->reg->rspreg3 - i);
cmd->response[i] = readl(offset) << 8;
if (i != 3) {
cmd->response[i] |=
readb(offset - 1);
}
debug("cmd->resp[%d]: %08x\n",
i, cmd->response[i]);
}
} else if (cmd->resp_type & MMC_RSP_BUSY) {
for (i = 0; i < retry; i++) {
/* PRNTDATA[23:20] : DAT[3:0] Line Signal */
if (readl(&host->reg->prnsts)
& (1 << 20)) /* DAT[0] */
break;
}
if (i == retry) {
printf("%s: card is still busy\n", __func__);
return TIMEOUT;
}
cmd->response[0] = readl(&host->reg->rspreg0);
debug("cmd->resp[0]: %08x\n", cmd->response[0]);
} else {
cmd->response[0] = readl(&host->reg->rspreg0);
debug("cmd->resp[0]: %08x\n", cmd->response[0]);
}
}
if (data) {
while (1) {
mask = readl(&host->reg->norintsts);
if (mask & (1 << 15)) {
/* Error Interrupt */
writel(mask, &host->reg->norintsts);
printf("%s: error during transfer: 0x%08x\n",
__func__, mask);
return -1;
} else if (mask & (1 << 3)) {
/*
* DMA Interrupt, restart the transfer where
* it was interrupted.
*/
unsigned int address = readl(&host->reg->sysad);
debug("DMA end\n");
writel((1 << 3), &host->reg->norintsts);
writel(address, &host->reg->sysad);
} else if (mask & (1 << 1)) {
/* Transfer Complete */
debug("r/w is done\n");
break;
}
}
writel(mask, &host->reg->norintsts);
}
udelay(1000);
return 0;
}
static void mmc_change_clock(struct mmc_host *host, uint clock)
{
int div;
unsigned short clk;
unsigned long timeout;
unsigned long ctrl2;
/*
* SELBASECLK[5:4]
* 00/01 = HCLK
* 10 = EPLL
* 11 = XTI or XEXTCLK
*/
ctrl2 = readl(&host->reg->control2);
ctrl2 &= ~(3 << 4);
ctrl2 |= (2 << 4);
writel(ctrl2, &host->reg->control2);
writew(0, &host->reg->clkcon);
/* XXX: we assume that clock is between 40MHz and 50MHz */
if (clock == 0)
goto out;
else if (clock <= 400000)
div = 0x100;
else if (clock <= 20000000)
div = 4;
else if (clock <= 26000000)
div = 2;
else
div = 1;
debug("div: %d\n", div);
div >>= 1;
/*
* CLKCON
* SELFREQ[15:8] : base clock divied by value
* ENSDCLK[2] : SD Clock Enable
* STBLINTCLK[1] : Internal Clock Stable
* ENINTCLK[0] : Internal Clock Enable
*/
clk = (div << 8) | (1 << 0);
writew(clk, &host->reg->clkcon);
set_mmc_clk(host->dev_index, div);
/* Wait max 10 ms */
timeout = 10;
while (!(readw(&host->reg->clkcon) & (1 << 1))) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return;
}
timeout--;
udelay(1000);
}
clk |= (1 << 2);
writew(clk, &host->reg->clkcon);
out:
host->clock = clock;
}
static void mmc_set_ios(struct mmc *mmc)
{
struct mmc_host *host = mmc->priv;
unsigned char ctrl;
unsigned long val;
debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
/*
* SELCLKPADDS[17:16]
* 00 = 2mA
* 01 = 4mA
* 10 = 7mA
* 11 = 9mA
*/
writel(0x3 << 16, &host->reg->control4);
val = readl(&host->reg->control2);
val &= (0x3 << 4);
val |= (1 << 31) | /* write status clear async mode enable */
(1 << 30) | /* command conflict mask enable */
(1 << 14) | /* Feedback Clock Enable for Rx Clock */
(1 << 8); /* SDCLK hold enable */
writel(val, &host->reg->control2);
/*
* FCSEL1[15] FCSEL0[7]
* FCSel[1:0] : Rx Feedback Clock Delay Control
* Inverter delay means10ns delay if SDCLK 50MHz setting
* 01 = Delay1 (basic delay)
* 11 = Delay2 (basic delay + 2ns)
* 00 = Delay3 (inverter delay)
* 10 = Delay4 (inverter delay + 2ns)
*/
writel(0x8080, &host->reg->control3);
mmc_change_clock(host, mmc->clock);
ctrl = readb(&host->reg->hostctl);
/*
* WIDE8[5]
* 0 = Depend on WIDE4
* 1 = 8-bit mode
* WIDE4[1]
* 1 = 4-bit mode
* 0 = 1-bit mode
*/
if (mmc->bus_width == 8)
ctrl |= (1 << 5);
else if (mmc->bus_width == 4)
ctrl |= (1 << 1);
else
ctrl &= ~(1 << 1);
/*
* OUTEDGEINV[2]
* 1 = Riging edge output
* 0 = Falling edge output
*/
ctrl &= ~(1 << 2);
writeb(ctrl, &host->reg->hostctl);
}
static void mmc_reset(struct mmc_host *host)
{
unsigned int timeout;
/*
* RSTALL[0] : Software reset for all
* 1 = reset
* 0 = work
*/
writeb((1 << 0), &host->reg->swrst);
host->clock = 0;
/* Wait max 100 ms */
timeout = 100;
/* hw clears the bit when it's done */
while (readb(&host->reg->swrst) & (1 << 0)) {
if (timeout == 0) {
printf("%s: timeout error\n", __func__);
return;
}
timeout--;
udelay(1000);
}
}
static int mmc_core_init(struct mmc *mmc)
{
struct mmc_host *host = (struct mmc_host *)mmc->priv;
unsigned int mask;
mmc_reset(host);
host->version = readw(&host->reg->hcver);
/* mask all */
writel(0xffffffff, &host->reg->norintstsen);
writel(0xffffffff, &host->reg->norintsigen);
writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
/*
* NORMAL Interrupt Status Enable Register init
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
* [3] ENSTADMAINT : DMA Interrupt Status Enable
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
* [0] ENSTACMDCMPLT : Command Complete Status Enable
*/
mask = readl(&host->reg->norintstsen);
mask &= ~(0xffff);
mask |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1) | (1 << 0);
writel(mask, &host->reg->norintstsen);
/*
* NORMAL Interrupt Signal Enable Register init
* [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
*/
mask = readl(&host->reg->norintsigen);
mask &= ~(0xffff);
mask |= (1 << 1);
writel(mask, &host->reg->norintsigen);
return 0;
}
static int s5p_mmc_initialize(int dev_index, int bus_width)
{
struct mmc *mmc;
mmc = &mmc_dev[dev_index];
sprintf(mmc->name, "SAMSUNG SD/MMC");
mmc->priv = &mmc_host[dev_index];
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_core_init;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
if (bus_width == 8)
mmc->host_caps = MMC_MODE_8BIT;
else
mmc->host_caps = MMC_MODE_4BIT;
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
mmc->f_min = 400000;
mmc->f_max = 52000000;
mmc_host[dev_index].dev_index = dev_index;
mmc_host[dev_index].clock = 0;
mmc_host[dev_index].reg = s5p_get_base_mmc(dev_index);
mmc->b_max = 0;
mmc_register(mmc);
return 0;
}
int s5p_mmc_init(int dev_index, int bus_width)
{
return s5p_mmc_initialize(dev_index, bus_width);
}
|
1001-study-uboot
|
drivers/mmc/s5p_mmc.c
|
C
|
gpl3
| 11,313
|
/*
* MMCIF driver.
*
* Copyright (C) 2011 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*
*/
#ifndef _SH_MMCIF_H_
#define _SH_MMCIF_H_
struct sh_mmcif_regs {
unsigned long ce_cmd_set;
unsigned long reserved;
unsigned long ce_arg;
unsigned long ce_arg_cmd12;
unsigned long ce_cmd_ctrl;
unsigned long ce_block_set;
unsigned long ce_clk_ctrl;
unsigned long ce_buf_acc;
unsigned long ce_resp3;
unsigned long ce_resp2;
unsigned long ce_resp1;
unsigned long ce_resp0;
unsigned long ce_resp_cmd12;
unsigned long ce_data;
unsigned long reserved2[2];
unsigned long ce_int;
unsigned long ce_int_mask;
unsigned long ce_host_sts1;
unsigned long ce_host_sts2;
unsigned long reserved3[11];
unsigned long ce_version;
};
/* CE_CMD_SET */
#define CMD_MASK 0x3f000000
#define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
/* R1/R1b/R3/R4/R5 */
#define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22))
/* R2 */
#define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22))
/* R1b */
#define CMD_SET_RBSY (1 << 21)
#define CMD_SET_CCSEN (1 << 20)
/* 1: on data, 0: no data */
#define CMD_SET_WDAT (1 << 19)
/* 1: write to card, 0: read from card */
#define CMD_SET_DWEN (1 << 18)
/* 1: multi block trans, 0: single */
#define CMD_SET_CMLTE (1 << 17)
/* 1: CMD12 auto issue */
#define CMD_SET_CMD12EN (1 << 16)
/* index check */
#define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14))
/* check bits check */
#define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14))
/* no check */
#define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14))
/* 1: CRC7 check*/
#define CMD_SET_CRC7C ((0 << 13) | (0 << 12))
/* 1: check bits check*/
#define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12))
/* 1: internal CRC7 check*/
#define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12))
/* 1: CRC16 check*/
#define CMD_SET_CRC16C (1 << 10)
/* 1: not receive CRC status */
#define CMD_SET_CRCSTE (1 << 8)
/* 1: tran mission bit "Low" */
#define CMD_SET_TBIT (1 << 7)
/* 1: open/drain */
#define CMD_SET_OPDM (1 << 6)
#define CMD_SET_CCSH (1 << 5)
/* 1bit */
#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0))
/* 4bit */
#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0))
/* 8bit */
#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0))
/* CE_CMD_CTRL */
#define CMD_CTRL_BREAK (1 << 0)
/* CE_BLOCK_SET */
#define BLOCK_SIZE_MASK 0x0000ffff
/* CE_CLK_CTRL */
#define CLK_ENABLE (1 << 24)
#define CLK_CLEAR ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
#define CLK_PCLK ((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))
/* respons timeout */
#define SRSPTO_256 ((1 << 13) | (0 << 12))
/* respons busy timeout */
#define SRBSYTO_29 ((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8))
/* read/write timeout */
#define SRWDTO_29 ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
/* ccs timeout */
#define SCCSTO_29 ((1 << 3) | (1 << 2) | (1 << 1) | (1 << 0))
/* CE_BUF_ACC */
#define BUF_ACC_DMAWEN (1 << 25)
#define BUF_ACC_DMAREN (1 << 24)
#define BUF_ACC_BUSW_32 (0 << 17)
#define BUF_ACC_BUSW_16 (1 << 17)
#define BUF_ACC_ATYP (1 << 16)
/* CE_INT */
#define INT_CCSDE (1 << 29)
#define INT_CMD12DRE (1 << 26)
#define INT_CMD12RBE (1 << 25)
#define INT_CMD12CRE (1 << 24)
#define INT_DTRANE (1 << 23)
#define INT_BUFRE (1 << 22)
#define INT_BUFWEN (1 << 21)
#define INT_BUFREN (1 << 20)
#define INT_CCSRCV (1 << 19)
#define INT_RBSYE (1 << 17)
#define INT_CRSPE (1 << 16)
#define INT_CMDVIO (1 << 15)
#define INT_BUFVIO (1 << 14)
#define INT_WDATERR (1 << 11)
#define INT_RDATERR (1 << 10)
#define INT_RIDXERR (1 << 9)
#define INT_RSPERR (1 << 8)
#define INT_CCSTO (1 << 5)
#define INT_CRCSTO (1 << 4)
#define INT_WDATTO (1 << 3)
#define INT_RDATTO (1 << 2)
#define INT_RBSYTO (1 << 1)
#define INT_RSPTO (1 << 0)
#define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
INT_RDATTO | INT_RBSYTO | INT_RSPTO)
#define INT_START_MAGIC 0xD80430C0
/* CE_INT_MASK */
#define MASK_ALL 0x00000000
#define MASK_MCCSDE (1 << 29)
#define MASK_MCMD12DRE (1 << 26)
#define MASK_MCMD12RBE (1 << 25)
#define MASK_MCMD12CRE (1 << 24)
#define MASK_MDTRANE (1 << 23)
#define MASK_MBUFRE (1 << 22)
#define MASK_MBUFWEN (1 << 21)
#define MASK_MBUFREN (1 << 20)
#define MASK_MCCSRCV (1 << 19)
#define MASK_MRBSYE (1 << 17)
#define MASK_MCRSPE (1 << 16)
#define MASK_MCMDVIO (1 << 15)
#define MASK_MBUFVIO (1 << 14)
#define MASK_MWDATERR (1 << 11)
#define MASK_MRDATERR (1 << 10)
#define MASK_MRIDXERR (1 << 9)
#define MASK_MRSPERR (1 << 8)
#define MASK_MCCSTO (1 << 5)
#define MASK_MCRCSTO (1 << 4)
#define MASK_MWDATTO (1 << 3)
#define MASK_MRDATTO (1 << 2)
#define MASK_MRBSYTO (1 << 1)
#define MASK_MRSPTO (1 << 0)
/* CE_HOST_STS1 */
#define STS1_CMDSEQ (1 << 31)
/* CE_HOST_STS2 */
#define STS2_CRCSTE (1 << 31)
#define STS2_CRC16E (1 << 30)
#define STS2_AC12CRCE (1 << 29)
#define STS2_RSPCRC7E (1 << 28)
#define STS2_CRCSTEBE (1 << 27)
#define STS2_RDATEBE (1 << 26)
#define STS2_AC12REBE (1 << 25)
#define STS2_RSPEBE (1 << 24)
#define STS2_AC12IDXE (1 << 23)
#define STS2_RSPIDXE (1 << 22)
#define STS2_CCSTO (1 << 15)
#define STS2_RDATTO (1 << 14)
#define STS2_DATBSYTO (1 << 13)
#define STS2_CRCSTTO (1 << 12)
#define STS2_AC12BSYTO (1 << 11)
#define STS2_RSPBSYTO (1 << 10)
#define STS2_AC12RSPTO (1 << 9)
#define STS2_RSPTO (1 << 8)
#define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
#define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
STS2_DATBSYTO | STS2_CRCSTTO | \
STS2_AC12BSYTO | STS2_RSPBSYTO | \
STS2_AC12RSPTO | STS2_RSPTO)
/* CE_VERSION */
#define SOFT_RST_ON (1 << 31)
#define SOFT_RST_OFF (0 << 31)
#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
#define CLKDEV_MMC_INIT 400000 /* 100 - 400 KHz */
#define MMC_BUS_WIDTH_1 0
#define MMC_BUS_WIDTH_4 2
#define MMC_BUS_WIDTH_8 3
struct sh_mmcif_host {
struct mmc_data *data;
struct sh_mmcif_regs *regs;
unsigned int clk;
int bus_width;
u16 wait_int;
u16 sd_error;
u8 last_cmd;
};
static inline u32 sh_mmcif_read(unsigned long *reg)
{
return readl(reg);
}
static inline void sh_mmcif_write(u32 val, unsigned long *reg)
{
writel(val, reg);
}
static inline void sh_mmcif_bitset(u32 val, unsigned long *reg)
{
sh_mmcif_write(val | sh_mmcif_read(reg), reg);
}
static inline void sh_mmcif_bitclr(u32 val, unsigned long *reg)
{
sh_mmcif_write(~val & sh_mmcif_read(reg), reg);
}
#endif /* _SH_MMCIF_H_ */
|
1001-study-uboot
|
drivers/mmc/sh_mmcif.h
|
C
|
gpl3
| 6,664
|
/*
* Freescale i.MX28 SSP MMC driver
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
* Terry Lv
*
* Copyright 2007, Freescale Semiconductor, Inc
* Andy Fleming
*
* Based vaguely on the pxa mmc code:
* (C) Copyright 2003
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
struct mxsmmc_priv {
int id;
struct mx28_ssp_regs *regs;
uint32_t clkseq_bypass;
uint32_t *clkctrl_ssp;
uint32_t buswidth;
int (*mmc_is_wp)(int);
};
#define MXSMMC_MAX_TIMEOUT 10000
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
*/
static int
mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
struct mx28_ssp_regs *ssp_regs = priv->regs;
uint32_t reg;
int timeout;
uint32_t data_count;
uint32_t *data_ptr;
uint32_t ctrl0;
debug("MMC%d: CMD%d\n", mmc->block_dev.dev, cmd->cmdidx);
/* Check bus busy */
timeout = MXSMMC_MAX_TIMEOUT;
while (--timeout) {
udelay(1000);
reg = readl(&ssp_regs->hw_ssp_status);
if (!(reg &
(SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY |
SSP_STATUS_CMD_BUSY))) {
break;
}
}
if (!timeout) {
printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.dev);
return TIMEOUT;
}
/* See if card is present */
if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
return NO_CARD_ERR;
}
/* Start building CTRL0 contents */
ctrl0 = priv->buswidth;
/* Set up command */
if (!(cmd->resp_type & MMC_RSP_CRC))
ctrl0 |= SSP_CTRL0_IGNORE_CRC;
if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */
ctrl0 |= SSP_CTRL0_GET_RESP;
if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */
ctrl0 |= SSP_CTRL0_LONG_RESP;
/* Command index */
reg = readl(&ssp_regs->hw_ssp_cmd0);
reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC);
reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET;
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
reg |= SSP_CMD0_APPEND_8CYC;
writel(reg, &ssp_regs->hw_ssp_cmd0);
/* Command argument */
writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1);
/* Set up data */
if (data) {
/* READ or WRITE */
if (data->flags & MMC_DATA_READ) {
ctrl0 |= SSP_CTRL0_READ;
} else if (priv->mmc_is_wp(mmc->block_dev.dev)) {
printf("MMC%d: Can not write a locked card!\n",
mmc->block_dev.dev);
return UNUSABLE_ERR;
}
ctrl0 |= SSP_CTRL0_DATA_XFER;
reg = ((data->blocks - 1) <<
SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
((ffs(data->blocksize) - 1) <<
SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
writel(reg, &ssp_regs->hw_ssp_block_size);
reg = data->blocksize * data->blocks;
writel(reg, &ssp_regs->hw_ssp_xfer_size);
}
/* Kick off the command */
ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN;
writel(ctrl0, &ssp_regs->hw_ssp_ctrl0);
/* Wait for the command to complete */
timeout = MXSMMC_MAX_TIMEOUT;
while (--timeout) {
udelay(1000);
reg = readl(&ssp_regs->hw_ssp_status);
if (!(reg & SSP_STATUS_CMD_BUSY))
break;
}
if (!timeout) {
printf("MMC%d: Command %d busy\n",
mmc->block_dev.dev, cmd->cmdidx);
return TIMEOUT;
}
/* Check command timeout */
if (reg & SSP_STATUS_RESP_TIMEOUT) {
printf("MMC%d: Command %d timeout (status 0x%08x)\n",
mmc->block_dev.dev, cmd->cmdidx, reg);
return TIMEOUT;
}
/* Check command errors */
if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) {
printf("MMC%d: Command %d error (status 0x%08x)!\n",
mmc->block_dev.dev, cmd->cmdidx, reg);
return COMM_ERR;
}
/* Copy response to response buffer */
if (cmd->resp_type & MMC_RSP_136) {
cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0);
cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1);
cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2);
cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3);
} else
cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0);
/* Return if no data to process */
if (!data)
return 0;
/* Process the data */
data_count = data->blocksize * data->blocks;
timeout = MXSMMC_MAX_TIMEOUT;
if (data->flags & MMC_DATA_READ) {
data_ptr = (uint32_t *)data->dest;
while (data_count && --timeout) {
reg = readl(&ssp_regs->hw_ssp_status);
if (!(reg & SSP_STATUS_FIFO_EMPTY)) {
*data_ptr++ = readl(&ssp_regs->hw_ssp_data);
data_count -= 4;
timeout = MXSMMC_MAX_TIMEOUT;
} else
udelay(1000);
}
} else {
data_ptr = (uint32_t *)data->src;
timeout *= 100;
while (data_count && --timeout) {
reg = readl(&ssp_regs->hw_ssp_status);
if (!(reg & SSP_STATUS_FIFO_FULL)) {
writel(*data_ptr++, &ssp_regs->hw_ssp_data);
data_count -= 4;
timeout = MXSMMC_MAX_TIMEOUT;
} else
udelay(1000);
}
}
if (!timeout) {
printf("MMC%d: Data timeout with command %d (status 0x%08x)!\n",
mmc->block_dev.dev, cmd->cmdidx, reg);
return COMM_ERR;
}
/* Check data errors */
reg = readl(&ssp_regs->hw_ssp_status);
if (reg &
(SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR |
SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) {
printf("MMC%d: Data error with command %d (status 0x%08x)!\n",
mmc->block_dev.dev, cmd->cmdidx, reg);
return COMM_ERR;
}
return 0;
}
static void mxsmmc_set_ios(struct mmc *mmc)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
struct mx28_ssp_regs *ssp_regs = priv->regs;
/* Set the clock speed */
if (mmc->clock)
mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
switch (mmc->bus_width) {
case 1:
priv->buswidth = SSP_CTRL0_BUS_WIDTH_ONE_BIT;
break;
case 4:
priv->buswidth = SSP_CTRL0_BUS_WIDTH_FOUR_BIT;
break;
case 8:
priv->buswidth = SSP_CTRL0_BUS_WIDTH_EIGHT_BIT;
break;
}
/* Set the bus width */
clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
SSP_CTRL0_BUS_WIDTH_MASK, priv->buswidth);
debug("MMC%d: Set %d bits bus width\n",
mmc->block_dev.dev, mmc->bus_width);
}
static int mxsmmc_init(struct mmc *mmc)
{
struct mxsmmc_priv *priv = (struct mxsmmc_priv *)mmc->priv;
struct mx28_ssp_regs *ssp_regs = priv->regs;
/* Reset SSP */
mx28_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
/* 8 bits word length in MMC mode */
clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK,
SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
/* Set initial bit clock 400 KHz */
mx28_set_ssp_busclock(priv->id, 400);
/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
udelay(200);
writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_clr);
return 0;
}
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
{
struct mx28_clkctrl_regs *clkctrl_regs =
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mmc *mmc = NULL;
struct mxsmmc_priv *priv = NULL;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
priv = malloc(sizeof(struct mxsmmc_priv));
if (!priv) {
free(mmc);
return -ENOMEM;
}
priv->mmc_is_wp = wp;
priv->id = id;
switch (id) {
case 0:
priv->regs = (struct mx28_ssp_regs *)MXS_SSP0_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
break;
case 1:
priv->regs = (struct mx28_ssp_regs *)MXS_SSP1_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
break;
case 2:
priv->regs = (struct mx28_ssp_regs *)MXS_SSP2_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
break;
case 3:
priv->regs = (struct mx28_ssp_regs *)MXS_SSP3_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
break;
}
sprintf(mmc->name, "MXS MMC");
mmc->send_cmd = mxsmmc_send_cmd;
mmc->set_ios = mxsmmc_set_ios;
mmc->init = mxsmmc_init;
mmc->priv = priv;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
MMC_MODE_HS_52MHz | MMC_MODE_HS;
/*
* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
* CLOCK_DIVIDE has to be an even value from 2 to 254, and
* CLOCK_RATE could be any integer from 0 to 255.
*/
mmc->f_min = 400000;
mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
mmc->b_max = 0;
mmc_register(mmc);
return 0;
}
|
1001-study-uboot
|
drivers/mmc/mxsmmc.c
|
C
|
gpl3
| 9,547
|
/*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
* Sukumar Ghorai <s-ghorai@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
#include <twl4030.h>
#include <twl6030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS 1000
static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
unsigned int siz);
static struct mmc hsmmc_dev[2];
#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
u32 value = 0;
struct omap4_sys_ctrl_regs *const ctrl =
(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
value = readl(&ctrl->control_pbiaslite);
value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
writel(value, &ctrl->control_pbiaslite);
/* set VMMC to 3V */
twl6030_power_mmc_init();
value = readl(&ctrl->control_pbiaslite);
value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
writel(value, &ctrl->control_pbiaslite);
}
#endif
unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_TWL4030_POWER)
twl4030_power_mmc_init();
#endif
#if defined(CONFIG_OMAP34XX)
t2_t *t2_base = (t2_t *)T2_BASE;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
&t2_base->pbias_lite);
writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
&t2_base->devconf0);
writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
&t2_base->devconf1);
writel(readl(&prcm_base->fclken1_core) |
EN_MMC1 | EN_MMC2 | EN_MMC3,
&prcm_base->fclken1_core);
writel(readl(&prcm_base->iclken1_core) |
EN_MMC1 | EN_MMC2 | EN_MMC3,
&prcm_base->iclken1_core);
#endif
#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
/* PBIAS config needed for MMC1 only */
if (mmc->block_dev.dev == 0)
omap4_vmmc_pbias_config(mmc);
#endif
return 0;
}
void mmc_init_stream(struct hsmmc *mmc_base)
{
ulong start;
writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
writel(MMC_CMD0, &mmc_base->cmd);
start = get_timer(0);
while (!(readl(&mmc_base->stat) & CC_MASK)) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for cc!\n", __func__);
return;
}
}
writel(CC_MASK, &mmc_base->stat)
;
writel(MMC_CMD0, &mmc_base->cmd)
;
start = get_timer(0);
while (!(readl(&mmc_base->stat) & CC_MASK)) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for cc2!\n", __func__);
return;
}
}
writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}
static int mmc_init_setup(struct mmc *mmc)
{
struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
unsigned int reg_val;
unsigned int dsor;
ulong start;
mmc_board_init(mmc);
writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
&mmc_base->sysconfig);
start = get_timer(0);
while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for cc2!\n", __func__);
return TIMEOUT;
}
}
writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for softresetall!\n",
__func__);
return TIMEOUT;
}
}
writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
&mmc_base->capa);
reg_val = readl(&mmc_base->con) & RESERVED_MASK;
writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
dsor = 240;
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for ics!\n", __func__);
return TIMEOUT;
}
}
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
&mmc_base->ie);
mmc_init_stream(mmc_base);
return 0;
}
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
unsigned int flags, mmc_stat;
ulong start;
start = get_timer(0);
while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for cmddis!\n", __func__);
return TIMEOUT;
}
}
writel(0xFFFFFFFF, &mmc_base->stat);
start = get_timer(0);
while (readl(&mmc_base->stat)) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for stat!\n", __func__);
return TIMEOUT;
}
}
/*
* CMDREG
* CMDIDX[13:8] : Command index
* DATAPRNT[5] : Data Present Select
* ENCMDIDX[4] : Command Index Check Enable
* ENCMDCRC[3] : Command CRC Check Enable
* RSPTYP[1:0]
* 00 = No Response
* 01 = Length 136
* 10 = Length 48
* 11 = Length 48 Check busy after response
*/
/* Delay added before checking the status of frq change
* retry not supported by mmc.c(core file)
*/
if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
udelay(50000); /* wait 50 ms */
if (!(cmd->resp_type & MMC_RSP_PRESENT))
flags = 0;
else if (cmd->resp_type & MMC_RSP_136)
flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
else if (cmd->resp_type & MMC_RSP_BUSY)
flags = RSP_TYPE_LGHT48B;
else
flags = RSP_TYPE_LGHT48;
/* enable default flags */
flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);
if (cmd->resp_type & MMC_RSP_CRC)
flags |= CCCE_CHECK;
if (cmd->resp_type & MMC_RSP_OPCODE)
flags |= CICE_CHECK;
if (data) {
if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
flags |= (MSBS_MULTIBLK | BCE_ENABLE);
data->blocksize = 512;
writel(data->blocksize | (data->blocks << 16),
&mmc_base->blk);
} else
writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
if (data->flags & MMC_DATA_READ)
flags |= (DP_DATA | DDIR_READ);
else
flags |= (DP_DATA | DDIR_WRITE);
}
writel(cmd->cmdarg, &mmc_base->arg);
writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s : timeout: No status update\n", __func__);
return TIMEOUT;
}
} while (!mmc_stat);
if ((mmc_stat & IE_CTO) != 0)
return TIMEOUT;
else if ((mmc_stat & ERRI_MASK) != 0)
return -1;
if (mmc_stat & CC_MASK) {
writel(CC_MASK, &mmc_base->stat);
if (cmd->resp_type & MMC_RSP_PRESENT) {
if (cmd->resp_type & MMC_RSP_136) {
/* response type 2 */
cmd->response[3] = readl(&mmc_base->rsp10);
cmd->response[2] = readl(&mmc_base->rsp32);
cmd->response[1] = readl(&mmc_base->rsp54);
cmd->response[0] = readl(&mmc_base->rsp76);
} else
/* response types 1, 1b, 3, 4, 5, 6 */
cmd->response[0] = readl(&mmc_base->rsp10);
}
}
if (data && (data->flags & MMC_DATA_READ)) {
mmc_read_data(mmc_base, data->dest,
data->blocksize * data->blocks);
} else if (data && (data->flags & MMC_DATA_WRITE)) {
mmc_write_data(mmc_base, data->src,
data->blocksize * data->blocks);
}
return 0;
}
static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
unsigned int *output_buf = (unsigned int *)buf;
unsigned int mmc_stat;
unsigned int count;
/*
* Start Polled Read
*/
count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
count /= 4;
while (size) {
ulong start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for status!\n",
__func__);
return TIMEOUT;
}
} while (mmc_stat == 0);
if ((mmc_stat & ERRI_MASK) != 0)
return 1;
if (mmc_stat & BRR_MASK) {
unsigned int k;
writel(readl(&mmc_base->stat) | BRR_MASK,
&mmc_base->stat);
for (k = 0; k < count; k++) {
*output_buf = readl(&mmc_base->data);
output_buf++;
}
size -= (count*4);
}
if (mmc_stat & BWR_MASK)
writel(readl(&mmc_base->stat) | BWR_MASK,
&mmc_base->stat);
if (mmc_stat & TC_MASK) {
writel(readl(&mmc_base->stat) | TC_MASK,
&mmc_base->stat);
break;
}
}
return 0;
}
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
unsigned int size)
{
unsigned int *input_buf = (unsigned int *)buf;
unsigned int mmc_stat;
unsigned int count;
/*
* Start Polled Read
*/
count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
count /= 4;
while (size) {
ulong start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for status!\n",
__func__);
return TIMEOUT;
}
} while (mmc_stat == 0);
if ((mmc_stat & ERRI_MASK) != 0)
return 1;
if (mmc_stat & BWR_MASK) {
unsigned int k;
writel(readl(&mmc_base->stat) | BWR_MASK,
&mmc_base->stat);
for (k = 0; k < count; k++) {
writel(*input_buf, &mmc_base->data);
input_buf++;
}
size -= (count*4);
}
if (mmc_stat & BRR_MASK)
writel(readl(&mmc_base->stat) | BRR_MASK,
&mmc_base->stat);
if (mmc_stat & TC_MASK) {
writel(readl(&mmc_base->stat) | TC_MASK,
&mmc_base->stat);
break;
}
}
return 0;
}
static void mmc_set_ios(struct mmc *mmc)
{
struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
unsigned int dsor = 0;
ulong start;
/* configue bus width */
switch (mmc->bus_width) {
case 8:
writel(readl(&mmc_base->con) | DTW_8_BITMODE,
&mmc_base->con);
break;
case 4:
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
&mmc_base->con);
writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
&mmc_base->hctl);
break;
case 1:
default:
writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
&mmc_base->con);
writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
&mmc_base->hctl);
break;
}
/* configure clock with 96Mhz system clock.
*/
if (mmc->clock != 0) {
dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
dsor++;
}
mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
if (get_timer(0) - start > MAX_RETRY_MS) {
printf("%s: timedout waiting for ics!\n", __func__);
return;
}
}
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}
int omap_mmc_init(int dev_index)
{
struct mmc *mmc;
mmc = &hsmmc_dev[dev_index];
sprintf(mmc->name, "OMAP SD/MMC");
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
switch (dev_index) {
case 0:
mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
#ifdef OMAP_HSMMC2_BASE
case 1:
mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
break;
#endif
#ifdef OMAP_HSMMC3_BASE
case 2:
mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
break;
#endif
default:
mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
MMC_MODE_HC;
mmc->f_min = 400000;
mmc->f_max = 52000000;
mmc->b_max = 0;
#if defined(CONFIG_OMAP34XX)
/*
* Silicon revs 2.1 and older do not support multiblock transfers.
*/
if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
mmc->b_max = 1;
#endif
mmc_register(mmc);
return 0;
}
|
1001-study-uboot
|
drivers/mmc/omap_hsmmc.c
|
C
|
gpl3
| 13,096
|
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Portions Copyright (C) 2011 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __TEGRA2_MMC_H_
#define __TEGRA2_MMC_H_
#define TEGRA2_SDMMC1_BASE 0xC8000000
#define TEGRA2_SDMMC2_BASE 0xC8000200
#define TEGRA2_SDMMC3_BASE 0xC8000400
#define TEGRA2_SDMMC4_BASE 0xC8000600
#ifndef __ASSEMBLY__
struct tegra2_mmc {
unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
unsigned int argument; /* _ARGUMENT_0 */
unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
unsigned int prnsts; /* _PRESENT_STATE_0 */
unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
unsigned char swrst; /* _SW_RESET_ 31:24 */
unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
unsigned char res1[2]; /* _RESERVED 31:16 */
unsigned int capareg; /* _CAPABILITIES_0 */
unsigned char res2[4]; /* RESERVED, offset 44h-47h */
unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
unsigned short setacmd12err; /* offset 50h */
unsigned short setinterr; /* offset 52h */
unsigned char admaerr; /* offset 54h */
unsigned char res4[3]; /* RESERVED, offset 55h-57h */
unsigned long admaaddr; /* offset 58h-5Fh */
unsigned char res5[0x9c]; /* RESERVED, offset 60h-FBh */
unsigned short slotintstatus; /* offset FCh */
unsigned short hcver; /* HOST Version */
unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
};
#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
struct mmc_host {
struct tegra2_mmc *reg;
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
unsigned int base; /* Base address, SDMMC1/2/3/4 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
int pwr_gpio; /* Power GPIO */
int cd_gpio; /* Change Detect GPIO */
};
int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
#endif /* __ASSEMBLY__ */
#endif /* __TEGRA2_MMC_H_ */
|
1001-study-uboot
|
drivers/mmc/tegra2_mmc.h
|
C
|
gpl3
| 5,694
|
/*
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based vaguely on the pxa mmc code:
* (C) Copyright 2003
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
struct fsl_esdhc {
uint dsaddr;
uint blkattr;
uint cmdarg;
uint xfertyp;
uint cmdrsp0;
uint cmdrsp1;
uint cmdrsp2;
uint cmdrsp3;
uint datport;
uint prsstat;
uint proctl;
uint sysctl;
uint irqstat;
uint irqstaten;
uint irqsigen;
uint autoc12err;
uint hostcapblt;
uint wml;
char reserved1[8];
uint fevt;
char reserved2[168];
uint hostver;
char reserved3[780];
uint scr;
};
/* Return the XFERTYP flags for a given command and data packet */
uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
uint xfertyp = 0;
if (data) {
xfertyp |= XFERTYP_DPSEL;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
xfertyp |= XFERTYP_DMAEN;
#endif
if (data->blocks > 1) {
xfertyp |= XFERTYP_MSBSEL;
xfertyp |= XFERTYP_BCEN;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
xfertyp |= XFERTYP_AC12EN;
#endif
}
if (data->flags & MMC_DATA_READ)
xfertyp |= XFERTYP_DTDSEL;
}
if (cmd->resp_type & MMC_RSP_CRC)
xfertyp |= XFERTYP_CCCEN;
if (cmd->resp_type & MMC_RSP_OPCODE)
xfertyp |= XFERTYP_CICEN;
if (cmd->resp_type & MMC_RSP_136)
xfertyp |= XFERTYP_RSPTYP_136;
else if (cmd->resp_type & MMC_RSP_BUSY)
xfertyp |= XFERTYP_RSPTYP_48_BUSY;
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
#ifdef CONFIG_MX53
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
/*
* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
*/
static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
struct fsl_esdhc *regs = mmc->priv;
uint blocks;
char *buffer;
uint databuf;
uint size;
uint irqstat;
uint timeout;
if (data->flags & MMC_DATA_READ) {
blocks = data->blocks;
buffer = data->dest;
while (blocks) {
timeout = PIO_TIMEOUT;
size = data->blocksize;
irqstat = esdhc_read32(®s->irqstat);
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)
&& --timeout);
if (timeout <= 0) {
printf("\nData Read Failed in PIO Mode.");
return;
}
while (size && (!(irqstat & IRQSTAT_TC))) {
udelay(100); /* Wait before last byte transfer complete */
irqstat = esdhc_read32(®s->irqstat);
databuf = in_le32(®s->datport);
*((uint *)buffer) = databuf;
buffer += 4;
size -= 4;
}
blocks--;
}
} else {
blocks = data->blocks;
buffer = (char *)data->src;
while (blocks) {
timeout = PIO_TIMEOUT;
size = data->blocksize;
irqstat = esdhc_read32(®s->irqstat);
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)
&& --timeout);
if (timeout <= 0) {
printf("\nData Write Failed in PIO Mode.");
return;
}
while (size && (!(irqstat & IRQSTAT_TC))) {
udelay(100); /* Wait before last byte transfer complete */
databuf = *((uint *)buffer);
buffer += 4;
size -= 4;
irqstat = esdhc_read32(®s->irqstat);
out_le32(®s->datport, databuf);
}
blocks--;
}
}
}
#endif
static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
int timeout;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
uint wml_value;
wml_value = data->blocksize/4;
if (data->flags & MMC_DATA_READ) {
if (wml_value > WML_RD_WML_MAX)
wml_value = WML_RD_WML_MAX_VAL;
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
esdhc_write32(®s->dsaddr, (u32)data->dest);
} else {
if (wml_value > WML_WR_WML_MAX)
wml_value = WML_WR_WML_MAX_VAL;
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
return TIMEOUT;
}
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
esdhc_write32(®s->dsaddr, (u32)data->src);
}
#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
if (!(data->flags & MMC_DATA_READ)) {
if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
printf("\nThe SD card is locked. "
"Can not write to a locked card.\n\n");
return TIMEOUT;
}
esdhc_write32(®s->dsaddr, (u32)data->src);
} else
esdhc_write32(®s->dsaddr, (u32)data->dest);
#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
/* Calculate the timeout period for data transactions */
/*
* 1)Timeout period = (2^(timeout+13)) SD Clock cycles
* 2)Timeout period should be minimum 0.250sec as per SD Card spec
* So, Number of SD Clock cycles for 0.25sec should be minimum
* (SD Clock/sec * 0.25 sec) SD Clock cycles
* = (mmc->tran_speed * 1/4) SD Clock cycles
* As 1) >= 2)
* => (2^(timeout+13)) >= mmc->tran_speed * 1/4
* Taking log2 both the sides
* => timeout + 13 >= log2(mmc->tran_speed/4)
* Rounding up to next power of 2
* => timeout + 13 = log2(mmc->tran_speed/4) + 1
* => timeout + 13 = fls(mmc->tran_speed/4)
*/
timeout = fls(mmc->tran_speed/4);
timeout -= 13;
if (timeout > 14)
timeout = 14;
if (timeout < 0)
timeout = 0;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
if ((timeout == 4) || (timeout == 8) || (timeout == 12))
timeout++;
#endif
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
return 0;
}
/*
* Sends a command out on the bus. Takes the mmc pointer,
* a command pointer, and an optional data pointer.
*/
static int
esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
uint xfertyp;
uint irqstat;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
return 0;
#endif
esdhc_write32(®s->irqstat, -1);
sync();
/* Wait for the bus to be idle */
while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
(esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
;
while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
;
/* Wait at least 8 SD clock cycles before the next command */
/*
* Note: This is way more than 8 cycles, but 1ms seems to
* resolve timing issues with some cards
*/
udelay(1000);
/* Set up for a data transfer if we have one */
if (data) {
int err;
err = esdhc_setup_data(mmc, data);
if(err)
return err;
}
/* Figure out the transfer arguments */
xfertyp = esdhc_xfertyp(cmd, data);
/* Send the command */
esdhc_write32(®s->cmdarg, cmd->cmdarg);
esdhc_write32(®s->xfertyp, xfertyp);
/* Wait for the command to complete */
while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC))
;
irqstat = esdhc_read32(®s->irqstat);
esdhc_write32(®s->irqstat, irqstat);
if (irqstat & CMD_ERR)
return COMM_ERR;
if (irqstat & IRQSTAT_CTOE)
return TIMEOUT;
/* Copy the response to the response buffer */
if (cmd->resp_type & MMC_RSP_136) {
u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
cmdrsp3 = esdhc_read32(®s->cmdrsp3);
cmdrsp2 = esdhc_read32(®s->cmdrsp2);
cmdrsp1 = esdhc_read32(®s->cmdrsp1);
cmdrsp0 = esdhc_read32(®s->cmdrsp0);
cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
cmd->response[3] = (cmdrsp0 << 8);
} else
cmd->response[0] = esdhc_read32(®s->cmdrsp0);
/* Wait until all of the blocks are transferred */
if (data) {
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
esdhc_pio_read_write(mmc, data);
#else
do {
irqstat = esdhc_read32(®s->irqstat);
if (irqstat & IRQSTAT_DTOE)
return TIMEOUT;
if (irqstat & DATA_ERR)
return COMM_ERR;
} while (!(irqstat & IRQSTAT_TC) &&
(esdhc_read32(®s->prsstat) & PRSSTAT_DLA));
#endif
}
esdhc_write32(®s->irqstat, -1);
return 0;
}
void set_sysctl(struct mmc *mmc, uint clock)
{
int sdhc_clk = gd->sdhc_clk;
int div, pre_div;
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
uint clk;
if (clock < mmc->f_min)
clock = mmc->f_min;
if (sdhc_clk / 16 > clock) {
for (pre_div = 2; pre_div < 256; pre_div *= 2)
if ((sdhc_clk / pre_div) <= (clock * 16))
break;
} else
pre_div = 2;
for (div = 1; div <= 16; div++)
if ((sdhc_clk / (div * pre_div)) <= clock)
break;
pre_div >>= 1;
div -= 1;
clk = (pre_div << 8) | (div << 4);
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
udelay(10000);
clk = SYSCTL_PEREN | SYSCTL_CKEN;
esdhc_setbits32(®s->sysctl, clk);
}
static void esdhc_set_ios(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
/* Set the clock speed */
set_sysctl(mmc, mmc->clock);
/* Set the bus width */
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
if (mmc->bus_width == 4)
esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
else if (mmc->bus_width == 8)
esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
}
static int esdhc_init(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
int timeout = 1000;
int ret = 0;
u8 card_absent;
/* Reset the entire host controller */
esdhc_write32(®s->sysctl, SYSCTL_RSTA);
/* Wait until the controller is available */
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000);
/* Enable cache snooping */
if (cfg && !cfg->no_snoop)
esdhc_write32(®s->scr, 0x00000040);
esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
/* Set the initial clock speed */
mmc_set_clock(mmc, 400000);
/* Disable the BRR and BWR bits in IRQSTAT */
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
/* Put the PROCTL reg back to the default */
esdhc_write32(®s->proctl, PROCTL_INIT);
/* Set timout to the maximum value */
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
/* Check if there is a callback for detecting the card */
if (board_mmc_getcd(&card_absent, mmc)) {
timeout = 1000;
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) &&
--timeout)
udelay(1000);
if (timeout <= 0)
ret = NO_CARD_ERR;
} else {
if (card_absent)
ret = NO_CARD_ERR;
}
return ret;
}
static void esdhc_reset(struct fsl_esdhc *regs)
{
unsigned long timeout = 100; /* wait max 100 ms */
/* reset the controller */
esdhc_write32(®s->sysctl, SYSCTL_RSTA);
/* hardware clears the bit when it is done */
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout)
udelay(1000);
if (!timeout)
printf("MMC/SD: Reset never completed.\n");
}
int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
struct fsl_esdhc *regs;
struct mmc *mmc;
u32 caps, voltage_caps;
if (!cfg)
return -1;
mmc = malloc(sizeof(struct mmc));
sprintf(mmc->name, "FSL_ESDHC");
regs = (struct fsl_esdhc *)cfg->esdhc_base;
/* First reset the eSDHC controller */
esdhc_reset(regs);
mmc->priv = cfg;
mmc->send_cmd = esdhc_send_cmd;
mmc->set_ios = esdhc_set_ios;
mmc->init = esdhc_init;
voltage_caps = 0;
caps = regs->hostcapblt;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
#endif
if (caps & ESDHC_HOSTCAPBLT_VS18)
voltage_caps |= MMC_VDD_165_195;
if (caps & ESDHC_HOSTCAPBLT_VS30)
voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
if (caps & ESDHC_HOSTCAPBLT_VS33)
voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
#ifdef CONFIG_SYS_SD_VOLTAGE
mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
#else
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
if ((mmc->voltages & voltage_caps) == 0) {
printf("voltage not supported by controller\n");
return -1;
}
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
if (caps & ESDHC_HOSTCAPBLT_HSS)
mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
mmc->f_min = 400000;
mmc->f_max = MIN(gd->sdhc_clk, 52000000);
mmc->b_max = 0;
mmc_register(mmc);
return 0;
}
int fsl_esdhc_mmc_init(bd_t *bis)
{
struct fsl_esdhc_cfg *cfg;
cfg = malloc(sizeof(struct fsl_esdhc_cfg));
memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
return fsl_esdhc_initialize(bis, cfg);
}
#ifdef CONFIG_OF_LIBFDT
void fdt_fixup_esdhc(void *blob, bd_t *bd)
{
const char *compat = "fsl,esdhc";
#ifdef CONFIG_FSL_ESDHC_PIN_MUX
if (!hwconfig("esdhc")) {
do_fixup_by_compat(blob, compat, "status", "disabled",
8 + 1, 1);
return;
}
#endif
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
gd->sdhc_clk, 1);
do_fixup_by_compat(blob, compat, "status", "okay",
4 + 1, 1);
}
#endif
|
1001-study-uboot
|
drivers/mmc/fsl_esdhc.c
|
C
|
gpl3
| 14,061
|
/*
* This is a driver for the SDHC controller found in Freescale MX2/MX3
* SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
* Unlike the hardware found on MX1, this hardware just works and does
* not need all the quirks found in imxmmc.c, hence the seperate driver.
*
* Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>
* Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
* Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
*
* derived from pxamci.c by Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <config.h>
#include <common.h>
#include <command.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <asm/errno.h>
#include <asm/io.h>
#ifdef CONFIG_MX27
#include <asm/arch/clock.h>
#endif
#define DRIVER_NAME "mxc-mmc"
struct mxcmci_regs {
u32 str_stp_clk;
u32 status;
u32 clk_rate;
u32 cmd_dat_cont;
u32 res_to;
u32 read_to;
u32 blk_len;
u32 nob;
u32 rev_no;
u32 int_cntr;
u32 cmd;
u32 arg;
u32 pad;
u32 res_fifo;
u32 buffer_access;
};
#define STR_STP_CLK_RESET (1 << 3)
#define STR_STP_CLK_START_CLK (1 << 1)
#define STR_STP_CLK_STOP_CLK (1 << 0)
#define STATUS_CARD_INSERTION (1 << 31)
#define STATUS_CARD_REMOVAL (1 << 30)
#define STATUS_YBUF_EMPTY (1 << 29)
#define STATUS_XBUF_EMPTY (1 << 28)
#define STATUS_YBUF_FULL (1 << 27)
#define STATUS_XBUF_FULL (1 << 26)
#define STATUS_BUF_UND_RUN (1 << 25)
#define STATUS_BUF_OVFL (1 << 24)
#define STATUS_SDIO_INT_ACTIVE (1 << 14)
#define STATUS_END_CMD_RESP (1 << 13)
#define STATUS_WRITE_OP_DONE (1 << 12)
#define STATUS_DATA_TRANS_DONE (1 << 11)
#define STATUS_READ_OP_DONE (1 << 11)
#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
#define STATUS_CARD_BUS_CLK_RUN (1 << 8)
#define STATUS_BUF_READ_RDY (1 << 7)
#define STATUS_BUF_WRITE_RDY (1 << 6)
#define STATUS_RESP_CRC_ERR (1 << 5)
#define STATUS_CRC_READ_ERR (1 << 3)
#define STATUS_CRC_WRITE_ERR (1 << 2)
#define STATUS_TIME_OUT_RESP (1 << 1)
#define STATUS_TIME_OUT_READ (1 << 0)
#define STATUS_ERR_MASK 0x2f
#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
#define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
#define CMD_DAT_CONT_START_READWAIT (1 << 10)
#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
#define CMD_DAT_CONT_INIT (1 << 7)
#define CMD_DAT_CONT_WRITE (1 << 4)
#define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
#define INT_SDIO_INT_WKP_EN (1 << 18)
#define INT_CARD_INSERTION_WKP_EN (1 << 17)
#define INT_CARD_REMOVAL_WKP_EN (1 << 16)
#define INT_CARD_INSERTION_EN (1 << 15)
#define INT_CARD_REMOVAL_EN (1 << 14)
#define INT_SDIO_IRQ_EN (1 << 13)
#define INT_DAT0_EN (1 << 12)
#define INT_BUF_READ_EN (1 << 4)
#define INT_BUF_WRITE_EN (1 << 3)
#define INT_END_CMD_RES_EN (1 << 2)
#define INT_WRITE_OP_DONE_EN (1 << 1)
#define INT_READ_OP_EN (1 << 0)
struct mxcmci_host {
struct mmc *mmc;
struct mxcmci_regs *base;
int irq;
int detect_irq;
int dma;
int do_dma;
unsigned int power_mode;
struct mmc_cmd *cmd;
struct mmc_data *data;
unsigned int dma_nents;
unsigned int datasize;
unsigned int dma_dir;
u16 rev_no;
unsigned int cmdat;
int clock;
};
static struct mxcmci_host mxcmci_host;
static struct mxcmci_host *host = &mxcmci_host;
static inline int mxcmci_use_dma(struct mxcmci_host *host)
{
return host->do_dma;
}
static void mxcmci_softreset(struct mxcmci_host *host)
{
int i;
/* reset sequence */
writel(STR_STP_CLK_RESET, &host->base->str_stp_clk);
writel(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
&host->base->str_stp_clk);
for (i = 0; i < 8; i++)
writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
writel(0xff, &host->base->res_to);
}
static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
{
unsigned int nob = data->blocks;
unsigned int blksz = data->blocksize;
unsigned int datasize = nob * blksz;
host->data = data;
writel(nob, &host->base->nob);
writel(blksz, &host->base->blk_len);
host->datasize = datasize;
}
static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd,
unsigned int cmdat)
{
if (host->cmd != NULL)
printf("mxcmci: error!\n");
host->cmd = cmd;
switch (cmd->resp_type) {
case MMC_RSP_R1: /* short CRC, OPCODE */
case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
break;
case MMC_RSP_R2: /* long 136 bit + CRC */
cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
break;
case MMC_RSP_R3: /* short */
cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
break;
case MMC_RSP_NONE:
break;
default:
printf("mxcmci: unhandled response type 0x%x\n",
cmd->resp_type);
return -EINVAL;
}
writel(cmd->cmdidx, &host->base->cmd);
writel(cmd->cmdarg, &host->base->arg);
writel(cmdat, &host->base->cmd_dat_cont);
return 0;
}
static void mxcmci_finish_request(struct mxcmci_host *host,
struct mmc_cmd *cmd, struct mmc_data *data)
{
host->cmd = NULL;
host->data = NULL;
}
static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
{
int data_error = 0;
if (stat & STATUS_ERR_MASK) {
printf("request failed. status: 0x%08x\n",
stat);
if (stat & STATUS_CRC_READ_ERR) {
data_error = -EILSEQ;
} else if (stat & STATUS_CRC_WRITE_ERR) {
u32 err_code = (stat >> 9) & 0x3;
if (err_code == 2) /* No CRC response */
data_error = TIMEOUT;
else
data_error = -EILSEQ;
} else if (stat & STATUS_TIME_OUT_READ) {
data_error = TIMEOUT;
} else {
data_error = -EIO;
}
}
host->data = NULL;
return data_error;
}
static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
{
struct mmc_cmd *cmd = host->cmd;
int i;
u32 a, b, c;
u32 *resp = (u32 *)cmd->response;
if (!cmd)
return 0;
if (stat & STATUS_TIME_OUT_RESP) {
printf("CMD TIMEOUT\n");
return TIMEOUT;
} else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
printf("cmd crc error\n");
return -EILSEQ;
}
if (cmd->resp_type & MMC_RSP_PRESENT) {
if (cmd->resp_type & MMC_RSP_136) {
for (i = 0; i < 4; i++) {
a = readl(&host->base->res_fifo) & 0xFFFF;
b = readl(&host->base->res_fifo) & 0xFFFF;
resp[i] = a << 16 | b;
}
} else {
a = readl(&host->base->res_fifo) & 0xFFFF;
b = readl(&host->base->res_fifo) & 0xFFFF;
c = readl(&host->base->res_fifo) & 0xFFFF;
resp[0] = a << 24 | b << 8 | c >> 8;
}
}
return 0;
}
static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
{
u32 stat;
unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;
do {
stat = readl(&host->base->status);
if (stat & STATUS_ERR_MASK)
return stat;
if (timeout < get_ticks())
return STATUS_TIME_OUT_READ;
if (stat & mask)
return 0;
} while (1);
}
static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
{
unsigned int stat;
u32 *buf = _buf;
while (bytes > 3) {
stat = mxcmci_poll_status(host,
STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
if (stat)
return stat;
*buf++ = readl(&host->base->buffer_access);
bytes -= 4;
}
if (bytes) {
u8 *b = (u8 *)buf;
u32 tmp;
stat = mxcmci_poll_status(host,
STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
if (stat)
return stat;
tmp = readl(&host->base->buffer_access);
memcpy(b, &tmp, bytes);
}
return 0;
}
static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes)
{
unsigned int stat;
const u32 *buf = _buf;
while (bytes > 3) {
stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
if (stat)
return stat;
writel(*buf++, &host->base->buffer_access);
bytes -= 4;
}
if (bytes) {
const u8 *b = (u8 *)buf;
u32 tmp;
stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
if (stat)
return stat;
memcpy(&tmp, b, bytes);
writel(tmp, &host->base->buffer_access);
}
stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
if (stat)
return stat;
return 0;
}
static int mxcmci_transfer_data(struct mxcmci_host *host)
{
struct mmc_data *data = host->data;
int stat;
unsigned long length;
length = data->blocks * data->blocksize;
host->datasize = 0;
if (data->flags & MMC_DATA_READ) {
stat = mxcmci_pull(host, data->dest, length);
if (stat)
return stat;
host->datasize += length;
} else {
stat = mxcmci_push(host, (const void *)(data->src), length);
if (stat)
return stat;
host->datasize += length;
stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
if (stat)
return stat;
}
return 0;
}
static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
{
int datastat;
int ret;
ret = mxcmci_read_response(host, stat);
if (ret) {
mxcmci_finish_request(host, host->cmd, host->data);
return ret;
}
if (!host->data) {
mxcmci_finish_request(host, host->cmd, host->data);
return 0;
}
datastat = mxcmci_transfer_data(host);
ret = mxcmci_finish_data(host, datastat);
mxcmci_finish_request(host, host->cmd, host->data);
return ret;
}
static int mxcmci_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct mxcmci_host *host = mmc->priv;
unsigned int cmdat = host->cmdat;
u32 stat;
int ret;
host->cmdat &= ~CMD_DAT_CONT_INIT;
if (data) {
mxcmci_setup_data(host, data);
cmdat |= CMD_DAT_CONT_DATA_ENABLE;
if (data->flags & MMC_DATA_WRITE)
cmdat |= CMD_DAT_CONT_WRITE;
}
if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
mxcmci_finish_request(host, cmd, data);
return ret;
}
do {
stat = readl(&host->base->status);
writel(stat, &host->base->status);
} while (!(stat & STATUS_END_CMD_RESP));
return mxcmci_cmd_done(host, stat);
}
static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
{
unsigned int divider;
int prescaler = 0;
unsigned long clk_in = imx_get_perclk2();
while (prescaler <= 0x800) {
for (divider = 1; divider <= 0xF; divider++) {
int x;
x = (clk_in / (divider + 1));
if (prescaler)
x /= (prescaler * 2);
if (x <= clk_ios)
break;
}
if (divider < 0x10)
break;
if (prescaler == 0)
prescaler = 1;
else
prescaler <<= 1;
}
writel((prescaler << 4) | divider, &host->base->clk_rate);
}
static void mxcmci_set_ios(struct mmc *mmc)
{
struct mxcmci_host *host = mmc->priv;
if (mmc->bus_width == 4)
host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
else
host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
if (mmc->clock) {
mxcmci_set_clk_rate(host, mmc->clock);
writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
} else {
writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk);
}
host->clock = mmc->clock;
}
static int mxcmci_init(struct mmc *mmc)
{
struct mxcmci_host *host = mmc->priv;
mxcmci_softreset(host);
host->rev_no = readl(&host->base->rev_no);
if (host->rev_no != 0x400) {
printf("wrong rev.no. 0x%08x. aborting.\n",
host->rev_no);
return -ENODEV;
}
/* recommended in data sheet */
writel(0x2db4, &host->base->read_to);
writel(0, &host->base->int_cntr);
return 0;
}
static int mxcmci_initialize(bd_t *bis)
{
struct mmc *mmc = NULL;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
sprintf(mmc->name, "MXC MCI");
mmc->send_cmd = mxcmci_request;
mmc->set_ios = mxcmci_set_ios;
mmc->init = mxcmci_init;
mmc->host_caps = MMC_MODE_4BIT;
host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
mmc->priv = host;
host->mmc = mmc;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->f_min = imx_get_perclk2() >> 7;
mmc->f_max = imx_get_perclk2() >> 1;
mmc->b_max = 0;
mmc_register(mmc);
return 0;
}
int mxc_mmc_init(bd_t *bis)
{
return mxcmci_initialize(bis);
}
|
1001-study-uboot
|
drivers/mmc/mxcmmc.c
|
C
|
gpl3
| 11,867
|
#include <common.h>
#include <malloc.h>
#include <sdhci.h>
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
static struct sdhci_ops mv_ops;
#if defined(CONFIG_SHEEVA_88SV331xV5)
#define SD_CE_ATA_2 0xEA
#define MMC_CARD 0x1000
#define MMC_WIDTH 0x0100
static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
struct mmc *mmc = host->mmc;
u32 ata = (u32)host->ioaddr + SD_CE_ATA_2;
if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
if (mmc->bus_width == 8)
writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
else
writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
}
writeb(val, host->ioaddr + reg);
}
#else
#define mv_sdhci_writeb NULL
#endif /* CONFIG_SHEEVA_88SV331xV5 */
#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
static char *MVSDH_NAME = "mv_sdh";
int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
{
struct sdhci_host *host = NULL;
host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
if (!host) {
printf("sdh_host malloc fail!\n");
return 1;
}
host->name = MVSDH_NAME;
host->ioaddr = (void *)regbase;
host->quirks = quirks;
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
memset(&mv_ops, 0, sizeof(struct sdhci_ops));
if (mv_sdhci_writeb != NULL)
mv_ops.write_b = mv_sdhci_writeb;
host->ops = &mv_ops;
#endif
if (quirks & SDHCI_QUIRK_REG32_RW)
host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
else
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
add_sdhci(host, max_clk, min_clk);
return 0;
}
|
1001-study-uboot
|
drivers/mmc/mv_sdhci.c
|
C
|
gpl3
| 1,492
|
/*
* Driver for Blackfin on-chip SDH controller
*
* Copyright (c) 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <malloc.h>
#include <part.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/byteorder.h>
#include <asm/blackfin.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/sdh.h>
#include <asm/mach-common/bits/dma.h>
#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__)
# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
# define PORTMUX_PINS \
{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
#elif defined(__ADSPBF54x__)
# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
# define PORTMUX_PINS \
{ P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
#else
# error no support for this proc yet
#endif
static int
sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
unsigned int status, timeout;
int cmd = mmc_cmd->cmdidx;
int flags = mmc_cmd->resp_type;
int arg = mmc_cmd->cmdarg;
int ret;
u16 sdh_cmd;
sdh_cmd = cmd | CMD_E;
if (flags & MMC_RSP_PRESENT)
sdh_cmd |= CMD_RSP;
if (flags & MMC_RSP_136)
sdh_cmd |= CMD_L_RSP;
bfin_write_SDH_ARGUMENT(arg);
bfin_write_SDH_COMMAND(sdh_cmd);
/* wait for a while */
timeout = 0;
do {
if (++timeout > 1000000) {
status = CMD_TIME_OUT;
break;
}
udelay(1);
status = bfin_read_SDH_STATUS();
} while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
CMD_CRC_FAIL)));
if (flags & MMC_RSP_PRESENT) {
mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
if (flags & MMC_RSP_136) {
mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
}
}
if (status & CMD_TIME_OUT)
ret = TIMEOUT;
else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
ret = COMM_ERR;
else
ret = 0;
bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
return ret;
}
/* set data for single block transfer */
static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
{
u16 data_ctl = 0;
u16 dma_cfg = 0;
int ret = 0;
unsigned long data_size = data->blocksize * data->blocks;
/* Don't support write yet. */
if (data->flags & MMC_DATA_WRITE)
return UNUSABLE_ERR;
data_ctl |= ((ffs(data_size) - 1) << 4);
data_ctl |= DTX_DIR;
bfin_write_SDH_DATA_CTL(data_ctl);
dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
bfin_write_SDH_DATA_TIMER(-1);
blackfin_dcache_flush_invalidate_range(data->dest,
data->dest + data_size);
/* configure DMA */
bfin_write_DMA_START_ADDR(data->dest);
bfin_write_DMA_X_COUNT(data_size / 4);
bfin_write_DMA_X_MODIFY(4);
bfin_write_DMA_CONFIG(dma_cfg);
bfin_write_SDH_DATA_LGTH(data_size);
/* kick off transfer */
bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
return ret;
}
static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
u32 status;
int ret = 0;
ret = sdh_send_cmd(mmc, cmd);
if (ret) {
printf("sending CMD%d failed\n", cmd->cmdidx);
return ret;
}
if (data) {
ret = sdh_setup_data(mmc, data);
do {
udelay(1);
status = bfin_read_SDH_STATUS();
} while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
if (status & DAT_TIME_OUT) {
bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
ret |= TIMEOUT;
} else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
ret |= COMM_ERR;
} else
bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
if (ret) {
printf("tranfering data failed\n");
return ret;
}
}
return 0;
}
static void sdh_set_clk(unsigned long clk)
{
unsigned long sys_clk;
unsigned long clk_div;
u16 clk_ctl = 0;
clk_ctl = bfin_read_SDH_CLK_CTL();
if (clk) {
/* setting SD_CLK */
sys_clk = get_sclk();
bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
if (sys_clk % (2 * clk) == 0)
clk_div = sys_clk / (2 * clk) - 1;
else
clk_div = sys_clk / (2 * clk);
if (clk_div > 0xff)
clk_div = 0xff;
clk_ctl |= (clk_div & 0xff);
clk_ctl |= CLK_E;
bfin_write_SDH_CLK_CTL(clk_ctl);
} else
bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
}
static void bfin_sdh_set_ios(struct mmc *mmc)
{
u16 cfg = 0;
u16 clk_ctl = 0;
if (mmc->bus_width == 4) {
cfg = bfin_read_SDH_CFG();
cfg &= ~0x80;
cfg |= 0x40;
bfin_write_SDH_CFG(cfg);
clk_ctl |= WIDE_BUS;
}
bfin_write_SDH_CLK_CTL(clk_ctl);
sdh_set_clk(mmc->clock);
}
static int bfin_sdh_init(struct mmc *mmc)
{
const unsigned short pins[] = PORTMUX_PINS;
u16 pwr_ctl = 0;
/* Initialize sdh controller */
peripheral_request_list(pins, "bfin_sdh");
#if defined(__ADSPBF54x__)
bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
#endif
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
/* Disable card detect pin */
bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
pwr_ctl |= ROD_CTL;
pwr_ctl |= PWR_ON;
bfin_write_SDH_PWR_CTL(pwr_ctl);
return 0;
}
int bfin_mmc_init(bd_t *bis)
{
struct mmc *mmc = NULL;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
return -ENOMEM;
sprintf(mmc->name, "Blackfin SDH");
mmc->send_cmd = bfin_sdh_request;
mmc->set_ios = bfin_sdh_set_ios;
mmc->init = bfin_sdh_init;
mmc->host_caps = MMC_MODE_4BIT;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->f_max = get_sclk();
mmc->f_min = mmc->f_max >> 9;
mmc->block_dev.part_type = PART_TYPE_DOS;
mmc->b_max = 0;
mmc_register(mmc);
return 0;
}
|
1001-study-uboot
|
drivers/mmc/bfin_sdh.c
|
C
|
gpl3
| 6,977
|
/*
* MMCIF driver.
*
* Copyright (C) 2011 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#include <config.h>
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <mmc.h>
#include <malloc.h>
#include <asm/errno.h>
#include <asm/io.h>
#include "sh_mmcif.h"
#define DRIVER_NAME "sh_mmcif"
static void *mmc_priv(struct mmc *mmc)
{
return (void *)mmc->priv;
}
static int sh_mmcif_intr(void *dev_id)
{
struct sh_mmcif_host *host = dev_id;
u32 state = 0;
state = sh_mmcif_read(&host->regs->ce_int);
state &= sh_mmcif_read(&host->regs->ce_int_mask);
if (state & INT_RBSYE) {
sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
goto end;
} else if (state & INT_CRSPE) {
sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
/* one more interrupt (INT_RBSYE) */
if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
return -EAGAIN;
goto end;
} else if (state & INT_BUFREN) {
sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
goto end;
} else if (state & INT_BUFWEN) {
sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
goto end;
} else if (state & INT_CMD12DRE) {
sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
INT_BUFRE), &host->regs->ce_int);
sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
goto end;
} else if (state & INT_BUFRE) {
sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
goto end;
} else if (state & INT_DTRANE) {
sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
goto end;
} else if (state & INT_CMD12RBE) {
sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
&host->regs->ce_int);
sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
goto end;
} else if (state & INT_ERR_STS) {
/* err interrupts */
sh_mmcif_write(~state, &host->regs->ce_int);
sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
goto err;
} else
return -EAGAIN;
err:
host->sd_error = 1;
debug("%s: int err state = %08x\n", DRIVER_NAME, state);
end:
host->wait_int = 1;
return 0;
}
static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
{
int timeout = 10000000;
while (1) {
timeout--;
if (timeout < 0) {
printf("timeout\n");
return 0;
}
if (!sh_mmcif_intr(host))
break;
udelay(1); /* 1 usec */
}
return 1; /* Return value: NOT 0 = complete waiting */
}
static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
{
int i;
sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
if (!clk)
return;
if (clk == CLKDEV_EMMC_DATA) {
sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
} else {
for (i = 1; (unsigned int)host->clk / (1 << i) >= clk; i++)
;
sh_mmcif_bitset((i - 1) << 16, &host->regs->ce_clk_ctrl);
}
sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
}
static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
{
u32 tmp;
tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
CLK_CLEAR);
sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
&host->regs->ce_clk_ctrl);
/* byte swap on */
sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
}
static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
{
u32 state1, state2;
int ret, timeout = 10000000;
host->sd_error = 0;
host->wait_int = 0;
state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
debug("%s: ERR HOST_STS1 = %08x\n", \
DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
debug("%s: ERR HOST_STS2 = %08x\n", \
DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
if (state1 & STS1_CMDSEQ) {
debug("%s: Forced end of command sequence\n", DRIVER_NAME);
sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
while (1) {
timeout--;
if (timeout < 0) {
printf(DRIVER_NAME": Forceed end of " \
"command sequence timeout err\n");
return -EILSEQ;
}
if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
& STS1_CMDSEQ))
break;
}
sh_mmcif_sync_reset(host);
return -EILSEQ;
}
if (state2 & STS2_CRC_ERR)
ret = -EILSEQ;
else if (state2 & STS2_TIMEOUT_ERR)
ret = TIMEOUT;
else
ret = -EILSEQ;
return ret;
}
static int sh_mmcif_single_read(struct sh_mmcif_host *host,
struct mmc_data *data)
{
long time;
u32 blocksize, i;
unsigned long *p = (unsigned long *)data->dest;
if ((unsigned long)p & 0x00000001) {
printf("%s: The data pointer is unaligned.", __func__);
return -EIO;
}
host->wait_int = 0;
/* buf read enable */
sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
time = mmcif_wait_interrupt_flag(host);
if (time == 0 || host->sd_error != 0)
return sh_mmcif_error_manage(host);
host->wait_int = 0;
blocksize = (BLOCK_SIZE_MASK &
sh_mmcif_read(&host->regs->ce_block_set)) + 3;
for (i = 0; i < blocksize / 4; i++)
*p++ = sh_mmcif_read(&host->regs->ce_data);
/* buffer read end */
sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
time = mmcif_wait_interrupt_flag(host);
if (time == 0 || host->sd_error != 0)
return sh_mmcif_error_manage(host);
host->wait_int = 0;
return 0;
}
static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
struct mmc_data *data)
{
long time;
u32 blocksize, i, j;
unsigned long *p = (unsigned long *)data->dest;
if ((unsigned long)p & 0x00000001) {
printf("%s: The data pointer is unaligned.", __func__);
return -EIO;
}
host->wait_int = 0;
blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
for (j = 0; j < data->blocks; j++) {
sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
time = mmcif_wait_interrupt_flag(host);
if (time == 0 || host->sd_error != 0)
return sh_mmcif_error_manage(host);
host->wait_int = 0;
for (i = 0; i < blocksize / 4; i++)
*p++ = sh_mmcif_read(&host->regs->ce_data);
WATCHDOG_RESET();
}
return 0;
}
static int sh_mmcif_single_write(struct sh_mmcif_host *host,
struct mmc_data *data)
{
long time;
u32 blocksize, i;
const unsigned long *p = (unsigned long *)data->dest;
if ((unsigned long)p & 0x00000001) {
printf("%s: The data pointer is unaligned.", __func__);
return -EIO;
}
host->wait_int = 0;
sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
time = mmcif_wait_interrupt_flag(host);
if (time == 0 || host->sd_error != 0)
return sh_mmcif_error_manage(host);
host->wait_int = 0;
blocksize = (BLOCK_SIZE_MASK &
sh_mmcif_read(&host->regs->ce_block_set)) + 3;
for (i = 0; i < blocksize / 4; i++)
sh_mmcif_write(*p++, &host->regs->ce_data);
/* buffer write end */
sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
time = mmcif_wait_interrupt_flag(host);
if (time == 0 || host->sd_error != 0)
return sh_mmcif_error_manage(host);
host->wait_int = 0;
return 0;
}
static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
struct mmc_data *data)
{
long time;
u32 i, j, blocksize;
const unsigned long *p = (unsigned long *)data->dest;
if ((unsigned long)p & 0x00000001) {
printf("%s: The data pointer is unaligned.", __func__);
return -EIO;
}
host->wait_int = 0;
blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
for (j = 0; j < data->blocks; j++) {
sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
time = mmcif_wait_interrupt_flag(host);
if (time == 0 || host->sd_error != 0)
return sh_mmcif_error_manage(host);
host->wait_int = 0;
for (i = 0; i < blocksize / 4; i++)
sh_mmcif_write(*p++, &host->regs->ce_data);
WATCHDOG_RESET();
}
return 0;
}
static void sh_mmcif_get_response(struct sh_mmcif_host *host,
struct mmc_cmd *cmd)
{
if (cmd->resp_type & MMC_RSP_136) {
cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
cmd->response[1], cmd->response[2], cmd->response[3]);
} else {
cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
}
}
static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
struct mmc_cmd *cmd)
{
cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
}
static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
struct mmc_data *data, struct mmc_cmd *cmd)
{
u32 tmp = 0;
u32 opc = cmd->cmdidx;
/* Response Type check */
switch (cmd->resp_type) {
case MMC_RSP_NONE:
tmp |= CMD_SET_RTYP_NO;
break;
case MMC_RSP_R1:
case MMC_RSP_R1b:
case MMC_RSP_R3:
tmp |= CMD_SET_RTYP_6B;
break;
case MMC_RSP_R2:
tmp |= CMD_SET_RTYP_17B;
break;
default:
printf(DRIVER_NAME": Not support type response.\n");
break;
}
/* RBSY */
if (opc == MMC_CMD_SWITCH)
tmp |= CMD_SET_RBSY;
/* WDAT / DATW */
if (host->data) {
tmp |= CMD_SET_WDAT;
switch (host->bus_width) {
case MMC_BUS_WIDTH_1:
tmp |= CMD_SET_DATW_1;
break;
case MMC_BUS_WIDTH_4:
tmp |= CMD_SET_DATW_4;
break;
case MMC_BUS_WIDTH_8:
tmp |= CMD_SET_DATW_8;
break;
default:
printf(DRIVER_NAME": Not support bus width.\n");
break;
}
}
/* DWEN */
if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
tmp |= CMD_SET_DWEN;
/* CMLTE/CMD12EN */
if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
}
/* RIDXC[1:0] check bits */
if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
tmp |= CMD_SET_RIDXC_BITS;
/* RCRC7C[1:0] check bits */
if (opc == MMC_CMD_SEND_OP_COND)
tmp |= CMD_SET_CRC7C_BITS;
/* RCRC7C[1:0] internal CRC7 */
if (opc == MMC_CMD_ALL_SEND_CID ||
opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
tmp |= CMD_SET_CRC7C_INTERNAL;
return opc = ((opc << 24) | tmp);
}
static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
struct mmc_data *data, u16 opc)
{
u32 ret;
switch (opc) {
case MMC_CMD_READ_MULTIPLE_BLOCK:
ret = sh_mmcif_multi_read(host, data);
break;
case MMC_CMD_WRITE_MULTIPLE_BLOCK:
ret = sh_mmcif_multi_write(host, data);
break;
case MMC_CMD_WRITE_SINGLE_BLOCK:
ret = sh_mmcif_single_write(host, data);
break;
case MMC_CMD_READ_SINGLE_BLOCK:
case MMC_CMD_SEND_EXT_CSD:
ret = sh_mmcif_single_read(host, data);
break;
default:
printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
ret = -EINVAL;
break;
}
return ret;
}
static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
struct mmc_data *data, struct mmc_cmd *cmd)
{
long time;
int ret = 0, mask = 0;
u32 opc = cmd->cmdidx;
if (opc == MMC_CMD_STOP_TRANSMISSION) {
/* MMCIF sends the STOP command automatically */
if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
sh_mmcif_bitset(MASK_MCMD12DRE,
&host->regs->ce_int_mask);
else
sh_mmcif_bitset(MASK_MCMD12RBE,
&host->regs->ce_int_mask);
time = mmcif_wait_interrupt_flag(host);
if (time == 0 || host->sd_error != 0)
return sh_mmcif_error_manage(host);
sh_mmcif_get_cmd12response(host, cmd);
return 0;
}
if (opc == MMC_CMD_SWITCH)
mask = MASK_MRBSYE;
else
mask = MASK_MCRSPE;
mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
if (host->data) {
sh_mmcif_write(0, &host->regs->ce_block_set);
sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
}
opc = sh_mmcif_set_cmd(host, data, cmd);
sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
sh_mmcif_write(mask, &host->regs->ce_int_mask);
debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
/* set arg */
sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
host->wait_int = 0;
/* set cmd */
sh_mmcif_write(opc, &host->regs->ce_cmd_set);
time = mmcif_wait_interrupt_flag(host);
if (time == 0)
return sh_mmcif_error_manage(host);
if (host->sd_error) {
switch (cmd->cmdidx) {
case MMC_CMD_ALL_SEND_CID:
case MMC_CMD_SELECT_CARD:
case MMC_CMD_APP_CMD:
ret = TIMEOUT;
break;
default:
printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
ret = sh_mmcif_error_manage(host);
break;
}
host->sd_error = 0;
host->wait_int = 0;
return ret;
}
/* if no response */
if (!(opc & 0x00C00000))
return 0;
if (host->wait_int == 1) {
sh_mmcif_get_response(host, cmd);
host->wait_int = 0;
}
if (host->data)
ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
host->last_cmd = cmd->cmdidx;
return ret;
}
static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
struct sh_mmcif_host *host = mmc_priv(mmc);
int ret;
WATCHDOG_RESET();
switch (cmd->cmdidx) {
case MMC_CMD_APP_CMD:
return TIMEOUT;
case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
if (data)
/* ext_csd */
break;
else
/* send_if_cond cmd (not support) */
return TIMEOUT;
default:
break;
}
host->sd_error = 0;
host->data = data;
ret = sh_mmcif_start_cmd(host, data, cmd);
host->data = NULL;
return ret;
}
static void sh_mmcif_set_ios(struct mmc *mmc)
{
struct sh_mmcif_host *host = mmc_priv(mmc);
if (mmc->clock)
sh_mmcif_clock_control(host, mmc->clock);
if (mmc->bus_width == 8)
host->bus_width = MMC_BUS_WIDTH_8;
else if (mmc->bus_width == 4)
host->bus_width = MMC_BUS_WIDTH_4;
else
host->bus_width = MMC_BUS_WIDTH_1;
debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
}
static int sh_mmcif_init(struct mmc *mmc)
{
struct sh_mmcif_host *host = mmc_priv(mmc);
sh_mmcif_sync_reset(host);
sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
return 0;
}
int mmcif_mmc_init(void)
{
int ret = 0;
struct mmc *mmc;
struct sh_mmcif_host *host = NULL;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
ret = -ENOMEM;
memset(mmc, 0, sizeof(*mmc));
host = malloc(sizeof(struct sh_mmcif_host));
if (!host)
ret = -ENOMEM;
memset(host, 0, sizeof(*host));
mmc->f_min = CLKDEV_MMC_INIT;
mmc->f_max = CLKDEV_EMMC_DATA;
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
MMC_MODE_8BIT;
memcpy(mmc->name, DRIVER_NAME, sizeof(DRIVER_NAME));
mmc->send_cmd = sh_mmcif_request;
mmc->set_ios = sh_mmcif_set_ios;
mmc->init = sh_mmcif_init;
host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
host->clk = CONFIG_SH_MMCIF_CLK;
mmc->priv = host;
mmc_register(mmc);
return ret;
}
|
1001-study-uboot
|
drivers/mmc/sh_mmcif.c
|
C
|
gpl3
| 15,317
|
/*
* ARM PrimeCell MultiMedia Card Interface - PL180
*
* Copyright (C) ST-Ericsson SA 2010
*
* Author: Ulf Hansson <ulf.hansson@stericsson.com>
* Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
* Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ARM_PL180_MMCI_H__
#define __ARM_PL180_MMCI_H__
int arm_pl180_mmci_init(void);
#define COMMAND_REG_DELAY 300
#define DATA_REG_DELAY 1000
#define CLK_CHANGE_DELAY 2000
#define INIT_PWR 0xBF /* Power on, full power, not open drain */
#define ARM_MCLK (100*1000*1000)
/* SDI Power Control register bits */
#define SDI_PWR_PWRCTRL_MASK 0x00000003
#define SDI_PWR_PWRCTRL_ON 0x00000003
#define SDI_PWR_PWRCTRL_OFF 0x00000000
#define SDI_PWR_DAT2DIREN 0x00000004
#define SDI_PWR_CMDDIREN 0x00000008
#define SDI_PWR_DAT0DIREN 0x00000010
#define SDI_PWR_DAT31DIREN 0x00000020
#define SDI_PWR_OPD 0x00000040
#define SDI_PWR_FBCLKEN 0x00000080
#define SDI_PWR_DAT74DIREN 0x00000100
#define SDI_PWR_RSTEN 0x00000200
#define VOLTAGE_WINDOW_MMC 0x00FF8080
#define VOLTAGE_WINDOW_SD 0x80010000
/* SDI clock control register bits */
#define SDI_CLKCR_CLKDIV_MASK 0x000000FF
#define SDI_CLKCR_CLKEN 0x00000100
#define SDI_CLKCR_PWRSAV 0x00000200
#define SDI_CLKCR_BYPASS 0x00000400
#define SDI_CLKCR_WIDBUS_MASK 0x00001800
#define SDI_CLKCR_WIDBUS_1 0x00000000
#define SDI_CLKCR_WIDBUS_4 0x00000800
#define SDI_CLKCR_CLKDIV_INIT 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
/* SDI command register bits */
#define SDI_CMD_CMDINDEX_MASK 0x000000FF
#define SDI_CMD_WAITRESP 0x00000040
#define SDI_CMD_LONGRESP 0x00000080
#define SDI_CMD_WAITINT 0x00000100
#define SDI_CMD_WAITPEND 0x00000200
#define SDI_CMD_CPSMEN 0x00000400
#define SDI_CMD_SDIOSUSPEND 0x00000800
#define SDI_CMD_ENDCMDCOMPL 0x00001000
#define SDI_CMD_NIEN 0x00002000
#define SDI_CMD_CE_ATACMD 0x00004000
#define SDI_CMD_CBOOTMODEEN 0x00008000
#define SDI_DTIMER_DEFAULT 0xFFFF0000
/* SDI Status register bits */
#define SDI_STA_CCRCFAIL 0x00000001
#define SDI_STA_DCRCFAIL 0x00000002
#define SDI_STA_CTIMEOUT 0x00000004
#define SDI_STA_DTIMEOUT 0x00000008
#define SDI_STA_TXUNDERR 0x00000010
#define SDI_STA_RXOVERR 0x00000020
#define SDI_STA_CMDREND 0x00000040
#define SDI_STA_CMDSENT 0x00000080
#define SDI_STA_DATAEND 0x00000100
#define SDI_STA_STBITERR 0x00000200
#define SDI_STA_DBCKEND 0x00000400
#define SDI_STA_CMDACT 0x00000800
#define SDI_STA_TXACT 0x00001000
#define SDI_STA_RXACT 0x00002000
#define SDI_STA_TXFIFOBW 0x00004000
#define SDI_STA_RXFIFOBR 0x00008000
#define SDI_STA_TXFIFOF 0x00010000
#define SDI_STA_RXFIFOF 0x00020000
#define SDI_STA_TXFIFOE 0x00040000
#define SDI_STA_RXFIFOE 0x00080000
#define SDI_STA_TXDAVL 0x00100000
#define SDI_STA_RXDAVL 0x00200000
#define SDI_STA_SDIOIT 0x00400000
#define SDI_STA_CEATAEND 0x00800000
#define SDI_STA_CARDBUSY 0x01000000
#define SDI_STA_BOOTMODE 0x02000000
#define SDI_STA_BOOTACKERR 0x04000000
#define SDI_STA_BOOTACKTIMEOUT 0x08000000
#define SDI_STA_RSTNEND 0x10000000
/* SDI Interrupt Clear register bits */
#define SDI_ICR_MASK 0x1DC007FF
#define SDI_ICR_CCRCFAILC 0x00000001
#define SDI_ICR_DCRCFAILC 0x00000002
#define SDI_ICR_CTIMEOUTC 0x00000004
#define SDI_ICR_DTIMEOUTC 0x00000008
#define SDI_ICR_TXUNDERRC 0x00000010
#define SDI_ICR_RXOVERRC 0x00000020
#define SDI_ICR_CMDRENDC 0x00000040
#define SDI_ICR_CMDSENTC 0x00000080
#define SDI_ICR_DATAENDC 0x00000100
#define SDI_ICR_STBITERRC 0x00000200
#define SDI_ICR_DBCKENDC 0x00000400
#define SDI_ICR_SDIOITC 0x00400000
#define SDI_ICR_CEATAENDC 0x00800000
#define SDI_ICR_BUSYENDC 0x01000000
#define SDI_ICR_BOOTACKERRC 0x04000000
#define SDI_ICR_BOOTACKTIMEOUTC 0x08000000
#define SDI_ICR_RSTNENDC 0x10000000
#define SDI_MASK0_MASK 0x1FFFFFFF
/* SDI Data control register bits */
#define SDI_DCTRL_DTEN 0x00000001
#define SDI_DCTRL_DTDIR_IN 0x00000002
#define SDI_DCTRL_DTMODE_STREAM 0x00000004
#define SDI_DCTRL_DMAEN 0x00000008
#define SDI_DCTRL_DBLKSIZE_MASK 0x000000F0
#define SDI_DCTRL_RWSTART 0x00000100
#define SDI_DCTRL_RWSTOP 0x00000200
#define SDI_DCTRL_RWMOD 0x00000200
#define SDI_DCTRL_SDIOEN 0x00000800
#define SDI_DCTRL_DMAREQCTL 0x00001000
#define SDI_DCTRL_DBOOTMODEEN 0x00002000
#define SDI_DCTRL_BUSYMODE 0x00004000
#define SDI_DCTRL_DDR_MODE 0x00008000
#define SDI_FIFO_BURST_SIZE 8
struct sdi_registers {
u32 power; /* 0x00*/
u32 clock; /* 0x04*/
u32 argument; /* 0x08*/
u32 command; /* 0x0c*/
u32 respcommand; /* 0x10*/
u32 response0; /* 0x14*/
u32 response1; /* 0x18*/
u32 response2; /* 0x1c*/
u32 response3; /* 0x20*/
u32 datatimer; /* 0x24*/
u32 datalength; /* 0x28*/
u32 datactrl; /* 0x2c*/
u32 datacount; /* 0x30*/
u32 status; /* 0x34*/
u32 status_clear; /* 0x38*/
u32 mask0; /* 0x3c*/
u32 mask1; /* 0x40*/
u32 card_select; /* 0x44*/
u32 fifo_count; /* 0x48*/
u32 padding1[(0x80-0x4C)>>2];
u32 fifo; /* 0x80*/
u32 padding2[(0xFE0-0x84)>>2];
u32 periph_id0; /* 0xFE0 mmc Peripheral Identifcation Register*/
u32 periph_id1; /* 0xFE4*/
u32 periph_id2; /* 0xFE8*/
u32 periph_id3; /* 0xFEC*/
u32 pcell_id0; /* 0xFF0*/
u32 pcell_id1; /* 0xFF4*/
u32 pcell_id2; /* 0xFF8*/
u32 pcell_id3; /* 0xFFC*/
};
#endif
|
1001-study-uboot
|
drivers/mmc/arm_pl180_mmci.h
|
C
|
gpl3
| 5,924
|
/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* (C) Copyright 2004
* ARM Ltd.
* Philippe Robin, <philippe.robin@arm.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
#include "serial_pl01x.h"
/*
* Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
* Integrator CP has two UARTs, use the first one, at 38400-8-N-1
* Versatile PB has four UARTs.
*/
#define CONSOLE_PORT CONFIG_CONS_INDEX
static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
static void pl01x_putc (int portnum, char c);
static int pl01x_getc (int portnum);
static int pl01x_tstc (int portnum);
unsigned int baudrate = CONFIG_BAUDRATE;
DECLARE_GLOBAL_DATA_PTR;
static struct pl01x_regs *pl01x_get_regs(int portnum)
{
return (struct pl01x_regs *) port[portnum];
}
#ifdef CONFIG_PL010_SERIAL
int serial_init (void)
{
struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int divisor;
/* First, disable everything */
writel(0, ®s->pl010_cr);
/* Set baud rate */
switch (baudrate) {
case 9600:
divisor = UART_PL010_BAUD_9600;
break;
case 19200:
divisor = UART_PL010_BAUD_9600;
break;
case 38400:
divisor = UART_PL010_BAUD_38400;
break;
case 57600:
divisor = UART_PL010_BAUD_57600;
break;
case 115200:
divisor = UART_PL010_BAUD_115200;
break;
default:
divisor = UART_PL010_BAUD_38400;
}
writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
writel(divisor & 0xff, ®s->pl010_lcrl);
/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh);
/* Finally, enable the UART */
writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
return 0;
}
#endif /* CONFIG_PL010_SERIAL */
#ifdef CONFIG_PL011_SERIAL
int serial_init (void)
{
struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int temp;
unsigned int divider;
unsigned int remainder;
unsigned int fraction;
unsigned int lcr;
#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
/* Empty RX fifo if necessary */
if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
readl(®s->dr);
}
#endif
/* First, disable everything */
writel(0, ®s->pl011_cr);
/*
* Set baud rate
*
* IBRD = UART_CLK / (16 * BAUD_RATE)
* FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
*/
temp = 16 * baudrate;
divider = CONFIG_PL011_CLOCK / temp;
remainder = CONFIG_PL011_CLOCK % temp;
temp = (8 * remainder) / baudrate;
fraction = (temp >> 1) + (temp & 1);
writel(divider, ®s->pl011_ibrd);
writel(fraction, ®s->pl011_fbrd);
/* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
writel(lcr, ®s->pl011_lcrh);
#ifdef CONFIG_PL011_SERIAL_RLCR
{
int i;
/*
* Program receive line control register after waiting
* 10 bus cycles. Delay be writing to readonly register
* 10 times
*/
for (i = 0; i < 10; i++)
writel(lcr, ®s->fr);
writel(lcr, ®s->pl011_rlcr);
}
#endif
/* Finally, enable the UART */
writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE,
®s->pl011_cr);
return 0;
}
#endif /* CONFIG_PL011_SERIAL */
void serial_putc (const char c)
{
if (c == '\n')
pl01x_putc (CONSOLE_PORT, '\r');
pl01x_putc (CONSOLE_PORT, c);
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int serial_getc (void)
{
return pl01x_getc (CONSOLE_PORT);
}
int serial_tstc (void)
{
return pl01x_tstc (CONSOLE_PORT);
}
void serial_setbrg (void)
{
struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
baudrate = gd->baudrate;
/*
* Flush FIFO and wait for non-busy before changing baudrate to avoid
* crap in console
*/
while (!(readl(®s->fr) & UART_PL01x_FR_TXFE))
WATCHDOG_RESET();
while (readl(®s->fr) & UART_PL01x_FR_BUSY)
WATCHDOG_RESET();
serial_init();
}
static void pl01x_putc (int portnum, char c)
{
struct pl01x_regs *regs = pl01x_get_regs(portnum);
/* Wait until there is space in the FIFO */
while (readl(®s->fr) & UART_PL01x_FR_TXFF)
WATCHDOG_RESET();
/* Send the character */
writel(c, ®s->dr);
}
static int pl01x_getc (int portnum)
{
struct pl01x_regs *regs = pl01x_get_regs(portnum);
unsigned int data;
/* Wait until there is data in the FIFO */
while (readl(®s->fr) & UART_PL01x_FR_RXFE)
WATCHDOG_RESET();
data = readl(®s->dr);
/* Check for an error flag */
if (data & 0xFFFFFF00) {
/* Clear the error */
writel(0xFFFFFFFF, ®s->ecr);
return -1;
}
return (int) data;
}
static int pl01x_tstc (int portnum)
{
struct pl01x_regs *regs = pl01x_get_regs(portnum);
WATCHDOG_RESET();
return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
}
|
1001-study-uboot
|
drivers/serial/serial_pl01x.c
|
C
|
gpl3
| 5,716
|
/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/compiler.h>
#include <ns16550.h>
#ifdef CONFIG_NS87308
#include <ns87308.h>
#endif
#if defined (CONFIG_SERIAL_MULTI)
#include <serial.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_CONS_INDEX)
#if defined (CONFIG_SERIAL_MULTI)
/* with CONFIG_SERIAL_MULTI we might have no console
* on these devices
*/
#else
#error "No console index specified."
#endif /* CONFIG_SERIAL_MULTI */
#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
#error "Invalid console index value."
#endif
#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
#error "Console port 1 defined but not configured."
#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
#error "Console port 2 defined but not configured."
#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
#error "Console port 3 defined but not configured."
#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
#error "Console port 4 defined but not configured."
#endif
/* Note: The port number specified in the functions is 1 based.
* the array is 0 based.
*/
static NS16550_t serial_ports[4] = {
#ifdef CONFIG_SYS_NS16550_COM1
(NS16550_t)CONFIG_SYS_NS16550_COM1,
#else
NULL,
#endif
#ifdef CONFIG_SYS_NS16550_COM2
(NS16550_t)CONFIG_SYS_NS16550_COM2,
#else
NULL,
#endif
#ifdef CONFIG_SYS_NS16550_COM3
(NS16550_t)CONFIG_SYS_NS16550_COM3,
#else
NULL,
#endif
#ifdef CONFIG_SYS_NS16550_COM4
(NS16550_t)CONFIG_SYS_NS16550_COM4
#else
NULL
#endif
};
#define PORT serial_ports[port-1]
#if defined(CONFIG_CONS_INDEX)
#define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1])
#endif
#if defined(CONFIG_SERIAL_MULTI)
/* Multi serial device functions */
#define DECLARE_ESERIAL_FUNCTIONS(port) \
int eserial##port##_init (void) {\
int clock_divisor; \
clock_divisor = calc_divisor(serial_ports[port-1]); \
NS16550_init(serial_ports[port-1], clock_divisor); \
return(0);}\
void eserial##port##_setbrg (void) {\
serial_setbrg_dev(port);}\
int eserial##port##_getc (void) {\
return serial_getc_dev(port);}\
int eserial##port##_tstc (void) {\
return serial_tstc_dev(port);}\
void eserial##port##_putc (const char c) {\
serial_putc_dev(port, c);}\
void eserial##port##_puts (const char *s) {\
serial_puts_dev(port, s);}
/* Serial device descriptor */
#define INIT_ESERIAL_STRUCTURE(port, name) {\
name,\
eserial##port##_init,\
NULL,\
eserial##port##_setbrg,\
eserial##port##_getc,\
eserial##port##_tstc,\
eserial##port##_putc,\
eserial##port##_puts, }
#endif /* CONFIG_SERIAL_MULTI */
static int calc_divisor (NS16550_t port)
{
#ifdef CONFIG_OMAP1510
/* If can't cleanly clock 115200 set div to 1 */
if ((CONFIG_SYS_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
return (1); /* return 1 for base divisor */
}
port->osc_12m_sel = 0; /* clear if previsouly set */
#endif
#ifdef CONFIG_OMAP1610
/* If can't cleanly clock 115200 set div to 1 */
if ((CONFIG_SYS_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
return (26); /* return 26 for base divisor */
}
#endif
#ifdef CONFIG_APTIX
#define MODE_X_DIV 13
#else
#define MODE_X_DIV 16
#endif
/* Compute divisor value. Normally, we should simply return:
* CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
* but we need to round that value by adding 0.5.
* Rounding is especially important at high baud rates.
*/
return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
(MODE_X_DIV * gd->baudrate);
}
#if !defined(CONFIG_SERIAL_MULTI)
int serial_init (void)
{
int clock_divisor;
#ifdef CONFIG_NS87308
initialise_ns87308();
#endif
#ifdef CONFIG_SYS_NS16550_COM1
clock_divisor = calc_divisor(serial_ports[0]);
NS16550_init(serial_ports[0], clock_divisor);
#endif
#ifdef CONFIG_SYS_NS16550_COM2
clock_divisor = calc_divisor(serial_ports[1]);
NS16550_init(serial_ports[1], clock_divisor);
#endif
#ifdef CONFIG_SYS_NS16550_COM3
clock_divisor = calc_divisor(serial_ports[2]);
NS16550_init(serial_ports[2], clock_divisor);
#endif
#ifdef CONFIG_SYS_NS16550_COM4
clock_divisor = calc_divisor(serial_ports[3]);
NS16550_init(serial_ports[3], clock_divisor);
#endif
return (0);
}
#endif
void
_serial_putc(const char c,const int port)
{
if (c == '\n')
NS16550_putc(PORT, '\r');
NS16550_putc(PORT, c);
}
void
_serial_putc_raw(const char c,const int port)
{
NS16550_putc(PORT, c);
}
void
_serial_puts (const char *s,const int port)
{
while (*s) {
_serial_putc (*s++,port);
}
}
int
_serial_getc(const int port)
{
return NS16550_getc(PORT);
}
int
_serial_tstc(const int port)
{
return NS16550_tstc(PORT);
}
void
_serial_setbrg (const int port)
{
int clock_divisor;
clock_divisor = calc_divisor(PORT);
NS16550_reinit(PORT, clock_divisor);
}
#if defined(CONFIG_SERIAL_MULTI)
static inline void
serial_putc_dev(unsigned int dev_index,const char c)
{
_serial_putc(c,dev_index);
}
#else
void
serial_putc(const char c)
{
_serial_putc(c,CONFIG_CONS_INDEX);
}
#endif
#if defined(CONFIG_SERIAL_MULTI)
static inline void
serial_putc_raw_dev(unsigned int dev_index,const char c)
{
_serial_putc_raw(c,dev_index);
}
#else
void
serial_putc_raw(const char c)
{
_serial_putc_raw(c,CONFIG_CONS_INDEX);
}
#endif
#if defined(CONFIG_SERIAL_MULTI)
static inline void
serial_puts_dev(unsigned int dev_index,const char *s)
{
_serial_puts(s,dev_index);
}
#else
void
serial_puts(const char *s)
{
_serial_puts(s,CONFIG_CONS_INDEX);
}
#endif
#if defined(CONFIG_SERIAL_MULTI)
static inline int
serial_getc_dev(unsigned int dev_index)
{
return _serial_getc(dev_index);
}
#else
int
serial_getc(void)
{
return _serial_getc(CONFIG_CONS_INDEX);
}
#endif
#if defined(CONFIG_SERIAL_MULTI)
static inline int
serial_tstc_dev(unsigned int dev_index)
{
return _serial_tstc(dev_index);
}
#else
int
serial_tstc(void)
{
return _serial_tstc(CONFIG_CONS_INDEX);
}
#endif
#if defined(CONFIG_SERIAL_MULTI)
static inline void
serial_setbrg_dev(unsigned int dev_index)
{
_serial_setbrg(dev_index);
}
#else
void
serial_setbrg(void)
{
_serial_setbrg(CONFIG_CONS_INDEX);
}
#endif
#if defined(CONFIG_SERIAL_MULTI)
DECLARE_ESERIAL_FUNCTIONS(1);
struct serial_device eserial1_device =
INIT_ESERIAL_STRUCTURE(1, "eserial0");
DECLARE_ESERIAL_FUNCTIONS(2);
struct serial_device eserial2_device =
INIT_ESERIAL_STRUCTURE(2, "eserial1");
DECLARE_ESERIAL_FUNCTIONS(3);
struct serial_device eserial3_device =
INIT_ESERIAL_STRUCTURE(3, "eserial2");
DECLARE_ESERIAL_FUNCTIONS(4);
struct serial_device eserial4_device =
INIT_ESERIAL_STRUCTURE(4, "eserial3");
__weak struct serial_device *default_serial_console(void)
{
#if CONFIG_CONS_INDEX == 1
return &eserial1_device;
#elif CONFIG_CONS_INDEX == 2
return &eserial2_device;
#elif CONFIG_CONS_INDEX == 3
return &eserial3_device;
#elif CONFIG_CONS_INDEX == 4
return &eserial4_device;
#else
#error "Bad CONFIG_CONS_INDEX."
#endif
}
#endif /* CONFIG_SERIAL_MULTI */
|
1001-study-uboot
|
drivers/serial/serial.c
|
C
|
gpl3
| 7,830
|
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <watchdog.h>
#include <serial.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/regs-uart.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
* easily handle enabling of clock.
*/
#ifdef CONFIG_CPU_MONAHANS
#define UART_CLK_BASE CKENA_21_BTUART
#define UART_CLK_REG CKENA
#define BTUART_INDEX 0
#define FFUART_INDEX 1
#define STUART_INDEX 2
#elif CONFIG_CPU_PXA25X
#define UART_CLK_BASE (1 << 4) /* HWUART */
#define UART_CLK_REG CKEN
#define HWUART_INDEX 0
#define STUART_INDEX 1
#define FFUART_INDEX 2
#define BTUART_INDEX 3
#else /* PXA27x */
#define UART_CLK_BASE CKEN5_STUART
#define UART_CLK_REG CKEN
#define STUART_INDEX 0
#define FFUART_INDEX 1
#define BTUART_INDEX 2
#endif
/*
* Only PXA250 has HWUART, to avoid poluting the code with more macros,
* artificially introduce this.
*/
#ifndef CONFIG_CPU_PXA25X
#define HWUART_INDEX 0xff
#endif
#ifndef CONFIG_SERIAL_MULTI
#if defined(CONFIG_FFUART)
#define UART_INDEX FFUART_INDEX
#elif defined(CONFIG_BTUART)
#define UART_INDEX BTUART_INDEX
#elif defined(CONFIG_STUART)
#define UART_INDEX STUART_INDEX
#elif defined(CONFIG_HWUART)
#define UART_INDEX HWUART_INDEX
#else
#error "Please select CONFIG_(FF|BT|ST|HW)UART in board config file."
#endif
#endif
uint32_t pxa_uart_get_baud_divider(void)
{
if (gd->baudrate == 1200)
return 768;
else if (gd->baudrate == 9600)
return 96;
else if (gd->baudrate == 19200)
return 48;
else if (gd->baudrate == 38400)
return 24;
else if (gd->baudrate == 57600)
return 16;
else if (gd->baudrate == 115200)
return 8;
else /* Unsupported baudrate */
return 0;
}
struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
{
switch (uart_index) {
case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
default:
return NULL;
}
}
void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
{
uint32_t clk_reg, clk_offset, reg;
clk_reg = UART_CLK_REG;
clk_offset = UART_CLK_BASE << uart_index;
reg = readl(clk_reg);
if (enable)
reg |= clk_offset;
else
reg &= ~clk_offset;
writel(reg, clk_reg);
}
/*
* Enable clock and set baud rate, parity etc.
*/
void pxa_setbrg_dev(uint32_t uart_index)
{
uint32_t divider = 0;
struct pxa_uart_regs *uart_regs;
divider = pxa_uart_get_baud_divider();
if (!divider)
hang();
uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
hang();
pxa_uart_toggle_clock(uart_index, 1);
/* Disable interrupts and FIFOs */
writel(0, &uart_regs->ier);
writel(0, &uart_regs->fcr);
/* Set baud rate */
writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr);
writel(divider & 0xff, &uart_regs->dll);
writel(divider >> 8, &uart_regs->dlh);
writel(LCR_WLS0 | LCR_WLS1, &uart_regs->lcr);
/* Enable UART */
writel(IER_UUE, &uart_regs->ier);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
int pxa_init_dev(unsigned int uart_index)
{
pxa_setbrg_dev (uart_index);
return 0;
}
/*
* Output a single byte to the serial port.
*/
void pxa_putc_dev(unsigned int uart_index, const char c)
{
struct pxa_uart_regs *uart_regs;
uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
hang();
while (!(readl(&uart_regs->lsr) & LSR_TEMT))
WATCHDOG_RESET();
writel(c, &uart_regs->thr);
/* If \n, also do \r */
if (c == '\n')
pxa_putc_dev (uart_index,'\r');
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int pxa_tstc_dev(unsigned int uart_index)
{
struct pxa_uart_regs *uart_regs;
uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
return -1;
return readl(&uart_regs->lsr) & LSR_DR;
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int pxa_getc_dev(unsigned int uart_index)
{
struct pxa_uart_regs *uart_regs;
uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
return -1;
while (!(readl(&uart_regs->lsr) & LSR_DR))
WATCHDOG_RESET();
return readl(&uart_regs->rbr) & 0xff;
}
void pxa_puts_dev(unsigned int uart_index, const char *s)
{
while (*s)
pxa_putc_dev(uart_index, *s++);
}
#define pxa_uart(uart, UART) \
int uart##_init(void) \
{ \
return pxa_init_dev(UART##_INDEX); \
} \
\
void uart##_setbrg(void) \
{ \
return pxa_setbrg_dev(UART##_INDEX); \
} \
\
void uart##_putc(const char c) \
{ \
return pxa_putc_dev(UART##_INDEX, c); \
} \
\
void uart##_puts(const char *s) \
{ \
return pxa_puts_dev(UART##_INDEX, s); \
} \
\
int uart##_getc(void) \
{ \
return pxa_getc_dev(UART##_INDEX); \
} \
\
int uart##_tstc(void) \
{ \
return pxa_tstc_dev(UART##_INDEX); \
} \
#define pxa_uart_desc(uart) \
struct serial_device serial_##uart##_device = \
{ \
"serial_"#uart, \
uart##_init, \
NULL, \
uart##_setbrg, \
uart##_getc, \
uart##_tstc, \
uart##_putc, \
uart##_puts, \
};
#define pxa_uart_multi(uart, UART) \
pxa_uart(uart, UART) \
pxa_uart_desc(uart)
#if defined(CONFIG_HWUART)
pxa_uart_multi(hwuart, HWUART)
#endif
#if defined(CONFIG_STUART)
pxa_uart_multi(stuart, STUART)
#endif
#if defined(CONFIG_FFUART)
pxa_uart_multi(ffuart, FFUART)
#endif
#if defined(CONFIG_BTUART)
pxa_uart_multi(btuart, BTUART)
#endif
#ifndef CONFIG_SERIAL_MULTI
pxa_uart(serial, UART)
#endif
|
1001-study-uboot
|
drivers/serial/serial_pxa.c
|
C
|
gpl3
| 7,146
|