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stringlengths 1
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stringlengths 3
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/*
* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew, Tsi-Chung.Liew@freescale.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/*
* Minimal serial functions needed to use one of the uart ports
* as serial console interface.
*/
#include <common.h>
#include <asm/immap.h>
#include <asm/uart.h>
DECLARE_GLOBAL_DATA_PTR;
extern void uart_port_conf(int port);
int serial_init(void)
{
volatile uart_t *uart;
u32 counter;
uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
uart_port_conf(CONFIG_SYS_UART_PORT);
/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
uart->ucr = UART_UCR_RESET_RX;
uart->ucr = UART_UCR_RESET_TX;
uart->ucr = UART_UCR_RESET_ERROR;
uart->ucr = UART_UCR_RESET_MR;
__asm__("nop");
uart->uimr = 0;
/* write to CSR: RX/TX baud rate from timers */
uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
uart->umr = UART_UMR_SB_STOP_BITS_1;
/* Setting up BaudRate */
counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
counter = counter / gd->baudrate;
/* write to CTUR: divide counter upper byte */
uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
/* write to CTLR: divide counter lower byte */
uart->ubg2 = (u8) (counter & 0x00ff);
uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
return (0);
}
void serial_putc(const char c)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
if (c == '\n')
serial_putc('\r');
/* Wait for last character to go. */
while (!(uart->usr & UART_USR_TXRDY)) ;
uart->utb = c;
}
void serial_puts(const char *s)
{
while (*s) {
serial_putc(*s++);
}
}
int serial_getc(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
/* Wait for a character to arrive. */
while (!(uart->usr & UART_USR_RXRDY)) ;
return uart->urb;
}
int serial_tstc(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
return (uart->usr & UART_USR_RXRDY);
}
void serial_setbrg(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
u32 counter;
/* Setting up BaudRate */
counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
counter = counter / gd->baudrate;
/* write to CTUR: divide counter upper byte */
uart->ubg1 = ((counter & 0xff00) >> 8);
/* write to CTLR: divide counter lower byte */
uart->ubg2 = (counter & 0x00ff);
uart->ucr = UART_UCR_RESET_RX;
uart->ucr = UART_UCR_RESET_TX;
uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
}
|
1001-study-uboot
|
drivers/serial/mcfuart.c
|
C
|
gpl3
| 3,283
|
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
#include <nios2-io.h>
DECLARE_GLOBAL_DATA_PTR;
/*------------------------------------------------------------------
* UART the serial port
*-----------------------------------------------------------------*/
static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE;
#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
/* Everything's already setup for fixed-baud PTF
* assignment
*/
void serial_setbrg (void){ return; }
int serial_init (void) { return (0);}
#else
void serial_setbrg (void)
{
unsigned div;
div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
writel (div, &uart->divisor);
return;
}
int serial_init (void)
{
serial_setbrg ();
return (0);
}
#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
/*-----------------------------------------------------------------------
* UART CONSOLE
*---------------------------------------------------------------------*/
void serial_putc (char c)
{
if (c == '\n')
serial_putc ('\r');
while ((readl (&uart->status) & NIOS_UART_TRDY) == 0)
WATCHDOG_RESET ();
writel ((unsigned char)c, &uart->txdata);
}
void serial_puts (const char *s)
{
while (*s != 0) {
serial_putc (*s++);
}
}
int serial_tstc (void)
{
return (readl (&uart->status) & NIOS_UART_RRDY);
}
int serial_getc (void)
{
while (serial_tstc () == 0)
WATCHDOG_RESET ();
return (readl (&uart->rxdata) & 0x00ff );
}
|
1001-study-uboot
|
drivers/serial/altera_uart.c
|
C
|
gpl3
| 2,298
|
/*
* (C) Copyright 2003
* Gerry Hamel, geh@ti.com, Texas Instruments
*
* (C) Copyright 2006
* Bryan O'Donoghue, bodonoghue@codehermit.ie
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <circbuf.h>
#include <stdio_dev.h>
#include <asm/unaligned.h>
#include "usbtty.h"
#include "usb_cdc_acm.h"
#include "usbdescriptors.h"
#ifdef DEBUG
#define TTYDBG(fmt,args...)\
serial_printf("[%s] %s %d: "fmt, __FILE__,__FUNCTION__,__LINE__,##args)
#else
#define TTYDBG(fmt,args...) do{}while(0)
#endif
#if 1
#define TTYERR(fmt,args...)\
serial_printf("ERROR![%s] %s %d: "fmt, __FILE__,__FUNCTION__,\
__LINE__,##args)
#else
#define TTYERR(fmt,args...) do{}while(0)
#endif
/*
* Defines
*/
#define NUM_CONFIGS 1
#define MAX_INTERFACES 2
#define NUM_ENDPOINTS 3
#define ACM_TX_ENDPOINT 3
#define ACM_RX_ENDPOINT 2
#define GSERIAL_TX_ENDPOINT 2
#define GSERIAL_RX_ENDPOINT 1
#define NUM_ACM_INTERFACES 2
#define NUM_GSERIAL_INTERFACES 1
#define CONFIG_USBD_DATA_INTERFACE_STR "Bulk Data Interface"
#define CONFIG_USBD_CTRL_INTERFACE_STR "Control Interface"
/*
* Buffers to hold input and output data
*/
#define USBTTY_BUFFER_SIZE 256
static circbuf_t usbtty_input;
static circbuf_t usbtty_output;
/*
* Instance variables
*/
static struct stdio_dev usbttydev;
static struct usb_device_instance device_instance[1];
static struct usb_bus_instance bus_instance[1];
static struct usb_configuration_instance config_instance[NUM_CONFIGS];
static struct usb_interface_instance interface_instance[MAX_INTERFACES];
static struct usb_alternate_instance alternate_instance[MAX_INTERFACES];
/* one extra for control endpoint */
static struct usb_endpoint_instance endpoint_instance[NUM_ENDPOINTS+1];
/*
* Global flag
*/
int usbtty_configured_flag = 0;
/*
* Serial number
*/
static char serial_number[16];
/*
* Descriptors, Strings, Local variables.
*/
/* defined and used by gadget/ep0.c */
extern struct usb_string_descriptor **usb_strings;
/* Indicies, References */
static unsigned short rx_endpoint = 0;
static unsigned short tx_endpoint = 0;
static unsigned short interface_count = 0;
static struct usb_string_descriptor *usbtty_string_table[STR_COUNT];
/* USB Descriptor Strings */
static u8 wstrLang[4] = {4,USB_DT_STRING,0x9,0x4};
static u8 wstrManufacturer[2 + 2*(sizeof(CONFIG_USBD_MANUFACTURER)-1)];
static u8 wstrProduct[2 + 2*(sizeof(CONFIG_USBD_PRODUCT_NAME)-1)];
static u8 wstrSerial[2 + 2*(sizeof(serial_number) - 1)];
static u8 wstrConfiguration[2 + 2*(sizeof(CONFIG_USBD_CONFIGURATION_STR)-1)];
static u8 wstrDataInterface[2 + 2*(sizeof(CONFIG_USBD_DATA_INTERFACE_STR)-1)];
static u8 wstrCtrlInterface[2 + 2*(sizeof(CONFIG_USBD_DATA_INTERFACE_STR)-1)];
/* Standard USB Data Structures */
static struct usb_interface_descriptor interface_descriptors[MAX_INTERFACES];
static struct usb_endpoint_descriptor *ep_descriptor_ptrs[NUM_ENDPOINTS];
static struct usb_configuration_descriptor *configuration_descriptor = 0;
static struct usb_device_descriptor device_descriptor = {
.bLength = sizeof(struct usb_device_descriptor),
.bDescriptorType = USB_DT_DEVICE,
.bcdUSB = cpu_to_le16(USB_BCD_VERSION),
.bDeviceSubClass = 0x00,
.bDeviceProtocol = 0x00,
.bMaxPacketSize0 = EP0_MAX_PACKET_SIZE,
.idVendor = cpu_to_le16(CONFIG_USBD_VENDORID),
.bcdDevice = cpu_to_le16(USBTTY_BCD_DEVICE),
.iManufacturer = STR_MANUFACTURER,
.iProduct = STR_PRODUCT,
.iSerialNumber = STR_SERIAL,
.bNumConfigurations = NUM_CONFIGS
};
/*
* Static CDC ACM specific descriptors
*/
struct acm_config_desc {
struct usb_configuration_descriptor configuration_desc;
/* Master Interface */
struct usb_interface_descriptor interface_desc;
struct usb_class_header_function_descriptor usb_class_header;
struct usb_class_call_management_descriptor usb_class_call_mgt;
struct usb_class_abstract_control_descriptor usb_class_acm;
struct usb_class_union_function_descriptor usb_class_union;
struct usb_endpoint_descriptor notification_endpoint;
/* Slave Interface */
struct usb_interface_descriptor data_class_interface;
struct usb_endpoint_descriptor data_endpoints[NUM_ENDPOINTS-1];
} __attribute__((packed));
static struct acm_config_desc acm_configuration_descriptors[NUM_CONFIGS] = {
{
.configuration_desc ={
.bLength =
sizeof(struct usb_configuration_descriptor),
.bDescriptorType = USB_DT_CONFIG,
.wTotalLength =
cpu_to_le16(sizeof(struct acm_config_desc)),
.bNumInterfaces = NUM_ACM_INTERFACES,
.bConfigurationValue = 1,
.iConfiguration = STR_CONFIG,
.bmAttributes =
BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED,
.bMaxPower = USBTTY_MAXPOWER
},
/* Interface 1 */
.interface_desc = {
.bLength = sizeof(struct usb_interface_descriptor),
.bDescriptorType = USB_DT_INTERFACE,
.bInterfaceNumber = 0,
.bAlternateSetting = 0,
.bNumEndpoints = 0x01,
.bInterfaceClass =
COMMUNICATIONS_INTERFACE_CLASS_CONTROL,
.bInterfaceSubClass = COMMUNICATIONS_ACM_SUBCLASS,
.bInterfaceProtocol = COMMUNICATIONS_V25TER_PROTOCOL,
.iInterface = STR_CTRL_INTERFACE,
},
.usb_class_header = {
.bFunctionLength =
sizeof(struct usb_class_header_function_descriptor),
.bDescriptorType = CS_INTERFACE,
.bDescriptorSubtype = USB_ST_HEADER,
.bcdCDC = cpu_to_le16(110),
},
.usb_class_call_mgt = {
.bFunctionLength =
sizeof(struct usb_class_call_management_descriptor),
.bDescriptorType = CS_INTERFACE,
.bDescriptorSubtype = USB_ST_CMF,
.bmCapabilities = 0x00,
.bDataInterface = 0x01,
},
.usb_class_acm = {
.bFunctionLength =
sizeof(struct usb_class_abstract_control_descriptor),
.bDescriptorType = CS_INTERFACE,
.bDescriptorSubtype = USB_ST_ACMF,
.bmCapabilities = 0x00,
},
.usb_class_union = {
.bFunctionLength =
sizeof(struct usb_class_union_function_descriptor),
.bDescriptorType = CS_INTERFACE,
.bDescriptorSubtype = USB_ST_UF,
.bMasterInterface = 0x00,
.bSlaveInterface0 = 0x01,
},
.notification_endpoint = {
.bLength =
sizeof(struct usb_endpoint_descriptor),
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = UDC_INT_ENDPOINT | USB_DIR_IN,
.bmAttributes = USB_ENDPOINT_XFER_INT,
.wMaxPacketSize
= cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
.bInterval = 0xFF,
},
/* Interface 2 */
.data_class_interface = {
.bLength =
sizeof(struct usb_interface_descriptor),
.bDescriptorType = USB_DT_INTERFACE,
.bInterfaceNumber = 0x01,
.bAlternateSetting = 0x00,
.bNumEndpoints = 0x02,
.bInterfaceClass =
COMMUNICATIONS_INTERFACE_CLASS_DATA,
.bInterfaceSubClass = DATA_INTERFACE_SUBCLASS_NONE,
.bInterfaceProtocol = DATA_INTERFACE_PROTOCOL_NONE,
.iInterface = STR_DATA_INTERFACE,
},
.data_endpoints = {
{
.bLength =
sizeof(struct usb_endpoint_descriptor),
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = UDC_OUT_ENDPOINT | USB_DIR_OUT,
.bmAttributes =
USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize =
cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
.bInterval = 0xFF,
},
{
.bLength =
sizeof(struct usb_endpoint_descriptor),
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = UDC_IN_ENDPOINT | USB_DIR_IN,
.bmAttributes =
USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize =
cpu_to_le16(CONFIG_USBD_SERIAL_BULK_PKTSIZE),
.bInterval = 0xFF,
},
},
},
};
static struct rs232_emu rs232_desc={
.dter = 115200,
.stop_bits = 0x00,
.parity = 0x00,
.data_bits = 0x08
};
/*
* Static Generic Serial specific data
*/
struct gserial_config_desc {
struct usb_configuration_descriptor configuration_desc;
struct usb_interface_descriptor interface_desc[NUM_GSERIAL_INTERFACES];
struct usb_endpoint_descriptor data_endpoints[NUM_ENDPOINTS];
} __attribute__((packed));
static struct gserial_config_desc
gserial_configuration_descriptors[NUM_CONFIGS] ={
{
.configuration_desc ={
.bLength = sizeof(struct usb_configuration_descriptor),
.bDescriptorType = USB_DT_CONFIG,
.wTotalLength =
cpu_to_le16(sizeof(struct gserial_config_desc)),
.bNumInterfaces = NUM_GSERIAL_INTERFACES,
.bConfigurationValue = 1,
.iConfiguration = STR_CONFIG,
.bmAttributes =
BMATTRIBUTE_SELF_POWERED|BMATTRIBUTE_RESERVED,
.bMaxPower = USBTTY_MAXPOWER
},
.interface_desc = {
{
.bLength =
sizeof(struct usb_interface_descriptor),
.bDescriptorType = USB_DT_INTERFACE,
.bInterfaceNumber = 0,
.bAlternateSetting = 0,
.bNumEndpoints = NUM_ENDPOINTS,
.bInterfaceClass =
COMMUNICATIONS_INTERFACE_CLASS_VENDOR,
.bInterfaceSubClass =
COMMUNICATIONS_NO_SUBCLASS,
.bInterfaceProtocol =
COMMUNICATIONS_NO_PROTOCOL,
.iInterface = STR_DATA_INTERFACE
},
},
.data_endpoints = {
{
.bLength =
sizeof(struct usb_endpoint_descriptor),
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = UDC_OUT_ENDPOINT | USB_DIR_OUT,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize =
cpu_to_le16(CONFIG_USBD_SERIAL_OUT_PKTSIZE),
.bInterval= 0xFF,
},
{
.bLength =
sizeof(struct usb_endpoint_descriptor),
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = UDC_IN_ENDPOINT | USB_DIR_IN,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize =
cpu_to_le16(CONFIG_USBD_SERIAL_IN_PKTSIZE),
.bInterval = 0xFF,
},
{
.bLength =
sizeof(struct usb_endpoint_descriptor),
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = UDC_INT_ENDPOINT | USB_DIR_IN,
.bmAttributes = USB_ENDPOINT_XFER_INT,
.wMaxPacketSize =
cpu_to_le16(CONFIG_USBD_SERIAL_INT_PKTSIZE),
.bInterval = 0xFF,
},
},
},
};
/*
* Static Function Prototypes
*/
static void usbtty_init_strings (void);
static void usbtty_init_instances (void);
static void usbtty_init_endpoints (void);
static void usbtty_init_terminal_type(short type);
static void usbtty_event_handler (struct usb_device_instance *device,
usb_device_event_t event, int data);
static int usbtty_cdc_setup(struct usb_device_request *request,
struct urb *urb);
static int usbtty_configured (void);
static int write_buffer (circbuf_t * buf);
static int fill_buffer (circbuf_t * buf);
void usbtty_poll (void);
/* utility function for converting char* to wide string used by USB */
static void str2wide (char *str, u16 * wide)
{
int i;
for (i = 0; i < strlen (str) && str[i]; i++){
#if defined(__LITTLE_ENDIAN)
wide[i] = (u16) str[i];
#elif defined(__BIG_ENDIAN)
wide[i] = ((u16)(str[i])<<8);
#else
#error "__LITTLE_ENDIAN or __BIG_ENDIAN undefined"
#endif
}
}
/*
* Test whether a character is in the RX buffer
*/
int usbtty_tstc (void)
{
struct usb_endpoint_instance *endpoint =
&endpoint_instance[rx_endpoint];
/* If no input data exists, allow more RX to be accepted */
if(usbtty_input.size <= 0){
udc_unset_nak(endpoint->endpoint_address&0x03);
}
usbtty_poll ();
return (usbtty_input.size > 0);
}
/*
* Read a single byte from the usb client port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int usbtty_getc (void)
{
char c;
struct usb_endpoint_instance *endpoint =
&endpoint_instance[rx_endpoint];
while (usbtty_input.size <= 0) {
udc_unset_nak(endpoint->endpoint_address&0x03);
usbtty_poll ();
}
buf_pop (&usbtty_input, &c, 1);
udc_set_nak(endpoint->endpoint_address&0x03);
return c;
}
/*
* Output a single byte to the usb client port.
*/
void usbtty_putc (const char c)
{
if (!usbtty_configured ())
return;
buf_push (&usbtty_output, &c, 1);
/* If \n, also do \r */
if (c == '\n')
buf_push (&usbtty_output, "\r", 1);
/* Poll at end to handle new data... */
if ((usbtty_output.size + 2) >= usbtty_output.totalsize) {
usbtty_poll ();
}
}
/* usbtty_puts() helper function for finding the next '\n' in a string */
static int next_nl_pos (const char *s)
{
int i;
for (i = 0; s[i] != '\0'; i++) {
if (s[i] == '\n')
return i;
}
return i;
}
/*
* Output a string to the usb client port - implementing flow control
*/
static void __usbtty_puts (const char *str, int len)
{
int maxlen = usbtty_output.totalsize;
int space, n;
/* break str into chunks < buffer size, if needed */
while (len > 0) {
usbtty_poll ();
space = maxlen - usbtty_output.size;
/* Empty buffer here, if needed, to ensure space... */
if (space) {
write_buffer (&usbtty_output);
n = MIN (space, MIN (len, maxlen));
buf_push (&usbtty_output, str, n);
str += n;
len -= n;
}
}
}
void usbtty_puts (const char *str)
{
int n;
int len;
if (!usbtty_configured ())
return;
len = strlen (str);
/* add '\r' for each '\n' */
while (len > 0) {
n = next_nl_pos (str);
if (str[n] == '\n') {
__usbtty_puts (str, n + 1);
__usbtty_puts ("\r", 1);
str += (n + 1);
len -= (n + 1);
} else {
/* No \n found. All done. */
__usbtty_puts (str, n);
break;
}
}
/* Poll at end to handle new data... */
usbtty_poll ();
}
/*
* Initialize the usb client port.
*
*/
int drv_usbtty_init (void)
{
int rc;
char * sn;
char * tt;
int snlen;
/* Ger seiral number */
if (!(sn = getenv("serial#"))) {
sn = "000000000000";
}
snlen = strlen(sn);
if (snlen > sizeof(serial_number) - 1) {
printf ("Warning: serial number %s is too long (%d > %lu)\n",
sn, snlen, (ulong)(sizeof(serial_number) - 1));
snlen = sizeof(serial_number) - 1;
}
memcpy (serial_number, sn, snlen);
serial_number[snlen] = '\0';
/* Decide on which type of UDC device to be.
*/
if(!(tt = getenv("usbtty"))) {
tt = "generic";
}
usbtty_init_terminal_type(strcmp(tt,"cdc_acm"));
/* prepare buffers... */
buf_init (&usbtty_input, USBTTY_BUFFER_SIZE);
buf_init (&usbtty_output, USBTTY_BUFFER_SIZE);
/* Now, set up USB controller and infrastructure */
udc_init (); /* Basic USB initialization */
usbtty_init_strings ();
usbtty_init_instances ();
usbtty_init_endpoints ();
udc_startup_events (device_instance);/* Enable dev, init udc pointers */
udc_connect (); /* Enable pullup for host detection */
/* Device initialization */
memset (&usbttydev, 0, sizeof (usbttydev));
strcpy (usbttydev.name, "usbtty");
usbttydev.ext = 0; /* No extensions */
usbttydev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT;
usbttydev.tstc = usbtty_tstc; /* 'tstc' function */
usbttydev.getc = usbtty_getc; /* 'getc' function */
usbttydev.putc = usbtty_putc; /* 'putc' function */
usbttydev.puts = usbtty_puts; /* 'puts' function */
rc = stdio_register (&usbttydev);
return (rc == 0) ? 1 : rc;
}
static void usbtty_init_strings (void)
{
struct usb_string_descriptor *string;
usbtty_string_table[STR_LANG] =
(struct usb_string_descriptor*)wstrLang;
string = (struct usb_string_descriptor *) wstrManufacturer;
string->bLength = sizeof(wstrManufacturer);
string->bDescriptorType = USB_DT_STRING;
str2wide (CONFIG_USBD_MANUFACTURER, string->wData);
usbtty_string_table[STR_MANUFACTURER]=string;
string = (struct usb_string_descriptor *) wstrProduct;
string->bLength = sizeof(wstrProduct);
string->bDescriptorType = USB_DT_STRING;
str2wide (CONFIG_USBD_PRODUCT_NAME, string->wData);
usbtty_string_table[STR_PRODUCT]=string;
string = (struct usb_string_descriptor *) wstrSerial;
string->bLength = sizeof(serial_number);
string->bDescriptorType = USB_DT_STRING;
str2wide (serial_number, string->wData);
usbtty_string_table[STR_SERIAL]=string;
string = (struct usb_string_descriptor *) wstrConfiguration;
string->bLength = sizeof(wstrConfiguration);
string->bDescriptorType = USB_DT_STRING;
str2wide (CONFIG_USBD_CONFIGURATION_STR, string->wData);
usbtty_string_table[STR_CONFIG]=string;
string = (struct usb_string_descriptor *) wstrDataInterface;
string->bLength = sizeof(wstrDataInterface);
string->bDescriptorType = USB_DT_STRING;
str2wide (CONFIG_USBD_DATA_INTERFACE_STR, string->wData);
usbtty_string_table[STR_DATA_INTERFACE]=string;
string = (struct usb_string_descriptor *) wstrCtrlInterface;
string->bLength = sizeof(wstrCtrlInterface);
string->bDescriptorType = USB_DT_STRING;
str2wide (CONFIG_USBD_CTRL_INTERFACE_STR, string->wData);
usbtty_string_table[STR_CTRL_INTERFACE]=string;
/* Now, initialize the string table for ep0 handling */
usb_strings = usbtty_string_table;
}
#define init_wMaxPacketSize(x) le16_to_cpu(get_unaligned(\
&ep_descriptor_ptrs[(x) - 1]->wMaxPacketSize));
static void usbtty_init_instances (void)
{
int i;
/* initialize device instance */
memset (device_instance, 0, sizeof (struct usb_device_instance));
device_instance->device_state = STATE_INIT;
device_instance->device_descriptor = &device_descriptor;
device_instance->event = usbtty_event_handler;
device_instance->cdc_recv_setup = usbtty_cdc_setup;
device_instance->bus = bus_instance;
device_instance->configurations = NUM_CONFIGS;
device_instance->configuration_instance_array = config_instance;
/* initialize bus instance */
memset (bus_instance, 0, sizeof (struct usb_bus_instance));
bus_instance->device = device_instance;
bus_instance->endpoint_array = endpoint_instance;
bus_instance->max_endpoints = 1;
bus_instance->maxpacketsize = 64;
bus_instance->serial_number_str = serial_number;
/* configuration instance */
memset (config_instance, 0,
sizeof (struct usb_configuration_instance));
config_instance->interfaces = interface_count;
config_instance->configuration_descriptor = configuration_descriptor;
config_instance->interface_instance_array = interface_instance;
/* interface instance */
memset (interface_instance, 0,
sizeof (struct usb_interface_instance));
interface_instance->alternates = 1;
interface_instance->alternates_instance_array = alternate_instance;
/* alternates instance */
memset (alternate_instance, 0,
sizeof (struct usb_alternate_instance));
alternate_instance->interface_descriptor = interface_descriptors;
alternate_instance->endpoints = NUM_ENDPOINTS;
alternate_instance->endpoints_descriptor_array = ep_descriptor_ptrs;
/* endpoint instances */
memset (&endpoint_instance[0], 0,
sizeof (struct usb_endpoint_instance));
endpoint_instance[0].endpoint_address = 0;
endpoint_instance[0].rcv_packetSize = EP0_MAX_PACKET_SIZE;
endpoint_instance[0].rcv_attributes = USB_ENDPOINT_XFER_CONTROL;
endpoint_instance[0].tx_packetSize = EP0_MAX_PACKET_SIZE;
endpoint_instance[0].tx_attributes = USB_ENDPOINT_XFER_CONTROL;
udc_setup_ep (device_instance, 0, &endpoint_instance[0]);
for (i = 1; i <= NUM_ENDPOINTS; i++) {
memset (&endpoint_instance[i], 0,
sizeof (struct usb_endpoint_instance));
endpoint_instance[i].endpoint_address =
ep_descriptor_ptrs[i - 1]->bEndpointAddress;
endpoint_instance[i].rcv_attributes =
ep_descriptor_ptrs[i - 1]->bmAttributes;
endpoint_instance[i].rcv_packetSize = init_wMaxPacketSize(i);
endpoint_instance[i].tx_attributes =
ep_descriptor_ptrs[i - 1]->bmAttributes;
endpoint_instance[i].tx_packetSize = init_wMaxPacketSize(i);
endpoint_instance[i].tx_attributes =
ep_descriptor_ptrs[i - 1]->bmAttributes;
urb_link_init (&endpoint_instance[i].rcv);
urb_link_init (&endpoint_instance[i].rdy);
urb_link_init (&endpoint_instance[i].tx);
urb_link_init (&endpoint_instance[i].done);
if (endpoint_instance[i].endpoint_address & USB_DIR_IN)
endpoint_instance[i].tx_urb =
usbd_alloc_urb (device_instance,
&endpoint_instance[i]);
else
endpoint_instance[i].rcv_urb =
usbd_alloc_urb (device_instance,
&endpoint_instance[i]);
}
}
static void usbtty_init_endpoints (void)
{
int i;
bus_instance->max_endpoints = NUM_ENDPOINTS + 1;
for (i = 1; i <= NUM_ENDPOINTS; i++) {
udc_setup_ep (device_instance, i, &endpoint_instance[i]);
}
}
/* usbtty_init_terminal_type
*
* Do some late binding for our device type.
*/
static void usbtty_init_terminal_type(short type)
{
switch(type){
/* CDC ACM */
case 0:
/* Assign endpoint descriptors */
ep_descriptor_ptrs[0] =
&acm_configuration_descriptors[0].notification_endpoint;
ep_descriptor_ptrs[1] =
&acm_configuration_descriptors[0].data_endpoints[0];
ep_descriptor_ptrs[2] =
&acm_configuration_descriptors[0].data_endpoints[1];
/* Enumerate Device Descriptor */
device_descriptor.bDeviceClass =
COMMUNICATIONS_DEVICE_CLASS;
device_descriptor.idProduct =
cpu_to_le16(CONFIG_USBD_PRODUCTID_CDCACM);
/* Assign endpoint indices */
tx_endpoint = ACM_TX_ENDPOINT;
rx_endpoint = ACM_RX_ENDPOINT;
/* Configuration Descriptor */
configuration_descriptor =
(struct usb_configuration_descriptor*)
&acm_configuration_descriptors;
/* Interface count */
interface_count = NUM_ACM_INTERFACES;
break;
/* BULK IN/OUT & Default */
case 1:
default:
/* Assign endpoint descriptors */
ep_descriptor_ptrs[0] =
&gserial_configuration_descriptors[0].data_endpoints[0];
ep_descriptor_ptrs[1] =
&gserial_configuration_descriptors[0].data_endpoints[1];
ep_descriptor_ptrs[2] =
&gserial_configuration_descriptors[0].data_endpoints[2];
/* Enumerate Device Descriptor */
device_descriptor.bDeviceClass = 0xFF;
device_descriptor.idProduct =
cpu_to_le16(CONFIG_USBD_PRODUCTID_GSERIAL);
/* Assign endpoint indices */
tx_endpoint = GSERIAL_TX_ENDPOINT;
rx_endpoint = GSERIAL_RX_ENDPOINT;
/* Configuration Descriptor */
configuration_descriptor =
(struct usb_configuration_descriptor*)
&gserial_configuration_descriptors;
/* Interface count */
interface_count = NUM_GSERIAL_INTERFACES;
break;
}
}
/******************************************************************************/
static struct urb *next_urb (struct usb_device_instance *device,
struct usb_endpoint_instance *endpoint)
{
struct urb *current_urb = NULL;
int space;
/* If there's a queue, then we should add to the last urb */
if (!endpoint->tx_queue) {
current_urb = endpoint->tx_urb;
} else {
/* Last urb from tx chain */
current_urb =
p2surround (struct urb, link, endpoint->tx.prev);
}
/* Make sure this one has enough room */
space = current_urb->buffer_length - current_urb->actual_length;
if (space > 0) {
return current_urb;
} else { /* No space here */
/* First look at done list */
current_urb = first_urb_detached (&endpoint->done);
if (!current_urb) {
current_urb = usbd_alloc_urb (device, endpoint);
}
urb_append (&endpoint->tx, current_urb);
endpoint->tx_queue++;
}
return current_urb;
}
static int write_buffer (circbuf_t * buf)
{
if (!usbtty_configured ()) {
return 0;
}
struct usb_endpoint_instance *endpoint =
&endpoint_instance[tx_endpoint];
struct urb *current_urb = NULL;
current_urb = next_urb (device_instance, endpoint);
/* TX data still exists - send it now
*/
if(endpoint->sent < current_urb->actual_length){
if(udc_endpoint_write (endpoint)){
/* Write pre-empted by RX */
return -1;
}
}
if (buf->size) {
char *dest;
int space_avail;
int popnum, popped;
int total = 0;
/* Break buffer into urb sized pieces,
* and link each to the endpoint
*/
while (buf->size > 0) {
if (!current_urb) {
TTYERR ("current_urb is NULL, buf->size %d\n",
buf->size);
return total;
}
dest = (char*)current_urb->buffer +
current_urb->actual_length;
space_avail =
current_urb->buffer_length -
current_urb->actual_length;
popnum = MIN (space_avail, buf->size);
if (popnum == 0)
break;
popped = buf_pop (buf, dest, popnum);
if (popped == 0)
break;
current_urb->actual_length += popped;
total += popped;
/* If endpoint->last == 0, then transfers have
* not started on this endpoint
*/
if (endpoint->last == 0) {
if(udc_endpoint_write (endpoint)){
/* Write pre-empted by RX */
return -1;
}
}
}/* end while */
return total;
}
return 0;
}
static int fill_buffer (circbuf_t * buf)
{
struct usb_endpoint_instance *endpoint =
&endpoint_instance[rx_endpoint];
if (endpoint->rcv_urb && endpoint->rcv_urb->actual_length) {
unsigned int nb = 0;
char *src = (char *) endpoint->rcv_urb->buffer;
unsigned int rx_avail = buf->totalsize - buf->size;
if(rx_avail >= endpoint->rcv_urb->actual_length){
nb = endpoint->rcv_urb->actual_length;
buf_push (buf, src, nb);
endpoint->rcv_urb->actual_length = 0;
}
return nb;
}
return 0;
}
static int usbtty_configured (void)
{
return usbtty_configured_flag;
}
/******************************************************************************/
static void usbtty_event_handler (struct usb_device_instance *device,
usb_device_event_t event, int data)
{
switch (event) {
case DEVICE_RESET:
case DEVICE_BUS_INACTIVE:
usbtty_configured_flag = 0;
break;
case DEVICE_CONFIGURED:
usbtty_configured_flag = 1;
break;
case DEVICE_ADDRESS_ASSIGNED:
usbtty_init_endpoints ();
default:
break;
}
}
/******************************************************************************/
int usbtty_cdc_setup(struct usb_device_request *request, struct urb *urb)
{
switch (request->bRequest){
case ACM_SET_CONTROL_LINE_STATE: /* Implies DTE ready */
break;
case ACM_SEND_ENCAPSULATED_COMMAND : /* Required */
break;
case ACM_SET_LINE_ENCODING : /* DTE stop/parity bits
* per character */
break;
case ACM_GET_ENCAPSULATED_RESPONSE : /* request response */
break;
case ACM_GET_LINE_ENCODING : /* request DTE rate,
* stop/parity bits */
memcpy (urb->buffer , &rs232_desc, sizeof(rs232_desc));
urb->actual_length = sizeof(rs232_desc);
break;
default:
return 1;
}
return 0;
}
/******************************************************************************/
/*
* Since interrupt handling has not yet been implemented, we use this function
* to handle polling. This is called by the tstc,getc,putc,puts routines to
* update the USB state.
*/
void usbtty_poll (void)
{
/* New interrupts? */
udc_irq();
/* Write any output data to host buffer
* (do this before checking interrupts to avoid missing one)
*/
if (usbtty_configured ()) {
write_buffer (&usbtty_output);
}
/* New interrupts? */
udc_irq();
/* Check for new data from host..
* (do this after checking interrupts to get latest data)
*/
if (usbtty_configured ()) {
fill_buffer (&usbtty_input);
}
/* New interrupts? */
udc_irq();
}
|
1001-study-uboot
|
drivers/serial/usbtty.c
|
C
|
gpl3
| 27,155
|
/*
* SuperH SCIF device driver.
* Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
* Copyright (C) 2002 - 2008 Paul Mundt
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#include "serial_sh.h"
#if defined(CONFIG_CONS_SCIF0)
# define SCIF_BASE SCIF0_BASE
#elif defined(CONFIG_CONS_SCIF1)
# define SCIF_BASE SCIF1_BASE
#elif defined(CONFIG_CONS_SCIF2)
# define SCIF_BASE SCIF2_BASE
#elif defined(CONFIG_CONS_SCIF3)
# define SCIF_BASE SCIF3_BASE
#elif defined(CONFIG_CONS_SCIF4)
# define SCIF_BASE SCIF4_BASE
#elif defined(CONFIG_CONS_SCIF5)
# define SCIF_BASE SCIF5_BASE
#else
# error "Default SCIF doesn't set....."
#endif
#if defined(CONFIG_SCIF_A)
#define SCIF_BASE_PORT PORT_SCIFA
#else
#define SCIF_BASE_PORT PORT_SCIF
#endif
static struct uart_port sh_sci = {
.membase = (unsigned char*)SCIF_BASE,
.mapbase = SCIF_BASE,
.type = SCIF_BASE_PORT,
};
void serial_setbrg(void)
{
DECLARE_GLOBAL_DATA_PTR;
sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ));
}
int serial_init(void)
{
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
sci_out(&sh_sci, SCSMR, 0);
sci_out(&sh_sci, SCSMR, 0);
sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
sci_in(&sh_sci, SCFCR);
sci_out(&sh_sci, SCFCR, 0);
serial_setbrg();
return 0;
}
#if defined(CONFIG_CPU_SH7760) || \
defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)
static int scif_rxfill(struct uart_port *port)
{
return sci_in(port, SCRFDR) & 0xff;
}
#elif defined(CONFIG_CPU_SH7763)
static int scif_rxfill(struct uart_port *port)
{
if ((port->mapbase == 0xffe00000) ||
(port->mapbase == 0xffe08000)) {
/* SCIF0/1*/
return sci_in(port, SCRFDR) & 0xff;
} else {
/* SCIF2 */
return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
}
}
#elif defined(CONFIG_ARCH_SH7372)
static int scif_rxfill(struct uart_port *port)
{
if (port->type == PORT_SCIFA)
return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
else
return sci_in(port, SCRFDR);
}
#else
static int scif_rxfill(struct uart_port *port)
{
return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
}
#endif
static int serial_rx_fifo_level(void)
{
return scif_rxfill(&sh_sci);
}
void serial_raw_putc(const char c)
{
while (1) {
/* Tx fifo is empty */
if (sci_in(&sh_sci, SCxSR) & SCxSR_TEND(&sh_sci))
break;
}
sci_out(&sh_sci, SCxTDR, c);
sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci));
}
void serial_putc(const char c)
{
if (c == '\n')
serial_raw_putc('\r');
serial_raw_putc(c);
}
void serial_puts(const char *s)
{
char c;
while ((c = *s++) != 0)
serial_putc(c);
}
int serial_tstc(void)
{
return serial_rx_fifo_level() ? 1 : 0;
}
void handle_error(void)
{
sci_in(&sh_sci, SCxSR);
sci_out(&sh_sci, SCxSR, SCxSR_ERROR_CLEAR(&sh_sci));
sci_in(&sh_sci, SCLSR);
sci_out(&sh_sci, SCLSR, 0x00);
}
int serial_getc_check(void)
{
unsigned short status;
status = sci_in(&sh_sci, SCxSR);
if (status & SCIF_ERRORS)
handle_error();
if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
handle_error();
return status & (SCIF_DR | SCxSR_RDxF(&sh_sci));
}
int serial_getc(void)
{
unsigned short status;
char ch;
while (!serial_getc_check())
;
ch = sci_in(&sh_sci, SCxRDR);
status = sci_in(&sh_sci, SCxSR);
sci_out(&sh_sci, SCxSR, SCxSR_RDxF_CLEAR(&sh_sci));
if (status & SCIF_ERRORS)
handle_error();
if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci))
handle_error();
return ch;
}
|
1001-study-uboot
|
drivers/serial/serial_sh.c
|
C
|
gpl3
| 4,203
|
/*
* (C) Copyright 2004
* DAVE Srl
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
/* flush serial input queue. returns 0 on success or negative error
* number otherwise
*/
static int serial_flush_input(void)
{
volatile u32 tmp;
/* keep on reading as long as the receiver is not empty */
while(UTRSTAT0&0x01) {
tmp = REGB(URXH0);
}
return 0;
}
/* flush output queue. returns 0 on success or negative error number
* otherwise
*/
static int serial_flush_output(void)
{
/* wait until the transmitter is no longer busy */
while(!(UTRSTAT0 & 0x02)) {
}
return 0;
}
void serial_setbrg (void)
{
u32 divisor = 0;
/* get correct divisor */
switch(gd->baudrate) {
case 1200:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
divisor = 3124;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
divisor = 3905;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif
break;
case 9600:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
divisor = 390;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
divisor = 487;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif
break;
case 19200:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
divisor = 194;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
divisor = 243;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif
break;
case 38400:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
divisor = 97;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
divisor = 121;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif /* break; */
case 57600:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
divisor = 64;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
divisor = 80;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif /* break; */
case 115200:
#if CONFIG_S3C44B0_CLOCK_SPEED==66
divisor = 32;
#elif CONFIG_S3C44B0_CLOCK_SPEED==75
divisor = 40;
#else
# error CONFIG_S3C44B0_CLOCK_SPEED undefined
#endif /* break; */
}
serial_flush_output();
serial_flush_input();
UFCON0 = 0x0;
ULCON0 = 0x03;
UCON0 = 0x05;
UBRDIV0 = divisor;
UFCON1 = 0x0;
ULCON1 = 0x03;
UCON1 = 0x05;
UBRDIV1 = divisor;
for(divisor=0; divisor<100; divisor++) {
/* NOP */
}
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
serial_setbrg ();
return (0);
}
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
{
/* wait for room in the transmit FIFO */
while(!(UTRSTAT0 & 0x02));
UTXH0 = (unsigned char)c;
/*
to be polite with serial console add a line feed
to the carriage return character
*/
if (c=='\n')
serial_putc('\r');
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_tstc (void)
{
return (UTRSTAT0 & 0x01);
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc (void)
{
int rv;
for(;;) {
rv = serial_tstc();
if(rv > 0)
return URXH0;
}
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
|
1001-study-uboot
|
drivers/serial/serial_s3c44b0.c
|
C
|
gpl3
| 4,377
|
/*
* Serial Port stuff - taken from Linux
*
* (C) Copyright 2002
* MAZeT GmbH <www.mazet.de>
* Stephan Linz <linz@mazet.de>, <linz@li-pro.net>
*
* (c) 2004
* IMMS gGmbH <www.imms.de>
* Thomas Elste <info@elste.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
#if !defined(CONFIG_NETARM_NS7520)
#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
#else
#define PORTC (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTC))
#endif
/* wait until transmitter is ready for another character */
#define TXWAITRDY(registers) \
{ \
ulong tmo = get_timer(0) + 1 * CONFIG_SYS_HZ; \
while (((registers)->status_a & NETARM_SER_STATA_TX_RDY) == 0 ) { \
if (get_timer(0) > tmo) \
break; \
} \
}
volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0);
volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1);
extern void _netarm_led_FAIL1(void);
/*
* Setup both serial i/f with given baudrate
*/
void serial_setbrg (void)
{
/* set 0 ... make sure pins are configured for serial */
#if !defined(CONFIG_NETARM_NS7520)
PORTA = PORTB =
NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
#else
PORTA = NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
PORTC = NETARM_GEN_PORT_CSF (0xef) | NETARM_GEN_PORT_MODE (0xef) | NETARM_GEN_PORT_DIR (0xe0);
#endif
/* first turn em off */
serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a = 0;
/* clear match register, we don't need it */
serial_reg_ch1->rx_match = serial_reg_ch2->rx_match = 0;
/* setup bit rate generator and rx buffer gap timer (1 byte only) */
if ((gd->baudrate >= MIN_BAUD_RATE)
&& (gd->baudrate <= MAX_BAUD_RATE)) {
serial_reg_ch1->bitrate = serial_reg_ch2->bitrate =
NETARM_SER_BR_X16 (gd->baudrate);
serial_reg_ch1->rx_buf_timer = serial_reg_ch2->rx_buf_timer =
0;
serial_reg_ch1->rx_char_timer = serial_reg_ch2->rx_char_timer =
NETARM_SER_RXGAP (gd->baudrate);
} else {
hang ();
}
/* setup port mode */
serial_reg_ch1->ctrl_b = serial_reg_ch2->ctrl_b =
( NETARM_SER_CTLB_RCGT_EN |
NETARM_SER_CTLB_UART_MODE);
serial_reg_ch1->ctrl_a = serial_reg_ch2->ctrl_a =
( NETARM_SER_CTLA_ENABLE |
NETARM_SER_CTLA_P_NONE |
/* see errata */
NETARM_SER_CTLA_2STOP |
NETARM_SER_CTLA_8BITS |
NETARM_SER_CTLA_DTR_EN |
NETARM_SER_CTLA_RTS_EN);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
int serial_init (void)
{
serial_setbrg ();
return 0;
}
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
{
volatile unsigned char *fifo;
/* If \n, also do \r */
if (c == '\n')
serial_putc ('\r');
fifo = (volatile unsigned char *) &(serial_reg_ch1->fifo);
TXWAITRDY (serial_reg_ch1);
*fifo = c;
}
/*
* Test of a single byte from the serial port. Returns 1 on success, 0
* otherwise.
*/
int serial_tstc(void)
{
return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY;
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise.
*/
int serial_getc (void)
{
unsigned int ch_uint;
volatile unsigned int *fifo;
volatile unsigned char *fifo_char = NULL;
int buf_count = 0;
while (!(serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY))
/* NOP */ ;
fifo = (volatile unsigned int *) &(serial_reg_ch1->fifo);
fifo_char = (unsigned char *) &ch_uint;
ch_uint = *fifo;
buf_count = NETARM_SER_STATA_RXFDB (serial_reg_ch1->status_a);
switch (buf_count) {
case NETARM_SER_STATA_RXFDB_4BYTES:
buf_count = 4;
break;
case NETARM_SER_STATA_RXFDB_3BYTES:
buf_count = 3;
break;
case NETARM_SER_STATA_RXFDB_2BYTES:
buf_count = 2;
break;
case NETARM_SER_STATA_RXFDB_1BYTES:
buf_count = 1;
break;
default:
/* panic, be never here */
break;
}
serial_reg_ch1->status_a |= NETARM_SER_STATA_RX_CLOSED;
return ch_uint & 0xff;
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
|
1001-study-uboot
|
drivers/serial/serial_netarm.c
|
C
|
gpl3
| 4,969
|
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <lh7a40x.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CONSOLE_UART1)
# define UART_CONSOLE 1
#elif defined(CONFIG_CONSOLE_UART2)
# define UART_CONSOLE 2
#elif defined(CONFIG_CONSOLE_UART3)
# define UART_CONSOLE 3
#else
# error "No console configured ... "
#endif
void serial_setbrg (void)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
int i;
unsigned int reg = 0;
/*
* userguide 15.1.2.4
*
* BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1
*
* UART_REF_FREQ = external system clock input / 2 (Hz)
* BAUD is desired baudrate (bits/s)
*
* NOTE: we add (divisor/2) to numerator to round for
* more precision
*/
reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1;
uart->brcon = reg;
for (i = 0; i < 100; i++);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
/* UART must be enabled before writing to any config registers */
uart->con |= (UART_EN);
#ifdef CONFIG_CONSOLE_UART1
/* infrared disabled */
uart->con |= UART_SIRD;
#endif
/* loopback disabled */
uart->con &= ~(UART_LBE);
/* modem lines and tx/rx polarities */
uart->con &= ~(UART_MXP | UART_TXP | UART_RXP);
/* FIFO enable, N81 */
uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1);
/* set baudrate */
serial_setbrg ();
/* enable rx interrupt */
uart->inten |= UART_RI;
return (0);
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc (void)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
/* wait for character to arrive */
while (uart->status & UART_RXFE);
return(uart->data & 0xff);
}
#ifdef CONFIG_HWFLOW
static int hwflow = 0; /* turned off by default */
int hwflow_onoff(int on)
{
switch(on) {
case 0:
default:
break; /* return current */
case 1:
hwflow = 1; /* turn on */
break;
case -1:
hwflow = 0; /* turn off */
break;
}
return hwflow;
}
#endif
#ifdef CONFIG_MODEM_SUPPORT
static int be_quiet = 0;
void disable_putc(void)
{
be_quiet = 1;
}
void enable_putc(void)
{
be_quiet = 0;
}
#endif
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
#ifdef CONFIG_MODEM_SUPPORT
if (be_quiet)
return;
#endif
/* wait for room in the tx FIFO */
while (!(uart->status & UART_TXFE));
#ifdef CONFIG_HWFLOW
/* Wait for CTS up */
while(hwflow && !(uart->status & UART_CTS));
#endif
uart->data = c;
/* If \n, also do \r */
if (c == '\n')
serial_putc ('\r');
}
/*
* Test whether a character is in the RX buffer
*/
int serial_tstc (void)
{
lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
return(!(uart->status & UART_RXFE));
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
|
1001-study-uboot
|
drivers/serial/serial_lh7a40x.c
|
C
|
gpl3
| 3,869
|
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <linux/compiler.h>
#include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SERIAL1
#define UART_NR S3C24X0_UART0
#elif defined(CONFIG_SERIAL2)
#define UART_NR S3C24X0_UART1
#elif defined(CONFIG_SERIAL3)
#define UART_NR S3C24X0_UART2
#else
#error "Bad: you didn't configure serial ..."
#endif
#include <asm/io.h>
#if defined(CONFIG_SERIAL_MULTI)
#include <serial.h>
/* Multi serial device functions */
#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \
int s3serial##port##_init(void) \
{ \
return serial_init_dev(port); \
} \
void s3serial##port##_setbrg(void) \
{ \
serial_setbrg_dev(port); \
} \
int s3serial##port##_getc(void) \
{ \
return serial_getc_dev(port); \
} \
int s3serial##port##_tstc(void) \
{ \
return serial_tstc_dev(port); \
} \
void s3serial##port##_putc(const char c) \
{ \
serial_putc_dev(port, c); \
} \
void s3serial##port##_puts(const char *s) \
{ \
serial_puts_dev(port, s); \
}
#define INIT_S3C_SERIAL_STRUCTURE(port, name) { \
name, \
s3serial##port##_init, \
NULL,\
s3serial##port##_setbrg, \
s3serial##port##_getc, \
s3serial##port##_tstc, \
s3serial##port##_putc, \
s3serial##port##_puts, \
}
#endif /* CONFIG_SERIAL_MULTI */
#ifdef CONFIG_HWFLOW
static int hwflow;
#endif
void _serial_setbrg(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
unsigned int reg = 0;
int i;
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
writel(reg, &uart->ubrdiv);
for (i = 0; i < 100; i++)
/* Delay */ ;
}
#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_setbrg_dev(unsigned int dev_index)
{
_serial_setbrg(dev_index);
}
#else
void serial_setbrg(void)
{
_serial_setbrg(UART_NR);
}
#endif
/* Initialise the serial port. The settings are always 8 data bits, no parity,
* 1 stop bit, no start bits.
*/
static int serial_init_dev(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
#ifdef CONFIG_HWFLOW
hwflow = 0; /* turned off by default */
#endif
/* FIFO enable, Tx/Rx FIFO clear */
writel(0x07, &uart->ufcon);
writel(0x0, &uart->umcon);
/* Normal,No parity,1 stop,8 bit */
writel(0x3, &uart->ulcon);
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
writel(0x245, &uart->ucon);
#ifdef CONFIG_HWFLOW
writel(0x1, &uart->umcon); /* rts up */
#endif
/* FIXME: This is sooooooooooooooooooo ugly */
#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2)
/* we need auto hw flow control on the gsm and gps port */
if (dev_index == 0 || dev_index == 1)
writel(0x10, &uart->umcon);
#endif
_serial_setbrg(dev_index);
return (0);
}
#if !defined(CONFIG_SERIAL_MULTI)
/* Initialise the serial port. The settings are always 8 data bits, no parity,
* 1 stop bit, no start bits.
*/
int serial_init(void)
{
return serial_init_dev(UART_NR);
}
#endif
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int _serial_getc(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
while (!(readl(&uart->utrstat) & 0x1))
/* wait for character to arrive */ ;
return readb(&uart->urxh) & 0xff;
}
#if defined(CONFIG_SERIAL_MULTI)
static inline int serial_getc_dev(unsigned int dev_index)
{
return _serial_getc(dev_index);
}
#else
int serial_getc(void)
{
return _serial_getc(UART_NR);
}
#endif
#ifdef CONFIG_HWFLOW
int hwflow_onoff(int on)
{
switch (on) {
case 0:
default:
break; /* return current */
case 1:
hwflow = 1; /* turn on */
break;
case -1:
hwflow = 0; /* turn off */
break;
}
return hwflow;
}
#endif
#ifdef CONFIG_MODEM_SUPPORT
static int be_quiet = 0;
void disable_putc(void)
{
be_quiet = 1;
}
void enable_putc(void)
{
be_quiet = 0;
}
#endif
/*
* Output a single byte to the serial port.
*/
void _serial_putc(const char c, const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
#ifdef CONFIG_MODEM_SUPPORT
if (be_quiet)
return;
#endif
while (!(readl(&uart->utrstat) & 0x2))
/* wait for room in the tx FIFO */ ;
#ifdef CONFIG_HWFLOW
while (hwflow && !(readl(&uart->umstat) & 0x1))
/* Wait for CTS up */ ;
#endif
writeb(c, &uart->utxh);
/* If \n, also do \r */
if (c == '\n')
serial_putc('\r');
}
#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_putc_dev(unsigned int dev_index, const char c)
{
_serial_putc(c, dev_index);
}
#else
void serial_putc(const char c)
{
_serial_putc(c, UART_NR);
}
#endif
/*
* Test whether a character is in the RX buffer
*/
int _serial_tstc(const int dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
return readl(&uart->utrstat) & 0x1;
}
#if defined(CONFIG_SERIAL_MULTI)
static inline int serial_tstc_dev(unsigned int dev_index)
{
return _serial_tstc(dev_index);
}
#else
int serial_tstc(void)
{
return _serial_tstc(UART_NR);
}
#endif
void _serial_puts(const char *s, const int dev_index)
{
while (*s) {
_serial_putc(*s++, dev_index);
}
}
#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_puts_dev(int dev_index, const char *s)
{
_serial_puts(s, dev_index);
}
#else
void serial_puts(const char *s)
{
_serial_puts(s, UART_NR);
}
#endif
#if defined(CONFIG_SERIAL_MULTI)
DECLARE_S3C_SERIAL_FUNCTIONS(0);
struct serial_device s3c24xx_serial0_device =
INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0");
DECLARE_S3C_SERIAL_FUNCTIONS(1);
struct serial_device s3c24xx_serial1_device =
INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1");
DECLARE_S3C_SERIAL_FUNCTIONS(2);
struct serial_device s3c24xx_serial2_device =
INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2");
__weak struct serial_device *default_serial_console(void)
{
#if defined(CONFIG_SERIAL1)
return &s3c24xx_serial0_device;
#elif defined(CONFIG_SERIAL2)
return &s3c24xx_serial1_device;
#elif defined(CONFIG_SERIAL3)
return &s3c24xx_serial2_device;
#else
#error "CONFIG_SERIAL? missing."
#endif
}
#endif /* CONFIG_SERIAL_MULTI */
|
1001-study-uboot
|
drivers/serial/serial_s3c24x0.c
|
C
|
gpl3
| 6,927
|
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* (C) Copyright 2008
* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/arch/s3c6400.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SERIAL1
#define UART_NR S3C64XX_UART0
#elif defined(CONFIG_SERIAL2)
#define UART_NR S3C64XX_UART1
#elif defined(CONFIG_SERIAL3)
#define UART_NR S3C64XX_UART2
#else
#error "Bad: you didn't configure serial ..."
#endif
#define barrier() asm volatile("" ::: "memory")
/*
* The coefficient, used to calculate the baudrate on S3C6400 UARTs is
* calculated as
* C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
* however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
* 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
*/
static const int udivslot[] = {
0,
0x0080,
0x0808,
0x0888,
0x2222,
0x4924,
0x4a52,
0x54aa,
0x5555,
0xd555,
0xd5d5,
0xddd5,
0xdddd,
0xdfdd,
0xdfdf,
0xffdf,
};
void serial_setbrg(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
u32 pclk = get_PCLK();
u32 baudrate = gd->baudrate;
int i;
i = (pclk / baudrate) % 16;
uart->UBRDIV = pclk / baudrate / 16 - 1;
uart->UDIVSLOT = udivslot[i];
for (i = 0; i < 100; i++)
barrier();
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
int serial_init(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
/* reset and enable FIFOs, set triggers to the maximum */
uart->UFCON = 0xff;
uart->UMCON = 0;
/* 8N1 */
uart->ULCON = 3;
/* No interrupts, no DMA, pure polling */
uart->UCON = 5;
serial_setbrg();
return 0;
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
/* wait for character to arrive */
while (!(uart->UTRSTAT & 0x1));
return uart->URXH & 0xff;
}
#ifdef CONFIG_MODEM_SUPPORT
static int be_quiet;
void disable_putc(void)
{
be_quiet = 1;
}
void enable_putc(void)
{
be_quiet = 0;
}
#endif
/*
* Output a single byte to the serial port.
*/
void serial_putc(const char c)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
#ifdef CONFIG_MODEM_SUPPORT
if (be_quiet)
return;
#endif
/* wait for room in the tx FIFO */
while (!(uart->UTRSTAT & 0x2));
uart->UTXH = c;
/* If \n, also do \r */
if (c == '\n')
serial_putc('\r');
}
/*
* Test whether a character is in the RX buffer
*/
int serial_tstc(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
return uart->UTRSTAT & 0x1;
}
void serial_puts(const char *s)
{
while (*s)
serial_putc(*s++);
}
|
1001-study-uboot
|
drivers/serial/s3c64xx.c
|
C
|
gpl3
| 3,589
|
/*
* (C) Copyright 2008-2011 Michal Simek <monstr@monstr.eu>
* Clean driver and add xilinx constant from header file
*
* (C) Copyright 2004 Atmark Techno, Inc.
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <serial.h>
#define SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */
#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
struct uartlite {
unsigned int rx_fifo;
unsigned int tx_fifo;
unsigned int status;
};
static struct uartlite *userial_ports[4] = {
#ifdef XILINX_UARTLITE_BASEADDR
[0] = (struct uartlite *)XILINX_UARTLITE_BASEADDR,
#endif
#ifdef XILINX_UARTLITE_BASEADDR1
[1] = (struct uartlite *)XILINX_UARTLITE_BASEADDR1,
#endif
#ifdef XILINX_UARTLITE_BASEADDR2
[2] = (struct uartlite *)XILINX_UARTLITE_BASEADDR2,
#endif
#ifdef XILINX_UARTLITE_BASEADDR3
[3] = (struct uartlite *)XILINX_UARTLITE_BASEADDR3
#endif
};
void uartlite_serial_putc(const char c, const int port)
{
struct uartlite *regs = userial_ports[port];
if (c == '\n')
uartlite_serial_putc('\r', port);
while (in_be32(®s->status) & SR_TX_FIFO_FULL)
;
out_be32(®s->tx_fifo, c & 0xff);
}
void uartlite_serial_puts(const char *s, const int port)
{
while (*s)
uartlite_serial_putc(*s++, port);
}
int uartlite_serial_getc(const int port)
{
struct uartlite *regs = userial_ports[port];
while (!(in_be32(®s->status) & SR_RX_FIFO_VALID_DATA))
;
return in_be32(®s->rx_fifo) & 0xff;
}
int uartlite_serial_tstc(const int port)
{
struct uartlite *regs = userial_ports[port];
return in_be32(®s->status) & SR_RX_FIFO_VALID_DATA;
}
#if !defined(CONFIG_SERIAL_MULTI)
int serial_init(void)
{
/* FIXME: Nothing for now. We should initialize fifo, etc */
return 0;
}
void serial_setbrg(void)
{
/* FIXME: what's this for? */
}
void serial_putc(const char c)
{
uartlite_serial_putc(c, 0);
}
void serial_puts(const char *s)
{
uartlite_serial_puts(s, 0);
}
int serial_getc(void)
{
return uartlite_serial_getc(0);
}
int serial_tstc(void)
{
return uartlite_serial_tstc(0);
}
#endif
#if defined(CONFIG_SERIAL_MULTI)
/* Multi serial device functions */
#define DECLARE_ESERIAL_FUNCTIONS(port) \
int userial##port##_init(void) \
{ return(0); } \
void userial##port##_setbrg(void) {} \
int userial##port##_getc(void) \
{ return uartlite_serial_getc(port); } \
int userial##port##_tstc(void) \
{ return uartlite_serial_tstc(port); } \
void userial##port##_putc(const char c) \
{ uartlite_serial_putc(c, port); } \
void userial##port##_puts(const char *s) \
{ uartlite_serial_puts(s, port); }
/* Serial device descriptor */
#define INIT_ESERIAL_STRUCTURE(port, name) {\
name,\
userial##port##_init,\
NULL,\
userial##port##_setbrg,\
userial##port##_getc,\
userial##port##_tstc,\
userial##port##_putc,\
userial##port##_puts, }
DECLARE_ESERIAL_FUNCTIONS(0);
struct serial_device uartlite_serial0_device =
INIT_ESERIAL_STRUCTURE(0, "ttyUL0");
DECLARE_ESERIAL_FUNCTIONS(1);
struct serial_device uartlite_serial1_device =
INIT_ESERIAL_STRUCTURE(1, "ttyUL1");
DECLARE_ESERIAL_FUNCTIONS(2);
struct serial_device uartlite_serial2_device =
INIT_ESERIAL_STRUCTURE(2, "ttyUL2");
DECLARE_ESERIAL_FUNCTIONS(3);
struct serial_device uartlite_serial3_device =
INIT_ESERIAL_STRUCTURE(3, "ttyUL3");
__weak struct serial_device *default_serial_console(void)
{
# ifdef XILINX_UARTLITE_BASEADDR
return &uartlite_serial0_device;
# endif /* XILINX_UARTLITE_BASEADDR */
# ifdef XILINX_UARTLITE_BASEADDR1
return &uartlite_serial1_device;
# endif /* XILINX_UARTLITE_BASEADDR1 */
# ifdef XILINX_UARTLITE_BASEADDR2
return &uartlite_serial2_device;
# endif /* XILINX_UARTLITE_BASEADDR2 */
# ifdef XILINX_UARTLITE_BASEADDR3
return &uartlite_serial3_device;
# endif /* XILINX_UARTLITE_BASEADDR3 */
}
#endif /* CONFIG_SERIAL_MULTI */
|
1001-study-uboot
|
drivers/serial/serial_xuartlite.c
|
C
|
gpl3
| 4,714
|
/*
* serial.c -- KS8695 serial driver
*
* (C) Copyright 2004, Greg Ungerer <greg.ungerer@opengear.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/platform.h>
#ifndef CONFIG_SERIAL1
#error "Bad: you didn't configure serial ..."
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* Define the UART hardware register access structure.
*/
struct ks8695uart {
unsigned int RX; /* 0x00 - Receive data (r) */
unsigned int TX; /* 0x04 - Transmit data (w) */
unsigned int FCR; /* 0x08 - Fifo Control (r/w) */
unsigned int LCR; /* 0x0c - Line Control (r/w) */
unsigned int MCR; /* 0x10 - Modem Control (r/w) */
unsigned int LSR; /* 0x14 - Line Status (r/w) */
unsigned int MSR; /* 0x18 - Modem Status (r/w) */
unsigned int BD; /* 0x1c - Baud Rate (r/w) */
unsigned int SR; /* 0x20 - Status (r/w) */
};
#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER))
#define KS8695_UART_CLK 25000000
/*
* Under some circumstances we want to be "quiet" and not issue any
* serial output - though we want u-boot to otherwise work and behave
* the same. By default be noisy.
*/
int serial_console = 1;
void serial_setbrg(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
/* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/
uartp->BD = KS8695_UART_CLK / gd->baudrate;
uartp->LCR = KS8695_UART_LINEC_WLEN8;
}
int serial_init(void)
{
serial_console = 1;
serial_setbrg();
return 0;
}
void serial_raw_putc(const char c)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
int i;
for (i = 0; (i < 0x100000); i++) {
if (uartp->LSR & KS8695_UART_LINES_TXFE)
break;
}
uartp->TX = c;
}
void serial_putc(const char c)
{
if (serial_console) {
serial_raw_putc(c);
if (c == '\n')
serial_raw_putc('\r');
}
}
int serial_tstc(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
if (serial_console)
return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0);
return 0;
}
void serial_puts(const char *s)
{
char c;
while ((c = *s++) != 0)
serial_putc(c);
}
int serial_getc(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0)
;
return (uartp->RX);
}
|
1001-study-uboot
|
drivers/serial/serial_ks8695.c
|
C
|
gpl3
| 2,914
|
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <SA-1100.h>
DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
unsigned int reg = 0;
if (gd->baudrate == 1200)
reg = 191;
else if (gd->baudrate == 9600)
reg = 23;
else if (gd->baudrate == 19200)
reg = 11;
else if (gd->baudrate == 38400)
reg = 5;
else if (gd->baudrate == 57600)
reg = 3;
else if (gd->baudrate == 115200)
reg = 1;
else
hang ();
#ifdef CONFIG_SERIAL1
/* SA1110 uart function */
Ser1SDCR0 |= SDCR0_SUS;
/* Wait until port is ready ... */
while(Ser1UTSR1 & UTSR1_TBY) {}
/* init serial serial 1 */
Ser1UTCR3 = 0x00;
Ser1UTSR0 = 0xff;
Ser1UTCR0 = ( UTCR0_1StpBit | UTCR0_8BitData );
Ser1UTCR1 = 0;
Ser1UTCR2 = (u32)reg;
Ser1UTCR3 = ( UTCR3_RXE | UTCR3_TXE );
#elif defined(CONFIG_SERIAL3)
/* Wait until port is ready ... */
while (Ser3UTSR1 & UTSR1_TBY) {
}
/* init serial serial 3 */
Ser3UTCR3 = 0x00;
Ser3UTSR0 = 0xff;
Ser3UTCR0 = (UTCR0_1StpBit | UTCR0_8BitData);
Ser3UTCR1 = 0;
Ser3UTCR2 = (u32) reg;
Ser3UTCR3 = (UTCR3_RXE | UTCR3_TXE);
#else
#error "Bad: you didn't configured serial ..."
#endif
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
serial_setbrg ();
return (0);
}
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
{
#ifdef CONFIG_SERIAL1
/* wait for room in the tx FIFO on SERIAL1 */
while ((Ser1UTSR0 & UTSR0_TFS) == 0);
Ser1UTDR = c;
#elif defined(CONFIG_SERIAL3)
/* wait for room in the tx FIFO on SERIAL3 */
while ((Ser3UTSR0 & UTSR0_TFS) == 0);
Ser3UTDR = c;
#endif
/* If \n, also do \r */
if (c == '\n')
serial_putc ('\r');
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_tstc (void)
{
#ifdef CONFIG_SERIAL1
return Ser1UTSR1 & UTSR1_RNE;
#elif defined(CONFIG_SERIAL3)
return Ser3UTSR1 & UTSR1_RNE;
#endif
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc (void)
{
#ifdef CONFIG_SERIAL1
while (!(Ser1UTSR1 & UTSR1_RNE));
return (char) Ser1UTDR & 0xff;
#elif defined(CONFIG_SERIAL3)
while (!(Ser3UTSR1 & UTSR1_RNE));
return (char) Ser3UTDR & 0xff;
#endif
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
|
1001-study-uboot
|
drivers/serial/serial_sa1100.c
|
C
|
gpl3
| 3,620
|
/*
* Copyright 2010, Renato Andreola <renato.andreola@imagos.it>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
#include <nios2-yanu.h>
DECLARE_GLOBAL_DATA_PTR;
/*-----------------------------------------------------------------*/
/* YANU Imagos serial port */
/*-----------------------------------------------------------------*/
static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE;
#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
/* Everything's already setup for fixed-baud PTF assignment*/
void serial_setbrg (void)
{
int n, k;
const unsigned max_uns = 0xFFFFFFFF;
unsigned best_n, best_m, baud;
/* compute best N and M couple */
best_n = YANU_MAX_PRESCALER_N;
for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
(unsigned)CONFIG_BAUDRATE) {
best_n = n;
break;
}
}
for (k = 0;; k++) {
if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k)))
break;
}
best_m =
((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) /
((unsigned)CONFIG_SYS_CLK_FREQ >> k);
baud = best_m + best_n * YANU_BAUDE;
writel(baud, &uart->baud);
return;
}
#else
void serial_setbrg (void)
{
int n, k;
const unsigned max_uns = 0xFFFFFFFF;
unsigned best_n, best_m, baud;
/* compute best N and M couple */
best_n = YANU_MAX_PRESCALER_N;
for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) {
if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >=
gd->baudrate) {
best_n = n;
break;
}
}
for (k = 0;; k++) {
if (gd->baudrate <= (max_uns >> (15+n-k)))
break;
}
best_m =
(gd->baudrate * (1 << (15 + n - k))) /
((unsigned)CONFIG_SYS_CLK_FREQ >> k);
baud = best_m + best_n * YANU_BAUDE;
writel(baud, &uart->baud);
return;
}
#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
int serial_init (void)
{
unsigned action,control;
/* status register cleanup */
action = YANU_ACTION_RRRDY |
YANU_ACTION_RTRDY |
YANU_ACTION_ROE |
YANU_ACTION_RBRK |
YANU_ACTION_RFE |
YANU_ACTION_RPE |
YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR;
writel(action, &uart->action);
/*
* control register cleanup
* no interrupts enabled
* one stop bit
* hardware flow control disabled
* 8 bits
*/
control = (0x7 << YANU_CONTROL_BITS_POS);
/* enven parity just to be clean */
control |= YANU_CONTROL_PAREVEN;
/* we set threshold for fifo */
control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY;
control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR;
writel(control, &uart->control);
/* to set baud rate */
serial_setbrg();
return (0);
}
/*-----------------------------------------------------------------------
* YANU CONSOLE
*---------------------------------------------------------------------*/
void serial_putc (char c)
{
int tx_chars;
unsigned status;
if (c == '\n')
serial_putc ('\r');
while (1) {
status = readl(&uart->status);
tx_chars = (status>>YANU_TFIFO_CHARS_POS)
& ((1<<YANU_TFIFO_CHARS_N)-1);
if (tx_chars < YANU_TXFIFO_SIZE-1)
break;
WATCHDOG_RESET ();
}
writel((unsigned char)c, &uart->data);
}
void serial_puts (const char *s)
{
while (*s != 0) {
serial_putc (*s++);
}
}
int serial_tstc(void)
{
unsigned status ;
status = readl(&uart->status);
return (((status >> YANU_RFIFO_CHARS_POS) &
((1 << YANU_RFIFO_CHARS_N) - 1)) > 0);
}
int serial_getc (void)
{
while (serial_tstc() == 0)
WATCHDOG_RESET ();
/* first we pull the char */
writel(YANU_ACTION_RFIFO_PULL, &uart->action);
return(readl(&uart->data) & YANU_DATA_CHAR_MASK);
}
|
1001-study-uboot
|
drivers/serial/opencores_yanu.c
|
C
|
gpl3
| 4,386
|
/*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <clps7111.h>
DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
unsigned int reg = 0;
switch (gd->baudrate) {
case 1200: reg = 191; break;
case 9600: reg = 23; break;
case 19200: reg = 11; break;
case 38400: reg = 5; break;
case 57600: reg = 3; break;
case 115200: reg = 1; break;
default: hang (); break;
}
/* init serial serial 1,2 */
IO_SYSCON1 = SYSCON1_UART1EN;
IO_SYSCON2 = SYSCON2_UART2EN;
reg |= UBRLCR_WRDLEN8;
IO_UBRLCR1 = reg;
IO_UBRLCR2 = reg;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
serial_setbrg ();
return (0);
}
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
{
int tmo;
/* If \n, also do \r */
if (c == '\n')
serial_putc ('\r');
tmo = get_timer (0) + 1 * CONFIG_SYS_HZ;
while (IO_SYSFLG1 & SYSFLG1_UTXFF)
if (get_timer (0) > tmo)
break;
IO_UARTDR1 = c;
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_tstc (void)
{
return !(IO_SYSFLG1 & SYSFLG1_URXFE);
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc (void)
{
while (IO_SYSFLG1 & SYSFLG1_URXFE);
return IO_UARTDR1 & 0xff;
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
|
1001-study-uboot
|
drivers/serial/serial_clps7111.c
|
C
|
gpl3
| 2,724
|
#
# (C) Copyright 2006-2009
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libserial.o
COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
COBJS-$(CONFIG_MCFUART) += mcfuart.o
COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_S5P) += serial_s5p.o
COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o
COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o
COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o
COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o
COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
endif
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/serial/Makefile
|
Makefile
|
gpl3
| 2,782
|
#ifndef __UART_H
#define __UART_H
/*
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
* Curt Brune <curt@cucy.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Description: S3C4510B UART register layout
*/
/* UART LINE CONTROL register */
typedef struct __BF_UART_LINE_CTRL {
u32 wordLen: 2;
u32 nStop: 1;
u32 parity: 3;
u32 clk: 1;
u32 infra_red: 1;
u32 unused:24;
} BF_UART_LINE_CTRL;
typedef union _UART_LINE_CTRL {
u32 ui;
BF_UART_LINE_CTRL bf;
} UART_LINE_CTRL;
/* UART CONTROL register */
typedef struct __BF_UART_CTRL {
u32 rxMode: 2;
u32 rxIrq: 1;
u32 txMode: 2;
u32 DSR: 1;
u32 sendBreak: 1;
u32 loopBack: 1;
u32 unused:24;
} BF_UART_CTRL;
typedef union _UART_CTRL {
u32 ui;
BF_UART_CTRL bf;
} UART_CTRL;
/* UART STATUS register */
typedef struct __BF_UART_STAT {
u32 overrun: 1;
u32 parity: 1;
u32 frame: 1;
u32 breakIrq: 1;
u32 DTR: 1;
u32 rxReady: 1;
u32 txBufEmpty: 1;
u32 txComplete: 1;
u32 unused:24;
} BF_UART_STAT;
typedef union _UART_STAT {
u32 ui;
BF_UART_STAT bf;
} UART_STAT;
/* UART BAUD_DIV register */
typedef struct __BF_UART_BAUD_DIV {
u32 cnt1: 4;
u32 cnt0:12;
u32 unused:16;
} BF_UART_BAUD_DIV;
typedef union _UART_BAUD_DIV {
u32 ui;
BF_UART_BAUD_DIV bf;
} UART_BAUD_DIV;
/* UART register block */
typedef struct __UART {
volatile UART_LINE_CTRL m_lineCtrl;
volatile UART_CTRL m_ctrl;
volatile UART_STAT m_stat;
volatile u32 m_tx;
volatile u32 m_rx;
volatile UART_BAUD_DIV m_baudDiv;
volatile u32 m_baudCnt;
volatile u32 m_baudClk;
} UART;
#define NL 0x0A
#define CR 0x0D
#define BSP 0x08
#define ESC 0x1B
#define CTRLZ 0x1A
#define RUBOUT 0x7F
#endif
|
1001-study-uboot
|
drivers/serial/s3c4510b_uart.h
|
C
|
gpl3
| 2,699
|
/*
* (C) Copyright 2003
* Gerry Hamel, geh@ti.com, Texas Instruments
*
* (C) Copyright 2006
* Bryan O'Donoghue, bodonoghue@codehermit.ie, CodeHermit
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __USB_TTY_H__
#define __USB_TTY_H__
#include <usbdevice.h>
#if defined(CONFIG_PPC)
#include <usb/mpc8xx_udc.h>
#elif defined(CONFIG_OMAP1510)
#include <usb/omap1510_udc.h>
#elif defined(CONFIG_MUSB_UDC)
#include <usb/musb_udc.h>
#elif defined(CONFIG_CPU_PXA27X)
#include <usb/pxa27x_udc.h>
#elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600)
#include <usb/spr_udc.h>
#endif
#include <version.h>
/* If no VendorID/ProductID is defined in config.h, pretend to be Linux
* DO NOT Reuse this Vendor/Product setup with protocol incompatible devices */
#ifndef CONFIG_USBD_VENDORID
#define CONFIG_USBD_VENDORID 0x0525 /* Linux/NetChip */
#endif
#ifndef CONFIG_USBD_PRODUCTID_GSERIAL
#define CONFIG_USBD_PRODUCTID_GSERIAL 0xa4a6 /* gserial */
#endif
#ifndef CONFIG_USBD_PRODUCTID_CDCACM
#define CONFIG_USBD_PRODUCTID_CDCACM 0xa4a7 /* CDC ACM */
#endif
#ifndef CONFIG_USBD_MANUFACTURER
#define CONFIG_USBD_MANUFACTURER "Das U-Boot"
#endif
#ifndef CONFIG_USBD_PRODUCT_NAME
#define CONFIG_USBD_PRODUCT_NAME U_BOOT_VERSION
#endif
#ifndef CONFIG_USBD_CONFIGURATION_STR
#define CONFIG_USBD_CONFIGURATION_STR "TTY via USB"
#endif
#define CONFIG_USBD_SERIAL_OUT_ENDPOINT UDC_OUT_ENDPOINT
#define CONFIG_USBD_SERIAL_OUT_PKTSIZE UDC_OUT_PACKET_SIZE
#define CONFIG_USBD_SERIAL_IN_ENDPOINT UDC_IN_ENDPOINT
#define CONFIG_USBD_SERIAL_IN_PKTSIZE UDC_IN_PACKET_SIZE
#define CONFIG_USBD_SERIAL_INT_ENDPOINT UDC_INT_ENDPOINT
#define CONFIG_USBD_SERIAL_INT_PKTSIZE UDC_INT_PACKET_SIZE
#define CONFIG_USBD_SERIAL_BULK_PKTSIZE UDC_BULK_PACKET_SIZE
#define USBTTY_DEVICE_CLASS COMMUNICATIONS_DEVICE_CLASS
#define USBTTY_BCD_DEVICE 0x00
#define USBTTY_MAXPOWER 0x00
#define STR_LANG 0x00
#define STR_MANUFACTURER 0x01
#define STR_PRODUCT 0x02
#define STR_SERIAL 0x03
#define STR_CONFIG 0x04
#define STR_DATA_INTERFACE 0x05
#define STR_CTRL_INTERFACE 0x06
#define STR_COUNT 0x07
#endif
|
1001-study-uboot
|
drivers/serial/usbtty.h
|
C
|
gpl3
| 2,766
|
/*
* (C) Copyright 2009 SAMSUNG Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Heungjun Kim <riverful.kim@samsung.com>
*
* based on drivers/serial/s3c64xx.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/uart.h>
#include <asm/arch/clk.h>
#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
{
u32 offset = dev_index * sizeof(struct s5p_uart);
return (struct s5p_uart *)(samsung_get_base_uart() + offset);
}
/*
* The coefficient, used to calculate the baudrate on S5P UARTs is
* calculated as
* C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
* however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
* 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
*/
static const int udivslot[] = {
0,
0x0080,
0x0808,
0x0888,
0x2222,
0x4924,
0x4a52,
0x54aa,
0x5555,
0xd555,
0xd5d5,
0xddd5,
0xdddd,
0xdfdd,
0xdfdf,
0xffdf,
};
void serial_setbrg_dev(const int dev_index)
{
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
u32 uclk = get_uart_clk(dev_index);
u32 baudrate = gd->baudrate;
u32 val;
val = uclk / baudrate;
writel(val / 16 - 1, &uart->ubrdiv);
if (s5p_uart_divslot())
writew(udivslot[val % 16], &uart->rest.slot);
else
writeb(val % 16, &uart->rest.value);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
int serial_init_dev(const int dev_index)
{
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
/* reset and enable FIFOs, set triggers to the maximum */
writel(0, &uart->ufcon);
writel(0, &uart->umcon);
/* 8N1 */
writel(0x3, &uart->ulcon);
/* No interrupts, no DMA, pure polling */
writel(0x245, &uart->ucon);
serial_setbrg_dev(dev_index);
return 0;
}
static int serial_err_check(const int dev_index, int op)
{
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
unsigned int mask;
/*
* UERSTAT
* Break Detect [3]
* Frame Err [2] : receive operation
* Parity Err [1] : receive operation
* Overrun Err [0] : receive operation
*/
if (op)
mask = 0x8;
else
mask = 0xf;
return readl(&uart->uerstat) & mask;
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc_dev(const int dev_index)
{
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
/* wait for character to arrive */
while (!(readl(&uart->utrstat) & 0x1)) {
if (serial_err_check(dev_index, 0))
return 0;
}
return (int)(readb(&uart->urxh) & 0xff);
}
/*
* Output a single byte to the serial port.
*/
void serial_putc_dev(const char c, const int dev_index)
{
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
/* wait for room in the tx FIFO */
while (!(readl(&uart->utrstat) & 0x2)) {
if (serial_err_check(dev_index, 1))
return;
}
writeb(c, &uart->utxh);
/* If \n, also do \r */
if (c == '\n')
serial_putc('\r');
}
/*
* Test whether a character is in the RX buffer
*/
int serial_tstc_dev(const int dev_index)
{
struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
return (int)(readl(&uart->utrstat) & 0x1);
}
void serial_puts_dev(const char *s, const int dev_index)
{
while (*s)
serial_putc_dev(*s++, dev_index);
}
/* Multi serial device functions */
#define DECLARE_S5P_SERIAL_FUNCTIONS(port) \
int s5p_serial##port##_init(void) { return serial_init_dev(port); } \
void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \
int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \
int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \
void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
#define INIT_S5P_SERIAL_STRUCTURE(port, name) { \
name, \
s5p_serial##port##_init, \
NULL, \
s5p_serial##port##_setbrg, \
s5p_serial##port##_getc, \
s5p_serial##port##_tstc, \
s5p_serial##port##_putc, \
s5p_serial##port##_puts, }
DECLARE_S5P_SERIAL_FUNCTIONS(0);
struct serial_device s5p_serial0_device =
INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0");
DECLARE_S5P_SERIAL_FUNCTIONS(1);
struct serial_device s5p_serial1_device =
INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1");
DECLARE_S5P_SERIAL_FUNCTIONS(2);
struct serial_device s5p_serial2_device =
INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2");
DECLARE_S5P_SERIAL_FUNCTIONS(3);
struct serial_device s5p_serial3_device =
INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3");
__weak struct serial_device *default_serial_console(void)
{
#if defined(CONFIG_SERIAL0)
return &s5p_serial0_device;
#elif defined(CONFIG_SERIAL1)
return &s5p_serial1_device;
#elif defined(CONFIG_SERIAL2)
return &s5p_serial2_device;
#elif defined(CONFIG_SERIAL3)
return &s5p_serial3_device;
#else
#error "CONFIG_SERIAL? missing."
#endif
}
|
1001-study-uboot
|
drivers/serial/serial_s5p.c
|
C
|
gpl3
| 5,712
|
/*
* COM1 NS16550 support
* originally from linux source (arch/powerpc/boot/ns16550.c)
* modified to use CONFIG_SYS_ISA_MEM and new defines
*/
#include <config.h>
#include <ns16550.h>
#include <watchdog.h>
#include <linux/types.h>
#include <asm/io.h>
#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
#define UART_MCRVAL (UART_MCR_DTR | \
UART_MCR_RTS) /* RTS/DTR */
#define UART_FCRVAL (UART_FCR_FIFO_EN | \
UART_FCR_RXSR | \
UART_FCR_TXSR) /* Clear & enable FIFOs */
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
#define serial_out(x, y) outb(x, (ulong)y)
#define serial_in(y) inb((ulong)y)
#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0)
#define serial_out(x, y) out_be32(y, x)
#define serial_in(y) in_be32(y)
#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0)
#define serial_out(x, y) out_le32(y, x)
#define serial_in(y) in_le32(y)
#else
#define serial_out(x, y) writeb(x, y)
#define serial_in(y) readb(y)
#endif
#ifndef CONFIG_SYS_NS16550_IER
#define CONFIG_SYS_NS16550_IER 0x00
#endif /* CONFIG_SYS_NS16550_IER */
void NS16550_init(NS16550_t com_port, int baud_divisor)
{
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
defined(CONFIG_AM33XX)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr);
serial_out(0, &com_port->dll);
serial_out(0, &com_port->dlm);
serial_out(UART_LCRVAL, &com_port->lcr);
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(UART_FCRVAL, &com_port->fcr);
serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
serial_out(baud_divisor & 0xff, &com_port->dll);
serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
serial_out(UART_LCRVAL, &com_port->lcr);
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
defined(CONFIG_AM33XX)
#if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
serial_out(3, &com_port->mdr1);
#else
/* /16 is proper to hit 115200 with 48MHz */
serial_out(0, &com_port->mdr1);
#endif
#endif /* CONFIG_OMAP */
}
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
void NS16550_reinit(NS16550_t com_port, int baud_divisor)
{
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
serial_out(0, &com_port->dll);
serial_out(0, &com_port->dlm);
serial_out(UART_LCRVAL, &com_port->lcr);
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(UART_FCRVAL, &com_port->fcr);
serial_out(UART_LCR_BKSE, &com_port->lcr);
serial_out(baud_divisor & 0xff, &com_port->dll);
serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
serial_out(UART_LCRVAL, &com_port->lcr);
}
#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
void NS16550_putc(NS16550_t com_port, char c)
{
while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
;
serial_out(c, &com_port->thr);
/*
* Call watchdog_reset() upon newline. This is done here in putc
* since the environment code uses a single puts() to print the complete
* environment upon "printenv". So we can't put this watchdog call
* in puts().
*/
if (c == '\n')
WATCHDOG_RESET();
}
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
char NS16550_getc(NS16550_t com_port)
{
while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
#ifdef CONFIG_USB_TTY
extern void usbtty_poll(void);
usbtty_poll();
#endif
WATCHDOG_RESET();
}
return serial_in(&com_port->rbr);
}
int NS16550_tstc(NS16550_t com_port)
{
return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
}
#endif /* CONFIG_NS16550_MIN_FUNCTIONS */
|
1001-study-uboot
|
drivers/serial/ns16550.c
|
C
|
gpl3
| 3,640
|
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
#include <nios2-io.h>
DECLARE_GLOBAL_DATA_PTR;
/*------------------------------------------------------------------
* JTAG acts as the serial port
*-----------------------------------------------------------------*/
static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
void serial_setbrg( void ){ return; }
int serial_init( void ) { return(0);}
void serial_putc (char c)
{
while (1) {
unsigned st = readl(&jtag->control);
if (NIOS_JTAG_WSPACE(st))
break;
#ifdef CONFIG_ALTERA_JTAG_UART_BYPASS
if (!(st & NIOS_JTAG_AC)) /* no connection */
return;
#endif
WATCHDOG_RESET();
}
writel ((unsigned char)c, &jtag->data);
}
void serial_puts (const char *s)
{
while (*s != 0)
serial_putc (*s++);
}
int serial_tstc (void)
{
return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
}
int serial_getc (void)
{
int c;
unsigned val;
while (1) {
WATCHDOG_RESET ();
val = readl (&jtag->data);
if (val & NIOS_JTAG_RVALID)
break;
}
c = val & 0x0ff;
return (c);
}
|
1001-study-uboot
|
drivers/serial/altera_jtag_uart.c
|
C
|
gpl3
| 1,960
|
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/arch/ixp425.h>
#include <watchdog.h>
/*
* 14.7456 MHz
* Baud Rate = --------------
* 16 x Divisor
*/
#define SERIAL_CLOCK 921600
DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
unsigned int quot = 0;
int uart = CONFIG_SYS_IXP425_CONSOLE;
if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0))
quot = SERIAL_CLOCK / gd->baudrate;
else
hang ();
IER(uart) = 0; /* Disable for now */
FCR(uart) = 0; /* No fifos enabled */
/* set baud rate */
LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
DLL(uart) = quot & 0xff;
DLH(uart) = quot >> 8;
LCR(uart) = LCR_WLS0 | LCR_WLS1;
#ifdef CONFIG_SERIAL_RTS_ACTIVE
MCR(uart) = MCR_RTS; /* set RTS active */
#else
MCR(uart) = 0; /* set RTS inactive */
#endif
IER(uart) = IER_UUE;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
serial_setbrg ();
return (0);
}
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
{
/* wait for room in the tx FIFO on UART */
while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0)
WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
THR(CONFIG_SYS_IXP425_CONSOLE) = c;
/* If \n, also do \r */
if (c == '\n')
serial_putc ('\r');
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_tstc (void)
{
return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR;
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc (void)
{
while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR))
WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
|
1001-study-uboot
|
drivers/serial/serial_ixp.c
|
C
|
gpl3
| 3,189
|
/*
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
* Curt Brune <curt@cucy.com>
*
* (C) Copyright 2004
* DAVE Srl
* http://www.dave-tech.it
* http://www.wawnet.biz
* mailto:info@wawnet.biz
*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* MODULE: $Id:$
* Description: UART/Serial interface for Samsung S3C4510B SoC
* Runtime Env: ARM7TDMI
* Change History:
* 03-02-04 Create (Curt Brune) curt@cucy.com
*
*/
#include <common.h>
#include <asm/hardware.h>
#include "s3c4510b_uart.h"
DECLARE_GLOBAL_DATA_PTR;
static UART *uart;
/* flush serial input queue. returns 0 on success or negative error
* number otherwise
*/
static int serial_flush_input(void)
{
volatile u32 tmp;
/* keep on reading as long as the receiver is not empty */
while( uart->m_stat.bf.rxReady) {
tmp = uart->m_rx;
}
return 0;
}
/* flush output queue. returns 0 on success or negative error number
* otherwise
*/
static int serial_flush_output(void)
{
/* wait until the transmitter is no longer busy */
while( !uart->m_stat.bf.txBufEmpty);
return 0;
}
void serial_setbrg (void)
{
UART_LINE_CTRL ulctrl;
UART_CTRL uctrl;
UART_BAUD_DIV ubd;
serial_flush_output();
serial_flush_input();
/* control register */
uctrl.ui = 0x0;
uctrl.bf.rxMode = 0x1;
uctrl.bf.rxIrq = 0x0;
uctrl.bf.txMode = 0x1;
uctrl.bf.DSR = 0x0;
uctrl.bf.sendBreak = 0x0;
uctrl.bf.loopBack = 0x0;
uart->m_ctrl.ui = uctrl.ui;
/* line control register */
ulctrl.ui = 0x0;
ulctrl.bf.wordLen = 0x3; /* 8 bit data */
ulctrl.bf.nStop = 0x0; /* 1 stop bit */
ulctrl.bf.parity = 0x0; /* no parity */
ulctrl.bf.clk = 0x0; /* internal clock */
ulctrl.bf.infra_red = 0x0; /* no infra_red */
uart->m_lineCtrl.ui = ulctrl.ui;
ubd.ui = 0x0;
/* see table on page 10-15 in SAMSUNG S3C4510B manual */
/* get correct divisor */
switch(gd->baudrate) {
case 1200: ubd.bf.cnt0 = 1301; break;
case 2400: ubd.bf.cnt0 = 650; break;
case 4800: ubd.bf.cnt0 = 324; break;
case 9600: ubd.bf.cnt0 = 162; break;
case 19200: ubd.bf.cnt0 = 80; break;
case 38400: ubd.bf.cnt0 = 40; break;
case 57600: ubd.bf.cnt0 = 26; break;
case 115200: ubd.bf.cnt0 = 13; break;
}
uart->m_baudDiv.ui = ubd.ui;
uart->m_baudCnt = 0x0;
uart->m_baudClk = 0x0;
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
#if CONFIG_SERIAL1 == 1
uart = (UART *)UART0_BASE;
#elif CONFIG_SERIAL1 == 2
uart = (UART *)UART1_BASE;
#else
#error CONFIG_SERIAL1 not equal to 1 or 2
#endif
serial_setbrg ();
return (0);
}
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
{
/* wait for room in the transmit FIFO */
while( !uart->m_stat.bf.txBufEmpty);
uart->m_tx = c;
/*
to be polite with serial console add a line feed
to the carriage return character
*/
if (c=='\n')
serial_putc('\r');
}
/*
* Test if an input byte is ready from the serial port. Returns non-zero on
* success, 0 otherwise.
*/
int serial_tstc (void)
{
return uart->m_stat.bf.rxReady;
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc (void)
{
int rv;
for(;;) {
rv = serial_tstc();
if (rv) {
return uart->m_rx & 0xFF;
}
}
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
/* busy wait for tx complete */
while ( !uart->m_stat.bf.txComplete);
/* clear break */
uart->m_ctrl.bf.sendBreak = 0;
}
|
1001-study-uboot
|
drivers/serial/s3c4510b_uart.c
|
C
|
gpl3
| 4,709
|
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This provide a test serial port. It provides an emulated serial port where
* a test program and read out the serial output and inject serial input for
* U-Boot.
*/
#include <common.h>
#include <os.h>
int serial_init(void)
{
os_tty_raw(0);
return 0;
}
void serial_setbrg(void)
{
}
void serial_putc(const char ch)
{
os_write(1, &ch, 1);
}
void serial_puts(const char *str)
{
os_write(1, str, strlen(str));
}
int serial_getc(void)
{
char buf;
ssize_t count;
count = os_read(0, &buf, 1);
return count == 1 ? buf : 0;
}
int serial_tstc(void)
{
return 0;
}
|
1001-study-uboot
|
drivers/serial/sandbox.c
|
C
|
gpl3
| 1,423
|
/*
* Copyright (C) 2004-2006 Atmel Corporation
*
* Modified to support C structur SoC access by
* Andreas Bießmann <biessmann@corscience.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include "atmel_usart.h"
DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
unsigned long divisor;
unsigned long usart_hz;
/*
* Master Clock
* Baud Rate = --------------
* 16 * CD
*/
usart_hz = get_usart_clk_rate(CONFIG_USART_ID);
divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
writel(USART3_BF(CD, divisor), &usart->brgr);
}
int serial_init(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
serial_setbrg();
writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
&usart->mr);
return 0;
}
void serial_putc(char c)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
if (c == '\n')
serial_putc('\r');
while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
writel(c, &usart->thr);
}
void serial_puts(const char *s)
{
while (*s)
serial_putc(*s++);
}
int serial_getc(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
WATCHDOG_RESET();
return readl(&usart->rhr);
}
int serial_tstc(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}
|
1001-study-uboot
|
drivers/serial/atmel_usart.c
|
C
|
gpl3
| 2,532
|
/*
* (C) Copyright 2003
*
* Pantelis Antoniou <panto@intracom.gr>
* Intracom S.A.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <watchdog.h>
DECLARE_GLOBAL_DATA_PTR;
/**************************************************************/
/* convienient macros */
#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT)
#define MAX3100_SPI_TXD(x) \
do { \
if (x) \
MAX3100_SPI_TXD_PORT |= MAX3100_SPI_TXD_BIT; \
else \
MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \
} while(0)
#define MAX3100_SPI_CLK(x) \
do { \
if (x) \
MAX3100_SPI_CLK_PORT |= MAX3100_SPI_CLK_BIT; \
else \
MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \
} while(0)
#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT)
#define MAX3100_CS(x) \
do { \
if (x) \
MAX3100_CS_PORT |= MAX3100_CS_BIT; \
else \
MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \
} while(0)
/**************************************************************/
/* MAX3100 definitions */
#define MAX3100_WC (3 << 14) /* write configuration */
#define MAX3100_RC (1 << 14) /* read configuration */
#define MAX3100_WD (2 << 14) /* write data */
#define MAX3100_RD (0 << 14) /* read data */
/* configuration register bits */
#define MAX3100_FEN (1 << 13) /* FIFO enable */
#define MAX3100_SHDN (1 << 12) /* shutdown bit */
#define MAX3100_TM (1 << 11) /* T bit irq mask */
#define MAX3100_RM (1 << 10) /* R bit irq mask */
#define MAX3100_PM (1 << 9) /* P bit irq mask */
#define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */
#define MAX3100_IR (1 << 7) /* IRDA timing mode */
#define MAX3100_ST (1 << 6) /* transmit stop bit */
#define MAX3100_PE (1 << 5) /* parity enable bit */
#define MAX3100_L (1 << 4) /* Length bit */
#define MAX3100_B_MASK (0x000F) /* baud rate bits mask */
#define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */
/* data register bits (write) */
#define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */
#define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */
/* data register bits (read) */
#define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */
#define MAX3100_FE (1 << 10) /* framing error when in normal mode */
#define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */
/* data register bits (both directions) */
#define MAX3100_R (1 << 15) /* receive bit */
#define MAX3100_T (1 << 14) /* transmit bit */
#define MAX3100_P (1 << 8) /* parity bit */
#define MAX3100_D_MASK 0x00FF /* data bits mask */
#define MAX3100_D(x) ((x) & 0x00FF) /* data bits */
/* these definitions are valid only for fOSC = 3.6864MHz */
#define MAX3100_B_230400 MAX3100_B(0)
#define MAX3100_B_115200 MAX3100_B(1)
#define MAX3100_B_57600 MAX3100_B(2)
#define MAX3100_B_38400 MAX3100_B(9)
#define MAX3100_B_19200 MAX3100_B(10)
#define MAX3100_B_9600 MAX3100_B(11)
#define MAX3100_B_4800 MAX3100_B(12)
#define MAX3100_B_2400 MAX3100_B(13)
#define MAX3100_B_1200 MAX3100_B(14)
#define MAX3100_B_600 MAX3100_B(15)
/**************************************************************/
static inline unsigned int max3100_transfer(unsigned int val)
{
unsigned int rx;
int b;
MAX3100_SPI_CLK(0);
MAX3100_CS(0);
rx = 0; b = 16;
while (--b >= 0) {
MAX3100_SPI_TXD(val & 0x8000);
val <<= 1;
MAX3100_SPI_CLK_TOGGLE();
udelay(1);
rx <<= 1;
if (MAX3100_SPI_RXD())
rx |= 1;
MAX3100_SPI_CLK_TOGGLE();
udelay(1);
}
MAX3100_SPI_CLK(1);
MAX3100_CS(1);
return rx;
}
/**************************************************************/
/* must be power of 2 */
#define RXFIFO_SZ 16
static int rxfifo_cnt;
static int rxfifo_in;
static int rxfifo_out;
static unsigned char rxfifo_buf[16];
static void max3100_putc(int c)
{
unsigned int rx;
while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0)
WATCHDOG_RESET();
rx = max3100_transfer(MAX3100_WD | (c & 0xff));
if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) {
rxfifo_cnt++;
rxfifo_buf[rxfifo_in++] = rx & 0xff;
rxfifo_in &= RXFIFO_SZ - 1;
}
}
static int max3100_getc(void)
{
int c;
unsigned int rx;
while (rxfifo_cnt == 0) {
rx = max3100_transfer(MAX3100_RD);
if ((rx & MAX3100_R) != 0) {
do {
rxfifo_cnt++;
rxfifo_buf[rxfifo_in++] = rx & 0xff;
rxfifo_in &= RXFIFO_SZ - 1;
if (rxfifo_cnt >= RXFIFO_SZ)
break;
} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
}
WATCHDOG_RESET();
}
rxfifo_cnt--;
c = rxfifo_buf[rxfifo_out++];
rxfifo_out &= RXFIFO_SZ - 1;
return c;
}
static int max3100_tstc(void)
{
unsigned int rx;
if (rxfifo_cnt > 0)
return 1;
rx = max3100_transfer(MAX3100_RD);
if ((rx & MAX3100_R) == 0)
return 0;
do {
rxfifo_cnt++;
rxfifo_buf[rxfifo_in++] = rx & 0xff;
rxfifo_in &= RXFIFO_SZ - 1;
if (rxfifo_cnt >= RXFIFO_SZ)
break;
} while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0);
return 1;
}
int serial_init(void)
{
unsigned int wconf, rconf;
int i;
wconf = 0;
/* Set baud rate */
switch (gd->baudrate) {
case 1200:
wconf = MAX3100_B_1200;
break;
case 2400:
wconf = MAX3100_B_2400;
break;
case 4800:
wconf = MAX3100_B_4800;
break;
case 9600:
wconf = MAX3100_B_9600;
break;
case 19200:
wconf = MAX3100_B_19200;
break;
case 38400:
wconf = MAX3100_B_38400;
break;
case 57600:
wconf = MAX3100_B_57600;
break;
default:
case 115200:
wconf = MAX3100_B_115200;
break;
case 230400:
wconf = MAX3100_B_230400;
break;
}
/* try for 10ms, with a 100us gap */
for (i = 0; i < 10000; i += 100) {
max3100_transfer(MAX3100_WC | wconf);
rconf = max3100_transfer(MAX3100_RC) & 0x3fff;
if (rconf == wconf)
break;
udelay(100);
}
rxfifo_in = rxfifo_out = rxfifo_cnt = 0;
return (0);
}
void serial_putc(const char c)
{
if (c == '\n')
max3100_putc('\r');
max3100_putc(c);
}
void serial_puts(const char *s)
{
while (*s)
serial_putc (*s++);
}
int serial_getc(void)
{
return max3100_getc();
}
int serial_tstc(void)
{
return max3100_tstc();
}
/* XXX WTF? */
void serial_setbrg(void)
{
}
|
1001-study-uboot
|
drivers/serial/serial_max3100.c
|
C
|
gpl3
| 7,106
|
/*
* (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/arch/hardware.h>
DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
unsigned short divisor = 0;
switch (gd->baudrate) {
case 1200: divisor = 3072; break;
case 9600: divisor = 384; break;
case 19200: divisor = 192; break;
case 38400: divisor = 96; break;
case 57600: divisor = 64; break;
case 115200: divisor = 32; break;
default: hang (); break;
}
/* init serial UART0 */
PUT8(U0LCR, 0);
PUT8(U0IER, 0);
PUT8(U0LCR, 0x80); /* DLAB=1 */
PUT8(U0DLL, (unsigned char)(divisor & 0x00FF));
PUT8(U0DLM, (unsigned char)(divisor >> 8));
PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */
PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */
}
int serial_init (void)
{
unsigned long pinsel0;
serial_setbrg ();
pinsel0 = GET32(PINSEL0);
pinsel0 &= ~(0x00000003);
pinsel0 |= 5;
PUT32(PINSEL0, pinsel0);
return (0);
}
void serial_putc (const char c)
{
if (c == '\n')
{
while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
PUT8(U0THR, '\r');
}
while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */
PUT8(U0THR, c);
}
int serial_getc (void)
{
while((GET8(U0LSR) & 1) == 0);
return GET8(U0RBR);
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
/* Test if there is a byte to read */
int serial_tstc (void)
{
return (GET8(U0LSR) & 1);
}
|
1001-study-uboot
|
drivers/serial/serial_lpc2292.c
|
C
|
gpl3
| 2,454
|
/*
* (C) Copyright 2003, 2004
* ARM Ltd.
* Philippe Robin, <philippe.robin@arm.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* ARM PrimeCell UART's (PL010 & PL011)
* ------------------------------------
*
* Definitions common to both PL010 & PL011
*
*/
#ifndef __ASSEMBLY__
/*
* We can use a combined structure for PL010 and PL011, because they overlap
* only in common registers.
*/
struct pl01x_regs {
u32 dr; /* 0x00 Data register */
u32 ecr; /* 0x04 Error clear register (Write) */
u32 pl010_lcrh; /* 0x08 Line control register, high byte */
u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
u32 pl010_lcrl; /* 0x10 Line control register, low byte */
u32 pl010_cr; /* 0x14 Control register */
u32 fr; /* 0x18 Flag register (Read only) */
#ifdef CONFIG_PL011_SERIAL_RLCR
u32 pl011_rlcr; /* 0x1c Receive line control register */
#else
u32 reserved;
#endif
u32 ilpr; /* 0x20 IrDA low-power counter register */
u32 pl011_ibrd; /* 0x24 Integer baud rate register */
u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
u32 pl011_lcrh; /* 0x2C Line control register */
u32 pl011_cr; /* 0x30 Control register */
};
#endif
#define UART_PL01x_RSR_OE 0x08
#define UART_PL01x_RSR_BE 0x04
#define UART_PL01x_RSR_PE 0x02
#define UART_PL01x_RSR_FE 0x01
#define UART_PL01x_FR_TXFE 0x80
#define UART_PL01x_FR_RXFF 0x40
#define UART_PL01x_FR_TXFF 0x20
#define UART_PL01x_FR_RXFE 0x10
#define UART_PL01x_FR_BUSY 0x08
#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
/*
* PL010 definitions
*
*/
#define UART_PL010_CR_LPE (1 << 7)
#define UART_PL010_CR_RTIE (1 << 6)
#define UART_PL010_CR_TIE (1 << 5)
#define UART_PL010_CR_RIE (1 << 4)
#define UART_PL010_CR_MSIE (1 << 3)
#define UART_PL010_CR_IIRLP (1 << 2)
#define UART_PL010_CR_SIREN (1 << 1)
#define UART_PL010_CR_UARTEN (1 << 0)
#define UART_PL010_LCRH_WLEN_8 (3 << 5)
#define UART_PL010_LCRH_WLEN_7 (2 << 5)
#define UART_PL010_LCRH_WLEN_6 (1 << 5)
#define UART_PL010_LCRH_WLEN_5 (0 << 5)
#define UART_PL010_LCRH_FEN (1 << 4)
#define UART_PL010_LCRH_STP2 (1 << 3)
#define UART_PL010_LCRH_EPS (1 << 2)
#define UART_PL010_LCRH_PEN (1 << 1)
#define UART_PL010_LCRH_BRK (1 << 0)
#define UART_PL010_BAUD_460800 1
#define UART_PL010_BAUD_230400 3
#define UART_PL010_BAUD_115200 7
#define UART_PL010_BAUD_57600 15
#define UART_PL010_BAUD_38400 23
#define UART_PL010_BAUD_19200 47
#define UART_PL010_BAUD_14400 63
#define UART_PL010_BAUD_9600 95
#define UART_PL010_BAUD_4800 191
#define UART_PL010_BAUD_2400 383
#define UART_PL010_BAUD_1200 767
/*
* PL011 definitions
*
*/
#define UART_PL011_LCRH_SPS (1 << 7)
#define UART_PL011_LCRH_WLEN_8 (3 << 5)
#define UART_PL011_LCRH_WLEN_7 (2 << 5)
#define UART_PL011_LCRH_WLEN_6 (1 << 5)
#define UART_PL011_LCRH_WLEN_5 (0 << 5)
#define UART_PL011_LCRH_FEN (1 << 4)
#define UART_PL011_LCRH_STP2 (1 << 3)
#define UART_PL011_LCRH_EPS (1 << 2)
#define UART_PL011_LCRH_PEN (1 << 1)
#define UART_PL011_LCRH_BRK (1 << 0)
#define UART_PL011_CR_CTSEN (1 << 15)
#define UART_PL011_CR_RTSEN (1 << 14)
#define UART_PL011_CR_OUT2 (1 << 13)
#define UART_PL011_CR_OUT1 (1 << 12)
#define UART_PL011_CR_RTS (1 << 11)
#define UART_PL011_CR_DTR (1 << 10)
#define UART_PL011_CR_RXE (1 << 9)
#define UART_PL011_CR_TXE (1 << 8)
#define UART_PL011_CR_LPE (1 << 7)
#define UART_PL011_CR_IIRLP (1 << 2)
#define UART_PL011_CR_SIREN (1 << 1)
#define UART_PL011_CR_UARTEN (1 << 0)
#define UART_PL011_IMSC_OEIM (1 << 10)
#define UART_PL011_IMSC_BEIM (1 << 9)
#define UART_PL011_IMSC_PEIM (1 << 8)
#define UART_PL011_IMSC_FEIM (1 << 7)
#define UART_PL011_IMSC_RTIM (1 << 6)
#define UART_PL011_IMSC_TXIM (1 << 5)
#define UART_PL011_IMSC_RXIM (1 << 4)
#define UART_PL011_IMSC_DSRMIM (1 << 3)
#define UART_PL011_IMSC_DCDMIM (1 << 2)
#define UART_PL011_IMSC_CTSMIM (1 << 1)
#define UART_PL011_IMSC_RIMIM (1 << 0)
|
1001-study-uboot
|
drivers/serial/serial_pl01x.h
|
C
|
gpl3
| 5,440
|
/***********************************************************************
*
* Copyright (C) 2004 by FS Forth-Systeme GmbH.
* All rights reserved.
*
* $Id: ns9750_serial.c,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
* @Author: Markus Pietrek
* @Descr: Serial driver for the NS9750. Only one UART is supported yet.
* @References: [1] NS9750 Hardware Reference/December 2003
* @TODO: Implement Character GAP Timer when chip is fixed for PLL bypass
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
***********************************************************************/
#include <common.h>
#include "ns9750_bbus.h" /* for GPIOs */
#include "ns9750_ser.h" /* for serial configuration */
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_CONS_INDEX)
#error "No console index specified."
#endif
#define CONSOLE CONFIG_CONS_INDEX
static unsigned int calcBitrateRegister( void );
static unsigned int calcRxCharGapRegister( void );
static char cCharsAvailable; /* Numbers of chars in unCharCache */
static unsigned int unCharCache; /* unCharCache is only valid if
* cCharsAvailable > 0 */
/***********************************************************************
* @Function: serial_init
* @Return: 0
* @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off
***********************************************************************/
int serial_init( void )
{
unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 };
unsigned int aunGPIORxD[] = { 1, 9, 41, 45 };
cCharsAvailable = 0;
/* configure TxD and RxD pins for their special function */
set_gpio_cfg_reg_val( aunGPIOTxD[ CONSOLE ],
NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_OUTPUT );
set_gpio_cfg_reg_val( aunGPIORxD[ CONSOLE ],
NS9750_GPIO_CFG_FUNC_0 | NS9750_GPIO_CFG_INPUT );
/* configure serial engine */
*get_ser_reg_addr_channel( NS9750_SER_CTRL_A, CONSOLE ) =
NS9750_SER_CTRL_A_CE |
NS9750_SER_CTRL_A_STOP |
NS9750_SER_CTRL_A_WLS_8;
serial_setbrg();
*get_ser_reg_addr_channel( NS9750_SER_CTRL_B, CONSOLE ) =
NS9750_SER_CTRL_B_RCGT;
return 0;
}
/***********************************************************************
* @Function: serial_putc
* @Return: n/a
* @Descr: writes one character to the FIFO. Blocks until FIFO is not full
***********************************************************************/
void serial_putc( const char c )
{
if (c == '\n')
serial_putc( '\r' );
while (!(*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE) &
NS9750_SER_STAT_A_TRDY ) ) {
/* do nothing, wait for characters in FIFO sent */
}
*(volatile char*) get_ser_reg_addr_channel( NS9750_SER_FIFO,
CONSOLE) = c;
}
/***********************************************************************
* @Function: serial_puts
* @Return: n/a
* @Descr: writes non-zero string to the FIFO.
***********************************************************************/
void serial_puts( const char *s )
{
while (*s) {
serial_putc( *s++ );
}
}
/***********************************************************************
* @Function: serial_getc
* @Return: the character read
* @Descr: performs only 8bit accesses to the FIFO. No error handling
***********************************************************************/
int serial_getc( void )
{
int i;
while (!serial_tstc() ) {
/* do nothing, wait for incoming characters */
}
/* at least one character in unCharCache */
i = (int) (unCharCache & 0xff);
unCharCache >>= 8;
cCharsAvailable--;
return i;
}
/***********************************************************************
* @Function: serial_tstc
* @Return: 0 if no input available, otherwise != 0
* @Descr: checks for incoming FIFO not empty. Stores the incoming chars in
* unCharCache and the numbers of characters in cCharsAvailable
***********************************************************************/
int serial_tstc( void )
{
unsigned int unRegCache;
if ( cCharsAvailable )
return 1;
unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,CONSOLE );
if( unRegCache & NS9750_SER_STAT_A_RBC ) {
*get_ser_reg_addr_channel( NS9750_SER_STAT_A, CONSOLE ) =
NS9750_SER_STAT_A_RBC;
unRegCache = *get_ser_reg_addr_channel( NS9750_SER_STAT_A,
CONSOLE );
}
if ( unRegCache & NS9750_SER_STAT_A_RRDY ) {
cCharsAvailable = (unRegCache & NS9750_SER_STAT_A_RXFDB_MA)>>20;
if ( !cCharsAvailable )
cCharsAvailable = 4;
unCharCache = *get_ser_reg_addr_channel( NS9750_SER_FIFO,
CONSOLE );
return 1;
}
/* no chars available */
return 0;
}
void serial_setbrg( void )
{
*get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) =
calcBitrateRegister();
*get_ser_reg_addr_channel( NS9750_SER_RX_CHAR_TIMER, CONSOLE ) =
calcRxCharGapRegister();
}
/***********************************************************************
* @Function: calcBitrateRegister
* @Return: value for the serial bitrate register
* @Descr: register value depends on clock frequency and baudrate
***********************************************************************/
static unsigned int calcBitrateRegister( void )
{
return ( NS9750_SER_BITRATE_EBIT |
NS9750_SER_BITRATE_CLKMUX_BCLK |
NS9750_SER_BITRATE_TMODE |
NS9750_SER_BITRATE_TCDR_16 |
NS9750_SER_BITRATE_RCDR_16 |
( ( ( ( CONFIG_SYS_CLK_FREQ / 8 ) / /* BBUS clock,[1] Fig. 38 */
( gd->baudrate * 16 ) ) - 1 ) &
NS9750_SER_BITRATE_N_MA ) );
}
/***********************************************************************
* @Function: calcRxCharGapRegister
* @Return: value for the character gap timer register
* @Descr: register value depends on clock frequency and baudrate. Currently 0
* is used as there is a bug with the gap timer in PLL bypass mode.
***********************************************************************/
static unsigned int calcRxCharGapRegister( void )
{
return NS9750_SER_RX_CHAR_TIMER_TRUN;
}
|
1001-study-uboot
|
drivers/serial/ns9750_serial.c
|
C
|
gpl3
| 6,556
|
/*
* Register definitions for the Atmel USART3 module.
*
* Copyright (C) 2005-2006 Atmel Corporation
*
* Modified to support C structure SoC access by
* Andreas Bießmann <biessmann@corscience.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __DRIVERS_ATMEL_USART_H__
#define __DRIVERS_ATMEL_USART_H__
/* USART3 register footprint */
typedef struct atmel_usart3 {
u32 cr;
u32 mr;
u32 ier;
u32 idr;
u32 imr;
u32 csr;
u32 rhr;
u32 thr;
u32 brgr;
u32 rtor;
u32 ttgr;
u32 reserved0[5];
u32 fidi;
u32 ner;
u32 reserved1;
u32 ifr;
u32 man;
u32 reserved2[54]; /* version and PDC not needed */
} atmel_usart3_t;
/* Bitfields in CR */
#define USART3_RSTRX_OFFSET 2
#define USART3_RSTRX_SIZE 1
#define USART3_RSTTX_OFFSET 3
#define USART3_RSTTX_SIZE 1
#define USART3_RXEN_OFFSET 4
#define USART3_RXEN_SIZE 1
#define USART3_RXDIS_OFFSET 5
#define USART3_RXDIS_SIZE 1
#define USART3_TXEN_OFFSET 6
#define USART3_TXEN_SIZE 1
#define USART3_TXDIS_OFFSET 7
#define USART3_TXDIS_SIZE 1
#define USART3_RSTSTA_OFFSET 8
#define USART3_RSTSTA_SIZE 1
#define USART3_STTBRK_OFFSET 9
#define USART3_STTBRK_SIZE 1
#define USART3_STPBRK_OFFSET 10
#define USART3_STPBRK_SIZE 1
#define USART3_STTTO_OFFSET 11
#define USART3_STTTO_SIZE 1
#define USART3_SENDA_OFFSET 12
#define USART3_SENDA_SIZE 1
#define USART3_RSTIT_OFFSET 13
#define USART3_RSTIT_SIZE 1
#define USART3_RSTNACK_OFFSET 14
#define USART3_RSTNACK_SIZE 1
#define USART3_RETTO_OFFSET 15
#define USART3_RETTO_SIZE 1
#define USART3_DTREN_OFFSET 16
#define USART3_DTREN_SIZE 1
#define USART3_DTRDIS_OFFSET 17
#define USART3_DTRDIS_SIZE 1
#define USART3_RTSEN_OFFSET 18
#define USART3_RTSEN_SIZE 1
#define USART3_RTSDIS_OFFSET 19
#define USART3_RTSDIS_SIZE 1
#define USART3_COMM_TX_OFFSET 30
#define USART3_COMM_TX_SIZE 1
#define USART3_COMM_RX_OFFSET 31
#define USART3_COMM_RX_SIZE 1
/* Bitfields in MR */
#define USART3_USART_MODE_OFFSET 0
#define USART3_USART_MODE_SIZE 4
#define USART3_USCLKS_OFFSET 4
#define USART3_USCLKS_SIZE 2
#define USART3_CHRL_OFFSET 6
#define USART3_CHRL_SIZE 2
#define USART3_SYNC_OFFSET 8
#define USART3_SYNC_SIZE 1
#define USART3_PAR_OFFSET 9
#define USART3_PAR_SIZE 3
#define USART3_NBSTOP_OFFSET 12
#define USART3_NBSTOP_SIZE 2
#define USART3_CHMODE_OFFSET 14
#define USART3_CHMODE_SIZE 2
#define USART3_MSBF_OFFSET 16
#define USART3_MSBF_SIZE 1
#define USART3_MODE9_OFFSET 17
#define USART3_MODE9_SIZE 1
#define USART3_CLKO_OFFSET 18
#define USART3_CLKO_SIZE 1
#define USART3_OVER_OFFSET 19
#define USART3_OVER_SIZE 1
#define USART3_INACK_OFFSET 20
#define USART3_INACK_SIZE 1
#define USART3_DSNACK_OFFSET 21
#define USART3_DSNACK_SIZE 1
#define USART3_MAX_ITERATION_OFFSET 24
#define USART3_MAX_ITERATION_SIZE 3
#define USART3_FILTER_OFFSET 28
#define USART3_FILTER_SIZE 1
/* Bitfields in CSR */
#define USART3_RXRDY_OFFSET 0
#define USART3_RXRDY_SIZE 1
#define USART3_TXRDY_OFFSET 1
#define USART3_TXRDY_SIZE 1
#define USART3_RXBRK_OFFSET 2
#define USART3_RXBRK_SIZE 1
#define USART3_ENDRX_OFFSET 3
#define USART3_ENDRX_SIZE 1
#define USART3_ENDTX_OFFSET 4
#define USART3_ENDTX_SIZE 1
#define USART3_OVRE_OFFSET 5
#define USART3_OVRE_SIZE 1
#define USART3_FRAME_OFFSET 6
#define USART3_FRAME_SIZE 1
#define USART3_PARE_OFFSET 7
#define USART3_PARE_SIZE 1
#define USART3_TIMEOUT_OFFSET 8
#define USART3_TIMEOUT_SIZE 1
#define USART3_TXEMPTY_OFFSET 9
#define USART3_TXEMPTY_SIZE 1
#define USART3_ITERATION_OFFSET 10
#define USART3_ITERATION_SIZE 1
#define USART3_TXBUFE_OFFSET 11
#define USART3_TXBUFE_SIZE 1
#define USART3_RXBUFF_OFFSET 12
#define USART3_RXBUFF_SIZE 1
#define USART3_NACK_OFFSET 13
#define USART3_NACK_SIZE 1
#define USART3_RIIC_OFFSET 16
#define USART3_RIIC_SIZE 1
#define USART3_DSRIC_OFFSET 17
#define USART3_DSRIC_SIZE 1
#define USART3_DCDIC_OFFSET 18
#define USART3_DCDIC_SIZE 1
#define USART3_CTSIC_OFFSET 19
#define USART3_CTSIC_SIZE 1
#define USART3_RI_OFFSET 20
#define USART3_RI_SIZE 1
#define USART3_DSR_OFFSET 21
#define USART3_DSR_SIZE 1
#define USART3_DCD_OFFSET 22
#define USART3_DCD_SIZE 1
#define USART3_CTS_OFFSET 23
#define USART3_CTS_SIZE 1
/* Bitfields in RHR */
#define USART3_RXCHR_OFFSET 0
#define USART3_RXCHR_SIZE 9
/* Bitfields in THR */
#define USART3_TXCHR_OFFSET 0
#define USART3_TXCHR_SIZE 9
/* Bitfields in BRGR */
#define USART3_CD_OFFSET 0
#define USART3_CD_SIZE 16
/* Bitfields in RTOR */
#define USART3_TO_OFFSET 0
#define USART3_TO_SIZE 16
/* Bitfields in TTGR */
#define USART3_TG_OFFSET 0
#define USART3_TG_SIZE 8
/* Bitfields in FIDI */
#define USART3_FI_DI_RATIO_OFFSET 0
#define USART3_FI_DI_RATIO_SIZE 11
/* Bitfields in NER */
#define USART3_NB_ERRORS_OFFSET 0
#define USART3_NB_ERRORS_SIZE 8
/* Bitfields in XXR */
#define USART3_XOFF_OFFSET 0
#define USART3_XOFF_SIZE 8
#define USART3_XON_OFFSET 8
#define USART3_XON_SIZE 8
/* Bitfields in IFR */
#define USART3_IRDA_FILTER_OFFSET 0
#define USART3_IRDA_FILTER_SIZE 8
/* Bitfields in RCR */
#define USART3_RXCTR_OFFSET 0
#define USART3_RXCTR_SIZE 16
/* Bitfields in TCR */
#define USART3_TXCTR_OFFSET 0
#define USART3_TXCTR_SIZE 16
/* Bitfields in RNCR */
#define USART3_RXNCR_OFFSET 0
#define USART3_RXNCR_SIZE 16
/* Bitfields in TNCR */
#define USART3_TXNCR_OFFSET 0
#define USART3_TXNCR_SIZE 16
/* Bitfields in PTCR */
#define USART3_RXTEN_OFFSET 0
#define USART3_RXTEN_SIZE 1
#define USART3_RXTDIS_OFFSET 1
#define USART3_RXTDIS_SIZE 1
#define USART3_TXTEN_OFFSET 8
#define USART3_TXTEN_SIZE 1
#define USART3_TXTDIS_OFFSET 9
#define USART3_TXTDIS_SIZE 1
/* Constants for USART_MODE */
#define USART3_USART_MODE_NORMAL 0
#define USART3_USART_MODE_RS485 1
#define USART3_USART_MODE_HARDWARE 2
#define USART3_USART_MODE_MODEM 3
#define USART3_USART_MODE_ISO7816_T0 4
#define USART3_USART_MODE_ISO7816_T1 6
#define USART3_USART_MODE_IRDA 8
/* Constants for USCLKS */
#define USART3_USCLKS_MCK 0
#define USART3_USCLKS_MCK_DIV 1
#define USART3_USCLKS_SCK 3
/* Constants for CHRL */
#define USART3_CHRL_5 0
#define USART3_CHRL_6 1
#define USART3_CHRL_7 2
#define USART3_CHRL_8 3
/* Constants for PAR */
#define USART3_PAR_EVEN 0
#define USART3_PAR_ODD 1
#define USART3_PAR_SPACE 2
#define USART3_PAR_MARK 3
#define USART3_PAR_NONE 4
#define USART3_PAR_MULTI 6
/* Constants for NBSTOP */
#define USART3_NBSTOP_1 0
#define USART3_NBSTOP_1_5 1
#define USART3_NBSTOP_2 2
/* Constants for CHMODE */
#define USART3_CHMODE_NORMAL 0
#define USART3_CHMODE_ECHO 1
#define USART3_CHMODE_LOCAL_LOOP 2
#define USART3_CHMODE_REMOTE_LOOP 3
/* Constants for MSBF */
#define USART3_MSBF_LSBF 0
#define USART3_MSBF_MSBF 1
/* Constants for OVER */
#define USART3_OVER_X16 0
#define USART3_OVER_X8 1
/* Constants for CD */
#define USART3_CD_DISABLE 0
#define USART3_CD_BYPASS 1
/* Constants for TO */
#define USART3_TO_DISABLE 0
/* Constants for TG */
#define USART3_TG_DISABLE 0
/* Constants for FI_DI_RATIO */
#define USART3_FI_DI_RATIO_DISABLE 0
/* Bit manipulation macros */
#define USART3_BIT(name) \
(1 << USART3_##name##_OFFSET)
#define USART3_BF(name,value) \
(((value) & ((1 << USART3_##name##_SIZE) - 1)) \
<< USART3_##name##_OFFSET)
#define USART3_BFEXT(name,value) \
(((value) >> USART3_##name##_OFFSET) \
& ((1 << USART3_##name##_SIZE) - 1))
#define USART3_BFINS(name,value,old) \
(((old) & ~(((1 << USART3_##name##_SIZE) - 1) \
<< USART3_##name##_OFFSET)) \
| USART3_BF(name,value))
#endif /* __DRIVERS_ATMEL_USART_H__ */
|
1001-study-uboot
|
drivers/serial/atmel_usart.h
|
C
|
gpl3
| 8,440
|
/*
* Copyright (C) 2004-2007 ARM Limited.
* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* As a special exception, if other files instantiate templates or use macros
* or inline functions from this file, or you compile this file and link it
* with other works to produce a work based on this file, this file does not
* by itself cause the resulting work to be covered by the GNU General Public
* License. However the source code for this file must still be made available
* in accordance with section (3) of the GNU General Public License.
* This exception does not invalidate any other reasons why a work based on
* this file might be covered by the GNU General Public License.
*/
#include <common.h>
#include <stdio_dev.h>
#if defined(CONFIG_CPU_V6)
/*
* ARMV6
*/
#define DCC_RBIT (1 << 30)
#define DCC_WBIT (1 << 29)
#define write_dcc(x) \
__asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x))
#define read_dcc(x) \
__asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x))
#define status_dcc(x) \
__asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x))
#elif defined(CONFIG_CPU_XSCALE)
/*
* XSCALE
*/
#define DCC_RBIT (1 << 31)
#define DCC_WBIT (1 << 28)
#define write_dcc(x) \
__asm__ volatile ("mcr p14, 0, %0, c8, c0, 0\n" : : "r" (x))
#define read_dcc(x) \
__asm__ volatile ("mrc p14, 0, %0, c9, c0, 0\n" : "=r" (x))
#define status_dcc(x) \
__asm__ volatile ("mrc p14, 0, %0, c14, c0, 0\n" : "=r" (x))
#else
#define DCC_RBIT (1 << 0)
#define DCC_WBIT (1 << 1)
#define write_dcc(x) \
__asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x))
#define read_dcc(x) \
__asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x))
#define status_dcc(x) \
__asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x))
#endif
#define can_read_dcc(x) do { \
status_dcc(x); \
x &= DCC_RBIT; \
} while (0);
#define can_write_dcc(x) do { \
status_dcc(x); \
x &= DCC_WBIT; \
x = (x == 0); \
} while (0);
#define TIMEOUT_COUNT 0x4000000
#ifndef CONFIG_ARM_DCC_MULTI
#define arm_dcc_init serial_init
void serial_setbrg(void) {}
#define arm_dcc_getc serial_getc
#define arm_dcc_putc serial_putc
#define arm_dcc_puts serial_puts
#define arm_dcc_tstc serial_tstc
#endif
int arm_dcc_init(void)
{
return 0;
}
int arm_dcc_getc(void)
{
int ch;
register unsigned int reg;
do {
can_read_dcc(reg);
} while (!reg);
read_dcc(ch);
return ch;
}
void arm_dcc_putc(char ch)
{
register unsigned int reg;
unsigned int timeout_count = TIMEOUT_COUNT;
while (--timeout_count) {
can_write_dcc(reg);
if (reg)
break;
}
if (timeout_count == 0)
return;
else
write_dcc(ch);
}
void arm_dcc_puts(const char *s)
{
while (*s)
arm_dcc_putc(*s++);
}
int arm_dcc_tstc(void)
{
register unsigned int reg;
can_read_dcc(reg);
return reg;
}
#ifdef CONFIG_ARM_DCC_MULTI
static struct stdio_dev arm_dcc_dev;
int drv_arm_dcc_init(void)
{
int rc;
/* Device initialization */
memset(&arm_dcc_dev, 0, sizeof(arm_dcc_dev));
strcpy(arm_dcc_dev.name, "dcc");
arm_dcc_dev.ext = 0; /* No extensions */
arm_dcc_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT;
arm_dcc_dev.tstc = arm_dcc_tstc; /* 'tstc' function */
arm_dcc_dev.getc = arm_dcc_getc; /* 'getc' function */
arm_dcc_dev.putc = arm_dcc_putc; /* 'putc' function */
arm_dcc_dev.puts = arm_dcc_puts; /* 'puts' function */
return stdio_register(&arm_dcc_dev);
}
#endif
|
1001-study-uboot
|
drivers/serial/arm_dcc.c
|
C
|
gpl3
| 4,088
|
/*
* Copy and modify from linux/drivers/serial/sh-sci.h
*/
struct uart_port {
unsigned long iobase; /* in/out[bwl] */
unsigned char *membase; /* read/write[bwl] */
unsigned long mapbase; /* for ioremap */
unsigned int type; /* port type */
};
#define PORT_SCI 52
#define PORT_SCIF 53
#define PORT_SCIFA 83
#define PORT_SCIFB 93
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
#include <asm/regs306x.h>
#endif
#if defined(CONFIG_H8S2678)
#include <asm/regs267x.h>
#endif
#if defined(CONFIG_CPU_SH7706) || \
defined(CONFIG_CPU_SH7707) || \
defined(CONFIG_CPU_SH7708) || \
defined(CONFIG_CPU_SH7709)
# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
#elif defined(CONFIG_CPU_SH7705)
# define SCIF0 0xA4400000
# define SCIF2 0xA4410000
# define SCSMR_Ir 0xA44A0000
# define IRDA_SCIF SCIF0
# define SCPCR 0xA4000116
# define SCPDR 0xA4000136
/* Set the clock source,
* SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
*/
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
#elif defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
# define PORT_PTCR 0xA405011EUL
# define PORT_PVCR 0xA4050122UL
# define SCIF_ORER 0x0200 /* overrun error bit */
#elif defined(CONFIG_SH_RTS7751R2D)
# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7750S) || \
defined(CONFIG_CPU_SH7091) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R)
# define SCSPTR1 0xffe0001c /* 8 bit SCI */
# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
#elif defined(CONFIG_CPU_SH7760)
# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define PACR 0xa4050100
# define PBCR 0xa4050102
# define SCSCR_INIT(port) 0x3B
#elif defined(CONFIG_CPU_SH7343)
# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
#elif defined(CONFIG_CPU_SH7722)
# define PADR 0xA4050120
# undef PSDR
# define PSDR 0xA405013e
# define PWDR 0xA4050166
# define PSCR 0xA405011E
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7366)
# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
# define SCSPTR0 SCPDR0
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7723)
# define SCSPTR0 0xa4050160
# define SCSPTR1 0xa405013e
# define SCSPTR2 0xa4050160
# define SCSPTR3 0xa405013e
# define SCSPTR4 0xa4050128
# define SCSPTR5 0xa4050128
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7724)
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
#elif defined(CONFIG_CPU_SH4_202)
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
# define SCIF_BASE_ADDR 0x01030000
# define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
# define SCIF_PTR2_OFFS 0x0000020
# define SCIF_LSR2_OFFS 0x0000024
# define SCSPTR\
((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
# define SCLSR2\
((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
#elif defined(CONFIG_H8S2678)
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
# define H8300_SCI_DR(ch) (*(volatile char *)(P1DR + h8300_sci_pins[ch].port))
#elif defined(CONFIG_CPU_SH7757)
# define SCSPTR0 0xfe4b0020
# define SCSPTR1 0xfe4b0020
# define SCSPTR2 0xfe4b0020
# define SCIF_ORER 0x0001
# define SCSCR_INIT(port) 0x38
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SH7763)
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7770)
# define SCSPTR0 0xff923020 /* 16 bit SCIF */
# define SCSPTR1 0xff924020 /* 16 bit SCIF */
# define SCSPTR2 0xff925020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
#elif defined(CONFIG_CPU_SH7780)
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
#if defined(CONFIG_SH_SH2007)
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
# define SCSCR_INIT(port) 0x38
#else
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
# define SCSCR_INIT(port) 0x3a
#endif
#elif defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7201) || \
defined(CONFIG_CPU_SH7203) || \
defined(CONFIG_CPU_SH7206) || \
defined(CONFIG_CPU_SH7263) || \
defined(CONFIG_CPU_SH7264)
# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
# if defined(CONFIG_CPU_SH7201)
# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
# endif
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SH7619)
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_CPU_SHX3)
# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#else
# error CPU subtype not defined
#endif
/* SCSCR */
#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
#define SCI_CTRL_FLAGS_TE 0x20 /* all */
#define SCI_CTRL_FLAGS_RE 0x10 /* all */
#if defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7091) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7722) || \
defined(CONFIG_CPU_SH7750S) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7763) || \
defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786) || \
defined(CONFIG_CPU_SHX3)
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
#elif defined(CONFIG_CPU_SH7724)
#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
#else
#define SCI_CTRL_FLAGS_REIE 0
#endif
/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
/* SCxSR SCI */
#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
/* SCxSR SCIF */
#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#if defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
# define SCIF_ORER 0x0200
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
# define SCIF_RFDC_MASK 0x007f
# define SCIF_TXROOM_MAX 64
#elif defined(CONFIG_CPU_SH7763)
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK 0x007f
# define SCIF_TXROOM_MAX 64
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
#else
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK 0x001f
# define SCIF_TXROOM_MAX 16
#endif
#ifndef SCIF_ORER
#define SCIF_ORER 0x0000
#endif
#define SCxSR_TEND(port)\
(((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
#define SCxSR_ERRORS(port)\
(((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
#define SCxSR_RDxF(port)\
(((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
#define SCxSR_TDxE(port)\
(((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
#define SCxSR_FER(port)\
(((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
#define SCxSR_PER(port)\
(((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
#define SCxSR_BRK(port)\
((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
#define SCxSR_ORER(port)\
(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
#if defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
#else
# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
#endif
/* SCFCR */
#define SCFCR_RFRST 0x0002
#define SCFCR_TFRST 0x0004
#define SCFCR_TCRST 0x4000
#define SCFCR_MCE 0x0008
#define SCI_MAJOR 204
#define SCI_MINOR_START 8
/* Generic serial flags */
#define SCI_RX_THROTTLE 0x0000001
#define SCI_MAGIC 0xbabeface
/*
* Events are used to schedule things to happen at timer-interrupt
* time, instead of at rs interrupt time.
*/
#define SCI_EVENT_WRITE_WAKEUP 0
#define SCI_IN(size, offset)\
if ((size) == 8) {\
return readb(port->membase + (offset));\
} else {\
return readw(port->membase + (offset));\
}
#define SCI_OUT(size, offset, value)\
if ((size) == 8) {\
writeb(value, port->membase + (offset));\
} else if ((size) == 16) {\
writew(value, port->membase + (offset));\
}
#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
SCI_IN(scif_size, scif_offset)\
} else { /* PORT_SCI or PORT_SCIFA */\
SCI_IN(sci_size, sci_offset);\
}\
}\
static inline void sci_##name##_out(struct uart_port *port,\
unsigned int value) {\
if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
SCI_OUT(scif_size, scif_offset, value)\
} else { /* PORT_SCI or PORT_SCIFA */\
SCI_OUT(sci_size, sci_offset, value);\
}\
}
#ifdef CONFIG_H8300
/* h8300 don't have SCIF */
#define CPU_SCIF_FNS(name) \
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
return 0;\
}\
static inline void sci_##name##_out(struct uart_port *port,\
unsigned int value) {\
}
#else
#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
SCI_IN(scif_size, scif_offset);\
}\
static inline void sci_##name##_out(struct uart_port *port,\
unsigned int value) {\
SCI_OUT(scif_size, scif_offset, value);\
}
#endif
#define CPU_SCI_FNS(name, sci_offset, sci_size)\
static inline unsigned int sci_##name##_in(struct uart_port *port) {\
SCI_IN(sci_size, sci_offset);\
}\
static inline void sci_##name##_out(struct uart_port *port,\
unsigned int value) {\
SCI_OUT(sci_size, sci_offset, value);\
}
#if defined(CONFIG_SH3) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
sh4_sci_offset, sh4_sci_size, \
sh3_scif_offset, sh3_scif_size, \
sh4_scif_offset, sh4_scif_size, \
h8_sci_offset, h8_sci_size) \
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
sh4_scif_offset, sh4_scif_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#elif defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
#elif defined(CONFIG_ARCH_SH7372)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scifb_offset, sh4_scifb_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scifb_offset, sh4_scifb_size)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
#else
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
sh4_sci_offset, sh4_sci_size, \
sh3_scif_offset, sh3_scif_size,\
sh4_scif_offset, sh4_scif_size, \
h8_sci_offset, h8_sci_size) \
CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
sh3_scif_offset, sh3_scif_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
#endif
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
sh4_sci_offset, sh4_sci_size, \
sh3_scif_offset, sh3_scif_size,\
sh4_scif_offset, sh4_scif_size, \
h8_sci_offset, h8_sci_size) \
CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name)
#elif defined(CONFIG_CPU_SH7723) || defined(CONFIG_CPU_SH7724)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
sh4_scif_offset, sh4_scif_size)
#define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#else
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
sh4_sci_offset, sh4_sci_size, \
sh3_scif_offset, sh3_scif_size,\
sh4_scif_offset, sh4_scif_size, \
h8_sci_offset, h8_sci_size) \
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
sh4_scif_offset, sh4_scif_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#endif
#if defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
SCIF_FNS(SCSCR, 0x08, 16)
SCIF_FNS(SCTDSR, 0x0c, 8)
SCIF_FNS(SCFER, 0x10, 16)
SCIF_FNS(SCxSR, 0x14, 16)
SCIF_FNS(SCFCR, 0x18, 16)
SCIF_FNS(SCFDR, 0x1c, 16)
SCIF_FNS(SCxTDR, 0x20, 8)
SCIF_FNS(SCxRDR, 0x24, 8)
SCIF_FNS(SCLSR, 0x00, 0)
#elif defined(CONFIG_ARCH_SH7372)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
SCIF_FNS(SCSCR, 0x08, 16)
SCIF_FNS(SCTDSR, 0x0c, 16)
SCIF_FNS(SCFER, 0x10, 16)
SCIF_FNS(SCxSR, 0x14, 16)
SCIF_FNS(SCFCR, 0x18, 16)
SCIF_FNS(SCFDR, 0x1c, 16)
SCIF_FNS(SCTFDR, 0x38, 16)
SCIF_FNS(SCRFDR, 0x3c, 16)
SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
SCIF_FNS(SCLSR, 0x00, 0)
#elif defined(CONFIG_CPU_SH7723) ||\
defined(CONFIG_CPU_SH7724)
SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
SCIx_FNS(SCSPTR, 0, 0, 0, 0)
SCIF_FNS(SCTDSR, 0x0c, 8)
SCIF_FNS(SCFER, 0x10, 16)
SCIF_FNS(SCFCR, 0x18, 16)
SCIF_FNS(SCFDR, 0x1c, 16)
SCIF_FNS(SCLSR, 0x24, 16)
#else
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
/* name off sz off sz off sz off sz off sz*/
SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
#if defined(CONFIG_CPU_SH7760) || \
defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
#elif defined(CONFIG_CPU_SH7763)
SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
#else
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
#if defined(CONFIG_CPU_SH7722)
SCIF_FNS(SCSPTR, 0, 0, 0, 0)
#else
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
#endif
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
#endif
#define sci_in(port, reg) sci_##reg##_in(port)
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
/* H8/300 series SCI pins assignment */
#if defined(__H8300H__) || defined(__H8300S__)
static const struct __attribute__((packed)) {
int port; /* GPIO port no */
unsigned short rx, tx; /* GPIO bit no */
} h8300_sci_pins[] = {
#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
{ /* SCI0 */
.port = H8300_GPIO_P9,
.rx = H8300_GPIO_B2,
.tx = H8300_GPIO_B0,
},
{ /* SCI1 */
.port = H8300_GPIO_P9,
.rx = H8300_GPIO_B3,
.tx = H8300_GPIO_B1,
},
{ /* SCI2 */
.port = H8300_GPIO_PB,
.rx = H8300_GPIO_B7,
.tx = H8300_GPIO_B6,
}
#elif defined(CONFIG_H8S2678)
{ /* SCI0 */
.port = H8300_GPIO_P3,
.rx = H8300_GPIO_B2,
.tx = H8300_GPIO_B0,
},
{ /* SCI1 */
.port = H8300_GPIO_P3,
.rx = H8300_GPIO_B3,
.tx = H8300_GPIO_B1,
},
{ /* SCI2 */
.port = H8300_GPIO_P5,
.rx = H8300_GPIO_B1,
.tx = H8300_GPIO_B0,
}
#endif
};
#endif
#if defined(CONFIG_CPU_SH7706) || \
defined(CONFIG_CPU_SH7707) || \
defined(CONFIG_CPU_SH7708) || \
defined(CONFIG_CPU_SH7709)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xfffffe80)
return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
return 1;
}
#elif defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7750R) || \
defined(CONFIG_CPU_SH7750S) || \
defined(CONFIG_CPU_SH7091)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xffe00000)
return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
return 1;
}
#elif defined(__H8300H__) || defined(__H8300S__)
static inline int sci_rxd_in(struct uart_port *port)
{
int ch = (port->mapbase - SMR0) >> 3;
return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
}
#else /* default case for non-SCI processors */
static inline int sci_rxd_in(struct uart_port *port)
{
return 1;
}
#endif
/*
* Values for the BitRate Register (SCBRR)
*
* The values are actually divisors for a frequency which can
* be internal to the SH3 (14.7456MHz) or derived from an external
* clock source. This driver assumes the internal clock is used;
* to support using an external clock source, config options or
* possibly command-line options would need to be added.
*
* Also, to support speeds below 2400 (why?) the lower 2 bits of
* the SCSMR register would also need to be set to non-zero values.
*
* -- Greg Banks 27Feb2000
*
* Answer: The SCBRR register is only eight bits, and the value in
* it gets larger with lower baud rates. At around 2400 (depending on
* the peripherial module clock) you run out of bits. However the
* lower two bits of SCSMR allow the module clock to be divided down,
* scaling the value which is needed in SCBRR.
*
* -- Stuart Menefy - 23 May 2000
*
* I meant, why would anyone bother with bitrates below 2400.
*
* -- Greg Banks - 7Jul2000
*
* You "speedist"! How will I use my 110bps ASR-33 teletype with paper
* tape reader as a console!
*
* -- Mitch Davis - 15 Jul 2000
*/
#if (defined(CONFIG_CPU_SH7780) || \
defined(CONFIG_CPU_SH7785) || \
defined(CONFIG_CPU_SH7786)) && \
!defined(CONFIG_SH_SH2007)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
#elif defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_ARCH_SH7367) || \
defined(CONFIG_ARCH_SH7377) || \
defined(CONFIG_ARCH_SH7372)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
#elif defined(CONFIG_CPU_SH7723) ||\
defined(CONFIG_CPU_SH7724)
static inline int scbrr_calc(struct uart_port port, int bps, int clk)
{
if (port.type == PORT_SCIF)
return (clk+16*bps)/(32*bps)-1;
else
return ((clk*2)+16*bps)/(16*bps)-1;
}
#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
#elif defined(CONFIG_CPU_SH7264)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps))
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
|
1001-study-uboot
|
drivers/serial/serial_sh.h
|
C
|
gpl3
| 24,853
|
/*
* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#define __REG(x) (*((volatile u32 *)(x)))
#ifndef CONFIG_MXC_UART_BASE
#error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
#endif
#define UART_PHYS CONFIG_MXC_UART_BASE
#ifdef CONFIG_SERIAL_MULTI
#warning "MXC driver does not support MULTI serials."
#endif
/* Register definitions */
#define URXD 0x0 /* Receiver Register */
#define UTXD 0x40 /* Transmitter Register */
#define UCR1 0x80 /* Control Register 1 */
#define UCR2 0x84 /* Control Register 2 */
#define UCR3 0x88 /* Control Register 3 */
#define UCR4 0x8c /* Control Register 4 */
#define UFCR 0x90 /* FIFO Control Register */
#define USR1 0x94 /* Status Register 1 */
#define USR2 0x98 /* Status Register 2 */
#define UESC 0x9c /* Escape Character Register */
#define UTIM 0xa0 /* Escape Timer Register */
#define UBIR 0xa4 /* BRM Incremental Register */
#define UBMR 0xa8 /* BRM Modulator Register */
#define UBRC 0xac /* Baud Rate Count Register */
#define UTS 0xb4 /* UART Test Register (mx31) */
/* UART Control Register Bit Fields.*/
#define URXD_CHARRDY (1<<15)
#define URXD_ERR (1<<14)
#define URXD_OVRRUN (1<<13)
#define URXD_FRMERR (1<<12)
#define URXD_BRK (1<<11)
#define URXD_PRERR (1<<10)
#define URXD_RX_DATA (0xFF)
#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
#define UCR1_IREN (1<<7) /* Infrared interface enable */
#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
#define UCR1_SNDBRK (1<<4) /* Send break */
#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
#define UCR1_DOZE (1<<1) /* Doze */
#define UCR1_UARTEN (1<<0) /* UART enabled */
#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
#define UCR2_CTSC (1<<13) /* CTS pin control */
#define UCR2_CTS (1<<12) /* Clear to send */
#define UCR2_ESCEN (1<<11) /* Escape enable */
#define UCR2_PREN (1<<8) /* Parity enable */
#define UCR2_PROE (1<<7) /* Parity odd/even */
#define UCR2_STPB (1<<6) /* Stop */
#define UCR2_WS (1<<5) /* Word size */
#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
#define UCR2_TXEN (1<<2) /* Transmitter enabled */
#define UCR2_RXEN (1<<1) /* Receiver enabled */
#define UCR2_SRST (1<<0) /* SW reset */
#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
#define UCR3_PARERREN (1<<12) /* Parity enable */
#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
#define UCR3_DSR (1<<10) /* Data set ready */
#define UCR3_DCD (1<<9) /* Data carrier detect */
#define UCR3_RI (1<<8) /* Ring indicator */
#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
#define UCR3_BPEN (1<<0) /* Preset registers enable */
#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
#define UCR4_INVR (1<<9) /* Inverted infrared reception */
#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
#define UCR4_IRSC (1<<5) /* IR special case */
#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
#define USR1_RTSS (1<<14) /* RTS pin status */
#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
#define USR1_RTSD (1<<12) /* RTS delta */
#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
#define USR2_IDLE (1<<12) /* Idle condition */
#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
#define USR2_WAKE (1<<7) /* Wake */
#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
#define USR2_TXDC (1<<3) /* Transmitter complete */
#define USR2_BRCD (1<<2) /* Break condition */
#define USR2_ORE (1<<1) /* Overrun error */
#define USR2_RDR (1<<0) /* Recv data ready */
#define UTS_FRCPERR (1<<13) /* Force parity error */
#define UTS_LOOP (1<<12) /* Loop tx and rx */
#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
#define UTS_TXFULL (1<<4) /* TxFIFO full */
#define UTS_RXFULL (1<<3) /* RxFIFO full */
#define UTS_SOFTRST (1<<0) /* Software reset */
DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
u32 clk = imx_get_uartclk();
if (!gd->baudrate)
gd->baudrate = CONFIG_BAUDRATE;
__REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */
__REG(UART_PHYS + UBIR) = 0xf;
__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
}
int serial_getc (void)
{
while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
WATCHDOG_RESET();
return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
}
void serial_putc (const char c)
{
__REG(UART_PHYS + UTXD) = c;
/* wait for transmitter to be ready */
while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
WATCHDOG_RESET();
/* If \n, also do \r */
if (c == '\n')
serial_putc ('\r');
}
/*
* Test whether a character is in the RX buffer
*/
int serial_tstc (void)
{
/* If receive fifo is empty, return false */
if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
return 0;
return 1;
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
__REG(UART_PHYS + UCR1) = 0x0;
__REG(UART_PHYS + UCR2) = 0x0;
while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
__REG(UART_PHYS + UCR3) = 0x0704;
__REG(UART_PHYS + UCR4) = 0x8000;
__REG(UART_PHYS + UESC) = 0x002b;
__REG(UART_PHYS + UTIM) = 0x0;
__REG(UART_PHYS + UTS) = 0x0;
serial_setbrg();
__REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
__REG(UART_PHYS + UCR1) = UCR1_UARTEN;
return 0;
}
|
1001-study-uboot
|
drivers/serial/serial_mxc.c
|
C
|
gpl3
| 8,634
|
/*
* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <asm/arch/imx-regs.h>
#if defined CONFIG_IMX_SERIAL1
#define UART_BASE IMX_UART1_BASE
#elif defined CONFIG_IMX_SERIAL2
#define UART_BASE IMX_UART2_BASE
#else
#error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE"
#endif
struct imx_serial {
volatile uint32_t urxd[16];
volatile uint32_t utxd[16];
volatile uint32_t ucr1;
volatile uint32_t ucr2;
volatile uint32_t ucr3;
volatile uint32_t ucr4;
volatile uint32_t ufcr;
volatile uint32_t usr1;
volatile uint32_t usr2;
volatile uint32_t uesc;
volatile uint32_t utim;
volatile uint32_t ubir;
volatile uint32_t ubmr;
volatile uint32_t ubrc;
volatile uint32_t bipr[4];
volatile uint32_t bmpr[4];
volatile uint32_t uts;
};
DECLARE_GLOBAL_DATA_PTR;
void serial_setbrg (void)
{
serial_init();
}
extern void imx_gpio_mode(int gpio_mode);
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
unsigned int ufcr_rfdiv;
unsigned int refclk;
#ifdef CONFIG_IMX_SERIAL1
imx_gpio_mode(PC11_PF_UART1_TXD);
imx_gpio_mode(PC12_PF_UART1_RXD);
#else
imx_gpio_mode(PB30_PF_UART2_TXD);
imx_gpio_mode(PB31_PF_UART2_RXD);
#endif
/* Disable UART */
base->ucr1 &= ~UCR1_UARTEN;
/* Set to default POR state */
base->ucr1 = 0x00000004;
base->ucr2 = 0x00000000;
base->ucr3 = 0x00000000;
base->ucr4 = 0x00008040;
base->uesc = 0x0000002B;
base->utim = 0x00000000;
base->ubir = 0x00000000;
base->ubmr = 0x00000000;
base->uts = 0x00000000;
/* Set clocks */
base->ucr4 |= UCR4_REF16;
/* Configure FIFOs */
base->ufcr = 0xa81;
/* set the baud rate.
*
* baud * 16 x
* --------- = -
* refclk y
*
* x - 1 = UBIR
* y - 1 = UBMR
*
* each register is 16 bits wide. refclk max is 96 MHz
*
*/
ufcr_rfdiv = ((base->ufcr) & UFCR_RFDIV) >> 7;
if (ufcr_rfdiv == 6)
ufcr_rfdiv = 7;
else
ufcr_rfdiv = 6 - ufcr_rfdiv;
refclk = get_PERCLK1();
refclk /= ufcr_rfdiv;
/* Set the numerator value minus one of the BRM ratio */
base->ubir = (gd->baudrate / 100) - 1;
/* Set the denominator value minus one of the BRM ratio */
base->ubmr = (refclk/(16 * 100)) - 1;
/* Set to 8N1 */
base->ucr2 &= ~UCR2_PREN;
base->ucr2 |= UCR2_WS;
base->ucr2 &= ~UCR2_STPB;
/* Ignore RTS */
base->ucr2 |= UCR2_IRTS;
/* Enable UART */
base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN;
/* Enable FIFOs */
base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
/* Clear status flags */
base->usr2 |= USR2_ADET |
USR2_DTRF |
USR2_IDLE |
USR2_IRINT |
USR2_WAKE |
USR2_RTSF |
USR2_BRCD |
USR2_ORE;
/* Clear status flags */
base->usr1 |= USR1_PARITYERR |
USR1_RTSD |
USR1_ESCF |
USR1_FRAMERR |
USR1_AIRINT |
USR1_AWAKE;
return (0);
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is successful, the character read is
* written into its argument c.
*/
int serial_getc (void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
unsigned char ch;
while(base->uts & UTS_RXEMPTY);
ch = (char)base->urxd[0];
return ch;
}
#ifdef CONFIG_HWFLOW
static int hwflow = 0; /* turned off by default */
int hwflow_onoff(int on)
{
}
#endif
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
/* Wait for Tx FIFO not full */
while (base->uts & UTS_TXFULL);
base->utxd[0] = c;
/* If \n, also do \r */
if (c == '\n')
serial_putc ('\r');
}
/*
* Test whether a character is in the RX buffer
*/
int serial_tstc (void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
/* If receive fifo is empty, return false */
if (base->uts & UTS_RXEMPTY)
return 0;
return 1;
}
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
|
1001-study-uboot
|
drivers/serial/serial_imx.c
|
C
|
gpl3
| 4,848
|
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Contains task code and structures for Multi-channel DMA */
#include <common.h>
#include <MCD_dma.h>
u32 MCD_varTab0[];
u32 MCD_varTab1[];
u32 MCD_varTab2[];
u32 MCD_varTab3[];
u32 MCD_varTab4[];
u32 MCD_varTab5[];
u32 MCD_varTab6[];
u32 MCD_varTab7[];
u32 MCD_varTab8[];
u32 MCD_varTab9[];
u32 MCD_varTab10[];
u32 MCD_varTab11[];
u32 MCD_varTab12[];
u32 MCD_varTab13[];
u32 MCD_varTab14[];
u32 MCD_varTab15[];
u32 MCD_funcDescTab0[];
#ifdef MCD_INCLUDE_EU
u32 MCD_funcDescTab1[];
u32 MCD_funcDescTab2[];
u32 MCD_funcDescTab3[];
u32 MCD_funcDescTab4[];
u32 MCD_funcDescTab5[];
u32 MCD_funcDescTab6[];
u32 MCD_funcDescTab7[];
u32 MCD_funcDescTab8[];
u32 MCD_funcDescTab9[];
u32 MCD_funcDescTab10[];
u32 MCD_funcDescTab11[];
u32 MCD_funcDescTab12[];
u32 MCD_funcDescTab13[];
u32 MCD_funcDescTab14[];
u32 MCD_funcDescTab15[];
#endif
u32 MCD_contextSave0[];
u32 MCD_contextSave1[];
u32 MCD_contextSave2[];
u32 MCD_contextSave3[];
u32 MCD_contextSave4[];
u32 MCD_contextSave5[];
u32 MCD_contextSave6[];
u32 MCD_contextSave7[];
u32 MCD_contextSave8[];
u32 MCD_contextSave9[];
u32 MCD_contextSave10[];
u32 MCD_contextSave11[];
u32 MCD_contextSave12[];
u32 MCD_contextSave13[];
u32 MCD_contextSave14[];
u32 MCD_contextSave15[];
u32 MCD_realTaskTableSrc[] = {
0x00000000,
0x00000000,
(u32) MCD_varTab0, /* Task 0 Variable Table */
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
0x00000000,
0x00000000,
(u32) MCD_contextSave0, /* Task 0 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab1, /* Task 1 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab1, /* Task 1 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave1, /* Task 1 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab2, /* Task 2 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab2, /* Task 2 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave2, /* Task 2 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab3, /* Task 3 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab3, /* Task 3 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave3, /* Task 3 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab4, /* Task 4 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab4, /* Task 4 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave4, /* Task 4 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab5, /* Task 5 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab5, /* Task 5 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave5, /* Task 5 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab6, /* Task 6 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab6, /* Task 6 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave6, /* Task 6 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab7, /* Task 7 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab7, /* Task 7 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave7, /* Task 7 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab8, /* Task 8 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab8, /* Task 8 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave8, /* Task 8 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab9, /* Task 9 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab9, /* Task 9 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave9, /* Task 9 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab10, /* Task 10 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab10, /* Task 10 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave10, /* Task 10 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab11, /* Task 11 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab11, /* Task 11 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave11, /* Task 11 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab12, /* Task 12 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab12, /* Task 12 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave12, /* Task 12 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab13, /* Task 13 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab13, /* Task 13 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave13, /* Task 13 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab14, /* Task 14 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab14, /* Task 14 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave14, /* Task 14 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_varTab15, /* Task 15 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32) MCD_funcDescTab15, /* Task 15 Fn Desc. Table & Flags */
#else
(u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
#endif
0x00000000,
0x00000000,
(u32) MCD_contextSave15, /* Task 15 context save space */
0x00000000,
};
u32 MCD_varTab0[] = { /* Task 0 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
0x00000000, /* var[2] */
0x00000000, /* var[3] */
0x00000000, /* var[4] */
0x00000000, /* var[5] */
0x00000000, /* var[6] */
0x00000000, /* var[7] */
0x00000000, /* var[8] */
0x00000000, /* var[9] */
0x00000000, /* var[10] */
0x00000000, /* var[11] */
0x00000000, /* var[12] */
0x00000000, /* var[13] */
0x00000000, /* var[14] */
0x00000000, /* var[15] */
0x00000000, /* var[16] */
0x00000000, /* var[17] */
0x00000000, /* var[18] */
0x00000000, /* var[19] */
0x00000000, /* var[20] */
0x00000000, /* var[21] */
0x00000000, /* var[22] */
0x00000000, /* var[23] */
0xe0000000, /* inc[0] */
0x20000000, /* inc[1] */
0x2000ffff, /* inc[2] */
0x00000000, /* inc[3] */
0x00000000, /* inc[4] */
0x00000000, /* inc[5] */
0x00000000, /* inc[6] */
0x00000000, /* inc[7] */
};
u32 MCD_varTab1[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab2[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab3[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab4[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab5[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab6[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab7[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab8[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab9[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab10[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab11[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab12[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab13[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab14[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_varTab15[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xe0000000,
0x20000000,
0x2000ffff,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_funcDescTab0[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
#ifdef MCD_INCLUDE_EU
u32 MCD_funcDescTab1[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab2[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab3[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab4[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab5[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab6[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab7[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab8[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab9[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab10[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab11[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab12[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab13[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab14[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
u32 MCD_funcDescTab15[] = {
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670,
0xa0000000,
0xa0000000,
0x20000000,
0x21800000,
0x21e00000,
0x20400000,
0x20500000,
0x205a0000,
0x20a00000,
0x202fa000,
0x202f9000,
0x202ea000,
0x202da000,
0x202e2000,
0x202f2000,
};
#endif /*MCD_INCLUDE_EU */
u32 MCD_contextSave0[128]; /* Task 0 context save space */
u32 MCD_contextSave1[128]; /* Task 1 context save space */
u32 MCD_contextSave2[128]; /* Task 2 context save space */
u32 MCD_contextSave3[128]; /* Task 3 context save space */
u32 MCD_contextSave4[128]; /* Task 4 context save space */
u32 MCD_contextSave5[128]; /* Task 5 context save space */
u32 MCD_contextSave6[128]; /* Task 6 context save space */
u32 MCD_contextSave7[128]; /* Task 7 context save space */
u32 MCD_contextSave8[128]; /* Task 8 context save space */
u32 MCD_contextSave9[128]; /* Task 9 context save space */
u32 MCD_contextSave10[128]; /* Task 10 context save space */
u32 MCD_contextSave11[128]; /* Task 11 context save space */
u32 MCD_contextSave12[128]; /* Task 12 context save space */
u32 MCD_contextSave13[128]; /* Task 13 context save space */
u32 MCD_contextSave14[128]; /* Task 14 context save space */
u32 MCD_contextSave15[128]; /* Task 15 context save space */
u32 MCD_ChainNoEu_TDT[];
u32 MCD_SingleNoEu_TDT[];
#ifdef MCD_INCLUDE_EU
u32 MCD_ChainEu_TDT[];
u32 MCD_SingleEu_TDT[];
#endif
u32 MCD_ENetRcv_TDT[];
u32 MCD_ENetXmit_TDT[];
u32 MCD_modelTaskTableSrc[] = {
(u32) MCD_ChainNoEu_TDT,
(u32) & ((u8 *) MCD_ChainNoEu_TDT)[0x0000016c],
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_SingleNoEu_TDT,
(u32) & ((u8 *) MCD_SingleNoEu_TDT)[0x000000d4],
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
#ifdef MCD_INCLUDE_EU
(u32) MCD_ChainEu_TDT,
(u32) & ((u8 *) MCD_ChainEu_TDT)[0x000001b4],
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_SingleEu_TDT,
(u32) & ((u8 *) MCD_SingleEu_TDT)[0x00000124],
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
#endif
(u32) MCD_ENetRcv_TDT,
(u32) & ((u8 *) MCD_ENetRcv_TDT)[0x0000009c],
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
(u32) MCD_ENetXmit_TDT,
(u32) & ((u8 *) MCD_ENetXmit_TDT)[0x000000d0],
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
};
u32 MCD_ChainNoEu_TDT[] = {
0x80004000,
0x8118801b,
0xb8c60018,
0x10002b10,
0x7000000d,
0x018cf89f,
0x6000000a,
0x080cf89f,
0x000001f8,
0x98180364,
0x8118801b,
0xf8c6001a,
0xb8c6601b,
0x10002710,
0x00000f18,
0xb8c6001d,
0x10001310,
0x60000007,
0x014cf88b,
0x98c6001c,
0x00000710,
0x98c70018,
0x10001f10,
0x0000c818,
0x000001f8,
0xc1476018,
0xc003231d,
0x811a601b,
0xc1862102,
0x849be009,
0x03fed7b8,
0xda9b001b,
0x9b9be01b,
0x1000cb20,
0x70000006,
0x088cf88f,
0x1000cb28,
0x70000006,
0x088cf88f,
0x1000cb30,
0x70000006,
0x088cf88f,
0x1000cb38,
0x0000c728,
0x000001f8,
0xc1476018,
0xc003241d,
0x811a601b,
0xda9b001b,
0x9b9be01b,
0x0000d3a0,
0xc1862102,
0x849be009,
0x0bfed7b8,
0xda9b001b,
0x9b9be01b,
0x1000cb20,
0x70000006,
0x088cf88f,
0x1000cb28,
0x70000006,
0x088cf88f,
0x1000cb30,
0x70000006,
0x088cf88f,
0x1000cb38,
0x0000c728,
0x000001f8,
0x8118801b,
0xd8c60018,
0x98c6601c,
0x6000000b,
0x0c8cfc9f,
0x000001f8,
0xa146001e,
0x10000b08,
0x10002050,
0xb8c60018,
0x10002b10,
0x7000000a,
0x080cf89f,
0x6000000d,
0x018cf89f,
0x000001f8,
0x8618801b,
0x7000000e,
0x084cf21f,
0xd8990336,
0x8019801b,
0x040001f8,
0x000001f8,
0x000001f8,
};
u32 MCD_SingleNoEu_TDT[] = {
0x8198001b,
0x7000000d,
0x080cf81f,
0x8198801b,
0x6000000e,
0x084cf85f,
0x000001f8,
0x8298001b,
0x7000000d,
0x010cf81f,
0x6000000e,
0x018cf81f,
0xc202601b,
0xc002221c,
0x809a601b,
0xc10420c2,
0x839be009,
0x03fed7b8,
0xda9b001b,
0x9b9be01b,
0x70000006,
0x088cf889,
0x1000cb28,
0x70000006,
0x088cf889,
0x1000cb30,
0x70000006,
0x088cf889,
0x0000cb38,
0x000001f8,
0xc202601b,
0xc002229c,
0x809a601b,
0xda9b001b,
0x9b9be01b,
0x0000d3a0,
0xc10420c2,
0x839be009,
0x0bfed7b8,
0xda9b001b,
0x9b9be01b,
0x70000006,
0x088cf889,
0x1000cb28,
0x70000006,
0x088cf889,
0x1000cb30,
0x70000006,
0x088cf889,
0x0000cb38,
0x000001f8,
0xc318022d,
0x8018801b,
0x040001f8,
};
#ifdef MCD_INCLUDE_EU
u32 MCD_ChainEu_TDT[] = {
0x80004000,
0x8198801b,
0xb8c68018,
0x10002f10,
0x7000000d,
0x01ccf89f,
0x6000000a,
0x080cf89f,
0x000001f8,
0x981803a4,
0x8198801b,
0xf8c6801a,
0xb8c6e01b,
0x10002b10,
0x00001318,
0xb8c6801d,
0x10001710,
0x60000007,
0x018cf88c,
0x98c6801c,
0x00000b10,
0x98c78018,
0x10002310,
0x0000c820,
0x000001f8,
0x8698801b,
0x7000000f,
0x084cf2df,
0xd899042d,
0x8019801b,
0x60000003,
0x2cd7c7df,
0xd8990364,
0x8019801b,
0x60000003,
0x2c17c7df,
0x000001f8,
0xc1c7e018,
0xc003a35e,
0x819a601b,
0xc206a142,
0x851be009,
0x63fe0000,
0x0d4cfddf,
0xda9b001b,
0x9b9be01b,
0x70000002,
0x004cf81f,
0x1000cb20,
0x70000006,
0x088cf891,
0x1000cb28,
0x70000006,
0x088cf891,
0x1000cb30,
0x70000006,
0x088cf891,
0x1000cb38,
0x0000c728,
0x000001f8,
0xc1c7e018,
0xc003a49e,
0x819a601b,
0xda9b001b,
0x9b9be01b,
0x0000d3a0,
0xc206a142,
0x851be009,
0x6bfe0000,
0x0d4cfddf,
0xda9b001b,
0x9b9be01b,
0x70000002,
0x004cf81f,
0x1000cb20,
0x70000006,
0x088cf891,
0x1000cb28,
0x70000006,
0x088cf891,
0x1000cb30,
0x70000006,
0x088cf891,
0x1000cb38,
0x0000c728,
0x000001f8,
0x8198801b,
0xd8c68018,
0x98c6e01c,
0x6000000b,
0x0c8cfc9f,
0x0000cc08,
0xa1c6801e,
0x10000f08,
0x10002458,
0xb8c68018,
0x10002f10,
0x7000000a,
0x080cf89f,
0x6000000d,
0x01ccf89f,
0x000001f8,
0x8698801b,
0x7000000e,
0x084cf25f,
0xd899037f,
0x8019801b,
0x040001f8,
0x000001f8,
0x000001f8,
};
u32 MCD_SingleEu_TDT[] = {
0x8218001b,
0x7000000d,
0x080cf81f,
0x8218801b,
0x6000000e,
0x084cf85f,
0x000001f8,
0x8318001b,
0x7000000d,
0x014cf81f,
0x6000000e,
0x01ccf81f,
0x8498001b,
0x7000000f,
0x080cf19f,
0xd81882a4,
0x8019001b,
0x60000003,
0x2c97c7df,
0xd818826d,
0x8019001b,
0x60000003,
0x2c17c7df,
0x000001f8,
0xc282e01b,
0xc002a25e,
0x811a601b,
0xc184a102,
0x841be009,
0x63fe0000,
0x0d4cfddf,
0xda9b001b,
0x9b9be01b,
0x70000002,
0x004cf99f,
0x70000006,
0x088cf88b,
0x1000cb28,
0x70000006,
0x088cf88b,
0x1000cb30,
0x70000006,
0x088cf88b,
0x0000cb38,
0x000001f8,
0xc282e01b,
0xc002a31e,
0x811a601b,
0xda9b001b,
0x9b9be01b,
0x0000d3a0,
0xc184a102,
0x841be009,
0x6bfe0000,
0x0d4cfddf,
0xda9b001b,
0x9b9be01b,
0x70000002,
0x004cf99f,
0x70000006,
0x088cf88b,
0x1000cb28,
0x70000006,
0x088cf88b,
0x1000cb30,
0x70000006,
0x088cf88b,
0x0000cb38,
0x000001f8,
0x8144801c,
0x0000c008,
0xc398027f,
0x8018801b,
0x040001f8,
};
#endif
u32 MCD_ENetRcv_TDT[] = {
0x80004000,
0x81988000,
0x10000788,
0x6000000a,
0x080cf05f,
0x98180209,
0x81c40004,
0x7000000e,
0x010cf05f,
0x7000000c,
0x01ccf05f,
0x70000004,
0x014cf049,
0x70000004,
0x004cf04a,
0x00000b88,
0xc4030150,
0x8119e012,
0x03e0cf90,
0x81188000,
0x000ac788,
0xc4030000,
0x8199e000,
0x70000004,
0x084cfc8b,
0x60000005,
0x0cccf841,
0x81c60000,
0xc399021b,
0x80198000,
0x00008400,
0x00000f08,
0x81988000,
0x10000788,
0x6000000a,
0x080cf05f,
0xc2188209,
0x80190000,
0x040001f8,
0x000001f8,
};
u32 MCD_ENetXmit_TDT[] = {
0x80004000,
0x81988000,
0x10000788,
0x6000000a,
0x080cf05f,
0x98180309,
0x80004003,
0x81c60004,
0x7000000e,
0x014cf05f,
0x7000000c,
0x028cf05f,
0x7000000d,
0x018cf05f,
0x70000004,
0x01ccf04d,
0x10000b90,
0x60000004,
0x020cf0a1,
0xc3188312,
0x83c70000,
0x00001f10,
0xc583a3c3,
0x81042325,
0x03e0c798,
0xd8990000,
0x9999e000,
0x000acf98,
0xd8992306,
0x9999e03f,
0x03eac798,
0xd8990000,
0x9999e000,
0x000acf98,
0xd8990000,
0x99832302,
0x0beac798,
0x81988000,
0x6000000b,
0x0c4cfc5f,
0x81c80000,
0xc5190312,
0x80198000,
0x00008400,
0x00000f08,
0x81988000,
0x10000788,
0x6000000a,
0x080cf05f,
0xc2988309,
0x80190000,
0x040001f8,
0x000001f8,
};
#ifdef MCD_INCLUDE_EU
MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
#endif
|
1001-study-uboot
|
drivers/dma/MCD_tasks.c
|
C
|
gpl3
| 36,621
|
/* Copyright (C) 2011
* Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This is a basic implementation of the SDMA/DMA4 controller of OMAP3
* Tested on Silicon Revision major:0x4 minor:0x0
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
#include <asm/arch/dma.h>
#include <asm/io.h>
#include <asm/errno.h>
static struct dma4 *dma4_cfg = (struct dma4 *)OMAP34XX_DMA4_BASE;
uint32_t dma_active; /* if a transfer is started the respective
bit is set for the logical channel */
/* Check if we have the given channel
* PARAMETERS:
* chan: Channel number
*
* RETURN of non-zero means error */
static inline int check_channel(uint32_t chan)
{
if (chan < CHAN_NR_MIN || chan > CHAN_NR_MAX)
return -EINVAL;
return 0;
}
static inline void reset_irq(uint32_t chan)
{
/* reset IRQ reason */
writel(0x1DFE, &dma4_cfg->chan[chan].csr);
/* reset IRQ */
writel((1 << chan), &dma4_cfg->irqstatus_l[0]);
dma_active &= ~(1 << chan);
}
/* Set Source, Destination and Size of DMA transfer for the
* specified channel.
* PARAMETERS:
* chan: channel to use
* src: source of the transfer
* dst: destination of the transfer
* sze: Size of the transfer
*
* RETURN of non-zero means error */
int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
uint32_t sze)
{
if (check_channel(chan))
return -EINVAL;
/* CDSA0 */
writel((uint32_t)src, &dma4_cfg->chan[chan].cssa);
writel((uint32_t)dst, &dma4_cfg->chan[chan].cdsa);
writel(sze, &dma4_cfg->chan[chan].cen);
return 0;
}
/* Start the DMA transfer */
int omap3_dma_start_transfer(uint32_t chan)
{
uint32_t val;
if (check_channel(chan))
return -EINVAL;
val = readl(&dma4_cfg->chan[chan].ccr);
/* Test for channel already in use */
if (val & CCR_ENABLE_ENABLE)
return -EBUSY;
writel((val | CCR_ENABLE_ENABLE), &dma4_cfg->chan[chan].ccr);
dma_active |= (1 << chan);
debug("started transfer...\n");
return 0;
}
/* Busy-waiting for a DMA transfer
* This has to be called before another transfer is started
* PARAMETER
* chan: Channel to wait for
*
* RETURN of non-zero means error*/
int omap3_dma_wait_for_transfer(uint32_t chan)
{
uint32_t val;
if (!(dma_active & (1 << chan))) {
val = readl(&dma4_cfg->irqstatus_l[0]);
if (!(val & chan)) {
debug("dma: The channel you are trying to wait for "
"was never activated - ERROR\n");
return -1; /* channel was never active */
}
}
/* all irqs on line 0 */
while (!(readl(&dma4_cfg->irqstatus_l[0]) & (1 << chan)))
asm("nop");
val = readl(&dma4_cfg->chan[chan].csr);
if ((val & CSR_TRANS_ERR) | (val & CSR_SUPERVISOR_ERR) |
(val & CSR_MISALIGNED_ADRS_ERR)) {
debug("err code: %X\n", val);
debug("dma: transfer error detected\n");
reset_irq(chan);
return -1;
}
reset_irq(chan);
return 0;
}
/* Get the revision of the DMA module
* PARAMETER
* minor: Address of minor revision to write
* major: Address of major revision to write
*
* RETURN of non-zero means error
*/
int omap3_dma_get_revision(uint32_t *minor, uint32_t *major)
{
uint32_t val;
/* debug information */
val = readl(&dma4_cfg->revision);
*major = (val & 0x000000F0) >> 4;
*minor = (val & 0x0000000F);
debug("DMA Silicon revision (maj/min): 0x%X/0x%X\n", *major, *minor);
return 0;
}
/* Initial config of omap dma
*/
void omap3_dma_init(void)
{
dma_active = 0;
/* All interrupts on channel 0 */
writel(0xFFFFFFFF, &dma4_cfg->irqenable_l[0]);
}
/* set channel config to config
*
* RETURN of non-zero means error */
int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config)
{
if (check_channel(chan))
return -EINVAL;
dma4_cfg->chan[chan] = *config;
return 0;
}
/* get channel config to config
*
* RETURN of non-zero means error */
int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config)
{
if (check_channel(chan))
return -EINVAL;
*config = dma4_cfg->chan[chan];
return 0;
}
|
1001-study-uboot
|
drivers/dma/omap3_dma.c
|
C
|
gpl3
| 4,642
|
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libdma.o
COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
COBJS-$(CONFIG_APBH_DMA) += apbh_dma.o
COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/dma/Makefile
|
Makefile
|
gpl3
| 1,492
|
/*
* Freescale i.MX28 APBH DMA driver
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/list.h>
#include <common.h>
#include <malloc.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/dma.h>
static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
/*
* Test is the DMA channel is valid channel
*/
int mxs_dma_validate_chan(int channel)
{
struct mxs_dma_chan *pchan;
if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
return -EINVAL;
pchan = mxs_dma_channels + channel;
if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
return -EINVAL;
return 0;
}
/*
* Return the address of the command within a descriptor.
*/
static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
{
return desc->address + offsetof(struct mxs_dma_desc, cmd);
}
/*
* Read a DMA channel's hardware semaphore.
*
* As used by the MXS platform's DMA software, the DMA channel's hardware
* semaphore reflects the number of DMA commands the hardware will process, but
* has not yet finished. This is a volatile value read directly from hardware,
* so it must be be viewed as immediately stale.
*
* If the channel is not marked busy, or has finished processing all its
* commands, this value should be zero.
*
* See mxs_dma_append() for details on how DMA command blocks must be configured
* to maintain the expected behavior of the semaphore's value.
*/
static int mxs_dma_read_semaphore(int channel)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
uint32_t tmp;
int ret;
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);
tmp &= APBH_CHn_SEMA_PHORE_MASK;
tmp >>= APBH_CHn_SEMA_PHORE_OFFSET;
return tmp;
}
/*
* Enable a DMA channel.
*
* If the given channel has any DMA descriptors on its active list, this
* function causes the DMA hardware to begin processing them.
*
* This function marks the DMA channel as "busy," whether or not there are any
* descriptors to process.
*/
static int mxs_dma_enable(int channel)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
unsigned int sem;
struct mxs_dma_chan *pchan;
struct mxs_dma_desc *pdesc;
int ret;
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
pchan = mxs_dma_channels + channel;
if (pchan->pending_num == 0) {
pchan->flags |= MXS_DMA_FLAGS_BUSY;
return 0;
}
pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
if (pdesc == NULL)
return -EFAULT;
if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
return 0;
sem = mxs_dma_read_semaphore(channel);
if (sem == 0)
return 0;
if (sem == 1) {
pdesc = list_entry(pdesc->node.next,
struct mxs_dma_desc, node);
writel(mxs_dma_cmd_address(pdesc),
&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
}
writel(pchan->pending_num,
&apbh_regs->ch[channel].hw_apbh_ch_sema);
pchan->active_num += pchan->pending_num;
pchan->pending_num = 0;
} else {
pchan->active_num += pchan->pending_num;
pchan->pending_num = 0;
writel(mxs_dma_cmd_address(pdesc),
&apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
writel(pchan->active_num,
&apbh_regs->ch[channel].hw_apbh_ch_sema);
writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
&apbh_regs->hw_apbh_ctrl0_clr);
}
pchan->flags |= MXS_DMA_FLAGS_BUSY;
return 0;
}
/*
* Disable a DMA channel.
*
* This function shuts down a DMA channel and marks it as "not busy." Any
* descriptors on the active list are immediately moved to the head of the
* "done" list, whether or not they have actually been processed by the
* hardware. The "ready" flags of these descriptors are NOT cleared, so they
* still appear to be active.
*
* This function immediately shuts down a DMA channel's hardware, aborting any
* I/O that may be in progress, potentially leaving I/O hardware in an undefined
* state. It is unwise to call this function if there is ANY chance the hardware
* is still processing a command.
*/
static int mxs_dma_disable(int channel)
{
struct mxs_dma_chan *pchan;
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
pchan = mxs_dma_channels + channel;
if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
return -EINVAL;
writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
&apbh_regs->hw_apbh_ctrl0_set);
pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
pchan->active_num = 0;
pchan->pending_num = 0;
list_splice_init(&pchan->active, &pchan->done);
return 0;
}
/*
* Resets the DMA channel hardware.
*/
static int mxs_dma_reset(int channel)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
writel(1 << (channel + APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET),
&apbh_regs->hw_apbh_channel_ctrl_set);
return 0;
}
/*
* Enable or disable DMA interrupt.
*
* This function enables the given DMA channel to interrupt the CPU.
*/
static int mxs_dma_enable_irq(int channel, int enable)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
if (enable)
writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
&apbh_regs->hw_apbh_ctrl1_set);
else
writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
&apbh_regs->hw_apbh_ctrl1_clr);
return 0;
}
/*
* Clear DMA interrupt.
*
* The software that is using the DMA channel must register to receive its
* interrupts and, when they arrive, must call this function to clear them.
*/
static int mxs_dma_ack_irq(int channel)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);
writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);
return 0;
}
/*
* Request to reserve a DMA channel
*/
static int mxs_dma_request(int channel)
{
struct mxs_dma_chan *pchan;
if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
return -EINVAL;
pchan = mxs_dma_channels + channel;
if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
return -ENODEV;
if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
return -EBUSY;
pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
pchan->active_num = 0;
pchan->pending_num = 0;
INIT_LIST_HEAD(&pchan->active);
INIT_LIST_HEAD(&pchan->done);
return 0;
}
/*
* Release a DMA channel.
*
* This function releases a DMA channel from its current owner.
*
* The channel will NOT be released if it's marked "busy" (see
* mxs_dma_enable()).
*/
static int mxs_dma_release(int channel)
{
struct mxs_dma_chan *pchan;
int ret;
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
pchan = mxs_dma_channels + channel;
if (pchan->flags & MXS_DMA_FLAGS_BUSY)
return -EBUSY;
pchan->dev = 0;
pchan->active_num = 0;
pchan->pending_num = 0;
pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
return 0;
}
/*
* Allocate DMA descriptor
*/
struct mxs_dma_desc *mxs_dma_desc_alloc(void)
{
struct mxs_dma_desc *pdesc;
pdesc = memalign(MXS_DMA_ALIGNMENT, sizeof(struct mxs_dma_desc));
if (pdesc == NULL)
return NULL;
memset(pdesc, 0, sizeof(*pdesc));
pdesc->address = (dma_addr_t)pdesc;
return pdesc;
};
/*
* Free DMA descriptor
*/
void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
{
if (pdesc == NULL)
return;
free(pdesc);
}
/*
* Add a DMA descriptor to a channel.
*
* If the descriptor list for this channel is not empty, this function sets the
* CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
* it will chain to the new descriptor's command.
*
* Then, this function marks the new descriptor as "ready," adds it to the end
* of the active descriptor list, and increments the count of pending
* descriptors.
*
* The MXS platform DMA software imposes some rules on DMA commands to maintain
* important invariants. These rules are NOT checked, but they must be carefully
* applied by software that uses MXS DMA channels.
*
* Invariant:
* The DMA channel's hardware semaphore must reflect the number of DMA
* commands the hardware will process, but has not yet finished.
*
* Explanation:
* A DMA channel begins processing commands when its hardware semaphore is
* written with a value greater than zero, and it stops processing commands
* when the semaphore returns to zero.
*
* When a channel finishes a DMA command, it will decrement its semaphore if
* the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
*
* In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
* unless it suits the purposes of the software. For example, one could
* construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
* bit set only in the last one. Then, setting the DMA channel's hardware
* semaphore to one would cause the entire series of five commands to be
* processed. However, this example would violate the invariant given above.
*
* Rule:
* ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
* channel's hardware semaphore will be decremented EVERY time a command is
* processed.
*/
int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
{
struct mxs_dma_chan *pchan;
struct mxs_dma_desc *last;
int ret;
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
pchan = mxs_dma_channels + channel;
pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
if (!list_empty(&pchan->active)) {
last = list_entry(pchan->active.prev, struct mxs_dma_desc,
node);
pdesc->flags &= ~MXS_DMA_DESC_FIRST;
last->flags &= ~MXS_DMA_DESC_LAST;
last->cmd.next = mxs_dma_cmd_address(pdesc);
last->cmd.data |= MXS_DMA_DESC_CHAIN;
}
pdesc->flags |= MXS_DMA_DESC_READY;
if (pdesc->flags & MXS_DMA_DESC_FIRST)
pchan->pending_num++;
list_add_tail(&pdesc->node, &pchan->active);
return ret;
}
/*
* Clean up processed DMA descriptors.
*
* This function removes processed DMA descriptors from the "active" list. Pass
* in a non-NULL list head to get the descriptors moved to your list. Pass NULL
* to get the descriptors moved to the channel's "done" list. Descriptors on
* the "done" list can be retrieved with mxs_dma_get_finished().
*
* This function marks the DMA channel as "not busy" if no unprocessed
* descriptors remain on the "active" list.
*/
static int mxs_dma_finish(int channel, struct list_head *head)
{
int sem;
struct mxs_dma_chan *pchan;
struct list_head *p, *q;
struct mxs_dma_desc *pdesc;
int ret;
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
pchan = mxs_dma_channels + channel;
sem = mxs_dma_read_semaphore(channel);
if (sem < 0)
return sem;
if (sem == pchan->active_num)
return 0;
list_for_each_safe(p, q, &pchan->active) {
if ((pchan->active_num) <= sem)
break;
pdesc = list_entry(p, struct mxs_dma_desc, node);
pdesc->flags &= ~MXS_DMA_DESC_READY;
if (head)
list_move_tail(p, head);
else
list_move_tail(p, &pchan->done);
if (pdesc->flags & MXS_DMA_DESC_LAST)
pchan->active_num--;
}
if (sem == 0)
pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
return 0;
}
/*
* Wait for DMA channel to complete
*/
static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
int ret;
ret = mxs_dma_validate_chan(chan);
if (ret)
return ret;
if (mx28_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
1 << chan, timeout)) {
ret = -ETIMEDOUT;
mxs_dma_reset(chan);
}
return ret;
}
/*
* Execute the DMA channel
*/
int mxs_dma_go(int chan)
{
uint32_t timeout = 10000;
int ret;
LIST_HEAD(tmp_desc_list);
mxs_dma_enable_irq(chan, 1);
mxs_dma_enable(chan);
/* Wait for DMA to finish. */
ret = mxs_dma_wait_complete(timeout, chan);
/* Clear out the descriptors we just ran. */
mxs_dma_finish(chan, &tmp_desc_list);
/* Shut the DMA channel down. */
mxs_dma_ack_irq(chan);
mxs_dma_reset(chan);
mxs_dma_enable_irq(chan, 0);
mxs_dma_disable(chan);
return ret;
}
/*
* Initialize the DMA hardware
*/
int mxs_dma_init(void)
{
struct mx28_apbh_regs *apbh_regs =
(struct mx28_apbh_regs *)MXS_APBH_BASE;
struct mxs_dma_chan *pchan;
int ret, channel;
mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
#ifdef CONFIG_APBH_DMA_BURST8
writel(APBH_CTRL0_AHB_BURST8_EN,
&apbh_regs->hw_apbh_ctrl0_set);
#else
writel(APBH_CTRL0_AHB_BURST8_EN,
&apbh_regs->hw_apbh_ctrl0_clr);
#endif
#ifdef CONFIG_APBH_DMA_BURST
writel(APBH_CTRL0_APB_BURST_EN,
&apbh_regs->hw_apbh_ctrl0_set);
#else
writel(APBH_CTRL0_APB_BURST_EN,
&apbh_regs->hw_apbh_ctrl0_clr);
#endif
for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
pchan = mxs_dma_channels + channel;
pchan->flags = MXS_DMA_FLAGS_VALID;
ret = mxs_dma_request(channel);
if (ret) {
printf("MXS DMA: Can't acquire DMA channel %i\n",
channel);
goto err;
}
mxs_dma_reset(channel);
mxs_dma_ack_irq(channel);
}
return 0;
err:
while (--channel >= 0)
mxs_dma_release(channel);
return ret;
}
|
1001-study-uboot
|
drivers/dma/apbh_dma.c
|
C
|
gpl3
| 14,386
|
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
/* Functions for initializing variable tables of different types of tasks. */
/*
* Do not edit!
*/
#include <MCD_dma.h>
extern dmaRegs *MCD_dmaBar;
/* Task 0 */
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
int xferSize, short xferSizeIncr, int *cSave,
volatile TaskTableEntry * taskTable, int channel)
{
volatile TaskTableEntry *taskChan = taskTable + channel;
MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskChan, 11, (u32) xferSize); /* var[11] */
MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
MCD_SET_VAR(taskChan, 3, (u32) 0x00000000); /* var[3] */
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
MCD_SET_VAR(taskChan, 13, (u32) 0x80000000); /* var[13] */
MCD_SET_VAR(taskChan, 14, (u32) 0x00000010); /* var[14] */
MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
MCD_SET_VAR(taskChan, 16, (u32) 0x08000000); /* var[16] */
MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
MCD_SET_VAR(taskChan, 29, (u32) 0x80000001); /* inc[5] */
MCD_SET_VAR(taskChan, 30, (u32) 0x40000000); /* inc[6] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
}
/* Task 1 */
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
short destIncr, int dmaSize, short xferSizeIncr,
int flags, int *currBD, int *cSave,
volatile TaskTableEntry * taskTable, int channel)
{
volatile TaskTableEntry *taskChan = taskTable + channel;
MCD_SET_VAR(taskChan, 7, (u32) srcAddr); /* var[7] */
MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskChan, 2, (u32) destAddr); /* var[2] */
MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskChan, 3, (u32) dmaSize); /* var[3] */
MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskChan, 5, (u32) flags); /* var[5] */
MCD_SET_VAR(taskChan, 1, (u32) currBD); /* var[1] */
MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
MCD_SET_VAR(taskChan, 9, (u32) 0x00000004); /* var[9] */
MCD_SET_VAR(taskChan, 10, (u32) 0x08000000); /* var[10] */
MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
MCD_SET_VAR(taskChan, 28, (u32) 0x80000001); /* inc[4] */
MCD_SET_VAR(taskChan, 29, (u32) 0x40000000); /* inc[5] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
}
/* Task 2 */
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
int xferSize, short xferSizeIncr, int *cSave,
volatile TaskTableEntry * taskTable, int channel)
{
volatile TaskTableEntry *taskChan = taskTable + channel;
MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskChan, 12, (u32) xferSize); /* var[12] */
MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
MCD_SET_VAR(taskChan, 11, (u32) 0x00000000); /* var[11] */
MCD_SET_VAR(taskChan, 13, (u32) 0x00000000); /* var[13] */
MCD_SET_VAR(taskChan, 14, (u32) 0x80000000); /* var[14] */
MCD_SET_VAR(taskChan, 15, (u32) 0x00000010); /* var[15] */
MCD_SET_VAR(taskChan, 16, (u32) 0x00000001); /* var[16] */
MCD_SET_VAR(taskChan, 17, (u32) 0x00000004); /* var[17] */
MCD_SET_VAR(taskChan, 18, (u32) 0x08000000); /* var[18] */
MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */
MCD_SET_VAR(taskChan, 29, (u32) 0xc0000000); /* inc[5] */
MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
}
/* Task 3 */
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
short destIncr, int dmaSize, short xferSizeIncr,
int flags, int *currBD, int *cSave,
volatile TaskTableEntry * taskTable, int channel)
{
volatile TaskTableEntry *taskChan = taskTable + channel;
MCD_SET_VAR(taskChan, 8, (u32) srcAddr); /* var[8] */
MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskChan, 3, (u32) destAddr); /* var[3] */
MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskChan, 4, (u32) dmaSize); /* var[4] */
MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskChan, 6, (u32) flags); /* var[6] */
MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */
MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
MCD_SET_VAR(taskChan, 10, (u32) 0x00000001); /* var[10] */
MCD_SET_VAR(taskChan, 11, (u32) 0x00000004); /* var[11] */
MCD_SET_VAR(taskChan, 12, (u32) 0x08000000); /* var[12] */
MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */
MCD_SET_VAR(taskChan, 28, (u32) 0xc0000000); /* inc[4] */
MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */
MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
}
/* Task 4 */
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
volatile TaskTableEntry * taskTable, int channel)
{
volatile TaskTableEntry *taskChan = taskTable + channel;
MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
MCD_SET_VAR(taskChan, 6, (u32) rcvFifoPtr); /* var[6] */
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
MCD_SET_VAR(taskChan, 9, (u32) 0x0000ffff); /* var[9] */
MCD_SET_VAR(taskChan, 10, (u32) 0x30000000); /* var[10] */
MCD_SET_VAR(taskChan, 11, (u32) 0x0fffffff); /* var[11] */
MCD_SET_VAR(taskChan, 12, (u32) 0x00000008); /* var[12] */
MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
MCD_SET_VAR(taskChan, 26, (u32) 0x20000004); /* inc[2] */
MCD_SET_VAR(taskChan, 27, (u32) 0x40000000); /* inc[3] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
}
/* Task 5 */
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
volatile TaskTableEntry * taskTable, int channel)
{
volatile TaskTableEntry *taskChan = taskTable + channel;
MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */
MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */
MCD_SET_VAR(taskChan, 11, (u32) xmitFifoPtr); /* var[11] */
MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */
MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */
MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */
MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */
MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */
MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */
MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */
MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */
MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */
MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */
MCD_SET_VAR(taskChan, 13, (u32) 0x0000ffff); /* var[13] */
MCD_SET_VAR(taskChan, 14, (u32) 0xffffffff); /* var[14] */
MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */
MCD_SET_VAR(taskChan, 16, (u32) 0x00000008); /* var[16] */
MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */
MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */
MCD_SET_VAR(taskChan, 26, (u32) 0x40000000); /* inc[2] */
MCD_SET_VAR(taskChan, 27, (u32) 0xc000fffc); /* inc[3] */
MCD_SET_VAR(taskChan, 28, (u32) 0xe0000004); /* inc[4] */
MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */
MCD_SET_VAR(taskChan, 30, (u32) 0x4000ffff); /* inc[6] */
MCD_SET_VAR(taskChan, 31, (u32) 0xe0000001); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16) 0x8000;
}
|
1001-study-uboot
|
drivers/dma/MCD_tasksInit.c
|
C
|
gpl3
| 11,185
|
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*Main C file for multi-channel DMA API. */
#include <common.h>
#include <MCD_dma.h>
#include <MCD_tasksInit.h>
#include <MCD_progCheck.h>
/********************************************************************/
/* This is an API-internal pointer to the DMA's registers */
dmaRegs *MCD_dmaBar;
/*
* These are the real and model task tables as generated by the
* build process
*/
extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
/*
* However, this (usually) gets relocated to on-chip SRAM, at which
* point we access them as these tables
*/
volatile TaskTableEntry *MCD_taskTable;
TaskTableEntry *MCD_modelTaskTable;
/*
* MCD_chStatus[] is an array of status indicators for remembering
* whether a DMA has ever been attempted on each channel, pausing
* status, etc.
*/
static int MCD_chStatus[NCHANNELS] = {
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
};
/* Prototypes for local functions */
static void MCD_memcpy(int *dest, int *src, u32 size);
static void MCD_resmActions(int channel);
/*
* Buffer descriptors used for storage of progress info for single Dmas
* Also used as storage for the DMA for CRCs for single DMAs
* Otherwise, the DMA does not parse these buffer descriptors
*/
#ifdef MCD_INCLUDE_EU
extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
#else
MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
#endif
MCD_bufDesc *MCD_relocBuffDesc;
/* Defines for the debug control register's functions */
#define DBG_CTL_COMP1_TASK (0x00002000)
#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \
DBG_CTL_BREAK | \
DBG_CTL_INT_BREAK | \
DBG_CTL_COMP1_TASK)
#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \
DBG_CTL_INT_BREAK | \
DBG_CTL_COMP1_TASK)
#define DBG_KILL_ALL_STAT (0xFFFFFFFF)
/* Offset to context save area where progress info is stored */
#define CSAVE_OFFSET 10
/* Defines for Byte Swapping */
#define MCD_BYTE_SWAP_KILLER 0xFFF8888F
#define MCD_NO_BYTE_SWAP_ATALL 0x00040000
/* Execution Unit Identifiers */
#define MAC 0 /* legacy - not used */
#define LUAC 1 /* legacy - not used */
#define CRC 2 /* legacy - not used */
#define LURC 3 /* Logic Unit with CRC */
/* Task Identifiers */
#define TASK_CHAINNOEU 0
#define TASK_SINGLENOEU 1
#ifdef MCD_INCLUDE_EU
#define TASK_CHAINEU 2
#define TASK_SINGLEEU 3
#define TASK_FECRX 4
#define TASK_FECTX 5
#else
#define TASK_CHAINEU 0
#define TASK_SINGLEEU 1
#define TASK_FECRX 2
#define TASK_FECTX 3
#endif
/*
* Structure to remember which variant is on which channel
* TBD- need this?
*/
typedef struct MCD_remVariants_struct MCD_remVariant;
struct MCD_remVariants_struct {
int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */
int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */
s16 remDestIncr[NCHANNELS]; /* DestIncr */
s16 remSrcIncr[NCHANNELS]; /* srcIncr */
u32 remXferSize[NCHANNELS]; /* xferSize */
};
/* Structure to remember the startDma parameters for each channel */
MCD_remVariant MCD_remVariants;
/********************************************************************/
/* Function: MCD_initDma
* Purpose: Initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task
* structures, and setting up some global settings
* Arguments:
* dmaBarAddr - pointer to the multichannel DMA registers
* taskTableDest - location to move DMA task code and structs to
* flags - operational parameters
* Return Value:
* MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
* MCD_OK otherwise
*/
extern u32 MCD_funcDescTab0[];
int MCD_initDma(dmaRegs * dmaBarAddr, void *taskTableDest, u32 flags)
{
int i;
TaskTableEntry *entryPtr;
/* setup the local pointer to register set */
MCD_dmaBar = dmaBarAddr;
/* do we need to move/create a task table */
if ((flags & MCD_RELOC_TASKS) != 0) {
int fixedSize;
u32 *fixedPtr;
/*int *tablePtr = taskTableDest;TBD */
int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
int taskDescTabsOffset;
int taskTableSize, varTabsSize, funcDescTabsSize,
contextSavesSize;
int taskDescTabSize;
int i;
/* check if physical address is aligned on 512 byte boundary */
if (((u32) taskTableDest & 0x000001ff) != 0)
return (MCD_TABLE_UNALIGNED);
/* set up local pointer to task Table */
MCD_taskTable = taskTableDest;
/*
* Create a task table:
* - compute aligned base offsets for variable tables and
* function descriptor tables, then
* - loop through the task table and setup the pointers
* - copy over model task table with the the actual task
* descriptor tables
*/
taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
/* align variable tables to size */
varTabsOffset = taskTableSize + (u32) taskTableDest;
if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
varTabsOffset =
(varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
/* align function descriptor tables */
varTabsSize = NCHANNELS * VAR_TAB_SIZE;
funcDescTabsOffset = varTabsOffset + varTabsSize;
if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
funcDescTabsOffset =
(funcDescTabsOffset +
FUNCDESC_TAB_SIZE) & (~FUNCDESC_TAB_SIZE);
funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
fixedSize =
taskTableSize + varTabsSize + funcDescTabsSize +
contextSavesSize;
/* zero the thing out */
fixedPtr = (u32 *) taskTableDest;
for (i = 0; i < (fixedSize / 4); i++)
fixedPtr[i] = 0;
entryPtr = (TaskTableEntry *) MCD_taskTable;
/* set up fixed pointers */
for (i = 0; i < NCHANNELS; i++) {
/* update ptr to local value */
entryPtr[i].varTab = (u32) varTabsOffset;
entryPtr[i].FDTandFlags =
(u32) funcDescTabsOffset | MCD_TT_FLAGS_DEF;
entryPtr[i].contextSaveSpace = (u32) contextSavesOffset;
varTabsOffset += VAR_TAB_SIZE;
#ifdef MCD_INCLUDE_EU
/* if not there is only one, just point to the
same one */
funcDescTabsOffset += FUNCDESC_TAB_SIZE;
#endif
contextSavesOffset += CONTEXT_SAVE_SIZE;
}
/* copy over the function descriptor table */
for (i = 0; i < FUNCDESC_TAB_NUM; i++) {
MCD_memcpy((void *)(entryPtr[i].
FDTandFlags & ~MCD_TT_FLAGS_MASK),
(void *)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
}
/* copy model task table to where the context saves stuff
leaves off */
MCD_modelTaskTable = (TaskTableEntry *) contextSavesOffset;
MCD_memcpy((void *)MCD_modelTaskTable,
(void *)MCD_modelTaskTableSrc,
NUMOFVARIANTS * sizeof(TaskTableEntry));
/* point to local version of model task table */
entryPtr = MCD_modelTaskTable;
taskDescTabsOffset = (u32) MCD_modelTaskTable +
(NUMOFVARIANTS * sizeof(TaskTableEntry));
/* copy actual task code and update TDT ptrs in local
model task table */
for (i = 0; i < NUMOFVARIANTS; i++) {
taskDescTabSize =
entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
MCD_memcpy((void *)taskDescTabsOffset,
(void *)entryPtr[i].TDTstart,
taskDescTabSize);
entryPtr[i].TDTstart = (u32) taskDescTabsOffset;
taskDescTabsOffset += taskDescTabSize;
entryPtr[i].TDTend = (u32) taskDescTabsOffset - 4;
}
#ifdef MCD_INCLUDE_EU
/* Tack single DMA BDs onto end of code so API controls
where they are since DMA might write to them */
MCD_relocBuffDesc =
(MCD_bufDesc *) (entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
#else
/* DMA does not touch them so they can be wherever and we
don't need to waste SRAM on them */
MCD_relocBuffDesc = MCD_singleBufDescs;
#endif
} else {
/* point the would-be relocated task tables and the
buffer descriptors to the ones the linker generated */
if (((u32) MCD_realTaskTableSrc & 0x000001ff) != 0)
return (MCD_TABLE_UNALIGNED);
/* need to add code to make sure that every thing else is
aligned properly TBD. this is problematic if we init
more than once or after running tasks, need to add
variable to see if we have aleady init'd */
entryPtr = MCD_realTaskTableSrc;
for (i = 0; i < NCHANNELS; i++) {
if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
((entryPtr[i].
FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
return (MCD_TABLE_UNALIGNED);
}
MCD_taskTable = MCD_realTaskTableSrc;
MCD_modelTaskTable = MCD_modelTaskTableSrc;
MCD_relocBuffDesc = MCD_singleBufDescs;
}
/* Make all channels as totally inactive, and remember them as such: */
MCD_dmaBar->taskbar = (u32) MCD_taskTable;
for (i = 0; i < NCHANNELS; i++) {
MCD_dmaBar->taskControl[i] = 0x0;
MCD_chStatus[i] = MCD_NO_DMA;
}
/* Set up pausing mechanism to inactive state: */
/* no particular values yet for either comparator registers */
MCD_dmaBar->debugComp1 = 0;
MCD_dmaBar->debugComp2 = 0;
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
/* enable or disable commbus prefetch, really need an ifdef or
something to keep from trying to set this in the 8220 */
if ((flags & MCD_COMM_PREFETCH_EN) != 0)
MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
else
MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
return (MCD_OK);
}
/*********************** End of MCD_initDma() ***********************/
/********************************************************************/
/* Function: MCD_dmaStatus
* Purpose: Returns the status of the DMA on the requested channel
* Arguments: channel - channel number
* Returns: Predefined status indicators
*/
int MCD_dmaStatus(int channel)
{
u16 tcrValue;
if ((channel < 0) || (channel >= NCHANNELS))
return (MCD_CHANNEL_INVALID);
tcrValue = MCD_dmaBar->taskControl[channel];
if ((tcrValue & TASK_CTL_EN) == 0) { /* nothing running */
/* if last reported with task enabled */
if (MCD_chStatus[channel] == MCD_RUNNING
|| MCD_chStatus[channel] == MCD_IDLE)
MCD_chStatus[channel] = MCD_DONE;
} else { /* something is running */
/* There are three possibilities: paused, running or idle. */
if (MCD_chStatus[channel] == MCD_RUNNING
|| MCD_chStatus[channel] == MCD_IDLE) {
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
/* This register is selected to know which initiator is
actually asserted. */
if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
MCD_chStatus[channel] = MCD_RUNNING;
else
MCD_chStatus[channel] = MCD_IDLE;
/* do not change the status if it is already paused. */
}
}
return MCD_chStatus[channel];
}
/******************** End of MCD_dmaStatus() ************************/
/********************************************************************/
/* Function: MCD_startDma
* Ppurpose: Starts a particular kind of DMA
* Arguments:
* srcAddr - the channel on which to run the DMA
* srcIncr - the address to move data from, or buffer-descriptor address
* destAddr - the amount to increment the source address per transfer
* destIncr - the address to move data to
* dmaSize - the amount to increment the destination address per transfer
* xferSize - the number bytes in of each data movement (1, 2, or 4)
* initiator - what device initiates the DMA
* priority - priority of the DMA
* flags - flags describing the DMA
* funcDesc - description of byte swapping, bit swapping, and CRC actions
* srcAddrVirt - virtual buffer descriptor address TBD
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*/
int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr,
s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator,
int priority, u32 flags, u32 funcDesc
#ifdef MCD_NEED_ADDR_TRANS
s8 * srcAddrVirt
#endif
)
{
int srcRsdIncr, destRsdIncr;
int *cSave;
short xferSizeIncr;
int tcrCount = 0;
#ifdef MCD_INCLUDE_EU
u32 *realFuncArray;
#endif
if ((channel < 0) || (channel >= NCHANNELS))
return (MCD_CHANNEL_INVALID);
/* tbd - need to determine the proper response to a bad funcDesc when
not including EU functions, for now, assign a benign funcDesc, but
maybe should return an error */
#ifndef MCD_INCLUDE_EU
funcDesc = MCD_FUNC_NOEU1;
#endif
#ifdef MCD_DEBUG
printf("startDma:Setting up params\n");
#endif
/* Set us up for task-wise priority. We don't technically need to do
this on every start, but since the register involved is in the same
longword as other registers that users are in control of, setting
it more than once is probably preferable. That since the
documentation doesn't seem to be completely consistent about the
nature of the PTD control register. */
MCD_dmaBar->ptdControl |= (u16) 0x8000;
/* Not sure what we need to keep here rtm TBD */
#if 1
/* Calculate additional parameters to the regular DMA calls. */
srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
/* Remember for each channel which variant is running. */
MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
MCD_remVariants.remDestIncr[channel] = destIncr;
MCD_remVariants.remSrcIncr[channel] = srcIncr;
MCD_remVariants.remXferSize[channel] = xferSize;
#endif
cSave =
(int *)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET +
CURRBD;
#ifdef MCD_INCLUDE_EU
/* may move this to EU specific calls */
realFuncArray =
(u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
/* Modify the LURC's normal and byte-residue-loop functions according
to parameter. */
realFuncArray[(LURC * 16)] = xferSize == 4 ?
funcDesc : xferSize == 2 ?
funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
realFuncArray[(LURC * 16 + 1)] =
(funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
#endif
/* Write the initiator field in the TCR, and also set the
initiator-hold bit. Note that,due to a hardware quirk, this could
collide with an MDE access to the initiator-register file, so we
have to verify that the write reads back correctly. */
MCD_dmaBar->taskControl[channel] =
(initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
while (((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM))
&& (tcrCount < 1000)) {
tcrCount++;
/*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020; */
MCD_dmaBar->taskControl[channel] =
(initiator << 8) | TASK_CTL_HIPRITSKEN |
TASK_CTL_HLDINITNUM;
}
MCD_dmaBar->priority[channel] = (u8) priority & PRIORITY_PRI_MASK;
/* should be albe to handle this stuff with only one write to ts reg
- tbd */
if (channel < 8 && channel >= 0) {
MCD_dmaBar->taskSize0 &= ~(0xf << (7 - channel) * 4);
MCD_dmaBar->taskSize0 |=
(xferSize & 3) << (((7 - channel) * 4) + 2);
MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel) * 4);
} else {
MCD_dmaBar->taskSize1 &= ~(0xf << (15 - channel) * 4);
MCD_dmaBar->taskSize1 |=
(xferSize & 3) << (((15 - channel) * 4) + 2);
MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel) * 4);
}
/* setup task table flags/options which mostly control the line
buffers */
MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
if (flags & MCD_FECTX_DMA) {
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart =
MCD_modelTaskTable[TASK_FECTX].TDTstart;
MCD_taskTable[channel].TDTend =
MCD_modelTaskTable[TASK_FECTX].TDTend;
MCD_startDmaENetXmit((char *)srcAddr, (char *)srcAddr,
(char *)destAddr, MCD_taskTable,
channel);
} else if (flags & MCD_FECRX_DMA) {
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart =
MCD_modelTaskTable[TASK_FECRX].TDTstart;
MCD_taskTable[channel].TDTend =
MCD_modelTaskTable[TASK_FECRX].TDTend;
MCD_startDmaENetRcv((char *)srcAddr, (char *)srcAddr,
(char *)destAddr, MCD_taskTable,
channel);
} else if (flags & MCD_SINGLE_DMA) {
/* this buffer descriptor is used for storing off initial
parameters for later progress query calculation and for the
DMA to write the resulting checksum. The DMA does not use
this to determine how to operate, that info is passed with
the init routine */
MCD_relocBuffDesc[channel].srcAddr = srcAddr;
MCD_relocBuffDesc[channel].destAddr = destAddr;
/* definitely not its final value */
MCD_relocBuffDesc[channel].lastDestAddr = destAddr;
MCD_relocBuffDesc[channel].dmaSize = dmaSize;
MCD_relocBuffDesc[channel].flags = 0; /* not used */
MCD_relocBuffDesc[channel].csumResult = 0; /* not used */
MCD_relocBuffDesc[channel].next = 0; /* not used */
/* Initialize the progress-querying stuff to show no
progress: */
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
(u32) & (MCD_relocBuffDesc[channel]);
/* tbd - need to keep the user from trying to call the EU
routine when MCD_INCLUDE_EU is not defined */
if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart =
MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
MCD_taskTable[channel].TDTend =
MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
MCD_startDmaSingleNoEu((char *)srcAddr, srcIncr,
(char *)destAddr, destIncr,
(int)dmaSize, xferSizeIncr,
flags, (int *)
&(MCD_relocBuffDesc[channel]),
cSave, MCD_taskTable, channel);
} else {
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart =
MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
MCD_taskTable[channel].TDTend =
MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
MCD_startDmaSingleEu((char *)srcAddr, srcIncr,
(char *)destAddr, destIncr,
(int)dmaSize, xferSizeIncr,
flags, (int *)
&(MCD_relocBuffDesc[channel]),
cSave, MCD_taskTable, channel);
}
} else { /* chained DMAS */
/* Initialize the progress-querying stuff to show no
progress: */
#if 1
/* (!defined(MCD_NEED_ADDR_TRANS)) */
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc *) srcAddr)->srcAddr;
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc *) srcAddr)->destAddr;
#else
/* if using address translation, need the virtual addr of the
first buffdesc */
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc *) srcAddrVirt)->srcAddr;
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc *) srcAddrVirt)->destAddr;
#endif
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) {
/*TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart =
MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
MCD_taskTable[channel].TDTend =
MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
MCD_startDmaChainNoEu((int *)srcAddr, srcIncr,
destIncr, xferSize,
xferSizeIncr, cSave,
MCD_taskTable, channel);
} else {
/*TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart =
MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
MCD_taskTable[channel].TDTend =
MCD_modelTaskTable[TASK_CHAINEU].TDTend;
MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr,
xferSize, xferSizeIncr, cSave,
MCD_taskTable, channel);
}
}
MCD_chStatus[channel] = MCD_IDLE;
return (MCD_OK);
}
/************************ End of MCD_startDma() *********************/
/********************************************************************/
/* Function: MCD_XferProgrQuery
* Purpose: Returns progress of DMA on requested channel
* Arguments: channel - channel to retrieve progress for
* progRep - pointer to user supplied MCD_XferProg struct
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*
* Notes:
* MCD_XferProgrQuery() upon completing or after aborting a DMA, or
* while the DMA is in progress, this function returns the first
* DMA-destination address not (or not yet) used in the DMA. When
* encountering a non-ready buffer descriptor, the information for
* the last completed descriptor is returned.
*
* MCD_XferProgQuery() has to avoid the possibility of getting
* partially-updated information in the event that we should happen
* to query DMA progress just as the DMA is updating it. It does that
* by taking advantage of the fact context is not saved frequently for
* the most part. We therefore read it at least twice until we get the
* same information twice in a row.
*
* Because a small, but not insignificant, amount of time is required
* to write out the progress-query information, especially upon
* completion of the DMA, it would be wise to guarantee some time lag
* between successive readings of the progress-query information.
*/
/* How many iterations of the loop below to execute to stabilize values */
#define STABTIME 0
int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep)
{
MCD_XferProg prevRep;
int again; /* true if we are to try again to ge
consistent results */
int i; /* used as a time-waste counter */
int destDiffBytes; /* Total no of bytes that we think actually
got xfered. */
int numIterations; /* number of iterations */
int bytesNotXfered; /* bytes that did not get xfered. */
s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
int subModVal, addModVal; /* Mode values to added and subtracted
from the final destAddr */
if ((channel < 0) || (channel >= NCHANNELS))
return (MCD_CHANNEL_INVALID);
/* Read a trial value for the progress-reporting values */
prevRep.lastSrcAddr =
(s8 *) ((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
prevRep.lastDestAddr =
(s8 *) ((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
prevRep.dmaSize =
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT +
CSAVE_OFFSET];
prevRep.currBufDesc =
(MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[CURRBD + CSAVE_OFFSET];
/* Repeatedly reread those values until they match previous values: */
do {
/* Waste a little bit of time to ensure stability: */
for (i = 0; i < STABTIME; i++) {
/* make sure this loop does something so that it
doesn't get optimized out */
i += i >> 2;
}
/* Check them again: */
progRep->lastSrcAddr =
(s8 *) ((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
progRep->lastDestAddr =
(s8 *) ((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
progRep->dmaSize =
((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
progRep->currBufDesc =
(MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel].
contextSaveSpace)[CURRBD + CSAVE_OFFSET];
/* See if they match: */
if (prevRep.lastSrcAddr != progRep->lastSrcAddr
|| prevRep.lastDestAddr != progRep->lastDestAddr
|| prevRep.dmaSize != progRep->dmaSize
|| prevRep.currBufDesc != progRep->currBufDesc) {
/* If they don't match, remember previous values and
try again: */
prevRep.lastSrcAddr = progRep->lastSrcAddr;
prevRep.lastDestAddr = progRep->lastDestAddr;
prevRep.dmaSize = progRep->dmaSize;
prevRep.currBufDesc = progRep->currBufDesc;
again = MCD_TRUE;
} else
again = MCD_FALSE;
} while (again == MCD_TRUE);
/* Update the dCount, srcAddr and destAddr */
/* To calculate dmaCount, we consider destination address. C
overs M1,P1,Z for destination */
switch (MCD_remVariants.remDestRsdIncr[channel]) {
case MINUS1:
subModVal =
((int)progRep->
lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
1);
addModVal =
((int)progRep->currBufDesc->
destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
LWAlignedInitDestAddr =
(progRep->currBufDesc->destAddr) - addModVal;
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
bytesNotXfered =
(destDiffBytes / MCD_remVariants.remDestIncr[channel]) *
(MCD_remVariants.remDestIncr[channel]
+ MCD_remVariants.remXferSize[channel]);
progRep->dmaSize =
destDiffBytes - bytesNotXfered + addModVal - subModVal;
break;
case ZERO:
progRep->lastDestAddr = progRep->currBufDesc->destAddr;
break;
case PLUS1:
/* This value has to be subtracted from the final
calculated dCount. */
subModVal =
((int)progRep->currBufDesc->
destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
/* These bytes are already in lastDestAddr. */
addModVal =
((int)progRep->
lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) -
1);
LWAlignedInitDestAddr =
(progRep->currBufDesc->destAddr) - subModVal;
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
numIterations =
(LWAlignedCurrDestAddr -
LWAlignedInitDestAddr) /
MCD_remVariants.remDestIncr[channel];
bytesNotXfered =
numIterations * (MCD_remVariants.remDestIncr[channel]
- MCD_remVariants.remXferSize[channel]);
progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
break;
default:
break;
}
/* This covers M1,P1,Z for source */
switch (MCD_remVariants.remSrcRsdIncr[channel]) {
case MINUS1:
progRep->lastSrcAddr =
progRep->currBufDesc->srcAddr +
(MCD_remVariants.remSrcIncr[channel] *
(progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
break;
case ZERO:
progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
break;
case PLUS1:
progRep->lastSrcAddr =
progRep->currBufDesc->srcAddr +
(MCD_remVariants.remSrcIncr[channel] *
(progRep->dmaSize / MCD_remVariants.remXferSize[channel]));
break;
default:
break;
}
return (MCD_OK);
}
/******************* End of MCD_XferProgrQuery() ********************/
/********************************************************************/
/* MCD_resmActions() does the majority of the actions of a DMA resume.
* It is called from MCD_killDma() and MCD_resumeDma(). It has to be
* a separate function because the kill function has to negate the task
* enable before resuming it, but the resume function has to do nothing
* if there is no DMA on that channel (i.e., if the enable bit is 0).
*/
static void MCD_resmActions(int channel)
{
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
/* This register is selected to know which initiator is
actually asserted. */
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
MCD_chStatus[channel] = MCD_RUNNING;
else
MCD_chStatus[channel] = MCD_IDLE;
}
/********************* End of MCD_resmActions() *********************/
/********************************************************************/
/* Function: MCD_killDma
* Purpose: Halt the DMA on the requested channel, without any
* intention of resuming the DMA.
* Arguments: channel - requested channel
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*
* Notes:
* A DMA may be killed from any state, including paused state, and it
* always goes to the MCD_HALTED state even if it is killed while in
* the MCD_NO_DMA or MCD_IDLE states.
*/
int MCD_killDma(int channel)
{
/* MCD_XferProg progRep; */
if ((channel < 0) || (channel >= NCHANNELS))
return (MCD_CHANNEL_INVALID);
MCD_dmaBar->taskControl[channel] = 0x0;
MCD_resumeDma(channel);
/*
* This must be after the write to the TCR so that the task doesn't
* start up again momentarily, and before the status assignment so
* as to override whatever MCD_resumeDma() may do to the channel
* status.
*/
MCD_chStatus[channel] = MCD_HALTED;
/*
* Update the current buffer descriptor's lastDestAddr field
*
* MCD_XferProgrQuery (channel, &progRep);
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
*/
return (MCD_OK);
}
/************************ End of MCD_killDma() **********************/
/********************************************************************/
/* Function: MCD_continDma
* Purpose: Continue a DMA which as stopped due to encountering an
* unready buffer descriptor.
* Arguments: channel - channel to continue the DMA on
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*
* Notes:
* This routine does not check to see if there is a task which can
* be continued. Also this routine should not be used with single DMAs.
*/
int MCD_continDma(int channel)
{
if ((channel < 0) || (channel >= NCHANNELS))
return (MCD_CHANNEL_INVALID);
MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
MCD_chStatus[channel] = MCD_RUNNING;
return (MCD_OK);
}
/********************** End of MCD_continDma() **********************/
/*********************************************************************
* MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
* to freeze a task and resume it. We freeze a task by breakpointing
* on the stated task. That is, not any specific place in the task,
* but any time that task executes. In particular, when that task
* executes, we want to freeze that task and only that task.
*
* The bits of the debug control register influence interrupts vs.
* breakpoints as follows:
* - Bits 14 and 0 enable or disable debug functions. If enabled, you
* will get the interrupt but you may or may not get a breakpoint.
* - Bits 2 and 1 decide whether you also get a breakpoint in addition
* to an interrupt.
*
* The debug unit can do these actions in response to either internally
* detected breakpoint conditions from the comparators, or in response
* to the external breakpoint pin, or both.
* - Bits 14 and 1 perform the above-described functions for
* internally-generated conditions, i.e., the debug comparators.
* - Bits 0 and 2 perform the above-described functions for external
* conditions, i.e., the breakpoint external pin.
*
* Note that, although you "always" get the interrupt when you turn
* the debug functions, the interrupt can nevertheless, if desired, be
* masked by the corresponding bit in the PTD's IMR. Note also that
* this means that bits 14 and 0 must enable debug functions before
* bits 1 and 2, respectively, have any effect.
*
* NOTE: It's extremely important to not pause more than one DMA channel
* at a time.
********************************************************************/
/********************************************************************/
/* Function: MCD_pauseDma
* Purpose: Pauses the DMA on a given channel (if any DMA is running
* on that channel).
* Arguments: channel
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*/
int MCD_pauseDma(int channel)
{
/* MCD_XferProg progRep; */
if ((channel < 0) || (channel >= NCHANNELS))
return (MCD_CHANNEL_INVALID);
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) {
MCD_dmaBar->debugComp1 = channel;
MCD_dmaBar->debugControl =
DBG_CTL_ENABLE | (1 << (channel + 16));
MCD_chStatus[channel] = MCD_PAUSED;
/*
* Update the current buffer descriptor's lastDestAddr field
*
* MCD_XferProgrQuery (channel, &progRep);
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
*/
}
return (MCD_OK);
}
/************************* End of MCD_pauseDma() ********************/
/********************************************************************/
/* Function: MCD_resumeDma
* Purpose: Resumes the DMA on a given channel (if any DMA is
* running on that channel).
* Arguments: channel - channel on which to resume DMA
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*/
int MCD_resumeDma(int channel)
{
if ((channel < 0) || (channel >= NCHANNELS))
return (MCD_CHANNEL_INVALID);
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
MCD_resmActions(channel);
return (MCD_OK);
}
/************************ End of MCD_resumeDma() ********************/
/********************************************************************/
/* Function: MCD_csumQuery
* Purpose: Provide the checksum after performing a non-chained DMA
* Arguments: channel - channel to report on
* csum - pointer to where to write the checksum/CRC
* Returns: MCD_ERROR if the channel is invalid, else MCD_OK
*
* Notes:
*
*/
int MCD_csumQuery(int channel, u32 * csum)
{
#ifdef MCD_INCLUDE_EU
if ((channel < 0) || (channel >= NCHANNELS))
return (MCD_CHANNEL_INVALID);
*csum = MCD_relocBuffDesc[channel].csumResult;
return (MCD_OK);
#else
return (MCD_ERROR);
#endif
}
/*********************** End of MCD_resumeDma() *********************/
/********************************************************************/
/* Function: MCD_getCodeSize
* Purpose: Provide the size requirements of the microcoded tasks
* Returns: Size in bytes
*/
int MCD_getCodeSize(void)
{
#ifdef MCD_INCLUDE_EU
return (0x2b5c);
#else
return (0x173c);
#endif
}
/********************** End of MCD_getCodeSize() ********************/
/********************************************************************/
/* Function: MCD_getVersion
* Purpose: Provide the version string and number
* Arguments: longVersion - user supplied pointer to a pointer to a char
* which points to the version string
* Returns: Version number and version string (by reference)
*/
char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
#define MCD_REV_MAJOR 0x00
#define MCD_REV_MINOR 0x03
int MCD_getVersion(char **longVersion)
{
*longVersion = MCD_versionString;
return ((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
}
/********************** End of MCD_getVersion() *********************/
/********************************************************************/
/* Private version of memcpy()
* Note that everything this is used for is longword-aligned.
*/
static void MCD_memcpy(int *dest, int *src, u32 size)
{
u32 i;
for (i = 0; i < size; i += sizeof(int), dest++, src++)
*dest = *src;
}
|
1001-study-uboot
|
drivers/dma/MCD_dmaApi.c
|
C
|
gpl3
| 36,189
|
/*
* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_dma.h>
/* Controller can only transfer 2^26 - 1 bytes at a time */
#define FSL_DMA_MAX_SIZE (0x3ffffff)
#if defined(CONFIG_MPC83xx)
#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
#else
#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
#endif
#if defined(CONFIG_MPC83xx)
dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
#elif defined(CONFIG_MPC85xx)
ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
#elif defined(CONFIG_MPC86xx)
ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
#else
#error "Freescale DMA engine not supported on your processor"
#endif
static void dma_sync(void)
{
#if defined(CONFIG_MPC85xx)
asm("sync; isync; msync");
#elif defined(CONFIG_MPC86xx)
asm("sync; isync");
#endif
}
static void out_dma32(volatile unsigned *addr, int val)
{
#if defined(CONFIG_MPC83xx)
out_le32(addr, val);
#else
out_be32(addr, val);
#endif
}
static uint in_dma32(volatile unsigned *addr)
{
#if defined(CONFIG_MPC83xx)
return in_le32(addr);
#else
return in_be32(addr);
#endif
}
static uint dma_check(void) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
uint status;
/* While the channel is busy, spin */
do {
status = in_dma32(&dma->sr);
} while (status & FSL_DMA_SR_CB);
/* clear MR[CS] channel start bit */
out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
dma_sync();
if (status != 0)
printf ("DMA Error: status = %x\n", status);
return status;
}
#if !defined(CONFIG_MPC83xx)
void dma_init(void) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
out_dma32(&dma->sr, 0xffffffff); /* clear any errors */
dma_sync();
}
#endif
int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
volatile fsl_dma_t *dma = &dma_base->dma[0];
uint xfer_size;
while (count) {
xfer_size = MIN(FSL_DMA_MAX_SIZE, count);
out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
#if !defined(CONFIG_MPC83xx)
out_dma32(&dma->satr,
in_dma32(&dma->satr) | (u32)((u64)src >> 32));
out_dma32(&dma->datr,
in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
#endif
out_dma32(&dma->bcr, xfer_size);
dma_sync();
/* Prepare mode register */
out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
dma_sync();
/* Start the transfer */
out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
count -= xfer_size;
src += xfer_size;
dest += xfer_size;
dma_sync();
if (dma_check())
return -1;
}
return 0;
}
/*
* 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
* while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
*/
#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
(defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
void dma_meminit(uint val, uint size)
{
uint *p = 0;
uint i = 0;
for (*p = 0; p < (uint *)(8 * 1024); p++) {
if (((uint)p & 0x1f) == 0)
ppcDcbz((ulong)p);
*p = (uint)CONFIG_MEM_INIT_VALUE;
if (((uint)p & 0x1c) == 0x1c)
ppcDcbf((ulong)p);
}
dmacpy(0x002000, 0, 0x002000); /* 8K */
dmacpy(0x004000, 0, 0x004000); /* 16K */
dmacpy(0x008000, 0, 0x008000); /* 32K */
dmacpy(0x010000, 0, 0x010000); /* 64K */
dmacpy(0x020000, 0, 0x020000); /* 128K */
dmacpy(0x040000, 0, 0x040000); /* 256K */
dmacpy(0x080000, 0, 0x080000); /* 512K */
dmacpy(0x100000, 0, 0x100000); /* 1M */
dmacpy(0x200000, 0, 0x200000); /* 2M */
dmacpy(0x400000, 0, 0x400000); /* 4M */
for (i = 1; i < size / 0x800000; i++)
dmacpy((0x800000 * i), 0, 0x800000);
}
#endif
|
1001-study-uboot
|
drivers/dma/fsl_dma.c
|
C
|
gpl3
| 4,797
|
/* -------------------------------------------------------------------- */
/* RPX Boards from Embedded Planet */
/* -------------------------------------------------------------------- */
#include <common.h>
#ifdef CONFIG_8xx
#include <mpc8xx.h>
#endif
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_PCMCIA) \
&& (defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE))
#define PCMCIA_BOARD_MSG "RPX CLASSIC or RPX LITE"
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
u_long reg = 0;
switch(vcc) {
case 0: break;
case 33: reg |= BCSR1_PCVCTL4; break;
case 50: reg |= BCSR1_PCVCTL5; break;
default: return 1;
}
switch(vpp) {
case 0: break;
case 33:
case 50:
if(vcc == vpp)
reg |= BCSR1_PCVCTL6;
else
return 1;
break;
case 120:
reg |= BCSR1_PCVCTL7;
default: return 1;
}
/* first, turn off all power */
*((uint *)RPX_CSR_ADDR) &= ~(BCSR1_PCVCTL4 | BCSR1_PCVCTL5
| BCSR1_PCVCTL6 | BCSR1_PCVCTL7);
/* enable new powersettings */
*((uint *)RPX_CSR_ADDR) |= reg;
return 0;
}
int pcmcia_hardware_enable (int slot)
{
return 0; /* No hardware to enable */
}
#if defined(CONFIG_CMD_PCMCIA)
static int pcmcia_hardware_disable(int slot)
{
return 0; /* No hardware to disable */
}
#endif
#endif /* CONFIG_PCMCIA && (CONFIG_RPXCLASSIC || CONFIG_RPXLITE) */
|
1001-study-uboot
|
drivers/pcmcia/rpx_pcmcia.c
|
C
|
gpl3
| 1,486
|
#include <common.h>
#include <config.h>
#include <pcmcia.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
static inline void msWait(unsigned msVal)
{
udelay(msVal*1000);
}
int pcmcia_on (void)
{
unsigned int reg_arr[] = {
0x48000028, CONFIG_SYS_MCMEM0_VAL,
0x4800002c, CONFIG_SYS_MCMEM1_VAL,
0x48000030, CONFIG_SYS_MCATT0_VAL,
0x48000034, CONFIG_SYS_MCATT1_VAL,
0x48000038, CONFIG_SYS_MCIO0_VAL,
0x4800003c, CONFIG_SYS_MCIO1_VAL,
0, 0
};
int i, rc;
#ifdef CONFIG_EXADRON1
int cardDetect;
volatile unsigned int *v_pBCRReg =
(volatile unsigned int *) 0x08000000;
#endif
debug ("%s\n", __FUNCTION__);
i = 0;
while (reg_arr[i]) {
(*(volatile unsigned int *) reg_arr[i]) |= reg_arr[i + 1];
i += 2;
}
udelay (1000);
debug ("%s: programmed mem controller \n", __FUNCTION__);
#ifdef CONFIG_EXADRON1
/*define useful BCR masks */
#define BCR_CF_INIT_VAL 0x00007230
#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231
#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233
#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213
#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211
/* we see from the GPIO bit if the card is present */
cardDetect = !(GPLR0 & GPIO_bit (14));
if (cardDetect) {
printf ("No PCMCIA card found!\n");
}
/* reset the card via the BCR line */
*v_pBCRReg = (unsigned) BCR_CF_INIT_VAL;
msWait (500);
*v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL;
msWait (500);
*v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL;
msWait (500);
*v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL;
msWait (500);
*v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL;
msWait (1500);
/* enable address bus */
GPCR1 = 0x01;
/* and the first CF slot */
MECR = 0x00000002;
#endif /* EXADRON 1 */
rc = check_ide_device (0); /* use just slot 0 */
return rc;
}
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_off (void)
{
return 0;
}
#endif
|
1001-study-uboot
|
drivers/pcmcia/pxa_pcmcia.c
|
C
|
gpl3
| 1,937
|
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libpcmcia.o
COBJS-$(CONFIG_I82365) += i82365.o
COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o
COBJS-$(CONFIG_PXA_PCMCIA) += pxa_pcmcia.o
COBJS-y += rpx_pcmcia.o
COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o
COBJS-y += tqm8xx_pcmcia.o
COBJS-$(CONFIG_MARUBUN_PCCARD) += marubun_pcmcia.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/pcmcia/Makefile
|
Makefile
|
gpl3
| 1,580
|
/*
* Marubun MR-SHPC-01 PCMCIA controller device driver
*
* (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <config.h>
#include <pcmcia.h>
#include <asm/io.h>
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_CMD_IDE)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_PCMCIA)
/* MR-SHPC-01 register */
#define MRSHPC_MODE (CONFIG_SYS_MARUBUN_MRSHPC + 4)
#define MRSHPC_OPTION (CONFIG_SYS_MARUBUN_MRSHPC + 6)
#define MRSHPC_CSR (CONFIG_SYS_MARUBUN_MRSHPC + 8)
#define MRSHPC_ISR (CONFIG_SYS_MARUBUN_MRSHPC + 10)
#define MRSHPC_ICR (CONFIG_SYS_MARUBUN_MRSHPC + 12)
#define MRSHPC_CPWCR (CONFIG_SYS_MARUBUN_MRSHPC + 14)
#define MRSHPC_MW0CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 16)
#define MRSHPC_MW1CR1 (CONFIG_SYS_MARUBUN_MRSHPC + 18)
#define MRSHPC_IOWCR1 (CONFIG_SYS_MARUBUN_MRSHPC + 20)
#define MRSHPC_MW0CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 22)
#define MRSHPC_MW1CR2 (CONFIG_SYS_MARUBUN_MRSHPC + 24)
#define MRSHPC_IOWCR2 (CONFIG_SYS_MARUBUN_MRSHPC + 26)
#define MRSHPC_CDCR (CONFIG_SYS_MARUBUN_MRSHPC + 28)
#define MRSHPC_PCIC_INFO (CONFIG_SYS_MARUBUN_MRSHPC + 30)
int pcmcia_on (void)
{
printf("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
/* Init */
outw( 0x0000 , MRSHPC_MODE );
if ((inw(MRSHPC_CSR) & 0x000c) == 0){ /* if card detect is true */
if ((inw(MRSHPC_CSR) & 0x0080) == 0){
outw(0x0674 ,MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
}else{
outw(0x0678 ,MRSHPC_CPWCR); /* Card Vcc is 5V */
}
udelay( 100000 ); /* wait for power on */
}else{
return 1;
}
/*
* PC-Card window open
* flag == COMMON/ATTRIBUTE/IO
*/
/* common window open */
outw(0x8a84,MRSHPC_MW0CR1); /* window 0xb8400000 */
if ((inw(MRSHPC_CSR) & 0x4000) != 0)
outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */
else
outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */
/* attribute window open */
outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */
if ((inw(MRSHPC_CSR) & 0x4000) != 0)
outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */
else
outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */
/* I/O window open */
outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */
outw(0x0008,MRSHPC_CDCR); /* I/O card mode */
if ((inw(MRSHPC_CSR) & 0x4000) != 0)
outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */
else
outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */
outw(0x0000,MRSHPC_ISR);
outw(0x2000,MRSHPC_ICR);
outb(0x00,(CONFIG_SYS_MARUBUN_MW2 + 0x206));
outb(0x42,(CONFIG_SYS_MARUBUN_MW2 + 0x200));
return 0;
}
int pcmcia_off (void)
{
printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
return 0;
}
#endif /* CONFIG_PCMCIA */
|
1001-study-uboot
|
drivers/pcmcia/marubun_pcmcia.c
|
C
|
gpl3
| 3,515
|
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************
*
* Lots of code copied from:
*
* i82365.c 1.352 - Linux driver for Intel 82365 and compatible
* PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
* (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <pcmcia.h>
#include <asm/io.h>
#include <pcmcia/ss.h>
#include <pcmcia/i82365.h>
#include <pcmcia/yenta.h>
#ifdef CONFIG_CPC45
#include <pcmcia/cirrus.h>
#else
#include <pcmcia/ti113x.h>
#endif
static struct pci_device_id supported[] = {
#ifdef CONFIG_CPC45
{PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729},
#else
{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
#endif
{0, 0}
};
#define CYCLE_TIME 120
#ifdef CONFIG_CPC45
extern int SPD67290Init (void);
#endif
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev);
#endif
typedef struct socket_info_t {
pci_dev_t dev;
u_short bcr;
u_char pci_lat, cb_lat, sub_bus, cache;
u_int cb_phys;
socket_cap_t cap;
u_short type;
u_int flags;
#ifdef CONFIG_CPC45
cirrus_state_t c_state;
#else
ti113x_state_t state;
#endif
} socket_info_t;
#ifdef CONFIG_CPC45
/* These definitions must match the pcic table! */
typedef enum pcic_id {
IS_PD6710, IS_PD672X, IS_VT83C469
} pcic_id;
typedef struct pcic_t {
char *name;
} pcic_t;
static pcic_t pcic[] = {
{" Cirrus PD6710: "},
{" Cirrus PD672x: "},
{" VIA VT83C469: "},
};
#endif
static socket_info_t socket;
static socket_state_t state;
static struct pccard_mem_map mem;
static struct pccard_io_map io;
/*====================================================================*/
/* Some PCI shortcuts */
static int pci_readb (socket_info_t * s, int r, u_char * v)
{
return pci_read_config_byte (s->dev, r, v);
}
static int pci_writeb (socket_info_t * s, int r, u_char v)
{
return pci_write_config_byte (s->dev, r, v);
}
static int pci_readw (socket_info_t * s, int r, u_short * v)
{
return pci_read_config_word (s->dev, r, v);
}
static int pci_writew (socket_info_t * s, int r, u_short v)
{
return pci_write_config_word (s->dev, r, v);
}
#ifndef CONFIG_CPC45
static int pci_readl (socket_info_t * s, int r, u_int * v)
{
return pci_read_config_dword (s->dev, r, v);
}
static int pci_writel (socket_info_t * s, int r, u_int v)
{
return pci_write_config_dword (s->dev, r, v);
}
#endif /* !CONFIG_CPC45 */
/*====================================================================*/
#ifdef CONFIG_CPC45
#define cb_readb(s) readb((s)->cb_phys + 1)
#define cb_writeb(s, v) writeb(v, (s)->cb_phys)
#define cb_writeb2(s, v) writeb(v, (s)->cb_phys + 1)
#define cb_readl(s, r) readl((s)->cb_phys + (r))
#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
static u_char i365_get (socket_info_t * s, u_short reg)
{
u_char val;
#ifdef CONFIG_PCMCIA_SLOT_A
int slot = 0;
#else
int slot = 1;
#endif
val = I365_REG (slot, reg);
cb_writeb (s, val);
val = cb_readb (s);
debug ("i365_get slot:%x reg: %x val: %x\n", slot, reg, val);
return val;
}
static void i365_set (socket_info_t * s, u_short reg, u_char data)
{
#ifdef CONFIG_PCMCIA_SLOT_A
int slot = 0;
#else
int slot = 1;
#endif
u_char val;
val = I365_REG (slot, reg);
cb_writeb (s, val);
cb_writeb2 (s, data);
debug ("i365_set slot:%x reg: %x data:%x\n", slot, reg, data);
}
#else /* ! CONFIG_CPC45 */
#define cb_readb(s, r) readb((s)->cb_phys + (r))
#define cb_readl(s, r) readl((s)->cb_phys + (r))
#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
static u_char i365_get (socket_info_t * s, u_short reg)
{
return cb_readb (s, 0x0800 + reg);
}
static void i365_set (socket_info_t * s, u_short reg, u_char data)
{
cb_writeb (s, 0x0800 + reg, data);
}
#endif /* CONFIG_CPC45 */
static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) | mask);
}
static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
{
i365_set (s, reg, i365_get (s, reg) & ~mask);
}
#if 0 /* not used */
static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
{
u_char d = i365_get (s, reg);
i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
}
static u_short i365_get_pair (socket_info_t * s, u_short reg)
{
return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
}
#endif /* not used */
static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
{
i365_set (s, reg, data & 0xff);
i365_set (s, reg + 1, data >> 8);
}
#ifdef CONFIG_CPC45
/*======================================================================
Code to save and restore global state information for Cirrus
PD67xx controllers, and to set and report global configuration
options.
======================================================================*/
#define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
static void cirrus_get_state (socket_info_t * s)
{
int i;
cirrus_state_t *p = &s->c_state;
p->misc1 = i365_get (s, PD67_MISC_CTL_1);
p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
p->misc2 = i365_get (s, PD67_MISC_CTL_2);
for (i = 0; i < 6; i++)
p->timer[i] = i365_get (s, PD67_TIME_SETUP (0) + i);
}
static void cirrus_set_state (socket_info_t * s)
{
int i;
u_char misc;
cirrus_state_t *p = &s->c_state;
misc = i365_get (s, PD67_MISC_CTL_2);
i365_set (s, PD67_MISC_CTL_2, p->misc2);
if (misc & PD67_MC2_SUSPEND)
udelay (50000);
misc = i365_get (s, PD67_MISC_CTL_1);
misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
i365_set (s, PD67_MISC_CTL_1, misc | p->misc1);
for (i = 0; i < 6; i++)
i365_set (s, PD67_TIME_SETUP (0) + i, p->timer[i]);
}
static u_int cirrus_set_opts (socket_info_t * s)
{
cirrus_state_t *p = &s->c_state;
u_int mask = 0xffff;
char buf[200] = {0};
if (has_ring == -1)
has_ring = 1;
flip (p->misc2, PD67_MC2_IRQ15_RI, has_ring);
flip (p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
#if DEBUG
if (p->misc2 & PD67_MC2_IRQ15_RI)
strcat (buf, " [ring]");
if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
strcat (buf, " [dyn mode]");
if (p->misc1 & PD67_MC1_INPACK_ENA)
strcat (buf, " [inpack]");
#endif
if (p->misc2 & PD67_MC2_IRQ15_RI)
mask &= ~0x8000;
if (has_led > 0) {
#if DEBUG
strcat (buf, " [led]");
#endif
mask &= ~0x1000;
}
if (has_dma > 0) {
#if DEBUG
strcat (buf, " [dma]");
#endif
mask &= ~0x0600;
flip (p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
#if DEBUG
if (p->misc2 & PD67_MC2_FREQ_BYPASS)
strcat (buf, " [freq bypass]");
#endif
}
if (setup_time >= 0)
p->timer[0] = p->timer[3] = setup_time;
if (cmd_time > 0) {
p->timer[1] = cmd_time;
p->timer[4] = cmd_time * 2 + 4;
}
if (p->timer[1] == 0) {
p->timer[1] = 6;
p->timer[4] = 16;
if (p->timer[0] == 0)
p->timer[0] = p->timer[3] = 1;
}
if (recov_time >= 0)
p->timer[2] = p->timer[5] = recov_time;
debug ("i82365 Opt: %s [%d/%d/%d] [%d/%d/%d]\n",
buf,
p->timer[0], p->timer[1], p->timer[2],
p->timer[3], p->timer[4], p->timer[5]);
return mask;
}
#else /* !CONFIG_CPC45 */
/*======================================================================
Code to save and restore global state information for TI 1130 and
TI 1131 controllers, and to set and report global configuration
options.
======================================================================*/
static void ti113x_get_state (socket_info_t * s)
{
ti113x_state_t *p = &s->state;
pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
}
static void ti113x_set_state (socket_info_t * s)
{
ti113x_state_t *p = &s->state;
pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
pci_writel (s, TI12XX_IRQMUX, p->irqmux);
i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
}
static u_int ti113x_set_opts (socket_info_t * s)
{
ti113x_state_t *p = &s->state;
u_int mask = 0xffff;
p->cardctl &= ~TI113X_CCR_ZVENABLE;
p->cardctl |= TI113X_CCR_SPKROUTEN;
return mask;
}
#endif /* CONFIG_CPC45 */
/*======================================================================
Routines to handle common CardBus options
======================================================================*/
/* Default settings for PCI command configuration register */
#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
static void cb_get_state (socket_info_t * s)
{
pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
}
static void cb_set_state (socket_info_t * s)
{
#ifndef CONFIG_CPC45
pci_writel (s, CB_LEGACY_MODE_BASE, 0);
pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
#endif
pci_writew (s, PCI_COMMAND, CMD_DFLT);
pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
}
static void cb_set_opts (socket_info_t * s)
{
#ifndef CONFIG_CPC45
if (s->cache == 0)
s->cache = 8;
if (s->pci_lat == 0)
s->pci_lat = 0xa8;
if (s->cb_lat == 0)
s->cb_lat = 0xb0;
#endif
}
/*======================================================================
Power control for Cardbus controllers: used both for 16-bit and
Cardbus cards.
======================================================================*/
static int cb_set_power (socket_info_t * s, socket_state_t * state)
{
u_int reg = 0;
#ifdef CONFIG_CPC45
reg = I365_PWR_NORESET;
if (state->flags & SS_PWR_AUTO)
reg |= I365_PWR_AUTO;
if (state->flags & SS_OUTPUT_ENA)
reg |= I365_PWR_OUT;
if (state->Vpp != 0) {
if (state->Vpp == 120) {
reg |= I365_VPP1_12V;
puts (" 12V card found: ");
} else if (state->Vpp == state->Vcc) {
reg |= I365_VPP1_5V;
} else {
puts (" power not found: ");
return -1;
}
}
if (state->Vcc != 0) {
reg |= I365_VCC_5V;
if (state->Vcc == 33) {
puts (" 3.3V card found: ");
i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
} else if (state->Vcc == 50) {
puts (" 5V card found: ");
i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
} else {
puts (" power not found: ");
return -1;
}
}
if (reg != i365_get (s, I365_POWER)) {
reg = (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V);
i365_set (s, I365_POWER, reg);
}
#else /* ! CONFIG_CPC45 */
/* restart card voltage detection if it seems appropriate */
if ((state->Vcc == 0) && (state->Vpp == 0) &&
!(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
switch (state->Vcc) {
case 0:
reg = 0;
break;
case 33:
reg = CB_SC_VCC_3V;
break;
case 50:
reg = CB_SC_VCC_5V;
break;
default:
return -1;
}
switch (state->Vpp) {
case 0:
break;
case 33:
reg |= CB_SC_VPP_3V;
break;
case 50:
reg |= CB_SC_VPP_5V;
break;
case 120:
reg |= CB_SC_VPP_12V;
break;
default:
return -1;
}
if (reg != cb_readl (s, CB_SOCKET_CONTROL))
cb_writel (s, CB_SOCKET_CONTROL, reg);
#endif /* CONFIG_CPC45 */
return 0;
}
/*======================================================================
Generic routines to get and set controller options
======================================================================*/
static void get_bridge_state (socket_info_t * s)
{
#ifdef CONFIG_CPC45
cirrus_get_state (s);
#else
ti113x_get_state (s);
#endif
cb_get_state (s);
}
static void set_bridge_state (socket_info_t * s)
{
cb_set_state (s);
i365_set (s, I365_GBLCTL, 0x00);
i365_set (s, I365_GENCTL, 0x00);
#ifdef CONFIG_CPC45
cirrus_set_state (s);
#else
ti113x_set_state (s);
#endif
}
static void set_bridge_opts (socket_info_t * s)
{
#ifdef CONFIG_CPC45
cirrus_set_opts (s);
#else
ti113x_set_opts (s);
#endif
cb_set_opts (s);
}
/*====================================================================*/
#define PD67_EXT_INDEX 0x2e /* Extension index */
#define PD67_EXT_DATA 0x2f /* Extension data */
#define PD67_EXD_VS1(s) (0x01 << ((s)<<1))
#define pd67_ext_get(s, r) \
(i365_set(s, PD67_EXT_INDEX, r), i365_get(s, PD67_EXT_DATA))
static int i365_get_status (socket_info_t * s, u_int * value)
{
u_int status;
#ifdef CONFIG_CPC45
u_char val;
u_char power, vcc, vpp;
u_int powerstate;
#endif
status = i365_get (s, I365_IDENT);
status = i365_get (s, I365_STATUS);
*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
*value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
} else {
*value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
*value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
}
*value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
*value |= (status & I365_CS_READY) ? SS_READY : 0;
*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
#ifdef CONFIG_CPC45
/* Check for Cirrus CL-PD67xx chips */
i365_set (s, PD67_CHIP_INFO, 0);
val = i365_get (s, PD67_CHIP_INFO);
s->type = -1;
if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
val = i365_get (s, PD67_CHIP_INFO);
if ((val & PD67_INFO_CHIP_ID) == 0) {
s->type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
i365_set (s, PD67_EXT_INDEX, 0xe5);
if (i365_get (s, PD67_EXT_INDEX) != 0xe5)
s->type = IS_VT83C469;
}
} else {
printf ("no Cirrus Chip found\n");
*value = 0;
return -1;
}
power = i365_get (s, I365_POWER);
state.flags |= (power & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
state.flags |= (power & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
vcc = power & I365_VCC_MASK;
vpp = power & I365_VPP1_MASK;
state.Vcc = state.Vpp = 0;
if((vcc== 0) || (vpp == 0)) {
/*
* On the Cirrus we get the info which card voltage
* we have in EXTERN DATA and write it to MISC_CTL1
*/
powerstate = pd67_ext_get(s, PD67_EXTERN_DATA);
if (powerstate & PD67_EXD_VS1(0)) {
/* 5V Card */
i365_bclr (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
} else {
/* 3.3V Card */
i365_bset (s, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
}
i365_set (s, I365_POWER, (I365_PWR_OUT | I365_PWR_NORESET | I365_VCC_5V | I365_VPP1_5V));
power = i365_get (s, I365_POWER);
}
if (power & I365_VCC_5V) {
state.Vcc = (i365_get(s, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) ? 33 : 50;
}
if (power == I365_VPP1_12V)
state.Vpp = 120;
/* IO card, RESET flags, IO interrupt */
power = i365_get (s, I365_INTCTL);
state.flags |= (power & I365_PC_RESET) ? 0 : SS_RESET;
if (power & I365_PC_IOCARD)
state.flags |= SS_IOCARD;
state.io_irq = power & I365_IRQ_MASK;
/* Card status change mask */
power = i365_get (s, I365_CSCINT);
state.csc_mask = (power & I365_CSC_DETECT) ? SS_DETECT : 0;
if (state.flags & SS_IOCARD)
state.csc_mask |= (power & I365_CSC_STSCHG) ? SS_STSCHG : 0;
else {
state.csc_mask |= (power & I365_CSC_BVD1) ? SS_BATDEAD : 0;
state.csc_mask |= (power & I365_CSC_BVD2) ? SS_BATWARN : 0;
state.csc_mask |= (power & I365_CSC_READY) ? SS_READY : 0;
}
debug ("i82365: GetStatus(0) = flags %#3.3x, Vcc %d, Vpp %d, "
"io_irq %d, csc_mask %#2.2x\n", state.flags,
state.Vcc, state.Vpp, state.io_irq, state.csc_mask);
#else /* !CONFIG_CPC45 */
status = cb_readl (s, CB_SOCKET_STATE);
*value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
*value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
*value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
*value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
/* For now, ignore cards with unsupported voltage keys */
if (*value & SS_XVCARD)
*value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
#endif /* CONFIG_CPC45 */
return 0;
} /* i365_get_status */
static int i365_set_socket (socket_info_t * s, socket_state_t * state)
{
u_char reg;
set_bridge_state (s);
/* IO card, RESET flag */
reg = 0;
reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
i365_set (s, I365_INTCTL, reg);
#ifdef CONFIG_CPC45
cb_set_power (s, state);
#if 0
/* Card status change interrupt mask */
reg = s->cs_irq << 4;
if (state->csc_mask & SS_DETECT)
reg |= I365_CSC_DETECT;
if (state->flags & SS_IOCARD) {
if (state->csc_mask & SS_STSCHG)
reg |= I365_CSC_STSCHG;
} else {
if (state->csc_mask & SS_BATDEAD)
reg |= I365_CSC_BVD1;
if (state->csc_mask & SS_BATWARN)
reg |= I365_CSC_BVD2;
if (state->csc_mask & SS_READY)
reg |= I365_CSC_READY;
}
i365_set (s, I365_CSCINT, reg);
i365_get (s, I365_CSC);
#endif /* 0 */
#else /* !CONFIG_CPC45 */
reg = I365_PWR_NORESET;
if (state->flags & SS_PWR_AUTO)
reg |= I365_PWR_AUTO;
if (state->flags & SS_OUTPUT_ENA)
reg |= I365_PWR_OUT;
cb_set_power (s, state);
reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
if (reg != i365_get (s, I365_POWER))
i365_set (s, I365_POWER, reg);
#endif /* CONFIG_CPC45 */
return 0;
} /* i365_set_socket */
/*====================================================================*/
static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
{
u_short base, i;
u_char map;
debug ("i82365: SetMemMap(%d, %#2.2x, %d ns, %#5.5lx-%#5.5lx, %#5.5x)\n",
mem->map, mem->flags, mem->speed,
mem->sys_start, mem->sys_stop, mem->card_start);
map = mem->map;
if ((map > 4) ||
(mem->card_start > 0x3ffffff) ||
(mem->sys_start > mem->sys_stop) ||
(mem->speed > 1000)) {
return -1;
}
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
/* Take care of high byte, for PCI controllers */
i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
base = I365_MEM (map);
i = (mem->sys_start >> 12) & 0x0fff;
if (mem->flags & MAP_16BIT)
i |= I365_MEM_16BIT;
if (mem->flags & MAP_0WS)
i |= I365_MEM_0WS;
i365_set_pair (s, base + I365_W_START, i);
i = (mem->sys_stop >> 12) & 0x0fff;
switch (mem->speed / CYCLE_TIME) {
case 0:
break;
case 1:
i |= I365_MEM_WS0;
break;
case 2:
i |= I365_MEM_WS1;
break;
default:
i |= I365_MEM_WS1 | I365_MEM_WS0;
break;
}
i365_set_pair (s, base + I365_W_STOP, i);
#ifdef CONFIG_CPC45
i = 0;
#else
i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
#endif
if (mem->flags & MAP_WRPROT)
i |= I365_MEM_WRPROT;
if (mem->flags & MAP_ATTRIB)
i |= I365_MEM_REG;
i365_set_pair (s, base + I365_W_OFF, i);
#ifdef CONFIG_CPC45
/* set System Memory map Upper Adress */
i365_set(s, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
i365_set(s, PD67_EXT_DATA, ((mem->sys_start >> 24) & 0xff));
#endif
/* Turn on the window if necessary */
if (mem->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
return 0;
} /* i365_set_mem_map */
static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
{
u_char map, ioctl;
map = io->map;
/* comment out: comparison is always false due to limited range of data type */
if ((map > 1) || /* (io->start > 0xffff) || (io->stop > 0xffff) || */
(io->stop < io->start))
return -1;
/* Turn off the window before changing anything */
if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
if (io->speed)
ioctl |= I365_IOCTL_WAIT (map);
if (io->flags & MAP_0WS)
ioctl |= I365_IOCTL_0WS (map);
if (io->flags & MAP_16BIT)
ioctl |= I365_IOCTL_16BIT (map);
if (io->flags & MAP_AUTOSZ)
ioctl |= I365_IOCTL_IOCS16 (map);
i365_set (s, I365_IOCTL, ioctl);
/* Turn on the window if necessary */
if (io->flags & MAP_ACTIVE)
i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
return 0;
} /* i365_set_io_map */
/*====================================================================*/
int i82365_init (void)
{
u_int val;
int i;
#ifdef CONFIG_CPC45
if (SPD67290Init () != 0)
return 1;
#endif
if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
/* Controller not found */
return 1;
}
debug ("i82365 Device Found!\n");
pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
socket.cb_phys &= ~0xf;
#ifdef CONFIG_CPC45
/* + 0xfe000000 see MPC 8245 Users Manual Adress Map B */
socket.cb_phys += 0xfe000000;
#endif
get_bridge_state (&socket);
set_bridge_opts (&socket);
i = i365_get_status (&socket, &val);
#ifdef CONFIG_CPC45
if (i > -1) {
puts (pcic[socket.type].name);
} else {
printf ("i82365: Controller not found.\n");
return 1;
}
if((val & SS_DETECT) != SS_DETECT){
puts ("No card\n");
return 1;
}
#else /* !CONFIG_CPC45 */
if (val & SS_DETECT) {
if (val & SS_3VCARD) {
state.Vcc = state.Vpp = 33;
puts (" 3.3V card found: ");
} else if (!(val & SS_XVCARD)) {
state.Vcc = state.Vpp = 50;
puts (" 5.0V card found: ");
} else {
puts ("i82365: unsupported voltage key\n");
state.Vcc = state.Vpp = 0;
}
} else {
/* No card inserted */
puts ("No card\n");
return 1;
}
#endif /* CONFIG_CPC45 */
#ifdef CONFIG_CPC45
state.flags |= SS_OUTPUT_ENA;
#else
state.flags = SS_IOCARD | SS_OUTPUT_ENA;
state.csc_mask = 0;
state.io_irq = 0;
#endif
i365_set_socket (&socket, &state);
for (i = 500; i; i--) {
if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
break;
udelay (1000);
}
if (i == 0) {
/* PC Card not ready for data transfer */
puts ("i82365 PC Card not ready for data transfer\n");
return 1;
}
debug (" PC Card ready for data transfer: ");
mem.map = 0;
mem.flags = MAP_ATTRIB | MAP_ACTIVE;
mem.speed = 300;
mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
#ifdef CONFIG_CPC45
mem.map = 1;
mem.flags = MAP_ACTIVE;
mem.speed = 300;
mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE;
mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
#else /* !CONFIG_CPC45 */
io.map = 0;
io.flags = MAP_AUTOSZ | MAP_ACTIVE;
io.speed = 0;
io.start = 0x0100;
io.stop = 0x010F;
i365_set_io_map (&socket, &io);
#endif /* CONFIG_CPC45 */
#ifdef DEBUG
i82365_dump_regions (socket.dev);
#endif
return 0;
}
void i82365_exit (void)
{
io.map = 0;
io.flags = 0;
io.speed = 0;
io.start = 0;
io.stop = 0x1;
i365_set_io_map (&socket, &io);
mem.map = 0;
mem.flags = 0;
mem.speed = 0;
mem.sys_start = 0;
mem.sys_stop = 0x1000;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
#ifdef CONFIG_CPC45
mem.map = 1;
mem.flags = 0;
mem.speed = 0;
mem.sys_start = 0;
mem.sys_stop = 0x1000;
mem.card_start = 0;
i365_set_mem_map (&socket, &mem);
#else /* !CONFIG_CPC45 */
socket.state.sysctl &= 0xFFFF00FF;
#endif
state.Vcc = state.Vpp = 0;
i365_set_socket (&socket, &state);
}
/*======================================================================
Debug stuff
======================================================================*/
#ifdef DEBUG
static void i82365_dump_regions (pci_dev_t dev)
{
u_int tmp[2];
u_int *mem = (void *) socket.cb_phys;
u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
pci_read_config_dword (dev, 0x00, tmp + 0);
pci_read_config_dword (dev, 0x80, tmp + 1);
printf ("PCI CONF: %08X ... %08X\n",
tmp[0], tmp[1]);
printf ("PCI MEM: ... %08X ... %08X\n",
mem[0x8 / 4], mem[0x800 / 4]);
printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
printf ("CIS CONF: %02X %02X %02X ...\n",
cis[0x200], cis[0x202], cis[0x204]);
printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
ide[0], ide[1], ide[2], ide[3],
ide[4], ide[5], ide[6], ide[7]);
}
#endif /* DEBUG */
|
1001-study-uboot
|
drivers/pcmcia/i82365.c
|
C
|
gpl3
| 25,348
|
#include <common.h>
#include <mpc8xx.h>
#include <pcmcia.h>
#include <linux/compiler.h>
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_PCMCIA)
#if defined(CONFIG_IDE_8xx_PCCARD)
extern int check_ide_device (int slot);
#endif
extern int pcmcia_hardware_enable (int slot);
extern int pcmcia_voltage_set(int slot, int vcc, int vpp);
#if defined(CONFIG_CMD_PCMCIA)
extern int pcmcia_hardware_disable(int slot);
#endif
static u_int m8xx_get_graycode(u_int size);
#if 0 /* Disabled */
static u_int m8xx_get_speed(u_int ns, u_int is_io);
#endif
/* look up table for pgcrx registers */
u_int *pcmcia_pgcrx[2] = {
&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcra,
&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb,
};
/*
* Search this table to see if the windowsize is
* supported...
*/
#define M8XX_SIZES_NO 32
static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
0x00000080, 0x00000040, 0x00000010, 0x00000020,
0x00008000, 0x00004000, 0x00001000, 0x00002000,
0x00000100, 0x00000200, 0x00000800, 0x00000400,
0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0x01000000, 0x02000000, 0xffffffff, 0x04000000,
0x00010000, 0x00020000, 0x00080000, 0x00040000,
0x00800000, 0x00400000, 0x00100000, 0x00200000 };
/* -------------------------------------------------------------------- */
#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(9) \
| PCMCIA_SST(3) \
| PCMCIA_SL(12))
#else
#define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(2) \
| PCMCIA_SST(4) \
| PCMCIA_SL(9))
#endif
/* -------------------------------------------------------------------- */
int pcmcia_on (void)
{
u_long reg, base;
pcmcia_win_t *win;
u_int rc, slot;
__maybe_unused u_int slotbit;
int i;
debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
/* intialize the fixed memory windows */
win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
base = CONFIG_SYS_PCMCIA_MEM_ADDR;
if((reg = m8xx_get_graycode(CONFIG_SYS_PCMCIA_MEM_SIZE)) == -1) {
printf ("Cannot set window size to 0x%08x\n",
CONFIG_SYS_PCMCIA_MEM_SIZE);
return (1);
}
slotbit = PCMCIA_SLOT_x;
for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
win->br = base;
#if (PCMCIA_SOCKETS_NO == 2)
if (i == 4) /* Another slot starting from win 4 */
slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
#endif
switch (i) {
#ifdef CONFIG_IDE_8xx_PCCARD
case 4:
case 0: { /* map attribute memory */
win->or = ( PCMCIA_BSIZE_64M
| PCMCIA_PPS_8
| PCMCIA_PRS_ATTR
| slotbit
| PCMCIA_PV
| CONFIG_SYS_PCMCIA_TIMING );
break;
}
case 5:
case 1: { /* map I/O window for data reg */
win->or = ( PCMCIA_BSIZE_1K
| PCMCIA_PPS_16
| PCMCIA_PRS_IO
| slotbit
| PCMCIA_PV
| CONFIG_SYS_PCMCIA_TIMING );
break;
}
case 6:
case 2: { /* map I/O window for cmd/ctrl reg block */
win->or = ( PCMCIA_BSIZE_1K
| PCMCIA_PPS_8
| PCMCIA_PRS_IO
| slotbit
| PCMCIA_PV
| CONFIG_SYS_PCMCIA_TIMING );
break;
}
#endif /* CONFIG_IDE_8xx_PCCARD */
default: /* set to not valid */
win->or = 0;
break;
}
debug ("MemWin %d: PBR 0x%08lX POR %08lX\n",
i, win->br, win->or);
base += CONFIG_SYS_PCMCIA_MEM_SIZE;
++win;
}
for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {
/* turn off voltage */
if ((rc = pcmcia_voltage_set(slot, 0, 0)))
continue;
/* Enable external hardware */
if ((rc = pcmcia_hardware_enable(slot)))
continue;
#ifdef CONFIG_IDE_8xx_PCCARD
if ((rc = check_ide_device(i)))
continue;
#endif
}
return rc;
}
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_off (void)
{
int i;
pcmcia_win_t *win;
printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
/* clear interrupt state, and disable interrupts */
((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_);
((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);
/* turn off interrupt and disable CxOE */
PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;
/* turn off memory windows */
win = (pcmcia_win_t *)(&((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pbr0);
for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
/* disable memory window */
win->or = 0;
++win;
}
/* turn off voltage */
pcmcia_voltage_set(_slot_, 0, 0);
/* disable external hardware */
printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
pcmcia_hardware_disable(_slot_);
return 0;
}
#endif
static u_int m8xx_get_graycode(u_int size)
{
u_int k;
for (k = 0; k < M8XX_SIZES_NO; k++) {
if(m8xx_size_to_gray[k] == size)
break;
}
if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
k = -1;
return k;
}
#if 0
#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
* SYPCR is write once only, therefore must the slowest memory be faster
* than the bus monitor or we will get a machine check due to the bus timeout.
*/
#undef PCMCIA_BMT_LIMIT
#define PCMCIA_BMT_LIMIT (6*8)
#endif
static u_int m8xx_get_speed(u_int ns, u_int is_io)
{
u_int reg, clocks, psst, psl, psht;
if(!ns) {
/*
* We get called with IO maps setup to 0ns
* if not specified by the user.
* They should be 255ns.
*/
if(is_io)
ns = 255;
else
ns = 100; /* fast memory if 0 */
}
/*
* In PSST, PSL, PSHT fields we tell the controller
* timing parameters in CLKOUT clock cycles.
* CLKOUT is the same as GCLK2_50.
*/
/* how we want to adjust the timing - in percent */
#define ADJ 180 /* 80 % longer accesstime - to be sure */
clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
clocks = (clocks * ADJ) / (100*1000);
if(clocks >= PCMCIA_BMT_LIMIT) {
DEBUG(0, "Max access time limit reached\n");
clocks = PCMCIA_BMT_LIMIT-1;
}
psst = clocks / 7; /* setup time */
psht = clocks / 7; /* hold time */
psl = (clocks * 5) / 7; /* strobe length */
psst += clocks - (psst + psht + psl);
reg = psst << 12;
reg |= psl << 7;
reg |= psht << 16;
return reg;
}
#endif /* 0 */
#endif /* CONFIG_PCMCIA */
|
1001-study-uboot
|
drivers/pcmcia/mpc8xx_pcmcia.c
|
C
|
gpl3
| 6,268
|
/* -------------------------------------------------------------------- */
/* TQM8xxL Boards by TQ Components */
/* SC8xx Boards by SinoVee Microsystems */
/* -------------------------------------------------------------------- */
#include <common.h>
#include <asm/io.h>
#ifdef CONFIG_8xx
#include <mpc8xx.h>
#endif
#include <pcmcia.h>
#undef CONFIG_PCMCIA
#if defined(CONFIG_CMD_PCMCIA)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
#define CONFIG_PCMCIA
#endif
#if defined(CONFIG_PCMCIA) \
&& (defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx))
#if defined(CONFIG_VIRTLAB2)
#define PCMCIA_BOARD_MSG "Virtlab2"
#elif defined(CONFIG_TQM8xxL)
#define PCMCIA_BOARD_MSG "TQM8xxL"
#elif defined(CONFIG_SVM_SC8xx)
#define PCMCIA_BOARD_MSG "SC8xx"
#endif
#if defined(CONFIG_NSCU)
static inline void power_config(int slot) {}
static inline void power_off(int slot) {}
static inline void power_on_5_0(int slot) {}
static inline void power_on_3_3(int slot) {}
#elif defined(CONFIG_VIRTLAB2)
static inline void power_config(int slot) {}
static inline void power_off(int slot)
{
volatile unsigned __iomem *addr;
addr = (volatile unsigned __iomem *)PCMCIA_CTRL;
out_be32(addr, 0);
}
static inline void power_on_5_0(int slot)
{
volatile unsigned __iomem *addr;
addr = (volatile unsigned __iomem *)PCMCIA_CTRL;
/* Enable 5V Vccout */
out_be32(addr, 2);
}
static inline void power_on_3_3(int slot)
{
volatile unsigned __iomem *addr;
addr = (volatile unsigned __iomem *)PCMCIA_CTRL;
/* Enable 3.3V Vccout */
out_be32(addr, 1);
}
#else
static inline void power_config(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
/*
* Configure Port C pins for
* 5 Volts Enable and 3 Volts enable
*/
clrbits_be16(&immap->im_ioport.iop_pcpar, 0x0002 | 0x0004);
clrbits_be16(&immap->im_ioport.iop_pcso, 0x0002 | 0x0004);
}
static inline void power_off(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
clrbits_be16(&immap->im_ioport.iop_pcdat, 0x0002 | 0x0004);
}
static inline void power_on_5_0(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
setbits_be16(&immap->im_ioport.iop_pcdat, 0x0004);
setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004);
}
static inline void power_on_3_3(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
setbits_be16(&immap->im_ioport.iop_pcdat, 0x0002);
setbits_be16(&immap->im_ioport.iop_pcdir, 0x0002 | 0x0004);
}
#endif
/*
* Function to retrieve the PIPR register, used for debuging purposes.
*/
static inline uint32_t debug_get_pipr(void)
{
uint32_t pipr = 0;
#ifdef DEBUG
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);
#endif
return pipr;
}
static inline int check_card_is_absent(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
uint32_t pipr = in_be32(&immap->im_pcmcia.pcmc_pipr);
return pipr & (0x18000000 >> (slot << 4));
}
#ifdef NSCU_OE_INV
#define NSCU_GCRX_CXOE 0
#else
#define NSCU_GCRX_CXOE __MY_PCMCIA_GCRX_CXOE
#endif
int pcmcia_hardware_enable(int slot)
{
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
uint reg, mask;
debug("hardware_enable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
udelay(10000);
/*
* Configure SIUMCR to enable PCMCIA port B
* (VFLS[0:1] are not used for debugging, we connect FRZ# instead)
*/
/* Set DBGC to 00 */
clrbits_be32(&immap->im_siu_conf.sc_siumcr, SIUMCR_DBGC11);
/* Clear interrupt state, and disable interrupts */
out_be32(&immap->im_pcmcia.pcmc_pscr, PCMCIA_MASK(slot));
clrbits_be32(&immap->im_pcmcia.pcmc_per, PCMCIA_MASK(slot));
/*
* Disable interrupts, DMA, and PCMCIA buffers
* (isolate the interface) and assert RESET signal
*/
debug("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= NSCU_GCRX_CXOE;
PCMCIA_PGCRX(slot) = reg;
udelay(500);
power_config(slot);
power_off(slot);
/*
* Make sure there is a card in the slot, then configure the interface.
*/
udelay(10000);
reg = debug_get_pipr();
debug("[%d] %s: PIPR(%p)=0x%x\n", __LINE__, __FUNCTION__,
&immap->im_pcmcia.pcmc_pipr, reg);
if (check_card_is_absent(slot)) {
printf (" No Card found\n");
return (1);
}
/*
* Power On.
*/
mask = PCMCIA_VS1(slot) | PCMCIA_VS2(slot);
reg = in_be32(&immap->im_pcmcia.pcmc_pipr);
debug ("PIPR: 0x%x ==> VS1=o%s, VS2=o%s\n",
reg,
(reg & PCMCIA_VS1(slot)) ? "n" : "ff",
(reg & PCMCIA_VS2(slot)) ? "n" : "ff");
if ((reg & mask) == mask) {
power_on_5_0(slot);
puts (" 5.0V card found: ");
} else {
power_on_3_3(slot);
puts (" 3.3V card found: ");
}
#if 0
/* VCC switch error flag, PCMCIA slot INPACK_ pin */
cp->cp_pbdir &= ~(0x0020 | 0x0010);
cp->cp_pbpar &= ~(0x0020 | 0x0010);
udelay(500000);
#endif
udelay(1000);
debug("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
reg &= ~NSCU_GCRX_CXOE;
PCMCIA_PGCRX(slot) = reg;
udelay(250000); /* some cards need >150 ms to come up :-( */
debug("# hardware_enable done\n");
return (0);
}
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_hardware_disable(int slot)
{
u_long reg;
debug("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
/* remove all power */
power_off(slot);
debug("Disable PCMCIA buffers and assert RESET\n");
reg = 0;
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= NSCU_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(10000);
return (0);
}
#endif
int pcmcia_voltage_set(int slot, int vcc, int vpp)
{
#ifndef CONFIG_NSCU
u_long reg;
uint32_t pipr = 0;
debug("voltage_set: " PCMCIA_BOARD_MSG
" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
/*
* Disable PCMCIA buffers (isolate the interface)
* and assert RESET signal
*/
debug("Disable PCMCIA buffers and assert RESET\n");
reg = PCMCIA_PGCRX(slot);
reg |= __MY_PCMCIA_GCRX_CXRESET; /* active high */
reg &= ~__MY_PCMCIA_GCRX_CXOE; /* active low */
reg |= NSCU_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug("PCMCIA power OFF\n");
power_config(slot);
power_off(slot);
switch(vcc) {
case 0: break;
case 33: power_on_3_3(slot); break;
case 50: power_on_5_0(slot); break;
default: goto done;
}
/* Checking supported voltages */
pipr = debug_get_pipr();
debug("PIPR: 0x%x --> %s\n", pipr,
(pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
if (vcc)
debug("PCMCIA powered at %sV\n", (vcc == 50) ? "5.0" : "3.3");
else
debug("PCMCIA powered down\n");
done:
debug("Enable PCMCIA buffers and stop RESET\n");
reg = PCMCIA_PGCRX(slot);
reg &= ~__MY_PCMCIA_GCRX_CXRESET; /* active high */
reg |= __MY_PCMCIA_GCRX_CXOE; /* active low */
reg &= ~NSCU_GCRX_CXOE; /* active low */
PCMCIA_PGCRX(slot) = reg;
udelay(500);
debug("voltage_set: " PCMCIA_BOARD_MSG " Slot %c, DONE\n", slot+'A');
#endif /* CONFIG_NSCU */
return 0;
}
#endif /* CONFIG_PCMCIA && (CONFIG_TQM8xxL || CONFIG_SVM_SC8xx) */
|
1001-study-uboot
|
drivers/pcmcia/tqm8xx_pcmcia.c
|
C
|
gpl3
| 7,149
|
/*
* (C) Copyright 2000-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
********************************************************************
*
* Lots of code copied from:
*
* m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series.
* (C) 1999-2000 Magnus Damm <damm@bitsmart.com>
*
* "The ExCA standard specifies that socket controllers should provide
* two IO and five memory windows per socket, which can be independently
* configured and positioned in the host address space and mapped to
* arbitrary segments of card address space. " - David A Hinds. 1999
*
* This controller does _not_ meet the ExCA standard.
*
* m8xx pcmcia controller brief info:
* + 8 windows (attrib, mem, i/o)
* + up to two slots (SLOT_A and SLOT_B)
* + inputpins, outputpins, event and mask registers.
* - no offset register. sigh.
*
* Because of the lacking offset register we must map the whole card.
* We assign each memory window PCMCIA_MEM_WIN_SIZE address space.
* Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO
* * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE.
* The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE.
* They are maximum 64KByte each...
*/
#undef DEBUG /**/
/*
* PCMCIA support
*/
#include <common.h>
#include <command.h>
#include <config.h>
#include <pci.h>
#include <asm/io.h>
#include <pcmcia.h>
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_on(int ide_base_bus);
static int hardware_disable(int slot);
static int hardware_enable(int slot);
static int voltage_set(int slot, int vcc, int vpp);
static void print_funcid(int func);
static void print_fixed(volatile char *p);
static int identify(volatile char *p);
static int check_ide_device(int slot, int ide_base_bus);
/* ------------------------------------------------------------------------- */
const char *indent = "\t ";
/* ------------------------------------------------------------------------- */
static struct pci_device_id supported[] = {
{ PCI_VENDOR_ID_TI, 0xac50 }, /* Ti PCI1410A */
{ PCI_VENDOR_ID_TI, 0xac56 }, /* Ti PCI1510 */
{ }
};
static pci_dev_t devbusfn;
static u32 socket_base;
static u32 pcmcia_cis_ptr;
int pcmcia_on(int ide_base_bus)
{
u16 dev_id;
u32 socket_status;
int slot = 0;
int cis_len;
u16 io_base;
u16 io_len;
/*
* Find the CardBus PCI device(s).
*/
if ((devbusfn = pci_find_devices(supported, 0)) < 0) {
printf("Ti CardBus: not found\n");
return 1;
}
pci_read_config_word(devbusfn, PCI_DEVICE_ID, &dev_id);
if (dev_id == 0xac56) {
debug("Enable PCMCIA Ti PCI1510\n");
} else {
debug("Enable PCMCIA Ti PCI1410A\n");
}
pcmcia_cis_ptr = CONFIG_SYS_PCMCIA_CIS_WIN;
cis_len = CONFIG_SYS_PCMCIA_CIS_WIN_SIZE;
io_base = CONFIG_SYS_PCMCIA_IO_WIN;
io_len = CONFIG_SYS_PCMCIA_IO_WIN_SIZE;
/*
* Setup the PCI device.
*/
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &socket_base);
socket_base &= ~0xf;
socket_status = readl(socket_base+8);
if ((socket_status & 6) == 0) {
printf("Card Present: ");
switch (socket_status & 0x3c00) {
case 0x400:
printf("5V ");
break;
case 0x800:
printf("3.3V ");
break;
case 0xc00:
printf("3.3/5V ");
break;
default:
printf("unsupported Vcc ");
break;
}
switch (socket_status & 0x30) {
case 0x10:
printf("16bit PC-Card\n");
break;
case 0x20:
printf("32bit CardBus Card\n");
break;
default:
printf("8bit PC-Card\n");
break;
}
}
writeb(0x41, socket_base + 0x806); /* Enable I/O window 0 and memory window 0 */
writeb(0x0e, socket_base + 0x807); /* Reset I/O window options */
/* Careful: the linux yenta driver do not seem to reset the offset
* in the i/o windows, so leaving them non-zero is a problem */
writeb(io_base & 0xff, socket_base + 0x808); /* I/O window 0 base address */
writeb(io_base>>8, socket_base + 0x809);
writeb((io_base + io_len - 1) & 0xff, socket_base + 0x80a); /* I/O window 0 end address */
writeb((io_base + io_len - 1)>>8, socket_base + 0x80b);
writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address 0x000 */
writeb(0x00, socket_base + 0x837);
writeb((pcmcia_cis_ptr&0x000ff000) >> 12,
socket_base + 0x810); /* Memory window 0 start address bits 19-12 */
writeb((pcmcia_cis_ptr&0x00f00000) >> 20,
socket_base + 0x811); /* Memory window 0 start address bits 23-20 */
writeb(((pcmcia_cis_ptr+cis_len-1) & 0x000ff000) >> 12,
socket_base + 0x812); /* Memory window 0 end address bits 19-12*/
writeb(((pcmcia_cis_ptr+cis_len-1) & 0x00f00000) >> 20,
socket_base + 0x813); /* Memory window 0 end address bits 23-20*/
writeb(0x00, socket_base + 0x814); /* Memory window 0 offset bits 19-12 */
writeb(0x40, socket_base + 0x815); /* Memory window 0 offset bits 23-20 and
* options (read/write, attribute access) */
writeb(0x00, socket_base + 0x816); /* ExCA card-detect and general control */
writeb(0x00, socket_base + 0x81e); /* ExCA global control (interrupt modes) */
writeb((pcmcia_cis_ptr & 0xff000000) >> 24,
socket_base + 0x840); /* Memory window address bits 31-24 */
/* turn off voltage */
if (voltage_set(slot, 0, 0)) {
return 1;
}
/* Enable external hardware */
if (hardware_enable(slot)) {
return 1;
}
if (check_ide_device(slot, ide_base_bus)) {
return 1;
}
return 0;
}
/* ------------------------------------------------------------------------- */
#if defined(CONFIG_CMD_PCMCIA)
int pcmcia_off (void)
{
int slot = 0;
writeb(0x00, socket_base + 0x806); /* disable all I/O and memory windows */
writeb(0x00, socket_base + 0x808); /* I/O window 0 base address */
writeb(0x00, socket_base + 0x809);
writeb(0x00, socket_base + 0x80a); /* I/O window 0 end address */
writeb(0x00, socket_base + 0x80b);
writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address */
writeb(0x00, socket_base + 0x837);
writeb(0x00, socket_base + 0x80c); /* I/O window 1 base address */
writeb(0x00, socket_base + 0x80d);
writeb(0x00, socket_base + 0x80e); /* I/O window 1 end address */
writeb(0x00, socket_base + 0x80f);
writeb(0x00, socket_base + 0x838); /* I/O window 1 offset address */
writeb(0x00, socket_base + 0x839);
writeb(0x00, socket_base + 0x810); /* Memory window 0 start address */
writeb(0x00, socket_base + 0x811);
writeb(0x00, socket_base + 0x812); /* Memory window 0 end address */
writeb(0x00, socket_base + 0x813);
writeb(0x00, socket_base + 0x814); /* Memory window 0 offset */
writeb(0x00, socket_base + 0x815);
writeb(0xc0, socket_base + 0x840); /* Memory window 0 page address */
/* turn off voltage */
voltage_set(slot, 0, 0);
/* disable external hardware */
printf ("Shutdown and Poweroff Ti PCI1410A\n");
hardware_disable(slot);
return 0;
}
#endif
/* ------------------------------------------------------------------------- */
#define MAX_TUPEL_SZ 512
#define MAX_FEATURES 4
int ide_devices_found;
static int check_ide_device(int slot, int ide_base_bus)
{
volatile char *ident = NULL;
volatile char *feature_p[MAX_FEATURES];
volatile char *p, *start;
int n_features = 0;
uchar func_id = ~0;
uchar code, len;
ushort config_base = 0;
int found = 0;
int i;
u32 socket_status;
debug ("PCMCIA MEM: %08X\n", pcmcia_cis_ptr);
socket_status = readl(socket_base+8);
if ((socket_status & 6) != 0 || (socket_status & 0x20) != 0) {
printf("no card or CardBus card\n");
return 1;
}
start = p = (volatile char *) pcmcia_cis_ptr;
while ((p - start) < MAX_TUPEL_SZ) {
code = *p; p += 2;
if (code == 0xFF) { /* End of chain */
break;
}
len = *p; p += 2;
#if defined(DEBUG) && (DEBUG > 1)
{
volatile uchar *q = p;
printf ("\nTuple code %02x length %d\n\tData:",
code, len);
for (i = 0; i < len; ++i) {
printf (" %02x", *q);
q+= 2;
}
}
#endif /* DEBUG */
switch (code) {
case CISTPL_VERS_1:
ident = p + 4;
break;
case CISTPL_FUNCID:
/* Fix for broken SanDisk which may have 0x80 bit set */
func_id = *p & 0x7F;
break;
case CISTPL_FUNCE:
if (n_features < MAX_FEATURES)
feature_p[n_features++] = p;
break;
case CISTPL_CONFIG:
config_base = (*(p+6) << 8) + (*(p+4));
debug ("\n## Config_base = %04x ###\n", config_base);
default:
break;
}
p += 2 * len;
}
found = identify(ident);
if (func_id != ((uchar)~0)) {
print_funcid (func_id);
if (func_id == CISTPL_FUNCID_FIXED)
found = 1;
else
return 1; /* no disk drive */
}
for (i=0; i<n_features; ++i) {
print_fixed(feature_p[i]);
}
if (!found) {
printf("unknown card type\n");
return 1;
}
/* select config index 1 */
writeb(1, pcmcia_cis_ptr + config_base);
#if 0
printf("Confiuration Option Register: %02x\n", readb(pcmcia_cis_ptr + config_base));
printf("Card Confiuration and Status Register: %02x\n", readb(pcmcia_cis_ptr + config_base + 2));
printf("Pin Replacement Register Register: %02x\n", readb(pcmcia_cis_ptr + config_base + 4));
printf("Socket and Copy Register: %02x\n", readb(pcmcia_cis_ptr + config_base + 6));
#endif
ide_devices_found |= (1 << (slot+ide_base_bus));
return 0;
}
static int voltage_set(int slot, int vcc, int vpp)
{
u32 socket_control;
int reg=0;
switch (slot) {
case 0:
reg = socket_base + 0x10;
break;
default:
return 1;
}
socket_control = 0;
switch (vcc) {
case 50:
socket_control |= 0x20;
break;
case 33:
socket_control |= 0x30;
break;
case 0:
default: ;
}
switch (vpp) {
case 120:
socket_control |= 0x1;
break;
case 50:
socket_control |= 0x2;
break;
case 33:
socket_control |= 0x3;
break;
case 0:
default: ;
}
writel(socket_control, reg);
debug ("voltage_set: Ti PCI1410A Slot %d, Vcc=%d.%d, Vpp=%d.%d\n",
slot, vcc/10, vcc%10, vpp/10, vpp%10);
udelay(500);
return 0;
}
static int hardware_enable(int slot)
{
u32 socket_status;
u16 brg_ctrl;
int is_82365sl;
socket_status = readl(socket_base+8);
if ((socket_status & 6) == 0) {
switch (socket_status & 0x3c00) {
case 0x400:
printf("5V ");
voltage_set(slot, 50, 0);
break;
case 0x800:
voltage_set(slot, 33, 0);
break;
case 0xc00:
voltage_set(slot, 33, 0);
break;
default:
voltage_set(slot, 0, 0);
break;
}
} else {
voltage_set(slot, 0, 0);
}
pci_read_config_word(devbusfn, PCI_BRIDGE_CONTROL, &brg_ctrl);
brg_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config_word(devbusfn, PCI_BRIDGE_CONTROL, brg_ctrl);
is_82365sl = ((readb(socket_base+0x800) & 0x0f) == 2);
writeb(is_82365sl?0x90:0x98, socket_base+0x802);
writeb(0x67, socket_base+0x803);
udelay(100000);
#if 0
printf("ExCA Id %02x, Card Status %02x, Power config %02x, Interrupt Config %02x, bridge control %04x %d\n",
readb(socket_base+0x800), readb(socket_base+0x801),
readb(socket_base+0x802), readb(socket_base+0x803), brg_ctrl, is_82365sl);
#endif
return ((readb(socket_base+0x801)&0x6c)==0x6c)?0:1;
}
static int hardware_disable(int slot)
{
voltage_set(slot, 0, 0);
return 0;
}
static void print_funcid(int func)
{
puts(indent);
switch (func) {
case CISTPL_FUNCID_MULTI:
puts(" Multi-Function");
break;
case CISTPL_FUNCID_MEMORY:
puts(" Memory");
break;
case CISTPL_FUNCID_SERIAL:
puts(" Serial Port");
break;
case CISTPL_FUNCID_PARALLEL:
puts(" Parallel Port");
break;
case CISTPL_FUNCID_FIXED:
puts(" Fixed Disk");
break;
case CISTPL_FUNCID_VIDEO:
puts(" Video Adapter");
break;
case CISTPL_FUNCID_NETWORK:
puts(" Network Adapter");
break;
case CISTPL_FUNCID_AIMS:
puts(" AIMS Card");
break;
case CISTPL_FUNCID_SCSI:
puts(" SCSI Adapter");
break;
default:
puts(" Unknown");
break;
}
puts(" Card\n");
}
/* ------------------------------------------------------------------------- */
static void print_fixed(volatile char *p)
{
if (p == NULL)
return;
puts(indent);
switch (*p) {
case CISTPL_FUNCE_IDE_IFACE:
{ uchar iface = *(p+2);
puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
puts (" interface ");
break;
}
case CISTPL_FUNCE_IDE_MASTER:
case CISTPL_FUNCE_IDE_SLAVE:
{
uchar f1 = *(p+2);
uchar f2 = *(p+4);
puts((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
if (f1 & CISTPL_IDE_UNIQUE) {
puts(" [unique]");
}
puts((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
if (f2 & CISTPL_IDE_HAS_SLEEP) {
puts(" [sleep]");
}
if (f2 & CISTPL_IDE_HAS_STANDBY) {
puts(" [standby]");
}
if (f2 & CISTPL_IDE_HAS_IDLE) {
puts(" [idle]");
}
if (f2 & CISTPL_IDE_LOW_POWER) {
puts(" [low power]");
}
if (f2 & CISTPL_IDE_REG_INHIBIT) {
puts(" [reg inhibit]");
}
if (f2 & CISTPL_IDE_HAS_INDEX) {
puts(" [index]");
}
if (f2 & CISTPL_IDE_IOIS16) {
puts(" [IOis16]");
}
break;
}
}
putc('\n');
}
/* ------------------------------------------------------------------------- */
#define MAX_IDENT_CHARS 64
#define MAX_IDENT_FIELDS 4
static char *known_cards[] = {
"ARGOSY PnPIDE D5",
NULL
};
static int identify(volatile char *p)
{
char id_str[MAX_IDENT_CHARS];
char data;
char *t;
char **card;
int i, done;
if (p == NULL)
return (0); /* Don't know */
t = id_str;
done =0;
for (i=0; i<=4 && !done; ++i, p+=2) {
while ((data = *p) != '\0') {
if (data == 0xFF) {
done = 1;
break;
}
*t++ = data;
if (t == &id_str[MAX_IDENT_CHARS-1]) {
done = 1;
break;
}
p += 2;
}
if (!done)
*t++ = ' ';
}
*t = '\0';
while (--t > id_str) {
if (*t == ' ') {
*t = '\0';
} else {
break;
}
}
puts(id_str);
putc('\n');
for (card=known_cards; *card; ++card) {
debug ("## Compare against \"%s\"\n", *card);
if (strcmp(*card, id_str) == 0) { /* found! */
debug ("## CARD FOUND ##\n");
return 1;
}
}
return 0; /* don't know */
}
#endif /* CONFIG_CMD_PCMCIA */
|
1001-study-uboot
|
drivers/pcmcia/ti_pci1410a.c
|
C
|
gpl3
| 14,690
|
/****************************************************************************
*
* BIOS emulator and interface
* to Realmode X86 Emulator Library
*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1996-1999 SciTech Software, Inc.
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Module implementing the BIOS specific functions.
*
* Jason ported this file to u-boot to run the ATI video card
* video BIOS.
*
****************************************************************************/
#include <common.h>
#include "biosemui.h"
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
PARAMETERS:
intno - Interrupt number being serviced
REMARKS:
Handler for undefined interrupts.
****************************************************************************/
static void X86API undefined_intr(int intno)
{
if (BE_rdw(intno * 4 + 2) == BIOS_SEG) {
DB(printf("biosEmu: undefined interrupt %xh called!\n", intno);)
} else
X86EMU_prepareForInt(intno);
}
/****************************************************************************
PARAMETERS:
intno - Interrupt number being serviced
REMARKS:
This function handles the default system BIOS Int 10h (the default is stored
in the Int 42h vector by the system BIOS at bootup). We only need to handle
a small number of special functions used by the BIOS during POST time.
****************************************************************************/
static void X86API int42(int intno)
{
if (M.x86.R_AH == 0x12 && M.x86.R_BL == 0x32) {
if (M.x86.R_AL == 0) {
/* Enable CPU accesses to video memory */
PM_outpb(0x3c2, PM_inpb(0x3cc) | (u8) 0x02);
return;
} else if (M.x86.R_AL == 1) {
/* Disable CPU accesses to video memory */
PM_outpb(0x3c2, PM_inpb(0x3cc) & (u8) ~ 0x02);
return;
}
#ifdef DEBUG
else {
printf("int42: unknown function AH=0x12, BL=0x32, AL=%#02x\n",
M.x86.R_AL);
}
#endif
}
#ifdef DEBUG
else {
printf("int42: unknown function AH=%#02x, AL=%#02x, BL=%#02x\n",
M.x86.R_AH, M.x86.R_AL, M.x86.R_BL);
}
#endif
}
/****************************************************************************
PARAMETERS:
intno - Interrupt number being serviced
REMARKS:
This function handles the default system BIOS Int 10h. If the POST code
has not yet re-vectored the Int 10h BIOS interrupt vector, we handle this
by simply calling the int42 interrupt handler above. Very early in the
BIOS POST process, the vector gets replaced and we simply let the real
mode interrupt handler process the interrupt.
****************************************************************************/
static void X86API int10(int intno)
{
if (BE_rdw(intno * 4 + 2) == BIOS_SEG)
int42(intno);
else
X86EMU_prepareForInt(intno);
}
/* Result codes returned by the PCI BIOS */
#define SUCCESSFUL 0x00
#define FUNC_NOT_SUPPORT 0x81
#define BAD_VENDOR_ID 0x83
#define DEVICE_NOT_FOUND 0x86
#define BAD_REGISTER_NUMBER 0x87
#define SET_FAILED 0x88
#define BUFFER_TOO_SMALL 0x89
/****************************************************************************
PARAMETERS:
intno - Interrupt number being serviced
REMARKS:
This function handles the default Int 1Ah interrupt handler for the real
mode code, which provides support for the PCI BIOS functions. Since we only
want to allow the real mode BIOS code *only* see the PCI config space for
its own device, we only return information for the specific PCI config
space that we have passed in to the init function. This solves problems
when using the BIOS to warm boot a secondary adapter when there is an
identical adapter before it on the bus (some BIOS'es get confused in this
case).
****************************************************************************/
static void X86API int1A(int unused)
{
u16 pciSlot;
#ifdef __KERNEL__
u8 interface, subclass, baseclass;
/* Initialise the PCI slot number */
pciSlot = ((int)_BE_env.vgaInfo.bus << 8) |
((int)_BE_env.vgaInfo.device << 3) | (int)_BE_env.vgaInfo.function;
#else
/* Fail if no PCI device information has been registered */
if (!_BE_env.vgaInfo.pciInfo)
return;
pciSlot = (u16) (_BE_env.vgaInfo.pciInfo->slot.i >> 8);
#endif
switch (M.x86.R_AX) {
case 0xB101: /* PCI bios present? */
M.x86.R_AL = 0x00; /* no config space/special cycle generation support */
M.x86.R_EDX = 0x20494350; /* " ICP" */
M.x86.R_BX = 0x0210; /* Version 2.10 */
M.x86.R_CL = 0; /* Max bus number in system */
CLEAR_FLAG(F_CF);
break;
case 0xB102: /* Find PCI device */
M.x86.R_AH = DEVICE_NOT_FOUND;
#ifdef __KERNEL__
if (M.x86.R_DX == _BE_env.vgaInfo.VendorID &&
M.x86.R_CX == _BE_env.vgaInfo.DeviceID && M.x86.R_SI == 0) {
#else
if (M.x86.R_DX == _BE_env.vgaInfo.pciInfo->VendorID &&
M.x86.R_CX == _BE_env.vgaInfo.pciInfo->DeviceID &&
M.x86.R_SI == 0) {
#endif
M.x86.R_AH = SUCCESSFUL;
M.x86.R_BX = pciSlot;
}
CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
break;
case 0xB103: /* Find PCI class code */
M.x86.R_AH = DEVICE_NOT_FOUND;
#ifdef __KERNEL__
pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
&interface);
pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
&subclass);
pci_read_config_byte(_BE_env.vgaInfo.pcidev,
PCI_CLASS_DEVICE + 1, &baseclass);
if (M.x86.R_CL == interface && M.x86.R_CH == subclass
&& (u8) (M.x86.R_ECX >> 16) == baseclass) {
#else
if (M.x86.R_CL == _BE_env.vgaInfo.pciInfo->Interface &&
M.x86.R_CH == _BE_env.vgaInfo.pciInfo->SubClass &&
(u8) (M.x86.R_ECX >> 16) ==
_BE_env.vgaInfo.pciInfo->BaseClass) {
#endif
M.x86.R_AH = SUCCESSFUL;
M.x86.R_BX = pciSlot;
}
CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
break;
case 0xB108: /* Read configuration byte */
M.x86.R_AH = BAD_REGISTER_NUMBER;
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
pci_read_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
&M.x86.R_CL);
#else
M.x86.R_CL =
(u8) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_BYTE,
_BE_env.vgaInfo.pciInfo);
#endif
}
CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
break;
case 0xB109: /* Read configuration word */
M.x86.R_AH = BAD_REGISTER_NUMBER;
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
pci_read_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
&M.x86.R_CX);
#else
M.x86.R_CX =
(u16) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_WORD,
_BE_env.vgaInfo.pciInfo);
#endif
}
CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
break;
case 0xB10A: /* Read configuration dword */
M.x86.R_AH = BAD_REGISTER_NUMBER;
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
pci_read_config_dword(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, &M.x86.R_ECX);
#else
M.x86.R_ECX =
(u32) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_DWORD,
_BE_env.vgaInfo.pciInfo);
#endif
}
CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
break;
case 0xB10B: /* Write configuration byte */
M.x86.R_AH = BAD_REGISTER_NUMBER;
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
pci_write_config_byte(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, M.x86.R_CL);
#else
PCI_accessReg(M.x86.R_DI, M.x86.R_CL, PCI_WRITE_BYTE,
_BE_env.vgaInfo.pciInfo);
#endif
}
CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
break;
case 0xB10C: /* Write configuration word */
M.x86.R_AH = BAD_REGISTER_NUMBER;
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
pci_write_config_word(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, M.x86.R_CX);
#else
PCI_accessReg(M.x86.R_DI, M.x86.R_CX, PCI_WRITE_WORD,
_BE_env.vgaInfo.pciInfo);
#endif
}
CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
break;
case 0xB10D: /* Write configuration dword */
M.x86.R_AH = BAD_REGISTER_NUMBER;
if (M.x86.R_BX == pciSlot) {
M.x86.R_AH = SUCCESSFUL;
#ifdef __KERNEL__
pci_write_config_dword(_BE_env.vgaInfo.pcidev,
M.x86.R_DI, M.x86.R_ECX);
#else
PCI_accessReg(M.x86.R_DI, M.x86.R_ECX, PCI_WRITE_DWORD,
_BE_env.vgaInfo.pciInfo);
#endif
}
CONDITIONAL_SET_FLAG((M.x86.R_AH != SUCCESSFUL), F_CF);
break;
default:
printf("biosEmu/bios.int1a: unknown function AX=%#04x\n",
M.x86.R_AX);
}
}
/****************************************************************************
REMARKS:
This function initialises the BIOS emulation functions for the specific
PCI display device. We insulate the real mode BIOS from any other devices
on the bus, so that it will work correctly thinking that it is the only
device present on the bus (ie: avoiding any adapters present in from of
the device we are trying to control).
****************************************************************************/
#define BE_constLE_32(v) ((((((v)&0xff00)>>8)|(((v)&0xff)<<8))<<16)|(((((v)&0xff000000)>>8)|(((v)&0x00ff0000)<<8))>>16))
void _BE_bios_init(u32 * intrTab)
{
int i;
X86EMU_intrFuncs bios_intr_tab[256];
for (i = 0; i < 256; ++i) {
intrTab[i] = BE_constLE_32(BIOS_SEG << 16);
bios_intr_tab[i] = undefined_intr;
}
bios_intr_tab[0x10] = int10;
bios_intr_tab[0x1A] = int1A;
bios_intr_tab[0x42] = int42;
bios_intr_tab[0x6D] = int10;
X86EMU_setupIntrFuncs(bios_intr_tab);
}
|
1001-study-uboot
|
drivers/bios_emulator/bios.c
|
C
|
gpl3
| 10,916
|
/****************************************************************************
*
* BIOS emulator and interface
* to Realmode X86 Emulator Library
*
* ========================================================================
*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin<Jason.jin@freescale.com>
*
* Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved.
*
* This file may be distributed and/or modified under the terms of the
* GNU General Public License version 2.0 as published by the Free
* Software Foundation and appearing in the file LICENSE.GPL included
* in the packaging of this file.
*
* Licensees holding a valid Commercial License for this product from
* SciTech Software, Inc. may use this file in accordance with the
* Commercial License Agreement provided with the Software.
*
* This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING
* THE WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE.
*
* See http://www.scitechsoft.com/license/ for information about
* the licensing options available and how to purchase a Commercial
* License Agreement.
*
* Contact license@scitechsoft.com if any conditions of this licensing
* are not clear to you, or you have questions about licensing options.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: This file includes BIOS emulator I/O and memory access
* functions.
*
* Jason ported this file to u-boot to run the ATI video card
* BIOS in u-boot. Removed some emulate functions such as the
* timer port access. Made all the VGA port except reading 0x3c3
* be emulated. Seems like reading 0x3c3 should return the high
* 16 bit of the io port.
*
****************************************************************************/
#include <common.h>
#include "biosemui.h"
/*------------------------- Global Variables ------------------------------*/
#ifndef __i386__
static char *BE_biosDate = "08/14/99";
static u8 BE_model = 0xFC;
static u8 BE_submodel = 0x00;
#endif
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to convert
RETURNS:
Actual memory address to read or write the data
REMARKS:
This function converts an emulator memory address in a 32-bit range to
a real memory address that we wish to access. It handles splitting up the
memory address space appropriately to access the emulator BIOS image, video
memory and system BIOS etc.
****************************************************************************/
static u8 *BE_memaddr(u32 addr)
{
if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
return (u8*)(_BE_env.biosmem_base + addr - 0xC0000);
} else if (addr > _BE_env.biosmem_limit && addr < 0xD0000) {
DB(printf("BE_memaddr: address %#lx may be invalid!\n", addr);)
return M.mem_base;
} else if (addr >= 0xA0000 && addr <= 0xBFFFF) {
return (u8*)(_BE_env.busmem_base + addr - 0xA0000);
}
#ifdef __i386__
else if (addr >= 0xD0000 && addr <= 0xFFFFF) {
/* We map the real System BIOS directly on real PC's */
DB(printf("BE_memaddr: System BIOS address %#lx\n", addr);)
return _BE_env.busmem_base + addr - 0xA0000;
}
#else
else if (addr >= 0xFFFF5 && addr < 0xFFFFE) {
/* Return a faked BIOS date string for non-x86 machines */
DB(printf("BE_memaddr - Returning BIOS date\n");)
return (u8 *)(BE_biosDate + addr - 0xFFFF5);
} else if (addr == 0xFFFFE) {
/* Return system model identifier for non-x86 machines */
DB(printf("BE_memaddr - Returning model\n");)
return &BE_model;
} else if (addr == 0xFFFFF) {
/* Return system submodel identifier for non-x86 machines */
DB(printf("BE_memaddr - Returning submodel\n");)
return &BE_submodel;
}
#endif
else if (addr > M.mem_size - 1) {
HALT_SYS();
return M.mem_base;
}
return M.mem_base + addr;
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Byte value read from emulator memory.
REMARKS:
Reads a byte value from the emulator memory. We have three distinct memory
regions that are handled differently, which this function handles.
****************************************************************************/
u8 X86API BE_rdb(u32 addr)
{
if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)
return 0;
else {
u8 val = readb_le(BE_memaddr(addr));
return val;
}
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Word value read from emulator memory.
REMARKS:
Reads a word value from the emulator memory. We have three distinct memory
regions that are handled differently, which this function handles.
****************************************************************************/
u16 X86API BE_rdw(u32 addr)
{
if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)
return 0;
else {
u8 *base = BE_memaddr(addr);
u16 val = readw_le(base);
return val;
}
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Long value read from emulator memory.
REMARKS:
Reads a 32-bit value from the emulator memory. We have three distinct memory
regions that are handled differently, which this function handles.
****************************************************************************/
u32 X86API BE_rdl(u32 addr)
{
if (_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)
return 0;
else {
u8 *base = BE_memaddr(addr);
u32 val = readl_le(base);
return val;
}
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
val - Value to store
REMARKS:
Writes a byte value to emulator memory. We have three distinct memory
regions that are handled differently, which this function handles.
****************************************************************************/
void X86API BE_wrb(u32 addr, u8 val)
{
if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) {
writeb_le(BE_memaddr(addr), val);
}
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
val - Value to store
REMARKS:
Writes a word value to emulator memory. We have three distinct memory
regions that are handled differently, which this function handles.
****************************************************************************/
void X86API BE_wrw(u32 addr, u16 val)
{
if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) {
u8 *base = BE_memaddr(addr);
writew_le(base, val);
}
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
val - Value to store
REMARKS:
Writes a 32-bit value to emulator memory. We have three distinct memory
regions that are handled differently, which this function handles.
****************************************************************************/
void X86API BE_wrl(u32 addr, u32 val)
{
if (!(_BE_env.emulateVGA && addr >= 0xA0000 && addr <= 0xBFFFF)) {
u8 *base = BE_memaddr(addr);
writel_le(base, val);
}
}
#if defined(DEBUG) || !defined(__i386__)
/* For Non-Intel machines we may need to emulate some I/O port accesses that
* the BIOS may try to access, such as the PCI config registers.
*/
#define IS_TIMER_PORT(port) (0x40 <= port && port <= 0x43)
#define IS_CMOS_PORT(port) (0x70 <= port && port <= 0x71)
/*#define IS_VGA_PORT(port) (_BE_env.emulateVGA && 0x3C0 <= port && port <= 0x3DA)*/
#define IS_VGA_PORT(port) (0x3C0 <= port && port <= 0x3DA)
#define IS_PCI_PORT(port) (0xCF8 <= port && port <= 0xCFF)
#define IS_SPKR_PORT(port) (port == 0x61)
/****************************************************************************
PARAMETERS:
port - Port to read from
type - Type of access to perform
REMARKS:
Performs an emulated read from the Standard VGA I/O ports. If the target
hardware does not support mapping the VGA I/O and memory (such as some
PowerPC systems), we emulate the VGA so that the BIOS will still be able to
set NonVGA display modes such as on ATI hardware.
****************************************************************************/
static u8 VGA_inpb (const int port)
{
u8 val = 0xff;
switch (port) {
case 0x3C0:
/* 3C0 has funky characteristics because it can act as either
a data register or index register depending on the state
of an internal flip flop in the hardware. Hence we have
to emulate that functionality in here. */
if (_BE_env.flipFlop3C0 == 0) {
/* Access 3C0 as index register */
val = _BE_env.emu3C0;
} else {
/* Access 3C0 as data register */
if (_BE_env.emu3C0 < ATT_C)
val = _BE_env.emu3C1[_BE_env.emu3C0];
}
_BE_env.flipFlop3C0 ^= 1;
break;
case 0x3C1:
if (_BE_env.emu3C0 < ATT_C)
return _BE_env.emu3C1[_BE_env.emu3C0];
break;
case 0x3CC:
return _BE_env.emu3C2;
case 0x3C4:
return _BE_env.emu3C4;
case 0x3C5:
if (_BE_env.emu3C4 < ATT_C)
return _BE_env.emu3C5[_BE_env.emu3C4];
break;
case 0x3C6:
return _BE_env.emu3C6;
case 0x3C7:
return _BE_env.emu3C7;
case 0x3C8:
return _BE_env.emu3C8;
case 0x3C9:
if (_BE_env.emu3C7 < PAL_C)
return _BE_env.emu3C9[_BE_env.emu3C7++];
break;
case 0x3CE:
return _BE_env.emu3CE;
case 0x3CF:
if (_BE_env.emu3CE < GRA_C)
return _BE_env.emu3CF[_BE_env.emu3CE];
break;
case 0x3D4:
if (_BE_env.emu3C2 & 0x1)
return _BE_env.emu3D4;
break;
case 0x3D5:
if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C))
return _BE_env.emu3D5[_BE_env.emu3D4];
break;
case 0x3DA:
_BE_env.flipFlop3C0 = 0;
val = _BE_env.emu3DA;
_BE_env.emu3DA ^= 0x9;
break;
}
return val;
}
/****************************************************************************
PARAMETERS:
port - Port to write to
type - Type of access to perform
REMARKS:
Performs an emulated write to one of the 8253 timer registers. For now
we only emulate timer 0 which is the only timer that the BIOS code appears
to use.
****************************************************************************/
static void VGA_outpb (int port, u8 val)
{
switch (port) {
case 0x3C0:
/* 3C0 has funky characteristics because it can act as either
a data register or index register depending on the state
of an internal flip flop in the hardware. Hence we have
to emulate that functionality in here. */
if (_BE_env.flipFlop3C0 == 0) {
/* Access 3C0 as index register */
_BE_env.emu3C0 = val;
} else {
/* Access 3C0 as data register */
if (_BE_env.emu3C0 < ATT_C)
_BE_env.emu3C1[_BE_env.emu3C0] = val;
}
_BE_env.flipFlop3C0 ^= 1;
break;
case 0x3C2:
_BE_env.emu3C2 = val;
break;
case 0x3C4:
_BE_env.emu3C4 = val;
break;
case 0x3C5:
if (_BE_env.emu3C4 < ATT_C)
_BE_env.emu3C5[_BE_env.emu3C4] = val;
break;
case 0x3C6:
_BE_env.emu3C6 = val;
break;
case 0x3C7:
_BE_env.emu3C7 = (int) val *3;
break;
case 0x3C8:
_BE_env.emu3C8 = (int) val *3;
break;
case 0x3C9:
if (_BE_env.emu3C8 < PAL_C)
_BE_env.emu3C9[_BE_env.emu3C8++] = val;
break;
case 0x3CE:
_BE_env.emu3CE = val;
break;
case 0x3CF:
if (_BE_env.emu3CE < GRA_C)
_BE_env.emu3CF[_BE_env.emu3CE] = val;
break;
case 0x3D4:
if (_BE_env.emu3C2 & 0x1)
_BE_env.emu3D4 = val;
break;
case 0x3D5:
if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C))
_BE_env.emu3D5[_BE_env.emu3D4] = val;
break;
}
}
/****************************************************************************
PARAMETERS:
regOffset - Offset into register space for non-DWORD accesses
value - Value to write to register for PCI_WRITE_* operations
func - Function to perform (PCIAccessRegFlags)
RETURNS:
Value read from configuration register for PCI_READ_* operations
REMARKS:
Accesses a PCI configuration space register by decoding the value currently
stored in the _BE_env.configAddress variable and passing it through to the
portable PCI_accessReg function.
****************************************************************************/
static u32 BE_accessReg(int regOffset, u32 value, int func)
{
#ifdef __KERNEL__
int function, device, bus;
u8 val8;
u16 val16;
u32 val32;
/* Decode the configuration register values for the register we wish to
* access
*/
regOffset += (_BE_env.configAddress & 0xFF);
function = (_BE_env.configAddress >> 8) & 0x7;
device = (_BE_env.configAddress >> 11) & 0x1F;
bus = (_BE_env.configAddress >> 16) & 0xFF;
/* Ignore accesses to all devices other than the one we're POSTing */
if ((function == _BE_env.vgaInfo.function) &&
(device == _BE_env.vgaInfo.device) &&
(bus == _BE_env.vgaInfo.bus)) {
switch (func) {
case REG_READ_BYTE:
pci_read_config_byte(_BE_env.vgaInfo.pcidev, regOffset,
&val8);
return val8;
case REG_READ_WORD:
pci_read_config_word(_BE_env.vgaInfo.pcidev, regOffset,
&val16);
return val16;
case REG_READ_DWORD:
pci_read_config_dword(_BE_env.vgaInfo.pcidev, regOffset,
&val32);
return val32;
case REG_WRITE_BYTE:
pci_write_config_byte(_BE_env.vgaInfo.pcidev, regOffset,
value);
return 0;
case REG_WRITE_WORD:
pci_write_config_word(_BE_env.vgaInfo.pcidev, regOffset,
value);
return 0;
case REG_WRITE_DWORD:
pci_write_config_dword(_BE_env.vgaInfo.pcidev,
regOffset, value);
return 0;
}
}
return 0;
#else
PCIDeviceInfo pciInfo;
pciInfo.mech1 = 1;
pciInfo.slot.i = 0;
pciInfo.slot.p.Function = (_BE_env.configAddress >> 8) & 0x7;
pciInfo.slot.p.Device = (_BE_env.configAddress >> 11) & 0x1F;
pciInfo.slot.p.Bus = (_BE_env.configAddress >> 16) & 0xFF;
pciInfo.slot.p.Enable = 1;
/* Ignore accesses to all devices other than the one we're POSTing */
if ((pciInfo.slot.p.Function ==
_BE_env.vgaInfo.pciInfo->slot.p.Function)
&& (pciInfo.slot.p.Device == _BE_env.vgaInfo.pciInfo->slot.p.Device)
&& (pciInfo.slot.p.Bus == _BE_env.vgaInfo.pciInfo->slot.p.Bus))
return PCI_accessReg((_BE_env.configAddress & 0xFF) + regOffset,
value, func, &pciInfo);
return 0;
#endif
}
/****************************************************************************
PARAMETERS:
port - Port to read from
type - Type of access to perform
REMARKS:
Performs an emulated read from one of the PCI configuration space registers.
We emulate this using our PCI_accessReg function which will access the PCI
configuration space registers in a portable fashion.
****************************************************************************/
static u32 PCI_inp(int port, int type)
{
switch (type) {
case REG_READ_BYTE:
if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port
&& port <= 0xCFF)
return BE_accessReg(port - 0xCFC, 0, REG_READ_BYTE);
break;
case REG_READ_WORD:
if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port
&& port <= 0xCFF)
return BE_accessReg(port - 0xCFC, 0, REG_READ_WORD);
break;
case REG_READ_DWORD:
if (port == 0xCF8)
return _BE_env.configAddress;
else if ((_BE_env.configAddress & 0x80000000) && port == 0xCFC)
return BE_accessReg(0, 0, REG_READ_DWORD);
break;
}
return 0;
}
/****************************************************************************
PARAMETERS:
port - Port to write to
type - Type of access to perform
REMARKS:
Performs an emulated write to one of the PCI control registers.
****************************************************************************/
static void PCI_outp(int port, u32 val, int type)
{
switch (type) {
case REG_WRITE_BYTE:
if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port
&& port <= 0xCFF)
BE_accessReg(port - 0xCFC, val, REG_WRITE_BYTE);
break;
case REG_WRITE_WORD:
if ((_BE_env.configAddress & 0x80000000) && 0xCFC <= port
&& port <= 0xCFF)
BE_accessReg(port - 0xCFC, val, REG_WRITE_WORD);
break;
case REG_WRITE_DWORD:
if (port == 0xCF8)
{
_BE_env.configAddress = val & 0x80FFFFFC;
}
else if ((_BE_env.configAddress & 0x80000000) && port == 0xCFC)
BE_accessReg(0, val, REG_WRITE_DWORD);
break;
}
}
#endif
/****************************************************************************
PARAMETERS:
port - Port to write to
RETURNS:
Value read from the I/O port
REMARKS:
Performs an emulated 8-bit read from an I/O port. We handle special cases
that we need to emulate in here, and fall through to reflecting the write
through to the real hardware if we don't need to special case it.
****************************************************************************/
u8 X86API BE_inb(X86EMU_pioAddr port)
{
u8 val = 0;
#if defined(DEBUG) || !defined(__i386__)
if (IS_VGA_PORT(port)){
/*seems reading port 0x3c3 return the high 16 bit of io port*/
if(port == 0x3c3)
val = LOG_inpb(port);
else
val = VGA_inpb(port);
}
else if (IS_TIMER_PORT(port))
DB(printf("Can not interept TIMER port now!\n");)
else if (IS_SPKR_PORT(port))
DB(printf("Can not interept SPEAKER port now!\n");)
else if (IS_CMOS_PORT(port))
DB(printf("Can not interept CMOS port now!\n");)
else if (IS_PCI_PORT(port))
val = PCI_inp(port, REG_READ_BYTE);
else if (port < 0x100) {
DB(printf("WARN: INVALID inb.%04X -> %02X\n", (u16) port, val);)
val = LOG_inpb(port);
} else
#endif
val = LOG_inpb(port);
return val;
}
/****************************************************************************
PARAMETERS:
port - Port to write to
RETURNS:
Value read from the I/O port
REMARKS:
Performs an emulated 16-bit read from an I/O port. We handle special cases
that we need to emulate in here, and fall through to reflecting the write
through to the real hardware if we don't need to special case it.
****************************************************************************/
u16 X86API BE_inw(X86EMU_pioAddr port)
{
u16 val = 0;
#if defined(DEBUG) || !defined(__i386__)
if (IS_PCI_PORT(port))
val = PCI_inp(port, REG_READ_WORD);
else if (port < 0x100) {
DB(printf("WARN: Maybe INVALID inw.%04X -> %04X\n", (u16) port, val);)
val = LOG_inpw(port);
} else
#endif
val = LOG_inpw(port);
return val;
}
/****************************************************************************
PARAMETERS:
port - Port to write to
RETURNS:
Value read from the I/O port
REMARKS:
Performs an emulated 32-bit read from an I/O port. We handle special cases
that we need to emulate in here, and fall through to reflecting the write
through to the real hardware if we don't need to special case it.
****************************************************************************/
u32 X86API BE_inl(X86EMU_pioAddr port)
{
u32 val = 0;
#if defined(DEBUG) || !defined(__i386__)
if (IS_PCI_PORT(port))
val = PCI_inp(port, REG_READ_DWORD);
else if (port < 0x100) {
val = LOG_inpd(port);
} else
#endif
val = LOG_inpd(port);
return val;
}
/****************************************************************************
PARAMETERS:
port - Port to write to
val - Value to write to port
REMARKS:
Performs an emulated 8-bit write to an I/O port. We handle special cases
that we need to emulate in here, and fall through to reflecting the write
through to the real hardware if we don't need to special case it.
****************************************************************************/
void X86API BE_outb(X86EMU_pioAddr port, u8 val)
{
#if defined(DEBUG) || !defined(__i386__)
if (IS_VGA_PORT(port))
VGA_outpb(port, val);
else if (IS_TIMER_PORT(port))
DB(printf("Can not interept TIMER port now!\n");)
else if (IS_SPKR_PORT(port))
DB(printf("Can not interept SPEAKER port now!\n");)
else if (IS_CMOS_PORT(port))
DB(printf("Can not interept CMOS port now!\n");)
else if (IS_PCI_PORT(port))
PCI_outp(port, val, REG_WRITE_BYTE);
else if (port < 0x100) {
DB(printf("WARN:Maybe INVALID outb.%04X <- %02X\n", (u16) port, val);)
LOG_outpb(port, val);
} else
#endif
LOG_outpb(port, val);
}
/****************************************************************************
PARAMETERS:
port - Port to write to
val - Value to write to port
REMARKS:
Performs an emulated 16-bit write to an I/O port. We handle special cases
that we need to emulate in here, and fall through to reflecting the write
through to the real hardware if we don't need to special case it.
****************************************************************************/
void X86API BE_outw(X86EMU_pioAddr port, u16 val)
{
#if defined(DEBUG) || !defined(__i386__)
if (IS_VGA_PORT(port)) {
VGA_outpb(port, val);
VGA_outpb(port + 1, val >> 8);
} else if (IS_PCI_PORT(port))
PCI_outp(port, val, REG_WRITE_WORD);
else if (port < 0x100) {
DB(printf("WARN: MAybe INVALID outw.%04X <- %04X\n", (u16) port,
val);)
LOG_outpw(port, val);
} else
#endif
LOG_outpw(port, val);
}
/****************************************************************************
PARAMETERS:
port - Port to write to
val - Value to write to port
REMARKS:
Performs an emulated 32-bit write to an I/O port. We handle special cases
that we need to emulate in here, and fall through to reflecting the write
through to the real hardware if we don't need to special case it.
****************************************************************************/
void X86API BE_outl(X86EMU_pioAddr port, u32 val)
{
#if defined(DEBUG) || !defined(__i386__)
if (IS_PCI_PORT(port))
PCI_outp(port, val, REG_WRITE_DWORD);
else if (port < 0x100) {
DB(printf("WARN: INVALID outl.%04X <- %08X\n", (u16) port,val);)
LOG_outpd(port, val);
} else
#endif
LOG_outpd(port, val);
}
|
1001-study-uboot
|
drivers/bios_emulator/besys.c
|
C
|
gpl3
| 21,981
|
/****************************************************************************
*
* Video BOOT Graphics Card POST Module
*
* ========================================================================
* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1991-2004 SciTech Software, Inc. All rights reserved.
*
* This file may be distributed and/or modified under the terms of the
* GNU General Public License version 2.0 as published by the Free
* Software Foundation and appearing in the file LICENSE.GPL included
* in the packaging of this file.
*
* Licensees holding a valid Commercial License for this product from
* SciTech Software, Inc. may use this file in accordance with the
* Commercial License Agreement provided with the Software.
*
* This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING
* THE WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE.
*
* See http://www.scitechsoft.com/license/ for information about
* the licensing options available and how to purchase a Commercial
* License Agreement.
*
* Contact license@scitechsoft.com if any conditions of this licensing
* are not clear to you, or you have questions about licensing options.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Linux Kernel
* Developer: Kendall Bennett
*
* Description: Module to implement booting PCI/AGP controllers on the
* bus. We use the x86 real mode emulator to run the BIOS on
* graphics controllers to bring the cards up.
*
* Note that at present this module does *not* support
* multiple controllers.
*
* The orignal name of this file is warmboot.c.
* Jason ported this file to u-boot to run the ATI video card
* BIOS in u-boot.
****************************************************************************/
#include <common.h>
#include "biosemui.h"
#include <malloc.h>
/* Length of the BIOS image */
#define MAX_BIOSLEN (128 * 1024L)
/* Define some useful types and macros */
#define true 1
#define false 0
/* Place to save PCI BAR's that we change and later restore */
static u32 saveROMBaseAddress;
static u32 saveBaseAddress10;
static u32 saveBaseAddress14;
static u32 saveBaseAddress18;
static u32 saveBaseAddress20;
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus to boot
VGAInfo - BIOS emulator VGA info structure
REMARKS:
This function executes the BIOS POST code on the controller. We assume that
at this stage the controller has its I/O and memory space enabled and
that all other controllers are in a disabled state.
****************************************************************************/
static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
{
RMREGS regs;
RMSREGS sregs;
/* Determine the value to store in AX for BIOS POST. Per the PCI specs,
AH must contain the bus and AL must contain the devfn, encoded as
(dev << 3) | fn
*/
memset(®s, 0, sizeof(regs));
memset(&sregs, 0, sizeof(sregs));
regs.x.ax = ((int)PCI_BUS(pcidev) << 8) |
((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
/*Setup the X86 emulator for the VGA BIOS*/
BE_setVGA(VGAInfo);
/*Execute the BIOS POST code*/
BE_callRealMode(0xC000, 0x0003, ®s, &sregs);
/*Cleanup and exit*/
BE_getVGA(VGAInfo);
}
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus
bar - Place to return the base address register offset to use
RETURNS:
The address to use to map the secondary BIOS (AGP devices)
REMARKS:
Searches all the PCI base address registers for the device looking for a
memory mapping that is large enough to hold our ROM BIOS. We usually end up
finding the framebuffer mapping (usually BAR 0x10), and we use this mapping
to map the BIOS for the device into. We use a mapping that is already
assigned to the device to ensure the memory range will be passed through
by any PCI->PCI or AGP->PCI bridge that may be present.
NOTE: Usually this function is only used for AGP devices, but it may be
used for PCI devices that have already been POST'ed and the BIOS
ROM base address has been zero'ed out.
NOTE: This function leaves the original memory aperture disabled by leaving
it programmed to all 1's. It must be restored to the correct value
later.
****************************************************************************/
static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar)
{
u32 base, size;
for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) {
pci_read_config_dword(pcidev, *bar, &base);
if (!(base & 0x1)) {
pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF);
pci_read_config_dword(pcidev, *bar, &size);
size = ~(size & ~0xFF) + 1;
if (size >= MAX_BIOSLEN)
return base & ~0xFF;
}
}
return 0;
}
/****************************************************************************
REMARKS:
Some non-x86 Linux kernels map PCI relocateable I/O to values that
are above 64K, which will not work with the BIOS image that requires
the offset for the I/O ports to be a maximum of 16-bits. Ideally
someone should fix the kernel to map the I/O ports for VGA compatible
devices to a different location (or just all I/O ports since it is
unlikely you can have enough devices in the machine to use up all
64K of the I/O space - a total of more than 256 cards would be
necessary).
Anyway to fix this we change all I/O mapped base registers and
chop off the top bits.
****************************************************************************/
static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base)
{
if ((*base & 0x1) && (*base > 0xFFFE)) {
*base &= 0xFFFF;
pci_write_config_dword(pcidev, reg, *base);
}
}
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus
RETURNS:
Pointers to the mapped BIOS image
REMARKS:
Maps a pointer to the BIOS image on the graphics card on the PCI bus.
****************************************************************************/
void *PCI_mapBIOSImage(pci_dev_t pcidev)
{
u32 BIOSImageBus;
int BIOSImageBAR;
u8 *BIOSImage;
/*Save PCI BAR registers that might get changed*/
pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
/*Fix up I/O base registers to less than 64K */
if(saveBaseAddress14 != 0)
PCI_fixupIObase(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
else
PCI_fixupIObase(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
/* Some cards have problems that stop us from being able to read the
BIOS image from the ROM BAR. To fix this we have to do some chipset
specific programming for different cards to solve this problem.
*/
BIOSImageBus = PCI_findBIOSAddr(pcidev, &BIOSImageBAR);
if (BIOSImageBus == 0) {
printf("Find bios addr error\n");
return NULL;
}
BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus,
PCI_REGION_MEM, 0, MAP_NOCACHE);
/*Change the PCI BAR registers to map it onto the bus.*/
pci_write_config_dword(pcidev, BIOSImageBAR, 0);
pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
udelay(1);
/*Check that the BIOS image is valid. If not fail, or return the
compiled in BIOS image if that option was enabled
*/
if (BIOSImage[0] != 0x55 || BIOSImage[1] != 0xAA || BIOSImage[2] == 0) {
return NULL;
}
return BIOSImage;
}
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus
REMARKS:
Unmaps the BIOS image for the device and restores framebuffer mappings
****************************************************************************/
void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage)
{
pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10);
pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14);
pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
}
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus to boot
VGAInfo - BIOS emulator VGA info structure
RETURNS:
True if successfully initialised, false if not.
REMARKS:
Loads and POST's the display controllers BIOS, directly from the BIOS
image we can extract over the PCI bus.
****************************************************************************/
static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo)
{
u32 BIOSImageLen;
uchar *mappedBIOS;
uchar *copyOfBIOS;
/*Allocate memory to store copy of BIOS from display controller*/
if ((mappedBIOS = PCI_mapBIOSImage(pcidev)) == NULL) {
printf("videoboot: Video ROM failed to map!\n");
return false;
}
BIOSImageLen = mappedBIOS[2] * 512;
if ((copyOfBIOS = malloc(BIOSImageLen)) == NULL) {
printf("videoboot: Out of memory!\n");
return false;
}
memcpy(copyOfBIOS, mappedBIOS, BIOSImageLen);
PCI_unmapBIOSImage(pcidev, mappedBIOS);
/*Save information in VGAInfo structure*/
VGAInfo->function = PCI_FUNC(pcidev);
VGAInfo->device = PCI_DEV(pcidev);
VGAInfo->bus = PCI_BUS(pcidev);
VGAInfo->pcidev = pcidev;
VGAInfo->BIOSImage = copyOfBIOS;
VGAInfo->BIOSImageLen = BIOSImageLen;
/*Now execute the BIOS POST for the device*/
if (copyOfBIOS[0] != 0x55 || copyOfBIOS[1] != 0xAA) {
printf("videoboot: Video ROM image is invalid!\n");
return false;
}
PCI_doBIOSPOST(pcidev, VGAInfo);
/*Reset the size of the BIOS image to the final size*/
VGAInfo->BIOSImageLen = copyOfBIOS[2] * 512;
return true;
}
/****************************************************************************
PARAMETERS:
pcidev - PCI device info for the video card on the bus to boot
pVGAInfo - Place to return VGA info structure is requested
cleanUp - True to clean up on exit, false to leave emulator active
REMARKS:
Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
and the X86 BIOS emulator module.
****************************************************************************/
int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp)
{
BE_VGAInfo *VGAInfo;
printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
/*Initialise the x86 BIOS emulator*/
if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
printf("videoboot: Out of memory!\n");
return false;
}
memset(VGAInfo, 0, sizeof(*VGAInfo));
BE_init(0, 65536, VGAInfo, 0);
/*Post all the display controller BIOS'es*/
if (!PCI_postController(pcidev, VGAInfo))
return false;
/*Cleanup and exit the emulator if requested. If the BIOS emulator
is needed after booting the card, we will not call BE_exit and
leave it enabled for further use (ie: VESA driver etc).
*/
if (cleanUp) {
BE_exit();
if (VGAInfo->BIOSImage)
free(VGAInfo->BIOSImage);
free(VGAInfo);
VGAInfo = NULL;
}
/*Return VGA info pointer if the caller requested it*/
if (pVGAInfo)
*pVGAInfo = VGAInfo;
return true;
}
|
1001-study-uboot
|
drivers/bios_emulator/atibios.c
|
C
|
gpl3
| 11,654
|
/****************************************************************************
*
* BIOS emulator and interface
* to Realmode X86 Emulator Library
*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1996-1999 SciTech Software, Inc.
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Internal header file for the BIOS emulator library.
*
* Jason ported this file to u-boot, Added some architecture
* related Macro.
*
****************************************************************************/
#ifndef __BIOSEMUI_H
#define __BIOSEMUI_H
#include "biosemu.h"
#include <asm/io.h>
/*---------------------- Macros and type definitions ----------------------*/
#ifdef DEBUG
#define DB(x) x
#else
#define DB(x) do{}while(0);
#endif
#define BIOS_SEG 0xfff0
extern X86EMU_sysEnv _X86EMU_env;
#define M _X86EMU_env
/* Macros to read and write values to x86 emulator memory. Memory is always
* considered to be little endian, so we use macros to do endian swapping
* where necessary.
*/
#ifdef __BIG_ENDIAN__
#define readb_le(base) *((u8*)(base))
#define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8))
#define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \
((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24))
#define writeb_le(base, v) *((u8*)(base)) = (v)
#define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \
writeb_le(base + 1, (v >> 8) & 0xff)
#define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \
writeb_le(base + 1, (v >> 8) & 0xff), \
writeb_le(base + 2, (v >> 16) & 0xff), \
writeb_le(base + 3, (v >> 24) & 0xff)
#else
#define readb_le(base) *((u8*)(base))
#define readw_le(base) *((u16*)(base))
#define readl_le(base) *((u32*)(base))
#define writeb_le(base, v) *((u8*)(base)) = (v)
#define writew_le(base, v) *((u16*)(base)) = (v)
#define writel_le(base, v) *((u32*)(base)) = (v)
#endif
/****************************************************************************
REMARKS:
Function codes passed to the emulated I/O port functions to determine the
type of operation to perform.
****************************************************************************/
typedef enum {
REG_READ_BYTE = 0,
REG_READ_WORD = 1,
REG_READ_DWORD = 2,
REG_WRITE_BYTE = 3,
REG_WRITE_WORD = 4,
REG_WRITE_DWORD = 5
} RegisterFlags;
/****************************************************************************
REMARKS:
Function codes passed to the emulated I/O port functions to determine the
type of operation to perform.
****************************************************************************/
typedef enum {
PORT_BYTE = 1,
PORT_WORD = 2,
PORT_DWORD = 3,
} PortInfoFlags;
/****************************************************************************
REMARKS:
Data structure used to describe the details for the BIOS emulator system
environment as used by the X86 emulator library.
HEADER:
biosemu.h
MEMBERS:
type - Type of port access (1 = byte, 2 = word, 3 = dword)
defVal - Default power on value
finalVal - Final value
****************************************************************************/
typedef struct {
u8 type;
u32 defVal;
u32 finalVal;
} BE_portInfo;
#define PM_inpb(port) inb(port+VIDEO_IO_OFFSET)
#define PM_inpw(port) inw(port+VIDEO_IO_OFFSET)
#define PM_inpd(port) inl(port+VIDEO_IO_OFFSET)
#define PM_outpb(port,val) outb(val,port+VIDEO_IO_OFFSET)
#define PM_outpw(port,val) outw(val,port+VIDEO_IO_OFFSET)
#define PM_outpd(port,val) outl(val,port+VIDEO_IO_OFFSET)
#define LOG_inpb(port) PM_inpb(port)
#define LOG_inpw(port) PM_inpw(port)
#define LOG_inpd(port) PM_inpd(port)
#define LOG_outpb(port,val) PM_outpb(port,val)
#define LOG_outpw(port,val) PM_outpw(port,val)
#define LOG_outpd(port,val) PM_outpd(port,val)
/*-------------------------- Function Prototypes --------------------------*/
/* bios.c */
void _BE_bios_init(u32 * intrTab);
void _BE_setup_funcs(void);
/* besys.c */
#define DEBUG_IO() (M.x86.debug & DEBUG_IO_TRACE_F)
u8 X86API BE_rdb(u32 addr);
u16 X86API BE_rdw(u32 addr);
u32 X86API BE_rdl(u32 addr);
void X86API BE_wrb(u32 addr, u8 val);
void X86API BE_wrw(u32 addr, u16 val);
void X86API BE_wrl(u32 addr, u32 val);
u8 X86API BE_inb(X86EMU_pioAddr port);
u16 X86API BE_inw(X86EMU_pioAddr port);
u32 X86API BE_inl(X86EMU_pioAddr port);
void X86API BE_outb(X86EMU_pioAddr port, u8 val);
void X86API BE_outw(X86EMU_pioAddr port, u16 val);
void X86API BE_outl(X86EMU_pioAddr port, u32 val);
#endif
/* __BIOSEMUI_H */
|
1001-study-uboot
|
drivers/bios_emulator/biosemui.h
|
C
|
gpl3
| 5,918
|
include $(TOPDIR)/config.mk
LIB := $(obj)libatibiosemu.o
X86DIR = x86emu
$(shell mkdir -p $(obj)$(X86DIR))
COBJS-$(CONFIG_BIOSEMU) = atibios.o biosemu.o besys.o bios.o \
$(X86DIR)/decode.o \
$(X86DIR)/ops2.o \
$(X86DIR)/ops.o \
$(X86DIR)/prim_ops.o \
$(X86DIR)/sys.o \
$(X86DIR)/debug.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
EXTRA_CFLAGS += -I. -I./include -I$(TOPDIR)/include \
-D__PPC__ -D__BIG_ENDIAN__
CFLAGS += $(EXTRA_CFLAGS)
HOSTCFLAGS += $(EXTRA_CFLAGS)
CPPFLAGS += $(EXTRA_CFLAGS)
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/bios_emulator/Makefile
|
Makefile
|
gpl3
| 831
|
/****************************************************************************
*
* BIOS emulator and interface
* to Realmode X86 Emulator Library
*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1996-1999 SciTech Software, Inc.
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Module implementing the system specific functions. This
* module is always compiled and linked in the OS depedent
* libraries, and never in a binary portable driver.
*
* Jason ported this file to u-boot to run the ATI video card BIOS
* in u-boot. Made all the video memory be emulated during the
* BIOS runing process which may affect the VGA function but the
* frambuffer function can work after run the BIOS.
*
****************************************************************************/
#include <malloc.h>
#include <common.h>
#include "biosemui.h"
BE_sysEnv _BE_env = {{0}};
static X86EMU_memFuncs _BE_mem __attribute__((section(GOT2_TYPE))) = {
BE_rdb,
BE_rdw,
BE_rdl,
BE_wrb,
BE_wrw,
BE_wrl,
};
static X86EMU_pioFuncs _BE_pio __attribute__((section(GOT2_TYPE))) = {
BE_inb,
BE_inw,
BE_inl,
BE_outb,
BE_outw,
BE_outl,
};
#define OFF(addr) (u16)(((addr) >> 0) & 0xffff)
#define SEG(addr) (u16)(((addr) >> 4) & 0xf000)
/****************************************************************************
PARAMETERS:
debugFlags - Flags to enable debugging options (debug builds only)
memSize - Amount of memory to allocate for real mode machine
info - Pointer to default VGA device information
REMARKS:
This functions initialises the BElib, and uses the passed in
BIOS image as the BIOS that is used and emulated at 0xC0000.
****************************************************************************/
int X86API BE_init(u32 debugFlags, int memSize, BE_VGAInfo * info, int shared)
{
#if !defined(__DRIVER__) && !defined(__KERNEL__)
PM_init();
#endif
memset(&M, 0, sizeof(M));
if (memSize < 20480){
printf("Emulator requires at least 20Kb of memory!\n");
return 0;
}
M.mem_base = malloc(memSize);
if (M.mem_base == NULL){
printf("Biosemu:Out of memory!");
return 0;
}
M.mem_size = memSize;
_BE_env.emulateVGA = 0;
_BE_env.busmem_base = (unsigned long)malloc(128 * 1024);
if ((void *)_BE_env.busmem_base == NULL){
printf("Biosemu:Out of memory!");
return 0;
}
M.x86.debug = debugFlags;
_BE_bios_init((u32*)info->LowMem);
X86EMU_setupMemFuncs(&_BE_mem);
X86EMU_setupPioFuncs(&_BE_pio);
BE_setVGA(info);
return 1;
}
/****************************************************************************
PARAMETERS:
info - Pointer to VGA device information to make current
REMARKS:
This function sets the VGA BIOS functions in the emulator to point to the
specific VGA BIOS in use. This includes swapping the BIOS interrupt
vectors, BIOS image and BIOS data area to the new BIOS. This allows the
real mode BIOS to be swapped without resetting the entire emulator.
****************************************************************************/
void X86API BE_setVGA(BE_VGAInfo * info)
{
#ifdef __KERNEL__
_BE_env.vgaInfo.function = info->function;
_BE_env.vgaInfo.device = info->device;
_BE_env.vgaInfo.bus = info->bus;
_BE_env.vgaInfo.pcidev = info->pcidev;
#else
_BE_env.vgaInfo.pciInfo = info->pciInfo;
#endif
_BE_env.vgaInfo.BIOSImage = info->BIOSImage;
if (info->BIOSImage) {
_BE_env.biosmem_base = (ulong) info->BIOSImage;
_BE_env.biosmem_limit = 0xC0000 + info->BIOSImageLen - 1;
} else {
_BE_env.biosmem_base = _BE_env.busmem_base + 0x20000;
_BE_env.biosmem_limit = 0xC7FFF;
}
if ((info->LowMem[0] == 0) && (info->LowMem[1] == 0) &&
(info->LowMem[2] == 0) && (info->LowMem[3] == 0))
_BE_bios_init((u32 *) info->LowMem);
memcpy((u8 *) M.mem_base, info->LowMem, sizeof(info->LowMem));
}
/****************************************************************************
PARAMETERS:
info - Pointer to VGA device information to retrieve current
REMARKS:
This function returns the VGA BIOS functions currently active in the
emulator, so they can be restored at a later date.
****************************************************************************/
void X86API BE_getVGA(BE_VGAInfo * info)
{
#ifdef __KERNEL__
info->function = _BE_env.vgaInfo.function;
info->device = _BE_env.vgaInfo.device;
info->bus = _BE_env.vgaInfo.bus;
info->pcidev = _BE_env.vgaInfo.pcidev;
#else
info->pciInfo = _BE_env.vgaInfo.pciInfo;
#endif
info->BIOSImage = _BE_env.vgaInfo.BIOSImage;
memcpy(info->LowMem, (u8 *) M.mem_base, sizeof(info->LowMem));
}
/****************************************************************************
PARAMETERS:
r_seg - Segment for pointer to convert
r_off - Offset for pointer to convert
REMARKS:
This function maps a real mode pointer in the emulator memory to a protected
mode pointer that can be used to directly access the memory.
NOTE: The memory is *always* in little endian format, son on non-x86
systems you will need to do endian translations to access this
memory.
****************************************************************************/
void *X86API BE_mapRealPointer(uint r_seg, uint r_off)
{
u32 addr = ((u32) r_seg << 4) + r_off;
if (addr >= 0xC0000 && addr <= _BE_env.biosmem_limit) {
return (void *)(_BE_env.biosmem_base + addr - 0xC0000);
} else if (addr >= 0xA0000 && addr <= 0xFFFFF) {
return (void *)(_BE_env.busmem_base + addr - 0xA0000);
}
return (void *)(M.mem_base + addr);
}
/****************************************************************************
PARAMETERS:
len - Return the length of the VESA buffer
rseg - Place to store VESA buffer segment
roff - Place to store VESA buffer offset
REMARKS:
This function returns the address of the VESA transfer buffer in real
_BE_piomode emulator memory. The VESA transfer buffer is always 1024 bytes long,
and located at 15Kb into the start of the real mode memory (16Kb is where
we put the real mode code we execute for issuing interrupts).
NOTE: The memory is *always* in little endian format, son on non-x86
systems you will need to do endian translations to access this
memory.
****************************************************************************/
void *X86API BE_getVESABuf(uint * len, uint * rseg, uint * roff)
{
*len = 1024;
*rseg = SEG(0x03C00);
*roff = OFF(0x03C00);
return (void *)(M.mem_base + ((u32) * rseg << 4) + *roff);
}
/****************************************************************************
REMARKS:
Cleans up and exits the emulator.
****************************************************************************/
void X86API BE_exit(void)
{
free(M.mem_base);
free((void *)_BE_env.busmem_base);
}
/****************************************************************************
PARAMETERS:
seg - Segment of code to call
off - Offset of code to call
regs - Real mode registers to load
sregs - Real mode segment registers to load
REMARKS:
This functions calls a real mode far function at the specified address,
and loads all the x86 registers from the passed in registers structure.
On exit the registers returned from the call are returned in the same
structures.
****************************************************************************/
void X86API BE_callRealMode(uint seg, uint off, RMREGS * regs, RMSREGS * sregs)
{
M.x86.R_EAX = regs->e.eax;
M.x86.R_EBX = regs->e.ebx;
M.x86.R_ECX = regs->e.ecx;
M.x86.R_EDX = regs->e.edx;
M.x86.R_ESI = regs->e.esi;
M.x86.R_EDI = regs->e.edi;
M.x86.R_DS = sregs->ds;
M.x86.R_ES = sregs->es;
M.x86.R_FS = sregs->fs;
M.x86.R_GS = sregs->gs;
((u8 *) M.mem_base)[0x4000] = 0x9A;
((u8 *) M.mem_base)[0x4001] = (u8) off;
((u8 *) M.mem_base)[0x4002] = (u8) (off >> 8);
((u8 *) M.mem_base)[0x4003] = (u8) seg;
((u8 *) M.mem_base)[0x4004] = (u8) (seg >> 8);
((u8 *) M.mem_base)[0x4005] = 0xF1; /* Illegal op-code */
M.x86.R_CS = SEG(0x04000);
M.x86.R_IP = OFF(0x04000);
M.x86.R_SS = SEG(M.mem_size - 2);
M.x86.R_SP = OFF(M.mem_size - 2) + 2;
X86EMU_exec();
regs->e.cflag = M.x86.R_EFLG & F_CF;
regs->e.eax = M.x86.R_EAX;
regs->e.ebx = M.x86.R_EBX;
regs->e.ecx = M.x86.R_ECX;
regs->e.edx = M.x86.R_EDX;
regs->e.esi = M.x86.R_ESI;
regs->e.edi = M.x86.R_EDI;
sregs->ds = M.x86.R_DS;
sregs->es = M.x86.R_ES;
sregs->fs = M.x86.R_FS;
sregs->gs = M.x86.R_GS;
}
/****************************************************************************
PARAMETERS:
intno - Interrupt number to execute
in - Real mode registers to load
out - Place to store resulting real mode registers
REMARKS:
This functions calls a real mode interrupt function at the specified address,
and loads all the x86 registers from the passed in registers structure.
On exit the registers returned from the call are returned in out stucture.
****************************************************************************/
int X86API BE_int86(int intno, RMREGS * in, RMREGS * out)
{
M.x86.R_EAX = in->e.eax;
M.x86.R_EBX = in->e.ebx;
M.x86.R_ECX = in->e.ecx;
M.x86.R_EDX = in->e.edx;
M.x86.R_ESI = in->e.esi;
M.x86.R_EDI = in->e.edi;
((u8 *) M.mem_base)[0x4000] = 0xCD;
((u8 *) M.mem_base)[0x4001] = (u8) intno;
((u8 *) M.mem_base)[0x4002] = 0xF1;
M.x86.R_CS = SEG(0x04000);
M.x86.R_IP = OFF(0x04000);
M.x86.R_SS = SEG(M.mem_size - 1);
M.x86.R_SP = OFF(M.mem_size - 1) - 1;
X86EMU_exec();
out->e.cflag = M.x86.R_EFLG & F_CF;
out->e.eax = M.x86.R_EAX;
out->e.ebx = M.x86.R_EBX;
out->e.ecx = M.x86.R_ECX;
out->e.edx = M.x86.R_EDX;
out->e.esi = M.x86.R_ESI;
out->e.edi = M.x86.R_EDI;
return out->x.ax;
}
/****************************************************************************
PARAMETERS:
intno - Interrupt number to execute
in - Real mode registers to load
out - Place to store resulting real mode registers
sregs - Real mode segment registers to load
REMARKS:
This functions calls a real mode interrupt function at the specified address,
and loads all the x86 registers from the passed in registers structure.
On exit the registers returned from the call are returned in out stucture.
****************************************************************************/
int X86API BE_int86x(int intno, RMREGS * in, RMREGS * out, RMSREGS * sregs)
{
M.x86.R_EAX = in->e.eax;
M.x86.R_EBX = in->e.ebx;
M.x86.R_ECX = in->e.ecx;
M.x86.R_EDX = in->e.edx;
M.x86.R_ESI = in->e.esi;
M.x86.R_EDI = in->e.edi;
M.x86.R_DS = sregs->ds;
M.x86.R_ES = sregs->es;
M.x86.R_FS = sregs->fs;
M.x86.R_GS = sregs->gs;
((u8 *) M.mem_base)[0x4000] = 0xCD;
((u8 *) M.mem_base)[0x4001] = (u8) intno;
((u8 *) M.mem_base)[0x4002] = 0xF1;
M.x86.R_CS = SEG(0x04000);
M.x86.R_IP = OFF(0x04000);
M.x86.R_SS = SEG(M.mem_size - 1);
M.x86.R_SP = OFF(M.mem_size - 1) - 1;
X86EMU_exec();
out->e.cflag = M.x86.R_EFLG & F_CF;
out->e.eax = M.x86.R_EAX;
out->e.ebx = M.x86.R_EBX;
out->e.ecx = M.x86.R_ECX;
out->e.edx = M.x86.R_EDX;
out->e.esi = M.x86.R_ESI;
out->e.edi = M.x86.R_EDI;
sregs->ds = M.x86.R_DS;
sregs->es = M.x86.R_ES;
sregs->fs = M.x86.R_FS;
sregs->gs = M.x86.R_GS;
return out->x.ax;
}
|
1001-study-uboot
|
drivers/bios_emulator/biosemu.c
|
C
|
gpl3
| 12,321
|
/****************************************************************************
* Realmode X86 Emulator Library
*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: This file includes subroutines to implement the decoding
* and emulation of all the x86 processor instructions.
*
* There are approximately 250 subroutines in here, which correspond
* to the 256 byte-"opcodes" found on the 8086. The table which
* dispatches this is found in the files optab.[ch].
*
* Each opcode proc has a comment preceeding it which gives it's table
* address. Several opcodes are missing (undefined) in the table.
*
* Each proc includes information for decoding (DECODE_PRINTF and
* DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc
* functions (START_OF_INSTR, END_OF_INSTR).
*
* Many of the procedures are *VERY* similar in coding. This has
* allowed for a very large amount of code to be generated in a fairly
* short amount of time (i.e. cut, paste, and modify). The result is
* that much of the code below could have been folded into subroutines
* for a large reduction in size of this file. The downside would be
* that there would be a penalty in execution speed. The file could
* also have been *MUCH* larger by inlining certain functions which
* were called. This could have resulted even faster execution. The
* prime directive I used to decide whether to inline the code or to
* modularize it, was basically: 1) no unnecessary subroutine calls,
* 2) no routines more than about 200 lines in size, and 3) modularize
* any code that I might not get right the first time. The fetch_*
* subroutines fall into the latter category. The The decode_* fall
* into the second category. The coding of the "switch(mod){ .... }"
* in many of the subroutines below falls into the first category.
* Especially, the coding of {add,and,or,sub,...}_{byte,word}
* subroutines are an especially glaring case of the third guideline.
* Since so much of the code is cloned from other modules (compare
* opcode #00 to opcode #01), making the basic operations subroutine
* calls is especially important; otherwise mistakes in coding an
* "add" would represent a nightmare in maintenance.
*
****************************************************************************/
#include <common.h>
#include "x86emu/x86emui.h"
/*----------------------------- Implementation ----------------------------*/
/* constant arrays to do several instructions in just one function */
#ifdef DEBUG
static char *x86emu_GenOpName[8] = {
"ADD", "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP"};
#endif
/* used by several opcodes */
static u8 (*genop_byte_operation[])(u8 d, u8 s) =
{
add_byte, /* 00 */
or_byte, /* 01 */
adc_byte, /* 02 */
sbb_byte, /* 03 */
and_byte, /* 04 */
sub_byte, /* 05 */
xor_byte, /* 06 */
cmp_byte, /* 07 */
};
static u16 (*genop_word_operation[])(u16 d, u16 s) =
{
add_word, /*00 */
or_word, /*01 */
adc_word, /*02 */
sbb_word, /*03 */
and_word, /*04 */
sub_word, /*05 */
xor_word, /*06 */
cmp_word, /*07 */
};
static u32 (*genop_long_operation[])(u32 d, u32 s) =
{
add_long, /*00 */
or_long, /*01 */
adc_long, /*02 */
sbb_long, /*03 */
and_long, /*04 */
sub_long, /*05 */
xor_long, /*06 */
cmp_long, /*07 */
};
/* used by opcodes 80, c0, d0, and d2. */
static u8(*opcD0_byte_operation[])(u8 d, u8 s) =
{
rol_byte,
ror_byte,
rcl_byte,
rcr_byte,
shl_byte,
shr_byte,
shl_byte, /* sal_byte === shl_byte by definition */
sar_byte,
};
/* used by opcodes c1, d1, and d3. */
static u16(*opcD1_word_operation[])(u16 s, u8 d) =
{
rol_word,
ror_word,
rcl_word,
rcr_word,
shl_word,
shr_word,
shl_word, /* sal_byte === shl_byte by definition */
sar_word,
};
/* used by opcodes c1, d1, and d3. */
static u32 (*opcD1_long_operation[])(u32 s, u8 d) =
{
rol_long,
ror_long,
rcl_long,
rcr_long,
shl_long,
shr_long,
shl_long, /* sal_byte === shl_byte by definition */
sar_long,
};
#ifdef DEBUG
static char *opF6_names[8] =
{ "TEST\t", "", "NOT\t", "NEG\t", "MUL\t", "IMUL\t", "DIV\t", "IDIV\t" };
#endif
/****************************************************************************
PARAMETERS:
op1 - Instruction op code
REMARKS:
Handles illegal opcodes.
****************************************************************************/
void x86emuOp_illegal_op(
u8 op1)
{
START_OF_INSTR();
if (M.x86.R_SP != 0) {
DECODE_PRINTF("ILLEGAL X86 OPCODE\n");
TRACE_REGS();
DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n",
M.x86.R_CS, M.x86.R_IP-1,op1));
HALT_SYS();
}
else {
/* If we get here, it means the stack pointer is back to zero
* so we are just returning from an emulator service call
* so therte is no need to display an error message. We trap
* the emulator with an 0xF1 opcode to finish the service
* call.
*/
X86EMU_halt_sys();
}
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcodes 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38
****************************************************************************/
void x86emuOp_genop_byte_RM_R(u8 op1)
{
int mod, rl, rh;
uint destoffset;
u8 *destreg, *srcreg;
u8 destval;
op1 = (op1 >> 3) & 0x7;
START_OF_INSTR();
DECODE_PRINTF(x86emu_GenOpName[op1]);
DECODE_PRINTF("\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if(mod<3)
{ destoffset = decode_rmXX_address(mod,rl);
DECODE_PRINTF(",");
destval = fetch_data_byte(destoffset);
srcreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = genop_byte_operation[op1](destval, *srcreg);
store_data_byte(destoffset, destval);
}
else
{ /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = genop_byte_operation[op1](*destreg, *srcreg);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcodes 0x01, 0x09, 0x11, 0x19, 0x21, 0x29, 0x31, 0x39
****************************************************************************/
void x86emuOp_genop_word_RM_R(u8 op1)
{
int mod, rl, rh;
uint destoffset;
op1 = (op1 >> 3) & 0x7;
START_OF_INSTR();
DECODE_PRINTF(x86emu_GenOpName[op1]);
DECODE_PRINTF("\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if(mod<3) {
destoffset = decode_rmXX_address(mod,rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
u32 *srcreg;
DECODE_PRINTF(",");
destval = fetch_data_long(destoffset);
srcreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = genop_long_operation[op1](destval, *srcreg);
store_data_long(destoffset, destval);
} else {
u16 destval;
u16 *srcreg;
DECODE_PRINTF(",");
destval = fetch_data_word(destoffset);
srcreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = genop_word_operation[op1](destval, *srcreg);
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*srcreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = genop_long_operation[op1](*destreg, *srcreg);
} else {
u16 *destreg,*srcreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = genop_word_operation[op1](*destreg, *srcreg);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcodes 0x02, 0x0a, 0x12, 0x1a, 0x22, 0x2a, 0x32, 0x3a
****************************************************************************/
void x86emuOp_genop_byte_R_RM(u8 op1)
{
int mod, rl, rh;
u8 *destreg, *srcreg;
uint srcoffset;
u8 srcval;
op1 = (op1 >> 3) & 0x7;
START_OF_INSTR();
DECODE_PRINTF(x86emu_GenOpName[op1]);
DECODE_PRINTF("\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod,rl);
srcval = fetch_data_byte(srcoffset);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rl);
srcval = *srcreg;
}
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = genop_byte_operation[op1](*destreg, srcval);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcodes 0x03, 0x0b, 0x13, 0x1b, 0x23, 0x2b, 0x33, 0x3b
****************************************************************************/
void x86emuOp_genop_word_R_RM(u8 op1)
{
int mod, rl, rh;
uint srcoffset;
u32 *destreg32, srcval;
u16 *destreg;
op1 = (op1 >> 3) & 0x7;
START_OF_INSTR();
DECODE_PRINTF(x86emu_GenOpName[op1]);
DECODE_PRINTF("\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcoffset = decode_rmXX_address(mod,rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
destreg32 = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcval = fetch_data_long(srcoffset);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg32 = genop_long_operation[op1](*destreg32, srcval);
} else {
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcval = fetch_data_word(srcoffset);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = genop_word_operation[op1](*destreg, srcval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg;
destreg32 = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg32 = genop_long_operation[op1](*destreg32, *srcreg);
} else {
u16 *srcreg;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = genop_word_operation[op1](*destreg, *srcreg);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcodes 0x04, 0x0c, 0x14, 0x1c, 0x24, 0x2c, 0x34, 0x3c
****************************************************************************/
void x86emuOp_genop_byte_AL_IMM(u8 op1)
{
u8 srcval;
op1 = (op1 >> 3) & 0x7;
START_OF_INSTR();
DECODE_PRINTF(x86emu_GenOpName[op1]);
DECODE_PRINTF("\tAL,");
srcval = fetch_byte_imm();
DECODE_PRINTF2("%x\n", srcval);
TRACE_AND_STEP();
M.x86.R_AL = genop_byte_operation[op1](M.x86.R_AL, srcval);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcodes 0x05, 0x0d, 0x15, 0x1d, 0x25, 0x2d, 0x35, 0x3d
****************************************************************************/
void x86emuOp_genop_word_AX_IMM(u8 op1)
{
u32 srcval;
op1 = (op1 >> 3) & 0x7;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF(x86emu_GenOpName[op1]);
DECODE_PRINTF("\tEAX,");
srcval = fetch_long_imm();
} else {
DECODE_PRINTF(x86emu_GenOpName[op1]);
DECODE_PRINTF("\tAX,");
srcval = fetch_word_imm();
}
DECODE_PRINTF2("%x\n", srcval);
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval);
} else {
M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x06
****************************************************************************/
void x86emuOp_push_ES(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("PUSH\tES\n");
TRACE_AND_STEP();
push_word(M.x86.R_ES);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x07
****************************************************************************/
void x86emuOp_pop_ES(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("POP\tES\n");
TRACE_AND_STEP();
M.x86.R_ES = pop_word();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0e
****************************************************************************/
void x86emuOp_push_CS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("PUSH\tCS\n");
TRACE_AND_STEP();
push_word(M.x86.R_CS);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f. Escape for two-byte opcode (286 or better)
****************************************************************************/
void x86emuOp_two_byte(u8 X86EMU_UNUSED(op1))
{
u8 op2 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
INC_DECODED_INST_LEN(1);
(*x86emu_optab2[op2])(op2);
}
/****************************************************************************
REMARKS:
Handles opcode 0x16
****************************************************************************/
void x86emuOp_push_SS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("PUSH\tSS\n");
TRACE_AND_STEP();
push_word(M.x86.R_SS);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x17
****************************************************************************/
void x86emuOp_pop_SS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("POP\tSS\n");
TRACE_AND_STEP();
M.x86.R_SS = pop_word();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x1e
****************************************************************************/
void x86emuOp_push_DS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("PUSH\tDS\n");
TRACE_AND_STEP();
push_word(M.x86.R_DS);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x1f
****************************************************************************/
void x86emuOp_pop_DS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("POP\tDS\n");
TRACE_AND_STEP();
M.x86.R_DS = pop_word();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x26
****************************************************************************/
void x86emuOp_segovr_ES(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("ES:\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_SEGOVR_ES;
/*
* note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4
* opcode subroutines we do not want to do this.
*/
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x27
****************************************************************************/
void x86emuOp_daa(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("DAA\n");
TRACE_AND_STEP();
M.x86.R_AL = daa_byte(M.x86.R_AL);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x2e
****************************************************************************/
void x86emuOp_segovr_CS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("CS:\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_SEGOVR_CS;
/* note no DECODE_CLEAR_SEGOVR here. */
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x2f
****************************************************************************/
void x86emuOp_das(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("DAS\n");
TRACE_AND_STEP();
M.x86.R_AL = das_byte(M.x86.R_AL);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x36
****************************************************************************/
void x86emuOp_segovr_SS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("SS:\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_SEGOVR_SS;
/* no DECODE_CLEAR_SEGOVR ! */
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x37
****************************************************************************/
void x86emuOp_aaa(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("AAA\n");
TRACE_AND_STEP();
M.x86.R_AX = aaa_word(M.x86.R_AX);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x3e
****************************************************************************/
void x86emuOp_segovr_DS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("DS:\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_SEGOVR_DS;
/* NO DECODE_CLEAR_SEGOVR! */
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x3f
****************************************************************************/
void x86emuOp_aas(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("AAS\n");
TRACE_AND_STEP();
M.x86.R_AX = aas_word(M.x86.R_AX);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x40 - 0x47
****************************************************************************/
void x86emuOp_inc_register(u8 op1)
{
START_OF_INSTR();
op1 &= 0x7;
DECODE_PRINTF("INC\t");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *reg;
reg = DECODE_RM_LONG_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*reg = inc_long(*reg);
} else {
u16 *reg;
reg = DECODE_RM_WORD_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*reg = inc_word(*reg);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x48 - 0x4F
****************************************************************************/
void x86emuOp_dec_register(u8 op1)
{
START_OF_INSTR();
op1 &= 0x7;
DECODE_PRINTF("DEC\t");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *reg;
reg = DECODE_RM_LONG_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*reg = dec_long(*reg);
} else {
u16 *reg;
reg = DECODE_RM_WORD_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*reg = dec_word(*reg);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x50 - 0x57
****************************************************************************/
void x86emuOp_push_register(u8 op1)
{
START_OF_INSTR();
op1 &= 0x7;
DECODE_PRINTF("PUSH\t");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *reg;
reg = DECODE_RM_LONG_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
push_long(*reg);
} else {
u16 *reg;
reg = DECODE_RM_WORD_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
push_word(*reg);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x58 - 0x5F
****************************************************************************/
void x86emuOp_pop_register(u8 op1)
{
START_OF_INSTR();
op1 &= 0x7;
DECODE_PRINTF("POP\t");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *reg;
reg = DECODE_RM_LONG_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*reg = pop_long();
} else {
u16 *reg;
reg = DECODE_RM_WORD_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*reg = pop_word();
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x60
****************************************************************************/
void x86emuOp_push_all(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("PUSHAD\n");
} else {
DECODE_PRINTF("PUSHA\n");
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 old_sp = M.x86.R_ESP;
push_long(M.x86.R_EAX);
push_long(M.x86.R_ECX);
push_long(M.x86.R_EDX);
push_long(M.x86.R_EBX);
push_long(old_sp);
push_long(M.x86.R_EBP);
push_long(M.x86.R_ESI);
push_long(M.x86.R_EDI);
} else {
u16 old_sp = M.x86.R_SP;
push_word(M.x86.R_AX);
push_word(M.x86.R_CX);
push_word(M.x86.R_DX);
push_word(M.x86.R_BX);
push_word(old_sp);
push_word(M.x86.R_BP);
push_word(M.x86.R_SI);
push_word(M.x86.R_DI);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x61
****************************************************************************/
void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("POPAD\n");
} else {
DECODE_PRINTF("POPA\n");
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
M.x86.R_EDI = pop_long();
M.x86.R_ESI = pop_long();
M.x86.R_EBP = pop_long();
M.x86.R_ESP += 4; /* skip ESP */
M.x86.R_EBX = pop_long();
M.x86.R_EDX = pop_long();
M.x86.R_ECX = pop_long();
M.x86.R_EAX = pop_long();
} else {
M.x86.R_DI = pop_word();
M.x86.R_SI = pop_word();
M.x86.R_BP = pop_word();
M.x86.R_SP += 2; /* skip SP */
M.x86.R_BX = pop_word();
M.x86.R_DX = pop_word();
M.x86.R_CX = pop_word();
M.x86.R_AX = pop_word();
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */
/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */
/****************************************************************************
REMARKS:
Handles opcode 0x64
****************************************************************************/
void x86emuOp_segovr_FS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("FS:\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_SEGOVR_FS;
/*
* note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4
* opcode subroutines we do not want to do this.
*/
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x65
****************************************************************************/
void x86emuOp_segovr_GS(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("GS:\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_SEGOVR_GS;
/*
* note the lack of DECODE_CLEAR_SEGOVR(r) since, here is one of 4
* opcode subroutines we do not want to do this.
*/
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x66 - prefix for 32-bit register
****************************************************************************/
void x86emuOp_prefix_data(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("DATA:\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_PREFIX_DATA;
/* note no DECODE_CLEAR_SEGOVR here. */
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x67 - prefix for 32-bit address
****************************************************************************/
void x86emuOp_prefix_addr(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("ADDR:\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_PREFIX_ADDR;
/* note no DECODE_CLEAR_SEGOVR here. */
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x68
****************************************************************************/
void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1))
{
u32 imm;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
imm = fetch_long_imm();
} else {
imm = fetch_word_imm();
}
DECODE_PRINTF2("PUSH\t%x\n", imm);
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
push_long(imm);
} else {
push_word((u16)imm);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x69
****************************************************************************/
void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("IMUL\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 srcval;
u32 res_lo,res_hi;
s32 imm;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcval = fetch_data_long(srcoffset);
imm = fetch_long_imm();
DECODE_PRINTF2(",%d\n", (s32)imm);
TRACE_AND_STEP();
imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
(((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
*destreg = (u32)res_lo;
} else {
u16 *destreg;
u16 srcval;
u32 res;
s16 imm;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcval = fetch_data_word(srcoffset);
imm = fetch_word_imm();
DECODE_PRINTF2(",%d\n", (s32)imm);
TRACE_AND_STEP();
res = (s16)srcval * (s16)imm;
if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
(((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
*destreg = (u16)res;
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*srcreg;
u32 res_lo,res_hi;
s32 imm;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rl);
imm = fetch_long_imm();
DECODE_PRINTF2(",%d\n", (s32)imm);
TRACE_AND_STEP();
imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm);
if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
(((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
*destreg = (u32)res_lo;
} else {
u16 *destreg,*srcreg;
u32 res;
s16 imm;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rl);
imm = fetch_word_imm();
DECODE_PRINTF2(",%d\n", (s32)imm);
res = (s16)*srcreg * (s16)imm;
if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
(((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
*destreg = (u16)res;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x6a
****************************************************************************/
void x86emuOp_push_byte_IMM(u8 X86EMU_UNUSED(op1))
{
s16 imm;
START_OF_INSTR();
imm = (s8)fetch_byte_imm();
DECODE_PRINTF2("PUSH\t%d\n", imm);
TRACE_AND_STEP();
push_word(imm);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x6b
****************************************************************************/
void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint srcoffset;
s8 imm;
START_OF_INSTR();
DECODE_PRINTF("IMUL\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 srcval;
u32 res_lo,res_hi;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcval = fetch_data_long(srcoffset);
imm = fetch_byte_imm();
DECODE_PRINTF2(",%d\n", (s32)imm);
TRACE_AND_STEP();
imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm);
if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
(((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
*destreg = (u32)res_lo;
} else {
u16 *destreg;
u16 srcval;
u32 res;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcval = fetch_data_word(srcoffset);
imm = fetch_byte_imm();
DECODE_PRINTF2(",%d\n", (s32)imm);
TRACE_AND_STEP();
res = (s16)srcval * (s16)imm;
if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
(((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
*destreg = (u16)res;
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*srcreg;
u32 res_lo,res_hi;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rl);
imm = fetch_byte_imm();
DECODE_PRINTF2(",%d\n", (s32)imm);
TRACE_AND_STEP();
imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm);
if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) ||
(((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
*destreg = (u32)res_lo;
} else {
u16 *destreg,*srcreg;
u32 res;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rl);
imm = fetch_byte_imm();
DECODE_PRINTF2(",%d\n", (s32)imm);
TRACE_AND_STEP();
res = (s16)*srcreg * (s16)imm;
if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) ||
(((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
*destreg = (u16)res;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x6c
****************************************************************************/
void x86emuOp_ins_byte(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("INSB\n");
ins(1);
TRACE_AND_STEP();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x6d
****************************************************************************/
void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("INSD\n");
ins(4);
} else {
DECODE_PRINTF("INSW\n");
ins(2);
}
TRACE_AND_STEP();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x6e
****************************************************************************/
void x86emuOp_outs_byte(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("OUTSB\n");
outs(1);
TRACE_AND_STEP();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x6f
****************************************************************************/
void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("OUTSD\n");
outs(4);
} else {
DECODE_PRINTF("OUTSW\n");
outs(2);
}
TRACE_AND_STEP();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x70 - 0x7F
****************************************************************************/
int x86emu_check_jump_condition(u8 op);
void x86emuOp_jump_near_cond(u8 op1)
{
s8 offset;
u16 target;
int cond;
/* jump to byte offset if overflow flag is set */
START_OF_INSTR();
cond = x86emu_check_jump_condition(op1 & 0xF);
offset = (s8)fetch_byte_imm();
target = (u16)(M.x86.R_IP + (s16)offset);
DECODE_PRINTF2("%x\n", target);
TRACE_AND_STEP();
if (cond)
M.x86.R_IP = target;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x80
****************************************************************************/
void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg;
uint destoffset;
u8 imm;
u8 destval;
/*
* Weirdo special case instruction format. Part of the opcode
* held below in "RH". Doubly nested case would result, except
* that the decoded instruction
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ADD\t");
break;
case 1:
DECODE_PRINTF("OR\t");
break;
case 2:
DECODE_PRINTF("ADC\t");
break;
case 3:
DECODE_PRINTF("SBB\t");
break;
case 4:
DECODE_PRINTF("AND\t");
break;
case 5:
DECODE_PRINTF("SUB\t");
break;
case 6:
DECODE_PRINTF("XOR\t");
break;
case 7:
DECODE_PRINTF("CMP\t");
break;
}
}
#endif
/* know operation, decode the mod byte to find the addressing
mode. */
if (mod < 3) {
DECODE_PRINTF("BYTE PTR ");
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
destval = fetch_data_byte(destoffset);
imm = fetch_byte_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_byte_operation[rh]) (destval, imm);
if (rh != 7)
store_data_byte(destoffset, destval);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF(",");
imm = fetch_byte_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_byte_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x81
****************************************************************************/
void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
/*
* Weirdo special case instruction format. Part of the opcode
* held below in "RH". Doubly nested case would result, except
* that the decoded instruction
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ADD\t");
break;
case 1:
DECODE_PRINTF("OR\t");
break;
case 2:
DECODE_PRINTF("ADC\t");
break;
case 3:
DECODE_PRINTF("SBB\t");
break;
case 4:
DECODE_PRINTF("AND\t");
break;
case 5:
DECODE_PRINTF("SUB\t");
break;
case 6:
DECODE_PRINTF("XOR\t");
break;
case 7:
DECODE_PRINTF("CMP\t");
break;
}
}
#endif
/*
* Know operation, decode the mod byte to find the addressing
* mode.
*/
if (mod < 3) {
DECODE_PRINTF("DWORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval,imm;
DECODE_PRINTF(",");
destval = fetch_data_long(destoffset);
imm = fetch_long_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_long_operation[rh]) (destval, imm);
if (rh != 7)
store_data_long(destoffset, destval);
} else {
u16 destval,imm;
DECODE_PRINTF(",");
destval = fetch_data_word(destoffset);
imm = fetch_word_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_word_operation[rh]) (destval, imm);
if (rh != 7)
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 destval,imm;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
imm = fetch_long_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_long_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
} else {
u16 *destreg;
u16 destval,imm;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
imm = fetch_word_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_word_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x82
****************************************************************************/
void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg;
uint destoffset;
u8 imm;
u8 destval;
/*
* Weirdo special case instruction format. Part of the opcode
* held below in "RH". Doubly nested case would result, except
* that the decoded instruction Similar to opcode 81, except that
* the immediate byte is sign extended to a word length.
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ADD\t");
break;
case 1:
DECODE_PRINTF("OR\t");
break;
case 2:
DECODE_PRINTF("ADC\t");
break;
case 3:
DECODE_PRINTF("SBB\t");
break;
case 4:
DECODE_PRINTF("AND\t");
break;
case 5:
DECODE_PRINTF("SUB\t");
break;
case 6:
DECODE_PRINTF("XOR\t");
break;
case 7:
DECODE_PRINTF("CMP\t");
break;
}
}
#endif
/* know operation, decode the mod byte to find the addressing
mode. */
if (mod < 3) {
DECODE_PRINTF("BYTE PTR ");
destoffset = decode_rmXX_address(mod, rl);
destval = fetch_data_byte(destoffset);
imm = fetch_byte_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_byte_operation[rh]) (destval, imm);
if (rh != 7)
store_data_byte(destoffset, destval);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
imm = fetch_byte_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_byte_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x83
****************************************************************************/
void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
/*
* Weirdo special case instruction format. Part of the opcode
* held below in "RH". Doubly nested case would result, except
* that the decoded instruction Similar to opcode 81, except that
* the immediate byte is sign extended to a word length.
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ADD\t");
break;
case 1:
DECODE_PRINTF("OR\t");
break;
case 2:
DECODE_PRINTF("ADC\t");
break;
case 3:
DECODE_PRINTF("SBB\t");
break;
case 4:
DECODE_PRINTF("AND\t");
break;
case 5:
DECODE_PRINTF("SUB\t");
break;
case 6:
DECODE_PRINTF("XOR\t");
break;
case 7:
DECODE_PRINTF("CMP\t");
break;
}
}
#endif
/* know operation, decode the mod byte to find the addressing
mode. */
if (mod < 3) {
DECODE_PRINTF("DWORD PTR ");
destoffset = decode_rmXX_address(mod,rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval,imm;
destval = fetch_data_long(destoffset);
imm = (s8) fetch_byte_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_long_operation[rh]) (destval, imm);
if (rh != 7)
store_data_long(destoffset, destval);
} else {
u16 destval,imm;
destval = fetch_data_word(destoffset);
imm = (s8) fetch_byte_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_word_operation[rh]) (destval, imm);
if (rh != 7)
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 destval,imm;
destreg = DECODE_RM_LONG_REGISTER(rl);
imm = (s8) fetch_byte_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_long_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
} else {
u16 *destreg;
u16 destval,imm;
destreg = DECODE_RM_WORD_REGISTER(rl);
imm = (s8) fetch_byte_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
destval = (*genop_word_operation[rh]) (*destreg, imm);
if (rh != 7)
*destreg = destval;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x84
****************************************************************************/
void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg, *srcreg;
uint destoffset;
u8 destval;
START_OF_INSTR();
DECODE_PRINTF("TEST\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
destval = fetch_data_byte(destoffset);
srcreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
test_byte(destval, *srcreg);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
test_byte(*destreg, *srcreg);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x85
****************************************************************************/
void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
START_OF_INSTR();
DECODE_PRINTF("TEST\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
u32 *srcreg;
DECODE_PRINTF(",");
destval = fetch_data_long(destoffset);
srcreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
test_long(destval, *srcreg);
} else {
u16 destval;
u16 *srcreg;
DECODE_PRINTF(",");
destval = fetch_data_word(destoffset);
srcreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
test_word(destval, *srcreg);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*srcreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
test_long(*destreg, *srcreg);
} else {
u16 *destreg,*srcreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
test_word(*destreg, *srcreg);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x86
****************************************************************************/
void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg, *srcreg;
uint destoffset;
u8 destval;
u8 tmp;
START_OF_INSTR();
DECODE_PRINTF("XCHG\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
destval = fetch_data_byte(destoffset);
srcreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
tmp = *srcreg;
*srcreg = destval;
destval = tmp;
store_data_byte(destoffset, destval);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
tmp = *srcreg;
*srcreg = *destreg;
*destreg = tmp;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x87
****************************************************************************/
void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
START_OF_INSTR();
DECODE_PRINTF("XCHG\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg;
u32 destval,tmp;
destval = fetch_data_long(destoffset);
srcreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
tmp = *srcreg;
*srcreg = destval;
destval = tmp;
store_data_long(destoffset, destval);
} else {
u16 *srcreg;
u16 destval,tmp;
destval = fetch_data_word(destoffset);
srcreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
tmp = *srcreg;
*srcreg = destval;
destval = tmp;
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*srcreg;
u32 tmp;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
tmp = *srcreg;
*srcreg = *destreg;
*destreg = tmp;
} else {
u16 *destreg,*srcreg;
u16 tmp;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
tmp = *srcreg;
*srcreg = *destreg;
*destreg = tmp;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x88
****************************************************************************/
void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg, *srcreg;
uint destoffset;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
store_data_byte(destoffset, *srcreg);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x89
****************************************************************************/
void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg;
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
store_data_long(destoffset, *srcreg);
} else {
u16 *srcreg;
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
store_data_word(destoffset, *srcreg);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*srcreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
} else {
u16 *destreg,*srcreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x8a
****************************************************************************/
void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg, *srcreg;
uint srcoffset;
u8 srcval;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = fetch_data_byte(srcoffset);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x8b
****************************************************************************/
void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 srcval;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = fetch_data_long(srcoffset);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
} else {
u16 *destreg;
u16 srcval;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = fetch_data_word(srcoffset);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg, *srcreg;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
} else {
u16 *destreg, *srcreg;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x8c
****************************************************************************/
void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u16 *destreg, *srcreg;
uint destoffset;
u16 destval;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
srcreg = decode_rm_seg_register(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = *srcreg;
store_data_word(destoffset, destval);
} else { /* register to register */
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
srcreg = decode_rm_seg_register(rh);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x8d
****************************************************************************/
void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u16 *srcreg;
uint destoffset;
/*
* TODO: Need to handle address size prefix!
*
* lea eax,[eax+ebx*2] ??
*/
START_OF_INSTR();
DECODE_PRINTF("LEA\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*srcreg = (u16)destoffset;
}
/* } else { undefined. Do nothing. } */
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x8e
****************************************************************************/
void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u16 *destreg, *srcreg;
uint srcoffset;
u16 srcval;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destreg = decode_rm_seg_register(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = fetch_data_word(srcoffset);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
} else { /* register to register */
destreg = decode_rm_seg_register(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
}
/*
* Clean up, and reset all the R_xSP pointers to the correct
* locations. This is about 3x too much overhead (doing all the
* segreg ptrs when only one is needed, but this instruction
* *cannot* be that common, and this isn't too much work anyway.
*/
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x8f
****************************************************************************/
void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
START_OF_INSTR();
DECODE_PRINTF("POP\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
HALT_SYS();
}
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = pop_long();
store_data_long(destoffset, destval);
} else {
u16 destval;
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = pop_word();
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = pop_long();
} else {
u16 *destreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = pop_word();
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x90
****************************************************************************/
void x86emuOp_nop(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("NOP\n");
TRACE_AND_STEP();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x91-0x97
****************************************************************************/
void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1))
{
u32 tmp;
op1 &= 0x7;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *reg32;
DECODE_PRINTF("XCHG\tEAX,");
reg32 = DECODE_RM_LONG_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
tmp = M.x86.R_EAX;
M.x86.R_EAX = *reg32;
*reg32 = tmp;
} else {
u16 *reg16;
DECODE_PRINTF("XCHG\tAX,");
reg16 = DECODE_RM_WORD_REGISTER(op1);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
tmp = M.x86.R_AX;
M.x86.R_EAX = *reg16;
*reg16 = (u16)tmp;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x98
****************************************************************************/
void x86emuOp_cbw(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("CWDE\n");
} else {
DECODE_PRINTF("CBW\n");
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
if (M.x86.R_AX & 0x8000) {
M.x86.R_EAX |= 0xffff0000;
} else {
M.x86.R_EAX &= 0x0000ffff;
}
} else {
if (M.x86.R_AL & 0x80) {
M.x86.R_AH = 0xff;
} else {
M.x86.R_AH = 0x0;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x99
****************************************************************************/
void x86emuOp_cwd(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("CDQ\n");
} else {
DECODE_PRINTF("CWD\n");
}
DECODE_PRINTF("CWD\n");
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
if (M.x86.R_EAX & 0x80000000) {
M.x86.R_EDX = 0xffffffff;
} else {
M.x86.R_EDX = 0x0;
}
} else {
if (M.x86.R_AX & 0x8000) {
M.x86.R_DX = 0xffff;
} else {
M.x86.R_DX = 0x0;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x9a
****************************************************************************/
void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1))
{
u16 farseg, faroff;
START_OF_INSTR();
DECODE_PRINTF("CALL\t");
faroff = fetch_word_imm();
farseg = fetch_word_imm();
DECODE_PRINTF2("%04x:", farseg);
DECODE_PRINTF2("%04x\n", faroff);
CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, farseg, faroff, "FAR ");
/* XXX
*
* Hooked interrupt vectors calling into our "BIOS" will cause
* problems unless all intersegment stuff is checked for BIOS
* access. Check needed here. For moment, let it alone.
*/
TRACE_AND_STEP();
push_word(M.x86.R_CS);
M.x86.R_CS = farseg;
push_word(M.x86.R_IP);
M.x86.R_IP = faroff;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x9b
****************************************************************************/
void x86emuOp_wait(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("WAIT");
TRACE_AND_STEP();
/* NADA. */
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x9c
****************************************************************************/
void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1))
{
u32 flags;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("PUSHFD\n");
} else {
DECODE_PRINTF("PUSHF\n");
}
TRACE_AND_STEP();
/* clear out *all* bits not representing flags, and turn on real bits */
flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON;
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
push_long(flags);
} else {
push_word((u16)flags);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x9d
****************************************************************************/
void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("POPFD\n");
} else {
DECODE_PRINTF("POPF\n");
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
M.x86.R_EFLG = pop_long();
} else {
M.x86.R_FLG = pop_word();
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x9e
****************************************************************************/
void x86emuOp_sahf(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("SAHF\n");
TRACE_AND_STEP();
/* clear the lower bits of the flag register */
M.x86.R_FLG &= 0xffffff00;
/* or in the AH register into the flags register */
M.x86.R_FLG |= M.x86.R_AH;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x9f
****************************************************************************/
void x86emuOp_lahf(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("LAHF\n");
TRACE_AND_STEP();
M.x86.R_AH = (u8)(M.x86.R_FLG & 0xff);
/*undocumented TC++ behavior??? Nope. It's documented, but
you have too look real hard to notice it. */
M.x86.R_AH |= 0x2;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa0
****************************************************************************/
void x86emuOp_mov_AL_M_IMM(u8 X86EMU_UNUSED(op1))
{
u16 offset;
START_OF_INSTR();
DECODE_PRINTF("MOV\tAL,");
offset = fetch_word_imm();
DECODE_PRINTF2("[%04x]\n", offset);
TRACE_AND_STEP();
M.x86.R_AL = fetch_data_byte(offset);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa1
****************************************************************************/
void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1))
{
u16 offset;
START_OF_INSTR();
offset = fetch_word_imm();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset);
} else {
DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset);
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
M.x86.R_EAX = fetch_data_long(offset);
} else {
M.x86.R_AX = fetch_data_word(offset);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa2
****************************************************************************/
void x86emuOp_mov_M_AL_IMM(u8 X86EMU_UNUSED(op1))
{
u16 offset;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
offset = fetch_word_imm();
DECODE_PRINTF2("[%04x],AL\n", offset);
TRACE_AND_STEP();
store_data_byte(offset, M.x86.R_AL);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa3
****************************************************************************/
void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1))
{
u16 offset;
START_OF_INSTR();
offset = fetch_word_imm();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset);
} else {
DECODE_PRINTF2("MOV\t[%04x],AX\n", offset);
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
store_data_long(offset, M.x86.R_EAX);
} else {
store_data_word(offset, M.x86.R_AX);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa4
****************************************************************************/
void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1))
{
u8 val;
u32 count;
int inc;
START_OF_INSTR();
DECODE_PRINTF("MOVS\tBYTE\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -1;
else
inc = 1;
TRACE_AND_STEP();
count = 1;
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* dont care whether REPE or REPNE */
/* move them until CX is ZERO. */
count = M.x86.R_CX;
M.x86.R_CX = 0;
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
}
while (count--) {
val = fetch_data_byte(M.x86.R_SI);
store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val);
M.x86.R_SI += inc;
M.x86.R_DI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa5
****************************************************************************/
void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1))
{
u32 val;
int inc;
u32 count;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("MOVS\tDWORD\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -4;
else
inc = 4;
} else {
DECODE_PRINTF("MOVS\tWORD\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -2;
else
inc = 2;
}
TRACE_AND_STEP();
count = 1;
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* dont care whether REPE or REPNE */
/* move them until CX is ZERO. */
count = M.x86.R_CX;
M.x86.R_CX = 0;
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
}
while (count--) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
val = fetch_data_long(M.x86.R_SI);
store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val);
} else {
val = fetch_data_word(M.x86.R_SI);
store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val);
}
M.x86.R_SI += inc;
M.x86.R_DI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa6
****************************************************************************/
void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1))
{
s8 val1, val2;
int inc;
START_OF_INSTR();
DECODE_PRINTF("CMPS\tBYTE\n");
TRACE_AND_STEP();
if (ACCESS_FLAG(F_DF)) /* down */
inc = -1;
else
inc = 1;
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* REPE */
/* move them until CX is ZERO. */
while (M.x86.R_CX != 0) {
val1 = fetch_data_byte(M.x86.R_SI);
val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
cmp_byte(val1, val2);
M.x86.R_CX -= 1;
M.x86.R_SI += inc;
M.x86.R_DI += inc;
if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break;
if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break;
}
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
} else {
val1 = fetch_data_byte(M.x86.R_SI);
val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
cmp_byte(val1, val2);
M.x86.R_SI += inc;
M.x86.R_DI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa7
****************************************************************************/
void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1))
{
u32 val1,val2;
int inc;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("CMPS\tDWORD\n");
inc = 4;
} else {
DECODE_PRINTF("CMPS\tWORD\n");
inc = 2;
}
if (ACCESS_FLAG(F_DF)) /* down */
inc = -inc;
TRACE_AND_STEP();
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* REPE */
/* move them until CX is ZERO. */
while (M.x86.R_CX != 0) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
val1 = fetch_data_long(M.x86.R_SI);
val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
cmp_long(val1, val2);
} else {
val1 = fetch_data_word(M.x86.R_SI);
val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
cmp_word((u16)val1, (u16)val2);
}
M.x86.R_CX -= 1;
M.x86.R_SI += inc;
M.x86.R_DI += inc;
if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break;
if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break;
}
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
} else {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
val1 = fetch_data_long(M.x86.R_SI);
val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
cmp_long(val1, val2);
} else {
val1 = fetch_data_word(M.x86.R_SI);
val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
cmp_word((u16)val1, (u16)val2);
}
M.x86.R_SI += inc;
M.x86.R_DI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa8
****************************************************************************/
void x86emuOp_test_AL_IMM(u8 X86EMU_UNUSED(op1))
{
int imm;
START_OF_INSTR();
DECODE_PRINTF("TEST\tAL,");
imm = fetch_byte_imm();
DECODE_PRINTF2("%04x\n", imm);
TRACE_AND_STEP();
test_byte(M.x86.R_AL, (u8)imm);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xa9
****************************************************************************/
void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1))
{
u32 srcval;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("TEST\tEAX,");
srcval = fetch_long_imm();
} else {
DECODE_PRINTF("TEST\tAX,");
srcval = fetch_word_imm();
}
DECODE_PRINTF2("%x\n", srcval);
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
test_long(M.x86.R_EAX, srcval);
} else {
test_word(M.x86.R_AX, (u16)srcval);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xaa
****************************************************************************/
void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1))
{
int inc;
START_OF_INSTR();
DECODE_PRINTF("STOS\tBYTE\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -1;
else
inc = 1;
TRACE_AND_STEP();
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* dont care whether REPE or REPNE */
/* move them until CX is ZERO. */
while (M.x86.R_CX != 0) {
store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL);
M.x86.R_CX -= 1;
M.x86.R_DI += inc;
}
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
} else {
store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL);
M.x86.R_DI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xab
****************************************************************************/
void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1))
{
int inc;
u32 count;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("STOS\tDWORD\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -4;
else
inc = 4;
} else {
DECODE_PRINTF("STOS\tWORD\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -2;
else
inc = 2;
}
TRACE_AND_STEP();
count = 1;
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* dont care whether REPE or REPNE */
/* move them until CX is ZERO. */
count = M.x86.R_CX;
M.x86.R_CX = 0;
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
}
while (count--) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX);
} else {
store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX);
}
M.x86.R_DI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xac
****************************************************************************/
void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1))
{
int inc;
START_OF_INSTR();
DECODE_PRINTF("LODS\tBYTE\n");
TRACE_AND_STEP();
if (ACCESS_FLAG(F_DF)) /* down */
inc = -1;
else
inc = 1;
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* dont care whether REPE or REPNE */
/* move them until CX is ZERO. */
while (M.x86.R_CX != 0) {
M.x86.R_AL = fetch_data_byte(M.x86.R_SI);
M.x86.R_CX -= 1;
M.x86.R_SI += inc;
}
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
} else {
M.x86.R_AL = fetch_data_byte(M.x86.R_SI);
M.x86.R_SI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xad
****************************************************************************/
void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1))
{
int inc;
u32 count;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("LODS\tDWORD\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -4;
else
inc = 4;
} else {
DECODE_PRINTF("LODS\tWORD\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -2;
else
inc = 2;
}
TRACE_AND_STEP();
count = 1;
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* dont care whether REPE or REPNE */
/* move them until CX is ZERO. */
count = M.x86.R_CX;
M.x86.R_CX = 0;
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
}
while (count--) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
M.x86.R_EAX = fetch_data_long(M.x86.R_SI);
} else {
M.x86.R_AX = fetch_data_word(M.x86.R_SI);
}
M.x86.R_SI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xae
****************************************************************************/
void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1))
{
s8 val2;
int inc;
START_OF_INSTR();
DECODE_PRINTF("SCAS\tBYTE\n");
TRACE_AND_STEP();
if (ACCESS_FLAG(F_DF)) /* down */
inc = -1;
else
inc = 1;
if (M.x86.mode & SYSMODE_PREFIX_REPE) {
/* REPE */
/* move them until CX is ZERO. */
while (M.x86.R_CX != 0) {
val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
cmp_byte(M.x86.R_AL, val2);
M.x86.R_CX -= 1;
M.x86.R_DI += inc;
if (ACCESS_FLAG(F_ZF) == 0)
break;
}
M.x86.mode &= ~SYSMODE_PREFIX_REPE;
} else if (M.x86.mode & SYSMODE_PREFIX_REPNE) {
/* REPNE */
/* move them until CX is ZERO. */
while (M.x86.R_CX != 0) {
val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
cmp_byte(M.x86.R_AL, val2);
M.x86.R_CX -= 1;
M.x86.R_DI += inc;
if (ACCESS_FLAG(F_ZF))
break; /* zero flag set means equal */
}
M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
} else {
val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI);
cmp_byte(M.x86.R_AL, val2);
M.x86.R_DI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xaf
****************************************************************************/
void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1))
{
int inc;
u32 val;
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("SCAS\tDWORD\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -4;
else
inc = 4;
} else {
DECODE_PRINTF("SCAS\tWORD\n");
if (ACCESS_FLAG(F_DF)) /* down */
inc = -2;
else
inc = 2;
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_REPE) {
/* REPE */
/* move them until CX is ZERO. */
while (M.x86.R_CX != 0) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
cmp_long(M.x86.R_EAX, val);
} else {
val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
cmp_word(M.x86.R_AX, (u16)val);
}
M.x86.R_CX -= 1;
M.x86.R_DI += inc;
if (ACCESS_FLAG(F_ZF) == 0)
break;
}
M.x86.mode &= ~SYSMODE_PREFIX_REPE;
} else if (M.x86.mode & SYSMODE_PREFIX_REPNE) {
/* REPNE */
/* move them until CX is ZERO. */
while (M.x86.R_CX != 0) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
cmp_long(M.x86.R_EAX, val);
} else {
val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
cmp_word(M.x86.R_AX, (u16)val);
}
M.x86.R_CX -= 1;
M.x86.R_DI += inc;
if (ACCESS_FLAG(F_ZF))
break; /* zero flag set means equal */
}
M.x86.mode &= ~SYSMODE_PREFIX_REPNE;
} else {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI);
cmp_long(M.x86.R_EAX, val);
} else {
val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI);
cmp_word(M.x86.R_AX, (u16)val);
}
M.x86.R_DI += inc;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xb0 - 0xb7
****************************************************************************/
void x86emuOp_mov_byte_register_IMM(u8 op1)
{
u8 imm, *ptr;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
ptr = DECODE_RM_BYTE_REGISTER(op1 & 0x7);
DECODE_PRINTF(",");
imm = fetch_byte_imm();
DECODE_PRINTF2("%x\n", imm);
TRACE_AND_STEP();
*ptr = imm;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xb8 - 0xbf
****************************************************************************/
void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1))
{
u32 srcval;
op1 &= 0x7;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *reg32;
reg32 = DECODE_RM_LONG_REGISTER(op1);
srcval = fetch_long_imm();
DECODE_PRINTF2(",%x\n", srcval);
TRACE_AND_STEP();
*reg32 = srcval;
} else {
u16 *reg16;
reg16 = DECODE_RM_WORD_REGISTER(op1);
srcval = fetch_word_imm();
DECODE_PRINTF2(",%x\n", srcval);
TRACE_AND_STEP();
*reg16 = (u16)srcval;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc0
****************************************************************************/
void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg;
uint destoffset;
u8 destval;
u8 amt;
/*
* Yet another weirdo special case instruction format. Part of
* the opcode held below in "RH". Doubly nested case would
* result, except that the decoded instruction
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ROL\t");
break;
case 1:
DECODE_PRINTF("ROR\t");
break;
case 2:
DECODE_PRINTF("RCL\t");
break;
case 3:
DECODE_PRINTF("RCR\t");
break;
case 4:
DECODE_PRINTF("SHL\t");
break;
case 5:
DECODE_PRINTF("SHR\t");
break;
case 6:
DECODE_PRINTF("SAL\t");
break;
case 7:
DECODE_PRINTF("SAR\t");
break;
}
}
#endif
/* know operation, decode the mod byte to find the addressing
mode. */
if (mod < 3) {
DECODE_PRINTF("BYTE PTR ");
destoffset = decode_rmXX_address(mod, rl);
amt = fetch_byte_imm();
DECODE_PRINTF2(",%x\n", amt);
destval = fetch_data_byte(destoffset);
TRACE_AND_STEP();
destval = (*opcD0_byte_operation[rh]) (destval, amt);
store_data_byte(destoffset, destval);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
amt = fetch_byte_imm();
DECODE_PRINTF2(",%x\n", amt);
TRACE_AND_STEP();
destval = (*opcD0_byte_operation[rh]) (*destreg, amt);
*destreg = destval;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc1
****************************************************************************/
void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
u8 amt;
/*
* Yet another weirdo special case instruction format. Part of
* the opcode held below in "RH". Doubly nested case would
* result, except that the decoded instruction
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ROL\t");
break;
case 1:
DECODE_PRINTF("ROR\t");
break;
case 2:
DECODE_PRINTF("RCL\t");
break;
case 3:
DECODE_PRINTF("RCR\t");
break;
case 4:
DECODE_PRINTF("SHL\t");
break;
case 5:
DECODE_PRINTF("SHR\t");
break;
case 6:
DECODE_PRINTF("SAL\t");
break;
case 7:
DECODE_PRINTF("SAR\t");
break;
}
}
#endif
/* know operation, decode the mod byte to find the addressing
mode. */
if (mod < 3) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
DECODE_PRINTF("DWORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
amt = fetch_byte_imm();
DECODE_PRINTF2(",%x\n", amt);
destval = fetch_data_long(destoffset);
TRACE_AND_STEP();
destval = (*opcD1_long_operation[rh]) (destval, amt);
store_data_long(destoffset, destval);
} else {
u16 destval;
DECODE_PRINTF("WORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
amt = fetch_byte_imm();
DECODE_PRINTF2(",%x\n", amt);
destval = fetch_data_word(destoffset);
TRACE_AND_STEP();
destval = (*opcD1_word_operation[rh]) (destval, amt);
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
amt = fetch_byte_imm();
DECODE_PRINTF2(",%x\n", amt);
TRACE_AND_STEP();
*destreg = (*opcD1_long_operation[rh]) (*destreg, amt);
} else {
u16 *destreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
amt = fetch_byte_imm();
DECODE_PRINTF2(",%x\n", amt);
TRACE_AND_STEP();
*destreg = (*opcD1_word_operation[rh]) (*destreg, amt);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc2
****************************************************************************/
void x86emuOp_ret_near_IMM(u8 X86EMU_UNUSED(op1))
{
u16 imm;
START_OF_INSTR();
DECODE_PRINTF("RET\t");
imm = fetch_word_imm();
DECODE_PRINTF2("%x\n", imm);
RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip);
TRACE_AND_STEP();
M.x86.R_IP = pop_word();
M.x86.R_SP += imm;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc3
****************************************************************************/
void x86emuOp_ret_near(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("RET\n");
RETURN_TRACE("RET",M.x86.saved_cs,M.x86.saved_ip);
TRACE_AND_STEP();
M.x86.R_IP = pop_word();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc4
****************************************************************************/
void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rh, rl;
u16 *dstreg;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("LES\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
dstreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*dstreg = fetch_data_word(srcoffset);
M.x86.R_ES = fetch_data_word(srcoffset + 2);
}
/* else UNDEFINED! register to register */
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc5
****************************************************************************/
void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rh, rl;
u16 *dstreg;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("LDS\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
dstreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*dstreg = fetch_data_word(srcoffset);
M.x86.R_DS = fetch_data_word(srcoffset + 2);
}
/* else UNDEFINED! */
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc6
****************************************************************************/
void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg;
uint destoffset;
u8 imm;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n");
HALT_SYS();
}
if (mod < 3) {
DECODE_PRINTF("BYTE PTR ");
destoffset = decode_rmXX_address(mod, rl);
imm = fetch_byte_imm();
DECODE_PRINTF2(",%2x\n", imm);
TRACE_AND_STEP();
store_data_byte(destoffset, imm);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
imm = fetch_byte_imm();
DECODE_PRINTF2(",%2x\n", imm);
TRACE_AND_STEP();
*destreg = imm;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc7
****************************************************************************/
void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
START_OF_INSTR();
DECODE_PRINTF("MOV\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (rh != 0) {
DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n");
HALT_SYS();
}
if (mod < 3) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 imm;
DECODE_PRINTF("DWORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
imm = fetch_long_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
store_data_long(destoffset, imm);
} else {
u16 imm;
DECODE_PRINTF("WORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
imm = fetch_word_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
store_data_word(destoffset, imm);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 imm;
destreg = DECODE_RM_LONG_REGISTER(rl);
imm = fetch_long_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
*destreg = imm;
} else {
u16 *destreg;
u16 imm;
destreg = DECODE_RM_WORD_REGISTER(rl);
imm = fetch_word_imm();
DECODE_PRINTF2(",%x\n", imm);
TRACE_AND_STEP();
*destreg = imm;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc8
****************************************************************************/
void x86emuOp_enter(u8 X86EMU_UNUSED(op1))
{
u16 local,frame_pointer;
u8 nesting;
int i;
START_OF_INSTR();
local = fetch_word_imm();
nesting = fetch_byte_imm();
DECODE_PRINTF2("ENTER %x\n", local);
DECODE_PRINTF2(",%x\n", nesting);
TRACE_AND_STEP();
push_word(M.x86.R_BP);
frame_pointer = M.x86.R_SP;
if (nesting > 0) {
for (i = 1; i < nesting; i++) {
M.x86.R_BP -= 2;
push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP));
}
push_word(frame_pointer);
}
M.x86.R_BP = frame_pointer;
M.x86.R_SP = (u16)(M.x86.R_SP - local);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xc9
****************************************************************************/
void x86emuOp_leave(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("LEAVE\n");
TRACE_AND_STEP();
M.x86.R_SP = M.x86.R_BP;
M.x86.R_BP = pop_word();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xca
****************************************************************************/
void x86emuOp_ret_far_IMM(u8 X86EMU_UNUSED(op1))
{
u16 imm;
START_OF_INSTR();
DECODE_PRINTF("RETF\t");
imm = fetch_word_imm();
DECODE_PRINTF2("%x\n", imm);
RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip);
TRACE_AND_STEP();
M.x86.R_IP = pop_word();
M.x86.R_CS = pop_word();
M.x86.R_SP += imm;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xcb
****************************************************************************/
void x86emuOp_ret_far(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("RETF\n");
RETURN_TRACE("RETF",M.x86.saved_cs,M.x86.saved_ip);
TRACE_AND_STEP();
M.x86.R_IP = pop_word();
M.x86.R_CS = pop_word();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xcc
****************************************************************************/
void x86emuOp_int3(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("INT 3\n");
(void)mem_access_word(3 * 4 + 2);
/* access the segment register */
TRACE_AND_STEP();
if (_X86EMU_intrTab[3]) {
(*_X86EMU_intrTab[3])(3);
} else {
push_word((u16)M.x86.R_FLG);
CLEAR_FLAG(F_IF);
CLEAR_FLAG(F_TF);
push_word(M.x86.R_CS);
M.x86.R_CS = mem_access_word(3 * 4 + 2);
push_word(M.x86.R_IP);
M.x86.R_IP = mem_access_word(3 * 4);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xcd
****************************************************************************/
void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1))
{
u8 intnum;
START_OF_INSTR();
DECODE_PRINTF("INT\t");
intnum = fetch_byte_imm();
DECODE_PRINTF2("%x\n", intnum);
(void)mem_access_word(intnum * 4 + 2);
TRACE_AND_STEP();
if (_X86EMU_intrTab[intnum]) {
(*_X86EMU_intrTab[intnum])(intnum);
} else {
push_word((u16)M.x86.R_FLG);
CLEAR_FLAG(F_IF);
CLEAR_FLAG(F_TF);
push_word(M.x86.R_CS);
M.x86.R_CS = mem_access_word(intnum * 4 + 2);
push_word(M.x86.R_IP);
M.x86.R_IP = mem_access_word(intnum * 4);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xce
****************************************************************************/
void x86emuOp_into(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("INTO\n");
TRACE_AND_STEP();
if (ACCESS_FLAG(F_OF)) {
(void)mem_access_word(4 * 4 + 2);
if (_X86EMU_intrTab[4]) {
(*_X86EMU_intrTab[4])(4);
} else {
push_word((u16)M.x86.R_FLG);
CLEAR_FLAG(F_IF);
CLEAR_FLAG(F_TF);
push_word(M.x86.R_CS);
M.x86.R_CS = mem_access_word(4 * 4 + 2);
push_word(M.x86.R_IP);
M.x86.R_IP = mem_access_word(4 * 4);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xcf
****************************************************************************/
void x86emuOp_iret(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("IRET\n");
TRACE_AND_STEP();
M.x86.R_IP = pop_word();
M.x86.R_CS = pop_word();
M.x86.R_FLG = pop_word();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xd0
****************************************************************************/
void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg;
uint destoffset;
u8 destval;
/*
* Yet another weirdo special case instruction format. Part of
* the opcode held below in "RH". Doubly nested case would
* result, except that the decoded instruction
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ROL\t");
break;
case 1:
DECODE_PRINTF("ROR\t");
break;
case 2:
DECODE_PRINTF("RCL\t");
break;
case 3:
DECODE_PRINTF("RCR\t");
break;
case 4:
DECODE_PRINTF("SHL\t");
break;
case 5:
DECODE_PRINTF("SHR\t");
break;
case 6:
DECODE_PRINTF("SAL\t");
break;
case 7:
DECODE_PRINTF("SAR\t");
break;
}
}
#endif
/* know operation, decode the mod byte to find the addressing
mode. */
if (mod < 3) {
DECODE_PRINTF("BYTE PTR ");
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",1\n");
destval = fetch_data_byte(destoffset);
TRACE_AND_STEP();
destval = (*opcD0_byte_operation[rh]) (destval, 1);
store_data_byte(destoffset, destval);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF(",1\n");
TRACE_AND_STEP();
destval = (*opcD0_byte_operation[rh]) (*destreg, 1);
*destreg = destval;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xd1
****************************************************************************/
void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
/*
* Yet another weirdo special case instruction format. Part of
* the opcode held below in "RH". Doubly nested case would
* result, except that the decoded instruction
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ROL\t");
break;
case 1:
DECODE_PRINTF("ROR\t");
break;
case 2:
DECODE_PRINTF("RCL\t");
break;
case 3:
DECODE_PRINTF("RCR\t");
break;
case 4:
DECODE_PRINTF("SHL\t");
break;
case 5:
DECODE_PRINTF("SHR\t");
break;
case 6:
DECODE_PRINTF("SAL\t");
break;
case 7:
DECODE_PRINTF("SAR\t");
break;
}
}
#endif
/* know operation, decode the mod byte to find the addressing
mode. */
if (mod < 3) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
DECODE_PRINTF("DWORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",1\n");
destval = fetch_data_long(destoffset);
TRACE_AND_STEP();
destval = (*opcD1_long_operation[rh]) (destval, 1);
store_data_long(destoffset, destval);
} else {
u16 destval;
DECODE_PRINTF("WORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",1\n");
destval = fetch_data_word(destoffset);
TRACE_AND_STEP();
destval = (*opcD1_word_operation[rh]) (destval, 1);
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
u32 *destreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",1\n");
TRACE_AND_STEP();
destval = (*opcD1_long_operation[rh]) (*destreg, 1);
*destreg = destval;
} else {
u16 destval;
u16 *destreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",1\n");
TRACE_AND_STEP();
destval = (*opcD1_word_operation[rh]) (*destreg, 1);
*destreg = destval;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xd2
****************************************************************************/
void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg;
uint destoffset;
u8 destval;
u8 amt;
/*
* Yet another weirdo special case instruction format. Part of
* the opcode held below in "RH". Doubly nested case would
* result, except that the decoded instruction
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ROL\t");
break;
case 1:
DECODE_PRINTF("ROR\t");
break;
case 2:
DECODE_PRINTF("RCL\t");
break;
case 3:
DECODE_PRINTF("RCR\t");
break;
case 4:
DECODE_PRINTF("SHL\t");
break;
case 5:
DECODE_PRINTF("SHR\t");
break;
case 6:
DECODE_PRINTF("SAL\t");
break;
case 7:
DECODE_PRINTF("SAR\t");
break;
}
}
#endif
/* know operation, decode the mod byte to find the addressing
mode. */
amt = M.x86.R_CL;
if (mod < 3) {
DECODE_PRINTF("BYTE PTR ");
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",CL\n");
destval = fetch_data_byte(destoffset);
TRACE_AND_STEP();
destval = (*opcD0_byte_operation[rh]) (destval, amt);
store_data_byte(destoffset, destval);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
destval = (*opcD0_byte_operation[rh]) (*destreg, amt);
*destreg = destval;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xd3
****************************************************************************/
void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
u8 amt;
/*
* Yet another weirdo special case instruction format. Part of
* the opcode held below in "RH". Doubly nested case would
* result, except that the decoded instruction
*/
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("ROL\t");
break;
case 1:
DECODE_PRINTF("ROR\t");
break;
case 2:
DECODE_PRINTF("RCL\t");
break;
case 3:
DECODE_PRINTF("RCR\t");
break;
case 4:
DECODE_PRINTF("SHL\t");
break;
case 5:
DECODE_PRINTF("SHR\t");
break;
case 6:
DECODE_PRINTF("SAL\t");
break;
case 7:
DECODE_PRINTF("SAR\t");
break;
}
}
#endif
/* know operation, decode the mod byte to find the addressing
mode. */
amt = M.x86.R_CL;
if (mod < 3) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
DECODE_PRINTF("DWORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",CL\n");
destval = fetch_data_long(destoffset);
TRACE_AND_STEP();
destval = (*opcD1_long_operation[rh]) (destval, amt);
store_data_long(destoffset, destval);
} else {
u16 destval;
DECODE_PRINTF("WORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",CL\n");
destval = fetch_data_word(destoffset);
TRACE_AND_STEP();
destval = (*opcD1_word_operation[rh]) (destval, amt);
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
*destreg = (*opcD1_long_operation[rh]) (*destreg, amt);
} else {
u16 *destreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
*destreg = (*opcD1_word_operation[rh]) (*destreg, amt);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xd4
****************************************************************************/
void x86emuOp_aam(u8 X86EMU_UNUSED(op1))
{
u8 a;
START_OF_INSTR();
DECODE_PRINTF("AAM\n");
a = fetch_byte_imm(); /* this is a stupid encoding. */
if (a != 10) {
DECODE_PRINTF("ERROR DECODING AAM\n");
TRACE_REGS();
HALT_SYS();
}
TRACE_AND_STEP();
/* note the type change here --- returning AL and AH in AX. */
M.x86.R_AX = aam_word(M.x86.R_AL);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xd5
****************************************************************************/
void x86emuOp_aad(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("AAD\n");
(void)fetch_byte_imm();
TRACE_AND_STEP();
M.x86.R_AX = aad_word(M.x86.R_AX);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/* opcode 0xd6 ILLEGAL OPCODE */
/****************************************************************************
REMARKS:
Handles opcode 0xd7
****************************************************************************/
void x86emuOp_xlat(u8 X86EMU_UNUSED(op1))
{
u16 addr;
START_OF_INSTR();
DECODE_PRINTF("XLAT\n");
TRACE_AND_STEP();
addr = (u16)(M.x86.R_BX + (u8)M.x86.R_AL);
M.x86.R_AL = fetch_data_byte(addr);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/* instuctions D8 .. DF are in i87_ops.c */
/****************************************************************************
REMARKS:
Handles opcode 0xe0
****************************************************************************/
void x86emuOp_loopne(u8 X86EMU_UNUSED(op1))
{
s16 ip;
START_OF_INSTR();
DECODE_PRINTF("LOOPNE\t");
ip = (s8) fetch_byte_imm();
ip += (s16) M.x86.R_IP;
DECODE_PRINTF2("%04x\n", ip);
TRACE_AND_STEP();
M.x86.R_CX -= 1;
if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */
M.x86.R_IP = ip;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xe1
****************************************************************************/
void x86emuOp_loope(u8 X86EMU_UNUSED(op1))
{
s16 ip;
START_OF_INSTR();
DECODE_PRINTF("LOOPE\t");
ip = (s8) fetch_byte_imm();
ip += (s16) M.x86.R_IP;
DECODE_PRINTF2("%04x\n", ip);
TRACE_AND_STEP();
M.x86.R_CX -= 1;
if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */
M.x86.R_IP = ip;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xe2
****************************************************************************/
void x86emuOp_loop(u8 X86EMU_UNUSED(op1))
{
s16 ip;
START_OF_INSTR();
DECODE_PRINTF("LOOP\t");
ip = (s8) fetch_byte_imm();
ip += (s16) M.x86.R_IP;
DECODE_PRINTF2("%04x\n", ip);
TRACE_AND_STEP();
M.x86.R_CX -= 1;
if (M.x86.R_CX != 0)
M.x86.R_IP = ip;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xe3
****************************************************************************/
void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1))
{
u16 target;
s8 offset;
/* jump to byte offset if overflow flag is set */
START_OF_INSTR();
DECODE_PRINTF("JCXZ\t");
offset = (s8)fetch_byte_imm();
target = (u16)(M.x86.R_IP + offset);
DECODE_PRINTF2("%x\n", target);
TRACE_AND_STEP();
if (M.x86.R_CX == 0)
M.x86.R_IP = target;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xe4
****************************************************************************/
void x86emuOp_in_byte_AL_IMM(u8 X86EMU_UNUSED(op1))
{
u8 port;
START_OF_INSTR();
DECODE_PRINTF("IN\t");
port = (u8) fetch_byte_imm();
DECODE_PRINTF2("%x,AL\n", port);
TRACE_AND_STEP();
M.x86.R_AL = (*sys_inb)(port);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xe5
****************************************************************************/
void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1))
{
u8 port;
START_OF_INSTR();
DECODE_PRINTF("IN\t");
port = (u8) fetch_byte_imm();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF2("EAX,%x\n", port);
} else {
DECODE_PRINTF2("AX,%x\n", port);
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
M.x86.R_EAX = (*sys_inl)(port);
} else {
M.x86.R_AX = (*sys_inw)(port);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xe6
****************************************************************************/
void x86emuOp_out_byte_IMM_AL(u8 X86EMU_UNUSED(op1))
{
u8 port;
START_OF_INSTR();
DECODE_PRINTF("OUT\t");
port = (u8) fetch_byte_imm();
DECODE_PRINTF2("%x,AL\n", port);
TRACE_AND_STEP();
(*sys_outb)(port, M.x86.R_AL);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xe7
****************************************************************************/
void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1))
{
u8 port;
START_OF_INSTR();
DECODE_PRINTF("OUT\t");
port = (u8) fetch_byte_imm();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF2("%x,EAX\n", port);
} else {
DECODE_PRINTF2("%x,AX\n", port);
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
(*sys_outl)(port, M.x86.R_EAX);
} else {
(*sys_outw)(port, M.x86.R_AX);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xe8
****************************************************************************/
void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1))
{
s16 ip;
START_OF_INSTR();
DECODE_PRINTF("CALL\t");
ip = (s16) fetch_word_imm();
ip += (s16) M.x86.R_IP; /* CHECK SIGN */
DECODE_PRINTF2("%04x\n", ip);
CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, "");
TRACE_AND_STEP();
push_word(M.x86.R_IP);
M.x86.R_IP = ip;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xe9
****************************************************************************/
void x86emuOp_jump_near_IMM(u8 X86EMU_UNUSED(op1))
{
int ip;
START_OF_INSTR();
DECODE_PRINTF("JMP\t");
ip = (s16)fetch_word_imm();
ip += (s16)M.x86.R_IP;
DECODE_PRINTF2("%04x\n", ip);
TRACE_AND_STEP();
M.x86.R_IP = (u16)ip;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xea
****************************************************************************/
void x86emuOp_jump_far_IMM(u8 X86EMU_UNUSED(op1))
{
u16 cs, ip;
START_OF_INSTR();
DECODE_PRINTF("JMP\tFAR ");
ip = fetch_word_imm();
cs = fetch_word_imm();
DECODE_PRINTF2("%04x:", cs);
DECODE_PRINTF2("%04x\n", ip);
TRACE_AND_STEP();
M.x86.R_IP = ip;
M.x86.R_CS = cs;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xeb
****************************************************************************/
void x86emuOp_jump_byte_IMM(u8 X86EMU_UNUSED(op1))
{
u16 target;
s8 offset;
START_OF_INSTR();
DECODE_PRINTF("JMP\t");
offset = (s8)fetch_byte_imm();
target = (u16)(M.x86.R_IP + offset);
DECODE_PRINTF2("%x\n", target);
TRACE_AND_STEP();
M.x86.R_IP = target;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xec
****************************************************************************/
void x86emuOp_in_byte_AL_DX(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("IN\tAL,DX\n");
TRACE_AND_STEP();
M.x86.R_AL = (*sys_inb)(M.x86.R_DX);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xed
****************************************************************************/
void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("IN\tEAX,DX\n");
} else {
DECODE_PRINTF("IN\tAX,DX\n");
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
M.x86.R_EAX = (*sys_inl)(M.x86.R_DX);
} else {
M.x86.R_AX = (*sys_inw)(M.x86.R_DX);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xee
****************************************************************************/
void x86emuOp_out_byte_DX_AL(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("OUT\tDX,AL\n");
TRACE_AND_STEP();
(*sys_outb)(M.x86.R_DX, M.x86.R_AL);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xef
****************************************************************************/
void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("OUT\tDX,EAX\n");
} else {
DECODE_PRINTF("OUT\tDX,AX\n");
}
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
(*sys_outl)(M.x86.R_DX, M.x86.R_EAX);
} else {
(*sys_outw)(M.x86.R_DX, M.x86.R_AX);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xf0
****************************************************************************/
void x86emuOp_lock(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("LOCK:\n");
TRACE_AND_STEP();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/*opcode 0xf1 ILLEGAL OPERATION */
/****************************************************************************
REMARKS:
Handles opcode 0xf2
****************************************************************************/
void x86emuOp_repne(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("REPNE\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_PREFIX_REPNE;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xf3
****************************************************************************/
void x86emuOp_repe(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("REPE\n");
TRACE_AND_STEP();
M.x86.mode |= SYSMODE_PREFIX_REPE;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xf4
****************************************************************************/
void x86emuOp_halt(u8 X86EMU_UNUSED(op1))
{
START_OF_INSTR();
DECODE_PRINTF("HALT\n");
TRACE_AND_STEP();
HALT_SYS();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xf5
****************************************************************************/
void x86emuOp_cmc(u8 X86EMU_UNUSED(op1))
{
/* complement the carry flag. */
START_OF_INSTR();
DECODE_PRINTF("CMC\n");
TRACE_AND_STEP();
TOGGLE_FLAG(F_CF);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xf6
****************************************************************************/
void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
u8 *destreg;
uint destoffset;
u8 destval, srcval;
/* long, drawn out code follows. Double switch for a total
of 32 cases. */
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
DECODE_PRINTF(opF6_names[rh]);
if (mod < 3) {
DECODE_PRINTF("BYTE PTR ");
destoffset = decode_rmXX_address(mod, rl);
destval = fetch_data_byte(destoffset);
switch (rh) {
case 0: /* test byte imm */
DECODE_PRINTF(",");
srcval = fetch_byte_imm();
DECODE_PRINTF2("%02x\n", srcval);
TRACE_AND_STEP();
test_byte(destval, srcval);
break;
case 1:
DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = not_byte(destval);
store_data_byte(destoffset, destval);
break;
case 3:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = neg_byte(destval);
store_data_byte(destoffset, destval);
break;
case 4:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
mul_byte(destval);
break;
case 5:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
imul_byte(destval);
break;
case 6:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
div_byte(destval);
break;
default:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
idiv_byte(destval);
break;
}
} else { /* mod=11 */
destreg = DECODE_RM_BYTE_REGISTER(rl);
switch (rh) {
case 0: /* test byte imm */
DECODE_PRINTF(",");
srcval = fetch_byte_imm();
DECODE_PRINTF2("%02x\n", srcval);
TRACE_AND_STEP();
test_byte(*destreg, srcval);
break;
case 1:
DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = not_byte(*destreg);
break;
case 3:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = neg_byte(*destreg);
break;
case 4:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
mul_byte(*destreg); /*!!! */
break;
case 5:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
imul_byte(*destreg);
break;
case 6:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
div_byte(*destreg);
break;
default:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
idiv_byte(*destreg);
break;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xf7
****************************************************************************/
void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1))
{
int mod, rl, rh;
uint destoffset;
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
DECODE_PRINTF(opF6_names[rh]);
if (mod < 3) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval, srcval;
DECODE_PRINTF("DWORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
destval = fetch_data_long(destoffset);
switch (rh) {
case 0:
DECODE_PRINTF(",");
srcval = fetch_long_imm();
DECODE_PRINTF2("%x\n", srcval);
TRACE_AND_STEP();
test_long(destval, srcval);
break;
case 1:
DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
HALT_SYS();
break;
case 2:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = not_long(destval);
store_data_long(destoffset, destval);
break;
case 3:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = neg_long(destval);
store_data_long(destoffset, destval);
break;
case 4:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
mul_long(destval);
break;
case 5:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
imul_long(destval);
break;
case 6:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
div_long(destval);
break;
case 7:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
idiv_long(destval);
break;
}
} else {
u16 destval, srcval;
DECODE_PRINTF("WORD PTR ");
destoffset = decode_rmXX_address(mod, rl);
destval = fetch_data_word(destoffset);
switch (rh) {
case 0: /* test word imm */
DECODE_PRINTF(",");
srcval = fetch_word_imm();
DECODE_PRINTF2("%x\n", srcval);
TRACE_AND_STEP();
test_word(destval, srcval);
break;
case 1:
DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n");
HALT_SYS();
break;
case 2:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = not_word(destval);
store_data_word(destoffset, destval);
break;
case 3:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
destval = neg_word(destval);
store_data_word(destoffset, destval);
break;
case 4:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
mul_word(destval);
break;
case 5:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
imul_word(destval);
break;
case 6:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
div_word(destval);
break;
case 7:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
idiv_word(destval);
break;
}
}
} else { /* mod=11 */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 srcval;
destreg = DECODE_RM_LONG_REGISTER(rl);
switch (rh) {
case 0: /* test word imm */
DECODE_PRINTF(",");
srcval = fetch_long_imm();
DECODE_PRINTF2("%x\n", srcval);
TRACE_AND_STEP();
test_long(*destreg, srcval);
break;
case 1:
DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = not_long(*destreg);
break;
case 3:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = neg_long(*destreg);
break;
case 4:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
mul_long(*destreg); /*!!! */
break;
case 5:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
imul_long(*destreg);
break;
case 6:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
div_long(*destreg);
break;
case 7:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
idiv_long(*destreg);
break;
}
} else {
u16 *destreg;
u16 srcval;
destreg = DECODE_RM_WORD_REGISTER(rl);
switch (rh) {
case 0: /* test word imm */
DECODE_PRINTF(",");
srcval = fetch_word_imm();
DECODE_PRINTF2("%x\n", srcval);
TRACE_AND_STEP();
test_word(*destreg, srcval);
break;
case 1:
DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n");
HALT_SYS();
break;
case 2:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = not_word(*destreg);
break;
case 3:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = neg_word(*destreg);
break;
case 4:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
mul_word(*destreg); /*!!! */
break;
case 5:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
imul_word(*destreg);
break;
case 6:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
div_word(*destreg);
break;
case 7:
DECODE_PRINTF("\n");
TRACE_AND_STEP();
idiv_word(*destreg);
break;
}
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xf8
****************************************************************************/
void x86emuOp_clc(u8 X86EMU_UNUSED(op1))
{
/* clear the carry flag. */
START_OF_INSTR();
DECODE_PRINTF("CLC\n");
TRACE_AND_STEP();
CLEAR_FLAG(F_CF);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xf9
****************************************************************************/
void x86emuOp_stc(u8 X86EMU_UNUSED(op1))
{
/* set the carry flag. */
START_OF_INSTR();
DECODE_PRINTF("STC\n");
TRACE_AND_STEP();
SET_FLAG(F_CF);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xfa
****************************************************************************/
void x86emuOp_cli(u8 X86EMU_UNUSED(op1))
{
/* clear interrupts. */
START_OF_INSTR();
DECODE_PRINTF("CLI\n");
TRACE_AND_STEP();
CLEAR_FLAG(F_IF);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xfb
****************************************************************************/
void x86emuOp_sti(u8 X86EMU_UNUSED(op1))
{
/* enable interrupts. */
START_OF_INSTR();
DECODE_PRINTF("STI\n");
TRACE_AND_STEP();
SET_FLAG(F_IF);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xfc
****************************************************************************/
void x86emuOp_cld(u8 X86EMU_UNUSED(op1))
{
/* clear interrupts. */
START_OF_INSTR();
DECODE_PRINTF("CLD\n");
TRACE_AND_STEP();
CLEAR_FLAG(F_DF);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xfd
****************************************************************************/
void x86emuOp_std(u8 X86EMU_UNUSED(op1))
{
/* clear interrupts. */
START_OF_INSTR();
DECODE_PRINTF("STD\n");
TRACE_AND_STEP();
SET_FLAG(F_DF);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xfe
****************************************************************************/
void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1))
{
int mod, rh, rl;
u8 destval;
uint destoffset;
u8 *destreg;
/* Yet another special case instruction. */
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
DECODE_PRINTF("INC\t");
break;
case 1:
DECODE_PRINTF("DEC\t");
break;
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod);
HALT_SYS();
break;
}
}
#endif
if (mod < 3) {
DECODE_PRINTF("BYTE PTR ");
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF("\n");
destval = fetch_data_byte(destoffset);
TRACE_AND_STEP();
if (rh == 0)
destval = inc_byte(destval);
else
destval = dec_byte(destval);
store_data_byte(destoffset, destval);
} else {
destreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
if (rh == 0)
*destreg = inc_byte(*destreg);
else
*destreg = dec_byte(*destreg);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0xff
****************************************************************************/
void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1))
{
int mod, rh, rl;
uint destoffset = 0;
u16 *destreg;
u16 destval,destval2;
/* Yet another special case instruction. */
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
#ifdef DEBUG
if (DEBUG_DECODE()) {
/* XXX DECODE_PRINTF may be changed to something more
general, so that it is important to leave the strings
in the same format, even though the result is that the
above test is done twice. */
switch (rh) {
case 0:
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("INC\tDWORD PTR ");
} else {
DECODE_PRINTF("INC\tWORD PTR ");
}
break;
case 1:
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
DECODE_PRINTF("DEC\tDWORD PTR ");
} else {
DECODE_PRINTF("DEC\tWORD PTR ");
}
break;
case 2:
DECODE_PRINTF("CALL\t ");
break;
case 3:
DECODE_PRINTF("CALL\tFAR ");
break;
case 4:
DECODE_PRINTF("JMP\t");
break;
case 5:
DECODE_PRINTF("JMP\tFAR ");
break;
case 6:
DECODE_PRINTF("PUSH\t");
break;
case 7:
DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t");
HALT_SYS();
break;
}
}
#endif
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF("\n");
switch (rh) {
case 0: /* inc word ptr ... */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
destval = fetch_data_long(destoffset);
TRACE_AND_STEP();
destval = inc_long(destval);
store_data_long(destoffset, destval);
} else {
u16 destval;
destval = fetch_data_word(destoffset);
TRACE_AND_STEP();
destval = inc_word(destval);
store_data_word(destoffset, destval);
}
break;
case 1: /* dec word ptr ... */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
destval = fetch_data_long(destoffset);
TRACE_AND_STEP();
destval = dec_long(destval);
store_data_long(destoffset, destval);
} else {
u16 destval;
destval = fetch_data_word(destoffset);
TRACE_AND_STEP();
destval = dec_word(destval);
store_data_word(destoffset, destval);
}
break;
case 2: /* call word ptr ... */
destval = fetch_data_word(destoffset);
TRACE_AND_STEP();
push_word(M.x86.R_IP);
M.x86.R_IP = destval;
break;
case 3: /* call far ptr ... */
destval = fetch_data_word(destoffset);
destval2 = fetch_data_word(destoffset + 2);
TRACE_AND_STEP();
push_word(M.x86.R_CS);
M.x86.R_CS = destval2;
push_word(M.x86.R_IP);
M.x86.R_IP = destval;
break;
case 4: /* jmp word ptr ... */
destval = fetch_data_word(destoffset);
TRACE_AND_STEP();
M.x86.R_IP = destval;
break;
case 5: /* jmp far ptr ... */
destval = fetch_data_word(destoffset);
destval2 = fetch_data_word(destoffset + 2);
TRACE_AND_STEP();
M.x86.R_IP = destval;
M.x86.R_CS = destval2;
break;
case 6: /* push word ptr ... */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
destval = fetch_data_long(destoffset);
TRACE_AND_STEP();
push_long(destval);
} else {
u16 destval;
destval = fetch_data_word(destoffset);
TRACE_AND_STEP();
push_word(destval);
}
break;
}
} else {
switch (rh) {
case 0:
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = inc_long(*destreg);
} else {
u16 *destreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = inc_word(*destreg);
}
break;
case 1:
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = dec_long(*destreg);
} else {
u16 *destreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = dec_word(*destreg);
}
break;
case 2: /* call word ptr ... */
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
push_word(M.x86.R_IP);
M.x86.R_IP = *destreg;
break;
case 3: /* jmp far ptr ... */
DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
TRACE_AND_STEP();
HALT_SYS();
break;
case 4: /* jmp ... */
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
M.x86.R_IP = (u16) (*destreg);
break;
case 5: /* jmp far ptr ... */
DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n");
TRACE_AND_STEP();
HALT_SYS();
break;
case 6:
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
push_long(*destreg);
} else {
u16 *destreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
push_word(*destreg);
}
break;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/***************************************************************************
* Single byte operation code table:
**************************************************************************/
void (*x86emu_optab[256])(u8) =
{
/* 0x00 */ x86emuOp_genop_byte_RM_R,
/* 0x01 */ x86emuOp_genop_word_RM_R,
/* 0x02 */ x86emuOp_genop_byte_R_RM,
/* 0x03 */ x86emuOp_genop_word_R_RM,
/* 0x04 */ x86emuOp_genop_byte_AL_IMM,
/* 0x05 */ x86emuOp_genop_word_AX_IMM,
/* 0x06 */ x86emuOp_push_ES,
/* 0x07 */ x86emuOp_pop_ES,
/* 0x08 */ x86emuOp_genop_byte_RM_R,
/* 0x09 */ x86emuOp_genop_word_RM_R,
/* 0x0a */ x86emuOp_genop_byte_R_RM,
/* 0x0b */ x86emuOp_genop_word_R_RM,
/* 0x0c */ x86emuOp_genop_byte_AL_IMM,
/* 0x0d */ x86emuOp_genop_word_AX_IMM,
/* 0x0e */ x86emuOp_push_CS,
/* 0x0f */ x86emuOp_two_byte,
/* 0x10 */ x86emuOp_genop_byte_RM_R,
/* 0x11 */ x86emuOp_genop_word_RM_R,
/* 0x12 */ x86emuOp_genop_byte_R_RM,
/* 0x13 */ x86emuOp_genop_word_R_RM,
/* 0x14 */ x86emuOp_genop_byte_AL_IMM,
/* 0x15 */ x86emuOp_genop_word_AX_IMM,
/* 0x16 */ x86emuOp_push_SS,
/* 0x17 */ x86emuOp_pop_SS,
/* 0x18 */ x86emuOp_genop_byte_RM_R,
/* 0x19 */ x86emuOp_genop_word_RM_R,
/* 0x1a */ x86emuOp_genop_byte_R_RM,
/* 0x1b */ x86emuOp_genop_word_R_RM,
/* 0x1c */ x86emuOp_genop_byte_AL_IMM,
/* 0x1d */ x86emuOp_genop_word_AX_IMM,
/* 0x1e */ x86emuOp_push_DS,
/* 0x1f */ x86emuOp_pop_DS,
/* 0x20 */ x86emuOp_genop_byte_RM_R,
/* 0x21 */ x86emuOp_genop_word_RM_R,
/* 0x22 */ x86emuOp_genop_byte_R_RM,
/* 0x23 */ x86emuOp_genop_word_R_RM,
/* 0x24 */ x86emuOp_genop_byte_AL_IMM,
/* 0x25 */ x86emuOp_genop_word_AX_IMM,
/* 0x26 */ x86emuOp_segovr_ES,
/* 0x27 */ x86emuOp_daa,
/* 0x28 */ x86emuOp_genop_byte_RM_R,
/* 0x29 */ x86emuOp_genop_word_RM_R,
/* 0x2a */ x86emuOp_genop_byte_R_RM,
/* 0x2b */ x86emuOp_genop_word_R_RM,
/* 0x2c */ x86emuOp_genop_byte_AL_IMM,
/* 0x2d */ x86emuOp_genop_word_AX_IMM,
/* 0x2e */ x86emuOp_segovr_CS,
/* 0x2f */ x86emuOp_das,
/* 0x30 */ x86emuOp_genop_byte_RM_R,
/* 0x31 */ x86emuOp_genop_word_RM_R,
/* 0x32 */ x86emuOp_genop_byte_R_RM,
/* 0x33 */ x86emuOp_genop_word_R_RM,
/* 0x34 */ x86emuOp_genop_byte_AL_IMM,
/* 0x35 */ x86emuOp_genop_word_AX_IMM,
/* 0x36 */ x86emuOp_segovr_SS,
/* 0x37 */ x86emuOp_aaa,
/* 0x38 */ x86emuOp_genop_byte_RM_R,
/* 0x39 */ x86emuOp_genop_word_RM_R,
/* 0x3a */ x86emuOp_genop_byte_R_RM,
/* 0x3b */ x86emuOp_genop_word_R_RM,
/* 0x3c */ x86emuOp_genop_byte_AL_IMM,
/* 0x3d */ x86emuOp_genop_word_AX_IMM,
/* 0x3e */ x86emuOp_segovr_DS,
/* 0x3f */ x86emuOp_aas,
/* 0x40 */ x86emuOp_inc_register,
/* 0x41 */ x86emuOp_inc_register,
/* 0x42 */ x86emuOp_inc_register,
/* 0x43 */ x86emuOp_inc_register,
/* 0x44 */ x86emuOp_inc_register,
/* 0x45 */ x86emuOp_inc_register,
/* 0x46 */ x86emuOp_inc_register,
/* 0x47 */ x86emuOp_inc_register,
/* 0x48 */ x86emuOp_dec_register,
/* 0x49 */ x86emuOp_dec_register,
/* 0x4a */ x86emuOp_dec_register,
/* 0x4b */ x86emuOp_dec_register,
/* 0x4c */ x86emuOp_dec_register,
/* 0x4d */ x86emuOp_dec_register,
/* 0x4e */ x86emuOp_dec_register,
/* 0x4f */ x86emuOp_dec_register,
/* 0x50 */ x86emuOp_push_register,
/* 0x51 */ x86emuOp_push_register,
/* 0x52 */ x86emuOp_push_register,
/* 0x53 */ x86emuOp_push_register,
/* 0x54 */ x86emuOp_push_register,
/* 0x55 */ x86emuOp_push_register,
/* 0x56 */ x86emuOp_push_register,
/* 0x57 */ x86emuOp_push_register,
/* 0x58 */ x86emuOp_pop_register,
/* 0x59 */ x86emuOp_pop_register,
/* 0x5a */ x86emuOp_pop_register,
/* 0x5b */ x86emuOp_pop_register,
/* 0x5c */ x86emuOp_pop_register,
/* 0x5d */ x86emuOp_pop_register,
/* 0x5e */ x86emuOp_pop_register,
/* 0x5f */ x86emuOp_pop_register,
/* 0x60 */ x86emuOp_push_all,
/* 0x61 */ x86emuOp_pop_all,
/* 0x62 */ x86emuOp_illegal_op, /* bound */
/* 0x63 */ x86emuOp_illegal_op, /* arpl */
/* 0x64 */ x86emuOp_segovr_FS,
/* 0x65 */ x86emuOp_segovr_GS,
/* 0x66 */ x86emuOp_prefix_data,
/* 0x67 */ x86emuOp_prefix_addr,
/* 0x68 */ x86emuOp_push_word_IMM,
/* 0x69 */ x86emuOp_imul_word_IMM,
/* 0x6a */ x86emuOp_push_byte_IMM,
/* 0x6b */ x86emuOp_imul_byte_IMM,
/* 0x6c */ x86emuOp_ins_byte,
/* 0x6d */ x86emuOp_ins_word,
/* 0x6e */ x86emuOp_outs_byte,
/* 0x6f */ x86emuOp_outs_word,
/* 0x70 */ x86emuOp_jump_near_cond,
/* 0x71 */ x86emuOp_jump_near_cond,
/* 0x72 */ x86emuOp_jump_near_cond,
/* 0x73 */ x86emuOp_jump_near_cond,
/* 0x74 */ x86emuOp_jump_near_cond,
/* 0x75 */ x86emuOp_jump_near_cond,
/* 0x76 */ x86emuOp_jump_near_cond,
/* 0x77 */ x86emuOp_jump_near_cond,
/* 0x78 */ x86emuOp_jump_near_cond,
/* 0x79 */ x86emuOp_jump_near_cond,
/* 0x7a */ x86emuOp_jump_near_cond,
/* 0x7b */ x86emuOp_jump_near_cond,
/* 0x7c */ x86emuOp_jump_near_cond,
/* 0x7d */ x86emuOp_jump_near_cond,
/* 0x7e */ x86emuOp_jump_near_cond,
/* 0x7f */ x86emuOp_jump_near_cond,
/* 0x80 */ x86emuOp_opc80_byte_RM_IMM,
/* 0x81 */ x86emuOp_opc81_word_RM_IMM,
/* 0x82 */ x86emuOp_opc82_byte_RM_IMM,
/* 0x83 */ x86emuOp_opc83_word_RM_IMM,
/* 0x84 */ x86emuOp_test_byte_RM_R,
/* 0x85 */ x86emuOp_test_word_RM_R,
/* 0x86 */ x86emuOp_xchg_byte_RM_R,
/* 0x87 */ x86emuOp_xchg_word_RM_R,
/* 0x88 */ x86emuOp_mov_byte_RM_R,
/* 0x89 */ x86emuOp_mov_word_RM_R,
/* 0x8a */ x86emuOp_mov_byte_R_RM,
/* 0x8b */ x86emuOp_mov_word_R_RM,
/* 0x8c */ x86emuOp_mov_word_RM_SR,
/* 0x8d */ x86emuOp_lea_word_R_M,
/* 0x8e */ x86emuOp_mov_word_SR_RM,
/* 0x8f */ x86emuOp_pop_RM,
/* 0x90 */ x86emuOp_nop,
/* 0x91 */ x86emuOp_xchg_word_AX_register,
/* 0x92 */ x86emuOp_xchg_word_AX_register,
/* 0x93 */ x86emuOp_xchg_word_AX_register,
/* 0x94 */ x86emuOp_xchg_word_AX_register,
/* 0x95 */ x86emuOp_xchg_word_AX_register,
/* 0x96 */ x86emuOp_xchg_word_AX_register,
/* 0x97 */ x86emuOp_xchg_word_AX_register,
/* 0x98 */ x86emuOp_cbw,
/* 0x99 */ x86emuOp_cwd,
/* 0x9a */ x86emuOp_call_far_IMM,
/* 0x9b */ x86emuOp_wait,
/* 0x9c */ x86emuOp_pushf_word,
/* 0x9d */ x86emuOp_popf_word,
/* 0x9e */ x86emuOp_sahf,
/* 0x9f */ x86emuOp_lahf,
/* 0xa0 */ x86emuOp_mov_AL_M_IMM,
/* 0xa1 */ x86emuOp_mov_AX_M_IMM,
/* 0xa2 */ x86emuOp_mov_M_AL_IMM,
/* 0xa3 */ x86emuOp_mov_M_AX_IMM,
/* 0xa4 */ x86emuOp_movs_byte,
/* 0xa5 */ x86emuOp_movs_word,
/* 0xa6 */ x86emuOp_cmps_byte,
/* 0xa7 */ x86emuOp_cmps_word,
/* 0xa8 */ x86emuOp_test_AL_IMM,
/* 0xa9 */ x86emuOp_test_AX_IMM,
/* 0xaa */ x86emuOp_stos_byte,
/* 0xab */ x86emuOp_stos_word,
/* 0xac */ x86emuOp_lods_byte,
/* 0xad */ x86emuOp_lods_word,
/* 0xac */ x86emuOp_scas_byte,
/* 0xad */ x86emuOp_scas_word,
/* 0xb0 */ x86emuOp_mov_byte_register_IMM,
/* 0xb1 */ x86emuOp_mov_byte_register_IMM,
/* 0xb2 */ x86emuOp_mov_byte_register_IMM,
/* 0xb3 */ x86emuOp_mov_byte_register_IMM,
/* 0xb4 */ x86emuOp_mov_byte_register_IMM,
/* 0xb5 */ x86emuOp_mov_byte_register_IMM,
/* 0xb6 */ x86emuOp_mov_byte_register_IMM,
/* 0xb7 */ x86emuOp_mov_byte_register_IMM,
/* 0xb8 */ x86emuOp_mov_word_register_IMM,
/* 0xb9 */ x86emuOp_mov_word_register_IMM,
/* 0xba */ x86emuOp_mov_word_register_IMM,
/* 0xbb */ x86emuOp_mov_word_register_IMM,
/* 0xbc */ x86emuOp_mov_word_register_IMM,
/* 0xbd */ x86emuOp_mov_word_register_IMM,
/* 0xbe */ x86emuOp_mov_word_register_IMM,
/* 0xbf */ x86emuOp_mov_word_register_IMM,
/* 0xc0 */ x86emuOp_opcC0_byte_RM_MEM,
/* 0xc1 */ x86emuOp_opcC1_word_RM_MEM,
/* 0xc2 */ x86emuOp_ret_near_IMM,
/* 0xc3 */ x86emuOp_ret_near,
/* 0xc4 */ x86emuOp_les_R_IMM,
/* 0xc5 */ x86emuOp_lds_R_IMM,
/* 0xc6 */ x86emuOp_mov_byte_RM_IMM,
/* 0xc7 */ x86emuOp_mov_word_RM_IMM,
/* 0xc8 */ x86emuOp_enter,
/* 0xc9 */ x86emuOp_leave,
/* 0xca */ x86emuOp_ret_far_IMM,
/* 0xcb */ x86emuOp_ret_far,
/* 0xcc */ x86emuOp_int3,
/* 0xcd */ x86emuOp_int_IMM,
/* 0xce */ x86emuOp_into,
/* 0xcf */ x86emuOp_iret,
/* 0xd0 */ x86emuOp_opcD0_byte_RM_1,
/* 0xd1 */ x86emuOp_opcD1_word_RM_1,
/* 0xd2 */ x86emuOp_opcD2_byte_RM_CL,
/* 0xd3 */ x86emuOp_opcD3_word_RM_CL,
/* 0xd4 */ x86emuOp_aam,
/* 0xd5 */ x86emuOp_aad,
/* 0xd6 */ x86emuOp_illegal_op, /* Undocumented SETALC instruction */
/* 0xd7 */ x86emuOp_xlat,
/* 0xd8 */ NULL, /*x86emuOp_esc_coprocess_d8,*/
/* 0xd9 */ NULL, /*x86emuOp_esc_coprocess_d9,*/
/* 0xda */ NULL, /*x86emuOp_esc_coprocess_da,*/
/* 0xdb */ NULL, /*x86emuOp_esc_coprocess_db,*/
/* 0xdc */ NULL, /*x86emuOp_esc_coprocess_dc,*/
/* 0xdd */ NULL, /*x86emuOp_esc_coprocess_dd,*/
/* 0xde */ NULL, /*x86emuOp_esc_coprocess_de,*/
/* 0xdf */ NULL, /*x86emuOp_esc_coprocess_df,*/
/* 0xe0 */ x86emuOp_loopne,
/* 0xe1 */ x86emuOp_loope,
/* 0xe2 */ x86emuOp_loop,
/* 0xe3 */ x86emuOp_jcxz,
/* 0xe4 */ x86emuOp_in_byte_AL_IMM,
/* 0xe5 */ x86emuOp_in_word_AX_IMM,
/* 0xe6 */ x86emuOp_out_byte_IMM_AL,
/* 0xe7 */ x86emuOp_out_word_IMM_AX,
/* 0xe8 */ x86emuOp_call_near_IMM,
/* 0xe9 */ x86emuOp_jump_near_IMM,
/* 0xea */ x86emuOp_jump_far_IMM,
/* 0xeb */ x86emuOp_jump_byte_IMM,
/* 0xec */ x86emuOp_in_byte_AL_DX,
/* 0xed */ x86emuOp_in_word_AX_DX,
/* 0xee */ x86emuOp_out_byte_DX_AL,
/* 0xef */ x86emuOp_out_word_DX_AX,
/* 0xf0 */ x86emuOp_lock,
/* 0xf1 */ x86emuOp_illegal_op,
/* 0xf2 */ x86emuOp_repne,
/* 0xf3 */ x86emuOp_repe,
/* 0xf4 */ x86emuOp_halt,
/* 0xf5 */ x86emuOp_cmc,
/* 0xf6 */ x86emuOp_opcF6_byte_RM,
/* 0xf7 */ x86emuOp_opcF7_word_RM,
/* 0xf8 */ x86emuOp_clc,
/* 0xf9 */ x86emuOp_stc,
/* 0xfa */ x86emuOp_cli,
/* 0xfb */ x86emuOp_sti,
/* 0xfc */ x86emuOp_cld,
/* 0xfd */ x86emuOp_std,
/* 0xfe */ x86emuOp_opcFE_byte_RM,
/* 0xff */ x86emuOp_opcFF_word_RM,
};
|
1001-study-uboot
|
drivers/bios_emulator/x86emu/ops.c
|
C
|
gpl3
| 143,458
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: This file contains the code to handle debugging of the
* emulator.
*
****************************************************************************/
#include <stdarg.h>
#include <common.h>
#include <linux/ctype.h>
#include "x86emu/x86emui.h"
/*----------------------------- Implementation ----------------------------*/
#ifdef DEBUG
static void print_encoded_bytes(u16 s, u16 o);
static void print_decoded_instruction(void);
static int x86emu_parse_line(char *s, int *ps, int *n);
/* should look something like debug's output. */
void X86EMU_trace_regs(void)
{
if (DEBUG_TRACE()) {
x86emu_dump_regs();
}
if (DEBUG_DECODE() && !DEBUG_DECODE_NOPRINT()) {
printk("%04x:%04x ", M.x86.saved_cs, M.x86.saved_ip);
print_encoded_bytes(M.x86.saved_cs, M.x86.saved_ip);
print_decoded_instruction();
}
}
void X86EMU_trace_xregs(void)
{
if (DEBUG_TRACE()) {
x86emu_dump_xregs();
}
}
void x86emu_just_disassemble(void)
{
/*
* This routine called if the flag DEBUG_DISASSEMBLE is set kind
* of a hack!
*/
printk("%04x:%04x ", M.x86.saved_cs, M.x86.saved_ip);
print_encoded_bytes(M.x86.saved_cs, M.x86.saved_ip);
print_decoded_instruction();
}
static void disassemble_forward(u16 seg, u16 off, int n)
{
X86EMU_sysEnv tregs;
int i;
u8 op1;
/*
* hack, hack, hack. What we do is use the exact machinery set up
* for execution, except that now there is an additional state
* flag associated with the "execution", and we are using a copy
* of the register struct. All the major opcodes, once fully
* decoded, have the following two steps: TRACE_REGS(r,m);
* SINGLE_STEP(r,m); which disappear if DEBUG is not defined to
* the preprocessor. The TRACE_REGS macro expands to:
*
* if (debug&DEBUG_DISASSEMBLE)
* {just_disassemble(); goto EndOfInstruction;}
* if (debug&DEBUG_TRACE) trace_regs(r,m);
*
* ...... and at the last line of the routine.
*
* EndOfInstruction: end_instr();
*
* Up to the point where TRACE_REG is expanded, NO modifications
* are done to any register EXCEPT the IP register, for fetch and
* decoding purposes.
*
* This was done for an entirely different reason, but makes a
* nice way to get the system to help debug codes.
*/
tregs = M;
tregs.x86.R_IP = off;
tregs.x86.R_CS = seg;
/* reset the decoding buffers */
tregs.x86.enc_str_pos = 0;
tregs.x86.enc_pos = 0;
/* turn on the "disassemble only, no execute" flag */
tregs.x86.debug |= DEBUG_DISASSEMBLE_F;
/* DUMP NEXT n instructions to screen in straight_line fashion */
/*
* This looks like the regular instruction fetch stream, except
* that when this occurs, each fetched opcode, upon seeing the
* DEBUG_DISASSEMBLE flag set, exits immediately after decoding
* the instruction. XXX --- CHECK THAT MEM IS NOT AFFECTED!!!
* Note the use of a copy of the register structure...
*/
for (i = 0; i < n; i++) {
op1 = (*sys_rdb) (((u32) M.x86.R_CS << 4) + (M.x86.R_IP++));
(x86emu_optab[op1]) (op1);
}
/* end major hack mode. */
}
void x86emu_check_ip_access(void)
{
/* NULL as of now */
}
void x86emu_check_sp_access(void)
{
}
void x86emu_check_mem_access(u32 dummy)
{
/* check bounds, etc */
}
void x86emu_check_data_access(uint dummy1, uint dummy2)
{
/* check bounds, etc */
}
void x86emu_inc_decoded_inst_len(int x)
{
M.x86.enc_pos += x;
}
void x86emu_decode_printf(char *x)
{
sprintf(M.x86.decoded_buf + M.x86.enc_str_pos, "%s", x);
M.x86.enc_str_pos += strlen(x);
}
void x86emu_decode_printf2(char *x, int y)
{
char temp[100];
sprintf(temp, x, y);
sprintf(M.x86.decoded_buf + M.x86.enc_str_pos, "%s", temp);
M.x86.enc_str_pos += strlen(temp);
}
void x86emu_end_instr(void)
{
M.x86.enc_str_pos = 0;
M.x86.enc_pos = 0;
}
static void print_encoded_bytes(u16 s, u16 o)
{
int i;
char buf1[64];
for (i = 0; i < M.x86.enc_pos; i++) {
sprintf(buf1 + 2 * i, "%02x", fetch_data_byte_abs(s, o + i));
}
printk("%-20s", buf1);
}
static void print_decoded_instruction(void)
{
printk("%s", M.x86.decoded_buf);
}
void x86emu_print_int_vect(u16 iv)
{
u16 seg, off;
if (iv > 256)
return;
seg = fetch_data_word_abs(0, iv * 4);
off = fetch_data_word_abs(0, iv * 4 + 2);
printk("%04x:%04x ", seg, off);
}
void X86EMU_dump_memory(u16 seg, u16 off, u32 amt)
{
u32 start = off & 0xfffffff0;
u32 end = (off + 16) & 0xfffffff0;
u32 i;
u32 current;
current = start;
while (end <= off + amt) {
printk("%04x:%04x ", seg, start);
for (i = start; i < off; i++)
printk(" ");
for (; i < end; i++)
printk("%02x ", fetch_data_byte_abs(seg, i));
printk("\n");
start = end;
end = start + 16;
}
}
void x86emu_single_step(void)
{
char s[1024];
int ps[10];
int ntok;
int cmd;
int done;
int segment;
int offset;
static int breakpoint;
static int noDecode = 1;
char *p;
if (DEBUG_BREAK()) {
if (M.x86.saved_ip != breakpoint) {
return;
} else {
M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F;
M.x86.debug |= DEBUG_TRACE_F;
M.x86.debug &= ~DEBUG_BREAK_F;
print_decoded_instruction();
X86EMU_trace_regs();
}
}
done = 0;
offset = M.x86.saved_ip;
while (!done) {
printk("-");
cmd = x86emu_parse_line(s, ps, &ntok);
switch (cmd) {
case 'u':
disassemble_forward(M.x86.saved_cs, (u16) offset, 10);
break;
case 'd':
if (ntok == 2) {
segment = M.x86.saved_cs;
offset = ps[1];
X86EMU_dump_memory(segment, (u16) offset, 16);
offset += 16;
} else if (ntok == 3) {
segment = ps[1];
offset = ps[2];
X86EMU_dump_memory(segment, (u16) offset, 16);
offset += 16;
} else {
segment = M.x86.saved_cs;
X86EMU_dump_memory(segment, (u16) offset, 16);
offset += 16;
}
break;
case 'c':
M.x86.debug ^= DEBUG_TRACECALL_F;
break;
case 's':
M.x86.debug ^=
DEBUG_SVC_F | DEBUG_SYS_F | DEBUG_SYSINT_F;
break;
case 'r':
X86EMU_trace_regs();
break;
case 'x':
X86EMU_trace_xregs();
break;
case 'g':
if (ntok == 2) {
breakpoint = ps[1];
if (noDecode) {
M.x86.debug |= DEBUG_DECODE_NOPRINT_F;
} else {
M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F;
}
M.x86.debug &= ~DEBUG_TRACE_F;
M.x86.debug |= DEBUG_BREAK_F;
done = 1;
}
break;
case 'q':
M.x86.debug |= DEBUG_EXIT;
return;
case 'P':
noDecode = (noDecode) ? 0 : 1;
printk("Toggled decoding to %s\n",
(noDecode) ? "FALSE" : "TRUE");
break;
case 't':
case 0:
done = 1;
break;
}
}
}
int X86EMU_trace_on(void)
{
return M.x86.debug |= DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F;
}
int X86EMU_trace_off(void)
{
return M.x86.debug &= ~(DEBUG_STEP_F | DEBUG_DECODE_F | DEBUG_TRACE_F);
}
static int x86emu_parse_line(char *s, int *ps, int *n)
{
int cmd;
*n = 0;
while (isblank(*s))
s++;
ps[*n] = *s;
switch (*s) {
case '\n':
*n += 1;
return 0;
default:
cmd = *s;
*n += 1;
}
while (1) {
while (!isblank(*s) && *s != '\n')
s++;
if (*s == '\n')
return cmd;
while (isblank(*s))
s++;
*n += 1;
}
}
#endif /* DEBUG */
void x86emu_dump_regs(void)
{
printk("\tAX=%04x ", M.x86.R_AX);
printk("BX=%04x ", M.x86.R_BX);
printk("CX=%04x ", M.x86.R_CX);
printk("DX=%04x ", M.x86.R_DX);
printk("SP=%04x ", M.x86.R_SP);
printk("BP=%04x ", M.x86.R_BP);
printk("SI=%04x ", M.x86.R_SI);
printk("DI=%04x\n", M.x86.R_DI);
printk("\tDS=%04x ", M.x86.R_DS);
printk("ES=%04x ", M.x86.R_ES);
printk("SS=%04x ", M.x86.R_SS);
printk("CS=%04x ", M.x86.R_CS);
printk("IP=%04x ", M.x86.R_IP);
if (ACCESS_FLAG(F_OF))
printk("OV "); /* CHECKED... */
else
printk("NV ");
if (ACCESS_FLAG(F_DF))
printk("DN ");
else
printk("UP ");
if (ACCESS_FLAG(F_IF))
printk("EI ");
else
printk("DI ");
if (ACCESS_FLAG(F_SF))
printk("NG ");
else
printk("PL ");
if (ACCESS_FLAG(F_ZF))
printk("ZR ");
else
printk("NZ ");
if (ACCESS_FLAG(F_AF))
printk("AC ");
else
printk("NA ");
if (ACCESS_FLAG(F_PF))
printk("PE ");
else
printk("PO ");
if (ACCESS_FLAG(F_CF))
printk("CY ");
else
printk("NC ");
printk("\n");
}
void x86emu_dump_xregs(void)
{
printk("\tEAX=%08x ", M.x86.R_EAX);
printk("EBX=%08x ", M.x86.R_EBX);
printk("ECX=%08x ", M.x86.R_ECX);
printk("EDX=%08x \n", M.x86.R_EDX);
printk("\tESP=%08x ", M.x86.R_ESP);
printk("EBP=%08x ", M.x86.R_EBP);
printk("ESI=%08x ", M.x86.R_ESI);
printk("EDI=%08x\n", M.x86.R_EDI);
printk("\tDS=%04x ", M.x86.R_DS);
printk("ES=%04x ", M.x86.R_ES);
printk("SS=%04x ", M.x86.R_SS);
printk("CS=%04x ", M.x86.R_CS);
printk("EIP=%08x\n\t", M.x86.R_EIP);
if (ACCESS_FLAG(F_OF))
printk("OV "); /* CHECKED... */
else
printk("NV ");
if (ACCESS_FLAG(F_DF))
printk("DN ");
else
printk("UP ");
if (ACCESS_FLAG(F_IF))
printk("EI ");
else
printk("DI ");
if (ACCESS_FLAG(F_SF))
printk("NG ");
else
printk("PL ");
if (ACCESS_FLAG(F_ZF))
printk("ZR ");
else
printk("NZ ");
if (ACCESS_FLAG(F_AF))
printk("AC ");
else
printk("NA ");
if (ACCESS_FLAG(F_PF))
printk("PE ");
else
printk("PO ");
if (ACCESS_FLAG(F_CF))
printk("CY ");
else
printk("NC ");
printk("\n");
}
|
1001-study-uboot
|
drivers/bios_emulator/x86emu/debug.c
|
C
|
gpl3
| 10,764
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: This file includes subroutines which are related to
* instruction decoding and accessess of immediate data via IP. etc.
*
****************************************************************************/
#include <common.h>
#include "x86emu/x86emui.h"
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
REMARKS:
Handles any pending asychronous interrupts.
****************************************************************************/
static void x86emu_intr_handle(void)
{
u8 intno;
if (M.x86.intr & INTR_SYNCH) {
intno = M.x86.intno;
if (_X86EMU_intrTab[intno]) {
(*_X86EMU_intrTab[intno])(intno);
} else {
push_word((u16)M.x86.R_FLG);
CLEAR_FLAG(F_IF);
CLEAR_FLAG(F_TF);
push_word(M.x86.R_CS);
M.x86.R_CS = mem_access_word(intno * 4 + 2);
push_word(M.x86.R_IP);
M.x86.R_IP = mem_access_word(intno * 4);
M.x86.intr = 0;
}
}
}
/****************************************************************************
PARAMETERS:
intrnum - Interrupt number to raise
REMARKS:
Raise the specified interrupt to be handled before the execution of the
next instruction.
****************************************************************************/
void x86emu_intr_raise(
u8 intrnum)
{
M.x86.intno = intrnum;
M.x86.intr |= INTR_SYNCH;
}
/****************************************************************************
REMARKS:
Main execution loop for the emulator. We return from here when the system
halts, which is normally caused by a stack fault when we return from the
original real mode call.
****************************************************************************/
void X86EMU_exec(void)
{
u8 op1;
M.x86.intr = 0;
DB(x86emu_end_instr();)
for (;;) {
DB( if (CHECK_IP_FETCH())
x86emu_check_ip_access();)
/* If debugging, save the IP and CS values. */
SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP);
INC_DECODED_INST_LEN(1);
if (M.x86.intr) {
if (M.x86.intr & INTR_HALTED) {
DB( if (M.x86.R_SP != 0) {
printk("halted\n");
X86EMU_trace_regs();
}
else {
if (M.x86.debug)
printk("Service completed successfully\n");
})
return;
}
if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) ||
!ACCESS_FLAG(F_IF)) {
x86emu_intr_handle();
}
}
op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
(*x86emu_optab[op1])(op1);
if (M.x86.debug & DEBUG_EXIT) {
M.x86.debug &= ~DEBUG_EXIT;
return;
}
}
}
/****************************************************************************
REMARKS:
Halts the system by setting the halted system flag.
****************************************************************************/
void X86EMU_halt_sys(void)
{
M.x86.intr |= INTR_HALTED;
}
/****************************************************************************
PARAMETERS:
mod - Mod value from decoded byte
regh - Reg h value from decoded byte
regl - Reg l value from decoded byte
REMARKS:
Raise the specified interrupt to be handled before the execution of the
next instruction.
NOTE: Do not inline this function, as (*sys_rdb) is already inline!
****************************************************************************/
void fetch_decode_modrm(
int *mod,
int *regh,
int *regl)
{
int fetched;
DB( if (CHECK_IP_FETCH())
x86emu_check_ip_access();)
fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
INC_DECODED_INST_LEN(1);
*mod = (fetched >> 6) & 0x03;
*regh = (fetched >> 3) & 0x07;
*regl = (fetched >> 0) & 0x07;
}
/****************************************************************************
RETURNS:
Immediate byte value read from instruction queue
REMARKS:
This function returns the immediate byte from the instruction queue, and
moves the instruction pointer to the next value.
NOTE: Do not inline this function, as (*sys_rdb) is already inline!
****************************************************************************/
u8 fetch_byte_imm(void)
{
u8 fetched;
DB( if (CHECK_IP_FETCH())
x86emu_check_ip_access();)
fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++));
INC_DECODED_INST_LEN(1);
return fetched;
}
/****************************************************************************
RETURNS:
Immediate word value read from instruction queue
REMARKS:
This function returns the immediate byte from the instruction queue, and
moves the instruction pointer to the next value.
NOTE: Do not inline this function, as (*sys_rdw) is already inline!
****************************************************************************/
u16 fetch_word_imm(void)
{
u16 fetched;
DB( if (CHECK_IP_FETCH())
x86emu_check_ip_access();)
fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP));
M.x86.R_IP += 2;
INC_DECODED_INST_LEN(2);
return fetched;
}
/****************************************************************************
RETURNS:
Immediate lone value read from instruction queue
REMARKS:
This function returns the immediate byte from the instruction queue, and
moves the instruction pointer to the next value.
NOTE: Do not inline this function, as (*sys_rdw) is already inline!
****************************************************************************/
u32 fetch_long_imm(void)
{
u32 fetched;
DB( if (CHECK_IP_FETCH())
x86emu_check_ip_access();)
fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP));
M.x86.R_IP += 4;
INC_DECODED_INST_LEN(4);
return fetched;
}
/****************************************************************************
RETURNS:
Value of the default data segment
REMARKS:
Inline function that returns the default data segment for the current
instruction.
On the x86 processor, the default segment is not always DS if there is
no segment override. Address modes such as -3[BP] or 10[BP+SI] all refer to
addresses relative to SS (ie: on the stack). So, at the minimum, all
decodings of addressing modes would have to set/clear a bit describing
whether the access is relative to DS or SS. That is the function of the
cpu-state-varible M.x86.mode. There are several potential states:
repe prefix seen (handled elsewhere)
repne prefix seen (ditto)
cs segment override
ds segment override
es segment override
fs segment override
gs segment override
ss segment override
ds/ss select (in absense of override)
Each of the above 7 items are handled with a bit in the mode field.
****************************************************************************/
_INLINE u32 get_data_segment(void)
{
#define GET_SEGMENT(segment)
switch (M.x86.mode & SYSMODE_SEGMASK) {
case 0: /* default case: use ds register */
case SYSMODE_SEGOVR_DS:
case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS:
return M.x86.R_DS;
case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */
return M.x86.R_SS;
case SYSMODE_SEGOVR_CS:
case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS:
return M.x86.R_CS;
case SYSMODE_SEGOVR_ES:
case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS:
return M.x86.R_ES;
case SYSMODE_SEGOVR_FS:
case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS:
return M.x86.R_FS;
case SYSMODE_SEGOVR_GS:
case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS:
return M.x86.R_GS;
case SYSMODE_SEGOVR_SS:
case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS:
return M.x86.R_SS;
default:
#ifdef DEBUG
printk("error: should not happen: multiple overrides.\n");
#endif
HALT_SYS();
return 0;
}
}
/****************************************************************************
PARAMETERS:
offset - Offset to load data from
RETURNS:
Byte value read from the absolute memory location.
NOTE: Do not inline this function as (*sys_rdX) is already inline!
****************************************************************************/
u8 fetch_data_byte(
uint offset)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
return (*sys_rdb)((get_data_segment() << 4) + offset);
}
/****************************************************************************
PARAMETERS:
offset - Offset to load data from
RETURNS:
Word value read from the absolute memory location.
NOTE: Do not inline this function as (*sys_rdX) is already inline!
****************************************************************************/
u16 fetch_data_word(
uint offset)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
return (*sys_rdw)((get_data_segment() << 4) + offset);
}
/****************************************************************************
PARAMETERS:
offset - Offset to load data from
RETURNS:
Long value read from the absolute memory location.
NOTE: Do not inline this function as (*sys_rdX) is already inline!
****************************************************************************/
u32 fetch_data_long(
uint offset)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
return (*sys_rdl)((get_data_segment() << 4) + offset);
}
/****************************************************************************
PARAMETERS:
segment - Segment to load data from
offset - Offset to load data from
RETURNS:
Byte value read from the absolute memory location.
NOTE: Do not inline this function as (*sys_rdX) is already inline!
****************************************************************************/
u8 fetch_data_byte_abs(
uint segment,
uint offset)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
return (*sys_rdb)(((u32)segment << 4) + offset);
}
/****************************************************************************
PARAMETERS:
segment - Segment to load data from
offset - Offset to load data from
RETURNS:
Word value read from the absolute memory location.
NOTE: Do not inline this function as (*sys_rdX) is already inline!
****************************************************************************/
u16 fetch_data_word_abs(
uint segment,
uint offset)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
return (*sys_rdw)(((u32)segment << 4) + offset);
}
/****************************************************************************
PARAMETERS:
segment - Segment to load data from
offset - Offset to load data from
RETURNS:
Long value read from the absolute memory location.
NOTE: Do not inline this function as (*sys_rdX) is already inline!
****************************************************************************/
u32 fetch_data_long_abs(
uint segment,
uint offset)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
return (*sys_rdl)(((u32)segment << 4) + offset);
}
/****************************************************************************
PARAMETERS:
offset - Offset to store data at
val - Value to store
REMARKS:
Writes a word value to an segmented memory location. The segment used is
the current 'default' segment, which may have been overridden.
NOTE: Do not inline this function as (*sys_wrX) is already inline!
****************************************************************************/
void store_data_byte(
uint offset,
u8 val)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
(*sys_wrb)((get_data_segment() << 4) + offset, val);
}
/****************************************************************************
PARAMETERS:
offset - Offset to store data at
val - Value to store
REMARKS:
Writes a word value to an segmented memory location. The segment used is
the current 'default' segment, which may have been overridden.
NOTE: Do not inline this function as (*sys_wrX) is already inline!
****************************************************************************/
void store_data_word(
uint offset,
u16 val)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
(*sys_wrw)((get_data_segment() << 4) + offset, val);
}
/****************************************************************************
PARAMETERS:
offset - Offset to store data at
val - Value to store
REMARKS:
Writes a long value to an segmented memory location. The segment used is
the current 'default' segment, which may have been overridden.
NOTE: Do not inline this function as (*sys_wrX) is already inline!
****************************************************************************/
void store_data_long(
uint offset,
u32 val)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access((u16)get_data_segment(), offset);
#endif
(*sys_wrl)((get_data_segment() << 4) + offset, val);
}
/****************************************************************************
PARAMETERS:
segment - Segment to store data at
offset - Offset to store data at
val - Value to store
REMARKS:
Writes a byte value to an absolute memory location.
NOTE: Do not inline this function as (*sys_wrX) is already inline!
****************************************************************************/
void store_data_byte_abs(
uint segment,
uint offset,
u8 val)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
(*sys_wrb)(((u32)segment << 4) + offset, val);
}
/****************************************************************************
PARAMETERS:
segment - Segment to store data at
offset - Offset to store data at
val - Value to store
REMARKS:
Writes a word value to an absolute memory location.
NOTE: Do not inline this function as (*sys_wrX) is already inline!
****************************************************************************/
void store_data_word_abs(
uint segment,
uint offset,
u16 val)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
(*sys_wrw)(((u32)segment << 4) + offset, val);
}
/****************************************************************************
PARAMETERS:
segment - Segment to store data at
offset - Offset to store data at
val - Value to store
REMARKS:
Writes a long value to an absolute memory location.
NOTE: Do not inline this function as (*sys_wrX) is already inline!
****************************************************************************/
void store_data_long_abs(
uint segment,
uint offset,
u32 val)
{
#ifdef DEBUG
if (CHECK_DATA_ACCESS())
x86emu_check_data_access(segment, offset);
#endif
(*sys_wrl)(((u32)segment << 4) + offset, val);
}
/****************************************************************************
PARAMETERS:
reg - Register to decode
RETURNS:
Pointer to the appropriate register
REMARKS:
Return a pointer to the register given by the R/RM field of the
modrm byte, for byte operands. Also enables the decoding of instructions.
****************************************************************************/
u8* decode_rm_byte_register(
int reg)
{
switch (reg) {
case 0:
DECODE_PRINTF("AL");
return &M.x86.R_AL;
case 1:
DECODE_PRINTF("CL");
return &M.x86.R_CL;
case 2:
DECODE_PRINTF("DL");
return &M.x86.R_DL;
case 3:
DECODE_PRINTF("BL");
return &M.x86.R_BL;
case 4:
DECODE_PRINTF("AH");
return &M.x86.R_AH;
case 5:
DECODE_PRINTF("CH");
return &M.x86.R_CH;
case 6:
DECODE_PRINTF("DH");
return &M.x86.R_DH;
case 7:
DECODE_PRINTF("BH");
return &M.x86.R_BH;
}
HALT_SYS();
return NULL; /* NOT REACHED OR REACHED ON ERROR */
}
/****************************************************************************
PARAMETERS:
reg - Register to decode
RETURNS:
Pointer to the appropriate register
REMARKS:
Return a pointer to the register given by the R/RM field of the
modrm byte, for word operands. Also enables the decoding of instructions.
****************************************************************************/
u16* decode_rm_word_register(
int reg)
{
switch (reg) {
case 0:
DECODE_PRINTF("AX");
return &M.x86.R_AX;
case 1:
DECODE_PRINTF("CX");
return &M.x86.R_CX;
case 2:
DECODE_PRINTF("DX");
return &M.x86.R_DX;
case 3:
DECODE_PRINTF("BX");
return &M.x86.R_BX;
case 4:
DECODE_PRINTF("SP");
return &M.x86.R_SP;
case 5:
DECODE_PRINTF("BP");
return &M.x86.R_BP;
case 6:
DECODE_PRINTF("SI");
return &M.x86.R_SI;
case 7:
DECODE_PRINTF("DI");
return &M.x86.R_DI;
}
HALT_SYS();
return NULL; /* NOTREACHED OR REACHED ON ERROR */
}
/****************************************************************************
PARAMETERS:
reg - Register to decode
RETURNS:
Pointer to the appropriate register
REMARKS:
Return a pointer to the register given by the R/RM field of the
modrm byte, for dword operands. Also enables the decoding of instructions.
****************************************************************************/
u32* decode_rm_long_register(
int reg)
{
switch (reg) {
case 0:
DECODE_PRINTF("EAX");
return &M.x86.R_EAX;
case 1:
DECODE_PRINTF("ECX");
return &M.x86.R_ECX;
case 2:
DECODE_PRINTF("EDX");
return &M.x86.R_EDX;
case 3:
DECODE_PRINTF("EBX");
return &M.x86.R_EBX;
case 4:
DECODE_PRINTF("ESP");
return &M.x86.R_ESP;
case 5:
DECODE_PRINTF("EBP");
return &M.x86.R_EBP;
case 6:
DECODE_PRINTF("ESI");
return &M.x86.R_ESI;
case 7:
DECODE_PRINTF("EDI");
return &M.x86.R_EDI;
}
HALT_SYS();
return NULL; /* NOTREACHED OR REACHED ON ERROR */
}
/****************************************************************************
PARAMETERS:
reg - Register to decode
RETURNS:
Pointer to the appropriate register
REMARKS:
Return a pointer to the register given by the R/RM field of the
modrm byte, for word operands, modified from above for the weirdo
special case of segreg operands. Also enables the decoding of instructions.
****************************************************************************/
u16* decode_rm_seg_register(
int reg)
{
switch (reg) {
case 0:
DECODE_PRINTF("ES");
return &M.x86.R_ES;
case 1:
DECODE_PRINTF("CS");
return &M.x86.R_CS;
case 2:
DECODE_PRINTF("SS");
return &M.x86.R_SS;
case 3:
DECODE_PRINTF("DS");
return &M.x86.R_DS;
case 4:
DECODE_PRINTF("FS");
return &M.x86.R_FS;
case 5:
DECODE_PRINTF("GS");
return &M.x86.R_GS;
case 6:
case 7:
DECODE_PRINTF("ILLEGAL SEGREG");
break;
}
HALT_SYS();
return NULL; /* NOT REACHED OR REACHED ON ERROR */
}
/****************************************************************************
PARAMETERS:
scale - scale value of SIB byte
index - index value of SIB byte
RETURNS:
Value of scale * index
REMARKS:
Decodes scale/index of SIB byte and returns relevant offset part of
effective address.
****************************************************************************/
unsigned decode_sib_si(
int scale,
int index)
{
scale = 1 << scale;
if (scale > 1) {
DECODE_PRINTF2("[%d*", scale);
} else {
DECODE_PRINTF("[");
}
switch (index) {
case 0:
DECODE_PRINTF("EAX]");
return M.x86.R_EAX * index;
case 1:
DECODE_PRINTF("ECX]");
return M.x86.R_ECX * index;
case 2:
DECODE_PRINTF("EDX]");
return M.x86.R_EDX * index;
case 3:
DECODE_PRINTF("EBX]");
return M.x86.R_EBX * index;
case 4:
DECODE_PRINTF("0]");
return 0;
case 5:
DECODE_PRINTF("EBP]");
return M.x86.R_EBP * index;
case 6:
DECODE_PRINTF("ESI]");
return M.x86.R_ESI * index;
case 7:
DECODE_PRINTF("EDI]");
return M.x86.R_EDI * index;
}
HALT_SYS();
return 0; /* NOT REACHED OR REACHED ON ERROR */
}
/****************************************************************************
PARAMETERS:
mod - MOD value of preceding ModR/M byte
RETURNS:
Offset in memory for the address decoding
REMARKS:
Decodes SIB addressing byte and returns calculated effective address.
****************************************************************************/
unsigned decode_sib_address(
int mod)
{
int sib = fetch_byte_imm();
int ss = (sib >> 6) & 0x03;
int index = (sib >> 3) & 0x07;
int base = sib & 0x07;
int offset = 0;
int displacement;
switch (base) {
case 0:
DECODE_PRINTF("[EAX]");
offset = M.x86.R_EAX;
break;
case 1:
DECODE_PRINTF("[ECX]");
offset = M.x86.R_ECX;
break;
case 2:
DECODE_PRINTF("[EDX]");
offset = M.x86.R_EDX;
break;
case 3:
DECODE_PRINTF("[EBX]");
offset = M.x86.R_EBX;
break;
case 4:
DECODE_PRINTF("[ESP]");
offset = M.x86.R_ESP;
break;
case 5:
switch (mod) {
case 0:
displacement = (s32)fetch_long_imm();
DECODE_PRINTF2("[%d]", displacement);
offset = displacement;
break;
case 1:
displacement = (s8)fetch_byte_imm();
DECODE_PRINTF2("[%d][EBP]", displacement);
offset = M.x86.R_EBP + displacement;
break;
case 2:
displacement = (s32)fetch_long_imm();
DECODE_PRINTF2("[%d][EBP]", displacement);
offset = M.x86.R_EBP + displacement;
break;
default:
HALT_SYS();
}
DECODE_PRINTF("[EAX]");
offset = M.x86.R_EAX;
break;
case 6:
DECODE_PRINTF("[ESI]");
offset = M.x86.R_ESI;
break;
case 7:
DECODE_PRINTF("[EDI]");
offset = M.x86.R_EDI;
break;
default:
HALT_SYS();
}
offset += decode_sib_si(ss, index);
return offset;
}
/****************************************************************************
PARAMETERS:
rm - RM value to decode
RETURNS:
Offset in memory for the address decoding
REMARKS:
Return the offset given by mod=00 addressing. Also enables the
decoding of instructions.
NOTE: The code which specifies the corresponding segment (ds vs ss)
below in the case of [BP+..]. The assumption here is that at the
point that this subroutine is called, the bit corresponding to
SYSMODE_SEG_DS_SS will be zero. After every instruction
except the segment override instructions, this bit (as well
as any bits indicating segment overrides) will be clear. So
if a SS access is needed, set this bit. Otherwise, DS access
occurs (unless any of the segment override bits are set).
****************************************************************************/
unsigned decode_rm00_address(
int rm)
{
unsigned offset;
if (M.x86.mode & SYSMODE_PREFIX_ADDR) {
/* 32-bit addressing */
switch (rm) {
case 0:
DECODE_PRINTF("[EAX]");
return M.x86.R_EAX;
case 1:
DECODE_PRINTF("[ECX]");
return M.x86.R_ECX;
case 2:
DECODE_PRINTF("[EDX]");
return M.x86.R_EDX;
case 3:
DECODE_PRINTF("[EBX]");
return M.x86.R_EBX;
case 4:
return decode_sib_address(0);
case 5:
offset = fetch_long_imm();
DECODE_PRINTF2("[%08x]", offset);
return offset;
case 6:
DECODE_PRINTF("[ESI]");
return M.x86.R_ESI;
case 7:
DECODE_PRINTF("[EDI]");
return M.x86.R_EDI;
}
} else {
/* 16-bit addressing */
switch (rm) {
case 0:
DECODE_PRINTF("[BX+SI]");
return (M.x86.R_BX + M.x86.R_SI) & 0xffff;
case 1:
DECODE_PRINTF("[BX+DI]");
return (M.x86.R_BX + M.x86.R_DI) & 0xffff;
case 2:
DECODE_PRINTF("[BP+SI]");
M.x86.mode |= SYSMODE_SEG_DS_SS;
return (M.x86.R_BP + M.x86.R_SI) & 0xffff;
case 3:
DECODE_PRINTF("[BP+DI]");
M.x86.mode |= SYSMODE_SEG_DS_SS;
return (M.x86.R_BP + M.x86.R_DI) & 0xffff;
case 4:
DECODE_PRINTF("[SI]");
return M.x86.R_SI;
case 5:
DECODE_PRINTF("[DI]");
return M.x86.R_DI;
case 6:
offset = fetch_word_imm();
DECODE_PRINTF2("[%04x]", offset);
return offset;
case 7:
DECODE_PRINTF("[BX]");
return M.x86.R_BX;
}
}
HALT_SYS();
return 0;
}
/****************************************************************************
PARAMETERS:
rm - RM value to decode
RETURNS:
Offset in memory for the address decoding
REMARKS:
Return the offset given by mod=01 addressing. Also enables the
decoding of instructions.
****************************************************************************/
unsigned decode_rm01_address(
int rm)
{
int displacement;
if (M.x86.mode & SYSMODE_PREFIX_ADDR) {
/* 32-bit addressing */
if (rm != 4)
displacement = (s8)fetch_byte_imm();
else
displacement = 0;
switch (rm) {
case 0:
DECODE_PRINTF2("%d[EAX]", displacement);
return M.x86.R_EAX + displacement;
case 1:
DECODE_PRINTF2("%d[ECX]", displacement);
return M.x86.R_ECX + displacement;
case 2:
DECODE_PRINTF2("%d[EDX]", displacement);
return M.x86.R_EDX + displacement;
case 3:
DECODE_PRINTF2("%d[EBX]", displacement);
return M.x86.R_EBX + displacement;
case 4: {
int offset = decode_sib_address(1);
displacement = (s8)fetch_byte_imm();
DECODE_PRINTF2("[%d]", displacement);
return offset + displacement;
}
case 5:
DECODE_PRINTF2("%d[EBP]", displacement);
return M.x86.R_EBP + displacement;
case 6:
DECODE_PRINTF2("%d[ESI]", displacement);
return M.x86.R_ESI + displacement;
case 7:
DECODE_PRINTF2("%d[EDI]", displacement);
return M.x86.R_EDI + displacement;
}
} else {
/* 16-bit addressing */
displacement = (s8)fetch_byte_imm();
switch (rm) {
case 0:
DECODE_PRINTF2("%d[BX+SI]", displacement);
return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff;
case 1:
DECODE_PRINTF2("%d[BX+DI]", displacement);
return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff;
case 2:
DECODE_PRINTF2("%d[BP+SI]", displacement);
M.x86.mode |= SYSMODE_SEG_DS_SS;
return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff;
case 3:
DECODE_PRINTF2("%d[BP+DI]", displacement);
M.x86.mode |= SYSMODE_SEG_DS_SS;
return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff;
case 4:
DECODE_PRINTF2("%d[SI]", displacement);
return (M.x86.R_SI + displacement) & 0xffff;
case 5:
DECODE_PRINTF2("%d[DI]", displacement);
return (M.x86.R_DI + displacement) & 0xffff;
case 6:
DECODE_PRINTF2("%d[BP]", displacement);
M.x86.mode |= SYSMODE_SEG_DS_SS;
return (M.x86.R_BP + displacement) & 0xffff;
case 7:
DECODE_PRINTF2("%d[BX]", displacement);
return (M.x86.R_BX + displacement) & 0xffff;
}
}
HALT_SYS();
return 0; /* SHOULD NOT HAPPEN */
}
/****************************************************************************
PARAMETERS:
rm - RM value to decode
RETURNS:
Offset in memory for the address decoding
REMARKS:
Return the offset given by mod=10 addressing. Also enables the
decoding of instructions.
****************************************************************************/
unsigned decode_rm10_address(
int rm)
{
if (M.x86.mode & SYSMODE_PREFIX_ADDR) {
int displacement;
/* 32-bit addressing */
if (rm != 4)
displacement = (s32)fetch_long_imm();
else
displacement = 0;
switch (rm) {
case 0:
DECODE_PRINTF2("%d[EAX]", displacement);
return M.x86.R_EAX + displacement;
case 1:
DECODE_PRINTF2("%d[ECX]", displacement);
return M.x86.R_ECX + displacement;
case 2:
DECODE_PRINTF2("%d[EDX]", displacement);
return M.x86.R_EDX + displacement;
case 3:
DECODE_PRINTF2("%d[EBX]", displacement);
return M.x86.R_EBX + displacement;
case 4: {
int offset = decode_sib_address(2);
displacement = (s32)fetch_long_imm();
DECODE_PRINTF2("[%d]", displacement);
return offset + displacement;
}
case 5:
DECODE_PRINTF2("%d[EBP]", displacement);
return M.x86.R_EBP + displacement;
case 6:
DECODE_PRINTF2("%d[ESI]", displacement);
return M.x86.R_ESI + displacement;
case 7:
DECODE_PRINTF2("%d[EDI]", displacement);
return M.x86.R_EDI + displacement;
}
} else {
int displacement = (s16)fetch_word_imm();
/* 16-bit addressing */
switch (rm) {
case 0:
DECODE_PRINTF2("%d[BX+SI]", displacement);
return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff;
case 1:
DECODE_PRINTF2("%d[BX+DI]", displacement);
return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff;
case 2:
DECODE_PRINTF2("%d[BP+SI]", displacement);
M.x86.mode |= SYSMODE_SEG_DS_SS;
return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff;
case 3:
DECODE_PRINTF2("%d[BP+DI]", displacement);
M.x86.mode |= SYSMODE_SEG_DS_SS;
return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff;
case 4:
DECODE_PRINTF2("%d[SI]", displacement);
return (M.x86.R_SI + displacement) & 0xffff;
case 5:
DECODE_PRINTF2("%d[DI]", displacement);
return (M.x86.R_DI + displacement) & 0xffff;
case 6:
DECODE_PRINTF2("%d[BP]", displacement);
M.x86.mode |= SYSMODE_SEG_DS_SS;
return (M.x86.R_BP + displacement) & 0xffff;
case 7:
DECODE_PRINTF2("%d[BX]", displacement);
return (M.x86.R_BX + displacement) & 0xffff;
}
}
HALT_SYS();
return 0; /* SHOULD NOT HAPPEN */
}
/****************************************************************************
PARAMETERS:
mod - modifier
rm - RM value to decode
RETURNS:
Offset in memory for the address decoding, multiplexing calls to
the decode_rmXX_address functions
REMARKS:
Return the offset given by "mod" addressing.
****************************************************************************/
unsigned decode_rmXX_address(int mod, int rm)
{
if(mod == 0)
return decode_rm00_address(rm);
if(mod == 1)
return decode_rm01_address(rm);
return decode_rm10_address(rm);
}
|
1001-study-uboot
|
drivers/bios_emulator/x86emu/decode.c
|
C
|
gpl3
| 31,431
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
* Jason Jin <Jason.jin@freescale.com>
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: This file includes subroutines to implement the decoding
* and emulation of all the x86 extended two-byte processor
* instructions.
*
****************************************************************************/
#include <common.h>
#include <linux/compiler.h>
#include "x86emu/x86emui.h"
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
PARAMETERS:
op1 - Instruction op code
REMARKS:
Handles illegal opcodes.
****************************************************************************/
void x86emuOp2_illegal_op(
u8 op2)
{
START_OF_INSTR();
DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
TRACE_REGS();
printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n",
M.x86.R_CS, M.x86.R_IP-2,op2);
HALT_SYS();
END_OF_INSTR();
}
#define xorl(a,b) ((a) && !(b)) || (!(a) && (b))
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0x80-0x8F
****************************************************************************/
int x86emu_check_jump_condition(u8 op)
{
switch (op) {
case 0x0:
DECODE_PRINTF("JO\t");
return ACCESS_FLAG(F_OF);
case 0x1:
DECODE_PRINTF("JNO\t");
return !ACCESS_FLAG(F_OF);
break;
case 0x2:
DECODE_PRINTF("JB\t");
return ACCESS_FLAG(F_CF);
break;
case 0x3:
DECODE_PRINTF("JNB\t");
return !ACCESS_FLAG(F_CF);
break;
case 0x4:
DECODE_PRINTF("JZ\t");
return ACCESS_FLAG(F_ZF);
break;
case 0x5:
DECODE_PRINTF("JNZ\t");
return !ACCESS_FLAG(F_ZF);
break;
case 0x6:
DECODE_PRINTF("JBE\t");
return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
break;
case 0x7:
DECODE_PRINTF("JNBE\t");
return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
break;
case 0x8:
DECODE_PRINTF("JS\t");
return ACCESS_FLAG(F_SF);
break;
case 0x9:
DECODE_PRINTF("JNS\t");
return !ACCESS_FLAG(F_SF);
break;
case 0xa:
DECODE_PRINTF("JP\t");
return ACCESS_FLAG(F_PF);
break;
case 0xb:
DECODE_PRINTF("JNP\t");
return !ACCESS_FLAG(F_PF);
break;
case 0xc:
DECODE_PRINTF("JL\t");
return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
break;
case 0xd:
DECODE_PRINTF("JNL\t");
return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
break;
case 0xe:
DECODE_PRINTF("JLE\t");
return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
ACCESS_FLAG(F_ZF));
break;
default:
DECODE_PRINTF("JNLE\t");
return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
ACCESS_FLAG(F_ZF));
}
}
void x86emuOp2_long_jump(u8 op2)
{
s32 target;
int cond;
/* conditional jump to word offset. */
START_OF_INSTR();
cond = x86emu_check_jump_condition(op2 & 0xF);
target = (s16) fetch_word_imm();
target += (s16) M.x86.R_IP;
DECODE_PRINTF2("%04x\n", target);
TRACE_AND_STEP();
if (cond)
M.x86.R_IP = (u16)target;
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0x90-0x9F
****************************************************************************/
void x86emuOp2_set_byte(u8 op2)
{
int mod, rl, rh;
uint destoffset;
u8 *destreg;
__maybe_unused char *name = 0;
int cond = 0;
START_OF_INSTR();
switch (op2) {
case 0x90:
name = "SETO\t";
cond = ACCESS_FLAG(F_OF);
break;
case 0x91:
name = "SETNO\t";
cond = !ACCESS_FLAG(F_OF);
break;
case 0x92:
name = "SETB\t";
cond = ACCESS_FLAG(F_CF);
break;
case 0x93:
name = "SETNB\t";
cond = !ACCESS_FLAG(F_CF);
break;
case 0x94:
name = "SETZ\t";
cond = ACCESS_FLAG(F_ZF);
break;
case 0x95:
name = "SETNZ\t";
cond = !ACCESS_FLAG(F_ZF);
break;
case 0x96:
name = "SETBE\t";
cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF);
break;
case 0x97:
name = "SETNBE\t";
cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF));
break;
case 0x98:
name = "SETS\t";
cond = ACCESS_FLAG(F_SF);
break;
case 0x99:
name = "SETNS\t";
cond = !ACCESS_FLAG(F_SF);
break;
case 0x9a:
name = "SETP\t";
cond = ACCESS_FLAG(F_PF);
break;
case 0x9b:
name = "SETNP\t";
cond = !ACCESS_FLAG(F_PF);
break;
case 0x9c:
name = "SETL\t";
cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
break;
case 0x9d:
name = "SETNL\t";
cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF));
break;
case 0x9e:
name = "SETLE\t";
cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
ACCESS_FLAG(F_ZF));
break;
case 0x9f:
name = "SETNLE\t";
cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) ||
ACCESS_FLAG(F_ZF));
break;
}
DECODE_PRINTF(name);
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
TRACE_AND_STEP();
store_data_byte(destoffset, cond ? 0x01 : 0x00);
} else { /* register to register */
destreg = DECODE_RM_BYTE_REGISTER(rl);
TRACE_AND_STEP();
*destreg = cond ? 0x01 : 0x00;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xa0
****************************************************************************/
void x86emuOp2_push_FS(u8 X86EMU_UNUSED(op2))
{
START_OF_INSTR();
DECODE_PRINTF("PUSH\tFS\n");
TRACE_AND_STEP();
push_word(M.x86.R_FS);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xa1
****************************************************************************/
void x86emuOp2_pop_FS(u8 X86EMU_UNUSED(op2))
{
START_OF_INSTR();
DECODE_PRINTF("POP\tFS\n");
TRACE_AND_STEP();
M.x86.R_FS = pop_word();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xa3
****************************************************************************/
void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
int bit,disp;
START_OF_INSTR();
DECODE_PRINTF("BT\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 srcval;
u32 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0x1F;
disp = (s16)*shiftreg >> 5;
srcval = fetch_data_long(srcoffset+disp);
CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
} else {
u16 srcval;
u16 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0xF;
disp = (s16)*shiftreg >> 4;
srcval = fetch_data_word(srcoffset+disp);
CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg,*shiftreg;
srcreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0x1F;
CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
} else {
u16 *srcreg,*shiftreg;
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0xF;
CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xa4
****************************************************************************/
void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint destoffset;
u8 shift;
START_OF_INSTR();
DECODE_PRINTF("SHLD\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
u32 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
shift = fetch_byte_imm();
DECODE_PRINTF2("%d\n", shift);
TRACE_AND_STEP();
destval = fetch_data_long(destoffset);
destval = shld_long(destval,*shiftreg,shift);
store_data_long(destoffset, destval);
} else {
u16 destval;
u16 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
shift = fetch_byte_imm();
DECODE_PRINTF2("%d\n", shift);
TRACE_AND_STEP();
destval = fetch_data_word(destoffset);
destval = shld_word(destval,*shiftreg,shift);
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*shiftreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
shift = fetch_byte_imm();
DECODE_PRINTF2("%d\n", shift);
TRACE_AND_STEP();
*destreg = shld_long(*destreg,*shiftreg,shift);
} else {
u16 *destreg,*shiftreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
shift = fetch_byte_imm();
DECODE_PRINTF2("%d\n", shift);
TRACE_AND_STEP();
*destreg = shld_word(*destreg,*shiftreg,shift);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xa5
****************************************************************************/
void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint destoffset;
START_OF_INSTR();
DECODE_PRINTF("SHLD\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
u32 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
destval = fetch_data_long(destoffset);
destval = shld_long(destval,*shiftreg,M.x86.R_CL);
store_data_long(destoffset, destval);
} else {
u16 destval;
u16 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
destval = fetch_data_word(destoffset);
destval = shld_word(destval,*shiftreg,M.x86.R_CL);
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*shiftreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
*destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL);
} else {
u16 *destreg,*shiftreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
*destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xa8
****************************************************************************/
void x86emuOp2_push_GS(u8 X86EMU_UNUSED(op2))
{
START_OF_INSTR();
DECODE_PRINTF("PUSH\tGS\n");
TRACE_AND_STEP();
push_word(M.x86.R_GS);
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xa9
****************************************************************************/
void x86emuOp2_pop_GS(u8 X86EMU_UNUSED(op2))
{
START_OF_INSTR();
DECODE_PRINTF("POP\tGS\n");
TRACE_AND_STEP();
M.x86.R_GS = pop_word();
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xaa
****************************************************************************/
void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
int bit,disp;
START_OF_INSTR();
DECODE_PRINTF("BTS\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 srcval,mask;
u32 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0x1F;
disp = (s16)*shiftreg >> 5;
srcval = fetch_data_long(srcoffset+disp);
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
store_data_long(srcoffset+disp, srcval | mask);
} else {
u16 srcval,mask;
u16 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0xF;
disp = (s16)*shiftreg >> 4;
srcval = fetch_data_word(srcoffset+disp);
mask = (u16)(0x1 << bit);
CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
store_data_word(srcoffset+disp, srcval | mask);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg,*shiftreg;
u32 mask;
srcreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0x1F;
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
*srcreg |= mask;
} else {
u16 *srcreg,*shiftreg;
u16 mask;
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0xF;
mask = (u16)(0x1 << bit);
CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
*srcreg |= mask;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xac
****************************************************************************/
void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint destoffset;
u8 shift;
START_OF_INSTR();
DECODE_PRINTF("SHLD\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
u32 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
shift = fetch_byte_imm();
DECODE_PRINTF2("%d\n", shift);
TRACE_AND_STEP();
destval = fetch_data_long(destoffset);
destval = shrd_long(destval,*shiftreg,shift);
store_data_long(destoffset, destval);
} else {
u16 destval;
u16 *shiftreg;
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
shift = fetch_byte_imm();
DECODE_PRINTF2("%d\n", shift);
TRACE_AND_STEP();
destval = fetch_data_word(destoffset);
destval = shrd_word(destval,*shiftreg,shift);
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*shiftreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
shift = fetch_byte_imm();
DECODE_PRINTF2("%d\n", shift);
TRACE_AND_STEP();
*destreg = shrd_long(*destreg,*shiftreg,shift);
} else {
u16 *destreg,*shiftreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
shift = fetch_byte_imm();
DECODE_PRINTF2("%d\n", shift);
TRACE_AND_STEP();
*destreg = shrd_word(*destreg,*shiftreg,shift);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xad
****************************************************************************/
void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint destoffset;
START_OF_INSTR();
DECODE_PRINTF("SHLD\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 destval;
u32 *shiftreg;
shiftreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
destval = fetch_data_long(destoffset);
destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
store_data_long(destoffset, destval);
} else {
u16 destval;
u16 *shiftreg;
shiftreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
destval = fetch_data_word(destoffset);
destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
store_data_word(destoffset, destval);
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*shiftreg;
destreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
*destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL);
} else {
u16 *destreg,*shiftreg;
destreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",CL\n");
TRACE_AND_STEP();
*destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xaf
****************************************************************************/
void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("IMUL\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 srcval;
u32 res_lo,res_hi;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = fetch_data_long(srcoffset);
TRACE_AND_STEP();
imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
if (res_hi != 0) {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
} else {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
}
*destreg = (u32)res_lo;
} else {
u16 *destreg;
u16 srcval;
u32 res;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = fetch_data_word(srcoffset);
TRACE_AND_STEP();
res = (s16)*destreg * (s16)srcval;
if (res > 0xFFFF) {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
} else {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
}
*destreg = (u16)res;
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg,*srcreg;
u32 res_lo,res_hi;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_LONG_REGISTER(rl);
TRACE_AND_STEP();
imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg);
if (res_hi != 0) {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
} else {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
}
*destreg = (u32)res_lo;
} else {
u16 *destreg,*srcreg;
u32 res;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rl);
res = (s16)*destreg * (s16)*srcreg;
if (res > 0xFFFF) {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
} else {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
}
*destreg = (u16)res;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xb2
****************************************************************************/
void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2))
{
int mod, rh, rl;
u16 *dstreg;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("LSS\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
dstreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*dstreg = fetch_data_word(srcoffset);
M.x86.R_SS = fetch_data_word(srcoffset + 2);
} else { /* register to register */
/* UNDEFINED! */
TRACE_AND_STEP();
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xb3
****************************************************************************/
void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
int bit,disp;
START_OF_INSTR();
DECODE_PRINTF("BTR\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 srcval,mask;
u32 *shiftreg;
shiftreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0x1F;
disp = (s16)*shiftreg >> 5;
srcval = fetch_data_long(srcoffset+disp);
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
store_data_long(srcoffset+disp, srcval & ~mask);
} else {
u16 srcval,mask;
u16 *shiftreg;
shiftreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0xF;
disp = (s16)*shiftreg >> 4;
srcval = fetch_data_word(srcoffset+disp);
mask = (u16)(0x1 << bit);
CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg,*shiftreg;
u32 mask;
srcreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0x1F;
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
*srcreg &= ~mask;
} else {
u16 *srcreg,*shiftreg;
u16 mask;
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0xF;
mask = (u16)(0x1 << bit);
CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
*srcreg &= ~mask;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xb4
****************************************************************************/
void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2))
{
int mod, rh, rl;
u16 *dstreg;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("LFS\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
dstreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*dstreg = fetch_data_word(srcoffset);
M.x86.R_FS = fetch_data_word(srcoffset + 2);
} else { /* register to register */
/* UNDEFINED! */
TRACE_AND_STEP();
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xb5
****************************************************************************/
void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2))
{
int mod, rh, rl;
u16 *dstreg;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("LGS\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
dstreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*dstreg = fetch_data_word(srcoffset);
M.x86.R_GS = fetch_data_word(srcoffset + 2);
} else { /* register to register */
/* UNDEFINED! */
TRACE_AND_STEP();
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xb6
****************************************************************************/
void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("MOVZX\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 srcval;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = fetch_data_byte(srcoffset);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
} else {
u16 *destreg;
u16 srcval;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = fetch_data_byte(srcoffset);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u8 *srcreg;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
} else {
u16 *destreg;
u8 *srcreg;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xb7
****************************************************************************/
void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
u32 *destreg;
u32 srcval;
u16 *srcreg;
START_OF_INSTR();
DECODE_PRINTF("MOVZX\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = fetch_data_word(srcoffset);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
} else { /* register to register */
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = *srcreg;
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xba
****************************************************************************/
void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
u8 shift;
int bit;
START_OF_INSTR();
FETCH_DECODE_MODRM(mod, rh, rl);
switch (rh) {
case 4:
DECODE_PRINTF("BT\t");
break;
case 5:
DECODE_PRINTF("BTS\t");
break;
case 6:
DECODE_PRINTF("BTR\t");
break;
case 7:
DECODE_PRINTF("BTC\t");
break;
default:
DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n");
TRACE_REGS();
printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n",
M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl);
HALT_SYS();
}
if (mod < 3) {
srcoffset = decode_rmXX_address(mod, rl);
shift = fetch_byte_imm();
DECODE_PRINTF2(",%d\n", shift);
TRACE_AND_STEP();
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 srcval, mask;
bit = shift & 0x1F;
srcval = fetch_data_long(srcoffset);
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
switch (rh) {
case 5:
store_data_long(srcoffset, srcval | mask);
break;
case 6:
store_data_long(srcoffset, srcval & ~mask);
break;
case 7:
store_data_long(srcoffset, srcval ^ mask);
break;
default:
break;
}
} else {
u16 srcval, mask;
bit = shift & 0xF;
srcval = fetch_data_word(srcoffset);
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
switch (rh) {
case 5:
store_data_word(srcoffset, srcval | mask);
break;
case 6:
store_data_word(srcoffset, srcval & ~mask);
break;
case 7:
store_data_word(srcoffset, srcval ^ mask);
break;
default:
break;
}
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg;
u32 mask;
srcreg = DECODE_RM_LONG_REGISTER(rl);
shift = fetch_byte_imm();
DECODE_PRINTF2(",%d\n", shift);
TRACE_AND_STEP();
bit = shift & 0x1F;
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
switch (rh) {
case 5:
*srcreg |= mask;
break;
case 6:
*srcreg &= ~mask;
break;
case 7:
*srcreg ^= mask;
break;
default:
break;
}
} else {
u16 *srcreg;
u16 mask;
srcreg = DECODE_RM_WORD_REGISTER(rl);
shift = fetch_byte_imm();
DECODE_PRINTF2(",%d\n", shift);
TRACE_AND_STEP();
bit = shift & 0xF;
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
switch (rh) {
case 5:
*srcreg |= mask;
break;
case 6:
*srcreg &= ~mask;
break;
case 7:
*srcreg ^= mask;
break;
default:
break;
}
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xbb
****************************************************************************/
void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
int bit,disp;
START_OF_INSTR();
DECODE_PRINTF("BTC\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 srcval,mask;
u32 *shiftreg;
shiftreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0x1F;
disp = (s16)*shiftreg >> 5;
srcval = fetch_data_long(srcoffset+disp);
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
store_data_long(srcoffset+disp, srcval ^ mask);
} else {
u16 srcval,mask;
u16 *shiftreg;
shiftreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0xF;
disp = (s16)*shiftreg >> 4;
srcval = fetch_data_word(srcoffset+disp);
mask = (u16)(0x1 << bit);
CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
store_data_word(srcoffset+disp, (u16)(srcval ^ mask));
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg,*shiftreg;
u32 mask;
srcreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0x1F;
mask = (0x1 << bit);
CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
*srcreg ^= mask;
} else {
u16 *srcreg,*shiftreg;
u16 mask;
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
shiftreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
bit = *shiftreg & 0xF;
mask = (u16)(0x1 << bit);
CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
*srcreg ^= mask;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xbc
****************************************************************************/
void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("BSF\n");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 srcval, *dstreg;
dstreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
srcval = fetch_data_long(srcoffset);
CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
if ((srcval >> *dstreg) & 1) break;
} else {
u16 srcval, *dstreg;
dstreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
srcval = fetch_data_word(srcoffset);
CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
if ((srcval >> *dstreg) & 1) break;
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg, *dstreg;
srcreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
dstreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
for(*dstreg = 0; *dstreg < 32; (*dstreg)++)
if ((*srcreg >> *dstreg) & 1) break;
} else {
u16 *srcreg, *dstreg;
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
dstreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
for(*dstreg = 0; *dstreg < 16; (*dstreg)++)
if ((*srcreg >> *dstreg) & 1) break;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xbd
****************************************************************************/
void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("BSF\n");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
srcoffset = decode_rmXX_address(mod, rl);
DECODE_PRINTF(",");
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 srcval, *dstreg;
dstreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
srcval = fetch_data_long(srcoffset);
CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
if ((srcval >> *dstreg) & 1) break;
} else {
u16 srcval, *dstreg;
dstreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
srcval = fetch_data_word(srcoffset);
CONDITIONAL_SET_FLAG(srcval == 0, F_ZF);
for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
if ((srcval >> *dstreg) & 1) break;
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *srcreg, *dstreg;
srcreg = DECODE_RM_LONG_REGISTER(rl);
DECODE_PRINTF(",");
dstreg = DECODE_RM_LONG_REGISTER(rh);
TRACE_AND_STEP();
CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
for(*dstreg = 31; *dstreg > 0; (*dstreg)--)
if ((*srcreg >> *dstreg) & 1) break;
} else {
u16 *srcreg, *dstreg;
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF(",");
dstreg = DECODE_RM_WORD_REGISTER(rh);
TRACE_AND_STEP();
CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF);
for(*dstreg = 15; *dstreg > 0; (*dstreg)--)
if ((*srcreg >> *dstreg) & 1) break;
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xbe
****************************************************************************/
void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
START_OF_INSTR();
DECODE_PRINTF("MOVSX\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u32 srcval;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = (s32)((s8)fetch_data_byte(srcoffset));
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
} else {
u16 *destreg;
u16 srcval;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = (s16)((s8)fetch_data_byte(srcoffset));
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
}
} else { /* register to register */
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
u32 *destreg;
u8 *srcreg;
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = (s32)((s8)*srcreg);
} else {
u16 *destreg;
u8 *srcreg;
destreg = DECODE_RM_WORD_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_BYTE_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = (s16)((s8)*srcreg);
}
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xbf
****************************************************************************/
void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2))
{
int mod, rl, rh;
uint srcoffset;
u32 *destreg;
u32 srcval;
u16 *srcreg;
START_OF_INSTR();
DECODE_PRINTF("MOVSX\t");
FETCH_DECODE_MODRM(mod, rh, rl);
if (mod < 3) {
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcoffset = decode_rmXX_address(mod, rl);
srcval = (s32)((s16)fetch_data_word(srcoffset));
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = srcval;
} else { /* register to register */
destreg = DECODE_RM_LONG_REGISTER(rh);
DECODE_PRINTF(",");
srcreg = DECODE_RM_WORD_REGISTER(rl);
DECODE_PRINTF("\n");
TRACE_AND_STEP();
*destreg = (s32)((s16)*srcreg);
}
DECODE_CLEAR_SEGOVR();
END_OF_INSTR();
}
/***************************************************************************
* Double byte operation code table:
**************************************************************************/
void (*x86emu_optab2[256])(u8) =
{
/* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */
/* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */
/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */
/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */
/* 0x04 */ x86emuOp2_illegal_op,
/* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */
/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */
/* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */
/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */
/* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */
/* 0x0a */ x86emuOp2_illegal_op,
/* 0x0b */ x86emuOp2_illegal_op,
/* 0x0c */ x86emuOp2_illegal_op,
/* 0x0d */ x86emuOp2_illegal_op,
/* 0x0e */ x86emuOp2_illegal_op,
/* 0x0f */ x86emuOp2_illegal_op,
/* 0x10 */ x86emuOp2_illegal_op,
/* 0x11 */ x86emuOp2_illegal_op,
/* 0x12 */ x86emuOp2_illegal_op,
/* 0x13 */ x86emuOp2_illegal_op,
/* 0x14 */ x86emuOp2_illegal_op,
/* 0x15 */ x86emuOp2_illegal_op,
/* 0x16 */ x86emuOp2_illegal_op,
/* 0x17 */ x86emuOp2_illegal_op,
/* 0x18 */ x86emuOp2_illegal_op,
/* 0x19 */ x86emuOp2_illegal_op,
/* 0x1a */ x86emuOp2_illegal_op,
/* 0x1b */ x86emuOp2_illegal_op,
/* 0x1c */ x86emuOp2_illegal_op,
/* 0x1d */ x86emuOp2_illegal_op,
/* 0x1e */ x86emuOp2_illegal_op,
/* 0x1f */ x86emuOp2_illegal_op,
/* 0x20 */ x86emuOp2_illegal_op, /* mov reg32,creg (ring 0 PM) */
/* 0x21 */ x86emuOp2_illegal_op, /* mov reg32,dreg (ring 0 PM) */
/* 0x22 */ x86emuOp2_illegal_op, /* mov creg,reg32 (ring 0 PM) */
/* 0x23 */ x86emuOp2_illegal_op, /* mov dreg,reg32 (ring 0 PM) */
/* 0x24 */ x86emuOp2_illegal_op, /* mov reg32,treg (ring 0 PM) */
/* 0x25 */ x86emuOp2_illegal_op,
/* 0x26 */ x86emuOp2_illegal_op, /* mov treg,reg32 (ring 0 PM) */
/* 0x27 */ x86emuOp2_illegal_op,
/* 0x28 */ x86emuOp2_illegal_op,
/* 0x29 */ x86emuOp2_illegal_op,
/* 0x2a */ x86emuOp2_illegal_op,
/* 0x2b */ x86emuOp2_illegal_op,
/* 0x2c */ x86emuOp2_illegal_op,
/* 0x2d */ x86emuOp2_illegal_op,
/* 0x2e */ x86emuOp2_illegal_op,
/* 0x2f */ x86emuOp2_illegal_op,
/* 0x30 */ x86emuOp2_illegal_op,
/* 0x31 */ x86emuOp2_illegal_op,
/* 0x32 */ x86emuOp2_illegal_op,
/* 0x33 */ x86emuOp2_illegal_op,
/* 0x34 */ x86emuOp2_illegal_op,
/* 0x35 */ x86emuOp2_illegal_op,
/* 0x36 */ x86emuOp2_illegal_op,
/* 0x37 */ x86emuOp2_illegal_op,
/* 0x38 */ x86emuOp2_illegal_op,
/* 0x39 */ x86emuOp2_illegal_op,
/* 0x3a */ x86emuOp2_illegal_op,
/* 0x3b */ x86emuOp2_illegal_op,
/* 0x3c */ x86emuOp2_illegal_op,
/* 0x3d */ x86emuOp2_illegal_op,
/* 0x3e */ x86emuOp2_illegal_op,
/* 0x3f */ x86emuOp2_illegal_op,
/* 0x40 */ x86emuOp2_illegal_op,
/* 0x41 */ x86emuOp2_illegal_op,
/* 0x42 */ x86emuOp2_illegal_op,
/* 0x43 */ x86emuOp2_illegal_op,
/* 0x44 */ x86emuOp2_illegal_op,
/* 0x45 */ x86emuOp2_illegal_op,
/* 0x46 */ x86emuOp2_illegal_op,
/* 0x47 */ x86emuOp2_illegal_op,
/* 0x48 */ x86emuOp2_illegal_op,
/* 0x49 */ x86emuOp2_illegal_op,
/* 0x4a */ x86emuOp2_illegal_op,
/* 0x4b */ x86emuOp2_illegal_op,
/* 0x4c */ x86emuOp2_illegal_op,
/* 0x4d */ x86emuOp2_illegal_op,
/* 0x4e */ x86emuOp2_illegal_op,
/* 0x4f */ x86emuOp2_illegal_op,
/* 0x50 */ x86emuOp2_illegal_op,
/* 0x51 */ x86emuOp2_illegal_op,
/* 0x52 */ x86emuOp2_illegal_op,
/* 0x53 */ x86emuOp2_illegal_op,
/* 0x54 */ x86emuOp2_illegal_op,
/* 0x55 */ x86emuOp2_illegal_op,
/* 0x56 */ x86emuOp2_illegal_op,
/* 0x57 */ x86emuOp2_illegal_op,
/* 0x58 */ x86emuOp2_illegal_op,
/* 0x59 */ x86emuOp2_illegal_op,
/* 0x5a */ x86emuOp2_illegal_op,
/* 0x5b */ x86emuOp2_illegal_op,
/* 0x5c */ x86emuOp2_illegal_op,
/* 0x5d */ x86emuOp2_illegal_op,
/* 0x5e */ x86emuOp2_illegal_op,
/* 0x5f */ x86emuOp2_illegal_op,
/* 0x60 */ x86emuOp2_illegal_op,
/* 0x61 */ x86emuOp2_illegal_op,
/* 0x62 */ x86emuOp2_illegal_op,
/* 0x63 */ x86emuOp2_illegal_op,
/* 0x64 */ x86emuOp2_illegal_op,
/* 0x65 */ x86emuOp2_illegal_op,
/* 0x66 */ x86emuOp2_illegal_op,
/* 0x67 */ x86emuOp2_illegal_op,
/* 0x68 */ x86emuOp2_illegal_op,
/* 0x69 */ x86emuOp2_illegal_op,
/* 0x6a */ x86emuOp2_illegal_op,
/* 0x6b */ x86emuOp2_illegal_op,
/* 0x6c */ x86emuOp2_illegal_op,
/* 0x6d */ x86emuOp2_illegal_op,
/* 0x6e */ x86emuOp2_illegal_op,
/* 0x6f */ x86emuOp2_illegal_op,
/* 0x70 */ x86emuOp2_illegal_op,
/* 0x71 */ x86emuOp2_illegal_op,
/* 0x72 */ x86emuOp2_illegal_op,
/* 0x73 */ x86emuOp2_illegal_op,
/* 0x74 */ x86emuOp2_illegal_op,
/* 0x75 */ x86emuOp2_illegal_op,
/* 0x76 */ x86emuOp2_illegal_op,
/* 0x77 */ x86emuOp2_illegal_op,
/* 0x78 */ x86emuOp2_illegal_op,
/* 0x79 */ x86emuOp2_illegal_op,
/* 0x7a */ x86emuOp2_illegal_op,
/* 0x7b */ x86emuOp2_illegal_op,
/* 0x7c */ x86emuOp2_illegal_op,
/* 0x7d */ x86emuOp2_illegal_op,
/* 0x7e */ x86emuOp2_illegal_op,
/* 0x7f */ x86emuOp2_illegal_op,
/* 0x80 */ x86emuOp2_long_jump,
/* 0x81 */ x86emuOp2_long_jump,
/* 0x82 */ x86emuOp2_long_jump,
/* 0x83 */ x86emuOp2_long_jump,
/* 0x84 */ x86emuOp2_long_jump,
/* 0x85 */ x86emuOp2_long_jump,
/* 0x86 */ x86emuOp2_long_jump,
/* 0x87 */ x86emuOp2_long_jump,
/* 0x88 */ x86emuOp2_long_jump,
/* 0x89 */ x86emuOp2_long_jump,
/* 0x8a */ x86emuOp2_long_jump,
/* 0x8b */ x86emuOp2_long_jump,
/* 0x8c */ x86emuOp2_long_jump,
/* 0x8d */ x86emuOp2_long_jump,
/* 0x8e */ x86emuOp2_long_jump,
/* 0x8f */ x86emuOp2_long_jump,
/* 0x90 */ x86emuOp2_set_byte,
/* 0x91 */ x86emuOp2_set_byte,
/* 0x92 */ x86emuOp2_set_byte,
/* 0x93 */ x86emuOp2_set_byte,
/* 0x94 */ x86emuOp2_set_byte,
/* 0x95 */ x86emuOp2_set_byte,
/* 0x96 */ x86emuOp2_set_byte,
/* 0x97 */ x86emuOp2_set_byte,
/* 0x98 */ x86emuOp2_set_byte,
/* 0x99 */ x86emuOp2_set_byte,
/* 0x9a */ x86emuOp2_set_byte,
/* 0x9b */ x86emuOp2_set_byte,
/* 0x9c */ x86emuOp2_set_byte,
/* 0x9d */ x86emuOp2_set_byte,
/* 0x9e */ x86emuOp2_set_byte,
/* 0x9f */ x86emuOp2_set_byte,
/* 0xa0 */ x86emuOp2_push_FS,
/* 0xa1 */ x86emuOp2_pop_FS,
/* 0xa2 */ x86emuOp2_illegal_op,
/* 0xa3 */ x86emuOp2_bt_R,
/* 0xa4 */ x86emuOp2_shld_IMM,
/* 0xa5 */ x86emuOp2_shld_CL,
/* 0xa6 */ x86emuOp2_illegal_op,
/* 0xa7 */ x86emuOp2_illegal_op,
/* 0xa8 */ x86emuOp2_push_GS,
/* 0xa9 */ x86emuOp2_pop_GS,
/* 0xaa */ x86emuOp2_illegal_op,
/* 0xab */ x86emuOp2_bt_R,
/* 0xac */ x86emuOp2_shrd_IMM,
/* 0xad */ x86emuOp2_shrd_CL,
/* 0xae */ x86emuOp2_illegal_op,
/* 0xaf */ x86emuOp2_imul_R_RM,
/* 0xb0 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */
/* 0xb1 */ x86emuOp2_illegal_op, /* TODO: cmpxchg */
/* 0xb2 */ x86emuOp2_lss_R_IMM,
/* 0xb3 */ x86emuOp2_btr_R,
/* 0xb4 */ x86emuOp2_lfs_R_IMM,
/* 0xb5 */ x86emuOp2_lgs_R_IMM,
/* 0xb6 */ x86emuOp2_movzx_byte_R_RM,
/* 0xb7 */ x86emuOp2_movzx_word_R_RM,
/* 0xb8 */ x86emuOp2_illegal_op,
/* 0xb9 */ x86emuOp2_illegal_op,
/* 0xba */ x86emuOp2_btX_I,
/* 0xbb */ x86emuOp2_btc_R,
/* 0xbc */ x86emuOp2_bsf,
/* 0xbd */ x86emuOp2_bsr,
/* 0xbe */ x86emuOp2_movsx_byte_R_RM,
/* 0xbf */ x86emuOp2_movsx_word_R_RM,
/* 0xc0 */ x86emuOp2_illegal_op, /* TODO: xadd */
/* 0xc1 */ x86emuOp2_illegal_op, /* TODO: xadd */
/* 0xc2 */ x86emuOp2_illegal_op,
/* 0xc3 */ x86emuOp2_illegal_op,
/* 0xc4 */ x86emuOp2_illegal_op,
/* 0xc5 */ x86emuOp2_illegal_op,
/* 0xc6 */ x86emuOp2_illegal_op,
/* 0xc7 */ x86emuOp2_illegal_op,
/* 0xc8 */ x86emuOp2_illegal_op, /* TODO: bswap */
/* 0xc9 */ x86emuOp2_illegal_op, /* TODO: bswap */
/* 0xca */ x86emuOp2_illegal_op, /* TODO: bswap */
/* 0xcb */ x86emuOp2_illegal_op, /* TODO: bswap */
/* 0xcc */ x86emuOp2_illegal_op, /* TODO: bswap */
/* 0xcd */ x86emuOp2_illegal_op, /* TODO: bswap */
/* 0xce */ x86emuOp2_illegal_op, /* TODO: bswap */
/* 0xcf */ x86emuOp2_illegal_op, /* TODO: bswap */
/* 0xd0 */ x86emuOp2_illegal_op,
/* 0xd1 */ x86emuOp2_illegal_op,
/* 0xd2 */ x86emuOp2_illegal_op,
/* 0xd3 */ x86emuOp2_illegal_op,
/* 0xd4 */ x86emuOp2_illegal_op,
/* 0xd5 */ x86emuOp2_illegal_op,
/* 0xd6 */ x86emuOp2_illegal_op,
/* 0xd7 */ x86emuOp2_illegal_op,
/* 0xd8 */ x86emuOp2_illegal_op,
/* 0xd9 */ x86emuOp2_illegal_op,
/* 0xda */ x86emuOp2_illegal_op,
/* 0xdb */ x86emuOp2_illegal_op,
/* 0xdc */ x86emuOp2_illegal_op,
/* 0xdd */ x86emuOp2_illegal_op,
/* 0xde */ x86emuOp2_illegal_op,
/* 0xdf */ x86emuOp2_illegal_op,
/* 0xe0 */ x86emuOp2_illegal_op,
/* 0xe1 */ x86emuOp2_illegal_op,
/* 0xe2 */ x86emuOp2_illegal_op,
/* 0xe3 */ x86emuOp2_illegal_op,
/* 0xe4 */ x86emuOp2_illegal_op,
/* 0xe5 */ x86emuOp2_illegal_op,
/* 0xe6 */ x86emuOp2_illegal_op,
/* 0xe7 */ x86emuOp2_illegal_op,
/* 0xe8 */ x86emuOp2_illegal_op,
/* 0xe9 */ x86emuOp2_illegal_op,
/* 0xea */ x86emuOp2_illegal_op,
/* 0xeb */ x86emuOp2_illegal_op,
/* 0xec */ x86emuOp2_illegal_op,
/* 0xed */ x86emuOp2_illegal_op,
/* 0xee */ x86emuOp2_illegal_op,
/* 0xef */ x86emuOp2_illegal_op,
/* 0xf0 */ x86emuOp2_illegal_op,
/* 0xf1 */ x86emuOp2_illegal_op,
/* 0xf2 */ x86emuOp2_illegal_op,
/* 0xf3 */ x86emuOp2_illegal_op,
/* 0xf4 */ x86emuOp2_illegal_op,
/* 0xf5 */ x86emuOp2_illegal_op,
/* 0xf6 */ x86emuOp2_illegal_op,
/* 0xf7 */ x86emuOp2_illegal_op,
/* 0xf8 */ x86emuOp2_illegal_op,
/* 0xf9 */ x86emuOp2_illegal_op,
/* 0xfa */ x86emuOp2_illegal_op,
/* 0xfb */ x86emuOp2_illegal_op,
/* 0xfc */ x86emuOp2_illegal_op,
/* 0xfd */ x86emuOp2_illegal_op,
/* 0xfe */ x86emuOp2_illegal_op,
/* 0xff */ x86emuOp2_illegal_op,
};
|
1001-study-uboot
|
drivers/bios_emulator/x86emu/ops2.c
|
C
|
gpl3
| 49,129
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: This file includes subroutines which are related to
* programmed I/O and memory access. Included in this module
* are default functions that do nothing. For real uses these
* functions will have to be overriden by the user library.
*
****************************************************************************/
#include <common.h>
#include "x86emu/x86emui.h"
/*------------------------- Global Variables ------------------------------*/
X86EMU_sysEnv _X86EMU_env; /* Global emulator machine state */
X86EMU_intrFuncs _X86EMU_intrTab[256];
int debug_intr;
/*----------------------------- Implementation ----------------------------*/
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Byte value read from emulator memory.
REMARKS:
Reads a byte value from the emulator memory.
****************************************************************************/
u8 X86API rdb(u32 addr)
{
return 0;
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Word value read from emulator memory.
REMARKS:
Reads a word value from the emulator memory.
****************************************************************************/
u16 X86API rdw(u32 addr)
{
return 0;
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
RETURNS:
Long value read from emulator memory.
REMARKS:
Reads a long value from the emulator memory.
****************************************************************************/
u32 X86API rdl(u32 addr)
{
return 0;
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
val - Value to store
REMARKS:
Writes a byte value to emulator memory.
****************************************************************************/
void X86API wrb(u32 addr, u8 val)
{
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
val - Value to store
REMARKS:
Writes a word value to emulator memory.
****************************************************************************/
void X86API wrw(u32 addr, u16 val)
{
}
/****************************************************************************
PARAMETERS:
addr - Emulator memory address to read
val - Value to store
REMARKS:
Writes a long value to emulator memory.
****************************************************************************/
void X86API wrl(u32 addr, u32 val)
{
}
/****************************************************************************
PARAMETERS:
addr - PIO address to read
RETURN:
0
REMARKS:
Default PIO byte read function. Doesn't perform real inb.
****************************************************************************/
static u8 X86API p_inb(X86EMU_pioAddr addr)
{
DB(if (DEBUG_IO_TRACE())
printk("inb %#04x \n", addr);)
return 0;
}
/****************************************************************************
PARAMETERS:
addr - PIO address to read
RETURN:
0
REMARKS:
Default PIO word read function. Doesn't perform real inw.
****************************************************************************/
static u16 X86API p_inw(X86EMU_pioAddr addr)
{
DB(if (DEBUG_IO_TRACE())
printk("inw %#04x \n", addr);)
return 0;
}
/****************************************************************************
PARAMETERS:
addr - PIO address to read
RETURN:
0
REMARKS:
Default PIO long read function. Doesn't perform real inl.
****************************************************************************/
static u32 X86API p_inl(X86EMU_pioAddr addr)
{
DB(if (DEBUG_IO_TRACE())
printk("inl %#04x \n", addr);)
return 0;
}
/****************************************************************************
PARAMETERS:
addr - PIO address to write
val - Value to store
REMARKS:
Default PIO byte write function. Doesn't perform real outb.
****************************************************************************/
static void X86API p_outb(X86EMU_pioAddr addr, u8 val)
{
DB(if (DEBUG_IO_TRACE())
printk("outb %#02x -> %#04x \n", val, addr);)
return;
}
/****************************************************************************
PARAMETERS:
addr - PIO address to write
val - Value to store
REMARKS:
Default PIO word write function. Doesn't perform real outw.
****************************************************************************/
static void X86API p_outw(X86EMU_pioAddr addr, u16 val)
{
DB(if (DEBUG_IO_TRACE())
printk("outw %#04x -> %#04x \n", val, addr);)
return;
}
/****************************************************************************
PARAMETERS:
addr - PIO address to write
val - Value to store
REMARKS:
Default PIO ;ong write function. Doesn't perform real outl.
****************************************************************************/
static void X86API p_outl(X86EMU_pioAddr addr, u32 val)
{
DB(if (DEBUG_IO_TRACE())
printk("outl %#08x -> %#04x \n", val, addr);)
return;
}
/*------------------------- Global Variables ------------------------------*/
u8(X86APIP sys_rdb) (u32 addr) = rdb;
u16(X86APIP sys_rdw) (u32 addr) = rdw;
u32(X86APIP sys_rdl) (u32 addr) = rdl;
void (X86APIP sys_wrb) (u32 addr, u8 val) = wrb;
void (X86APIP sys_wrw) (u32 addr, u16 val) = wrw;
void (X86APIP sys_wrl) (u32 addr, u32 val) = wrl;
u8(X86APIP sys_inb) (X86EMU_pioAddr addr) = p_inb;
u16(X86APIP sys_inw) (X86EMU_pioAddr addr) = p_inw;
u32(X86APIP sys_inl) (X86EMU_pioAddr addr) = p_inl;
void (X86APIP sys_outb) (X86EMU_pioAddr addr, u8 val) = p_outb;
void (X86APIP sys_outw) (X86EMU_pioAddr addr, u16 val) = p_outw;
void (X86APIP sys_outl) (X86EMU_pioAddr addr, u32 val) = p_outl;
/*----------------------------- Setup -------------------------------------*/
/****************************************************************************
PARAMETERS:
funcs - New memory function pointers to make active
REMARKS:
This function is used to set the pointers to functions which access
memory space, allowing the user application to override these functions
and hook them out as necessary for their application.
****************************************************************************/
void X86EMU_setupMemFuncs(X86EMU_memFuncs * funcs)
{
sys_rdb = funcs->rdb;
sys_rdw = funcs->rdw;
sys_rdl = funcs->rdl;
sys_wrb = funcs->wrb;
sys_wrw = funcs->wrw;
sys_wrl = funcs->wrl;
}
/****************************************************************************
PARAMETERS:
funcs - New programmed I/O function pointers to make active
REMARKS:
This function is used to set the pointers to functions which access
I/O space, allowing the user application to override these functions
and hook them out as necessary for their application.
****************************************************************************/
void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs)
{
sys_inb = funcs->inb;
sys_inw = funcs->inw;
sys_inl = funcs->inl;
sys_outb = funcs->outb;
sys_outw = funcs->outw;
sys_outl = funcs->outl;
}
/****************************************************************************
PARAMETERS:
funcs - New interrupt vector table to make active
REMARKS:
This function is used to set the pointers to functions which handle
interrupt processing in the emulator, allowing the user application to
hook interrupts as necessary for their application. Any interrupts that
are not hooked by the user application, and reflected and handled internally
in the emulator via the interrupt vector table. This allows the application
to get control when the code being emulated executes specific software
interrupts.
****************************************************************************/
void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[])
{
int i;
for (i = 0; i < 256; i++)
_X86EMU_intrTab[i] = NULL;
if (funcs) {
for (i = 0; i < 256; i++)
_X86EMU_intrTab[i] = funcs[i];
}
}
/****************************************************************************
PARAMETERS:
int - New software interrupt to prepare for
REMARKS:
This function is used to set up the emulator state to exceute a software
interrupt. This can be used by the user application code to allow an
interrupt to be hooked, examined and then reflected back to the emulator
so that the code in the emulator will continue processing the software
interrupt as per normal. This essentially allows system code to actively
hook and handle certain software interrupts as necessary.
****************************************************************************/
void X86EMU_prepareForInt(int num)
{
push_word((u16) M.x86.R_FLG);
CLEAR_FLAG(F_IF);
CLEAR_FLAG(F_TF);
push_word(M.x86.R_CS);
M.x86.R_CS = mem_access_word(num * 4 + 2);
push_word(M.x86.R_IP);
M.x86.R_IP = mem_access_word(num * 4);
M.x86.intr = 0;
}
|
1001-study-uboot
|
drivers/bios_emulator/x86emu/sys.c
|
C
|
gpl3
| 10,694
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: This file contains the code to implement the primitive
* machine operations used by the emulation code in ops.c
*
* Carry Chain Calculation
*
* This represents a somewhat expensive calculation which is
* apparently required to emulate the setting of the OF343364 and AF flag.
* The latter is not so important, but the former is. The overflow
* flag is the XOR of the top two bits of the carry chain for an
* addition (similar for subtraction). Since we do not want to
* simulate the addition in a bitwise manner, we try to calculate the
* carry chain given the two operands and the result.
*
* So, given the following table, which represents the addition of two
* bits, we can derive a formula for the carry chain.
*
* a b cin r cout
* 0 0 0 0 0
* 0 0 1 1 0
* 0 1 0 1 0
* 0 1 1 0 1
* 1 0 0 1 0
* 1 0 1 0 1
* 1 1 0 0 1
* 1 1 1 1 1
*
* Construction of table for cout:
*
* ab
* r \ 00 01 11 10
* |------------------
* 0 | 0 1 1 1
* 1 | 0 0 1 0
*
* By inspection, one gets: cc = ab + r'(a + b)
*
* That represents alot of operations, but NO CHOICE....
*
* Borrow Chain Calculation.
*
* The following table represents the subtraction of two bits, from
* which we can derive a formula for the borrow chain.
*
* a b bin r bout
* 0 0 0 0 0
* 0 0 1 1 1
* 0 1 0 1 1
* 0 1 1 0 1
* 1 0 0 1 0
* 1 0 1 0 0
* 1 1 0 0 0
* 1 1 1 1 1
*
* Construction of table for cout:
*
* ab
* r \ 00 01 11 10
* |------------------
* 0 | 0 1 0 0
* 1 | 1 1 1 0
*
* By inspection, one gets: bc = a'b + r(a' + b)
*
****************************************************************************/
#include <common.h>
#define PRIM_OPS_NO_REDEFINE_ASM
#include "x86emu/x86emui.h"
/*------------------------- Global Variables ------------------------------*/
static u32 x86emu_parity_tab[8] =
{
0x96696996,
0x69969669,
0x69969669,
0x96696996,
0x69969669,
0x96696996,
0x96696996,
0x69969669,
};
#define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0)
#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1)
/*----------------------------- Implementation ----------------------------*/
int abs(int v)
{
return (v>0)?v:-v;
}
/*----------------------------- Implementation ----------------------------*/
/*--------- Side effects helper functions -------*/
/****************************************************************************
REMARKS:
implements side efects for byte operations that don't overflow
****************************************************************************/
static void set_parity_flag(u32 res)
{
CONDITIONAL_SET_FLAG(PARITY(res & 0xFF), F_PF);
}
static void set_szp_flags_8(u8 res)
{
CONDITIONAL_SET_FLAG(res & 0x80, F_SF);
CONDITIONAL_SET_FLAG(res == 0, F_ZF);
set_parity_flag(res);
}
static void set_szp_flags_16(u16 res)
{
CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
CONDITIONAL_SET_FLAG(res == 0, F_ZF);
set_parity_flag(res);
}
static void set_szp_flags_32(u32 res)
{
CONDITIONAL_SET_FLAG(res & 0x80000000, F_SF);
CONDITIONAL_SET_FLAG(res == 0, F_ZF);
set_parity_flag(res);
}
static void no_carry_byte_side_eff(u8 res)
{
CLEAR_FLAG(F_OF);
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_AF);
set_szp_flags_8(res);
}
static void no_carry_word_side_eff(u16 res)
{
CLEAR_FLAG(F_OF);
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_AF);
set_szp_flags_16(res);
}
static void no_carry_long_side_eff(u32 res)
{
CLEAR_FLAG(F_OF);
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_AF);
set_szp_flags_32(res);
}
static void calc_carry_chain(int bits, u32 d, u32 s, u32 res, int set_carry)
{
u32 cc;
cc = (s & d) | ((~res) & (s | d));
CONDITIONAL_SET_FLAG(XOR2(cc >> (bits - 2)), F_OF);
CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
if (set_carry) {
CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF);
}
}
static void calc_borrow_chain(int bits, u32 d, u32 s, u32 res, int set_carry)
{
u32 bc;
bc = (res & (~d | s)) | (~d & s);
CONDITIONAL_SET_FLAG(XOR2(bc >> (bits - 2)), F_OF);
CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
if (set_carry) {
CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF);
}
}
/****************************************************************************
REMARKS:
Implements the AAA instruction and side effects.
****************************************************************************/
u16 aaa_word(u16 d)
{
u16 res;
if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) {
d += 0x6;
d += 0x100;
SET_FLAG(F_AF);
SET_FLAG(F_CF);
} else {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_AF);
}
res = (u16)(d & 0xFF0F);
set_szp_flags_16(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the AAA instruction and side effects.
****************************************************************************/
u16 aas_word(u16 d)
{
u16 res;
if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) {
d -= 0x6;
d -= 0x100;
SET_FLAG(F_AF);
SET_FLAG(F_CF);
} else {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_AF);
}
res = (u16)(d & 0xFF0F);
set_szp_flags_16(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the AAD instruction and side effects.
****************************************************************************/
u16 aad_word(u16 d)
{
u16 l;
u8 hb, lb;
hb = (u8)((d >> 8) & 0xff);
lb = (u8)((d & 0xff));
l = (u16)((lb + 10 * hb) & 0xFF);
no_carry_byte_side_eff(l & 0xFF);
return l;
}
/****************************************************************************
REMARKS:
Implements the AAM instruction and side effects.
****************************************************************************/
u16 aam_word(u8 d)
{
u16 h, l;
h = (u16)(d / 10);
l = (u16)(d % 10);
l |= (u16)(h << 8);
no_carry_byte_side_eff(l & 0xFF);
return l;
}
/****************************************************************************
REMARKS:
Implements the ADC instruction and side effects.
****************************************************************************/
u8 adc_byte(u8 d, u8 s)
{
u32 res; /* all operands in native machine order */
res = d + s;
if (ACCESS_FLAG(F_CF)) res++;
set_szp_flags_8(res);
calc_carry_chain(8,s,d,res,1);
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the ADC instruction and side effects.
****************************************************************************/
u16 adc_word(u16 d, u16 s)
{
u32 res; /* all operands in native machine order */
res = d + s;
if (ACCESS_FLAG(F_CF))
res++;
set_szp_flags_16((u16)res);
calc_carry_chain(16,s,d,res,1);
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the ADC instruction and side effects.
****************************************************************************/
u32 adc_long(u32 d, u32 s)
{
u32 lo; /* all operands in native machine order */
u32 hi;
u32 res;
lo = (d & 0xFFFF) + (s & 0xFFFF);
res = d + s;
if (ACCESS_FLAG(F_CF)) {
lo++;
res++;
}
hi = (lo >> 16) + (d >> 16) + (s >> 16);
set_szp_flags_32(res);
calc_carry_chain(32,s,d,res,0);
CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF);
return res;
}
/****************************************************************************
REMARKS:
Implements the ADD instruction and side effects.
****************************************************************************/
u8 add_byte(u8 d, u8 s)
{
u32 res; /* all operands in native machine order */
res = d + s;
set_szp_flags_8((u8)res);
calc_carry_chain(8,s,d,res,1);
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the ADD instruction and side effects.
****************************************************************************/
u16 add_word(u16 d, u16 s)
{
u32 res; /* all operands in native machine order */
res = d + s;
set_szp_flags_16((u16)res);
calc_carry_chain(16,s,d,res,1);
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the ADD instruction and side effects.
****************************************************************************/
u32 add_long(u32 d, u32 s)
{
u32 res;
res = d + s;
set_szp_flags_32(res);
calc_carry_chain(32,s,d,res,0);
CONDITIONAL_SET_FLAG(res < d || res < s, F_CF);
return res;
}
/****************************************************************************
REMARKS:
Implements the AND instruction and side effects.
****************************************************************************/
u8 and_byte(u8 d, u8 s)
{
u8 res; /* all operands in native machine order */
res = d & s;
no_carry_byte_side_eff(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the AND instruction and side effects.
****************************************************************************/
u16 and_word(u16 d, u16 s)
{
u16 res; /* all operands in native machine order */
res = d & s;
no_carry_word_side_eff(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the AND instruction and side effects.
****************************************************************************/
u32 and_long(u32 d, u32 s)
{
u32 res; /* all operands in native machine order */
res = d & s;
no_carry_long_side_eff(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the CMP instruction and side effects.
****************************************************************************/
u8 cmp_byte(u8 d, u8 s)
{
u32 res; /* all operands in native machine order */
res = d - s;
set_szp_flags_8((u8)res);
calc_borrow_chain(8, d, s, res, 1);
return d;
}
/****************************************************************************
REMARKS:
Implements the CMP instruction and side effects.
****************************************************************************/
u16 cmp_word(u16 d, u16 s)
{
u32 res; /* all operands in native machine order */
res = d - s;
set_szp_flags_16((u16)res);
calc_borrow_chain(16, d, s, res, 1);
return d;
}
/****************************************************************************
REMARKS:
Implements the CMP instruction and side effects.
****************************************************************************/
u32 cmp_long(u32 d, u32 s)
{
u32 res; /* all operands in native machine order */
res = d - s;
set_szp_flags_32(res);
calc_borrow_chain(32, d, s, res, 1);
return d;
}
/****************************************************************************
REMARKS:
Implements the DAA instruction and side effects.
****************************************************************************/
u8 daa_byte(u8 d)
{
u32 res = d;
if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) {
res += 6;
SET_FLAG(F_AF);
}
if (res > 0x9F || ACCESS_FLAG(F_CF)) {
res += 0x60;
SET_FLAG(F_CF);
}
set_szp_flags_8((u8)res);
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the DAS instruction and side effects.
****************************************************************************/
u8 das_byte(u8 d)
{
if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) {
d -= 6;
SET_FLAG(F_AF);
}
if (d > 0x9F || ACCESS_FLAG(F_CF)) {
d -= 0x60;
SET_FLAG(F_CF);
}
set_szp_flags_8(d);
return d;
}
/****************************************************************************
REMARKS:
Implements the DEC instruction and side effects.
****************************************************************************/
u8 dec_byte(u8 d)
{
u32 res; /* all operands in native machine order */
res = d - 1;
set_szp_flags_8((u8)res);
calc_borrow_chain(8, d, 1, res, 0);
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the DEC instruction and side effects.
****************************************************************************/
u16 dec_word(u16 d)
{
u32 res; /* all operands in native machine order */
res = d - 1;
set_szp_flags_16((u16)res);
calc_borrow_chain(16, d, 1, res, 0);
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the DEC instruction and side effects.
****************************************************************************/
u32 dec_long(u32 d)
{
u32 res; /* all operands in native machine order */
res = d - 1;
set_szp_flags_32(res);
calc_borrow_chain(32, d, 1, res, 0);
return res;
}
/****************************************************************************
REMARKS:
Implements the INC instruction and side effects.
****************************************************************************/
u8 inc_byte(u8 d)
{
u32 res; /* all operands in native machine order */
res = d + 1;
set_szp_flags_8((u8)res);
calc_carry_chain(8, d, 1, res, 0);
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the INC instruction and side effects.
****************************************************************************/
u16 inc_word(u16 d)
{
u32 res; /* all operands in native machine order */
res = d + 1;
set_szp_flags_16((u16)res);
calc_carry_chain(16, d, 1, res, 0);
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the INC instruction and side effects.
****************************************************************************/
u32 inc_long(u32 d)
{
u32 res; /* all operands in native machine order */
res = d + 1;
set_szp_flags_32(res);
calc_carry_chain(32, d, 1, res, 0);
return res;
}
/****************************************************************************
REMARKS:
Implements the OR instruction and side effects.
****************************************************************************/
u8 or_byte(u8 d, u8 s)
{
u8 res; /* all operands in native machine order */
res = d | s;
no_carry_byte_side_eff(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the OR instruction and side effects.
****************************************************************************/
u16 or_word(u16 d, u16 s)
{
u16 res; /* all operands in native machine order */
res = d | s;
no_carry_word_side_eff(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the OR instruction and side effects.
****************************************************************************/
u32 or_long(u32 d, u32 s)
{
u32 res; /* all operands in native machine order */
res = d | s;
no_carry_long_side_eff(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the OR instruction and side effects.
****************************************************************************/
u8 neg_byte(u8 s)
{
u8 res;
CONDITIONAL_SET_FLAG(s != 0, F_CF);
res = (u8)-s;
set_szp_flags_8(res);
calc_borrow_chain(8, 0, s, res, 0);
return res;
}
/****************************************************************************
REMARKS:
Implements the OR instruction and side effects.
****************************************************************************/
u16 neg_word(u16 s)
{
u16 res;
CONDITIONAL_SET_FLAG(s != 0, F_CF);
res = (u16)-s;
set_szp_flags_16((u16)res);
calc_borrow_chain(16, 0, s, res, 0);
return res;
}
/****************************************************************************
REMARKS:
Implements the OR instruction and side effects.
****************************************************************************/
u32 neg_long(u32 s)
{
u32 res;
CONDITIONAL_SET_FLAG(s != 0, F_CF);
res = (u32)-s;
set_szp_flags_32(res);
calc_borrow_chain(32, 0, s, res, 0);
return res;
}
/****************************************************************************
REMARKS:
Implements the NOT instruction and side effects.
****************************************************************************/
u8 not_byte(u8 s)
{
return ~s;
}
/****************************************************************************
REMARKS:
Implements the NOT instruction and side effects.
****************************************************************************/
u16 not_word(u16 s)
{
return ~s;
}
/****************************************************************************
REMARKS:
Implements the NOT instruction and side effects.
****************************************************************************/
u32 not_long(u32 s)
{
return ~s;
}
/****************************************************************************
REMARKS:
Implements the RCL instruction and side effects.
****************************************************************************/
u8 rcl_byte(u8 d, u8 s)
{
unsigned int res, cnt, mask, cf;
/* s is the rotate distance. It varies from 0 - 8. */
/* have
CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0
want to rotate through the carry by "s" bits. We could
loop, but that's inefficient. So the width is 9,
and we split into three parts:
The new carry flag (was B_n)
the stuff in B_n-1 .. B_0
the stuff in B_7 .. B_n+1
The new rotate is done mod 9, and given this,
for a rotation of n bits (mod 9) the new carry flag is
then located n bits from the MSB. The low part is
then shifted up cnt bits, and the high part is or'd
in. Using CAPS for new values, and lowercase for the
original values, this can be expressed as:
IF n > 0
1) CF <- b_(8-n)
2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0
3) B_(n-1) <- cf
4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1))
*/
res = d;
if ((cnt = s % 9) != 0) {
/* extract the new CARRY FLAG. */
/* CF <- b_(8-n) */
cf = (d >> (8 - cnt)) & 0x1;
/* get the low stuff which rotated
into the range B_7 .. B_cnt */
/* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */
/* note that the right hand side done by the mask */
res = (d << cnt) & 0xff;
/* now the high stuff which rotated around
into the positions B_cnt-2 .. B_0 */
/* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */
/* shift it downward, 7-(n-2) = 9-n positions.
and mask off the result before or'ing in.
*/
mask = (1 << (cnt - 1)) - 1;
res |= (d >> (9 - cnt)) & mask;
/* if the carry flag was set, or it in. */
if (ACCESS_FLAG(F_CF)) { /* carry flag is set */
/* B_(n-1) <- cf */
res |= 1 << (cnt - 1);
}
/* set the new carry flag, based on the variable "cf" */
CONDITIONAL_SET_FLAG(cf, F_CF);
/* OVERFLOW is set *IFF* cnt==1, then it is the
xor of CF and the most significant bit. Blecck. */
/* parenthesized this expression since it appears to
be causing OF to be misset */
CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)),
F_OF);
}
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the RCL instruction and side effects.
****************************************************************************/
u16 rcl_word(u16 d, u8 s)
{
unsigned int res, cnt, mask, cf;
res = d;
if ((cnt = s % 17) != 0) {
cf = (d >> (16 - cnt)) & 0x1;
res = (d << cnt) & 0xffff;
mask = (1 << (cnt - 1)) - 1;
res |= (d >> (17 - cnt)) & mask;
if (ACCESS_FLAG(F_CF)) {
res |= 1 << (cnt - 1);
}
CONDITIONAL_SET_FLAG(cf, F_CF);
CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)),
F_OF);
}
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the RCL instruction and side effects.
****************************************************************************/
u32 rcl_long(u32 d, u8 s)
{
u32 res, cnt, mask, cf;
res = d;
if ((cnt = s % 33) != 0) {
cf = (d >> (32 - cnt)) & 0x1;
res = (d << cnt) & 0xffffffff;
mask = (1 << (cnt - 1)) - 1;
res |= (d >> (33 - cnt)) & mask;
if (ACCESS_FLAG(F_CF)) { /* carry flag is set */
res |= 1 << (cnt - 1);
}
CONDITIONAL_SET_FLAG(cf, F_CF);
CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)),
F_OF);
}
return res;
}
/****************************************************************************
REMARKS:
Implements the RCR instruction and side effects.
****************************************************************************/
u8 rcr_byte(u8 d, u8 s)
{
u32 res, cnt;
u32 mask, cf, ocf = 0;
/* rotate right through carry */
/*
s is the rotate distance. It varies from 0 - 8.
d is the byte object rotated.
have
CF B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0
The new rotate is done mod 9, and given this,
for a rotation of n bits (mod 9) the new carry flag is
then located n bits from the LSB. The low part is
then shifted up cnt bits, and the high part is or'd
in. Using CAPS for new values, and lowercase for the
original values, this can be expressed as:
IF n > 0
1) CF <- b_(n-1)
2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n)
3) B_(8-n) <- cf
4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0)
*/
res = d;
if ((cnt = s % 9) != 0) {
/* extract the new CARRY FLAG. */
/* CF <- b_(n-1) */
if (cnt == 1) {
cf = d & 0x1;
/* note hackery here. Access_flag(..) evaluates to either
0 if flag not set
non-zero if flag is set.
doing access_flag(..) != 0 casts that into either
0..1 in any representation of the flags register
(i.e. packed bit array or unpacked.)
*/
ocf = ACCESS_FLAG(F_CF) != 0;
} else
cf = (d >> (cnt - 1)) & 0x1;
/* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */
/* note that the right hand side done by the mask
This is effectively done by shifting the
object to the right. The result must be masked,
in case the object came in and was treated
as a negative number. Needed??? */
mask = (1 << (8 - cnt)) - 1;
res = (d >> cnt) & mask;
/* now the high stuff which rotated around
into the positions B_cnt-2 .. B_0 */
/* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */
/* shift it downward, 7-(n-2) = 9-n positions.
and mask off the result before or'ing in.
*/
res |= (d << (9 - cnt));
/* if the carry flag was set, or it in. */
if (ACCESS_FLAG(F_CF)) { /* carry flag is set */
/* B_(8-n) <- cf */
res |= 1 << (8 - cnt);
}
/* set the new carry flag, based on the variable "cf" */
CONDITIONAL_SET_FLAG(cf, F_CF);
/* OVERFLOW is set *IFF* cnt==1, then it is the
xor of CF and the most significant bit. Blecck. */
/* parenthesized... */
if (cnt == 1) {
CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)),
F_OF);
}
}
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the RCR instruction and side effects.
****************************************************************************/
u16 rcr_word(u16 d, u8 s)
{
u32 res, cnt;
u32 mask, cf, ocf = 0;
/* rotate right through carry */
res = d;
if ((cnt = s % 17) != 0) {
if (cnt == 1) {
cf = d & 0x1;
ocf = ACCESS_FLAG(F_CF) != 0;
} else
cf = (d >> (cnt - 1)) & 0x1;
mask = (1 << (16 - cnt)) - 1;
res = (d >> cnt) & mask;
res |= (d << (17 - cnt));
if (ACCESS_FLAG(F_CF)) {
res |= 1 << (16 - cnt);
}
CONDITIONAL_SET_FLAG(cf, F_CF);
if (cnt == 1) {
CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)),
F_OF);
}
}
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the RCR instruction and side effects.
****************************************************************************/
u32 rcr_long(u32 d, u8 s)
{
u32 res, cnt;
u32 mask, cf, ocf = 0;
/* rotate right through carry */
res = d;
if ((cnt = s % 33) != 0) {
if (cnt == 1) {
cf = d & 0x1;
ocf = ACCESS_FLAG(F_CF) != 0;
} else
cf = (d >> (cnt - 1)) & 0x1;
mask = (1 << (32 - cnt)) - 1;
res = (d >> cnt) & mask;
if (cnt != 1)
res |= (d << (33 - cnt));
if (ACCESS_FLAG(F_CF)) { /* carry flag is set */
res |= 1 << (32 - cnt);
}
CONDITIONAL_SET_FLAG(cf, F_CF);
if (cnt == 1) {
CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)),
F_OF);
}
}
return res;
}
/****************************************************************************
REMARKS:
Implements the ROL instruction and side effects.
****************************************************************************/
u8 rol_byte(u8 d, u8 s)
{
unsigned int res, cnt, mask;
/* rotate left */
/*
s is the rotate distance. It varies from 0 - 8.
d is the byte object rotated.
have
CF B_7 ... B_0
The new rotate is done mod 8.
Much simpler than the "rcl" or "rcr" operations.
IF n > 0
1) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0)
2) B_(n-1) .. B_(0) <- b_(7) .. b_(8-n)
*/
res = d;
if ((cnt = s % 8) != 0) {
/* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */
res = (d << cnt);
/* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */
mask = (1 << cnt) - 1;
res |= (d >> (8 - cnt)) & mask;
/* set the new carry flag, Note that it is the low order
bit of the result!!! */
CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
/* OVERFLOW is set *IFF* s==1, then it is the
xor of CF and the most significant bit. Blecck. */
CONDITIONAL_SET_FLAG(s == 1 &&
XOR2((res & 0x1) + ((res >> 6) & 0x2)),
F_OF);
} if (s != 0) {
/* set the new carry flag, Note that it is the low order
bit of the result!!! */
CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
}
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the ROL instruction and side effects.
****************************************************************************/
u16 rol_word(u16 d, u8 s)
{
unsigned int res, cnt, mask;
res = d;
if ((cnt = s % 16) != 0) {
res = (d << cnt);
mask = (1 << cnt) - 1;
res |= (d >> (16 - cnt)) & mask;
CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
CONDITIONAL_SET_FLAG(s == 1 &&
XOR2((res & 0x1) + ((res >> 14) & 0x2)),
F_OF);
} if (s != 0) {
/* set the new carry flag, Note that it is the low order
bit of the result!!! */
CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
}
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the ROL instruction and side effects.
****************************************************************************/
u32 rol_long(u32 d, u8 s)
{
u32 res, cnt, mask;
res = d;
if ((cnt = s % 32) != 0) {
res = (d << cnt);
mask = (1 << cnt) - 1;
res |= (d >> (32 - cnt)) & mask;
CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
CONDITIONAL_SET_FLAG(s == 1 &&
XOR2((res & 0x1) + ((res >> 30) & 0x2)),
F_OF);
} if (s != 0) {
/* set the new carry flag, Note that it is the low order
bit of the result!!! */
CONDITIONAL_SET_FLAG(res & 0x1, F_CF);
}
return res;
}
/****************************************************************************
REMARKS:
Implements the ROR instruction and side effects.
****************************************************************************/
u8 ror_byte(u8 d, u8 s)
{
unsigned int res, cnt, mask;
/* rotate right */
/*
s is the rotate distance. It varies from 0 - 8.
d is the byte object rotated.
have
B_7 ... B_0
The rotate is done mod 8.
IF n > 0
1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n)
2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0)
*/
res = d;
if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */
/* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */
res = (d << (8 - cnt));
/* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */
mask = (1 << (8 - cnt)) - 1;
res |= (d >> (cnt)) & mask;
/* set the new carry flag, Note that it is the low order
bit of the result!!! */
CONDITIONAL_SET_FLAG(res & 0x80, F_CF);
/* OVERFLOW is set *IFF* s==1, then it is the
xor of the two most significant bits. Blecck. */
CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF);
} else if (s != 0) {
/* set the new carry flag, Note that it is the low order
bit of the result!!! */
CONDITIONAL_SET_FLAG(res & 0x80, F_CF);
}
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the ROR instruction and side effects.
****************************************************************************/
u16 ror_word(u16 d, u8 s)
{
unsigned int res, cnt, mask;
res = d;
if ((cnt = s % 16) != 0) {
res = (d << (16 - cnt));
mask = (1 << (16 - cnt)) - 1;
res |= (d >> (cnt)) & mask;
CONDITIONAL_SET_FLAG(res & 0x8000, F_CF);
CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF);
} else if (s != 0) {
/* set the new carry flag, Note that it is the low order
bit of the result!!! */
CONDITIONAL_SET_FLAG(res & 0x8000, F_CF);
}
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the ROR instruction and side effects.
****************************************************************************/
u32 ror_long(u32 d, u8 s)
{
u32 res, cnt, mask;
res = d;
if ((cnt = s % 32) != 0) {
res = (d << (32 - cnt));
mask = (1 << (32 - cnt)) - 1;
res |= (d >> (cnt)) & mask;
CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF);
CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF);
} else if (s != 0) {
/* set the new carry flag, Note that it is the low order
bit of the result!!! */
CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF);
}
return res;
}
/****************************************************************************
REMARKS:
Implements the SHL instruction and side effects.
****************************************************************************/
u8 shl_byte(u8 d, u8 s)
{
unsigned int cnt, res, cf;
if (s < 8) {
cnt = s % 8;
/* last bit shifted out goes into carry flag */
if (cnt > 0) {
res = d << cnt;
cf = d & (1 << (8 - cnt));
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_8((u8)res);
} else {
res = (u8) d;
}
if (cnt == 1) {
/* Needs simplification. */
CONDITIONAL_SET_FLAG(
(((res & 0x80) == 0x80) ^
(ACCESS_FLAG(F_CF) != 0)),
/* was (M.x86.R_FLG&F_CF)==F_CF)), */
F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF);
CLEAR_FLAG(F_OF);
CLEAR_FLAG(F_SF);
SET_FLAG(F_PF);
SET_FLAG(F_ZF);
}
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the SHL instruction and side effects.
****************************************************************************/
u16 shl_word(u16 d, u8 s)
{
unsigned int cnt, res, cf;
if (s < 16) {
cnt = s % 16;
if (cnt > 0) {
res = d << cnt;
cf = d & (1 << (16 - cnt));
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_16((u16)res);
} else {
res = (u16) d;
}
if (cnt == 1) {
CONDITIONAL_SET_FLAG(
(((res & 0x8000) == 0x8000) ^
(ACCESS_FLAG(F_CF) != 0)),
F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF);
CLEAR_FLAG(F_OF);
CLEAR_FLAG(F_SF);
SET_FLAG(F_PF);
SET_FLAG(F_ZF);
}
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the SHL instruction and side effects.
****************************************************************************/
u32 shl_long(u32 d, u8 s)
{
unsigned int cnt, res, cf;
if (s < 32) {
cnt = s % 32;
if (cnt > 0) {
res = d << cnt;
cf = d & (1 << (32 - cnt));
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_32((u32)res);
} else {
res = d;
}
if (cnt == 1) {
CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^
(ACCESS_FLAG(F_CF) != 0)), F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF);
CLEAR_FLAG(F_OF);
CLEAR_FLAG(F_SF);
SET_FLAG(F_PF);
SET_FLAG(F_ZF);
}
return res;
}
/****************************************************************************
REMARKS:
Implements the SHR instruction and side effects.
****************************************************************************/
u8 shr_byte(u8 d, u8 s)
{
unsigned int cnt, res, cf;
if (s < 8) {
cnt = s % 8;
if (cnt > 0) {
cf = d & (1 << (cnt - 1));
res = d >> cnt;
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_8((u8)res);
} else {
res = (u8) d;
}
if (cnt == 1) {
CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF);
CLEAR_FLAG(F_OF);
CLEAR_FLAG(F_SF);
SET_FLAG(F_PF);
SET_FLAG(F_ZF);
}
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the SHR instruction and side effects.
****************************************************************************/
u16 shr_word(u16 d, u8 s)
{
unsigned int cnt, res, cf;
if (s < 16) {
cnt = s % 16;
if (cnt > 0) {
cf = d & (1 << (cnt - 1));
res = d >> cnt;
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_16((u16)res);
} else {
res = d;
}
if (cnt == 1) {
CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
SET_FLAG(F_ZF);
CLEAR_FLAG(F_SF);
CLEAR_FLAG(F_PF);
}
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the SHR instruction and side effects.
****************************************************************************/
u32 shr_long(u32 d, u8 s)
{
unsigned int cnt, res, cf;
if (s < 32) {
cnt = s % 32;
if (cnt > 0) {
cf = d & (1 << (cnt - 1));
res = d >> cnt;
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_32((u32)res);
} else {
res = d;
}
if (cnt == 1) {
CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
SET_FLAG(F_ZF);
CLEAR_FLAG(F_SF);
CLEAR_FLAG(F_PF);
}
return res;
}
/****************************************************************************
REMARKS:
Implements the SAR instruction and side effects.
****************************************************************************/
u8 sar_byte(u8 d, u8 s)
{
unsigned int cnt, res, cf, mask, sf;
res = d;
sf = d & 0x80;
cnt = s % 8;
if (cnt > 0 && cnt < 8) {
mask = (1 << (8 - cnt)) - 1;
cf = d & (1 << (cnt - 1));
res = (d >> cnt) & mask;
CONDITIONAL_SET_FLAG(cf, F_CF);
if (sf) {
res |= ~mask;
}
set_szp_flags_8((u8)res);
} else if (cnt >= 8) {
if (sf) {
res = 0xff;
SET_FLAG(F_CF);
CLEAR_FLAG(F_ZF);
SET_FLAG(F_SF);
SET_FLAG(F_PF);
} else {
res = 0;
CLEAR_FLAG(F_CF);
SET_FLAG(F_ZF);
CLEAR_FLAG(F_SF);
CLEAR_FLAG(F_PF);
}
}
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the SAR instruction and side effects.
****************************************************************************/
u16 sar_word(u16 d, u8 s)
{
unsigned int cnt, res, cf, mask, sf;
sf = d & 0x8000;
cnt = s % 16;
res = d;
if (cnt > 0 && cnt < 16) {
mask = (1 << (16 - cnt)) - 1;
cf = d & (1 << (cnt - 1));
res = (d >> cnt) & mask;
CONDITIONAL_SET_FLAG(cf, F_CF);
if (sf) {
res |= ~mask;
}
set_szp_flags_16((u16)res);
} else if (cnt >= 16) {
if (sf) {
res = 0xffff;
SET_FLAG(F_CF);
CLEAR_FLAG(F_ZF);
SET_FLAG(F_SF);
SET_FLAG(F_PF);
} else {
res = 0;
CLEAR_FLAG(F_CF);
SET_FLAG(F_ZF);
CLEAR_FLAG(F_SF);
CLEAR_FLAG(F_PF);
}
}
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the SAR instruction and side effects.
****************************************************************************/
u32 sar_long(u32 d, u8 s)
{
u32 cnt, res, cf, mask, sf;
sf = d & 0x80000000;
cnt = s % 32;
res = d;
if (cnt > 0 && cnt < 32) {
mask = (1 << (32 - cnt)) - 1;
cf = d & (1 << (cnt - 1));
res = (d >> cnt) & mask;
CONDITIONAL_SET_FLAG(cf, F_CF);
if (sf) {
res |= ~mask;
}
set_szp_flags_32(res);
} else if (cnt >= 32) {
if (sf) {
res = 0xffffffff;
SET_FLAG(F_CF);
CLEAR_FLAG(F_ZF);
SET_FLAG(F_SF);
SET_FLAG(F_PF);
} else {
res = 0;
CLEAR_FLAG(F_CF);
SET_FLAG(F_ZF);
CLEAR_FLAG(F_SF);
CLEAR_FLAG(F_PF);
}
}
return res;
}
/****************************************************************************
REMARKS:
Implements the SHLD instruction and side effects.
****************************************************************************/
u16 shld_word (u16 d, u16 fill, u8 s)
{
unsigned int cnt, res, cf;
if (s < 16) {
cnt = s % 16;
if (cnt > 0) {
res = (d << cnt) | (fill >> (16-cnt));
cf = d & (1 << (16 - cnt));
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_16((u16)res);
} else {
res = d;
}
if (cnt == 1) {
CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^
(ACCESS_FLAG(F_CF) != 0)), F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF);
CLEAR_FLAG(F_OF);
CLEAR_FLAG(F_SF);
SET_FLAG(F_PF);
SET_FLAG(F_ZF);
}
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the SHLD instruction and side effects.
****************************************************************************/
u32 shld_long (u32 d, u32 fill, u8 s)
{
unsigned int cnt, res, cf;
if (s < 32) {
cnt = s % 32;
if (cnt > 0) {
res = (d << cnt) | (fill >> (32-cnt));
cf = d & (1 << (32 - cnt));
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_32((u32)res);
} else {
res = d;
}
if (cnt == 1) {
CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^
(ACCESS_FLAG(F_CF) != 0)), F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF);
CLEAR_FLAG(F_OF);
CLEAR_FLAG(F_SF);
SET_FLAG(F_PF);
SET_FLAG(F_ZF);
}
return res;
}
/****************************************************************************
REMARKS:
Implements the SHRD instruction and side effects.
****************************************************************************/
u16 shrd_word (u16 d, u16 fill, u8 s)
{
unsigned int cnt, res, cf;
if (s < 16) {
cnt = s % 16;
if (cnt > 0) {
cf = d & (1 << (cnt - 1));
res = (d >> cnt) | (fill << (16 - cnt));
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_16((u16)res);
} else {
res = d;
}
if (cnt == 1) {
CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
SET_FLAG(F_ZF);
CLEAR_FLAG(F_SF);
CLEAR_FLAG(F_PF);
}
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the SHRD instruction and side effects.
****************************************************************************/
u32 shrd_long (u32 d, u32 fill, u8 s)
{
unsigned int cnt, res, cf;
if (s < 32) {
cnt = s % 32;
if (cnt > 0) {
cf = d & (1 << (cnt - 1));
res = (d >> cnt) | (fill << (32 - cnt));
CONDITIONAL_SET_FLAG(cf, F_CF);
set_szp_flags_32((u32)res);
} else {
res = d;
}
if (cnt == 1) {
CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF);
} else {
CLEAR_FLAG(F_OF);
}
} else {
res = 0;
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
SET_FLAG(F_ZF);
CLEAR_FLAG(F_SF);
CLEAR_FLAG(F_PF);
}
return res;
}
/****************************************************************************
REMARKS:
Implements the SBB instruction and side effects.
****************************************************************************/
u8 sbb_byte(u8 d, u8 s)
{
u32 res; /* all operands in native machine order */
u32 bc;
if (ACCESS_FLAG(F_CF))
res = d - s - 1;
else
res = d - s;
set_szp_flags_8((u8)res);
/* calculate the borrow chain. See note at top */
bc = (res & (~d | s)) | (~d & s);
CONDITIONAL_SET_FLAG(bc & 0x80, F_CF);
CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the SBB instruction and side effects.
****************************************************************************/
u16 sbb_word(u16 d, u16 s)
{
u32 res; /* all operands in native machine order */
u32 bc;
if (ACCESS_FLAG(F_CF))
res = d - s - 1;
else
res = d - s;
set_szp_flags_16((u16)res);
/* calculate the borrow chain. See note at top */
bc = (res & (~d | s)) | (~d & s);
CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF);
CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the SBB instruction and side effects.
****************************************************************************/
u32 sbb_long(u32 d, u32 s)
{
u32 res; /* all operands in native machine order */
u32 bc;
if (ACCESS_FLAG(F_CF))
res = d - s - 1;
else
res = d - s;
set_szp_flags_32(res);
/* calculate the borrow chain. See note at top */
bc = (res & (~d | s)) | (~d & s);
CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF);
CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
return res;
}
/****************************************************************************
REMARKS:
Implements the SUB instruction and side effects.
****************************************************************************/
u8 sub_byte(u8 d, u8 s)
{
u32 res; /* all operands in native machine order */
u32 bc;
res = d - s;
set_szp_flags_8((u8)res);
/* calculate the borrow chain. See note at top */
bc = (res & (~d | s)) | (~d & s);
CONDITIONAL_SET_FLAG(bc & 0x80, F_CF);
CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
return (u8)res;
}
/****************************************************************************
REMARKS:
Implements the SUB instruction and side effects.
****************************************************************************/
u16 sub_word(u16 d, u16 s)
{
u32 res; /* all operands in native machine order */
u32 bc;
res = d - s;
set_szp_flags_16((u16)res);
/* calculate the borrow chain. See note at top */
bc = (res & (~d | s)) | (~d & s);
CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF);
CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
return (u16)res;
}
/****************************************************************************
REMARKS:
Implements the SUB instruction and side effects.
****************************************************************************/
u32 sub_long(u32 d, u32 s)
{
u32 res; /* all operands in native machine order */
u32 bc;
res = d - s;
set_szp_flags_32(res);
/* calculate the borrow chain. See note at top */
bc = (res & (~d | s)) | (~d & s);
CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF);
CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
return res;
}
/****************************************************************************
REMARKS:
Implements the TEST instruction and side effects.
****************************************************************************/
void test_byte(u8 d, u8 s)
{
u32 res; /* all operands in native machine order */
res = d & s;
CLEAR_FLAG(F_OF);
set_szp_flags_8((u8)res);
/* AF == dont care */
CLEAR_FLAG(F_CF);
}
/****************************************************************************
REMARKS:
Implements the TEST instruction and side effects.
****************************************************************************/
void test_word(u16 d, u16 s)
{
u32 res; /* all operands in native machine order */
res = d & s;
CLEAR_FLAG(F_OF);
set_szp_flags_16((u16)res);
/* AF == dont care */
CLEAR_FLAG(F_CF);
}
/****************************************************************************
REMARKS:
Implements the TEST instruction and side effects.
****************************************************************************/
void test_long(u32 d, u32 s)
{
u32 res; /* all operands in native machine order */
res = d & s;
CLEAR_FLAG(F_OF);
set_szp_flags_32(res);
/* AF == dont care */
CLEAR_FLAG(F_CF);
}
/****************************************************************************
REMARKS:
Implements the XOR instruction and side effects.
****************************************************************************/
u8 xor_byte(u8 d, u8 s)
{
u8 res; /* all operands in native machine order */
res = d ^ s;
no_carry_byte_side_eff(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the XOR instruction and side effects.
****************************************************************************/
u16 xor_word(u16 d, u16 s)
{
u16 res; /* all operands in native machine order */
res = d ^ s;
no_carry_word_side_eff(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the XOR instruction and side effects.
****************************************************************************/
u32 xor_long(u32 d, u32 s)
{
u32 res; /* all operands in native machine order */
res = d ^ s;
no_carry_long_side_eff(res);
return res;
}
/****************************************************************************
REMARKS:
Implements the IMUL instruction and side effects.
****************************************************************************/
void imul_byte(u8 s)
{
s16 res = (s16)((s8)M.x86.R_AL * (s8)s);
M.x86.R_AX = res;
if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) ||
((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
}
/****************************************************************************
REMARKS:
Implements the IMUL instruction and side effects.
****************************************************************************/
void imul_word(u16 s)
{
s32 res = (s16)M.x86.R_AX * (s16)s;
M.x86.R_AX = (u16)res;
M.x86.R_DX = (u16)(res >> 16);
if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x0000) ||
((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
}
/****************************************************************************
REMARKS:
Implements the IMUL instruction and side effects.
****************************************************************************/
void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s)
{
#ifdef __HAS_LONG_LONG__
s64 res = (s32)d * (s32)s;
*res_lo = (u32)res;
*res_hi = (u32)(res >> 32);
#else
u32 d_lo,d_hi,d_sign;
u32 s_lo,s_hi,s_sign;
u32 rlo_lo,rlo_hi,rhi_lo;
if ((d_sign = d & 0x80000000) != 0)
d = -d;
d_lo = d & 0xFFFF;
d_hi = d >> 16;
if ((s_sign = s & 0x80000000) != 0)
s = -s;
s_lo = s & 0xFFFF;
s_hi = s >> 16;
rlo_lo = d_lo * s_lo;
rlo_hi = (d_hi * s_lo + d_lo * s_hi) + (rlo_lo >> 16);
rhi_lo = d_hi * s_hi + (rlo_hi >> 16);
*res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF);
*res_hi = rhi_lo;
if (d_sign != s_sign) {
d = ~*res_lo;
s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16);
*res_lo = ~*res_lo+1;
*res_hi = ~*res_hi+(s >> 16);
}
#endif
}
/****************************************************************************
REMARKS:
Implements the IMUL instruction and side effects.
****************************************************************************/
void imul_long(u32 s)
{
imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s);
if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00000000) ||
((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
}
/****************************************************************************
REMARKS:
Implements the MUL instruction and side effects.
****************************************************************************/
void mul_byte(u8 s)
{
u16 res = (u16)(M.x86.R_AL * s);
M.x86.R_AX = res;
if (M.x86.R_AH == 0) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
}
/****************************************************************************
REMARKS:
Implements the MUL instruction and side effects.
****************************************************************************/
void mul_word(u16 s)
{
u32 res = M.x86.R_AX * s;
M.x86.R_AX = (u16)res;
M.x86.R_DX = (u16)(res >> 16);
if (M.x86.R_DX == 0) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
}
/****************************************************************************
REMARKS:
Implements the MUL instruction and side effects.
****************************************************************************/
void mul_long(u32 s)
{
#ifdef __HAS_LONG_LONG__
u64 res = (u32)M.x86.R_EAX * (u32)s;
M.x86.R_EAX = (u32)res;
M.x86.R_EDX = (u32)(res >> 32);
#else
u32 a,a_lo,a_hi;
u32 s_lo,s_hi;
u32 rlo_lo,rlo_hi,rhi_lo;
a = M.x86.R_EAX;
a_lo = a & 0xFFFF;
a_hi = a >> 16;
s_lo = s & 0xFFFF;
s_hi = s >> 16;
rlo_lo = a_lo * s_lo;
rlo_hi = (a_hi * s_lo + a_lo * s_hi) + (rlo_lo >> 16);
rhi_lo = a_hi * s_hi + (rlo_hi >> 16);
M.x86.R_EAX = (rlo_hi << 16) | (rlo_lo & 0xFFFF);
M.x86.R_EDX = rhi_lo;
#endif
if (M.x86.R_EDX == 0) {
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_OF);
} else {
SET_FLAG(F_CF);
SET_FLAG(F_OF);
}
}
/****************************************************************************
REMARKS:
Implements the IDIV instruction and side effects.
****************************************************************************/
void idiv_byte(u8 s)
{
s32 dvd, div, mod;
dvd = (s16)M.x86.R_AX;
if (s == 0) {
x86emu_intr_raise(0);
return;
}
div = dvd / (s8)s;
mod = dvd % (s8)s;
if (abs(div) > 0x7f) {
x86emu_intr_raise(0);
return;
}
M.x86.R_AL = (s8) div;
M.x86.R_AH = (s8) mod;
}
/****************************************************************************
REMARKS:
Implements the IDIV instruction and side effects.
****************************************************************************/
void idiv_word(u16 s)
{
s32 dvd, div, mod;
dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX;
if (s == 0) {
x86emu_intr_raise(0);
return;
}
div = dvd / (s16)s;
mod = dvd % (s16)s;
if (abs(div) > 0x7fff) {
x86emu_intr_raise(0);
return;
}
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_SF);
CONDITIONAL_SET_FLAG(div == 0, F_ZF);
set_parity_flag(mod);
M.x86.R_AX = (u16)div;
M.x86.R_DX = (u16)mod;
}
/****************************************************************************
REMARKS:
Implements the IDIV instruction and side effects.
****************************************************************************/
void idiv_long(u32 s)
{
#ifdef __HAS_LONG_LONG__
s64 dvd, div, mod;
dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX;
if (s == 0) {
x86emu_intr_raise(0);
return;
}
div = dvd / (s32)s;
mod = dvd % (s32)s;
if (abs(div) > 0x7fffffff) {
x86emu_intr_raise(0);
return;
}
#else
s32 div = 0, mod;
s32 h_dvd = M.x86.R_EDX;
u32 l_dvd = M.x86.R_EAX;
u32 abs_s = s & 0x7FFFFFFF;
u32 abs_h_dvd = h_dvd & 0x7FFFFFFF;
u32 h_s = abs_s >> 1;
u32 l_s = abs_s << 31;
int counter = 31;
int carry;
if (s == 0) {
x86emu_intr_raise(0);
return;
}
do {
div <<= 1;
carry = (l_dvd >= l_s) ? 0 : 1;
if (abs_h_dvd < (h_s + carry)) {
h_s >>= 1;
l_s = abs_s << (--counter);
continue;
} else {
abs_h_dvd -= (h_s + carry);
l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1)
: (l_dvd - l_s);
h_s >>= 1;
l_s = abs_s << (--counter);
div |= 1;
continue;
}
} while (counter > -1);
/* overflow */
if (abs_h_dvd || (l_dvd > abs_s)) {
x86emu_intr_raise(0);
return;
}
/* sign */
div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000));
mod = l_dvd;
#endif
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_AF);
CLEAR_FLAG(F_SF);
SET_FLAG(F_ZF);
set_parity_flag(mod);
M.x86.R_EAX = (u32)div;
M.x86.R_EDX = (u32)mod;
}
/****************************************************************************
REMARKS:
Implements the DIV instruction and side effects.
****************************************************************************/
void div_byte(u8 s)
{
u32 dvd, div, mod;
dvd = M.x86.R_AX;
if (s == 0) {
x86emu_intr_raise(0);
return;
}
div = dvd / (u8)s;
mod = dvd % (u8)s;
if (abs(div) > 0xff) {
x86emu_intr_raise(0);
return;
}
M.x86.R_AL = (u8)div;
M.x86.R_AH = (u8)mod;
}
/****************************************************************************
REMARKS:
Implements the DIV instruction and side effects.
****************************************************************************/
void div_word(u16 s)
{
u32 dvd, div, mod;
dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX;
if (s == 0) {
x86emu_intr_raise(0);
return;
}
div = dvd / (u16)s;
mod = dvd % (u16)s;
if (abs(div) > 0xffff) {
x86emu_intr_raise(0);
return;
}
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_SF);
CONDITIONAL_SET_FLAG(div == 0, F_ZF);
set_parity_flag(mod);
M.x86.R_AX = (u16)div;
M.x86.R_DX = (u16)mod;
}
/****************************************************************************
REMARKS:
Implements the DIV instruction and side effects.
****************************************************************************/
void div_long(u32 s)
{
#ifdef __HAS_LONG_LONG__
u64 dvd, div, mod;
dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX;
if (s == 0) {
x86emu_intr_raise(0);
return;
}
div = dvd / (u32)s;
mod = dvd % (u32)s;
if (abs(div) > 0xffffffff) {
x86emu_intr_raise(0);
return;
}
#else
s32 div = 0, mod;
s32 h_dvd = M.x86.R_EDX;
u32 l_dvd = M.x86.R_EAX;
u32 h_s = s;
u32 l_s = 0;
int counter = 32;
int carry;
if (s == 0) {
x86emu_intr_raise(0);
return;
}
do {
div <<= 1;
carry = (l_dvd >= l_s) ? 0 : 1;
if (h_dvd < (h_s + carry)) {
h_s >>= 1;
l_s = s << (--counter);
continue;
} else {
h_dvd -= (h_s + carry);
l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1)
: (l_dvd - l_s);
h_s >>= 1;
l_s = s << (--counter);
div |= 1;
continue;
}
} while (counter > -1);
/* overflow */
if (h_dvd || (l_dvd > s)) {
x86emu_intr_raise(0);
return;
}
mod = l_dvd;
#endif
CLEAR_FLAG(F_CF);
CLEAR_FLAG(F_AF);
CLEAR_FLAG(F_SF);
SET_FLAG(F_ZF);
set_parity_flag(mod);
M.x86.R_EAX = (u32)div;
M.x86.R_EDX = (u32)mod;
}
/****************************************************************************
REMARKS:
Implements the IN string instruction and side effects.
****************************************************************************/
static void single_in(int size)
{
if(size == 1)
store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX));
else if (size == 2)
store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX));
else
store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX));
}
void ins(int size)
{
int inc = size;
if (ACCESS_FLAG(F_DF)) {
inc = -size;
}
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* dont care whether REPE or REPNE */
/* in until CX is ZERO. */
u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ?
M.x86.R_ECX : M.x86.R_CX);
while (count--) {
single_in(size);
M.x86.R_DI += inc;
}
M.x86.R_CX = 0;
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
M.x86.R_ECX = 0;
}
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
} else {
single_in(size);
M.x86.R_DI += inc;
}
}
/****************************************************************************
REMARKS:
Implements the OUT string instruction and side effects.
****************************************************************************/
static void single_out(int size)
{
if(size == 1)
(*sys_outb)(M.x86.R_DX,fetch_data_byte_abs(M.x86.R_ES, M.x86.R_SI));
else if (size == 2)
(*sys_outw)(M.x86.R_DX,fetch_data_word_abs(M.x86.R_ES, M.x86.R_SI));
else
(*sys_outl)(M.x86.R_DX,fetch_data_long_abs(M.x86.R_ES, M.x86.R_SI));
}
void outs(int size)
{
int inc = size;
if (ACCESS_FLAG(F_DF)) {
inc = -size;
}
if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) {
/* dont care whether REPE or REPNE */
/* out until CX is ZERO. */
u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ?
M.x86.R_ECX : M.x86.R_CX);
while (count--) {
single_out(size);
M.x86.R_SI += inc;
}
M.x86.R_CX = 0;
if (M.x86.mode & SYSMODE_PREFIX_DATA) {
M.x86.R_ECX = 0;
}
M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE);
} else {
single_out(size);
M.x86.R_SI += inc;
}
}
/****************************************************************************
PARAMETERS:
addr - Address to fetch word from
REMARKS:
Fetches a word from emulator memory using an absolute address.
****************************************************************************/
u16 mem_access_word(int addr)
{
DB( if (CHECK_MEM_ACCESS())
x86emu_check_mem_access(addr);)
return (*sys_rdw)(addr);
}
/****************************************************************************
REMARKS:
Pushes a word onto the stack.
NOTE: Do not inline this, as (*sys_wrX) is already inline!
****************************************************************************/
void push_word(u16 w)
{
DB( if (CHECK_SP_ACCESS())
x86emu_check_sp_access();)
M.x86.R_SP -= 2;
(*sys_wrw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w);
}
/****************************************************************************
REMARKS:
Pushes a long onto the stack.
NOTE: Do not inline this, as (*sys_wrX) is already inline!
****************************************************************************/
void push_long(u32 w)
{
DB( if (CHECK_SP_ACCESS())
x86emu_check_sp_access();)
M.x86.R_SP -= 4;
(*sys_wrl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP, w);
}
/****************************************************************************
REMARKS:
Pops a word from the stack.
NOTE: Do not inline this, as (*sys_rdX) is already inline!
****************************************************************************/
u16 pop_word(void)
{
u16 res;
DB( if (CHECK_SP_ACCESS())
x86emu_check_sp_access();)
res = (*sys_rdw)(((u32)M.x86.R_SS << 4) + M.x86.R_SP);
M.x86.R_SP += 2;
return res;
}
/****************************************************************************
REMARKS:
Pops a long from the stack.
NOTE: Do not inline this, as (*sys_rdX) is already inline!
****************************************************************************/
u32 pop_long(void)
{
u32 res;
DB( if (CHECK_SP_ACCESS())
x86emu_check_sp_access();)
res = (*sys_rdl)(((u32)M.x86.R_SS << 4) + M.x86.R_SP);
M.x86.R_SP += 4;
return res;
}
|
1001-study-uboot
|
drivers/bios_emulator/x86emu/prim_ops.c
|
C
|
gpl3
| 63,136
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1996-1999 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Header file for public specific functions.
* Any application linking against us should only
* include this header
*
****************************************************************************/
#ifndef __X86EMU_X86EMU_H
#define __X86EMU_X86EMU_H
#include <asm/types.h>
#include <common.h>
#include <pci.h>
#include <asm/io.h>
#define X86API
#define X86APIP *
typedef u16 X86EMU_pioAddr;
#include "x86emu/regs.h"
/*---------------------- Macros and type definitions ----------------------*/
#if defined (CONFIG_ARM)
#define GAS_LINE_COMMENT "@"
#elif defined(CONFIG_MIPS) || defined(CONFIG_PPC)
#define GAS_LINE_COMMENT "#"
#elif defined (CONFIG_SH)
#define GAS_LINE_COMMENT "!"
#endif
#define GOT2_TYPE ".got2,\"aw\"\t"GAS_LINE_COMMENT
#pragma pack(1)
/****************************************************************************
REMARKS:
Data structure containing ponters to programmed I/O functions used by the
emulator. This is used so that the user program can hook all programmed
I/O for the emulator to handled as necessary by the user program. By
default the emulator contains simple functions that do not do access the
hardware in any way. To allow the emualtor access the hardware, you will
need to override the programmed I/O functions using the X86EMU_setupPioFuncs
function.
HEADER:
x86emu.h
MEMBERS:
inb - Function to read a byte from an I/O port
inw - Function to read a word from an I/O port
inl - Function to read a dword from an I/O port
outb - Function to write a byte to an I/O port
outw - Function to write a word to an I/O port
outl - Function to write a dword to an I/O port
****************************************************************************/
typedef struct {
u8(X86APIP inb) (X86EMU_pioAddr addr);
u16(X86APIP inw) (X86EMU_pioAddr addr);
u32(X86APIP inl) (X86EMU_pioAddr addr);
void (X86APIP outb) (X86EMU_pioAddr addr, u8 val);
void (X86APIP outw) (X86EMU_pioAddr addr, u16 val);
void (X86APIP outl) (X86EMU_pioAddr addr, u32 val);
} X86EMU_pioFuncs;
/****************************************************************************
REMARKS:
Data structure containing ponters to memory access functions used by the
emulator. This is used so that the user program can hook all memory
access functions as necessary for the emulator. By default the emulator
contains simple functions that only access the internal memory of the
emulator. If you need specialised functions to handle access to different
types of memory (ie: hardware framebuffer accesses and BIOS memory access
etc), you will need to override this using the X86EMU_setupMemFuncs
function.
HEADER:
x86emu.h
MEMBERS:
rdb - Function to read a byte from an address
rdw - Function to read a word from an address
rdl - Function to read a dword from an address
wrb - Function to write a byte to an address
wrw - Function to write a word to an address
wrl - Function to write a dword to an address
****************************************************************************/
typedef struct {
u8(X86APIP rdb) (u32 addr);
u16(X86APIP rdw) (u32 addr);
u32(X86APIP rdl) (u32 addr);
void (X86APIP wrb) (u32 addr, u8 val);
void (X86APIP wrw) (u32 addr, u16 val);
void (X86APIP wrl) (u32 addr, u32 val);
} X86EMU_memFuncs;
/****************************************************************************
Here are the default memory read and write
function in case they are needed as fallbacks.
***************************************************************************/
extern u8 X86API rdb(u32 addr);
extern u16 X86API rdw(u32 addr);
extern u32 X86API rdl(u32 addr);
extern void X86API wrb(u32 addr, u8 val);
extern void X86API wrw(u32 addr, u16 val);
extern void X86API wrl(u32 addr, u32 val);
#pragma pack()
/*--------------------- type definitions -----------------------------------*/
typedef void (X86APIP X86EMU_intrFuncs) (int num);
extern X86EMU_intrFuncs _X86EMU_intrTab[256];
/*-------------------------- Function Prototypes --------------------------*/
#ifdef __cplusplus
extern "C" { /* Use "C" linkage when in C++ mode */
#endif
void X86EMU_setupMemFuncs(X86EMU_memFuncs * funcs);
void X86EMU_setupPioFuncs(X86EMU_pioFuncs * funcs);
void X86EMU_setupIntrFuncs(X86EMU_intrFuncs funcs[]);
void X86EMU_prepareForInt(int num);
/* decode.c */
void X86EMU_exec(void);
void X86EMU_halt_sys(void);
#ifdef DEBUG
#define HALT_SYS() \
printf("halt_sys: file %s, line %d\n", __FILE__, __LINE__), \
X86EMU_halt_sys()
#else
#define HALT_SYS() X86EMU_halt_sys()
#endif
/* Debug options */
#define DEBUG_DECODE_F 0x0001 /* print decoded instruction */
#define DEBUG_TRACE_F 0x0002 /* dump regs before/after execution */
#define DEBUG_STEP_F 0x0004
#define DEBUG_DISASSEMBLE_F 0x0008
#define DEBUG_BREAK_F 0x0010
#define DEBUG_SVC_F 0x0020
#define DEBUG_SAVE_CS_IP 0x0040
#define DEBUG_FS_F 0x0080
#define DEBUG_PROC_F 0x0100
#define DEBUG_SYSINT_F 0x0200 /* bios system interrupts. */
#define DEBUG_TRACECALL_F 0x0400
#define DEBUG_INSTRUMENT_F 0x0800
#define DEBUG_MEM_TRACE_F 0x1000
#define DEBUG_IO_TRACE_F 0x2000
#define DEBUG_TRACECALL_REGS_F 0x4000
#define DEBUG_DECODE_NOPRINT_F 0x8000
#define DEBUG_EXIT 0x10000
#define DEBUG_SYS_F (DEBUG_SVC_F|DEBUG_FS_F|DEBUG_PROC_F)
void X86EMU_trace_regs(void);
void X86EMU_trace_xregs(void);
void X86EMU_dump_memory(u16 seg, u16 off, u32 amt);
int X86EMU_trace_on(void);
int X86EMU_trace_off(void);
#ifdef __cplusplus
} /* End of "C" linkage for C++ */
#endif
#endif /* __X86EMU_X86EMU_H */
|
1001-study-uboot
|
drivers/bios_emulator/include/x86emu.h
|
C
|
gpl3
| 7,381
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Header file for system specific functions. These functions
* are always compiled and linked in the OS depedent libraries,
* and never in a binary portable driver.
*
****************************************************************************/
#ifndef __X86EMU_X86EMUI_H
#define __X86EMU_X86EMUI_H
/* If we are compiling in C++ mode, we can compile some functions as
* inline to increase performance (however the code size increases quite
* dramatically in this case).
*/
#if defined(__cplusplus) && !defined(_NO_INLINE)
#define _INLINE inline
#else
#define _INLINE static
#endif
/* Get rid of unused parameters in C++ compilation mode */
#ifdef __cplusplus
#define X86EMU_UNUSED(v)
#else
#define X86EMU_UNUSED(v) v
#endif
#include "x86emu.h"
#include "x86emu/regs.h"
#include "x86emu/debug.h"
#include "x86emu/decode.h"
#include "x86emu/ops.h"
#include "x86emu/prim_ops.h"
#ifndef __KERNEL__
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#endif
#define printk printf
/*--------------------------- Inline Functions ----------------------------*/
#ifdef __cplusplus
extern "C" { /* Use "C" linkage when in C++ mode */
#endif
extern u8(X86APIP sys_rdb) (u32 addr);
extern u16(X86APIP sys_rdw) (u32 addr);
extern u32(X86APIP sys_rdl) (u32 addr);
extern void (X86APIP sys_wrb) (u32 addr, u8 val);
extern void (X86APIP sys_wrw) (u32 addr, u16 val);
extern void (X86APIP sys_wrl) (u32 addr, u32 val);
extern u8(X86APIP sys_inb) (X86EMU_pioAddr addr);
extern u16(X86APIP sys_inw) (X86EMU_pioAddr addr);
extern u32(X86APIP sys_inl) (X86EMU_pioAddr addr);
extern void (X86APIP sys_outb) (X86EMU_pioAddr addr, u8 val);
extern void (X86APIP sys_outw) (X86EMU_pioAddr addr, u16 val);
extern void (X86APIP sys_outl) (X86EMU_pioAddr addr, u32 val);
#ifdef __cplusplus
} /* End of "C" linkage for C++ */
#endif
#endif /* __X86EMU_X86EMUI_H */
|
1001-study-uboot
|
drivers/bios_emulator/include/x86emu/x86emui.h
|
C
|
gpl3
| 3,582
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Header file for debug definitions.
*
****************************************************************************/
#ifndef __X86EMU_DEBUG_H
#define __X86EMU_DEBUG_H
/*---------------------- Macros and type definitions ----------------------*/
/* checks to be enabled for "runtime" */
#define CHECK_IP_FETCH_F 0x1
#define CHECK_SP_ACCESS_F 0x2
#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */
#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */
#ifdef DEBUG
# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F)
# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F)
# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F)
# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F)
#else
# define CHECK_IP_FETCH()
# define CHECK_SP_ACCESS()
# define CHECK_MEM_ACCESS()
# define CHECK_DATA_ACCESS()
#endif
#ifdef DEBUG
# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F)
# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F)
# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F)
# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F)
# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F)
# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F)
# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F)
# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP)
# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F)
# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F)
# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F)
# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F)
# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F)
# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F)
# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F)
# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F)
# define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F)
#else
# define DEBUG_INSTRUMENT() 0
# define DEBUG_DECODE() 0
# define DEBUG_TRACE() 0
# define DEBUG_STEP() 0
# define DEBUG_DISASSEMBLE() 0
# define DEBUG_BREAK() 0
# define DEBUG_SVC() 0
# define DEBUG_SAVE_IP_CS() 0
# define DEBUG_FS() 0
# define DEBUG_PROC() 0
# define DEBUG_SYSINT() 0
# define DEBUG_TRACECALL() 0
# define DEBUG_TRACECALLREGS() 0
# define DEBUG_SYS() 0
# define DEBUG_MEM_TRACE() 0
# define DEBUG_IO_TRACE() 0
# define DEBUG_DECODE_NOPRINT() 0
#endif
#ifdef DEBUG
# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \
x86emu_decode_printf(x)
# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \
x86emu_decode_printf2(x,y)
/*
* The following allow us to look at the bytes of an instruction. The
* first INCR_INSTRN_LEN, is called everytime bytes are consumed in
* the decoding process. The SAVE_IP_CS is called initially when the
* major opcode of the instruction is accessed.
*/
#define INC_DECODED_INST_LEN(x) \
if (DEBUG_DECODE()) \
x86emu_inc_decoded_inst_len(x)
#define SAVE_IP_CS(x,y) \
if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \
| DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
M.x86.saved_cs = x; \
M.x86.saved_ip = y; \
}
#else
# define INC_DECODED_INST_LEN(x)
# define DECODE_PRINTF(x)
# define DECODE_PRINTF2(x,y)
# define SAVE_IP_CS(x,y)
#endif
#ifdef DEBUG
#define TRACE_REGS() \
if (DEBUG_DISASSEMBLE()) { \
x86emu_just_disassemble(); \
goto EndOfTheInstructionProcedure; \
} \
if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs()
#else
# define TRACE_REGS()
#endif
#ifdef DEBUG
# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step()
#else
# define SINGLE_STEP()
#endif
#define TRACE_AND_STEP() \
TRACE_REGS(); \
SINGLE_STEP()
#ifdef DEBUG
# define START_OF_INSTR()
# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr();
# define END_OF_INSTR_NO_TRACE() x86emu_end_instr();
#else
# define START_OF_INSTR()
# define END_OF_INSTR()
# define END_OF_INSTR_NO_TRACE()
#endif
#ifdef DEBUG
# define CALL_TRACE(u,v,w,x,s) \
if (DEBUG_TRACECALLREGS()) \
x86emu_dump_regs(); \
if (DEBUG_TRACECALL()) \
printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x);
# define RETURN_TRACE(n,u,v) \
if (DEBUG_TRACECALLREGS()) \
x86emu_dump_regs(); \
if (DEBUG_TRACECALL()) \
printk("%04x:%04x: %s\n",u,v,n);
#else
# define CALL_TRACE(u,v,w,x,s)
# define RETURN_TRACE(n,u,v)
#endif
#ifdef DEBUG
#define DB(x) x
#else
#define DB(x)
#endif
/*-------------------------- Function Prototypes --------------------------*/
#ifdef __cplusplus
extern "C" { /* Use "C" linkage when in C++ mode */
#endif
extern void x86emu_inc_decoded_inst_len(int x);
extern void x86emu_decode_printf(char *x);
extern void x86emu_decode_printf2(char *x, int y);
extern void x86emu_just_disassemble(void);
extern void x86emu_single_step(void);
extern void x86emu_end_instr(void);
extern void x86emu_dump_regs(void);
extern void x86emu_dump_xregs(void);
extern void x86emu_print_int_vect(u16 iv);
extern void x86emu_instrument_instruction(void);
extern void x86emu_check_ip_access(void);
extern void x86emu_check_sp_access(void);
extern void x86emu_check_mem_access(u32 p);
extern void x86emu_check_data_access(uint s, uint o);
#ifdef __cplusplus
} /* End of "C" linkage for C++ */
#endif
#endif /* __X86EMU_DEBUG_H */
|
1001-study-uboot
|
drivers/bios_emulator/include/x86emu/debug.h
|
C
|
gpl3
| 6,948
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Header file for instruction decoding logic.
*
****************************************************************************/
#ifndef __X86EMU_DECODE_H
#define __X86EMU_DECODE_H
/*---------------------- Macros and type definitions ----------------------*/
/* Instruction Decoding Stuff */
#define FETCH_DECODE_MODRM(mod,rh,rl) fetch_decode_modrm(&mod,&rh,&rl)
#define DECODE_RM_BYTE_REGISTER(r) decode_rm_byte_register(r)
#define DECODE_RM_WORD_REGISTER(r) decode_rm_word_register(r)
#define DECODE_RM_LONG_REGISTER(r) decode_rm_long_register(r)
#define DECODE_CLEAR_SEGOVR() M.x86.mode &= ~SYSMODE_CLRMASK
/*-------------------------- Function Prototypes --------------------------*/
#ifdef __cplusplus
extern "C" { /* Use "C" linkage when in C++ mode */
#endif
void x86emu_intr_raise (u8 type);
void fetch_decode_modrm (int *mod,int *regh,int *regl);
u8 fetch_byte_imm (void);
u16 fetch_word_imm (void);
u32 fetch_long_imm (void);
u8 fetch_data_byte (uint offset);
u8 fetch_data_byte_abs (uint segment, uint offset);
u16 fetch_data_word (uint offset);
u16 fetch_data_word_abs (uint segment, uint offset);
u32 fetch_data_long (uint offset);
u32 fetch_data_long_abs (uint segment, uint offset);
void store_data_byte (uint offset, u8 val);
void store_data_byte_abs (uint segment, uint offset, u8 val);
void store_data_word (uint offset, u16 val);
void store_data_word_abs (uint segment, uint offset, u16 val);
void store_data_long (uint offset, u32 val);
void store_data_long_abs (uint segment, uint offset, u32 val);
u8* decode_rm_byte_register(int reg);
u16* decode_rm_word_register(int reg);
u32* decode_rm_long_register(int reg);
u16* decode_rm_seg_register(int reg);
unsigned decode_rm00_address(int rm);
unsigned decode_rm01_address(int rm);
unsigned decode_rm10_address(int rm);
unsigned decode_rmXX_address(int mod, int rm);
#ifdef __cplusplus
} /* End of "C" linkage for C++ */
#endif
#endif /* __X86EMU_DECODE_H */
|
1001-study-uboot
|
drivers/bios_emulator/include/x86emu/decode.h
|
C
|
gpl3
| 3,766
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Header file for x86 register definitions.
*
****************************************************************************/
#ifndef __X86EMU_REGS_H
#define __X86EMU_REGS_H
/*---------------------- Macros and type definitions ----------------------*/
#pragma pack(1)
/*
* General EAX, EBX, ECX, EDX type registers. Note that for
* portability, and speed, the issue of byte swapping is not addressed
* in the registers. All registers are stored in the default format
* available on the host machine. The only critical issue is that the
* registers should line up EXACTLY in the same manner as they do in
* the 386. That is:
*
* EAX & 0xff === AL
* EAX & 0xffff == AX
*
* etc. The result is that alot of the calculations can then be
* done using the native instruction set fully.
*/
#ifdef __BIG_ENDIAN__
typedef struct {
u32 e_reg;
} I32_reg_t;
typedef struct {
u16 filler0, x_reg;
} I16_reg_t;
typedef struct {
u8 filler0, filler1, h_reg, l_reg;
} I8_reg_t;
#else /* !__BIG_ENDIAN__ */
typedef struct {
u32 e_reg;
} I32_reg_t;
typedef struct {
u16 x_reg;
} I16_reg_t;
typedef struct {
u8 l_reg, h_reg;
} I8_reg_t;
#endif /* BIG_ENDIAN */
typedef union {
I32_reg_t I32_reg;
I16_reg_t I16_reg;
I8_reg_t I8_reg;
} i386_general_register;
struct i386_general_regs {
i386_general_register A, B, C, D;
};
typedef struct i386_general_regs Gen_reg_t;
struct i386_special_regs {
i386_general_register SP, BP, SI, DI, IP;
u32 FLAGS;
};
/*
* Segment registers here represent the 16 bit quantities
* CS, DS, ES, SS.
*/
#undef CS
#undef DS
#undef SS
#undef ES
#undef FS
#undef GS
struct i386_segment_regs {
u16 CS, DS, SS, ES, FS, GS;
};
/* 8 bit registers */
#define R_AH gen.A.I8_reg.h_reg
#define R_AL gen.A.I8_reg.l_reg
#define R_BH gen.B.I8_reg.h_reg
#define R_BL gen.B.I8_reg.l_reg
#define R_CH gen.C.I8_reg.h_reg
#define R_CL gen.C.I8_reg.l_reg
#define R_DH gen.D.I8_reg.h_reg
#define R_DL gen.D.I8_reg.l_reg
/* 16 bit registers */
#define R_AX gen.A.I16_reg.x_reg
#define R_BX gen.B.I16_reg.x_reg
#define R_CX gen.C.I16_reg.x_reg
#define R_DX gen.D.I16_reg.x_reg
/* 32 bit extended registers */
#define R_EAX gen.A.I32_reg.e_reg
#define R_EBX gen.B.I32_reg.e_reg
#define R_ECX gen.C.I32_reg.e_reg
#define R_EDX gen.D.I32_reg.e_reg
/* special registers */
#define R_SP spc.SP.I16_reg.x_reg
#define R_BP spc.BP.I16_reg.x_reg
#define R_SI spc.SI.I16_reg.x_reg
#define R_DI spc.DI.I16_reg.x_reg
#define R_IP spc.IP.I16_reg.x_reg
#define R_FLG spc.FLAGS
/* special registers */
#define R_SP spc.SP.I16_reg.x_reg
#define R_BP spc.BP.I16_reg.x_reg
#define R_SI spc.SI.I16_reg.x_reg
#define R_DI spc.DI.I16_reg.x_reg
#define R_IP spc.IP.I16_reg.x_reg
#define R_FLG spc.FLAGS
/* special registers */
#define R_ESP spc.SP.I32_reg.e_reg
#define R_EBP spc.BP.I32_reg.e_reg
#define R_ESI spc.SI.I32_reg.e_reg
#define R_EDI spc.DI.I32_reg.e_reg
#define R_EIP spc.IP.I32_reg.e_reg
#define R_EFLG spc.FLAGS
/* segment registers */
#define R_CS seg.CS
#define R_DS seg.DS
#define R_SS seg.SS
#define R_ES seg.ES
#define R_FS seg.FS
#define R_GS seg.GS
/* flag conditions */
#define FB_CF 0x0001 /* CARRY flag */
#define FB_PF 0x0004 /* PARITY flag */
#define FB_AF 0x0010 /* AUX flag */
#define FB_ZF 0x0040 /* ZERO flag */
#define FB_SF 0x0080 /* SIGN flag */
#define FB_TF 0x0100 /* TRAP flag */
#define FB_IF 0x0200 /* INTERRUPT ENABLE flag */
#define FB_DF 0x0400 /* DIR flag */
#define FB_OF 0x0800 /* OVERFLOW flag */
/* 80286 and above always have bit#1 set */
#define F_ALWAYS_ON (0x0002) /* flag bits always on */
/*
* Define a mask for only those flag bits we will ever pass back
* (via PUSHF)
*/
#define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF)
/* following bits masked in to a 16bit quantity */
#define F_CF 0x0001 /* CARRY flag */
#define F_PF 0x0004 /* PARITY flag */
#define F_AF 0x0010 /* AUX flag */
#define F_ZF 0x0040 /* ZERO flag */
#define F_SF 0x0080 /* SIGN flag */
#define F_TF 0x0100 /* TRAP flag */
#define F_IF 0x0200 /* INTERRUPT ENABLE flag */
#define F_DF 0x0400 /* DIR flag */
#define F_OF 0x0800 /* OVERFLOW flag */
#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag))
#define SET_FLAG(flag) (M.x86.R_FLG |= (flag))
#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag))
#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag))
#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0)
#define CONDITIONAL_SET_FLAG(COND,FLAG) \
if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG)
#define F_PF_CALC 0x010000 /* PARITY flag has been calced */
#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */
#define F_SF_CALC 0x040000 /* SIGN flag has been calced */
#define F_ALL_CALC 0xff0000 /* All have been calced */
/*
* Emulator machine state.
* Segment usage control.
*/
#define SYSMODE_SEG_DS_SS 0x00000001
#define SYSMODE_SEGOVR_CS 0x00000002
#define SYSMODE_SEGOVR_DS 0x00000004
#define SYSMODE_SEGOVR_ES 0x00000008
#define SYSMODE_SEGOVR_FS 0x00000010
#define SYSMODE_SEGOVR_GS 0x00000020
#define SYSMODE_SEGOVR_SS 0x00000040
#define SYSMODE_PREFIX_REPE 0x00000080
#define SYSMODE_PREFIX_REPNE 0x00000100
#define SYSMODE_PREFIX_DATA 0x00000200
#define SYSMODE_PREFIX_ADDR 0x00000400
#define SYSMODE_INTR_PENDING 0x10000000
#define SYSMODE_EXTRN_INTR 0x20000000
#define SYSMODE_HALTED 0x40000000
#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \
SYSMODE_SEGOVR_CS | \
SYSMODE_SEGOVR_DS | \
SYSMODE_SEGOVR_ES | \
SYSMODE_SEGOVR_FS | \
SYSMODE_SEGOVR_GS | \
SYSMODE_SEGOVR_SS)
#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \
SYSMODE_SEGOVR_CS | \
SYSMODE_SEGOVR_DS | \
SYSMODE_SEGOVR_ES | \
SYSMODE_SEGOVR_FS | \
SYSMODE_SEGOVR_GS | \
SYSMODE_SEGOVR_SS | \
SYSMODE_PREFIX_DATA | \
SYSMODE_PREFIX_ADDR)
#define INTR_SYNCH 0x1
#define INTR_ASYNCH 0x2
#define INTR_HALTED 0x4
typedef struct {
struct i386_general_regs gen;
struct i386_special_regs spc;
struct i386_segment_regs seg;
/*
* MODE contains information on:
* REPE prefix 2 bits repe,repne
* SEGMENT overrides 5 bits normal,DS,SS,CS,ES
* Delayed flag set 3 bits (zero, signed, parity)
* reserved 6 bits
* interrupt # 8 bits instruction raised interrupt
* BIOS video segregs 4 bits
* Interrupt Pending 1 bits
* Extern interrupt 1 bits
* Halted 1 bits
*/
long mode;
u8 intno;
volatile int intr; /* mask of pending interrupts */
int debug;
#ifdef DEBUG
int check;
u16 saved_ip;
u16 saved_cs;
int enc_pos;
int enc_str_pos;
char decode_buf[32]; /* encoded byte stream */
char decoded_buf[256]; /* disassembled strings */
#endif
} X86EMU_regs;
/****************************************************************************
REMARKS:
Structure maintaining the emulator machine state.
MEMBERS:
x86 - X86 registers
mem_base - Base real mode memory for the emulator
mem_size - Size of the real mode memory block for the emulator
****************************************************************************/
#undef x86
typedef struct {
X86EMU_regs x86;
u8 *mem_base;
u32 mem_size;
void *private;
} X86EMU_sysEnv;
#pragma pack()
/*----------------------------- Global Variables --------------------------*/
#ifdef __cplusplus
extern "C" { /* Use "C" linkage when in C++ mode */
#endif
/* Global emulator machine state.
*
* We keep it global to avoid pointer dereferences in the code for speed.
*/
extern X86EMU_sysEnv _X86EMU_env;
#define M _X86EMU_env
/*-------------------------- Function Prototypes --------------------------*/
/* Function to log information at runtime */
#ifndef __KERNEL__
void printk(const char *fmt, ...);
#endif
#ifdef __cplusplus
} /* End of "C" linkage for C++ */
#endif
#endif /* __X86EMU_REGS_H */
|
1001-study-uboot
|
drivers/bios_emulator/include/x86emu/regs.h
|
C
|
gpl3
| 9,441
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Header file for primitive operation functions.
*
****************************************************************************/
#ifndef __X86EMU_PRIM_OPS_H
#define __X86EMU_PRIM_OPS_H
#ifdef __cplusplus
extern "C" { /* Use "C" linkage when in C++ mode */
#endif
u16 aaa_word (u16 d);
u16 aas_word (u16 d);
u16 aad_word (u16 d);
u16 aam_word (u8 d);
u8 adc_byte (u8 d, u8 s);
u16 adc_word (u16 d, u16 s);
u32 adc_long (u32 d, u32 s);
u8 add_byte (u8 d, u8 s);
u16 add_word (u16 d, u16 s);
u32 add_long (u32 d, u32 s);
u8 and_byte (u8 d, u8 s);
u16 and_word (u16 d, u16 s);
u32 and_long (u32 d, u32 s);
u8 cmp_byte (u8 d, u8 s);
u16 cmp_word (u16 d, u16 s);
u32 cmp_long (u32 d, u32 s);
u8 daa_byte (u8 d);
u8 das_byte (u8 d);
u8 dec_byte (u8 d);
u16 dec_word (u16 d);
u32 dec_long (u32 d);
u8 inc_byte (u8 d);
u16 inc_word (u16 d);
u32 inc_long (u32 d);
u8 or_byte (u8 d, u8 s);
u16 or_word (u16 d, u16 s);
u32 or_long (u32 d, u32 s);
u8 neg_byte (u8 s);
u16 neg_word (u16 s);
u32 neg_long (u32 s);
u8 not_byte (u8 s);
u16 not_word (u16 s);
u32 not_long (u32 s);
u8 rcl_byte (u8 d, u8 s);
u16 rcl_word (u16 d, u8 s);
u32 rcl_long (u32 d, u8 s);
u8 rcr_byte (u8 d, u8 s);
u16 rcr_word (u16 d, u8 s);
u32 rcr_long (u32 d, u8 s);
u8 rol_byte (u8 d, u8 s);
u16 rol_word (u16 d, u8 s);
u32 rol_long (u32 d, u8 s);
u8 ror_byte (u8 d, u8 s);
u16 ror_word (u16 d, u8 s);
u32 ror_long (u32 d, u8 s);
u8 shl_byte (u8 d, u8 s);
u16 shl_word (u16 d, u8 s);
u32 shl_long (u32 d, u8 s);
u8 shr_byte (u8 d, u8 s);
u16 shr_word (u16 d, u8 s);
u32 shr_long (u32 d, u8 s);
u8 sar_byte (u8 d, u8 s);
u16 sar_word (u16 d, u8 s);
u32 sar_long (u32 d, u8 s);
u16 shld_word (u16 d, u16 fill, u8 s);
u32 shld_long (u32 d, u32 fill, u8 s);
u16 shrd_word (u16 d, u16 fill, u8 s);
u32 shrd_long (u32 d, u32 fill, u8 s);
u8 sbb_byte (u8 d, u8 s);
u16 sbb_word (u16 d, u16 s);
u32 sbb_long (u32 d, u32 s);
u8 sub_byte (u8 d, u8 s);
u16 sub_word (u16 d, u16 s);
u32 sub_long (u32 d, u32 s);
void test_byte (u8 d, u8 s);
void test_word (u16 d, u16 s);
void test_long (u32 d, u32 s);
u8 xor_byte (u8 d, u8 s);
u16 xor_word (u16 d, u16 s);
u32 xor_long (u32 d, u32 s);
void imul_byte (u8 s);
void imul_word (u16 s);
void imul_long (u32 s);
void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s);
void mul_byte (u8 s);
void mul_word (u16 s);
void mul_long (u32 s);
void idiv_byte (u8 s);
void idiv_word (u16 s);
void idiv_long (u32 s);
void div_byte (u8 s);
void div_word (u16 s);
void div_long (u32 s);
void ins (int size);
void outs (int size);
u16 mem_access_word (int addr);
void push_word (u16 w);
void push_long (u32 w);
u16 pop_word (void);
u32 pop_long (void);
#ifdef __cplusplus
} /* End of "C" linkage for C++ */
#endif
#endif /* __X86EMU_PRIM_OPS_H */
|
1001-study-uboot
|
drivers/bios_emulator/include/x86emu/prim_ops.h
|
C
|
gpl3
| 4,831
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: Watcom C++ 10.6 or later
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Inline assembler versions of the primitive operand
* functions for faster performance. At the moment this is
* x86 inline assembler, but these functions could be replaced
* with native inline assembler for each supported processor
* platform.
*
****************************************************************************/
#ifndef __X86EMU_PRIM_ASM_H
#define __X86EMU_PRIM_ASM_H
#ifdef __WATCOMC__
#ifndef VALIDATE
#define __HAVE_INLINE_ASSEMBLER__
#endif
u32 get_flags_asm(void);
#pragma aux get_flags_asm = \
"pushf" \
"pop eax" \
value [eax] \
modify exact [eax];
u16 aaa_word_asm(u32 * flags, u16 d);
#pragma aux aaa_word_asm = \
"push [edi]" \
"popf" \
"aaa" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] \
value [ax] \
modify exact [ax];
u16 aas_word_asm(u32 * flags, u16 d);
#pragma aux aas_word_asm = \
"push [edi]" \
"popf" \
"aas" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] \
value [ax] \
modify exact [ax];
u16 aad_word_asm(u32 * flags, u16 d);
#pragma aux aad_word_asm = \
"push [edi]" \
"popf" \
"aad" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] \
value [ax] \
modify exact [ax];
u16 aam_word_asm(u32 * flags, u8 d);
#pragma aux aam_word_asm = \
"push [edi]" \
"popf" \
"aam" \
"pushf" \
"pop [edi]" \
parm [edi] [al] \
value [ax] \
modify exact [ax];
u8 adc_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux adc_byte_asm = \
"push [edi]" \
"popf" \
"adc al,bl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [bl] \
value [al] \
modify exact [al bl];
u16 adc_word_asm(u32 * flags, u16 d, u16 s);
#pragma aux adc_word_asm = \
"push [edi]" \
"popf" \
"adc ax,bx" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [bx] \
value [ax] \
modify exact [ax bx];
u32 adc_long_asm(u32 * flags, u32 d, u32 s);
#pragma aux adc_long_asm = \
"push [edi]" \
"popf" \
"adc eax,ebx" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [ebx] \
value [eax] \
modify exact [eax ebx];
u8 add_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux add_byte_asm = \
"push [edi]" \
"popf" \
"add al,bl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [bl] \
value [al] \
modify exact [al bl];
u16 add_word_asm(u32 * flags, u16 d, u16 s);
#pragma aux add_word_asm = \
"push [edi]" \
"popf" \
"add ax,bx" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [bx] \
value [ax] \
modify exact [ax bx];
u32 add_long_asm(u32 * flags, u32 d, u32 s);
#pragma aux add_long_asm = \
"push [edi]" \
"popf" \
"add eax,ebx" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [ebx] \
value [eax] \
modify exact [eax ebx];
u8 and_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux and_byte_asm = \
"push [edi]" \
"popf" \
"and al,bl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [bl] \
value [al] \
modify exact [al bl];
u16 and_word_asm(u32 * flags, u16 d, u16 s);
#pragma aux and_word_asm = \
"push [edi]" \
"popf" \
"and ax,bx" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [bx] \
value [ax] \
modify exact [ax bx];
u32 and_long_asm(u32 * flags, u32 d, u32 s);
#pragma aux and_long_asm = \
"push [edi]" \
"popf" \
"and eax,ebx" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [ebx] \
value [eax] \
modify exact [eax ebx];
u8 cmp_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux cmp_byte_asm = \
"push [edi]" \
"popf" \
"cmp al,bl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [bl] \
value [al] \
modify exact [al bl];
u16 cmp_word_asm(u32 * flags, u16 d, u16 s);
#pragma aux cmp_word_asm = \
"push [edi]" \
"popf" \
"cmp ax,bx" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [bx] \
value [ax] \
modify exact [ax bx];
u32 cmp_long_asm(u32 * flags, u32 d, u32 s);
#pragma aux cmp_long_asm = \
"push [edi]" \
"popf" \
"cmp eax,ebx" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [ebx] \
value [eax] \
modify exact [eax ebx];
u8 daa_byte_asm(u32 * flags, u8 d);
#pragma aux daa_byte_asm = \
"push [edi]" \
"popf" \
"daa" \
"pushf" \
"pop [edi]" \
parm [edi] [al] \
value [al] \
modify exact [al];
u8 das_byte_asm(u32 * flags, u8 d);
#pragma aux das_byte_asm = \
"push [edi]" \
"popf" \
"das" \
"pushf" \
"pop [edi]" \
parm [edi] [al] \
value [al] \
modify exact [al];
u8 dec_byte_asm(u32 * flags, u8 d);
#pragma aux dec_byte_asm = \
"push [edi]" \
"popf" \
"dec al" \
"pushf" \
"pop [edi]" \
parm [edi] [al] \
value [al] \
modify exact [al];
u16 dec_word_asm(u32 * flags, u16 d);
#pragma aux dec_word_asm = \
"push [edi]" \
"popf" \
"dec ax" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] \
value [ax] \
modify exact [ax];
u32 dec_long_asm(u32 * flags, u32 d);
#pragma aux dec_long_asm = \
"push [edi]" \
"popf" \
"dec eax" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] \
value [eax] \
modify exact [eax];
u8 inc_byte_asm(u32 * flags, u8 d);
#pragma aux inc_byte_asm = \
"push [edi]" \
"popf" \
"inc al" \
"pushf" \
"pop [edi]" \
parm [edi] [al] \
value [al] \
modify exact [al];
u16 inc_word_asm(u32 * flags, u16 d);
#pragma aux inc_word_asm = \
"push [edi]" \
"popf" \
"inc ax" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] \
value [ax] \
modify exact [ax];
u32 inc_long_asm(u32 * flags, u32 d);
#pragma aux inc_long_asm = \
"push [edi]" \
"popf" \
"inc eax" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] \
value [eax] \
modify exact [eax];
u8 or_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux or_byte_asm = \
"push [edi]" \
"popf" \
"or al,bl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [bl] \
value [al] \
modify exact [al bl];
u16 or_word_asm(u32 * flags, u16 d, u16 s);
#pragma aux or_word_asm = \
"push [edi]" \
"popf" \
"or ax,bx" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [bx] \
value [ax] \
modify exact [ax bx];
u32 or_long_asm(u32 * flags, u32 d, u32 s);
#pragma aux or_long_asm = \
"push [edi]" \
"popf" \
"or eax,ebx" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [ebx] \
value [eax] \
modify exact [eax ebx];
u8 neg_byte_asm(u32 * flags, u8 d);
#pragma aux neg_byte_asm = \
"push [edi]" \
"popf" \
"neg al" \
"pushf" \
"pop [edi]" \
parm [edi] [al] \
value [al] \
modify exact [al];
u16 neg_word_asm(u32 * flags, u16 d);
#pragma aux neg_word_asm = \
"push [edi]" \
"popf" \
"neg ax" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] \
value [ax] \
modify exact [ax];
u32 neg_long_asm(u32 * flags, u32 d);
#pragma aux neg_long_asm = \
"push [edi]" \
"popf" \
"neg eax" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] \
value [eax] \
modify exact [eax];
u8 not_byte_asm(u32 * flags, u8 d);
#pragma aux not_byte_asm = \
"push [edi]" \
"popf" \
"not al" \
"pushf" \
"pop [edi]" \
parm [edi] [al] \
value [al] \
modify exact [al];
u16 not_word_asm(u32 * flags, u16 d);
#pragma aux not_word_asm = \
"push [edi]" \
"popf" \
"not ax" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] \
value [ax] \
modify exact [ax];
u32 not_long_asm(u32 * flags, u32 d);
#pragma aux not_long_asm = \
"push [edi]" \
"popf" \
"not eax" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] \
value [eax] \
modify exact [eax];
u8 rcl_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux rcl_byte_asm = \
"push [edi]" \
"popf" \
"rcl al,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [cl] \
value [al] \
modify exact [al cl];
u16 rcl_word_asm(u32 * flags, u16 d, u8 s);
#pragma aux rcl_word_asm = \
"push [edi]" \
"popf" \
"rcl ax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [cl] \
value [ax] \
modify exact [ax cl];
u32 rcl_long_asm(u32 * flags, u32 d, u8 s);
#pragma aux rcl_long_asm = \
"push [edi]" \
"popf" \
"rcl eax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [cl] \
value [eax] \
modify exact [eax cl];
u8 rcr_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux rcr_byte_asm = \
"push [edi]" \
"popf" \
"rcr al,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [cl] \
value [al] \
modify exact [al cl];
u16 rcr_word_asm(u32 * flags, u16 d, u8 s);
#pragma aux rcr_word_asm = \
"push [edi]" \
"popf" \
"rcr ax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [cl] \
value [ax] \
modify exact [ax cl];
u32 rcr_long_asm(u32 * flags, u32 d, u8 s);
#pragma aux rcr_long_asm = \
"push [edi]" \
"popf" \
"rcr eax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [cl] \
value [eax] \
modify exact [eax cl];
u8 rol_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux rol_byte_asm = \
"push [edi]" \
"popf" \
"rol al,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [cl] \
value [al] \
modify exact [al cl];
u16 rol_word_asm(u32 * flags, u16 d, u8 s);
#pragma aux rol_word_asm = \
"push [edi]" \
"popf" \
"rol ax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [cl] \
value [ax] \
modify exact [ax cl];
u32 rol_long_asm(u32 * flags, u32 d, u8 s);
#pragma aux rol_long_asm = \
"push [edi]" \
"popf" \
"rol eax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [cl] \
value [eax] \
modify exact [eax cl];
u8 ror_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux ror_byte_asm = \
"push [edi]" \
"popf" \
"ror al,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [cl] \
value [al] \
modify exact [al cl];
u16 ror_word_asm(u32 * flags, u16 d, u8 s);
#pragma aux ror_word_asm = \
"push [edi]" \
"popf" \
"ror ax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [cl] \
value [ax] \
modify exact [ax cl];
u32 ror_long_asm(u32 * flags, u32 d, u8 s);
#pragma aux ror_long_asm = \
"push [edi]" \
"popf" \
"ror eax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [cl] \
value [eax] \
modify exact [eax cl];
u8 shl_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux shl_byte_asm = \
"push [edi]" \
"popf" \
"shl al,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [cl] \
value [al] \
modify exact [al cl];
u16 shl_word_asm(u32 * flags, u16 d, u8 s);
#pragma aux shl_word_asm = \
"push [edi]" \
"popf" \
"shl ax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [cl] \
value [ax] \
modify exact [ax cl];
u32 shl_long_asm(u32 * flags, u32 d, u8 s);
#pragma aux shl_long_asm = \
"push [edi]" \
"popf" \
"shl eax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [cl] \
value [eax] \
modify exact [eax cl];
u8 shr_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux shr_byte_asm = \
"push [edi]" \
"popf" \
"shr al,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [cl] \
value [al] \
modify exact [al cl];
u16 shr_word_asm(u32 * flags, u16 d, u8 s);
#pragma aux shr_word_asm = \
"push [edi]" \
"popf" \
"shr ax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [cl] \
value [ax] \
modify exact [ax cl];
u32 shr_long_asm(u32 * flags, u32 d, u8 s);
#pragma aux shr_long_asm = \
"push [edi]" \
"popf" \
"shr eax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [cl] \
value [eax] \
modify exact [eax cl];
u8 sar_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux sar_byte_asm = \
"push [edi]" \
"popf" \
"sar al,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [cl] \
value [al] \
modify exact [al cl];
u16 sar_word_asm(u32 * flags, u16 d, u8 s);
#pragma aux sar_word_asm = \
"push [edi]" \
"popf" \
"sar ax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [cl] \
value [ax] \
modify exact [ax cl];
u32 sar_long_asm(u32 * flags, u32 d, u8 s);
#pragma aux sar_long_asm = \
"push [edi]" \
"popf" \
"sar eax,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [cl] \
value [eax] \
modify exact [eax cl];
u16 shld_word_asm(u32 * flags, u16 d, u16 fill, u8 s);
#pragma aux shld_word_asm = \
"push [edi]" \
"popf" \
"shld ax,dx,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [dx] [cl] \
value [ax] \
modify exact [ax dx cl];
u32 shld_long_asm(u32 * flags, u32 d, u32 fill, u8 s);
#pragma aux shld_long_asm = \
"push [edi]" \
"popf" \
"shld eax,edx,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [edx] [cl] \
value [eax] \
modify exact [eax edx cl];
u16 shrd_word_asm(u32 * flags, u16 d, u16 fill, u8 s);
#pragma aux shrd_word_asm = \
"push [edi]" \
"popf" \
"shrd ax,dx,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [dx] [cl] \
value [ax] \
modify exact [ax dx cl];
u32 shrd_long_asm(u32 * flags, u32 d, u32 fill, u8 s);
#pragma aux shrd_long_asm = \
"push [edi]" \
"popf" \
"shrd eax,edx,cl" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [edx] [cl] \
value [eax] \
modify exact [eax edx cl];
u8 sbb_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux sbb_byte_asm = \
"push [edi]" \
"popf" \
"sbb al,bl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [bl] \
value [al] \
modify exact [al bl];
u16 sbb_word_asm(u32 * flags, u16 d, u16 s);
#pragma aux sbb_word_asm = \
"push [edi]" \
"popf" \
"sbb ax,bx" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [bx] \
value [ax] \
modify exact [ax bx];
u32 sbb_long_asm(u32 * flags, u32 d, u32 s);
#pragma aux sbb_long_asm = \
"push [edi]" \
"popf" \
"sbb eax,ebx" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [ebx] \
value [eax] \
modify exact [eax ebx];
u8 sub_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux sub_byte_asm = \
"push [edi]" \
"popf" \
"sub al,bl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [bl] \
value [al] \
modify exact [al bl];
u16 sub_word_asm(u32 * flags, u16 d, u16 s);
#pragma aux sub_word_asm = \
"push [edi]" \
"popf" \
"sub ax,bx" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [bx] \
value [ax] \
modify exact [ax bx];
u32 sub_long_asm(u32 * flags, u32 d, u32 s);
#pragma aux sub_long_asm = \
"push [edi]" \
"popf" \
"sub eax,ebx" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [ebx] \
value [eax] \
modify exact [eax ebx];
void test_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux test_byte_asm = \
"push [edi]" \
"popf" \
"test al,bl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [bl] \
modify exact [al bl];
void test_word_asm(u32 * flags, u16 d, u16 s);
#pragma aux test_word_asm = \
"push [edi]" \
"popf" \
"test ax,bx" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [bx] \
modify exact [ax bx];
void test_long_asm(u32 * flags, u32 d, u32 s);
#pragma aux test_long_asm = \
"push [edi]" \
"popf" \
"test eax,ebx" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [ebx] \
modify exact [eax ebx];
u8 xor_byte_asm(u32 * flags, u8 d, u8 s);
#pragma aux xor_byte_asm = \
"push [edi]" \
"popf" \
"xor al,bl" \
"pushf" \
"pop [edi]" \
parm [edi] [al] [bl] \
value [al] \
modify exact [al bl];
u16 xor_word_asm(u32 * flags, u16 d, u16 s);
#pragma aux xor_word_asm = \
"push [edi]" \
"popf" \
"xor ax,bx" \
"pushf" \
"pop [edi]" \
parm [edi] [ax] [bx] \
value [ax] \
modify exact [ax bx];
u32 xor_long_asm(u32 * flags, u32 d, u32 s);
#pragma aux xor_long_asm = \
"push [edi]" \
"popf" \
"xor eax,ebx" \
"pushf" \
"pop [edi]" \
parm [edi] [eax] [ebx] \
value [eax] \
modify exact [eax ebx];
void imul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s);
#pragma aux imul_byte_asm = \
"push [edi]" \
"popf" \
"imul bl" \
"pushf" \
"pop [edi]" \
"mov [esi],ax" \
parm [edi] [esi] [al] [bl] \
modify exact [esi ax bl];
void imul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s);
#pragma aux imul_word_asm = \
"push [edi]" \
"popf" \
"imul bx" \
"pushf" \
"pop [edi]" \
"mov [esi],ax" \
"mov [ecx],dx" \
parm [edi] [esi] [ecx] [ax] [bx]\
modify exact [esi edi ax bx dx];
void imul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s);
#pragma aux imul_long_asm = \
"push [edi]" \
"popf" \
"imul ebx" \
"pushf" \
"pop [edi]" \
"mov [esi],eax" \
"mov [ecx],edx" \
parm [edi] [esi] [ecx] [eax] [ebx] \
modify exact [esi edi eax ebx edx];
void mul_byte_asm(u32 * flags, u16 * ax, u8 d, u8 s);
#pragma aux mul_byte_asm = \
"push [edi]" \
"popf" \
"mul bl" \
"pushf" \
"pop [edi]" \
"mov [esi],ax" \
parm [edi] [esi] [al] [bl] \
modify exact [esi ax bl];
void mul_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 d, u16 s);
#pragma aux mul_word_asm = \
"push [edi]" \
"popf" \
"mul bx" \
"pushf" \
"pop [edi]" \
"mov [esi],ax" \
"mov [ecx],dx" \
parm [edi] [esi] [ecx] [ax] [bx]\
modify exact [esi edi ax bx dx];
void mul_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 d, u32 s);
#pragma aux mul_long_asm = \
"push [edi]" \
"popf" \
"mul ebx" \
"pushf" \
"pop [edi]" \
"mov [esi],eax" \
"mov [ecx],edx" \
parm [edi] [esi] [ecx] [eax] [ebx] \
modify exact [esi edi eax ebx edx];
void idiv_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s);
#pragma aux idiv_byte_asm = \
"push [edi]" \
"popf" \
"idiv bl" \
"pushf" \
"pop [edi]" \
"mov [esi],al" \
"mov [ecx],ah" \
parm [edi] [esi] [ecx] [ax] [bl]\
modify exact [esi edi ax bl];
void idiv_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s);
#pragma aux idiv_word_asm = \
"push [edi]" \
"popf" \
"idiv bx" \
"pushf" \
"pop [edi]" \
"mov [esi],ax" \
"mov [ecx],dx" \
parm [edi] [esi] [ecx] [ax] [dx] [bx]\
modify exact [esi edi ax dx bx];
void idiv_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s);
#pragma aux idiv_long_asm = \
"push [edi]" \
"popf" \
"idiv ebx" \
"pushf" \
"pop [edi]" \
"mov [esi],eax" \
"mov [ecx],edx" \
parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
modify exact [esi edi eax edx ebx];
void div_byte_asm(u32 * flags, u8 * al, u8 * ah, u16 d, u8 s);
#pragma aux div_byte_asm = \
"push [edi]" \
"popf" \
"div bl" \
"pushf" \
"pop [edi]" \
"mov [esi],al" \
"mov [ecx],ah" \
parm [edi] [esi] [ecx] [ax] [bl]\
modify exact [esi edi ax bl];
void div_word_asm(u32 * flags, u16 * ax, u16 * dx, u16 dlo, u16 dhi, u16 s);
#pragma aux div_word_asm = \
"push [edi]" \
"popf" \
"div bx" \
"pushf" \
"pop [edi]" \
"mov [esi],ax" \
"mov [ecx],dx" \
parm [edi] [esi] [ecx] [ax] [dx] [bx]\
modify exact [esi edi ax dx bx];
void div_long_asm(u32 * flags, u32 * eax, u32 * edx, u32 dlo, u32 dhi, u32 s);
#pragma aux div_long_asm = \
"push [edi]" \
"popf" \
"div ebx" \
"pushf" \
"pop [edi]" \
"mov [esi],eax" \
"mov [ecx],edx" \
parm [edi] [esi] [ecx] [eax] [edx] [ebx]\
modify exact [esi edi eax edx ebx];
#endif
#endif /* __X86EMU_PRIM_ASM_H */
|
1001-study-uboot
|
drivers/bios_emulator/include/x86emu/prim_asm.h
|
C
|
gpl3
| 33,816
|
/****************************************************************************
*
* Realmode X86 Emulator Library
*
* Copyright (C) 1991-2004 SciTech Software, Inc.
* Copyright (C) David Mosberger-Tang
* Copyright (C) 1999 Egbert Eich
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Header file for operand decoding functions.
*
****************************************************************************/
#ifndef __X86EMU_OPS_H
#define __X86EMU_OPS_H
extern void (*x86emu_optab[0x100])(u8 op1);
extern void (*x86emu_optab2[0x100])(u8 op2);
#endif /* __X86EMU_OPS_H */
|
1001-study-uboot
|
drivers/bios_emulator/include/x86emu/ops.h
|
C
|
gpl3
| 1,957
|
/****************************************************************************
*
* BIOS emulator and interface
* to Realmode X86 Emulator Library
*
* Copyright (C) 1996-1999 SciTech Software, Inc.
*
* ========================================================================
*
* Permission to use, copy, modify, distribute, and sell this software and
* its documentation for any purpose is hereby granted without fee,
* provided that the above copyright notice appear in all copies and that
* both that copyright notice and this permission notice appear in
* supporting documentation, and that the name of the authors not be used
* in advertising or publicity pertaining to distribution of the software
* without specific, written prior permission. The authors makes no
* representations about the suitability of this software for any purpose.
* It is provided "as is" without express or implied warranty.
*
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*
* ========================================================================
*
* Language: ANSI C
* Environment: Any
* Developer: Kendall Bennett
*
* Description: Header file for the real mode x86 BIOS emulator, which is
* used to warmboot any number of VGA compatible PCI/AGP
* controllers under any OS, on any processor family that
* supports PCI. We also allow the user application to call
* real mode BIOS functions and Int 10h functions (including
* the VESA BIOS).
*
****************************************************************************/
#ifndef __BIOSEMU_H
#define __BIOSEMU_H
#ifdef __KERNEL__
#include "x86emu.h"
#else
#include "x86emu.h"
#include "pmapi.h"
#include "pcilib.h"
#endif
/*---------------------- Macros and type definitions ----------------------*/
#pragma pack(1)
#ifndef __KERNEL__
/****************************************************************************
REMARKS:
Data structure used to describe the details specific to a particular VGA
controller. This information is used to allow the VGA controller to be
swapped on the fly within the BIOS emulator.
HEADER:
biosemu.h
MEMBERS:
pciInfo - PCI device information block for the controller
BIOSImage - Pointer to a read/write copy of the BIOS image
BIOSImageLen - Length of the BIOS image
LowMem - Copy of key low memory areas
****************************************************************************/
typedef struct {
PCIDeviceInfo *pciInfo;
void *BIOSImage;
ulong BIOSImageLen;
uchar LowMem[1536];
} BE_VGAInfo;
#else
/****************************************************************************
REMARKS:
Data structure used to describe the details for the BIOS emulator system
environment as used by the X86 emulator library.
HEADER:
biosemu.h
MEMBERS:
vgaInfo - VGA BIOS information structure
biosmem_base - Base of the BIOS image
biosmem_limit - Limit of the BIOS image
busmem_base - Base of the VGA bus memory
****************************************************************************/
typedef struct {
int function;
int device;
int bus;
u32 VendorID;
u32 DeviceID;
pci_dev_t pcidev;
void *BIOSImage;
u32 BIOSImageLen;
u8 LowMem[1536];
} BE_VGAInfo;
#endif /* __KERNEL__ */
#define CRT_C 24 /* 24 CRT Controller Registers */
#define ATT_C 21 /* 21 Attribute Controller Registers */
#define GRA_C 9 /* 9 Graphics Controller Registers */
#define SEQ_C 5 /* 5 Sequencer Registers */
#define PAL_C 768 /* 768 Palette Registers */
/****************************************************************************
REMARKS:
Data structure used to describe the details for the BIOS emulator system
environment as used by the X86 emulator library.
HEADER:
biosemu.h
MEMBERS:
vgaInfo - VGA BIOS information structure
biosmem_base - Base of the BIOS image
biosmem_limit - Limit of the BIOS image
busmem_base - Base of the VGA bus memory
timer - Timer used to emulate PC timer ports
timer0 - Latched value for timer 0
timer0Latched - True if timer 0 value was just latched
timer2 - Current value for timer 2
emulateVGA - True to emulate VGA I/O and memory accesses
****************************************************************************/
typedef struct {
BE_VGAInfo vgaInfo;
ulong biosmem_base;
ulong biosmem_limit;
ulong busmem_base;
u32 timer0;
int timer0Latched;
u32 timer1;
int timer1Latched;
u32 timer2;
int timer2Latched;
int emulateVGA;
u8 emu61;
u8 emu70;
int flipFlop3C0;
u32 configAddress;
u8 emu3C0;
u8 emu3C1[ATT_C];
u8 emu3C2;
u8 emu3C4;
u8 emu3C5[SEQ_C];
u8 emu3C6;
uint emu3C7;
uint emu3C8;
u8 emu3C9[PAL_C];
u8 emu3CE;
u8 emu3CF[GRA_C];
u8 emu3D4;
u8 emu3D5[CRT_C];
u8 emu3DA;
} BE_sysEnv;
#ifdef __KERNEL__
/* Define some types when compiling for the Linux kernel that normally
* come from the SciTech PM library.
*/
/****************************************************************************
REMARKS:
Structure describing the 32-bit extended x86 CPU registers
HEADER:
pmapi.h
MEMBERS:
eax - Value of the EAX register
ebx - Value of the EBX register
ecx - Value of the ECX register
edx - Value of the EDX register
esi - Value of the ESI register
edi - Value of the EDI register
cflag - Value of the carry flag
****************************************************************************/
typedef struct {
u32 eax;
u32 ebx;
u32 ecx;
u32 edx;
u32 esi;
u32 edi;
u32 cflag;
} RMDWORDREGS;
/****************************************************************************
REMARKS:
Structure describing the 16-bit x86 CPU registers
HEADER:
pmapi.h
MEMBERS:
ax - Value of the AX register
bx - Value of the BX register
cx - Value of the CX register
dx - Value of the DX register
si - Value of the SI register
di - Value of the DI register
cflag - Value of the carry flag
****************************************************************************/
#ifdef __BIG_ENDIAN__
typedef struct {
u16 ax_hi, ax;
u16 bx_hi, bx;
u16 cx_hi, cx;
u16 dx_hi, dx;
u16 si_hi, si;
u16 di_hi, di;
u16 cflag_hi, cflag;
} RMWORDREGS;
#else
typedef struct {
u16 ax, ax_hi;
u16 bx, bx_hi;
u16 cx, cx_hi;
u16 dx, dx_hi;
u16 si, si_hi;
u16 di, di_hi;
u16 cflag, cflag_hi;
} RMWORDREGS;
#endif
/****************************************************************************
REMARKS:
Structure describing the 8-bit x86 CPU registers
HEADER:
pmapi.h
MEMBERS:
al - Value of the AL register
ah - Value of the AH register
bl - Value of the BL register
bh - Value of the BH register
cl - Value of the CL register
ch - Value of the CH register
dl - Value of the DL register
dh - Value of the DH register
****************************************************************************/
#ifdef __BIG_ENDIAN__
typedef struct {
u16 ax_hi;
u8 ah, al;
u16 bx_hi;
u8 bh, bl;
u16 cx_hi;
u8 ch, cl;
u16 dx_hi;
u8 dh, dl;
} RMBYTEREGS;
#else
typedef struct {
u8 al;
u8 ah;
u16 ax_hi;
u8 bl;
u8 bh;
u16 bx_hi;
u8 cl;
u8 ch;
u16 cx_hi;
u8 dl;
u8 dh;
u16 dx_hi;
} RMBYTEREGS;
#endif
/****************************************************************************
REMARKS:
Structure describing all the x86 CPU registers
HEADER:
pmapi.h
MEMBERS:
e - Member to access registers as 32-bit values
x - Member to access registers as 16-bit values
h - Member to access registers as 8-bit values
****************************************************************************/
typedef union {
RMDWORDREGS e;
RMWORDREGS x;
RMBYTEREGS h;
} RMREGS;
/****************************************************************************
REMARKS:
Structure describing all the x86 segment registers
HEADER:
pmapi.h
MEMBERS:
es - ES segment register
cs - CS segment register
ss - SS segment register
ds - DS segment register
fs - FS segment register
gs - GS segment register
****************************************************************************/
typedef struct {
u16 es;
u16 cs;
u16 ss;
u16 ds;
u16 fs;
u16 gs;
} RMSREGS;
#endif /* __KERNEL__ */
#ifndef __KERNEL__
/****************************************************************************
REMARKS:
Structure defining all the BIOS Emulator API functions as exported from
the Binary Portable DLL.
{secret}
****************************************************************************/
typedef struct {
ulong dwSize;
ibool(PMAPIP BE_init) (u32 debugFlags, int memSize, BE_VGAInfo * info);
void (PMAPIP BE_setVGA) (BE_VGAInfo * info);
void (PMAPIP BE_getVGA) (BE_VGAInfo * info);
void *(PMAPIP BE_mapRealPointer) (uint r_seg, uint r_off);
void *(PMAPIP BE_getVESABuf) (uint * len, uint * rseg, uint * roff);
void (PMAPIP BE_callRealMode) (uint seg, uint off, RMREGS * regs,
RMSREGS * sregs);
int (PMAPIP BE_int86) (int intno, RMREGS * in, RMREGS * out);
int (PMAPIP BE_int86x) (int intno, RMREGS * in, RMREGS * out,
RMSREGS * sregs);
void *reserved1;
void (PMAPIP BE_exit) (void);
} BE_exports;
/****************************************************************************
REMARKS:
Function pointer type for the Binary Portable DLL initialisation entry point.
{secret}
****************************************************************************/
typedef BE_exports *(PMAPIP BE_initLibrary_t) (PM_imports * PMImp);
#endif
#pragma pack()
/*---------------------------- Global variables ---------------------------*/
#ifdef __cplusplus
extern "C" { /* Use "C" linkage when in C++ mode */
#endif
/* {secret} Global BIOS emulator system environment */
extern BE_sysEnv _BE_env;
/*-------------------------- Function Prototypes --------------------------*/
/* BIOS emulator library entry points */
int X86API BE_init(u32 debugFlags, int memSize, BE_VGAInfo * info,
int shared);
void X86API BE_setVGA(BE_VGAInfo * info);
void X86API BE_getVGA(BE_VGAInfo * info);
void X86API BE_setDebugFlags(u32 debugFlags);
void *X86API BE_mapRealPointer(uint r_seg, uint r_off);
void *X86API BE_getVESABuf(uint * len, uint * rseg, uint * roff);
void X86API BE_callRealMode(uint seg, uint off, RMREGS * regs,
RMSREGS * sregs);
int X86API BE_int86(int intno, RMREGS * in, RMREGS * out);
int X86API BE_int86x(int intno, RMREGS * in, RMREGS * out,
RMSREGS * sregs);
void X86API BE_exit(void);
#ifdef __cplusplus
} /* End of "C" linkage for C++ */
#endif
#endif /* __BIOSEMU_H */
|
1001-study-uboot
|
drivers/bios_emulator/include/biosemu.h
|
C
|
gpl3
| 11,050
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/*
* Configuration support for Xilinx Virtex2 devices. Based
* on spartan2.c (Rich Ireland, rireland@enterasys.com).
*/
#include <common.h>
#include <virtex2.h>
#if 0
#define FPGA_DEBUG
#endif
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/*
* If the SelectMap interface can be overrun by the processor, define
* CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board configuration
* file and add board-specific support for checking BUSY status. By default,
* assume that the SelectMap interface cannot be overrun.
*/
#ifndef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_CHECK_BUSY
#endif
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif
#ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#endif
/*
* Don't allow config cycle to be interrupted
*/
#ifndef CONFIG_SYS_FPGA_CHECK_CTRLC
#undef CONFIG_SYS_FPGA_CHECK_CTRLC
#endif
/*
* Check for errors during configuration by default
*/
#ifndef CONFIG_SYS_FPGA_CHECK_ERROR
#define CONFIG_SYS_FPGA_CHECK_ERROR
#endif
/*
* The default timeout in mS for INIT_B to deassert after PROG_B has
* been deasserted. Per the latest Virtex II Handbook (page 347), the
* max time from PORG_B deassertion to INIT_B deassertion is 4uS per
* data frame for the XC2V8000. The XC2V8000 has 2860 data frames
* which yields 11.44 mS. So let's make it bigger in order to handle
* an XC2V1000, if anyone can ever get ahold of one.
*/
#ifndef CONFIG_SYS_FPGA_WAIT_INIT
#define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ/2 /* 500 ms */
#endif
/*
* The default timeout for waiting for BUSY to deassert during configuration.
* This is normally not necessary since for most reasonable configuration
* clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
*/
#ifndef CONFIG_SYS_FPGA_WAIT_BUSY
#define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ/200 /* 5 ms*/
#endif
/* Default timeout for waiting for FPGA to enter operational mode after
* configuration data has been written.
*/
#ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
#define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */
#endif
static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
ret_val = Virtex2_ss_load (desc, buf, bsize);
break;
case slave_selectmap:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
ret_val = Virtex2_ssm_load (desc, buf, bsize);
break;
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
ret_val = Virtex2_ss_dump (desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
ret_val = Virtex2_ssm_dump (desc, buf, bsize);
break;
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int Virtex2_info (Xilinx_desc * desc)
{
return FPGA_SUCCESS;
}
/*
* Virtex-II Slave SelectMap configuration loader. Configuration via
* SelectMap is as follows:
* 1. Set the FPGA's PROG_B line low.
* 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
* 3. Write data to the SelectMap port. If INIT_B goes low at any time
* this process, a configuration error (most likely CRC failure) has
* ocurred. At this point a status word may be read from the
* SelectMap interface to determine the source of the problem (You
* could, for instance, put this in your 'abort' function handler).
* 4. After all data has been written, test the state of the FPGA
* INIT_B and DONE lines. If both are high, configuration has
* succeeded. Congratulations!
*/
static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
__FUNCTION__, __LINE__, fn);
if (fn) {
size_t bytecount = 0;
unsigned char *data = (unsigned char *) buf;
int cookie = desc->cookie;
unsigned long ts;
/* Gotta split this one up (so the stack won't blow??) */
PRINTF ("%s:%d: Function Table:\n"
" base 0x%p\n"
" struct 0x%p\n"
" pre 0x%p\n"
" prog 0x%p\n"
" init 0x%p\n"
" error 0x%p\n",
__FUNCTION__, __LINE__,
&fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
PRINTF (" clock 0x%p\n"
" cs 0x%p\n"
" write 0x%p\n"
" rdata 0x%p\n"
" wdata 0x%p\n"
" busy 0x%p\n"
" abort 0x%p\n"
" post 0x%p\n\n",
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
fn->busy, fn->abort, fn->post);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Initializing FPGA Device %d...\n", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
if (*fn->pre) {
(*fn->pre) (cookie);
}
/*
* Assert the program line. The minimum pulse width for
* Virtex II devices is 300 nS (Tprogram parameter in datasheet).
* There is no maximum value for the pulse width. Check to make
* sure that INIT_B goes low after assertion of PROG_B
*/
(*fn->pgm) (TRUE, TRUE, cookie);
udelay (10);
ts = get_timer (0);
do {
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to assert.\n", __FUNCTION__, __LINE__,
CONFIG_SYS_FPGA_WAIT_INIT);
(*fn->abort) (cookie);
return FPGA_FAIL;
}
} while (!(*fn->init) (cookie));
(*fn->pgm) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie);
/*
* Start a timer and wait for INIT_B to go high
*/
ts = get_timer (0);
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
printf ("%s:%d: ** Timeout after %d ticks waiting for INIT"
" to deassert.\n", __FUNCTION__, __LINE__,
CONFIG_SYS_FPGA_WAIT_INIT);
(*fn->abort) (cookie);
return FPGA_FAIL;
}
} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
(*fn->wr) (TRUE, TRUE, cookie);
(*fn->cs) (TRUE, TRUE, cookie);
udelay (10000);
/*
* Load the data byte by byte
*/
while (bytecount < bsize) {
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
if (ctrlc ()) {
(*fn->abort) (cookie);
return FPGA_FAIL;
}
#endif
if ((*fn->done) (cookie) == FPGA_SUCCESS) {
PRINTF ("%s:%d:done went active early, bytecount = %d\n",
__FUNCTION__, __LINE__, bytecount);
break;
}
#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
if ((*fn->init) (cookie)) {
printf ("\n%s:%d: ** Error: INIT asserted during"
" configuration\n", __FUNCTION__, __LINE__);
printf ("%d = buffer offset, %d = buffer size\n",
bytecount, bsize);
(*fn->abort) (cookie);
return FPGA_FAIL;
}
#endif
(*fn->wdata) (data[bytecount++], TRUE, cookie);
CONFIG_FPGA_DELAY ();
/*
* Cycle the clock pin
*/
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie);
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer (0);
while ((*fn->busy) (cookie)) {
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
printf ("%s:%d: ** Timeout after %d ticks waiting for"
" BUSY to deassert\n",
__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_BUSY);
(*fn->abort) (cookie);
return FPGA_FAIL;
}
}
#endif
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.');
#endif
}
/*
* Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
*/
CONFIG_FPGA_DELAY ();
(*fn->cs) (FALSE, TRUE, cookie);
(*fn->wr) (FALSE, TRUE, cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n');
#endif
/*
* Check for successful configuration. FPGA INIT_B and DONE should
* both be high upon successful configuration.
*/
ts = get_timer (0);
ret_val = FPGA_SUCCESS;
while (((*fn->done) (cookie) == FPGA_FAIL) || (*fn->init) (cookie)) {
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
printf ("%s:%d: ** Timeout after %d ticks waiting for DONE to"
"assert and INIT to deassert\n",
__FUNCTION__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
(*fn->abort) (cookie);
ret_val = FPGA_FAIL;
break;
}
}
if (ret_val == FPGA_SUCCESS) {
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Initialization of FPGA device %d complete\n", cookie);
#endif
/*
* Run the post configuration function if there is one.
*/
if (*fn->post) {
(*fn->post) (cookie);
}
} else {
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("** Initialization of FPGA device %d FAILED\n",
cookie);
#endif
}
} else {
printf ("%s:%d: NULL Interface function table!\n",
__FUNCTION__, __LINE__);
}
return ret_val;
}
/*
* Read the FPGA configuration data
*/
static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
size_t bytecount = 0;
int cookie = desc->cookie;
printf ("Starting Dump of FPGA Device %d...\n", cookie);
(*fn->cs) (TRUE, TRUE, cookie);
(*fn->clk) (TRUE, TRUE, cookie);
while (bytecount < bsize) {
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
if (ctrlc ()) {
(*fn->abort) (cookie);
return FPGA_FAIL;
}
#endif
/*
* Cycle the clock and read the data
*/
(*fn->clk) (FALSE, TRUE, cookie);
(*fn->clk) (TRUE, TRUE, cookie);
(*fn->rdata) (&(data[bytecount++]), cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.');
#endif
}
/*
* Deassert CS_B and cycle the clock to deselect the device.
*/
(*fn->cs) (FALSE, FALSE, cookie);
(*fn->clk) (FALSE, TRUE, cookie);
(*fn->clk) (TRUE, TRUE, cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n');
#endif
puts ("Done.\n");
} else {
printf ("%s:%d: NULL Interface function table!\n",
__FUNCTION__, __LINE__);
}
return ret_val;
}
static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
}
static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
return FPGA_FAIL;
}
/* vim: set ts=4 tw=78: */
|
1001-study-uboot
|
drivers/fpga/virtex2.c
|
C
|
gpl3
| 11,949
|
/*
* (C) Copyright 2007
* Eran Liberty, Extricom , eran.liberty@gmail.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h> /* core U-Boot definitions */
#include <altera.h>
int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
int isSerial, int isSecure);
int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);
/****************************************************************/
/* Stratix II Generic Implementation */
int StratixII_load (Altera_desc * desc, void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0);
break;
case fast_passive_parallel:
ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0);
break;
case fast_passive_parallel_security:
ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
desc->iface);
}
return ret_val;
}
int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
case fast_passive_parallel:
case fast_passive_parallel_security:
ret_val = StratixII_ps_fpp_dump (desc, buf, bsize);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
desc->iface);
}
return ret_val;
}
int StratixII_info (Altera_desc * desc)
{
return FPGA_SUCCESS;
}
int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize)
{
printf ("Stratix II Fast Passive Parallel dump is not implemented\n");
return FPGA_FAIL;
}
int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
int isSerial, int isSecure)
{
altera_board_specific_func *fns;
int cookie;
int ret_val = FPGA_FAIL;
int bytecount;
char *buff = buf;
int i;
if (!desc) {
printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__);
return FPGA_FAIL;
}
if (!buff) {
printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__);
return FPGA_FAIL;
}
if (!bsize) {
printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__);
return FPGA_FAIL;
}
if (!desc->iface_fns) {
printf
("%s(%d) Altera_desc function interface table is missing\n",
__FUNCTION__, __LINE__);
return FPGA_FAIL;
}
fns = (altera_board_specific_func *) (desc->iface_fns);
cookie = desc->cookie;
if (!
(fns->config && fns->status && fns->done && fns->data
&& fns->abort)) {
printf
("%s(%d) Missing some function in the function interface table\n",
__FUNCTION__, __LINE__);
return FPGA_FAIL;
}
/* 1. give board specific a chance to do anything before we start */
if (fns->pre) {
if ((ret_val = fns->pre (cookie)) < 0) {
return ret_val;
}
}
/* from this point on we must fail gracfully by calling lower layer abort */
/* 2. Strat burn cycle by deasserting config for t_CFG and waiting t_CF2CK after reaserted */
fns->config (0, 1, cookie);
udelay (5); /* nCONFIG low pulse width 2usec */
fns->config (1, 1, cookie);
udelay (100); /* nCONFIG high to first rising edge on DCLK */
/* 3. Start the Data cycle with clk deasserted */
bytecount = 0;
fns->clk (0, 1, cookie);
printf ("loading to fpga ");
while (bytecount < bsize) {
/* 3.1 check stratix has not signaled us an error */
if (fns->status (cookie) != 1) {
printf
("\n%s(%d) Stratix failed (byte transfered till failure 0x%x)\n",
__FUNCTION__, __LINE__, bytecount);
fns->abort (cookie);
return FPGA_FAIL;
}
if (isSerial) {
int i;
uint8_t data = buff[bytecount++];
for (i = 0; i < 8; i++) {
/* 3.2(ps) put data on the bus */
fns->data ((data >> i) & 1, 1, cookie);
/* 3.3(ps) clock once */
fns->clk (1, 1, cookie);
fns->clk (0, 1, cookie);
}
} else {
/* 3.2(fpp) put data on the bus */
fns->data (buff[bytecount++], 1, cookie);
/* 3.3(fpp) clock once */
fns->clk (1, 1, cookie);
fns->clk (0, 1, cookie);
/* 3.4(fpp) for secure cycle push 3 more clocks */
for (i = 0; isSecure && i < 3; i++) {
fns->clk (1, 1, cookie);
fns->clk (0, 1, cookie);
}
}
/* 3.5 while clk is deasserted it is safe to print some progress indication */
if ((bytecount % (bsize / 100)) == 0) {
printf ("\b\b\b%02d\%", bytecount * 100 / bsize);
}
}
/* 4. Set one last clock and check conf done signal */
fns->clk (1, 1, cookie);
udelay (100);
if (!fns->done (cookie)) {
printf (" error!.\n");
fns->abort (cookie);
return FPGA_FAIL;
} else {
printf ("\b\b\b done.\n");
}
/* 5. call lower layer post configuration */
if (fns->post) {
if ((ret_val = fns->post (cookie)) < 0) {
fns->abort (cookie);
return ret_val;
}
}
return FPGA_SUCCESS;
}
|
1001-study-uboot
|
drivers/fpga/stratixII.c
|
C
|
gpl3
| 5,626
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/*
* Generic FPGA support
*/
#include <common.h> /* core U-Boot definitions */
#include <xilinx.h> /* xilinx specific definitions */
#include <altera.h> /* altera specific definitions */
#include <lattice.h>
#if 0
#define FPGA_DEBUG /* define FPGA_DEBUG to get debug messages */
#endif
/* Local definitions */
#ifndef CONFIG_MAX_FPGA_DEVICES
#define CONFIG_MAX_FPGA_DEVICES 5
#endif
/* Enable/Disable debug console messages */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/* Local static data */
static int next_desc = FPGA_INVALID_DEVICE;
static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
/* Local static functions */
static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum );
static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn );
static int fpga_dev_info( int devnum );
/* ------------------------------------------------------------------------- */
/* fpga_no_sup
* 'no support' message function
*/
static void fpga_no_sup( char *fn, char *msg )
{
if ( fn && msg ) {
printf( "%s: No support for %s.\n", fn, msg);
} else if ( msg ) {
printf( "No support for %s.\n", msg);
} else {
printf( "No FPGA suport!\n");
}
}
/* fpga_get_desc
* map a device number to a descriptor
*/
static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_get_desc( int devnum )
{
fpga_desc *desc = (fpga_desc * )NULL;
if (( devnum >= 0 ) && (devnum < next_desc )) {
desc = &desc_table[devnum];
PRINTF( "%s: found fpga descriptor #%d @ 0x%p\n",
__FUNCTION__, devnum, desc );
}
return desc;
}
/* fpga_validate
* generic parameter checking code
*/
static __attribute__((__const__)) fpga_desc * __attribute__((__const__)) fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn )
{
fpga_desc * desc = fpga_get_desc( devnum );
if ( !desc ) {
printf( "%s: Invalid device number %d\n", fn, devnum );
}
if ( !buf ) {
printf( "%s: Null buffer.\n", fn );
return (fpga_desc * const)NULL;
}
return desc;
}
/* fpga_dev_info
* generic multiplexing code
*/
static int fpga_dev_info( int devnum )
{
int ret_val = FPGA_FAIL; /* assume failure */
const fpga_desc * const desc = fpga_get_desc( devnum );
if ( desc ) {
PRINTF( "%s: Device Descriptor @ 0x%p\n",
__FUNCTION__, desc->devdesc );
switch ( desc->devtype ) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
ret_val = xilinx_info( desc->devdesc );
#else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
ret_val = altera_info( desc->devdesc );
#else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
printf("Lattice Device\nDescriptor @ 0x%p\n", desc);
ret_val = lattice_info(desc->devdesc);
#else
fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
#endif
break;
default:
printf( "%s: Invalid or unsupported device type %d\n",
__FUNCTION__, desc->devtype );
}
} else {
printf( "%s: Invalid device number %d\n",
__FUNCTION__, devnum );
}
return ret_val;
}
/* ------------------------------------------------------------------------- */
/* fgpa_init is usually called from misc_init_r() and MUST be called
* before any of the other fpga functions are used.
*/
void fpga_init(void)
{
next_desc = 0;
memset( desc_table, 0, sizeof(desc_table));
PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA );
}
/* fpga_count
* Basic interface function to get the current number of devices available.
*/
int fpga_count( void )
{
return next_desc;
}
/* fpga_add
* Add the device descriptor to the device table.
*/
int fpga_add( fpga_type devtype, void *desc )
{
int devnum = FPGA_INVALID_DEVICE;
if ( next_desc < 0 ) {
printf( "%s: FPGA support not initialized!\n", __FUNCTION__ );
} else if (( devtype > fpga_min_type ) && ( devtype < fpga_undefined )) {
if ( desc ) {
if ( next_desc < CONFIG_MAX_FPGA_DEVICES ) {
devnum = next_desc;
desc_table[next_desc].devtype = devtype;
desc_table[next_desc++].devdesc = desc;
} else {
printf( "%s: Exceeded Max FPGA device count\n", __FUNCTION__ );
}
} else {
printf( "%s: NULL device descriptor\n", __FUNCTION__ );
}
} else {
printf( "%s: Unsupported FPGA type %d\n", __FUNCTION__, devtype );
}
return devnum;
}
/*
* Generic multiplexing code
*/
int fpga_load(int devnum, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume failure */
fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
if ( desc ) {
switch ( desc->devtype ) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_load( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_load( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
ret_val = lattice_load(desc->devdesc, buf, bsize);
#else
fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
#endif
break;
default:
printf( "%s: Invalid or unsupported device type %d\n",
__FUNCTION__, desc->devtype );
}
}
return ret_val;
}
/* fpga_dump
* generic multiplexing code
*/
int fpga_dump(int devnum, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume failure */
fpga_desc * desc = fpga_validate( devnum, buf, bsize, (char *)__FUNCTION__ );
if ( desc ) {
switch ( desc->devtype ) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_dump( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_dump( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#endif
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
ret_val = lattice_dump(desc->devdesc, buf, bsize);
#else
fpga_no_sup( (char *)__FUNCTION__, "Lattice devices" );
#endif
break;
default:
printf( "%s: Invalid or unsupported device type %d\n",
__FUNCTION__, desc->devtype );
}
}
return ret_val;
}
/* fpga_info
* front end to fpga_dev_info. If devnum is invalid, report on all
* available devices.
*/
int fpga_info( int devnum )
{
if ( devnum == FPGA_INVALID_DEVICE ) {
if ( next_desc > 0 ) {
int dev;
for ( dev = 0; dev < next_desc; dev++ ) {
fpga_dev_info( dev );
}
return FPGA_SUCCESS;
} else {
printf( "%s: No FPGA devices available.\n", __FUNCTION__ );
return FPGA_FAIL;
}
}
else return fpga_dev_info( devnum );
}
/* ------------------------------------------------------------------------- */
|
1001-study-uboot
|
drivers/fpga/fpga.c
|
C
|
gpl3
| 8,107
|
/*
* (C) Copyright 2003
* Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/*
* Altera FPGA support
*/
#include <common.h>
#include <ACEX1K.h>
#include <stratixII.h>
/* Define FPGA_DEBUG to get debug printf's */
/* #define FPGA_DEBUG */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/* Local Static Functions */
static int altera_validate (Altera_desc * desc, const char *fn);
/* ------------------------------------------------------------------------- */
int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
if (!altera_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else {
switch (desc->family) {
case Altera_ACEX1K:
case Altera_CYC2:
#if defined(CONFIG_FPGA_ACEX1K)
PRINTF ("%s: Launching the ACEX1K Loader...\n",
__FUNCTION__);
ret_val = ACEX1K_load (desc, buf, bsize);
#elif defined(CONFIG_FPGA_CYCLON2)
PRINTF ("%s: Launching the CYCLONE II Loader...\n",
__FUNCTION__);
ret_val = CYC2_load (desc, buf, bsize);
#else
printf ("%s: No support for ACEX1K devices.\n",
__FUNCTION__);
#endif
break;
#if defined(CONFIG_FPGA_STRATIX_II)
case Altera_StratixII:
PRINTF ("%s: Launching the Stratix II Loader...\n",
__FUNCTION__);
ret_val = StratixII_load (desc, buf, bsize);
break;
#endif
default:
printf ("%s: Unsupported family type, %d\n",
__FUNCTION__, desc->family);
}
}
return ret_val;
}
int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
if (!altera_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else {
switch (desc->family) {
case Altera_ACEX1K:
#if defined(CONFIG_FPGA_ACEX)
PRINTF ("%s: Launching the ACEX1K Reader...\n",
__FUNCTION__);
ret_val = ACEX1K_dump (desc, buf, bsize);
#else
printf ("%s: No support for ACEX1K devices.\n",
__FUNCTION__);
#endif
break;
#if defined(CONFIG_FPGA_STRATIX_II)
case Altera_StratixII:
PRINTF ("%s: Launching the Stratix II Reader...\n",
__FUNCTION__);
ret_val = StratixII_dump (desc, buf, bsize);
break;
#endif
default:
printf ("%s: Unsupported family type, %d\n",
__FUNCTION__, desc->family);
}
}
return ret_val;
}
int altera_info( Altera_desc *desc )
{
int ret_val = FPGA_FAIL;
if (altera_validate (desc, (char *)__FUNCTION__)) {
printf ("Family: \t");
switch (desc->family) {
case Altera_ACEX1K:
printf ("ACEX1K\n");
break;
case Altera_CYC2:
printf ("CYCLON II\n");
break;
case Altera_StratixII:
printf ("Stratix II\n");
break;
/* Add new family types here */
default:
printf ("Unknown family type, %d\n", desc->family);
}
printf ("Interface type:\t");
switch (desc->iface) {
case passive_serial:
printf ("Passive Serial (PS)\n");
break;
case passive_parallel_synchronous:
printf ("Passive Parallel Synchronous (PPS)\n");
break;
case passive_parallel_asynchronous:
printf ("Passive Parallel Asynchronous (PPA)\n");
break;
case passive_serial_asynchronous:
printf ("Passive Serial Asynchronous (PSA)\n");
break;
case altera_jtag_mode: /* Not used */
printf ("JTAG Mode\n");
break;
case fast_passive_parallel:
printf ("Fast Passive Parallel (FPP)\n");
break;
case fast_passive_parallel_security:
printf
("Fast Passive Parallel with Security (FPPS) \n");
break;
/* Add new interface types here */
default:
printf ("Unsupported interface type, %d\n", desc->iface);
}
printf ("Device Size: \t%d bytes\n"
"Cookie: \t0x%x (%d)\n",
desc->size, desc->cookie, desc->cookie);
if (desc->iface_fns) {
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
switch (desc->family) {
case Altera_ACEX1K:
case Altera_CYC2:
#if defined(CONFIG_FPGA_ACEX1K)
ACEX1K_info (desc);
#elif defined(CONFIG_FPGA_CYCLON2)
CYC2_info (desc);
#else
/* just in case */
printf ("%s: No support for ACEX1K devices.\n",
__FUNCTION__);
#endif
break;
#if defined(CONFIG_FPGA_STRATIX_II)
case Altera_StratixII:
StratixII_info (desc);
break;
#endif
/* Add new family types here */
default:
/* we don't need a message here - we give one up above */
break;
}
} else {
printf ("No Device Function Table.\n");
}
ret_val = FPGA_SUCCESS;
} else {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
}
return ret_val;
}
/* ------------------------------------------------------------------------- */
static int altera_validate (Altera_desc * desc, const char *fn)
{
int ret_val = FALSE;
if (desc) {
if ((desc->family > min_altera_type) &&
(desc->family < max_altera_type)) {
if ((desc->iface > min_altera_iface_type) &&
(desc->iface < max_altera_iface_type)) {
if (desc->size) {
ret_val = TRUE;
} else {
printf ("%s: NULL part size\n", fn);
}
} else {
printf ("%s: Invalid Interface type, %d\n",
fn, desc->iface);
}
} else {
printf ("%s: Invalid family type, %d\n", fn, desc->family);
}
} else {
printf ("%s: NULL descriptor!\n", fn);
}
return ret_val;
}
/* ------------------------------------------------------------------------- */
|
1001-study-uboot
|
drivers/fpga/altera.c
|
C
|
gpl3
| 6,303
|
#
# (C) Copyright 2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libfpga.o
ifdef CONFIG_FPGA
COBJS-y += fpga.o
COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
COBJS-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
ifdef CONFIG_FPGA_ALTERA
COBJS-y += altera.o
COBJS-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
COBJS-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
COBJS-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
endif
endif
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/fpga/Makefile
|
Makefile
|
gpl3
| 1,751
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/*
* Xilinx FPGA support
*/
#include <common.h>
#include <virtex2.h>
#include <spartan2.h>
#include <spartan3.h>
#if 0
#define FPGA_DEBUG
#endif
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/* Local Static Functions */
static int xilinx_validate (Xilinx_desc * desc, char *fn);
/* ------------------------------------------------------------------------- */
int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
case Xilinx_Spartan2:
#if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Loader...\n",
__FUNCTION__);
ret_val = Spartan2_load (desc, buf, bsize);
#else
printf ("%s: No support for Spartan-II devices.\n",
__FUNCTION__);
#endif
break;
case Xilinx_Spartan3:
#if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Loader...\n",
__FUNCTION__);
ret_val = Spartan3_load (desc, buf, bsize);
#else
printf ("%s: No support for Spartan-III devices.\n",
__FUNCTION__);
#endif
break;
case Xilinx_Virtex2:
#if defined(CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Loader...\n",
__FUNCTION__);
ret_val = Virtex2_load (desc, buf, bsize);
#else
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
#endif
break;
default:
printf ("%s: Unsupported family type, %d\n",
__FUNCTION__, desc->family);
}
return ret_val;
}
int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume a failure */
if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
} else
switch (desc->family) {
case Xilinx_Spartan2:
#if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Reader...\n",
__FUNCTION__);
ret_val = Spartan2_dump (desc, buf, bsize);
#else
printf ("%s: No support for Spartan-II devices.\n",
__FUNCTION__);
#endif
break;
case Xilinx_Spartan3:
#if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Reader...\n",
__FUNCTION__);
ret_val = Spartan3_dump (desc, buf, bsize);
#else
printf ("%s: No support for Spartan-III devices.\n",
__FUNCTION__);
#endif
break;
case Xilinx_Virtex2:
#if defined( CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Reader...\n",
__FUNCTION__);
ret_val = Virtex2_dump (desc, buf, bsize);
#else
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
#endif
break;
default:
printf ("%s: Unsupported family type, %d\n",
__FUNCTION__, desc->family);
}
return ret_val;
}
int xilinx_info (Xilinx_desc * desc)
{
int ret_val = FPGA_FAIL;
if (xilinx_validate (desc, (char *)__FUNCTION__)) {
printf ("Family: \t");
switch (desc->family) {
case Xilinx_Spartan2:
printf ("Spartan-II\n");
break;
case Xilinx_Spartan3:
printf ("Spartan-III\n");
break;
case Xilinx_Virtex2:
printf ("Virtex-II\n");
break;
/* Add new family types here */
default:
printf ("Unknown family type, %d\n", desc->family);
}
printf ("Interface type:\t");
switch (desc->iface) {
case slave_serial:
printf ("Slave Serial\n");
break;
case master_serial: /* Not used */
printf ("Master Serial\n");
break;
case slave_parallel:
printf ("Slave Parallel\n");
break;
case jtag_mode: /* Not used */
printf ("JTAG Mode\n");
break;
case slave_selectmap:
printf ("Slave SelectMap Mode\n");
break;
case master_selectmap:
printf ("Master SelectMap Mode\n");
break;
/* Add new interface types here */
default:
printf ("Unsupported interface type, %d\n", desc->iface);
}
printf ("Device Size: \t%d bytes\n"
"Cookie: \t0x%x (%d)\n",
desc->size, desc->cookie, desc->cookie);
if (desc->iface_fns) {
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
switch (desc->family) {
case Xilinx_Spartan2:
#if defined(CONFIG_FPGA_SPARTAN2)
Spartan2_info (desc);
#else
/* just in case */
printf ("%s: No support for Spartan-II devices.\n",
__FUNCTION__);
#endif
break;
case Xilinx_Spartan3:
#if defined(CONFIG_FPGA_SPARTAN3)
Spartan3_info (desc);
#else
/* just in case */
printf ("%s: No support for Spartan-III devices.\n",
__FUNCTION__);
#endif
break;
case Xilinx_Virtex2:
#if defined(CONFIG_FPGA_VIRTEX2)
Virtex2_info (desc);
#else
/* just in case */
printf ("%s: No support for Virtex-II devices.\n",
__FUNCTION__);
#endif
break;
/* Add new family types here */
default:
/* we don't need a message here - we give one up above */
;
}
} else
printf ("No Device Function Table.\n");
ret_val = FPGA_SUCCESS;
} else {
printf ("%s: Invalid device descriptor\n", __FUNCTION__);
}
return ret_val;
}
/* ------------------------------------------------------------------------- */
static int xilinx_validate (Xilinx_desc * desc, char *fn)
{
int ret_val = FALSE;
if (desc) {
if ((desc->family > min_xilinx_type) &&
(desc->family < max_xilinx_type)) {
if ((desc->iface > min_xilinx_iface_type) &&
(desc->iface < max_xilinx_iface_type)) {
if (desc->size) {
ret_val = TRUE;
} else
printf ("%s: NULL part size\n", fn);
} else
printf ("%s: Invalid Interface type, %d\n",
fn, desc->iface);
} else
printf ("%s: Invalid family type, %d\n", fn, desc->family);
} else
printf ("%s: NULL descriptor!\n", fn);
return ret_val;
}
|
1001-study-uboot
|
drivers/fpga/xilinx.c
|
C
|
gpl3
| 6,727
|
/*
* (C) Copyright 2006
* Heiko Schocher, hs@denx.de
* Based on ACE1XK.c
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h> /* core U-Boot definitions */
#include <altera.h>
#include <ACEX1K.h> /* ACEX device family */
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
* the board config file to slow things down.
*/
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif
#ifndef CONFIG_SYS_FPGA_WAIT
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
#endif
static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
/* static int CYC2_ps_info( Altera_desc *desc ); */
/* ------------------------------------------------------------------------- */
/* CYCLON2 Generic Implementation */
int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
ret_val = CYC2_ps_load (desc, buf, bsize);
break;
case fast_passive_parallel:
/* Fast Passive Parallel (FPP) and PS only differ in what is
* done in the write() callback. Use the existing PS load
* function for FPP, too.
*/
PRINTF ("%s: Launching Fast Passive Parallel Loader\n",
__FUNCTION__);
ret_val = CYC2_ps_load(desc, buf, bsize);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
ret_val = CYC2_ps_dump (desc, buf, bsize);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int CYC2_info( Altera_desc *desc )
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
/* CYCLON2 Passive Serial Generic Implementation */
static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
int ret = 0;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
if (fn) {
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"config:\t0x%p\n"
"status:\t0x%p\n"
"write:\t0x%p\n"
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->config, fn->status,
fn->write, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
if (*fn->pre) {
(*fn->pre) (cookie);
}
/* Establish the initial state */
(*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
udelay(2); /* T_cfg > 2us */
/* Wait for nSTATUS to be asserted */
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
}
} while (!(*fn->status) (cookie));
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
ret = (*fn->write) (buf, bsize, TRUE, cookie);
if (ret) {
puts ("** Write failed.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
}
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
puts(" OK? ...");
#endif
CONFIG_FPGA_DELAY ();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc (' '); /* terminate the dotted line */
#endif
/*
* Checking FPGA's CONF_DONE signal - correctly booted ?
*/
if ( ! (*fn->done) (cookie) ) {
puts ("** Booting failed! CONF_DONE is still deasserted.\n");
(*fn->abort) (cookie);
return (FPGA_FAIL);
}
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
puts(" OK\n");
#endif
ret_val = FPGA_SUCCESS;
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS) {
puts ("Done.\n");
}
else {
puts ("Fail.\n");
}
#endif
(*fn->post) (cookie);
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}
return ret_val;
}
static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
printf ("%s: Passive Serial Dumping is unavailable\n",
__FUNCTION__);
return FPGA_FAIL;
}
|
1001-study-uboot
|
drivers/fpga/cyclon2.c
|
C
|
gpl3
| 5,810
|
/*
* (C) Copyright 2003
* Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h> /* core U-Boot definitions */
#include <ACEX1K.h> /* ACEX device family */
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
* the board config file to slow things down.
*/
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif
#ifndef CONFIG_SYS_FPGA_WAIT
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/10 /* 100 ms */
#endif
static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
/* static int ACEX1K_ps_info(Altera_desc *desc); */
/* ------------------------------------------------------------------------- */
/* ACEX1K Generic Implementation */
int ACEX1K_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
PRINTF ("%s: Launching Passive Serial Loader\n", __FUNCTION__);
ret_val = ACEX1K_ps_load (desc, buf, bsize);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int ACEX1K_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
PRINTF ("%s: Launching Passive Serial Dump\n", __FUNCTION__);
ret_val = ACEX1K_ps_dump (desc, buf, bsize);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int ACEX1K_info( Altera_desc *desc )
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
/* ACEX1K Passive Serial Generic Implementation */
static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Altera_ACEX1K_Passive_Serial_fns *fn = desc->iface_fns;
int i;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
if (fn) {
size_t bytecount = 0;
unsigned char *data = (unsigned char *) buf;
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"config:\t0x%p\n"
"status:\t0x%p\n"
"clk:\t0x%p\n"
"data:\t0x%p\n"
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->config, fn->status,
fn->clk, fn->data, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
if (*fn->pre) {
(*fn->pre) (cookie);
}
/* Establish the initial state */
(*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */
udelay(2); /* T_cfg > 2us */
/* nSTATUS should be asserted now */
(*fn->done) (cookie);
if ( !(*fn->status) (cookie) ) {
puts ("** nSTATUS is not asserted.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
}
(*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */
udelay(2); /* T_cf2st1 < 4us */
/* Wait for nSTATUS to be released (i.e. deasserted) */
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for STATUS to go high.\n");
(*fn->abort) (cookie);
return FPGA_FAIL;
}
(*fn->done) (cookie);
} while ((*fn->status) (cookie));
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
/* Load the data */
while (bytecount < bsize) {
unsigned char val=0;
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
if (ctrlc ()) {
(*fn->abort) (cookie);
return FPGA_FAIL;
}
#endif
/* Altera detects an error if INIT goes low (active)
while DONE is low (inactive) */
#if 0 /* not yet implemented */
if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
puts ("** CRC error during FPGA load.\n");
(*fn->abort) (cookie);
return (FPGA_FAIL);
}
#endif
val = data [bytecount ++ ];
i = 8;
do {
/* Deassert the clock */
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
(*fn->data) ( (val & 0x01), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
val >>= 1;
i --;
} while (i > 0);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.'); /* let them know we are alive */
#endif
}
CONFIG_FPGA_DELAY ();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc (' '); /* terminate the dotted line */
#endif
/*
* Checking FPGA's CONF_DONE signal - correctly booted ?
*/
if ( ! (*fn->done) (cookie) ) {
puts ("** Booting failed! CONF_DONE is still deasserted.\n");
(*fn->abort) (cookie);
return (FPGA_FAIL);
}
/*
* "DCLK must be clocked an additional 10 times fpr ACEX 1K..."
*/
for (i = 0; i < 12; i++) {
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
}
ret_val = FPGA_SUCCESS;
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS) {
puts ("Done.\n");
}
else {
puts ("Fail.\n");
}
#endif
(*fn->post) (cookie);
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}
return ret_val;
}
static int ACEX1K_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
printf ("%s: Passive Serial Dumping is unavailable\n",
__FUNCTION__);
return FPGA_FAIL;
}
|
1001-study-uboot
|
drivers/fpga/ACEX1K.c
|
C
|
gpl3
| 7,035
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/*
* Configuration support for Xilinx Spartan3 devices. Based
* on spartan2.c (Rich Ireland, rireland@enterasys.com).
*/
#include <common.h> /* core U-Boot definitions */
#include <spartan3.h> /* Spartan-II device family */
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
#undef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
* the board config file to slow things down.
*/
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif
#ifndef CONFIG_SYS_FPGA_WAIT
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
/* static int Spartan3_sp_info(Xilinx_desc *desc ); */
static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
/* static int Spartan3_ss_info(Xilinx_desc *desc); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
ret_val = Spartan3_ss_load (desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
ret_val = Spartan3_sp_load (desc, buf, bsize);
break;
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
ret_val = Spartan3_ss_dump (desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
ret_val = Spartan3_sp_dump (desc, buf, bsize);
break;
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int Spartan3_info( Xilinx_desc *desc )
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
if (fn) {
size_t bytecount = 0;
unsigned char *data = (unsigned char *) buf;
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pre: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"err:\t0x%p\n"
"clk:\t0x%p\n"
"cs:\t0x%p\n"
"wr:\t0x%p\n"
"read data:\t0x%p\n"
"write data:\t0x%p\n"
"busy:\t0x%p\n"
"abort:\t0x%p\n",
"post:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
fn->abort, fn->post);
/*
* This code is designed to emulate the "Express Style"
* Continuous Data Loading in Slave Parallel Mode for
* the Spartan-II Family.
*/
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...\n", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
if (*fn->pre) {
(*fn->pre) (cookie);
}
/* Establish the initial state */
(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT and BUSY to go high */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
}
} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
(*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
/* Load the data */
while (bytecount < bsize) {
/* XXX - do we check for an Ctrl-C press in here ??? */
/* XXX - Check the error bit? */
(*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer (0); /* get current time */
while ((*fn->busy) (cookie)) {
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for BUSY to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
}
}
#endif
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.'); /* let them know we are alive */
#endif
}
CONFIG_FPGA_DELAY ();
(*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
(*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
#endif
/* now check for done signal */
ts = get_timer (0); /* get current time */
ret_val = FPGA_SUCCESS;
while ((*fn->done) (cookie) == FPGA_FAIL) {
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
ret_val = FPGA_FAIL;
break;
}
}
/*
* Run the post configuration function if there is one.
*/
if (*fn->post)
(*fn->post) (cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS)
puts ("Done.\n");
else
puts ("Fail.\n");
#endif
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}
return ret_val;
}
static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
size_t bytecount = 0;
int cookie = desc->cookie; /* make a local copy */
printf ("Starting Dump of FPGA Device %d...\n", cookie);
(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
/* dump the data */
while (bytecount < bsize) {
/* XXX - do we check for an Ctrl-C press in here ??? */
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
(*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.'); /* let them know we are alive */
#endif
}
(*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
#endif
puts ("Done.\n");
/* XXX - checksum the data? */
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}
return ret_val;
}
/* ------------------------------------------------------------------------- */
static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
int i;
unsigned char val;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
if (fn) {
size_t bytecount = 0;
unsigned char *data = (unsigned char *) buf;
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"clk:\t0x%p\n"
"wr:\t0x%p\n"
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->pgm, fn->init,
fn->clk, fn->wr, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...\n", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
if (*fn->pre) {
(*fn->pre) (cookie);
}
/* Establish the initial state */
(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
/* Wait for INIT state (init low) */
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
if (*fn->abort)
(*fn->abort) (cookie);
return FPGA_FAIL;
}
} while (!(*fn->init) (cookie));
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT to go high */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
if (*fn->abort)
(*fn->abort) (cookie);
return FPGA_FAIL;
}
} while ((*fn->init) (cookie));
/* Load the data */
if(*fn->bwr)
(*fn->bwr) (data, bsize, TRUE, cookie);
else {
while (bytecount < bsize) {
/* Xilinx detects an error if INIT goes low (active)
while DONE is low (inactive) */
if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
puts ("** CRC error during FPGA load.\n");
if (*fn->abort)
(*fn->abort) (cookie);
return (FPGA_FAIL);
}
val = data [bytecount ++];
i = 8;
do {
/* Deassert the clock */
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
val <<= 1;
i --;
} while (i > 0);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.'); /* let them know we are alive */
#endif
}
}
CONFIG_FPGA_DELAY ();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
#endif
/* now check for done signal */
ts = get_timer (0); /* get current time */
ret_val = FPGA_SUCCESS;
(*fn->wr) (TRUE, TRUE, cookie);
while (! (*fn->done) (cookie)) {
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
putc ('*');
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
ret_val = FPGA_FAIL;
break;
}
}
putc ('\n'); /* terminate the dotted line */
/*
* Run the post configuration function if there is one.
*/
if (*fn->post)
(*fn->post) (cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS)
puts ("Done.\n");
else
puts ("Fail.\n");
#endif
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}
return ret_val;
}
static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
printf ("%s: Slave Serial Dumping is unavailable\n",
__FUNCTION__);
return FPGA_FAIL;
}
|
1001-study-uboot
|
drivers/fpga/spartan3.c
|
C
|
gpl3
| 13,803
|
/*
* Porting to u-boot:
*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Lattice ispVME Embedded code to load Lattice's FPGA:
*
* Copyright 2009 Lattice Semiconductor Corp.
*
* ispVME Embedded allows programming of Lattice's suite of FPGA
* devices on embedded systems through the JTAG port. The software
* is distributed in source code form and is open to re - distribution
* and modification where applicable.
*
* Revision History of ivm_core.c module:
* 4/25/06 ht Change some variables from unsigned short or int
* to long int to make the code compiler independent.
* 5/24/06 ht Support using RESET (TRST) pin as a special purpose
* control pin such as triggering the loading of known
* state exit.
* 3/6/07 ht added functions to support output to terminals
*
* 09/11/07 NN Type cast mismatch variables
* Moved the sclock() function to hardware.c
* 08/28/08 NN Added Calculate checksum support.
* 4/1/09 Nguyen replaced the recursive function call codes on
* the ispVMLCOUNT function
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/string.h>
#include <malloc.h>
#include <lattice.h>
#define vme_out_char(c) printf("%c", c)
#define vme_out_hex(c) printf("%x", c)
#define vme_out_string(s) printf("%s", s)
/*
*
* Global variables used to specify the flow control and data type.
*
* g_usFlowControl: flow control register. Each bit in the
* register can potentially change the
* personality of the embedded engine.
* g_usDataType: holds the data type of the current row.
*
*/
static unsigned short g_usFlowControl;
unsigned short g_usDataType;
/*
*
* Global variables used to specify the ENDDR and ENDIR.
*
* g_ucEndDR: the state that the device goes to after SDR.
* g_ucEndIR: the state that the device goes to after SIR.
*
*/
unsigned char g_ucEndDR = DRPAUSE;
unsigned char g_ucEndIR = IRPAUSE;
/*
*
* Global variables used to support header/trailer.
*
* g_usHeadDR: the number of lead devices in bypass.
* g_usHeadIR: the sum of IR length of lead devices.
* g_usTailDR: the number of tail devices in bypass.
* g_usTailIR: the sum of IR length of tail devices.
*
*/
static unsigned short g_usHeadDR;
static unsigned short g_usHeadIR;
static unsigned short g_usTailDR;
static unsigned short g_usTailIR;
/*
*
* Global variable to store the number of bits of data or instruction
* to be shifted into or out from the device.
*
*/
static unsigned short g_usiDataSize;
/*
*
* Stores the frequency. Default to 1 MHz.
*
*/
static int g_iFrequency = 1000;
/*
*
* Stores the maximum amount of ram needed to hold a row of data.
*
*/
static unsigned short g_usMaxSize;
/*
*
* Stores the LSH or RSH value.
*
*/
static unsigned short g_usShiftValue;
/*
*
* Stores the current repeat loop value.
*
*/
static unsigned short g_usRepeatLoops;
/*
*
* Stores the current vendor.
*
*/
static signed char g_cVendor = LATTICE;
/*
*
* Stores the VME file CRC.
*
*/
unsigned short g_usCalculatedCRC;
/*
*
* Stores the Device Checksum.
*
*/
/* 08/28/08 NN Added Calculate checksum support. */
unsigned long g_usChecksum;
static unsigned int g_uiChecksumIndex;
/*
*
* Stores the current state of the JTAG state machine.
*
*/
static signed char g_cCurrentJTAGState;
/*
*
* Global variables used to support looping.
*
* g_pucHeapMemory: holds the entire repeat loop.
* g_iHeapCounter: points to the current byte in the repeat loop.
* g_iHEAPSize: the current size of the repeat in bytes.
*
*/
unsigned char *g_pucHeapMemory;
unsigned short g_iHeapCounter;
unsigned short g_iHEAPSize;
static unsigned short previous_size;
/*
*
* Global variables used to support intelligent programming.
*
* g_usIntelDataIndex: points to the current byte of the
* intelligent buffer.
* g_usIntelBufferSize: holds the size of the intelligent
* buffer.
*
*/
unsigned short g_usIntelDataIndex;
unsigned short g_usIntelBufferSize;
/*
*
* Supported VME versions.
*
*/
const char *const g_szSupportedVersions[] = {
"__VME2.0", "__VME3.0", "____12.0", "____12.1", 0};
/*
*
* Holds the maximum size of each respective buffer. These variables are used
* to write the HEX files when converting VME to HEX.
*
*/
static unsigned short g_usTDOSize;
static unsigned short g_usMASKSize;
static unsigned short g_usTDISize;
static unsigned short g_usDMASKSize;
static unsigned short g_usLCOUNTSize;
static unsigned short g_usHDRSize;
static unsigned short g_usTDRSize;
static unsigned short g_usHIRSize;
static unsigned short g_usTIRSize;
static unsigned short g_usHeapSize;
/*
*
* Global variables used to store data.
*
* g_pucOutMaskData: local RAM to hold one row of MASK data.
* g_pucInData: local RAM to hold one row of TDI data.
* g_pucOutData: local RAM to hold one row of TDO data.
* g_pucHIRData: local RAM to hold the current SIR header.
* g_pucTIRData: local RAM to hold the current SIR trailer.
* g_pucHDRData: local RAM to hold the current SDR header.
* g_pucTDRData: local RAM to hold the current SDR trailer.
* g_pucIntelBuffer: local RAM to hold the current intelligent buffer
* g_pucOutDMaskData: local RAM to hold one row of DMASK data.
*
*/
unsigned char *g_pucOutMaskData = NULL,
*g_pucInData = NULL,
*g_pucOutData = NULL,
*g_pucHIRData = NULL,
*g_pucTIRData = NULL,
*g_pucHDRData = NULL,
*g_pucTDRData = NULL,
*g_pucIntelBuffer = NULL,
*g_pucOutDMaskData = NULL;
/*
*
* JTAG state machine transition table.
*
*/
struct {
unsigned char CurState; /* From this state */
unsigned char NextState; /* Step to this state */
unsigned char Pattern; /* The tragetory of TMS */
unsigned char Pulses; /* The number of steps */
} g_JTAGTransistions[25] = {
{ RESET, RESET, 0xFC, 6 }, /* Transitions from RESET */
{ RESET, IDLE, 0x00, 1 },
{ RESET, DRPAUSE, 0x50, 5 },
{ RESET, IRPAUSE, 0x68, 6 },
{ IDLE, RESET, 0xE0, 3 }, /* Transitions from IDLE */
{ IDLE, DRPAUSE, 0xA0, 4 },
{ IDLE, IRPAUSE, 0xD0, 5 },
{ DRPAUSE, RESET, 0xF8, 5 }, /* Transitions from DRPAUSE */
{ DRPAUSE, IDLE, 0xC0, 3 },
{ DRPAUSE, IRPAUSE, 0xF4, 7 },
{ DRPAUSE, DRPAUSE, 0xE8, 6 },/* 06/14/06 Support POLL STATUS LOOP*/
{ IRPAUSE, RESET, 0xF8, 5 }, /* Transitions from IRPAUSE */
{ IRPAUSE, IDLE, 0xC0, 3 },
{ IRPAUSE, DRPAUSE, 0xE8, 6 },
{ DRPAUSE, SHIFTDR, 0x80, 2 }, /* Extra transitions using SHIFTDR */
{ IRPAUSE, SHIFTDR, 0xE0, 5 },
{ SHIFTDR, DRPAUSE, 0x80, 2 },
{ SHIFTDR, IDLE, 0xC0, 3 },
{ IRPAUSE, SHIFTIR, 0x80, 2 },/* Extra transitions using SHIFTIR */
{ SHIFTIR, IRPAUSE, 0x80, 2 },
{ SHIFTIR, IDLE, 0xC0, 3 },
{ DRPAUSE, DRCAPTURE, 0xE0, 4 }, /* 11/15/05 Support DRCAPTURE*/
{ DRCAPTURE, DRPAUSE, 0x80, 2 },
{ IDLE, DRCAPTURE, 0x80, 2 },
{ IRPAUSE, DRCAPTURE, 0xE0, 4 }
};
/*
*
* List to hold all LVDS pairs.
*
*/
LVDSPair *g_pLVDSList;
unsigned short g_usLVDSPairCount;
/*
*
* Function prototypes.
*
*/
static signed char ispVMDataCode(void);
static long int ispVMDataSize(void);
static void ispVMData(unsigned char *Data);
static signed char ispVMShift(signed char Code);
static signed char ispVMAmble(signed char Code);
static signed char ispVMLoop(unsigned short a_usLoopCount);
static signed char ispVMBitShift(signed char mode, unsigned short bits);
static void ispVMComment(unsigned short a_usCommentSize);
static void ispVMHeader(unsigned short a_usHeaderSize);
static signed char ispVMLCOUNT(unsigned short a_usCountSize);
static void ispVMClocks(unsigned short Clocks);
static void ispVMBypass(signed char ScanType, unsigned short Bits);
static void ispVMStateMachine(signed char NextState);
static signed char ispVMSend(unsigned short int);
static signed char ispVMRead(unsigned short int);
static signed char ispVMReadandSave(unsigned short int);
static signed char ispVMProcessLVDS(unsigned short a_usLVDSCount);
static void ispVMMemManager(signed char types, unsigned short size);
/*
*
* External variables and functions in hardware.c module
*
*/
static signed char g_cCurrentJTAGState;
#ifdef DEBUG
/*
*
* GetState
*
* Returns the state as a string based on the opcode. Only used
* for debugging purposes.
*
*/
const char *GetState(unsigned char a_ucState)
{
switch (a_ucState) {
case RESET:
return "RESET";
case IDLE:
return "IDLE";
case IRPAUSE:
return "IRPAUSE";
case DRPAUSE:
return "DRPAUSE";
case SHIFTIR:
return "SHIFTIR";
case SHIFTDR:
return "SHIFTDR";
case DRCAPTURE:/* 11/15/05 support DRCAPTURE*/
return "DRCAPTURE";
default:
break;
}
return 0;
}
/*
*
* PrintData
*
* Prints the data. Only used for debugging purposes.
*
*/
void PrintData(unsigned short a_iDataSize, unsigned char *a_pucData)
{
/* 09/11/07 NN added local variables initialization */
unsigned short usByteSize = 0;
unsigned short usBitIndex = 0;
signed short usByteIndex = 0;
unsigned char ucByte = 0;
unsigned char ucFlipByte = 0;
if (a_iDataSize % 8) {
/* 09/11/07 NN Type cast mismatch variables */
usByteSize = (unsigned short)(a_iDataSize / 8 + 1);
} else {
/* 09/11/07 NN Type cast mismatch variables */
usByteSize = (unsigned short)(a_iDataSize / 8);
}
puts("(");
/* 09/11/07 NN Type cast mismatch variables */
for (usByteIndex = (signed short)(usByteSize - 1);
usByteIndex >= 0; usByteIndex--) {
ucByte = a_pucData[usByteIndex];
ucFlipByte = 0x00;
/*
*
* Flip each byte.
*
*/
for (usBitIndex = 0; usBitIndex < 8; usBitIndex++) {
ucFlipByte <<= 1;
if (ucByte & 0x1) {
ucFlipByte |= 0x1;
}
ucByte >>= 1;
}
/*
*
* Print the flipped byte.
*
*/
printf("%.02X", ucFlipByte);
if ((usByteSize - usByteIndex) % 40 == 39) {
puts("\n\t\t");
}
if (usByteIndex < 0)
break;
}
puts(")");
}
#endif /* DEBUG */
void ispVMMemManager(signed char cTarget, unsigned short usSize)
{
switch (cTarget) {
case XTDI:
case TDI:
if (g_pucInData != NULL) {
if (previous_size == usSize) {/*memory exist*/
break;
} else {
free(g_pucInData);
g_pucInData = NULL;
}
}
g_pucInData = (unsigned char *) malloc(usSize / 8 + 2);
previous_size = usSize;
case XTDO:
case TDO:
if (g_pucOutData != NULL) {
if (previous_size == usSize) { /*already exist*/
break;
} else {
free(g_pucOutData);
g_pucOutData = NULL;
}
}
g_pucOutData = (unsigned char *) malloc(usSize / 8 + 2);
previous_size = usSize;
break;
case MASK:
if (g_pucOutMaskData != NULL) {
if (previous_size == usSize) {/*already allocated*/
break;
} else {
free(g_pucOutMaskData);
g_pucOutMaskData = NULL;
}
}
g_pucOutMaskData = (unsigned char *) malloc(usSize / 8 + 2);
previous_size = usSize;
break;
case HIR:
if (g_pucHIRData != NULL) {
free(g_pucHIRData);
g_pucHIRData = NULL;
}
g_pucHIRData = (unsigned char *) malloc(usSize / 8 + 2);
break;
case TIR:
if (g_pucTIRData != NULL) {
free(g_pucTIRData);
g_pucTIRData = NULL;
}
g_pucTIRData = (unsigned char *) malloc(usSize / 8 + 2);
break;
case HDR:
if (g_pucHDRData != NULL) {
free(g_pucHDRData);
g_pucHDRData = NULL;
}
g_pucHDRData = (unsigned char *) malloc(usSize / 8 + 2);
break;
case TDR:
if (g_pucTDRData != NULL) {
free(g_pucTDRData);
g_pucTDRData = NULL;
}
g_pucTDRData = (unsigned char *) malloc(usSize / 8 + 2);
break;
case HEAP:
if (g_pucHeapMemory != NULL) {
free(g_pucHeapMemory);
g_pucHeapMemory = NULL;
}
g_pucHeapMemory = (unsigned char *) malloc(usSize + 2);
break;
case DMASK:
if (g_pucOutDMaskData != NULL) {
if (previous_size == usSize) { /*already allocated*/
break;
} else {
free(g_pucOutDMaskData);
g_pucOutDMaskData = NULL;
}
}
g_pucOutDMaskData = (unsigned char *) malloc(usSize / 8 + 2);
previous_size = usSize;
break;
case LHEAP:
if (g_pucIntelBuffer != NULL) {
free(g_pucIntelBuffer);
g_pucIntelBuffer = NULL;
}
g_pucIntelBuffer = (unsigned char *) malloc(usSize + 2);
break;
case LVDS:
if (g_pLVDSList != NULL) {
free(g_pLVDSList);
g_pLVDSList = NULL;
}
g_pLVDSList = (LVDSPair *) malloc(usSize * sizeof(LVDSPair));
if (g_pLVDSList)
memset(g_pLVDSList, 0, usSize * sizeof(LVDSPair));
break;
default:
return;
}
}
void ispVMFreeMem(void)
{
if (g_pucHeapMemory != NULL) {
free(g_pucHeapMemory);
g_pucHeapMemory = NULL;
}
if (g_pucOutMaskData != NULL) {
free(g_pucOutMaskData);
g_pucOutMaskData = NULL;
}
if (g_pucInData != NULL) {
free(g_pucInData);
g_pucInData = NULL;
}
if (g_pucOutData != NULL) {
free(g_pucOutData);
g_pucOutData = NULL;
}
if (g_pucHIRData != NULL) {
free(g_pucHIRData);
g_pucHIRData = NULL;
}
if (g_pucTIRData != NULL) {
free(g_pucTIRData);
g_pucTIRData = NULL;
}
if (g_pucHDRData != NULL) {
free(g_pucHDRData);
g_pucHDRData = NULL;
}
if (g_pucTDRData != NULL) {
free(g_pucTDRData);
g_pucTDRData = NULL;
}
if (g_pucOutDMaskData != NULL) {
free(g_pucOutDMaskData);
g_pucOutDMaskData = NULL;
}
if (g_pucIntelBuffer != NULL) {
free(g_pucIntelBuffer);
g_pucIntelBuffer = NULL;
}
if (g_pLVDSList != NULL) {
free(g_pLVDSList);
g_pLVDSList = NULL;
}
}
/*
*
* ispVMDataSize
*
* Returns a VME-encoded number, usually used to indicate the
* bit length of an SIR/SDR command.
*
*/
long int ispVMDataSize()
{
/* 09/11/07 NN added local variables initialization */
long int iSize = 0;
signed char cCurrentByte = 0;
signed char cIndex = 0;
cIndex = 0;
while ((cCurrentByte = GetByte()) & 0x80) {
iSize |= ((long int) (cCurrentByte & 0x7F)) << cIndex;
cIndex += 7;
}
iSize |= ((long int) (cCurrentByte & 0x7F)) << cIndex;
return iSize;
}
/*
*
* ispVMCode
*
* This is the heart of the embedded engine. All the high-level opcodes
* are extracted here. Once they have been identified, then it
* will call other functions to handle the processing.
*
*/
signed char ispVMCode()
{
/* 09/11/07 NN added local variables initialization */
unsigned short iRepeatSize = 0;
signed char cOpcode = 0;
signed char cRetCode = 0;
unsigned char ucState = 0;
unsigned short usDelay = 0;
unsigned short usToggle = 0;
unsigned char usByte = 0;
/*
*
* Check the compression flag only if this is the first time
* this function is entered. Do not check the compression flag if
* it is being called recursively from other functions within
* the embedded engine.
*
*/
if (!(g_usDataType & LHEAP_IN) && !(g_usDataType & HEAP_IN)) {
usByte = GetByte();
if (usByte == 0xf1) {
g_usDataType |= COMPRESS;
} else if (usByte == 0xf2) {
g_usDataType &= ~COMPRESS;
} else {
return VME_INVALID_FILE;
}
}
/*
*
* Begin looping through all the VME opcodes.
*
*/
while ((cOpcode = GetByte()) >= 0) {
switch (cOpcode) {
case STATE:
/*
* Step the JTAG state machine.
*/
ucState = GetByte();
/*
* Step the JTAG state machine to DRCAPTURE
* to support Looping.
*/
if ((g_usDataType & LHEAP_IN) &&
(ucState == DRPAUSE) &&
(g_cCurrentJTAGState == ucState)) {
ispVMStateMachine(DRCAPTURE);
}
ispVMStateMachine(ucState);
#ifdef DEBUG
if (g_usDataType & LHEAP_IN) {
debug("LDELAY %s ", GetState(ucState));
} else {
debug("STATE %s;\n", GetState(ucState));
}
#endif /* DEBUG */
break;
case SIR:
case SDR:
case XSDR:
#ifdef DEBUG
switch (cOpcode) {
case SIR:
puts("SIR ");
break;
case SDR:
case XSDR:
if (g_usDataType & LHEAP_IN) {
puts("LSDR ");
} else {
puts("SDR ");
}
break;
}
#endif /* DEBUG */
/*
*
* Shift in data into the device.
*
*/
cRetCode = ispVMShift(cOpcode);
if (cRetCode != 0) {
return cRetCode;
}
break;
case WAIT:
/*
*
* Observe delay.
*
*/
/* 09/11/07 NN Type cast mismatch variables */
usDelay = (unsigned short) ispVMDataSize();
ispVMDelay(usDelay);
#ifdef DEBUG
if (usDelay & 0x8000) {
/*
* Since MSB is set, the delay time must be
* decoded to millisecond. The SVF2VME encodes
* the MSB to represent millisecond.
*/
usDelay &= ~0x8000;
if (g_usDataType & LHEAP_IN) {
printf("%.2E SEC;\n",
(float) usDelay / 1000);
} else {
printf("RUNTEST %.2E SEC;\n",
(float) usDelay / 1000);
}
} else {
/*
* Since MSB is not set, the delay time
* is given as microseconds.
*/
if (g_usDataType & LHEAP_IN) {
printf("%.2E SEC;\n",
(float) usDelay / 1000000);
} else {
printf("RUNTEST %.2E SEC;\n",
(float) usDelay / 1000000);
}
}
#endif /* DEBUG */
break;
case TCK:
/*
* Issue clock toggles.
*/
/* 09/11/07 NN Type cast mismatch variables */
usToggle = (unsigned short) ispVMDataSize();
ispVMClocks(usToggle);
#ifdef DEBUG
printf("RUNTEST %d TCK;\n", usToggle);
#endif /* DEBUG */
break;
case ENDDR:
/*
*
* Set the ENDDR.
*
*/
g_ucEndDR = GetByte();
#ifdef DEBUG
printf("ENDDR %s;\n", GetState(g_ucEndDR));
#endif /* DEBUG */
break;
case ENDIR:
/*
*
* Set the ENDIR.
*
*/
g_ucEndIR = GetByte();
#ifdef DEBUG
printf("ENDIR %s;\n", GetState(g_ucEndIR));
#endif /* DEBUG */
break;
case HIR:
case TIR:
case HDR:
case TDR:
#ifdef DEBUG
switch (cOpcode) {
case HIR:
puts("HIR ");
break;
case TIR:
puts("TIR ");
break;
case HDR:
puts("HDR ");
break;
case TDR:
puts("TDR ");
break;
}
#endif /* DEBUG */
/*
* Set the header/trailer of the device in order
* to bypass
* successfully.
*/
cRetCode = ispVMAmble(cOpcode);
if (cRetCode != 0) {
return cRetCode;
}
#ifdef DEBUG
puts(";\n");
#endif /* DEBUG */
break;
case MEM:
/*
* The maximum RAM required to support
* processing one row of the VME file.
*/
/* 09/11/07 NN Type cast mismatch variables */
g_usMaxSize = (unsigned short) ispVMDataSize();
#ifdef DEBUG
printf("// MEMSIZE %d\n", g_usMaxSize);
#endif /* DEBUG */
break;
case VENDOR:
/*
*
* Set the VENDOR type.
*
*/
cOpcode = GetByte();
switch (cOpcode) {
case LATTICE:
#ifdef DEBUG
puts("// VENDOR LATTICE\n");
#endif /* DEBUG */
g_cVendor = LATTICE;
break;
case ALTERA:
#ifdef DEBUG
puts("// VENDOR ALTERA\n");
#endif /* DEBUG */
g_cVendor = ALTERA;
break;
case XILINX:
#ifdef DEBUG
puts("// VENDOR XILINX\n");
#endif /* DEBUG */
g_cVendor = XILINX;
break;
default:
break;
}
break;
case SETFLOW:
/*
* Set the flow control. Flow control determines
* the personality of the embedded engine.
*/
/* 09/11/07 NN Type cast mismatch variables */
g_usFlowControl |= (unsigned short) ispVMDataSize();
break;
case RESETFLOW:
/*
*
* Unset the flow control.
*
*/
/* 09/11/07 NN Type cast mismatch variables */
g_usFlowControl &= (unsigned short) ~(ispVMDataSize());
break;
case HEAP:
/*
*
* Allocate heap size to store loops.
*
*/
cRetCode = GetByte();
if (cRetCode != SECUREHEAP) {
return VME_INVALID_FILE;
}
/* 09/11/07 NN Type cast mismatch variables */
g_iHEAPSize = (unsigned short) ispVMDataSize();
/*
* Store the maximum size of the HEAP buffer.
* Used to convert VME to HEX.
*/
if (g_iHEAPSize > g_usHeapSize) {
g_usHeapSize = g_iHEAPSize;
}
ispVMMemManager(HEAP, (unsigned short) g_iHEAPSize);
break;
case REPEAT:
/*
*
* Execute loops.
*
*/
g_usRepeatLoops = 0;
/* 09/11/07 NN Type cast mismatch variables */
iRepeatSize = (unsigned short) ispVMDataSize();
cRetCode = ispVMLoop((unsigned short) iRepeatSize);
if (cRetCode != 0) {
return cRetCode;
}
break;
case ENDLOOP:
/*
*
* Exit point from processing loops.
*
*/
return cRetCode;
case ENDVME:
/*
* The only valid exit point that indicates
* end of programming.
*/
return cRetCode;
case SHR:
/*
*
* Right-shift address.
*
*/
g_usFlowControl |= SHIFTRIGHT;
/* 09/11/07 NN Type cast mismatch variables */
g_usShiftValue = (unsigned short) (g_usRepeatLoops *
(unsigned short)GetByte());
break;
case SHL:
/*
* Left-shift address.
*/
g_usFlowControl |= SHIFTLEFT;
/* 09/11/07 NN Type cast mismatch variables */
g_usShiftValue = (unsigned short) (g_usRepeatLoops *
(unsigned short)GetByte());
break;
case FREQUENCY:
/*
*
* Set the frequency.
*
*/
/* 09/11/07 NN Type cast mismatch variables */
g_iFrequency = (int) (ispVMDataSize() / 1000);
if (g_iFrequency == 1)
g_iFrequency = 1000;
#ifdef DEBUG
printf("FREQUENCY %.2E HZ;\n",
(float) g_iFrequency * 1000);
#endif /* DEBUG */
break;
case LCOUNT:
/*
*
* Process LCOUNT command.
*
*/
cRetCode = ispVMLCOUNT((unsigned short)ispVMDataSize());
if (cRetCode != 0) {
return cRetCode;
}
break;
case VUES:
/*
*
* Set the flow control to verify USERCODE.
*
*/
g_usFlowControl |= VERIFYUES;
break;
case COMMENT:
/*
*
* Display comment.
*
*/
ispVMComment((unsigned short) ispVMDataSize());
break;
case LVDS:
/*
*
* Process LVDS command.
*
*/
ispVMProcessLVDS((unsigned short) ispVMDataSize());
break;
case HEADER:
/*
*
* Discard header.
*
*/
ispVMHeader((unsigned short) ispVMDataSize());
break;
/* 03/14/06 Support Toggle ispENABLE signal*/
case ispEN:
ucState = GetByte();
if ((ucState == ON) || (ucState == 0x01))
writePort(g_ucPinENABLE, 0x01);
else
writePort(g_ucPinENABLE, 0x00);
ispVMDelay(1);
break;
/* 05/24/06 support Toggle TRST pin*/
case TRST:
ucState = GetByte();
if (ucState == 0x01)
writePort(g_ucPinTRST, 0x01);
else
writePort(g_ucPinTRST, 0x00);
ispVMDelay(1);
break;
default:
/*
*
* Invalid opcode encountered.
*
*/
#ifdef DEBUG
printf("\nINVALID OPCODE: 0x%.2X\n", cOpcode);
#endif /* DEBUG */
return VME_INVALID_FILE;
}
}
/*
*
* Invalid exit point. Processing the token 'ENDVME' is the only
* valid way to exit the embedded engine.
*
*/
return VME_INVALID_FILE;
}
/*
*
* ispVMDataCode
*
* Processes the TDI/TDO/MASK/DMASK etc of an SIR/SDR command.
*
*/
signed char ispVMDataCode()
{
/* 09/11/07 NN added local variables initialization */
signed char cDataByte = 0;
signed char siDataSource = 0; /*source of data from file by default*/
if (g_usDataType & HEAP_IN) {
siDataSource = 1; /*the source of data from memory*/
}
/*
*
* Clear the data type register.
*
**/
g_usDataType &= ~(MASK_DATA + TDI_DATA +
TDO_DATA + DMASK_DATA + CMASK_DATA);
/*
* Iterate through SIR/SDR command and look for TDI,
* TDO, MASK, etc.
*/
while ((cDataByte = GetByte()) >= 0) {
ispVMMemManager(cDataByte, g_usMaxSize);
switch (cDataByte) {
case TDI:
/*
* Store the maximum size of the TDI buffer.
* Used to convert VME to HEX.
*/
if (g_usiDataSize > g_usTDISize) {
g_usTDISize = g_usiDataSize;
}
/*
* Updated data type register to indicate that
* TDI data is currently being used. Process the
* data in the VME file into the TDI buffer.
*/
g_usDataType |= TDI_DATA;
ispVMData(g_pucInData);
break;
case XTDO:
/*
* Store the maximum size of the TDO buffer.
* Used to convert VME to HEX.
*/
if (g_usiDataSize > g_usTDOSize) {
g_usTDOSize = g_usiDataSize;
}
/*
* Updated data type register to indicate that
* TDO data is currently being used.
*/
g_usDataType |= TDO_DATA;
break;
case TDO:
/*
* Store the maximum size of the TDO buffer.
* Used to convert VME to HEX.
*/
if (g_usiDataSize > g_usTDOSize) {
g_usTDOSize = g_usiDataSize;
}
/*
* Updated data type register to indicate
* that TDO data is currently being used.
* Process the data in the VME file into the
* TDO buffer.
*/
g_usDataType |= TDO_DATA;
ispVMData(g_pucOutData);
break;
case MASK:
/*
* Store the maximum size of the MASK buffer.
* Used to convert VME to HEX.
*/
if (g_usiDataSize > g_usMASKSize) {
g_usMASKSize = g_usiDataSize;
}
/*
* Updated data type register to indicate that
* MASK data is currently being used. Process
* the data in the VME file into the MASK buffer
*/
g_usDataType |= MASK_DATA;
ispVMData(g_pucOutMaskData);
break;
case DMASK:
/*
* Store the maximum size of the DMASK buffer.
* Used to convert VME to HEX.
*/
if (g_usiDataSize > g_usDMASKSize) {
g_usDMASKSize = g_usiDataSize;
}
/*
* Updated data type register to indicate that
* DMASK data is currently being used. Process
* the data in the VME file into the DMASK
* buffer.
*/
g_usDataType |= DMASK_DATA;
ispVMData(g_pucOutDMaskData);
break;
case CMASK:
/*
* Updated data type register to indicate that
* MASK data is currently being used. Process
* the data in the VME file into the MASK buffer
*/
g_usDataType |= CMASK_DATA;
ispVMData(g_pucOutMaskData);
break;
case CONTINUE:
return 0;
default:
/*
* Encountered invalid opcode.
*/
return VME_INVALID_FILE;
}
switch (cDataByte) {
case TDI:
/*
* Left bit shift. Used when performing
* algorithm looping.
*/
if (g_usFlowControl & SHIFTLEFT) {
ispVMBitShift(SHL, g_usShiftValue);
g_usFlowControl &= ~SHIFTLEFT;
}
/*
* Right bit shift. Used when performing
* algorithm looping.
*/
if (g_usFlowControl & SHIFTRIGHT) {
ispVMBitShift(SHR, g_usShiftValue);
g_usFlowControl &= ~SHIFTRIGHT;
}
default:
break;
}
if (siDataSource) {
g_usDataType |= HEAP_IN; /*restore from memory*/
}
}
if (siDataSource) { /*fetch data from heap memory upon return*/
g_usDataType |= HEAP_IN;
}
if (cDataByte < 0) {
/*
* Encountered invalid opcode.
*/
return VME_INVALID_FILE;
} else {
return 0;
}
}
/*
*
* ispVMData
* Extract one row of data operand from the current data type opcode. Perform
* the decompression if necessary. Extra RAM is not required for the
* decompression process. The decompression scheme employed in this module
* is on row by row basis. The format of the data stream:
* [compression code][compressed data stream]
* 0x00 --No compression
* 0x01 --Compress by 0x00.
* Example:
* Original stream: 0x000000000000000000000001
* Compressed stream: 0x01000901
* Detail: 0x01 is the code, 0x00 is the key,
* 0x09 is the count of 0x00 bytes,
* 0x01 is the uncompressed byte.
* 0x02 --Compress by 0xFF.
* Example:
* Original stream: 0xFFFFFFFFFFFFFFFFFFFFFF01
* Compressed stream: 0x02FF0901
* Detail: 0x02 is the code, 0xFF is the key,
* 0x09 is the count of 0xFF bytes,
* 0x01 is the uncompressed byte.
* 0x03
* : :
* 0xFE -- Compress by nibble blocks.
* Example:
* Original stream: 0x84210842108421084210
* Compressed stream: 0x0584210
* Detail: 0x05 is the code, means 5 nibbles block.
* 0x84210 is the 5 nibble blocks.
* The whole row is 80 bits given by g_usiDataSize.
* The number of times the block repeat itself
* is found by g_usiDataSize/(4*0x05) which is 4.
* 0xFF -- Compress by the most frequently happen byte.
* Example:
* Original stream: 0x04020401030904040404
* Compressed stream: 0xFF04(0,1,0x02,0,1,0x01,1,0x03,1,0x09,0,0,0)
* or: 0xFF044090181C240
* Detail: 0xFF is the code, 0x04 is the key.
* a bit of 0 represent the key shall be put into
* the current bit position and a bit of 1
* represent copying the next of 8 bits of data
* in.
*
*/
void ispVMData(unsigned char *ByteData)
{
/* 09/11/07 NN added local variables initialization */
unsigned short size = 0;
unsigned short i, j, m, getData = 0;
unsigned char cDataByte = 0;
unsigned char compress = 0;
unsigned short FFcount = 0;
unsigned char compr_char = 0xFF;
unsigned short index = 0;
signed char compression = 0;
/*convert number in bits to bytes*/
if (g_usiDataSize % 8 > 0) {
/* 09/11/07 NN Type cast mismatch variables */
size = (unsigned short)(g_usiDataSize / 8 + 1);
} else {
/* 09/11/07 NN Type cast mismatch variables */
size = (unsigned short)(g_usiDataSize / 8);
}
/*
* If there is compression, then check if compress by key
* of 0x00 or 0xFF or by other keys or by nibble blocks
*/
if (g_usDataType & COMPRESS) {
compression = 1;
compress = GetByte();
if ((compress == VAR) && (g_usDataType & HEAP_IN)) {
getData = 1;
g_usDataType &= ~(HEAP_IN);
compress = GetByte();
}
switch (compress) {
case 0x00:
/* No compression */
compression = 0;
break;
case 0x01:
/* Compress by byte 0x00 */
compr_char = 0x00;
break;
case 0x02:
/* Compress by byte 0xFF */
compr_char = 0xFF;
break;
case 0xFF:
/* Huffman encoding */
compr_char = GetByte();
i = 8;
for (index = 0; index < size; index++) {
ByteData[index] = 0x00;
if (i > 7) {
cDataByte = GetByte();
i = 0;
}
if ((cDataByte << i++) & 0x80)
m = 8;
else {
ByteData[index] = compr_char;
m = 0;
}
for (j = 0; j < m; j++) {
if (i > 7) {
cDataByte = GetByte();
i = 0;
}
ByteData[index] |=
((cDataByte << i++) & 0x80) >> j;
}
}
size = 0;
break;
default:
for (index = 0; index < size; index++)
ByteData[index] = 0x00;
for (index = 0; index < compress; index++) {
if (index % 2 == 0)
cDataByte = GetByte();
for (i = 0; i < size * 2 / compress; i++) {
j = (unsigned short)(index +
(i * (unsigned short)compress));
/*clear the nibble to zero first*/
if (j%2) {
if (index % 2)
ByteData[j/2] |=
cDataByte & 0xF;
else
ByteData[j/2] |=
cDataByte >> 4;
} else {
if (index % 2)
ByteData[j/2] |=
cDataByte << 4;
else
ByteData[j/2] |=
cDataByte & 0xF0;
}
}
}
size = 0;
break;
}
}
FFcount = 0;
/* Decompress by byte 0x00 or 0xFF */
for (index = 0; index < size; index++) {
if (FFcount <= 0) {
cDataByte = GetByte();
if ((cDataByte == VAR) && (g_usDataType&HEAP_IN) &&
!getData && !(g_usDataType&COMPRESS)) {
getData = 1;
g_usDataType &= ~(HEAP_IN);
cDataByte = GetByte();
}
ByteData[index] = cDataByte;
if ((compression) && (cDataByte == compr_char))
/* 09/11/07 NN Type cast mismatch variables */
FFcount = (unsigned short) ispVMDataSize();
/*The number of 0xFF or 0x00 bytes*/
} else {
FFcount--; /*Use up the 0xFF chain first*/
ByteData[index] = compr_char;
}
}
if (getData) {
g_usDataType |= HEAP_IN;
getData = 0;
}
}
/*
*
* ispVMShift
*
* Processes the SDR/XSDR/SIR commands.
*
*/
signed char ispVMShift(signed char a_cCode)
{
/* 09/11/07 NN added local variables initialization */
unsigned short iDataIndex = 0;
unsigned short iReadLoop = 0;
signed char cRetCode = 0;
cRetCode = 0;
/* 09/11/07 NN Type cast mismatch variables */
g_usiDataSize = (unsigned short) ispVMDataSize();
/*clear the flags first*/
g_usDataType &= ~(SIR_DATA + EXPRESS + SDR_DATA);
switch (a_cCode) {
case SIR:
g_usDataType |= SIR_DATA;
/*
* 1/15/04 If performing cascading, then go directly to SHIFTIR.
* Else, go to IRPAUSE before going to SHIFTIR
*/
if (g_usFlowControl & CASCADE) {
ispVMStateMachine(SHIFTIR);
} else {
ispVMStateMachine(IRPAUSE);
ispVMStateMachine(SHIFTIR);
if (g_usHeadIR > 0) {
ispVMBypass(HIR, g_usHeadIR);
sclock();
}
}
break;
case XSDR:
g_usDataType |= EXPRESS; /*mark simultaneous in and out*/
case SDR:
g_usDataType |= SDR_DATA;
/*
* 1/15/04 If already in SHIFTDR, then do not move state or
* shift in header. This would imply that the previously
* shifted frame was a cascaded frame.
*/
if (g_cCurrentJTAGState != SHIFTDR) {
/*
* 1/15/04 If performing cascading, then go directly
* to SHIFTDR. Else, go to DRPAUSE before going
* to SHIFTDR
*/
if (g_usFlowControl & CASCADE) {
if (g_cCurrentJTAGState == DRPAUSE) {
ispVMStateMachine(SHIFTDR);
/*
* 1/15/04 If cascade flag has been seat
* and the current state is DRPAUSE,
* this implies that the first cascaded
* frame is about to be shifted in. The
* header must be shifted prior to
* shifting the first cascaded frame.
*/
if (g_usHeadDR > 0) {
ispVMBypass(HDR, g_usHeadDR);
sclock();
}
} else {
ispVMStateMachine(SHIFTDR);
}
} else {
ispVMStateMachine(DRPAUSE);
ispVMStateMachine(SHIFTDR);
if (g_usHeadDR > 0) {
ispVMBypass(HDR, g_usHeadDR);
sclock();
}
}
}
break;
default:
return VME_INVALID_FILE;
}
cRetCode = ispVMDataCode();
if (cRetCode != 0) {
return VME_INVALID_FILE;
}
#ifdef DEBUG
printf("%d ", g_usiDataSize);
if (g_usDataType & TDI_DATA) {
puts("TDI ");
PrintData(g_usiDataSize, g_pucInData);
}
if (g_usDataType & TDO_DATA) {
puts("\n\t\tTDO ");
PrintData(g_usiDataSize, g_pucOutData);
}
if (g_usDataType & MASK_DATA) {
puts("\n\t\tMASK ");
PrintData(g_usiDataSize, g_pucOutMaskData);
}
if (g_usDataType & DMASK_DATA) {
puts("\n\t\tDMASK ");
PrintData(g_usiDataSize, g_pucOutDMaskData);
}
puts(";\n");
#endif /* DEBUG */
if (g_usDataType & TDO_DATA || g_usDataType & DMASK_DATA) {
if (g_usDataType & DMASK_DATA) {
cRetCode = ispVMReadandSave(g_usiDataSize);
if (!cRetCode) {
if (g_usTailDR > 0) {
sclock();
ispVMBypass(TDR, g_usTailDR);
}
ispVMStateMachine(DRPAUSE);
ispVMStateMachine(SHIFTDR);
if (g_usHeadDR > 0) {
ispVMBypass(HDR, g_usHeadDR);
sclock();
}
for (iDataIndex = 0;
iDataIndex < g_usiDataSize / 8 + 1;
iDataIndex++)
g_pucInData[iDataIndex] =
g_pucOutData[iDataIndex];
g_usDataType &= ~(TDO_DATA + DMASK_DATA);
cRetCode = ispVMSend(g_usiDataSize);
}
} else {
cRetCode = ispVMRead(g_usiDataSize);
if (cRetCode == -1 && g_cVendor == XILINX) {
for (iReadLoop = 0; iReadLoop < 30;
iReadLoop++) {
cRetCode = ispVMRead(g_usiDataSize);
if (!cRetCode) {
break;
} else {
/* Always DRPAUSE */
ispVMStateMachine(DRPAUSE);
/*
* Bypass other devices
* when appropriate
*/
ispVMBypass(TDR, g_usTailDR);
ispVMStateMachine(g_ucEndDR);
ispVMStateMachine(IDLE);
ispVMDelay(1000);
}
}
}
}
} else { /*TDI only*/
cRetCode = ispVMSend(g_usiDataSize);
}
/*transfer the input data to the output buffer for the next verify*/
if ((g_usDataType & EXPRESS) || (a_cCode == SDR)) {
if (g_pucOutData) {
for (iDataIndex = 0; iDataIndex < g_usiDataSize / 8 + 1;
iDataIndex++)
g_pucOutData[iDataIndex] =
g_pucInData[iDataIndex];
}
}
switch (a_cCode) {
case SIR:
/* 1/15/04 If not performing cascading, then shift ENDIR */
if (!(g_usFlowControl & CASCADE)) {
if (g_usTailIR > 0) {
sclock();
ispVMBypass(TIR, g_usTailIR);
}
ispVMStateMachine(g_ucEndIR);
}
break;
case XSDR:
case SDR:
/* 1/15/04 If not performing cascading, then shift ENDDR */
if (!(g_usFlowControl & CASCADE)) {
if (g_usTailDR > 0) {
sclock();
ispVMBypass(TDR, g_usTailDR);
}
ispVMStateMachine(g_ucEndDR);
}
break;
default:
break;
}
return cRetCode;
}
/*
*
* ispVMAmble
*
* This routine is to extract Header and Trailer parameter for SIR and
* SDR operations.
*
* The Header and Trailer parameter are the pre-amble and post-amble bit
* stream need to be shifted into TDI or out of TDO of the devices. Mostly
* is for the purpose of bypassing the leading or trailing devices. ispVM
* supports only shifting data into TDI to bypass the devices.
*
* For a single device, the header and trailer parameters are all set to 0
* as default by ispVM. If it is for multiple devices, the header and trailer
* value will change as specified by the VME file.
*
*/
signed char ispVMAmble(signed char Code)
{
signed char compress = 0;
/* 09/11/07 NN Type cast mismatch variables */
g_usiDataSize = (unsigned short)ispVMDataSize();
#ifdef DEBUG
printf("%d", g_usiDataSize);
#endif /* DEBUG */
if (g_usiDataSize) {
/*
* Discard the TDI byte and set the compression bit in the data
* type register to false if compression is set because TDI data
* after HIR/HDR/TIR/TDR is not compressed.
*/
GetByte();
if (g_usDataType & COMPRESS) {
g_usDataType &= ~(COMPRESS);
compress = 1;
}
}
switch (Code) {
case HIR:
/*
* Store the maximum size of the HIR buffer.
* Used to convert VME to HEX.
*/
if (g_usiDataSize > g_usHIRSize) {
g_usHIRSize = g_usiDataSize;
}
/*
* Assign the HIR value and allocate memory.
*/
g_usHeadIR = g_usiDataSize;
if (g_usHeadIR) {
ispVMMemManager(HIR, g_usHeadIR);
ispVMData(g_pucHIRData);
#ifdef DEBUG
puts(" TDI ");
PrintData(g_usHeadIR, g_pucHIRData);
#endif /* DEBUG */
}
break;
case TIR:
/*
* Store the maximum size of the TIR buffer.
* Used to convert VME to HEX.
*/
if (g_usiDataSize > g_usTIRSize) {
g_usTIRSize = g_usiDataSize;
}
/*
* Assign the TIR value and allocate memory.
*/
g_usTailIR = g_usiDataSize;
if (g_usTailIR) {
ispVMMemManager(TIR, g_usTailIR);
ispVMData(g_pucTIRData);
#ifdef DEBUG
puts(" TDI ");
PrintData(g_usTailIR, g_pucTIRData);
#endif /* DEBUG */
}
break;
case HDR:
/*
* Store the maximum size of the HDR buffer.
* Used to convert VME to HEX.
*/
if (g_usiDataSize > g_usHDRSize) {
g_usHDRSize = g_usiDataSize;
}
/*
* Assign the HDR value and allocate memory.
*
*/
g_usHeadDR = g_usiDataSize;
if (g_usHeadDR) {
ispVMMemManager(HDR, g_usHeadDR);
ispVMData(g_pucHDRData);
#ifdef DEBUG
puts(" TDI ");
PrintData(g_usHeadDR, g_pucHDRData);
#endif /* DEBUG */
}
break;
case TDR:
/*
* Store the maximum size of the TDR buffer.
* Used to convert VME to HEX.
*/
if (g_usiDataSize > g_usTDRSize) {
g_usTDRSize = g_usiDataSize;
}
/*
* Assign the TDR value and allocate memory.
*
*/
g_usTailDR = g_usiDataSize;
if (g_usTailDR) {
ispVMMemManager(TDR, g_usTailDR);
ispVMData(g_pucTDRData);
#ifdef DEBUG
puts(" TDI ");
PrintData(g_usTailDR, g_pucTDRData);
#endif /* DEBUG */
}
break;
default:
break;
}
/*
*
* Re-enable compression if it was previously set.
*
**/
if (compress) {
g_usDataType |= COMPRESS;
}
if (g_usiDataSize) {
Code = GetByte();
if (Code == CONTINUE) {
return 0;
} else {
/*
* Encountered invalid opcode.
*/
return VME_INVALID_FILE;
}
}
return 0;
}
/*
*
* ispVMLoop
*
* Perform the function call upon by the REPEAT opcode.
* Memory is to be allocated to store the entire loop from REPEAT to ENDLOOP.
* After the loop is stored then execution begin. The REPEATLOOP flag is set
* on the g_usFlowControl register to indicate the repeat loop is in session
* and therefore fetch opcode from the memory instead of from the file.
*
*/
signed char ispVMLoop(unsigned short a_usLoopCount)
{
/* 09/11/07 NN added local variables initialization */
signed char cRetCode = 0;
unsigned short iHeapIndex = 0;
unsigned short iLoopIndex = 0;
g_usShiftValue = 0;
for (iHeapIndex = 0; iHeapIndex < g_iHEAPSize; iHeapIndex++) {
g_pucHeapMemory[iHeapIndex] = GetByte();
}
if (g_pucHeapMemory[iHeapIndex - 1] != ENDLOOP) {
return VME_INVALID_FILE;
}
g_usFlowControl |= REPEATLOOP;
g_usDataType |= HEAP_IN;
for (iLoopIndex = 0; iLoopIndex < a_usLoopCount; iLoopIndex++) {
g_iHeapCounter = 0;
cRetCode = ispVMCode();
g_usRepeatLoops++;
if (cRetCode < 0) {
break;
}
}
g_usDataType &= ~(HEAP_IN);
g_usFlowControl &= ~(REPEATLOOP);
return cRetCode;
}
/*
*
* ispVMBitShift
*
* Shift the TDI stream left or right by the number of bits. The data in
* *g_pucInData is of the VME format, so the actual shifting is the reverse of
* IEEE 1532 or SVF format.
*
*/
signed char ispVMBitShift(signed char mode, unsigned short bits)
{
/* 09/11/07 NN added local variables initialization */
unsigned short i = 0;
unsigned short size = 0;
unsigned short tmpbits = 0;
if (g_usiDataSize % 8 > 0) {
/* 09/11/07 NN Type cast mismatch variables */
size = (unsigned short)(g_usiDataSize / 8 + 1);
} else {
/* 09/11/07 NN Type cast mismatch variables */
size = (unsigned short)(g_usiDataSize / 8);
}
switch (mode) {
case SHR:
for (i = 0; i < size; i++) {
if (g_pucInData[i] != 0) {
tmpbits = bits;
while (tmpbits > 0) {
g_pucInData[i] <<= 1;
if (g_pucInData[i] == 0) {
i--;
g_pucInData[i] = 1;
}
tmpbits--;
}
}
}
break;
case SHL:
for (i = 0; i < size; i++) {
if (g_pucInData[i] != 0) {
tmpbits = bits;
while (tmpbits > 0) {
g_pucInData[i] >>= 1;
if (g_pucInData[i] == 0) {
i--;
g_pucInData[i] = 8;
}
tmpbits--;
}
}
}
break;
default:
return VME_INVALID_FILE;
}
return 0;
}
/*
*
* ispVMComment
*
* Displays the SVF comments.
*
*/
void ispVMComment(unsigned short a_usCommentSize)
{
char cCurByte = 0;
for (; a_usCommentSize > 0; a_usCommentSize--) {
/*
*
* Print character to the terminal.
*
**/
cCurByte = GetByte();
vme_out_char(cCurByte);
}
cCurByte = '\n';
vme_out_char(cCurByte);
}
/*
*
* ispVMHeader
*
* Iterate the length of the header and discard it.
*
*/
void ispVMHeader(unsigned short a_usHeaderSize)
{
for (; a_usHeaderSize > 0; a_usHeaderSize--) {
GetByte();
}
}
/*
*
* ispVMCalculateCRC32
*
* Calculate the 32-bit CRC.
*
*/
void ispVMCalculateCRC32(unsigned char a_ucData)
{
/* 09/11/07 NN added local variables initialization */
unsigned char ucIndex = 0;
unsigned char ucFlipData = 0;
unsigned short usCRCTableEntry = 0;
unsigned int crc_table[16] = {
0x0000, 0xCC01, 0xD801,
0x1400, 0xF001, 0x3C00,
0x2800, 0xE401, 0xA001,
0x6C00, 0x7800, 0xB401,
0x5000, 0x9C01, 0x8801,
0x4400
};
for (ucIndex = 0; ucIndex < 8; ucIndex++) {
ucFlipData <<= 1;
if (a_ucData & 0x01) {
ucFlipData |= 0x01;
}
a_ucData >>= 1;
}
/* 09/11/07 NN Type cast mismatch variables */
usCRCTableEntry = (unsigned short)(crc_table[g_usCalculatedCRC & 0xF]);
g_usCalculatedCRC = (unsigned short)((g_usCalculatedCRC >> 4) & 0x0FFF);
g_usCalculatedCRC = (unsigned short)(g_usCalculatedCRC ^
usCRCTableEntry ^ crc_table[ucFlipData & 0xF]);
usCRCTableEntry = (unsigned short)(crc_table[g_usCalculatedCRC & 0xF]);
g_usCalculatedCRC = (unsigned short)((g_usCalculatedCRC >> 4) & 0x0FFF);
g_usCalculatedCRC = (unsigned short)(g_usCalculatedCRC ^
usCRCTableEntry ^ crc_table[(ucFlipData >> 4) & 0xF]);
}
/*
*
* ispVMLCOUNT
*
* Process the intelligent programming loops.
*
*/
signed char ispVMLCOUNT(unsigned short a_usCountSize)
{
unsigned short usContinue = 1;
unsigned short usIntelBufferIndex = 0;
unsigned short usCountIndex = 0;
signed char cRetCode = 0;
signed char cRepeatHeap = 0;
signed char cOpcode = 0;
unsigned char ucState = 0;
unsigned short usDelay = 0;
unsigned short usToggle = 0;
g_usIntelBufferSize = (unsigned short)ispVMDataSize();
/*
* Allocate memory for intel buffer.
*
*/
ispVMMemManager(LHEAP, g_usIntelBufferSize);
/*
* Store the maximum size of the intelligent buffer.
* Used to convert VME to HEX.
*/
if (g_usIntelBufferSize > g_usLCOUNTSize) {
g_usLCOUNTSize = g_usIntelBufferSize;
}
/*
* Copy intel data to the buffer.
*/
for (usIntelBufferIndex = 0; usIntelBufferIndex < g_usIntelBufferSize;
usIntelBufferIndex++) {
g_pucIntelBuffer[usIntelBufferIndex] = GetByte();
}
/*
* Set the data type register to get data from the intelligent
* data buffer.
*/
g_usDataType |= LHEAP_IN;
/*
*
* If the HEAP_IN flag is set, temporarily unset the flag so data will be
* retrieved from the status buffer.
*
**/
if (g_usDataType & HEAP_IN) {
g_usDataType &= ~HEAP_IN;
cRepeatHeap = 1;
}
#ifdef DEBUG
printf("LCOUNT %d;\n", a_usCountSize);
#endif /* DEBUG */
/*
* Iterate through the intelligent programming command.
*/
for (usCountIndex = 0; usCountIndex < a_usCountSize; usCountIndex++) {
/*
*
* Initialize the intel data index to 0 before each iteration.
*
**/
g_usIntelDataIndex = 0;
cOpcode = 0;
ucState = 0;
usDelay = 0;
usToggle = 0;
usContinue = 1;
/*
*
* Begin looping through all the VME opcodes.
*
*/
/*
* 4/1/09 Nguyen replaced the recursive function call codes on
* the ispVMLCOUNT function
*
*/
while (usContinue) {
cOpcode = GetByte();
switch (cOpcode) {
case HIR:
case TIR:
case HDR:
case TDR:
/*
* Set the header/trailer of the device in order
* to bypass successfully.
*/
ispVMAmble(cOpcode);
break;
case STATE:
/*
* Step the JTAG state machine.
*/
ucState = GetByte();
/*
* Step the JTAG state machine to DRCAPTURE
* to support Looping.
*/
if ((g_usDataType & LHEAP_IN) &&
(ucState == DRPAUSE) &&
(g_cCurrentJTAGState == ucState)) {
ispVMStateMachine(DRCAPTURE);
}
ispVMStateMachine(ucState);
#ifdef DEBUG
printf("LDELAY %s ", GetState(ucState));
#endif /* DEBUG */
break;
case SIR:
#ifdef DEBUG
printf("SIR ");
#endif /* DEBUG */
/*
* Shift in data into the device.
*/
cRetCode = ispVMShift(cOpcode);
break;
case SDR:
#ifdef DEBUG
printf("LSDR ");
#endif /* DEBUG */
/*
* Shift in data into the device.
*/
cRetCode = ispVMShift(cOpcode);
break;
case WAIT:
/*
*
* Observe delay.
*
*/
usDelay = (unsigned short)ispVMDataSize();
ispVMDelay(usDelay);
#ifdef DEBUG
if (usDelay & 0x8000) {
/*
* Since MSB is set, the delay time must
* be decoded to millisecond. The
* SVF2VME encodes the MSB to represent
* millisecond.
*/
usDelay &= ~0x8000;
printf("%.2E SEC;\n",
(float) usDelay / 1000);
} else {
/*
* Since MSB is not set, the delay time
* is given as microseconds.
*/
printf("%.2E SEC;\n",
(float) usDelay / 1000000);
}
#endif /* DEBUG */
break;
case TCK:
/*
* Issue clock toggles.
*/
usToggle = (unsigned short)ispVMDataSize();
ispVMClocks(usToggle);
#ifdef DEBUG
printf("RUNTEST %d TCK;\n", usToggle);
#endif /* DEBUG */
break;
case ENDLOOP:
/*
* Exit point from processing loops.
*/
usContinue = 0;
break;
case COMMENT:
/*
* Display comment.
*/
ispVMComment((unsigned short) ispVMDataSize());
break;
case ispEN:
ucState = GetByte();
if ((ucState == ON) || (ucState == 0x01))
writePort(g_ucPinENABLE, 0x01);
else
writePort(g_ucPinENABLE, 0x00);
ispVMDelay(1);
break;
case TRST:
if (GetByte() == 0x01)
writePort(g_ucPinTRST, 0x01);
else
writePort(g_ucPinTRST, 0x00);
ispVMDelay(1);
break;
default:
/*
* Invalid opcode encountered.
*/
debug("\nINVALID OPCODE: 0x%.2X\n", cOpcode);
return VME_INVALID_FILE;
}
}
if (cRetCode >= 0) {
/*
* Break if intelligent programming is successful.
*/
break;
}
}
/*
* If HEAP_IN flag was temporarily disabled,
* re-enable it before exiting
*/
if (cRepeatHeap) {
g_usDataType |= HEAP_IN;
}
/*
* Set the data type register to not get data from the
* intelligent data buffer.
*/
g_usDataType &= ~LHEAP_IN;
return cRetCode;
}
/*
*
* ispVMClocks
*
* Applies the specified number of pulses to TCK.
*
*/
void ispVMClocks(unsigned short Clocks)
{
unsigned short iClockIndex = 0;
for (iClockIndex = 0; iClockIndex < Clocks; iClockIndex++) {
sclock();
}
}
/*
*
* ispVMBypass
*
* This procedure takes care of the HIR, HDR, TIR, TDR for the
* purpose of putting the other devices into Bypass mode. The
* current state is checked to find out if it is at DRPAUSE or
* IRPAUSE. If it is at DRPAUSE, perform bypass register scan.
* If it is at IRPAUSE, scan into instruction registers the bypass
* instruction.
*
*/
void ispVMBypass(signed char ScanType, unsigned short Bits)
{
/* 09/11/07 NN added local variables initialization */
unsigned short iIndex = 0;
unsigned short iSourceIndex = 0;
unsigned char cBitState = 0;
unsigned char cCurByte = 0;
unsigned char *pcSource = NULL;
if (Bits <= 0) {
return;
}
switch (ScanType) {
case HIR:
pcSource = g_pucHIRData;
break;
case TIR:
pcSource = g_pucTIRData;
break;
case HDR:
pcSource = g_pucHDRData;
break;
case TDR:
pcSource = g_pucTDRData;
break;
default:
break;
}
iSourceIndex = 0;
cBitState = 0;
for (iIndex = 0; iIndex < Bits - 1; iIndex++) {
/* Scan instruction or bypass register */
if (iIndex % 8 == 0) {
cCurByte = pcSource[iSourceIndex++];
}
cBitState = (unsigned char) (((cCurByte << iIndex % 8) & 0x80)
? 0x01 : 0x00);
writePort(g_ucPinTDI, cBitState);
sclock();
}
if (iIndex % 8 == 0) {
cCurByte = pcSource[iSourceIndex++];
}
cBitState = (unsigned char) (((cCurByte << iIndex % 8) & 0x80)
? 0x01 : 0x00);
writePort(g_ucPinTDI, cBitState);
}
/*
*
* ispVMStateMachine
*
* This procedure steps all devices in the daisy chain from a given
* JTAG state to the next desirable state. If the next state is TLR,
* the JTAG state machine is brute forced into TLR by driving TMS
* high and pulse TCK 6 times.
*
*/
void ispVMStateMachine(signed char cNextJTAGState)
{
/* 09/11/07 NN added local variables initialization */
signed char cPathIndex = 0;
signed char cStateIndex = 0;
if ((g_cCurrentJTAGState == cNextJTAGState) &&
(cNextJTAGState != RESET)) {
return;
}
for (cStateIndex = 0; cStateIndex < 25; cStateIndex++) {
if ((g_cCurrentJTAGState ==
g_JTAGTransistions[cStateIndex].CurState) &&
(cNextJTAGState ==
g_JTAGTransistions[cStateIndex].NextState)) {
break;
}
}
g_cCurrentJTAGState = cNextJTAGState;
for (cPathIndex = 0;
cPathIndex < g_JTAGTransistions[cStateIndex].Pulses;
cPathIndex++) {
if ((g_JTAGTransistions[cStateIndex].Pattern << cPathIndex)
& 0x80) {
writePort(g_ucPinTMS, (unsigned char) 0x01);
} else {
writePort(g_ucPinTMS, (unsigned char) 0x00);
}
sclock();
}
writePort(g_ucPinTDI, 0x00);
writePort(g_ucPinTMS, 0x00);
}
/*
*
* ispVMStart
*
* Enable the port to the device and set the state to RESET (TLR).
*
*/
void ispVMStart()
{
#ifdef DEBUG
printf("// ISPVM EMBEDDED ADDED\n");
printf("STATE RESET;\n");
#endif
g_usFlowControl = 0;
g_usDataType = g_uiChecksumIndex = g_cCurrentJTAGState = 0;
g_usHeadDR = g_usHeadIR = g_usTailDR = g_usTailIR = 0;
g_usMaxSize = g_usShiftValue = g_usRepeatLoops = 0;
g_usTDOSize = g_usMASKSize = g_usTDISize = 0;
g_usDMASKSize = g_usLCOUNTSize = g_usHDRSize = 0;
g_usTDRSize = g_usHIRSize = g_usTIRSize = g_usHeapSize = 0;
g_pLVDSList = NULL;
g_usLVDSPairCount = 0;
previous_size = 0;
ispVMStateMachine(RESET); /*step devices to RESET state*/
}
/*
*
* ispVMEnd
*
* Set the state of devices to RESET to enable the devices and disable
* the port.
*
*/
void ispVMEnd()
{
#ifdef DEBUG
printf("// ISPVM EMBEDDED ADDED\n");
printf("STATE RESET;\n");
printf("RUNTEST 1.00E-001 SEC;\n");
#endif
ispVMStateMachine(RESET); /*step devices to RESET state */
ispVMDelay(1000); /*wake up devices*/
}
/*
*
* ispVMSend
*
* Send the TDI data stream to devices. The data stream can be
* instructions or data.
*
*/
signed char ispVMSend(unsigned short a_usiDataSize)
{
/* 09/11/07 NN added local variables initialization */
unsigned short iIndex = 0;
unsigned short iInDataIndex = 0;
unsigned char cCurByte = 0;
unsigned char cBitState = 0;
for (iIndex = 0; iIndex < a_usiDataSize - 1; iIndex++) {
if (iIndex % 8 == 0) {
cCurByte = g_pucInData[iInDataIndex++];
}
cBitState = (unsigned char)(((cCurByte << iIndex % 8) & 0x80)
? 0x01 : 0x00);
writePort(g_ucPinTDI, cBitState);
sclock();
}
if (iIndex % 8 == 0) {
/* Take care of the last bit */
cCurByte = g_pucInData[iInDataIndex];
}
cBitState = (unsigned char) (((cCurByte << iIndex % 8) & 0x80)
? 0x01 : 0x00);
writePort(g_ucPinTDI, cBitState);
if (g_usFlowControl & CASCADE) {
/*1/15/04 Clock in last bit for the first n-1 cascaded frames */
sclock();
}
return 0;
}
/*
*
* ispVMRead
*
* Read the data stream from devices and verify.
*
*/
signed char ispVMRead(unsigned short a_usiDataSize)
{
/* 09/11/07 NN added local variables initialization */
unsigned short usDataSizeIndex = 0;
unsigned short usErrorCount = 0;
unsigned short usLastBitIndex = 0;
unsigned char cDataByte = 0;
unsigned char cMaskByte = 0;
unsigned char cInDataByte = 0;
unsigned char cCurBit = 0;
unsigned char cByteIndex = 0;
unsigned short usBufferIndex = 0;
unsigned char ucDisplayByte = 0x00;
unsigned char ucDisplayFlag = 0x01;
char StrChecksum[256] = {0};
unsigned char g_usCalculateChecksum = 0x00;
/* 09/11/07 NN Type cast mismatch variables */
usLastBitIndex = (unsigned short)(a_usiDataSize - 1);
#ifndef DEBUG
/*
* If mask is not all zeros, then set the display flag to 0x00,
* otherwise it shall be set to 0x01 to indicate that data read
* from the device shall be displayed. If DEBUG is defined,
* always display data.
*/
for (usDataSizeIndex = 0; usDataSizeIndex < (a_usiDataSize + 7) / 8;
usDataSizeIndex++) {
if (g_usDataType & MASK_DATA) {
if (g_pucOutMaskData[usDataSizeIndex] != 0x00) {
ucDisplayFlag = 0x00;
break;
}
} else if (g_usDataType & CMASK_DATA) {
g_usCalculateChecksum = 0x01;
ucDisplayFlag = 0x00;
break;
} else {
ucDisplayFlag = 0x00;
break;
}
}
#endif /* DEBUG */
/*
*
* Begin shifting data in and out of the device.
*
**/
for (usDataSizeIndex = 0; usDataSizeIndex < a_usiDataSize;
usDataSizeIndex++) {
if (cByteIndex == 0) {
/*
* Grab byte from TDO buffer.
*/
if (g_usDataType & TDO_DATA) {
cDataByte = g_pucOutData[usBufferIndex];
}
/*
* Grab byte from MASK buffer.
*/
if (g_usDataType & MASK_DATA) {
cMaskByte = g_pucOutMaskData[usBufferIndex];
} else {
cMaskByte = 0xFF;
}
/*
* Grab byte from CMASK buffer.
*/
if (g_usDataType & CMASK_DATA) {
cMaskByte = 0x00;
g_usCalculateChecksum = 0x01;
}
/*
* Grab byte from TDI buffer.
*/
if (g_usDataType & TDI_DATA) {
cInDataByte = g_pucInData[usBufferIndex];
}
usBufferIndex++;
}
cCurBit = readPort();
if (ucDisplayFlag) {
ucDisplayByte <<= 1;
ucDisplayByte |= cCurBit;
}
/*
* Check if data read from port matches with expected TDO.
*/
if (g_usDataType & TDO_DATA) {
/* 08/28/08 NN Added Calculate checksum support. */
if (g_usCalculateChecksum) {
if (cCurBit == 0x01)
g_usChecksum +=
(1 << (g_uiChecksumIndex % 8));
g_uiChecksumIndex++;
} else {
if ((((cMaskByte << cByteIndex) & 0x80)
? 0x01 : 0x00)) {
if (cCurBit != (unsigned char)
(((cDataByte << cByteIndex) & 0x80)
? 0x01 : 0x00)) {
usErrorCount++;
}
}
}
}
/*
* Write TDI data to the port.
*/
writePort(g_ucPinTDI,
(unsigned char)(((cInDataByte << cByteIndex) & 0x80)
? 0x01 : 0x00));
if (usDataSizeIndex < usLastBitIndex) {
/*
* Clock data out from the data shift register.
*/
sclock();
} else if (g_usFlowControl & CASCADE) {
/*
* Clock in last bit for the first N - 1 cascaded frames
*/
sclock();
}
/*
* Increment the byte index. If it exceeds 7, then reset it back
* to zero.
*/
cByteIndex++;
if (cByteIndex >= 8) {
if (ucDisplayFlag) {
/*
* Store displayed data in the TDO buffer. By reusing
* the TDO buffer to store displayed data, there is no
* need to allocate a buffer simply to hold display
* data. This will not cause any false verification
* errors because the true TDO byte has already
* been consumed.
*/
g_pucOutData[usBufferIndex - 1] = ucDisplayByte;
ucDisplayByte = 0;
}
cByteIndex = 0;
}
/* 09/12/07 Nguyen changed to display the 1 bit expected data */
else if (a_usiDataSize == 1) {
if (ucDisplayFlag) {
/*
* Store displayed data in the TDO buffer.
* By reusing the TDO buffer to store displayed
* data, there is no need to allocate
* a buffer simply to hold display data. This
* will not cause any false verification errors
* because the true TDO byte has already
* been consumed.
*/
/*
* Flip ucDisplayByte and store it in cDataByte.
*/
cDataByte = 0x00;
for (usBufferIndex = 0; usBufferIndex < 8;
usBufferIndex++) {
cDataByte <<= 1;
if (ucDisplayByte & 0x01) {
cDataByte |= 0x01;
}
ucDisplayByte >>= 1;
}
g_pucOutData[0] = cDataByte;
ucDisplayByte = 0;
}
cByteIndex = 0;
}
}
if (ucDisplayFlag) {
#ifdef DEBUG
debug("RECEIVED TDO (");
#else
vme_out_string("Display Data: 0x");
#endif /* DEBUG */
/* 09/11/07 NN Type cast mismatch variables */
for (usDataSizeIndex = (unsigned short)
((a_usiDataSize + 7) / 8);
usDataSizeIndex > 0 ; usDataSizeIndex--) {
cMaskByte = g_pucOutData[usDataSizeIndex - 1];
cDataByte = 0x00;
/*
* Flip cMaskByte and store it in cDataByte.
*/
for (usBufferIndex = 0; usBufferIndex < 8;
usBufferIndex++) {
cDataByte <<= 1;
if (cMaskByte & 0x01) {
cDataByte |= 0x01;
}
cMaskByte >>= 1;
}
#ifdef DEBUG
printf("%.2X", cDataByte);
if ((((a_usiDataSize + 7) / 8) - usDataSizeIndex)
% 40 == 39) {
printf("\n\t\t");
}
#else
vme_out_hex(cDataByte);
#endif /* DEBUG */
}
#ifdef DEBUG
printf(")\n\n");
#else
vme_out_string("\n\n");
#endif /* DEBUG */
/* 09/02/08 Nguyen changed to display the data Checksum */
if (g_usChecksum != 0) {
g_usChecksum &= 0xFFFF;
sprintf(StrChecksum, "Data Checksum: %.4lX\n\n",
g_usChecksum);
vme_out_string(StrChecksum);
g_usChecksum = 0;
}
}
if (usErrorCount > 0) {
if (g_usFlowControl & VERIFYUES) {
vme_out_string(
"USERCODE verification failed. "
"Continue programming......\n\n");
g_usFlowControl &= ~(VERIFYUES);
return 0;
} else {
#ifdef DEBUG
printf("TOTAL ERRORS: %d\n", usErrorCount);
#endif /* DEBUG */
return VME_VERIFICATION_FAILURE;
}
} else {
if (g_usFlowControl & VERIFYUES) {
vme_out_string("USERCODE verification passed. "
"Programming aborted.\n\n");
g_usFlowControl &= ~(VERIFYUES);
return 1;
} else {
return 0;
}
}
}
/*
*
* ispVMReadandSave
*
* Support dynamic I/O.
*
*/
signed char ispVMReadandSave(unsigned short int a_usiDataSize)
{
/* 09/11/07 NN added local variables initialization */
unsigned short int usDataSizeIndex = 0;
unsigned short int usLastBitIndex = 0;
unsigned short int usBufferIndex = 0;
unsigned short int usOutBitIndex = 0;
unsigned short int usLVDSIndex = 0;
unsigned char cDataByte = 0;
unsigned char cDMASKByte = 0;
unsigned char cInDataByte = 0;
unsigned char cCurBit = 0;
unsigned char cByteIndex = 0;
signed char cLVDSByteIndex = 0;
/* 09/11/07 NN Type cast mismatch variables */
usLastBitIndex = (unsigned short) (a_usiDataSize - 1);
/*
*
* Iterate through the data bits.
*
*/
for (usDataSizeIndex = 0; usDataSizeIndex < a_usiDataSize;
usDataSizeIndex++) {
if (cByteIndex == 0) {
/*
* Grab byte from DMASK buffer.
*/
if (g_usDataType & DMASK_DATA) {
cDMASKByte = g_pucOutDMaskData[usBufferIndex];
} else {
cDMASKByte = 0x00;
}
/*
* Grab byte from TDI buffer.
*/
if (g_usDataType & TDI_DATA) {
cInDataByte = g_pucInData[usBufferIndex];
}
usBufferIndex++;
}
cCurBit = readPort();
cDataByte = (unsigned char)(((cInDataByte << cByteIndex) & 0x80)
? 0x01 : 0x00);
/*
* Initialize the byte to be zero.
*/
if (usOutBitIndex % 8 == 0) {
g_pucOutData[usOutBitIndex / 8] = 0x00;
}
/*
* Use TDI, DMASK, and device TDO to create new TDI (actually
* stored in g_pucOutData).
*/
if ((((cDMASKByte << cByteIndex) & 0x80) ? 0x01 : 0x00)) {
if (g_pLVDSList) {
for (usLVDSIndex = 0;
usLVDSIndex < g_usLVDSPairCount;
usLVDSIndex++) {
if (g_pLVDSList[usLVDSIndex].
usNegativeIndex ==
usDataSizeIndex) {
g_pLVDSList[usLVDSIndex].
ucUpdate = 0x01;
break;
}
}
}
/*
* DMASK bit is 1, use TDI.
*/
g_pucOutData[usOutBitIndex / 8] |= (unsigned char)
(((cDataByte & 0x1) ? 0x01 : 0x00) <<
(7 - usOutBitIndex % 8));
} else {
/*
* DMASK bit is 0, use device TDO.
*/
g_pucOutData[usOutBitIndex / 8] |= (unsigned char)
(((cCurBit & 0x1) ? 0x01 : 0x00) <<
(7 - usOutBitIndex % 8));
}
/*
* Shift in TDI in order to get TDO out.
*/
usOutBitIndex++;
writePort(g_ucPinTDI, cDataByte);
if (usDataSizeIndex < usLastBitIndex) {
sclock();
}
/*
* Increment the byte index. If it exceeds 7, then reset it back
* to zero.
*/
cByteIndex++;
if (cByteIndex >= 8) {
cByteIndex = 0;
}
}
/*
* If g_pLVDSList exists and pairs need updating, then update
* the negative-pair to receive the flipped positive-pair value.
*/
if (g_pLVDSList) {
for (usLVDSIndex = 0; usLVDSIndex < g_usLVDSPairCount;
usLVDSIndex++) {
if (g_pLVDSList[usLVDSIndex].ucUpdate) {
/*
* Read the positive value and flip it.
*/
cDataByte = (unsigned char)
(((g_pucOutData[g_pLVDSList[usLVDSIndex].
usPositiveIndex / 8]
<< (g_pLVDSList[usLVDSIndex].
usPositiveIndex % 8)) & 0x80) ?
0x01 : 0x00);
/* 09/11/07 NN Type cast mismatch variables */
cDataByte = (unsigned char) (!cDataByte);
/*
* Get the byte that needs modification.
*/
cInDataByte =
g_pucOutData[g_pLVDSList[usLVDSIndex].
usNegativeIndex / 8];
if (cDataByte) {
/*
* Copy over the current byte and
* set the negative bit to 1.
*/
cDataByte = 0x00;
for (cLVDSByteIndex = 7;
cLVDSByteIndex >= 0;
cLVDSByteIndex--) {
cDataByte <<= 1;
if (7 -
(g_pLVDSList[usLVDSIndex].
usNegativeIndex % 8) ==
cLVDSByteIndex) {
/*
* Set negative bit to 1
*/
cDataByte |= 0x01;
} else if (cInDataByte & 0x80) {
cDataByte |= 0x01;
}
cInDataByte <<= 1;
}
/*
* Store the modified byte.
*/
g_pucOutData[g_pLVDSList[usLVDSIndex].
usNegativeIndex / 8] = cDataByte;
} else {
/*
* Copy over the current byte and set
* the negative bit to 0.
*/
cDataByte = 0x00;
for (cLVDSByteIndex = 7;
cLVDSByteIndex >= 0;
cLVDSByteIndex--) {
cDataByte <<= 1;
if (7 -
(g_pLVDSList[usLVDSIndex].
usNegativeIndex % 8) ==
cLVDSByteIndex) {
/*
* Set negative bit to 0
*/
cDataByte |= 0x00;
} else if (cInDataByte & 0x80) {
cDataByte |= 0x01;
}
cInDataByte <<= 1;
}
/*
* Store the modified byte.
*/
g_pucOutData[g_pLVDSList[usLVDSIndex].
usNegativeIndex / 8] = cDataByte;
}
break;
}
}
}
return 0;
}
signed char ispVMProcessLVDS(unsigned short a_usLVDSCount)
{
unsigned short usLVDSIndex = 0;
/*
* Allocate memory to hold LVDS pairs.
*/
ispVMMemManager(LVDS, a_usLVDSCount);
g_usLVDSPairCount = a_usLVDSCount;
#ifdef DEBUG
printf("LVDS %d (", a_usLVDSCount);
#endif /* DEBUG */
/*
* Iterate through each given LVDS pair.
*/
for (usLVDSIndex = 0; usLVDSIndex < g_usLVDSPairCount; usLVDSIndex++) {
/*
* Assign the positive and negative indices of the LVDS pair.
*/
/* 09/11/07 NN Type cast mismatch variables */
g_pLVDSList[usLVDSIndex].usPositiveIndex =
(unsigned short) ispVMDataSize();
/* 09/11/07 NN Type cast mismatch variables */
g_pLVDSList[usLVDSIndex].usNegativeIndex =
(unsigned short)ispVMDataSize();
#ifdef DEBUG
if (usLVDSIndex < g_usLVDSPairCount - 1) {
printf("%d:%d, ",
g_pLVDSList[usLVDSIndex].usPositiveIndex,
g_pLVDSList[usLVDSIndex].usNegativeIndex);
} else {
printf("%d:%d",
g_pLVDSList[usLVDSIndex].usPositiveIndex,
g_pLVDSList[usLVDSIndex].usNegativeIndex);
}
#endif /* DEBUG */
}
#ifdef DEBUG
printf(");\n", a_usLVDSCount);
#endif /* DEBUG */
return 0;
}
|
1001-study-uboot
|
drivers/fpga/ivm_core.c
|
C
|
gpl3
| 67,068
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h> /* core U-Boot definitions */
#include <spartan2.h> /* Spartan-II device family */
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
#undef CONFIG_SYS_FPGA_CHECK_BUSY
#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).
* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
* the board config file to slow things down.
*/
#ifndef CONFIG_FPGA_DELAY
#define CONFIG_FPGA_DELAY()
#endif
#ifndef CONFIG_SYS_FPGA_WAIT
#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
#endif
static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
/* static int Spartan2_sp_info(Xilinx_desc *desc ); */
static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
/* static int Spartan2_ss_info(Xilinx_desc *desc ); */
/* ------------------------------------------------------------------------- */
/* Spartan-II Generic Implementation */
int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
ret_val = Spartan2_ss_load (desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
ret_val = Spartan2_sp_load (desc, buf, bsize);
break;
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case slave_serial:
PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
ret_val = Spartan2_ss_dump (desc, buf, bsize);
break;
case slave_parallel:
PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
ret_val = Spartan2_sp_dump (desc, buf, bsize);
break;
default:
printf ("%s: Unsupported interface type, %d\n",
__FUNCTION__, desc->iface);
}
return ret_val;
}
int Spartan2_info( Xilinx_desc *desc )
{
return FPGA_SUCCESS;
}
/* ------------------------------------------------------------------------- */
/* Spartan-II Slave Parallel Generic Implementation */
static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
if (fn) {
size_t bytecount = 0;
unsigned char *data = (unsigned char *) buf;
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pre: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"err:\t0x%p\n"
"clk:\t0x%p\n"
"cs:\t0x%p\n"
"wr:\t0x%p\n"
"read data:\t0x%p\n"
"write data:\t0x%p\n"
"busy:\t0x%p\n"
"abort:\t0x%p\n",
"post:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
fn->abort, fn->post);
/*
* This code is designed to emulate the "Express Style"
* Continuous Data Loading in Slave Parallel Mode for
* the Spartan-II Family.
*/
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...\n", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
if (*fn->pre) {
(*fn->pre) (cookie);
}
/* Establish the initial state */
(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT and BUSY to go high */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
}
} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
(*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
/* Load the data */
while (bytecount < bsize) {
/* XXX - do we check for an Ctrl-C press in here ??? */
/* XXX - Check the error bit? */
(*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
ts = get_timer (0); /* get current time */
while ((*fn->busy) (cookie)) {
/* XXX - we should have a check in here somewhere to
* make sure we aren't busy forever... */
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for BUSY to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
return FPGA_FAIL;
}
}
#endif
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.'); /* let them know we are alive */
#endif
}
CONFIG_FPGA_DELAY ();
(*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
(*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
#endif
/* now check for done signal */
ts = get_timer (0); /* get current time */
ret_val = FPGA_SUCCESS;
while ((*fn->done) (cookie) == FPGA_FAIL) {
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
(*fn->abort) (cookie); /* abort the burn */
ret_val = FPGA_FAIL;
break;
}
}
/*
* Run the post configuration function if there is one.
*/
if (*fn->post)
(*fn->post) (cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS)
puts ("Done.\n");
else
puts ("Fail.\n");
#endif
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}
return ret_val;
}
static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
if (fn) {
unsigned char *data = (unsigned char *) buf;
size_t bytecount = 0;
int cookie = desc->cookie; /* make a local copy */
printf ("Starting Dump of FPGA Device %d...\n", cookie);
(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
/* dump the data */
while (bytecount < bsize) {
/* XXX - do we check for an Ctrl-C press in here ??? */
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
(*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.'); /* let them know we are alive */
#endif
}
(*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
#endif
puts ("Done.\n");
/* XXX - checksum the data? */
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}
return ret_val;
}
/* ------------------------------------------------------------------------- */
static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume the worst */
Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
int i;
unsigned char val;
PRINTF ("%s: start with interface functions @ 0x%p\n",
__FUNCTION__, fn);
if (fn) {
size_t bytecount = 0;
unsigned char *data = (unsigned char *) buf;
int cookie = desc->cookie; /* make a local copy */
unsigned long ts; /* timestamp */
PRINTF ("%s: Function Table:\n"
"ptr:\t0x%p\n"
"struct: 0x%p\n"
"pgm:\t0x%p\n"
"init:\t0x%p\n"
"clk:\t0x%p\n"
"wr:\t0x%p\n"
"done:\t0x%p\n\n",
__FUNCTION__, &fn, fn, fn->pgm, fn->init,
fn->clk, fn->wr, fn->done);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
printf ("Loading FPGA Device %d...\n", cookie);
#endif
/*
* Run the pre configuration function if there is one.
*/
if (*fn->pre) {
(*fn->pre) (cookie);
}
/* Establish the initial state */
(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
/* Wait for INIT state (init low) */
ts = get_timer (0); /* get current time */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to start.\n");
return FPGA_FAIL;
}
} while (!(*fn->init) (cookie));
/* Get ready for the burn */
CONFIG_FPGA_DELAY ();
(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
ts = get_timer (0); /* get current time */
/* Now wait for INIT to go high */
do {
CONFIG_FPGA_DELAY ();
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for INIT to clear.\n");
return FPGA_FAIL;
}
} while ((*fn->init) (cookie));
/* Load the data */
while (bytecount < bsize) {
/* Xilinx detects an error if INIT goes low (active)
while DONE is low (inactive) */
if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
puts ("** CRC error during FPGA load.\n");
return (FPGA_FAIL);
}
val = data [bytecount ++];
i = 8;
do {
/* Deassert the clock */
(*fn->clk) (FALSE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Write data */
(*fn->wr) ((val & 0x80), TRUE, cookie);
CONFIG_FPGA_DELAY ();
/* Assert the clock */
(*fn->clk) (TRUE, TRUE, cookie);
CONFIG_FPGA_DELAY ();
val <<= 1;
i --;
} while (i > 0);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (bytecount % (bsize / 40) == 0)
putc ('.'); /* let them know we are alive */
#endif
}
CONFIG_FPGA_DELAY ();
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc ('\n'); /* terminate the dotted line */
#endif
/* now check for done signal */
ts = get_timer (0); /* get current time */
ret_val = FPGA_SUCCESS;
(*fn->wr) (TRUE, TRUE, cookie);
while (! (*fn->done) (cookie)) {
CONFIG_FPGA_DELAY ();
(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
CONFIG_FPGA_DELAY ();
(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
putc ('*');
if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
puts ("** Timeout waiting for DONE to clear.\n");
ret_val = FPGA_FAIL;
break;
}
}
putc ('\n'); /* terminate the dotted line */
/*
* Run the post configuration function if there is one.
*/
if (*fn->post)
(*fn->post) (cookie);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
if (ret_val == FPGA_SUCCESS)
puts ("Done.\n");
else
puts ("Fail.\n");
#endif
} else {
printf ("%s: NULL Interface function table!\n", __FUNCTION__);
}
return ret_val;
}
static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
{
/* Readback is only available through the Slave Parallel and */
/* boundary-scan interfaces. */
printf ("%s: Slave Serial Dumping is unavailable\n",
__FUNCTION__);
return FPGA_FAIL;
}
|
1001-study-uboot
|
drivers/fpga/spartan2.c
|
C
|
gpl3
| 13,234
|
/*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* ispVM functions adapted from Lattice's ispmVMEmbedded code:
* Copyright 2009 Lattice Semiconductor Corp.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <malloc.h>
#include <fpga.h>
#include <lattice.h>
static lattice_board_specific_func *pfns;
static const char *fpga_image;
static unsigned long read_bytes;
static unsigned long bufsize;
static unsigned short expectedCRC;
/*
* External variables and functions declared in ivm_core.c module.
*/
extern unsigned short g_usCalculatedCRC;
extern unsigned short g_usDataType;
extern unsigned char *g_pucIntelBuffer;
extern unsigned char *g_pucHeapMemory;
extern unsigned short g_iHeapCounter;
extern unsigned short g_iHEAPSize;
extern unsigned short g_usIntelDataIndex;
extern unsigned short g_usIntelBufferSize;
extern char *const g_szSupportedVersions[];
/*
* ispVMDelay
*
* Users must implement a delay to observe a_usTimeDelay, where
* bit 15 of the a_usTimeDelay defines the unit.
* 1 = milliseconds
* 0 = microseconds
* Example:
* a_usTimeDelay = 0x0001 = 1 microsecond delay.
* a_usTimeDelay = 0x8001 = 1 millisecond delay.
*
* This subroutine is called upon to provide a delay from 1 millisecond to a few
* hundreds milliseconds each time.
* It is understood that due to a_usTimeDelay is defined as unsigned short, a 16
* bits integer, this function is restricted to produce a delay to 64000
* micro-seconds or 32000 milli-second maximum. The VME file will never pass on
* to this function a delay time > those maximum number. If it needs more than
* those maximum, the VME file will launch the delay function several times to
* realize a larger delay time cummulatively.
* It is perfectly alright to provide a longer delay than required. It is not
* acceptable if the delay is shorter.
*/
void ispVMDelay(unsigned short delay)
{
if (delay & 0x8000)
delay = (delay & ~0x8000) * 1000;
udelay(delay);
}
void writePort(unsigned char a_ucPins, unsigned char a_ucValue)
{
a_ucValue = a_ucValue ? 1 : 0;
switch (a_ucPins) {
case g_ucPinTDI:
pfns->jtag_set_tdi(a_ucValue);
break;
case g_ucPinTCK:
pfns->jtag_set_tck(a_ucValue);
break;
case g_ucPinTMS:
pfns->jtag_set_tms(a_ucValue);
break;
default:
printf("%s: requested unknown pin\n", __func__);
}
}
unsigned char readPort(void)
{
return pfns->jtag_get_tdo();
}
void sclock(void)
{
writePort(g_ucPinTCK, 0x01);
writePort(g_ucPinTCK, 0x00);
}
void calibration(void)
{
/* Apply 2 pulses to TCK. */
writePort(g_ucPinTCK, 0x00);
writePort(g_ucPinTCK, 0x01);
writePort(g_ucPinTCK, 0x00);
writePort(g_ucPinTCK, 0x01);
writePort(g_ucPinTCK, 0x00);
ispVMDelay(0x8001);
/* Apply 2 pulses to TCK. */
writePort(g_ucPinTCK, 0x01);
writePort(g_ucPinTCK, 0x00);
writePort(g_ucPinTCK, 0x01);
writePort(g_ucPinTCK, 0x00);
}
/*
* GetByte
*
* Returns a byte to the caller. The returned byte depends on the
* g_usDataType register. If the HEAP_IN bit is set, then the byte
* is returned from the HEAP. If the LHEAP_IN bit is set, then
* the byte is returned from the intelligent buffer. Otherwise,
* the byte is returned directly from the VME file.
*/
unsigned char GetByte(void)
{
unsigned char ucData;
unsigned int block_size = 4 * 1024;
if (g_usDataType & HEAP_IN) {
/*
* Get data from repeat buffer.
*/
if (g_iHeapCounter > g_iHEAPSize) {
/*
* Data over-run.
*/
return 0xFF;
}
ucData = g_pucHeapMemory[g_iHeapCounter++];
} else if (g_usDataType & LHEAP_IN) {
/*
* Get data from intel buffer.
*/
if (g_usIntelDataIndex >= g_usIntelBufferSize) {
return 0xFF;
}
ucData = g_pucIntelBuffer[g_usIntelDataIndex++];
} else {
if (read_bytes == bufsize) {
return 0xFF;
}
ucData = *fpga_image++;
read_bytes++;
if (!(read_bytes % block_size)) {
printf("Downloading FPGA %ld/%ld completed\r",
read_bytes,
bufsize);
}
if (expectedCRC != 0) {
ispVMCalculateCRC32(ucData);
}
}
return ucData;
}
signed char ispVM(void)
{
char szFileVersion[9] = { 0 };
signed char cRetCode = 0;
signed char cIndex = 0;
signed char cVersionIndex = 0;
unsigned char ucReadByte = 0;
unsigned short crc;
g_pucHeapMemory = NULL;
g_iHeapCounter = 0;
g_iHEAPSize = 0;
g_usIntelDataIndex = 0;
g_usIntelBufferSize = 0;
g_usCalculatedCRC = 0;
expectedCRC = 0;
ucReadByte = GetByte();
switch (ucReadByte) {
case FILE_CRC:
crc = (unsigned char)GetByte();
crc <<= 8;
crc |= GetByte();
expectedCRC = crc;
for (cIndex = 0; cIndex < 8; cIndex++)
szFileVersion[cIndex] = GetByte();
break;
default:
szFileVersion[0] = (signed char) ucReadByte;
for (cIndex = 1; cIndex < 8; cIndex++)
szFileVersion[cIndex] = GetByte();
break;
}
/*
*
* Compare the VME file version against the supported version.
*
*/
for (cVersionIndex = 0; g_szSupportedVersions[cVersionIndex] != 0;
cVersionIndex++) {
for (cIndex = 0; cIndex < 8; cIndex++) {
if (szFileVersion[cIndex] !=
g_szSupportedVersions[cVersionIndex][cIndex]) {
cRetCode = VME_VERSION_FAILURE;
break;
}
cRetCode = 0;
}
if (cRetCode == 0) {
break;
}
}
if (cRetCode < 0) {
return VME_VERSION_FAILURE;
}
printf("VME file checked: starting downloading to FPGA\n");
ispVMStart();
cRetCode = ispVMCode();
ispVMEnd();
ispVMFreeMem();
puts("\n");
if (cRetCode == 0 && expectedCRC != 0 &&
(expectedCRC != g_usCalculatedCRC)) {
printf("Expected CRC: 0x%.4X\n", expectedCRC);
printf("Calculated CRC: 0x%.4X\n", g_usCalculatedCRC);
return VME_CRC_FAILURE;
}
return cRetCode;
}
static int lattice_validate(Lattice_desc *desc, const char *fn)
{
int ret_val = FALSE;
if (desc) {
if ((desc->family > min_lattice_type) &&
(desc->family < max_lattice_type)) {
if ((desc->iface > min_lattice_iface_type) &&
(desc->iface < max_lattice_iface_type)) {
if (desc->size) {
ret_val = TRUE;
} else {
printf("%s: NULL part size\n", fn);
}
} else {
printf("%s: Invalid Interface type, %d\n",
fn, desc->iface);
}
} else {
printf("%s: Invalid family type, %d\n",
fn, desc->family);
}
} else {
printf("%s: NULL descriptor!\n", fn);
}
return ret_val;
}
int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
if (!lattice_validate(desc, (char *)__func__)) {
printf("%s: Invalid device descriptor\n", __func__);
} else {
pfns = desc->iface_fns;
switch (desc->family) {
case Lattice_XP2:
fpga_image = buf;
read_bytes = 0;
bufsize = bsize;
debug("%s: Launching the Lattice ISPVME Loader:"
" addr %p size 0x%lx...\n",
__func__, fpga_image, bufsize);
ret_val = ispVM();
if (ret_val)
printf("%s: error %d downloading FPGA image\n",
__func__, ret_val);
else
puts("FPGA downloaded successfully\n");
break;
default:
printf("%s: Unsupported family type, %d\n",
__func__, desc->family);
}
}
return ret_val;
}
int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize)
{
puts("Dump not supported for Lattice FPGA\n");
return FPGA_FAIL;
}
int lattice_info(Lattice_desc *desc)
{
int ret_val = FPGA_FAIL;
if (lattice_validate(desc, (char *)__func__)) {
printf("Family: \t");
switch (desc->family) {
case Lattice_XP2:
puts("XP2\n");
break;
/* Add new family types here */
default:
printf("Unknown family type, %d\n", desc->family);
}
puts("Interface type:\t");
switch (desc->iface) {
case lattice_jtag_mode:
puts("JTAG Mode\n");
break;
/* Add new interface types here */
default:
printf("Unsupported interface type, %d\n", desc->iface);
}
printf("Device Size: \t%d bytes\n",
desc->size);
if (desc->iface_fns) {
printf("Device Function Table @ 0x%p\n",
desc->iface_fns);
switch (desc->family) {
case Lattice_XP2:
break;
/* Add new family types here */
default:
break;
}
} else {
puts("No Device Function Table.\n");
}
if (desc->desc)
printf("Model: \t%s\n", desc->desc);
ret_val = FPGA_SUCCESS;
} else {
printf("%s: Invalid device descriptor\n", __func__);
}
return ret_val;
}
|
1001-study-uboot
|
drivers/fpga/lattice.c
|
C
|
gpl3
| 9,150
|
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libinput.o
COBJS-$(CONFIG_I8042_KBD) += i8042.o
ifdef CONFIG_PS2KBD
COBJS-y += keyboard.o pc_keyb.o
COBJS-$(CONFIG_PS2MULT) += ps2mult.o ps2ser.o
endif
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/input/Makefile
|
Makefile
|
gpl3
| 1,453
|
/***********************************************************************
*
* (C) Copyright 2004
* DENX Software Engineering
* Wolfgang Denk, wd@denx.de
*
* PS/2 multiplexer driver
*
* Originally from linux source (drivers/char/ps2mult.c)
*
* Uses simple serial driver (ps2ser.c) to access the multiplexer
* Used by PS/2 keyboard driver (pc_keyb.c)
*
***********************************************************************/
#include <common.h>
#include <pc_keyb.h>
#include <asm/atomic.h>
#include <ps2mult.h>
/* #define DEBUG_MULT */
/* #define DEBUG_KEYB */
#define KBD_STAT_DEFAULT (KBD_STAT_SELFTEST | KBD_STAT_UNLOCKED)
#define PRINTF(format, args...) printf("ps2mult.c: " format, ## args)
#ifdef DEBUG_MULT
#define PRINTF_MULT(format, args...) printf("PS2MULT: " format, ## args)
#else
#define PRINTF_MULT(format, args...)
#endif
#ifdef DEBUG_KEYB
#define PRINTF_KEYB(format, args...) printf("KEYB: " format, ## args)
#else
#define PRINTF_KEYB(format, args...)
#endif
static ulong start_time;
static int init_done = 0;
static int received_escape = 0;
static int received_bsync = 0;
static int received_selector = 0;
static int kbd_command_active = 0;
static int mouse_command_active = 0;
static int ctl_command_active = 0;
static u_char command_byte = 0;
static void (*keyb_handler)(void *dev_id);
static u_char ps2mult_buf [PS2BUF_SIZE];
static atomic_t ps2mult_buf_cnt;
static int ps2mult_buf_in_idx;
static int ps2mult_buf_out_idx;
static u_char ps2mult_buf_status [PS2BUF_SIZE];
#ifndef CONFIG_BOARD_EARLY_INIT_R
#error #define CONFIG_BOARD_EARLY_INIT_R and call ps2mult_early_init() in board_early_init_r()
#endif
void ps2mult_early_init (void)
{
start_time = get_timer(0);
}
static void ps2mult_send_byte(u_char byte, u_char sel)
{
ps2ser_putc(sel);
if (sel == PS2MULT_KB_SELECTOR) {
PRINTF_MULT("0x%02x send KEYBOARD\n", byte);
kbd_command_active = 1;
} else {
PRINTF_MULT("0x%02x send MOUSE\n", byte);
mouse_command_active = 1;
}
switch (byte) {
case PS2MULT_ESCAPE:
case PS2MULT_BSYNC:
case PS2MULT_KB_SELECTOR:
case PS2MULT_MS_SELECTOR:
case PS2MULT_SESSION_START:
case PS2MULT_SESSION_END:
ps2ser_putc(PS2MULT_ESCAPE);
break;
default:
break;
}
ps2ser_putc(byte);
}
static void ps2mult_receive_byte(u_char byte, u_char sel)
{
u_char status = KBD_STAT_DEFAULT;
#if 1 /* Ignore mouse in U-Boot */
if (sel == PS2MULT_MS_SELECTOR) return;
#endif
if (sel == PS2MULT_KB_SELECTOR) {
if (kbd_command_active) {
if (!received_bsync) {
PRINTF_MULT("0x%02x lost KEYBOARD !!!\n", byte);
return;
} else {
kbd_command_active = 0;
received_bsync = 0;
}
}
PRINTF_MULT("0x%02x receive KEYBOARD\n", byte);
status |= KBD_STAT_IBF | KBD_STAT_OBF;
} else {
if (mouse_command_active) {
if (!received_bsync) {
PRINTF_MULT("0x%02x lost MOUSE !!!\n", byte);
return;
} else {
mouse_command_active = 0;
received_bsync = 0;
}
}
PRINTF_MULT("0x%02x receive MOUSE\n", byte);
status |= KBD_STAT_IBF | KBD_STAT_OBF | KBD_STAT_MOUSE_OBF;
}
if (atomic_read(&ps2mult_buf_cnt) < PS2BUF_SIZE) {
ps2mult_buf_status[ps2mult_buf_in_idx] = status;
ps2mult_buf[ps2mult_buf_in_idx++] = byte;
ps2mult_buf_in_idx &= (PS2BUF_SIZE - 1);
atomic_inc(&ps2mult_buf_cnt);
} else {
PRINTF("buffer overflow\n");
}
if (received_bsync) {
PRINTF("unexpected BSYNC\n");
received_bsync = 0;
}
}
void ps2mult_callback (int in_cnt)
{
int i;
u_char byte;
static int keyb_handler_active = 0;
if (!init_done) {
return;
}
for (i = 0; i < in_cnt; i ++) {
byte = ps2ser_getc();
if (received_escape) {
ps2mult_receive_byte(byte, received_selector);
received_escape = 0;
} else switch (byte) {
case PS2MULT_ESCAPE:
PRINTF_MULT("ESCAPE receive\n");
received_escape = 1;
break;
case PS2MULT_BSYNC:
PRINTF_MULT("BSYNC receive\n");
received_bsync = 1;
break;
case PS2MULT_KB_SELECTOR:
case PS2MULT_MS_SELECTOR:
PRINTF_MULT("%s receive\n",
byte == PS2MULT_KB_SELECTOR ? "KB_SEL" : "MS_SEL");
received_selector = byte;
break;
case PS2MULT_SESSION_START:
case PS2MULT_SESSION_END:
PRINTF_MULT("%s receive\n",
byte == PS2MULT_SESSION_START ?
"SESSION_START" : "SESSION_END");
break;
default:
ps2mult_receive_byte(byte, received_selector);
}
}
if (keyb_handler && !keyb_handler_active &&
atomic_read(&ps2mult_buf_cnt)) {
keyb_handler_active = 1;
keyb_handler(NULL);
keyb_handler_active = 0;
}
}
u_char ps2mult_read_status(void)
{
u_char byte;
if (atomic_read(&ps2mult_buf_cnt) == 0) {
ps2ser_check();
}
if (atomic_read(&ps2mult_buf_cnt)) {
byte = ps2mult_buf_status[ps2mult_buf_out_idx];
} else {
byte = KBD_STAT_DEFAULT;
}
PRINTF_KEYB("read_status()=0x%02x\n", byte);
return byte;
}
u_char ps2mult_read_input(void)
{
u_char byte = 0;
if (atomic_read(&ps2mult_buf_cnt) == 0) {
ps2ser_check();
}
if (atomic_read(&ps2mult_buf_cnt)) {
byte = ps2mult_buf[ps2mult_buf_out_idx++];
ps2mult_buf_out_idx &= (PS2BUF_SIZE - 1);
atomic_dec(&ps2mult_buf_cnt);
}
PRINTF_KEYB("read_input()=0x%02x\n", byte);
return byte;
}
void ps2mult_write_output(u_char val)
{
int i;
PRINTF_KEYB("write_output(0x%02x)\n", val);
for (i = 0; i < KBD_TIMEOUT; i++) {
if (!kbd_command_active && !mouse_command_active) {
break;
}
udelay(1000);
ps2ser_check();
}
if (kbd_command_active) {
PRINTF("keyboard command not acknoledged\n");
kbd_command_active = 0;
}
if (mouse_command_active) {
PRINTF("mouse command not acknoledged\n");
mouse_command_active = 0;
}
if (ctl_command_active) {
switch (ctl_command_active) {
case KBD_CCMD_WRITE_MODE:
/* Scan code conversion not supported */
command_byte = val & ~KBD_MODE_KCC;
break;
case KBD_CCMD_WRITE_AUX_OBUF:
ps2mult_receive_byte(val, PS2MULT_MS_SELECTOR);
break;
case KBD_CCMD_WRITE_MOUSE:
ps2mult_send_byte(val, PS2MULT_MS_SELECTOR);
break;
default:
PRINTF("invalid controller command\n");
break;
}
ctl_command_active = 0;
return;
}
ps2mult_send_byte(val, PS2MULT_KB_SELECTOR);
}
void ps2mult_write_command(u_char val)
{
ctl_command_active = 0;
PRINTF_KEYB("write_command(0x%02x)\n", val);
switch (val) {
case KBD_CCMD_READ_MODE:
ps2mult_receive_byte(command_byte, PS2MULT_KB_SELECTOR);
break;
case KBD_CCMD_WRITE_MODE:
ctl_command_active = val;
break;
case KBD_CCMD_MOUSE_DISABLE:
break;
case KBD_CCMD_MOUSE_ENABLE:
break;
case KBD_CCMD_SELF_TEST:
ps2mult_receive_byte(0x55, PS2MULT_KB_SELECTOR);
break;
case KBD_CCMD_KBD_TEST:
ps2mult_receive_byte(0x00, PS2MULT_KB_SELECTOR);
break;
case KBD_CCMD_KBD_DISABLE:
break;
case KBD_CCMD_KBD_ENABLE:
break;
case KBD_CCMD_WRITE_AUX_OBUF:
ctl_command_active = val;
break;
case KBD_CCMD_WRITE_MOUSE:
ctl_command_active = val;
break;
default:
PRINTF("invalid controller command\n");
break;
}
}
static int ps2mult_getc_w (void)
{
int res = -1;
int i;
for (i = 0; i < KBD_TIMEOUT; i++) {
if (ps2ser_check()) {
res = ps2ser_getc();
break;
}
udelay(1000);
}
switch (res) {
case PS2MULT_KB_SELECTOR:
case PS2MULT_MS_SELECTOR:
received_selector = res;
break;
default:
break;
}
return res;
}
int ps2mult_init (void)
{
int byte;
int kbd_found = 0;
int mouse_found = 0;
while (get_timer(start_time) < CONFIG_PS2MULT_DELAY);
ps2ser_init();
ps2ser_putc(PS2MULT_SESSION_START);
ps2ser_putc(PS2MULT_KB_SELECTOR);
ps2ser_putc(KBD_CMD_RESET);
do {
byte = ps2mult_getc_w();
} while (byte >= 0 && byte != KBD_REPLY_ACK);
if (byte == KBD_REPLY_ACK) {
byte = ps2mult_getc_w();
if (byte == 0xaa) {
kbd_found = 1;
puts("keyboard");
}
}
if (!kbd_found) {
while (byte >= 0) {
byte = ps2mult_getc_w();
}
}
#if 1 /* detect mouse */
ps2ser_putc(PS2MULT_MS_SELECTOR);
ps2ser_putc(AUX_RESET);
do {
byte = ps2mult_getc_w();
} while (byte >= 0 && byte != AUX_ACK);
if (byte == AUX_ACK) {
byte = ps2mult_getc_w();
if (byte == 0xaa) {
byte = ps2mult_getc_w();
if (byte == 0x00) {
mouse_found = 1;
puts(", mouse");
}
}
}
if (!mouse_found) {
while (byte >= 0) {
byte = ps2mult_getc_w();
}
}
#endif
if (mouse_found || kbd_found) {
if (!received_selector) {
if (mouse_found) {
received_selector = PS2MULT_MS_SELECTOR;
} else {
received_selector = PS2MULT_KB_SELECTOR;
}
}
init_done = 1;
} else {
puts("No device found");
}
puts("\n");
#if 0 /* for testing */
{
int i;
u_char key[] = {
0x1f, 0x12, 0x14, 0x12, 0x31, 0x2f, 0x39, /* setenv */
0x1f, 0x14, 0x20, 0x17, 0x31, 0x39, /* stdin */
0x1f, 0x12, 0x13, 0x17, 0x1e, 0x26, 0x1c, /* serial */
};
for (i = 0; i < sizeof (key); i++) {
ps2mult_receive_byte (key[i], PS2MULT_KB_SELECTOR);
ps2mult_receive_byte (key[i] | 0x80, PS2MULT_KB_SELECTOR);
}
}
#endif
return init_done ? 0 : -1;
}
int ps2mult_request_irq(void (*handler)(void *))
{
keyb_handler = handler;
return 0;
}
|
1001-study-uboot
|
drivers/input/ps2mult.c
|
C
|
gpl3
| 9,028
|
/***********************************************************************
*
* (C) Copyright 2004-2009
* DENX Software Engineering
* Wolfgang Denk, wd@denx.de
*
* Simple 16550A serial driver
*
* Originally from linux source (drivers/char/ps2ser.c)
*
* Used by the PS/2 multiplexer driver (ps2mult.c)
*
***********************************************************************/
#include <common.h>
#include <asm/io.h>
#include <asm/atomic.h>
#include <ps2mult.h>
/* This is needed for ns16550.h */
#ifndef CONFIG_SYS_NS16550_REG_SIZE
#define CONFIG_SYS_NS16550_REG_SIZE 1
#endif
#include <ns16550.h>
DECLARE_GLOBAL_DATA_PTR;
/* #define DEBUG */
#define PS2SER_BAUD 57600
#ifdef CONFIG_MPC5xxx
#if CONFIG_PS2SERIAL == 1
#define PSC_BASE MPC5XXX_PSC1
#elif CONFIG_PS2SERIAL == 2
#define PSC_BASE MPC5XXX_PSC2
#elif CONFIG_PS2SERIAL == 3
#define PSC_BASE MPC5XXX_PSC3
#elif CONFIG_PS2SERIAL == 4
#define PSC_BASE MPC5XXX_PSC4
#elif CONFIG_PS2SERIAL == 5
#define PSC_BASE MPC5XXX_PSC5
#elif CONFIG_PS2SERIAL == 6
#define PSC_BASE MPC5XXX_PSC6
#else
#error CONFIG_PS2SERIAL must be in 1 ... 6
#endif
#else
#if CONFIG_PS2SERIAL == 1
#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500)
#elif CONFIG_PS2SERIAL == 2
#define COM_BASE (CONFIG_SYS_CCSRBAR+0x4600)
#else
#error CONFIG_PS2SERIAL must be in 1 ... 2
#endif
#endif /* CONFIG_MPC5xxx / other */
static int ps2ser_getc_hw(void);
static void ps2ser_interrupt(void *dev_id);
extern struct serial_state rs_table[]; /* in serial.c */
static u_char ps2buf[PS2BUF_SIZE];
static atomic_t ps2buf_cnt;
static int ps2buf_in_idx;
static int ps2buf_out_idx;
#ifdef CONFIG_MPC5xxx
int ps2ser_init(void)
{
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
unsigned long baseclk;
int div;
/* reset PSC */
psc->command = PSC_SEL_MODE_REG_1;
/* select clock sources */
psc->psc_clock_select = 0;
baseclk = (gd->ipb_clk + 16) / 32;
/* switch to UART mode */
psc->sicr = 0;
/* configure parity, bit length and so on */
psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
psc->mode = PSC_MODE_ONE_STOP;
/* set up UART divisor */
div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
psc->ctur = (div >> 8) & 0xff;
psc->ctlr = div & 0xff;
/* disable all interrupts */
psc->psc_imr = 0;
/* reset and enable Rx/Tx */
psc->command = PSC_RST_RX;
psc->command = PSC_RST_TX;
psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
return (0);
}
#else
int ps2ser_init(void)
{
NS16550_t com_port = (NS16550_t)COM_BASE;
com_port->ier = 0x00;
com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
com_port->dll = (CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
com_port->dlm = ((CONFIG_SYS_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
com_port->lcr = UART_LCR_8N1;
com_port->mcr = (UART_MCR_DTR | UART_MCR_RTS);
com_port->fcr = (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR);
return (0);
}
#endif /* CONFIG_MPC5xxx / other */
void ps2ser_putc(int chr)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#else
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
debug(">>>> 0x%02x\n", chr);
#ifdef CONFIG_MPC5xxx
while (!(psc->psc_status & PSC_SR_TXRDY));
psc->psc_buffer_8 = chr;
#else
while ((com_port->lsr & UART_LSR_THRE) == 0);
com_port->thr = chr;
#endif
}
static int ps2ser_getc_hw(void)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#else
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int res = -1;
#ifdef CONFIG_MPC5xxx
if (psc->psc_status & PSC_SR_RXRDY) {
res = (psc->psc_buffer_8);
}
#else
if (com_port->lsr & UART_LSR_DR) {
res = com_port->rbr;
}
#endif
return res;
}
int ps2ser_getc(void)
{
volatile int chr;
int flags;
debug("<< ");
flags = disable_interrupts();
do {
if (atomic_read(&ps2buf_cnt) != 0) {
chr = ps2buf[ps2buf_out_idx++];
ps2buf_out_idx &= (PS2BUF_SIZE - 1);
atomic_dec(&ps2buf_cnt);
} else {
chr = ps2ser_getc_hw();
}
}
while (chr < 0);
if (flags)
enable_interrupts();
debug("0x%02x\n", chr);
return chr;
}
int ps2ser_check(void)
{
int flags;
flags = disable_interrupts();
ps2ser_interrupt(NULL);
if (flags) enable_interrupts();
return atomic_read(&ps2buf_cnt);
}
static void ps2ser_interrupt(void *dev_id)
{
#ifdef CONFIG_MPC5xxx
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
#else
NS16550_t com_port = (NS16550_t)COM_BASE;
#endif
int chr;
int status;
do {
chr = ps2ser_getc_hw();
#ifdef CONFIG_MPC5xxx
status = psc->psc_status;
#else
status = com_port->lsr;
#endif
if (chr < 0) continue;
if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
ps2buf[ps2buf_in_idx++] = chr;
ps2buf_in_idx &= (PS2BUF_SIZE - 1);
atomic_inc(&ps2buf_cnt);
} else {
printf ("ps2ser.c: buffer overflow\n");
}
#ifdef CONFIG_MPC5xxx
} while (status & PSC_SR_RXRDY);
#else
} while (status & UART_LSR_DR);
#endif
if (atomic_read(&ps2buf_cnt)) {
ps2mult_callback(atomic_read(&ps2buf_cnt));
}
}
|
1001-study-uboot
|
drivers/input/ps2ser.c
|
C
|
gpl3
| 4,980
|
/*
* (C) Copyright 2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* i8042.c - Intel 8042 keyboard driver routines */
/* includes */
#include <common.h>
#ifdef CONFIG_USE_CPCIDVI
extern u8 gt_cpcidvi_in8(u32 offset);
extern void gt_cpcidvi_out8(u32 offset, u8 data);
#define in8(a) gt_cpcidvi_in8(a)
#define out8(a, b) gt_cpcidvi_out8(a, b)
#endif
#include <i8042.h>
/* defines */
#ifdef CONFIG_CONSOLE_CURSOR
extern void console_cursor(int state);
static int blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT;
static int cursor_state;
#endif
/* locals */
static int kbd_input = -1; /* no input yet */
static int kbd_mapping = KBD_US; /* default US keyboard */
static int kbd_flags = NORMAL; /* after reset */
static int kbd_state; /* unshift code */
static void kbd_conv_char(unsigned char scan_code);
static void kbd_led_set(void);
static void kbd_normal(unsigned char scan_code);
static void kbd_shift(unsigned char scan_code);
static void kbd_ctrl(unsigned char scan_code);
static void kbd_num(unsigned char scan_code);
static void kbd_caps(unsigned char scan_code);
static void kbd_scroll(unsigned char scan_code);
static void kbd_alt(unsigned char scan_code);
static int kbd_input_empty(void);
static int kbd_reset(void);
static unsigned char kbd_fct_map[144] = {
/* kbd_fct_map table for scan code */
0, AS, AS, AS, AS, AS, AS, AS, /* scan 0- 7 */
AS, AS, AS, AS, AS, AS, AS, AS, /* scan 8- F */
AS, AS, AS, AS, AS, AS, AS, AS, /* scan 10-17 */
AS, AS, AS, AS, AS, CN, AS, AS, /* scan 18-1F */
AS, AS, AS, AS, AS, AS, AS, AS, /* scan 20-27 */
AS, AS, SH, AS, AS, AS, AS, AS, /* scan 28-2F */
AS, AS, AS, AS, AS, AS, SH, AS, /* scan 30-37 */
AS, AS, CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, ES, /* scan 40-47 */
ES, ES, ES, ES, ES, ES, ES, ES, /* scan 48-4F */
ES, ES, ES, ES, 0, 0, AS, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
AS, 0, 0, AS, 0, 0, AS, 0, /* scan 70-77 */
0, AS, 0, 0, 0, AS, 0, 0, /* scan 78-7F */
AS, CN, AS, AS, AK, ST, EX, EX, /* enhanced */
AS, EX, EX, AS, EX, AS, EX, EX /* enhanced */
};
static unsigned char kbd_key_map[2][5][144] = {
{ /* US keyboard */
{ /* unshift code */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
'\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* shift code */
0, 0x1b, '!', '@', '#', '$', '%', '^', /* scan 0- 7 */
'&', '*', '(', ')', '_', '+', 0x08, '\t', /* scan 8- F */
'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', /* scan 10-17 */
'O', 'P', '{', '}', '\r', CN, 'A', 'S', /* scan 18-1F */
'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', /* scan 20-27 */
'"', '~', SH, '|', 'Z', 'X', 'C', 'V', /* scan 28-2F */
'B', 'N', 'M', '<', '>', '?', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', '.', 0, 0, 0, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* control code */
0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
},
{ /* non numeric code */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', '-', '=', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', /* scan 10-17 */
'o', 'p', '[', ']', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', ';', /* scan 20-27 */
'\'', '`', SH, '\\', 'z', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '/', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
'r', 's', 'p', 'n', 0, 0, 0, 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* right alt mode - not used in US keyboard */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 8 - F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50 -57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
}
},
{ /* german keyboard */
{ /* unshift code */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
0x84, '^', SH, '#', 'y', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', ',', 0, 0, '<', 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* shift code */
0, 0x1b, '!', '"', 0x15, '$', '%', '&', /* scan 0- 7 */
'/', '(', ')', '=', '?', '`', 0x08, '\t', /* scan 8- F */
'Q', 'W', 'E', 'R', 'T', 'Z', 'U', 'I', /* scan 10-17 */
'O', 'P', 0x9a, '*', '\r', CN, 'A', 'S', /* scan 18-1F */
'D', 'F', 'G', 'H', 'J', 'K', 'L', 0x99, /* scan 20-27 */
0x8e, 0xf8, SH, '\'', 'Y', 'X', 'C', 'V', /* scan 28-2F */
'B', 'N', 'M', ';', ':', '_', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, '7', /* scan 40-47 */
'8', '9', '-', '4', '5', '6', '+', '1', /* scan 48-4F */
'2', '3', '0', ',', 0, 0, '>', 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* control code */
0xff, 0x1b, 0xff, 0x00, 0xff, 0xff, 0xff, 0xff, /* scan 0- 7 */
0x1e, 0xff, 0xff, 0xff, 0x1f, 0xff, 0xff, '\t', /* scan 8- F */
0x11, 0x17, 0x05, 0x12, 0x14, 0x19, 0x15, 0x09, /* scan 10-17 */
0x0f, 0x10, 0x1b, 0x1d, '\r', CN, 0x01, 0x13, /* scan 18-1F */
0x04, 0x06, 0x07, 0x08, 0x0a, 0x0b, 0x0c, 0xff, /* scan 20-27 */
0xff, 0x1c, SH, 0xff, 0x1a, 0x18, 0x03, 0x16, /* scan 28-2F */
0x02, 0x0e, 0x0d, 0xff, 0xff, 0xff, SH, 0xff, /* scan 30-37 */
0xff, 0xff, CP, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38-3F */
0xff, 0xff, 0xff, 0xff, 0xff, NM, ST, 0xff, /* scan 40-47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48-4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 50-57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58-5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60-67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68-6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70-77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
},
{ /* non numeric code */
0, 0x1b, '1', '2', '3', '4', '5', '6', /* scan 0- 7 */
'7', '8', '9', '0', 0xe1, '\'', 0x08, '\t', /* scan 8- F */
'q', 'w', 'e', 'r', 't', 'z', 'u', 'i', /* scan 10-17 */
'o', 'p', 0x81, '+', '\r', CN, 'a', 's', /* scan 18-1F */
'd', 'f', 'g', 'h', 'j', 'k', 'l', 0x94, /* scan 20-27 */
0x84, '^', SH, 0, 'y', 'x', 'c', 'v', /* scan 28-2F */
'b', 'n', 'm', ',', '.', '-', SH, '*', /* scan 30-37 */
' ', ' ', CP, 0, 0, 0, 0, 0, /* scan 38-3F */
0, 0, 0, 0, 0, NM, ST, 'w', /* scan 40-47 */
'x', 'y', 'l', 't', 'u', 'v', 'm', 'q', /* scan 48-4F */
'r', 's', 'p', 'n', 0, 0, '<', 0, /* scan 50-57 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 58-5F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 60-67 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 68-6F */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 70-77 */
0, 0, 0, 0, 0, 0, 0, 0, /* scan 78-7F */
'\r', CN, '/', '*', ' ', ST, 'F', 'A', /* extended */
0, 'D', 'C', 0, 'B', 0, '@', 'P' /* extended */
},
{ /* Right alt mode - is used in German keyboard */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 0 - 7 */
'{', '[', ']', '}', '\\', 0xff, 0xff, 0xff, /* scan 8 - F */
'@', 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 10 -17 */
0xff, 0xff, 0xff, '~', 0xff, 0xff, 0xff, 0xff, /* scan 18 -1F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 20 -27 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 28 -2F */
0xff, 0xff, 0xe6, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 30 -37 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 38 -3F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 40 -47 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 48 -4F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, '|', 0xff, /* scan 50 -57 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 58 -5F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 60 -67 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 68 -6F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 70 -77 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* scan 78 -7F */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* extended */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff /* extended */
}
}
};
static unsigned char ext_key_map[] = {
0x1c, /* keypad enter */
0x1d, /* right control */
0x35, /* keypad slash */
0x37, /* print screen */
0x38, /* right alt */
0x46, /* break */
0x47, /* editpad home */
0x48, /* editpad up */
0x49, /* editpad pgup */
0x4b, /* editpad left */
0x4d, /* editpad right */
0x4f, /* editpad end */
0x50, /* editpad dn */
0x51, /* editpad pgdn */
0x52, /* editpad ins */
0x53, /* editpad del */
0x00 /* map end */
};
/******************************************************************************/
static int kbd_controller_present(void)
{
return in8(I8042_STATUS_REG) != 0xff;
}
/*******************************************************************************
*
* i8042_kbd_init - reset keyboard and init state flags
*/
int i8042_kbd_init(void)
{
int keymap, try;
char *penv;
if (!kbd_controller_present())
return -1;
#ifdef CONFIG_USE_CPCIDVI
penv = getenv("console");
if (penv != NULL) {
if (strncmp(penv, "serial", 7) == 0)
return -1;
}
#endif
/* Init keyboard device (default US layout) */
keymap = KBD_US;
penv = getenv("keymap");
if (penv != NULL) {
if (strncmp(penv, "de", 3) == 0)
keymap = KBD_GER;
}
for (try = 0; try < KBD_RESET_TRIES; try++) {
if (kbd_reset() == 0) {
kbd_mapping = keymap;
kbd_flags = NORMAL;
kbd_state = 0;
kbd_led_set();
return 0;
}
}
return -1;
}
/*******************************************************************************
*
* i8042_tstc - test if keyboard input is available
* option: cursor blinking if called in a loop
*/
int i8042_tstc(void)
{
unsigned char scan_code = 0;
#ifdef CONFIG_CONSOLE_CURSOR
if (--blinkCount == 0) {
cursor_state ^= 1;
console_cursor(cursor_state);
blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT;
udelay(10);
}
#endif
if ((in8(I8042_STATUS_REG) & 0x01) == 0) {
return 0;
} else {
scan_code = in8(I8042_DATA_REG);
if (scan_code == 0xfa)
return 0;
kbd_conv_char(scan_code);
if (kbd_input != -1)
return 1;
}
return 0;
}
/*******************************************************************************
*
* i8042_getc - wait till keyboard input is available
* option: turn on/off cursor while waiting
*/
int i8042_getc(void)
{
int ret_chr;
unsigned char scan_code;
while (kbd_input == -1) {
while ((in8(I8042_STATUS_REG) & 0x01) == 0) {
#ifdef CONFIG_CONSOLE_CURSOR
if (--blinkCount == 0) {
cursor_state ^= 1;
console_cursor(cursor_state);
blinkCount = CONFIG_SYS_CONSOLE_BLINK_COUNT;
}
udelay(10);
#endif
}
scan_code = in8(I8042_DATA_REG);
if (scan_code != 0xfa)
kbd_conv_char (scan_code);
}
ret_chr = kbd_input;
kbd_input = -1;
return ret_chr;
}
/******************************************************************************/
static void kbd_conv_char(unsigned char scan_code)
{
if (scan_code == 0xe0) {
kbd_flags |= EXT;
return;
}
/* if high bit of scan_code, set break flag */
if (scan_code & 0x80)
kbd_flags |= BRK;
else
kbd_flags &= ~BRK;
if ((scan_code == 0xe1) || (kbd_flags & E1)) {
if (scan_code == 0xe1) {
kbd_flags ^= BRK; /* reset the break flag */
kbd_flags ^= E1; /* bitwise EXOR with E1 flag */
}
return;
}
scan_code &= 0x7f;
if (kbd_flags & EXT) {
int i;
kbd_flags ^= EXT;
for (i = 0; ext_key_map[i]; i++) {
if (ext_key_map[i] == scan_code) {
scan_code = 0x80 + i;
break;
}
}
/* not found ? */
if (!ext_key_map[i])
return;
}
switch (kbd_fct_map[scan_code]) {
case AS:
kbd_normal(scan_code);
break;
case SH:
kbd_shift(scan_code);
break;
case CN:
kbd_ctrl(scan_code);
break;
case NM:
kbd_num(scan_code);
break;
case CP:
kbd_caps(scan_code);
break;
case ST:
kbd_scroll(scan_code);
break;
case AK:
kbd_alt(scan_code);
break;
}
return;
}
/******************************************************************************/
static void kbd_normal(unsigned char scan_code)
{
unsigned char chr;
if ((kbd_flags & BRK) == NORMAL) {
chr = kbd_key_map[kbd_mapping][kbd_state][scan_code];
if ((chr == 0xff) || (chr == 0x00))
return;
/* if caps lock convert upper to lower */
if (((kbd_flags & CAPS) == CAPS) &&
(chr >= 'a' && chr <= 'z')) {
chr -= 'a' - 'A';
}
kbd_input = chr;
}
}
/******************************************************************************/
static void kbd_shift(unsigned char scan_code)
{
if ((kbd_flags & BRK) == BRK) {
kbd_state = AS;
kbd_flags &= (~SHIFT);
} else {
kbd_state = SH;
kbd_flags |= SHIFT;
}
}
/******************************************************************************/
static void kbd_ctrl(unsigned char scan_code)
{
if ((kbd_flags & BRK) == BRK) {
kbd_state = AS;
kbd_flags &= (~CTRL);
} else {
kbd_state = CN;
kbd_flags |= CTRL;
}
}
/******************************************************************************/
static void kbd_caps(unsigned char scan_code)
{
if ((kbd_flags & BRK) == NORMAL) {
kbd_flags ^= CAPS;
kbd_led_set(); /* update keyboard LED */
}
}
/******************************************************************************/
static void kbd_num(unsigned char scan_code)
{
if ((kbd_flags & BRK) == NORMAL) {
kbd_flags ^= NUM;
kbd_state = (kbd_flags & NUM) ? AS : NM;
kbd_led_set(); /* update keyboard LED */
}
}
/******************************************************************************/
static void kbd_scroll(unsigned char scan_code)
{
if ((kbd_flags & BRK) == NORMAL) {
kbd_flags ^= STP;
kbd_led_set(); /* update keyboard LED */
if (kbd_flags & STP)
kbd_input = 0x13;
else
kbd_input = 0x11;
}
}
/******************************************************************************/
static void kbd_alt(unsigned char scan_code)
{
if ((kbd_flags & BRK) == BRK) {
kbd_state = AS;
kbd_flags &= (~ALT);
} else {
kbd_state = AK;
kbd_flags &= ALT;
}
}
/******************************************************************************/
static void kbd_led_set(void)
{
kbd_input_empty();
out8(I8042_DATA_REG, 0xed); /* SET LED command */
kbd_input_empty();
out8(I8042_DATA_REG, (kbd_flags & 0x7)); /* LED bits only */
}
/******************************************************************************/
static int kbd_input_empty(void)
{
int kbdTimeout = KBD_TIMEOUT;
/* wait for input buf empty */
while ((in8(I8042_STATUS_REG) & 0x02) && kbdTimeout--)
udelay(1000);
return kbdTimeout != -1;
}
/******************************************************************************/
static int kbd_reset(void)
{
if (kbd_input_empty() == 0)
return -1;
out8(I8042_DATA_REG, 0xff);
udelay(250000);
if (kbd_input_empty() == 0)
return -1;
#ifdef CONFIG_USE_CPCIDVI
out8(I8042_COMMAND_REG, 0x60);
#else
out8(I8042_DATA_REG, 0x60);
#endif
if (kbd_input_empty() == 0)
return -1;
out8(I8042_DATA_REG, 0x45);
if (kbd_input_empty() == 0)
return -1;
out8(I8042_COMMAND_REG, 0xae);
if (kbd_input_empty() == 0)
return -1;
return 0;
}
|
1001-study-uboot
|
drivers/input/i8042.c
|
C
|
gpl3
| 22,491
|
/***********************************************************************
*
* (C) Copyright 2004
* DENX Software Engineering
* Wolfgang Denk, wd@denx.de
*
* PS/2 keyboard driver
*
* Originally from linux source (drivers/char/pc_keyb.c)
*
***********************************************************************/
#include <common.h>
#include <keyboard.h>
#include <pc_keyb.h>
#undef KBG_DEBUG
#ifdef KBG_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
/*
* This reads the keyboard status port, and does the
* appropriate action.
*
*/
static unsigned char handle_kbd_event(void)
{
unsigned char status = kbd_read_status();
unsigned int work = 10000;
while ((--work > 0) && (status & KBD_STAT_OBF)) {
unsigned char scancode;
scancode = kbd_read_input();
/* Error bytes must be ignored to make the
Synaptics touchpads compaq use work */
/* Ignore error bytes */
if (!(status & (KBD_STAT_GTO | KBD_STAT_PERR))) {
if (status & KBD_STAT_MOUSE_OBF)
; /* not supported: handle_mouse_event(scancode); */
else
handle_scancode(scancode);
}
status = kbd_read_status();
}
if (!work)
PRINTF("pc_keyb: controller jammed (0x%02X).\n", status);
return status;
}
static int kbd_read_data(void)
{
int val;
unsigned char status;
val = -1;
status = kbd_read_status();
if (status & KBD_STAT_OBF) {
val = kbd_read_input();
if (status & (KBD_STAT_GTO | KBD_STAT_PERR))
val = -2;
}
return val;
}
static int kbd_wait_for_input(void)
{
unsigned long timeout;
int val;
timeout = KBD_TIMEOUT;
val=kbd_read_data();
while(val < 0) {
if(timeout--==0)
return -1;
udelay(1000);
val=kbd_read_data();
}
return val;
}
static int kb_wait(void)
{
unsigned long timeout = KBC_TIMEOUT * 10;
do {
unsigned char status = handle_kbd_event();
if (!(status & KBD_STAT_IBF))
return 0; /* ok */
udelay(1000);
timeout--;
} while (timeout);
return 1;
}
static void kbd_write_command_w(int data)
{
if(kb_wait())
PRINTF("timeout in kbd_write_command_w\n");
kbd_write_command(data);
}
static void kbd_write_output_w(int data)
{
if(kb_wait())
PRINTF("timeout in kbd_write_output_w\n");
kbd_write_output(data);
}
static void kbd_send_data(unsigned char data)
{
kbd_write_output_w(data);
kbd_wait_for_input();
}
static char * kbd_initialize(void)
{
int status;
/*
* Test the keyboard interface.
* This seems to be the only way to get it going.
* If the test is successful a x55 is placed in the input buffer.
*/
kbd_write_command_w(KBD_CCMD_SELF_TEST);
if (kbd_wait_for_input() != 0x55)
return "Kbd: failed self test";
/*
* Perform a keyboard interface test. This causes the controller
* to test the keyboard clock and data lines. The results of the
* test are placed in the input buffer.
*/
kbd_write_command_w(KBD_CCMD_KBD_TEST);
if (kbd_wait_for_input() != 0x00)
return "Kbd: interface failed self test";
/*
* Enable the keyboard by allowing the keyboard clock to run.
*/
kbd_write_command_w(KBD_CCMD_KBD_ENABLE);
/*
* Reset keyboard. If the read times out
* then the assumption is that no keyboard is
* plugged into the machine.
* This defaults the keyboard to scan-code set 2.
*
* Set up to try again if the keyboard asks for RESEND.
*/
do {
kbd_write_output_w(KBD_CMD_RESET);
status = kbd_wait_for_input();
if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND) {
PRINTF("status: %X\n",status);
return "Kbd: reset failed, no ACK";
}
} while (1);
if (kbd_wait_for_input() != KBD_REPLY_POR)
return "Kbd: reset failed, no POR";
/*
* Set keyboard controller mode. During this, the keyboard should be
* in the disabled state.
*
* Set up to try again if the keyboard asks for RESEND.
*/
do {
kbd_write_output_w(KBD_CMD_DISABLE);
status = kbd_wait_for_input();
if (status == KBD_REPLY_ACK)
break;
if (status != KBD_REPLY_RESEND)
return "Kbd: disable keyboard: no ACK";
} while (1);
kbd_write_command_w(KBD_CCMD_WRITE_MODE);
kbd_write_output_w(KBD_MODE_KBD_INT
| KBD_MODE_SYS
| KBD_MODE_DISABLE_MOUSE
| KBD_MODE_KCC);
/* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
kbd_write_command_w(KBD_CCMD_READ_MODE);
if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
/*
* If the controller does not support conversion,
* Set the keyboard to scan-code set 1.
*/
kbd_write_output_w(0xF0);
kbd_wait_for_input();
kbd_write_output_w(0x01);
kbd_wait_for_input();
}
kbd_write_output_w(KBD_CMD_ENABLE);
if (kbd_wait_for_input() != KBD_REPLY_ACK)
return "Kbd: enable keyboard: no ACK";
/*
* Finally, set the typematic rate to maximum.
*/
kbd_write_output_w(KBD_CMD_SET_RATE);
if (kbd_wait_for_input() != KBD_REPLY_ACK)
return "Kbd: Set rate: no ACK";
kbd_write_output_w(0x00);
if (kbd_wait_for_input() != KBD_REPLY_ACK)
return "Kbd: Set rate: no ACK";
return NULL;
}
static void kbd_interrupt(void *dev_id)
{
handle_kbd_event();
}
/******************************************************************
* Init
******************************************************************/
int kbd_init_hw(void)
{
char* result;
kbd_request_region();
result=kbd_initialize();
if (result==NULL) {
PRINTF("AT Keyboard initialized\n");
kbd_request_irq(kbd_interrupt);
return (1);
} else {
printf("%s\n",result);
return (-1);
}
}
void pckbd_leds(unsigned char leds)
{
kbd_send_data(KBD_CMD_SET_LEDS);
kbd_send_data(leds);
}
|
1001-study-uboot
|
drivers/input/pc_keyb.c
|
C
|
gpl3
| 5,554
|
/***********************************************************************
*
* (C) Copyright 2004
* DENX Software Engineering
* Wolfgang Denk, wd@denx.de
*
* Keyboard driver
*
***********************************************************************/
#include <common.h>
#include <stdio_dev.h>
#include <keyboard.h>
#undef KBG_DEBUG
#ifdef KBG_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
#define DEVNAME "kbd"
#define LED_SCR 0x01 /* scroll lock led */
#define LED_CAP 0x04 /* caps lock led */
#define LED_NUM 0x02 /* num lock led */
#define KBD_BUFFER_LEN 0x20 /* size of the keyboardbuffer */
#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
int ps2ser_check(void);
#endif
static volatile char kbd_buffer[KBD_BUFFER_LEN];
static volatile int in_pointer = 0;
static volatile int out_pointer = 0;
static unsigned char leds = 0;
static unsigned char num_lock = 0;
static unsigned char caps_lock = 0;
static unsigned char scroll_lock = 0;
static unsigned char shift = 0;
static unsigned char ctrl = 0;
static unsigned char alt = 0;
static unsigned char e0 = 0;
/******************************************************************
* Queue handling
******************************************************************/
/* puts character in the queue and sets up the in and out pointer */
static void kbd_put_queue(char data)
{
if((in_pointer+1)==KBD_BUFFER_LEN) {
if(out_pointer==0) {
return; /* buffer full */
} else{
in_pointer=0;
}
} else {
if((in_pointer+1)==out_pointer)
return; /* buffer full */
in_pointer++;
}
kbd_buffer[in_pointer]=data;
return;
}
/* test if a character is in the queue */
static int kbd_testc(void)
{
#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
#endif
if(in_pointer==out_pointer)
return(0); /* no data */
else
return(1);
}
/* gets the character from the queue */
static int kbd_getc(void)
{
char c;
while(in_pointer==out_pointer) {
#if defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
/* no ISR is used, so received chars must be polled */
ps2ser_check();
#endif
;}
if((out_pointer+1)==KBD_BUFFER_LEN)
out_pointer=0;
else
out_pointer++;
c=kbd_buffer[out_pointer];
return (int)c;
}
/* Simple translation table for the keys */
static unsigned char kbd_plain_xlate[] = {
0xff,0x1b, '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', '-', '=','\b','\t', /* 0x00 - 0x0f */
'q', 'w', 'e', 'r', 't', 'y', 'u', 'i', 'o', 'p', '[', ']','\r',0xff, 'a', 's', /* 0x10 - 0x1f */
'd', 'f', 'g', 'h', 'j', 'k', 'l', ';','\'', '`',0xff,'\\', 'z', 'x', 'c', 'v', /* 0x20 - 0x2f */
'b', 'n', 'm', ',', '.', '/',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
'2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
'\r',0xff,0xff
};
static unsigned char kbd_shift_xlate[] = {
0xff,0x1b, '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', '+','\b','\t', /* 0x00 - 0x0f */
'Q', 'W', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', 'P', '{', '}','\r',0xff, 'A', 'S', /* 0x10 - 0x1f */
'D', 'F', 'G', 'H', 'J', 'K', 'L', ':', '"', '~',0xff, '|', 'Z', 'X', 'C', 'V', /* 0x20 - 0x2f */
'B', 'N', 'M', '<', '>', '?',0xff,0xff,0xff, ' ',0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
'2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
'\r',0xff,0xff
};
static unsigned char kbd_ctrl_xlate[] = {
0xff,0x1b, '1',0x00, '3', '4', '5',0x1E, '7', '8', '9', '0',0x1F, '=','\b','\t', /* 0x00 - 0x0f */
0x11,0x17,0x05,0x12,0x14,0x18,0x15,0x09,0x0f,0x10,0x1b,0x1d,'\n',0xff,0x01,0x13, /* 0x10 - 0x1f */
0x04,0x06,0x08,0x09,0x0a,0x0b,0x0c, ';','\'', '~',0x00,0x1c,0x1a,0x18,0x03,0x16, /* 0x20 - 0x2f */
0x02,0x0e,0x0d, '<', '>', '?',0xff,0xff,0xff,0x00,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x30 - 0x3f */
0xff,0xff,0xff,0xff,0xff,0xff,0xff, '7', '8', '9', '-', '4', '5', '6', '+', '1', /* 0x40 - 0x4f */
'2', '3', '0', '.',0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, /* 0x50 - 0x5F */
'\r',0xff,0xff
};
void handle_scancode(unsigned char scancode)
{
unsigned char keycode;
/* Convert scancode to keycode */
PRINTF("scancode %x\n",scancode);
if(scancode==0xe0) {
e0=1; /* special charakters */
return;
}
if(e0==1) {
e0=0; /* delete flag */
if(!( ((scancode&0x7F)==0x38)|| /* the right ctrl key */
((scancode&0x7F)==0x1D)|| /* the right alt key */
((scancode&0x7F)==0x35)|| /* the right '/' key */
((scancode&0x7F)==0x1C) )) /* the right enter key */
/* we swallow unknown e0 codes */
return;
}
/* special cntrl keys */
switch(scancode) {
case 0x2A:
case 0x36: /* shift pressed */
shift=1;
return; /* do nothing else */
case 0xAA:
case 0xB6: /* shift released */
shift=0;
return; /* do nothing else */
case 0x38: /* alt pressed */
alt=1;
return; /* do nothing else */
case 0xB8: /* alt released */
alt=0;
return; /* do nothing else */
case 0x1d: /* ctrl pressed */
ctrl=1;
return; /* do nothing else */
case 0x9d: /* ctrl released */
ctrl=0;
return; /* do nothing else */
case 0x46: /* scrollock pressed */
scroll_lock=~scroll_lock;
if(scroll_lock==0)
leds&=~LED_SCR; /* switch LED off */
else
leds|=LED_SCR; /* switch on LED */
pckbd_leds(leds);
return; /* do nothing else */
case 0x3A: /* capslock pressed */
caps_lock=~caps_lock;
if(caps_lock==0)
leds&=~LED_CAP; /* switch caps_lock off */
else
leds|=LED_CAP; /* switch on LED */
pckbd_leds(leds);
return;
case 0x45: /* numlock pressed */
num_lock=~num_lock;
if(num_lock==0)
leds&=~LED_NUM; /* switch LED off */
else
leds|=LED_NUM; /* switch on LED */
pckbd_leds(leds);
return;
case 0xC6: /* scroll lock released */
case 0xC5: /* num lock released */
case 0xBA: /* caps lock released */
return; /* just swallow */
}
#if 1
if((scancode&0x80)==0x80) /* key released */
return;
#else
if((scancode&0x80)==0x00) /* key pressed */
return;
scancode &= ~0x80;
#endif
/* now, decide which table we need */
if(scancode > (sizeof(kbd_plain_xlate)/sizeof(kbd_plain_xlate[0]))) { /* scancode not in list */
PRINTF("unkown scancode %X\n",scancode);
return; /* swallow it */
}
/* setup plain code first */
keycode=kbd_plain_xlate[scancode];
if(caps_lock==1) { /* caps_lock is pressed, overwrite plain code */
if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF("unkown caps-locked scancode %X\n",scancode);
return; /* swallow it */
}
keycode=kbd_shift_xlate[scancode];
if(keycode<'A') { /* we only want the alphas capital */
keycode=kbd_plain_xlate[scancode];
}
}
if(shift==1) { /* shift overwrites caps_lock */
if(scancode > (sizeof(kbd_shift_xlate)/sizeof(kbd_shift_xlate[0]))) { /* scancode not in list */
PRINTF("unkown shifted scancode %X\n",scancode);
return; /* swallow it */
}
keycode=kbd_shift_xlate[scancode];
}
if(ctrl==1) { /* ctrl overwrites caps_lock and shift */
if(scancode > (sizeof(kbd_ctrl_xlate)/sizeof(kbd_ctrl_xlate[0]))) { /* scancode not in list */
PRINTF("unkown ctrl scancode %X\n",scancode);
return; /* swallow it */
}
keycode=kbd_ctrl_xlate[scancode];
}
/* check if valid keycode */
if(keycode==0xff) {
PRINTF("unkown scancode %X\n",scancode);
return; /* swallow unknown codes */
}
kbd_put_queue(keycode);
PRINTF("%x\n",keycode);
}
/******************************************************************
* Init
******************************************************************/
#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
extern int overwrite_console (void);
#define OVERWRITE_CONSOLE overwrite_console ()
#else
#define OVERWRITE_CONSOLE 0
#endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */
int kbd_init (void)
{
int error;
struct stdio_dev kbddev ;
char *stdinname = getenv ("stdin");
if(kbd_init_hw()==-1)
return -1;
memset (&kbddev, 0, sizeof(kbddev));
strcpy(kbddev.name, DEVNAME);
kbddev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
kbddev.putc = NULL ;
kbddev.puts = NULL ;
kbddev.getc = kbd_getc ;
kbddev.tstc = kbd_testc ;
error = stdio_register (&kbddev);
if(error==0) {
/* check if this is the standard input device */
if(strcmp(stdinname,DEVNAME)==0) {
/* reassign the console */
if(OVERWRITE_CONSOLE) {
return 1;
}
error=console_assign(stdin,DEVNAME);
if(error==0)
return 1;
else
return error;
}
return 1;
}
return error;
}
|
1001-study-uboot
|
drivers/input/keyboard.c
|
C
|
gpl3
| 8,937
|
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Driver for DS4510, a CPU supervisor with integrated EEPROM, SRAM,
* and 4 programmable non-volatile GPIO pins.
*/
#include <common.h>
#include <i2c.h>
#include <command.h>
#include <ds4510.h>
/* Default to an address that hopefully won't corrupt other i2c devices */
#ifndef CONFIG_SYS_I2C_DS4510_ADDR
#define CONFIG_SYS_I2C_DS4510_ADDR (~0)
#endif
enum {
DS4510_CMD_INFO,
DS4510_CMD_DEVICE,
DS4510_CMD_NV,
DS4510_CMD_RSTDELAY,
DS4510_CMD_OUTPUT,
DS4510_CMD_INPUT,
DS4510_CMD_PULLUP,
DS4510_CMD_EEPROM,
DS4510_CMD_SEEPROM,
DS4510_CMD_SRAM,
};
/*
* Write to DS4510, taking page boundaries into account
*/
int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count)
{
int wrlen;
int i = 0;
do {
wrlen = DS4510_EEPROM_PAGE_SIZE -
DS4510_EEPROM_PAGE_OFFSET(offset);
if (count < wrlen)
wrlen = count;
if (i2c_write(chip, offset, 1, &buf[i], wrlen))
return -1;
/*
* This delay isn't needed for SRAM writes but shouldn't delay
* things too much, so do it unconditionally for simplicity
*/
udelay(DS4510_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
count -= wrlen;
offset += wrlen;
i += wrlen;
} while (count > 0);
return 0;
}
/*
* General read from DS4510
*/
int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count)
{
return i2c_read(chip, offset, 1, buf, count);
}
/*
* Write SEE bit in config register.
* nv = 0 - Writes to SEEPROM registers behave like EEPROM
* nv = 1 - Writes to SEEPROM registers behave like SRAM
*/
int ds4510_see_write(uint8_t chip, uint8_t nv)
{
uint8_t data;
if (i2c_read(chip, DS4510_CFG, 1, &data, 1))
return -1;
if (nv) /* Treat SEEPROM bits as EEPROM */
data &= ~DS4510_CFG_SEE;
else /* Treat SEEPROM bits as SRAM */
data |= DS4510_CFG_SEE;
return ds4510_mem_write(chip, DS4510_CFG, &data, 1);
}
/*
* Write de-assertion of reset signal delay
*/
int ds4510_rstdelay_write(uint8_t chip, uint8_t delay)
{
uint8_t data;
if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1))
return -1;
data &= ~DS4510_RSTDELAY_MASK;
data |= delay & DS4510_RSTDELAY_MASK;
return ds4510_mem_write(chip, DS4510_RSTDELAY, &data, 1);
}
/*
* Write pullup characteristics of IO pins
*/
int ds4510_pullup_write(uint8_t chip, uint8_t val)
{
val &= DS4510_IO_MASK;
return ds4510_mem_write(chip, DS4510_PULLUP, (uint8_t *)&val, 1);
}
/*
* Read pullup characteristics of IO pins
*/
int ds4510_pullup_read(uint8_t chip)
{
uint8_t val;
if (i2c_read(chip, DS4510_PULLUP, 1, &val, 1))
return -1;
return val & DS4510_IO_MASK;
}
/*
* Write drive level of IO pins
*/
int ds4510_gpio_write(uint8_t chip, uint8_t val)
{
uint8_t data;
int i;
for (i = 0; i < DS4510_NUM_IO; i++) {
if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1))
return -1;
if (val & (0x1 << i))
data |= 0x1;
else
data &= ~0x1;
if (ds4510_mem_write(chip, DS4510_IO0 - i, &data, 1))
return -1;
}
return 0;
}
/*
* Read drive level of IO pins
*/
int ds4510_gpio_read(uint8_t chip)
{
uint8_t data;
int val = 0;
int i;
for (i = 0; i < DS4510_NUM_IO; i++) {
if (i2c_read(chip, DS4510_IO0 - i, 1, &data, 1))
return -1;
if (data & 1)
val |= (1 << i);
}
return val;
}
/*
* Read physical level of IO pins
*/
int ds4510_gpio_read_val(uint8_t chip)
{
uint8_t val;
if (i2c_read(chip, DS4510_IO_STATUS, 1, &val, 1))
return -1;
return val & DS4510_IO_MASK;
}
#ifdef CONFIG_CMD_DS4510
#ifdef CONFIG_CMD_DS4510_INFO
/*
* Display DS4510 information
*/
static int ds4510_info(uint8_t chip)
{
int i;
int tmp;
uint8_t data;
printf("DS4510 @ 0x%x:\n\n", chip);
if (i2c_read(chip, DS4510_RSTDELAY, 1, &data, 1))
return -1;
printf("rstdelay = 0x%x\n\n", data & DS4510_RSTDELAY_MASK);
if (i2c_read(chip, DS4510_CFG, 1, &data, 1))
return -1;
printf("config = 0x%x\n", data);
printf(" /ready = %d\n", data & DS4510_CFG_READY ? 1 : 0);
printf(" trip pt = %d\n", data & DS4510_CFG_TRIP_POINT ? 1 : 0);
printf(" rst sts = %d\n", data & DS4510_CFG_RESET ? 1 : 0);
printf(" /see = %d\n", data & DS4510_CFG_SEE ? 1 : 0);
printf(" swrst = %d\n\n", data & DS4510_CFG_SWRST ? 1 : 0);
printf("gpio pins: 3210\n");
printf("---------------\n");
printf("pullup ");
tmp = ds4510_pullup_read(chip);
if (tmp == -1)
return tmp;
for (i = DS4510_NUM_IO - 1; i >= 0; i--)
printf("%d", (tmp & (1 << i)) ? 1 : 0);
printf("\n");
printf("driven ");
tmp = ds4510_gpio_read(chip);
if (tmp == -1)
return -1;
for (i = DS4510_NUM_IO - 1; i >= 0; i--)
printf("%d", (tmp & (1 << i)) ? 1 : 0);
printf("\n");
printf("read ");
tmp = ds4510_gpio_read_val(chip);
if (tmp == -1)
return -1;
for (i = DS4510_NUM_IO - 1; i >= 0; i--)
printf("%d", (tmp & (1 << i)) ? 1 : 0);
printf("\n");
return 0;
}
#endif /* CONFIG_CMD_DS4510_INFO */
cmd_tbl_t cmd_ds4510[] = {
U_BOOT_CMD_MKENT(device, 3, 0, (void *)DS4510_CMD_DEVICE, "", ""),
U_BOOT_CMD_MKENT(nv, 3, 0, (void *)DS4510_CMD_NV, "", ""),
U_BOOT_CMD_MKENT(output, 4, 0, (void *)DS4510_CMD_OUTPUT, "", ""),
U_BOOT_CMD_MKENT(input, 3, 0, (void *)DS4510_CMD_INPUT, "", ""),
U_BOOT_CMD_MKENT(pullup, 4, 0, (void *)DS4510_CMD_PULLUP, "", ""),
#ifdef CONFIG_CMD_DS4510_INFO
U_BOOT_CMD_MKENT(info, 2, 0, (void *)DS4510_CMD_INFO, "", ""),
#endif
#ifdef CONFIG_CMD_DS4510_RST
U_BOOT_CMD_MKENT(rstdelay, 3, 0, (void *)DS4510_CMD_RSTDELAY, "", ""),
#endif
#ifdef CONFIG_CMD_DS4510_MEM
U_BOOT_CMD_MKENT(eeprom, 6, 0, (void *)DS4510_CMD_EEPROM, "", ""),
U_BOOT_CMD_MKENT(seeprom, 6, 0, (void *)DS4510_CMD_SEEPROM, "", ""),
U_BOOT_CMD_MKENT(sram, 6, 0, (void *)DS4510_CMD_SRAM, "", ""),
#endif
};
int do_ds4510(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
static uint8_t chip = CONFIG_SYS_I2C_DS4510_ADDR;
cmd_tbl_t *c;
ulong ul_arg2 = 0;
ulong ul_arg3 = 0;
int tmp;
#ifdef CONFIG_CMD_DS4510_MEM
ulong addr;
ulong off;
ulong cnt;
int end;
int (*rw_func)(uint8_t, int, uint8_t *, int);
#endif
c = find_cmd_tbl(argv[1], cmd_ds4510, ARRAY_SIZE(cmd_ds4510));
/* All commands but "device" require 'maxargs' arguments */
if (!c || !((argc == (c->maxargs)) ||
(((int)c->cmd == DS4510_CMD_DEVICE) &&
(argc == (c->maxargs - 1))))) {
return cmd_usage(cmdtp);
}
/* arg2 used as chip addr and pin number */
if (argc > 2)
ul_arg2 = simple_strtoul(argv[2], NULL, 16);
/* arg3 used as output/pullup value */
if (argc > 3)
ul_arg3 = simple_strtoul(argv[3], NULL, 16);
switch ((int)c->cmd) {
case DS4510_CMD_DEVICE:
if (argc == 3)
chip = ul_arg2;
printf("Current device address: 0x%x\n", chip);
return 0;
case DS4510_CMD_NV:
return ds4510_see_write(chip, ul_arg2);
case DS4510_CMD_OUTPUT:
tmp = ds4510_gpio_read(chip);
if (tmp == -1)
return -1;
if (ul_arg3)
tmp |= (1 << ul_arg2);
else
tmp &= ~(1 << ul_arg2);
return ds4510_gpio_write(chip, tmp);
case DS4510_CMD_INPUT:
tmp = ds4510_gpio_read_val(chip);
if (tmp == -1)
return -1;
return (tmp & (1 << ul_arg2)) != 0;
case DS4510_CMD_PULLUP:
tmp = ds4510_pullup_read(chip);
if (tmp == -1)
return -1;
if (ul_arg3)
tmp |= (1 << ul_arg2);
else
tmp &= ~(1 << ul_arg2);
return ds4510_pullup_write(chip, tmp);
#ifdef CONFIG_CMD_DS4510_INFO
case DS4510_CMD_INFO:
return ds4510_info(chip);
#endif
#ifdef CONFIG_CMD_DS4510_RST
case DS4510_CMD_RSTDELAY:
return ds4510_rstdelay_write(chip, ul_arg2);
#endif
#ifdef CONFIG_CMD_DS4510_MEM
case DS4510_CMD_EEPROM:
end = DS4510_EEPROM + DS4510_EEPROM_SIZE;
off = DS4510_EEPROM;
break;
case DS4510_CMD_SEEPROM:
end = DS4510_SEEPROM + DS4510_SEEPROM_SIZE;
off = DS4510_SEEPROM;
break;
case DS4510_CMD_SRAM:
end = DS4510_SRAM + DS4510_SRAM_SIZE;
off = DS4510_SRAM;
break;
#endif
default:
/* We should never get here... */
return 1;
}
#ifdef CONFIG_CMD_DS4510_MEM
/* Only eeprom, seeprom, and sram commands should make it here */
if (strcmp(argv[2], "read") == 0)
rw_func = ds4510_mem_read;
else if (strcmp(argv[2], "write") == 0)
rw_func = ds4510_mem_write;
else
return cmd_usage(cmdtp);
addr = simple_strtoul(argv[3], NULL, 16);
off += simple_strtoul(argv[4], NULL, 16);
cnt = simple_strtoul(argv[5], NULL, 16);
if ((off + cnt) > end) {
printf("ERROR: invalid len\n");
return -1;
}
return rw_func(chip, off, (uint8_t *)addr, cnt);
#endif
}
U_BOOT_CMD(
ds4510, 6, 1, do_ds4510,
"ds4510 eeprom/seeprom/sram/gpio access",
"device [dev]\n"
" - show or set current device address\n"
#ifdef CONFIG_CMD_DS4510_INFO
"ds4510 info\n"
" - display ds4510 info\n"
#endif
"ds4510 output pin 0|1\n"
" - set pin low or high-Z\n"
"ds4510 input pin\n"
" - read value of pin\n"
"ds4510 pullup pin 0|1\n"
" - disable/enable pullup on specified pin\n"
"ds4510 nv 0|1\n"
" - make gpio and seeprom writes volatile/non-volatile"
#ifdef CONFIG_CMD_DS4510_RST
"\n"
"ds4510 rstdelay 0-3\n"
" - set reset output delay"
#endif
#ifdef CONFIG_CMD_DS4510_MEM
"\n"
"ds4510 eeprom read addr off cnt\n"
"ds4510 eeprom write addr off cnt\n"
" - read/write 'cnt' bytes at EEPROM offset 'off'\n"
"ds4510 seeprom read addr off cnt\n"
"ds4510 seeprom write addr off cnt\n"
" - read/write 'cnt' bytes at SRAM-shadowed EEPROM offset 'off'\n"
"ds4510 sram read addr off cnt\n"
"ds4510 sram write addr off cnt\n"
" - read/write 'cnt' bytes at SRAM offset 'off'"
#endif
);
#endif /* CONFIG_CMD_DS4510 */
|
1001-study-uboot
|
drivers/misc/ds4510.c
|
C
|
gpl3
| 10,037
|
/*
* Copyright 2010 Sergey Poselenov, Emcraft Systems, <sposelenov@emcraft.com>
* Copyright 2010 Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#include <common.h>
#include <led-display.h>
#include <asm/io.h>
#ifdef CONFIG_CMD_DISPLAY
#define CWORD_CLEAR 0x80
#define CLEAR_DELAY (110 * 2)
#define DISPLAY_SIZE 8
static int pos; /* Current display position */
/* Handle different display commands */
void display_set(int cmd)
{
if (cmd & DISPLAY_CLEAR) {
out_8((unsigned char *)CONFIG_SYS_DISP_CWORD, CWORD_CLEAR);
udelay(1000 * CLEAR_DELAY);
}
if (cmd & DISPLAY_HOME) {
pos = 0;
}
}
/*
* Display a character at the current display position.
* Characters beyond the display size are ignored.
*/
int display_putc(char c)
{
if (pos >= DISPLAY_SIZE)
return -1;
out_8((unsigned char *)CONFIG_SYS_DISP_CHR_RAM + pos++, c);
return c;
}
#endif
|
1001-study-uboot
|
drivers/misc/pdsp188x.c
|
C
|
gpl3
| 1,591
|
/*
* Copyright (C) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pmic.h>
#include <max8998_pmic.h>
int pmic_init(void)
{
struct pmic *p = get_pmic();
static const char name[] = "MAX8998_PMIC";
puts("Board PMIC init\n");
p->name = name;
p->interface = PMIC_I2C;
p->number_of_regs = PMIC_NUM_OF_REGS;
p->hw.i2c.addr = MAX8998_I2C_ADDR;
p->hw.i2c.tx_num = 1;
p->bus = I2C_PMIC;
return 0;
}
|
1001-study-uboot
|
drivers/misc/pmic_max8998.c
|
C
|
gpl3
| 1,256
|
/*
* Status LED driver based on GPIO access conventions of Linux
*
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <status_led.h>
#include <asm/gpio.h>
void __led_init(led_id_t mask, int state)
{
gpio_request(mask, "gpio_led");
gpio_direction_output(mask, state == STATUS_LED_ON);
}
void __led_set(led_id_t mask, int state)
{
gpio_set_value(mask, state == STATUS_LED_ON);
}
void __led_toggle(led_id_t mask)
{
gpio_set_value(mask, !gpio_get_value(mask));
}
|
1001-study-uboot
|
drivers/misc/gpio_led.c
|
C
|
gpl3
| 546
|
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix at windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* twl4030_led_init is from cpu/omap3/common.c, power_init_r
*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*
* Author :
* Sunil Kumar <sunilsaini05 at gmail.com>
* Shashi Ranjan <shashiranjanmca05 at gmail.com>
*
* Derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2 at ti.com>
* Syed Mohammed Khasim <khasim at ti.com>
*
*/
#include <twl4030.h>
void twl4030_led_init(unsigned char ledon_mask)
{
/* LEDs need to have corresponding PWMs enabled */
if (ledon_mask & TWL4030_LED_LEDEN_LEDAON)
ledon_mask |= TWL4030_LED_LEDEN_LEDAPWM;
if (ledon_mask & TWL4030_LED_LEDEN_LEDBON)
ledon_mask |= TWL4030_LED_LEDEN_LEDBPWM;
twl4030_i2c_write_u8(TWL4030_CHIP_LED, ledon_mask,
TWL4030_LED_LEDEN);
}
|
1001-study-uboot
|
drivers/misc/twl4030_led.c
|
C
|
gpl3
| 1,571
|
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <status_led.h>
/*
* The purpose of this code is to signal the operational status of a
* target which usually boots over the network; while running in
* U-Boot, a status LED is blinking. As soon as a valid BOOTP reply
* message has been received, the LED is turned off. The Linux
* kernel, once it is running, will start blinking the LED again,
* with another frequency.
*/
/* ------------------------------------------------------------------------- */
typedef struct {
led_id_t mask;
int state;
int period;
int cnt;
} led_dev_t;
led_dev_t led_dev[] = {
{ STATUS_LED_BIT,
STATUS_LED_STATE,
STATUS_LED_PERIOD,
0,
},
#if defined(STATUS_LED_BIT1)
{ STATUS_LED_BIT1,
STATUS_LED_STATE1,
STATUS_LED_PERIOD1,
0,
},
#endif
#if defined(STATUS_LED_BIT2)
{ STATUS_LED_BIT2,
STATUS_LED_STATE2,
STATUS_LED_PERIOD2,
0,
},
#endif
#if defined(STATUS_LED_BIT3)
{ STATUS_LED_BIT3,
STATUS_LED_STATE3,
STATUS_LED_PERIOD3,
0,
},
#endif
};
#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t))
static int status_led_init_done = 0;
static void status_led_init (void)
{
led_dev_t *ld;
int i;
for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++)
__led_init (ld->mask, ld->state);
status_led_init_done = 1;
}
void status_led_tick (ulong timestamp)
{
led_dev_t *ld;
int i;
if (!status_led_init_done)
status_led_init ();
for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) {
if (ld->state != STATUS_LED_BLINKING)
continue;
if (++ld->cnt >= ld->period) {
__led_toggle (ld->mask);
ld->cnt -= ld->period;
}
}
}
void status_led_set (int led, int state)
{
led_dev_t *ld;
if (led < 0 || led >= MAX_LED_DEV)
return;
if (!status_led_init_done)
status_led_init ();
ld = &led_dev[led];
ld->state = state;
if (state == STATUS_LED_BLINKING) {
ld->cnt = 0; /* always start with full period */
state = STATUS_LED_ON; /* always start with LED _ON_ */
}
__led_set (ld->mask, state);
}
|
1001-study-uboot
|
drivers/misc/status_led.c
|
C
|
gpl3
| 2,890
|
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Based on sc520cdp.c from rolo 1.6:
*----------------------------------------------------------------------
* (C) Copyright 2000
* Sysgo Real-Time Solutions GmbH
* Klein-Winternheim, Germany
*----------------------------------------------------------------------
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <ali512x.h>
/* ALI M5123 Logical device numbers:
* 0 FDC
* 1 unused?
* 2 unused?
* 3 lpt
* 4 UART1
* 5 UART2
* 6 RTC
* 7 mouse/kbd
* 8 CIO
*/
/*
************************************************************
* Some access primitives for the ALi chip: *
************************************************************
*/
static void ali_write(u8 index, u8 value)
{
/* write an arbirary register */
outb(index, ALI_INDEX);
outb(value, ALI_DATA);
}
#if 0
static int ali_read(u8 index)
{
outb(index, ALI_INDEX);
return inb(ALI_DATA);
}
#endif
#define ALI_OPEN() \
outb(0x51, ALI_INDEX); \
outb(0x23, ALI_INDEX)
#define ALI_CLOSE() \
outb(0xbb, ALI_INDEX)
/* Select a logical device */
#define ALI_SELDEV(dev) \
ali_write(0x07, dev)
void ali512x_init(void)
{
ALI_OPEN();
ali_write(0x02, 0x01); /* soft reset */
ali_write(0x03, 0x03); /* disable access to CIOs */
ali_write(0x22, 0x00); /* disable direct powerdown */
ali_write(0x23, 0x00); /* disable auto powerdown */
ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */
ALI_CLOSE();
}
void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel)
{
ALI_OPEN();
ALI_SELDEV(0);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x60, io >> 8);
ali_write(0x61, io & 0xff);
ali_write(0x70, irq);
ali_write(0x74, dma_channel);
/* AT mode, no drive swap */
ali_write(0xf0, 0x08);
ali_write(0xf1, 0x00);
ali_write(0xf2, 0xff);
ali_write(0xf4, 0x00);
}
ALI_CLOSE();
}
void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel)
{
ALI_OPEN();
ALI_SELDEV(3);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x60, io >> 8);
ali_write(0x61, io & 0xff);
ali_write(0x70, irq);
ali_write(0x74, dma_channel);
/* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */
ali_write(0xf0, 0xbc);
/* 12 MHz, Burst DMA in ECP */
ali_write(0xf1, 0x05);
}
ALI_CLOSE();
}
void ali512x_set_uart(int enabled, int index, u16 io, u8 irq)
{
ALI_OPEN();
ALI_SELDEV(index?5:4);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x60, io >> 8);
ali_write(0x61, io & 0xff);
ali_write(0x70, irq);
ali_write(0xf0, 0x00);
ali_write(0xf1, 0x00);
/* huh? write 0xf2 twice - a typo in rolo
* or some secret ali errata? Who knows?
*/
if (index) {
ali_write(0xf2, 0x00);
}
ali_write(0xf2, 0x0c);
}
ALI_CLOSE();
}
void ali512x_set_uart2_irda(int enabled)
{
ALI_OPEN();
ALI_SELDEV(5);
ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */
ALI_CLOSE();
}
void ali512x_set_rtc(int enabled, u16 io, u8 irq)
{
ALI_OPEN();
ALI_SELDEV(6);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x60, io >> 8);
ali_write(0x61, io & 0xff);
ali_write(0x70, irq);
ali_write(0xf0, 0x00);
}
ALI_CLOSE();
}
void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq)
{
ALI_OPEN();
ALI_SELDEV(7);
ali_write(0x30, enabled?1:0);
if (enabled) {
ali_write(0x70, kbc_irq);
ali_write(0x72, mouse_irq);
ali_write(0xf0, 0x00);
}
ALI_CLOSE();
}
/* Common I/O
*
* (This descripotsion is base on several incompete sources
* since I have not been able to obtain any datasheet for the device
* there may be some mis-understandings burried in here.
* -- Daniel daniel@omicron.se)
*
* There are 22 CIO pins numbered
* 10-17
* 20-25
* 30-37
*
* 20-24 are dedicated CIO pins, the other 17 are muliplexed with
* other functions.
*
* Secondary
* CIO Pin Function Decription
* =======================================================
* CIO10 IRQIN1 Interrupt input 1?
* CIO11 IRQIN2 Interrupt input 2?
* CIO12 IRRX IrDa Receive
* CIO13 IRTX IrDa Transmit
* CIO14 P21 KBC P21 fucntion
* CIO15 P20 KBC P21 fucntion
* CIO16 I2C_CLK I2C Clock
* CIO17 I2C_DAT I2C Data
*
* CIO20 -
* CIO21 -
* CIO22 -
* CIO23 -
* CIO24 -
* CIO25 LOCK Keylock
*
* CIO30 KBC_CLK Keybaord Clock
* CIO31 CS0J General Chip Select decoder CS0J
* CIO32 CS1J General Chip Select decoder CS1J
* CIO33 ALT_KCLK Alternative Keyboard Clock
* CIO34 ALT_KDAT Alternative Keyboard Data
* CIO35 ALT_MCLK Alternative Mouse Clock
* CIO36 ALT_MDAT Alternative Mouse Data
* CIO37 ALT_KBC Alternative KBC select
*
* The CIO use an indirect address scheme.
*
* Reigster 3 in the SIO is used to select the index and data
* port addresses where the CIO I/O registers show up.
* The function selection registers are accessible under
* function SIO 8.
*
* SIO reigster 3 (CIO Address Selection) bit definitions:
* bit 7 CIO index and data registers enabled
* bit 1-0 CIO indirect registers port address select
* 0 index = 0xE0 data = 0xE1
* 1 index = 0xE2 data = 0xE3
* 2 index = 0xE4 data = 0xE5
* 3 index = 0xEA data = 0xEB
*
* There are three CIO I/O register accessed via CIO index port and CIO data port
* 0x01 CIO 10-17 data
* 0x02 CIO 20-25 data (bits 7-6 unused)
* 0x03 CIO 30-37 data
*
*
* The pin function is accessed through normal
* SIO registers, each register have the same format:
*
* Bit Function Value
* 0 Input/output 1=input
* 1 Polarity of signal 1=inverted
* 2 Unused ??
* 3 Function (normal or special) 1=special
* 7-4 Unused
*
* SIO REG
* 0xe0 CIO 10 Config
* 0xe1 CIO 11 Config
* 0xe2 CIO 12 Config
* 0xe3 CIO 13 Config
* 0xe4 CIO 14 Config
* 0xe5 CIO 15 Config
* 0xe6 CIO 16 Config
* 0xe7 CIO 16 Config
*
* 0xe8 CIO 20 Config
* 0xe9 CIO 21 Config
* 0xea CIO 22 Config
* 0xeb CIO 23 Config
* 0xec CIO 24 Config
* 0xed CIO 25 Config
*
* 0xf5 CIO 30 Config
* 0xf6 CIO 31 Config
* 0xf7 CIO 32 Config
* 0xf8 CIO 33 Config
* 0xf9 CIO 34 Config
* 0xfa CIO 35 Config
* 0xfb CIO 36 Config
* 0xfc CIO 37 Config
*
*/
#define ALI_CIO_PORT_SEL 0x83
#define ALI_CIO_INDEX 0xea
#define ALI_CIO_DATA 0xeb
void ali512x_set_cio(int enabled)
{
int i;
ALI_OPEN();
if (enabled) {
ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */
} else {
ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80);
}
ALI_SELDEV(8);
ali_write(0x30, enabled?1:0);
/* set all pins to input to start with */
for (i=0xe0;i<0xee;i++) {
ali_write(i, 1);
}
for (i=0xf5;i<0xfe;i++) {
ali_write(i, 1);
}
ALI_CLOSE();
}
void ali512x_cio_function(int pin, int special, int inv, int input)
{
u8 data;
u8 addr;
/* valid pins are 10-17, 20-25 and 30-37 */
if (pin >= 10 && pin <= 17) {
addr = 0xe0+(pin&7);
} else if (pin >= 20 && pin <= 25) {
addr = 0xe8+(pin&7);
} else if (pin >= 30 && pin <= 37) {
addr = 0xf5+(pin&7);
} else {
return;
}
ALI_OPEN();
ALI_SELDEV(8);
data=0xf4;
if (special) {
data |= 0x08;
} else {
if (inv) {
data |= 0x02;
}
if (input) {
data |= 0x01;
}
}
ali_write(addr, data);
ALI_CLOSE();
}
void ali512x_cio_out(int pin, int value)
{
u8 reg;
u8 data;
u8 bit;
reg = pin/10;
bit = 1 << (pin%10);
outb(reg, ALI_CIO_INDEX); /* select I/O register */
data = inb(ALI_CIO_DATA);
if (value) {
data |= bit;
} else {
data &= ~bit;
}
outb(data, ALI_CIO_DATA);
}
int ali512x_cio_in(int pin)
{
u8 reg;
u8 data;
u8 bit;
/* valid pins are 10-17, 20-25 and 30-37 */
reg = pin/10;
bit = 1 << (pin%10);
outb(reg, ALI_CIO_INDEX); /* select I/O register */
data = inb(ALI_CIO_DATA);
return data & bit;
}
|
1001-study-uboot
|
drivers/misc/ali512x.c
|
C
|
gpl3
| 8,892
|
/*
* (C) Copyright 2010 Stefano Babic <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/errno.h>
#include <linux/types.h>
#include <i2c.h>
#include <mc9sdz60.h>
#ifndef CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR
#error "You have to configure I2C address for MC9SDZ60"
#endif
u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg)
{
u8 val;
if (i2c_read(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1)) {
puts("Error reading MC9SDZ60 register\n");
return -1;
}
return val;
}
void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val)
{
i2c_write(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1);
}
|
1001-study-uboot
|
drivers/misc/mc9sdz60.c
|
C
|
gpl3
| 1,414
|
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libmisc.o
COBJS-$(CONFIG_ALI152X) += ali512x.o
COBJS-$(CONFIG_DS4510) += ds4510.o
COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
COBJS-$(CONFIG_NS87308) += ns87308.o
COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
COBJS-$(CONFIG_STATUS_LED) += status_led.o
COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
COBJS-$(CONFIG_PMIC) += pmic_core.o
COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o
COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o
COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o
COBJS-$(CONFIG_PMIC_MAX8998) += pmic_max8998.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/misc/Makefile
|
Makefile
|
gpl3
| 1,867
|
/*
* Copyright 2008-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
#ifdef CONFIG_FSL_CORENET
#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
#define LAWBAR_SHIFT 0
#else
#define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
#define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
#define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
#define LAWBAR_SHIFT 12
#endif
static inline phys_addr_t get_law_base_addr(int idx)
{
#ifdef CONFIG_FSL_CORENET
return (phys_addr_t)
((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
in_be32(LAWBARL_ADDR(idx));
#else
return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
#endif
}
static inline void set_law_base_addr(int idx, phys_addr_t addr)
{
#ifdef CONFIG_FSL_CORENET
out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
#else
out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
#endif
}
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
gd->used_laws |= (1 << idx);
out_be32(LAWAR_ADDR(idx), 0);
set_law_base_addr(idx, addr);
out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
/* Read back so that we sync the writes */
in_be32(LAWAR_ADDR(idx));
}
void disable_law(u8 idx)
{
gd->used_laws &= ~(1 << idx);
out_be32(LAWAR_ADDR(idx), 0);
set_law_base_addr(idx, 0);
/* Read back so that we sync the writes */
in_be32(LAWAR_ADDR(idx));
return;
}
#ifndef CONFIG_NAND_SPL
static int get_law_entry(u8 i, struct law_entry *e)
{
u32 lawar;
lawar = in_be32(LAWAR_ADDR(i));
if (!(lawar & LAW_EN))
return 0;
e->addr = get_law_base_addr(i);
e->size = lawar & 0x3f;
e->trgt_id = (lawar >> 20) & 0xff;
return 1;
}
#endif
int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx = ffz(gd->used_laws);
if (idx >= FSL_HW_NUM_LAWS)
return -1;
set_law(idx, addr, sz, id);
return idx;
}
#ifndef CONFIG_NAND_SPL
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx;
/* we have no LAWs free */
if (gd->used_laws == -1)
return -1;
/* grab the last free law */
idx = __ilog2(~(gd->used_laws));
if (idx >= FSL_HW_NUM_LAWS)
return -1;
set_law(idx, addr, sz, id);
return idx;
}
struct law_entry find_law(phys_addr_t addr)
{
struct law_entry entry;
int i;
entry.index = -1;
entry.addr = 0;
entry.size = 0;
entry.trgt_id = 0;
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
u64 upper;
if (!get_law_entry(i, &entry))
continue;
upper = entry.addr + (2ull << entry.size);
if ((addr >= entry.addr) && (addr < upper)) {
entry.index = i;
break;
}
}
return entry;
}
void print_laws(void)
{
int i;
u32 lawar;
printf("\nLocal Access Window Configuration\n");
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
lawar = in_be32(LAWAR_ADDR(i));
#ifdef CONFIG_FSL_CORENET
printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
i, in_be32(LAWBARH_ADDR(i)),
i, in_be32(LAWBARL_ADDR(i)));
#else
printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
#endif
printf(" LAWAR%02d: 0x%08x\n", i, lawar);
printf("\t(EN: %d TGT: 0x%02x SIZE: ",
(lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
print_size(lawar_size(lawar), ")\n");
}
return;
}
/* use up to 2 LAWs for DDR, used the last available LAWs */
int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
{
u64 start_align, law_sz;
int law_sz_enc;
if (start == 0)
start_align = 1ull << (LAW_SIZE_32G + 1);
else
start_align = 1ull << (ffs64(start) - 1);
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
if (set_last_law(start, law_sz_enc, id) < 0)
return -1;
/* recalculate size based on what was actually covered by the law */
law_sz = 1ull << __ilog2_u64(law_sz);
/* do we still have anything to map */
sz = sz - law_sz;
if (sz) {
start += law_sz;
start_align = 1ull << (ffs64(start) - 1);
law_sz = min(start_align, sz);
law_sz_enc = __ilog2_u64(law_sz) - 1;
if (set_last_law(start, law_sz_enc, id) < 0)
return -1;
} else {
return 0;
}
/* do we still have anything to map */
sz = sz - law_sz;
if (sz)
return 1;
return 0;
}
#endif
void init_laws(void)
{
int i;
#if FSL_HW_NUM_LAWS < 32
gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
#elif FSL_HW_NUM_LAWS == 32
gd->used_laws = 0;
#else
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
/*
* Any LAWs that were set up before we booted assume they are meant to
* be around and mark them used.
*/
for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
u32 lawar = in_be32(LAWAR_ADDR(i));
if (lawar & LAW_EN)
gd->used_laws |= (1 << i);
}
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* in NAND boot we've already parsed the law_table and setup those LAWs
* so don't do it again.
*/
return;
#endif
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index == -1)
set_next_law(law_table[i].addr, law_table[i].size,
law_table[i].trgt_id);
else
set_law(law_table[i].index, law_table[i].addr,
law_table[i].size, law_table[i].trgt_id);
}
return ;
}
|
1001-study-uboot
|
drivers/misc/fsl_law.c
|
C
|
gpl3
| 6,292
|
/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <ns87308.h>
void initialise_ns87308 (void)
{
#ifdef CONFIG_SYS_NS87308_PS2MOD
unsigned char data;
/*
* Switch floppy drive to PS/2 mode.
*/
read_pnp_config(SUPOERIO_CONF1, &data);
data &= 0xFB;
write_pnp_config(SUPOERIO_CONF1, data);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_KBC1)
PNP_SET_DEVICE_BASE(LDEV_KBC1, CONFIG_SYS_NS87308_KBC1_BASE);
write_pnp_config(LUN_CONFIG_REG, 0);
write_pnp_config(CBASE_HIGH, 0x00);
write_pnp_config(CBASE_LOW, 0x64);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_MOUSE)
PNP_ACTIVATE_DEVICE(LDEV_MOUSE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_RTC_APC)
PNP_SET_DEVICE_BASE(LDEV_RTC_APC, CONFIG_SYS_NS87308_RTC_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_FDC)
PNP_SET_DEVICE_BASE(LDEV_FDC, CONFIG_SYS_NS87308_FDC_BASE);
write_pnp_config(LUN_CONFIG_REG, 0x40);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_RARP)
PNP_SET_DEVICE_BASE(LDEV_PARP, CONFIG_SYS_NS87308_LPT_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_UART1)
PNP_SET_DEVICE_BASE(LDEV_UART1, CONFIG_SYS_NS87308_UART1_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_UART2)
PNP_SET_DEVICE_BASE(LDEV_UART2, CONFIG_SYS_NS87308_UART2_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_GPIO)
PNP_SET_DEVICE_BASE(LDEV_GPIO, CONFIG_SYS_NS87308_GPIO_BASE);
#endif
#if (CONFIG_SYS_NS87308_DEVS & CONFIG_SYS_NS87308_POWRMAN)
#ifndef CONFIG_SYS_NS87308_PWMAN_BASE
PNP_ACTIVATE_DEVICE(LDEV_POWRMAN);
#else
PNP_SET_DEVICE_BASE(LDEV_POWRMAN, CONFIG_SYS_NS87308_PWMAN_BASE);
/*
* Enable all units
*/
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_FER1, 0x7d);
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_FER2, 0x87);
#ifdef CONFIG_SYS_NS87308_PMC1
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC1, CONFIG_SYS_NS87308_PMC1);
#endif
#ifdef CONFIG_SYS_NS87308_PMC2
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC2, CONFIG_SYS_NS87308_PMC2);
#endif
#ifdef CONFIG_SYS_NS87308_PMC3
write_pm_reg(CONFIG_SYS_NS87308_PWMAN_BASE, PWM_PMC3, CONFIG_SYS_NS87308_PMC3);
#endif
#endif
#endif
#ifdef CONFIG_SYS_NS87308_CS0_BASE
PNP_PGCS_CSLINE_BASE(0, CONFIG_SYS_NS87308_CS0_BASE);
PNP_PGCS_CSLINE_CONF(0, CONFIG_SYS_NS87308_CS0_CONF);
#endif
#ifdef CONFIG_SYS_NS87308_CS1_BASE
PNP_PGCS_CSLINE_BASE(1, CONFIG_SYS_NS87308_CS1_BASE);
PNP_PGCS_CSLINE_CONF(1, CONFIG_SYS_NS87308_CS1_CONF);
#endif
#ifdef CONFIG_SYS_NS87308_CS2_BASE
PNP_PGCS_CSLINE_BASE(2, CONFIG_SYS_NS87308_CS2_BASE);
PNP_PGCS_CSLINE_CONF(2, CONFIG_SYS_NS87308_CS2_CONF);
#endif
}
|
1001-study-uboot
|
drivers/misc/ns87308.c
|
C
|
gpl3
| 3,506
|
/*
* Copyright (C) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/types.h>
#include <pmic.h>
#include <i2c.h>
int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
{
unsigned char buf[4] = { 0 };
if (check_reg(reg))
return -1;
switch (pmic_i2c_tx_num) {
case 3:
buf[0] = (val >> 16) & 0xff;
buf[1] = (val >> 8) & 0xff;
buf[2] = val & 0xff;
break;
case 1:
buf[0] = val & 0xff;
break;
}
if (i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num))
return -1;
return 0;
}
int pmic_reg_read(struct pmic *p, u32 reg, u32 *val)
{
unsigned char buf[4] = { 0 };
u32 ret_val = 0;
if (check_reg(reg))
return -1;
if (i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num))
return -1;
switch (pmic_i2c_tx_num) {
case 3:
ret_val = buf[0] << 16 | buf[1] << 8 | buf[2];
break;
case 1:
ret_val = buf[0];
break;
}
memcpy(val, &ret_val, sizeof(ret_val));
return 0;
}
int pmic_probe(struct pmic *p)
{
I2C_SET_BUS(p->bus);
debug("PMIC:%s probed!\n", p->name);
if (i2c_probe(pmic_i2c_addr)) {
printf("Can't find PMIC:%s\n", p->name);
return -1;
}
return 0;
}
|
1001-study-uboot
|
drivers/misc/pmic_i2c.c
|
C
|
gpl3
| 2,105
|
/*
* Copyright (C) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <linux/types.h>
#include <pmic.h>
static struct pmic pmic;
int check_reg(u32 reg)
{
if (reg >= pmic.number_of_regs) {
printf("<reg num> = %d is invalid. Should be less than %d\n",
reg, pmic.number_of_regs);
return -1;
}
return 0;
}
int pmic_set_output(struct pmic *p, u32 reg, int out, int on)
{
u32 val;
if (pmic_reg_read(p, reg, &val))
return -1;
if (on)
val |= out;
else
val &= ~out;
if (pmic_reg_write(p, reg, val))
return -1;
return 0;
}
static void pmic_show_info(struct pmic *p)
{
printf("PMIC: %s\n", p->name);
}
static void pmic_dump(struct pmic *p)
{
int i, ret;
u32 val;
pmic_show_info(p);
for (i = 0; i < p->number_of_regs; i++) {
ret = pmic_reg_read(p, i, &val);
if (ret)
puts("PMIC: Registers dump failed\n");
if (!(i % 8))
printf("\n0x%02x: ", i);
printf("%08x ", val);
}
puts("\n");
}
struct pmic *get_pmic(void)
{
return &pmic;
}
int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 ret, reg, val;
char *cmd;
struct pmic *p = &pmic;
/* at least two arguments please */
if (argc < 2)
return cmd_usage(cmdtp);
cmd = argv[1];
if (strcmp(cmd, "dump") == 0) {
pmic_dump(p);
return 0;
}
if (strcmp(cmd, "read") == 0) {
if (argc < 3)
return cmd_usage(cmdtp);
reg = simple_strtoul(argv[2], NULL, 16);
ret = pmic_reg_read(p, reg, &val);
if (ret)
puts("PMIC: Register read failed\n");
printf("\n0x%02x: 0x%08x\n", reg, val);
return 0;
}
if (strcmp(cmd, "write") == 0) {
if (argc < 4)
return cmd_usage(cmdtp);
reg = simple_strtoul(argv[2], NULL, 16);
val = simple_strtoul(argv[3], NULL, 16);
pmic_reg_write(p, reg, val);
return 0;
}
/* No subcommand found */
return 1;
}
U_BOOT_CMD(
pmic, CONFIG_SYS_MAXARGS, 1, do_pmic,
"PMIC",
"dump - dump PMIC registers\n"
"pmic read <reg> - read register\n"
"pmic write <reg> <value> - write register"
);
|
1001-study-uboot
|
drivers/misc/pmic_core.c
|
C
|
gpl3
| 2,972
|