code
stringlengths 1
2.01M
| repo_name
stringlengths 3
62
| path
stringlengths 1
267
| language
stringclasses 231
values | license
stringclasses 13
values | size
int64 1
2.01M
|
|---|---|---|---|---|---|
/*
* Copyright (C) 2008 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
* port from the libata of linux kernel
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <libata.h>
u64 ata_id_n_sectors(u16 *id)
{
if (ata_id_has_lba(id)) {
if (ata_id_has_lba48(id))
return ata_id_u64(id, ATA_ID_LBA48_SECTORS);
else
return ata_id_u32(id, ATA_ID_LBA_SECTORS);
} else {
return 0;
}
}
u32 ata_dev_classify(u32 sig)
{
u8 lbam, lbah;
lbam = (sig >> 16) & 0xff;
lbah = (sig >> 24) & 0xff;
if (((lbam == 0) && (lbah == 0)) ||
((lbam == 0x3c) && (lbah == 0xc3)))
return ATA_DEV_ATA;
if ((lbam == 0x14) && (lbah == 0xeb))
return ATA_DEV_ATAPI;
if ((lbam == 0x69) && (lbah == 0x96))
return ATA_DEV_PMP;
return ATA_DEV_UNKNOWN;
}
static void ata_id_string(const u16 *id, unsigned char *s,
unsigned int ofs, unsigned int len)
{
unsigned int c;
while (len > 0) {
c = id[ofs] >> 8;
*s = c;
s++;
c = id[ofs] & 0xff;
*s = c;
s++;
ofs++;
len -= 2;
}
}
void ata_id_c_string(const u16 *id, unsigned char *s,
unsigned int ofs, unsigned int len)
{
unsigned char *p;
ata_id_string(id, s, ofs, len - 1);
p = s + strnlen((char *)s, len - 1);
while (p > s && p[-1] == ' ')
p--;
*p = '\0';
}
void ata_dump_id(u16 *id)
{
unsigned char serial[ATA_ID_SERNO_LEN + 1];
unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
unsigned char product[ATA_ID_PROD_LEN + 1];
u64 n_sectors;
/* Serial number */
ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
printf("S/N: %s\n\r", serial);
/* Firmware version */
ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
printf("Firmware version: %s\n\r", firmware);
/* Product model */
ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
printf("Product model number: %s\n\r", product);
/* Total sectors of device */
n_sectors = ata_id_n_sectors(id);
printf("Capablity: %lld sectors\n\r", n_sectors);
printf ("id[49]: capabilities = 0x%04x\n"
"id[53]: field valid = 0x%04x\n"
"id[63]: mwdma = 0x%04x\n"
"id[64]: pio = 0x%04x\n"
"id[75]: queue depth = 0x%04x\n",
id[49],
id[53],
id[63],
id[64],
id[75]);
printf ("id[76]: sata capablity = 0x%04x\n"
"id[78]: sata features supported = 0x%04x\n"
"id[79]: sata features enable = 0x%04x\n",
id[76],
id[78],
id[79]);
printf ("id[80]: major version = 0x%04x\n"
"id[81]: minor version = 0x%04x\n"
"id[82]: command set supported 1 = 0x%04x\n"
"id[83]: command set supported 2 = 0x%04x\n"
"id[84]: command set extension = 0x%04x\n",
id[80],
id[81],
id[82],
id[83],
id[84]);
printf ("id[85]: command set enable 1 = 0x%04x\n"
"id[86]: command set enable 2 = 0x%04x\n"
"id[87]: command set default = 0x%04x\n"
"id[88]: udma = 0x%04x\n"
"id[93]: hardware reset result = 0x%04x\n",
id[85],
id[86],
id[87],
id[88],
id[93]);
}
void ata_swap_buf_le16(u16 *buf, unsigned int buf_words)
{
unsigned int i;
for (i = 0; i < buf_words; i++)
buf[i] = le16_to_cpu(buf[i]);
}
|
1001-study-uboot
|
drivers/block/libata.c
|
C
|
gpl3
| 3,699
|
/*
* sata_dwc.h
*
* Synopsys DesignWare Cores (DWC) SATA host driver
*
* Author: Mark Miesfeld <mmiesfeld@amcc.com>
*
* Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
* Copyright 2008 DENX Software Engineering
*
* Based on versions provided by AMCC and Synopsys which are:
* Copyright 2006 Applied Micro Circuits Corporation
* COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
*
* This program is free software; you can redistribute
* it and/or modify it under the terms of the GNU
* General Public License as published by the
* Free Software Foundation; either version 2 of the License,
* or (at your option) any later version.
*
*/
/*
* SATA support based on the chip canyonlands.
*
* 04-17-2009
* The local version of this driver for the canyonlands board
* does not use interrupts but polls the chip instead.
*/
#ifndef _SATA_DWC_H_
#define _SATA_DWC_H_
#define __U_BOOT__
#define HZ 100
#define READ 0
#define WRITE 1
enum {
ATA_READID_POSTRESET = (1 << 0),
ATA_DNXFER_PIO = 0,
ATA_DNXFER_DMA = 1,
ATA_DNXFER_40C = 2,
ATA_DNXFER_FORCE_PIO = 3,
ATA_DNXFER_FORCE_PIO0 = 4,
ATA_DNXFER_QUIET = (1 << 31),
};
enum hsm_task_states {
HSM_ST_IDLE,
HSM_ST_FIRST,
HSM_ST,
HSM_ST_LAST,
HSM_ST_ERR,
};
#define ATA_SHORT_PAUSE ((HZ >> 6) + 1)
struct ata_queued_cmd {
struct ata_port *ap;
struct ata_device *dev;
struct ata_taskfile tf;
u8 cdb[ATAPI_CDB_LEN];
unsigned long flags;
unsigned int tag;
unsigned int n_elem;
int dma_dir;
unsigned int sect_size;
unsigned int nbytes;
unsigned int extrabytes;
unsigned int curbytes;
unsigned int err_mask;
struct ata_taskfile result_tf;
void *private_data;
#ifndef __U_BOOT__
void *lldd_task;
#endif
unsigned char *pdata;
};
typedef void (*ata_qc_cb_t) (struct ata_queued_cmd *qc);
#define ATA_TAG_POISON 0xfafbfcfdU
enum {
LIBATA_MAX_PRD = ATA_MAX_PRD / 2,
LIBATA_DUMB_MAX_PRD = ATA_MAX_PRD / 4,
ATA_MAX_PORTS = 8,
ATA_DEF_QUEUE = 1,
ATA_MAX_QUEUE = 32,
ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1,
ATA_MAX_BUS = 2,
ATA_DEF_BUSY_WAIT = 10000,
ATAPI_MAX_DRAIN = 16 << 10,
ATA_SHT_EMULATED = 1,
ATA_SHT_CMD_PER_LUN = 1,
ATA_SHT_THIS_ID = -1,
ATA_SHT_USE_CLUSTERING = 1,
ATA_DFLAG_LBA = (1 << 0),
ATA_DFLAG_LBA48 = (1 << 1),
ATA_DFLAG_CDB_INTR = (1 << 2),
ATA_DFLAG_NCQ = (1 << 3),
ATA_DFLAG_FLUSH_EXT = (1 << 4),
ATA_DFLAG_ACPI_PENDING = (1 << 5),
ATA_DFLAG_ACPI_FAILED = (1 << 6),
ATA_DFLAG_AN = (1 << 7),
ATA_DFLAG_HIPM = (1 << 8),
ATA_DFLAG_DIPM = (1 << 9),
ATA_DFLAG_DMADIR = (1 << 10),
ATA_DFLAG_CFG_MASK = (1 << 12) - 1,
ATA_DFLAG_PIO = (1 << 12),
ATA_DFLAG_NCQ_OFF = (1 << 13),
ATA_DFLAG_SPUNDOWN = (1 << 14),
ATA_DFLAG_SLEEPING = (1 << 15),
ATA_DFLAG_DUBIOUS_XFER = (1 << 16),
ATA_DFLAG_INIT_MASK = (1 << 24) - 1,
ATA_DFLAG_DETACH = (1 << 24),
ATA_DFLAG_DETACHED = (1 << 25),
ATA_LFLAG_HRST_TO_RESUME = (1 << 0),
ATA_LFLAG_SKIP_D2H_BSY = (1 << 1),
ATA_LFLAG_NO_SRST = (1 << 2),
ATA_LFLAG_ASSUME_ATA = (1 << 3),
ATA_LFLAG_ASSUME_SEMB = (1 << 4),
ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB,
ATA_LFLAG_NO_RETRY = (1 << 5),
ATA_LFLAG_DISABLED = (1 << 6),
ATA_FLAG_SLAVE_POSS = (1 << 0),
ATA_FLAG_SATA = (1 << 1),
ATA_FLAG_NO_LEGACY = (1 << 2),
ATA_FLAG_MMIO = (1 << 3),
ATA_FLAG_SRST = (1 << 4),
ATA_FLAG_SATA_RESET = (1 << 5),
ATA_FLAG_NO_ATAPI = (1 << 6),
ATA_FLAG_PIO_DMA = (1 << 7),
ATA_FLAG_PIO_LBA48 = (1 << 8),
ATA_FLAG_PIO_POLLING = (1 << 9),
ATA_FLAG_NCQ = (1 << 10),
ATA_FLAG_DEBUGMSG = (1 << 13),
ATA_FLAG_IGN_SIMPLEX = (1 << 15),
ATA_FLAG_NO_IORDY = (1 << 16),
ATA_FLAG_ACPI_SATA = (1 << 17),
ATA_FLAG_AN = (1 << 18),
ATA_FLAG_PMP = (1 << 19),
ATA_FLAG_IPM = (1 << 20),
ATA_FLAG_DISABLED = (1 << 23),
ATA_PFLAG_EH_PENDING = (1 << 0),
ATA_PFLAG_EH_IN_PROGRESS = (1 << 1),
ATA_PFLAG_FROZEN = (1 << 2),
ATA_PFLAG_RECOVERED = (1 << 3),
ATA_PFLAG_LOADING = (1 << 4),
ATA_PFLAG_UNLOADING = (1 << 5),
ATA_PFLAG_SCSI_HOTPLUG = (1 << 6),
ATA_PFLAG_INITIALIZING = (1 << 7),
ATA_PFLAG_RESETTING = (1 << 8),
ATA_PFLAG_SUSPENDED = (1 << 17),
ATA_PFLAG_PM_PENDING = (1 << 18),
ATA_QCFLAG_ACTIVE = (1 << 0),
ATA_QCFLAG_DMAMAP = (1 << 1),
ATA_QCFLAG_IO = (1 << 3),
ATA_QCFLAG_RESULT_TF = (1 << 4),
ATA_QCFLAG_CLEAR_EXCL = (1 << 5),
ATA_QCFLAG_QUIET = (1 << 6),
ATA_QCFLAG_FAILED = (1 << 16),
ATA_QCFLAG_SENSE_VALID = (1 << 17),
ATA_QCFLAG_EH_SCHEDULED = (1 << 18),
ATA_HOST_SIMPLEX = (1 << 0),
ATA_HOST_STARTED = (1 << 1),
ATA_TMOUT_BOOT = 30 * 100,
ATA_TMOUT_BOOT_QUICK = 7 * 100,
ATA_TMOUT_INTERNAL = 30 * 100,
ATA_TMOUT_INTERNAL_QUICK = 5 * 100,
/* FIXME: GoVault needs 2s but we can't afford that without
* parallel probing. 800ms is enough for iVDR disk
* HHD424020F7SV00. Increase to 2secs when parallel probing
* is in place.
*/
ATA_TMOUT_FF_WAIT = 4 * 100 / 5,
BUS_UNKNOWN = 0,
BUS_DMA = 1,
BUS_IDLE = 2,
BUS_NOINTR = 3,
BUS_NODATA = 4,
BUS_TIMER = 5,
BUS_PIO = 6,
BUS_EDD = 7,
BUS_IDENTIFY = 8,
BUS_PACKET = 9,
PORT_UNKNOWN = 0,
PORT_ENABLED = 1,
PORT_DISABLED = 2,
/* encoding various smaller bitmaps into a single
* unsigned long bitmap
*/
ATA_NR_PIO_MODES = 7,
ATA_NR_MWDMA_MODES = 5,
ATA_NR_UDMA_MODES = 8,
ATA_SHIFT_PIO = 0,
ATA_SHIFT_MWDMA = ATA_SHIFT_PIO + ATA_NR_PIO_MODES,
ATA_SHIFT_UDMA = ATA_SHIFT_MWDMA + ATA_NR_MWDMA_MODES,
ATA_DMA_PAD_SZ = 4,
ATA_ERING_SIZE = 32,
ATA_DEFER_LINK = 1,
ATA_DEFER_PORT = 2,
ATA_EH_DESC_LEN = 80,
ATA_EH_REVALIDATE = (1 << 0),
ATA_EH_SOFTRESET = (1 << 1),
ATA_EH_HARDRESET = (1 << 2),
ATA_EH_ENABLE_LINK = (1 << 3),
ATA_EH_LPM = (1 << 4),
ATA_EH_RESET_MASK = ATA_EH_SOFTRESET | ATA_EH_HARDRESET,
ATA_EH_PERDEV_MASK = ATA_EH_REVALIDATE,
ATA_EHI_HOTPLUGGED = (1 << 0),
ATA_EHI_RESUME_LINK = (1 << 1),
ATA_EHI_NO_AUTOPSY = (1 << 2),
ATA_EHI_QUIET = (1 << 3),
ATA_EHI_DID_SOFTRESET = (1 << 16),
ATA_EHI_DID_HARDRESET = (1 << 17),
ATA_EHI_PRINTINFO = (1 << 18),
ATA_EHI_SETMODE = (1 << 19),
ATA_EHI_POST_SETMODE = (1 << 20),
ATA_EHI_DID_RESET = ATA_EHI_DID_SOFTRESET | ATA_EHI_DID_HARDRESET,
ATA_EHI_RESET_MODIFIER_MASK = ATA_EHI_RESUME_LINK,
ATA_EH_MAX_TRIES = 5,
ATA_PROBE_MAX_TRIES = 3,
ATA_EH_DEV_TRIES = 3,
ATA_EH_PMP_TRIES = 5,
ATA_EH_PMP_LINK_TRIES = 3,
SATA_PMP_SCR_TIMEOUT = 250,
/* Horkage types. May be set by libata or controller on drives
(some horkage may be drive/controller pair dependant */
ATA_HORKAGE_DIAGNOSTIC = (1 << 0),
ATA_HORKAGE_NODMA = (1 << 1),
ATA_HORKAGE_NONCQ = (1 << 2),
ATA_HORKAGE_MAX_SEC_128 = (1 << 3),
ATA_HORKAGE_BROKEN_HPA = (1 << 4),
ATA_HORKAGE_SKIP_PM = (1 << 5),
ATA_HORKAGE_HPA_SIZE = (1 << 6),
ATA_HORKAGE_IPM = (1 << 7),
ATA_HORKAGE_IVB = (1 << 8),
ATA_HORKAGE_STUCK_ERR = (1 << 9),
ATA_DMA_MASK_ATA = (1 << 0),
ATA_DMA_MASK_ATAPI = (1 << 1),
ATA_DMA_MASK_CFA = (1 << 2),
ATAPI_READ = 0,
ATAPI_WRITE = 1,
ATAPI_READ_CD = 2,
ATAPI_PASS_THRU = 3,
ATAPI_MISC = 4,
};
enum ata_completion_errors {
AC_ERR_DEV = (1 << 0),
AC_ERR_HSM = (1 << 1),
AC_ERR_TIMEOUT = (1 << 2),
AC_ERR_MEDIA = (1 << 3),
AC_ERR_ATA_BUS = (1 << 4),
AC_ERR_HOST_BUS = (1 << 5),
AC_ERR_SYSTEM = (1 << 6),
AC_ERR_INVALID = (1 << 7),
AC_ERR_OTHER = (1 << 8),
AC_ERR_NODEV_HINT = (1 << 9),
AC_ERR_NCQ = (1 << 10),
};
enum ata_xfer_mask {
ATA_MASK_PIO = ((1LU << ATA_NR_PIO_MODES) - 1) << ATA_SHIFT_PIO,
ATA_MASK_MWDMA = ((1LU << ATA_NR_MWDMA_MODES) - 1) << ATA_SHIFT_MWDMA,
ATA_MASK_UDMA = ((1LU << ATA_NR_UDMA_MODES) - 1) << ATA_SHIFT_UDMA,
};
struct ata_port_info {
#ifndef __U_BOOT__
struct scsi_host_template *sht;
#endif
unsigned long flags;
unsigned long link_flags;
unsigned long pio_mask;
unsigned long mwdma_mask;
unsigned long udma_mask;
#ifndef __U_BOOT__
const struct ata_port_operations *port_ops;
void *private_data;
#endif
};
struct ata_ioports {
void __iomem *cmd_addr;
void __iomem *data_addr;
void __iomem *error_addr;
void __iomem *feature_addr;
void __iomem *nsect_addr;
void __iomem *lbal_addr;
void __iomem *lbam_addr;
void __iomem *lbah_addr;
void __iomem *device_addr;
void __iomem *status_addr;
void __iomem *command_addr;
void __iomem *altstatus_addr;
void __iomem *ctl_addr;
#ifndef __U_BOOT__
void __iomem *bmdma_addr;
#endif
void __iomem *scr_addr;
};
struct ata_host {
#ifndef __U_BOOT__
void __iomem * const *iomap;
void *private_data;
const struct ata_port_operations *ops;
unsigned long flags;
struct ata_port *simplex_claimed;
#endif
unsigned int n_ports;
struct ata_port *ports[0];
};
#ifndef __U_BOOT__
struct ata_port_stats {
unsigned long unhandled_irq;
unsigned long idle_irq;
unsigned long rw_reqbuf;
};
#endif
struct ata_device {
struct ata_link *link;
unsigned int devno;
unsigned long flags;
unsigned int horkage;
#ifndef __U_BOOT__
struct scsi_device *sdev;
#ifdef CONFIG_ATA_ACPI
acpi_handle acpi_handle;
union acpi_object *gtf_cache;
#endif
#endif
u64 n_sectors;
unsigned int class;
union {
u16 id[ATA_ID_WORDS];
u32 gscr[SATA_PMP_GSCR_DWORDS];
};
#ifndef __U_BOOT__
u8 pio_mode;
u8 dma_mode;
u8 xfer_mode;
unsigned int xfer_shift;
#endif
unsigned int multi_count;
unsigned int max_sectors;
unsigned int cdb_len;
#ifndef __U_BOOT__
unsigned long pio_mask;
unsigned long mwdma_mask;
#endif
unsigned long udma_mask;
u16 cylinders;
u16 heads;
u16 sectors;
#ifndef __U_BOOT__
int spdn_cnt;
#endif
};
enum dma_data_direction {
DMA_BIDIRECTIONAL = 0,
DMA_TO_DEVICE = 1,
DMA_FROM_DEVICE = 2,
DMA_NONE = 3,
};
struct ata_link {
struct ata_port *ap;
int pmp;
unsigned int active_tag;
u32 sactive;
unsigned int flags;
unsigned int hw_sata_spd_limit;
#ifndef __U_BOOT__
unsigned int sata_spd_limit;
unsigned int sata_spd;
struct ata_device device[2];
#endif
};
struct ata_port {
unsigned long flags;
unsigned int pflags;
unsigned int print_id;
unsigned int port_no;
struct ata_ioports ioaddr;
u8 ctl;
u8 last_ctl;
unsigned int pio_mask;
unsigned int mwdma_mask;
unsigned int udma_mask;
unsigned int cbl;
struct ata_queued_cmd qcmd[ATA_MAX_QUEUE];
unsigned long qc_allocated;
unsigned int qc_active;
int nr_active_links;
struct ata_link link;
#ifndef __U_BOOT__
int nr_pmp_links;
struct ata_link *pmp_link;
#endif
struct ata_link *excl_link;
int nr_pmp_links;
#ifndef __U_BOOT__
struct ata_port_stats stats;
struct device *dev;
u32 msg_enable;
#endif
struct ata_host *host;
void *port_task_data;
unsigned int hsm_task_state;
void *private_data;
unsigned char *pdata;
};
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif
|
1001-study-uboot
|
drivers/block/sata_dwc.h
|
C
|
gpl3
| 10,773
|
/*
* Freescale iMX51 ATA driver
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* Based on code by:
* Mahesh Mahadevan <mahesh.mahadevan@freescale.com>
*
* Based on code from original FSL ATA driver, which is
* part of eCos, the Embedded Configurable Operating System.
* Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <config.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <ide.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
/* MXC ATA register offsets */
struct mxc_ata_config_regs {
u8 time_off; /* 0x00 */
u8 time_on;
u8 time_1;
u8 time_2w;
u8 time_2r;
u8 time_ax;
u8 time_pio_rdx;
u8 time_4;
u8 time_9;
u8 time_m;
u8 time_jn;
u8 time_d;
u8 time_k;
u8 time_ack;
u8 time_env;
u8 time_udma_rdx;
u8 time_zah; /* 0x10 */
u8 time_mlix;
u8 time_dvh;
u8 time_dzfs;
u8 time_dvs;
u8 time_cvh;
u8 time_ss;
u8 time_cyc;
u32 fifo_data_32; /* 0x18 */
u32 fifo_data_16;
u32 fifo_fill;
u32 ata_control;
u32 interrupt_pending;
u32 interrupt_enable;
u32 interrupt_clear;
u32 fifo_alarm;
};
struct mxc_data_hdd_regs {
u32 drive_data; /* 0xa0 */
u32 drive_features;
u32 drive_sector_count;
u32 drive_sector_num;
u32 drive_cyl_low;
u32 drive_cyl_high;
u32 drive_dev_head;
u32 command;
u32 status;
u32 alt_status;
};
/* PIO timing table */
#define NR_PIO_SPECS 5
static uint16_t pio_t1[NR_PIO_SPECS] = { 70, 50, 30, 30, 25 };
static uint16_t pio_t2_8[NR_PIO_SPECS] = { 290, 290, 290, 80, 70 };
static uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 };
static uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 };
static uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 };
#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8)
static void set_ata_bus_timing(unsigned char mode)
{
uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK);
struct mxc_ata_config_regs *ata_regs;
ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
if (mode >= NR_PIO_SPECS)
return;
/* Write TIME_OFF/ON/1/2W */
writeb(3, &ata_regs->time_off);
writeb(3, &ata_regs->time_on);
writeb((pio_t1[mode] + T) / T, &ata_regs->time_1);
writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2w);
/* Write TIME_2R/AX/RDX/4 */
writeb((pio_t2_8[mode] + T) / T, &ata_regs->time_2r);
writeb((pio_tA[mode] + T) / T + 2, &ata_regs->time_ax);
writeb(1, &ata_regs->time_pio_rdx);
writeb((pio_t4[mode] + T) / T, &ata_regs->time_4);
/* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */
writeb((pio_t9[mode] + T) / T, &ata_regs->time_9);
}
int ide_preinit(void)
{
struct mxc_ata_config_regs *ata_regs;
ata_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR;
/* 46.3.3.4 @ FSL iMX51 manual */
/* FIFO normal op., drive reset */
writel(0x80, &ata_regs->ata_control);
/* FIFO normal op., drive not reset */
writel(0xc0, &ata_regs->ata_control);
/* Configure the PIO timing */
set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE);
/* 46.3.3.4 @ FSL iMX51 manual */
/* Drive not reset, IORDY handshake */
writel(0x41, &ata_regs->ata_control);
return 0;
}
|
1001-study-uboot
|
drivers/block/mxc_ata.c
|
C
|
gpl3
| 3,859
|
/*
* Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
* Author: Tor Krill <tor@excito.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef SATA_SIL3114_H
#define SATA_SIL3114_H
struct sata_ioports {
unsigned long cmd_addr;
unsigned long data_addr;
unsigned long error_addr;
unsigned long feature_addr;
unsigned long nsect_addr;
unsigned long lbal_addr;
unsigned long lbam_addr;
unsigned long lbah_addr;
unsigned long device_addr;
unsigned long status_addr;
unsigned long command_addr;
unsigned long altstatus_addr;
unsigned long ctl_addr;
unsigned long bmdma_addr;
unsigned long scr_addr;
};
struct sata_port {
unsigned char port_no; /* primary=0, secondary=1 */
struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
unsigned char ctl_reg;
unsigned char last_ctl;
unsigned char port_state; /* 1-port is available and */
/* 0-port is not available */
unsigned char dev_mask;
};
/* Missing ata defines */
#define ATA_CMD_STANDBY 0xE2
#define ATA_CMD_STANDBYNOW1 0xE0
#define ATA_CMD_IDLE 0xE3
#define ATA_CMD_IDLEIMMEDIATE 0xE1
/* Defines for SIL3114 chip */
/* PCI defines */
#define SIL_VEND_ID 0x1095
#define SIL3114_DEVICE_ID 0x3114
/* some vendor specific registers */
#define VND_SYSCONFSTAT 0x88 /* System Configuration Status and Command */
#define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22)
#define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23)
#define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24)
#define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25)
/* internal registers mapped by BAR5 */
/* SATA Control*/
#define VND_SCONTROL_CH0 0x100
#define VND_SCONTROL_CH1 0x180
#define VND_SCONTROL_CH2 0x300
#define VND_SCONTROL_CH3 0x380
#define SATA_SC_IPM_T2P (1<<16)
#define SATA_SC_IPM_T2S (2<<16)
#define SATA_SC_SPD_1_5 (1<<4)
#define SATA_SC_SPD_3_0 (2<<4)
#define SATA_SC_DET_RST (1) /* ATA Reset sequence */
#define SATA_SC_DET_PDIS (4) /* PHY Disable */
/* SATA Status */
#define VND_SSTATUS_CH0 0x104
#define VND_SSTATUS_CH1 0x184
#define VND_SSTATUS_CH2 0x304
#define VND_SSTATUS_CH3 0x384
#define SATA_SS_IPM_ACTIVE (1<<8)
#define SATA_SS_IPM_PARTIAL (2<<8)
#define SATA_SS_IPM_SLUMBER (6<<8)
#define SATA_SS_SPD_1_5 (1<<4)
#define SATA_SS_SPD_3_0 (2<<4)
#define SATA_DET_P_NOPHY (1) /* Device presence but no PHY connection established */
#define SATA_DET_PRES (3) /* Device presence and active PHY */
#define SATA_DET_OFFLINE (4) /* Device offline or in loopback mode */
/* Task file registers in BAR5 mapping */
#define VND_TF0_CH0 0x80
#define VND_TF0_CH1 0xc0
#define VND_TF0_CH2 0x280
#define VND_TF0_CH3 0x2c0
#define VND_TF1_CH0 0x88
#define VND_TF1_CH1 0xc8
#define VND_TF1_CH2 0x288
#define VND_TF1_CH3 0x2c8
#define VND_TF2_CH0 0x88
#define VND_TF2_CH1 0xc8
#define VND_TF2_CH2 0x288
#define VND_TF2_CH3 0x2c8
#define VND_BMDMA_CH0 0x00
#define VND_BMDMA_CH1 0x08
#define VND_BMDMA_CH2 0x200
#define VND_BMDMA_CH3 0x208
#define VND_BMDMA2_CH0 0x10
#define VND_BMDMA2_CH1 0x18
#define VND_BMDMA2_CH2 0x210
#define VND_BMDMA2_CH3 0x218
/* FIFO control */
#define VND_FIFOCFG_CH0 0x40
#define VND_FIFOCFG_CH1 0x44
#define VND_FIFOCFG_CH2 0x240
#define VND_FIFOCFG_CH3 0x244
/* Task File configuration and status */
#define VND_TF_CNST_CH0 0xa0
#define VND_TF_CNST_CH1 0xe0
#define VND_TF_CNST_CH2 0x2a0
#define VND_TF_CNST_CH3 0x2e0
#define VND_TF_CNST_BFCMD (1<<1)
#define VND_TF_CNST_CHNRST (1<<2)
#define VND_TF_CNST_VDMA (1<<10)
#define VND_TF_CNST_INTST (1<<11)
#define VND_TF_CNST_WDTO (1<<12)
#define VND_TF_CNST_WDEN (1<<13)
#define VND_TF_CNST_WDIEN (1<<14)
/* for testing */
#define VND_SSDR 0x04c /* System Software Data Register */
#define VND_FMACS 0x050 /* Flash Memory Address control and status */
#endif
|
1001-study-uboot
|
drivers/block/sata_sil3114.h
|
C
|
gpl3
| 4,448
|
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* partly derived from
* linux/drivers/scsi/sym53c8xx.c
*
*/
/*
* SCSI support based on the chip sym53C810.
*
* 09-19-2001 Andreas Heppel, Sysgo RTS GmbH <aheppel@sysgo.de>
* The local version of this driver for the BAB750 board does not
* use interrupts but polls the chip instead (see the call of
* 'handle_scsi_int()' in 'scsi_issue()'.
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <sym53c8xx.h>
#include <scsi.h>
#undef SYM53C8XX_DEBUG
#ifdef SYM53C8XX_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
#if defined(CONFIG_CMD_SCSI) && defined(CONFIG_SCSI_SYM53C8XX)
#undef SCSI_SINGLE_STEP
/*
* Single Step is only used for debug purposes
*/
#ifdef SCSI_SINGLE_STEP
static unsigned long start_script_select;
static unsigned long start_script_msgout;
static unsigned long start_script_msgin;
static unsigned long start_script_msg_ext;
static unsigned long start_script_cmd;
static unsigned long start_script_data_in;
static unsigned long start_script_data_out;
static unsigned long start_script_status;
static unsigned long start_script_complete;
static unsigned long start_script_error;
static unsigned long start_script_reselection;
static unsigned int len_script_select;
static unsigned int len_script_msgout;
static unsigned int len_script_msgin;
static unsigned int len_script_msg_ext;
static unsigned int len_script_cmd;
static unsigned int len_script_data_in;
static unsigned int len_script_data_out;
static unsigned int len_script_status;
static unsigned int len_script_complete;
static unsigned int len_script_error;
static unsigned int len_script_reselection;
#endif
static unsigned short scsi_int_mask; /* shadow register for SCSI related interrupts */
static unsigned char script_int_mask; /* shadow register for SCRIPT related interrupts */
static unsigned long script_select[8]; /* script for selection */
static unsigned long script_msgout[8]; /* script for message out phase (NOT USED) */
static unsigned long script_msgin[14]; /* script for message in phase */
static unsigned long script_msg_ext[32]; /* script for message in phase when more than 1 byte message */
static unsigned long script_cmd[18]; /* script for command phase */
static unsigned long script_data_in[8]; /* script for data in phase */
static unsigned long script_data_out[8]; /* script for data out phase */
static unsigned long script_status[6]; /* script for status phase */
static unsigned long script_complete[10]; /* script for complete */
static unsigned long script_reselection[4]; /* script for reselection (NOT USED) */
static unsigned long script_error[2]; /* script for error handling */
static unsigned long int_stat[3]; /* interrupt status */
static unsigned long scsi_mem_addr; /* base memory address =SCSI_MEM_ADDRESS; */
#define bus_to_phys(a) pci_mem_to_phys(busdevfunc, (unsigned long) (a))
#define phys_to_bus(a) pci_phys_to_mem(busdevfunc, (unsigned long) (a))
#define SCSI_MAX_RETRY 3 /* number of retries in scsi_issue() */
#define SCSI_MAX_RETRY_NOT_READY 10 /* number of retries when device is not ready */
#define SCSI_NOT_READY_TIME_OUT 500 /* timeout per retry when not ready */
/*********************************************************************************
* forward declerations
*/
void scsi_chip_init(void);
void handle_scsi_int(void);
/********************************************************************************
* reports SCSI errors to the user
*/
void scsi_print_error (ccb * pccb)
{
int i;
printf ("SCSI Error: Target %d LUN %d Command %02X\n", pccb->target,
pccb->lun, pccb->cmd[0]);
printf (" CCB: ");
for (i = 0; i < pccb->cmdlen; i++)
printf ("%02X ", pccb->cmd[i]);
printf ("(len=%d)\n", pccb->cmdlen);
printf (" Cntrl: ");
switch (pccb->contr_stat) {
case SIR_COMPLETE:
printf ("Complete (no Error)\n");
break;
case SIR_SEL_ATN_NO_MSG_OUT:
printf ("Selected with ATN no MSG out phase\n");
break;
case SIR_CMD_OUT_ILL_PH:
printf ("Command out illegal phase\n");
break;
case SIR_MSG_RECEIVED:
printf ("MSG received Error\n");
break;
case SIR_DATA_IN_ERR:
printf ("Data in Error\n");
break;
case SIR_DATA_OUT_ERR:
printf ("Data out Error\n");
break;
case SIR_SCRIPT_ERROR:
printf ("Script Error\n");
break;
case SIR_MSG_OUT_NO_CMD:
printf ("MSG out no Command phase\n");
break;
case SIR_MSG_OVER7:
printf ("MSG in over 7 bytes\n");
break;
case INT_ON_FY:
printf ("Interrupt on fly\n");
break;
case SCSI_SEL_TIME_OUT:
printf ("SCSI Selection Timeout\n");
break;
case SCSI_HNS_TIME_OUT:
printf ("SCSI Handshake Timeout\n");
break;
case SCSI_MA_TIME_OUT:
printf ("SCSI Phase Error\n");
break;
case SCSI_UNEXP_DIS:
printf ("SCSI unexpected disconnect\n");
break;
default:
printf ("unknown status %lx\n", pccb->contr_stat);
break;
}
printf (" Sense: SK %x (", pccb->sense_buf[2] & 0x0f);
switch (pccb->sense_buf[2] & 0xf) {
case SENSE_NO_SENSE:
printf ("No Sense)");
break;
case SENSE_RECOVERED_ERROR:
printf ("Recovered Error)");
break;
case SENSE_NOT_READY:
printf ("Not Ready)");
break;
case SENSE_MEDIUM_ERROR:
printf ("Medium Error)");
break;
case SENSE_HARDWARE_ERROR:
printf ("Hardware Error)");
break;
case SENSE_ILLEGAL_REQUEST:
printf ("Illegal request)");
break;
case SENSE_UNIT_ATTENTION:
printf ("Unit Attention)");
break;
case SENSE_DATA_PROTECT:
printf ("Data Protect)");
break;
case SENSE_BLANK_CHECK:
printf ("Blank check)");
break;
case SENSE_VENDOR_SPECIFIC:
printf ("Vendor specific)");
break;
case SENSE_COPY_ABORTED:
printf ("Copy aborted)");
break;
case SENSE_ABORTED_COMMAND:
printf ("Aborted Command)");
break;
case SENSE_VOLUME_OVERFLOW:
printf ("Volume overflow)");
break;
case SENSE_MISCOMPARE:
printf ("Misscompare\n");
break;
default:
printf ("Illegal Sensecode\n");
break;
}
printf (" ASC %x ASCQ %x\n", pccb->sense_buf[12],
pccb->sense_buf[13]);
printf (" Status: ");
switch (pccb->status) {
case S_GOOD:
printf ("Good\n");
break;
case S_CHECK_COND:
printf ("Check condition\n");
break;
case S_COND_MET:
printf ("Condition Met\n");
break;
case S_BUSY:
printf ("Busy\n");
break;
case S_INT:
printf ("Intermediate\n");
break;
case S_INT_COND_MET:
printf ("Intermediate condition met\n");
break;
case S_CONFLICT:
printf ("Reservation conflict\n");
break;
case S_TERMINATED:
printf ("Command terminated\n");
break;
case S_QUEUE_FULL:
printf ("Task set full\n");
break;
default:
printf ("unknown: %02X\n", pccb->status);
break;
}
}
/******************************************************************************
* sets-up the SCSI controller
* the base memory address is retrived via the pci_read_config_dword
*/
void scsi_low_level_init(int busdevfunc)
{
unsigned int cmd;
unsigned int addr;
unsigned char vec;
pci_read_config_byte(busdevfunc, PCI_INTERRUPT_LINE, &vec);
pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_1, &addr);
addr = bus_to_phys(addr & ~0xf);
/*
* Enable bus mastering in case this has not been done, yet.
*/
pci_read_config_dword(busdevfunc, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER;
pci_write_config_dword(busdevfunc, PCI_COMMAND, cmd);
scsi_mem_addr = addr;
scsi_chip_init();
scsi_bus_reset();
}
/************************************************************************************
* Low level Part of SCSI Driver
*/
/*
* big-endian -> little endian conversion for the script
*/
unsigned long swap_script(unsigned long val)
{
unsigned long tmp;
tmp = ((val>>24)&0xff) | ((val>>8)&0xff00) | ((val<<8)&0xff0000) | ((val<<24)&0xff000000);
return tmp;
}
void scsi_write_byte(ulong offset,unsigned char val)
{
out8(scsi_mem_addr+offset,val);
}
unsigned char scsi_read_byte(ulong offset)
{
return(in8(scsi_mem_addr+offset));
}
/********************************************************************************
* interrupt handler
*/
void handle_scsi_int(void)
{
unsigned char stat,stat1,stat2;
unsigned short sstat;
int i;
#ifdef SCSI_SINGLE_STEP
unsigned long tt;
#endif
stat=scsi_read_byte(ISTAT);
if((stat & DIP)==DIP) { /* DMA Interrupt pending */
stat1=scsi_read_byte(DSTAT);
#ifdef SCSI_SINGLE_STEP
if((stat1 & SSI)==SSI) {
tt=in32r(scsi_mem_addr+DSP);
if(((tt)>=start_script_select) && ((tt)<start_script_select+len_script_select)) {
printf("select %d\n",(tt-start_script_select)>>2);
goto end_single;
}
if(((tt)>=start_script_msgout) && ((tt)<start_script_msgout+len_script_msgout)) {
printf("msgout %d\n",(tt-start_script_msgout)>>2);
goto end_single;
}
if(((tt)>=start_script_msgin) && ((tt)<start_script_msgin+len_script_msgin)) {
printf("msgin %d\n",(tt-start_script_msgin)>>2);
goto end_single;
}
if(((tt)>=start_script_msg_ext) && ((tt)<start_script_msg_ext+len_script_msg_ext)) {
printf("msgin_ext %d\n",(tt-start_script_msg_ext)>>2);
goto end_single;
}
if(((tt)>=start_script_cmd) && ((tt)<start_script_cmd+len_script_cmd)) {
printf("cmd %d\n",(tt-start_script_cmd)>>2);
goto end_single;
}
if(((tt)>=start_script_data_in) && ((tt)<start_script_data_in+len_script_data_in)) {
printf("data_in %d\n",(tt-start_script_data_in)>>2);
goto end_single;
}
if(((tt)>=start_script_data_out) && ((tt)<start_script_data_out+len_script_data_out)) {
printf("data_out %d\n",(tt-start_script_data_out)>>2);
goto end_single;
}
if(((tt)>=start_script_status) && ((tt)<start_script_status+len_script_status)) {
printf("status %d\n",(tt-start_script_status)>>2);
goto end_single;
}
if(((tt)>=start_script_complete) && ((tt)<start_script_complete+len_script_complete)) {
printf("complete %d\n",(tt-start_script_complete)>>2);
goto end_single;
}
if(((tt)>=start_script_error) && ((tt)<start_script_error+len_script_error)) {
printf("error %d\n",(tt-start_script_error)>>2);
goto end_single;
}
if(((tt)>=start_script_reselection) && ((tt)<start_script_reselection+len_script_reselection)) {
printf("reselection %d\n",(tt-start_script_reselection)>>2);
goto end_single;
}
printf("sc: %lx\n",tt);
end_single:
stat2=scsi_read_byte(DCNTL);
stat2|=STD;
scsi_write_byte(DCNTL,stat2);
}
#endif
if((stat1 & SIR)==SIR) /* script interrupt */
{
int_stat[0]=in32(scsi_mem_addr+DSPS);
}
if((stat1 & DFE)==0) { /* fifo not epmty */
scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
stat2=scsi_read_byte(STEST3);
scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
}
}
if((stat & SIP)==SIP) { /* scsi interrupt */
sstat = (unsigned short)scsi_read_byte(SIST+1);
sstat <<=8;
sstat |= (unsigned short)scsi_read_byte(SIST);
for(i=0;i<3;i++) {
if(int_stat[i]==0)
break; /* found an empty int status */
}
int_stat[i]=SCSI_INT_STATE | sstat;
stat1=scsi_read_byte(DSTAT);
if((stat1 & DFE)==0) { /* fifo not epmty */
scsi_write_byte(CTEST3,CLF); /* Clear DMA FIFO */
stat2=scsi_read_byte(STEST3);
scsi_write_byte(STEST3,(stat2 | CSF)); /* Clear SCSI FIFO */
}
}
if((stat & INTF)==INTF) { /* interrupt on Fly */
scsi_write_byte(ISTAT,stat); /* clear it */
for(i=0;i<3;i++) {
if(int_stat[i]==0)
break; /* found an empty int status */
}
int_stat[i]=INT_ON_FY;
}
}
void scsi_bus_reset(void)
{
unsigned char t;
int i;
int end = CONFIG_SYS_SCSI_SPIN_UP_TIME*1000;
t=scsi_read_byte(SCNTL1);
scsi_write_byte(SCNTL1,(t | CRST));
udelay(50);
scsi_write_byte(SCNTL1,t);
puts("waiting for devices to spin up");
for(i=0;i<end;i++) {
udelay(1000); /* give the devices time to spin up */
if (i % 1000 == 0)
putc('.');
}
putc('\n');
scsi_chip_init(); /* reinit the chip ...*/
}
void scsi_int_enable(void)
{
scsi_write_byte(SIEN,(unsigned char)scsi_int_mask);
scsi_write_byte(SIEN+1,(unsigned char)(scsi_int_mask>>8));
scsi_write_byte(DIEN,script_int_mask);
}
void scsi_write_dsp(unsigned long start)
{
#ifdef SCSI_SINGLE_STEP
unsigned char t;
#endif
out32r(scsi_mem_addr + DSP,start);
#ifdef SCSI_SINGLE_STEP
t=scsi_read_byte(DCNTL);
t|=STD;
scsi_write_byte(DCNTL,t);
#endif
}
/* only used for debug purposes */
void scsi_print_script(void)
{
printf("script_select @ 0x%08lX\n",(unsigned long)&script_select[0]);
printf("script_msgout @ 0x%08lX\n",(unsigned long)&script_msgout[0]);
printf("script_msgin @ 0x%08lX\n",(unsigned long)&script_msgin[0]);
printf("script_msgext @ 0x%08lX\n",(unsigned long)&script_msg_ext[0]);
printf("script_cmd @ 0x%08lX\n",(unsigned long)&script_cmd[0]);
printf("script_data_in @ 0x%08lX\n",(unsigned long)&script_data_in[0]);
printf("script_data_out @ 0x%08lX\n",(unsigned long)&script_data_out[0]);
printf("script_status @ 0x%08lX\n",(unsigned long)&script_status[0]);
printf("script_complete @ 0x%08lX\n",(unsigned long)&script_complete[0]);
printf("script_error @ 0x%08lX\n",(unsigned long)&script_error[0]);
}
void scsi_set_script(ccb *pccb)
{
int busdevfunc = pccb->priv;
int i;
i=0;
script_select[i++]=swap_script(SCR_REG_REG(GPREG, SCR_AND, 0xfe));
script_select[i++]=0; /* LED ON */
script_select[i++]=swap_script(SCR_CLR(SCR_TRG)); /* select initiator mode */
script_select[i++]=0;
/* script_select[i++]=swap_script(SCR_SEL_ABS_ATN | pccb->target << 16); */
script_select[i++]=swap_script(SCR_SEL_ABS | pccb->target << 16);
script_select[i++]=swap_script(phys_to_bus(&script_cmd[4])); /* error handling */
script_select[i++]=swap_script(SCR_JUMP); /* next section */
/* script_select[i++]=swap_script((unsigned long)&script_msgout[0]); */ /* message out */
script_select[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* command out */
#ifdef SCSI_SINGLE_STEP
start_script_select=(unsigned long)&script_select[0];
len_script_select=i*4;
#endif
i=0;
script_msgout[i++]=swap_script(SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)));
script_msgout[i++]=SIR_SEL_ATN_NO_MSG_OUT;
script_msgout[i++]=swap_script( SCR_MOVE_ABS(1) ^ SCR_MSG_OUT);
script_msgout[i++]=swap_script(phys_to_bus(&pccb->msgout[0]));
script_msgout[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_COMMAND))); /* if Command phase */
script_msgout[i++]=swap_script(phys_to_bus(&script_cmd[0])); /* switch to command */
script_msgout[i++]=swap_script(SCR_INT); /* interrupt if not */
script_msgout[i++]=SIR_MSG_OUT_NO_CMD;
#ifdef SCSI_SINGLE_STEP
start_script_msgout=(unsigned long)&script_msgout[0];
len_script_msgout=i*4;
#endif
i=0;
script_cmd[i++]=swap_script(SCR_MOVE_ABS(pccb->cmdlen) ^ SCR_COMMAND);
script_cmd[i++]=swap_script(phys_to_bus(&pccb->cmd[0]));
script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN))); /* message in ? */
script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT))); /* data out ? */
script_cmd[i++]=swap_script(phys_to_bus(&script_data_out[0]));
script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN))); /* data in ? */
script_cmd[i++]=swap_script(phys_to_bus(&script_data_in[0]));
script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_STATUS))); /* status ? */
script_cmd[i++]=swap_script(phys_to_bus(&script_status[0]));
script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND))); /* command ? */
script_cmd[i++]=swap_script(phys_to_bus(&script_cmd[0]));
script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT))); /* message out ? */
script_cmd[i++]=swap_script(phys_to_bus(&script_msgout[0]));
script_cmd[i++]=swap_script(SCR_JUMP ^ IFTRUE (IF (SCR_MSG_IN))); /* just for error handling message in ? */
script_cmd[i++]=swap_script(phys_to_bus(&script_msgin[0]));
script_cmd[i++]=swap_script(SCR_INT); /* interrupt if not */
script_cmd[i++]=SIR_CMD_OUT_ILL_PH;
#ifdef SCSI_SINGLE_STEP
start_script_cmd=(unsigned long)&script_cmd[0];
len_script_cmd=i*4;
#endif
i=0;
script_data_out[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_OUT); /* move */
script_data_out[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
script_data_out[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
script_data_out[i++]=swap_script(phys_to_bus(&script_status[0]));
script_data_out[i++]=swap_script(SCR_INT);
script_data_out[i++]=SIR_DATA_OUT_ERR;
#ifdef SCSI_SINGLE_STEP
start_script_data_out=(unsigned long)&script_data_out[0];
len_script_data_out=i*4;
#endif
i=0;
script_data_in[i++]=swap_script(SCR_MOVE_ABS(pccb->datalen)^ SCR_DATA_IN); /* move */
script_data_in[i++]=swap_script(phys_to_bus(pccb->pdata)); /* pointer to buffer */
script_data_in[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)));
script_data_in[i++]=swap_script(phys_to_bus(&script_status[0]));
script_data_in[i++]=swap_script(SCR_INT);
script_data_in[i++]=SIR_DATA_IN_ERR;
#ifdef SCSI_SINGLE_STEP
start_script_data_in=(unsigned long)&script_data_in[0];
len_script_data_in=i*4;
#endif
i=0;
script_msgin[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN);
script_msgin[i++]=swap_script(phys_to_bus(&pccb->msgin[0]));
script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)));
script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)));
script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)));
script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)));
script_msgin[i++]=swap_script(phys_to_bus(&script_complete[0]));
script_msgin[i++]=swap_script(SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)));
script_msgin[i++]=swap_script(phys_to_bus(&script_msg_ext[0]));
script_msgin[i++]=swap_script(SCR_INT);
script_msgin[i++]=SIR_MSG_RECEIVED;
#ifdef SCSI_SINGLE_STEP
start_script_msgin=(unsigned long)&script_msgin[0];
len_script_msgin=i*4;
#endif
i=0;
script_msg_ext[i++]=swap_script(SCR_CLR (SCR_ACK)); /* clear ACK */
script_msg_ext[i++]=0;
script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* assuming this is the msg length */
script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[1]));
script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[2]));
script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[3]));
script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[4]));
script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[5]));
script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[6]));
script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
script_msg_ext[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_MSG_IN); /* next */
script_msg_ext[i++]=swap_script(phys_to_bus(&pccb->msgin[7]));
script_msg_ext[i++]=swap_script(SCR_JUMP ^ IFFALSE (IF (SCR_MSG_IN)));
script_msg_ext[i++]=swap_script(phys_to_bus(&script_complete[0])); /* no more bytes */
script_msg_ext[i++]=swap_script(SCR_INT);
script_msg_ext[i++]=SIR_MSG_OVER7;
#ifdef SCSI_SINGLE_STEP
start_script_msg_ext=(unsigned long)&script_msg_ext[0];
len_script_msg_ext=i*4;
#endif
i=0;
script_status[i++]=swap_script(SCR_MOVE_ABS (1) ^ SCR_STATUS);
script_status[i++]=swap_script(phys_to_bus(&pccb->status));
script_status[i++]=swap_script(SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)));
script_status[i++]=swap_script(phys_to_bus(&script_msgin[0]));
script_status[i++]=swap_script(SCR_INT);
script_status[i++]=SIR_STATUS_ILL_PH;
#ifdef SCSI_SINGLE_STEP
start_script_status=(unsigned long)&script_status[0];
len_script_status=i*4;
#endif
i=0;
script_complete[i++]=swap_script(SCR_REG_REG (SCNTL2, SCR_AND, 0x7f));
script_complete[i++]=0;
script_complete[i++]=swap_script(SCR_CLR (SCR_ACK|SCR_ATN));
script_complete[i++]=0;
script_complete[i++]=swap_script(SCR_WAIT_DISC);
script_complete[i++]=0;
script_complete[i++]=swap_script(SCR_REG_REG(GPREG, SCR_OR, 0x01));
script_complete[i++]=0; /* LED OFF */
script_complete[i++]=swap_script(SCR_INT);
script_complete[i++]=SIR_COMPLETE;
#ifdef SCSI_SINGLE_STEP
start_script_complete=(unsigned long)&script_complete[0];
len_script_complete=i*4;
#endif
i=0;
script_error[i++]=swap_script(SCR_INT); /* interrupt if error */
script_error[i++]=SIR_SCRIPT_ERROR;
#ifdef SCSI_SINGLE_STEP
start_script_error=(unsigned long)&script_error[0];
len_script_error=i*4;
#endif
i=0;
script_reselection[i++]=swap_script(SCR_CLR (SCR_TRG)); /* target status */
script_reselection[i++]=0;
script_reselection[i++]=swap_script(SCR_WAIT_RESEL);
script_reselection[i++]=swap_script(phys_to_bus(&script_select[0])); /* len = 4 */
#ifdef SCSI_SINGLE_STEP
start_script_reselection=(unsigned long)&script_reselection[0];
len_script_reselection=i*4;
#endif
}
void scsi_issue(ccb *pccb)
{
int busdevfunc = pccb->priv;
int i;
unsigned short sstat;
int retrycnt; /* retry counter */
for(i=0;i<3;i++)
int_stat[i]=0; /* delete all int status */
/* struct pccb must be set-up correctly */
retrycnt=0;
PRINTF("ID %d issue cmd %02X\n",pccb->target,pccb->cmd[0]);
pccb->trans_bytes=0; /* no bytes transfered yet */
scsi_set_script(pccb); /* fill in SCRIPT */
scsi_int_mask=STO | UDC | MA; /* | CMP; / * Interrupts which are enabled */
script_int_mask=0xff; /* enable all Ints */
scsi_int_enable();
scsi_write_dsp(phys_to_bus(&script_select[0])); /* start script */
/* now we have to wait for IRQs */
retry:
/*
* This version of the driver is _not_ interrupt driven,
* but polls the chip's interrupt registers (ISTAT, DSTAT).
*/
while(int_stat[0]==0)
handle_scsi_int();
if(int_stat[0]==SIR_COMPLETE) {
if(pccb->msgin[0]==M_DISCONNECT) {
PRINTF("Wait for reselection\n");
for(i=0;i<3;i++)
int_stat[i]=0; /* delete all int status */
scsi_write_dsp(phys_to_bus(&script_reselection[0])); /* start reselection script */
goto retry;
}
pccb->contr_stat=SIR_COMPLETE;
return;
}
if((int_stat[0] & SCSI_INT_STATE)==SCSI_INT_STATE) { /* scsi interrupt */
sstat=(unsigned short)int_stat[0];
if((sstat & STO)==STO) { /* selection timeout */
pccb->contr_stat=SCSI_SEL_TIME_OUT;
scsi_write_byte(GPREG,0x01);
PRINTF("ID: %X Selection Timeout\n",pccb->target);
return;
}
if((sstat & UDC)==UDC) { /* unexpected disconnect */
pccb->contr_stat=SCSI_UNEXP_DIS;
scsi_write_byte(GPREG,0x01);
PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
return;
}
if((sstat & RSL)==RSL) { /* reselection */
pccb->contr_stat=SCSI_UNEXP_DIS;
scsi_write_byte(GPREG,0x01);
PRINTF("ID: %X Unexpected Disconnect\n",pccb->target);
return;
}
if(((sstat & MA)==MA)||((sstat & HTH)==HTH)) { /* phase missmatch */
if(retrycnt<SCSI_MAX_RETRY) {
pccb->trans_bytes=pccb->datalen -
((unsigned long)scsi_read_byte(DBC) |
((unsigned long)scsi_read_byte(DBC+1)<<8) |
((unsigned long)scsi_read_byte(DBC+2)<<16));
for(i=0;i<3;i++)
int_stat[i]=0; /* delete all int status */
retrycnt++;
PRINTF("ID: %X Phase Missmatch Retry %d Phase %02X transfered %lx\n",
pccb->target,retrycnt,scsi_read_byte(SBCL),pccb->trans_bytes);
scsi_write_dsp(phys_to_bus(&script_cmd[4])); /* start retry script */
goto retry;
}
if((sstat & MA)==MA)
pccb->contr_stat=SCSI_MA_TIME_OUT;
else
pccb->contr_stat=SCSI_HNS_TIME_OUT;
PRINTF("Phase Missmatch stat %lx\n",pccb->contr_stat);
return;
} /* no phase int */
/* if((sstat & CMP)==CMP) {
pccb->contr_stat=SIR_COMPLETE;
return;
}
*/
PRINTF("SCSI INT %lX\n",int_stat[0]);
pccb->contr_stat=int_stat[0];
return;
} /* end scsi int */
PRINTF("SCRIPT INT %lX phase %02X\n",int_stat[0],scsi_read_byte(SBCL));
pccb->contr_stat=int_stat[0];
return;
}
int scsi_exec(ccb *pccb)
{
unsigned char tmpcmd[16],tmpstat;
int i,retrycnt,t;
unsigned long transbytes,datalen;
unsigned char *tmpptr;
retrycnt=0;
retry:
scsi_issue(pccb);
if(pccb->contr_stat!=SIR_COMPLETE)
return FALSE;
if(pccb->status==S_GOOD)
return TRUE;
if(pccb->status==S_CHECK_COND) { /* check condition */
for(i=0;i<16;i++)
tmpcmd[i]=pccb->cmd[i];
pccb->cmd[0]=SCSI_REQ_SENSE;
pccb->cmd[1]=pccb->lun<<5;
pccb->cmd[2]=0;
pccb->cmd[3]=0;
pccb->cmd[4]=14;
pccb->cmd[5]=0;
pccb->cmdlen=6;
pccb->msgout[0]=SCSI_IDENTIFY;
transbytes=pccb->trans_bytes;
tmpptr=pccb->pdata;
pccb->pdata = &pccb->sense_buf[0];
datalen=pccb->datalen;
pccb->datalen=14;
tmpstat=pccb->status;
scsi_issue(pccb);
for(i=0;i<16;i++)
pccb->cmd[i]=tmpcmd[i];
pccb->trans_bytes=transbytes;
pccb->pdata=tmpptr;
pccb->datalen=datalen;
pccb->status=tmpstat;
PRINTF("Request_sense sense key %x ASC %x ASCQ %x\n",pccb->sense_buf[2]&0x0f,
pccb->sense_buf[12],pccb->sense_buf[13]);
switch(pccb->sense_buf[2]&0xf) {
case SENSE_NO_SENSE:
case SENSE_RECOVERED_ERROR:
/* seems to be ok */
return TRUE;
break;
case SENSE_NOT_READY:
if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) {
/* if device is not in process of becoming ready */
return FALSE;
break;
} /* else fall through */
case SENSE_UNIT_ATTENTION:
if(retrycnt<SCSI_MAX_RETRY_NOT_READY) {
PRINTF("Target %d not ready, retry %d\n",pccb->target,retrycnt);
for(t=0;t<SCSI_NOT_READY_TIME_OUT;t++)
udelay(1000); /* 1sec wait */
retrycnt++;
goto retry;
}
PRINTF("Target %d not ready, %d retried\n",pccb->target,retrycnt);
return FALSE;
default:
return FALSE;
}
}
PRINTF("Status = %X\n",pccb->status);
return FALSE;
}
void scsi_chip_init(void)
{
/* first we issue a soft reset */
scsi_write_byte(ISTAT,SRST);
udelay(1000);
scsi_write_byte(ISTAT,0);
/* setup chip */
scsi_write_byte(SCNTL0,0xC0); /* full arbitration no start, no message, parity disabled, master */
scsi_write_byte(SCNTL1,0x00);
scsi_write_byte(SCNTL2,0x00);
#ifndef CONFIG_SYS_SCSI_SYM53C8XX_CCF /* config value for none 40 MHz clocks */
scsi_write_byte(SCNTL3,0x13); /* synchronous clock 40/4=10MHz, asynchronous 40MHz */
#else
scsi_write_byte(SCNTL3,CONFIG_SYS_SCSI_SYM53C8XX_CCF); /* config value for none 40 MHz clocks */
#endif
scsi_write_byte(SCID,0x47); /* ID=7, enable reselection */
scsi_write_byte(SXFER,0x00); /* synchronous transfer period 10MHz, asynchronous */
scsi_write_byte(SDID,0x00); /* targed SCSI ID = 0 */
scsi_int_mask=0x0000; /* no Interrupt is enabled */
script_int_mask=0x00;
scsi_int_enable();
scsi_write_byte(GPREG,0x01); /* GPIO0 is LED (off) */
scsi_write_byte(GPCNTL,0x0E); /* GPIO0 is Output */
scsi_write_byte(STIME0,0x08); /* handshake timer disabled, selection timeout 512msec */
scsi_write_byte(RESPID,0x80); /* repond only to the own ID (reselection) */
scsi_write_byte(STEST1,0x00); /* not isolated, SCLK is used */
scsi_write_byte(STEST2,0x00); /* no Lowlevel Mode? */
scsi_write_byte(STEST3,0x80); /* enable tolerANT */
scsi_write_byte(CTEST3,0x04); /* clear FIFO */
scsi_write_byte(CTEST4,0x00);
scsi_write_byte(CTEST5,0x00);
#ifdef SCSI_SINGLE_STEP
/* scsi_write_byte(DCNTL,IRQM | SSM); */
scsi_write_byte(DCNTL,IRQD | SSM);
scsi_write_byte(DMODE,MAN);
#else
/* scsi_write_byte(DCNTL,IRQM); */
scsi_write_byte(DCNTL,IRQD);
scsi_write_byte(DMODE,0x00);
#endif
}
#endif
|
1001-study-uboot
|
drivers/block/sym53c8xx.c
|
C
|
gpl3
| 29,409
|
/*
* Copyright (C) Procsys. All rights reserved.
* Author: Mushtaq Khan <mushtaq_k@procsys.com>
* <mushtaqk_921@yahoo.co.in>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* with the reference to ata_piix driver in kernel 2.4.32
*/
/*
* This file contains SATA controller and SATA drive initialization functions
*/
#include <common.h>
#include <asm/io.h>
#include <pci.h>
#include <command.h>
#include <config.h>
#include <asm/byteorder.h>
#include <part.h>
#include <ide.h>
#include <ata.h>
extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
extern int sata_curr_device;
#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
#define SATA_DECL
#define DRV_DECL /*For file specific declarations */
#include "ata_piix.h"
/*Macros realted to PCI*/
#define PCI_SATA_BUS 0x00
#define PCI_SATA_DEV 0x1f
#define PCI_SATA_FUNC 0x02
#define PCI_SATA_BASE1 0x10
#define PCI_SATA_BASE2 0x14
#define PCI_SATA_BASE3 0x18
#define PCI_SATA_BASE4 0x1c
#define PCI_SATA_BASE5 0x20
#define PCI_PMR 0x90
#define PCI_PI 0x09
#define PCI_PCS 0x92
#define PCI_DMA_CTL 0x48
#define PORT_PRESENT (1<<0)
#define PORT_ENABLED (1<<4)
u32 bdf;
u32 iobase1 = 0; /*Primary cmd block */
u32 iobase2 = 0; /*Primary ctl block */
u32 iobase3 = 0; /*Sec cmd block */
u32 iobase4 = 0; /*sec ctl block */
u32 iobase5 = 0; /*BMDMA*/
int
pci_sata_init (void)
{
u32 bus = PCI_SATA_BUS;
u32 dev = PCI_SATA_DEV;
u32 fun = PCI_SATA_FUNC;
u16 cmd = 0;
u8 lat = 0, pcibios_max_latency = 0xff;
u8 pmr; /*Port mapping reg */
u8 pi; /*Prgming Interface reg */
bdf = PCI_BDF (bus, dev, fun);
pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
(iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
(iobase5 == 0xFFFFFFFF)) {
printf ("error no base addr for SATA controller\n");
return 1;
/*ERROR*/}
iobase1 &= 0xFFFFFFFE;
iobase2 &= 0xFFFFFFFE;
iobase3 &= 0xFFFFFFFE;
iobase4 &= 0xFFFFFFFE;
iobase5 &= 0xFFFFFFFE;
/*check for mode */
pci_read_config_byte (bdf, PCI_PMR, &pmr);
if (pmr > 1) {
printf ("combined mode not supported\n");
return 1;
}
pci_read_config_byte (bdf, PCI_PI, &pi);
if ((pi & 0x05) != 0x05) {
printf ("Sata is in Legacy mode\n");
return 1;
} else {
printf ("sata is in Native mode\n");
}
/*MASTER CFG AND IO CFG */
pci_read_config_word (bdf, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
pci_write_config_word (bdf, PCI_COMMAND, cmd);
pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
if (lat < 16)
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
else if (lat > pcibios_max_latency)
lat = pcibios_max_latency;
pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
return 0;
}
int
sata_bus_probe (int port_no)
{
int orig_mask, mask;
u16 pcs;
mask = (PORT_PRESENT << port_no);
pci_read_config_word (bdf, PCI_PCS, &pcs);
orig_mask = (int) pcs & 0xff;
if ((orig_mask & mask) != mask)
return 0;
else
return 1;
}
int
init_sata (int dev)
{
static int done = 0;
u8 i, rv = 0;
if (!done)
done = 1;
else
return 0;
rv = pci_sata_init ();
if (rv == 1) {
printf ("pci initialization failed\n");
return 1;
}
port[0].port_no = 0;
port[0].ioaddr.cmd_addr = iobase1;
port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
iobase2 | ATA_PCI_CTL_OFS;
port[0].ioaddr.bmdma_addr = iobase5;
port[1].port_no = 1;
port[1].ioaddr.cmd_addr = iobase3;
port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
iobase4 | ATA_PCI_CTL_OFS;
port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
sata_port (&port[i].ioaddr);
for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
if (!(sata_bus_probe (i))) {
port[i].port_state = 0;
printf ("SATA#%d port is not present \n", i);
} else {
printf ("SATA#%d port is present\n", i);
if (sata_bus_softreset (i)) {
port[i].port_state = 0;
} else {
port[i].port_state = 1;
}
}
}
for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
u8 j, devno;
if (port[i].port_state == 0)
continue;
for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
sata_identify (i, j);
set_Feature_cmd (i, j);
devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
if ((sata_dev_desc[devno].lba > 0) &&
(sata_dev_desc[devno].blksz > 0)) {
dev_print (&sata_dev_desc[devno]);
/* initialize partition type */
init_part (&sata_dev_desc[devno]);
if (sata_curr_device < 0)
sata_curr_device =
i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
}
}
}
return 0;
}
static u8 __inline__
sata_inb (unsigned long ioaddr)
{
return inb (ioaddr);
}
static void __inline__
sata_outb (unsigned char val, unsigned long ioaddr)
{
outb (val, ioaddr);
}
static void
output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
outsw (ioaddr->data_addr, sect_buf, words << 1);
}
static int
input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
insw (ioaddr->data_addr, sect_buf, words << 1);
return 0;
}
static void
sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
{
unsigned char *end, *last;
last = dst;
end = src + len - 1;
/* reserve space for '\0' */
if (len < 2)
goto OUT;
/* skip leading white space */
while ((*src) && (src < end) && (*src == ' '))
++src;
/* copy string, omitting trailing white space */
while ((*src) && (src < end)) {
*dst++ = *src;
if (*src++ != ' ')
last = dst;
}
OUT:
*last = '\0';
}
int
sata_bus_softreset (int num)
{
u8 dev = 0, status = 0, i;
port[num].dev_mask = 0;
for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
if (!(sata_devchk (&port[num].ioaddr, i))) {
PRINTF ("dev_chk failed for dev#%d\n", i);
} else {
port[num].dev_mask |= (1 << i);
PRINTF ("dev_chk passed for dev#%d\n", i);
}
}
if (!(port[num].dev_mask)) {
printf ("no devices on port%d\n", num);
return 1;
}
dev_select (&port[num].ioaddr, dev);
port[num].ctl_reg = 0x08; /*Default value of control reg */
sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
udelay (10);
sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
udelay (10);
sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
/* spec mandates ">= 2ms" before checking status.
* We wait 150ms, because that was the magic delay used for
* ATAPI devices in Hale Landis's ATADRVR, for the period of time
* between when the ATA command register is written, and then
* status is checked. Because waiting for "a while" before
* checking status is fine, post SRST, we perform this magic
* delay here as well.
*/
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
}
if (status & ATA_BUSY)
printf ("ata%u is slow to respond,plz be patient\n", num);
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_chk_status (&port[num].ioaddr);
}
if (status & ATA_BUSY) {
printf ("ata%u failed to respond : ", num);
printf ("bus reset failed\n");
return 1;
}
return 0;
}
void
sata_identify (int num, int dev)
{
u8 cmd = 0, status = 0, devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
u16 iobuf[ATA_SECT_SIZE];
u64 n_sectors = 0;
u8 mask = 0;
memset (iobuf, 0, sizeof (iobuf));
hd_driveid_t *iop = (hd_driveid_t *) iobuf;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
printf ("dev%d is not present on port#%d\n", dev, num);
return;
}
printf ("port=%d dev=%d\n", num, dev);
dev_select (&port[num].ioaddr, dev);
status = 0;
cmd = ATA_CMD_IDENT; /*Device Identify Command */
sata_outb (cmd, port[num].ioaddr.command_addr);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (10);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
if (status & ATA_ERR) {
printf ("\ndevice not responding\n");
port[num].dev_mask &= ~mask;
return;
}
input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
"86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
iobuf[87], iobuf[88]);
/* we require LBA and DMA support (bits 8 & 9 of word 49) */
if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
PRINTF ("ata%u: no dma/lba\n", num);
}
ata_dump_id (iobuf);
if (ata_id_has_lba48 (iobuf)) {
n_sectors = ata_id_u64 (iobuf, 100);
} else {
n_sectors = ata_id_u32 (iobuf, 60);
}
PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
if (n_sectors == 0) {
port[num].dev_mask &= ~mask;
return;
}
sata_cpy ((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
sizeof (sata_dev_desc[devno].revision));
sata_cpy ((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
sizeof (sata_dev_desc[devno].vendor));
sata_cpy ((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
sizeof (sata_dev_desc[devno].product));
strswab (sata_dev_desc[devno].revision);
strswab (sata_dev_desc[devno].vendor);
if ((iop->config & 0x0080) == 0x0080) {
sata_dev_desc[devno].removable = 1;
} else {
sata_dev_desc[devno].removable = 0;
}
sata_dev_desc[devno].lba = iop->lba_capacity;
PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
#ifdef CONFIG_LBA48
if (iop->command_set_2 & 0x0400) {
sata_dev_desc[devno].lba48 = 1;
lba = (unsigned long long) iop->lba48_capacity[0] |
((unsigned long long) iop->lba48_capacity[1] << 16) |
((unsigned long long) iop->lba48_capacity[2] << 32) |
((unsigned long long) iop->lba48_capacity[3] << 48);
} else {
sata_dev_desc[devno].lba48 = 0;
}
#endif
/* assuming HD */
sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
sata_dev_desc[devno].lun = 0; /* just to fill something in... */
}
void
set_Feature_cmd (int num, int dev)
{
u8 mask = 0x00, status = 0;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
PRINTF ("dev%d is not present on port#%d\n", dev, num);
return;
}
dev_select (&port[num].ioaddr, dev);
sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
sata_outb (0, port[num].ioaddr.lbal_addr);
sata_outb (0, port[num].ioaddr.lbam_addr);
sata_outb (0, port[num].ioaddr.lbah_addr);
sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
udelay (50);
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
printf ("Error : status 0x%02x\n", status);
port[num].dev_mask &= ~mask;
}
}
void
sata_port (struct sata_ioports *ioport)
{
ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
}
int
sata_devchk (struct sata_ioports *ioaddr, int dev)
{
u8 nsect, lbal;
dev_select (ioaddr, dev);
sata_outb (0x55, ioaddr->nsect_addr);
sata_outb (0xaa, ioaddr->lbal_addr);
sata_outb (0xaa, ioaddr->nsect_addr);
sata_outb (0x55, ioaddr->lbal_addr);
sata_outb (0x55, ioaddr->nsect_addr);
sata_outb (0xaa, ioaddr->lbal_addr);
nsect = sata_inb (ioaddr->nsect_addr);
lbal = sata_inb (ioaddr->lbal_addr);
if ((nsect == 0x55) && (lbal == 0xaa))
return 1; /* we found a device */
else
return 0; /* nothing found */
}
void
dev_select (struct sata_ioports *ioaddr, int dev)
{
u8 tmp = 0;
if (dev == 0)
tmp = ATA_DEVICE_OBS;
else
tmp = ATA_DEVICE_OBS | ATA_DEV1;
sata_outb (tmp, ioaddr->device_addr);
sata_inb (ioaddr->altstatus_addr);
udelay (5);
}
u8
sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
{
u8 status;
do {
udelay (1000);
status = sata_chk_status (ioaddr);
max--;
} while ((status & bits) && (max > 0));
return status;
}
u8
sata_chk_status (struct sata_ioports * ioaddr)
{
return sata_inb (ioaddr->status_addr);
}
void
msleep (int count)
{
int i;
for (i = 0; i < count; i++)
udelay (1000);
}
ulong
sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
{
ulong n = 0, *buffer = (ulong *)buff;
u8 dev = 0, num = 0, mask = 0, status = 0;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
/*Port Number */
num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
/*dev on the port */
if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
else
dev = device;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
printf ("dev%d is not present on port#%d\n", dev, num);
return 0;
}
/* Select device */
dev_select (&port[num].ioaddr, dev);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", 0);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
sata_outb (0, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
sata_outb (1, port[num].ioaddr.nsect_addr);
sata_outb (((blknr) >> 0) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_READ_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_READ,
port[num].ioaddr.command_addr);
}
msleep (50);
/*may take up to 4 sec */
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
u8 err = 0;
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
err = sata_inb (port[num].ioaddr.error_addr);
printf ("Error reg = 0x%x\n", err);
return (n);
}
input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (50);
++n;
++blknr;
buffer += ATA_SECTORWORDS;
}
return n;
}
ulong
sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
{
ulong n = 0, *buffer = (ulong *)buff;
unsigned char status = 0, num = 0, dev = 0, mask = 0;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
/*Port Number */
num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
/*dev on the Port */
if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
else
dev = device;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
/* Select device */
dev_select (&port[num].ioaddr, dev);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n",
port[num].port_no);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
sata_outb (0, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
sata_outb (1, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_WRITE_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_WRITE,
port[num].ioaddr.command_addr);
}
msleep (50);
/*may take up to 4 sec */
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
return (n);
}
output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (50);
++n;
++blknr;
buffer += ATA_SECTORWORDS;
}
return n;
}
int scan_sata(int dev)
{
return 0;
}
|
1001-study-uboot
|
drivers/block/ata_piix.c
|
C
|
gpl3
| 18,793
|
/*
* Driver for Blackfin on-chip ATAPI controller.
*
* Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (c) 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <command.h>
#include <config.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/pata.h>
#include <ata.h>
#include <libata.h>
#include "pata_bfin.h"
static struct ata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
/**
* PIO Mode - Frequency compatibility
*/
/* mode: 0 1 2 3 4 */
static const u32 pio_fsclk[] =
{ 33333333, 33333333, 33333333, 33333333, 33333333 };
/**
* MDMA Mode - Frequency compatibility
*/
/* mode: 0 1 2 */
static const u32 mdma_fsclk[] = { 33333333, 33333333, 33333333 };
/**
* UDMA Mode - Frequency compatibility
*
* UDMA5 - 100 MB/s - SCLK = 133 MHz
* UDMA4 - 66 MB/s - SCLK >= 80 MHz
* UDMA3 - 44.4 MB/s - SCLK >= 50 MHz
* UDMA2 - 33 MB/s - SCLK >= 40 MHz
*/
/* mode: 0 1 2 3 4 5 */
static const u32 udma_fsclk[] =
{ 33333333, 33333333, 40000000, 50000000, 80000000, 133333333 };
/**
* Register transfer timing table
*/
/* mode: 0 1 2 3 4 */
/* Cycle Time */
static const u32 reg_t0min[] = { 600, 383, 330, 180, 120 };
/* DIOR/DIOW to end cycle */
static const u32 reg_t2min[] = { 290, 290, 290, 70, 25 };
/* DIOR/DIOW asserted pulse width */
static const u32 reg_teocmin[] = { 290, 290, 290, 80, 70 };
/**
* PIO timing table
*/
/* mode: 0 1 2 3 4 */
/* Cycle Time */
static const u32 pio_t0min[] = { 600, 383, 240, 180, 120 };
/* Address valid to DIOR/DIORW */
static const u32 pio_t1min[] = { 70, 50, 30, 30, 25 };
/* DIOR/DIOW to end cycle */
static const u32 pio_t2min[] = { 165, 125, 100, 80, 70 };
/* DIOR/DIOW asserted pulse width */
static const u32 pio_teocmin[] = { 165, 125, 100, 70, 25 };
/* DIOW data hold */
static const u32 pio_t4min[] = { 30, 20, 15, 10, 10 };
/* ******************************************************************
* Multiword DMA timing table
* ******************************************************************
*/
/* mode: 0 1 2 */
/* Cycle Time */
static const u32 mdma_t0min[] = { 480, 150, 120 };
/* DIOR/DIOW asserted pulse width */
static const u32 mdma_tdmin[] = { 215, 80, 70 };
/* DMACK to read data released */
static const u32 mdma_thmin[] = { 20, 15, 10 };
/* DIOR/DIOW to DMACK hold */
static const u32 mdma_tjmin[] = { 20, 5, 5 };
/* DIOR negated pulse width */
static const u32 mdma_tkrmin[] = { 50, 50, 25 };
/* DIOR negated pulse width */
static const u32 mdma_tkwmin[] = { 215, 50, 25 };
/* CS[1:0] valid to DIOR/DIOW */
static const u32 mdma_tmmin[] = { 50, 30, 25 };
/* DMACK to read data released */
static const u32 mdma_tzmax[] = { 20, 25, 25 };
/**
* Ultra DMA timing table
*/
/* mode: 0 1 2 3 4 5 */
static const u32 udma_tcycmin[] = { 112, 73, 54, 39, 25, 17 };
static const u32 udma_tdvsmin[] = { 70, 48, 31, 20, 7, 5 };
static const u32 udma_tenvmax[] = { 70, 70, 70, 55, 55, 50 };
static const u32 udma_trpmin[] = { 160, 125, 100, 100, 100, 85 };
static const u32 udma_tmin[] = { 5, 5, 5, 5, 3, 3 };
static const u32 udma_tmlimin = 20;
static const u32 udma_tzahmin = 20;
static const u32 udma_tenvmin = 20;
static const u32 udma_tackmin = 20;
static const u32 udma_tssmin = 50;
static void msleep(int count)
{
int i;
for (i = 0; i < count; i++)
udelay(1000);
}
/**
*
* Function: num_clocks_min
*
* Description:
* calculate number of SCLK cycles to meet minimum timing
*/
static unsigned short num_clocks_min(unsigned long tmin,
unsigned long fsclk)
{
unsigned long tmp ;
unsigned short result;
tmp = tmin * (fsclk/1000/1000) / 1000;
result = (unsigned short)tmp;
if ((tmp*1000*1000) < (tmin*(fsclk/1000)))
result++;
return result;
}
/**
* bfin_set_piomode - Initialize host controller PATA PIO timings
* @ap: Port whose timings we are configuring
* @pio_mode: mode
*
* Set PIO mode for device.
*
* LOCKING:
* None (inherited from caller).
*/
static void bfin_set_piomode(struct ata_port *ap, int pio_mode)
{
int mode = pio_mode - XFER_PIO_0;
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
unsigned int fsclk = get_sclk();
unsigned short teoc_reg, t2_reg, teoc_pio;
unsigned short t4_reg, t2_pio, t1_reg;
unsigned short n0, n6, t6min = 5;
/* the most restrictive timing value is t6 and tc, the DIOW - data hold
* If one SCLK pulse is longer than this minimum value then register
* transfers cannot be supported at this frequency.
*/
n6 = num_clocks_min(t6min, fsclk);
if (mode >= 0 && mode <= 4 && n6 >= 1) {
debug("set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
/* calculate the timing values for register transfers. */
while (mode > 0 && pio_fsclk[mode] > fsclk)
mode--;
/* DIOR/DIOW to end cycle time */
t2_reg = num_clocks_min(reg_t2min[mode], fsclk);
/* DIOR/DIOW asserted pulse width */
teoc_reg = num_clocks_min(reg_teocmin[mode], fsclk);
/* Cycle Time */
n0 = num_clocks_min(reg_t0min[mode], fsclk);
/* increase t2 until we meed the minimum cycle length */
if (t2_reg + teoc_reg < n0)
t2_reg = n0 - teoc_reg;
/* calculate the timing values for pio transfers. */
/* DIOR/DIOW to end cycle time */
t2_pio = num_clocks_min(pio_t2min[mode], fsclk);
/* DIOR/DIOW asserted pulse width */
teoc_pio = num_clocks_min(pio_teocmin[mode], fsclk);
/* Cycle Time */
n0 = num_clocks_min(pio_t0min[mode], fsclk);
/* increase t2 until we meed the minimum cycle length */
if (t2_pio + teoc_pio < n0)
t2_pio = n0 - teoc_pio;
/* Address valid to DIOR/DIORW */
t1_reg = num_clocks_min(pio_t1min[mode], fsclk);
/* DIOW data hold */
t4_reg = num_clocks_min(pio_t4min[mode], fsclk);
ATAPI_SET_REG_TIM_0(base, (teoc_reg<<8 | t2_reg));
ATAPI_SET_PIO_TIM_0(base, (t4_reg<<12 | t2_pio<<4 | t1_reg));
ATAPI_SET_PIO_TIM_1(base, teoc_pio);
if (mode > 2) {
ATAPI_SET_CONTROL(base,
ATAPI_GET_CONTROL(base) | IORDY_EN);
} else {
ATAPI_SET_CONTROL(base,
ATAPI_GET_CONTROL(base) & ~IORDY_EN);
}
/* Disable host ATAPI PIO interrupts */
ATAPI_SET_INT_MASK(base, ATAPI_GET_INT_MASK(base)
& ~(PIO_DONE_MASK | HOST_TERM_XFER_MASK));
SSYNC();
}
}
/**
*
* Function: wait_complete
*
* Description: Waits the interrupt from device
*
*/
static inline void wait_complete(void __iomem *base, unsigned short mask)
{
unsigned short status;
unsigned int i = 0;
for (i = 0; i < PATA_BFIN_WAIT_TIMEOUT; i++) {
status = ATAPI_GET_INT_STATUS(base) & mask;
if (status)
break;
}
ATAPI_SET_INT_STATUS(base, mask);
}
/**
*
* Function: write_atapi_register
*
* Description: Writes to ATA Device Resgister
*
*/
static void write_atapi_register(void __iomem *base,
unsigned long ata_reg, unsigned short value)
{
/* Program the ATA_DEV_TXBUF register with write data (to be
* written into the device).
*/
ATAPI_SET_DEV_TXBUF(base, value);
/* Program the ATA_DEV_ADDR register with address of the
* device register (0x01 to 0x0F).
*/
ATAPI_SET_DEV_ADDR(base, ata_reg);
/* Program the ATA_CTRL register with dir set to write (1)
*/
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
/* ensure PIO DMA is not set */
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
/* and start the transfer */
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
/* Wait for the interrupt to indicate the end of the transfer.
* (We need to wait on and clear rhe ATA_DEV_INT interrupt status)
*/
wait_complete(base, PIO_DONE_INT);
}
/**
*
* Function: read_atapi_register
*
*Description: Reads from ATA Device Resgister
*
*/
static unsigned short read_atapi_register(void __iomem *base,
unsigned long ata_reg)
{
/* Program the ATA_DEV_ADDR register with address of the
* device register (0x01 to 0x0F).
*/
ATAPI_SET_DEV_ADDR(base, ata_reg);
/* Program the ATA_CTRL register with dir set to read (0) and
*/
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
/* ensure PIO DMA is not set */
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
/* and start the transfer */
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
/* Wait for the interrupt to indicate the end of the transfer.
* (PIO_DONE interrupt is set and it doesn't seem to matter
* that we don't clear it)
*/
wait_complete(base, PIO_DONE_INT);
/* Read the ATA_DEV_RXBUF register with write data (to be
* written into the device).
*/
return ATAPI_GET_DEV_RXBUF(base);
}
/**
*
* Function: write_atapi_register_data
*
* Description: Writes to ATA Device Resgister
*
*/
static void write_atapi_data(void __iomem *base,
int len, unsigned short *buf)
{
int i;
/* Set transfer length to 1 */
ATAPI_SET_XFER_LEN(base, 1);
/* Program the ATA_DEV_ADDR register with address of the
* ATA_REG_DATA
*/
ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
/* Program the ATA_CTRL register with dir set to write (1)
*/
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | XFER_DIR));
/* ensure PIO DMA is not set */
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
for (i = 0; i < len; i++) {
/* Program the ATA_DEV_TXBUF register with write data (to be
* written into the device).
*/
ATAPI_SET_DEV_TXBUF(base, buf[i]);
/* and start the transfer */
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
/* Wait for the interrupt to indicate the end of the transfer.
* (We need to wait on and clear rhe ATA_DEV_INT
* interrupt status)
*/
wait_complete(base, PIO_DONE_INT);
}
}
/**
*
* Function: read_atapi_register_data
*
* Description: Reads from ATA Device Resgister
*
*/
static void read_atapi_data(void __iomem *base,
int len, unsigned short *buf)
{
int i;
/* Set transfer length to 1 */
ATAPI_SET_XFER_LEN(base, 1);
/* Program the ATA_DEV_ADDR register with address of the
* ATA_REG_DATA
*/
ATAPI_SET_DEV_ADDR(base, ATA_REG_DATA);
/* Program the ATA_CTRL register with dir set to read (0) and
*/
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~XFER_DIR));
/* ensure PIO DMA is not set */
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) & ~PIO_USE_DMA));
for (i = 0; i < len; i++) {
/* and start the transfer */
ATAPI_SET_CONTROL(base, (ATAPI_GET_CONTROL(base) | PIO_START));
/* Wait for the interrupt to indicate the end of the transfer.
* (PIO_DONE interrupt is set and it doesn't seem to matter
* that we don't clear it)
*/
wait_complete(base, PIO_DONE_INT);
/* Read the ATA_DEV_RXBUF register with write data (to be
* written into the device).
*/
buf[i] = ATAPI_GET_DEV_RXBUF(base);
}
}
/**
* bfin_check_status - Read device status reg & clear interrupt
* @ap: port where the device is
*
* Note: Original code is ata_check_status().
*/
static u8 bfin_check_status(struct ata_port *ap)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
return read_atapi_register(base, ATA_REG_STATUS);
}
/**
* bfin_check_altstatus - Read device alternate status reg
* @ap: port where the device is
*/
static u8 bfin_check_altstatus(struct ata_port *ap)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
return read_atapi_register(base, ATA_REG_ALTSTATUS);
}
/**
* bfin_ata_busy_wait - Wait for a port status register
* @ap: Port to wait for.
* @bits: bits that must be clear
* @max: number of 10uS waits to perform
*
* Waits up to max*10 microseconds for the selected bits in the port's
* status register to be cleared.
* Returns final value of status register.
*
* LOCKING:
* Inherited from caller.
*/
static inline u8 bfin_ata_busy_wait(struct ata_port *ap, unsigned int bits,
unsigned int max, u8 usealtstatus)
{
u8 status;
do {
udelay(10);
if (usealtstatus)
status = bfin_check_altstatus(ap);
else
status = bfin_check_status(ap);
max--;
} while (status != 0xff && (status & bits) && (max > 0));
return status;
}
/**
* bfin_ata_busy_sleep - sleep until BSY clears, or timeout
* @ap: port containing status register to be polled
* @tmout_pat: impatience timeout in msecs
* @tmout: overall timeout in msecs
*
* Sleep until ATA Status register bit BSY clears,
* or a timeout occurs.
*
* RETURNS:
* 0 on success, -errno otherwise.
*/
static int bfin_ata_busy_sleep(struct ata_port *ap,
long tmout_pat, unsigned long tmout)
{
u8 status;
status = bfin_ata_busy_wait(ap, ATA_BUSY, 300, 0);
while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
msleep(50);
tmout_pat -= 50;
status = bfin_ata_busy_wait(ap, ATA_BUSY, 3, 0);
}
if (status != 0xff && (status & ATA_BUSY))
printf("port is slow to respond, please be patient "
"(Status 0x%x)\n", status);
while (status != 0xff && (status & ATA_BUSY) && tmout_pat > 0) {
msleep(50);
tmout_pat -= 50;
status = bfin_check_status(ap);
}
if (status == 0xff)
return -ENODEV;
if (status & ATA_BUSY) {
printf("port failed to respond "
"(%lu secs, Status 0x%x)\n",
DIV_ROUND_UP(tmout, 1000), status);
return -EBUSY;
}
return 0;
}
/**
* bfin_dev_select - Select device 0/1 on ATA bus
* @ap: ATA channel to manipulate
* @device: ATA device (numbered from zero) to select
*
* Note: Original code is ata_sff_dev_select().
*/
static void bfin_dev_select(struct ata_port *ap, unsigned int device)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
u8 tmp;
if (device == 0)
tmp = ATA_DEVICE_OBS;
else
tmp = ATA_DEVICE_OBS | ATA_DEV1;
write_atapi_register(base, ATA_REG_DEVICE, tmp);
udelay(1);
}
/**
* bfin_devchk - PATA device presence detection
* @ap: ATA channel to examine
* @device: Device to examine (starting at zero)
*
* Note: Original code is ata_devchk().
*/
static unsigned int bfin_devchk(struct ata_port *ap,
unsigned int device)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
u8 nsect, lbal;
bfin_dev_select(ap, device);
write_atapi_register(base, ATA_REG_NSECT, 0x55);
write_atapi_register(base, ATA_REG_LBAL, 0xaa);
write_atapi_register(base, ATA_REG_NSECT, 0xaa);
write_atapi_register(base, ATA_REG_LBAL, 0x55);
write_atapi_register(base, ATA_REG_NSECT, 0x55);
write_atapi_register(base, ATA_REG_LBAL, 0xaa);
nsect = read_atapi_register(base, ATA_REG_NSECT);
lbal = read_atapi_register(base, ATA_REG_LBAL);
if ((nsect == 0x55) && (lbal == 0xaa))
return 1; /* we found a device */
return 0; /* nothing found */
}
/**
* bfin_bus_post_reset - PATA device post reset
*
* Note: Original code is ata_bus_post_reset().
*/
static void bfin_bus_post_reset(struct ata_port *ap, unsigned int devmask)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
unsigned int dev0 = devmask & (1 << 0);
unsigned int dev1 = devmask & (1 << 1);
long deadline;
/* if device 0 was found in ata_devchk, wait for its
* BSY bit to clear
*/
if (dev0)
bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
/* if device 1 was found in ata_devchk, wait for
* register access, then wait for BSY to clear
*/
deadline = ATA_TMOUT_BOOT;
while (dev1) {
u8 nsect, lbal;
bfin_dev_select(ap, 1);
nsect = read_atapi_register(base, ATA_REG_NSECT);
lbal = read_atapi_register(base, ATA_REG_LBAL);
if ((nsect == 1) && (lbal == 1))
break;
if (deadline <= 0) {
dev1 = 0;
break;
}
msleep(50); /* give drive a breather */
deadline -= 50;
}
if (dev1)
bfin_ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
/* is all this really necessary? */
bfin_dev_select(ap, 0);
if (dev1)
bfin_dev_select(ap, 1);
if (dev0)
bfin_dev_select(ap, 0);
}
/**
* bfin_bus_softreset - PATA device software reset
*
* Note: Original code is ata_bus_softreset().
*/
static unsigned int bfin_bus_softreset(struct ata_port *ap,
unsigned int devmask)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
/* software reset. causes dev0 to be selected */
write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
udelay(20);
write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg | ATA_SRST);
udelay(20);
write_atapi_register(base, ATA_REG_CTRL, ap->ctl_reg);
/* spec mandates ">= 2ms" before checking status.
* We wait 150ms, because that was the magic delay used for
* ATAPI devices in Hale Landis's ATADRVR, for the period of time
* between when the ATA command register is written, and then
* status is checked. Because waiting for "a while" before
* checking status is fine, post SRST, we perform this magic
* delay here as well.
*
* Old drivers/ide uses the 2mS rule and then waits for ready
*/
msleep(150);
/* Before we perform post reset processing we want to see if
* the bus shows 0xFF because the odd clown forgets the D7
* pulldown resistor.
*/
if (bfin_check_status(ap) == 0xFF)
return 0;
bfin_bus_post_reset(ap, devmask);
return 0;
}
/**
* bfin_softreset - reset host port via ATA SRST
* @ap: port to reset
*
* Note: Original code is ata_sff_softreset().
*/
static int bfin_softreset(struct ata_port *ap)
{
unsigned int err_mask;
ap->dev_mask = 0;
/* determine if device 0/1 are present.
* only one device is supported on one port by now.
*/
if (bfin_devchk(ap, 0))
ap->dev_mask |= (1 << 0);
else if (bfin_devchk(ap, 1))
ap->dev_mask |= (1 << 1);
else
return -ENODEV;
/* select device 0 again */
bfin_dev_select(ap, 0);
/* issue bus reset */
err_mask = bfin_bus_softreset(ap, ap->dev_mask);
if (err_mask) {
printf("SRST failed (err_mask=0x%x)\n",
err_mask);
ap->dev_mask = 0;
return -EIO;
}
return 0;
}
/**
* bfin_irq_clear - Clear ATAPI interrupt.
* @ap: Port associated with this ATA transaction.
*
* Note: Original code is ata_sff_irq_clear().
*/
static void bfin_irq_clear(struct ata_port *ap)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
| MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
| MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
}
static u8 bfin_wait_for_irq(struct ata_port *ap, unsigned int max)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
do {
if (ATAPI_GET_INT_STATUS(base) & (ATAPI_DEV_INT
| MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
| MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT)) {
break;
}
udelay(1000);
max--;
} while ((max > 0));
return max == 0;
}
/**
* bfin_ata_reset_port - initialize BFIN ATAPI port.
*/
static int bfin_ata_reset_port(struct ata_port *ap)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
int count;
unsigned short status;
/* Disable all ATAPI interrupts */
ATAPI_SET_INT_MASK(base, 0);
SSYNC();
/* Assert the RESET signal 25us*/
ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | DEV_RST);
udelay(30);
/* Negate the RESET signal for 2ms*/
ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) & ~DEV_RST);
msleep(2);
/* Wait on Busy flag to clear */
count = 10000000;
do {
status = read_atapi_register(base, ATA_REG_STATUS);
} while (--count && (status & ATA_BUSY));
/* Enable only ATAPI Device interrupt */
ATAPI_SET_INT_MASK(base, 1);
SSYNC();
return !count;
}
/**
*
* Function: bfin_config_atapi_gpio
*
* Description: Configures the ATAPI pins for use
*
*/
static int bfin_config_atapi_gpio(struct ata_port *ap)
{
const unsigned short pins[] = {
P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0,
P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ,
P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A,
P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A,
P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A,
P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0,
};
peripheral_request_list(pins, "pata_bfin");
return 0;
}
/**
* bfin_atapi_probe - attach a bfin atapi interface
* @pdev: platform device
*
* Register a bfin atapi interface.
*
*
* Platform devices are expected to contain 2 resources per port:
*
* - I/O Base (IORESOURCE_IO)
* - IRQ (IORESOURCE_IRQ)
*
*/
static int bfin_ata_probe_port(struct ata_port *ap)
{
if (bfin_config_atapi_gpio(ap)) {
printf("Requesting Peripherals faild\n");
return -EFAULT;
}
if (bfin_ata_reset_port(ap)) {
printf("Fail to reset ATAPI device\n");
return -EFAULT;
}
if (ap->ata_mode >= XFER_PIO_0 && ap->ata_mode <= XFER_PIO_4)
bfin_set_piomode(ap, ap->ata_mode);
else {
printf("Given ATA data transfer mode is not supported.\n");
return -EFAULT;
}
return 0;
}
#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
static void bfin_ata_identify(struct ata_port *ap, int dev)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
u8 status = 0;
static u16 iobuf[ATA_SECTOR_WORDS];
u64 n_sectors = 0;
hd_driveid_t *iop = (hd_driveid_t *)iobuf;
memset(iobuf, 0, sizeof(iobuf));
if (!(ap->dev_mask & (1 << dev)))
return;
debug("port=%d dev=%d\n", ap->port_no, dev);
bfin_dev_select(ap, dev);
status = 0;
/* Device Identify Command */
write_atapi_register(base, ATA_REG_CMD, ATA_CMD_ID_ATA);
bfin_check_altstatus(ap);
udelay(10);
status = bfin_ata_busy_wait(ap, ATA_BUSY, 1000, 0);
if (status & ATA_ERR) {
printf("\ndevice not responding\n");
ap->dev_mask &= ~(1 << dev);
return;
}
read_atapi_data(base, ATA_SECTOR_WORDS, iobuf);
ata_swap_buf_le16(iobuf, ATA_SECTOR_WORDS);
/* we require LBA and DMA support (bits 8 & 9 of word 49) */
if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
printf("ata%u: no dma/lba\n", ap->port_no);
#ifdef DEBUG
ata_dump_id(iobuf);
#endif
n_sectors = ata_id_n_sectors(iobuf);
if (n_sectors == 0) {
ap->dev_mask &= ~(1 << dev);
return;
}
ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].revision,
ATA_ID_FW_REV, sizeof(sata_dev_desc[ap->port_no].revision));
ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].vendor,
ATA_ID_PROD, sizeof(sata_dev_desc[ap->port_no].vendor));
ata_id_c_string(iobuf, (unsigned char *)sata_dev_desc[ap->port_no].product,
ATA_ID_SERNO, sizeof(sata_dev_desc[ap->port_no].product));
if ((iop->config & 0x0080) == 0x0080)
sata_dev_desc[ap->port_no].removable = 1;
else
sata_dev_desc[ap->port_no].removable = 0;
sata_dev_desc[ap->port_no].lba = (u32) n_sectors;
debug("lba=0x%x\n", sata_dev_desc[ap->port_no].lba);
#ifdef CONFIG_LBA48
if (iop->command_set_2 & 0x0400)
sata_dev_desc[ap->port_no].lba48 = 1;
else
sata_dev_desc[ap->port_no].lba48 = 0;
#endif
/* assuming HD */
sata_dev_desc[ap->port_no].type = DEV_TYPE_HARDDISK;
sata_dev_desc[ap->port_no].blksz = ATA_SECT_SIZE;
sata_dev_desc[ap->port_no].lun = 0; /* just to fill something in... */
printf("PATA device#%d %s is found on ata port#%d.\n",
ap->port_no%PATA_DEV_NUM_PER_PORT,
sata_dev_desc[ap->port_no].vendor,
ap->port_no/PATA_DEV_NUM_PER_PORT);
}
static void bfin_ata_set_Feature_cmd(struct ata_port *ap, int dev)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
u8 status = 0;
if (!(ap->dev_mask & (1 << dev)))
return;
bfin_dev_select(ap, dev);
write_atapi_register(base, ATA_REG_FEATURE, SETFEATURES_XFER);
write_atapi_register(base, ATA_REG_NSECT, ap->ata_mode);
write_atapi_register(base, ATA_REG_LBAL, 0);
write_atapi_register(base, ATA_REG_LBAM, 0);
write_atapi_register(base, ATA_REG_LBAH, 0);
write_atapi_register(base, ATA_REG_DEVICE, ATA_DEVICE_OBS);
write_atapi_register(base, ATA_REG_CMD, ATA_CMD_SET_FEATURES);
udelay(50);
msleep(150);
status = bfin_ata_busy_wait(ap, ATA_BUSY, 5000, 0);
if ((status & (ATA_BUSY | ATA_ERR))) {
printf("Error : status 0x%02x\n", status);
ap->dev_mask &= ~(1 << dev);
}
}
int scan_sata(int dev)
{
/* dev is the index of each ata device in the system. one PATA port
* contains 2 devices. one element in scan_done array indicates one
* PATA port. device connected to one PATA port is selected by
* bfin_dev_select() before access.
*/
struct ata_port *ap = &port[dev];
static int scan_done[(CONFIG_SYS_SATA_MAX_DEVICE+1)/PATA_DEV_NUM_PER_PORT];
if (scan_done[dev/PATA_DEV_NUM_PER_PORT])
return 0;
/* Check for attached device */
if (!bfin_ata_probe_port(ap)) {
if (bfin_softreset(ap)) {
/* soft reset failed, try a hard one */
bfin_ata_reset_port(ap);
if (bfin_softreset(ap))
scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
} else {
scan_done[dev/PATA_DEV_NUM_PER_PORT] = 1;
}
}
if (scan_done[dev/PATA_DEV_NUM_PER_PORT]) {
/* Probe device and set xfer mode */
bfin_ata_identify(ap, dev%PATA_DEV_NUM_PER_PORT);
bfin_ata_set_Feature_cmd(ap, dev%PATA_DEV_NUM_PER_PORT);
init_part(&sata_dev_desc[dev]);
return 0;
}
printf("PATA device#%d is not present on ATA port#%d.\n",
ap->port_no%PATA_DEV_NUM_PER_PORT,
ap->port_no/PATA_DEV_NUM_PER_PORT);
return -1;
}
int init_sata(int dev)
{
struct ata_port *ap = &port[dev];
static u8 init_done;
int res = 1;
if (init_done)
return res;
init_done = 1;
switch (dev/PATA_DEV_NUM_PER_PORT) {
case 0:
ap->ioaddr.ctl_addr = ATAPI_CONTROL;
ap->ata_mode = CONFIG_BFIN_ATA_MODE;
break;
default:
printf("Tried to scan unknown port %d.\n", dev);
return res;
}
if (ap->ata_mode < XFER_PIO_0 || ap->ata_mode > XFER_PIO_4) {
ap->ata_mode = XFER_PIO_4;
printf("DMA mode is not supported. Set to PIO mode 4.\n");
}
ap->port_no = dev;
ap->ctl_reg = 0x8; /*Default value of control reg */
res = 0;
return res;
}
/* Read up to 255 sectors
*
* Returns sectors read
*/
static u8 do_one_read(struct ata_port *ap, u64 blknr, u8 blkcnt, u16 *buffer,
uchar lba48)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
u8 sr = 0;
u8 status;
u16 err = 0;
if (!(bfin_check_status(ap) & ATA_DRDY)) {
printf("Device ata%d not ready\n", ap->port_no);
return 0;
}
/* Set up transfer */
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
write_atapi_register(base, ATA_REG_NSECT, 0);
write_atapi_register(base, ATA_REG_LBAL, (blknr >> 24) & 0xFF);
write_atapi_register(base, ATA_REG_LBAM, (blknr >> 32) & 0xFF);
write_atapi_register(base, ATA_REG_LBAH, (blknr >> 40) & 0xFF);
}
#endif
write_atapi_register(base, ATA_REG_NSECT, blkcnt);
write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
#ifdef CONFIG_LBA48
if (lba48) {
write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ_EXT);
} else
#endif
{
write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA | ((blknr >> 24) & 0xF));
write_atapi_register(base, ATA_REG_CMD, ATA_CMD_PIO_READ);
}
status = bfin_ata_busy_wait(ap, ATA_BUSY, 500000, 1);
if (status & (ATA_BUSY | ATA_ERR)) {
printf("Device %d not responding status 0x%x.\n", ap->port_no, status);
err = read_atapi_register(base, ATA_REG_ERR);
printf("Error reg = 0x%x\n", err);
return sr;
}
while (blkcnt--) {
if (bfin_wait_for_irq(ap, 500)) {
printf("ata%u irq failed\n", ap->port_no);
return sr;
}
status = bfin_check_status(ap);
if (status & ATA_ERR) {
err = read_atapi_register(base, ATA_REG_ERR);
printf("ata%u error %d\n", ap->port_no, err);
return sr;
}
bfin_irq_clear(ap);
/* Read one sector */
read_atapi_data(base, ATA_SECTOR_WORDS, buffer);
buffer += ATA_SECTOR_WORDS;
sr++;
}
return sr;
}
ulong sata_read(int dev, ulong block, ulong blkcnt, void *buff)
{
struct ata_port *ap = &port[dev];
ulong n = 0, sread;
u16 *buffer = (u16 *) buff;
u8 status = 0;
u64 blknr = (u64) block;
unsigned char lba48 = 0;
#ifdef CONFIG_LBA48
if (blknr > 0xfffffff) {
if (!sata_dev_desc[dev].lba48) {
printf("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
while (blkcnt > 0) {
if (blkcnt > 255)
sread = 255;
else
sread = blkcnt;
status = do_one_read(ap, blknr, sread, buffer, lba48);
if (status != sread) {
printf("Read failed\n");
return n;
}
blkcnt -= sread;
blknr += sread;
n += sread;
buffer += sread * ATA_SECTOR_WORDS;
}
return n;
}
ulong sata_write(int dev, ulong block, ulong blkcnt, const void *buff)
{
struct ata_port *ap = &port[dev];
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
ulong n = 0;
u16 *buffer = (u16 *) buff;
unsigned char status = 0;
u64 blknr = (u64) block;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr > 0xfffffff) {
if (!sata_dev_desc[dev].lba48) {
printf("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
bfin_dev_select(ap, dev%PATA_DEV_NUM_PER_PORT);
while (blkcnt-- > 0) {
status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
if (status & ATA_BUSY) {
printf("ata%u failed to respond\n", ap->port_no);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
write_atapi_register(base, ATA_REG_NSECT, 0);
write_atapi_register(base, ATA_REG_LBAL,
(blknr >> 24) & 0xFF);
write_atapi_register(base, ATA_REG_LBAM,
(blknr >> 32) & 0xFF);
write_atapi_register(base, ATA_REG_LBAH,
(blknr >> 40) & 0xFF);
}
#endif
write_atapi_register(base, ATA_REG_NSECT, 1);
write_atapi_register(base, ATA_REG_LBAL, (blknr >> 0) & 0xFF);
write_atapi_register(base, ATA_REG_LBAM, (blknr >> 8) & 0xFF);
write_atapi_register(base, ATA_REG_LBAH, (blknr >> 16) & 0xFF);
#ifdef CONFIG_LBA48
if (lba48) {
write_atapi_register(base, ATA_REG_DEVICE, ATA_LBA);
write_atapi_register(base, ATA_REG_CMD,
ATA_CMD_PIO_WRITE_EXT);
} else
#endif
{
write_atapi_register(base, ATA_REG_DEVICE,
ATA_LBA | ((blknr >> 24) & 0xF));
write_atapi_register(base, ATA_REG_CMD,
ATA_CMD_PIO_WRITE);
}
/*may take up to 5 sec */
status = bfin_ata_busy_wait(ap, ATA_BUSY, 50000, 0);
if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
ap->port_no, (ulong) blknr, status);
return n;
}
write_atapi_data(base, ATA_SECTOR_WORDS, buffer);
bfin_check_altstatus(ap);
udelay(1);
++n;
++blknr;
buffer += ATA_SECTOR_WORDS;
}
return n;
}
|
1001-study-uboot
|
drivers/block/pata_bfin.c
|
C
|
gpl3
| 30,932
|
/*
* (C) Copyright 2009 mGine co.
* unsik Kim <donari75@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MG_DISK_PRV_H__
#define __MG_DISK_PRV_H__
#include <mg_disk.h>
/* name for block device */
#define MG_DISK_NAME "mgd"
/* name for platform device */
#define MG_DEV_NAME "mg_disk"
#define MG_DISK_MAJ 240
#define MG_DISK_MAX_PART 16
#define MG_SECTOR_SIZE 512
#define MG_SECTOR_SIZE_MASK (512 - 1)
#define MG_SECTOR_SIZE_SHIFT (9)
#define MG_MAX_SECTS 256
/* Register offsets */
#define MG_BUFF_OFFSET 0x8000
#define MG_STORAGE_BUFFER_SIZE 0x200
#define MG_REG_OFFSET 0xC000
#define MG_REG_FEATURE (MG_REG_OFFSET + 2) /* write case */
#define MG_REG_ERROR (MG_REG_OFFSET + 2) /* read case */
#define MG_REG_SECT_CNT (MG_REG_OFFSET + 4)
#define MG_REG_SECT_NUM (MG_REG_OFFSET + 6)
#define MG_REG_CYL_LOW (MG_REG_OFFSET + 8)
#define MG_REG_CYL_HIGH (MG_REG_OFFSET + 0xA)
#define MG_REG_DRV_HEAD (MG_REG_OFFSET + 0xC)
#define MG_REG_COMMAND (MG_REG_OFFSET + 0xE) /* write case */
#define MG_REG_STATUS (MG_REG_OFFSET + 0xE) /* read case */
#define MG_REG_DRV_CTRL (MG_REG_OFFSET + 0x10)
#define MG_REG_BURST_CTRL (MG_REG_OFFSET + 0x12)
/* "Drive Select/Head Register" bit values */
#define MG_REG_HEAD_MUST_BE_ON 0xA0 /* These 2 bits are always on */
#define MG_REG_HEAD_DRIVE_MASTER (0x00 | MG_REG_HEAD_MUST_BE_ON)
#define MG_REG_HEAD_DRIVE_SLAVE (0x10 | MG_REG_HEAD_MUST_BE_ON)
#define MG_REG_HEAD_LBA_MODE (0x40 | MG_REG_HEAD_MUST_BE_ON)
/* "Device Control Register" bit values */
#define MG_REG_CTRL_INTR_ENABLE 0x0
#define MG_REG_CTRL_INTR_DISABLE (0x1 << 1)
#define MG_REG_CTRL_RESET (0x1 << 2)
#define MG_REG_CTRL_INTR_POLA_ACTIVE_HIGH 0x0
#define MG_REG_CTRL_INTR_POLA_ACTIVE_LOW (0x1 << 4)
#define MG_REG_CTRL_DPD_POLA_ACTIVE_LOW 0x0
#define MG_REG_CTRL_DPD_POLA_ACTIVE_HIGH (0x1 << 5)
#define MG_REG_CTRL_DPD_DISABLE 0x0
#define MG_REG_CTRL_DPD_ENABLE (0x1 << 6)
/* Status register bit */
/* error bit in status register */
#define MG_REG_STATUS_BIT_ERROR 0x01
/* corrected error in status register */
#define MG_REG_STATUS_BIT_CORRECTED_ERROR 0x04
/* data request bit in status register */
#define MG_REG_STATUS_BIT_DATA_REQ 0x08
/* DSC - Drive Seek Complete */
#define MG_REG_STATUS_BIT_SEEK_DONE 0x10
/* DWF - Drive Write Fault */
#define MG_REG_STATUS_BIT_WRITE_FAULT 0x20
#define MG_REG_STATUS_BIT_READY 0x40
#define MG_REG_STATUS_BIT_BUSY 0x80
/* handy status */
#define MG_STAT_READY (MG_REG_STATUS_BIT_READY | MG_REG_STATUS_BIT_SEEK_DONE)
#define MG_READY_OK(s) (((s) & (MG_STAT_READY | \
(MG_REG_STATUS_BIT_BUSY | \
MG_REG_STATUS_BIT_WRITE_FAULT | \
MG_REG_STATUS_BIT_ERROR))) == MG_STAT_READY)
/* Error register */
#define MG_REG_ERR_AMNF 0x01
#define MG_REG_ERR_ABRT 0x04
#define MG_REG_ERR_IDNF 0x10
#define MG_REG_ERR_UNC 0x40
#define MG_REG_ERR_BBK 0x80
/* error code for others */
#define MG_ERR_NONE 0
#define MG_ERR_TIMEOUT 0x100
#define MG_ERR_INIT_STAT 0x101
#define MG_ERR_TRANSLATION 0x102
#define MG_ERR_CTRL_RST 0x103
#define MG_ERR_NO_DRV_DATA 0x104
#define MG_MAX_ERRORS 16 /* Max read/write errors/sector */
#define MG_RESET_FREQ 4 /* Reset controller every 4th retry */
/* command */
#define MG_CMD_RD 0x20
#define MG_CMD_WR 0x30
#define MG_CMD_SLEEP 0x99
#define MG_CMD_WAKEUP 0xC3
#define MG_CMD_ID 0xEC
#define MG_CMD_WR_CONF 0x3C
#define MG_CMD_RD_CONF 0x40
union mg_uniwb{
u16 w;
u8 b[2];
};
/* main structure for mflash driver */
struct mg_host {
struct mg_drv_data *drv_data;
/* for future use */
};
/*
* Debugging macro and defines
*/
#undef DO_MG_DEBUG
#ifdef DO_MG_DEBUG
# define MG_DBG(fmt, args...) printf("%s:%d "fmt"\n", __func__, __LINE__,##args)
#else /* CONFIG_MG_DEBUG */
# define MG_DBG(fmt, args...) do { } while(0)
#endif /* CONFIG_MG_DEBUG */
#endif
|
1001-study-uboot
|
drivers/block/mg_disk_prv.h
|
C
|
gpl3
| 4,582
|
/*
* Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
* Author: Tor Krill <tor@excito.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This is a driver for Silicon Image sil3114 sata chip modelled on
* the ata_piix driver
*/
#include <common.h>
#include <pci.h>
#include <command.h>
#include <config.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <ide.h>
#include <libata.h>
#include "sata_sil3114.h"
/* Convert sectorsize to wordsize */
#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
/* Forwards */
u8 sil3114_spin_up (int num);
u8 sil3114_spin_down (int num);
static int sata_bus_softreset (int num);
static void sata_identify (int num, int dev);
static u8 check_power_mode (int num);
static void sata_port (struct sata_ioports *ioport);
static void set_Feature_cmd (int num, int dev);
static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
unsigned int max, u8 usealtstatus);
static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
static void msleep (int count);
static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
{
while (words--) {
__raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
}
}
static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
{
while (words--) {
*sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
}
return 0;
}
static int sata_bus_softreset (int num)
{
u8 status = 0;
port[num].dev_mask = 1;
port[num].ctl_reg = 0x08; /*Default value of control reg */
writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
udelay (10);
writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
udelay (10);
writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
/* spec mandates ">= 2ms" before checking status.
* We wait 150ms, because that was the magic delay used for
* ATAPI devices in Hale Landis's ATADRVR, for the period of time
* between when the ATA command register is written, and then
* status is checked. Because waiting for "a while" before
* checking status is fine, post SRST, we perform this magic
* delay here as well.
*/
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
}
if (status & ATA_BUSY) {
printf ("ata%u is slow to respond,plz be patient\n", num);
}
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_chk_status (&port[num].ioaddr, 0);
}
if (status & ATA_BUSY) {
printf ("ata%u failed to respond : ", num);
printf ("bus reset failed\n");
port[num].dev_mask = 0;
return 1;
}
return 0;
}
static void sata_identify (int num, int dev)
{
u8 cmd = 0, status = 0, devno = num;
u16 iobuf[ATA_SECTOR_WORDS];
u64 n_sectors = 0;
memset (iobuf, 0, sizeof (iobuf));
if (!(port[num].dev_mask & 0x01)) {
printf ("dev%d is not present on port#%d\n", dev, num);
return;
}
debug ("port=%d dev=%d\n", num, dev);
status = 0;
cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
writeb (cmd, port[num].ioaddr.command_addr);
readb (port[num].ioaddr.altstatus_addr);
udelay (10);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
if (status & ATA_ERR) {
printf ("\ndevice not responding\n");
port[num].dev_mask &= ~0x01;
return;
}
input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
debug ("Specific config: %x\n", iobuf[2]);
/* we require LBA and DMA support (bits 8 & 9 of word 49) */
if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
debug ("ata%u: no dma/lba\n", num);
}
#ifdef DEBUG
ata_dump_id (iobuf);
#endif
n_sectors = ata_id_n_sectors (iobuf);
if (n_sectors == 0) {
port[num].dev_mask &= ~0x01;
return;
}
ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
/* TODO - atm we asume harddisk ie not removable */
sata_dev_desc[devno].removable = 0;
sata_dev_desc[devno].lba = (u32) n_sectors;
debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
#ifdef CONFIG_LBA48
if (iobuf[83] & (1 << 10)) {
sata_dev_desc[devno].lba48 = 1;
} else {
sata_dev_desc[devno].lba48 = 0;
}
#endif
/* assuming HD */
sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
sata_dev_desc[devno].lun = 0; /* just to fill something in... */
}
static void set_Feature_cmd (int num, int dev)
{
u8 status = 0;
if (!(port[num].dev_mask & 0x01)) {
debug ("dev%d is not present on port#%d\n", dev, num);
return;
}
writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
writeb (0, port[num].ioaddr.lbal_addr);
writeb (0, port[num].ioaddr.lbam_addr);
writeb (0, port[num].ioaddr.lbah_addr);
writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
udelay (50);
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
if ((status & (ATA_BUSY | ATA_ERR))) {
printf ("Error : status 0x%02x\n", status);
port[num].dev_mask &= ~0x01;
}
}
u8 sil3114_spin_down (int num)
{
u8 status = 0;
debug ("Spin down disk\n");
if (!(port[num].dev_mask & 0x01)) {
debug ("Device ata%d is not present\n", num);
return 1;
}
if ((status = check_power_mode (num)) == 0x00) {
debug ("Already in standby\n");
return 0;
}
if (status == 0x01) {
printf ("Failed to check power mode on ata%d\n", num);
return 1;
}
if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
printf ("Device ata%d not ready\n", num);
return 1;
}
writeb (0x00, port[num].ioaddr.feature_addr);
writeb (0x00, port[num].ioaddr.nsect_addr);
writeb (0x00, port[num].ioaddr.lbal_addr);
writeb (0x00, port[num].ioaddr.lbam_addr);
writeb (0x00, port[num].ioaddr.lbah_addr);
writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
if ((status & (ATA_BUSY | ATA_ERR))) {
printf ("Error waiting for disk spin down: status 0x%02x\n",
status);
port[num].dev_mask &= ~0x01;
return 1;
}
return 0;
}
u8 sil3114_spin_up (int num)
{
u8 status = 0;
debug ("Spin up disk\n");
if (!(port[num].dev_mask & 0x01)) {
debug ("Device ata%d is not present\n", num);
return 1;
}
if ((status = check_power_mode (num)) != 0x00) {
if (status == 0x01) {
printf ("Failed to check power mode on ata%d\n", num);
return 1;
} else {
/* should be up and running already */
return 0;
}
}
if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
printf ("Device ata%d not ready\n", num);
return 1;
}
debug ("Stautus of device check: %d\n", status);
writeb (0x00, port[num].ioaddr.feature_addr);
writeb (0x00, port[num].ioaddr.nsect_addr);
writeb (0x00, port[num].ioaddr.lbal_addr);
writeb (0x00, port[num].ioaddr.lbam_addr);
writeb (0x00, port[num].ioaddr.lbah_addr);
writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
if ((status & (ATA_BUSY | ATA_ERR))) {
printf ("Error waiting for disk spin up: status 0x%02x\n",
status);
port[num].dev_mask &= ~0x01;
return 1;
}
/* Wait for disk to enter Active state */
do {
msleep (10);
status = check_power_mode (num);
} while ((status == 0x00) || (status == 0x80));
if (status == 0x01) {
printf ("Falied waiting for disk to spin up\n");
return 1;
}
return 0;
}
/* Return value is not the usual here
* 0x00 - Device stand by
* 0x01 - Operation failed
* 0x80 - Device idle
* 0xff - Device active
*/
static u8 check_power_mode (int num)
{
u8 status = 0;
u8 res = 0;
if (!(port[num].dev_mask & 0x01)) {
debug ("Device ata%d is not present\n", num);
return 1;
}
if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
printf ("Device ata%d not ready\n", num);
return 1;
}
writeb (0, port[num].ioaddr.feature_addr);
writeb (0, port[num].ioaddr.nsect_addr);
writeb (0, port[num].ioaddr.lbal_addr);
writeb (0, port[num].ioaddr.lbam_addr);
writeb (0, port[num].ioaddr.lbah_addr);
writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
if ((status & (ATA_BUSY | ATA_ERR))) {
printf
("Error waiting for check power mode complete : status 0x%02x\n",
status);
port[num].dev_mask &= ~0x01;
return 1;
}
res = readb (port[num].ioaddr.nsect_addr);
debug ("Check powermode: %d\n", res);
return res;
}
static void sata_port (struct sata_ioports *ioport)
{
ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
}
static u8 wait_for_irq (int num, unsigned int max)
{
u32 port = iobase[5];
switch (num) {
case 0:
port += VND_TF_CNST_CH0;
break;
case 1:
port += VND_TF_CNST_CH1;
break;
case 2:
port += VND_TF_CNST_CH2;
break;
case 3:
port += VND_TF_CNST_CH3;
break;
default:
return 1;
}
do {
if (readl (port) & VND_TF_CNST_INTST) {
break;
}
udelay (1000);
max--;
} while ((max > 0));
return (max == 0);
}
static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
unsigned int max, u8 usealtstatus)
{
u8 status;
do {
if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
break;
}
udelay (1000);
max--;
} while ((status & bits) && (max > 0));
return status;
}
static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
{
if (!usealtstatus) {
return readb (ioaddr->status_addr);
} else {
return readb (ioaddr->altstatus_addr);
}
}
static void msleep (int count)
{
int i;
for (i = 0; i < count; i++)
udelay (1000);
}
/* Read up to 255 sectors
*
* Returns sectors read
*/
static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
uchar lba48)
{
u8 sr = 0;
u8 status;
u64 blknr = (u64) block;
if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
printf ("Device ata%d not ready\n", device);
return 0;
}
/* Set up transfer */
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
writeb (0, port[device].ioaddr.nsect_addr);
writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
}
#endif
writeb (blkcnt, port[device].ioaddr.nsect_addr);
writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
writeb (ATA_LBA, port[device].ioaddr.device_addr);
writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
} else
#endif
{
writeb (ATA_LBA | ((blknr >> 24) & 0xF),
port[device].ioaddr.device_addr);
writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
}
status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
if (status & ATA_BUSY) {
u8 err = 0;
printf ("Device %d not responding status %d\n", device, status);
err = readb (port[device].ioaddr.error_addr);
printf ("Error reg = 0x%x\n", err);
return (sr);
}
while (blkcnt--) {
if (wait_for_irq (device, 500)) {
printf ("ata%u irq failed\n", device);
return sr;
}
status = sata_chk_status (&port[device].ioaddr, 0);
if (status & ATA_ERR) {
printf ("ata%u error %d\n", device,
readb (port[device].ioaddr.error_addr));
return sr;
}
/* Read one sector */
input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
buff += ATA_SECTOR_WORDS;
sr++;
}
return sr;
}
ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
{
ulong n = 0, sread;
u16 *buffer = (u16 *) buff;
u8 status = 0;
u64 blknr = (u64) block;
unsigned char lba48 = 0;
#ifdef CONFIG_LBA48
if (blknr > 0xfffffff) {
if (!sata_dev_desc[device].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
while (blkcnt > 0) {
if (blkcnt > 255) {
sread = 255;
} else {
sread = blkcnt;
}
status = do_one_read (device, blknr, sread, buffer, lba48);
if (status != sread) {
printf ("Read failed\n");
return n;
}
blkcnt -= sread;
blknr += sread;
n += sread;
buffer += sread * ATA_SECTOR_WORDS;
}
return n;
}
ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
{
ulong n = 0;
u16 *buffer = (u16 *) buff;
unsigned char status = 0, num = 0;
u64 blknr = (u64) block;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr > 0xfffffff) {
if (!sata_dev_desc[device].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
/*Port Number */
num = device;
while (blkcnt-- > 0) {
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", port[num].port_no);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
writeb (0, port[num].ioaddr.nsect_addr);
writeb ((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
writeb ((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
writeb ((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
writeb (1, port[num].ioaddr.nsect_addr);
writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
writeb (ATA_LBA, port[num].ioaddr.device_addr);
writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
} else
#endif
{
writeb (ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
}
msleep (50);
/*may take up to 4 sec */
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
return (n);
}
output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
readb (port[num].ioaddr.altstatus_addr);
udelay (50);
++n;
++blknr;
buffer += ATA_SECTOR_WORDS;
}
return n;
}
/* Driver implementation */
static u8 sil_get_device_cache_line (pci_dev_t pdev)
{
u8 cache_line = 0;
pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
return cache_line;
}
int init_sata (int dev)
{
static u8 init_done = 0;
static int res = 1;
pci_dev_t devno;
u8 cls = 0;
u16 cmd = 0;
u32 sconf = 0;
if (init_done) {
return res;
}
init_done = 1;
if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
res = 1;
return res;
}
/* Read out all BARs, even though we only use MMIO from BAR5 */
pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
(iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
(iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
printf ("Error no base addr for SATA controller\n");
res = 1;
return res;
}
/* mask off unused bits */
iobase[0] &= 0xfffffffc;
iobase[1] &= 0xfffffff8;
iobase[2] &= 0xfffffffc;
iobase[3] &= 0xfffffff8;
iobase[4] &= 0xfffffff0;
iobase[5] &= 0xfffffc00;
/* from sata_sil in Linux kernel */
cls = sil_get_device_cache_line (devno);
if (cls) {
cls >>= 3;
cls++; /* cls = (line_size/8)+1 */
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
} else {
printf ("Cache line not set. Driver may not function\n");
}
/* Enable operation */
pci_read_config_word (devno, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
pci_write_config_word (devno, PCI_COMMAND, cmd);
/* Disable interrupt usage */
pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
res = 0;
return res;
}
/* Check if device is connected to port */
int sata_bus_probe (int portno)
{
u32 port = iobase[5];
u32 val;
switch (portno) {
case 0:
port += VND_SSTATUS_CH0;
break;
case 1:
port += VND_SSTATUS_CH1;
break;
case 2:
port += VND_SSTATUS_CH2;
break;
case 3:
port += VND_SSTATUS_CH3;
break;
default:
return 0;
}
val = readl (port);
if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
return 1;
} else {
return 0;
}
}
int sata_phy_reset (int portno)
{
u32 port = iobase[5];
u32 val;
switch (portno) {
case 0:
port += VND_SCONTROL_CH0;
break;
case 1:
port += VND_SCONTROL_CH1;
break;
case 2:
port += VND_SCONTROL_CH2;
break;
case 3:
port += VND_SCONTROL_CH3;
break;
default:
return 0;
}
val = readl (port);
writel (val | SATA_SC_DET_RST, port);
msleep (150);
writel (val & ~SATA_SC_DET_RST, port);
return 0;
}
int scan_sata (int dev)
{
/* A bit brain dead, but the code has a legacy */
switch (dev) {
case 0:
port[0].port_no = 0;
port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
(iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
break;
#if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
case 1:
port[1].port_no = 0;
port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
(iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
break;
#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
case 2:
port[2].port_no = 0;
port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
(iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
break;
#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
case 3:
port[3].port_no = 0;
port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
(iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
break;
#endif
default:
printf ("Tried to scan unknown port: ata%d\n", dev);
return 1;
}
/* Initialize other registers */
sata_port (&port[dev].ioaddr);
/* Check for attached device */
if (!sata_bus_probe (dev)) {
port[dev].port_state = 0;
debug ("SATA#%d port is not present\n", dev);
} else {
debug ("SATA#%d port is present\n", dev);
if (sata_bus_softreset (dev)) {
/* soft reset failed, try a hard one */
sata_phy_reset (dev);
if (sata_bus_softreset (dev)) {
port[dev].port_state = 0;
} else {
port[dev].port_state = 1;
}
} else {
port[dev].port_state = 1;
}
}
if (port[dev].port_state == 1) {
/* Probe device and set xfer mode */
sata_identify (dev, 0);
set_Feature_cmd (dev, 0);
}
return 0;
}
|
1001-study-uboot
|
drivers/block/sata_sil3114.c
|
C
|
gpl3
| 21,379
|
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Author: Tang Yuantian <b29983@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <command.h>
#include <asm/byteorder.h>
#include <malloc.h>
#include <asm/io.h>
#include <fis.h>
#include <libata.h>
#include "sata_sil.h"
/* Convert sectorsize to wordsize */
#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
#define mdelay(n) udelay((n)*1000)
#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
static struct sata_info sata_info;
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
{}
};
static void sil_sata_dump_fis(struct sata_fis_d2h *s)
{
printf("Status FIS dump:\n");
printf("fis_type: %02x\n", s->fis_type);
printf("pm_port_i: %02x\n", s->pm_port_i);
printf("status: %02x\n", s->status);
printf("error: %02x\n", s->error);
printf("lba_low: %02x\n", s->lba_low);
printf("lba_mid: %02x\n", s->lba_mid);
printf("lba_high: %02x\n", s->lba_high);
printf("device: %02x\n", s->device);
printf("lba_low_exp: %02x\n", s->lba_low_exp);
printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
printf("lba_high_exp: %02x\n", s->lba_high_exp);
printf("res1: %02x\n", s->res1);
printf("sector_count: %02x\n", s->sector_count);
printf("sector_count_exp: %02x\n", s->sector_count_exp);
}
static const char *sata_spd_string(unsigned int speed)
{
static const char * const spd_str[] = {
"1.5 Gbps",
"3.0 Gbps",
"6.0 Gbps",
};
if ((speed - 1) > 2)
return "<unknown>";
return spd_str[speed - 1];
}
static u32 ata_wait_register(void *reg, u32 mask,
u32 val, int timeout_msec)
{
u32 tmp;
tmp = readl(reg);
while ((tmp & mask) == val && timeout_msec > 0) {
mdelay(1);
timeout_msec--;
tmp = readl(reg);
}
return tmp;
}
static void sil_config_port(void *port)
{
/* configure IRQ WoC */
writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
/* zero error counters. */
writew(0x8000, port + PORT_DECODE_ERR_THRESH);
writew(0x8000, port + PORT_CRC_ERR_THRESH);
writew(0x8000, port + PORT_HSHK_ERR_THRESH);
writew(0x0000, port + PORT_DECODE_ERR_CNT);
writew(0x0000, port + PORT_CRC_ERR_CNT);
writew(0x0000, port + PORT_HSHK_ERR_CNT);
/* always use 64bit activation */
writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
/* clear port multiplier enable and resume bits */
writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
}
static int sil_init_port(void *port)
{
u32 tmp;
writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
ata_wait_register(port + PORT_CTRL_STAT,
PORT_CS_INIT, PORT_CS_INIT, 100);
tmp = ata_wait_register(port + PORT_CTRL_STAT,
PORT_CS_RDY, 0, 100);
if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
return 1;
return 0;
}
static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
void *port = sata->port;
struct sil_prb *prb;
int i;
u32 *src, *dst;
prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
src = (u32 *)&prb->fis;
dst = (u32 *)fis;
for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
*dst++ = readl(src++);
}
static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
void *port = sata->port;
u64 paddr = virt_to_bus(sata->devno, pcmd);
u32 irq_mask, irq_stat;
int rc;
writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
/* better to add momery barrior here */
writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
0, 10000);
/* clear IRQs */
writel(irq_mask, port + PORT_IRQ_STAT);
irq_stat >>= PORT_IRQ_RAW_SHIFT;
if (irq_stat & PORT_IRQ_COMPLETE)
rc = 0;
else {
/* force port into known state */
sil_init_port(port);
if (irq_stat & PORT_IRQ_ERROR)
rc = 1; /* error */
else
rc = 2; /* busy */
}
return rc;
}
static int sil_cmd_set_feature(int dev)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sil_cmd_block cmdb, *pcmd = &cmdb;
struct sata_fis_d2h fis;
u8 udma_cap;
int ret;
memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
pcmd->prb.fis.pm_port_c = (1 << 7);
pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
pcmd->prb.fis.features = SETFEATURES_XFER;
/* First check the device capablity */
udma_cap = (u8)(sata->udma & 0xff);
debug("udma_cap %02x\n", udma_cap);
if (udma_cap == ATA_UDMA6)
pcmd->prb.fis.sector_count = XFER_UDMA_6;
if (udma_cap == ATA_UDMA5)
pcmd->prb.fis.sector_count = XFER_UDMA_5;
if (udma_cap == ATA_UDMA4)
pcmd->prb.fis.sector_count = XFER_UDMA_4;
if (udma_cap == ATA_UDMA3)
pcmd->prb.fis.sector_count = XFER_UDMA_3;
ret = sil_exec_cmd(dev, pcmd, 0);
if (ret) {
sil_read_fis(dev, 0, &fis);
printf("Err: exe cmd(0x%x).\n",
readl(sata->port + PORT_SERROR));
sil_sata_dump_fis(&fis);
return 1;
}
return 0;
}
static int sil_cmd_identify_device(int dev, u16 *id)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sil_cmd_block cmdb, *pcmd = &cmdb;
struct sata_fis_d2h fis;
int ret;
memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
pcmd->prb.fis.pm_port_c = (1 << 7);
pcmd->prb.fis.command = ATA_CMD_ID_ATA;
pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
pcmd->sge.flags = cpu_to_le32(SGE_TRM);
ret = sil_exec_cmd(dev, pcmd, 0);
if (ret) {
sil_read_fis(dev, 0, &fis);
printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
sil_sata_dump_fis(&fis);
return 1;
}
ata_swap_buf_le16(id, ATA_ID_WORDS);
return 0;
}
static int sil_cmd_soft_reset(int dev)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;
struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sata_fis_d2h fis;
void *port = sata->port;
int ret;
/* put the port into known state */
if (sil_init_port(port)) {
printf("SRST: port %d not ready\n", dev);
return 1;
}
memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
pcmd->prb.fis.pm_port_c = 0xf;
ret = sil_exec_cmd(dev, &cmdb, 0);
if (ret) {
sil_read_fis(dev, 0, &fis);
printf("SRST cmd error.\n");
sil_sata_dump_fis(&fis);
return 1;
}
return 0;
}
static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
u8 *buffer, int is_write)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sil_cmd_block cmdb, *pcmd = &cmdb;
struct sata_fis_d2h fis;
u64 block;
int ret;
block = (u64)start;
memset(pcmd, 0, sizeof(struct sil_cmd_block));
pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
pcmd->prb.fis.pm_port_c = (1 << 7);
if (is_write) {
pcmd->prb.fis.command = ATA_CMD_WRITE;
pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
} else {
pcmd->prb.fis.command = ATA_CMD_READ;
pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
}
pcmd->prb.fis.device = ATA_LBA;
pcmd->prb.fis.device |= (block >> 24) & 0xf;
pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
pcmd->prb.fis.lba_low = block & 0xff;
pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
pcmd->sge.flags = cpu_to_le32(SGE_TRM);
ret = sil_exec_cmd(dev, pcmd, 0);
if (ret) {
sil_read_fis(dev, 0, &fis);
printf("Err: rw cmd(0x%08x).\n",
readl(sata->port + PORT_SERROR));
sil_sata_dump_fis(&fis);
return 1;
}
return blkcnt;
}
static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
u8 *buffer, int is_write)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
struct sil_cmd_block cmdb, *pcmd = &cmdb;
struct sata_fis_d2h fis;
u64 block;
int ret;
block = (u64)start;
memset(pcmd, 0, sizeof(struct sil_cmd_block));
pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
pcmd->prb.fis.pm_port_c = (1 << 7);
if (is_write) {
pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
} else {
pcmd->prb.fis.command = ATA_CMD_READ_EXT;
pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
}
pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
pcmd->prb.fis.lba_low = block & 0xff;
pcmd->prb.fis.device = ATA_LBA;
pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
pcmd->prb.fis.sector_count = blkcnt & 0xff;
pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
pcmd->sge.flags = cpu_to_le32(SGE_TRM);
ret = sil_exec_cmd(dev, pcmd, 0);
if (ret) {
sil_read_fis(dev, 0, &fis);
printf("Err: rw ext cmd(0x%08x).\n",
readl(sata->port + PORT_SERROR));
sil_sata_dump_fis(&fis);
return 1;
}
return blkcnt;
}
ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
start = blknr;
blks = blkcnt;
addr = (u8 *)buffer;
max_blks = ATA_MAX_SECTORS;
do {
if (blks > max_blks) {
sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
start += max_blks;
blks -= max_blks;
addr += ATA_SECT_SIZE * max_blks;
} else {
sil_sata_rw_cmd(dev, start, blks, addr, is_write);
start += blks;
blks = 0;
addr += ATA_SECT_SIZE * blks;
}
} while (blks != 0);
return blkcnt;
}
ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
start = blknr;
blks = blkcnt;
addr = (u8 *)buffer;
max_blks = ATA_MAX_SECTORS_LBA48;
do {
if (blks > max_blks) {
sil_sata_rw_cmd_ext(dev, start, max_blks,
addr, is_write);
start += max_blks;
blks -= max_blks;
addr += ATA_SECT_SIZE * max_blks;
} else {
sil_sata_rw_cmd_ext(dev, start, blks,
addr, is_write);
start += blks;
blks = 0;
addr += ATA_SECT_SIZE * blks;
}
} while (blks != 0);
return blkcnt;
}
void sil_sata_cmd_flush_cache(int dev)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;
memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
pcmd->prb.fis.pm_port_c = (1 << 7);
pcmd->prb.fis.command = ATA_CMD_FLUSH;
sil_exec_cmd(dev, pcmd, 0);
}
void sil_sata_cmd_flush_cache_ext(int dev)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;
memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
pcmd->prb.fis.pm_port_c = (1 << 7);
pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
sil_exec_cmd(dev, pcmd, 0);
}
static void sil_sata_init_wcache(int dev, u16 *id)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
sata->wcache = 1;
if (ata_id_has_flush(id))
sata->flush = 1;
if (ata_id_has_flush_ext(id))
sata->flush_ext = 1;
}
static int sil_sata_get_wcache(int dev)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
return sata->wcache;
}
static int sil_sata_get_flush(int dev)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
return sata->flush;
}
static int sil_sata_get_flush_ext(int dev)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
return sata->flush_ext;
}
/*
* SATA interface between low level driver and command layer
*/
ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
ulong rc;
if (sata->lba48)
rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
else
rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
return rc;
}
/*
* SATA interface between low level driver and command layer
*/
ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
ulong rc;
if (sata->lba48) {
rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
sil_sata_cmd_flush_cache_ext(dev);
} else {
rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
sil_sata_cmd_flush_cache(dev);
}
return rc;
}
/*
* SATA interface between low level driver and command layer
*/
int init_sata(int dev)
{
static int init_done, idx;
pci_dev_t devno;
u16 word;
if (init_done == 1 && dev < sata_info.maxport)
return 1;
init_done = 1;
/* Find PCI device(s) */
devno = pci_find_devices(supported, idx++);
if (devno == -1)
return 1;
pci_read_config_word(devno, PCI_DEVICE_ID, &word);
/* get the port count */
word &= 0xf;
sata_info.portbase = sata_info.maxport;
sata_info.maxport = sata_info.portbase + word;
sata_info.devno = devno;
/* Read out all BARs */
sata_info.iobase[0] = (ulong)pci_map_bar(devno,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
sata_info.iobase[1] = (ulong)pci_map_bar(devno,
PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
sata_info.iobase[2] = (ulong)pci_map_bar(devno,
PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
/* mask out the unused bits */
sata_info.iobase[0] &= 0xffffff80;
sata_info.iobase[1] &= 0xfffffc00;
sata_info.iobase[2] &= 0xffffff80;
/* Enable Bus Mastering and memory region */
pci_write_config_word(devno, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check if mem accesses and Bus Mastering are enabled. */
pci_read_config_word(devno, PCI_COMMAND, &word);
if (!(word & PCI_COMMAND_MEMORY) ||
(!(word & PCI_COMMAND_MASTER))) {
printf("Error: Can not enable MEM access or Bus Mastering.\n");
debug("PCI command: %04x\n", word);
return 1;
}
/* GPIO off */
writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
/* clear global reset & mask interrupts during initialization */
writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
return 0;
}
/*
* SATA interface between low level driver and command layer
*/
int scan_sata(int dev)
{
unsigned char serial[ATA_ID_SERNO_LEN + 1];
unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
unsigned char product[ATA_ID_PROD_LEN + 1];
struct sil_sata *sata;
void *port;
int cnt;
u16 *id;
u32 tmp;
if (dev >= sata_info.maxport) {
printf("SATA#%d is not present\n", dev);
return 1;
}
printf("SATA#%d\n", dev);
port = (void *)sata_info.iobase[1] +
PORT_REGS_SIZE * (dev - sata_info.portbase);
/* Initial PHY setting */
writel(0x20c, port + PORT_PHY_CFG);
/* clear port RST */
tmp = readl(port + PORT_CTRL_STAT);
if (tmp & PORT_CS_PORT_RST) {
writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
tmp = ata_wait_register(port + PORT_CTRL_STAT,
PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
if (tmp & PORT_CS_PORT_RST)
printf("Err: Failed to clear port RST\n");
}
/* Check if device is present */
for (cnt = 0; cnt < 100; cnt++) {
tmp = readl(port + PORT_SSTATUS);
if ((tmp & 0xF) == 0x3)
break;
mdelay(1);
}
tmp = readl(port + PORT_SSTATUS);
if ((tmp & 0xf) != 0x3) {
printf(" (No RDY)\n");
return 1;
}
/* Wait for port ready */
tmp = ata_wait_register(port + PORT_CTRL_STAT,
PORT_CS_RDY, PORT_CS_RDY, 100);
if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
printf("%d port not ready.\n", dev);
return 1;
}
/* configure port */
sil_config_port(port);
/* Reset port */
writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
readl(port + PORT_CTRL_STAT);
tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
PORT_CS_DEV_RST, 100);
if (tmp & PORT_CS_DEV_RST) {
printf("%d port reset failed.\n", dev);
return 1;
}
sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
if (!sata) {
printf("%d no memory.\n", dev);
return 1;
}
memset((void *)sata, 0, sizeof(struct sil_sata));
/* turn on port interrupt */
tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
tmp |= (1 << (dev - sata_info.portbase));
writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));
/* Save the private struct to block device struct */
sata_dev_desc[dev].priv = (void *)sata;
sata->port = port;
sata->devno = sata_info.devno;
sprintf(sata->name, "SATA#%d", dev);
sil_cmd_soft_reset(dev);
tmp = readl(port + PORT_SSTATUS);
tmp = (tmp >> 4) & 0xf;
printf(" (%s)\n", sata_spd_string(tmp));
id = (u16 *)malloc(ATA_ID_WORDS * 2);
if (!id) {
printf("Id malloc failed\n");
free((void *)sata);
return 1;
}
sil_cmd_identify_device(dev, id);
#ifdef CONFIG_LBA48
/* Check if support LBA48 */
if (ata_id_has_lba48(id)) {
sata_dev_desc[dev].lba48 = 1;
sata->lba48 = 1;
debug("Device supports LBA48\n");
} else
debug("Device supports LBA28\n");
#endif
/* Serial number */
ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
/* Firmware version */
ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
/* Product model */
ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
/* Totoal sectors */
sata_dev_desc[dev].lba = ata_id_n_sectors(id);
sil_sata_init_wcache(dev, id);
sil_cmd_set_feature(dev);
#ifdef DEBUG
sil_cmd_identify_device(dev, id);
ata_dump_id(id);
#endif
free((void *)id);
return 0;
}
|
1001-study-uboot
|
drivers/block/sata_sil.c
|
C
|
gpl3
| 18,611
|
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <asm/io.h>
#if defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
#elif defined(CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
#endif
/* SATA port registers */
struct mvsata_port_registers {
u32 reserved0[10];
u32 edma_cmd;
u32 reserved1[181];
/* offset 0x300 : ATA Interface registers */
u32 sstatus;
u32 serror;
u32 scontrol;
u32 ltmode;
u32 phymode3;
u32 phymode4;
u32 reserved2[5];
u32 phymode1;
u32 phymode2;
u32 bist_cr;
u32 bist_dw1;
u32 bist_dw2;
u32 serrorintrmask;
};
/*
* Sanity checks:
* - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
* - for ide_preinit to make sense, we need at least one of
* CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE0_OFFSET;
* - for inde_preinit to be called, we need CONFIG_IDE_PREINIT.
* Fail with an explanation message if these conditions are not met.
* This is particularly important for CONFIG_IDE_PREINIT, because
* its lack would not cause a build error.
*/
#if !defined(CONFIG_SYS_ATA_BASE_ADDR)
#error CONFIG_SYS_ATA_BASE_ADDR must be defined
#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
&& !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
must be defined
#elif !defined(CONFIG_IDE_PREINIT)
#error CONFIG_IDE_PREINIT must be defined
#endif
/*
* Masks and values for SControl DETection and Interface Power Management,
* and for SStatus DETection.
*/
#define MVSATA_EDMA_CMD_ATA_RST 0x00000004
#define MVSATA_SCONTROL_DET_MASK 0x0000000F
#define MVSATA_SCONTROL_DET_NONE 0x00000000
#define MVSATA_SCONTROL_DET_INIT 0x00000001
#define MVSATA_SCONTROL_IPM_MASK 0x00000F00
#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED 0x00000300
#define MVSATA_SCONTROL_MASK \
(MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
#define MVSATA_PORT_INIT \
(MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
#define MVSATA_PORT_USE \
(MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
#define MVSATA_SSTATUS_DET_MASK 0x0000000F
#define MVSATA_SSTATUS_DET_DEVCOMM 0x00000003
/*
* Status codes to return to client callers. Currently, callers ignore
* exact value and only care for zero or nonzero, so no need to make this
* public, it is only #define'd for clarity.
* If/when standard negative codes are implemented in U-boot, then these
* #defines should be moved to, or replaced by ones from, the common list
* of status codes.
*/
#define MVSATA_STATUS_OK 0
#define MVSATA_STATUS_TIMEOUT -1
/*
* Initialize one MVSATAHC port: set SControl's IPM to "always active"
* and DET to "reset", then wait for SStatus's DET to become "device and
* comm ok" (or time out after 50 us if no device), then set SControl's
* DET back to "no action".
*/
static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
{
u32 control;
u32 status;
u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
/* Hard reset */
writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
udelay(25); /* taken from original marvell port */
writel(0, &port->edma_cmd);
/* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
control = readl(&port->scontrol);
control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
writel(control, &port->scontrol);
/* Toggle control DET back to 0 (normal operation) */
control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
writel(control, &port->scontrol);
/* wait for status DET to become 3 (device and communication OK) */
while (--timeleft) {
status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
if (status == MVSATA_SSTATUS_DET_DEVCOMM)
break;
udelay(1);
}
/* return success or time-out error depending on time left */
if (!timeleft)
return MVSATA_STATUS_TIMEOUT;
return MVSATA_STATUS_OK;
}
/*
* ide_preinit() will be called by ide_init in cmd_ide.c and will
* reset the MVSTATHC ports needed by the board.
*/
int ide_preinit(void)
{
int ret = MVSATA_STATUS_TIMEOUT;
int status;
/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
status = mvsata_ide_initialize_port(
(struct mvsata_port_registers *)
(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
if (status == MVSATA_STATUS_OK)
ret = MVSATA_STATUS_OK;
#endif
/* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
#if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
status = mvsata_ide_initialize_port(
(struct mvsata_port_registers *)
(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
if (status == MVSATA_STATUS_OK)
ret = MVSATA_STATUS_OK;
#endif
/* Return success if at least one port initialization succeeded */
return ret;
}
|
1001-study-uboot
|
drivers/block/mvsata_ide.c
|
C
|
gpl3
| 5,615
|
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006.
* Author: Jason Jin<Jason.jin@freescale.com>
* Zhang Wei<wei.zhang@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* with the reference on libata and ahci drvier in kernel
*
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <scsi.h>
#include <ata.h>
#include <linux/ctype.h>
#include <ahci.h>
struct ahci_probe_ent *probe_ent = NULL;
hd_driveid_t *ataid[AHCI_MAX_PORTS];
#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
static inline u32 ahci_port_base(u32 base, u32 port)
{
return base + 0x100 + (port * 0x80);
}
static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
unsigned int port_idx)
{
base = ahci_port_base(base, port_idx);
port->cmd_addr = base;
port->scr_addr = base + PORT_SCR;
}
#define msleep(a) udelay(a * 1000)
#define ssleep(a) msleep(a * 1000)
static int waiting_for_cmd_completed(volatile u8 *offset,
int timeout_msec,
u32 sign)
{
int i;
u32 status;
for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
msleep(1);
return (i < timeout_msec) ? 0 : -1;
}
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
pci_dev_t pdev = probe_ent->dev;
u16 tmp16;
unsigned short vendor;
#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
u32 tmp, cap_save;
int i, j;
volatile u8 *port_mmio;
cap_save = readl(mmio + HOST_CAP);
cap_save &= ((1 << 28) | (1 << 17));
cap_save |= (1 << 27);
/* global controller reset */
tmp = readl(mmio + HOST_CTL);
if ((tmp & HOST_RESET) == 0)
writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
/* reset must complete within 1 second, or
* the hardware should be considered fried.
*/
ssleep(1);
tmp = readl(mmio + HOST_CTL);
if (tmp & HOST_RESET) {
debug("controller reset failed (0x%x)\n", tmp);
return -1;
}
writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
writel(cap_save, mmio + HOST_CAP);
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
#ifndef CONFIG_SCSI_AHCI_PLAT
pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
if (vendor == PCI_VENDOR_ID_INTEL) {
u16 tmp16;
pci_read_config_word(pdev, 0x92, &tmp16);
tmp16 |= 0xf;
pci_write_config_word(pdev, 0x92, tmp16);
}
#endif
probe_ent->cap = readl(mmio + HOST_CAP);
probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
debug("cap 0x%x port_map 0x%x n_ports %d\n",
probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
for (i = 0; i < probe_ent->n_ports; i++) {
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
port_mmio = (u8 *) probe_ent->port[i].port_mmio;
ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
/* make sure port is not active */
tmp = readl(port_mmio + PORT_CMD);
if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
PORT_CMD_FIS_RX | PORT_CMD_START)) {
tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
PORT_CMD_FIS_RX | PORT_CMD_START);
writel_with_flush(tmp, port_mmio + PORT_CMD);
/* spec says 500 msecs for each bit, so
* this is slightly incorrect.
*/
msleep(500);
}
writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
j = 0;
while (j < 100) {
msleep(10);
tmp = readl(port_mmio + PORT_SCR_STAT);
if ((tmp & 0xf) == 0x3)
break;
j++;
}
tmp = readl(port_mmio + PORT_SCR_ERR);
debug("PORT_SCR_ERR 0x%x\n", tmp);
writel(tmp, port_mmio + PORT_SCR_ERR);
/* ack any pending irq events for this port */
tmp = readl(port_mmio + PORT_IRQ_STAT);
debug("PORT_IRQ_STAT 0x%x\n", tmp);
if (tmp)
writel(tmp, port_mmio + PORT_IRQ_STAT);
writel(1 << i, mmio + HOST_IRQ_STAT);
/* set irq mask (enables interrupts) */
writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
/*register linkup ports */
tmp = readl(port_mmio + PORT_SCR_STAT);
debug("Port %d status: 0x%x\n", i, tmp);
if ((tmp & 0xf) == 0x03)
probe_ent->link_port_map |= (0x01 << i);
}
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
tmp = readl(mmio + HOST_CTL);
debug("HOST_CTL 0x%x\n", tmp);
#ifndef CONFIG_SCSI_AHCI_PLAT
pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
tmp |= PCI_COMMAND_MASTER;
pci_write_config_word(pdev, PCI_COMMAND, tmp16);
#endif
return 0;
}
static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
#ifndef CONFIG_SCSI_AHCI_PLAT
pci_dev_t pdev = probe_ent->dev;
u16 cc;
#endif
volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
u32 vers, cap, impl, speed;
const char *speed_s;
const char *scc_s;
vers = readl(mmio + HOST_VERSION);
cap = probe_ent->cap;
impl = probe_ent->port_map;
speed = (cap >> 20) & 0xf;
if (speed == 1)
speed_s = "1.5";
else if (speed == 2)
speed_s = "3";
else
speed_s = "?";
#ifdef CONFIG_SCSI_AHCI_PLAT
scc_s = "SATA";
#else
pci_read_config_word(pdev, 0x0a, &cc);
if (cc == 0x0101)
scc_s = "IDE";
else if (cc == 0x0106)
scc_s = "SATA";
else if (cc == 0x0104)
scc_s = "RAID";
else
scc_s = "unknown";
#endif
printf("AHCI %02x%02x.%02x%02x "
"%u slots %u ports %s Gbps 0x%x impl %s mode\n",
(vers >> 24) & 0xff,
(vers >> 16) & 0xff,
(vers >> 8) & 0xff,
vers & 0xff,
((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
printf("flags: "
"%s%s%s%s%s%s"
"%s%s%s%s%s%s%s\n",
cap & (1 << 31) ? "64bit " : "",
cap & (1 << 30) ? "ncq " : "",
cap & (1 << 28) ? "ilck " : "",
cap & (1 << 27) ? "stag " : "",
cap & (1 << 26) ? "pm " : "",
cap & (1 << 25) ? "led " : "",
cap & (1 << 24) ? "clo " : "",
cap & (1 << 19) ? "nz " : "",
cap & (1 << 18) ? "only " : "",
cap & (1 << 17) ? "pmp " : "",
cap & (1 << 15) ? "pio " : "",
cap & (1 << 14) ? "slum " : "",
cap & (1 << 13) ? "part " : "");
}
#ifndef CONFIG_SCSI_AHCI_PLAT
static int ahci_init_one(pci_dev_t pdev)
{
u16 vendor;
int rc;
memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
probe_ent = malloc(sizeof(struct ahci_probe_ent));
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
probe_ent->dev = pdev;
probe_ent->host_flags = ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
| ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
| ATA_FLAG_NO_ATAPI;
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR,
PCI_REGION_MEM);
/* Take from kernel:
* JMicron-specific fixup:
* make sure we're in AHCI mode
*/
pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
if (vendor == 0x197b)
pci_write_config_byte(pdev, 0x41, 0xa1);
/* initialize adapter */
rc = ahci_host_init(probe_ent);
if (rc)
goto err_out;
ahci_print_info(probe_ent);
return 0;
err_out:
return rc;
}
#endif
#define MAX_DATA_BYTE_COUNT (4*1024*1024)
static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
u32 sg_count;
int i;
sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
if (sg_count > AHCI_MAX_SG) {
printf("Error:Too much sg!\n");
return -1;
}
for (i = 0; i < sg_count; i++) {
ahci_sg->addr =
cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
ahci_sg->addr_hi = 0;
ahci_sg->flags_size = cpu_to_le32(0x3fffff &
(buf_len < MAX_DATA_BYTE_COUNT
? (buf_len - 1)
: (MAX_DATA_BYTE_COUNT - 1)));
ahci_sg++;
buf_len -= MAX_DATA_BYTE_COUNT;
}
return sg_count;
}
static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
{
pp->cmd_slot->opts = cpu_to_le32(opts);
pp->cmd_slot->status = 0;
pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
pp->cmd_slot->tbl_addr_hi = 0;
}
static void ahci_set_feature(u8 port)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
u32 cmd_fis_len = 5; /* five dwords */
u8 fis[20];
/*set feature */
memset(fis, 0, 20);
fis[0] = 0x27;
fis[1] = 1 << 7;
fis[2] = ATA_CMD_SETF;
fis[3] = SETFEATURES_XFER;
fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
ahci_fill_cmd_slot(pp, cmd_fis_len);
writel(1, port_mmio + PORT_CMD_ISSUE);
readl(port_mmio + PORT_CMD_ISSUE);
if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
printf("set feature error!\n");
}
}
static int ahci_port_start(u8 port)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
u32 port_status;
u32 mem;
debug("Enter start port: %d\n", port);
port_status = readl(port_mmio + PORT_SCR_STAT);
debug("Port %d status: %x\n", port, port_status);
if ((port_status & 0xf) != 0x03) {
printf("No Link on this port!\n");
return -1;
}
mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
if (!mem) {
free(pp);
printf("No mem for table!\n");
return -ENOMEM;
}
mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
/*
* First item in chunk of DMA memory: 32-slot command table,
* 32 bytes each in size
*/
pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
debug("cmd_slot = %p\n", pp->cmd_slot);
mem += (AHCI_CMD_SLOT_SZ + 224);
/*
* Second item: Received-FIS area
*/
pp->rx_fis = mem;
mem += AHCI_RX_FIS_SZ;
/*
* Third item: data area for storing a single command
* and its scatter-gather table
*/
pp->cmd_tbl = mem;
debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
mem += AHCI_CMD_TBL_HDR;
pp->cmd_tbl_sg = (struct ahci_sg *)mem;
writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
PORT_CMD_START, port_mmio + PORT_CMD);
debug("Exit start port %d\n", port);
return 0;
}
static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
int buf_len)
{
struct ahci_ioports *pp = &(probe_ent->port[port]);
volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
u32 opts;
u32 port_status;
int sg_count;
debug("Enter get_ahci_device_data: for port %d\n", port);
if (port > probe_ent->n_ports) {
printf("Invaild port number %d\n", port);
return -1;
}
port_status = readl(port_mmio + PORT_SCR_STAT);
if ((port_status & 0xf) != 0x03) {
debug("No Link on port %d!\n", port);
return -1;
}
memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
sg_count = ahci_fill_sg(port, buf, buf_len);
opts = (fis_len >> 2) | (sg_count << 16);
ahci_fill_cmd_slot(pp, opts);
writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
printf("timeout exit!\n");
return -1;
}
debug("get_ahci_device_data: %d byte transferred.\n",
pp->cmd_slot->status);
return 0;
}
static char *ata_id_strcpy(u16 *target, u16 *src, int len)
{
int i;
for (i = 0; i < len / 2; i++)
target[i] = swab16(src[i]);
return (char *)target;
}
static void dump_ataid(hd_driveid_t *ataid)
{
debug("(49)ataid->capability = 0x%x\n", ataid->capability);
debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
}
/*
* SCSI INQUIRY command operation.
*/
static int ata_scsiop_inquiry(ccb *pccb)
{
u8 hdr[] = {
0,
0,
0x5, /* claim SPC-3 version compatibility */
2,
95 - 4,
};
u8 fis[20];
u8 *tmpid;
u8 port;
/* Clean ccb data buffer */
memset(pccb->pdata, 0, pccb->datalen);
memcpy(pccb->pdata, hdr, sizeof(hdr));
if (pccb->datalen <= 35)
return 0;
memset(fis, 0, 20);
/* Construct the FIS */
fis[0] = 0x27; /* Host to device FIS. */
fis[1] = 1 << 7; /* Command FIS. */
fis[2] = ATA_CMD_IDENT; /* Command byte. */
/* Read id from sata */
port = pccb->target;
if (!(tmpid = malloc(sizeof(hd_driveid_t))))
return -ENOMEM;
if (get_ahci_device_data(port, (u8 *) & fis, 20,
tmpid, sizeof(hd_driveid_t))) {
debug("scsi_ahci: SCSI inquiry command failure.\n");
return -EIO;
}
if (ataid[port])
free(ataid[port]);
ataid[port] = (hd_driveid_t *) tmpid;
memcpy(&pccb->pdata[8], "ATA ", 8);
ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
dump_ataid(ataid[port]);
return 0;
}
/*
* SCSI READ10 command operation.
*/
static int ata_scsiop_read10(ccb * pccb)
{
u32 len = 0;
u8 fis[20];
len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
/* For 10-byte and 16-byte SCSI R/W commands, transfer
* length 0 means transfer 0 block of data.
* However, for ATA R/W commands, sector count 0 means
* 256 or 65536 sectors, not 0 sectors as in SCSI.
*
* WARNING: one or two older ATA drives treat 0 as 0...
*/
if (!len)
return 0;
memset(fis, 0, 20);
/* Construct the FIS */
fis[0] = 0x27; /* Host to device FIS. */
fis[1] = 1 << 7; /* Command FIS. */
fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
/* LBA address, only support LBA28 in this driver */
fis[4] = pccb->cmd[5];
fis[5] = pccb->cmd[4];
fis[6] = pccb->cmd[3];
fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
/* Sector Count */
fis[12] = pccb->cmd[8];
fis[13] = pccb->cmd[7];
/* Read from ahci */
if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
pccb->pdata, pccb->datalen)) {
debug("scsi_ahci: SCSI READ10 command failure.\n");
return -EIO;
}
return 0;
}
/*
* SCSI READ CAPACITY10 command operation.
*/
static int ata_scsiop_read_capacity10(ccb *pccb)
{
u32 cap;
if (!ataid[pccb->target]) {
printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
"\tNo ATA info!\n"
"\tPlease run SCSI commmand INQUIRY firstly!\n");
return -EPERM;
}
cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
memcpy(pccb->pdata, &cap, sizeof(cap));
pccb->pdata[4] = pccb->pdata[5] = 0;
pccb->pdata[6] = 512 >> 8;
pccb->pdata[7] = 512 & 0xff;
return 0;
}
/*
* SCSI TEST UNIT READY command operation.
*/
static int ata_scsiop_test_unit_ready(ccb *pccb)
{
return (ataid[pccb->target]) ? 0 : -EPERM;
}
int scsi_exec(ccb *pccb)
{
int ret;
switch (pccb->cmd[0]) {
case SCSI_READ10:
ret = ata_scsiop_read10(pccb);
break;
case SCSI_RD_CAPAC:
ret = ata_scsiop_read_capacity10(pccb);
break;
case SCSI_TST_U_RDY:
ret = ata_scsiop_test_unit_ready(pccb);
break;
case SCSI_INQUIRY:
ret = ata_scsiop_inquiry(pccb);
break;
default:
printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
return FALSE;
}
if (ret) {
debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
return FALSE;
}
return TRUE;
}
void scsi_low_level_init(int busdevfunc)
{
int i;
u32 linkmap;
#ifndef CONFIG_SCSI_AHCI_PLAT
ahci_init_one(busdevfunc);
#endif
linkmap = probe_ent->link_port_map;
for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
if (((linkmap >> i) & 0x01)) {
if (ahci_port_start((u8) i)) {
printf("Can not start port %d\n", i);
continue;
}
ahci_set_feature((u8) i);
}
}
}
#ifdef CONFIG_SCSI_AHCI_PLAT
int ahci_init(u32 base)
{
int i, rc = 0;
u32 linkmap;
memset(ataid, 0, sizeof(ataid));
probe_ent = malloc(sizeof(struct ahci_probe_ent));
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
probe_ent->host_flags = ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
| ATA_FLAG_MMIO
| ATA_FLAG_PIO_DMA
| ATA_FLAG_NO_ATAPI;
probe_ent->pio_mask = 0x1f;
probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
probe_ent->mmio_base = base;
/* initialize adapter */
rc = ahci_host_init(probe_ent);
if (rc)
goto err_out;
ahci_print_info(probe_ent);
linkmap = probe_ent->link_port_map;
for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
if (((linkmap >> i) & 0x01)) {
if (ahci_port_start((u8) i)) {
printf("Can not start port %d\n", i);
continue;
}
ahci_set_feature((u8) i);
}
}
err_out:
return rc;
}
#endif
void scsi_bus_reset(void)
{
/*Not implement*/
}
void scsi_print_error(ccb * pccb)
{
/*The ahci error info can be read in the ahci driver*/
}
|
1001-study-uboot
|
drivers/block/ahci.c
|
C
|
gpl3
| 17,917
|
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libblock.o
COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o
COBJS-$(CONFIG_IDE_FTIDE020) += ftide020.o
COBJS-$(CONFIG_LIBATA) += libata.o
COBJS-$(CONFIG_CMD_MG_DISK) += mg_disk.o
COBJS-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
COBJS-$(CONFIG_MX51_PATA) += mxc_ata.o
COBJS-$(CONFIG_PATA_BFIN) += pata_bfin.o
COBJS-$(CONFIG_SATA_DWC) += sata_dwc.o
COBJS-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
COBJS-$(CONFIG_SATA_SIL) += sata_sil.o
COBJS-$(CONFIG_IDE_SIL680) += sil680.o
COBJS-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
COBJS-$(CONFIG_SYSTEMACE) += systemace.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/block/Makefile
|
Makefile
|
gpl3
| 1,919
|
/*
* Faraday FTIDE020 ATA Controller (AHB)
*
* (C) Copyright 2011 Andes Technology
* Greentime Hu <greentime@andestech.com>
* Macpaul Lin <macpaul@andestech.com>
* Kuo-Wei Chou <kwchou@andestech.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/* ftide020.c - ide support functions for the FTIDE020_S controller */
#include <config.h>
#include <common.h>
#include <ata.h>
#include <ide.h>
#include <asm/io.h>
#include <api_public.h>
#include "ftide020.h"
/* base address */
#define FTIDE_BASE CONFIG_SYS_ATA_BASE_ADDR
/*
* data address - The CMD and DATA use the same FIFO in FTIDE020_S
* FTIDE_DATA = CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_DATA_OFFSET
* = &ftide020->rw_fifo
*/
#define FTIDE_DATA (&ftide020->rw_fifo)
/* command and data I/O macros */
/* 0x0 - DATA FIFO */
#define WRITE_DATA(x) outl((x), &ftide020->rw_fifo) /* 0x00 */
#define READ_DATA() inl(&ftide020->rw_fifo) /* 0x00 */
/* 0x04 - R: Status Reg, W: CMD_FIFO */
#define WRITE_CMD(x) outl((x), &ftide020->cmd_fifo) /* 0x04 */
#define READ_STATUS() inl(&ftide020->cmd_fifo) /* 0x04 */
void ftide_set_device(int cx8, int dev)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
WRITE_CMD(SET_DEV_CMD | IDE_SET_CX8(cx8) | dev);
}
unsigned char ide_read_register(int dev, unsigned int port)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
ftide_set_device(0, dev);
WRITE_CMD(READ_REG_CMD | IDE_REG_CS_READ(CONFIG_IDE_REG_CS) |
IDE_REG_DA_WRITE(port));
return READ_DATA() & 0xff;
}
void ide_write_register(int dev, unsigned int port, unsigned char val)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
ftide_set_device(0, dev);
WRITE_CMD(WRITE_REG_CMD | IDE_REG_CS_WRITE(CONFIG_IDE_REG_CS) |
IDE_REG_DA_WRITE(port) | val);
}
void ide_write_data(int dev, ulong *sect_buf, int words)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
ftide_set_device(0, dev);
WRITE_CMD(WRITE_DATA_CMD | ((words << 2) - 1));
/* block write */
outsl(FTIDE_DATA, sect_buf, words);
}
void ide_read_data(int dev, ulong *sect_buf, int words)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
ftide_set_device(0, dev);
WRITE_CMD(READ_DATA_CMD | ((words << 2) - 1));
/* block read */
insl(FTIDE_DATA, sect_buf, words);
}
void ftide_dfifo_ready(ulong *time)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
while (!(READ_STATUS() & STATUS_RFE)) {
if (*time-- == 0)
break;
udelay(100);
}
}
extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
/* Reset_IDE_controller */
static void reset_ide_controller(void)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
unsigned int val;
val = inl(&ftide020->cr);
val |= CONTROL_RST;
outl(val, &ftide020->cr);
/* wait until reset OK, this is poor HW design */
mdelay(50);
val &= ~(CONTROL_RST);
outl(val, &ftide020->cr);
mdelay(50);
val |= CONTROL_SRST;
outl(val, &ftide020->cr);
/* wait until reset OK, this is poor HW design */
mdelay(50);
val &= ~(CONTROL_SRST);
outl(val, &ftide020->cr);
/* IORDY enable for PIO, for 2 device */
val |= (CONTROL_IRE0 | CONTROL_IRE1);
outl(val, &ftide020->cr);
}
/* IDE clock frequence */
uint ftide_clock_freq(void)
{
/*
* todo: To aquire dynamic system frequency is dependend on the power
* management unit which the ftide020 is connected to. In current,
* there are only few PMU supports in u-boot.
* So this function is wait for future enhancement.
*/
return 100;
}
/* Calculate Timing Registers */
static unsigned int timing_cal(u16 t0, u16 t1, u16 t2, u16 t4)
{
unsigned int val, ahb_ns = 8;
u8 TEOC, T1, T2, T4;
T1 = (u8) (t1 / ahb_ns);
if ((T1 * ahb_ns) == t1)
T1--;
T2 = (u8) (t2 / ahb_ns);
if ((T2 * ahb_ns) == t2)
T2--;
T4 = (u8) (t4 / ahb_ns);
if ((T4 * ahb_ns) == t4)
T4--;
TEOC = (u8) (t0 / ahb_ns);
if ((TEOC * ahb_ns) == t0)
TEOC--;
TEOC = ((TEOC > (T1 + T2 + T4)) ? (TEOC - (T1 + T2 + T4)) : 0);
/*
* Here the fields in data timing registers in PIO mode
* is accessed the same way as command timing registers.
*/
val = DT_REG_PIO_T1(T1) |
DT_REG_PIO_T2(T2) |
DT_REG_PIO_T4(T4) |
DT_REG_PIO_TEOC(TEOC);
return val;
}
/* Set Timing Register */
static unsigned int set_mode_timing(u8 dev, u8 id, u8 mode)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
u16 t0, t1, t2, t4;
u8 tcyc, tcvs, tmli, tenv, tack, trp;
unsigned int val, sysclk = 8;
if (id >= TATOL_TIMING)
return 0;
sysclk = ftide_clock_freq();
switch (id) {
case CMD_TIMING:
if (mode < REG_MODE) {
t0 = REG_ACCESS_TIMING[REG_T0][mode];
t1 = REG_ACCESS_TIMING[REG_T1][mode];
t2 = REG_ACCESS_TIMING[REG_T2][mode];
t4 = REG_ACCESS_TIMING[REG_T4][mode];
val = timing_cal(t0, t1, t2, t4);
outl(val, (dev ? &ftide020->ctrd1 : &ftide020->ctrd0));
return 1;
} else
return 0;
case PIO_TIMING:
if (mode < PIO_MODE) {
t0 = PIO_ACCESS_TIMING[PIO_T0][mode];
t1 = PIO_ACCESS_TIMING[PIO_T1][mode];
t2 = PIO_ACCESS_TIMING[PIO_T2][mode];
t4 = PIO_ACCESS_TIMING[PIO_T4][mode];
val = timing_cal(t0, t1, t2, t4);
outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));
return 1;
} else
return 0;
case DMA_TIMING:
if (mode < UDMA_MODE) {
/*
* 0.999 is ceiling
* for tcyc, tcvs, tmli, tenv, trp, tack
*/
tcyc = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCYC][mode] \
* sysclk) + 9990) / 10000);
tcvs = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCVS][mode] \
* sysclk) + 9990) / 10000);
tmli = (u8) (((UDMA_ACCESS_TIMING[UDMA_TMLI][mode] \
* sysclk) + 9990) / 10000);
tenv = (u8) (((UDMA_ACCESS_TIMING[UDMA_TENV][mode] \
* sysclk) + 9990) / 10000);
trp = (u8) (((UDMA_ACCESS_TIMING[UDMA_TRP][mode] \
* sysclk) + 9990) / 10000);
tack = (u8) (((UDMA_ACCESS_TIMING[UDMA_TACK][mode] \
* sysclk) + 9990) / 10000);
val = DT_REG_UDMA_TENV((tenv > 0) ? (tenv - 1) : 0) |
DT_REG_UDMA_TMLI((tmli > 0) ? (tmli - 1) : 0) |
DT_REG_UDMA_TCYC((tcyc > 0) ? (tcyc - 1) : 0) |
DT_REG_UDMA_TACK((tack > 0) ? (tack - 1) : 0) |
DT_REG_UDMA_TCVS((tcvs > 0) ? (tcvs - 1) : 0) |
DT_REG_UDMA_TRP((trp > 0) ? (trp - 1) : 0);
outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));
return 1;
} else
return 0;
default:
return 0;
}
}
static void ftide_read_hwrev(void)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
unsigned int rev;
rev = inl(&ftide020->revision);
}
static int ftide_controller_probe(void)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
unsigned int bak;
bak = inl(&ftide020->ctrd1);
/* probing by using shorter setup time */
outl(CONFIG_CTRD1_PROBE_T1, &ftide020->ctrd1);
if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T1) {
outl(bak, &ftide020->ctrd1);
return 0;
}
/* probing by using longer setup time */
outl(CONFIG_CTRD1_PROBE_T2, &ftide020->ctrd1);
if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T2) {
outl(bak, &ftide020->ctrd1);
return 0;
}
outl(bak, &ftide020->ctrd1);
return 1;
}
/* ide_preinit() was migrated from linux driver ide_probe_for_ftide() */
int ide_preinit(void)
{
static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
int status;
unsigned int val;
int i;
status = 1;
for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; i++)
ide_bus_offset[i] = -ATA_STATUS;
/* auto-detect IDE controller */
if (ftide_controller_probe()) {
printf("FTIDE020_S\n");
} else {
printf("FTIDE020_S ATA controller not found.\n");
return API_ENODEV;
}
/* check HW IP revision */
ftide_read_hwrev();
/* set FIFO threshold */
outl(((WRITE_FIFO - RX_THRESH) << 16) | RX_THRESH, &ftide020->dmatirr);
/* set Device_0 PIO_4 timing */
set_mode_timing(0, CMD_TIMING, REG_MODE4);
set_mode_timing(0, PIO_TIMING, PIO_MODE4);
/* set Device_1 PIO_4 timing */
set_mode_timing(1, CMD_TIMING, REG_MODE4);
set_mode_timing(1, PIO_TIMING, PIO_MODE4);
/* from E-bios */
/* little endian */
outl(0x0, &ftide020->cr);
mdelay(10);
outl(0x0fff0fff, &ftide020->ahbtr);
mdelay(10);
/* Enable controller Interrupt */
val = inl(&ftide020->cr);
/* Enable: IDE IRQ, IDE Terminate ERROR IRQ, AHB Timeout error IRQ */
val |= (CONTROL_IIE | CONTROL_TERIE | CONTROL_AERIE);
outl(val, &ftide020->cr);
status = 0;
return status;
}
void ide_set_reset(int flag)
{
debug("ide_set_reset()\n");
reset_ide_controller();
return;
}
|
1001-study-uboot
|
drivers/block/ftide020.c
|
C
|
gpl3
| 9,268
|
/*
* Copyright (c) 2004 Picture Elements, Inc.
* Stephen Williams (XXXXXXXXXXXXXXXX)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* The Xilinx SystemACE chip support is activated by defining
* CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE
* to set the base address of the device. This code currently
* assumes that the chip is connected via a byte-wide bus.
*
* The CONFIG_SYSTEMACE also adds to fat support the device class
* "ace" that allows the user to execute "fatls ace 0" and the
* like. This works by making the systemace_get_dev function
* available to cmd_fat.c:get_dev and filling in a block device
* description that has all the bits needed for FAT support to
* read sectors.
*
* According to Xilinx technical support, before accessing the
* SystemACE CF you need to set the following control bits:
* FORCECFGMODE : 1
* CFGMODE : 0
* CFGSTART : 0
*/
#include <common.h>
#include <command.h>
#include <systemace.h>
#include <part.h>
#include <asm/io.h>
/*
* The ace_readw and writew functions read/write 16bit words, but the
* offset value is the BYTE offset as most used in the Xilinx
* datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined
* to be the base address for the chip, usually in the local
* peripheral bus.
*/
#if (CONFIG_SYS_SYSTEMACE_WIDTH == 8)
#if !defined(__BIG_ENDIAN)
#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)<<8) | \
(readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)))
#define ace_writew(val, off) {writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off); \
writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off+1);}
#else
#define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)) | \
(readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)<<8))
#define ace_writew(val, off) {writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off); \
writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off+1);}
#endif
#else
#define ace_readw(off) (in16(CONFIG_SYS_SYSTEMACE_BASE+off))
#define ace_writew(val, off) (out16(CONFIG_SYS_SYSTEMACE_BASE+off,val))
#endif
/* */
static unsigned long systemace_read(int dev, unsigned long start,
unsigned long blkcnt, void *buffer);
static block_dev_desc_t systemace_dev = { 0 };
static int get_cf_lock(void)
{
int retry = 10;
/* CONTROLREG = LOCKREG */
unsigned val = ace_readw(0x18);
val |= 0x0002;
ace_writew((val & 0xffff), 0x18);
/* Wait for MPULOCK in STATUSREG[15:0] */
while (!(ace_readw(0x04) & 0x0002)) {
if (retry < 0)
return -1;
udelay(100000);
retry -= 1;
}
return 0;
}
static void release_cf_lock(void)
{
unsigned val = ace_readw(0x18);
val &= ~(0x0002);
ace_writew((val & 0xffff), 0x18);
}
#ifdef CONFIG_PARTITIONS
block_dev_desc_t *systemace_get_dev(int dev)
{
/* The first time through this, the systemace_dev object is
not yet initialized. In that case, fill it in. */
if (systemace_dev.blksz == 0) {
systemace_dev.if_type = IF_TYPE_UNKNOWN;
systemace_dev.dev = 0;
systemace_dev.part_type = PART_TYPE_UNKNOWN;
systemace_dev.type = DEV_TYPE_HARDDISK;
systemace_dev.blksz = 512;
systemace_dev.removable = 1;
systemace_dev.block_read = systemace_read;
/*
* Ensure the correct bus mode (8/16 bits) gets enabled
*/
ace_writew(CONFIG_SYS_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0);
init_part(&systemace_dev);
}
return &systemace_dev;
}
#endif
/*
* This function is called (by dereferencing the block_read pointer in
* the dev_desc) to read blocks of data. The return value is the
* number of blocks read. A zero return indicates an error.
*/
static unsigned long systemace_read(int dev, unsigned long start,
unsigned long blkcnt, void *buffer)
{
int retry;
unsigned blk_countdown;
unsigned char *dp = buffer;
unsigned val;
if (get_cf_lock() < 0) {
unsigned status = ace_readw(0x04);
/* If CFDETECT is false, card is missing. */
if (!(status & 0x0010)) {
printf("** CompactFlash card not present. **\n");
return 0;
}
printf("**** ACE locked away from me (STATUSREG=%04x)\n",
status);
return 0;
}
#ifdef DEBUG_SYSTEMACE
printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
#endif
retry = 2000;
for (;;) {
val = ace_readw(0x04);
/* If CFDETECT is false, card is missing. */
if (!(val & 0x0010)) {
printf("**** ACE CompactFlash not found.\n");
release_cf_lock();
return 0;
}
/* If RDYFORCMD, then we are ready to go. */
if (val & 0x0100)
break;
if (retry < 0) {
printf("**** SystemACE not ready.\n");
release_cf_lock();
return 0;
}
udelay(1000);
retry -= 1;
}
/* The SystemACE can only transfer 256 sectors at a time, so
limit the current chunk of sectors. The blk_countdown
variable is the number of sectors left to transfer. */
blk_countdown = blkcnt;
while (blk_countdown > 0) {
unsigned trans = blk_countdown;
if (trans > 256)
trans = 256;
#ifdef DEBUG_SYSTEMACE
printf("... transfer %lu sector in a chunk\n", trans);
#endif
/* Write LBA block address */
ace_writew((start >> 0) & 0xffff, 0x10);
ace_writew((start >> 16) & 0x0fff, 0x12);
/* NOTE: in the Write Sector count below, a count of 0
causes a transfer of 256, so &0xff gives the right
value for whatever transfer count we want. */
/* Write sector count | ReadMemCardData. */
ace_writew((trans & 0xff) | 0x0300, 0x14);
/*
* For FPGA configuration via SystemACE is reset unacceptable
* CFGDONE bit in STATUSREG is not set to 1.
*/
#ifndef SYSTEMACE_CONFIG_FPGA
/* Reset the configruation controller */
val = ace_readw(0x18);
val |= 0x0080;
ace_writew(val, 0x18);
#endif
retry = trans * 16;
while (retry > 0) {
int idx;
/* Wait for buffer to become ready. */
while (!(ace_readw(0x04) & 0x0020)) {
udelay(100);
}
/* Read 16 words of 2bytes from the sector buffer. */
for (idx = 0; idx < 16; idx += 1) {
unsigned short val = ace_readw(0x40);
*dp++ = val & 0xff;
*dp++ = (val >> 8) & 0xff;
}
retry -= 1;
}
/* Clear the configruation controller reset */
val = ace_readw(0x18);
val &= ~0x0080;
ace_writew(val, 0x18);
/* Count the blocks we transfer this time. */
start += trans;
blk_countdown -= trans;
}
release_cf_lock();
return blkcnt;
}
|
1001-study-uboot
|
drivers/block/systemace.c
|
C
|
gpl3
| 6,984
|
/*
* sata_dwc.c
*
* Synopsys DesignWare Cores (DWC) SATA host driver
*
* Author: Mark Miesfeld <mmiesfeld@amcc.com>
*
* Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
* Copyright 2008 DENX Software Engineering
*
* Based on versions provided by AMCC and Synopsys which are:
* Copyright 2006 Applied Micro Circuits Corporation
* COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
*
* This program is free software; you can redistribute
* it and/or modify it under the terms of the GNU
* General Public License as published by the
* Free Software Foundation; either version 2 of the License,
* or (at your option) any later version.
*
*/
/*
* SATA support based on the chip canyonlands.
*
* 04-17-2009
* The local version of this driver for the canyonlands board
* does not use interrupts but polls the chip instead.
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <malloc.h>
#include <ata.h>
#include <linux/ctype.h>
#include "sata_dwc.h"
#define DMA_NUM_CHANS 1
#define DMA_NUM_CHAN_REGS 8
#define AHB_DMA_BRST_DFLT 16
struct dmareg {
u32 low;
u32 high;
};
struct dma_chan_regs {
struct dmareg sar;
struct dmareg dar;
struct dmareg llp;
struct dmareg ctl;
struct dmareg sstat;
struct dmareg dstat;
struct dmareg sstatar;
struct dmareg dstatar;
struct dmareg cfg;
struct dmareg sgr;
struct dmareg dsr;
};
struct dma_interrupt_regs {
struct dmareg tfr;
struct dmareg block;
struct dmareg srctran;
struct dmareg dsttran;
struct dmareg error;
};
struct ahb_dma_regs {
struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
struct dma_interrupt_regs interrupt_raw;
struct dma_interrupt_regs interrupt_status;
struct dma_interrupt_regs interrupt_mask;
struct dma_interrupt_regs interrupt_clear;
struct dmareg statusInt;
struct dmareg rq_srcreg;
struct dmareg rq_dstreg;
struct dmareg rq_sgl_srcreg;
struct dmareg rq_sgl_dstreg;
struct dmareg rq_lst_srcreg;
struct dmareg rq_lst_dstreg;
struct dmareg dma_cfg;
struct dmareg dma_chan_en;
struct dmareg dma_id;
struct dmareg dma_test;
struct dmareg res1;
struct dmareg res2;
/* DMA Comp Params
* Param 6 = dma_param[0], Param 5 = dma_param[1],
* Param 4 = dma_param[2] ...
*/
struct dmareg dma_params[6];
};
#define DMA_EN 0x00000001
#define DMA_DI 0x00000000
#define DMA_CHANNEL(ch) (0x00000001 << (ch))
#define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
((0x000000001 << (ch)) << 8))
#define DMA_DISABLE_CHAN(ch) (0x00000000 | \
((0x000000001 << (ch)) << 8))
#define SATA_DWC_MAX_PORTS 1
#define SATA_DWC_SCR_OFFSET 0x24
#define SATA_DWC_REG_OFFSET 0x64
struct sata_dwc_regs {
u32 fptagr;
u32 fpbor;
u32 fptcr;
u32 dmacr;
u32 dbtsr;
u32 intpr;
u32 intmr;
u32 errmr;
u32 llcr;
u32 phycr;
u32 physr;
u32 rxbistpd;
u32 rxbistpd1;
u32 rxbistpd2;
u32 txbistpd;
u32 txbistpd1;
u32 txbistpd2;
u32 bistcr;
u32 bistfctr;
u32 bistsr;
u32 bistdecr;
u32 res[15];
u32 testr;
u32 versionr;
u32 idr;
u32 unimpl[192];
u32 dmadr[256];
};
#define SATA_DWC_TXFIFO_DEPTH 0x01FF
#define SATA_DWC_RXFIFO_DEPTH 0x01FF
#define SATA_DWC_DBTSR_MWR(size) ((size / 4) & SATA_DWC_TXFIFO_DEPTH)
#define SATA_DWC_DBTSR_MRD(size) (((size / 4) & \
SATA_DWC_RXFIFO_DEPTH) << 16)
#define SATA_DWC_INTPR_DMAT 0x00000001
#define SATA_DWC_INTPR_NEWFP 0x00000002
#define SATA_DWC_INTPR_PMABRT 0x00000004
#define SATA_DWC_INTPR_ERR 0x00000008
#define SATA_DWC_INTPR_NEWBIST 0x00000010
#define SATA_DWC_INTPR_IPF 0x10000000
#define SATA_DWC_INTMR_DMATM 0x00000001
#define SATA_DWC_INTMR_NEWFPM 0x00000002
#define SATA_DWC_INTMR_PMABRTM 0x00000004
#define SATA_DWC_INTMR_ERRM 0x00000008
#define SATA_DWC_INTMR_NEWBISTM 0x00000010
#define SATA_DWC_DMACR_TMOD_TXCHEN 0x00000004
#define SATA_DWC_DMACR_TXRXCH_CLEAR SATA_DWC_DMACR_TMOD_TXCHEN
#define SATA_DWC_QCMD_MAX 32
#define SATA_DWC_SERROR_ERR_BITS 0x0FFF0F03
#define HSDEVP_FROM_AP(ap) (struct sata_dwc_device_port*) \
(ap)->private_data
struct sata_dwc_device {
struct device *dev;
struct ata_probe_ent *pe;
struct ata_host *host;
u8 *reg_base;
struct sata_dwc_regs *sata_dwc_regs;
int irq_dma;
};
struct sata_dwc_device_port {
struct sata_dwc_device *hsdev;
int cmd_issued[SATA_DWC_QCMD_MAX];
u32 dma_chan[SATA_DWC_QCMD_MAX];
int dma_pending[SATA_DWC_QCMD_MAX];
};
enum {
SATA_DWC_CMD_ISSUED_NOT = 0,
SATA_DWC_CMD_ISSUED_PEND = 1,
SATA_DWC_CMD_ISSUED_EXEC = 2,
SATA_DWC_CMD_ISSUED_NODATA = 3,
SATA_DWC_DMA_PENDING_NONE = 0,
SATA_DWC_DMA_PENDING_TX = 1,
SATA_DWC_DMA_PENDING_RX = 2,
};
#define msleep(a) udelay(a * 1000)
#define ssleep(a) msleep(a * 1000)
static int ata_probe_timeout = (ATA_TMOUT_INTERNAL / 100);
enum sata_dev_state {
SATA_INIT = 0,
SATA_READY = 1,
SATA_NODEVICE = 2,
SATA_ERROR = 3,
};
enum sata_dev_state dev_state = SATA_INIT;
static struct ahb_dma_regs *sata_dma_regs = 0;
static struct ata_host *phost;
static struct ata_port ap;
static struct ata_port *pap = ≈
static struct ata_device ata_device;
static struct sata_dwc_device_port dwc_devp;
static void *scr_addr_sstatus;
static u32 temp_n_block = 0;
static unsigned ata_exec_internal(struct ata_device *dev,
struct ata_taskfile *tf, const u8 *cdb,
int dma_dir, unsigned int buflen,
unsigned long timeout);
static unsigned int ata_dev_set_feature(struct ata_device *dev,
u8 enable,u8 feature);
static unsigned int ata_dev_init_params(struct ata_device *dev,
u16 heads, u16 sectors);
static u8 ata_irq_on(struct ata_port *ap);
static struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
unsigned int tag);
static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
u8 status, int in_wq);
static void ata_tf_to_host(struct ata_port *ap,
const struct ata_taskfile *tf);
static void ata_exec_command(struct ata_port *ap,
const struct ata_taskfile *tf);
static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc);
static u8 ata_check_altstatus(struct ata_port *ap);
static u8 ata_check_status(struct ata_port *ap);
static void ata_dev_select(struct ata_port *ap, unsigned int device,
unsigned int wait, unsigned int can_sleep);
static void ata_qc_issue(struct ata_queued_cmd *qc);
static void ata_tf_load(struct ata_port *ap,
const struct ata_taskfile *tf);
static int ata_dev_read_sectors(unsigned char* pdata,
unsigned long datalen, u32 block, u32 n_block);
static int ata_dev_write_sectors(unsigned char* pdata,
unsigned long datalen , u32 block, u32 n_block);
static void ata_std_dev_select(struct ata_port *ap, unsigned int device);
static void ata_qc_complete(struct ata_queued_cmd *qc);
static void __ata_qc_complete(struct ata_queued_cmd *qc);
static void fill_result_tf(struct ata_queued_cmd *qc);
static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
static void ata_mmio_data_xfer(struct ata_device *dev,
unsigned char *buf,
unsigned int buflen,int do_write);
static void ata_pio_task(struct ata_port *arg_ap);
static void __ata_port_freeze(struct ata_port *ap);
static int ata_port_freeze(struct ata_port *ap);
static void ata_qc_free(struct ata_queued_cmd *qc);
static void ata_pio_sectors(struct ata_queued_cmd *qc);
static void ata_pio_sector(struct ata_queued_cmd *qc);
static void ata_pio_queue_task(struct ata_port *ap,
void *data,unsigned long delay);
static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq);
static int sata_dwc_softreset(struct ata_port *ap);
static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
unsigned int flags, u16 *id);
static int check_sata_dev_state(void);
extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
static const struct ata_port_info sata_dwc_port_info[] = {
{
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING |
ATA_FLAG_SRST | ATA_FLAG_NCQ,
.pio_mask = 0x1f,
.mwdma_mask = 0x07,
.udma_mask = 0x7f,
},
};
int init_sata(int dev)
{
struct sata_dwc_device hsdev;
struct ata_host host;
struct ata_port_info pi = sata_dwc_port_info[0];
struct ata_link *link;
struct sata_dwc_device_port hsdevp = dwc_devp;
u8 *base = 0;
u8 *sata_dma_regs_addr = 0;
u8 status;
unsigned long base_addr = 0;
int chan = 0;
int rc;
int i;
phost = &host;
base = (u8*)SATA_BASE_ADDR;
hsdev.sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
host.n_ports = SATA_DWC_MAX_PORTS;
for (i = 0; i < SATA_DWC_MAX_PORTS; i++) {
ap.pflags |= ATA_PFLAG_INITIALIZING;
ap.flags = ATA_FLAG_DISABLED;
ap.print_id = -1;
ap.ctl = ATA_DEVCTL_OBS;
ap.host = &host;
ap.last_ctl = 0xFF;
link = &ap.link;
link->ap = ≈
link->pmp = 0;
link->active_tag = ATA_TAG_POISON;
link->hw_sata_spd_limit = 0;
ap.port_no = i;
host.ports[i] = ≈
}
ap.pio_mask = pi.pio_mask;
ap.mwdma_mask = pi.mwdma_mask;
ap.udma_mask = pi.udma_mask;
ap.flags |= pi.flags;
ap.link.flags |= pi.link_flags;
host.ports[0]->ioaddr.cmd_addr = base;
host.ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
base_addr = (unsigned long)base;
host.ports[0]->ioaddr.cmd_addr = (void *)base_addr + 0x00;
host.ports[0]->ioaddr.data_addr = (void *)base_addr + 0x00;
host.ports[0]->ioaddr.error_addr = (void *)base_addr + 0x04;
host.ports[0]->ioaddr.feature_addr = (void *)base_addr + 0x04;
host.ports[0]->ioaddr.nsect_addr = (void *)base_addr + 0x08;
host.ports[0]->ioaddr.lbal_addr = (void *)base_addr + 0x0c;
host.ports[0]->ioaddr.lbam_addr = (void *)base_addr + 0x10;
host.ports[0]->ioaddr.lbah_addr = (void *)base_addr + 0x14;
host.ports[0]->ioaddr.device_addr = (void *)base_addr + 0x18;
host.ports[0]->ioaddr.command_addr = (void *)base_addr + 0x1c;
host.ports[0]->ioaddr.status_addr = (void *)base_addr + 0x1c;
host.ports[0]->ioaddr.altstatus_addr = (void *)base_addr + 0x20;
host.ports[0]->ioaddr.ctl_addr = (void *)base_addr + 0x20;
sata_dma_regs_addr = (u8*)SATA_DMA_REG_ADDR;
sata_dma_regs = (void *__iomem)sata_dma_regs_addr;
status = ata_check_altstatus(&ap);
if (status == 0x7f) {
printf("Hard Disk not found.\n");
dev_state = SATA_NODEVICE;
rc = FALSE;
return rc;
}
printf("Waiting for device...");
i = 0;
while (1) {
udelay(10000);
status = ata_check_altstatus(&ap);
if ((status & ATA_BUSY) == 0) {
printf("\n");
break;
}
i++;
if (i > (ATA_RESET_TIME * 100)) {
printf("** TimeOUT **\n");
dev_state = SATA_NODEVICE;
rc = FALSE;
return rc;
}
if ((i >= 100) && ((i % 100) == 0))
printf(".");
}
rc = sata_dwc_softreset(&ap);
if (rc) {
printf("sata_dwc : error. soft reset failed\n");
return rc;
}
for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
out_le32(&(sata_dma_regs->interrupt_mask.error.low),
DMA_DISABLE_CHAN(chan));
out_le32(&(sata_dma_regs->interrupt_mask.tfr.low),
DMA_DISABLE_CHAN(chan));
}
out_le32(&(sata_dma_regs->dma_cfg.low), DMA_DI);
out_le32(&hsdev.sata_dwc_regs->intmr,
SATA_DWC_INTMR_ERRM |
SATA_DWC_INTMR_PMABRTM);
/* Unmask the error bits that should trigger
* an error interrupt by setting the error mask register.
*/
out_le32(&hsdev.sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
hsdev.host = ap.host;
memset(&hsdevp, 0, sizeof(hsdevp));
hsdevp.hsdev = &hsdev;
for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
hsdevp.cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
out_le32((void __iomem *)scr_addr_sstatus + 4,
in_le32((void __iomem *)scr_addr_sstatus + 4));
rc = 0;
return rc;
}
static u8 ata_check_altstatus(struct ata_port *ap)
{
u8 val = 0;
val = readb(ap->ioaddr.altstatus_addr);
return val;
}
static int sata_dwc_softreset(struct ata_port *ap)
{
u8 nsect,lbal = 0;
u8 tmp = 0;
struct ata_ioports *ioaddr = &ap->ioaddr;
in_le32((void *)ap->ioaddr.scr_addr + (SCR_ERROR * 4));
writeb(0x55, ioaddr->nsect_addr);
writeb(0xaa, ioaddr->lbal_addr);
writeb(0xaa, ioaddr->nsect_addr);
writeb(0x55, ioaddr->lbal_addr);
writeb(0x55, ioaddr->nsect_addr);
writeb(0xaa, ioaddr->lbal_addr);
nsect = readb(ioaddr->nsect_addr);
lbal = readb(ioaddr->lbal_addr);
if ((nsect == 0x55) && (lbal == 0xaa)) {
printf("Device found\n");
} else {
printf("No device found\n");
dev_state = SATA_NODEVICE;
return FALSE;
}
tmp = ATA_DEVICE_OBS;
writeb(tmp, ioaddr->device_addr);
writeb(ap->ctl, ioaddr->ctl_addr);
udelay(200);
writeb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
udelay(200);
writeb(ap->ctl, ioaddr->ctl_addr);
msleep(150);
ata_check_status(ap);
msleep(50);
ata_check_status(ap);
while (1) {
u8 status = ata_check_status(ap);
if (!(status & ATA_BUSY))
break;
printf("Hard Disk status is BUSY.\n");
msleep(50);
}
tmp = ATA_DEVICE_OBS;
writeb(tmp, ioaddr->device_addr);
nsect = readb(ioaddr->nsect_addr);
lbal = readb(ioaddr->lbal_addr);
return 0;
}
static u8 ata_check_status(struct ata_port *ap)
{
u8 val = 0;
val = readb(ap->ioaddr.status_addr);
return val;
}
static int ata_id_has_hipm(const u16 *id)
{
u16 val = id[76];
if (val == 0 || val == 0xffff)
return -1;
return val & (1 << 9);
}
static int ata_id_has_dipm(const u16 *id)
{
u16 val = id[78];
if (val == 0 || val == 0xffff)
return -1;
return val & (1 << 3);
}
int scan_sata(int dev)
{
int i;
int rc;
u8 status;
const u16 *id;
struct ata_device *ata_dev = &ata_device;
unsigned long pio_mask, mwdma_mask;
char revbuf[7];
u16 iobuf[ATA_SECTOR_WORDS];
memset(iobuf, 0, sizeof(iobuf));
if (dev_state == SATA_NODEVICE)
return 1;
printf("Waiting for device...");
i = 0;
while (1) {
udelay(10000);
status = ata_check_altstatus(&ap);
if ((status & ATA_BUSY) == 0) {
printf("\n");
break;
}
i++;
if (i > (ATA_RESET_TIME * 100)) {
printf("** TimeOUT **\n");
dev_state = SATA_NODEVICE;
return 1;
}
if ((i >= 100) && ((i % 100) == 0))
printf(".");
}
udelay(1000);
rc = ata_dev_read_id(ata_dev, &ata_dev->class,
ATA_READID_POSTRESET,ata_dev->id);
if (rc) {
printf("sata_dwc : error. failed sata scan\n");
return 1;
}
/* SATA drives indicate we have a bridge. We don't know which
* end of the link the bridge is which is a problem
*/
if (ata_id_is_sata(ata_dev->id))
ap.cbl = ATA_CBL_SATA;
id = ata_dev->id;
ata_dev->flags &= ~ATA_DFLAG_CFG_MASK;
ata_dev->max_sectors = 0;
ata_dev->cdb_len = 0;
ata_dev->n_sectors = 0;
ata_dev->cylinders = 0;
ata_dev->heads = 0;
ata_dev->sectors = 0;
if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
pio_mask <<= 3;
pio_mask |= 0x7;
} else {
/* If word 64 isn't valid then Word 51 high byte holds
* the PIO timing number for the maximum. Turn it into
* a mask.
*/
u8 mode = (id[ATA_ID_OLD_PIO_MODES] >> 8) & 0xFF;
if (mode < 5) {
pio_mask = (2 << mode) - 1;
} else {
pio_mask = 1;
}
}
mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
if (ata_id_is_cfa(id)) {
int pio = id[163] & 0x7;
int dma = (id[163] >> 3) & 7;
if (pio)
pio_mask |= (1 << 5);
if (pio > 1)
pio_mask |= (1 << 6);
if (dma)
mwdma_mask |= (1 << 3);
if (dma > 1)
mwdma_mask |= (1 << 4);
}
if (ata_dev->class == ATA_DEV_ATA) {
if (ata_id_is_cfa(id)) {
if (id[162] & 1)
printf("supports DRM functions and may "
"not be fully accessable.\n");
sprintf(revbuf, "%s", "CFA");
} else {
if (ata_id_has_tpm(id))
printf("supports DRM functions and may "
"not be fully accessable.\n");
}
ata_dev->n_sectors = ata_id_n_sectors((u16*)id);
if (ata_dev->id[59] & 0x100)
ata_dev->multi_count = ata_dev->id[59] & 0xff;
if (ata_id_has_lba(id)) {
char ncq_desc[20];
ata_dev->flags |= ATA_DFLAG_LBA;
if (ata_id_has_lba48(id)) {
ata_dev->flags |= ATA_DFLAG_LBA48;
if (ata_dev->n_sectors >= (1UL << 28) &&
ata_id_has_flush_ext(id))
ata_dev->flags |= ATA_DFLAG_FLUSH_EXT;
}
if (!ata_id_has_ncq(ata_dev->id))
ncq_desc[0] = '\0';
if (ata_dev->horkage & ATA_HORKAGE_NONCQ)
sprintf(ncq_desc, "%s", "NCQ (not used)");
if (ap.flags & ATA_FLAG_NCQ)
ata_dev->flags |= ATA_DFLAG_NCQ;
}
ata_dev->cdb_len = 16;
}
ata_dev->max_sectors = ATA_MAX_SECTORS;
if (ata_dev->flags & ATA_DFLAG_LBA48)
ata_dev->max_sectors = ATA_MAX_SECTORS_LBA48;
if (!(ata_dev->horkage & ATA_HORKAGE_IPM)) {
if (ata_id_has_hipm(ata_dev->id))
ata_dev->flags |= ATA_DFLAG_HIPM;
if (ata_id_has_dipm(ata_dev->id))
ata_dev->flags |= ATA_DFLAG_DIPM;
}
if ((ap.cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ata_dev->id))) {
ata_dev->udma_mask &= ATA_UDMA5;
ata_dev->max_sectors = ATA_MAX_SECTORS;
}
if (ata_dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
printf("Drive reports diagnostics failure."
"This may indicate a drive\n");
printf("fault or invalid emulation."
"Contact drive vendor for information.\n");
}
rc = check_sata_dev_state();
ata_id_c_string(ata_dev->id,
(unsigned char *)sata_dev_desc[dev].revision,
ATA_ID_FW_REV, sizeof(sata_dev_desc[dev].revision));
ata_id_c_string(ata_dev->id,
(unsigned char *)sata_dev_desc[dev].vendor,
ATA_ID_PROD, sizeof(sata_dev_desc[dev].vendor));
ata_id_c_string(ata_dev->id,
(unsigned char *)sata_dev_desc[dev].product,
ATA_ID_SERNO, sizeof(sata_dev_desc[dev].product));
sata_dev_desc[dev].lba = (u32) ata_dev->n_sectors;
#ifdef CONFIG_LBA48
if (ata_dev->id[83] & (1 << 10)) {
sata_dev_desc[dev].lba48 = 1;
} else {
sata_dev_desc[dev].lba48 = 0;
}
#endif
return 0;
}
static u8 ata_busy_wait(struct ata_port *ap,
unsigned int bits,unsigned int max)
{
u8 status;
do {
udelay(10);
status = ata_check_status(ap);
max--;
} while (status != 0xff && (status & bits) && (max > 0));
return status;
}
static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
unsigned int flags, u16 *id)
{
struct ata_port *ap = pap;
unsigned int class = *p_class;
struct ata_taskfile tf;
unsigned int err_mask = 0;
const char *reason;
int may_fallback = 1, tried_spinup = 0;
u8 status;
int rc;
status = ata_busy_wait(ap, ATA_BUSY, 30000);
if (status & ATA_BUSY) {
printf("BSY = 0 check. timeout.\n");
rc = FALSE;
return rc;
}
ata_dev_select(ap, dev->devno, 1, 1);
retry:
memset(&tf, 0, sizeof(tf));
ap->print_id = 1;
ap->flags &= ~ATA_FLAG_DISABLED;
tf.ctl = ap->ctl;
tf.device = ATA_DEVICE_OBS;
tf.command = ATA_CMD_ID_ATA;
tf.protocol = ATA_PROT_PIO;
/* Some devices choke if TF registers contain garbage. Make
* sure those are properly initialized.
*/
tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
/* Device presence detection is unreliable on some
* controllers. Always poll IDENTIFY if available.
*/
tf.flags |= ATA_TFLAG_POLLING;
temp_n_block = 1;
err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
sizeof(id[0]) * ATA_ID_WORDS, 0);
if (err_mask) {
if (err_mask & AC_ERR_NODEV_HINT) {
printf("NODEV after polling detection\n");
return -ENOENT;
}
if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
/* Device or controller might have reported
* the wrong device class. Give a shot at the
* other IDENTIFY if the current one is
* aborted by the device.
*/
if (may_fallback) {
may_fallback = 0;
if (class == ATA_DEV_ATA) {
class = ATA_DEV_ATAPI;
} else {
class = ATA_DEV_ATA;
}
goto retry;
}
/* Control reaches here iff the device aborted
* both flavors of IDENTIFYs which happens
* sometimes with phantom devices.
*/
printf("both IDENTIFYs aborted, assuming NODEV\n");
return -ENOENT;
}
rc = -EIO;
reason = "I/O error";
goto err_out;
}
/* Falling back doesn't make sense if ID data was read
* successfully at least once.
*/
may_fallback = 0;
unsigned int id_cnt;
for (id_cnt = 0; id_cnt < ATA_ID_WORDS; id_cnt++)
id[id_cnt] = le16_to_cpu(id[id_cnt]);
rc = -EINVAL;
reason = "device reports invalid type";
if (class == ATA_DEV_ATA) {
if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
goto err_out;
} else {
if (ata_id_is_ata(id))
goto err_out;
}
if (!tried_spinup && (id[2] == 0x37c8 || id[2] == 0x738c)) {
tried_spinup = 1;
/*
* Drive powered-up in standby mode, and requires a specific
* SET_FEATURES spin-up subcommand before it will accept
* anything other than the original IDENTIFY command.
*/
err_mask = ata_dev_set_feature(dev, SETFEATURES_SPINUP, 0);
if (err_mask && id[2] != 0x738c) {
rc = -EIO;
reason = "SPINUP failed";
goto err_out;
}
/*
* If the drive initially returned incomplete IDENTIFY info,
* we now must reissue the IDENTIFY command.
*/
if (id[2] == 0x37c8)
goto retry;
}
if ((flags & ATA_READID_POSTRESET) && class == ATA_DEV_ATA) {
/*
* The exact sequence expected by certain pre-ATA4 drives is:
* SRST RESET
* IDENTIFY (optional in early ATA)
* INITIALIZE DEVICE PARAMETERS (later IDE and ATA)
* anything else..
* Some drives were very specific about that exact sequence.
*
* Note that ATA4 says lba is mandatory so the second check
* shoud never trigger.
*/
if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
err_mask = ata_dev_init_params(dev, id[3], id[6]);
if (err_mask) {
rc = -EIO;
reason = "INIT_DEV_PARAMS failed";
goto err_out;
}
/* current CHS translation info (id[53-58]) might be
* changed. reread the identify device info.
*/
flags &= ~ATA_READID_POSTRESET;
goto retry;
}
}
*p_class = class;
return 0;
err_out:
printf("failed to READ ID (%s, err_mask=0x%x)\n", reason, err_mask);
return rc;
}
static u8 ata_wait_idle(struct ata_port *ap)
{
u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
return status;
}
static void ata_dev_select(struct ata_port *ap, unsigned int device,
unsigned int wait, unsigned int can_sleep)
{
if (wait)
ata_wait_idle(ap);
ata_std_dev_select(ap, device);
if (wait)
ata_wait_idle(ap);
}
static void ata_std_dev_select(struct ata_port *ap, unsigned int device)
{
u8 tmp;
if (device == 0) {
tmp = ATA_DEVICE_OBS;
} else {
tmp = ATA_DEVICE_OBS | ATA_DEV1;
}
writeb(tmp, ap->ioaddr.device_addr);
readb(ap->ioaddr.altstatus_addr);
udelay(1);
}
static int waiting_for_reg_state(volatile u8 *offset,
int timeout_msec,
u32 sign)
{
int i;
u32 status;
for (i = 0; i < timeout_msec; i++) {
status = readl(offset);
if ((status & sign) != 0)
break;
msleep(1);
}
return (i < timeout_msec) ? 0 : -1;
}
static void ata_qc_reinit(struct ata_queued_cmd *qc)
{
qc->dma_dir = DMA_NONE;
qc->flags = 0;
qc->nbytes = qc->extrabytes = qc->curbytes = 0;
qc->n_elem = 0;
qc->err_mask = 0;
qc->sect_size = ATA_SECT_SIZE;
qc->nbytes = ATA_SECT_SIZE * temp_n_block;
memset(&qc->tf, 0, sizeof(qc->tf));
qc->tf.ctl = 0;
qc->tf.device = ATA_DEVICE_OBS;
qc->result_tf.command = ATA_DRDY;
qc->result_tf.feature = 0;
}
struct ata_queued_cmd *__ata_qc_from_tag(struct ata_port *ap,
unsigned int tag)
{
if (tag < ATA_MAX_QUEUE)
return &ap->qcmd[tag];
return NULL;
}
static void __ata_port_freeze(struct ata_port *ap)
{
printf("set port freeze.\n");
ap->pflags |= ATA_PFLAG_FROZEN;
}
static int ata_port_freeze(struct ata_port *ap)
{
__ata_port_freeze(ap);
return 0;
}
unsigned ata_exec_internal(struct ata_device *dev,
struct ata_taskfile *tf, const u8 *cdb,
int dma_dir, unsigned int buflen,
unsigned long timeout)
{
struct ata_link *link = dev->link;
struct ata_port *ap = pap;
struct ata_queued_cmd *qc;
unsigned int tag, preempted_tag;
u32 preempted_sactive, preempted_qc_active;
int preempted_nr_active_links;
unsigned int err_mask;
int rc = 0;
u8 status;
status = ata_busy_wait(ap, ATA_BUSY, 300000);
if (status & ATA_BUSY) {
printf("BSY = 0 check. timeout.\n");
rc = FALSE;
return rc;
}
if (ap->pflags & ATA_PFLAG_FROZEN)
return AC_ERR_SYSTEM;
tag = ATA_TAG_INTERNAL;
if (test_and_set_bit(tag, &ap->qc_allocated)) {
rc = FALSE;
return rc;
}
qc = __ata_qc_from_tag(ap, tag);
qc->tag = tag;
qc->ap = ap;
qc->dev = dev;
ata_qc_reinit(qc);
preempted_tag = link->active_tag;
preempted_sactive = link->sactive;
preempted_qc_active = ap->qc_active;
preempted_nr_active_links = ap->nr_active_links;
link->active_tag = ATA_TAG_POISON;
link->sactive = 0;
ap->qc_active = 0;
ap->nr_active_links = 0;
qc->tf = *tf;
if (cdb)
memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
qc->flags |= ATA_QCFLAG_RESULT_TF;
qc->dma_dir = dma_dir;
qc->private_data = 0;
ata_qc_issue(qc);
if (!timeout)
timeout = ata_probe_timeout * 1000 / HZ;
status = ata_busy_wait(ap, ATA_BUSY, 30000);
if (status & ATA_BUSY) {
printf("BSY = 0 check. timeout.\n");
printf("altstatus = 0x%x.\n", status);
qc->err_mask |= AC_ERR_OTHER;
return qc->err_mask;
}
if (waiting_for_reg_state(ap->ioaddr.altstatus_addr, 1000, 0x8)) {
u8 status = 0;
u8 errorStatus = 0;
status = readb(ap->ioaddr.altstatus_addr);
if ((status & 0x01) != 0) {
errorStatus = readb(ap->ioaddr.feature_addr);
if (errorStatus == 0x04 &&
qc->tf.command == ATA_CMD_PIO_READ_EXT){
printf("Hard Disk doesn't support LBA48\n");
dev_state = SATA_ERROR;
qc->err_mask |= AC_ERR_OTHER;
return qc->err_mask;
}
}
qc->err_mask |= AC_ERR_OTHER;
return qc->err_mask;
}
status = ata_busy_wait(ap, ATA_BUSY, 10);
if (status & ATA_BUSY) {
printf("BSY = 0 check. timeout.\n");
qc->err_mask |= AC_ERR_OTHER;
return qc->err_mask;
}
ata_pio_task(ap);
if (!rc) {
if (qc->flags & ATA_QCFLAG_ACTIVE) {
qc->err_mask |= AC_ERR_TIMEOUT;
ata_port_freeze(ap);
}
}
if (qc->flags & ATA_QCFLAG_FAILED) {
if (qc->result_tf.command & (ATA_ERR | ATA_DF))
qc->err_mask |= AC_ERR_DEV;
if (!qc->err_mask)
qc->err_mask |= AC_ERR_OTHER;
if (qc->err_mask & ~AC_ERR_OTHER)
qc->err_mask &= ~AC_ERR_OTHER;
}
*tf = qc->result_tf;
err_mask = qc->err_mask;
ata_qc_free(qc);
link->active_tag = preempted_tag;
link->sactive = preempted_sactive;
ap->qc_active = preempted_qc_active;
ap->nr_active_links = preempted_nr_active_links;
if (ap->flags & ATA_FLAG_DISABLED) {
err_mask |= AC_ERR_SYSTEM;
ap->flags &= ~ATA_FLAG_DISABLED;
}
return err_mask;
}
static void ata_qc_issue(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct ata_link *link = qc->dev->link;
u8 prot = qc->tf.protocol;
if (ata_is_ncq(prot)) {
if (!link->sactive)
ap->nr_active_links++;
link->sactive |= 1 << qc->tag;
} else {
ap->nr_active_links++;
link->active_tag = qc->tag;
}
qc->flags |= ATA_QCFLAG_ACTIVE;
ap->qc_active |= 1 << qc->tag;
if (qc->dev->flags & ATA_DFLAG_SLEEPING) {
msleep(1);
return;
}
qc->err_mask |= ata_qc_issue_prot(qc);
if (qc->err_mask)
goto err;
return;
err:
ata_qc_complete(qc);
}
static unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
if (ap->flags & ATA_FLAG_PIO_POLLING) {
switch (qc->tf.protocol) {
case ATA_PROT_PIO:
case ATA_PROT_NODATA:
case ATAPI_PROT_PIO:
case ATAPI_PROT_NODATA:
qc->tf.flags |= ATA_TFLAG_POLLING;
break;
default:
break;
}
}
ata_dev_select(ap, qc->dev->devno, 1, 0);
switch (qc->tf.protocol) {
case ATA_PROT_PIO:
if (qc->tf.flags & ATA_TFLAG_POLLING)
qc->tf.ctl |= ATA_NIEN;
ata_tf_to_host(ap, &qc->tf);
ap->hsm_task_state = HSM_ST;
if (qc->tf.flags & ATA_TFLAG_POLLING)
ata_pio_queue_task(ap, qc, 0);
break;
default:
return AC_ERR_SYSTEM;
}
return 0;
}
static void ata_tf_to_host(struct ata_port *ap,
const struct ata_taskfile *tf)
{
ata_tf_load(ap, tf);
ata_exec_command(ap, tf);
}
static void ata_tf_load(struct ata_port *ap,
const struct ata_taskfile *tf)
{
struct ata_ioports *ioaddr = &ap->ioaddr;
unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
if (tf->ctl != ap->last_ctl) {
if (ioaddr->ctl_addr)
writeb(tf->ctl, ioaddr->ctl_addr);
ap->last_ctl = tf->ctl;
ata_wait_idle(ap);
}
if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
writeb(tf->hob_feature, ioaddr->feature_addr);
writeb(tf->hob_nsect, ioaddr->nsect_addr);
writeb(tf->hob_lbal, ioaddr->lbal_addr);
writeb(tf->hob_lbam, ioaddr->lbam_addr);
writeb(tf->hob_lbah, ioaddr->lbah_addr);
}
if (is_addr) {
writeb(tf->feature, ioaddr->feature_addr);
writeb(tf->nsect, ioaddr->nsect_addr);
writeb(tf->lbal, ioaddr->lbal_addr);
writeb(tf->lbam, ioaddr->lbam_addr);
writeb(tf->lbah, ioaddr->lbah_addr);
}
if (tf->flags & ATA_TFLAG_DEVICE)
writeb(tf->device, ioaddr->device_addr);
ata_wait_idle(ap);
}
static void ata_exec_command(struct ata_port *ap,
const struct ata_taskfile *tf)
{
writeb(tf->command, ap->ioaddr.command_addr);
readb(ap->ioaddr.altstatus_addr);
udelay(1);
}
static void ata_pio_queue_task(struct ata_port *ap,
void *data,unsigned long delay)
{
ap->port_task_data = data;
}
static unsigned int ac_err_mask(u8 status)
{
if (status & (ATA_BUSY | ATA_DRQ))
return AC_ERR_HSM;
if (status & (ATA_ERR | ATA_DF))
return AC_ERR_DEV;
return 0;
}
static unsigned int __ac_err_mask(u8 status)
{
unsigned int mask = ac_err_mask(status);
if (mask == 0)
return AC_ERR_OTHER;
return mask;
}
static void ata_pio_task(struct ata_port *arg_ap)
{
struct ata_port *ap = arg_ap;
struct ata_queued_cmd *qc = ap->port_task_data;
u8 status;
int poll_next;
fsm_start:
/*
* This is purely heuristic. This is a fast path.
* Sometimes when we enter, BSY will be cleared in
* a chk-status or two. If not, the drive is probably seeking
* or something. Snooze for a couple msecs, then
* chk-status again. If still busy, queue delayed work.
*/
status = ata_busy_wait(ap, ATA_BUSY, 5);
if (status & ATA_BUSY) {
msleep(2);
status = ata_busy_wait(ap, ATA_BUSY, 10);
if (status & ATA_BUSY) {
ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
return;
}
}
poll_next = ata_hsm_move(ap, qc, status, 1);
/* another command or interrupt handler
* may be running at this point.
*/
if (poll_next)
goto fsm_start;
}
static int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
u8 status, int in_wq)
{
int poll_next;
fsm_start:
switch (ap->hsm_task_state) {
case HSM_ST_FIRST:
poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
if ((status & ATA_DRQ) == 0) {
if (status & (ATA_ERR | ATA_DF)) {
qc->err_mask |= AC_ERR_DEV;
} else {
qc->err_mask |= AC_ERR_HSM;
}
ap->hsm_task_state = HSM_ST_ERR;
goto fsm_start;
}
/* Device should not ask for data transfer (DRQ=1)
* when it finds something wrong.
* We ignore DRQ here and stop the HSM by
* changing hsm_task_state to HSM_ST_ERR and
* let the EH abort the command or reset the device.
*/
if (status & (ATA_ERR | ATA_DF)) {
if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
printf("DRQ=1 with device error, "
"dev_stat 0x%X\n", status);
qc->err_mask |= AC_ERR_HSM;
ap->hsm_task_state = HSM_ST_ERR;
goto fsm_start;
}
}
if (qc->tf.protocol == ATA_PROT_PIO) {
/* PIO data out protocol.
* send first data block.
*/
/* ata_pio_sectors() might change the state
* to HSM_ST_LAST. so, the state is changed here
* before ata_pio_sectors().
*/
ap->hsm_task_state = HSM_ST;
ata_pio_sectors(qc);
} else {
printf("protocol is not ATA_PROT_PIO \n");
}
break;
case HSM_ST:
if ((status & ATA_DRQ) == 0) {
if (status & (ATA_ERR | ATA_DF)) {
qc->err_mask |= AC_ERR_DEV;
} else {
/* HSM violation. Let EH handle this.
* Phantom devices also trigger this
* condition. Mark hint.
*/
qc->err_mask |= AC_ERR_HSM | AC_ERR_NODEV_HINT;
}
ap->hsm_task_state = HSM_ST_ERR;
goto fsm_start;
}
/* For PIO reads, some devices may ask for
* data transfer (DRQ=1) alone with ERR=1.
* We respect DRQ here and transfer one
* block of junk data before changing the
* hsm_task_state to HSM_ST_ERR.
*
* For PIO writes, ERR=1 DRQ=1 doesn't make
* sense since the data block has been
* transferred to the device.
*/
if (status & (ATA_ERR | ATA_DF)) {
qc->err_mask |= AC_ERR_DEV;
if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
ata_pio_sectors(qc);
status = ata_wait_idle(ap);
}
if (status & (ATA_BUSY | ATA_DRQ))
qc->err_mask |= AC_ERR_HSM;
/* ata_pio_sectors() might change the
* state to HSM_ST_LAST. so, the state
* is changed after ata_pio_sectors().
*/
ap->hsm_task_state = HSM_ST_ERR;
goto fsm_start;
}
ata_pio_sectors(qc);
if (ap->hsm_task_state == HSM_ST_LAST &&
(!(qc->tf.flags & ATA_TFLAG_WRITE))) {
status = ata_wait_idle(ap);
goto fsm_start;
}
poll_next = 1;
break;
case HSM_ST_LAST:
if (!ata_ok(status)) {
qc->err_mask |= __ac_err_mask(status);
ap->hsm_task_state = HSM_ST_ERR;
goto fsm_start;
}
ap->hsm_task_state = HSM_ST_IDLE;
ata_hsm_qc_complete(qc, in_wq);
poll_next = 0;
break;
case HSM_ST_ERR:
/* make sure qc->err_mask is available to
* know what's wrong and recover
*/
ap->hsm_task_state = HSM_ST_IDLE;
ata_hsm_qc_complete(qc, in_wq);
poll_next = 0;
break;
default:
poll_next = 0;
}
return poll_next;
}
static void ata_pio_sectors(struct ata_queued_cmd *qc)
{
struct ata_port *ap;
ap = pap;
qc->pdata = ap->pdata;
ata_pio_sector(qc);
readb(qc->ap->ioaddr.altstatus_addr);
udelay(1);
}
static void ata_pio_sector(struct ata_queued_cmd *qc)
{
int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
struct ata_port *ap = qc->ap;
unsigned int offset;
unsigned char *buf;
char temp_data_buf[512];
if (qc->curbytes == qc->nbytes - qc->sect_size)
ap->hsm_task_state = HSM_ST_LAST;
offset = qc->curbytes;
switch (qc->tf.command) {
case ATA_CMD_ID_ATA:
buf = (unsigned char *)&ata_device.id[0];
break;
case ATA_CMD_PIO_READ_EXT:
case ATA_CMD_PIO_READ:
case ATA_CMD_PIO_WRITE_EXT:
case ATA_CMD_PIO_WRITE:
buf = qc->pdata + offset;
break;
default:
buf = (unsigned char *)&temp_data_buf[0];
}
ata_mmio_data_xfer(qc->dev, buf, qc->sect_size, do_write);
qc->curbytes += qc->sect_size;
}
static void ata_mmio_data_xfer(struct ata_device *dev, unsigned char *buf,
unsigned int buflen, int do_write)
{
struct ata_port *ap = pap;
void __iomem *data_addr = ap->ioaddr.data_addr;
unsigned int words = buflen >> 1;
u16 *buf16 = (u16 *)buf;
unsigned int i = 0;
udelay(100);
if (do_write) {
for (i = 0; i < words; i++)
writew(le16_to_cpu(buf16[i]), data_addr);
} else {
for (i = 0; i < words; i++)
buf16[i] = cpu_to_le16(readw(data_addr));
}
if (buflen & 0x01) {
__le16 align_buf[1] = { 0 };
unsigned char *trailing_buf = buf + buflen - 1;
if (do_write) {
memcpy(align_buf, trailing_buf, 1);
writew(le16_to_cpu(align_buf[0]), data_addr);
} else {
align_buf[0] = cpu_to_le16(readw(data_addr));
memcpy(trailing_buf, align_buf, 1);
}
}
}
static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
{
struct ata_port *ap = qc->ap;
if (in_wq) {
/* EH might have kicked in while host lock is
* released.
*/
qc = &ap->qcmd[qc->tag];
if (qc) {
if (!(qc->err_mask & AC_ERR_HSM)) {
ata_irq_on(ap);
ata_qc_complete(qc);
} else {
ata_port_freeze(ap);
}
}
} else {
if (!(qc->err_mask & AC_ERR_HSM)) {
ata_qc_complete(qc);
} else {
ata_port_freeze(ap);
}
}
}
static u8 ata_irq_on(struct ata_port *ap)
{
struct ata_ioports *ioaddr = &ap->ioaddr;
u8 tmp;
ap->ctl &= ~ATA_NIEN;
ap->last_ctl = ap->ctl;
if (ioaddr->ctl_addr)
writeb(ap->ctl, ioaddr->ctl_addr);
tmp = ata_wait_idle(ap);
return tmp;
}
static unsigned int ata_tag_internal(unsigned int tag)
{
return tag == ATA_MAX_QUEUE - 1;
}
static void ata_qc_complete(struct ata_queued_cmd *qc)
{
struct ata_device *dev = qc->dev;
if (qc->err_mask)
qc->flags |= ATA_QCFLAG_FAILED;
if (qc->flags & ATA_QCFLAG_FAILED) {
if (!ata_tag_internal(qc->tag)) {
fill_result_tf(qc);
return;
}
}
if (qc->flags & ATA_QCFLAG_RESULT_TF)
fill_result_tf(qc);
/* Some commands need post-processing after successful
* completion.
*/
switch (qc->tf.command) {
case ATA_CMD_SET_FEATURES:
if (qc->tf.feature != SETFEATURES_WC_ON &&
qc->tf.feature != SETFEATURES_WC_OFF)
break;
case ATA_CMD_INIT_DEV_PARAMS:
case ATA_CMD_SET_MULTI:
break;
case ATA_CMD_SLEEP:
dev->flags |= ATA_DFLAG_SLEEPING;
break;
}
__ata_qc_complete(qc);
}
static void fill_result_tf(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
qc->result_tf.flags = qc->tf.flags;
ata_tf_read(ap, &qc->result_tf);
}
static void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
struct ata_ioports *ioaddr = &ap->ioaddr;
tf->command = ata_check_status(ap);
tf->feature = readb(ioaddr->error_addr);
tf->nsect = readb(ioaddr->nsect_addr);
tf->lbal = readb(ioaddr->lbal_addr);
tf->lbam = readb(ioaddr->lbam_addr);
tf->lbah = readb(ioaddr->lbah_addr);
tf->device = readb(ioaddr->device_addr);
if (tf->flags & ATA_TFLAG_LBA48) {
if (ioaddr->ctl_addr) {
writeb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
tf->hob_feature = readb(ioaddr->error_addr);
tf->hob_nsect = readb(ioaddr->nsect_addr);
tf->hob_lbal = readb(ioaddr->lbal_addr);
tf->hob_lbam = readb(ioaddr->lbam_addr);
tf->hob_lbah = readb(ioaddr->lbah_addr);
writeb(tf->ctl, ioaddr->ctl_addr);
ap->last_ctl = tf->ctl;
} else {
printf("sata_dwc warnning register read.\n");
}
}
}
static void __ata_qc_complete(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct ata_link *link = qc->dev->link;
link->active_tag = ATA_TAG_POISON;
ap->nr_active_links--;
if (qc->flags & ATA_QCFLAG_CLEAR_EXCL && ap->excl_link == link)
ap->excl_link = NULL;
qc->flags &= ~ATA_QCFLAG_ACTIVE;
ap->qc_active &= ~(1 << qc->tag);
}
static void ata_qc_free(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
unsigned int tag;
qc->flags = 0;
tag = qc->tag;
if (tag < ATA_MAX_QUEUE) {
qc->tag = ATA_TAG_POISON;
clear_bit(tag, &ap->qc_allocated);
}
}
static int check_sata_dev_state(void)
{
unsigned long datalen;
unsigned char *pdata;
int ret = 0;
int i = 0;
char temp_data_buf[512];
while (1) {
udelay(10000);
pdata = (unsigned char*)&temp_data_buf[0];
datalen = 512;
ret = ata_dev_read_sectors(pdata, datalen, 0, 1);
if (ret == TRUE)
break;
i++;
if (i > (ATA_RESET_TIME * 100)) {
printf("** TimeOUT **\n");
dev_state = SATA_NODEVICE;
return FALSE;
}
if ((i >= 100) && ((i % 100) == 0))
printf(".");
}
dev_state = SATA_READY;
return TRUE;
}
static unsigned int ata_dev_set_feature(struct ata_device *dev,
u8 enable, u8 feature)
{
struct ata_taskfile tf;
struct ata_port *ap;
ap = pap;
unsigned int err_mask;
memset(&tf, 0, sizeof(tf));
tf.ctl = ap->ctl;
tf.device = ATA_DEVICE_OBS;
tf.command = ATA_CMD_SET_FEATURES;
tf.feature = enable;
tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
tf.protocol = ATA_PROT_NODATA;
tf.nsect = feature;
err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
return err_mask;
}
static unsigned int ata_dev_init_params(struct ata_device *dev,
u16 heads, u16 sectors)
{
struct ata_taskfile tf;
struct ata_port *ap;
ap = pap;
unsigned int err_mask;
if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
return AC_ERR_INVALID;
memset(&tf, 0, sizeof(tf));
tf.ctl = ap->ctl;
tf.device = ATA_DEVICE_OBS;
tf.command = ATA_CMD_INIT_DEV_PARAMS;
tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
tf.protocol = ATA_PROT_NODATA;
tf.nsect = sectors;
tf.device |= (heads - 1) & 0x0f;
err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, 0, 0);
if (err_mask == AC_ERR_DEV && (tf.feature & ATA_ABORTED))
err_mask = 0;
return err_mask;
}
#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
#define SATA_MAX_READ_BLK 0xFF
#else
#define SATA_MAX_READ_BLK 0xFFFF
#endif
ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
{
ulong start,blks, buf_addr;
unsigned short smallblks;
unsigned long datalen;
unsigned char *pdata;
device &= 0xff;
u32 block = 0;
u32 n_block = 0;
if (dev_state != SATA_READY)
return 0;
buf_addr = (unsigned long)buffer;
start = blknr;
blks = blkcnt;
do {
pdata = (unsigned char *)buf_addr;
if (blks > SATA_MAX_READ_BLK) {
datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
smallblks = SATA_MAX_READ_BLK;
block = (u32)start;
n_block = (u32)smallblks;
start += SATA_MAX_READ_BLK;
blks -= SATA_MAX_READ_BLK;
} else {
datalen = sata_dev_desc[device].blksz * SATA_MAX_READ_BLK;
datalen = sata_dev_desc[device].blksz * blks;
smallblks = (unsigned short)blks;
block = (u32)start;
n_block = (u32)smallblks;
start += blks;
blks = 0;
}
if (ata_dev_read_sectors(pdata, datalen, block, n_block) != TRUE) {
printf("sata_dwc : Hard disk read error.\n");
blkcnt -= blks;
break;
}
buf_addr += datalen;
} while (blks != 0);
return (blkcnt);
}
static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen,
u32 block, u32 n_block)
{
struct ata_port *ap = pap;
struct ata_device *dev = &ata_device;
struct ata_taskfile tf;
unsigned int class = ATA_DEV_ATA;
unsigned int err_mask = 0;
const char *reason;
int may_fallback = 1;
if (dev_state == SATA_ERROR)
return FALSE;
ata_dev_select(ap, dev->devno, 1, 1);
retry:
memset(&tf, 0, sizeof(tf));
tf.ctl = ap->ctl;
ap->print_id = 1;
ap->flags &= ~ATA_FLAG_DISABLED;
ap->pdata = pdata;
tf.device = ATA_DEVICE_OBS;
temp_n_block = n_block;
#ifdef CONFIG_LBA48
tf.command = ATA_CMD_PIO_READ_EXT;
tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48;
tf.hob_feature = 31;
tf.feature = 31;
tf.hob_nsect = (n_block >> 8) & 0xff;
tf.nsect = n_block & 0xff;
tf.hob_lbah = 0x0;
tf.hob_lbam = 0x0;
tf.hob_lbal = (block >> 24) & 0xff;
tf.lbah = (block >> 16) & 0xff;
tf.lbam = (block >> 8) & 0xff;
tf.lbal = block & 0xff;
tf.device = 1 << 6;
if (tf.flags & ATA_TFLAG_FUA)
tf.device |= 1 << 7;
#else
tf.command = ATA_CMD_PIO_READ;
tf.flags |= ATA_TFLAG_LBA ;
tf.feature = 31;
tf.nsect = n_block & 0xff;
tf.lbah = (block >> 16) & 0xff;
tf.lbam = (block >> 8) & 0xff;
tf.lbal = block & 0xff;
tf.device = (block >> 24) & 0xf;
tf.device |= 1 << 6;
if (tf.flags & ATA_TFLAG_FUA)
tf.device |= 1 << 7;
#endif
tf.protocol = ATA_PROT_PIO;
/* Some devices choke if TF registers contain garbage. Make
* sure those are properly initialized.
*/
tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
tf.flags |= ATA_TFLAG_POLLING;
err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
if (err_mask) {
if (err_mask & AC_ERR_NODEV_HINT) {
printf("READ_SECTORS NODEV after polling detection\n");
return -ENOENT;
}
if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
/* Device or controller might have reported
* the wrong device class. Give a shot at the
* other IDENTIFY if the current one is
* aborted by the device.
*/
if (may_fallback) {
may_fallback = 0;
if (class == ATA_DEV_ATA) {
class = ATA_DEV_ATAPI;
} else {
class = ATA_DEV_ATA;
}
goto retry;
}
/* Control reaches here iff the device aborted
* both flavors of IDENTIFYs which happens
* sometimes with phantom devices.
*/
printf("both IDENTIFYs aborted, assuming NODEV\n");
return -ENOENT;
}
reason = "I/O error";
goto err_out;
}
return TRUE;
err_out:
printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
return FALSE;
}
#if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48)
#define SATA_MAX_WRITE_BLK 0xFF
#else
#define SATA_MAX_WRITE_BLK 0xFFFF
#endif
ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
{
ulong start,blks, buf_addr;
unsigned short smallblks;
unsigned long datalen;
unsigned char *pdata;
device &= 0xff;
u32 block = 0;
u32 n_block = 0;
if (dev_state != SATA_READY)
return 0;
buf_addr = (unsigned long)buffer;
start = blknr;
blks = blkcnt;
do {
pdata = (unsigned char *)buf_addr;
if (blks > SATA_MAX_WRITE_BLK) {
datalen = sata_dev_desc[device].blksz * SATA_MAX_WRITE_BLK;
smallblks = SATA_MAX_WRITE_BLK;
block = (u32)start;
n_block = (u32)smallblks;
start += SATA_MAX_WRITE_BLK;
blks -= SATA_MAX_WRITE_BLK;
} else {
datalen = sata_dev_desc[device].blksz * blks;
smallblks = (unsigned short)blks;
block = (u32)start;
n_block = (u32)smallblks;
start += blks;
blks = 0;
}
if (ata_dev_write_sectors(pdata, datalen, block, n_block) != TRUE) {
printf("sata_dwc : Hard disk read error.\n");
blkcnt -= blks;
break;
}
buf_addr += datalen;
} while (blks != 0);
return (blkcnt);
}
static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen,
u32 block, u32 n_block)
{
struct ata_port *ap = pap;
struct ata_device *dev = &ata_device;
struct ata_taskfile tf;
unsigned int class = ATA_DEV_ATA;
unsigned int err_mask = 0;
const char *reason;
int may_fallback = 1;
if (dev_state == SATA_ERROR)
return FALSE;
ata_dev_select(ap, dev->devno, 1, 1);
retry:
memset(&tf, 0, sizeof(tf));
tf.ctl = ap->ctl;
ap->print_id = 1;
ap->flags &= ~ATA_FLAG_DISABLED;
ap->pdata = pdata;
tf.device = ATA_DEVICE_OBS;
temp_n_block = n_block;
#ifdef CONFIG_LBA48
tf.command = ATA_CMD_PIO_WRITE_EXT;
tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_LBA48 | ATA_TFLAG_WRITE;
tf.hob_feature = 31;
tf.feature = 31;
tf.hob_nsect = (n_block >> 8) & 0xff;
tf.nsect = n_block & 0xff;
tf.hob_lbah = 0x0;
tf.hob_lbam = 0x0;
tf.hob_lbal = (block >> 24) & 0xff;
tf.lbah = (block >> 16) & 0xff;
tf.lbam = (block >> 8) & 0xff;
tf.lbal = block & 0xff;
tf.device = 1 << 6;
if (tf.flags & ATA_TFLAG_FUA)
tf.device |= 1 << 7;
#else
tf.command = ATA_CMD_PIO_WRITE;
tf.flags |= ATA_TFLAG_LBA | ATA_TFLAG_WRITE;
tf.feature = 31;
tf.nsect = n_block & 0xff;
tf.lbah = (block >> 16) & 0xff;
tf.lbam = (block >> 8) & 0xff;
tf.lbal = block & 0xff;
tf.device = (block >> 24) & 0xf;
tf.device |= 1 << 6;
if (tf.flags & ATA_TFLAG_FUA)
tf.device |= 1 << 7;
#endif
tf.protocol = ATA_PROT_PIO;
/* Some devices choke if TF registers contain garbage. Make
* sure those are properly initialized.
*/
tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
tf.flags |= ATA_TFLAG_POLLING;
err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE, 0, 0);
if (err_mask) {
if (err_mask & AC_ERR_NODEV_HINT) {
printf("READ_SECTORS NODEV after polling detection\n");
return -ENOENT;
}
if ((err_mask == AC_ERR_DEV) && (tf.feature & ATA_ABORTED)) {
/* Device or controller might have reported
* the wrong device class. Give a shot at the
* other IDENTIFY if the current one is
* aborted by the device.
*/
if (may_fallback) {
may_fallback = 0;
if (class == ATA_DEV_ATA) {
class = ATA_DEV_ATAPI;
} else {
class = ATA_DEV_ATA;
}
goto retry;
}
/* Control reaches here iff the device aborted
* both flavors of IDENTIFYs which happens
* sometimes with phantom devices.
*/
printf("both IDENTIFYs aborted, assuming NODEV\n");
return -ENOENT;
}
reason = "I/O error";
goto err_out;
}
return TRUE;
err_out:
printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask);
return FALSE;
}
|
1001-study-uboot
|
drivers/block/sata_dwc.c
|
C
|
gpl3
| 47,427
|
/*
* Driver for Blackfin on-chip ATAPI controller.
*
* Enter bugs at http://blackfin.uclinux.org/
*
* Copyright (c) 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef PATA_BFIN_H
#define PATA_BFIN_H
#include <asm/blackfin_local.h>
struct ata_ioports {
unsigned long cmd_addr;
unsigned long data_addr;
unsigned long error_addr;
unsigned long feature_addr;
unsigned long nsect_addr;
unsigned long lbal_addr;
unsigned long lbam_addr;
unsigned long lbah_addr;
unsigned long device_addr;
unsigned long status_addr;
unsigned long command_addr;
unsigned long altstatus_addr;
unsigned long ctl_addr;
unsigned long bmdma_addr;
unsigned long scr_addr;
};
struct ata_port {
unsigned int port_no; /* primary=0, secondary=1 */
struct ata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
unsigned long flag;
unsigned int ata_mode;
unsigned char ctl_reg;
unsigned char last_ctl;
unsigned char dev_mask;
};
extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
#define DRV_NAME "pata-bfin"
#define DRV_VERSION "0.9"
#define __iomem
#define ATA_REG_CTRL 0x0E
#define ATA_REG_ALTSTATUS ATA_REG_CTRL
#define ATA_TMOUT_BOOT 30000
#define ATA_TMOUT_BOOT_QUICK 7000
#define PATA_BFIN_WAIT_TIMEOUT 10000
#define PATA_DEV_NUM_PER_PORT 2
/* These are the offset of the controller's registers */
#define ATAPI_OFFSET_CONTROL 0x00
#define ATAPI_OFFSET_STATUS 0x04
#define ATAPI_OFFSET_DEV_ADDR 0x08
#define ATAPI_OFFSET_DEV_TXBUF 0x0c
#define ATAPI_OFFSET_DEV_RXBUF 0x10
#define ATAPI_OFFSET_INT_MASK 0x14
#define ATAPI_OFFSET_INT_STATUS 0x18
#define ATAPI_OFFSET_XFER_LEN 0x1c
#define ATAPI_OFFSET_LINE_STATUS 0x20
#define ATAPI_OFFSET_SM_STATE 0x24
#define ATAPI_OFFSET_TERMINATE 0x28
#define ATAPI_OFFSET_PIO_TFRCNT 0x2c
#define ATAPI_OFFSET_DMA_TFRCNT 0x30
#define ATAPI_OFFSET_UMAIN_TFRCNT 0x34
#define ATAPI_OFFSET_UDMAOUT_TFRCNT 0x38
#define ATAPI_OFFSET_REG_TIM_0 0x40
#define ATAPI_OFFSET_PIO_TIM_0 0x44
#define ATAPI_OFFSET_PIO_TIM_1 0x48
#define ATAPI_OFFSET_MULTI_TIM_0 0x50
#define ATAPI_OFFSET_MULTI_TIM_1 0x54
#define ATAPI_OFFSET_MULTI_TIM_2 0x58
#define ATAPI_OFFSET_ULTRA_TIM_0 0x60
#define ATAPI_OFFSET_ULTRA_TIM_1 0x64
#define ATAPI_OFFSET_ULTRA_TIM_2 0x68
#define ATAPI_OFFSET_ULTRA_TIM_3 0x6c
#define ATAPI_GET_CONTROL(base)\
bfin_read16(base + ATAPI_OFFSET_CONTROL)
#define ATAPI_SET_CONTROL(base, val)\
bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
#define ATAPI_GET_STATUS(base)\
bfin_read16(base + ATAPI_OFFSET_STATUS)
#define ATAPI_GET_DEV_ADDR(base)\
bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
#define ATAPI_SET_DEV_ADDR(base, val)\
bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
#define ATAPI_GET_DEV_TXBUF(base)\
bfin_read16(base + ATAPI_OFFSET_DEV_TXBUF)
#define ATAPI_SET_DEV_TXBUF(base, val)\
bfin_write16(base + ATAPI_OFFSET_DEV_TXBUF, val)
#define ATAPI_GET_DEV_RXBUF(base)\
bfin_read16(base + ATAPI_OFFSET_DEV_RXBUF)
#define ATAPI_SET_DEV_RXBUF(base, val)\
bfin_write16(base + ATAPI_OFFSET_DEV_RXBUF, val)
#define ATAPI_GET_INT_MASK(base)\
bfin_read16(base + ATAPI_OFFSET_INT_MASK)
#define ATAPI_SET_INT_MASK(base, val)\
bfin_write16(base + ATAPI_OFFSET_INT_MASK, val)
#define ATAPI_GET_INT_STATUS(base)\
bfin_read16(base + ATAPI_OFFSET_INT_STATUS)
#define ATAPI_SET_INT_STATUS(base, val)\
bfin_write16(base + ATAPI_OFFSET_INT_STATUS, val)
#define ATAPI_GET_XFER_LEN(base)\
bfin_read16(base + ATAPI_OFFSET_XFER_LEN)
#define ATAPI_SET_XFER_LEN(base, val)\
bfin_write16(base + ATAPI_OFFSET_XFER_LEN, val)
#define ATAPI_GET_LINE_STATUS(base)\
bfin_read16(base + ATAPI_OFFSET_LINE_STATUS)
#define ATAPI_GET_SM_STATE(base)\
bfin_read16(base + ATAPI_OFFSET_SM_STATE)
#define ATAPI_GET_TERMINATE(base)\
bfin_read16(base + ATAPI_OFFSET_TERMINATE)
#define ATAPI_SET_TERMINATE(base, val)\
bfin_write16(base + ATAPI_OFFSET_TERMINATE, val)
#define ATAPI_GET_PIO_TFRCNT(base)\
bfin_read16(base + ATAPI_OFFSET_PIO_TFRCNT)
#define ATAPI_GET_DMA_TFRCNT(base)\
bfin_read16(base + ATAPI_OFFSET_DMA_TFRCNT)
#define ATAPI_GET_UMAIN_TFRCNT(base)\
bfin_read16(base + ATAPI_OFFSET_UMAIN_TFRCNT)
#define ATAPI_GET_UDMAOUT_TFRCNT(base)\
bfin_read16(base + ATAPI_OFFSET_UDMAOUT_TFRCNT)
#define ATAPI_GET_REG_TIM_0(base)\
bfin_read16(base + ATAPI_OFFSET_REG_TIM_0)
#define ATAPI_SET_REG_TIM_0(base, val)\
bfin_write16(base + ATAPI_OFFSET_REG_TIM_0, val)
#define ATAPI_GET_PIO_TIM_0(base)\
bfin_read16(base + ATAPI_OFFSET_PIO_TIM_0)
#define ATAPI_SET_PIO_TIM_0(base, val)\
bfin_write16(base + ATAPI_OFFSET_PIO_TIM_0, val)
#define ATAPI_GET_PIO_TIM_1(base)\
bfin_read16(base + ATAPI_OFFSET_PIO_TIM_1)
#define ATAPI_SET_PIO_TIM_1(base, val)\
bfin_write16(base + ATAPI_OFFSET_PIO_TIM_1, val)
#define ATAPI_GET_MULTI_TIM_0(base)\
bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_0)
#define ATAPI_SET_MULTI_TIM_0(base, val)\
bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_0, val)
#define ATAPI_GET_MULTI_TIM_1(base)\
bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_1)
#define ATAPI_SET_MULTI_TIM_1(base, val)\
bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_1, val)
#define ATAPI_GET_MULTI_TIM_2(base)\
bfin_read16(base + ATAPI_OFFSET_MULTI_TIM_2)
#define ATAPI_SET_MULTI_TIM_2(base, val)\
bfin_write16(base + ATAPI_OFFSET_MULTI_TIM_2, val)
#define ATAPI_GET_ULTRA_TIM_0(base)\
bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_0)
#define ATAPI_SET_ULTRA_TIM_0(base, val)\
bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_0, val)
#define ATAPI_GET_ULTRA_TIM_1(base)\
bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_1)
#define ATAPI_SET_ULTRA_TIM_1(base, val)\
bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_1, val)
#define ATAPI_GET_ULTRA_TIM_2(base)\
bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_2)
#define ATAPI_SET_ULTRA_TIM_2(base, val)\
bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_2, val)
#define ATAPI_GET_ULTRA_TIM_3(base)\
bfin_read16(base + ATAPI_OFFSET_ULTRA_TIM_3)
#define ATAPI_SET_ULTRA_TIM_3(base, val)\
bfin_write16(base + ATAPI_OFFSET_ULTRA_TIM_3, val)
#endif
|
1001-study-uboot
|
drivers/block/pata_bfin.h
|
C
|
gpl3
| 5,954
|
/*
* Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/fsl_serdes.h>
#include <malloc.h>
#include <libata.h>
#include <fis.h>
#include "fsl_sata.h"
extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
#ifndef CONFIG_SYS_SATA1_FLAGS
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#endif
#ifndef CONFIG_SYS_SATA2_FLAGS
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
#endif
static struct fsl_sata_info fsl_sata_info[] = {
#ifdef CONFIG_SATA1
{CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
#else
{0, 0},
#endif
#ifdef CONFIG_SATA2
{CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
#else
{0, 0},
#endif
};
static inline void sdelay(unsigned long sec)
{
unsigned long i;
for (i = 0; i < sec; i++)
mdelay(1000);
}
void dprint_buffer(unsigned char *buf, int len)
{
int i, j;
i = 0;
j = 0;
printf("\n\r");
for (i = 0; i < len; i++) {
printf("%02x ", *buf++);
j++;
if (j == 16) {
printf("\n\r");
j = 0;
}
}
printf("\n\r");
}
static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
{
printf("Status FIS dump:\n\r");
printf("fis_type: %02x\n\r", s->fis_type);
printf("pm_port_i: %02x\n\r", s->pm_port_i);
printf("status: %02x\n\r", s->status);
printf("error: %02x\n\r", s->error);
printf("lba_low: %02x\n\r", s->lba_low);
printf("lba_mid: %02x\n\r", s->lba_mid);
printf("lba_high: %02x\n\r", s->lba_high);
printf("device: %02x\n\r", s->device);
printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
printf("res1: %02x\n\r", s->res1);
printf("sector_count: %02x\n\r", s->sector_count);
printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
}
static int ata_wait_register(volatile unsigned *addr, u32 mask,
u32 val, u32 timeout_msec)
{
int i;
u32 temp;
for (i = 0; (((temp = in_le32(addr)) & mask) != val)
&& i < timeout_msec; i++)
mdelay(1);
return (i < timeout_msec) ? 0 : -1;
}
int init_sata(int dev)
{
u32 length, align;
cmd_hdr_tbl_t *cmd_hdr;
u32 cda;
u32 val32;
fsl_sata_reg_t *reg;
u32 sig;
int i;
fsl_sata_t *sata;
if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
printf("the sata index %d is out of ranges\n\r", dev);
return -1;
}
#ifdef CONFIG_MPC85xx
if ((dev == 0) && (!is_serdes_configured(SATA1))) {
printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
return -1;
}
if ((dev == 1) && (!is_serdes_configured(SATA2))) {
printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
return -1;
}
#endif
/* Allocate SATA device driver struct */
sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
if (!sata) {
printf("alloc the sata device struct failed\n\r");
return -1;
}
/* Zero all of the device driver struct */
memset((void *)sata, 0, sizeof(fsl_sata_t));
/* Save the private struct to block device struct */
sata_dev_desc[dev].priv = (void *)sata;
sprintf(sata->name, "SATA%d", dev);
/* Set the controller register base address to device struct */
reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
sata->reg_base = reg;
/* Allocate the command header table, 4 bytes aligned */
length = sizeof(struct cmd_hdr_tbl);
align = SATA_HC_CMD_HDR_TBL_ALIGN;
sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
if (!sata) {
printf("alloc the command header failed\n\r");
return -1;
}
cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
& ~(align - 1));
sata->cmd_hdr = cmd_hdr;
/* Zero all of the command header table */
memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
/* Allocate command descriptor for all command */
length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
align = SATA_HC_CMD_DESC_ALIGN;
sata->cmd_desc_offset = (void *)malloc(length + align);
if (!sata->cmd_desc_offset) {
printf("alloc the command descriptor failed\n\r");
return -1;
}
sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
& ~(align - 1));
/* Zero all of command descriptor */
memset((void *)sata->cmd_desc_offset, 0, length + align);
/* Link the command descriptor to command header */
for (i = 0; i < SATA_HC_MAX_CMD; i++) {
cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
& ~(CMD_HDR_CDA_ALIGN - 1);
cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
}
/* To have safe state, force the controller offline */
val32 = in_le32(®->hcontrol);
val32 &= ~HCONTROL_ONOFF;
val32 |= HCONTROL_FORCE_OFFLINE;
out_le32(®->hcontrol, val32);
/* Wait the controller offline */
ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000);
/* Set the command header base address to CHBA register to tell DMA */
out_le32(®->chba, (u32)cmd_hdr & ~0x3);
/* Snoop for the command header */
val32 = in_le32(®->hcontrol);
val32 |= HCONTROL_HDR_SNOOP;
out_le32(®->hcontrol, val32);
/* Disable all of interrupts */
val32 = in_le32(®->hcontrol);
val32 &= ~HCONTROL_INT_EN_ALL;
out_le32(®->hcontrol, val32);
/* Clear all of interrupts */
val32 = in_le32(®->hstatus);
out_le32(®->hstatus, val32);
/* Set the ICC, no interrupt coalescing */
out_le32(®->icc, 0x01000000);
/* No PM attatched, the SATA device direct connect */
out_le32(®->cqpmp, 0);
/* Clear SError register */
val32 = in_le32(®->serror);
out_le32(®->serror, val32);
/* Clear CER register */
val32 = in_le32(®->cer);
out_le32(®->cer, val32);
/* Clear DER register */
val32 = in_le32(®->der);
out_le32(®->der, val32);
/* No device detection or initialization action requested */
out_le32(®->scontrol, 0x00000300);
/* Configure the transport layer, default value */
out_le32(®->transcfg, 0x08000016);
/* Configure the link layer, default value */
out_le32(®->linkcfg, 0x0000ff34);
/* Bring the controller online */
val32 = in_le32(®->hcontrol);
val32 |= HCONTROL_ONOFF;
out_le32(®->hcontrol, val32);
mdelay(100);
/* print sata device name */
if (!dev)
printf("%s ", sata->name);
else
printf(" %s ", sata->name);
/* Wait PHY RDY signal changed for 500ms */
ata_wait_register(®->hstatus, HSTATUS_PHY_RDY,
HSTATUS_PHY_RDY, 500);
/* Check PHYRDY */
val32 = in_le32(®->hstatus);
if (val32 & HSTATUS_PHY_RDY) {
sata->link = 1;
} else {
sata->link = 0;
printf("(No RDY)\n\r");
return -1;
}
/* Wait for signature updated, which is 1st D2H */
ata_wait_register(®->hstatus, HSTATUS_SIGNATURE,
HSTATUS_SIGNATURE, 10000);
if (val32 & HSTATUS_SIGNATURE) {
sig = in_le32(®->sig);
debug("Signature updated, the sig =%08x\n\r", sig);
sata->ata_device_type = ata_dev_classify(sig);
}
/* Check the speed */
val32 = in_le32(®->sstatus);
if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
printf("(1.5 Gbps)\n\r");
else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
printf("(3 Gbps)\n\r");
return 0;
}
/* Hardware reset, like Power-on and COMRESET */
void fsl_sata_hardware_reset(u32 reg_base)
{
fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base;
u32 scontrol;
/* Disable the SATA interface and put PHY offline */
scontrol = in_le32(®->scontrol);
scontrol = (scontrol & 0x0f0) | 0x304;
out_le32(®->scontrol, scontrol);
/* No speed strict */
scontrol = in_le32(®->scontrol);
scontrol = scontrol & ~0x0f0;
out_le32(®->scontrol, scontrol);
/* Issue PHY wake/reset, Hardware_reset_asserted */
scontrol = in_le32(®->scontrol);
scontrol = (scontrol & 0x0f0) | 0x301;
out_le32(®->scontrol, scontrol);
mdelay(100);
/* Resume PHY, COMRESET negated, the device initialize hardware
* and execute diagnostics, send good status-signature to host,
* which is D2H register FIS, and then the device enter idle state.
*/
scontrol = in_le32(®->scontrol);
scontrol = (scontrol & 0x0f0) | 0x300;
out_le32(®->scontrol, scontrol);
mdelay(100);
return;
}
static void fsl_sata_dump_regs(fsl_sata_reg_t *reg)
{
printf("\n\rSATA: %08x\n\r", (u32)reg);
printf("CQR: %08x\n\r", in_le32(®->cqr));
printf("CAR: %08x\n\r", in_le32(®->car));
printf("CCR: %08x\n\r", in_le32(®->ccr));
printf("CER: %08x\n\r", in_le32(®->cer));
printf("CQR: %08x\n\r", in_le32(®->cqr));
printf("DER: %08x\n\r", in_le32(®->der));
printf("CHBA: %08x\n\r", in_le32(®->chba));
printf("HStatus: %08x\n\r", in_le32(®->hstatus));
printf("HControl: %08x\n\r", in_le32(®->hcontrol));
printf("CQPMP: %08x\n\r", in_le32(®->cqpmp));
printf("SIG: %08x\n\r", in_le32(®->sig));
printf("ICC: %08x\n\r", in_le32(®->icc));
printf("SStatus: %08x\n\r", in_le32(®->sstatus));
printf("SError: %08x\n\r", in_le32(®->serror));
printf("SControl: %08x\n\r", in_le32(®->scontrol));
printf("SNotification: %08x\n\r", in_le32(®->snotification));
printf("TransCfg: %08x\n\r", in_le32(®->transcfg));
printf("TransStatus: %08x\n\r", in_le32(®->transstatus));
printf("LinkCfg: %08x\n\r", in_le32(®->linkcfg));
printf("LinkCfg1: %08x\n\r", in_le32(®->linkcfg1));
printf("LinkCfg2: %08x\n\r", in_le32(®->linkcfg2));
printf("LinkStatus: %08x\n\r", in_le32(®->linkstatus));
printf("LinkStatus1: %08x\n\r", in_le32(®->linkstatus1));
printf("PhyCtrlCfg: %08x\n\r", in_le32(®->phyctrlcfg));
printf("SYSPR: %08x\n\r", in_be32(®->syspr));
}
static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
int is_ncq, int tag, u8 *buffer, u32 len)
{
cmd_hdr_entry_t *cmd_hdr;
cmd_desc_t *cmd_desc;
sata_fis_h2d_t *h2d;
prd_entry_t *prde;
u32 ext_c_ddc;
u32 prde_count;
u32 val32;
u32 ttl;
fsl_sata_reg_t *reg = sata->reg_base;
int i;
/* Check xfer length */
if (len > SATA_HC_MAX_XFER_LEN) {
printf("max transfer length is 64MB\n\r");
return 0;
}
/* Setup the command descriptor */
cmd_desc = sata->cmd_desc + tag;
/* Get the pointer cfis of command descriptor */
h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
/* Zero the cfis of command descriptor */
memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
/* Copy the cfis from user to command descriptor */
h2d->fis_type = cfis->fis_type;
h2d->pm_port_c = cfis->pm_port_c;
h2d->command = cfis->command;
h2d->features = cfis->features;
h2d->features_exp = cfis->features_exp;
h2d->lba_low = cfis->lba_low;
h2d->lba_mid = cfis->lba_mid;
h2d->lba_high = cfis->lba_high;
h2d->lba_low_exp = cfis->lba_low_exp;
h2d->lba_mid_exp = cfis->lba_mid_exp;
h2d->lba_high_exp = cfis->lba_high_exp;
if (!is_ncq) {
h2d->sector_count = cfis->sector_count;
h2d->sector_count_exp = cfis->sector_count_exp;
} else { /* NCQ */
h2d->sector_count = (u8)(tag << 3);
}
h2d->device = cfis->device;
h2d->control = cfis->control;
/* Setup the PRD table */
prde = (prd_entry_t *)cmd_desc->prdt;
memset((void *)prde, 0, sizeof(struct prdt));
prde_count = 0;
ttl = len;
for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
if (!len)
break;
prde->dba = cpu_to_le32((u32)buffer & ~0x3);
debug("dba = %08x\n\r", (u32)buffer);
if (len < PRD_ENTRY_MAX_XFER_SZ) {
ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
prde_count++;
prde++;
break;
} else {
ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
buffer += PRD_ENTRY_MAX_XFER_SZ;
len -= PRD_ENTRY_MAX_XFER_SZ;
prde_count++;
prde++;
}
}
/* Setup the command slot of cmd hdr */
cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
val32 |= sizeof(sata_fis_h2d_t);
cmd_hdr->prde_fis_len = cpu_to_le32(val32);
cmd_hdr->ttl = cpu_to_le32(ttl);
if (!is_ncq) {
val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
} else {
val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
}
tag &= CMD_HDR_ATTR_TAG;
val32 |= tag;
debug("attribute = %08x\n\r", val32);
cmd_hdr->attribute = cpu_to_le32(val32);
/* Make sure cmd desc and cmd slot valid before commmand issue */
sync();
/* PMP*/
val32 = (u32)(h2d->pm_port_c & 0x0f);
out_le32(®->cqpmp, val32);
/* Wait no active */
if (ata_wait_register(®->car, (1 << tag), 0, 10000))
printf("Wait no active time out\n\r");
/* Issue command */
if (!(in_le32(®->cqr) & (1 << tag))) {
val32 = 1 << tag;
out_le32(®->cqr, val32);
}
/* Wait command completed for 10s */
if (ata_wait_register(®->ccr, (1 << tag), (1 << tag), 10000)) {
if (!is_ncq)
printf("Non-NCQ command time out\n\r");
else
printf("NCQ command time out\n\r");
}
val32 = in_le32(®->cer);
if (val32) {
u32 der;
fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
printf("CE at device\n\r");
fsl_sata_dump_regs(reg);
der = in_le32(®->der);
out_le32(®->cer, val32);
out_le32(®->der, der);
}
/* Clear complete flags */
val32 = in_le32(®->ccr);
out_le32(®->ccr, val32);
return len;
}
static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
int tag, u8 *buffer, u32 len)
{
return 0;
}
static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
enum cmd_type command_type, int tag, u8 *buffer, u32 len)
{
int rc;
if (tag > SATA_HC_MAX_CMD || tag < 0) {
printf("tag is out of range, tag=%d\n\r", tag);
return -1;
}
switch (command_type) {
case CMD_ATA:
rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
return rc;
case CMD_RESET:
rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
return rc;
case CMD_NCQ:
rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
return rc;
case CMD_ATAPI:
case CMD_VENDOR_BIST:
case CMD_BIST:
printf("not support now\n\r");
return -1;
default:
break;
}
return -1;
}
static void fsl_sata_identify(int dev, u16 *id)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
cfis->command = ATA_CMD_ID_ATA;
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
ata_swap_buf_le16(id, ATA_ID_WORDS);
}
static void fsl_sata_xfer_mode(int dev, u16 *id)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
sata->pio = id[ATA_ID_PIO_MODES];
sata->mwdma = id[ATA_ID_MWDMA_MODES];
sata->udma = id[ATA_ID_UDMA_MODES];
debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
}
static void fsl_sata_set_features(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
u8 udma_cap;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
cfis->command = ATA_CMD_SET_FEATURES;
cfis->features = SETFEATURES_XFER;
/* First check the device capablity */
udma_cap = (u8)(sata->udma & 0xff);
debug("udma_cap %02x\n\r", udma_cap);
if (udma_cap == ATA_UDMA6)
cfis->sector_count = XFER_UDMA_6;
if (udma_cap == ATA_UDMA5)
cfis->sector_count = XFER_UDMA_5;
if (udma_cap == ATA_UDMA4)
cfis->sector_count = XFER_UDMA_4;
if (udma_cap == ATA_UDMA3)
cfis->sector_count = XFER_UDMA_3;
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
}
static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
u32 block;
block = start;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
cfis->device = ATA_LBA;
cfis->device |= (block >> 24) & 0xf;
cfis->lba_high = (block >> 16) & 0xff;
cfis->lba_mid = (block >> 8) & 0xff;
cfis->lba_low = block & 0xff;
cfis->sector_count = (u8)(blkcnt & 0xff);
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
return blkcnt;
}
void fsl_sata_flush_cache(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
cfis->command = ATA_CMD_FLUSH;
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
}
static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
u64 block;
block = (u64)start;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
: ATA_CMD_READ_EXT;
cfis->lba_high_exp = (block >> 40) & 0xff;
cfis->lba_mid_exp = (block >> 32) & 0xff;
cfis->lba_low_exp = (block >> 24) & 0xff;
cfis->lba_high = (block >> 16) & 0xff;
cfis->lba_mid = (block >> 8) & 0xff;
cfis->lba_low = block & 0xff;
cfis->device = ATA_LBA;
cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
cfis->sector_count = blkcnt & 0xff;
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
return blkcnt;
}
u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
int ncq_channel;
u64 block;
if (sata->lba48 != 1) {
printf("execute FPDMA command on non-LBA48 hard disk\n\r");
return -1;
}
block = (u64)start;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
: ATA_CMD_FPDMA_READ;
cfis->lba_high_exp = (block >> 40) & 0xff;
cfis->lba_mid_exp = (block >> 32) & 0xff;
cfis->lba_low_exp = (block >> 24) & 0xff;
cfis->lba_high = (block >> 16) & 0xff;
cfis->lba_mid = (block >> 8) & 0xff;
cfis->lba_low = block & 0xff;
cfis->device = ATA_LBA;
cfis->features_exp = (blkcnt >> 8) & 0xff;
cfis->features = blkcnt & 0xff;
if (sata->queue_depth >= SATA_HC_MAX_CMD)
ncq_channel = SATA_HC_MAX_CMD - 1;
else
ncq_channel = sata->queue_depth - 1;
/* Use the latest queue */
fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
return blkcnt;
}
void fsl_sata_flush_cache_ext(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
memset(cfis, 0, sizeof(struct sata_fis_h2d));
cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
cfis->pm_port_c = 0x80; /* is command */
cfis->command = ATA_CMD_FLUSH_EXT;
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
}
/* Software reset, set SRST of the Device Control register */
void fsl_sata_software_reset(int dev)
{
return;
}
static void fsl_sata_init_wcache(int dev, u16 *id)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
sata->wcache = 1;
if (ata_id_has_flush(id))
sata->flush = 1;
if (ata_id_has_flush_ext(id))
sata->flush_ext = 1;
}
static int fsl_sata_get_wcache(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
return sata->wcache;
}
static int fsl_sata_get_flush(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
return sata->flush;
}
static int fsl_sata_get_flush_ext(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
return sata->flush_ext;
}
u32 ata_low_level_rw_lba48(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
int max_blks;
start = blknr;
blks = blkcnt;
addr = (u8 *)buffer;
max_blks = ATA_MAX_SECTORS_LBA48;
do {
if (blks > max_blks) {
if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
else
fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
start += max_blks;
blks -= max_blks;
addr += ATA_SECT_SIZE * max_blks;
} else {
if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
else
fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
start += blks;
blks = 0;
addr += ATA_SECT_SIZE * blks;
}
} while (blks != 0);
return blkcnt;
}
u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
int max_blks;
start = blknr;
blks = blkcnt;
addr = (u8 *)buffer;
max_blks = ATA_MAX_SECTORS;
do {
if (blks > max_blks) {
fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
start += max_blks;
blks -= max_blks;
addr += ATA_SECT_SIZE * max_blks;
} else {
fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
start += blks;
blks = 0;
addr += ATA_SECT_SIZE * blks;
}
} while (blks != 0);
return blkcnt;
}
/*
* SATA interface between low level driver and command layer
*/
ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer)
{
u32 rc;
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
if (sata->lba48)
rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
else
rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
return rc;
}
ulong sata_write(int dev, u32 blknr, u32 blkcnt, void *buffer)
{
u32 rc;
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
if (sata->lba48) {
rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
fsl_sata_flush_cache_ext(dev);
} else {
rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
fsl_sata_flush_cache(dev);
}
return rc;
}
int scan_sata(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
unsigned char serial[ATA_ID_SERNO_LEN + 1];
unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
unsigned char product[ATA_ID_PROD_LEN + 1];
u16 *id;
u64 n_sectors;
/* if no detected link */
if (!sata->link)
return -1;
id = (u16 *)malloc(ATA_ID_WORDS * 2);
if (!id) {
printf("id malloc failed\n\r");
return -1;
}
/* Identify device to get information */
fsl_sata_identify(dev, id);
/* Serial number */
ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
/* Firmware version */
ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
/* Product model */
ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
/* Totoal sectors */
n_sectors = ata_id_n_sectors(id);
sata_dev_desc[dev].lba = (u32)n_sectors;
#ifdef CONFIG_LBA48
/* Check if support LBA48 */
if (ata_id_has_lba48(id)) {
sata->lba48 = 1;
debug("Device support LBA48\n\r");
} else
debug("Device supports LBA28\n\r");
#endif
/* Get the NCQ queue depth from device */
sata->queue_depth = ata_id_queue_depth(id);
/* Get the xfer mode from device */
fsl_sata_xfer_mode(dev, id);
/* Get the write cache status from device */
fsl_sata_init_wcache(dev, id);
/* Set the xfer mode to highest speed */
fsl_sata_set_features(dev);
#ifdef DEBUG
fsl_sata_identify(dev, id);
ata_dump_id(id);
#endif
free((void *)id);
return 0;
}
|
1001-study-uboot
|
drivers/block/fsl_sata.c
|
C
|
gpl3
| 24,618
|
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Author: Tang Yuantian <b29983@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef SATA_SIL3132_H
#define SATA_SIL3132_H
#define READ_CMD 0
#define WRITE_CMD 1
extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
/*
* SATA device driver struct for each dev
*/
struct sil_sata {
char name[12];
void *port; /* the port base address */
int lba48;
u16 pio;
u16 mwdma;
u16 udma;
pci_dev_t devno;
int wcache;
int flush;
int flush_ext;
};
/* sata info for each controller */
struct sata_info {
ulong iobase[3];
pci_dev_t devno;
int portbase;
int maxport;
};
/*
* Scatter gather entry (SGE),MUST 8 bytes aligned
*/
struct sil_sge {
__le64 addr;
__le32 cnt;
__le32 flags;
} __attribute__ ((aligned(8), packed));
/*
* Port request block, MUST 8 bytes aligned
*/
struct sil_prb {
__le16 ctrl;
__le16 prot;
__le32 rx_cnt;
struct sata_fis_h2d fis;
} __attribute__ ((aligned(8), packed));
struct sil_cmd_block {
struct sil_prb prb;
struct sil_sge sge;
};
enum {
HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
HOST_CTRL = 0x40,
HOST_IRQ_STAT = 0x44,
HOST_PHY_CFG = 0x48,
HOST_BIST_CTRL = 0x50,
HOST_BIST_PTRN = 0x54,
HOST_BIST_STAT = 0x58,
HOST_MEM_BIST_STAT = 0x5c,
HOST_FLASH_CMD = 0x70,
/* 8 bit regs */
HOST_FLASH_DATA = 0x74,
HOST_TRANSITION_DETECT = 0x75,
HOST_GPIO_CTRL = 0x76,
HOST_I2C_ADDR = 0x78, /* 32 bit */
HOST_I2C_DATA = 0x7c,
HOST_I2C_XFER_CNT = 0x7e,
HOST_I2C_CTRL = 0x7f,
/* HOST_SLOT_STAT bits */
HOST_SSTAT_ATTN = (1 << 31),
/* HOST_CTRL bits */
HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
/*
* Port registers
* (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
*/
PORT_REGS_SIZE = 0x2000,
PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
PORT_PMP_STATUS = 0x0000, /* port device status offset */
PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
/* 32 bit regs */
PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
PORT_ACTIVATE_UPPER_ADDR = 0x101c,
PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
PORT_CMD_ERR = 0x1024, /* command error number */
PORT_FIS_CFG = 0x1028,
PORT_FIFO_THRES = 0x102c,
/* 16 bit regs */
PORT_DECODE_ERR_CNT = 0x1040,
PORT_DECODE_ERR_THRESH = 0x1042,
PORT_CRC_ERR_CNT = 0x1044,
PORT_CRC_ERR_THRESH = 0x1046,
PORT_HSHK_ERR_CNT = 0x1048,
PORT_HSHK_ERR_THRESH = 0x104a,
/* 32 bit regs */
PORT_PHY_CFG = 0x1050,
PORT_SLOT_STAT = 0x1800,
PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 */
PORT_CONTEXT = 0x1e04,
PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 */
PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 */
PORT_SCONTROL = 0x1f00,
PORT_SSTATUS = 0x1f04,
PORT_SERROR = 0x1f08,
PORT_SACTIVE = 0x1f0c,
/* PORT_CTRL_STAT bits */
PORT_CS_PORT_RST = (1 << 0), /* port reset */
PORT_CS_DEV_RST = (1 << 1), /* device reset */
PORT_CS_INIT = (1 << 2), /* port initialize */
PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
/* PORT_IRQ_STAT/ENABLE_SET/CLR */
/* bits[11:0] are masked */
PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
PORT_IRQ_ERROR = (1 << 1), /* command execution error */
PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
/* bits[27:16] are unmasked (raw) */
PORT_IRQ_RAW_SHIFT = 16,
PORT_IRQ_MASKED_MASK = 0x7ff,
PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
/* ENABLE_SET/CLR specific, intr steering - 2 bit field */
PORT_IRQ_STEER_SHIFT = 30,
PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
/* PORT_CMD_ERR constants */
PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
/* bits of PRB control field */
PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
/* PRB protocol field */
PRB_PROT_PACKET = (1 << 0),
PRB_PROT_TCQ = (1 << 1),
PRB_PROT_NCQ = (1 << 2),
PRB_PROT_READ = (1 << 3),
PRB_PROT_WRITE = (1 << 4),
PRB_PROT_TRANSPARENT = (1 << 5),
/*
* Other constants
*/
SGE_TRM = (1 << 31), /* Last SGE in chain */
SGE_LNK = (1 << 30), /* linked list
Points to SGT, not SGE */
SGE_DRD = (1 << 29), /* discard data read (/dev/null)
data address ignored */
CMD_ERR = 0x21,
};
#endif
|
1001-study-uboot
|
drivers/block/sata_sil.h
|
C
|
gpl3
| 7,180
|
/*
* (C) Copyright 2009 mGine co.
* unsik Kim <donari75@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <part.h>
#include <ata.h>
#include <asm/io.h>
#include "mg_disk_prv.h"
#ifndef CONFIG_MG_DISK_RES
#define CONFIG_MG_DISK_RES 0
#endif
#define MG_RES_SEC ((CONFIG_MG_DISK_RES) << 1)
static struct mg_host host;
static inline u32 mg_base(void)
{
return host.drv_data->base;
}
static block_dev_desc_t mg_disk_dev = {
.if_type = IF_TYPE_ATAPI,
.part_type = PART_TYPE_UNKNOWN,
.type = DEV_TYPE_HARDDISK,
.blksz = MG_SECTOR_SIZE,
.priv = &host };
static void mg_dump_status (const char *msg, unsigned int stat, unsigned err)
{
char *name = MG_DEV_NAME;
printf("%s: %s: status=0x%02x { ", name, msg, stat & 0xff);
if (stat & MG_REG_STATUS_BIT_BUSY)
printf("Busy ");
if (stat & MG_REG_STATUS_BIT_READY)
printf("DriveReady ");
if (stat & MG_REG_STATUS_BIT_WRITE_FAULT)
printf("WriteFault ");
if (stat & MG_REG_STATUS_BIT_SEEK_DONE)
printf("SeekComplete ");
if (stat & MG_REG_STATUS_BIT_DATA_REQ)
printf("DataRequest ");
if (stat & MG_REG_STATUS_BIT_CORRECTED_ERROR)
printf("CorrectedError ");
if (stat & MG_REG_STATUS_BIT_ERROR)
printf("Error ");
printf("}\n");
if ((stat & MG_REG_STATUS_BIT_ERROR)) {
printf("%s: %s: error=0x%02x { ", name, msg, err & 0xff);
if (err & MG_REG_ERR_BBK)
printf("BadSector ");
if (err & MG_REG_ERR_UNC)
printf("UncorrectableError ");
if (err & MG_REG_ERR_IDNF)
printf("SectorIdNotFound ");
if (err & MG_REG_ERR_ABRT)
printf("DriveStatusError ");
if (err & MG_REG_ERR_AMNF)
printf("AddrMarkNotFound ");
printf("}\n");
}
}
static unsigned int mg_wait (u32 expect, u32 msec)
{
u8 status;
u32 from, cur, err;
err = MG_ERR_NONE;
#ifdef CONFIG_SYS_LOW_RES_TIMER
reset_timer();
#endif
from = get_timer(0);
status = readb(mg_base() + MG_REG_STATUS);
do {
cur = get_timer(from);
if (status & MG_REG_STATUS_BIT_BUSY) {
if (expect == MG_REG_STATUS_BIT_BUSY)
break;
} else {
/* Check the error condition! */
if (status & MG_REG_STATUS_BIT_ERROR) {
err = readb(mg_base() + MG_REG_ERROR);
mg_dump_status("mg_wait", status, err);
break;
}
if (expect == MG_STAT_READY)
if (MG_READY_OK(status))
break;
if (expect == MG_REG_STATUS_BIT_DATA_REQ)
if (status & MG_REG_STATUS_BIT_DATA_REQ)
break;
}
status = readb(mg_base() + MG_REG_STATUS);
} while (cur < msec);
if (cur >= msec)
err = MG_ERR_TIMEOUT;
return err;
}
static int mg_get_disk_id (void)
{
u16 id[(MG_SECTOR_SIZE / sizeof(u16))];
hd_driveid_t *iop = (hd_driveid_t *)id;
u32 i, err, res;
writeb(MG_CMD_ID, mg_base() + MG_REG_COMMAND);
err = mg_wait(MG_REG_STATUS_BIT_DATA_REQ, 3000);
if (err)
return err;
for(i = 0; i < (MG_SECTOR_SIZE / sizeof(u16)); i++)
id[i] = readw(mg_base() + MG_BUFF_OFFSET + i * 2);
writeb(MG_CMD_RD_CONF, mg_base() + MG_REG_COMMAND);
err = mg_wait(MG_STAT_READY, 3000);
if (err)
return err;
ata_swap_buf_le16(id, MG_SECTOR_SIZE / sizeof(u16));
if((iop->field_valid & 1) == 0)
return MG_ERR_TRANSLATION;
ata_id_c_string(id, (unsigned char *)mg_disk_dev.revision,
ATA_ID_FW_REV, sizeof(mg_disk_dev.revision));
ata_id_c_string(id, (unsigned char *)mg_disk_dev.vendor,
ATA_ID_PROD, sizeof(mg_disk_dev.vendor));
ata_id_c_string(id, (unsigned char *)mg_disk_dev.product,
ATA_ID_SERNO, sizeof(mg_disk_dev.product));
#ifdef __BIG_ENDIAN
iop->lba_capacity = (iop->lba_capacity << 16) |
(iop->lba_capacity >> 16);
#endif /* __BIG_ENDIAN */
if (MG_RES_SEC) {
MG_DBG("MG_RES_SEC=%d\n", MG_RES_SEC);
iop->cyls = (iop->lba_capacity - MG_RES_SEC) /
iop->sectors / iop->heads;
res = iop->lba_capacity -
iop->cyls * iop->heads * iop->sectors;
iop->lba_capacity -= res;
printf("mg_disk: %d sectors reserved\n", res);
}
mg_disk_dev.lba = iop->lba_capacity;
return MG_ERR_NONE;
}
static int mg_disk_reset (void)
{
struct mg_drv_data *prv_data = host.drv_data;
s32 err;
u8 init_status;
/* hdd rst low */
prv_data->mg_hdrst_pin(0);
err = mg_wait(MG_REG_STATUS_BIT_BUSY, 300);
if(err)
return err;
/* hdd rst high */
prv_data->mg_hdrst_pin(1);
err = mg_wait(MG_STAT_READY, 3000);
if(err)
return err;
/* soft reset on */
writeb(MG_REG_CTRL_RESET | MG_REG_CTRL_INTR_DISABLE,
mg_base() + MG_REG_DRV_CTRL);
err = mg_wait(MG_REG_STATUS_BIT_BUSY, 3000);
if(err)
return err;
/* soft reset off */
writeb(MG_REG_CTRL_INTR_DISABLE, mg_base() + MG_REG_DRV_CTRL);
err = mg_wait(MG_STAT_READY, 3000);
if(err)
return err;
init_status = readb(mg_base() + MG_REG_STATUS) & 0xf;
if (init_status == 0xf)
return MG_ERR_INIT_STAT;
return err;
}
static unsigned int mg_out(unsigned int sect_num,
unsigned int sect_cnt,
unsigned int cmd)
{
u32 err = MG_ERR_NONE;
err = mg_wait(MG_STAT_READY, 3000);
if (err)
return err;
writeb((u8)sect_cnt, mg_base() + MG_REG_SECT_CNT);
writeb((u8)sect_num, mg_base() + MG_REG_SECT_NUM);
writeb((u8)(sect_num >> 8), mg_base() + MG_REG_CYL_LOW);
writeb((u8)(sect_num >> 16), mg_base() + MG_REG_CYL_HIGH);
writeb((u8)((sect_num >> 24) | MG_REG_HEAD_LBA_MODE),
mg_base() + MG_REG_DRV_HEAD);
writeb(cmd, mg_base() + MG_REG_COMMAND);
return err;
}
static unsigned int mg_do_read_sects(void *buff, u32 sect_num, u32 sect_cnt)
{
u32 i, j, err;
u8 *buff_ptr = buff;
union mg_uniwb uniwb;
err = mg_out(sect_num, sect_cnt, MG_CMD_RD);
if (err)
return err;
for (i = 0; i < sect_cnt; i++) {
err = mg_wait(MG_REG_STATUS_BIT_DATA_REQ, 3000);
if (err)
return err;
if ((u32)buff_ptr & 1) {
for (j = 0; j < MG_SECTOR_SIZE >> 1; j++) {
uniwb.w = readw(mg_base() + MG_BUFF_OFFSET
+ (j << 1));
*buff_ptr++ = uniwb.b[0];
*buff_ptr++ = uniwb.b[1];
}
} else {
for(j = 0; j < MG_SECTOR_SIZE >> 1; j++) {
*(u16 *)buff_ptr = readw(mg_base() +
MG_BUFF_OFFSET + (j << 1));
buff_ptr += 2;
}
}
writeb(MG_CMD_RD_CONF, mg_base() + MG_REG_COMMAND);
MG_DBG("%u (0x%8.8x) sector read", sect_num + i,
(sect_num + i) * MG_SECTOR_SIZE);
}
return err;
}
unsigned int mg_disk_read_sects(void *buff, u32 sect_num, u32 sect_cnt)
{
u32 quotient, residue, i, err;
u8 *buff_ptr = buff;
quotient = sect_cnt >> 8;
residue = sect_cnt % 256;
for (i = 0; i < quotient; i++) {
MG_DBG("sect num : %u buff : 0x%8.8x", sect_num, (u32)buff_ptr);
err = mg_do_read_sects(buff_ptr, sect_num, 256);
if (err)
return err;
sect_num += 256;
buff_ptr += 256 * MG_SECTOR_SIZE;
}
if (residue) {
MG_DBG("sect num : %u buff : %8.8x", sect_num, (u32)buff_ptr);
err = mg_do_read_sects(buff_ptr, sect_num, residue);
}
return err;
}
unsigned long mg_block_read (int dev, unsigned long start,
lbaint_t blkcnt, void *buffer)
{
start += MG_RES_SEC;
if (! mg_disk_read_sects(buffer, start, blkcnt))
return blkcnt;
else
return 0;
}
unsigned int mg_disk_read (u32 addr, u8 *buff, u32 len)
{
u8 *sect_buff, *buff_ptr = buff;
u32 cur_addr, next_sec_addr, end_addr, cnt, sect_num;
u32 err = MG_ERR_NONE;
/* TODO : sanity chk */
cnt = 0;
cur_addr = addr;
end_addr = addr + len;
sect_buff = malloc(MG_SECTOR_SIZE);
if (cur_addr & MG_SECTOR_SIZE_MASK) {
next_sec_addr = (cur_addr + MG_SECTOR_SIZE) &
~MG_SECTOR_SIZE_MASK;
sect_num = cur_addr >> MG_SECTOR_SIZE_SHIFT;
err = mg_disk_read_sects(sect_buff, sect_num, 1);
if (err)
goto mg_read_exit;
if (end_addr < next_sec_addr) {
memcpy(buff_ptr,
sect_buff + (cur_addr & MG_SECTOR_SIZE_MASK),
end_addr - cur_addr);
MG_DBG("copies %u byte from sector offset 0x%8.8x",
end_addr - cur_addr, cur_addr);
cur_addr = end_addr;
} else {
memcpy(buff_ptr,
sect_buff + (cur_addr & MG_SECTOR_SIZE_MASK),
next_sec_addr - cur_addr);
MG_DBG("copies %u byte from sector offset 0x%8.8x",
next_sec_addr - cur_addr, cur_addr);
buff_ptr += (next_sec_addr - cur_addr);
cur_addr = next_sec_addr;
}
}
if (cur_addr < end_addr) {
sect_num = cur_addr >> MG_SECTOR_SIZE_SHIFT;
cnt = ((end_addr & ~MG_SECTOR_SIZE_MASK) - cur_addr) >>
MG_SECTOR_SIZE_SHIFT;
if (cnt)
err = mg_disk_read_sects(buff_ptr, sect_num, cnt);
if (err)
goto mg_read_exit;
buff_ptr += cnt * MG_SECTOR_SIZE;
cur_addr += cnt * MG_SECTOR_SIZE;
if (cur_addr < end_addr) {
sect_num = cur_addr >> MG_SECTOR_SIZE_SHIFT;
err = mg_disk_read_sects(sect_buff, sect_num, 1);
if (err)
goto mg_read_exit;
memcpy(buff_ptr, sect_buff, end_addr - cur_addr);
MG_DBG("copies %u byte", end_addr - cur_addr);
}
}
mg_read_exit:
free(sect_buff);
return err;
}
static int mg_do_write_sects(void *buff, u32 sect_num, u32 sect_cnt)
{
u32 i, j, err;
u8 *buff_ptr = buff;
union mg_uniwb uniwb;
err = mg_out(sect_num, sect_cnt, MG_CMD_WR);
if (err)
return err;
for (i = 0; i < sect_cnt; i++) {
err = mg_wait(MG_REG_STATUS_BIT_DATA_REQ, 3000);
if (err)
return err;
if ((u32)buff_ptr & 1) {
uniwb.b[0] = *buff_ptr++;
uniwb.b[1] = *buff_ptr++;
writew(uniwb.w, mg_base() + MG_BUFF_OFFSET + (j << 1));
} else {
for(j = 0; j < MG_SECTOR_SIZE >> 1; j++) {
writew(*(u16 *)buff_ptr,
mg_base() + MG_BUFF_OFFSET +
(j << 1));
buff_ptr += 2;
}
}
writeb(MG_CMD_WR_CONF, mg_base() + MG_REG_COMMAND);
MG_DBG("%u (0x%8.8x) sector write",
sect_num + i, (sect_num + i) * MG_SECTOR_SIZE);
}
return err;
}
unsigned int mg_disk_write_sects(void *buff, u32 sect_num, u32 sect_cnt)
{
u32 quotient, residue, i;
u32 err = MG_ERR_NONE;
u8 *buff_ptr = buff;
quotient = sect_cnt >> 8;
residue = sect_cnt % 256;
for (i = 0; i < quotient; i++) {
MG_DBG("sect num : %u buff : %8.8x", sect_num, (u32)buff_ptr);
err = mg_do_write_sects(buff_ptr, sect_num, 256);
if (err)
return err;
sect_num += 256;
buff_ptr += 256 * MG_SECTOR_SIZE;
}
if (residue) {
MG_DBG("sect num : %u buff : %8.8x", sect_num, (u32)buff_ptr);
err = mg_do_write_sects(buff_ptr, sect_num, residue);
}
return err;
}
unsigned long mg_block_write (int dev, unsigned long start,
lbaint_t blkcnt, const void *buffer)
{
start += MG_RES_SEC;
if (!mg_disk_write_sects((void *)buffer, start, blkcnt))
return blkcnt;
else
return 0;
}
unsigned int mg_disk_write(u32 addr, u8 *buff, u32 len)
{
u8 *sect_buff, *buff_ptr = buff;
u32 cur_addr, next_sec_addr, end_addr, cnt, sect_num;
u32 err = MG_ERR_NONE;
/* TODO : sanity chk */
cnt = 0;
cur_addr = addr;
end_addr = addr + len;
sect_buff = malloc(MG_SECTOR_SIZE);
if (cur_addr & MG_SECTOR_SIZE_MASK) {
next_sec_addr = (cur_addr + MG_SECTOR_SIZE) &
~MG_SECTOR_SIZE_MASK;
sect_num = cur_addr >> MG_SECTOR_SIZE_SHIFT;
err = mg_disk_read_sects(sect_buff, sect_num, 1);
if (err)
goto mg_write_exit;
if (end_addr < next_sec_addr) {
memcpy(sect_buff + (cur_addr & MG_SECTOR_SIZE_MASK),
buff_ptr, end_addr - cur_addr);
MG_DBG("copies %u byte to sector offset 0x%8.8x",
end_addr - cur_addr, cur_addr);
cur_addr = end_addr;
} else {
memcpy(sect_buff + (cur_addr & MG_SECTOR_SIZE_MASK),
buff_ptr, next_sec_addr - cur_addr);
MG_DBG("copies %u byte to sector offset 0x%8.8x",
next_sec_addr - cur_addr, cur_addr);
buff_ptr += (next_sec_addr - cur_addr);
cur_addr = next_sec_addr;
}
err = mg_disk_write_sects(sect_buff, sect_num, 1);
if (err)
goto mg_write_exit;
}
if (cur_addr < end_addr) {
sect_num = cur_addr >> MG_SECTOR_SIZE_SHIFT;
cnt = ((end_addr & ~MG_SECTOR_SIZE_MASK) - cur_addr) >>
MG_SECTOR_SIZE_SHIFT;
if (cnt)
err = mg_disk_write_sects(buff_ptr, sect_num, cnt);
if (err)
goto mg_write_exit;
buff_ptr += cnt * MG_SECTOR_SIZE;
cur_addr += cnt * MG_SECTOR_SIZE;
if (cur_addr < end_addr) {
sect_num = cur_addr >> MG_SECTOR_SIZE_SHIFT;
err = mg_disk_read_sects(sect_buff, sect_num, 1);
if (err)
goto mg_write_exit;
memcpy(sect_buff, buff_ptr, end_addr - cur_addr);
MG_DBG("copies %u byte", end_addr - cur_addr);
err = mg_disk_write_sects(sect_buff, sect_num, 1);
}
}
mg_write_exit:
free(sect_buff);
return err;
}
#ifdef CONFIG_PARTITIONS
block_dev_desc_t *mg_disk_get_dev(int dev)
{
return ((block_dev_desc_t *) & mg_disk_dev);
}
#endif
/* must override this function */
struct mg_drv_data * __attribute__((weak)) mg_get_drv_data (void)
{
puts ("### WARNING ### port mg_get_drv_data function\n");
return NULL;
}
unsigned int mg_disk_init (void)
{
struct mg_drv_data *prv_data;
u32 err = MG_ERR_NONE;
prv_data = mg_get_drv_data();
if (! prv_data) {
printf("%s:%d fail (no driver_data)\n", __func__, __LINE__);
err = MG_ERR_NO_DRV_DATA;
return err;
}
((struct mg_host *)mg_disk_dev.priv)->drv_data = prv_data;
/* init ctrl pin */
if (prv_data->mg_ctrl_pin_init)
prv_data->mg_ctrl_pin_init();
if (! prv_data->mg_hdrst_pin) {
err = MG_ERR_CTRL_RST;
return err;
}
/* disk reset */
err = mg_disk_reset();
if (err) {
printf("%s:%d fail (err code : %d)\n", __func__, __LINE__, err);
return err;
}
/* get disk id */
err = mg_get_disk_id();
if (err) {
printf("%s:%d fail (err code : %d)\n", __func__, __LINE__, err);
return err;
}
mg_disk_dev.block_read = mg_block_read;
mg_disk_dev.block_write = mg_block_write;
init_part(&mg_disk_dev);
dev_print(&mg_disk_dev);
return err;
}
|
1001-study-uboot
|
drivers/block/mg_disk.c
|
C
|
gpl3
| 14,052
|
/*
* Faraday FTIDE020_s ATA Controller (AHB)
*
* (C) Copyright 2011 Andes Technology
* Greentime Hu <greentime@andestech.com>
* Macpaul Lin <macpaul@andestech.com>
* Kuo-Wei Chou <kwchou@andestech.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __FTIDE020_H
#define __FTIDE020_H
/* ftide020.h - ide support functions for the FTIDE020_S controller */
/* ATA controller register offset */
struct ftide020_s {
unsigned int rw_fifo; /* 0x00 - READ/WRITE FIFO */
unsigned int cmd_fifo; /* 0x04 - R: Status Reg, W: CMD_FIFO */
unsigned int cr; /* 0x08 - Control Reg */
unsigned int dmatirr; /* 0x0c - DMA Threshold/Interrupt Reg */
unsigned int ctrd0; /* 0x10 - Command Timing Reg Device 0 */
unsigned int dtrd0; /* 0x14 - Data Timing Reg Device 0 */
unsigned int ctrd1; /* 0x18 - Command Timing Reg Device 1 */
unsigned int dtrd1; /* 0x1c - Data Timing Reg Device 1 */
unsigned int ahbtr; /* 0x20 - AHB Timeout Reg */
unsigned int RESVD0; /* 0x24 */
unsigned int RESVD1; /* 0x28 */
unsigned int RESVD2; /* 0x2c */
unsigned int f_cfifo; /* 0x30 - Feature Info of CMD_FIFO */
unsigned int f_wfifo; /* 0x34 - Feature Info of WRITE_FIFO */
unsigned int f_rfifo; /* 0x3c - Feature Info of READ_FIFO */
unsigned int revision; /* 0x38 - Revision No. of FTIDE020_S */
};
/* reference parameters */
#define CONFIG_IDE_REG_CS 0x2 /* ref: ATA spec chaper 10, table 42 */
#define CONFIG_CTRD1_PROBE_T1 0x2
#define CONFIG_CTRD1_PROBE_T2 0x5
/* status register - 0x04 */
#define STATUS_CSEL (1 << 0) /* CSEL */
#define STATUS_CS(x) (((x) >> 1) & 0x3) /* CS#[1:0] */
#define STATUS_DMACK (1 << 3) /* DMACK# */
#define STATUS_DMARQ (1 << 4) /* DMA req */
#define STATUS_INTRQ (1 << 5) /* INT req */
#define STATUS_DIOR (1 << 6) /* DIOR */
#define STATUS_IORDY (1 << 7) /* I/O ready */
#define STATUS_DIOW (1 << 8) /* DIOW# */
#define STATUS_PDIAG (1 << 9) /* PDIAG */
#define STATUS_DASP (1 << 10) /* DASP# */
#define STATUS_DEV (1 << 11) /* selected device */
#define STATUS_PIO (1 << 12) /* PIO in progress */
#define STATUS_DMA (1 << 13) /* DMA in progress */
#define STATUS_WFE (1 << 14) /* write fifo full */
#define STATUS_RFE (1 << 15) /* read fifo empty */
#define STATUS_COUNTER(x) (((x) >> 16) & 0x3fff) /* data tx counter */
#define STATUS_ERR (1 << 30) /* trasfer terminated */
#define STATUS_AER (1 << 31) /* AHB timeout indicate */
/* Control register - 0x08 */
#define CONTROL_TYPE_PIO 0x0
#define CONTROL_TYPE_UDMA 0x1
/* Device 0 */
#define CONTROL_TYP0(x) (((x) & 0x7) << 0)
#define CONTROL_IRE0 (1 << 3) /* enable IORDY for PIO */
#define CONTROL_RESVD_DW0 (1 << 4) /* Reserved - DW0 ? */
#define CONTROL_E0 (1 << 5) /* E0: 1: Big Endian */
#define CONTROL_RESVD_WP0 (1 << 6) /* Reserved - WP0 ? */
#define CONTROL_RESVD_SE0 (1 << 7) /* Reserved - SE0 ? */
#define CONTROL_RESVD_ECC0 (1 << 8) /* Reserved - ECC0 ? */
#define CONTROL_RAEIE (1 << 9) /* IRQ - read fifo almost full */
#define CONTROL_RNEIE (1 << 10) /* IRQ - read fifo not empty */
#define CONTROL_WAFIE (1 << 11) /* IRQ - write fifo almost empty */
#define CONTROL_WNFIE (1 << 12) /* IRQ - write fifo not full */
#define CONTROL_RESVD_FIRQ (1 << 13) /* RESERVED - FIRQ ? */
#define CONTROL_AERIE (1 << 14) /* IRQ - AHB timeout error */
#define CONTROL_IIE (1 << 15) /* IDE IRQ enable */
/* Device 1 */
#define CONTROL_TYP1(x) (((x) & 0x7) << 16)
#define CONTROL_IRE1 (1 << 19) /* enable IORDY for PIO */
#define CONTROL_RESVD_DW1 (1 << 20) /* Reserved - DW1 ? */
#define CONTROL_E1 (1 << 21) /* E1: 1: Big Endian */
#define CONTROL_RESVD_WP1 (1 << 22) /* Reserved - WP1 ? */
#define CONTROL_RESVD_SE1 (1 << 23) /* Reserved - SE1 ? */
#define CONTROL_RESVD_ECC1 (1 << 24) /* Reserved - ECC1 ? */
#define CONTROL_DRE (1 << 25) /* DMA receive enable */
#define CONTROL_DTE (1 << 26) /* DMA transmit enable */
#define CONTRIL_RESVD (1 << 27)
#define CONTROL_TERIE (1 << 28) /* transfer terminate error IRQ */
#define CONTROL_T (1 << 29) /* terminate current operation */
#define CONTROL_SRST (1 << 30) /* IDE soft reset */
#define CONTROL_RST (1 << 31) /* IDE hardware reset */
/* IRQ register - 0x0c */
#define IRQ_RXTHRESH(x) (((x) & 0x3ff) << 0) /* Read FIFO threshold */
#define IRQ_RFAEIRQ (1 << 10) /* Read FIFO almost full intr req */
#define IRQ_RFNEIRQ (1 << 11) /* Read FIFO not empty intr req */
#define IRQ_WFAFIRQ (1 << 12) /* Write FIFO almost empty int req */
#define IRQ_WFNFIRQ (1 << 13) /* Write FIFO not full intr req */
#define IRQ_RESVD_FIRQ (1 << 14) /* Reserved - FIRQ ? */
#define IRQ_IIRQ (1 << 15) /* IDE device interrupt request */
#define IRQ_TXTHRESH(x) (((x) & 0x3ff) << 16) /* Write FIFO thershold */
#define IRQ_TERMERR (1 << 28) /* Transfer termination indication */
#define IRQ_AHBERR (1 << 29) /* AHB Timeout indication */
/* Command Timing Register 0-1: ctrd (0x10, 0x18) */
#define CT_REG_T1(x) (((x) & 0xff) << 0) /* setup time of addressed */
#define CT_REG_T2(x) (((x) & 0xff) << 8) /* pluse width of DIOR/DIOW */
#define CT_REG_T4(x) (((x) & 0xff) << 16) /* data hold time */
#define CT_REG_TEOC(x) (((x) & 0xff) << 24) /* time to the end of a cycle */
/* Data Timing Register 0-1: dtrd (0x14, 0x1c) */
/*
* PIO mode:
* b(0:7) DT_REG_PIO_T1: the setup time of addressed
* b(8:15) DT_REG_PIO_T2: the pluse width of DIOR/DIOW
* b(16:23) DT_REG_PIO_T4: data hold time
* b(24:31) DT_REG_PIO_TEOC: the time to the end of a cycle
*/
#define DT_REG_PIO_T1(x) (((x) & 0xff) << 0)
#define DT_REG_PIO_T2(x) (((x) & 0xff) << 8)
#define DT_REG_PIO_T4(x) (((x) & 0xff) << 16)
#define DT_REG_PIO_TEOC(x) (((x) & 0xff) << 24)
/*
* UDMA mode:
* b(0:3) DT_REG_UDMA_TENV: the envelope time
* b(4:7) DT_REG_UDMA_TMLI: interlock time
* b(8:15) DT_REG_UDMA_TCYC: cycle time - data time
* b(16:19) DT_REG_UDMA_TACK: setup and hold time of DMACK
* b(23:30) DT_REG_UDMA_TCVS: setup time of CRC
* b(24:31) DT_REG_UDMA_TRP: time to ready to pause
*/
#define DT_REG_UDMA_TENV(x) (((x) & 0xf) << 0)
#define DT_REG_UDMA_TMLI(x) (((x) & 0xf) << 4)
#define DT_REG_UDMA_TCYC(x) (((x) & 0xff) << 8)
#define DT_REG_UDMA_TACK(x) (((x) & 0xf) << 16)
#define DT_REG_UDMA_TCVS(x) (((x) & 0xf) << 20)
#define DT_REG_UDMA_TRP(x) (((x) & 0xff) << 24)
/* ftide020_s command formats */
/* read: IDE Register (CF1) */
#define IDE_REG_OPCODE_READ (1 << 13) /* 0x2000 */
#define IDE_REG_CS_READ(x) (((x) & 0x3) << 11)
#define IDE_REG_DA_READ(x) (((x) & 0x7) << 8)
#define IDE_REG_CMD_READ(x) 0x0 /* fixed value */
/* write: IDE Register (CF2) */
#define IDE_REG_OPCODE_WRITE (0x5 << 13) /* 0xA000 */
#define IDE_REG_CS_WRITE(x) (((x) & 0x3) << 11)
#define IDE_REG_DA_WRITE(x) (((x) & 0x7) << 8)
/* b(0:7) IDE_REG_CMD_WRITE(x): Actual ATA command or data */
#define IDE_REG_CMD_WRITE(x) (((x) & 0xff) << 0)
/* read/write data: PIO/UDMA (CF3) */
#define IDE_DATA_WRITE (1 << 15) /* read: 0, write: 1 */
#define IDE_DATA_OPCODE (0x2 << 13) /* device data access opcode */
/* b(0:12) IDE_DATA_COUNTER(x): Number of transfers minus 1 */
#define IDE_DATA_COUNTER(x) (((x) & 0x1fff) << 0)
/* set device: (CF4) */
#define IDE_SET_OPCODE (0x2740 << 2) /* [15:2], 0x9d00 */
/* CF3 counter value: 0: Tx in bytes, 1: in blocks (each block is 8 bytes) */
#define IDE_SET_CX8(x) (((x) & 0x1) << 1)
#define IDE_SET_DEV(x) (((x) & 0x1) << 0) /* 0: Master, 1: Slave */
/*
* IDE command bit definition
* This section is designed for minor hardware revision compatibility.
*/
#define READ_REG_CMD IDE_REG_OPCODE_READ /* 0x2000 */
#define WRITE_REG_CMD IDE_REG_OPCODE_WRITE /* 0xA000 */
#define READ_DATA_CMD IDE_DATA_OPCODE /* 0x4000 */
#define WRITE_DATA_CMD (IDE_DATA_OPCODE | IDE_DATA_WRITE) /* 0xC000 */
#define SET_DEV_CMD IDE_SET_OPCODE /* 0x9D00 */
#define TATOL_TIMING 3
#define CMD_TIMING 0
#define PIO_TIMING 1
#define DMA_TIMING 2
/* Timing Parameters */
/* Register Access Timing Parameters */
#define REG_PARAMETER 4
#define REG_T0 0
#define REG_T1 1
#define REG_T2 2
#define REG_T4 3
#define REG_MODE 5
#define REG_MODE0 0
#define REG_MODE1 1
#define REG_MODE2 2
#define REG_MODE3 3
#define REG_MODE4 4
/* PIO Access Timing Parameters */
#define PIO_PARAMETER 4
#define PIO_T0 0
#define PIO_T1 1
#define PIO_T2 2
#define PIO_T4 3
#define PIO_MODE 5
#define PIO_MODE0 0
#define PIO_MODE1 1
#define PIO_MODE2 2
#define PIO_MODE3 3
#define PIO_MODE4 4
/* UDMA Access Timing Parameters */
#define UDMA_PARAMETER 6
#define UDMA_TCYC 0
#define UDMA_TCVS 1
#define UDMA_TMLI 2
#define UDMA_TENV 3
#define UDMA_TRP 4
#define UDMA_TACK 5
#define UDMA_MODE 7
#define UDMA_MODE0 0
#define UDMA_MODE1 1
#define UDMA_MODE2 2
#define UDMA_MODE3 3
#define UDMA_MODE4 4
#define UDMA_MODE5 5
#define UDMA_MODE6 6
/*
* RX_THRESH:
* hardware limitation: max = 8, should support 1,4,8,16,32,64,128,256
*/
#define RX_THRESH 8
#define WRITE_FIFO 32 /* Hardwired value */
/* Time Table */
unsigned int REG_ACCESS_TIMING[REG_PARAMETER][REG_MODE] = {
{600, 383, 330, 180, 120},
{70, 50, 30, 30, 25},
{290, 290, 290, 80, 70},
{30, 20, 15, 10, 10},
};
unsigned int PIO_ACCESS_TIMING[PIO_PARAMETER][PIO_MODE] = {
{600, 383, 240, 180, 120},
{70, 50, 30, 30, 25},
{165, 125, 100, 80, 70},
{30, 20, 15, 10, 10},
};
unsigned int UDMA_ACCESS_TIMING[UDMA_PARAMETER][UDMA_MODE] = {
{1120, 730, 540, 390, 250, 168, 130}, /* 10X */
{700, 480, 310, 200, 67, 100, 100}, /* 10X */
{200, 200, 200, 200, 200, 200, 200}, /* 10X */
{200, 200, 200, 200, 200, 200, 200}, /* 10X */
{1600, 1250, 1000, 1000, 1000, 850, 850}, /* 10X */
{200, 200, 200, 200, 200, 200, 200}, /* 10X */
};
#endif /* __FTIDE020_H */
|
1001-study-uboot
|
drivers/block/ftide020.h
|
C
|
gpl3
| 10,399
|
/*
* (C) Copyright 2007
* Gary Jennejohn, DENX Software Engineering, garyj@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/* sil680.c - ide support functions for the Sil0680A controller */
/*
* The following parameters must be defined in the configuration file
* of the target board:
*
* #define CONFIG_IDE_SIL680
*
* #define CONFIG_PCI_PNP
* NOTE it may also be necessary to define this if the default of 8 is
* incorrect for the target board (e.g. the sequoia board requires 0).
* #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0
*
* #define CONFIG_CMD_IDE
* #undef CONFIG_IDE_8xx_DIRECT
* #undef CONFIG_IDE_LED
* #undef CONFIG_IDE_RESET
* #define CONFIG_IDE_PREINIT
* #define CONFIG_SYS_IDE_MAXBUS 2 - modify to suit
* #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) - modify to suit
* #define CONFIG_SYS_ATA_BASE_ADDR 0
* #define CONFIG_SYS_ATA_IDE0_OFFSET 0
* #define CONFIG_SYS_ATA_IDE1_OFFSET 0
* #define CONFIG_SYS_ATA_DATA_OFFSET 0
* #define CONFIG_SYS_ATA_REG_OFFSET 0
* #define CONFIG_SYS_ATA_ALT_OFFSET 0x0004
*
* The mapping for PCI IO-space.
* NOTE this is the value for the sequoia board. Modify to suit.
* #define CONFIG_SYS_PCI0_IO_SPACE 0xE8000000
*/
#include <common.h>
#include <ata.h>
#include <ide.h>
#include <pci.h>
extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
int ide_preinit (void)
{
int status;
pci_dev_t devbusfn;
int l;
status = 1;
for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
ide_bus_offset[l] = -ATA_STATUS;
}
devbusfn = pci_find_device (0x1095, 0x0680, 0);
if (devbusfn != -1) {
status = 0;
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
(u32 *) &ide_bus_offset[0]);
ide_bus_offset[0] &= 0xfffffff8;
ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
(u32 *) &ide_bus_offset[1]);
ide_bus_offset[1] &= 0xfffffff8;
ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
/* init various things - taken from the Linux driver */
/* set PIO mode */
pci_write_config_byte(devbusfn, 0x80, 0x00);
pci_write_config_byte(devbusfn, 0x84, 0x00);
/* IDE0 */
pci_write_config_byte(devbusfn, 0xA1, 0x02);
pci_write_config_word(devbusfn, 0xA2, 0x328A);
pci_write_config_dword(devbusfn, 0xA4, 0x62DD62DD);
pci_write_config_dword(devbusfn, 0xA8, 0x43924392);
pci_write_config_dword(devbusfn, 0xAC, 0x40094009);
/* IDE1 */
pci_write_config_byte(devbusfn, 0xB1, 0x02);
pci_write_config_word(devbusfn, 0xB2, 0x328A);
pci_write_config_dword(devbusfn, 0xB4, 0x62DD62DD);
pci_write_config_dword(devbusfn, 0xB8, 0x43924392);
pci_write_config_dword(devbusfn, 0xBC, 0x40094009);
}
return (status);
}
void ide_set_reset (int flag) {
return;
}
|
1001-study-uboot
|
drivers/block/sil680.c
|
C
|
gpl3
| 3,496
|
/*
* Copyright (C) 2007-2008 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FSL_SATA_H__
#define __FSL_SATA_H__
#define SATA_HC_MAX_NUM 4 /* Max host controller numbers */
#define SATA_HC_MAX_CMD 16 /* Max command queue depth per host controller */
#define SATA_HC_MAX_PORT 16 /* Max port number per host controller */
/*
* SATA Host Controller Registers
*/
typedef struct fsl_sata_reg {
/* SATA command registers */
u32 cqr; /* Command queue register */
u8 res1[0x4];
u32 car; /* Command active register */
u8 res2[0x4];
u32 ccr; /* Command completed register */
u8 res3[0x4];
u32 cer; /* Command error register */
u8 res4[0x4];
u32 der; /* Device error register */
u32 chba; /* Command header base address */
u32 hstatus; /* Host status register */
u32 hcontrol; /* Host control register */
u32 cqpmp; /* Port number queue register */
u32 sig; /* Signature register */
u32 icc; /* Interrupt coalescing control register */
u8 res5[0xc4];
/* SATA supperset registers */
u32 sstatus; /* SATA interface status register */
u32 serror; /* SATA interface error register */
u32 scontrol; /* SATA interface control register */
u32 snotification; /* SATA interface notification register */
u8 res6[0x30];
/* SATA control status registers */
u32 transcfg; /* Transport layer configuration */
u32 transstatus; /* Transport layer status */
u32 linkcfg; /* Link layer configuration */
u32 linkcfg1; /* Link layer configuration1 */
u32 linkcfg2; /* Link layer configuration2 */
u32 linkstatus; /* Link layer status */
u32 linkstatus1; /* Link layer status1 */
u32 phyctrlcfg; /* PHY control configuration */
u8 res7[0x2b0];
/* SATA system control registers */
u32 syspr; /* System priority register - big endian */
u8 res8[0xbec];
} __attribute__ ((packed)) fsl_sata_reg_t;
/* HStatus register
*/
#define HSTATUS_ONOFF 0x80000000 /* Online/offline status */
#define HSTATUS_FORCE_OFFLINE 0x40000000 /* In process going offline */
#define HSTATUS_BIST_ERR 0x20000000
/* Fatal error */
#define HSTATUS_MASTER_ERR 0x00004000
#define HSTATUS_DATA_UNDERRUN 0x00002000
#define HSTATUS_DATA_OVERRUN 0x00001000
#define HSTATUS_CRC_ERR_TX 0x00000800
#define HSTATUS_CRC_ERR_RX 0x00000400
#define HSTATUS_FIFO_OVERFLOW_TX 0x00000200
#define HSTATUS_FIFO_OVERFLOW_RX 0x00000100
#define HSTATUS_FATAL_ERR_ALL (HSTATUS_MASTER_ERR | \
HSTATUS_DATA_UNDERRUN | \
HSTATUS_DATA_OVERRUN | \
HSTATUS_CRC_ERR_TX | \
HSTATUS_CRC_ERR_RX | \
HSTATUS_FIFO_OVERFLOW_TX | \
HSTATUS_FIFO_OVERFLOW_RX)
/* Interrupt status */
#define HSTATUS_FATAL_ERR 0x00000020
#define HSTATUS_PHY_RDY 0x00000010
#define HSTATUS_SIGNATURE 0x00000008
#define HSTATUS_SNOTIFY 0x00000004
#define HSTATUS_DEVICE_ERR 0x00000002
#define HSTATUS_CMD_COMPLETE 0x00000001
/* HControl register
*/
#define HCONTROL_ONOFF 0x80000000 /* Online or offline request */
#define HCONTROL_FORCE_OFFLINE 0x40000000 /* Force offline request */
#define HCONTROL_ENTERPRISE_EN 0x10000000 /* Enterprise mode enabled */
#define HCONTROL_HDR_SNOOP 0x00000400 /* Command header snoop */
#define HCONTROL_PMP_ATTACHED 0x00000200 /* Port multiplier attached */
/* Interrupt enable */
#define HCONTROL_FATAL_ERR 0x00000020
#define HCONTROL_PHY_RDY 0x00000010
#define HCONTROL_SIGNATURE 0x00000008
#define HCONTROL_SNOTIFY 0x00000004
#define HCONTROL_DEVICE_ERR 0x00000002
#define HCONTROL_CMD_COMPLETE 0x00000001
#define HCONTROL_INT_EN_ALL (HCONTROL_FATAL_ERR | \
HCONTROL_PHY_RDY | \
HCONTROL_SIGNATURE | \
HCONTROL_SNOTIFY | \
HCONTROL_DEVICE_ERR | \
HCONTROL_CMD_COMPLETE)
/* SStatus register
*/
#define SSTATUS_IPM_MASK 0x00000780
#define SSTATUS_IPM_NOPRESENT 0x00000000
#define SSTATUS_IPM_ACTIVE 0x00000080
#define SSTATUS_IPM_PATIAL 0x00000100
#define SSTATUS_IPM_SLUMBER 0x00000300
#define SSTATUS_SPD_MASK 0x000000f0
#define SSTATUS_SPD_GEN1 0x00000010
#define SSTATUS_SPD_GEN2 0x00000020
#define SSTATUS_DET_MASK 0x0000000f
#define SSTATUS_DET_NODEVICE 0x00000000
#define SSTATUS_DET_DISCONNECT 0x00000001
#define SSTATUS_DET_CONNECT 0x00000003
#define SSTATUS_DET_PHY_OFFLINE 0x00000004
/* SControl register
*/
#define SCONTROL_SPM_MASK 0x0000f000
#define SCONTROL_SPM_GO_PARTIAL 0x00001000
#define SCONTROL_SPM_GO_SLUMBER 0x00002000
#define SCONTROL_SPM_GO_ACTIVE 0x00004000
#define SCONTROL_IPM_MASK 0x00000f00
#define SCONTROL_IPM_NO_RESTRICT 0x00000000
#define SCONTROL_IPM_PARTIAL 0x00000100
#define SCONTROL_IPM_SLUMBER 0x00000200
#define SCONTROL_IPM_PART_SLUM 0x00000300
#define SCONTROL_SPD_MASK 0x000000f0
#define SCONTROL_SPD_NO_RESTRICT 0x00000000
#define SCONTROL_SPD_GEN1 0x00000010
#define SCONTROL_SPD_GEN2 0x00000020
#define SCONTROL_DET_MASK 0x0000000f
#define SCONTROL_DET_HRESET 0x00000001
#define SCONTROL_DET_DISABLE 0x00000004
/* TransCfg register
*/
#define TRANSCFG_DFIS_SIZE_SHIFT 16
#define TRANSCFG_RX_WATER_MARK_MASK 0x0000001f
/* PhyCtrlCfg register
*/
#define PHYCTRLCFG_FPRFTI_MASK 0x00000018
#define PHYCTRLCFG_LOOPBACK_MASK 0x0000000e
/*
* Command Header Entry
*/
typedef struct cmd_hdr_entry {
u32 cda; /* Command Descriptor Address, 4 bytes aligned */
u32 prde_fis_len; /* Number of PRD entries and FIS length */
u32 ttl; /* Total transfer length */
u32 attribute; /* the attribute of command */
} __attribute__ ((packed)) cmd_hdr_entry_t;
#define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry)
/* cda
*/
#define CMD_HDR_CDA_ALIGN 4
/* prde_fis_len
*/
#define CMD_HDR_PRD_ENTRY_SHIFT 16
#define CMD_HDR_PRD_ENTRY_MASK 0x003f0000
#define CMD_HDR_FIS_LEN_SHIFT 2
/* attribute
*/
#define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */
#define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */
#define CMD_HDR_ATTR_SNOOP 0x00000200 /* Snoop enable for all descriptor */
#define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */
#define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */
#define CMD_HDR_ATTR_BIST 0x00000040 /* BIST - require the host to enter BIST mode */
#define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */
#define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */
/* command type
*/
enum cmd_type {
CMD_VENDOR_BIST,
CMD_BIST,
CMD_RESET, /* SRST or device reset */
CMD_ATAPI,
CMD_NCQ,
CMD_ATA, /* None of all above */
};
/*
* Command Header Table
*/
typedef struct cmd_hdr_tbl {
cmd_hdr_entry_t cmd_slot[SATA_HC_MAX_CMD];
} __attribute__ ((packed)) cmd_hdr_tbl_t;
#define SATA_HC_CMD_HDR_TBL_SIZE sizeof(struct cmd_hdr_tbl)
#define SATA_HC_CMD_HDR_TBL_ALIGN 4
/*
* PRD entry - Physical Region Descriptor entry
*/
typedef struct prd_entry {
u32 dba; /* Data base address, 4 bytes aligned */
u32 res1;
u32 res2;
u32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */
} __attribute__ ((packed)) prd_entry_t;
#define SATA_HC_CMD_DESC_PRD_SIZE sizeof(struct prd_entry)
/* dba
*/
#define PRD_ENTRY_DBA_ALIGN 4
/* ext_c_ddc
*/
#define PRD_ENTRY_EXT 0x80000000 /* extension flag */
#ifdef CONFIG_FSL_SATA_V2
#define PRD_ENTRY_DATA_SNOOP 0x10000000 /* Data snoop enable */
#else
#define PRD_ENTRY_DATA_SNOOP 0x00400000 /* Data snoop enable */
#endif
#define PRD_ENTRY_LEN_MASK 0x003fffff /* Data word count */
#define PRD_ENTRY_MAX_XFER_SZ (PRD_ENTRY_LEN_MASK + 1)
/*
* This SATA host controller supports a max of 16 direct PRD entries, but if use
* chained indirect PRD entries, then the contollers supports upto a max of 63
* entries including direct and indirect PRD entries.
* The PRDT is an array of 63 PRD entries contigiously, but the PRD entries#15
* will be setup as an indirect descriptor, pointing to it's next (contigious)
* PRD entries#16.
*/
#define SATA_HC_MAX_PRD 63 /* Max PRD entry numbers per command */
#define SATA_HC_MAX_PRD_DIRECT 16 /* Direct PRDT entries */
#define SATA_HC_MAX_PRD_USABLE (SATA_HC_MAX_PRD - 1)
#define SATA_HC_MAX_XFER_LEN 0x4000000
/*
* PRDT - Physical Region Descriptor Table
*/
typedef struct prdt {
prd_entry_t prdt[SATA_HC_MAX_PRD];
} __attribute__ ((packed)) prdt_t;
/*
* Command Descriptor
*/
#define SATA_HC_CMD_DESC_CFIS_SIZE 32 /* bytes */
#define SATA_HC_CMD_DESC_SFIS_SIZE 32 /* bytes */
#define SATA_HC_CMD_DESC_ACMD_SIZE 16 /* bytes */
#define SATA_HC_CMD_DESC_RES 16 /* bytes */
typedef struct cmd_desc {
u8 cfis[SATA_HC_CMD_DESC_CFIS_SIZE];
u8 sfis[SATA_HC_CMD_DESC_SFIS_SIZE];
u8 acmd[SATA_HC_CMD_DESC_ACMD_SIZE];
u8 res[SATA_HC_CMD_DESC_RES];
prd_entry_t prdt[SATA_HC_MAX_PRD];
} __attribute__ ((packed)) cmd_desc_t;
#define SATA_HC_CMD_DESC_SIZE sizeof(struct cmd_desc)
#define SATA_HC_CMD_DESC_ALIGN 4
/*
* SATA device driver info
*/
typedef struct fsl_sata_info {
u32 sata_reg_base;
u32 flags;
} fsl_sata_info_t;
#define FLAGS_DMA 0x00000000
#define FLAGS_FPDMA 0x00000001
/*
* SATA device driver struct
*/
typedef struct fsl_sata {
char name[12];
fsl_sata_reg_t *reg_base; /* the base address of controller register */
void *cmd_hdr_tbl_offset; /* alloc address of command header table */
cmd_hdr_tbl_t *cmd_hdr; /* aligned address of command header table */
void *cmd_desc_offset; /* alloc address of command descriptor */
cmd_desc_t *cmd_desc; /* aligned address of command descriptor */
int link; /* PHY link status */
/* device attribute */
int ata_device_type; /* device type */
int lba48;
int queue_depth; /* Max NCQ queue depth */
u16 pio;
u16 mwdma;
u16 udma;
int wcache;
int flush;
int flush_ext;
} fsl_sata_t;
#define READ_CMD 0
#define WRITE_CMD 1
#endif /* __FSL_SATA_H__ */
|
1001-study-uboot
|
drivers/block/fsl_sata.h
|
C
|
gpl3
| 10,316
|
#ifndef __ATA_PIIX_H__
#define __ATA_PIIX_H__
#if (DEBUG_SATA)
#define PRINTF(fmt,args...) printf (fmt ,##args)
#else
#define PRINTF(fmt,args...)
#endif
struct sata_ioports {
unsigned long cmd_addr;
unsigned long data_addr;
unsigned long error_addr;
unsigned long feature_addr;
unsigned long nsect_addr;
unsigned long lbal_addr;
unsigned long lbam_addr;
unsigned long lbah_addr;
unsigned long device_addr;
unsigned long status_addr;
unsigned long command_addr;
unsigned long altstatus_addr;
unsigned long ctl_addr;
unsigned long bmdma_addr;
unsigned long scr_addr;
};
struct sata_port {
unsigned char port_no; /* primary=0, secondary=1 */
struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
unsigned char ctl_reg;
unsigned char last_ctl;
unsigned char port_state; /* 1-port is available and */
/* 0-port is not available */
unsigned char dev_mask;
};
/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
#ifdef SATA_DECL /*SATA library specific declarations */
inline void
ata_dump_id (u16 * id)
{
PRINTF ("49 = 0x%04x "
"53 = 0x%04x "
"63 = 0x%04x "
"64 = 0x%04x "
"75 = 0x%04x \n", id[49], id[53], id[63], id[64], id[75]);
PRINTF ("80 = 0x%04x "
"81 = 0x%04x "
"82 = 0x%04x "
"83 = 0x%04x "
"84 = 0x%04x \n", id[80], id[81], id[82], id[83], id[84]);
PRINTF ("88 = 0x%04x " "93 = 0x%04x\n", id[88], id[93]);
}
#endif
#ifdef SATA_DECL /*SATA library specific declarations */
int sata_bus_softreset (int num);
void sata_identify (int num, int dev);
void sata_port (struct sata_ioports *ioport);
void set_Feature_cmd (int num, int dev);
int sata_devchk (struct sata_ioports *ioaddr, int dev);
void dev_select (struct sata_ioports *ioaddr, int dev);
u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max);
u8 sata_chk_status (struct sata_ioports *ioaddr);
ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer);
ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer);
void msleep (int count);
#endif
/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/
#ifdef DRV_DECL /*Driver specific declaration */
int init_sata (int dev);
#endif
#ifdef DRV_DECL /*Defines Driver Specific variables */
struct sata_port port[CONFIG_SYS_SATA_MAXBUS];
#endif
#endif /* __ATA_PIIX_H__ */
|
1001-study-uboot
|
drivers/block/ata_piix.h
|
C
|
gpl3
| 2,350
|
/* ax88180.h: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver */
/*
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
*/
#ifndef _AX88180_H_
#define _AX88180_H_
#include <asm/io.h>
#include <asm/types.h>
#include <config.h>
typedef enum _ax88180_link_state {
INS_LINK_DOWN,
INS_LINK_UP,
INS_LINK_UNKNOWN
} ax88180_link_state;
struct ax88180_private {
unsigned char BusWidth;
unsigned char PadSize;
unsigned short PhyAddr;
unsigned short PhyID0;
unsigned short PhyID1;
unsigned short FirstTxDesc;
unsigned short NextTxDesc;
ax88180_link_state LinkState;
};
#define BUS_WIDTH_16 1
#define BUS_WIDTH_32 2
#define ENABLE_JUMBO 1
#define DISABLE_JUMBO 0
#define ENABLE_BURST 1
#define DISABLE_BURST 0
#define NORMAL_RX_MODE 0
#define RX_LOOPBACK_MODE 1
#define RX_INIFINIT_LOOP_MODE 2
#define TX_INIFINIT_LOOP_MODE 3
#define DEFAULT_ETH_MTU 1500
/* Jumbo packet size 4086 bytes included 4 bytes CRC*/
#define MAX_JUMBO_MTU 4072
/* Max Tx Jumbo size 4086 bytes included 4 bytes CRC */
#define MAX_TX_JUMBO_SIZE 4086
/* Max Rx Jumbo size is 15K Bytes */
#define MAX_RX_SIZE 0x3C00
#define MARVELL_ALASKA_PHYSID0 0x141
#define MARVELL_88E1118_PHYSID1 0xE40
#define CICADA_CIS8201_PHYSID0 0x000F
#define MEDIA_AUTO 0
#define MEDIA_1000FULL 1
#define MEDIA_1000HALF 2
#define MEDIA_100FULL 3
#define MEDIA_100HALF 4
#define MEDIA_10FULL 5
#define MEDIA_10HALF 6
#define MEDIA_UNKNOWN 7
#define AUTO_MEDIA 0
#define FORCE_MEDIA 1
#define TXDP_MASK 3
#define TXDP0 0
#define TXDP1 1
#define TXDP2 2
#define TXDP3 3
#define CMD_MAP_SIZE 0x100
#if defined (CONFIG_DRIVER_AX88180_16BIT)
#define AX88180_MEMORY_SIZE 0x00004000
#define START_BASE 0x1000
#define RX_BUF_SIZE 0x1000
#define TX_BUF_SIZE 0x0F00
#define TX_BASE START_BASE
#define CMD_BASE (TX_BASE + TX_BUF_SIZE)
#define RX_BASE (CMD_BASE + CMD_MAP_SIZE)
#else
#define AX88180_MEMORY_SIZE 0x00010000
#define RX_BUF_SIZE 0x8000
#define TX_BUF_SIZE 0x7C00
#define RX_BASE 0x0000
#define TX_BASE (RX_BASE + RX_BUF_SIZE)
#define CMD_BASE (TX_BASE + TX_BUF_SIZE)
#endif
/* AX88180 Memory Mapping Definition */
#define RXBUFFER_START RX_BASE
#define RX_PACKET_LEN_OFFSET 0
#define RX_PAGE_NUM_MASK 0x7FF /* RX pages 0~7FFh */
#define TXBUFFER_START TX_BASE
/* AX88180 MAC Register Definition */
#define DECODE (0)
#define DECODE_EN 0x00000001
#define BASE (6)
#define CMD (CMD_BASE + 0x0000)
#define WAKEMOD 0x00000001
#define TXEN 0x00000100
#define RXEN 0x00000200
#define DEFAULT_CMD WAKEMOD
#define IMR (CMD_BASE + 0x0004)
#define IMR_RXBUFFOVR 0x00000001
#define IMR_WATCHDOG 0x00000002
#define IMR_TX 0x00000008
#define IMR_RX 0x00000010
#define IMR_PHY 0x00000020
#define CLEAR_IMR 0x00000000
#define DEFAULT_IMR (IMR_PHY | IMR_RX | IMR_TX |\
IMR_RXBUFFOVR | IMR_WATCHDOG)
#define ISR (CMD_BASE + 0x0008)
#define ISR_RXBUFFOVR 0x00000001
#define ISR_WATCHDOG 0x00000002
#define ISR_TX 0x00000008
#define ISR_RX 0x00000010
#define ISR_PHY 0x00000020
#define TXCFG (CMD_BASE + 0x0010)
#define AUTOPAD_CRC 0x00000050
#define DEFAULT_TXCFG AUTOPAD_CRC
#define TXCMD (CMD_BASE + 0x0014)
#define TXCMD_TXDP_MASK 0x00006000
#define TXCMD_TXDP0 0x00000000
#define TXCMD_TXDP1 0x00002000
#define TXCMD_TXDP2 0x00004000
#define TXCMD_TXDP3 0x00006000
#define TX_START_WRITE 0x00008000
#define TX_STOP_WRITE 0x00000000
#define DEFAULT_TXCMD 0x00000000
#define TXBS (CMD_BASE + 0x0018)
#define TXDP0_USED 0x00000001
#define TXDP1_USED 0x00000002
#define TXDP2_USED 0x00000004
#define TXDP3_USED 0x00000008
#define DEFAULT_TXBS 0x00000000
#define TXDES0 (CMD_BASE + 0x0020)
#define TXDPx_ENABLE 0x00008000
#define TXDPx_LEN_MASK 0x00001FFF
#define DEFAULT_TXDES0 0x00000000
#define TXDES1 (CMD_BASE + 0x0024)
#define TXDPx_ENABLE 0x00008000
#define TXDPx_LEN_MASK 0x00001FFF
#define DEFAULT_TXDES1 0x00000000
#define TXDES2 (CMD_BASE + 0x0028)
#define TXDPx_ENABLE 0x00008000
#define TXDPx_LEN_MASK 0x00001FFF
#define DEFAULT_TXDES2 0x00000000
#define TXDES3 (CMD_BASE + 0x002C)
#define TXDPx_ENABLE 0x00008000
#define TXDPx_LEN_MASK 0x00001FFF
#define DEFAULT_TXDES3 0x00000000
#define RXCFG (CMD_BASE + 0x0030)
#define RXBUFF_PROTECT 0x00000001
#define RXTCPCRC_CHECK 0x00000010
#define RXFLOW_ENABLE 0x00000100
#define DEFAULT_RXCFG RXBUFF_PROTECT
#define RXCURT (CMD_BASE + 0x0034)
#define DEFAULT_RXCURT 0x00000000
#define RXBOUND (CMD_BASE + 0x0038)
#define DEFAULT_RXBOUND 0x7FF /* RX pages 0~7FFh */
#define MACCFG0 (CMD_BASE + 0x0040)
#define MACCFG0_BIT3_0 0x00000007
#define IPGT_VAL 0x00000150
#define TXFLOW_ENABLE 0x00001000
#define SPEED100 0x00008000
#define DEFAULT_MACCFG0 (IPGT_VAL | MACCFG0_BIT3_0)
#define MACCFG1 (CMD_BASE + 0x0044)
#define RGMII_EN 0x00000002
#define RXFLOW_EN 0x00000020
#define FULLDUPLEX 0x00000040
#define MAX_JUMBO_LEN 0x00000780
#define RXJUMBO_EN 0x00000800
#define GIGA_MODE_EN 0x00001000
#define RXCRC_CHECK 0x00002000
#define RXPAUSE_DA_CHECK 0x00004000
#define JUMBO_LEN_4K 0x00000200
#define JUMBO_LEN_15K 0x00000780
#define DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK | \
RGMII_EN)
#define CICADA_DEFAULT_MACCFG1 (RXCRC_CHECK | RXPAUSE_DA_CHECK)
#define MACCFG2 (CMD_BASE + 0x0048)
#define MACCFG2_BIT15_8 0x00000100
#define JAM_LIMIT_MASK 0x000000FC
#define DEFAULT_JAM_LIMIT 0x00000064
#define DEFAULT_MACCFG2 MACCFG2_BIT15_8
#define MACCFG3 (CMD_BASE + 0x004C)
#define IPGR2_VAL 0x0000000E
#define IPGR1_VAL 0x00000600
#define NOABORT 0x00008000
#define DEFAULT_MACCFG3 (IPGR1_VAL | IPGR2_VAL)
#define TXPAUT (CMD_BASE + 0x0054)
#define DEFAULT_TXPAUT 0x001FE000
#define RXBTHD0 (CMD_BASE + 0x0058)
#define DEFAULT_RXBTHD0 0x00000300
#define RXBTHD1 (CMD_BASE + 0x005C)
#define DEFAULT_RXBTHD1 0x00000600
#define RXFULTHD (CMD_BASE + 0x0060)
#define DEFAULT_RXFULTHD 0x00000100
#define MISC (CMD_BASE + 0x0068)
/* Normal operation mode */
#define MISC_NORMAL 0x00000003
/* Clear bit 0 to reset MAC */
#define MISC_RESET_MAC 0x00000002
/* Clear bit 1 to reset PHY */
#define MISC_RESET_PHY 0x00000001
/* Clear bit 0 and 1 to reset MAC and PHY */
#define MISC_RESET_MAC_PHY 0x00000000
#define DEFAULT_MISC MISC_NORMAL
#define MACID0 (CMD_BASE + 0x0070)
#define MACID1 (CMD_BASE + 0x0074)
#define MACID2 (CMD_BASE + 0x0078)
#define TXLEN (CMD_BASE + 0x007C)
#define DEFAULT_TXLEN 0x000005FC
#define RXFILTER (CMD_BASE + 0x0080)
#define RX_RXANY 0x00000001
#define RX_MULTICAST 0x00000002
#define RX_UNICAST 0x00000004
#define RX_BROADCAST 0x00000008
#define RX_MULTI_HASH 0x00000010
#define DISABLE_RXFILTER 0x00000000
#define DEFAULT_RXFILTER (RX_BROADCAST + RX_UNICAST)
#define MDIOCTRL (CMD_BASE + 0x0084)
#define PHY_ADDR_MASK 0x0000001F
#define REG_ADDR_MASK 0x00001F00
#define READ_PHY 0x00004000
#define WRITE_PHY 0x00008000
#define MDIODP (CMD_BASE + 0x0088)
#define GPIOCTRL (CMD_BASE + 0x008C)
#define RXINDICATOR (CMD_BASE + 0x0090)
#define RX_START_READ 0x00000001
#define RX_STOP_READ 0x00000000
#define DEFAULT_RXINDICATOR RX_STOP_READ
#define TXST (CMD_BASE + 0x0094)
#define MDCCLKPAT (CMD_BASE + 0x00A0)
#define RXIPCRCCNT (CMD_BASE + 0x00A4)
#define RXCRCCNT (CMD_BASE + 0x00A8)
#define TXFAILCNT (CMD_BASE + 0x00AC)
#define PROMDP (CMD_BASE + 0x00B0)
#define PROMCTRL (CMD_BASE + 0x00B4)
#define RELOAD_EEPROM 0x00000200
#define MAXRXLEN (CMD_BASE + 0x00B8)
#define HASHTAB0 (CMD_BASE + 0x00C0)
#define HASHTAB1 (CMD_BASE + 0x00C4)
#define HASHTAB2 (CMD_BASE + 0x00C8)
#define HASHTAB3 (CMD_BASE + 0x00CC)
#define DOGTHD0 (CMD_BASE + 0x00E0)
#define DEFAULT_DOGTHD0 0x0000FFFF
#define DOGTHD1 (CMD_BASE + 0x00E4)
#define START_WATCHDOG_TIMER 0x00008000
#define DEFAULT_DOGTHD1 0x00000FFF
#define SOFTRST (CMD_BASE + 0x00EC)
#define SOFTRST_NORMAL 0x00000003
#define SOFTRST_RESET_MAC 0x00000002
/* Marvell 88E1111 Gigabit PHY Register Definition */
#define M88_SSR 0x0011
#define SSR_SPEED_MASK 0xC000
#define SSR_SPEED_1000 0x8000
#define SSR_SPEED_100 0x4000
#define SSR_SPEED_10 0x0000
#define SSR_DUPLEX 0x2000
#define SSR_MEDIA_RESOLVED_OK 0x0800
#define SSR_MEDIA_MASK (SSR_SPEED_MASK | SSR_DUPLEX)
#define SSR_1000FULL (SSR_SPEED_1000 | SSR_DUPLEX)
#define SSR_1000HALF SSR_SPEED_1000
#define SSR_100FULL (SSR_SPEED_100 | SSR_DUPLEX)
#define SSR_100HALF SSR_SPEED_100
#define SSR_10FULL (SSR_SPEED_10 | SSR_DUPLEX)
#define SSR_10HALF SSR_SPEED_10
#define M88_IER 0x0012
#define LINK_CHANGE_INT 0x0400
#define M88_ISR 0x0013
#define LINK_CHANGE_STATUS 0x0400
#define M88E1111_EXT_SCR 0x0014
#define RGMII_RXCLK_DELAY 0x0080
#define RGMII_TXCLK_DELAY 0x0002
#define DEFAULT_EXT_SCR (RGMII_TXCLK_DELAY | RGMII_RXCLK_DELAY)
#define M88E1111_EXT_SSR 0x001B
#define HWCFG_MODE_MASK 0x000F
#define RGMII_COPPER_MODE 0x000B
/* Marvell 88E1118 Gigabit PHY Register Definition */
#define M88E1118_CR 0x14
#define M88E1118_CR_RGMII_RXCLK_DELAY 0x0020
#define M88E1118_CR_RGMII_TXCLK_DELAY 0x0010
#define M88E1118_CR_DEFAULT (M88E1118_CR_RGMII_TXCLK_DELAY | \
M88E1118_CR_RGMII_RXCLK_DELAY)
#define M88E1118_LEDCTL 0x10 /* Reg 16 on page 3 */
#define M88E1118_LEDCTL_LED2INT 0x200
#define M88E1118_LEDCTL_LED2BLNK 0x400
#define M88E1118_LEDCTL_LED0DUALMODE1 0xc
#define M88E1118_LEDCTL_LED0DUALMODE2 0xd
#define M88E1118_LEDCTL_LED0DUALMODE3 0xe
#define M88E1118_LEDCTL_LED0DUALMODE4 0xf
#define M88E1118_LEDCTL_DEFAULT (M88E1118_LEDCTL_LED2BLNK | \
M88E1118_LEDCTL_LED0DUALMODE4)
#define M88E1118_LEDMIX 0x11 /* Reg 17 on page 3 */
#define M88E1118_LEDMIX_LED050 0x4
#define M88E1118_LEDMIX_LED150 0x8
#define M88E1118_PAGE_SEL 0x16 /* Reg page select */
/* CICADA CIS8201 Gigabit PHY Register Definition */
#define CIS_IMR 0x0019
#define CIS_INT_ENABLE 0x8000
#define CIS_LINK_CHANGE_INT 0x2000
#define CIS_ISR 0x001A
#define CIS_INT_PENDING 0x8000
#define CIS_LINK_CHANGE_STATUS 0x2000
#define CIS_AUX_CTRL_STATUS 0x001C
#define CIS_AUTONEG_COMPLETE 0x8000
#define CIS_SPEED_MASK 0x0018
#define CIS_SPEED_1000 0x0010
#define CIS_SPEED_100 0x0008
#define CIS_SPEED_10 0x0000
#define CIS_DUPLEX 0x0020
#define CIS_MEDIA_MASK (CIS_SPEED_MASK | CIS_DUPLEX)
#define CIS_1000FULL (CIS_SPEED_1000 | CIS_DUPLEX)
#define CIS_1000HALF CIS_SPEED_1000
#define CIS_100FULL (CIS_SPEED_100 | CIS_DUPLEX)
#define CIS_100HALF CIS_SPEED_100
#define CIS_10FULL (CIS_SPEED_10 | CIS_DUPLEX)
#define CIS_10HALF CIS_SPEED_10
#define CIS_SMI_PRIORITY 0x0004
static inline unsigned short INW (struct eth_device *dev, unsigned long addr)
{
return le16_to_cpu(readw(addr + (void *)dev->iobase));
}
/*
Access RXBUFFER_START/TXBUFFER_START to read RX buffer/write TX buffer
*/
#if defined (CONFIG_DRIVER_AX88180_16BIT)
static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
{
writew(cpu_to_le16(command), addr + (void *)dev->iobase);
}
static inline unsigned short READ_RXBUF (struct eth_device *dev)
{
return le16_to_cpu(readw(RXBUFFER_START + (void *)dev->iobase));
}
static inline void WRITE_TXBUF (struct eth_device *dev, unsigned short data)
{
writew(cpu_to_le16(data), TXBUFFER_START + (void *)dev->iobase);
}
#else
static inline void OUTW (struct eth_device *dev, unsigned short command, unsigned long addr)
{
writel(cpu_to_le32(command), addr + (void *)dev->iobase);
}
static inline unsigned long READ_RXBUF (struct eth_device *dev)
{
return le32_to_cpu(readl(RXBUFFER_START + (void *)dev->iobase));
}
static inline void WRITE_TXBUF (struct eth_device *dev, unsigned long data)
{
writel(cpu_to_le32(data), TXBUFFER_START + (void *)dev->iobase);
}
#endif
#endif /* _AX88180_H_ */
|
1001-study-uboot
|
drivers/net/ax88180.h
|
C
|
gpl3
| 12,557
|
/*
* RealTek PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <config.h>
#include <common.h>
#include <phy.h>
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
/* RTL8211B PHY Status Register */
#define MIIM_RTL8211B_PHY_STATUS 0x11
#define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000
#define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000
#define MIIM_RTL8211B_PHYSTAT_100 0x4000
#define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000
#define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800
#define MIIM_RTL8211B_PHYSTAT_LINK 0x0400
/* RealTek RTL8211B */
static int rtl8211b_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
genphy_config_aneg(phydev);
return 0;
}
static int rtl8211b_parse_status(struct phy_device *phydev)
{
unsigned int speed;
unsigned int mii_reg;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211B_PHY_STATUS);
if (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
int i = 0;
/* in case of timeout ->link is cleared */
phydev->link = 1;
puts("Waiting for PHY realtime link");
while (!(mii_reg & MIIM_RTL8211B_PHYSTAT_SPDDONE)) {
/* Timeout reached ? */
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
puts(" TIMEOUT !\n");
phydev->link = 0;
break;
}
if ((i++ % 1000) == 0)
putc('.');
udelay(1000); /* 1 ms */
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
MIIM_RTL8211B_PHY_STATUS);
}
puts(" done\n");
udelay(500000); /* another 500 ms (results in faster booting) */
} else {
if (mii_reg & MIIM_RTL8211B_PHYSTAT_LINK)
phydev->link = 1;
else
phydev->link = 0;
}
if (mii_reg & MIIM_RTL8211B_PHYSTAT_DUPLEX)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
speed = (mii_reg & MIIM_RTL8211B_PHYSTAT_SPEED);
switch (speed) {
case MIIM_RTL8211B_PHYSTAT_GBIT:
phydev->speed = SPEED_1000;
break;
case MIIM_RTL8211B_PHYSTAT_100:
phydev->speed = SPEED_100;
break;
default:
phydev->speed = SPEED_10;
}
return 0;
}
static int rtl8211b_startup(struct phy_device *phydev)
{
/* Read the Status (2x to make sure link is right) */
genphy_update_link(phydev);
rtl8211b_parse_status(phydev);
return 0;
}
static struct phy_driver RTL8211B_driver = {
.name = "RealTek RTL8211B",
.uid = 0x1cc910,
.mask = 0xfffff0,
.features = PHY_GBIT_FEATURES,
.config = &rtl8211b_config,
.startup = &rtl8211b_startup,
.shutdown = &genphy_shutdown,
};
int phy_realtek_init(void)
{
phy_register(&RTL8211B_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/realtek.c
|
C
|
gpl3
| 3,237
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _MV88E61XX_H
#define _MV88E61XX_H
#include <miiphy.h>
#define MV88E61XX_CPU_PORT 0x5
#define MV88E61XX_MAX_PORTS_NUM 0x6
#define MV88E61XX_PHY_TIMEOUT 100000
#define MV88E61XX_PRT_STS_REG 0x1
#define MV88E61XX_PRT_CTRL_REG 0x4
#define MV88E61XX_PRT_VMAP_REG 0x6
#define MV88E61XX_PRT_VID_REG 0x7
#define MV88E61XX_PRT_OFST 0x10
#define MV88E61XX_PHY_CMD 0x18
#define MV88E61XX_PHY_DATA 0x19
#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A
#define MV88E61XX_GLB2REG_DEVADR 0x1C
#define MV88E61XX_BUSY_OFST 15
#define MV88E61XX_MODE_OFST 12
#define MV88E61XX_OP_OFST 10
#define MV88E61XX_ADDR_OFST 5
#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data);
static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data);
#define WR_PHY mv88e61xx_wr_phy
#define RD_PHY mv88e61xx_rd_phy
#else
#define WR_PHY miiphy_write
#define RD_PHY miiphy_read
#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
#endif /* _MV88E61XX_H */
|
1001-study-uboot
|
drivers/net/phy/mv88e61xx.h
|
C
|
gpl3
| 2,001
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <netdev.h>
#include "mv88e61xx.h"
#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
/* Chip Address mode
* The Switch support two modes of operation
* 1. single chip mode and
* 2. Multi-chip mode
* Refer section 9.2 &9.3 in chip datasheet-02 for more details
*
* By default single chip mode is configured
* multichip mode operation can be configured in board header
*/
static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
{
u16 reg = 0;
u32 timeout = MV88E61XX_PHY_TIMEOUT;
/* Poll till SMIBusy bit is clear */
do {
miiphy_read(name, devaddr, 0x0, ®);
if (timeout-- == 0) {
printf("SMI busy timeout\n");
return -1;
}
} while (reg & (1 << 15));
return 0;
}
static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data)
{
u16 mii_dev_addr;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
printf("Error..could not read PHY dev address\n");
return;
}
mv88e61xx_busychk_multic(name, mii_dev_addr);
/* Write data to Switch indirect data register */
miiphy_write(name, mii_dev_addr, 0x1, data);
/* Write command to Switch indirect command register (write) */
miiphy_write(name, mii_dev_addr, 0x0,
reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
15));
}
static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data)
{
u16 mii_dev_addr;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
printf("Error..could not read PHY dev address\n");
return;
}
mv88e61xx_busychk_multic(name, mii_dev_addr);
/* Write command to Switch indirect command register (read) */
miiphy_write(name, mii_dev_addr, 0x0,
reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
15));
mv88e61xx_busychk_multic(name, mii_dev_addr);
/* Read data from Switch indirect data register */
miiphy_read(name, mii_dev_addr, 0x1, data);
}
#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig,
u32 max_prtnum, u32 ports_ofs)
{
u32 prt;
u16 reg;
char *name = swconfig->name;
u32 cpu_port = swconfig->cpuport;
u32 port_mask = swconfig->ports_enabled;
enum mv88e61xx_cfg_vlan vlancfg = swconfig->vlancfg;
/* be sure all ports are disabled */
for (prt = 0; prt < max_prtnum; prt++) {
RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, ®);
reg &= ~0x3;
WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, reg);
if (!(cpu_port & (1 << prt)))
continue;
/* Set CPU port VID to 0x1 */
RD_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, ®);
reg &= ~0xfff;
reg |= 0x1;
WR_PHY(name, (ports_ofs + prt), MV88E61XX_PRT_VID_REG, reg);
}
/* Setting Port default priority for all ports to zero */
for (prt = 0; prt < max_prtnum; prt++) {
RD_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, ®);
reg &= ~0xc000;
WR_PHY(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, reg);
}
/* Setting VID and VID map for all ports except CPU port */
for (prt = 0; prt < max_prtnum; prt++) {
/* only for enabled ports */
if ((1 << prt) & port_mask) {
/* skip CPU port */
if ((1 << prt) & cpu_port) {
/*
* Set Vlan map table for cpu_port to see
* all ports
*/
RD_PHY(name, (ports_ofs + prt),
MV88E61XX_PRT_VMAP_REG, ®);
reg &= ~((1 << max_prtnum) - 1);
reg |= port_mask & ~(1 << prt);
WR_PHY(name, (ports_ofs + prt),
MV88E61XX_PRT_VMAP_REG, reg);
} else {
/*
* set Ports VLAN Mapping.
* port prt <--> cpu_port VLAN #prt+1.
*/
RD_PHY(name, ports_ofs + prt,
MV88E61XX_PRT_VID_REG, ®);
reg &= ~0x0fff;
reg |= (prt + 1);
WR_PHY(name, ports_ofs + prt,
MV88E61XX_PRT_VID_REG, reg);
RD_PHY(name, ports_ofs + prt,
MV88E61XX_PRT_VMAP_REG, ®);
if (vlancfg == MV88E61XX_VLANCFG_DEFAULT) {
/*
* all any port can send frames to all other ports
* ref: sec 3.2.1.1 of datasheet
*/
reg |= 0x03f;
reg &= ~(1 << prt);
} else if (vlancfg == MV88E61XX_VLANCFG_ROUTER) {
/*
* all other ports can send frames to CPU port only
* ref: sec 3.2.1.2 of datasheet
*/
reg &= ~((1 << max_prtnum) - 1);
reg |= cpu_port;
}
WR_PHY(name, ports_ofs + prt,
MV88E61XX_PRT_VMAP_REG, reg);
}
}
}
/*
* enable only appropriate ports to forwarding mode
* and disable the others
*/
for (prt = 0; prt < max_prtnum; prt++) {
if ((1 << prt) & port_mask) {
RD_PHY(name, ports_ofs + prt,
MV88E61XX_PRT_CTRL_REG, ®);
reg |= 0x3;
WR_PHY(name, ports_ofs + prt,
MV88E61XX_PRT_CTRL_REG, reg);
} else {
/* Disable port */
RD_PHY(name, ports_ofs + prt,
MV88E61XX_PRT_CTRL_REG, ®);
reg &= ~0x3;
WR_PHY(name, ports_ofs + prt,
MV88E61XX_PRT_CTRL_REG, reg);
}
}
}
/*
* Make sure SMIBusy bit cleared before another
* SMI operation can take place
*/
static int mv88e61xx_busychk(char *name)
{
u16 reg = 0;
u32 timeout = MV88E61XX_PHY_TIMEOUT;
do {
RD_PHY(name, MV88E61XX_GLB2REG_DEVADR,
MV88E61XX_PHY_CMD, ®);
if (timeout-- == 0) {
printf("SMI busy timeout\n");
return -1;
}
} while (reg & 1 << 15); /* busy mask */
return 0;
}
/*
* Power up the specified port and reset PHY
*/
static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 prt)
{
char *name = swconfig->name;
/* Write Copper Specific control reg1 (0x14) for-
* Enable Phy power up
* Energy Detect on (sense&Xmit NLP Periodically
* reset other settings default
*/
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x3360);
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
MV88E61XX_PHY_CMD, (0x9410 | (prt << 5)));
if (mv88e61xx_busychk(name))
return -1;
/* Write PHY ctrl reg (0x0) to apply
* Phy reset (set bit 15 low)
* reset other default values
*/
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 0x1140);
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
MV88E61XX_PHY_CMD, (0x9400 | (prt << 5)));
if (mv88e61xx_busychk(name))
return -1;
return 0;
}
/*
* Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
* is set to "On-1000Mb/s Link, Off Else"
* This function sets it to "On-Link, Blink-Activity, Off-NoLink"
*
* This is optional settings may be needed on some boards
* to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
* Link status
*/
static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 prt)
{
char *name = swconfig->name;
u16 reg;
if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
return 0;
/* set page address to 3 */
reg = 3;
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
1 << MV88E61XX_MODE_OFST |
1 << MV88E61XX_OP_OFST |
prt << MV88E61XX_ADDR_OFST | 22));
if (mv88e61xx_busychk(name))
return -1;
/* set LED Func Ctrl reg */
reg = 1; /* LED[0] On-Link, Blink-Activity, Off-NoLink */
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
1 << MV88E61XX_MODE_OFST |
1 << MV88E61XX_OP_OFST |
prt << MV88E61XX_ADDR_OFST | 16));
if (mv88e61xx_busychk(name))
return -1;
/* set page address to 0 */
reg = 0;
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
1 << MV88E61XX_MODE_OFST |
1 << MV88E61XX_OP_OFST |
prt << MV88E61XX_ADDR_OFST | 22));
if (mv88e61xx_busychk(name))
return -1;
return 0;
}
/*
* Reverse Transmit polarity for Media Dependent Interface
* Pins (MDIP) bits in Copper Specific Control Register 3
* (Page 0, Reg 20 for each phy (except cpu port)
* Reference: Section 1.1 Switch datasheet-3
*
* This is optional settings may be needed on some boards
* for PHY<->magnetics h/w tuning
*/
static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 prt)
{
char *name = swconfig->name;
u16 reg;
if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
return 0;
reg = 0x0f; /*Reverse MDIP/N[3:0] bits */
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, reg);
WR_PHY(name, MV88E61XX_GLB2REG_DEVADR,
MV88E61XX_PHY_CMD, (1 << MV88E61XX_BUSY_OFST |
1 << MV88E61XX_MODE_OFST |
1 << MV88E61XX_OP_OFST |
prt << MV88E61XX_ADDR_OFST | 20));
if (mv88e61xx_busychk(name))
return -1;
return 0;
}
/*
* Marvell 88E61XX Switch initialization
*/
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
{
u32 prt;
u16 reg;
char *idstr;
char *name = swconfig->name;
if (miiphy_set_current_dev(name)) {
printf("%s failed\n", __FUNCTION__);
return -1;
}
if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
swconfig->cpuport = (1 << 5);
printf("Invalid cpu port config, using default port5\n");
}
RD_PHY(name, MV88E61XX_PRT_OFST, MII_PHYSID2, ®);
switch (reg &= 0xfff0) {
case 0x1610:
idstr = "88E6161";
break;
case 0x1650:
idstr = "88E6165";
break;
case 0x1210:
idstr = "88E6123";
/* ports 2,3,4 not available */
swconfig->ports_enabled &= 0x023;
break;
default:
/* Could not detect switch id */
idstr = "88E61??";
break;
}
/* Port based VLANs configuration */
if ((swconfig->vlancfg == MV88E61XX_VLANCFG_DEFAULT)
|| (swconfig->vlancfg == MV88E61XX_VLANCFG_ROUTER))
mv88e61xx_port_vlan_config(swconfig, MV88E61XX_MAX_PORTS_NUM,
MV88E61XX_PRT_OFST);
else {
printf("Unsupported mode %s failed\n", __FUNCTION__);
return -1;
}
if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 9.5 of chip datasheet-02
*/
WR_PHY(name, MV88E61XX_PRT_OFST + 5,
MV88E61XX_RGMII_TIMECTRL_REG, 0x18);
WR_PHY(name, MV88E61XX_PRT_OFST + 4,
MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
}
for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
if (!((1 << prt) & swconfig->cpuport)) {
if (mv88361xx_led_init(swconfig, prt))
return -1;
if (mv88361xx_reverse_mdipn(swconfig, prt))
return -1;
if (mv88361xx_powerup(swconfig, prt))
return -1;
}
/*Program port state */
RD_PHY(name, MV88E61XX_PRT_OFST + prt,
MV88E61XX_PRT_CTRL_REG, ®);
WR_PHY(name, MV88E61XX_PRT_OFST + prt,
MV88E61XX_PRT_CTRL_REG,
reg | (swconfig->portstate & 0x03));
}
printf("%s Initialized on %s\n", idstr, name);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/mv88e61xx.c
|
C
|
gpl3
| 11,621
|
/*
* Teranetics PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <config.h>
#include <common.h>
#include <phy.h>
#ifndef CONFIG_PHYLIB_10G
#error The Teranetics PHY needs 10G support
#endif
int tn2020_config(struct phy_device *phydev)
{
if (phydev->port == PORT_FIBRE) {
unsigned short restart_an = (MDIO_AN_CTRL1_RESTART |
MDIO_AN_CTRL1_ENABLE |
MDIO_AN_CTRL1_XNP);
phy_write(phydev, 30, 93, 2);
phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an);
}
return 0;
}
int tn2020_startup(struct phy_device *phydev)
{
unsigned int timeout = 5 * 1000; /* 5 second timeout */
#define MDIO_PHYXS_LANE_READY (MDIO_PHYXS_LNSTAT_SYNC0 | \
MDIO_PHYXS_LNSTAT_SYNC1 | \
MDIO_PHYXS_LNSTAT_SYNC2 | \
MDIO_PHYXS_LNSTAT_SYNC3 | \
MDIO_PHYXS_LNSTAT_ALIGN)
/*
* Wait for the XAUI-SERDES lanes to align first. Under normal
* circumstances, this can take up to three seconds.
*/
while (--timeout) {
int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT);
if (reg < 0) {
printf("TN2020: Error reading from PHY at "
"address %u\n", phydev->addr);
break;
}
if ((reg & MDIO_PHYXS_LANE_READY) == MDIO_PHYXS_LANE_READY)
break;
udelay(1000);
}
if (!timeout) {
/*
* A timeout is bad, but it may not be fatal, so don't
* return an error. Display a warning instead.
*/
printf("TN2020: Timeout waiting for PHY at address %u to "
"align.\n", phydev->addr);
}
if (phydev->port != PORT_FIBRE)
return gen10g_startup(phydev);
/*
* The TN2020 only pretends to support fiber.
* It works, but it doesn't look like it works,
* so the link status reports no link.
*/
phydev->link = 1;
/* For now just lie and say it's 10G all the time */
phydev->speed = SPEED_10000;
phydev->duplex = DUPLEX_FULL;
return 0;
}
struct phy_driver tn2020_driver = {
.name = "Teranetics TN2020",
.uid = PHY_UID_TN2020,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
.mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
.config = &tn2020_config,
.startup = &tn2020_startup,
.shutdown = &gen10g_shutdown,
};
int phy_teranetics_init(void)
{
phy_register(&tn2020_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/teranetics.c
|
C
|
gpl3
| 3,036
|
#
# (C) Copyright 2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libphy.o
COBJS-$(CONFIG_BITBANGMII) += miiphybb.o
COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o
COBJS-$(CONFIG_PHYLIB) += phy.o
COBJS-$(CONFIG_PHYLIB_10G) += generic_10g.o
COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o
COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o
COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o
COBJS-$(CONFIG_PHY_LXT) += lxt.o
COBJS-$(CONFIG_PHY_MARVELL) += marvell.o
COBJS-$(CONFIG_PHY_MICREL) += micrel.o
COBJS-$(CONFIG_PHY_NATSEMI) += natsemi.o
COBJS-$(CONFIG_PHY_REALTEK) += realtek.o
COBJS-$(CONFIG_PHY_SMSC) += smsc.o
COBJS-$(CONFIG_PHY_TERANETICS) += teranetics.o
COBJS-$(CONFIG_PHY_VITESSE) += vitesse.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/net/phy/Makefile
|
Makefile
|
gpl3
| 1,914
|
/*
* National Semiconductor PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <phy.h>
/* DP83865 Link and Auto-Neg Status Register */
#define MIIM_DP83865_LANR 0x11
#define MIIM_DP83865_SPD_MASK 0x0018
#define MIIM_DP83865_SPD_1000 0x0010
#define MIIM_DP83865_SPD_100 0x0008
#define MIIM_DP83865_DPX_FULL 0x0002
/* NatSemi DP83865 */
static int dp83865_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
genphy_config_aneg(phydev);
return 0;
}
static int dp83865_parse_status(struct phy_device *phydev)
{
int mii_reg;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
switch (mii_reg & MIIM_DP83865_SPD_MASK) {
case MIIM_DP83865_SPD_1000:
phydev->speed = SPEED_1000;
break;
case MIIM_DP83865_SPD_100:
phydev->speed = SPEED_100;
break;
default:
phydev->speed = SPEED_10;
break;
}
if (mii_reg & MIIM_DP83865_DPX_FULL)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
return 0;
}
static int dp83865_startup(struct phy_device *phydev)
{
genphy_update_link(phydev);
dp83865_parse_status(phydev);
return 0;
}
static struct phy_driver DP83865_driver = {
.name = "NatSemi DP83865",
.uid = 0x20005c70,
.mask = 0xfffffff0,
.features = PHY_GBIT_FEATURES,
.config = &dp83865_config,
.startup = &dp83865_startup,
.shutdown = &genphy_shutdown,
};
int phy_natsemi_init(void)
{
phy_register(&DP83865_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/natsemi.c
|
C
|
gpl3
| 2,223
|
/*
* Atheros PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <phy.h>
static int ar8021_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
return 0;
}
struct phy_driver AR8021_driver = {
.name = "AR8021",
.uid = 0x4dd040,
.mask = 0xfffff0,
.features = PHY_GBIT_FEATURES,
.config = ar8021_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
int phy_atheros_init(void)
{
phy_register(&AR8021_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/atheros.c
|
C
|
gpl3
| 1,298
|
/*
* Davicom PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <phy.h>
#define MIIM_DM9161_SCR 0x10
#define MIIM_DM9161_SCR_INIT 0x0610
/* DM9161 Specified Configuration and Status Register */
#define MIIM_DM9161_SCSR 0x11
#define MIIM_DM9161_SCSR_100F 0x8000
#define MIIM_DM9161_SCSR_100H 0x4000
#define MIIM_DM9161_SCSR_10F 0x2000
#define MIIM_DM9161_SCSR_10H 0x1000
/* DM9161 10BT Configuration/Status */
#define MIIM_DM9161_10BTCSR 0x12
#define MIIM_DM9161_10BTCSR_INIT 0x7800
/* Davicom DM9161E */
static int dm9161_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE);
/* Do not bypass the scrambler/descrambler */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR,
MIIM_DM9161_SCR_INIT);
/* Clear 10BTCSR to default */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR,
MIIM_DM9161_10BTCSR_INIT);
genphy_config_aneg(phydev);
return 0;
}
static int dm9161_parse_status(struct phy_device *phydev)
{
int mii_reg;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR);
if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
phydev->speed = SPEED_100;
else
phydev->speed = SPEED_10;
if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
return 0;
}
static int dm9161_startup(struct phy_device *phydev)
{
genphy_update_link(phydev);
dm9161_parse_status(phydev);
return 0;
}
static struct phy_driver DM9161_driver = {
.name = "Davicom DM9161E",
.uid = 0x181b880,
.mask = 0xffffff0,
.features = PHY_BASIC_FEATURES,
.config = &dm9161_config,
.startup = &dm9161_startup,
.shutdown = &genphy_shutdown,
};
int phy_davicom_init(void)
{
phy_register(&DM9161_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/davicom.c
|
C
|
gpl3
| 2,579
|
/*
* Generic PHY Management code
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*
* Copyright 2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
* Based loosely off of Linux's PHY Lib
*/
#include <config.h>
#include <common.h>
#include <miiphy.h>
#include <phy.h>
int gen10g_shutdown(struct phy_device *phydev)
{
return 0;
}
int gen10g_startup(struct phy_device *phydev)
{
int devad, reg;
u32 mmd_mask = phydev->mmds & MDIO_DEVS_LINK;
phydev->link = 1;
/* For now just lie and say it's 10G all the time */
phydev->speed = SPEED_10000;
phydev->duplex = DUPLEX_FULL;
/*
* Go through all the link-reporting devices, and make sure
* they're all up and happy
*/
for (devad = 0; mmd_mask; devad++, mmd_mask = mmd_mask >> 1) {
if (!(mmd_mask & 1))
continue;
/* Read twice because link state is latched and a
* read moves the current state into the register */
phy_read(phydev, devad, MDIO_STAT1);
reg = phy_read(phydev, devad, MDIO_STAT1);
if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
phydev->link = 0;
}
return 0;
}
int gen10g_discover_mmds(struct phy_device *phydev)
{
int mmd, stat2, devs1, devs2;
/* Assume PHY must have at least one of PMA/PMD, WIS, PCS, PHY
* XS or DTE XS; give up if none is present. */
for (mmd = 1; mmd <= 5; mmd++) {
/* Is this MMD present? */
stat2 = phy_read(phydev, mmd, MDIO_STAT2);
if (stat2 < 0 ||
(stat2 & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL)
continue;
/* It should tell us about all the other MMDs */
devs1 = phy_read(phydev, mmd, MDIO_DEVS1);
devs2 = phy_read(phydev, mmd, MDIO_DEVS2);
if (devs1 < 0 || devs2 < 0)
continue;
phydev->mmds = devs1 | (devs2 << 16);
return 0;
}
return 0;
}
int gen10g_config(struct phy_device *phydev)
{
/* For now, assume 10000baseT. Fill in later */
phydev->supported = phydev->advertising = SUPPORTED_10000baseT_Full;
return gen10g_discover_mmds(phydev);
}
struct phy_driver gen10g_driver = {
.uid = 0xffffffff,
.mask = 0xffffffff,
.name = "Generic 10G PHY",
.features = 0,
.config = gen10g_config,
.startup = gen10g_startup,
.shutdown = gen10g_shutdown,
};
|
1001-study-uboot
|
drivers/net/phy/generic_10g.c
|
C
|
gpl3
| 2,816
|
/*
* SMSC PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Base code from drivers/net/phy/davicom.c
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
* Some code get from linux kenrel
* Copyright (c) 2006 Herbert Valerio Riedel <hvr@gnu.org>
*
*/
#include <miiphy.h>
static int smsc_parse_status(struct phy_device *phydev)
{
int mii_reg;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
if (mii_reg & (BMSR_100FULL | BMSR_100HALF))
phydev->speed = SPEED_100;
else
phydev->speed = SPEED_10;
if (mii_reg & (BMSR_10FULL | BMSR_100FULL))
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
return 0;
}
static int smsc_startup(struct phy_device *phydev)
{
genphy_update_link(phydev);
smsc_parse_status(phydev);
return 0;
}
static struct phy_driver lan8700_driver = {
.name = "SMSC LAN8700",
.uid = 0x0007c0c0,
.mask = 0xffff0,
.features = PHY_BASIC_FEATURES,
.config = &genphy_config_aneg,
.startup = &smsc_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver lan911x_driver = {
.name = "SMSC LAN911x Internal PHY",
.uid = 0x0007c0d0,
.mask = 0xffff0,
.features = PHY_BASIC_FEATURES,
.config = &genphy_config_aneg,
.startup = &smsc_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver lan8710_driver = {
.name = "SMSC LAN8710/LAN8720",
.uid = 0x0007c0f0,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &genphy_config_aneg,
.startup = &smsc_startup,
.shutdown = &genphy_shutdown,
};
int phy_smsc_init(void)
{
phy_register(&lan8710_driver);
phy_register(&lan911x_driver);
phy_register(&lan8700_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/smsc.c
|
C
|
gpl3
| 2,344
|
/*
* LXT PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <phy.h>
/* LXT971 Status 2 registers */
#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
#define MIIM_LXT971_SR2_SPEED_MASK 0x4200
#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
/* LXT971 */
static int lxt971_parse_status(struct phy_device *phydev)
{
int mii_reg;
int speed;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_LXT971_SR2);
speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
switch (speed) {
case MIIM_LXT971_SR2_10HDX:
phydev->speed = SPEED_10;
phydev->duplex = DUPLEX_HALF;
break;
case MIIM_LXT971_SR2_10FDX:
phydev->speed = SPEED_10;
phydev->duplex = DUPLEX_FULL;
break;
case MIIM_LXT971_SR2_100HDX:
phydev->speed = SPEED_100;
phydev->duplex = DUPLEX_HALF;
break;
default:
phydev->speed = SPEED_100;
phydev->duplex = DUPLEX_FULL;
}
return 0;
}
static int lxt971_startup(struct phy_device *phydev)
{
genphy_update_link(phydev);
lxt971_parse_status(phydev);
return 0;
}
static struct phy_driver LXT971_driver = {
.name = "LXT971",
.uid = 0x1378e0,
.mask = 0xfffff0,
.features = PHY_BASIC_FEATURES,
.config = &genphy_config_aneg,
.startup = &lxt971_startup,
.shutdown = &genphy_shutdown,
};
int phy_lxt_init(void)
{
phy_register(&LXT971_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/lxt.c
|
C
|
gpl3
| 2,347
|
/*
* Generic PHY Management code
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*
* Copyright 2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
* Based loosely off of Linux's PHY Lib
*/
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <miiphy.h>
#include <phy.h>
#include <errno.h>
/* Generic PHY support and helper functions */
/**
* genphy_config_advert - sanitize and advertise auto-negotation parameters
* @phydev: target phy_device struct
*
* Description: Writes MII_ADVERTISE with the appropriate values,
* after sanitizing the values to make sure we only advertise
* what is supported. Returns < 0 on error, 0 if the PHY's advertisement
* hasn't changed, and > 0 if it has changed.
*/
int genphy_config_advert(struct phy_device *phydev)
{
u32 advertise;
int oldadv, adv;
int err, changed = 0;
/* Only allow advertising what
* this PHY supports */
phydev->advertising &= phydev->supported;
advertise = phydev->advertising;
/* Setup standard advertisement */
oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
if (adv < 0)
return adv;
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
ADVERTISE_PAUSE_ASYM);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
if (advertise & ADVERTISED_10baseT_Full)
adv |= ADVERTISE_10FULL;
if (advertise & ADVERTISED_100baseT_Half)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
if (advertise & ADVERTISED_Pause)
adv |= ADVERTISE_PAUSE_CAP;
if (advertise & ADVERTISED_Asym_Pause)
adv |= ADVERTISE_PAUSE_ASYM;
if (adv != oldadv) {
err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv);
if (err < 0)
return err;
changed = 1;
}
/* Configure gigabit if it's supported */
if (phydev->supported & (SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full)) {
oldadv = adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
if (adv < 0)
return adv;
adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
if (advertise & SUPPORTED_1000baseT_Half)
adv |= ADVERTISE_1000HALF;
if (advertise & SUPPORTED_1000baseT_Full)
adv |= ADVERTISE_1000FULL;
if (adv != oldadv) {
err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000,
adv);
if (err < 0)
return err;
changed = 1;
}
}
return changed;
}
/**
* genphy_setup_forced - configures/forces speed/duplex from @phydev
* @phydev: target phy_device struct
*
* Description: Configures MII_BMCR to force speed/duplex
* to the values in phydev. Assumes that the values are valid.
*/
int genphy_setup_forced(struct phy_device *phydev)
{
int err;
int ctl = 0;
phydev->pause = phydev->asym_pause = 0;
if (SPEED_1000 == phydev->speed)
ctl |= BMCR_SPEED1000;
else if (SPEED_100 == phydev->speed)
ctl |= BMCR_SPEED100;
if (DUPLEX_FULL == phydev->duplex)
ctl |= BMCR_FULLDPLX;
err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
return err;
}
/**
* genphy_restart_aneg - Enable and Restart Autonegotiation
* @phydev: target phy_device struct
*/
int genphy_restart_aneg(struct phy_device *phydev)
{
int ctl;
ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
if (ctl < 0)
return ctl;
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
/* Don't isolate the PHY if we're negotiating */
ctl &= ~(BMCR_ISOLATE);
ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
return ctl;
}
/**
* genphy_config_aneg - restart auto-negotiation or write BMCR
* @phydev: target phy_device struct
*
* Description: If auto-negotiation is enabled, we configure the
* advertising, and then restart auto-negotiation. If it is not
* enabled, then we write the BMCR.
*/
int genphy_config_aneg(struct phy_device *phydev)
{
int result;
if (AUTONEG_ENABLE != phydev->autoneg)
return genphy_setup_forced(phydev);
result = genphy_config_advert(phydev);
if (result < 0) /* error */
return result;
if (result == 0) {
/* Advertisment hasn't changed, but maybe aneg was never on to
* begin with? Or maybe phy was isolated? */
int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
if (ctl < 0)
return ctl;
if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
result = 1; /* do restart aneg */
}
/* Only restart aneg if we are advertising something different
* than we were before. */
if (result > 0)
result = genphy_restart_aneg(phydev);
return result;
}
/**
* genphy_update_link - update link status in @phydev
* @phydev: target phy_device struct
*
* Description: Update the value in phydev->link to reflect the
* current link value. In order to do this, we need to read
* the status register twice, keeping the second value.
*/
int genphy_update_link(struct phy_device *phydev)
{
unsigned int mii_reg;
/*
* Wait if the link is up, and autonegotiation is in progress
* (ie - we're capable and it's not done)
*/
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
/*
* If we already saw the link up, and it hasn't gone down, then
* we don't need to wait for autoneg again
*/
if (phydev->link && mii_reg & BMSR_LSTATUS)
return 0;
if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) {
int i = 0;
printf("%s Waiting for PHY auto negotiation to complete",
phydev->dev->name);
while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
if (i > PHY_ANEG_TIMEOUT) {
printf(" TIMEOUT !\n");
phydev->link = 0;
return 0;
}
if (ctrlc()) {
puts("user interrupt!\n");
phydev->link = 0;
return -EINTR;
}
if ((i++ % 500) == 0)
printf(".");
udelay(1000); /* 1 ms */
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
}
printf(" done\n");
phydev->link = 1;
} else {
/* Read the link a second time to clear the latched state */
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
if (mii_reg & BMSR_LSTATUS)
phydev->link = 1;
else
phydev->link = 0;
}
return 0;
}
/*
* Generic function which updates the speed and duplex. If
* autonegotiation is enabled, it uses the AND of the link
* partner's advertised capabilities and our advertised
* capabilities. If autonegotiation is disabled, we use the
* appropriate bits in the control register.
*
* Stolen from Linux's mii.c and phy_device.c
*/
static int genphy_parse_link(struct phy_device *phydev)
{
int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
/* We're using autonegotiation */
if (mii_reg & BMSR_ANEGCAPABLE) {
u32 lpa = 0;
u32 gblpa = 0;
/* Check for gigabit capability */
if (mii_reg & BMSR_ERCAP) {
/* We want a list of states supported by
* both PHYs in the link
*/
gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
gblpa &= phy_read(phydev,
MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
}
/* Set the baseline so we only have to set them
* if they're different
*/
phydev->speed = SPEED_10;
phydev->duplex = DUPLEX_HALF;
/* Check the gigabit fields */
if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
phydev->speed = SPEED_1000;
if (gblpa & PHY_1000BTSR_1000FD)
phydev->duplex = DUPLEX_FULL;
/* We're done! */
return 0;
}
lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
lpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
if (lpa & (LPA_100FULL | LPA_100HALF)) {
phydev->speed = SPEED_100;
if (lpa & LPA_100FULL)
phydev->duplex = DUPLEX_FULL;
} else if (lpa & LPA_10FULL)
phydev->duplex = DUPLEX_FULL;
} else {
u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
phydev->speed = SPEED_10;
phydev->duplex = DUPLEX_HALF;
if (bmcr & BMCR_FULLDPLX)
phydev->duplex = DUPLEX_FULL;
if (bmcr & BMCR_SPEED1000)
phydev->speed = SPEED_1000;
else if (bmcr & BMCR_SPEED100)
phydev->speed = SPEED_100;
}
return 0;
}
int genphy_config(struct phy_device *phydev)
{
int val;
u32 features;
/* For now, I'll claim that the generic driver supports
* all possible port types */
features = (SUPPORTED_TP | SUPPORTED_MII
| SUPPORTED_AUI | SUPPORTED_FIBRE |
SUPPORTED_BNC);
/* Do we support autonegotiation? */
val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
if (val < 0)
return val;
if (val & BMSR_ANEGCAPABLE)
features |= SUPPORTED_Autoneg;
if (val & BMSR_100FULL)
features |= SUPPORTED_100baseT_Full;
if (val & BMSR_100HALF)
features |= SUPPORTED_100baseT_Half;
if (val & BMSR_10FULL)
features |= SUPPORTED_10baseT_Full;
if (val & BMSR_10HALF)
features |= SUPPORTED_10baseT_Half;
if (val & BMSR_ESTATEN) {
val = phy_read(phydev, MDIO_DEVAD_NONE, MII_ESTATUS);
if (val < 0)
return val;
if (val & ESTATUS_1000_TFULL)
features |= SUPPORTED_1000baseT_Full;
if (val & ESTATUS_1000_THALF)
features |= SUPPORTED_1000baseT_Half;
}
phydev->supported = features;
phydev->advertising = features;
genphy_config_aneg(phydev);
return 0;
}
int genphy_startup(struct phy_device *phydev)
{
genphy_update_link(phydev);
genphy_parse_link(phydev);
return 0;
}
int genphy_shutdown(struct phy_device *phydev)
{
return 0;
}
static struct phy_driver genphy_driver = {
.uid = 0xffffffff,
.mask = 0xffffffff,
.name = "Generic PHY",
.features = 0,
.config = genphy_config,
.startup = genphy_startup,
.shutdown = genphy_shutdown,
};
static LIST_HEAD(phy_drivers);
int phy_init(void)
{
#ifdef CONFIG_PHY_ATHEROS
phy_atheros_init();
#endif
#ifdef CONFIG_PHY_BROADCOM
phy_broadcom_init();
#endif
#ifdef CONFIG_PHY_DAVICOM
phy_davicom_init();
#endif
#ifdef CONFIG_PHY_LXT
phy_lxt_init();
#endif
#ifdef CONFIG_PHY_MARVELL
phy_marvell_init();
#endif
#ifdef CONFIG_PHY_MICREL
phy_micrel_init();
#endif
#ifdef CONFIG_PHY_NATSEMI
phy_natsemi_init();
#endif
#ifdef CONFIG_PHY_REALTEK
phy_realtek_init();
#endif
#ifdef CONFIG_PHY_SMSC
phy_smsc_init();
#endif
#ifdef CONFIG_PHY_TERANETICS
phy_teranetics_init();
#endif
#ifdef CONFIG_PHY_VITESSE
phy_vitesse_init();
#endif
return 0;
}
int phy_register(struct phy_driver *drv)
{
INIT_LIST_HEAD(&drv->list);
list_add_tail(&drv->list, &phy_drivers);
return 0;
}
int phy_probe(struct phy_device *phydev)
{
int err = 0;
phydev->advertising = phydev->supported = phydev->drv->features;
phydev->mmds = phydev->drv->mmds;
if (phydev->drv->probe)
err = phydev->drv->probe(phydev);
return err;
}
static struct phy_driver *generic_for_interface(phy_interface_t interface)
{
#ifdef CONFIG_PHYLIB_10G
if (is_10g_interface(interface))
return &gen10g_driver;
#endif
return &genphy_driver;
}
struct phy_driver *get_phy_driver(struct phy_device *phydev,
phy_interface_t interface)
{
struct list_head *entry;
int phy_id = phydev->phy_id;
struct phy_driver *drv = NULL;
list_for_each(entry, &phy_drivers) {
drv = list_entry(entry, struct phy_driver, list);
if ((drv->uid & drv->mask) == (phy_id & drv->mask))
return drv;
}
/* If we made it here, there's no driver for this PHY */
return generic_for_interface(interface);
}
struct phy_device *phy_device_create(struct mii_dev *bus, int addr, int phy_id,
phy_interface_t interface)
{
struct phy_device *dev;
/* We allocate the device, and initialize the
* default values */
dev = malloc(sizeof(*dev));
if (!dev) {
printf("Failed to allocate PHY device for %s:%d\n",
bus->name, addr);
return NULL;
}
memset(dev, 0, sizeof(*dev));
dev->duplex = -1;
dev->link = 1;
dev->interface = interface;
dev->autoneg = AUTONEG_ENABLE;
dev->addr = addr;
dev->phy_id = phy_id;
dev->bus = bus;
dev->drv = get_phy_driver(dev, interface);
phy_probe(dev);
bus->phymap[addr] = dev;
return dev;
}
/**
* get_phy_id - reads the specified addr for its ID.
* @bus: the target MII bus
* @addr: PHY address on the MII bus
* @phy_id: where to store the ID retrieved.
*
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, stores it in @phy_id and returns zero on success.
*/
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
/* Grab the bits from PHYIR1, and put them
* in the upper half */
phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
if (phy_reg < 0)
return -EIO;
*phy_id = (phy_reg & 0xffff) << 16;
/* Grab the bits from PHYIR2, and put them in the lower half */
phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
if (phy_reg < 0)
return -EIO;
*phy_id |= (phy_reg & 0xffff);
return 0;
}
/**
* get_phy_device - reads the specified PHY device and returns its @phy_device struct
* @bus: the target MII bus
* @addr: PHY address on the MII bus
*
* Description: Reads the ID registers of the PHY at @addr on the
* @bus, then allocates and returns the phy_device to represent it.
*/
struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
phy_interface_t interface)
{
u32 phy_id = 0x1fffffff;
int i;
int r;
/* If we have one, return the existing device, with new interface */
if (bus->phymap[addr]) {
bus->phymap[addr]->interface = interface;
return bus->phymap[addr];
}
/* Try Standard (ie Clause 22) access */
r = get_phy_id(bus, addr, MDIO_DEVAD_NONE, &phy_id);
if (r)
return NULL;
/* If the PHY ID is mostly f's, we didn't find anything */
if ((phy_id & 0x1fffffff) != 0x1fffffff)
return phy_device_create(bus, addr, phy_id, interface);
/* Otherwise we have to try Clause 45 */
for (i = 1; i < 5; i++) {
r = get_phy_id(bus, addr, i, &phy_id);
if (r)
return NULL;
/* If the phy_id is mostly Fs, there is no device there */
if ((phy_id & 0x1fffffff) != 0x1fffffff)
break;
}
return phy_device_create(bus, addr, phy_id, interface);
}
int phy_reset(struct phy_device *phydev)
{
int reg;
int timeout = 500;
int devad = MDIO_DEVAD_NONE;
#ifdef CONFIG_PHYLIB_10G
/* If it's 10G, we need to issue reset through one of the MMDs */
if (is_10g_interface(phydev->interface)) {
if (!phydev->mmds)
gen10g_discover_mmds(phydev);
devad = ffs(phydev->mmds) - 1;
}
#endif
reg = phy_read(phydev, devad, MII_BMCR);
if (reg < 0) {
debug("PHY status read failed\n");
return -1;
}
reg |= BMCR_RESET;
if (phy_write(phydev, devad, MII_BMCR, reg) < 0) {
debug("PHY reset failed\n");
return -1;
}
#ifdef CONFIG_PHY_RESET_DELAY
udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
#endif
/*
* Poll the control register for the reset bit to go to 0 (it is
* auto-clearing). This should happen within 0.5 seconds per the
* IEEE spec.
*/
while ((reg & BMCR_RESET) && timeout--) {
reg = phy_read(phydev, devad, MII_BMCR);
if (reg < 0) {
debug("PHY status read failed\n");
return -1;
}
udelay(1000);
}
if (reg & BMCR_RESET) {
puts("PHY reset timed out\n");
return -1;
}
return 0;
}
int miiphy_reset(const char *devname, unsigned char addr)
{
struct mii_dev *bus = miiphy_get_dev_by_name(devname);
struct phy_device *phydev;
/*
* miiphy_reset was only used on standard PHYs, so we'll fake it here.
* If later code tries to connect with the right interface, this will
* be corrected by get_phy_device in phy_connect()
*/
phydev = get_phy_device(bus, addr, PHY_INTERFACE_MODE_MII);
return phy_reset(phydev);
}
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
phy_interface_t interface)
{
struct phy_device *phydev;
/* Reset the bus */
if (bus->reset)
bus->reset(bus);
/* Wait 15ms to make sure the PHY has come out of hard reset */
udelay(15000);
phydev = get_phy_device(bus, addr, interface);
if (!phydev) {
printf("Could not get PHY for %s:%d\n", bus->name, addr);
return NULL;
}
/* Soft Reset the PHY */
phy_reset(phydev);
if (phydev->dev)
printf("%s:%d is connected to %s. Reconnecting to %s\n",
bus->name, addr, phydev->dev->name, dev->name);
phydev->dev = dev;
debug("%s connected to %s\n", dev->name, phydev->drv->name);
return phydev;
}
int phy_startup(struct phy_device *phydev)
{
if (phydev->drv->startup)
phydev->drv->startup(phydev);
return 0;
}
static int __board_phy_config(struct phy_device *phydev)
{
return 0;
}
int board_phy_config(struct phy_device *phydev)
__attribute__((weak, alias("__board_phy_config")));
int phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
/* Invoke an optional board-specific helper */
board_phy_config(phydev);
return 0;
}
int phy_shutdown(struct phy_device *phydev)
{
if (phydev->drv->shutdown)
phydev->drv->shutdown(phydev);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/phy.c
|
C
|
gpl3
| 17,203
|
/*
* Marvell PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <config.h>
#include <common.h>
#include <phy.h>
#define PHY_AUTONEGOTIATE_TIMEOUT 5000
/* 88E1011 PHY Status Register */
#define MIIM_88E1xxx_PHY_STATUS 0x11
#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
#define MIIM_88E1xxx_PHYSTAT_100 0x4000
#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
#define MIIM_88E1xxx_PHY_SCR 0x10
#define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
/* 88E1111 PHY LED Control Register */
#define MIIM_88E1111_PHY_LED_CONTROL 24
#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
/* 88E1111 Extended PHY Specific Control Register */
#define MIIM_88E1111_PHY_EXT_CR 0x14
#define MIIM_88E1111_RX_DELAY 0x80
#define MIIM_88E1111_TX_DELAY 0x2
/* 88E1111 Extended PHY Specific Status Register */
#define MIIM_88E1111_PHY_EXT_SR 0x1b
#define MIIM_88E1111_HWCFG_MODE_MASK 0xf
#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
#define MIIM_88E1111_COPPER 0
#define MIIM_88E1111_FIBER 1
/* 88E1118 PHY defines */
#define MIIM_88E1118_PHY_PAGE 22
#define MIIM_88E1118_PHY_LED_PAGE 3
/* 88E1121 PHY LED Control Register */
#define MIIM_88E1121_PHY_LED_CTRL 16
#define MIIM_88E1121_PHY_LED_PAGE 3
#define MIIM_88E1121_PHY_LED_DEF 0x0030
/* 88E1121 PHY IRQ Enable/Status Register */
#define MIIM_88E1121_PHY_IRQ_EN 18
#define MIIM_88E1121_PHY_IRQ_STATUS 19
#define MIIM_88E1121_PHY_PAGE 22
/* 88E1145 Extended PHY Specific Control Register */
#define MIIM_88E1145_PHY_EXT_CR 20
#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
#define MIIM_88E1145_PHY_LED_CONTROL 24
#define MIIM_88E1145_PHY_LED_DIRECT 0x4100
#define MIIM_88E1145_PHY_PAGE 29
#define MIIM_88E1145_PHY_CAL_OV 30
#define MIIM_88E1149_PHY_PAGE 29
/* Marvell 88E1011S */
static int m88e1011s_config(struct phy_device *phydev)
{
/* Reset and configure the PHY */
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
genphy_config_aneg(phydev);
return 0;
}
/* Parse the 88E1011's status register for speed and duplex
* information
*/
static uint m88e1xxx_parse_status(struct phy_device *phydev)
{
unsigned int speed;
unsigned int mii_reg;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
int i = 0;
puts("Waiting for PHY realtime link");
while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
/* Timeout reached ? */
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
puts(" TIMEOUT !\n");
phydev->link = 0;
break;
}
if ((i++ % 1000) == 0)
putc('.');
udelay(1000);
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
MIIM_88E1xxx_PHY_STATUS);
}
puts(" done\n");
udelay(500000); /* another 500 ms (results in faster booting) */
} else {
if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
phydev->link = 1;
else
phydev->link = 0;
}
if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
switch (speed) {
case MIIM_88E1xxx_PHYSTAT_GBIT:
phydev->speed = SPEED_1000;
break;
case MIIM_88E1xxx_PHYSTAT_100:
phydev->speed = SPEED_100;
break;
default:
phydev->speed = SPEED_10;
break;
}
return 0;
}
static int m88e1011s_startup(struct phy_device *phydev)
{
genphy_update_link(phydev);
m88e1xxx_parse_status(phydev);
return 0;
}
/* Marvell 88E1111S */
static int m88e1111s_config(struct phy_device *phydev)
{
int reg;
int timeout;
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
reg = phy_read(phydev,
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
reg &= ~MIIM_88E1111_TX_DELAY;
reg |= MIIM_88E1111_RX_DELAY;
} else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
reg &= ~MIIM_88E1111_RX_DELAY;
reg |= MIIM_88E1111_TX_DELAY;
}
phy_write(phydev,
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
reg = phy_read(phydev,
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
else
reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
phy_write(phydev,
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
}
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
reg = phy_read(phydev,
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
phy_write(phydev, MDIO_DEVAD_NONE,
MIIM_88E1111_PHY_EXT_SR, reg);
}
if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
reg = phy_read(phydev,
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
phy_write(phydev,
MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
reg = phy_read(phydev, MDIO_DEVAD_NONE,
MIIM_88E1111_PHY_EXT_SR);
reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
phy_write(phydev, MDIO_DEVAD_NONE,
MIIM_88E1111_PHY_EXT_SR, reg);
/* soft reset */
timeout = 1000;
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
udelay(1000);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
while ((reg & BMCR_RESET) && --timeout) {
udelay(1000);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
}
if (!timeout)
printf("%s: phy soft reset timeout\n", __func__);
reg = phy_read(phydev, MDIO_DEVAD_NONE,
MIIM_88E1111_PHY_EXT_SR);
reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
phy_write(phydev, MDIO_DEVAD_NONE,
MIIM_88E1111_PHY_EXT_SR, reg);
}
/* soft reset */
timeout = 1000;
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
udelay(1000);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
while ((reg & BMCR_RESET) && --timeout) {
udelay(1000);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
}
if (!timeout)
printf("%s: phy soft reset timeout\n", __func__);
genphy_config_aneg(phydev);
phy_reset(phydev);
return 0;
}
/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
/* Delay RGMII TX and RX */
phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
/* Adjust LED control */
phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
genphy_config_aneg(phydev);
phy_reset(phydev);
return 0;
}
static int m88e1118_startup(struct phy_device *phydev)
{
/* Change Page Number */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
genphy_update_link(phydev);
m88e1xxx_parse_status(phydev);
return 0;
}
/* Marvell 88E1121R */
static int m88e1121_config(struct phy_device *phydev)
{
int pg;
/* Configure the PHY */
genphy_config_aneg(phydev);
/* Switch the page to access the led register */
pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
MIIM_88E1121_PHY_LED_PAGE);
/* Configure leds */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
MIIM_88E1121_PHY_LED_DEF);
/* Restore the page pointer */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
/* Disable IRQs and de-assert interrupt */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
return 0;
}
/* Marvell 88E1145 */
static int m88e1145_config(struct phy_device *phydev)
{
int reg;
/* Errata E0, E1 */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
MIIM_88E1xxx_PHY_MDI_X_AUTO);
reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
reg |= MIIM_M88E1145_RGMII_RX_DELAY |
MIIM_M88E1145_RGMII_TX_DELAY;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
genphy_config_aneg(phydev);
phy_reset(phydev);
return 0;
}
static int m88e1145_startup(struct phy_device *phydev)
{
genphy_update_link(phydev);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
MIIM_88E1145_PHY_LED_DIRECT);
m88e1xxx_parse_status(phydev);
return 0;
}
/* Marvell 88E1149S */
static int m88e1149_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
genphy_config_aneg(phydev);
phy_reset(phydev);
return 0;
}
static struct phy_driver M88E1011S_driver = {
.name = "Marvell 88E1011S",
.uid = 0x1410c60,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1011s_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver M88E1111S_driver = {
.name = "Marvell 88E1111S",
.uid = 0x1410cc0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1111s_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver M88E1118_driver = {
.name = "Marvell 88E1118",
.uid = 0x1410e10,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1118_config,
.startup = &m88e1118_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver M88E1121R_driver = {
.name = "Marvell 88E1121R",
.uid = 0x1410cb0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1121_config,
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver M88E1145_driver = {
.name = "Marvell 88E1145",
.uid = 0x1410cd0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1145_config,
.startup = &m88e1145_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver M88E1149S_driver = {
.name = "Marvell 88E1149S",
.uid = 0x1410ca0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &m88e1149_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
int phy_marvell_init(void)
{
phy_register(&M88E1149S_driver);
phy_register(&M88E1145_driver);
phy_register(&M88E1121R_driver);
phy_register(&M88E1118_driver);
phy_register(&M88E1111S_driver);
phy_register(&M88E1011S_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/marvell.c
|
C
|
gpl3
| 12,827
|
/*
* Broadcom PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <config.h>
#include <common.h>
#include <phy.h>
/* Broadcom BCM54xx -- taken from linux sungem_phy */
#define MIIM_BCM54xx_AUXCNTL 0x18
#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7))
#define MIIM_BCM54xx_AUXSTATUS 0x19
#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
#define MIIM_BCM54XX_SHD 0x1c
#define MIIM_BCM54XX_SHD_WRITE 0x8000
#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \
(MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
MIIM_BCM54XX_SHD_DATA(data))
#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
/* Broadcom BCM5461S */
static int bcm5461_config(struct phy_device *phydev)
{
genphy_config_aneg(phydev);
phy_reset(phydev);
return 0;
}
static int bcm54xx_parse_status(struct phy_device *phydev)
{
unsigned int mii_reg;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS);
switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
case 1:
phydev->duplex = DUPLEX_HALF;
phydev->speed = SPEED_10;
break;
case 2:
phydev->duplex = DUPLEX_FULL;
phydev->speed = SPEED_10;
break;
case 3:
phydev->duplex = DUPLEX_HALF;
phydev->speed = SPEED_100;
break;
case 5:
phydev->duplex = DUPLEX_FULL;
phydev->speed = SPEED_100;
break;
case 6:
phydev->duplex = DUPLEX_HALF;
phydev->speed = SPEED_1000;
break;
case 7:
phydev->duplex = DUPLEX_FULL;
phydev->speed = SPEED_1000;
break;
default:
printf("Auto-neg error, defaulting to 10BT/HD\n");
phydev->duplex = DUPLEX_HALF;
phydev->speed = SPEED_10;
break;
}
return 0;
}
static int bcm54xx_startup(struct phy_device *phydev)
{
/* Read the Status (2x to make sure link is right) */
genphy_update_link(phydev);
bcm54xx_parse_status(phydev);
return 0;
}
/* Broadcom BCM5482S */
/*
* "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
* circumstances. eg a gigabit TSEC connected to a gigabit switch with
* a 4-wire ethernet cable. Both ends advertise gigabit, but can't
* link. "Ethernet@Wirespeed" reduces advertised speed until link
* can be achieved.
*/
static u32 bcm5482_read_wirespeed(struct phy_device *phydev, u32 reg)
{
return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010;
}
static int bcm5482_config(struct phy_device *phydev)
{
unsigned int reg;
/* reset the PHY */
reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
reg |= BMCR_RESET;
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
/* Setup read from auxilary control shadow register 7 */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
MIIM_BCM54xx_AUXCNTL_ENCODE(7));
/* Read Misc Control register and or in Ethernet@Wirespeed */
reg = bcm5482_read_wirespeed(phydev, MIIM_BCM54xx_AUXCNTL);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg);
/* Initial config/enable of secondary SerDes interface */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf));
/* Write intial value to secondary SerDes Contol */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
MIIM_BCM54XX_EXP_SEL_SSD | 0);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA,
BMCR_ANRESTART);
/* Enable copper/fiber auto-detect */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201));
genphy_config_aneg(phydev);
return 0;
}
/*
* Find out if PHY is in copper or serdes mode by looking at Expansion Reg
* 0x42 - "Operating Mode Status Register"
*/
static int bcm5482_is_serdes(struct phy_device *phydev)
{
u16 val;
int serdes = 0;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
MIIM_BCM54XX_EXP_SEL_ER | 0x42);
val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
switch (val & 0x1f) {
case 0x0d: /* RGMII-to-100Base-FX */
case 0x0e: /* RGMII-to-SGMII */
case 0x0f: /* RGMII-to-SerDes */
case 0x12: /* SGMII-to-SerDes */
case 0x13: /* SGMII-to-100Base-FX */
case 0x16: /* SerDes-to-Serdes */
serdes = 1;
break;
case 0x6: /* RGMII-to-Copper */
case 0x14: /* SGMII-to-Copper */
case 0x17: /* SerDes-to-Copper */
break;
default:
printf("ERROR, invalid PHY mode (0x%x\n)", val);
break;
}
return serdes;
}
/*
* Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
* Mode Status Register"
*/
static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev)
{
u16 val;
int i = 0;
/* Wait 1s for link - Clause 37 autonegotiation happens very fast */
while (1) {
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
MIIM_BCM54XX_EXP_SEL_ER | 0x42);
val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
if (val & 0x8000)
break;
if (i++ > 1000) {
phydev->link = 0;
return 1;
}
udelay(1000); /* 1 ms */
}
phydev->link = 1;
switch ((val >> 13) & 0x3) {
case (0x00):
phydev->speed = 10;
break;
case (0x01):
phydev->speed = 100;
break;
case (0x02):
phydev->speed = 1000;
break;
}
phydev->duplex = (val & 0x1000) == 0x1000;
return 0;
}
/*
* Figure out if BCM5482 is in serdes or copper mode and determine link
* configuration accordingly
*/
static int bcm5482_startup(struct phy_device *phydev)
{
if (bcm5482_is_serdes(phydev)) {
bcm5482_parse_serdes_sr(phydev);
phydev->port = PORT_FIBRE;
} else {
/* Wait for auto-negotiation to complete or fail */
genphy_update_link(phydev);
/* Parse BCM54xx copper aux status register */
bcm54xx_parse_status(phydev);
}
return 0;
}
static struct phy_driver BCM5461S_driver = {
.name = "Broadcom BCM5461S",
.uid = 0x2060c0,
.mask = 0xfffff0,
.features = PHY_GBIT_FEATURES,
.config = &bcm5461_config,
.startup = &bcm54xx_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver BCM5464S_driver = {
.name = "Broadcom BCM5464S",
.uid = 0x2060b0,
.mask = 0xfffff0,
.features = PHY_GBIT_FEATURES,
.config = &bcm5461_config,
.startup = &bcm54xx_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver BCM5482S_driver = {
.name = "Broadcom BCM5482S",
.uid = 0x143bcb0,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
.config = &bcm5482_config,
.startup = &bcm5482_startup,
.shutdown = &genphy_shutdown,
};
int phy_broadcom_init(void)
{
phy_register(&BCM5482S_driver);
phy_register(&BCM5464S_driver);
phy_register(&BCM5461S_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/broadcom.c
|
C
|
gpl3
| 7,552
|
/*
* Micrel PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <phy.h>
static struct phy_driver KSZ804_driver = {
.name = "Micrel KSZ804",
.uid = 0x221510,
.mask = 0xfffff0,
.features = PHY_BASIC_FEATURES,
.config = &genphy_config,
.startup = &genphy_startup,
.shutdown = &genphy_shutdown,
};
int phy_micrel_init(void)
{
phy_register(&KSZ804_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/micrel.c
|
C
|
gpl3
| 1,149
|
/*
* Vitesse PHY drivers
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
* author Andy Fleming
*
*/
#include <miiphy.h>
/* Cicada Auxiliary Control/Status Register */
#define MIIM_CIS82xx_AUX_CONSTAT 0x1c
#define MIIM_CIS82xx_AUXCONSTAT_INIT 0x0004
#define MIIM_CIS82xx_AUXCONSTAT_DUPLEX 0x0020
#define MIIM_CIS82xx_AUXCONSTAT_SPEED 0x0018
#define MIIM_CIS82xx_AUXCONSTAT_GBIT 0x0010
#define MIIM_CIS82xx_AUXCONSTAT_100 0x0008
/* Cicada Extended Control Register 1 */
#define MIIM_CIS82xx_EXT_CON1 0x17
#define MIIM_CIS8201_EXTCON1_INIT 0x0000
/* Cicada 8204 Extended PHY Control Register 1 */
#define MIIM_CIS8204_EPHY_CON 0x17
#define MIIM_CIS8204_EPHYCON_INIT 0x0006
#define MIIM_CIS8204_EPHYCON_RGMII 0x1100
/* Cicada 8204 Serial LED Control Register */
#define MIIM_CIS8204_SLED_CON 0x1b
#define MIIM_CIS8204_SLEDCON_INIT 0x1115
/* Vitesse VSC8601 Extended PHY Control Register 1 */
#define MIIM_VSC8601_EPHY_CON 0x17
#define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120
#define MIIM_VSC8601_SKEW_CTRL 0x1c
#define PHY_EXT_PAGE_ACCESS 0x1f
/* CIS8201 */
static int vitesse_config(struct phy_device *phydev)
{
/* Override PHY config settings */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
MIIM_CIS82xx_AUXCONSTAT_INIT);
/* Set up the interface mode */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1,
MIIM_CIS8201_EXTCON1_INIT);
genphy_config_aneg(phydev);
return 0;
}
static int vitesse_parse_status(struct phy_device *phydev)
{
int speed;
int mii_reg;
mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT);
if (mii_reg & MIIM_CIS82xx_AUXCONSTAT_DUPLEX)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
speed = mii_reg & MIIM_CIS82xx_AUXCONSTAT_SPEED;
switch (speed) {
case MIIM_CIS82xx_AUXCONSTAT_GBIT:
phydev->speed = SPEED_1000;
break;
case MIIM_CIS82xx_AUXCONSTAT_100:
phydev->speed = SPEED_100;
break;
default:
phydev->speed = SPEED_10;
break;
}
return 0;
}
static int vitesse_startup(struct phy_device *phydev)
{
genphy_update_link(phydev);
vitesse_parse_status(phydev);
return 0;
}
static int cis8204_config(struct phy_device *phydev)
{
/* Override PHY config settings */
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT,
MIIM_CIS82xx_AUXCONSTAT_INIT);
genphy_config_aneg(phydev);
if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
MIIM_CIS8204_EPHYCON_INIT |
MIIM_CIS8204_EPHYCON_RGMII);
else
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON,
MIIM_CIS8204_EPHYCON_INIT);
return 0;
}
/* Vitesse VSC8601 */
int vsc8601_config(struct phy_device *phydev)
{
/* Configure some basic stuff */
#ifdef CONFIG_SYS_VSC8601_SKEWFIX
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_EPHY_CON,
MIIM_VSC8601_EPHY_CON_INIT_SKEW);
#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 1);
#define VSC8101_SKEW \
((CONFIG_SYS_VSC8601_SKEW_TX << 14) \
| (CONFIG_SYS_VSC8601_SKEW_RX << 12))
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8601_SKEW_CTRL,
VSC8101_SKEW);
phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
#endif
#endif
genphy_config_aneg(phydev);
return 0;
}
static struct phy_driver VSC8211_driver = {
.name = "Vitesse VSC8211",
.uid = 0xfc4b0,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &vitesse_config,
.startup = &vitesse_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver VSC8221_driver = {
.name = "Vitesse VSC8221",
.uid = 0xfc550,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &genphy_config_aneg,
.startup = &vitesse_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver VSC8244_driver = {
.name = "Vitesse VSC8244",
.uid = 0xfc6c0,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &genphy_config_aneg,
.startup = &vitesse_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver VSC8234_driver = {
.name = "Vitesse VSC8234",
.uid = 0xfc620,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &genphy_config_aneg,
.startup = &vitesse_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver VSC8601_driver = {
.name = "Vitesse VSC8601",
.uid = 0x70420,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &vsc8601_config,
.startup = &vitesse_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver VSC8641_driver = {
.name = "Vitesse VSC8641",
.uid = 0x70430,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &genphy_config_aneg,
.startup = &vitesse_startup,
.shutdown = &genphy_shutdown,
};
/* Vitesse bought Cicada, so we'll put these here */
static struct phy_driver cis8201_driver = {
.name = "CIS8201",
.uid = 0xfc410,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &vitesse_config,
.startup = &vitesse_startup,
.shutdown = &genphy_shutdown,
};
static struct phy_driver cis8204_driver = {
.name = "Cicada Cis8204",
.uid = 0xfc440,
.mask = 0xffff0,
.features = PHY_GBIT_FEATURES,
.config = &cis8204_config,
.startup = &vitesse_startup,
.shutdown = &genphy_shutdown,
};
int phy_vitesse_init(void)
{
phy_register(&VSC8641_driver);
phy_register(&VSC8601_driver);
phy_register(&VSC8234_driver);
phy_register(&VSC8244_driver);
phy_register(&VSC8211_driver);
phy_register(&VSC8221_driver);
phy_register(&cis8201_driver);
phy_register(&cis8204_driver);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/vitesse.c
|
C
|
gpl3
| 6,413
|
/*
* (C) Copyright 2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
*
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This provides a bit-banged interface to the ethernet MII management
* channel.
*/
#include <common.h>
#include <ioports.h>
#include <ppc_asm.tmpl>
#include <miiphy.h>
#define BB_MII_RELOCATE(v,off) (v += (v?off:0))
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_BITBANGMII_MULTI
/*
* If CONFIG_BITBANGMII_MULTI is not defined we use a
* compatibility layer with the previous miiphybb implementation
* based on macros usage.
*
*/
static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
{
#ifdef MII_INIT
MII_INIT;
#endif
return 0;
}
static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
{
#ifdef MDIO_DECLARE
MDIO_DECLARE;
#endif
MDIO_ACTIVE;
return 0;
}
static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
{
#ifdef MDIO_DECLARE
MDIO_DECLARE;
#endif
MDIO_TRISTATE;
return 0;
}
static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
{
#ifdef MDIO_DECLARE
MDIO_DECLARE;
#endif
MDIO(v);
return 0;
}
static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
{
#ifdef MDIO_DECLARE
MDIO_DECLARE;
#endif
*v = MDIO_READ;
return 0;
}
static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
{
#ifdef MDC_DECLARE
MDC_DECLARE;
#endif
MDC(v);
return 0;
}
static int bb_delay_wrap(struct bb_miiphy_bus *bus)
{
MIIDELAY;
return 0;
}
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = BB_MII_DEVNAME,
.init = bb_mii_init_wrap,
.mdio_active = bb_mdio_active_wrap,
.mdio_tristate = bb_mdio_tristate_wrap,
.set_mdio = bb_set_mdio_wrap,
.get_mdio = bb_get_mdio_wrap,
.set_mdc = bb_set_mdc_wrap,
.delay = bb_delay_wrap,
}
};
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);
#endif
void bb_miiphy_init(void)
{
int i;
for (i = 0; i < bb_miiphy_buses_num; i++) {
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/* Relocate the hook pointers*/
BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off);
BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off);
BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off);
BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off);
BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off);
#endif
if (bb_miiphy_buses[i].init != NULL) {
bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
}
}
}
static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
{
#ifdef CONFIG_BITBANGMII_MULTI
int i;
/* Search the correct bus */
for (i = 0; i < bb_miiphy_buses_num; i++) {
if (!strcmp(bb_miiphy_buses[i].name, devname)) {
return &bb_miiphy_buses[i];
}
}
return NULL;
#else
/* We have just one bitbanging bus */
return &bb_miiphy_buses[0];
#endif
}
/*****************************************************************************
*
* Utility to send the preamble, address, and register (common to read
* and write).
*/
static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
unsigned char addr, unsigned char reg)
{
int j;
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
* The IEEE spec says this is a PHY optional requirement. The AMD
* 79C874 requires one after power up and one after a MII communications
* error. This means that we are doing more preambles than we need,
* but it is safer and will be much more robust.
*/
bus->mdio_active(bus);
bus->set_mdio(bus, 1);
for (j = 0; j < 32; j++) {
bus->set_mdc(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
}
/* send the start bit (01) and the read opcode (10) or write (10) */
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->set_mdio(bus, read);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->set_mdio(bus, !read);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
/* send the PHY address */
for (j = 0; j < 5; j++) {
bus->set_mdc(bus, 0);
if ((addr & 0x10) == 0) {
bus->set_mdio(bus, 0);
} else {
bus->set_mdio(bus, 1);
}
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
addr <<= 1;
}
/* send the register address */
for (j = 0; j < 5; j++) {
bus->set_mdc(bus, 0);
if ((reg & 0x10) == 0) {
bus->set_mdio(bus, 0);
} else {
bus->set_mdio(bus, 1);
}
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
reg <<= 1;
}
}
/*****************************************************************************
*
* Read a MII PHY register.
*
* Returns:
* 0 on success
*/
int bb_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
int v;
int j; /* counter */
struct bb_miiphy_bus *bus;
bus = bb_miiphy_getbus(devname);
if (bus == NULL) {
return -1;
}
if (value == NULL) {
puts("NULL value pointer\n");
return -1;
}
miiphy_pre (bus, 1, addr, reg);
/* tri-state our MDIO I/O pin so we can read */
bus->set_mdc(bus, 0);
bus->mdio_tristate(bus);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
/* check the turnaround bit: the PHY should be driving it to zero */
bus->get_mdio(bus, &v);
if (v != 0) {
/* puts ("PHY didn't drive TA low\n"); */
for (j = 0; j < 32; j++) {
bus->set_mdc(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
}
/* There is no PHY, set value to 0xFFFF and return */
*value = 0xFFFF;
return -1;
}
bus->set_mdc(bus, 0);
bus->delay(bus);
/* read 16 bits of register data, MSB first */
rdreg = 0;
for (j = 0; j < 16; j++) {
bus->set_mdc(bus, 1);
bus->delay(bus);
rdreg <<= 1;
bus->get_mdio(bus, &v);
rdreg |= (v & 0x1);
bus->set_mdc(bus, 0);
bus->delay(bus);
}
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
*value = rdreg;
#ifdef DEBUG
printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value);
#endif
return 0;
}
/*****************************************************************************
*
* Write a MII PHY register.
*
* Returns:
* 0 on success
*/
int bb_miiphy_write (const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
struct bb_miiphy_bus *bus;
int j; /* counter */
bus = bb_miiphy_getbus(devname);
if (bus == NULL) {
/* Bus not found! */
return -1;
}
miiphy_pre (bus, 0, addr, reg);
/* send the turnaround (10) */
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
bus->set_mdc(bus, 0);
bus->set_mdio(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
/* write 16 bits of register data, MSB first */
for (j = 0; j < 16; j++) {
bus->set_mdc(bus, 0);
if ((value & 0x00008000) == 0) {
bus->set_mdio(bus, 0);
} else {
bus->set_mdio(bus, 1);
}
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
value <<= 1;
}
/*
* Tri-state the MDIO line.
*/
bus->mdio_tristate(bus);
bus->set_mdc(bus, 0);
bus->delay(bus);
bus->set_mdc(bus, 1);
bus->delay(bus);
return 0;
}
|
1001-study-uboot
|
drivers/net/phy/miiphybb.c
|
C
|
gpl3
| 8,294
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* (C) Copyright 2003
* Ingo Assmus <ingo.assmus@keymile.com>
*
* based on - Driver for MV64360X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <net.h>
#include <malloc.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/types.h>
#include <asm/system.h>
#include <asm/byteorder.h>
#include <asm/arch/cpu.h>
#if defined(CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
#elif defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
#endif
#include "mvgbe.h"
DECLARE_GLOBAL_DATA_PTR;
#define MV_PHY_ADR_REQUEST 0xee
#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
/*
* smi_reg_read - miiphy_read callback function.
*
* Returns 16bit phy register value, or 0xffff on error
*/
static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr read request */
if (phy_adr == MV_PHY_ADR_REQUEST &&
reg_ofs == MV_PHY_ADR_REQUEST) {
/* */
*data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
return 0;
}
/* check parameters */
if (phy_adr > PHYADR_MASK) {
printf("Err..(%s) Invalid PHY address %d\n",
__FUNCTION__, phy_adr);
return -EFAULT;
}
if (reg_ofs > PHYREG_MASK) {
printf("Err..(%s) Invalid register offset %d\n",
__FUNCTION__, reg_ofs);
return -EFAULT;
}
timeout = MVGBE_PHY_SMI_TIMEOUT;
/* wait till the SMI is not busy */
do {
/* read smi register */
smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -EFAULT;
}
} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
/* fill the phy address and regiser offset and read opcode */
smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
| MVGBE_PHY_SMI_OPCODE_READ;
/* write the smi register */
MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
/*wait till read value is ready */
timeout = MVGBE_PHY_SMI_TIMEOUT;
do {
/* read smi register */
smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI read ready timeout\n",
__FUNCTION__);
return -EFAULT;
}
} while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
/* Wait for the data to update in the SMI register */
for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
;
*data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
reg_ofs, *data);
return 0;
}
/*
* smi_reg_write - imiiphy_write callback function.
*
* Returns 0 if write succeed, -EINVAL on bad parameters
* -ETIME on timeout
*/
static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr write request*/
if (phy_adr == MV_PHY_ADR_REQUEST &&
reg_ofs == MV_PHY_ADR_REQUEST) {
MVGBE_REG_WR(regs->phyadr, data);
return 0;
}
/* check parameters */
if (phy_adr > PHYADR_MASK) {
printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
return -EINVAL;
}
if (reg_ofs > PHYREG_MASK) {
printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
return -EINVAL;
}
/* wait till the SMI is not busy */
timeout = MVGBE_PHY_SMI_TIMEOUT;
do {
/* read smi register */
smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -ETIME;
}
} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
/* fill the phy addr and reg offset and write opcode and data */
smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
/* write the smi register */
MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
return 0;
}
/* Stop and checks all queues */
static void stop_queue(u32 * qreg)
{
u32 reg_data;
reg_data = readl(qreg);
if (reg_data & 0xFF) {
/* Issue stop command for active channels only */
writel((reg_data << 8), qreg);
/* Wait for all queue activity to terminate. */
do {
/*
* Check port cause register that all queues
* are stopped
*/
reg_data = readl(qreg);
}
while (reg_data & 0xFF);
}
}
/*
* set_access_control - Config address decode parameters for Ethernet unit
*
* This function configures the address decode parameters for the Gigabit
* Ethernet Controller according the given parameters struct.
*
* @regs Register struct pointer.
* @param Address decode parameter struct.
*/
static void set_access_control(struct mvgbe_registers *regs,
struct mvgbe_winparam *param)
{
u32 access_prot_reg;
/* Set access control register */
access_prot_reg = MVGBE_REG_RD(regs->epap);
/* clear window permission */
access_prot_reg &= (~(3 << (param->win * 2)));
access_prot_reg |= (param->access_ctrl << (param->win * 2));
MVGBE_REG_WR(regs->epap, access_prot_reg);
/* Set window Size reg (SR) */
MVGBE_REG_WR(regs->barsz[param->win].size,
(((param->size / 0x10000) - 1) << 16));
/* Set window Base address reg (BA) */
MVGBE_REG_WR(regs->barsz[param->win].bar,
(param->target | param->attrib | param->base_addr));
/* High address remap reg (HARR) */
if (param->win < 4)
MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
/* Base address enable reg (BARER) */
if (param->enable == 1)
MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
else
MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
}
static void set_dram_access(struct mvgbe_registers *regs)
{
struct mvgbe_winparam win_param;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Set access parameters for DRAM bank i */
win_param.win = i; /* Use Ethernet window i */
/* Window target - DDR */
win_param.target = MVGBE_TARGET_DRAM;
/* Enable full access */
win_param.access_ctrl = EWIN_ACCESS_FULL;
win_param.high_addr = 0;
/* Get bank base and size */
win_param.base_addr = gd->bd->bi_dram[i].start;
win_param.size = gd->bd->bi_dram[i].size;
if (win_param.size == 0)
win_param.enable = 0;
else
win_param.enable = 1; /* Enable the access */
/* Enable DRAM bank */
switch (i) {
case 0:
win_param.attrib = EBAR_DRAM_CS0;
break;
case 1:
win_param.attrib = EBAR_DRAM_CS1;
break;
case 2:
win_param.attrib = EBAR_DRAM_CS2;
break;
case 3:
win_param.attrib = EBAR_DRAM_CS3;
break;
default:
/* invalid bank, disable access */
win_param.enable = 0;
win_param.attrib = 0;
break;
}
/* Set the access control for address window(EPAPR) RD/WR */
set_access_control(regs, &win_param);
}
}
/*
* port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
*
* Go through all the DA filter tables (Unicast, Special Multicast & Other
* Multicast) and set each entry to 0.
*/
static void port_init_mac_tables(struct mvgbe_registers *regs)
{
int table_index;
/* Clear DA filter unicast table (Ex_dFUT) */
for (table_index = 0; table_index < 4; ++table_index)
MVGBE_REG_WR(regs->dfut[table_index], 0);
for (table_index = 0; table_index < 64; ++table_index) {
/* Clear DA filter special multicast table (Ex_dFSMT) */
MVGBE_REG_WR(regs->dfsmt[table_index], 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */
MVGBE_REG_WR(regs->dfomt[table_index], 0);
}
}
/*
* port_uc_addr - This function Set the port unicast address table
*
* This function locates the proper entry in the Unicast table for the
* specified MAC nibble and sets its properties according to function
* parameters.
* This function add/removes MAC addresses from the port unicast address
* table.
*
* @uc_nibble Unicast MAC Address last nibble.
* @option 0 = Add, 1 = remove address.
*
* RETURN: 1 if output succeeded. 0 if option parameter is invalid.
*/
static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
int option)
{
u32 unicast_reg;
u32 tbl_offset;
u32 reg_offset;
/* Locate the Unicast table entry */
uc_nibble = (0xf & uc_nibble);
/* Register offset from unicast table base */
tbl_offset = (uc_nibble / 4);
/* Entry offset within the above register */
reg_offset = uc_nibble % 4;
switch (option) {
case REJECT_MAC_ADDR:
/*
* Clear accepts frame bit at specified unicast
* DA table entry
*/
unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
case ACCEPT_MAC_ADDR:
/* Set accepts frame bit at unicast DA filter table entry */
unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
default:
return 0;
}
return 1;
}
/*
* port_uc_addr_set - This function Set the port Unicast address.
*/
static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
{
u32 mac_h;
u32 mac_l;
mac_l = (p_addr[4] << 8) | (p_addr[5]);
mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
(p_addr[3] << 0);
MVGBE_REG_WR(regs->macal, mac_l);
MVGBE_REG_WR(regs->macah, mac_h);
/* Accept frames of this address */
port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
}
/*
* mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
*/
static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
{
struct mvgbe_rxdesc *p_rx_desc;
int i;
/* initialize the Rx descriptors ring */
p_rx_desc = dmvgbe->p_rxdesc;
for (i = 0; i < RINGSZ; i++) {
p_rx_desc->cmd_sts =
MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
p_rx_desc->buf_size = PKTSIZE_ALIGN;
p_rx_desc->byte_cnt = 0;
p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
if (i == (RINGSZ - 1))
p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
else {
p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
p_rx_desc = p_rx_desc->nxtdesc_p;
}
}
dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
}
static int mvgbe_init(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
mvgbe_init_rx_desc_ring(dmvgbe);
/* Clear the ethernet port interrupts */
MVGBE_REG_WR(regs->ic, 0);
MVGBE_REG_WR(regs->ice, 0);
/* Unmask RX buffer and TX end interrupt */
MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
/* Unmask phy and link status changes interrupts */
MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
set_dram_access(regs);
port_init_mac_tables(regs);
port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
/* Assign port configuration and command. */
MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
/* Assign port SDMA configuration */
MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
MVGBE_REG_WR(regs->tqx[0].tqxtbc,
(QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
/* Turn off the port/RXUQ bandwidth limitation */
MVGBE_REG_WR(regs->pmtu, 0);
/* Set maximum receive buffer to 9700 bytes */
MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
| (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
/* Enable port initially */
MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
/*
* Set ethernet MTU for leaky bucket mechanism to 0 - this will
* disable the leaky bucket mechanism .
*/
MVGBE_REG_WR(regs->pmtu, 0);
/* Assignment of Rx CRDB of given RXUQ */
MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
/* ensure previous write is done before enabling Rx DMA */
isb();
/* Enable port Rx. */
MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
/* Wait up to 5s for the link status */
for (i = 0; i < 5; i++) {
u16 phyadr;
miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
if (miiphy_link(dev->name, phyadr))
return 0;
udelay(1000000);
}
printf("No link on %s\n", dev->name);
return -1;
#endif
return 0;
}
static int mvgbe_halt(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
/* Disable all gigE address decoder */
MVGBE_REG_WR(regs->bare, 0x3f);
stop_queue(®s->tqc);
stop_queue(®s->rqc);
/* Disable port */
MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
/* Set port is not reset */
MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
#ifdef CONFIG_SYS_MII_MODE
/* Set MMI interface up */
MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
#endif
/* Disable & mask ethernet port interrupts */
MVGBE_REG_WR(regs->ic, 0);
MVGBE_REG_WR(regs->ice, 0);
MVGBE_REG_WR(regs->pim, 0);
MVGBE_REG_WR(regs->peim, 0);
return 0;
}
static int mvgbe_write_hwaddr(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
/* Programs net device MAC address after initialization */
port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
return 0;
}
static int mvgbe_send(struct eth_device *dev, void *dataptr,
int datasize)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe->regs;
struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
void *p = (void *)dataptr;
u32 cmd_sts;
u32 txuq0_reg_addr;
/* Copy buffer if it's misaligned */
if ((u32) dataptr & 0x07) {
if (datasize > PKTSIZE_ALIGN) {
printf("Non-aligned data too large (%d)\n",
datasize);
return -1;
}
memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
p = dmvgbe->p_aligned_txbuf;
}
p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
p_txdesc->buf_ptr = (u8 *) p;
p_txdesc->byte_cnt = datasize;
/* Set this tc desc as zeroth TXUQ */
txuq0_reg_addr = (u32)®s->tcqdp[TXUQ];
writel((u32) p_txdesc, txuq0_reg_addr);
/* ensure tx desc writes above are performed before we start Tx DMA */
isb();
/* Apply send command using zeroth TXUQ */
MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
/*
* wait for packet xmit completion
*/
cmd_sts = readl(&p_txdesc->cmd_sts);
while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
/* return fail if error is detected */
if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
(MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
printf("Err..(%s) in xmit packet\n", __FUNCTION__);
return -1;
}
cmd_sts = readl(&p_txdesc->cmd_sts);
};
return 0;
}
static int mvgbe_recv(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
u32 rxdesc_curr_addr;
/* wait untill rx packet available or timeout */
do {
if (timeout < MVGBE_PHY_SMI_TIMEOUT)
timeout++;
else {
debug("%s time out...\n", __FUNCTION__);
return -1;
}
} while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
if (p_rxdesc_curr->byte_cnt != 0) {
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
__FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
(u32) p_rxdesc_curr->buf_ptr,
(u32) p_rxdesc_curr->cmd_sts);
}
/*
* In case received a packet without first/last bits on
* OR the error summary bit is on,
* the packets needs to be dropeed.
*/
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
if ((cmd_sts &
(MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
!= (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
printf("Err..(%s) Dropping packet spread on"
" multiple descriptors\n", __FUNCTION__);
} else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
printf("Err..(%s) Dropping packet with errors\n",
__FUNCTION__);
} else {
/* !!! call higher layer processing */
debug("%s: Sending Received packet to"
" upper layer (NetReceive)\n", __FUNCTION__);
/* let the upper layer handle the packet */
NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
(int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
}
/*
* free these descriptors and point next in the ring
*/
p_rxdesc_curr->cmd_sts =
MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
return 0;
}
int mvgbe_initialize(bd_t *bis)
{
struct mvgbe_device *dmvgbe;
struct eth_device *dev;
int devnum;
char *s;
u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
/*skip if port is configured not to use */
if (used_ports[devnum] == 0)
continue;
dmvgbe = malloc(sizeof(struct mvgbe_device));
if (!dmvgbe)
goto error1;
memset(dmvgbe, 0, sizeof(struct mvgbe_device));
dmvgbe->p_rxdesc =
(struct mvgbe_rxdesc *)memalign(PKTALIGN,
MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
if (!dmvgbe->p_rxdesc)
goto error2;
dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
RINGSZ*PKTSIZE_ALIGN + 1);
if (!dmvgbe->p_rxbuf)
goto error3;
dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
if (!dmvgbe->p_aligned_txbuf)
goto error4;
dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
if (!dmvgbe->p_txdesc) {
free(dmvgbe->p_aligned_txbuf);
error4:
free(dmvgbe->p_rxbuf);
error3:
free(dmvgbe->p_rxdesc);
error2:
free(dmvgbe);
error1:
printf("Err.. %s Failed to allocate memory\n",
__FUNCTION__);
return -1;
}
dev = &dmvgbe->dev;
/* must be less than NAMESIZE (16) */
sprintf(dev->name, "egiga%d", devnum);
/* Extract the MAC address from the environment */
switch (devnum) {
case 0:
dmvgbe->regs = (void *)MVGBE0_BASE;
s = "ethaddr";
break;
#if defined(MVGBE1_BASE)
case 1:
dmvgbe->regs = (void *)MVGBE1_BASE;
s = "eth1addr";
break;
#endif
default: /* this should never happen */
printf("Err..(%s) Invalid device number %d\n",
__FUNCTION__, devnum);
return -1;
}
while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
/* Generate Private MAC addr if not set */
dev->enetaddr[0] = 0x02;
dev->enetaddr[1] = 0x50;
dev->enetaddr[2] = 0x43;
#if defined (CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION)
/* Generate fixed lower MAC half using devnum */
dev->enetaddr[3] = 0;
dev->enetaddr[4] = 0;
dev->enetaddr[5] = devnum;
#else
/* Generate random lower MAC half */
dev->enetaddr[3] = get_random_hex();
dev->enetaddr[4] = get_random_hex();
dev->enetaddr[5] = get_random_hex();
#endif
eth_setenv_enetaddr(s, dev->enetaddr);
}
dev->init = (void *)mvgbe_init;
dev->halt = (void *)mvgbe_halt;
dev->send = (void *)mvgbe_send;
dev->recv = (void *)mvgbe_recv;
dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, smi_reg_read, smi_reg_write);
/* Set phy address of the port */
miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
#endif
}
return 0;
}
|
1001-study-uboot
|
drivers/net/mvgbe.c
|
C
|
gpl3
| 20,613
|
/*
* Copyright (C) 2004 IMMS gGmbH <www.imms.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* author(s): Thomas Elste, <info@elste.org>
* (some parts derived from uCLinux Netarm Ethernet Driver)
*/
#include <common.h>
#include <command.h>
#include <net.h>
#include "netarm_eth.h"
#include <asm/arch/netarm_registers.h>
static int na_mii_poll_busy (void);
static void na_get_mac_addr (void)
{
unsigned short p[3];
char *m_addr;
char ethaddr[20];
m_addr = (char *) p;
p[0] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_1);
p[1] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_2);
p[2] = (unsigned short) GET_EADDR (NETARM_ETH_SAL_STATION_ADDR_3);
sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
m_addr[0], m_addr[1],
m_addr[2], m_addr[3], m_addr[4], m_addr[5]);
printf ("HW-MAC Address: %s\n", ethaddr);
/* set env, todo: check if already an adress is set */
setenv ("ethaddr", ethaddr);
}
static void na_mii_write (int reg, int value)
{
int mii_addr;
/* Select register */
mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
/* Write value */
SET_EADDR (NETARM_ETH_MII_WRITE, value);
na_mii_poll_busy ();
}
static unsigned int na_mii_read (int reg)
{
int mii_addr, val;
/* Select register */
mii_addr = CONFIG_SYS_ETH_PHY_ADDR + reg;
SET_EADDR (NETARM_ETH_MII_ADDR, mii_addr);
/* do one management cycle */
SET_EADDR (NETARM_ETH_MII_CMD,
GET_EADDR (NETARM_ETH_MII_CMD) | NETARM_ETH_MIIC_RSTAT);
na_mii_poll_busy ();
/* Return read value */
val = GET_EADDR (NETARM_ETH_MII_READ);
return val;
}
static int na_mii_poll_busy (void)
{
ulong start;
/* arm simple, non interrupt dependent timer */
start = get_timer(0));
while (get_timer(start) < NA_MII_POLL_BUSY_DELAY) {
if (!(GET_EADDR (NETARM_ETH_MII_IND) & NETARM_ETH_MIII_BUSY)) {
return 1;
}
}
printf ("na_mii_busy timeout\n");
return (0);
}
static int na_mii_identify_phy (void)
{
int id_reg_a = 0;
/* get phy id register */
id_reg_a = na_mii_read (MII_PHY_ID);
if (id_reg_a == 0x0043) {
/* This must be an Enable or a Lucent LU3X31 PHY chip */
return 1;
} else if (id_reg_a == 0x0013) {
/* it is an Intel LXT971A */
return 1;
}
return (0);
}
static int na_mii_negotiate (void)
{
int i = 0;
/* Enable auto-negotiation */
na_mii_write (MII_PHY_AUTONEGADV, 0x01e1);
/* FIXME: 0x01E1 is 100Mb half and full duplex, 0x0061 is 10Mb only */
/* Restart auto-negotiation */
na_mii_write (MII_PHY_CONTROL, 0x1200);
/* status register is 0xffff after setting the autoneg restart bit */
while (na_mii_read (MII_PHY_STATUS) == 0xffff) {
i++;
}
/* na_mii_read uses the timer already, so we can't use it again for
timeout checking.
Instead we just try some times.
*/
for (i = 0; i < 40000; i++) {
if ((na_mii_read (MII_PHY_STATUS) & 0x0024) == 0x0024) {
return 0;
}
}
/*
printf("*Warning* autonegotiation timeout, status: 0x%x\n",na_mii_read(MII_PHY_STATUS));
*/
return (1);
}
static unsigned int na_mii_check_speed (void)
{
unsigned int status;
/* Read Status register */
status = na_mii_read (MII_PHY_STATUS);
/* Check link status. If 0, default to 100 Mbps. */
if ((status & 0x0004) == 0) {
printf ("*Warning* no link detected, set default speed to 100Mbs\n");
return 1;
} else {
if ((na_mii_read (17) & 0x4000) != 0) {
printf ("100Mbs link detected\n");
return 1;
} else {
printf ("10Mbs link detected\n");
return 0;
}
}
return 0;
}
static int reset_eth (void)
{
int pt;
ulong start;
na_get_mac_addr ();
pt = na_mii_identify_phy ();
/* reset the phy */
na_mii_write (MII_PHY_CONTROL, 0x8000);
start = get_timer(0);
while (get_timer(start) < NA_MII_NEGOTIATE_DELAY) {
if ((na_mii_read (MII_PHY_STATUS) & 0x8000) == 0) {
break;
}
}
if (get_timer(start) >= NA_MII_NEGOTIATE_DELAY)
printf ("phy reset timeout\n");
/* set the PCS reg */
SET_EADDR (NETARM_ETH_PCS_CFG, NETARM_ETH_PCSC_CLKS_25M |
NETARM_ETH_PCSC_ENJAB | NETARM_ETH_PCSC_NOCFR);
na_mii_negotiate ();
na_mii_check_speed ();
/* Delay 10 millisecond. (Maybe this should be 1 second.) */
udelay (10000);
/* Turn receive on.
Enable statistics register autozero on read.
Do not insert MAC address on transmit.
Do not enable special test modes. */
SET_EADDR (NETARM_ETH_STL_CFG,
(NETARM_ETH_STLC_AUTOZ | NETARM_ETH_STLC_RXEN));
/* Set the inter-packet gap delay to 0.96us for MII.
The NET+ARM H/W Reference Guide indicates that the Back-to-back IPG
Gap Timer Register should be set to 0x15 and the Non Back-to-back IPG
Gap Timer Register should be set to 0x00000C12 for the MII PHY. */
SET_EADDR (NETARM_ETH_B2B_IPG_GAP_TMR, 0x15);
SET_EADDR (NETARM_ETH_NB2B_IPG_GAP_TMR, 0x00000C12);
/* Add CRC to end of packets.
Pad packets to minimum length of 64 bytes.
Allow unlimited length transmit packets.
Receive all broadcast packets.
NOTE: Multicast addressing is NOT enabled here currently. */
SET_EADDR (NETARM_ETH_MAC_CFG,
(NETARM_ETH_MACC_CRCEN |
NETARM_ETH_MACC_PADEN | NETARM_ETH_MACC_HUGEN));
SET_EADDR (NETARM_ETH_SAL_FILTER, NETARM_ETH_SALF_BROAD);
/* enable fifos */
SET_EADDR (NETARM_ETH_GEN_CTRL,
(NETARM_ETH_GCR_ERX | NETARM_ETH_GCR_ETX));
return (0);
}
extern int eth_init (bd_t * bd)
{
reset_eth ();
return 0;
}
extern void eth_halt (void)
{
SET_EADDR (NETARM_ETH_GEN_CTRL, 0);
}
/* Get a data block via Ethernet */
extern int eth_rx (void)
{
int i;
unsigned short rxlen;
unsigned int *addr;
unsigned int rxstatus, lastrxlen;
char *pa;
/* RXBR is 1, data block was received */
if ((GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXBR) == 0)
return 0;
/* get status register and the length of received block */
rxstatus = GET_EADDR (NETARM_ETH_RX_STAT);
rxlen = (rxstatus & NETARM_ETH_RXSTAT_SIZE) >> 16;
if (rxlen == 0)
return 0;
/* clear RXBR to make fifo available */
SET_EADDR (NETARM_ETH_GEN_STAT,
GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_RXBR);
/* clear TXBC to make fifo available */
/* According to NETARM50 data manual you just have to clear
RXBR but that has no effect. Only after clearing TXBC the
Fifo becomes readable. */
SET_EADDR (NETARM_ETH_GEN_STAT,
GET_EADDR (NETARM_ETH_GEN_STAT) & ~NETARM_ETH_GST_TXBC);
addr = (unsigned int *) NetRxPackets[0];
pa = (char *) NetRxPackets[0];
/* read the fifo */
for (i = 0; i < rxlen / 4; i++) {
*addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
addr++;
}
if (GET_EADDR (NETARM_ETH_GEN_STAT) & NETARM_ETH_GST_RXREGR) {
/* RXFDB indicates wether the last word is 1,2,3 or 4 bytes long */
lastrxlen =
(GET_EADDR (NETARM_ETH_GEN_STAT) &
NETARM_ETH_GST_RXFDB) >> 28;
*addr = GET_EADDR (NETARM_ETH_FIFO_DAT1);
switch (lastrxlen) {
case 1:
*addr &= 0xff000000;
break;
case 2:
*addr &= 0xffff0000;
break;
case 3:
*addr &= 0xffffff00;
break;
}
}
/* Pass the packet up to the protocol layers. */
NetReceive (NetRxPackets[0], rxlen);
return rxlen;
}
/* Send a data block via Ethernet. */
extern int eth_send (volatile void *packet, int length)
{
int i, length32;
char *pa;
unsigned int *pa32, lastp = 0, rest;
pa = (char *) packet;
pa32 = (unsigned int *) packet;
length32 = length / 4;
rest = length % 4;
/* make sure there's no garbage in the last word */
switch (rest) {
case 0:
lastp = pa32[length32];
length32--;
break;
case 1:
lastp = pa32[length32] & 0x000000ff;
break;
case 2:
lastp = pa32[length32] & 0x0000ffff;
break;
case 3:
lastp = pa32[length32] & 0x00ffffff;
break;
}
/* write to the fifo */
for (i = 0; i < length32; i++)
SET_EADDR (NETARM_ETH_FIFO_DAT1, pa32[i]);
/* the last word is written to an extra register, this
starts the transmission */
SET_EADDR (NETARM_ETH_FIFO_DAT2, lastp);
/* NETARM_ETH_TXSTAT_TXOK should be checked, to know if the transmission
went fine. But we can't use the timer for a timeout loop because
of it is used already in upper layers. So we just try some times. */
i = 0;
while (i < 50000) {
if ((GET_EADDR (NETARM_ETH_TX_STAT) & NETARM_ETH_TXSTAT_TXOK)
== NETARM_ETH_TXSTAT_TXOK)
return 0;
i++;
}
printf ("eth_send timeout\n");
return 1;
}
|
1001-study-uboot
|
drivers/net/netarm_eth.c
|
C
|
gpl3
| 8,950
|
/*
* (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include "ax88796.h"
/*
* Set 1 bit data
*/
static void ax88796_bitset(u32 bit)
{
/* DATA1 */
if( bit )
EEDI_HIGH;
else
EEDI_LOW;
EECLK_LOW;
udelay(1000);
EECLK_HIGH;
udelay(1000);
EEDI_LOW;
}
/*
* Get 1 bit data
*/
static u8 ax88796_bitget(void)
{
u8 bit;
EECLK_LOW;
udelay(1000);
/* DATA */
bit = EEDO;
EECLK_HIGH;
udelay(1000);
return bit;
}
/*
* Send COMMAND to EEPROM
*/
static void ax88796_eep_cmd(u8 cmd)
{
ax88796_bitset(BIT_DUMMY);
switch(cmd){
case MAC_EEP_READ:
ax88796_bitset(1);
ax88796_bitset(1);
ax88796_bitset(0);
break;
case MAC_EEP_WRITE:
ax88796_bitset(1);
ax88796_bitset(0);
ax88796_bitset(1);
break;
case MAC_EEP_ERACE:
ax88796_bitset(1);
ax88796_bitset(1);
ax88796_bitset(1);
break;
case MAC_EEP_EWEN:
ax88796_bitset(1);
ax88796_bitset(0);
ax88796_bitset(0);
break;
case MAC_EEP_EWDS:
ax88796_bitset(1);
ax88796_bitset(0);
ax88796_bitset(0);
break;
default:
break;
}
}
static void ax88796_eep_setaddr(u16 addr)
{
int i ;
for( i = 7 ; i >= 0 ; i-- )
ax88796_bitset(addr & (1 << i));
}
/*
* Get data from EEPROM
*/
static u16 ax88796_eep_getdata(void)
{
ushort data = 0;
int i;
ax88796_bitget(); /* DUMMY */
for( i = 0 ; i < 16 ; i++ ){
data <<= 1;
data |= ax88796_bitget();
}
return data;
}
static void ax88796_mac_read(u8 *buff)
{
int i ;
u16 data;
u16 addr = 0;
for( i = 0 ; i < 3; i++ )
{
EECS_HIGH;
EEDI_LOW;
udelay(1000);
/* READ COMMAND */
ax88796_eep_cmd(MAC_EEP_READ);
/* ADDRESS */
ax88796_eep_setaddr(addr++);
/* GET DATA */
data = ax88796_eep_getdata();
*buff++ = (uchar)(data & 0xff);
*buff++ = (uchar)((data >> 8) & 0xff);
EECLK_LOW;
EEDI_LOW;
EECS_LOW;
}
}
int get_prom(u8* mac_addr, u8* base_addr)
{
u8 prom[32];
int i;
ax88796_mac_read(prom);
for (i = 0; i < 6; i++){
mac_addr[i] = prom[i];
}
return 1;
}
|
1001-study-uboot
|
drivers/net/ax88796.c
|
C
|
gpl3
| 2,715
|
/*
* Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
* Jens Scharsig (esw@bus-elektronik.de)
*
* (C) Copyright 2003
* Author : Hamid Ikdoumi (Atmel)
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#ifndef CONFIG_AT91_LEGACY
#include <asm/arch/hardware.h>
#include <asm/arch/at91_emac.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#else
/* remove next 5 lines, if all RM9200 boards convert to at91 arch */
#include <asm/arch-at91/at91rm9200.h>
#include <asm/arch-at91/hardware.h>
#include <asm/arch-at91/at91_emac.h>
#include <asm/arch-at91/at91_pmc.h>
#include <asm/arch-at91/at91_pio.h>
#endif
#include <net.h>
#include <netdev.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mii.h>
#undef MII_DEBUG
#undef ET_DEBUG
#if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
#error AT91 EMAC supports max 1024 RX buffers. \
Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
#endif
#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
#endif
/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
#if (AT91C_MASTER_CLOCK > 80000000)
#define HCLK_DIV AT91_EMAC_CFG_MCLK_64
#elif (AT91C_MASTER_CLOCK > 40000000)
#define HCLK_DIV AT91_EMAC_CFG_MCLK_32
#elif (AT91C_MASTER_CLOCK > 20000000)
#define HCLK_DIV AT91_EMAC_CFG_MCLK_16
#else
#define HCLK_DIV AT91_EMAC_CFG_MCLK_8
#endif
#ifdef ET_DEBUG
#define DEBUG_AT91EMAC 1
#else
#define DEBUG_AT91EMAC 0
#endif
#ifdef MII_DEBUG
#define DEBUG_AT91PHY 1
#else
#define DEBUG_AT91PHY 0
#endif
#ifndef CONFIG_DRIVER_AT91EMAC_QUIET
#define VERBOSEP 1
#else
#define VERBOSEP 0
#endif
#define RBF_ADDR 0xfffffffc
#define RBF_OWNER (1<<0)
#define RBF_WRAP (1<<1)
#define RBF_BROADCAST (1<<31)
#define RBF_MULTICAST (1<<30)
#define RBF_UNICAST (1<<29)
#define RBF_EXTERNAL (1<<28)
#define RBF_UNKNOWN (1<<27)
#define RBF_SIZE 0x07ff
#define RBF_LOCAL4 (1<<26)
#define RBF_LOCAL3 (1<<25)
#define RBF_LOCAL2 (1<<24)
#define RBF_LOCAL1 (1<<23)
#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
#define RBF_FRAMELEN 0x600
typedef struct {
unsigned long addr, size;
} rbf_t;
typedef struct {
rbf_t rbfdt[RBF_FRAMEMAX];
unsigned long rbindex;
} emac_device;
void at91emac_EnableMDIO(at91_emac_t *at91mac)
{
/* Mac CTRL reg set for MDIO enable */
writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
}
void at91emac_DisableMDIO(at91_emac_t *at91mac)
{
/* Mac CTRL reg set for MDIO disable */
writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
}
int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
unsigned char reg, unsigned short *value)
{
unsigned long netstat;
at91emac_EnableMDIO(at91mac);
writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
AT91_EMAC_MAN_PHYA(addr),
&at91mac->man);
do {
netstat = readl(&at91mac->sr);
debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
} while (!(netstat & AT91_EMAC_SR_IDLE));
*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
at91emac_DisableMDIO(at91mac);
debug_cond(DEBUG_AT91PHY,
"AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value);
return 0;
}
int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
unsigned char reg, unsigned short value)
{
unsigned long netstat;
debug_cond(DEBUG_AT91PHY,
"AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value);
at91emac_EnableMDIO(at91mac);
writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
&at91mac->man);
do {
netstat = readl(&at91mac->sr);
debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
} while (!(netstat & AT91_EMAC_SR_IDLE));
at91emac_DisableMDIO(at91mac);
return 0;
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
at91_emac_t *get_emacbase_by_name(const char *devname)
{
struct eth_device *netdev;
netdev = eth_get_dev_by_name(devname);
return (at91_emac_t *) netdev->iobase;
}
int at91emac_mii_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
at91_emac_t *emac;
emac = get_emacbase_by_name(devname);
at91emac_read(emac , addr, reg, value);
return 0;
}
int at91emac_mii_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
at91_emac_t *emac;
emac = get_emacbase_by_name(devname);
at91emac_write(emac, addr, reg, value);
return 0;
}
#endif
static int at91emac_phy_reset(struct eth_device *netdev)
{
int i;
u16 status, adv;
at91_emac_t *emac;
emac = (at91_emac_t *) netdev->iobase;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_ADVERTISE, adv);
debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name);
at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
(BMCR_ANENABLE | BMCR_ANRESTART));
for (i = 0; i < 30000; i++) {
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_BMSR, &status);
if (status & BMSR_ANEGCOMPLETE)
break;
udelay(100);
}
if (status & BMSR_ANEGCOMPLETE) {
debug_cond(VERBOSEP,
"%s: Autonegotiation complete\n", netdev->name);
} else {
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
netdev->name, status);
return -1;
}
return 0;
}
static int at91emac_phy_init(struct eth_device *netdev)
{
u16 phy_id, status, adv, lpa;
int media, speed, duplex;
int i;
at91_emac_t *emac;
emac = (at91_emac_t *) netdev->iobase;
/* Check if the PHY is up to snuff... */
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_PHYSID1, &phy_id);
if (phy_id == 0xffff) {
printf("%s: No PHY present\n", netdev->name);
return -1;
}
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_BMSR, &status);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
if (at91emac_phy_reset(netdev))
return -2;
for (i = 0; i < 100000 / 100; i++) {
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_BMSR, &status);
if (status & BMSR_LSTATUS)
break;
udelay(100);
}
}
if (!(status & BMSR_LSTATUS)) {
debug_cond(VERBOSEP, "%s: link down\n", netdev->name);
return -3;
} else {
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_ADVERTISE, &adv);
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
MII_LPA, &lpa);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
? 1 : 0);
duplex = (media & ADVERTISE_FULL) ? 1 : 0;
debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n",
netdev->name,
speed ? "100" : "10",
duplex ? "full" : "half");
}
return 0;
}
int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
{
unsigned short stat1;
at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
return -1;
if (stat1 & BMSR_100FULL) {
/*set Emac for 100BaseTX and Full Duplex */
writel(readl(&emac->cfg) |
AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
&emac->cfg);
return 0;
}
if (stat1 & BMSR_10FULL) {
/*set MII for 10BaseT and Full Duplex */
writel((readl(&emac->cfg) &
~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
) | AT91_EMAC_CFG_FD,
&emac->cfg);
return 0;
}
if (stat1 & BMSR_100HALF) {
/*set MII for 100BaseTX and Half Duplex */
writel((readl(&emac->cfg) &
~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
) | AT91_EMAC_CFG_SPD,
&emac->cfg);
return 0;
}
if (stat1 & BMSR_10HALF) {
/*set MII for 10BaseT and Half Duplex */
writel((readl(&emac->cfg) &
~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
&emac->cfg);
return 0;
}
return 0;
}
static int at91emac_init(struct eth_device *netdev, bd_t *bd)
{
int i;
u32 value;
emac_device *dev;
at91_emac_t *emac;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
emac = (at91_emac_t *) netdev->iobase;
dev = (emac_device *) netdev->priv;
/* PIO Disable Register */
value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC |
ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 |
ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS |
ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 |
ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK;
writel(value, &pio->pioa.pdr);
writel(value, &pio->pioa.asr);
#ifdef CONFIG_RMII
value = ATMEL_PMX_BA_ERXCK;
#else
value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL |
ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 |
ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER |
ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2;
#endif
writel(value, &pio->piob.pdr);
writel(value, &pio->piob.bsr);
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);
/* Init Ethernet buffers */
for (i = 0; i < RBF_FRAMEMAX; i++) {
dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
dev->rbfdt[i].size = 0;
}
dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
dev->rbindex = 0;
writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
writel(readl(&emac->rsr) &
~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
&emac->rsr);
value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC |
HCLK_DIV;
#ifdef CONFIG_RMII
value |= AT91_EMAC_CFG_RMII;
#endif
writel(value, &emac->cfg);
writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
&emac->ctl);
if (!at91emac_phy_init(netdev)) {
at91emac_UpdateLinkSpeed(emac);
return 0;
}
return -1;
}
static void at91emac_halt(struct eth_device *netdev)
{
at91_emac_t *emac;
emac = (at91_emac_t *) netdev->iobase;
writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
&emac->ctl);
debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
}
static int at91emac_send(struct eth_device *netdev, volatile void *packet,
int length)
{
at91_emac_t *emac;
emac = (at91_emac_t *) netdev->iobase;
while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
;
writel((u32) packet, &emac->tar);
writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
;
debug_cond(DEBUG_AT91EMAC, "Send %d\n", length);
writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
return 0;
}
static int at91emac_recv(struct eth_device *netdev)
{
emac_device *dev;
at91_emac_t *emac;
rbf_t *rbfp;
int size;
emac = (at91_emac_t *) netdev->iobase;
dev = (emac_device *) netdev->priv;
rbfp = &dev->rbfdt[dev->rbindex];
while (rbfp->addr & RBF_OWNER) {
size = rbfp->size & RBF_SIZE;
NetReceive(NetRxPackets[dev->rbindex], size);
debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n",
dev->rbindex, size, rbfp->addr);
rbfp->addr &= ~RBF_OWNER;
rbfp->size = 0;
if (dev->rbindex < (RBF_FRAMEMAX-1))
dev->rbindex++;
else
dev->rbindex = 0;
rbfp = &(dev->rbfdt[dev->rbindex]);
if (!(rbfp->addr & RBF_OWNER))
writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
&emac->rsr);
}
if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
/* EMAC silicon bug 41.3.1 workaround 1 */
writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
dev->rbindex = 0;
printf("%s: reset receiver (EMAC dead lock bug)\n",
netdev->name);
}
return 0;
}
static int at91emac_write_hwaddr(struct eth_device *netdev)
{
at91_emac_t *emac;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
emac = (at91_emac_t *) netdev->iobase;
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
debug_cond(DEBUG_AT91EMAC,
"init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]);
writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 |
netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24),
&emac->sa2l);
writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h);
debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n",
readl(&emac->sa2h), readl(&emac->sa2l));
return 0;
}
int at91emac_register(bd_t *bis, unsigned long iobase)
{
emac_device *emac;
emac_device *emacfix;
struct eth_device *dev;
if (iobase == 0)
iobase = ATMEL_BASE_EMAC;
emac = malloc(sizeof(*emac)+512);
if (emac == NULL)
return -1;
dev = malloc(sizeof(*dev));
if (dev == NULL) {
free(emac);
return -1;
}
/* alignment as per Errata (64 bytes) is insufficient! */
emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
memset(emacfix, 0, sizeof(emac_device));
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "emac");
dev->iobase = iobase;
dev->priv = emacfix;
dev->init = at91emac_init;
dev->halt = at91emac_halt;
dev->send = at91emac_send;
dev->recv = at91emac_recv;
dev->write_hwaddr = at91emac_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
#endif
return 1;
}
|
1001-study-uboot
|
drivers/net/at91_emac.c
|
C
|
gpl3
| 13,608
|
/*
* Faraday FTGMAC100 Ethernet
*
* (C) Copyright 2010 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* (C) Copyright 2010 Andes Technology
* Macpaul Lin <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __FTGMAC100_H
#define __FTGMAC100_H
/* The registers offset table of ftgmac100 */
struct ftgmac100 {
unsigned int isr; /* 0x00 */
unsigned int ier; /* 0x04 */
unsigned int mac_madr; /* 0x08 */
unsigned int mac_ladr; /* 0x0c */
unsigned int maht0; /* 0x10 */
unsigned int maht1; /* 0x14 */
unsigned int txpd; /* 0x18 */
unsigned int rxpd; /* 0x1c */
unsigned int txr_badr; /* 0x20 */
unsigned int rxr_badr; /* 0x24 */
unsigned int hptxpd; /* 0x28 */
unsigned int hptxpd_badr; /* 0x2c */
unsigned int itc; /* 0x30 */
unsigned int aptc; /* 0x34 */
unsigned int dblac; /* 0x38 */
unsigned int dmafifos; /* 0x3c */
unsigned int revr; /* 0x40 */
unsigned int fear; /* 0x44 */
unsigned int tpafcr; /* 0x48 */
unsigned int rbsr; /* 0x4c */
unsigned int maccr; /* 0x50 */
unsigned int macsr; /* 0x54 */
unsigned int tm; /* 0x58 */
unsigned int resv1; /* 0x5c */ /* not defined in spec */
unsigned int phycr; /* 0x60 */
unsigned int phydata; /* 0x64 */
unsigned int fcr; /* 0x68 */
unsigned int bpr; /* 0x6c */
unsigned int wolcr; /* 0x70 */
unsigned int wolsr; /* 0x74 */
unsigned int wfcrc; /* 0x78 */
unsigned int resv2; /* 0x7c */ /* not defined in spec */
unsigned int wfbm1; /* 0x80 */
unsigned int wfbm2; /* 0x84 */
unsigned int wfbm3; /* 0x88 */
unsigned int wfbm4; /* 0x8c */
unsigned int nptxr_ptr; /* 0x90 */
unsigned int hptxr_ptr; /* 0x94 */
unsigned int rxr_ptr; /* 0x98 */
unsigned int resv3; /* 0x9c */ /* not defined in spec */
unsigned int tx; /* 0xa0 */
unsigned int tx_mcol_scol; /* 0xa4 */
unsigned int tx_ecol_fail; /* 0xa8 */
unsigned int tx_lcol_und; /* 0xac */
unsigned int rx; /* 0xb0 */
unsigned int rx_bc; /* 0xb4 */
unsigned int rx_mc; /* 0xb8 */
unsigned int rx_pf_aep; /* 0xbc */
unsigned int rx_runt; /* 0xc0 */
unsigned int rx_crcer_ftl; /* 0xc4 */
unsigned int rx_col_lost; /* 0xc8 */
};
/*
* Interrupt status register & interrupt enable register
*/
#define FTGMAC100_INT_RPKT_BUF (1 << 0)
#define FTGMAC100_INT_RPKT_FIFO (1 << 1)
#define FTGMAC100_INT_NO_RXBUF (1 << 2)
#define FTGMAC100_INT_RPKT_LOST (1 << 3)
#define FTGMAC100_INT_XPKT_ETH (1 << 4)
#define FTGMAC100_INT_XPKT_FIFO (1 << 5)
#define FTGMAC100_INT_NO_NPTXBUF (1 << 6)
#define FTGMAC100_INT_XPKT_LOST (1 << 7)
#define FTGMAC100_INT_AHB_ERR (1 << 8)
#define FTGMAC100_INT_PHYSTS_CHG (1 << 9)
#define FTGMAC100_INT_NO_HPTXBUF (1 << 10)
/*
* Interrupt timer control register
*/
#define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
#define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
#define FTGMAC100_ITC_RXINT_TIME_SEL (1 << 7)
#define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
#define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
#define FTGMAC100_ITC_TXINT_TIME_SEL (1 << 15)
/*
* Automatic polling timer control register
*/
#define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
#define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
/*
* DMA burst length and arbitration control register
*/
#define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
#define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
#define FTGMAC100_DBLAC_RX_THR_EN (1 << 6)
#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8)
#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10)
#define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12)
#define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16)
#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
/*
* DMA FIFO status register
*/
#define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf)
#define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf)
#define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7)
#define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
#define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
#define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY (1 << 26)
#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY (1 << 27)
#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
#define FTGMAC100_DMAFIFOS_RXDMA_REQ (1 << 30)
#define FTGMAC100_DMAFIFOS_TXDMA_REQ (1 << 31)
/*
* Receive buffer size register
*/
#define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff)
/*
* MAC control register
*/
#define FTGMAC100_MACCR_TXDMA_EN (1 << 0)
#define FTGMAC100_MACCR_RXDMA_EN (1 << 1)
#define FTGMAC100_MACCR_TXMAC_EN (1 << 2)
#define FTGMAC100_MACCR_RXMAC_EN (1 << 3)
#define FTGMAC100_MACCR_RM_VLAN (1 << 4)
#define FTGMAC100_MACCR_HPTXR_EN (1 << 5)
#define FTGMAC100_MACCR_LOOP_EN (1 << 6)
#define FTGMAC100_MACCR_ENRX_IN_HALFTX (1 << 7)
#define FTGMAC100_MACCR_FULLDUP (1 << 8)
#define FTGMAC100_MACCR_GIGA_MODE (1 << 9)
#define FTGMAC100_MACCR_CRC_APD (1 << 10)
#define FTGMAC100_MACCR_RX_RUNT (1 << 12)
#define FTGMAC100_MACCR_JUMBO_LF (1 << 13)
#define FTGMAC100_MACCR_RX_ALL (1 << 14)
#define FTGMAC100_MACCR_HT_MULTI_EN (1 << 15)
#define FTGMAC100_MACCR_RX_MULTIPKT (1 << 16)
#define FTGMAC100_MACCR_RX_BROADPKT (1 << 17)
#define FTGMAC100_MACCR_DISCARD_CRCERR (1 << 18)
#define FTGMAC100_MACCR_FAST_MODE (1 << 19)
#define FTGMAC100_MACCR_SW_RST (1 << 31)
/*
* PHY control register
*/
#define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f
#define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f)
#define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16)
#define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21)
#define FTGMAC100_PHYCR_MIIRD (1 << 26)
#define FTGMAC100_PHYCR_MIIWR (1 << 27)
/*
* PHY data register
*/
#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
#define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff)
/*
* Transmit descriptor, aligned to 16 bytes
*/
struct ftgmac100_txdes {
unsigned int txdes0;
unsigned int txdes1;
unsigned int txdes2; /* not used by HW */
unsigned int txdes3; /* TXBUF_BADR */
} __attribute__ ((aligned(16)));
#define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
#define FTGMAC100_TXDES0_EDOTR (1 << 15)
#define FTGMAC100_TXDES0_CRC_ERR (1 << 19)
#define FTGMAC100_TXDES0_LTS (1 << 28)
#define FTGMAC100_TXDES0_FTS (1 << 29)
#define FTGMAC100_TXDES0_TXDMA_OWN (1 << 31)
#define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff)
#define FTGMAC100_TXDES1_INS_VLANTAG (1 << 16)
#define FTGMAC100_TXDES1_TCP_CHKSUM (1 << 17)
#define FTGMAC100_TXDES1_UDP_CHKSUM (1 << 18)
#define FTGMAC100_TXDES1_IP_CHKSUM (1 << 19)
#define FTGMAC100_TXDES1_LLC (1 << 22)
#define FTGMAC100_TXDES1_TX2FIC (1 << 30)
#define FTGMAC100_TXDES1_TXIC (1 << 31)
/*
* Receive descriptor, aligned to 16 bytes
*/
struct ftgmac100_rxdes {
unsigned int rxdes0;
unsigned int rxdes1;
unsigned int rxdes2; /* not used by HW */
unsigned int rxdes3; /* RXBUF_BADR */
} __attribute__ ((aligned(16)));
#define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff)
#define FTGMAC100_RXDES0_EDORR (1 << 15)
#define FTGMAC100_RXDES0_MULTICAST (1 << 16)
#define FTGMAC100_RXDES0_BROADCAST (1 << 17)
#define FTGMAC100_RXDES0_RX_ERR (1 << 18)
#define FTGMAC100_RXDES0_CRC_ERR (1 << 19)
#define FTGMAC100_RXDES0_FTL (1 << 20)
#define FTGMAC100_RXDES0_RUNT (1 << 21)
#define FTGMAC100_RXDES0_RX_ODD_NB (1 << 22)
#define FTGMAC100_RXDES0_FIFO_FULL (1 << 23)
#define FTGMAC100_RXDES0_PAUSE_OPCODE (1 << 24)
#define FTGMAC100_RXDES0_PAUSE_FRAME (1 << 25)
#define FTGMAC100_RXDES0_LRS (1 << 28)
#define FTGMAC100_RXDES0_FRS (1 << 29)
#define FTGMAC100_RXDES0_RXPKT_RDY (1 << 31)
#define FTGMAC100_RXDES1_VLANTAG_CI 0xffff
#define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20)
#define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20)
#define FTGMAC100_RXDES1_PROT_IP (0x1 << 20)
#define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20)
#define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20)
#define FTGMAC100_RXDES1_LLC (1 << 22)
#define FTGMAC100_RXDES1_DF (1 << 23)
#define FTGMAC100_RXDES1_VLANTAG_AVAIL (1 << 24)
#define FTGMAC100_RXDES1_TCP_CHKSUM_ERR (1 << 25)
#define FTGMAC100_RXDES1_UDP_CHKSUM_ERR (1 << 26)
#define FTGMAC100_RXDES1_IP_CHKSUM_ERR (1 << 27)
#endif /* __FTGMAC100_H */
|
1001-study-uboot
|
drivers/net/ftgmac100.h
|
C
|
gpl3
| 9,077
|
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include "fm.h"
struct fm_eth_info fm_info[] = {
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(1, 1),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 2)
FM_DTSEC_INFO_INITIALIZER(1, 2),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 3)
FM_DTSEC_INFO_INITIALIZER(1, 3),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(1, 4),
#endif
#if (CONFIG_SYS_NUM_FM1_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(1, 5),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(2, 1),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 2)
FM_DTSEC_INFO_INITIALIZER(2, 2),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 3)
FM_DTSEC_INFO_INITIALIZER(2, 3),
#endif
#if (CONFIG_SYS_NUM_FM2_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(2, 4),
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
#if (CONFIG_SYS_NUM_FM2_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(2, 1),
#endif
};
int fm_standard_init(bd_t *bis)
{
int i;
struct ccsr_fman *reg;
reg = (void *)CONFIG_SYS_FSL_FM1_ADDR;
if (fm_init_common(0, reg))
return 0;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if ((fm_info[i].enabled) && (fm_info[i].index == 1))
fm_eth_initialize(reg, &fm_info[i]);
}
#if (CONFIG_SYS_NUM_FMAN == 2)
reg = (void *)CONFIG_SYS_FSL_FM2_ADDR;
if (fm_init_common(1, reg))
return 0;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if ((fm_info[i].enabled) && (fm_info[i].index == 2))
fm_eth_initialize(reg, &fm_info[i]);
}
#endif
return 1;
}
/* simple linear search to map from port to array index */
static int fm_port_to_index(enum fm_port port)
{
int i;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if (fm_info[i].port == port)
return i;
}
return -1;
}
/*
* Determine if an interface is actually active based on HW config
* we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NONE if
* the interface is not active based on HW cfg of the SoC
*/
void fman_enet_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
phy_interface_t enet_if;
enet_if = fman_port_enet_if(fm_info[i].port);
if (enet_if != PHY_INTERFACE_MODE_NONE) {
fm_info[i].enabled = 1;
fm_info[i].enet_if = enet_if;
} else {
fm_info[i].enabled = 0;
}
}
return ;
}
void fm_disable_port(enum fm_port port)
{
int i = fm_port_to_index(port);
fm_info[i].enabled = 0;
fman_disable_port(port);
}
void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].bus = bus;
}
void fm_info_set_phy_address(enum fm_port port, int address)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].phy_addr = address;
}
/*
* Returns the type of the data interface between the given MAC and its PHY.
* This is typically determined by the RCW.
*/
phy_interface_t fm_info_get_enet_if(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return PHY_INTERFACE_MODE_NONE;
if (fm_info[i].enabled)
return fm_info[i].enet_if;
return PHY_INTERFACE_MODE_NONE;
}
static void
__def_board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
{
return ;
}
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
__attribute__((weak, alias("__def_board_ft_fman_fixup_port")));
static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
{
int off, ph;
phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset;
u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS +
CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET;
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
if (info->enabled) {
fdt_fixup_phy_connection(blob, off, info->enet_if);
board_ft_fman_fixup_port(blob, prop, paddr, info->port, off);
return ;
}
/* board code might have caused offset to change */
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
if (paddr != dtsec1_addr) {
/* disable the mac node */
fdt_setprop_string(blob, off, "status", "disabled");
}
/* disable the node point to the mac */
ph = fdt_get_phandle(blob, off);
do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
"status", "disabled", strlen("disabled") + 1, 1);
}
void fdt_fixup_fman_ethernet(void *blob)
{
int i;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if (fm_info[i].type == FM_ETH_1G_E)
ft_fixup_port(blob, &fm_info[i], "fsl,fman-1g-mac");
else
ft_fixup_port(blob, &fm_info[i], "fsl,fman-10g-mac");
}
}
|
1001-study-uboot
|
drivers/net/fm/init.c
|
C
|
gpl3
| 5,355
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/errno.h>
#include "fm.h"
#include "../../qe/qe.h" /* For struct qe_firmware */
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
#include <spi_flash.h>
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
#include <mmc.h>
#endif
struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
u32 fm_muram_base(int fm_idx)
{
return muram[fm_idx].base;
}
u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
{
u32 ret;
u32 align_mask, off;
u32 save;
align_mask = align - 1;
save = muram[fm_idx].alloc;
off = save & align_mask;
if (off != 0)
muram[fm_idx].alloc += (align - off);
off = size & align_mask;
if (off != 0)
size += (align - off);
if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
muram[fm_idx].alloc = save;
printf("%s: run out of ram.\n", __func__);
}
ret = muram[fm_idx].alloc;
muram[fm_idx].alloc += size;
memset((void *)ret, 0, size);
return ret;
}
static void fm_init_muram(int fm_idx, void *reg)
{
u32 base = (u32)reg;
muram[fm_idx].base = base;
muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
}
/*
* fm_upload_ucode - Fman microcode upload worker function
*
* This function does the actual uploading of an Fman microcode
* to an Fman.
*/
static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
u32 *ucode, unsigned int size)
{
unsigned int i;
unsigned int timeout = 1000000;
/* enable address auto increase */
out_be32(&imem->iadd, IRAM_IADD_AIE);
/* write microcode to IRAM */
for (i = 0; i < size / 4; i++)
out_be32(&imem->idata, ucode[i]);
/* verify if the writing is over */
out_be32(&imem->iadd, 0);
while ((in_be32(&imem->idata) != ucode[0]) && --timeout)
;
if (!timeout)
printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
/* enable microcode from IRAM */
out_be32(&imem->iready, IRAM_READY);
}
/*
* Upload an Fman firmware
*
* This function is similar to qe_upload_firmware(), exception that it uploads
* a microcode to the Fman instead of the QE.
*
* Because the process for uploading a microcode to the Fman is similar for
* that of the QE, the QE firmware binary format is used for Fman microcode.
* It should be possible to unify these two functions, but for now we keep them
* separate.
*/
static int fman_upload_firmware(int fm_idx,
struct fm_imem *fm_imem,
const struct qe_firmware *firmware)
{
unsigned int i;
u32 crc;
size_t calc_size = sizeof(struct qe_firmware);
size_t length;
const struct qe_header *hdr;
if (!firmware) {
printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
return -EINVAL;
}
hdr = &firmware->header;
length = be32_to_cpu(hdr->length);
/* Check the magic */
if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
(hdr->magic[2] != 'F')) {
printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
firmware);
return -EPERM;
}
/* Check the version */
if (hdr->version != 1) {
printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
hdr->version);
return -EPERM;
}
/* Validate some of the fields */
if ((firmware->count != 1)) {
printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
return -EINVAL;
}
/* Validate the length and check if there's a CRC */
calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
for (i = 0; i < firmware->count; i++)
/*
* For situations where the second RISC uses the same microcode
* as the first, the 'code_offset' and 'count' fields will be
* zero, so it's okay to add those.
*/
calc_size += sizeof(u32) *
be32_to_cpu(firmware->microcode[i].count);
/* Validate the length */
if (length != calc_size + sizeof(u32)) {
printf("Fman%u: Invalid length in firmware header\n",
fm_idx + 1);
return -EPERM;
}
/*
* Validate the CRC. We would normally call crc32_no_comp(), but that
* function isn't available unless you turn on JFFS support.
*/
crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
return -EIO;
}
/* Loop through each microcode. */
for (i = 0; i < firmware->count; i++) {
const struct qe_microcode *ucode = &firmware->microcode[i];
/* Upload a microcode if it's present */
if (ucode->code_offset) {
u32 ucode_size;
u32 *code;
printf("Fman%u: Uploading microcode version %u.%u.%u\n",
fm_idx + 1, ucode->major, ucode->minor,
ucode->revision);
code = (void *)firmware + ucode->code_offset;
ucode_size = sizeof(u32) * ucode->count;
fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
}
}
return 0;
}
static u32 fm_assign_risc(int port_id)
{
u32 risc_sel, val;
risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
return val;
}
static void fm_init_fpm(struct fm_fpm *fpm)
{
int i, port_id;
u32 val;
setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
FMFPEE_CER | FMFPEE_DER);
/* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
/* offline/parser port */
for (i = 0; i < MAX_NUM_OH_PORT; i++) {
port_id = OH_PORT_ID_BASE + i;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
}
/* Rx 1G port */
for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
port_id = RX_PORT_1G_BASE + i;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
}
/* Tx 1G port */
for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
port_id = TX_PORT_1G_BASE + i;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
}
/* Rx 10G port */
port_id = RX_PORT_10G_BASE;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
/* Tx 10G port */
port_id = TX_PORT_10G_BASE;
val = fm_assign_risc(port_id);
out_be32(&fpm->fpmprc, val);
/* disable the dispatch limit in IM case */
out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
/* clear events */
out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
/* clear risc events */
for (i = 0; i < 4; i++)
out_be32(&fpm->fpmcev[i], 0xffffffff);
/* clear error */
out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
}
static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
{
int blk, i, port_id;
u32 val, offset, base;
/* alloc free buffer pool in MURAM */
base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
if (!base) {
printf("%s: no muram for free buffer pool\n", __func__);
return -ENOMEM;
}
offset = base - fm_muram_base(fm_idx);
/* Need 128KB total free buffer pool size */
val = offset / 256;
blk = FM_FREE_POOL_SIZE / 256;
/* in IM, we must not begin from offset 0 in MURAM */
val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
out_be32(&bmi->fmbm_cfg1, val);
/* disable all BMI interrupt */
out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
/* clear all events */
out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
/*
* set port parameters - FMBM_PP_x
* max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
* max dma 10G Rx/Tx=3, others is 1
* set port FIFO size - FMBM_PFS_x
* 4KB for all Rx and Tx ports
*/
/* offline/parser port */
for (i = 0; i < MAX_NUM_OH_PORT; i++) {
port_id = OH_PORT_ID_BASE + i - 1;
/* max tasks=1, max dma=1, no extra */
out_be32(&bmi->fmbm_pp[port_id], 0);
/* port FIFO size - 256 bytes, no extra */
out_be32(&bmi->fmbm_pfs[port_id], 0);
}
/* Rx 1G port */
for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
port_id = RX_PORT_1G_BASE + i - 1;
/* max tasks=4, max dma=1, no extra */
out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
/* FIFO size - 4KB, no extra */
out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
}
/* Tx 1G port FIFO size - 4KB, no extra */
for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
port_id = TX_PORT_1G_BASE + i - 1;
/* max tasks=4, max dma=1, no extra */
out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
/* FIFO size - 4KB, no extra */
out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
}
/* Rx 10G port */
port_id = RX_PORT_10G_BASE - 1;
/* max tasks=12, max dma=3, no extra */
out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
/* FIFO size - 4KB, no extra */
out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
/* Tx 10G port */
port_id = TX_PORT_10G_BASE - 1;
/* max tasks=12, max dma=3, no extra */
out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
/* FIFO size - 4KB, no extra */
out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
/* initialize internal buffers data base (linked list) */
out_be32(&bmi->fmbm_init, FMBM_INIT_START);
return 0;
}
static void fm_init_qmi(struct fm_qmi_common *qmi)
{
/* disable enqueue and dequeue of QMI */
clrbits_be32(&qmi->fmqm_gc, FMQM_GC_ENQ_EN | FMQM_GC_DEQ_EN);
/* disable all error interrupts */
out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
/* clear all error events */
out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
/* disable all interrupts */
out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
/* clear all interrupts */
out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
}
/* Init common part of FM, index is fm num# like fm as above */
int fm_init_common(int index, struct ccsr_fman *reg)
{
int rc;
char env_addr[32];
#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_ADDR,
&fw_length, (u_char *)addr);
if (rc == -EUCLEAN) {
printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
CONFIG_SYS_QE_FMAN_FW_ADDR, rc);
}
#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
struct spi_flash *ucode_flash;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
int ret = 0;
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!ucode_flash)
printf("SF: probe for ucode failed\n");
else {
ret = spi_flash_read(ucode_flash, CONFIG_SYS_QE_FMAN_FW_ADDR,
CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
if (ret)
printf("SF: read for ucode failed\n");
spi_flash_free(ucode_flash);
}
#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
int dev = CONFIG_SYS_MMC_ENV_DEV;
void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
u32 blk = CONFIG_SYS_QE_FMAN_FW_ADDR / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc)
printf("\nMMC cannot find device for ucode\n");
else {
printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
(void)mmc->block_dev.block_read(dev, blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
#endif
/* Upload the Fman microcode if it's present */
rc = fman_upload_firmware(index, ®->fm_imem, addr);
if (rc)
return rc;
sprintf(env_addr, "0x%lx", (long unsigned int)addr);
setenv("fman_ucode", env_addr);
fm_init_muram(index, ®->muram);
fm_init_qmi(®->fm_qmi_common);
fm_init_fpm(®->fm_fpm);
/* clear DMA status */
setbits_be32(®->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
/* set DMA mode */
setbits_be32(®->fm_dma.fmdmmr, FMDMMR_SBER);
return fm_init_bmi(index, ®->fm_bmi_common);
}
|
1001-study-uboot
|
drivers/net/fm/fm.c
|
C
|
gpl3
| 12,350
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/types.h>
#include <asm/io.h>
#include <asm/fsl_enet.h>
#include <asm/fsl_dtsec.h>
#include <fsl_mdio.h>
#include <phy.h>
#include "fm.h"
#define RCTRL_INIT (RCTRL_GRS | RCTRL_UPROM)
#define TCTRL_INIT TCTRL_GTS
#define MACCFG1_INIT MACCFG1_SOFT_RST
#define MACCFG2_INIT (MACCFG2_PRE_LEN(0x7) | MACCFG2_LEN_CHECK | \
MACCFG2_PAD_CRC | MACCFG2_FULL_DUPLEX | \
MACCFG2_IF_MODE_NIBBLE)
/* MAXFRM - maximum frame length register */
#define MAXFRM_MASK 0x00003fff
static void dtsec_init_mac(struct fsl_enet_mac *mac)
{
struct dtsec *regs = mac->base;
/* soft reset */
out_be32(®s->maccfg1, MACCFG1_SOFT_RST);
udelay(1000);
/* clear soft reset, Rx/Tx MAC disable */
out_be32(®s->maccfg1, 0);
/* graceful stop rx */
out_be32(®s->rctrl, RCTRL_INIT);
udelay(1000);
/* graceful stop tx */
out_be32(®s->tctrl, TCTRL_INIT);
udelay(1000);
/* disable all interrupts */
out_be32(®s->imask, IMASK_MASK_ALL);
/* clear all events */
out_be32(®s->ievent, IEVENT_CLEAR_ALL);
/* set the max Rx length */
out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK);
/* set the ecntrl to reset value */
out_be32(®s->ecntrl, ECNTRL_DEFAULT);
/*
* Rx length check, no strip CRC for Rx, pad and append CRC for Tx,
* full duplex
*/
out_be32(®s->maccfg2, MACCFG2_INIT);
}
static void dtsec_enable_mac(struct fsl_enet_mac *mac)
{
struct dtsec *regs = mac->base;
/* enable Rx/Tx MAC */
setbits_be32(®s->maccfg1, MACCFG1_RXTX_EN);
/* clear the graceful Rx stop */
clrbits_be32(®s->rctrl, RCTRL_GRS);
/* clear the graceful Tx stop */
clrbits_be32(®s->tctrl, TCTRL_GTS);
}
static void dtsec_disable_mac(struct fsl_enet_mac *mac)
{
struct dtsec *regs = mac->base;
/* graceful Rx stop */
setbits_be32(®s->rctrl, RCTRL_GRS);
/* graceful Tx stop */
setbits_be32(®s->tctrl, TCTRL_GTS);
/* disable Rx/Tx MAC */
clrbits_be32(®s->maccfg1, MACCFG1_RXTX_EN);
}
static void dtsec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
{
struct dtsec *regs = mac->base;
u32 mac_addr1, mac_addr2;
/*
* if a station address of 0x12345678ABCD, perform a write to
* MACSTNADDR1 of 0xCDAB7856, MACSTNADDR2 of 0x34120000
*/
mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
(mac_addr[3] << 8) | (mac_addr[2]);
out_be32(®s->macstnaddr1, mac_addr1);
mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
out_be32(®s->macstnaddr2, mac_addr2);
}
static void dtsec_set_interface_mode(struct fsl_enet_mac *mac,
phy_interface_t type, int speed)
{
struct dtsec *regs = mac->base;
u32 ecntrl, maccfg2;
/* clear all bits relative with interface mode */
ecntrl = in_be32(®s->ecntrl);
ecntrl &= ~(ECNTRL_TBIM | ECNTRL_GMIIM | ECNTRL_RPM |
ECNTRL_R100M | ECNTRL_SGMIIM);
maccfg2 = in_be32(®s->maccfg2);
maccfg2 &= ~MACCFG2_IF_MODE_MASK;
if (speed == SPEED_1000)
maccfg2 |= MACCFG2_IF_MODE_BYTE;
else
maccfg2 |= MACCFG2_IF_MODE_NIBBLE;
/* set interface mode */
switch (type) {
case PHY_INTERFACE_MODE_GMII:
ecntrl |= ECNTRL_GMIIM;
break;
case PHY_INTERFACE_MODE_RGMII:
ecntrl |= (ECNTRL_GMIIM | ECNTRL_RPM);
if (speed == SPEED_100)
ecntrl |= ECNTRL_R100M;
break;
case PHY_INTERFACE_MODE_RMII:
if (speed == SPEED_100)
ecntrl |= ECNTRL_R100M;
break;
case PHY_INTERFACE_MODE_SGMII:
ecntrl |= (ECNTRL_SGMIIM | ECNTRL_TBIM);
if (speed == SPEED_100)
ecntrl |= ECNTRL_R100M;
break;
default:
break;
}
out_be32(®s->ecntrl, ecntrl);
out_be32(®s->maccfg2, maccfg2);
}
void init_dtsec(struct fsl_enet_mac *mac, void *base,
void *phyregs, int max_rx_len)
{
mac->base = base;
mac->phyregs = phyregs;
mac->max_rx_len = max_rx_len;
mac->init_mac = dtsec_init_mac;
mac->enable_mac = dtsec_enable_mac;
mac->disable_mac = dtsec_disable_mac;
mac->set_mac_addr = dtsec_set_mac_addr;
mac->set_if_mode = dtsec_set_interface_mode;
}
|
1001-study-uboot
|
drivers/net/fm/dtsec.c
|
C
|
gpl3
| 4,704
|
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1,
[FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr = in_be32(&gur->devdisr);
return port_to_devdisr[port] & devdisr;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 pordevsr = in_be32(&gur->pordevsr);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
/* DTSEC1 can be SGMII, RGMII or RMII */
if (port == FM1_DTSEC1) {
if (is_serdes_configured(SGMII_FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) {
if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC)
return PHY_INTERFACE_MODE_RGMII;
else
return PHY_INTERFACE_MODE_RMII;
}
}
/* DTSEC2 only supports SGMII or RGMII */
if (port == FM1_DTSEC2) {
if (is_serdes_configured(SGMII_FM1_DTSEC2))
return PHY_INTERFACE_MODE_SGMII;
if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)
return PHY_INTERFACE_MODE_RGMII;
}
return PHY_INTERFACE_MODE_NONE;
}
|
1001-study-uboot
|
drivers/net/fm/p1023.c
|
C
|
gpl3
| 2,296
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* MAXFRM - maximum frame length */
#define MAXFRM_MASK 0x0000ffff
#include <common.h>
#include <phy.h>
#include <asm/types.h>
#include <asm/io.h>
#include <asm/fsl_enet.h>
#include <asm/fsl_tgec.h>
#include "fm.h"
#define TGEC_CMD_CFG_INIT (TGEC_CMD_CFG_NO_LEN_CHK | \
TGEC_CMD_CFG_RX_ER_DISC | \
TGEC_CMD_CFG_STAT_CLR | \
TGEC_CMD_CFG_PAUSE_IGNORE | \
TGEC_CMD_CFG_CRC_FWD)
#define TGEC_CMD_CFG_FINAL (TGEC_CMD_CFG_NO_LEN_CHK | \
TGEC_CMD_CFG_RX_ER_DISC | \
TGEC_CMD_CFG_PAUSE_IGNORE | \
TGEC_CMD_CFG_CRC_FWD)
static void tgec_init_mac(struct fsl_enet_mac *mac)
{
struct tgec *regs = mac->base;
/* mask all interrupt */
out_be32(®s->imask, IMASK_MASK_ALL);
/* clear all events */
out_be32(®s->ievent, IEVENT_CLEAR_ALL);
/* set the max receive length */
out_be32(®s->maxfrm, mac->max_rx_len & MAXFRM_MASK);
/*
* 1588 disable, insert second mac disable payload length check
* disable, normal operation, any rx error frame is discarded, clear
* counters, pause frame ignore, no promiscuous, LAN mode Rx CRC no
* strip, Tx CRC append, Rx disable and Tx disable
*/
out_be32(®s->command_config, TGEC_CMD_CFG_INIT);
udelay(1000);
out_be32(®s->command_config, TGEC_CMD_CFG_FINAL);
/* multicast frame reception for the hash entry disable */
out_be32(®s->hashtable_ctrl, 0);
}
static void tgec_enable_mac(struct fsl_enet_mac *mac)
{
struct tgec *regs = mac->base;
setbits_be32(®s->command_config, TGEC_CMD_CFG_RXTX_EN);
}
static void tgec_disable_mac(struct fsl_enet_mac *mac)
{
struct tgec *regs = mac->base;
clrbits_be32(®s->command_config, TGEC_CMD_CFG_RXTX_EN);
}
static void tgec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
{
struct tgec *regs = mac->base;
u32 mac_addr0, mac_addr1;
/*
* if a station address of 0x12345678ABCD, perform a write to
* MAC_ADDR0 of 0x78563412, MAC_ADDR1 of 0x0000CDAB
*/
mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \
(mac_addr[1] << 8) | (mac_addr[0]);
out_be32(®s->mac_addr_0, mac_addr0);
mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x0000ffff;
out_be32(®s->mac_addr_1, mac_addr1);
}
static void tgec_set_interface_mode(struct fsl_enet_mac *mac,
phy_interface_t type, int speed)
{
/* nothing right now */
return;
}
void init_tgec(struct fsl_enet_mac *mac, void *base,
void *phyregs, int max_rx_len)
{
mac->base = base;
mac->phyregs = phyregs;
mac->max_rx_len = max_rx_len;
mac->init_mac = tgec_init_mac;
mac->enable_mac = tgec_enable_mac;
mac->disable_mac = tgec_disable_mac;
mac->set_mac_addr = tgec_set_mac_addr;
mac->set_if_mode = tgec_set_interface_mode;
}
|
1001-study-uboot
|
drivers/net/fm/tgec.c
|
C
|
gpl3
| 3,473
|
#
# Copyright 2009-2011 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libfm.o
ifdef CONFIG_FMAN_ENET
COBJS-y += dtsec.o
COBJS-y += eth.o
COBJS-y += fm.o
COBJS-y += init.o
COBJS-y += tgec.o
COBJS-y += tgec_phy.o
# SoC specific SERDES support
COBJS-$(CONFIG_P1017) += p1023.o
COBJS-$(CONFIG_P1023) += p1023.o
# The P204x, P304x, and P5020 are the same
COBJS-$(CONFIG_PPC_P2040) += p5020.o
COBJS-$(CONFIG_PPC_P2041) += p5020.o
COBJS-$(CONFIG_PPC_P3041) += p5020.o
COBJS-$(CONFIG_PPC_P3060) += p3060.o
COBJS-$(CONFIG_PPC_P4080) += p4080.o
COBJS-$(CONFIG_PPC_P5020) += p5020.o
endif
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/net/fm/Makefile
|
Makefile
|
gpl3
| 1,749
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <net.h>
#include <hwconfig.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_tgec.h>
#include "fm.h"
static struct eth_device *devlist[NUM_FM_PORTS];
static int num_controllers;
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
TBIANA_FULL_DUPLEX)
#define TBIANA_SGMII_ACK 0x4001
#define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
/* Configure the TBI for SGMII operation */
void dtsec_configure_serdes(struct fm_eth *priv)
{
struct dtsec *regs = priv->mac->base;
struct tsec_mii_mng *phyregs = priv->mac->phyregs;
/*
* Access TBI PHY registers at given TSEC register offset as
* opposed to the register offset used for external PHY accesses
*/
tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_TBICON,
TBICON_CLK_SELECT);
tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0, TBI_ANA,
TBIANA_SGMII_ACK);
tsec_local_mdio_write(phyregs, in_be32(®s->tbipa), 0,
TBI_CR, TBICR_SETTINGS);
}
static void dtsec_init_phy(struct eth_device *dev)
{
struct fm_eth *fm_eth = dev->priv;
struct dtsec *regs = (struct dtsec *)fm_eth->mac->base;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
dtsec_configure_serdes(fm_eth);
}
static int tgec_is_fibre(struct eth_device *dev)
{
struct fm_eth *fm = dev->priv;
char phyopt[20];
sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
return hwconfig_arg_cmp(phyopt, "xfi");
}
#endif
static u16 muram_readw(u16 *addr)
{
u32 base = (u32)addr & ~0x3;
u32 val32 = *(u32 *)base;
int byte_pos;
u16 ret;
byte_pos = (u32)addr & 0x3;
if (byte_pos)
ret = (u16)(val32 & 0x0000ffff);
else
ret = (u16)((val32 & 0xffff0000) >> 16);
return ret;
}
static void muram_writew(u16 *addr, u16 val)
{
u32 base = (u32)addr & ~0x3;
u32 org32 = *(u32 *)base;
u32 val32;
int byte_pos;
byte_pos = (u32)addr & 0x3;
if (byte_pos)
val32 = (org32 & 0xffff0000) | val;
else
val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
*(u32 *)base = val32;
}
static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
{
int timeout = 1000000;
clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
/* wait until the rx port is not busy */
while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
;
}
static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
{
/* set BMI to independent mode, Rx port disable */
out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
/* clear FOF in IM case */
out_be32(&rx_port->fmbm_rim, 0);
/* Rx frame next engine -RISC */
out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
/* Rx command attribute - no order, MR[3] = 1 */
clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
/* enable Rx statistic counters */
out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
/* disable Rx performance counters */
out_be32(&rx_port->fmbm_rpc, 0);
}
static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
{
int timeout = 1000000;
clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
/* wait until the tx port is not busy */
while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
;
}
static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
{
/* set BMI to independent mode, Tx port disable */
out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
/* Tx frame next engine -RISC */
out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
/* Tx command attribute - no order, MR[3] = 1 */
clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
/* enable Tx statistic counters */
out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
/* disable Tx performance counters */
out_be32(&tx_port->fmbm_tpc, 0);
}
static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
{
struct fm_port_global_pram *pram;
u32 pram_page_offset;
void *rx_bd_ring_base;
void *rx_buf_pool;
struct fm_port_bd *rxbd;
struct fm_port_qd *rxqd;
struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
int i;
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
fm_eth->rx_pram = pram;
/* parameter page offset to MURAM */
pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
pram->mode = PRAM_MODE_GLOBAL;
/* init the Rx queue descriptor pionter */
pram->rxqd_ptr = pram_page_offset + 0x20;
/* set the max receive buffer length, power of 2 */
muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
/* alloc Rx buffer descriptors from main memory */
rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
if (!rx_bd_ring_base)
return 0;
memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
/* alloc Rx buffer from main memory */
rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
if (!rx_buf_pool)
return 0;
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
/* save them to fm_eth */
fm_eth->rx_bd_ring = rx_bd_ring_base;
fm_eth->cur_rxbd = rx_bd_ring_base;
fm_eth->rx_buf = rx_buf_pool;
/* init Rx BDs ring */
rxbd = (struct fm_port_bd *)rx_bd_ring_base;
for (i = 0; i < RX_BD_RING_SIZE; i++) {
rxbd->status = RxBD_EMPTY;
rxbd->len = 0;
rxbd->buf_ptr_hi = 0;
rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
rxbd++;
}
/* set the Rx queue descriptor */
rxqd = &pram->rxqd;
muram_writew(&rxqd->gen, 0);
muram_writew(&rxqd->bd_ring_base_hi, 0);
rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(&rxqd->offset_in, 0);
muram_writew(&rxqd->offset_out, 0);
/* set IM parameter ram pointer to Rx Frame Queue ID */
out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
return 1;
}
static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
{
struct fm_port_global_pram *pram;
u32 pram_page_offset;
void *tx_bd_ring_base;
struct fm_port_bd *txbd;
struct fm_port_qd *txqd;
struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
int i;
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
fm_eth->tx_pram = pram;
/* parameter page offset to MURAM */
pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
pram->mode = PRAM_MODE_GLOBAL;
/* init the Tx queue descriptor pionter */
pram->txqd_ptr = pram_page_offset + 0x40;
/* alloc Tx buffer descriptors from main memory */
tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
if (!tx_bd_ring_base)
return 0;
memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
/* save it to fm_eth */
fm_eth->tx_bd_ring = tx_bd_ring_base;
fm_eth->cur_txbd = tx_bd_ring_base;
/* init Tx BDs ring */
txbd = (struct fm_port_bd *)tx_bd_ring_base;
for (i = 0; i < TX_BD_RING_SIZE; i++) {
txbd->status = TxBD_LAST;
txbd->len = 0;
txbd->buf_ptr_hi = 0;
txbd->buf_ptr_lo = 0;
}
/* set the Tx queue decriptor */
txqd = &pram->txqd;
muram_writew(&txqd->bd_ring_base_hi, 0);
txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
muram_writew(&txqd->offset_in, 0);
muram_writew(&txqd->offset_out, 0);
/* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
return 1;
}
static int fm_eth_init(struct fm_eth *fm_eth)
{
if (!fm_eth_rx_port_parameter_init(fm_eth))
return 0;
if (!fm_eth_tx_port_parameter_init(fm_eth))
return 0;
return 1;
}
static int fm_eth_startup(struct fm_eth *fm_eth)
{
struct fsl_enet_mac *mac;
mac = fm_eth->mac;
/* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
if (!fm_eth_init(fm_eth))
return 0;
/* setup the MAC controller */
mac->init_mac(mac);
/* For some reason we need to set SPEED_100 */
if ((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) && mac->set_if_mode)
mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
/* init bmi rx port, IM mode and disable */
bmi_rx_port_init(fm_eth->rx_port);
/* init bmi tx port, IM mode and disable */
bmi_tx_port_init(fm_eth->tx_port);
return 1;
}
static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
{
struct fm_port_global_pram *pram;
pram = fm_eth->tx_pram;
/* graceful stop transmission of frames */
pram->mode |= PRAM_MODE_GRACEFUL_STOP;
sync();
}
static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
{
struct fm_port_global_pram *pram;
pram = fm_eth->tx_pram;
/* re-enable transmission of frames */
pram->mode &= ~PRAM_MODE_GRACEFUL_STOP;
sync();
}
static int fm_eth_open(struct eth_device *dev, bd_t *bd)
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
fm_eth = (struct fm_eth *)dev->priv;
mac = fm_eth->mac;
/* setup the MAC address */
if (dev->enetaddr[0] & 0x01) {
printf("%s: MacAddress is multcast address\n", __func__);
return 1;
}
mac->set_mac_addr(mac, dev->enetaddr);
/* enable bmi Rx port */
setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
/* enable MAC rx/tx port */
mac->enable_mac(mac);
/* enable bmi Tx port */
setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
/* re-enable transmission of frame */
fmc_tx_port_graceful_stop_disable(fm_eth);
#ifdef CONFIG_PHYLIB
phy_startup(fm_eth->phydev);
#else
fm_eth->phydev->speed = SPEED_1000;
fm_eth->phydev->link = 1;
fm_eth->phydev->duplex = DUPLEX_FULL;
#endif
/* set the MAC-PHY mode */
mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
if (!fm_eth->phydev->link)
printf("%s: No link.\n", fm_eth->phydev->dev->name);
return fm_eth->phydev->link ? 0 : -1;
}
static void fm_eth_halt(struct eth_device *dev)
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
fm_eth = (struct fm_eth *)dev->priv;
mac = fm_eth->mac;
/* graceful stop the transmission of frames */
fmc_tx_port_graceful_stop_enable(fm_eth);
/* disable bmi Tx port */
bmi_tx_port_disable(fm_eth->tx_port);
/* disable MAC rx/tx port */
mac->disable_mac(mac);
/* disable bmi Rx port */
bmi_rx_port_disable(fm_eth->rx_port);
phy_shutdown(fm_eth->phydev);
}
static int fm_eth_send(struct eth_device *dev, volatile void *buf, int len)
{
struct fm_eth *fm_eth;
struct fm_port_global_pram *pram;
struct fm_port_bd *txbd, *txbd_base;
u16 offset_in;
int i;
fm_eth = (struct fm_eth *)dev->priv;
pram = fm_eth->tx_pram;
txbd = fm_eth->cur_txbd;
/* find one empty TxBD */
for (i = 0; txbd->status & TxBD_READY; i++) {
udelay(100);
if (i > 0x1000) {
printf("%s: Tx buffer not ready\n", dev->name);
return 0;
}
}
/* setup TxBD */
txbd->buf_ptr_hi = 0;
txbd->buf_ptr_lo = (u32)buf;
txbd->len = len;
sync();
txbd->status = TxBD_READY | TxBD_LAST;
sync();
/* update TxQD, let RISC to send the packet */
offset_in = muram_readw(&pram->txqd.offset_in);
offset_in += sizeof(struct fm_port_bd);
if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
offset_in = 0;
muram_writew(&pram->txqd.offset_in, offset_in);
sync();
/* wait for buffer to be transmitted */
for (i = 0; txbd->status & TxBD_READY; i++) {
udelay(100);
if (i > 0x10000) {
printf("%s: Tx error\n", dev->name);
return 0;
}
}
/* advance the TxBD */
txbd++;
txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
if (txbd >= (txbd_base + TX_BD_RING_SIZE))
txbd = txbd_base;
/* update current txbd */
fm_eth->cur_txbd = (void *)txbd;
return 1;
}
static int fm_eth_recv(struct eth_device *dev)
{
struct fm_eth *fm_eth;
struct fm_port_global_pram *pram;
struct fm_port_bd *rxbd, *rxbd_base;
u16 status, len;
u8 *data;
u16 offset_out;
fm_eth = (struct fm_eth *)dev->priv;
pram = fm_eth->rx_pram;
rxbd = fm_eth->cur_rxbd;
status = rxbd->status;
while (!(status & RxBD_EMPTY)) {
if (!(status & RxBD_ERROR)) {
data = (u8 *)rxbd->buf_ptr_lo;
len = rxbd->len;
NetReceive(data, len);
} else {
printf("%s: Rx error\n", dev->name);
return 0;
}
/* clear the RxBDs */
rxbd->status = RxBD_EMPTY;
rxbd->len = 0;
sync();
/* advance RxBD */
rxbd++;
rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
rxbd = rxbd_base;
/* read next status */
status = rxbd->status;
/* update RxQD */
offset_out = muram_readw(&pram->rxqd.offset_out);
offset_out += sizeof(struct fm_port_bd);
if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
offset_out = 0;
muram_writew(&pram->rxqd.offset_out, offset_out);
sync();
}
fm_eth->cur_rxbd = (void *)rxbd;
return 1;
}
static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
{
struct fsl_enet_mac *mac;
int num;
void *base, *phyregs = NULL;
num = fm_eth->num;
/* Get the mac registers base address */
if (fm_eth->type == FM_ETH_1G_E) {
base = ®->mac_1g[num].fm_dtesc;
phyregs = ®->mac_1g[num].fm_mdio.miimcfg;
} else {
base = ®->mac_10g[num].fm_10gec;
phyregs = ®->mac_10g[num].fm_10gec_mdio;
}
/* alloc mac controller */
mac = malloc(sizeof(struct fsl_enet_mac));
if (!mac)
return 0;
memset(mac, 0, sizeof(struct fsl_enet_mac));
/* save the mac to fm_eth struct */
fm_eth->mac = mac;
if (fm_eth->type == FM_ETH_1G_E)
init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
else
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
return 1;
}
static int init_phy(struct eth_device *dev)
{
struct fm_eth *fm_eth = dev->priv;
struct phy_device *phydev = NULL;
u32 supported;
#ifdef CONFIG_PHYLIB
if (fm_eth->type == FM_ETH_1G_E)
dtsec_init_phy(dev);
if (fm_eth->bus) {
phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, dev,
fm_eth->enet_if);
}
if (!phydev) {
printf("Failed to connect\n");
return -1;
}
if (fm_eth->type == FM_ETH_1G_E) {
supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Full);
} else {
supported = SUPPORTED_10000baseT_Full;
if (tgec_is_fibre(dev))
phydev->port = PORT_FIBRE;
}
phydev->supported &= supported;
phydev->advertising = phydev->supported;
fm_eth->phydev = phydev;
phy_config(phydev);
#endif
return 0;
}
int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
{
struct eth_device *dev;
struct fm_eth *fm_eth;
int i, num = info->num;
/* alloc eth device */
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev)
return 0;
memset(dev, 0, sizeof(struct eth_device));
/* alloc the FMan ethernet private struct */
fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
if (!fm_eth)
return 0;
memset(fm_eth, 0, sizeof(struct fm_eth));
/* save off some things we need from the info struct */
fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
fm_eth->num = num;
fm_eth->type = info->type;
fm_eth->rx_port = (void *)®->port[info->rx_port_id - 1].fm_bmi;
fm_eth->tx_port = (void *)®->port[info->tx_port_id - 1].fm_bmi;
/* set the ethernet max receive length */
fm_eth->max_rx_len = MAX_RXBUF_LEN;
/* init global mac structure */
if (!fm_eth_init_mac(fm_eth, reg))
return 0;
/* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
if (fm_eth->type == FM_ETH_1G_E)
sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
else
sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
devlist[num_controllers++] = dev;
dev->iobase = 0;
dev->priv = (void *)fm_eth;
dev->init = fm_eth_open;
dev->halt = fm_eth_halt;
dev->send = fm_eth_send;
dev->recv = fm_eth_recv;
fm_eth->dev = dev;
fm_eth->bus = info->bus;
fm_eth->phyaddr = info->phy_addr;
fm_eth->enet_if = info->enet_if;
/* startup the FM im */
if (!fm_eth_startup(fm_eth))
return 0;
if (init_phy(dev))
return 0;
/* clear the ethernet address */
for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
eth_register(dev);
return 1;
}
|
1001-study-uboot
|
drivers/net/fm/eth.c
|
C
|
gpl3
| 17,291
|
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
/* handle RGMII first */
if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII))
return PHY_INTERFACE_MODE_MII;
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII))
return PHY_INTERFACE_MODE_MII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
case FM1_DTSEC5:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}
|
1001-study-uboot
|
drivers/net/fm/p5020.c
|
C
|
gpl3
| 2,912
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Andy Fleming <afleming@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
* Some part is taken from tsec.c
*/
#include <common.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/io.h>
#include <asm/fsl_tgec.h>
#include <fm_eth.h>
/*
* Write value to the PHY for this device to the register at regnum, waiting
* until the write is done before it returns. All PHY configuration has to be
* done through the TSEC1 MIIM regs
*/
int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
int regnum, u16 value)
{
u32 mdio_ctl;
u32 stat_val;
struct tgec_mdio_controller *regs = bus->priv;
if (dev_addr == MDIO_DEVAD_NONE)
return 0;
/* Wait till the bus is free */
stat_val = MDIO_STAT_CLKDIV(100);
out_be32(®s->mdio_stat, stat_val);
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Set the port and dev addr */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
out_be32(®s->mdio_ctl, mdio_ctl);
/* Set the register address */
out_be32(®s->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Write the value to the register */
out_be32(®s->mdio_data, MDIO_DATA(value));
/* Wait till the MDIO write is complete */
while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
;
return 0;
}
/*
* Reads from register regnum in the PHY for device dev, returning the value.
* Clears miimcom first. All PHY configuration has to be done through the
* TSEC1 MIIM regs
*/
int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
int regnum)
{
u32 mdio_ctl;
u32 stat_val;
struct tgec_mdio_controller *regs = bus->priv;
if (dev_addr == MDIO_DEVAD_NONE)
return 0xffff;
stat_val = MDIO_STAT_CLKDIV(100);
out_be32(®s->mdio_stat, stat_val);
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Set the Port and Device Addrs */
mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
out_be32(®s->mdio_ctl, mdio_ctl);
/* Set the register address */
out_be32(®s->mdio_addr, regnum & 0xffff);
/* Wait till the bus is free */
while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
;
/* Initiate the read */
mdio_ctl |= MDIO_CTL_READ;
out_be32(®s->mdio_ctl, mdio_ctl);
/* Wait till the MDIO write is complete */
while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
;
/* Return all Fs if nothing was there */
if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
return 0xffff;
return in_be32(®s->mdio_data) & 0xffff;
}
int tgec_mdio_reset(struct mii_dev *bus)
{
return 0;
}
int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info)
{
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate FM TGEC MDIO bus\n");
return -1;
}
bus->read = tgec_mdio_read;
bus->write = tgec_mdio_write;
bus->reset = tgec_mdio_reset;
sprintf(bus->name, info->name);
bus->priv = info->regs;
return mdio_register(bus);
}
|
1001-study-uboot
|
drivers/net/fm/tgec_phy.c
|
C
|
gpl3
| 3,734
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FM_H__
#define __FM_H__
#include <common.h>
#include <fm_eth.h>
#include <asm/fsl_enet.h>
#include <asm/fsl_fman.h>
/* Port ID */
#define OH_PORT_ID_BASE 0x01
#define MAX_NUM_OH_PORT 7
#define RX_PORT_1G_BASE 0x08
#define MAX_NUM_RX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
#define RX_PORT_10G_BASE 0x10
#define TX_PORT_1G_BASE 0x28
#define MAX_NUM_TX_PORT_1G CONFIG_SYS_NUM_FM1_DTSEC
#define TX_PORT_10G_BASE 0x30
struct fm_muram {
u32 base;
u32 top;
u32 size;
u32 alloc;
};
#define FM_MURAM_RES_SIZE 0x01000
/* Rx/Tx buffer descriptor */
struct fm_port_bd {
u16 status;
u16 len;
u32 res0;
u16 res1;
u16 buf_ptr_hi;
u32 buf_ptr_lo;
};
/* Common BD flags */
#define BD_LAST 0x0800
/* Rx BD status flags */
#define RxBD_EMPTY 0x8000
#define RxBD_LAST BD_LAST
#define RxBD_FIRST 0x0400
#define RxBD_PHYS_ERR 0x0008
#define RxBD_SIZE_ERR 0x0004
#define RxBD_ERROR (RxBD_PHYS_ERR | RxBD_SIZE_ERR)
/* Tx BD status flags */
#define TxBD_READY 0x8000
#define TxBD_LAST BD_LAST
/* Rx/Tx queue descriptor */
struct fm_port_qd {
u16 gen;
u16 bd_ring_base_hi;
u32 bd_ring_base_lo;
u16 bd_ring_size;
u16 offset_in;
u16 offset_out;
u16 res0;
u32 res1[0x4];
};
/* IM global parameter RAM */
struct fm_port_global_pram {
u32 mode; /* independent mode register */
u32 rxqd_ptr; /* Rx queue descriptor pointer */
u32 txqd_ptr; /* Tx queue descriptor pointer */
u16 mrblr; /* max Rx buffer length */
u16 rxqd_bsy_cnt; /* RxQD busy counter, should be cleared */
u32 res0[0x4];
struct fm_port_qd rxqd; /* Rx queue descriptor */
struct fm_port_qd txqd; /* Tx queue descriptor */
u32 res1[0x28];
};
#define FM_PRAM_SIZE sizeof(struct fm_port_global_pram)
#define FM_PRAM_ALIGN 256
#define PRAM_MODE_GLOBAL 0x20000000
#define PRAM_MODE_GRACEFUL_STOP 0x00800000
#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
#define FM_FREE_POOL_SIZE 0x2000 /* 8K bytes */
#else
#define FM_FREE_POOL_SIZE 0x20000 /* 128K bytes */
#endif
#define FM_FREE_POOL_ALIGN 256
u32 fm_muram_alloc(int fm_idx, u32 size, u32 align);
u32 fm_muram_base(int fm_idx);
int fm_init_common(int index, struct ccsr_fman *reg);
int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info);
phy_interface_t fman_port_enet_if(enum fm_port port);
void fman_disable_port(enum fm_port port);
struct fsl_enet_mac {
void *base; /* MAC controller registers base address */
void *phyregs;
int max_rx_len;
void (*init_mac)(struct fsl_enet_mac *mac);
void (*enable_mac)(struct fsl_enet_mac *mac);
void (*disable_mac)(struct fsl_enet_mac *mac);
void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr);
void (*set_if_mode)(struct fsl_enet_mac *mac, phy_interface_t type,
int speed);
};
/* Fman ethernet private struct */
struct fm_eth {
int fm_index; /* Fman index */
u32 num; /* 0..n-1 for give type */
struct fm_bmi_tx_port *tx_port;
struct fm_bmi_rx_port *rx_port;
enum fm_eth_type type; /* 1G or 10G ethernet */
phy_interface_t enet_if;
struct fsl_enet_mac *mac; /* MAC controller */
struct mii_dev *bus;
struct phy_device *phydev;
int phyaddr;
struct eth_device *dev;
int max_rx_len;
struct fm_port_global_pram *rx_pram; /* Rx parameter table */
struct fm_port_global_pram *tx_pram; /* Tx parameter table */
void *rx_bd_ring; /* Rx BD ring base */
void *cur_rxbd; /* current Rx BD */
void *rx_buf; /* Rx buffer base */
void *tx_bd_ring; /* Tx BD ring base */
void *cur_txbd; /* current Tx BD */
};
#define RX_BD_RING_SIZE 8
#define TX_BD_RING_SIZE 8
#define MAX_RXBUF_LOG2 11
#define MAX_RXBUF_LEN (1 << MAX_RXBUF_LOG2)
#endif /* __FM_H__ */
|
1001-study-uboot
|
drivers/net/fm/fm.h
|
C
|
gpl3
| 4,378
|
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
return PHY_INTERFACE_MODE_XGMII;
/* handle RGMII first */
if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
case FM2_DTSEC1:
case FM2_DTSEC2:
case FM2_DTSEC3:
case FM2_DTSEC4:
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}
|
1001-study-uboot
|
drivers/net/fm/p4080.c
|
C
|
gpl3
| 3,202
|
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
/* handle RGMII/MII first */
if ((port == FM1_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC2) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM2_DTSEC1) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1))
return PHY_INTERFACE_MODE_RGMII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
case FM2_DTSEC1:
case FM2_DTSEC2:
case FM2_DTSEC3:
case FM2_DTSEC4:
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}
|
1001-study-uboot
|
drivers/net/fm/p3060.c
|
C
|
gpl3
| 2,918
|
/*
dm9000.c: Version 1.2 12/15/2003
A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
Copyright (C) 1997 Sten Wang
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License
as published by the Free Software Foundation; either version 2
of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
(C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
06/22/2001 Support DM9801 progrmming
E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
R17 = (R17 & 0xfff0) | NF + 3
E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
R17 = (R17 & 0xfff0) | NF
v1.00 modify by simon 2001.9.5
change for kernel 2.4.x
v1.1 11/09/2001 fix force mode bug
v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
Fixed phy reset.
Added tx/rx 32 bit mode.
Cleaned up for kernel merge.
--------------------------------------
12/15/2003 Initial port to u-boot by
Sascha Hauer <saschahauer@web.de>
06/03/2008 Remy Bohmer <linux@bohmer.net>
- Fixed the driver to work with DM9000A.
(check on ISR receive status bit before reading the
FIFO as described in DM9000 programming guide and
application notes)
- Added autodetect of databus width.
- Made debug code compile again.
- Adapt eth_send such that it matches the DM9000*
application notes. Needed to make it work properly
for DM9000A.
- Adapted reset procedure to match DM9000 application
notes (i.e. double reset)
- some minor code cleanups
These changes are tested with DM9000{A,EP,E} together
with a 200MHz Atmel AT91SAM9261 core
TODO: external MII is not functional, only internal at the moment.
*/
#include <common.h>
#include <command.h>
#include <net.h>
#include <asm/io.h>
#include <dm9000.h>
#include "dm9000x.h"
/* Board/System/Debug information/definition ---------------- */
/* #define CONFIG_DM9000_DEBUG */
#ifdef CONFIG_DM9000_DEBUG
#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
#define DM9000_DMP_PACKET(func,packet,length) \
do { \
int i; \
printf("%s: length: %d\n", func, length); \
for (i = 0; i < length; i++) { \
if (i % 8 == 0) \
printf("\n%s: %02x: ", func, i); \
printf("%02x ", ((unsigned char *) packet)[i]); \
} printf("\n"); \
} while(0)
#else
#define DM9000_DBG(fmt,args...)
#define DM9000_DMP_PACKET(func,packet,length)
#endif
/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
u32 runt_length_counter; /* counter: RX length < 64byte */
u32 long_length_counter; /* counter: RX length > 1514byte */
u32 reset_counter; /* counter: RESET */
u32 reset_tx_timeout; /* RESET caused by TX Timeout */
u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
u16 tx_pkt_cnt;
u16 queue_start_addr;
u16 dbug_cnt;
u8 phy_addr;
u8 device_wait_reset; /* device state */
unsigned char srom[128];
void (*outblk)(volatile void *data_ptr, int count);
void (*inblk)(void *data_ptr, int count);
void (*rx_status)(u16 *RxStatus, u16 *RxLen);
struct eth_device netdev;
} board_info_t;
static board_info_t dm9000_info;
/* function declaration ------------------------------------- */
static int dm9000_probe(void);
static u16 dm9000_phy_read(int);
static void dm9000_phy_write(int, u16);
static u8 DM9000_ior(int);
static void DM9000_iow(int reg, u8 value);
/* DM9000 network board routine ---------------------------- */
#ifndef CONFIG_DM9000_BYTE_SWAPPED
#define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
#define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
#define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
#define DM9000_inb(r) readb((volatile u8 *)(r))
#define DM9000_inw(r) readw((volatile u16 *)(r))
#define DM9000_inl(r) readl((volatile u32 *)(r))
#else
#define DM9000_outb(d, r) __raw_writeb(d, r)
#define DM9000_outw(d, r) __raw_writew(d, r)
#define DM9000_outl(d, r) __raw_writel(d, r)
#define DM9000_inb(r) __raw_readb(r)
#define DM9000_inw(r) __raw_readw(r)
#define DM9000_inl(r) __raw_readl(r)
#endif
#ifdef CONFIG_DM9000_DEBUG
static void
dump_regs(void)
{
DM9000_DBG("\n");
DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
DM9000_DBG("\n");
}
#endif
static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
{
int i;
for (i = 0; i < count; i++)
DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
}
static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
{
int i;
u32 tmplen = (count + 1) / 2;
for (i = 0; i < tmplen; i++)
DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
}
static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
{
int i;
u32 tmplen = (count + 3) / 4;
for (i = 0; i < tmplen; i++)
DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
}
static void dm9000_inblk_8bit(void *data_ptr, int count)
{
int i;
for (i = 0; i < count; i++)
((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
}
static void dm9000_inblk_16bit(void *data_ptr, int count)
{
int i;
u32 tmplen = (count + 1) / 2;
for (i = 0; i < tmplen; i++)
((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
}
static void dm9000_inblk_32bit(void *data_ptr, int count)
{
int i;
u32 tmplen = (count + 3) / 4;
for (i = 0; i < tmplen; i++)
((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
}
static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
{
u32 tmpdata;
DM9000_outb(DM9000_MRCMD, DM9000_IO);
tmpdata = DM9000_inl(DM9000_DATA);
*RxStatus = __le16_to_cpu(tmpdata);
*RxLen = __le16_to_cpu(tmpdata >> 16);
}
static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
{
DM9000_outb(DM9000_MRCMD, DM9000_IO);
*RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
*RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
}
static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
{
DM9000_outb(DM9000_MRCMD, DM9000_IO);
*RxStatus =
__le16_to_cpu(DM9000_inb(DM9000_DATA) +
(DM9000_inb(DM9000_DATA) << 8));
*RxLen =
__le16_to_cpu(DM9000_inb(DM9000_DATA) +
(DM9000_inb(DM9000_DATA) << 8));
}
/*
Search DM9000 board, allocate space and register it
*/
int
dm9000_probe(void)
{
u32 id_val;
id_val = DM9000_ior(DM9000_VIDL);
id_val |= DM9000_ior(DM9000_VIDH) << 8;
id_val |= DM9000_ior(DM9000_PIDL) << 16;
id_val |= DM9000_ior(DM9000_PIDH) << 24;
if (id_val == DM9000_ID) {
printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
id_val);
return 0;
} else {
printf("dm9000 not found at 0x%08x id: 0x%08x\n",
CONFIG_DM9000_BASE, id_val);
return -1;
}
}
/* General Purpose dm9000 reset routine */
static void
dm9000_reset(void)
{
DM9000_DBG("resetting DM9000\n");
/* Reset DM9000,
see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
/* DEBUG: Make all GPIO0 outputs, all others inputs */
DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
/* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
DM9000_iow(DM9000_GPR, 0);
/* Step 2: Software reset */
DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
do {
DM9000_DBG("resetting the DM9000, 1st reset\n");
udelay(25); /* Wait at least 20 us */
} while (DM9000_ior(DM9000_NCR) & 1);
DM9000_iow(DM9000_NCR, 0);
DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
do {
DM9000_DBG("resetting the DM9000, 2nd reset\n");
udelay(25); /* Wait at least 20 us */
} while (DM9000_ior(DM9000_NCR) & 1);
/* Check whether the ethernet controller is present */
if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
(DM9000_ior(DM9000_PIDH) != 0x90))
printf("ERROR: resetting DM9000 -> not responding\n");
}
/* Initialize dm9000 board
*/
static int dm9000_init(struct eth_device *dev, bd_t *bd)
{
int i, oft, lnk;
u8 io_mode;
struct board_info *db = &dm9000_info;
DM9000_DBG("%s\n", __func__);
/* RESET device */
dm9000_reset();
if (dm9000_probe() < 0)
return -1;
/* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
io_mode = DM9000_ior(DM9000_ISR) >> 6;
switch (io_mode) {
case 0x0: /* 16-bit mode */
printf("DM9000: running in 16 bit mode\n");
db->outblk = dm9000_outblk_16bit;
db->inblk = dm9000_inblk_16bit;
db->rx_status = dm9000_rx_status_16bit;
break;
case 0x01: /* 32-bit mode */
printf("DM9000: running in 32 bit mode\n");
db->outblk = dm9000_outblk_32bit;
db->inblk = dm9000_inblk_32bit;
db->rx_status = dm9000_rx_status_32bit;
break;
case 0x02: /* 8 bit mode */
printf("DM9000: running in 8 bit mode\n");
db->outblk = dm9000_outblk_8bit;
db->inblk = dm9000_inblk_8bit;
db->rx_status = dm9000_rx_status_8bit;
break;
default:
/* Assume 8 bit mode, will probably not work anyway */
printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
db->outblk = dm9000_outblk_8bit;
db->inblk = dm9000_inblk_8bit;
db->rx_status = dm9000_rx_status_8bit;
break;
}
/* Program operating register, only internal phy supported */
DM9000_iow(DM9000_NCR, 0x0);
/* TX Polling clear */
DM9000_iow(DM9000_TCR, 0);
/* Less 3Kb, 200us */
DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
/* Flow Control : High/Low Water */
DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
/* SH FIXME: This looks strange! Flow Control */
DM9000_iow(DM9000_FCR, 0x0);
/* Special Mode */
DM9000_iow(DM9000_SMCR, 0);
/* clear TX status */
DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
/* Clear interrupt status */
DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
printf("MAC: %pM\n", dev->enetaddr);
/* fill device MAC address registers */
for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
DM9000_iow(oft, dev->enetaddr[i]);
for (i = 0, oft = 0x16; i < 8; i++, oft++)
DM9000_iow(oft, 0xff);
/* read back mac, just to be sure */
for (i = 0, oft = 0x10; i < 6; i++, oft++)
DM9000_DBG("%02x:", DM9000_ior(oft));
DM9000_DBG("\n");
/* Activate DM9000 */
/* RX enable */
DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
/* Enable TX/RX interrupt mask */
DM9000_iow(DM9000_IMR, IMR_PAR);
i = 0;
while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */
udelay(1000);
i++;
if (i == 3000) {
printf("could not establish link\n");
return 0;
}
}
/* see what we've got */
lnk = dm9000_phy_read(17) >> 12;
printf("operating at ");
switch (lnk) {
case 1:
printf("10M half duplex ");
break;
case 2:
printf("10M full duplex ");
break;
case 4:
printf("100M half duplex ");
break;
case 8:
printf("100M full duplex ");
break;
default:
printf("unknown: %d ", lnk);
break;
}
printf("mode\n");
return 0;
}
/*
Hardware start transmission.
Send a packet to media from the upper layer.
*/
static int dm9000_send(struct eth_device *netdev, volatile void *packet,
int length)
{
int tmo;
struct board_info *db = &dm9000_info;
DM9000_DMP_PACKET(__func__ , packet, length);
DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
/* Move data to DM9000 TX RAM */
DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
/* push the data to the TX-fifo */
(db->outblk)(packet, length);
/* Set TX length to DM9000 */
DM9000_iow(DM9000_TXPLL, length & 0xff);
DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
/* Issue TX polling command */
DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
/* wait for end of transmission */
tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
!(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
if (get_timer(0) >= tmo) {
printf("transmission timeout\n");
break;
}
}
DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
DM9000_DBG("transmit done\n\n");
return 0;
}
/*
Stop the interface.
The interface is stopped when it is brought.
*/
static void dm9000_halt(struct eth_device *netdev)
{
#if 0 //wx: resolve ping failed
DM9000_DBG("%s\n", __func__);
/* RESET devie */
dm9000_phy_write(0, 0x8000); /* PHY RESET */
DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
#else
printf("dm9000_halt\n");
#endif
}
/*
Received a packet and pass to upper layer
*/
static int dm9000_rx(struct eth_device *netdev)
{
u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
u16 RxStatus, RxLen = 0;
struct board_info *db = &dm9000_info;
/* Check packet ready or not, we must check
the ISR status first for DM9000A */
if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
return 0;
DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
/* There is _at least_ 1 package in the fifo, read them all */
for (;;) {
DM9000_ior(DM9000_MRCMDX); /* Dummy read */
/* Get most updated data,
only look at bits 0:1, See application notes DM9000 */
rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
/* Status check: this byte must be 0 or 1 */
if (rxbyte > DM9000_PKT_RDY) {
DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
printf("DM9000 error: status check fail: 0x%x\n",
rxbyte);
return 0;
}
if (rxbyte != DM9000_PKT_RDY)
return 0; /* No packet received, ignore */
DM9000_DBG("receiving packet\n");
/* A packet ready now & Get status/length */
(db->rx_status)(&RxStatus, &RxLen);
DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
/* Move data from DM9000 */
/* Read received packet from RX SRAM */
(db->inblk)(rdptr, RxLen);
if ((RxStatus & 0xbf00) || (RxLen < 0x40)
|| (RxLen > DM9000_PKT_MAX)) {
if (RxStatus & 0x100) {
printf("rx fifo error\n");
}
if (RxStatus & 0x200) {
printf("rx crc error\n");
}
if (RxStatus & 0x8000) {
printf("rx length error\n");
}
if (RxLen > DM9000_PKT_MAX) {
printf("rx length too big\n");
dm9000_reset();
}
} else {
DM9000_DMP_PACKET(__func__ , rdptr, RxLen);
DM9000_DBG("passing packet to upper layer\n");
NetReceive(NetRxPackets[0], RxLen);
}
}
return 0;
}
/*
Read a word data from SROM
*/
#if !defined(CONFIG_DM9000_NO_SROM)
void dm9000_read_srom_word(int offset, u8 *to)
{
DM9000_iow(DM9000_EPAR, offset);
DM9000_iow(DM9000_EPCR, 0x4);
udelay(8000);
DM9000_iow(DM9000_EPCR, 0x0);
to[0] = DM9000_ior(DM9000_EPDRL);
to[1] = DM9000_ior(DM9000_EPDRH);
}
void dm9000_write_srom_word(int offset, u16 val)
{
DM9000_iow(DM9000_EPAR, offset);
DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
DM9000_iow(DM9000_EPDRL, (val & 0xff));
DM9000_iow(DM9000_EPCR, 0x12);
udelay(8000);
DM9000_iow(DM9000_EPCR, 0);
}
#endif
static void dm9000_get_enetaddr(struct eth_device *dev)
{
#if !defined(CONFIG_DM9000_NO_SROM)
int i;
for (i = 0; i < 3; i++)
dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
#endif
}
/*
Read a byte from I/O port
*/
static u8
DM9000_ior(int reg)
{
DM9000_outb(reg, DM9000_IO);
return DM9000_inb(DM9000_DATA);
}
/*
Write a byte to I/O port
*/
static void
DM9000_iow(int reg, u8 value)
{
DM9000_outb(reg, DM9000_IO);
DM9000_outb(value, DM9000_DATA);
}
/*
Read a word from phyxcer
*/
static u16
dm9000_phy_read(int reg)
{
u16 val;
/* Fill the phyxcer register into REG_0C */
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
udelay(1000);//udelay(100); /* Wait read complete wx:resolve First times Ping failed*/
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
/* The read data keeps on REG_0D & REG_0E */
DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val);
return val;
}
/*
Write a word to phyxcer
*/
static void
dm9000_phy_write(int reg, u16 value)
{
/* Fill the phyxcer register into REG_0C */
DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
/* Fill the written data into REG_0D & REG_0E */
DM9000_iow(DM9000_EPDRL, (value & 0xff));
DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
udelay(500); /* Wait write complete */
DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value);
}
int dm9000_initialize(bd_t *bis)
{
struct eth_device *dev = &(dm9000_info.netdev);
/* Load MAC address from EEPROM */
dm9000_get_enetaddr(dev);
dev->init = dm9000_init;
dev->halt = dm9000_halt;
dev->send = dm9000_send;
dev->recv = dm9000_rx;
sprintf(dev->name, "dm9000");
eth_register(dev);
return 0;
}
|
1001-study-uboot
|
drivers/net/dm9000x.c
|
C
|
gpl3
| 17,272
|
/*
* sh_eth.c - Driver for Renesas SH7763's ethernet controler.
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (c) 2008 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/errno.h>
#include <asm/io.h>
#include "sh_eth.h"
#ifndef CONFIG_SH_ETHER_USE_PORT
# error "Please define CONFIG_SH_ETHER_USE_PORT"
#endif
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
#define flush_cache_wback(addr, len) \
dcache_wback_range((u32)addr, (u32)(addr + len - 1))
#else
#define flush_cache_wback(...)
#endif
#define SH_ETH_PHY_DELAY 50000
int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
{
struct sh_eth_dev *eth = dev->priv;
int port = eth->port, ret = 0, timeout;
struct sh_eth_info *port_info = ð->port_info[port];
if (!packet || len > 0xffff) {
printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
ret = -EINVAL;
goto err;
}
/* packet must be a 4 byte boundary */
if ((int)packet & (4 - 1)) {
printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
ret = -EFAULT;
goto err;
}
/* Update tx descriptor */
flush_cache_wback(packet, len);
port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
port_info->tx_desc_cur->td1 = len << 16;
/* Must preserve the end of descriptor list indication */
if (port_info->tx_desc_cur->td0 & TD_TDLE)
port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
else
port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
/* Restart the transmitter if disabled */
if (!(inl(EDTRR(port)) & EDTRR_TRNS))
outl(EDTRR_TRNS, EDTRR(port));
/* Wait until packet is transmitted */
timeout = 1000;
while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
udelay(100);
if (timeout < 0) {
printf(SHETHER_NAME ": transmit timeout\n");
ret = -ETIMEDOUT;
goto err;
}
port_info->tx_desc_cur++;
if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
port_info->tx_desc_cur = port_info->tx_desc_base;
return ret;
err:
return ret;
}
int sh_eth_recv(struct eth_device *dev)
{
struct sh_eth_dev *eth = dev->priv;
int port = eth->port, len = 0;
struct sh_eth_info *port_info = ð->port_info[port];
volatile u8 *packet;
/* Check if the rx descriptor is ready */
if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
/* Check for errors */
if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
len = port_info->rx_desc_cur->rd1 & 0xffff;
packet = (volatile u8 *)
ADDR_TO_P2(port_info->rx_desc_cur->rd2);
NetReceive(packet, len);
}
/* Make current descriptor available again */
if (port_info->rx_desc_cur->rd0 & RD_RDLE)
port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
else
port_info->rx_desc_cur->rd0 = RD_RACT;
/* Point to the next descriptor */
port_info->rx_desc_cur++;
if (port_info->rx_desc_cur >=
port_info->rx_desc_base + NUM_RX_DESC)
port_info->rx_desc_cur = port_info->rx_desc_base;
}
/* Restart the receiver if disabled */
if (!(inl(EDRRR(port)) & EDRRR_R))
outl(EDRRR_R, EDRRR(port));
return len;
}
#define EDMR_INIT_CNT 1000
static int sh_eth_reset(struct sh_eth_dev *eth)
{
int port = eth->port;
#if defined(CONFIG_CPU_SH7763)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
outl(EDSR_ENALL, EDSR(port));
/* Perform a software reset and wait for it to complete */
outl(EDMR_SRST, EDMR(port));
for (i = 0; i < EDMR_INIT_CNT; i++) {
if (!(inl(EDMR(port)) & EDMR_SRST))
break;
udelay(1000);
}
if (i == EDMR_INIT_CNT) {
printf(SHETHER_NAME ": Software reset timeout\n");
ret = -EIO;
}
return ret;
#else
outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
udelay(3000);
outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
return 0;
#endif
}
static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
{
int port = eth->port, i, ret = 0;
u32 tmp_addr;
struct sh_eth_info *port_info = ð->port_info[port];
struct tx_desc_s *cur_tx_desc;
/*
* Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
*/
port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
sizeof(struct tx_desc_s) +
TX_DESC_SIZE - 1);
if (!port_info->tx_desc_malloc) {
printf(SHETHER_NAME ": malloc failed\n");
ret = -ENOMEM;
goto err;
}
tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
~(TX_DESC_SIZE - 1));
flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
port_info->tx_desc_cur = port_info->tx_desc_base;
/* Initialize all descriptors */
for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
cur_tx_desc++, i++) {
cur_tx_desc->td0 = 0x00;
cur_tx_desc->td1 = 0x00;
cur_tx_desc->td2 = 0x00;
}
/* Mark the end of the descriptors */
cur_tx_desc--;
cur_tx_desc->td0 |= TD_TDLE;
/* Point the controller to the tx descriptor list. Must use physical
addresses */
outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
#if defined(CONFIG_CPU_SH7763)
outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
outl(0x01, TDFFR(port));/* Last discriptor bit */
#endif
err:
return ret;
}
static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
{
int port = eth->port, i , ret = 0;
struct sh_eth_info *port_info = ð->port_info[port];
struct rx_desc_s *cur_rx_desc;
u32 tmp_addr;
u8 *rx_buf;
/*
* Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
*/
port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
sizeof(struct rx_desc_s) +
RX_DESC_SIZE - 1);
if (!port_info->rx_desc_malloc) {
printf(SHETHER_NAME ": malloc failed\n");
ret = -ENOMEM;
goto err;
}
tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
~(RX_DESC_SIZE - 1));
flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
/* Make sure we use a P2 address (non-cacheable) */
port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
port_info->rx_desc_cur = port_info->rx_desc_base;
/*
* Allocate rx data buffers. They must be 32 bytes aligned and in
* P2 area
*/
port_info->rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
if (!port_info->rx_buf_malloc) {
printf(SHETHER_NAME ": malloc failed\n");
ret = -ENOMEM;
goto err_buf_malloc;
}
tmp_addr = (u32)(((int)port_info->rx_buf_malloc + (32 - 1)) &
~(32 - 1));
port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
/* Initialize all descriptors */
for (cur_rx_desc = port_info->rx_desc_base,
rx_buf = port_info->rx_buf_base, i = 0;
i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
cur_rx_desc->rd0 = RD_RACT;
cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
}
/* Mark the end of the descriptors */
cur_rx_desc--;
cur_rx_desc->rd0 |= RD_RDLE;
/* Point the controller to the rx descriptor list */
outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
#if defined(CONFIG_CPU_SH7763)
outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
outl(RDFFR_RDLF, RDFFR(port));
#endif
return ret;
err_buf_malloc:
free(port_info->rx_desc_malloc);
port_info->rx_desc_malloc = NULL;
err:
return ret;
}
static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
{
int port = eth->port;
struct sh_eth_info *port_info = ð->port_info[port];
if (port_info->tx_desc_malloc) {
free(port_info->tx_desc_malloc);
port_info->tx_desc_malloc = NULL;
}
}
static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
{
int port = eth->port;
struct sh_eth_info *port_info = ð->port_info[port];
if (port_info->rx_desc_malloc) {
free(port_info->rx_desc_malloc);
port_info->rx_desc_malloc = NULL;
}
if (port_info->rx_buf_malloc) {
free(port_info->rx_buf_malloc);
port_info->rx_buf_malloc = NULL;
}
}
static int sh_eth_desc_init(struct sh_eth_dev *eth)
{
int ret = 0;
ret = sh_eth_tx_desc_init(eth);
if (ret)
goto err_tx_init;
ret = sh_eth_rx_desc_init(eth);
if (ret)
goto err_rx_init;
return ret;
err_rx_init:
sh_eth_tx_desc_free(eth);
err_tx_init:
return ret;
}
static int sh_eth_phy_config(struct sh_eth_dev *eth)
{
int port = eth->port, ret = 0;
struct sh_eth_info *port_info = ð->port_info[port];
struct eth_device *dev = port_info->dev;
struct phy_device *phydev;
phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
port_info->phydev = phydev;
phy_config(phydev);
return ret;
}
static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
{
int port = eth->port, ret = 0;
u32 val;
struct sh_eth_info *port_info = ð->port_info[port];
struct eth_device *dev = port_info->dev;
struct phy_device *phy;
/* Configure e-dmac registers */
outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
outl(0, EESIPR(port));
outl(0, TRSCER(port));
outl(0, TFTR(port));
outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
outl(RMCR_RST, RMCR(port));
#ifndef CONFIG_CPU_SH7757
outl(0, RPADIR(port));
#endif
outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
/* Configure e-mac registers */
#if defined(CONFIG_CPU_SH7757)
outl(ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP |
ECSIPR_MPDIP | ECSIPR_ICDIP, ECSIPR(port));
#else
outl(0, ECSIPR(port));
#endif
/* Set Mac address */
val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
dev->enetaddr[2] << 8 | dev->enetaddr[3];
outl(val, MAHR(port));
val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
outl(val, MALR(port));
outl(RFLR_RFL_MIN, RFLR(port));
#ifndef CONFIG_CPU_SH7757
outl(0, PIPR(port));
#endif
outl(APR_AP, APR(port));
outl(MPR_MP, MPR(port));
#ifdef CONFIG_CPU_SH7757
outl(TPAUSER_UNLIMITED, TPAUSER(port));
#else
outl(TPAUSER_TPAUSE, TPAUSER(port));
#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
if (ret) {
printf(SHETHER_NAME ": phy config timeout\n");
goto err_phy_cfg;
}
phy = port_info->phydev;
phy_startup(phy);
/* Set the transfer speed */
#ifdef CONFIG_CPU_SH7763
if (phy->speed == 100) {
printf(SHETHER_NAME ": 100Base/");
outl(GECMR_100B, GECMR(port));
} else if (phy->speed == 10) {
printf(SHETHER_NAME ": 10Base/");
outl(GECMR_10B, GECMR(port));
}
#endif
#if defined(CONFIG_CPU_SH7757)
if (phy->speed == 100) {
printf("100Base/");
outl(1, RTRATE(port));
} else if (phy->speed == 10) {
printf("10Base/");
outl(0, RTRATE(port));
}
#endif
/* Check if full duplex mode is supported by the phy */
if (phy->duplex) {
printf("Full\n");
outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
} else {
printf("Half\n");
outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
}
return ret;
err_phy_cfg:
return ret;
}
static void sh_eth_start(struct sh_eth_dev *eth)
{
/*
* Enable the e-dmac receiver only. The transmitter will be enabled when
* we have something to transmit
*/
outl(EDRRR_R, EDRRR(eth->port));
}
static void sh_eth_stop(struct sh_eth_dev *eth)
{
outl(~EDRRR_R, EDRRR(eth->port));
}
int sh_eth_init(struct eth_device *dev, bd_t *bd)
{
int ret = 0;
struct sh_eth_dev *eth = dev->priv;
ret = sh_eth_reset(eth);
if (ret)
goto err;
ret = sh_eth_desc_init(eth);
if (ret)
goto err;
ret = sh_eth_config(eth, bd);
if (ret)
goto err_config;
sh_eth_start(eth);
return ret;
err_config:
sh_eth_tx_desc_free(eth);
sh_eth_rx_desc_free(eth);
err:
return ret;
}
void sh_eth_halt(struct eth_device *dev)
{
struct sh_eth_dev *eth = dev->priv;
sh_eth_stop(eth);
}
int sh_eth_initialize(bd_t *bd)
{
int ret = 0;
struct sh_eth_dev *eth = NULL;
struct eth_device *dev = NULL;
eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
if (!eth) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
memset(dev, 0, sizeof(struct eth_device));
memset(eth, 0, sizeof(struct sh_eth_dev));
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
dev->priv = (void *)eth;
dev->iobase = 0;
dev->init = sh_eth_init;
dev->halt = sh_eth_halt;
dev->send = sh_eth_send;
dev->recv = sh_eth_recv;
eth->port_info[eth->port].dev = dev;
sprintf(dev->name, SHETHER_NAME);
/* Register Device to EtherNet subsystem */
eth_register(dev);
bb_miiphy_buses[0].priv = eth;
miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
puts("Please set MAC address\n");
return ret;
err:
if (dev)
free(dev);
if (eth)
free(eth);
printf(SHETHER_NAME ": Failed\n");
return ret;
}
/******* for bb_miiphy *******/
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
{
return 0;
}
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
struct sh_eth_dev *eth = bus->priv;
int port = eth->port;
outl(inl(PIR(port)) | PIR_MMD, PIR(port));
return 0;
}
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct sh_eth_dev *eth = bus->priv;
int port = eth->port;
outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
return 0;
}
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct sh_eth_dev *eth = bus->priv;
int port = eth->port;
if (v)
outl(inl(PIR(port)) | PIR_MDO, PIR(port));
else
outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
return 0;
}
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct sh_eth_dev *eth = bus->priv;
int port = eth->port;
*v = (inl(PIR(port)) & PIR_MDI) >> 3;
return 0;
}
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct sh_eth_dev *eth = bus->priv;
int port = eth->port;
if (v)
outl(inl(PIR(port)) | PIR_MDC, PIR(port));
else
outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
return 0;
}
static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
{
udelay(10);
return 0;
}
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = "sh_eth",
.init = sh_eth_bb_init,
.mdio_active = sh_eth_bb_mdio_active,
.mdio_tristate = sh_eth_bb_mdio_tristate,
.set_mdio = sh_eth_bb_set_mdio,
.get_mdio = sh_eth_bb_get_mdio,
.set_mdc = sh_eth_bb_set_mdc,
.delay = sh_eth_bb_delay,
}
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
|
1001-study-uboot
|
drivers/net/sh_eth.c
|
C
|
gpl3
| 15,314
|
/*
* Copyright (C) 2005-2006 Atmel Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __DRIVERS_MACB_H__
#define __DRIVERS_MACB_H__
/* MACB register offsets */
#define MACB_NCR 0x0000
#define MACB_NCFGR 0x0004
#define MACB_NSR 0x0008
#define MACB_TSR 0x0014
#define MACB_RBQP 0x0018
#define MACB_TBQP 0x001c
#define MACB_RSR 0x0020
#define MACB_ISR 0x0024
#define MACB_IER 0x0028
#define MACB_IDR 0x002c
#define MACB_IMR 0x0030
#define MACB_MAN 0x0034
#define MACB_PTR 0x0038
#define MACB_PFR 0x003c
#define MACB_FTO 0x0040
#define MACB_SCF 0x0044
#define MACB_MCF 0x0048
#define MACB_FRO 0x004c
#define MACB_FCSE 0x0050
#define MACB_ALE 0x0054
#define MACB_DTF 0x0058
#define MACB_LCOL 0x005c
#define MACB_EXCOL 0x0060
#define MACB_TUND 0x0064
#define MACB_CSE 0x0068
#define MACB_RRE 0x006c
#define MACB_ROVR 0x0070
#define MACB_RSE 0x0074
#define MACB_ELE 0x0078
#define MACB_RJA 0x007c
#define MACB_USF 0x0080
#define MACB_STE 0x0084
#define MACB_RLE 0x0088
#define MACB_TPF 0x008c
#define MACB_HRB 0x0090
#define MACB_HRT 0x0094
#define MACB_SA1B 0x0098
#define MACB_SA1T 0x009c
#define MACB_SA2B 0x00a0
#define MACB_SA2T 0x00a4
#define MACB_SA3B 0x00a8
#define MACB_SA3T 0x00ac
#define MACB_SA4B 0x00b0
#define MACB_SA4T 0x00b4
#define MACB_TID 0x00b8
#define MACB_TPQ 0x00bc
#define MACB_USRIO 0x00c0
#define MACB_WOL 0x00c4
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
#define MACB_LB_SIZE 1
#define MACB_LLB_OFFSET 1
#define MACB_LLB_SIZE 1
#define MACB_RE_OFFSET 2
#define MACB_RE_SIZE 1
#define MACB_TE_OFFSET 3
#define MACB_TE_SIZE 1
#define MACB_MPE_OFFSET 4
#define MACB_MPE_SIZE 1
#define MACB_CLRSTAT_OFFSET 5
#define MACB_CLRSTAT_SIZE 1
#define MACB_INCSTAT_OFFSET 6
#define MACB_INCSTAT_SIZE 1
#define MACB_WESTAT_OFFSET 7
#define MACB_WESTAT_SIZE 1
#define MACB_BP_OFFSET 8
#define MACB_BP_SIZE 1
#define MACB_TSTART_OFFSET 9
#define MACB_TSTART_SIZE 1
#define MACB_THALT_OFFSET 10
#define MACB_THALT_SIZE 1
#define MACB_NCR_TPF_OFFSET 11
#define MACB_NCR_TPF_SIZE 1
#define MACB_TZQ_OFFSET 12
#define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */
#define MACB_SPD_OFFSET 0
#define MACB_SPD_SIZE 1
#define MACB_FD_OFFSET 1
#define MACB_FD_SIZE 1
#define MACB_BIT_RATE_OFFSET 2
#define MACB_BIT_RATE_SIZE 1
#define MACB_JFRAME_OFFSET 3
#define MACB_JFRAME_SIZE 1
#define MACB_CAF_OFFSET 4
#define MACB_CAF_SIZE 1
#define MACB_NBC_OFFSET 5
#define MACB_NBC_SIZE 1
#define MACB_NCFGR_MTI_OFFSET 6
#define MACB_NCFGR_MTI_SIZE 1
#define MACB_UNI_OFFSET 7
#define MACB_UNI_SIZE 1
#define MACB_BIG_OFFSET 8
#define MACB_BIG_SIZE 1
#define MACB_EAE_OFFSET 9
#define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2
#define MACB_RTY_OFFSET 12
#define MACB_RTY_SIZE 1
#define MACB_PAE_OFFSET 13
#define MACB_PAE_SIZE 1
#define MACB_RBOF_OFFSET 14
#define MACB_RBOF_SIZE 2
#define MACB_RLCE_OFFSET 16
#define MACB_RLCE_SIZE 1
#define MACB_DRFCS_OFFSET 17
#define MACB_DRFCS_SIZE 1
#define MACB_EFRHD_OFFSET 18
#define MACB_EFRHD_SIZE 1
#define MACB_IRXFCS_OFFSET 19
#define MACB_IRXFCS_SIZE 1
/* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0
#define MACB_NSR_LINK_SIZE 1
#define MACB_MDIO_OFFSET 1
#define MACB_MDIO_SIZE 1
#define MACB_IDLE_OFFSET 2
#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
#define MACB_UBR_OFFSET 0
#define MACB_UBR_SIZE 1
#define MACB_COL_OFFSET 1
#define MACB_COL_SIZE 1
#define MACB_TSR_RLE_OFFSET 2
#define MACB_TSR_RLE_SIZE 1
#define MACB_TGO_OFFSET 3
#define MACB_TGO_SIZE 1
#define MACB_BEX_OFFSET 4
#define MACB_BEX_SIZE 1
#define MACB_COMP_OFFSET 5
#define MACB_COMP_SIZE 1
#define MACB_UND_OFFSET 6
#define MACB_UND_SIZE 1
/* Bitfields in RSR */
#define MACB_BNA_OFFSET 0
#define MACB_BNA_SIZE 1
#define MACB_REC_OFFSET 1
#define MACB_REC_SIZE 1
#define MACB_OVR_OFFSET 2
#define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */
#define MACB_MFD_OFFSET 0
#define MACB_MFD_SIZE 1
#define MACB_RCOMP_OFFSET 1
#define MACB_RCOMP_SIZE 1
#define MACB_RXUBR_OFFSET 2
#define MACB_RXUBR_SIZE 1
#define MACB_TXUBR_OFFSET 3
#define MACB_TXUBR_SIZE 1
#define MACB_ISR_TUND_OFFSET 4
#define MACB_ISR_TUND_SIZE 1
#define MACB_ISR_RLE_OFFSET 5
#define MACB_ISR_RLE_SIZE 1
#define MACB_TXERR_OFFSET 6
#define MACB_TXERR_SIZE 1
#define MACB_TCOMP_OFFSET 7
#define MACB_TCOMP_SIZE 1
#define MACB_ISR_LINK_OFFSET 9
#define MACB_ISR_LINK_SIZE 1
#define MACB_ISR_ROVR_OFFSET 10
#define MACB_ISR_ROVR_SIZE 1
#define MACB_HRESP_OFFSET 11
#define MACB_HRESP_SIZE 1
#define MACB_PFR_OFFSET 12
#define MACB_PFR_SIZE 1
#define MACB_PTZ_OFFSET 13
#define MACB_PTZ_SIZE 1
/* Bitfields in MAN */
#define MACB_DATA_OFFSET 0
#define MACB_DATA_SIZE 16
#define MACB_CODE_OFFSET 16
#define MACB_CODE_SIZE 2
#define MACB_REGA_OFFSET 18
#define MACB_REGA_SIZE 5
#define MACB_PHYA_OFFSET 23
#define MACB_PHYA_SIZE 5
#define MACB_RW_OFFSET 28
#define MACB_RW_SIZE 2
#define MACB_SOF_OFFSET 30
#define MACB_SOF_SIZE 2
/* Bitfields in USRIO */
#define MACB_MII_OFFSET 0
#define MACB_MII_SIZE 1
#define MACB_EAM_OFFSET 1
#define MACB_EAM_SIZE 1
#define MACB_TX_PAUSE_OFFSET 2
#define MACB_TX_PAUSE_SIZE 1
#define MACB_TX_PAUSE_ZERO_OFFSET 3
#define MACB_TX_PAUSE_ZERO_SIZE 1
/* Bitfields in USRIO (AT91) */
#define MACB_RMII_OFFSET 0
#define MACB_RMII_SIZE 1
#define MACB_CLKEN_OFFSET 1
#define MACB_CLKEN_SIZE 1
/* Bitfields in WOL */
#define MACB_IP_OFFSET 0
#define MACB_IP_SIZE 16
#define MACB_MAG_OFFSET 16
#define MACB_MAG_SIZE 1
#define MACB_ARP_OFFSET 17
#define MACB_ARP_SIZE 1
#define MACB_SA1_OFFSET 18
#define MACB_SA1_SIZE 1
#define MACB_WOL_MTI_OFFSET 19
#define MACB_WOL_MTI_SIZE 1
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
#define MACB_CLK_DIV32 2
#define MACB_CLK_DIV64 3
/* Constants for MAN register */
#define MACB_MAN_SOF 1
#define MACB_MAN_WRITE 1
#define MACB_MAN_READ 2
#define MACB_MAN_CODE 2
/* Bit manipulation macros */
#define MACB_BIT(name) \
(1 << MACB_##name##_OFFSET)
#define MACB_BF(name,value) \
(((value) & ((1 << MACB_##name##_SIZE) - 1)) \
<< MACB_##name##_OFFSET)
#define MACB_BFEXT(name,value)\
(((value) >> MACB_##name##_OFFSET) \
& ((1 << MACB_##name##_SIZE) - 1))
#define MACB_BFINS(name,value,old) \
(((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
<< MACB_##name##_OFFSET)) \
| MACB_BF(name,value))
/* Register access macros */
#define macb_readl(port,reg) \
readl((port)->regs + MACB_##reg)
#define macb_writel(port,reg,value) \
writel((value), (port)->regs + MACB_##reg)
#endif /* __DRIVERS_MACB_H__ */
|
1001-study-uboot
|
drivers/net/macb.h
|
C
|
gpl3
| 7,778
|
/*
* PLB2800 internal switch ethernet driver.
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/addrspace.h>
#define NUM_RX_DESC PKTBUFSRX
#define TOUT_LOOP 1000000
#define LONG_REF(addr) (*((volatile unsigned long*)addr))
#define CMAC_CRX_CTRL LONG_REF(0xb800c870)
#define CMAC_CTX_CTRL LONG_REF(0xb800c874)
#define SYS_MAC_ADDR_0 LONG_REF(0xb800c878)
#define SYS_MAC_ADDR_1 LONG_REF(0xb800c87c)
#define MIPS_H_MASK LONG_REF(0xB800C810)
#define MA_LEARN LONG_REF(0xb8008004)
#define DA_LOOKUP LONG_REF(0xb8008008)
#define CMAC_CRX_CTRL_PD 0x00000001
#define CMAC_CRX_CTRL_CG 0x00000002
#define CMAC_CRX_CTRL_PL_SHIFT 2
#define CMAC_CRIT 0x0
#define CMAC_NON_CRIT 0x1
#define MBOX_STAT_ID_SHF 28
#define MBOX_STAT_CP 0x80000000
#define MBOX_STAT_MB 0x00000001
#define EN_MA_LEARN 0x02000000
#define EN_DA_LKUP 0x01000000
#define MA_DEST_SHF 11
#define DA_DEST_SHF 11
#define DA_STATE_SHF 19
#define TSTAMP_MS 0x00000000
#define SW_H_MBOX4_MASK 0x08000000
#define SW_H_MBOX3_MASK 0x04000000
#define SW_H_MBOX2_MASK 0x02000000
#define SW_H_MBOX1_MASK 0x01000000
typedef volatile struct {
unsigned int stat;
unsigned int cmd;
unsigned int cnt;
unsigned int adr;
} mailbox_t;
#define MBOX_REG(mb) ((mailbox_t*)(0xb800c830+(mb<<4)))
typedef volatile struct {
unsigned int word0;
unsigned int word1;
unsigned int word2;
} mbhdr_t;
#define MBOX_MEM(mb) ((void*)(0xb800a000+((3-mb)<<11)))
static int plb2800_eth_init(struct eth_device *dev, bd_t * bis);
static int plb2800_eth_send(struct eth_device *dev, volatile void *packet,
int length);
static int plb2800_eth_recv(struct eth_device *dev);
static void plb2800_eth_halt(struct eth_device *dev);
static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr);
static unsigned char * plb2800_get_mac_addr(void);
static int rx_new;
static int mac_addr_set = 0;
int plb2800_eth_initialize(bd_t * bis)
{
struct eth_device *dev;
ulong temp;
#ifdef DEBUG
printf("Entered plb2800_eth_initialize()\n");
#endif
if (!(dev = (struct eth_device *) malloc (sizeof *dev)))
{
printf("Failed to allocate memory\n");
return -1;
}
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "PLB2800 Switch");
dev->init = plb2800_eth_init;
dev->halt = plb2800_eth_halt;
dev->send = plb2800_eth_send;
dev->recv = plb2800_eth_recv;
eth_register(dev);
/* bug fix */
*(ulong *)0xb800e800 = 0x838;
/* Set MBOX ownership */
temp = CMAC_CRIT << MBOX_STAT_ID_SHF;
MBOX_REG(0)->stat = temp;
MBOX_REG(1)->stat = temp;
temp = CMAC_NON_CRIT << MBOX_STAT_ID_SHF;
MBOX_REG(2)->stat = temp;
MBOX_REG(3)->stat = temp;
plb2800_set_mac_addr(dev, plb2800_get_mac_addr());
/* Disable all Mbox interrupt */
temp = MIPS_H_MASK;
temp &= ~ (SW_H_MBOX1_MASK | SW_H_MBOX2_MASK | SW_H_MBOX3_MASK | SW_H_MBOX4_MASK) ;
MIPS_H_MASK = temp;
#ifdef DEBUG
printf("Leaving plb2800_eth_initialize()\n");
#endif
return 0;
}
static int plb2800_eth_init(struct eth_device *dev, bd_t * bis)
{
#ifdef DEBUG
printf("Entering plb2800_eth_init()\n");
#endif
plb2800_set_mac_addr(dev, dev->enetaddr);
rx_new = 0;
#ifdef DEBUG
printf("Leaving plb2800_eth_init()\n");
#endif
return 0;
}
static int plb2800_eth_send(struct eth_device *dev, volatile void *packet,
int length)
{
int i;
int res = -1;
u32 temp;
mailbox_t * mb = MBOX_REG(0);
char * mem = MBOX_MEM(0);
#ifdef DEBUG
printf("Entered plb2800_eth_send()\n");
#endif
if (length <= 0)
{
printf ("%s: bad packet size: %d\n", dev->name, length);
goto Done;
}
if (length < 64)
{
length = 64;
}
temp = CMAC_CRX_CTRL_CG | ((length + 4) << CMAC_CRX_CTRL_PL_SHIFT);
#ifdef DEBUG
printf("0 mb->stat = 0x%x\n", mb->stat);
#endif
for(i = 0; mb->stat & (MBOX_STAT_CP | MBOX_STAT_MB); i++)
{
if (i >= TOUT_LOOP)
{
printf("%s: tx buffer not ready\n", dev->name);
printf("1 mb->stat = 0x%x\n", mb->stat);
goto Done;
}
}
/* For some strange reason, memcpy doesn't work, here!
*/
do
{
int words = (length >> 2) + 1;
unsigned int* dst = (unsigned int*)(mem);
unsigned int* src = (unsigned int*)(packet);
for (i = 0; i < words; i++)
{
*dst = *src;
dst++;
src++;
};
} while(0);
CMAC_CRX_CTRL = temp;
mb->cmd = MBOX_STAT_CP;
#ifdef DEBUG
printf("2 mb->stat = 0x%x\n", mb->stat);
#endif
res = length;
Done:
#ifdef DEBUG
printf("Leaving plb2800_eth_send()\n");
#endif
return res;
}
static int plb2800_eth_recv(struct eth_device *dev)
{
int length = 0;
mailbox_t * mbox = MBOX_REG(3);
unsigned char * hdr = MBOX_MEM(3);
unsigned int stat;
#ifdef DEBUG
printf("Entered plb2800_eth_recv()\n");
#endif
for (;;)
{
stat = mbox->stat;
if (!(stat & MBOX_STAT_CP))
{
break;
}
length = ((*(hdr + 6) & 0x3f) << 8) + *(hdr + 7);
memcpy((void *)NetRxPackets[rx_new], hdr + 12, length);
stat &= ~MBOX_STAT_CP;
mbox->stat = stat;
#ifdef DEBUG
{
int i;
for (i=0;i<length - 4;i++)
{
if (i % 16 == 0) printf("\n%04x: ", i);
printf("%02X ", NetRxPackets[rx_new][i]);
}
printf("\n");
}
#endif
if (length)
{
#ifdef DEBUG
printf("Received %d bytes\n", length);
#endif
NetReceive((void*)(NetRxPackets[rx_new]),
length - 4);
}
else
{
#if 1
printf("Zero length!!!\n");
#endif
}
rx_new = (rx_new + 1) % NUM_RX_DESC;
}
#ifdef DEBUG
printf("Leaving plb2800_eth_recv()\n");
#endif
return length;
}
static void plb2800_eth_halt(struct eth_device *dev)
{
#ifdef DEBUG
printf("Entered plb2800_eth_halt()\n");
#endif
#ifdef DEBUG
printf("Leaving plb2800_eth_halt()\n");
#endif
}
static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr)
{
char packet[60];
ulong temp;
int ix;
if (mac_addr_set ||
NULL == addr || memcmp(addr, "\0\0\0\0\0\0", 6) == 0)
{
return;
}
/* send one packet through CPU port
* in order to learn system MAC address
*/
/* Set DA_LOOKUP register */
temp = EN_MA_LEARN | (0 << DA_STATE_SHF) | (63 << DA_DEST_SHF);
DA_LOOKUP = temp;
/* Set MA_LEARN register */
temp = 50 << MA_DEST_SHF; /* static entry */
MA_LEARN = temp;
/* set destination address */
for (ix=0;ix<6;ix++)
packet[ix] = 0xff;
/* set source address = system MAC address */
for (ix=0;ix<6;ix++)
packet[6+ix] = addr[ix];
/* set type field */
packet[12]=0xaa;
packet[13]=0x55;
/* set data field */
for(ix=14;ix<60;ix++)
packet[ix] = 0x00;
#ifdef DEBUG
for (ix=0;ix<6;ix++)
printf("mac_addr[%d]=%02X\n", ix, (unsigned char)packet[6+ix]);
#endif
/* set one packet */
plb2800_eth_send(dev, packet, sizeof(packet));
/* delay for a while */
for(ix=0;ix<65535;ix++)
temp = ~temp;
/* Set CMAC_CTX_CTRL register */
temp = TSTAMP_MS; /* no autocast */
CMAC_CTX_CTRL = temp;
/* Set DA_LOOKUP register */
temp = EN_DA_LKUP;
DA_LOOKUP = temp;
mac_addr_set = 1;
}
static unsigned char * plb2800_get_mac_addr(void)
{
static unsigned char addr[6];
char *tmp, *end;
int i;
tmp = getenv ("ethaddr");
if (NULL == tmp) return NULL;
for (i=0; i<6; i++) {
addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
if (tmp)
tmp = (*end) ? end+1 : end;
}
return addr;
}
|
1001-study-uboot
|
drivers/net/plb2800_eth.c
|
C
|
gpl3
| 8,219
|
/*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <net.h>
#include <netdev.h>
#ifdef CONFIG_MCF547x_8x
#include <asm/fsl_mcdmafec.h>
#else
#include <asm/fec.h>
#endif
#include <asm/immap.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_CMD_NET)
#undef MII_DEBUG
#undef ET_DEBUG
/*extern int fecpin_setclear(struct eth_device *dev, int setclear);*/
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
(REG & 0x1f) << 18))
#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
(REG & 0x1f) << 18) | (VAL & 0xffff))
#ifndef CONFIG_SYS_UNSPEC_PHYID
# define CONFIG_SYS_UNSPEC_PHYID 0
#endif
#ifndef CONFIG_SYS_UNSPEC_STRID
# define CONFIG_SYS_UNSPEC_STRID 0
#endif
#ifdef CONFIG_MCF547x_8x
typedef struct fec_info_dma FEC_INFO_T;
#define FEC_T fecdma_t
#else
typedef struct fec_info_s FEC_INFO_T;
#define FEC_T fec_t
#endif
typedef struct phy_info_struct {
u32 phyid;
char *strid;
} phy_info_t;
phy_info_t phyinfo[] = {
{0x0022561B, "AMD79C784VC"}, /* AMD 79C784VC */
{0x00406322, "BCM5222"}, /* Broadcom 5222 */
{0x02a80150, "Intel82555"}, /* Intel 82555 */
{0x0016f870, "LSI80225"}, /* LSI 80225 */
{0x0016f880, "LSI80225/B"}, /* LSI 80225/B */
{0x78100000, "LXT970"}, /* LXT970 */
{0x001378e0, "LXT971"}, /* LXT971 and 972 */
{0x00221619, "KS8721BL"}, /* Micrel KS8721BL/SL */
{0x00221512, "KSZ8041NL"}, /* Micrel KSZ8041NL */
{0x20005CE1, "N83640"}, /* National 83640 */
{0x20005C90, "N83848"}, /* National 83848 */
{0x20005CA2, "N83849"}, /* National 83849 */
{0x01814400, "QS6612"}, /* QS6612 */
#if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID)
{CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID},
#endif
{0, 0}
};
/*
* mii_init -- Initialize the MII for MII command without ethernet
* This function is a subset of eth_init
*/
void mii_reset(FEC_INFO_T *info)
{
volatile FEC_T *fecp = (FEC_T *) (info->miibase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY)
printf("FEC_RESET_DELAY timeout\n");
}
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
FEC_INFO_T *info;
volatile FEC_T *ep;
struct eth_device *dev;
uint mii_reply;
int j = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
ep = (FEC_T *) info->miibase;
ep->mmfr = mii_cmd; /* command to phy */
/* wait for mii complete */
while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("MII not complete\n");
return -1;
}
mii_reply = ep->mmfr; /* result from phy */
ep->eir = FEC_EIR_MII; /* clear MII complete */
#ifdef ET_DEBUG
printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
__FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
#endif
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
FEC_INFO_T *info = dev->priv;
int phyaddr, pass;
uint phyno, phytype;
int i, found = 0;
if (info->phyname_init)
return info->phy_addr;
phyaddr = -1; /* didn't find a PHY yet */
for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
if (pass > 1) {
/* PHY may need more time to recover from reset.
* The LXT970 needs 50ms typical, no maximum is
* specified, so wait 10ms before try again.
* With 11 passes this gives it 100ms to wake up.
*/
udelay(10000); /* wait 10ms */
}
for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
phytype = mii_send(mk_mii_read(phyno, MII_PHYSID1));
#ifdef ET_DEBUG
printf("PHY type 0x%x pass %d type\n", phytype, pass);
#endif
if (phytype == 0xffff)
continue;
phyaddr = phyno;
phytype <<= 16;
phytype |=
mii_send(mk_mii_read(phyno, MII_PHYSID2));
#ifdef ET_DEBUG
printf("PHY @ 0x%x pass %d\n", phyno, pass);
#endif
for (i = 0; (i < (sizeof(phyinfo) / sizeof(phy_info_t)))
&& (phyinfo[i].phyid != 0); i++) {
if (phyinfo[i].phyid == phytype) {
#ifdef ET_DEBUG
printf("phyid %x - %s\n",
phyinfo[i].phyid,
phyinfo[i].strid);
#endif
strcpy(info->phy_name, phyinfo[i].strid);
info->phyname_init = 1;
found = 1;
break;
}
}
if (!found) {
#ifdef ET_DEBUG
printf("0x%08x\n", phytype);
#endif
strcpy(info->phy_name, "unknown");
info->phyname_init = 1;
break;
}
}
}
if (phyaddr < 0)
printf("No PHY device found.\n");
return phyaddr;
}
#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
FEC_INFO_T *info;
volatile FEC_T *fecp;
struct eth_device *dev;
int miispd = 0, i = 0;
u16 status = 0;
u16 linkgood = 0;
/* retrieve from register structure */
dev = eth_get_dev();
info = dev->priv;
fecp = (FEC_T *) info->miibase;
fecpin_setclear(dev, 1);
mii_reset(info);
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set MII speed */
miispd = (gd->bus_clk / 1000000) / 5;
fecp->mscr = miispd << 1;
info->phy_addr = mii_discover_phy(dev);
while (i < MCFFEC_TOUT_LOOP) {
status = 0;
i++;
/* Read PHY control register */
miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status);
/* If phy set to autonegotiate, wait for autonegotiation done,
* if phy is not autonegotiating, just wait for link up.
*/
if ((status & BMCR_ANENABLE) == BMCR_ANENABLE) {
linkgood = (BMSR_ANEGCOMPLETE | BMSR_LSTATUS);
} else {
linkgood = BMSR_LSTATUS;
}
/* Read PHY status register */
miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status);
if ((status & linkgood) == linkgood)
break;
udelay(1);
}
if (i >= MCFFEC_TOUT_LOOP) {
printf("Link UP timeout\n");
}
/* adapt to the duplex and speed settings of the phy */
info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
}
/*
* Read and write a MII PHY register, routines used by MII Utilities
*
* FIXME: These routines are expected to return 0 on success, but mii_send
* does _not_ return an error code. Maybe 0xFFFF means error, i.e.
* no PHY connected...
* For now always return 0.
* FIXME: These routines only work after calling eth_init() at least once!
* Otherwise they hang in mii_send() !!! Sorry!
*/
int mcffec_miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
unsigned short *value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_read(addr, reg));
*value = rdreg;
#ifdef MII_DEBUG
printf("0x%04x\n", *value);
#endif
return 0;
}
int mcffec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
short rdreg; /* register working value */
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
rdreg = mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
#endif
return 0;
}
#endif /* CONFIG_CMD_NET */
|
1001-study-uboot
|
drivers/net/mcfmii.c
|
C
|
gpl3
| 8,328
|
/***********************************************************************
*
* Copyright (c) 2005 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Description:
* Ethernet interface for Tundra TSI108 bridge chip
*
***********************************************************************/
#include <config.h>
#if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2)
#error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2"
#endif
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/cache.h>
#ifdef DEBUG
#define TSI108_ETH_DEBUG 7
#else
#define TSI108_ETH_DEBUG 0
#endif
#if TSI108_ETH_DEBUG > 0
#define debug_lev(lev, fmt, args...) \
if (lev <= TSI108_ETH_DEBUG) \
printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
#else
#define debug_lev(lev, fmt, args...) do{}while(0)
#endif
#define RX_PRINT_ERRORS
#define TX_PRINT_ERRORS
#define ETH_BASE (CONFIG_SYS_TSI108_CSR_BASE + 0x6000)
#define ETH_PORT_OFFSET 0x400
#define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset))))
#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000)
#define MAC_CONFIG_1_TX_ENABLE (0x00000001)
#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002)
#define MAC_CONFIG_1_RX_ENABLE (0x00000004)
#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008)
#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010)
#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020)
#define MAC_CONFIG_1_LOOP_BACK (0x00000100)
#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000)
#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000)
#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000)
#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000)
#define MAC_CONFIG_1_SIM_RESET (0x40000000)
#define MAC_CONFIG_1_SOFT_RESET (0x80000000)
#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004)
#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001)
#define MAC_CONFIG_2_CRC_ENABLE (0x00000002)
#define MAC_CONFIG_2_PAD_CRC (0x00000004)
#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010)
#define MAC_CONFIG_2_HUGE_FRAME (0x00000020)
#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8)
#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12)
#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */
#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */
#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010)
#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020)
#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7)
#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010)
#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020)
#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000)
#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024)
#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001)
#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002)
#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028)
#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c)
#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030)
#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034)
#define MII_MGMT_INDICATORS_BUSY (0x00000001)
#define MII_MGMT_INDICATORS_SCAN (0x00000002)
#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004)
#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c)
#define INTERFACE_STATUS_LINK_FAIL (0x00000008)
#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200)
#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040)
#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044)
#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200)
#define PORT_CONTROL_PRI (0x00000001)
#define PORT_CONTROL_BPT (0x00010000)
#define PORT_CONTROL_SPD (0x00040000)
#define PORT_CONTROL_RBC (0x00080000)
#define PORT_CONTROL_PRB (0x00200000)
#define PORT_CONTROL_DIS (0x00400000)
#define PORT_CONTROL_TBI (0x00800000)
#define PORT_CONTROL_STE (0x10000000)
#define PORT_CONTROL_ZOR (0x20000000)
#define PORT_CONTROL_CLR (0x40000000)
#define PORT_CONTROL_SRT (0x80000000)
#define reg_TX_CONFIG(base) __REG32(base, 0x00000220)
#define TX_CONFIG_START_Q (0x00000003)
#define TX_CONFIG_EHP (0x00400000)
#define TX_CONFIG_CHP (0x00800000)
#define TX_CONFIG_RST (0x80000000)
#define reg_TX_CONTROL(base) __REG32(base, 0x00000224)
#define TX_CONTROL_GO (0x00008000)
#define TX_CONTROL_MP (0x01000000)
#define TX_CONTROL_EAI (0x20000000)
#define TX_CONTROL_ABT (0x40000000)
#define TX_CONTROL_EII (0x80000000)
#define reg_TX_STATUS(base) __REG32(base, 0x00000228)
#define TX_STATUS_QUEUE_USABLE (0x0000000f)
#define TX_STATUS_CURR_Q (0x00000300)
#define TX_STATUS_ACT (0x00008000)
#define TX_STATUS_QUEUE_IDLE (0x000f0000)
#define TX_STATUS_EOQ_PENDING (0x0f000000)
#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c)
#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f)
#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00)
#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230)
#define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270)
#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000)
#define TX_DIAGNOSTIC_ADDR_AI (0x80000000)
#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274)
#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278)
#define TX_ERROR_STATUS (0x00000278)
#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f)
#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010)
#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020)
#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040)
#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080)
#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00)
#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000)
#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000)
#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000)
#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000)
#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000)
#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000)
#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000)
#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000)
#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000)
#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000)
#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000)
#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000)
#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000)
#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000)
#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280)
#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
#define TX_QUEUE_0_CONFIG_BSWP (0x00000400)
#define TX_QUEUE_0_CONFIG_WSWP (0x00000800)
#define TX_QUEUE_0_CONFIG_AM (0x00004000)
#define TX_QUEUE_0_CONFIG_GVI (0x00008000)
#define TX_QUEUE_0_CONFIG_EEI (0x00010000)
#define TX_QUEUE_0_CONFIG_ELI (0x00020000)
#define TX_QUEUE_0_CONFIG_ENI (0x00040000)
#define TX_QUEUE_0_CONFIG_ESI (0x00080000)
#define TX_QUEUE_0_CONFIG_EDI (0x00100000)
#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284)
#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
#define OCN_PORT_HLP 0 /* HLP Interface */
#define OCN_PORT_PCI_X 1 /* PCI-X Interface */
#define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */
#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */
#define OCN_PORT_MEMORY 4 /* Memory Controller */
#define OCN_PORT_DMA 5 /* DMA Controller */
#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */
#define OCN_PORT_PRINT 7 /* Print Engine Interface */
#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288)
#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c)
#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
#define reg_RX_CONFIG(base) __REG32(base, 0x00000320)
#define RX_CONFIG_DEF_Q (0x00000003)
#define RX_CONFIG_EMF (0x00000100)
#define RX_CONFIG_EUF (0x00000200)
#define RX_CONFIG_BFE (0x00000400)
#define RX_CONFIG_MFE (0x00000800)
#define RX_CONFIG_UFE (0x00001000)
#define RX_CONFIG_SE (0x00002000)
#define RX_CONFIG_ABF (0x00200000)
#define RX_CONFIG_APE (0x00400000)
#define RX_CONFIG_CHP (0x00800000)
#define RX_CONFIG_RST (0x80000000)
#define reg_RX_CONTROL(base) __REG32(base, 0x00000324)
#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f)
#define GE_E0_RX_CONTROL_GO (0x00008000)
#define GE_E0_RX_CONTROL_EAI (0x20000000)
#define GE_E0_RX_CONTROL_ABT (0x40000000)
#define GE_E0_RX_CONTROL_EII (0x80000000)
#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c)
#define RX_EXTENDED_STATUS (0x0000032c)
#define RX_EXTENDED_STATUS_EOQ (0x0000000f)
#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001)
#define RX_EXTENDED_STATUS_EOF (0x00000f00)
#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330)
#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370)
#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000)
#define RX_DIAGNOSTIC_ADDR_AI (0x80000000)
#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374)
#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380)
#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
#define RX_QUEUE_0_CONFIG_BSWP (0x00000400)
#define RX_QUEUE_0_CONFIG_WSWP (0x00000800)
#define RX_QUEUE_0_CONFIG_AM (0x00004000)
#define RX_QUEUE_0_CONFIG_EEI (0x00010000)
#define RX_QUEUE_0_CONFIG_ELI (0x00020000)
#define RX_QUEUE_0_CONFIG_ENI (0x00040000)
#define RX_QUEUE_0_CONFIG_ESI (0x00080000)
#define RX_QUEUE_0_CONFIG_EDI (0x00100000)
#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384)
#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388)
#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c)
#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
/*
* PHY register definitions
*/
/* the first 15 PHY registers are standard. */
#define PHY_CTRL_REG 0 /* Control Register */
#define PHY_STATUS_REG 1 /* Status Regiser */
#define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */
#define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */
#define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */
#define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */
#define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */
#define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */
#define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */
#define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */
#define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */
#define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */
/*
* PHY Register bit masks.
*/
#define PHY_CTRL_RESET (1 << 15)
#define PHY_CTRL_LOOPBACK (1 << 14)
#define PHY_CTRL_SPEED0 (1 << 13)
#define PHY_CTRL_AN_EN (1 << 12)
#define PHY_CTRL_PWR_DN (1 << 11)
#define PHY_CTRL_ISOLATE (1 << 10)
#define PHY_CTRL_RESTART_AN (1 << 9)
#define PHY_CTRL_FULL_DUPLEX (1 << 8)
#define PHY_CTRL_CT_EN (1 << 7)
#define PHY_CTRL_SPEED1 (1 << 6)
#define PHY_STAT_100BASE_T4 (1 << 15)
#define PHY_STAT_100BASE_X_FD (1 << 14)
#define PHY_STAT_100BASE_X_HD (1 << 13)
#define PHY_STAT_10BASE_T_FD (1 << 12)
#define PHY_STAT_10BASE_T_HD (1 << 11)
#define PHY_STAT_100BASE_T2_FD (1 << 10)
#define PHY_STAT_100BASE_T2_HD (1 << 9)
#define PHY_STAT_EXT_STAT (1 << 8)
#define PHY_STAT_RESERVED (1 << 7)
#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */
#define PHY_STAT_AN_COMPLETE (1 << 5)
#define PHY_STAT_REM_FAULT (1 << 4)
#define PHY_STAT_AN_CAP (1 << 3)
#define PHY_STAT_LINK_UP (1 << 2)
#define PHY_STAT_JABBER (1 << 1)
#define PHY_STAT_EXT_CAP (1 << 0)
#define TBI_CONTROL_2 0x11
#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001
#define TBI_CONTROL_2_ENABLE_WRAP 0x0002
#define TBI_CONTROL_2_G_MII_MODE 0x0010
#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020
#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100
#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000
#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000
#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000
#define TBI_CONTROL_2_SOFT_RESET 0x8000
/* marvel specific */
#define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */
#define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */
#define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */
/*
* MARVELL 88E1111 PHY register bit masks
*/
/* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */
#define SPEC_STAT_SPEED_MASK (3 << 14)
#define SPEC_STAT_FULL_DUP (1 << 13)
#define SPEC_STAT_PAGE_RCVD (1 << 12)
#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */
#define SPEC_STAT_LINK_UP (1 << 10)
#define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */
#define SPEC_STAT_MDIX (1 << 6)
#define SPEC_STAT_POLARITY (1 << 1)
#define SPEC_STAT_JABBER (1 << 0)
#define SPEED_1000 (2 << 14)
#define SPEED_100 (1 << 14)
#define SPEED_10 (0 << 14)
#define TBI_ADDR 0x1E /* Ten Bit Interface address */
/* negotiated link parameters */
#define LINK_SPEED_UNKNOWN 0
#define LINK_SPEED_10 1
#define LINK_SPEED_100 2
#define LINK_SPEED_1000 3
#define LINK_DUPLEX_UNKNOWN 0
#define LINK_DUPLEX_HALF 1
#define LINK_DUPLEX_FULL 2
static unsigned int phy_address[] = { 8, 9 };
#define vuint32 volatile u32
/* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte)
* This structure is accessed by the ethernet DMA engine which means it
* MUST be in LITTLE ENDIAN format */
struct dma_descriptor {
vuint32 start_addr0; /* buffer address, least significant bytes. */
vuint32 start_addr1; /* buffer address, most significant bytes. */
vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */
vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */
vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */
vuint32 config_status; /* Configuration/Status. */
vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */
vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */
};
/* last next descriptor address flag */
#define DMA_DESCR_LAST (1 << 31)
/* TX DMA descriptor config status bits */
#define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */
#define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */
#define DMA_DESCR_TX_PFVLAN (1 << 2)
#define DMA_DESCR_TX_HUGE (1 << 3)
#define DMA_DESCR_TX_PAD (1 << 4)
#define DMA_DESCR_TX_CRC (1 << 5)
#define DMA_DESCR_TX_DESCR_INT (1 << 14)
#define DMA_DESCR_TX_RETRY_COUNT 0x000F0000
#define DMA_DESCR_TX_ONE_COLLISION (1 << 20)
#define DMA_DESCR_TX_LATE_COLLISION (1 << 24)
#define DMA_DESCR_TX_UNDERRUN (1 << 25)
#define DMA_DESCR_TX_RETRY_LIMIT (1 << 26)
#define DMA_DESCR_TX_OK (1 << 30)
#define DMA_DESCR_TX_OWNER (1 << 31)
/* RX DMA descriptor status bits */
#define DMA_DESCR_RX_EOF (1 << 0)
#define DMA_DESCR_RX_SOF (1 << 1)
#define DMA_DESCR_RX_VTF (1 << 2)
#define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3)
#define DMA_DESCR_RX_SHORT_FRAME (1 << 4)
#define DMA_DESCR_RX_HASH_MATCH (1 << 7)
#define DMA_DESCR_RX_BAD_FRAME (1 << 8)
#define DMA_DESCR_RX_OVERRUN (1 << 9)
#define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11)
#define DMA_DESCR_RX_CRC_ERROR (1 << 12)
#define DMA_DESCR_RX_DESCR_INT (1 << 13)
#define DMA_DESCR_RX_OWNER (1 << 15)
#define RX_BUFFER_SIZE PKTSIZE
#define NUM_RX_DESC PKTBUFSRX
static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32)));
static struct dma_descriptor rx_descr_array[NUM_RX_DESC]
__attribute__ ((aligned(32)));
static struct dma_descriptor *rx_descr_current;
static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis);
static int tsi108_eth_send (struct eth_device *dev,
volatile void *packet, int length);
static int tsi108_eth_recv (struct eth_device *dev);
static void tsi108_eth_halt (struct eth_device *dev);
static unsigned int read_phy (unsigned int base,
unsigned int phy_addr, unsigned int phy_reg);
static void write_phy (unsigned int base,
unsigned int phy_addr,
unsigned int phy_reg, unsigned int phy_data);
#if TSI108_ETH_DEBUG > 100
/*
* print phy debug infomation
*/
static void dump_phy_regs (unsigned int phy_addr)
{
int i;
printf ("PHY %d registers\n", phy_addr);
for (i = 0; i <= 30; i++) {
printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i));
}
printf ("\n");
}
#else
#define dump_phy_regs(base) do{}while(0)
#endif
#if TSI108_ETH_DEBUG > 100
/*
* print debug infomation
*/
static void tx_diag_regs (unsigned int base)
{
int i;
unsigned long dummy;
printf ("TX diagnostics registers\n");
reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI;
udelay (1000);
dummy = reg_TX_DIAGNOSTIC_DATA(base);
for (i = 0x00; i <= 0x05; i++) {
udelay (1000);
printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
}
reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI;
udelay (1000);
dummy = reg_TX_DIAGNOSTIC_DATA(base);
for (i = 0x40; i <= 0x47; i++) {
udelay (1000);
printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
}
printf ("\n");
}
#else
#define tx_diag_regs(base) do{}while(0)
#endif
#if TSI108_ETH_DEBUG > 100
/*
* print debug infomation
*/
static void rx_diag_regs (unsigned int base)
{
int i;
unsigned long dummy;
printf ("RX diagnostics registers\n");
reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI;
udelay (1000);
dummy = reg_RX_DIAGNOSTIC_DATA(base);
for (i = 0x00; i <= 0x05; i++) {
udelay (1000);
printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
}
reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI;
udelay (1000);
dummy = reg_RX_DIAGNOSTIC_DATA(base);
for (i = 0x08; i <= 0x0a; i++) {
udelay (1000);
printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
}
printf ("\n");
}
#else
#define rx_diag_regs(base) do{}while(0)
#endif
#if TSI108_ETH_DEBUG > 100
/*
* print debug infomation
*/
static void debug_mii_regs (unsigned int base)
{
printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base));
printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base));
printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base));
printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base));
printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base));
printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base));
printf ("\n");
}
#else
#define debug_mii_regs(base) do{}while(0)
#endif
/*
* Wait until the phy bus is non-busy
*/
static void phy_wait (unsigned int base, unsigned int condition)
{
int timeout;
timeout = 0;
while (reg_MII_MGMT_INDICATORS(base) & condition) {
udelay (10);
if (++timeout > 10000) {
printf ("ERROR: timeout waiting for phy bus (%d)\n",
condition);
break;
}
}
}
/*
* read phy register
*/
static unsigned int read_phy (unsigned int base,
unsigned int phy_addr, unsigned int phy_reg)
{
unsigned int value;
phy_wait (base, MII_MGMT_INDICATORS_BUSY);
reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
/* Ensure that the Read Cycle bit is cleared prior to next read cycle */
reg_MII_MGMT_COMMAND(base) = 0;
/* start the read */
reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE;
/* wait for the read to complete */
phy_wait (base,
MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY);
value = reg_MII_MGMT_STATUS(base);
reg_MII_MGMT_COMMAND(base) = 0;
return value;
}
/*
* write phy register
*/
static void write_phy (unsigned int base,
unsigned int phy_addr,
unsigned int phy_reg, unsigned int phy_data)
{
phy_wait (base, MII_MGMT_INDICATORS_BUSY);
reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
/* Ensure that the Read Cycle bit is cleared prior to next cycle */
reg_MII_MGMT_COMMAND(base) = 0;
/* start the write */
reg_MII_MGMT_CONTROL(base) = phy_data;
}
/*
* configure the marvell 88e1111 phy
*/
static int marvell_88e_phy_config (struct eth_device *dev, int *speed,
int *duplex)
{
unsigned long base;
unsigned long phy_addr;
unsigned int phy_status;
unsigned int phy_spec_status;
int timeout;
int phy_speed;
int phy_duplex;
unsigned int value;
phy_speed = LINK_SPEED_UNKNOWN;
phy_duplex = LINK_DUPLEX_UNKNOWN;
base = dev->iobase;
phy_addr = (unsigned long)dev->priv;
/* Take the PHY out of reset. */
write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET);
/* Wait for the reset process to complete. */
udelay (10);
timeout = 0;
while ((phy_status =
read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) {
udelay (10);
if (++timeout > 10000) {
printf ("ERROR: timeout waiting for phy reset\n");
break;
}
}
/* TBI Configuration. */
write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE |
TBI_CONTROL_2_RECEIVE_CLOCK_SELECT);
/* Wait for the link to be established. */
timeout = 0;
do {
udelay (20000);
phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG);
if (++timeout > 100) {
debug_lev(1, "ERROR: unable to establish link!!!\n");
break;
}
} while ((phy_status & PHY_STAT_LINK_UP) == 0);
if ((phy_status & PHY_STAT_LINK_UP) == 0)
return 0;
value = 0;
phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
if (phy_spec_status & SPEC_STAT_RESOLVED) {
switch (phy_spec_status & SPEC_STAT_SPEED_MASK) {
case SPEED_1000:
phy_speed = LINK_SPEED_1000;
value |= PHY_CTRL_SPEED1;
break;
case SPEED_100:
phy_speed = LINK_SPEED_100;
value |= PHY_CTRL_SPEED0;
break;
case SPEED_10:
phy_speed = LINK_SPEED_10;
break;
}
if (phy_spec_status & SPEC_STAT_FULL_DUP) {
phy_duplex = LINK_DUPLEX_FULL;
value |= PHY_CTRL_FULL_DUPLEX;
} else
phy_duplex = LINK_DUPLEX_HALF;
}
/* set TBI speed */
write_phy (base, TBI_ADDR, PHY_CTRL_REG, value);
write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
#if TSI108_ETH_DEBUG > 0
printf ("%s link is up", dev->name);
phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
if (phy_spec_status & SPEC_STAT_RESOLVED) {
switch (phy_speed) {
case LINK_SPEED_1000:
printf (", 1000 Mbps");
break;
case LINK_SPEED_100:
printf (", 100 Mbps");
break;
case LINK_SPEED_10:
printf (", 10 Mbps");
break;
}
if (phy_duplex == LINK_DUPLEX_FULL)
printf (", Full duplex");
else
printf (", Half duplex");
}
printf ("\n");
#endif
dump_phy_regs (TBI_ADDR);
if (speed)
*speed = phy_speed;
if (duplex)
*duplex = phy_duplex;
return 1;
}
/*
* External interface
*
* register the tsi108 ethernet controllers with the multi-ethernet system
*/
int tsi108_eth_initialize (bd_t * bis)
{
struct eth_device *dev;
int index;
for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) {
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev) {
printf("tsi108: Can not allocate memory\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "TSI108_eth%d", index);
dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET);
dev->priv = (void *)(phy_address[index]);
dev->init = tsi108_eth_probe;
dev->halt = tsi108_eth_halt;
dev->send = tsi108_eth_send;
dev->recv = tsi108_eth_recv;
eth_register(dev);
}
return index;
}
/*
* probe for and initialize a single ethernet interface
*/
static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
{
unsigned long base;
unsigned long value;
int index;
struct dma_descriptor *tx_descr;
struct dma_descriptor *rx_descr;
int speed;
int duplex;
base = dev->iobase;
reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT;
/* Bring DMA/FIFO out of reset. */
reg_TX_CONFIG(base) = 0x00000000;
reg_RX_CONFIG(base) = 0x00000000;
reg_TX_THRESHOLDS(base) = (192 << 16) | 192;
reg_RX_THRESHOLDS(base) = (192 << 16) | 112;
/* Bring MAC out of reset. */
reg_MAC_CONFIG_1(base) = 0x00000000;
/* DMA MAC configuration. */
reg_MAC_CONFIG_1(base) =
MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE;
reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE;
reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE;
/* Note: Early tsi108 manual did not have correct byte order
* for the station address.*/
reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) |
(dev->enetaddr[4] << 16) |
(dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0);
reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) |
(dev->enetaddr[0] << 16);
if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
return -1;
value =
MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
MAC_CONFIG_2_CRC_ENABLE;
if (speed == LINK_SPEED_1000)
value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE);
else {
value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE);
reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD;
}
if (duplex == LINK_DUPLEX_FULL) {
value |= MAC_CONFIG_2_FULL_DUPLEX;
reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT;
} else
reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT;
reg_MAC_CONFIG_2(base) = value;
reg_RX_CONFIG(base) = RX_CONFIG_SE;
reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
/* initialize the RX DMA descriptors */
rx_descr = &rx_descr_array[0];
rx_descr_current = rx_descr;
for (index = 0; index < NUM_RX_DESC; index++) {
/* make sure the receive buffers are not in cache */
invalidate_dcache_range((unsigned long)NetRxPackets[index],
(unsigned long)NetRxPackets[index] +
RX_BUFFER_SIZE);
rx_descr->start_addr0 =
cpu_to_le32((vuint32) NetRxPackets[index]);
rx_descr->start_addr1 = 0;
rx_descr->next_descr_addr0 =
cpu_to_le32((vuint32) (rx_descr + 1));
rx_descr->next_descr_addr1 = 0;
rx_descr->vlan_byte_count = 0;
rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) |
DMA_DESCR_RX_OWNER);
rx_descr++;
}
rx_descr--;
rx_descr->next_descr_addr0 = 0;
rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
/* Push the descriptors to RAM so the ethernet DMA can see them */
invalidate_dcache_range((unsigned long)rx_descr_array,
(unsigned long)rx_descr_array +
sizeof(rx_descr_array));
/* enable RX queue */
reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01;
reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current;
/* enable receive DMA */
reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
/* initialize the TX DMA descriptor */
tx_descr = &tx_descriptor;
tx_descr->start_addr0 = 0;
tx_descr->start_addr1 = 0;
tx_descr->next_descr_addr0 = 0;
tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
tx_descr->vlan_byte_count = 0;
tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK |
DMA_DESCR_TX_SOF |
DMA_DESCR_TX_EOF);
/* enable TX queue */
reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01;
return 0;
}
/*
* send a packet
*/
static int tsi108_eth_send (struct eth_device *dev,
volatile void *packet, int length)
{
unsigned long base;
int timeout;
struct dma_descriptor *tx_descr;
unsigned long status;
base = dev->iobase;
tx_descr = &tx_descriptor;
/* Wait until the last packet has been transmitted. */
timeout = 0;
do {
/* make sure we see the changes made by the DMA engine */
invalidate_dcache_range((unsigned long)tx_descr,
(unsigned long)tx_descr +
sizeof(struct dma_descriptor));
if (timeout != 0)
udelay (15);
if (++timeout > 10000) {
tx_diag_regs(base);
debug_lev(1,
"ERROR: timeout waiting for last transmit packet to be sent\n");
return 0;
}
} while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER));
status = le32_to_cpu(tx_descr->config_status);
if ((status & DMA_DESCR_TX_OK) == 0) {
#ifdef TX_PRINT_ERRORS
printf ("TX packet error: 0x%08lx\n %s%s%s%s\n", status,
status & DMA_DESCR_TX_OK ? "tx error, " : "",
status & DMA_DESCR_TX_RETRY_LIMIT ?
"retry limit reached, " : "",
status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "",
status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, "
: "");
#endif
}
debug_lev (9, "sending packet %d\n", length);
tx_descr->start_addr0 = cpu_to_le32((vuint32) packet);
tx_descr->start_addr1 = 0;
tx_descr->next_descr_addr0 = 0;
tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
tx_descr->vlan_byte_count = cpu_to_le32(length);
tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER |
DMA_DESCR_TX_CRC |
DMA_DESCR_TX_PAD |
DMA_DESCR_TX_SOF |
DMA_DESCR_TX_EOF);
invalidate_dcache_range((unsigned long)tx_descr,
(unsigned long)tx_descr +
sizeof(struct dma_descriptor));
invalidate_dcache_range((unsigned long)packet,
(unsigned long)packet + length);
reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr;
reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID;
return length;
}
/*
* Check for received packets and send them up the protocal stack
*/
static int tsi108_eth_recv (struct eth_device *dev)
{
struct dma_descriptor *rx_descr;
unsigned long base;
int length = 0;
unsigned long status;
volatile uchar *buffer;
base = dev->iobase;
/* make sure we see the changes made by the DMA engine */
invalidate_dcache_range ((unsigned long)rx_descr_array,
(unsigned long)rx_descr_array +
sizeof(rx_descr_array));
/* process all of the received packets */
rx_descr = rx_descr_current;
while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) {
/* check for error */
status = le32_to_cpu(rx_descr->config_status);
if (status & DMA_DESCR_RX_BAD_FRAME) {
#ifdef RX_PRINT_ERRORS
printf ("RX packet error: 0x%08lx\n %s%s%s%s%s%s\n",
status,
status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, "
: "",
status & DMA_DESCR_RX_SHORT_FRAME ? "too short, "
: "",
status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " :
"",
status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "",
status & DMA_DESCR_RX_MAX_FRAME_LEN ?
"max length, " : "",
status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " :
"");
#endif
} else {
length =
le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF;
/*** process packet ***/
buffer =
(volatile uchar
*)(le32_to_cpu (rx_descr->start_addr0));
NetReceive (buffer, length);
invalidate_dcache_range ((unsigned long)buffer,
(unsigned long)buffer +
RX_BUFFER_SIZE);
}
/* Give this buffer back to the DMA engine */
rx_descr->vlan_byte_count = 0;
rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) |
DMA_DESCR_RX_OWNER);
/* move descriptor pointer forward */
rx_descr =
(struct dma_descriptor
*)(le32_to_cpu (rx_descr->next_descr_addr0));
if (rx_descr == 0)
rx_descr = &rx_descr_array[0];
}
/* remember where we are for next time */
rx_descr_current = rx_descr;
/* If the DMA engine has reached the end of the queue
* start over at the begining */
if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) {
reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0;
reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0];
reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
}
return length;
}
/*
* disable an ethernet interface
*/
static void tsi108_eth_halt (struct eth_device *dev)
{
unsigned long base;
base = dev->iobase;
/* Put DMA/FIFO into reset state. */
reg_TX_CONFIG(base) = TX_CONFIG_RST;
reg_RX_CONFIG(base) = RX_CONFIG_RST;
/* Put MAC into reset state. */
reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET;
}
|
1001-study-uboot
|
drivers/net/tsi108_eth.c
|
C
|
gpl3
| 32,979
|
/*
ns8382x.c: A U-Boot driver for the NatSemi DP8382[01].
ported by: Mark A. Rakes (mark_rakes@vivato.net)
Adapted from:
1. an Etherboot driver for DP8381[56] written by:
Copyright (C) 2001 Entity Cyber, Inc.
This development of this Etherboot driver was funded by
Sicom Systems: http://www.sicompos.com/
Author: Marty Connor (mdc@thinguin.org)
Adapted from a Linux driver which was written by Donald Becker
This software may be used and distributed according to the terms
of the GNU Public License (GPL), incorporated herein by reference.
2. A Linux driver by Donald Becker, ns820.c:
Written/copyright 1999-2002 by Donald Becker.
This software may be used and distributed according to the terms of
the GNU General Public License (GPL), incorporated herein by reference.
Drivers based on or derived from this code fall under the GPL and must
retain the authorship, copyright and license notice. This file is not
a complete program and may only be used when the entire operating
system is licensed under the GPL. License for under other terms may be
available. Contact the original author for details.
The original author may be reached as becker@scyld.com, or at
Scyld Computing Corporation
410 Severn Ave., Suite 210
Annapolis MD 21403
Support information and updates available at
http://www.scyld.com/network/netsemi.html
Datasheets available from:
http://www.national.com/pf/DP/DP83820.html
http://www.national.com/pf/DP/DP83821.html
*/
/* Revision History
* October 2002 mar 1.0
* Initial U-Boot Release.
* Tested with Netgear GA622T (83820)
* and SMC9452TX (83821)
* NOTE: custom boards with these chips may (likely) require
* a programmed EEPROM device (if present) in order to work
* correctly.
*/
/* Includes */
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
/* defines */
#define DSIZE 0x00000FFF
#define ETH_ALEN 6
#define CRC_SIZE 4
#define TOUT_LOOP 500000
#define TX_BUF_SIZE 1536
#define RX_BUF_SIZE 1536
#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
enum register_offsets {
ChipCmd = 0x00,
ChipConfig = 0x04,
EECtrl = 0x08,
IntrMask = 0x14,
IntrEnable = 0x18,
TxRingPtr = 0x20,
TxRingPtrHi = 0x24,
TxConfig = 0x28,
RxRingPtr = 0x30,
RxRingPtrHi = 0x34,
RxConfig = 0x38,
PriQueue = 0x3C,
RxFilterAddr = 0x48,
RxFilterData = 0x4C,
ClkRun = 0xCC,
PCIPM = 0x44,
};
enum ChipCmdBits {
ChipReset = 0x100,
RxReset = 0x20,
TxReset = 0x10,
RxOff = 0x08,
RxOn = 0x04,
TxOff = 0x02,
TxOn = 0x01
};
enum ChipConfigBits {
LinkSts = 0x80000000,
GigSpeed = 0x40000000,
HundSpeed = 0x20000000,
FullDuplex = 0x10000000,
TBIEn = 0x01000000,
Mode1000 = 0x00400000,
T64En = 0x00004000,
D64En = 0x00001000,
M64En = 0x00000800,
PhyRst = 0x00000400,
PhyDis = 0x00000200,
ExtStEn = 0x00000100,
BEMode = 0x00000001,
};
#define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex)
enum TxConfig_bits {
TxDrthMask = 0x000000ff,
TxFlthMask = 0x0000ff00,
TxMxdmaMask = 0x00700000,
TxMxdma_8 = 0x00100000,
TxMxdma_16 = 0x00200000,
TxMxdma_32 = 0x00300000,
TxMxdma_64 = 0x00400000,
TxMxdma_128 = 0x00500000,
TxMxdma_256 = 0x00600000,
TxMxdma_512 = 0x00700000,
TxMxdma_1024 = 0x00000000,
TxCollRetry = 0x00800000,
TxAutoPad = 0x10000000,
TxMacLoop = 0x20000000,
TxHeartIgn = 0x40000000,
TxCarrierIgn = 0x80000000
};
enum RxConfig_bits {
RxDrthMask = 0x0000003e,
RxMxdmaMask = 0x00700000,
RxMxdma_8 = 0x00100000,
RxMxdma_16 = 0x00200000,
RxMxdma_32 = 0x00300000,
RxMxdma_64 = 0x00400000,
RxMxdma_128 = 0x00500000,
RxMxdma_256 = 0x00600000,
RxMxdma_512 = 0x00700000,
RxMxdma_1024 = 0x00000000,
RxAcceptLenErr = 0x04000000,
RxAcceptLong = 0x08000000,
RxAcceptTx = 0x10000000,
RxStripCRC = 0x20000000,
RxAcceptRunt = 0x40000000,
RxAcceptErr = 0x80000000,
};
/* Bits in the RxMode register. */
enum rx_mode_bits {
RxFilterEnable = 0x80000000,
AcceptAllBroadcast = 0x40000000,
AcceptAllMulticast = 0x20000000,
AcceptAllUnicast = 0x10000000,
AcceptPerfectMatch = 0x08000000,
};
typedef struct _BufferDesc {
u32 link;
u32 bufptr;
vu_long cmdsts;
u32 extsts; /*not used here */
} BufferDesc;
/* Bits in network_desc.status */
enum desc_status_bits {
DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
DescSizeMask = 0xfff,
DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
DescRxDest = 0x01800000, DescRxLong = 0x00400000,
DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
};
/* Bits in MEAR */
enum mii_reg_bits {
MDIO_ShiftClk = 0x0040,
MDIO_EnbOutput = 0x0020,
MDIO_Data = 0x0010,
};
/* PHY Register offsets. */
enum phy_reg_offsets {
BMCR = 0x00,
BMSR = 0x01,
PHYIDR1 = 0x02,
PHYIDR2 = 0x03,
ANAR = 0x04,
KTCR = 0x09,
};
/* basic mode control register bits */
enum bmcr_bits {
Bmcr_Reset = 0x8000,
Bmcr_Loop = 0x4000,
Bmcr_Speed0 = 0x2000,
Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */
Bmcr_RstAutoNeg = 0x0200,
Bmcr_Duplex = 0x0100,
Bmcr_Speed1 = 0x0040,
Bmcr_Force10H = 0x0000,
Bmcr_Force10F = 0x0100,
Bmcr_Force100H = 0x2000,
Bmcr_Force100F = 0x2100,
Bmcr_Force1000H = 0x0040,
Bmcr_Force1000F = 0x0140,
};
/* auto negotiation advertisement register */
enum anar_bits {
anar_adv_100F = 0x0100,
anar_adv_100H = 0x0080,
anar_adv_10F = 0x0040,
anar_adv_10H = 0x0020,
anar_ieee_8023 = 0x0001,
};
/* 1K-base T control register */
enum ktcr_bits {
ktcr_adv_1000H = 0x0100,
ktcr_adv_1000F = 0x0200,
};
/* Globals */
static u32 SavedClkRun;
static unsigned int cur_rx;
static unsigned int rx_config;
static unsigned int tx_config;
/* Note: transmit and receive buffers and descriptors must be
long long word aligned */
static BufferDesc txd __attribute__ ((aligned(8)));
static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8)));
static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8)));
static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
__attribute__ ((aligned(8)));
/* Function Prototypes */
static int mdio_read(struct eth_device *dev, int phy_id, int addr);
static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value);
static void mdio_sync(struct eth_device *dev, u32 offset);
static int ns8382x_init(struct eth_device *dev, bd_t * bis);
static void ns8382x_reset(struct eth_device *dev);
static void ns8382x_init_rxfilter(struct eth_device *dev);
static void ns8382x_init_txd(struct eth_device *dev);
static void ns8382x_init_rxd(struct eth_device *dev);
static void ns8382x_set_rx_mode(struct eth_device *dev);
static void ns8382x_check_duplex(struct eth_device *dev);
static int ns8382x_send(struct eth_device *dev, volatile void *packet,
int length);
static int ns8382x_poll(struct eth_device *dev);
static void ns8382x_disable(struct eth_device *dev);
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820},
{}
};
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
static inline int
INW(struct eth_device *dev, u_long addr)
{
return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
}
static int
INL(struct eth_device *dev, u_long addr)
{
return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
}
static inline void
OUTW(struct eth_device *dev, int command, u_long addr)
{
*(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
}
static inline void
OUTL(struct eth_device *dev, int command, u_long addr)
{
*(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
}
/* Function: ns8382x_initialize
* Description: Retrieves the MAC address of the card, and sets up some
* globals required by other routines, and initializes the NIC, making it
* ready to send and receive packets.
* Side effects: initializes ns8382xs, ready to receive packets.
* Returns: int: number of cards found
*/
int
ns8382x_initialize(bd_t * bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase, status;
int i, idx = 0;
u32 phyAddress;
u32 tmp;
u32 chip_config;
while (1) { /* Find PCI device(s) */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
debug("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase);
pci_write_config_dword(devno, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled. */
pci_read_config_dword(devno, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_MEMORY)) {
printf("Error: Can not enable MEM access.\n");
continue;
} else if (!(status & PCI_COMMAND_MASTER)) {
printf("Error: Can not enable Bus Mastering.\n");
continue;
}
dev = (struct eth_device *) malloc(sizeof *dev);
if (!dev) {
printf("ns8382x: Can not allocate memory\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "dp8382x#%d", card_number);
dev->iobase = bus_to_phys(iobase);
dev->priv = (void *) devno;
dev->init = ns8382x_init;
dev->halt = ns8382x_disable;
dev->send = ns8382x_send;
dev->recv = ns8382x_poll;
/* ns8382x has a non-standard PM control register
* in PCI config space. Some boards apparently need
* to be brought to D0 in this manner. */
pci_read_config_dword(devno, PCIPM, &tmp);
if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */
u32 newtmp = tmp & ~(0x03 | 0x100);
pci_write_config_dword(devno, PCIPM, newtmp);
}
/* get MAC address */
for (i = 0; i < 3; i++) {
u32 data;
char *mac = (char *)&dev->enetaddr[i * 2];
OUTL(dev, i * 2, RxFilterAddr);
data = INL(dev, RxFilterData);
*mac++ = data;
*mac++ = data >> 8;
}
/* get PHY address, can't be zero */
for (phyAddress = 1; phyAddress < 32; phyAddress++) {
u32 rev, phy1;
phy1 = mdio_read(dev, phyAddress, PHYIDR1);
if (phy1 == 0x2000) { /*check for 83861/91 */
rev = mdio_read(dev, phyAddress, PHYIDR2);
if ((rev & ~(0x000f)) == 0x00005c50 ||
(rev & ~(0x000f)) == 0x00005c60) {
debug("phy rev is %x\n", rev);
debug("phy address is %x\n",
phyAddress);
break;
}
}
}
/* set phy to autonegotiate && advertise everything */
mdio_write(dev, phyAddress, KTCR,
(ktcr_adv_1000H | ktcr_adv_1000F));
mdio_write(dev, phyAddress, ANAR,
(anar_adv_100F | anar_adv_100H | anar_adv_10H |
anar_adv_10F | anar_ieee_8023));
mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */
mdio_write(dev, phyAddress, BMCR,
(Bmcr_AutoNegEn | Bmcr_RstAutoNeg));
/* Reset the chip to erase any previous misconfiguration. */
OUTL(dev, (ChipReset), ChipCmd);
chip_config = INL(dev, ChipConfig);
/* reset the phy */
OUTL(dev, (chip_config | PhyRst), ChipConfig);
/* power up and initialize transceiver */
OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig);
mdio_sync(dev, EECtrl);
{
u32 chpcfg =
INL(dev, ChipConfig) ^ SpeedStatus_Polarity;
debug("%s: Transceiver 10%s %s duplex.\n", dev->name,
(chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed)
? "0" : "",
chpcfg & FullDuplex ? "full" : "half");
debug("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
dev->enetaddr[0], dev->enetaddr[1],
dev->enetaddr[2], dev->enetaddr[3],
dev->enetaddr[4], dev->enetaddr[5]);
}
/* Disable PME:
* The PME bit is initialized from the EEPROM contents.
* PCI cards probably have PME disabled, but motherboard
* implementations may have PME set to enable WakeOnLan.
* With PME set the chip will scan incoming packets but
* nothing will be written to memory. */
SavedClkRun = INL(dev, ClkRun);
OUTL(dev, SavedClkRun & ~0x100, ClkRun);
eth_register(dev);
card_number++;
pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60);
udelay(10 * 1000);
}
return card_number;
}
/* MII transceiver control section.
Read and write MII registers using software-generated serial MDIO
protocol. See the MII specifications or DP83840A data sheet for details.
The maximum data clock rate is 2.5 MHz. To meet minimum timing we
must flush writes to the PCI bus with a PCI read. */
#define mdio_delay(mdio_addr) INL(dev, mdio_addr)
#define MDIO_EnbIn (0)
#define MDIO_WRITE0 (MDIO_EnbOutput)
#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
/* Generate the preamble required for initial synchronization and
a few older transceivers. */
static void
mdio_sync(struct eth_device *dev, u32 offset)
{
int bits = 32;
/* Establish sync by sending at least 32 logic ones. */
while (--bits >= 0) {
OUTL(dev, MDIO_WRITE1, offset);
mdio_delay(offset);
OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset);
mdio_delay(offset);
}
}
static int
mdio_read(struct eth_device *dev, int phy_id, int addr)
{
int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr;
int i, retval = 0;
/* Shift the read command bits out. */
for (i = 15; i >= 0; i--) {
int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
OUTL(dev, dataval, EECtrl);
mdio_delay(EECtrl);
OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
mdio_delay(EECtrl);
}
/* Read the two transition, 16 data, and wire-idle bits. */
for (i = 19; i > 0; i--) {
OUTL(dev, MDIO_EnbIn, EECtrl);
mdio_delay(EECtrl);
retval =
(retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0);
OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
mdio_delay(EECtrl);
}
return (retval >> 1) & 0xffff;
}
static void
mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
{
int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value;
int i;
/* Shift the command bits out. */
for (i = 31; i >= 0; i--) {
int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
OUTL(dev, dataval, EECtrl);
mdio_delay(EECtrl);
OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
mdio_delay(EECtrl);
}
/* Clear out extra bits. */
for (i = 2; i > 0; i--) {
OUTL(dev, MDIO_EnbIn, EECtrl);
mdio_delay(EECtrl);
OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
mdio_delay(EECtrl);
}
return;
}
/* Function: ns8382x_init
* Description: resets the ethernet controller chip and configures
* registers and data structures required for sending and receiving packets.
* Arguments: struct eth_device *dev: NIC data structure
* returns: int.
*/
static int
ns8382x_init(struct eth_device *dev, bd_t * bis)
{
u32 config;
ns8382x_reset(dev);
/* Disable PME:
* The PME bit is initialized from the EEPROM contents.
* PCI cards probably have PME disabled, but motherboard
* implementations may have PME set to enable WakeOnLan.
* With PME set the chip will scan incoming packets but
* nothing will be written to memory. */
OUTL(dev, SavedClkRun & ~0x100, ClkRun);
ns8382x_init_rxfilter(dev);
ns8382x_init_txd(dev);
ns8382x_init_rxd(dev);
/*set up ChipConfig */
config = INL(dev, ChipConfig);
/*turn off 64 bit ops && Ten-bit interface
* && big-endian mode && extended status */
config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn);
OUTL(dev, config, ChipConfig);
/* Configure the PCI bus bursts and FIFO thresholds. */
tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad
| TxCollRetry | TxMxdma_1024 | (0x1002);
rx_config = RxMxdma_1024 | 0x20;
debug("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
debug("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
OUTL(dev, tx_config, TxConfig);
OUTL(dev, rx_config, RxConfig);
/*turn off priority queueing */
OUTL(dev, 0x0, PriQueue);
ns8382x_check_duplex(dev);
ns8382x_set_rx_mode(dev);
OUTL(dev, (RxOn | TxOn), ChipCmd);
return 1;
}
/* Function: ns8382x_reset
* Description: soft resets the controller chip
* Arguments: struct eth_device *dev: NIC data structure
* Returns: void.
*/
static void
ns8382x_reset(struct eth_device *dev)
{
OUTL(dev, ChipReset, ChipCmd);
while (INL(dev, ChipCmd))
/*wait until done */ ;
OUTL(dev, 0, IntrMask);
OUTL(dev, 0, IntrEnable);
}
/* Function: ns8382x_init_rxfilter
* Description: sets receive filter address to our MAC address
* Arguments: struct eth_device *dev: NIC data structure
* returns: void.
*/
static void
ns8382x_init_rxfilter(struct eth_device *dev)
{
int i;
for (i = 0; i < ETH_ALEN; i += 2) {
OUTL(dev, i, RxFilterAddr);
OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
RxFilterData);
}
}
/* Function: ns8382x_init_txd
* Description: initializes the Tx descriptor
* Arguments: struct eth_device *dev: NIC data structure
* returns: void.
*/
static void
ns8382x_init_txd(struct eth_device *dev)
{
txd.link = (u32) 0;
txd.bufptr = cpu_to_le32((u32) & txb[0]);
txd.cmdsts = (u32) 0;
txd.extsts = (u32) 0;
OUTL(dev, 0x0, TxRingPtrHi);
OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
debug("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n",
INL(dev, TxRingPtr), &txd);
}
/* Function: ns8382x_init_rxd
* Description: initializes the Rx descriptor ring
* Arguments: struct eth_device *dev: NIC data structure
* Returns: void.
*/
static void
ns8382x_init_rxd(struct eth_device *dev)
{
int i;
OUTL(dev, 0x0, RxRingPtrHi);
cur_rx = 0;
for (i = 0; i < NUM_RX_DESC; i++) {
rxd[i].link =
cpu_to_le32((i + 1 <
NUM_RX_DESC) ? (u32) & rxd[i +
1] : (u32) &
rxd[0]);
rxd[i].extsts = cpu_to_le32((u32) 0x0);
rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
debug
("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
i, &rxd[i], le32_to_cpu(rxd[i].link),
le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
}
OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr);
debug("ns8382x_init_rxd: RX descriptor register loaded with: %X\n",
INL(dev, RxRingPtr));
}
/* Function: ns8382x_set_rx_mode
* Description:
* sets the receive mode to accept all broadcast packets and packets
* with our MAC address, and reject all multicast packets.
* Arguments: struct eth_device *dev: NIC data structure
* Returns: void.
*/
static void
ns8382x_set_rx_mode(struct eth_device *dev)
{
u32 rx_mode = 0x0;
/*spec says RxFilterEnable has to be 0 for rest of
* this stuff to be properly configured. Linux driver
* seems to support this*/
/* OUTL(dev, rx_mode, RxFilterAddr);*/
rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch);
OUTL(dev, rx_mode, RxFilterAddr);
printf("ns8382x_set_rx_mode: set to %X\n", rx_mode);
/*now we turn RxFilterEnable back on */
/*rx_mode |= RxFilterEnable;
OUTL(dev, rx_mode, RxFilterAddr);*/
}
static void
ns8382x_check_duplex(struct eth_device *dev)
{
int gig = 0;
int hun = 0;
int duplex = 0;
int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity);
duplex = (config & FullDuplex) ? 1 : 0;
gig = (config & GigSpeed) ? 1 : 0;
hun = (config & HundSpeed) ? 1 : 0;
debug("%s: Setting 10%s %s-duplex based on negotiated link"
" capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
duplex ? "full" : "half");
if (duplex) {
rx_config |= RxAcceptTx;
tx_config |= (TxCarrierIgn | TxHeartIgn);
} else {
rx_config &= ~RxAcceptTx;
tx_config &= ~(TxCarrierIgn | TxHeartIgn);
}
debug("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
debug("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
OUTL(dev, tx_config, TxConfig);
OUTL(dev, rx_config, RxConfig);
/*if speed is 10 or 100, remove MODE1000,
* if it's 1000, then set it */
config = INL(dev, ChipConfig);
if (gig)
config |= Mode1000;
else
config &= ~Mode1000;
debug("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns");
OUTL(dev, config, ChipConfig);
}
/* Function: ns8382x_send
* Description: transmits a packet and waits for completion or timeout.
* Returns: void. */
static int
ns8382x_send(struct eth_device *dev, volatile void *packet, int length)
{
u32 i, status = 0;
vu_long tx_stat = 0;
/* Stop the transmitter */
OUTL(dev, TxOff, ChipCmd);
debug("ns8382x_send: sending %d bytes\n", (int)length);
/* set the transmit buffer descriptor and enable Transmit State Machine */
txd.link = cpu_to_le32(0x0);
txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet));
txd.extsts = cpu_to_le32(0x0);
txd.cmdsts = cpu_to_le32(DescOwn | length);
/* load Transmit Descriptor Register */
OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
debug("ns8382x_send: TX descriptor register loaded with: %#08X\n",
INL(dev, TxRingPtr));
debug("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n",
le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
/* restart the transmitter */
OUTL(dev, TxOn, ChipCmd);
for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
if (i >= TOUT_LOOP) {
printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n",
dev->name, tx_stat);
goto Done;
}
}
if (!(tx_stat & DescPktOK)) {
printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat);
goto Done;
}
debug("ns8382x_send: tx_stat: %#08lX\n", tx_stat);
status = 1;
Done:
return status;
}
/* Function: ns8382x_poll
* Description: checks for a received packet and returns it if found.
* Arguments: struct eth_device *dev: NIC data structure
* Returns: 1 if packet was received.
* 0 if no packet was received.
* Side effects:
* Returns (copies) the packet to the array dev->packet.
* Returns the length of the packet.
*/
static int
ns8382x_poll(struct eth_device *dev)
{
int retstat = 0;
int length = 0;
vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
if (!(rx_status & (u32) DescOwn))
return retstat;
debug("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n",
cur_rx, rx_status);
length = (rx_status & DSIZE) - CRC_SIZE;
if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
/* corrupted packet received */
printf("ns8382x_poll: Corrupted packet, status:%lx\n", rx_status);
retstat = 0;
} else {
/* give packet to higher level routine */
NetReceive((rxb + cur_rx * RX_BUF_SIZE), length);
retstat = 1;
}
/* return the descriptor and buffer to receive ring */
rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
if (++cur_rx == NUM_RX_DESC)
cur_rx = 0;
/* re-enable the potentially idle receive state machine */
OUTL(dev, RxOn, ChipCmd);
return retstat;
}
/* Function: ns8382x_disable
* Description: Turns off interrupts and stops Tx and Rx engines
* Arguments: struct eth_device *dev: NIC data structure
* Returns: void.
*/
static void
ns8382x_disable(struct eth_device *dev)
{
/* Disable interrupts using the mask. */
OUTL(dev, 0, IntrMask);
OUTL(dev, 0, IntrEnable);
/* Stop the chip's Tx and Rx processes. */
OUTL(dev, (RxOff | TxOff), ChipCmd);
/* Restore PME enable bit */
OUTL(dev, SavedClkRun, ClkRun);
}
|
1001-study-uboot
|
drivers/net/ns8382x.c
|
C
|
gpl3
| 23,574
|
/*
* rtl8139.c : U-Boot driver for the RealTek RTL8139
*
* Masami Komiya (mkomiya@sonare.it)
*
* Most part is taken from rtl8139.c of etherboot
*
*/
/* rtl8139.c - etherboot driver for the Realtek 8139 chipset
ported from the linux driver written by Donald Becker
by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
This software may be used and distributed according to the terms
of the GNU Public License, incorporated herein by reference.
changes to the original driver:
- removed support for interrupts, switching to polling mode (yuck!)
- removed support for the 8129 chip (external MII)
*/
/*********************************************************************/
/* Revision History */
/*********************************************************************/
/*
28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
Put in virt_to_bus calls to allow Etherboot relocation.
06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
Following email from Hyun-Joon Cha, added a disable routine, otherwise
NIC remains live and can crash the kernel later.
4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
Shuffled things around, removed the leftovers from the 8129 support
that was in the Linux driver and added a bit more 8139 definitions.
Moved the 8K receive buffer to a fixed, available address outside the
0x98000-0x9ffff range. This is a bit of a hack, but currently the only
way to make room for the Etherboot features that need substantial amounts
of code like the ANSI console support. Currently the buffer is just below
0x10000, so this even conforms to the tagged boot image specification,
which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
interpretation of this "reserved" is that Etherboot may do whatever it
likes, as long as its environment is kept intact (like the BIOS
variables). Hopefully fixed rtl_poll() once and for all. The symptoms
were that if Etherboot was left at the boot menu for several minutes, the
first eth_poll failed. Seems like I am the only person who does this.
First of all I fixed the debugging code and then set out for a long bug
hunting session. It took me about a week full time work - poking around
various places in the driver, reading Don Becker's and Jeff Garzik's Linux
driver and even the FreeBSD driver (what a piece of crap!) - and
eventually spotted the nasty thing: the transmit routine was acknowledging
each and every interrupt pending, including the RxOverrun and RxFIFIOver
interrupts. This confused the RTL8139 thoroughly. It destroyed the
Rx ring contents by dumping the 2K FIFO contents right where we wanted to
get the next packet. Oh well, what fun.
18 Jan 2000 mdc@thinguin.org (Marty Connor)
Drastically simplified error handling. Basically, if any error
in transmission or reception occurs, the card is reset.
Also, pointed all transmit descriptors to the same buffer to
save buffer space. This should decrease driver size and avoid
corruption because of exceeding 32K during runtime.
28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
rtl_poll was quite broken: it used the RxOK interrupt flag instead
of the RxBufferEmpty flag which often resulted in very bad
transmission performace - below 1kBytes/s.
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#define RTL_TIMEOUT 100000
#define ETH_FRAME_LEN 1514
#define ETH_ALEN 6
#define ETH_ZLEN 60
/* PCI Tuning Parameters
Threshold is bytes transferred to chip before transmission starts. */
#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
#define TX_DMA_BURST 4 /* Calculate as 16<<val. */
#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
#define DEBUG_TX 0 /* set to 1 to enable debug code */
#define DEBUG_RX 0 /* set to 1 to enable debug code */
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
/* Symbolic offsets to registers. */
enum RTL8139_registers {
MAC0=0, /* Ethernet hardware address. */
MAR0=8, /* Multicast filter. */
TxStatus0=0x10, /* Transmit status (four 32bit registers). */
TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
IntrMask=0x3C, IntrStatus=0x3E,
TxConfig=0x40, RxConfig=0x44,
Timer=0x48, /* general-purpose counter. */
RxMissed=0x4C, /* 24 bits valid, write clears. */
Cfg9346=0x50, Config0=0x51, Config1=0x52,
TimerIntrReg=0x54, /* intr if gp counter reaches this value */
MediaStatus=0x58,
Config3=0x59,
MultiIntr=0x5C,
RevisionID=0x5E, /* revision of the RTL8139 chip */
TxSummary=0x60,
MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
NWayExpansion=0x6A,
DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
NWayTestReg=0x70,
RxCnt=0x72, /* packet received counter */
CSCR=0x74, /* chip status and configuration register */
PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
/* from 0x84 onwards are a number of power management/wakeup frame
* definitions we will probably never need to know about. */
};
enum ChipCmdBits {
CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
/* Interrupt register bits, using my own meaningful names. */
enum IntrStatusBits {
PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
};
enum TxStatusBits {
TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
TxOutOfWindow=0x20000000, TxAborted=0x40000000,
TxCarrierLost=0x80000000,
};
enum RxStatusBits {
RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
RxBadAlign=0x0002, RxStatusOK=0x0001,
};
enum MediaStatusBits {
MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
};
enum MIIBMCRBits {
BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
};
enum CSCRBits {
CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
CSCR_LinkDownCmd=0x0f3c0,
};
/* Bits in RxConfig. */
enum rx_mode_bits {
RxCfgWrap=0x80,
AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
};
static int ioaddr;
static unsigned int cur_rx,cur_tx;
/* The RTL8139 can only transmit from a contiguous, aligned memory block. */
static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
static int read_eeprom(int location, int addr_len);
static void rtl_reset(struct eth_device *dev);
static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
static int rtl_poll(struct eth_device *dev);
static void rtl_disable(struct eth_device *dev);
#ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */
static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set)
{
return (0);
}
#endif
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
{PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
{}
};
int rtl8139_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
/* Find RTL8139 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("Can not allocate memory of rtl8139\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8139#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)bus_to_phys(iobase);
dev->init = rtl8139_probe;
dev->halt = rtl_disable;
dev->send = rtl_transmit;
dev->recv = rtl_poll;
#ifdef CONFIG_MCAST_TFTP
dev->mcast = rtl_bcast_addr;
#endif
eth_register (dev);
card_number++;
pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
udelay (10 * 1000);
}
return card_number;
}
static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
{
int i;
int addr_len;
unsigned short *ap = (unsigned short *)dev->enetaddr;
ioaddr = dev->iobase;
/* Bring the chip out of low-power mode. */
outb(0x00, ioaddr + Config1);
addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
for (i = 0; i < 3; i++)
*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
rtl_reset(dev);
if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
printf("Cable not connected or other link failure\n");
return -1 ;
}
return 0;
}
/* Serial EEPROM section. */
/* EEPROM_Ctrl bits. */
#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
#define EE_CS 0x08 /* EEPROM chip select. */
#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
#define EE_WRITE_0 0x00
#define EE_WRITE_1 0x02
#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
#define EE_ENB (0x80 | EE_CS)
/*
Delay between EEPROM clock transitions.
No extra delay is needed with 33MHz PCI, but 66MHz may change this.
*/
#define eeprom_delay() inl(ee_addr)
/* The EEPROM commands include the alway-set leading bit. */
#define EE_WRITE_CMD (5)
#define EE_READ_CMD (6)
#define EE_ERASE_CMD (7)
static int read_eeprom(int location, int addr_len)
{
int i;
unsigned int retval = 0;
long ee_addr = ioaddr + Cfg9346;
int read_cmd = location | (EE_READ_CMD << addr_len);
outb(EE_ENB & ~EE_CS, ee_addr);
outb(EE_ENB, ee_addr);
eeprom_delay();
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
outb(EE_ENB | dataval, ee_addr);
eeprom_delay();
outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
}
outb(EE_ENB, ee_addr);
eeprom_delay();
for (i = 16; i > 0; i--) {
outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
eeprom_delay();
retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
outb(EE_ENB, ee_addr);
eeprom_delay();
}
/* Terminate the EEPROM access. */
outb(~EE_CS, ee_addr);
eeprom_delay();
return retval;
}
static const unsigned int rtl8139_rx_config =
(RX_BUF_LEN_IDX << 11) |
(RX_FIFO_THRESH << 13) |
(RX_DMA_BURST << 8);
static void set_rx_mode(struct eth_device *dev) {
unsigned int mc_filter[2];
int rx_mode;
/* !IFF_PROMISC */
rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
mc_filter[1] = mc_filter[0] = 0xffffffff;
outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
outl(mc_filter[0], ioaddr + MAR0 + 0);
outl(mc_filter[1], ioaddr + MAR0 + 4);
}
static void rtl_reset(struct eth_device *dev)
{
int i;
outb(CmdReset, ioaddr + ChipCmd);
cur_rx = 0;
cur_tx = 0;
/* Give the chip 10ms to finish the reset. */
for (i=0; i<100; ++i){
if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
udelay (100); /* wait 100us */
}
for (i = 0; i < ETH_ALEN; i++)
outb(dev->enetaddr[i], ioaddr + MAC0 + i);
/* Must enable Tx/Rx before setting transfer thresholds! */
outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
ioaddr + RxConfig); /* accept no frames yet! */
outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
/* The Linux driver changes Config1 here to use a different LED pattern
* for half duplex or full/autodetect duplex (for full/autodetect, the
* outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
* TX/RX, Link100, Link10). This is messy, because it doesn't match
* the inscription on the mounting bracket. It should not be changed
* from the configuration EEPROM default, because the card manufacturer
* should have set that to match the card. */
debug_cond(DEBUG_RX,
"rx ring address is %lX\n",(unsigned long)rx_ring);
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
/* If we add multicast support, the MAR0 register would have to be
* initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
* only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
outl(rtl8139_rx_config, ioaddr + RxConfig);
/* Start the chip's Tx and Rx process. */
outl(0, ioaddr + RxMissed);
/* set_rx_mode */
set_rx_mode(dev);
/* Disable all known interrupts by setting the interrupt mask. */
outw(0, ioaddr + IntrMask);
}
static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
{
unsigned int status;
unsigned long txstatus;
unsigned int len = length;
int i = 0;
ioaddr = dev->iobase;
memcpy((char *)tx_buffer, (char *)packet, (int)length);
debug_cond(DEBUG_TX, "sending %d bytes\n", len);
/* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
* bytes are sent automatically for the FCS, totalling to 64 bytes). */
while (len < ETH_ZLEN) {
tx_buffer[len++] = '\0';
}
flush_cache((unsigned long)tx_buffer, length);
outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
ioaddr + TxStatus0 + cur_tx*4);
do {
status = inw(ioaddr + IntrStatus);
/* Only acknlowledge interrupt sources we can properly handle
* here - the RxOverflow/RxFIFOOver MUST be handled in the
* rtl_poll() function. */
outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
udelay(10);
} while (i++ < RTL_TIMEOUT);
txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
if (status & TxOK) {
cur_tx = (cur_tx + 1) % NUM_TX_DESC;
debug_cond(DEBUG_TX,
"tx done, status %hX txstatus %lX\n",
status, txstatus);
return length;
} else {
debug_cond(DEBUG_TX,
"tx timeout/error (%d usecs), status %hX txstatus %lX\n",
10*i, status, txstatus);
rtl_reset(dev);
return 0;
}
}
static int rtl_poll(struct eth_device *dev)
{
unsigned int status;
unsigned int ring_offs;
unsigned int rx_size, rx_status;
int length=0;
ioaddr = dev->iobase;
if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
return 0;
}
status = inw(ioaddr + IntrStatus);
/* See below for the rest of the interrupt acknowledges. */
outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
ring_offs = cur_rx % RX_BUF_LEN;
/* ring_offs is guaranteed being 4-byte aligned */
rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
rx_size = rx_status >> 16;
rx_status &= 0xffff;
if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
(rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
printf("rx error %hX\n", rx_status);
rtl_reset(dev); /* this clears all interrupts still pending */
return 0;
}
/* Received a good packet */
length = rx_size - 4; /* no one cares about the FCS */
if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
int semi_count = RX_BUF_LEN - ring_offs - 4;
unsigned char rxdata[RX_BUF_LEN];
memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
NetReceive(rxdata, length);
debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
semi_count, rx_size-4-semi_count);
} else {
NetReceive(rx_ring + ring_offs + 4, length);
debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
}
flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
outw(cur_rx - 16, ioaddr + RxBufPtr);
/* See RTL8139 Programming Guide V0.1 for the official handling of
* Rx overflow situations. The document itself contains basically no
* usable information, except for a few exception handling rules. */
outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
return length;
}
static void rtl_disable(struct eth_device *dev)
{
int i;
ioaddr = dev->iobase;
/* reset the chip */
outb(CmdReset, ioaddr + ChipCmd);
/* Give the chip 10ms to finish the reset. */
for (i=0; i<100; ++i){
if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
udelay (100); /* wait 100us */
}
}
|
1001-study-uboot
|
drivers/net/rtl8139.c
|
C
|
gpl3
| 16,889
|
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __ARMADA100_FEC_H__
#define __ARMADA100_FEC_H__
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#define PORT_NUM 0x0
/* RX & TX descriptor command */
#define BUF_OWNED_BY_DMA (1<<31)
/* RX descriptor status */
#define RX_EN_INT (1<<23)
#define RX_FIRST_DESC (1<<17)
#define RX_LAST_DESC (1<<16)
#define RX_ERROR (1<<15)
/* TX descriptor command */
#define TX_EN_INT (1<<23)
#define TX_GEN_CRC (1<<22)
#define TX_ZERO_PADDING (1<<18)
#define TX_FIRST_DESC (1<<17)
#define TX_LAST_DESC (1<<16)
#define TX_ERROR (1<<15)
/* smi register */
#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */
#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */
#define SMI_OP_W (0<<26) /* Write operation */
#define SMI_OP_R (1<<26) /* Read operation */
#define HASH_ADD 0
#define HASH_DELETE 1
#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
#define HOP_NUMBER 12
#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
#define PHY_WAIT_MICRO_SECONDS 10
#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
#define ETH_EXTRA_HEADER (6+6+2+4)
/* dest+src addr+protocol id+crc */
#define MAX_PKT_SIZE 1536
/* Bit definitions of the SDMA Config Reg */
#define SDCR_BSZ_OFF 12
#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF)
#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF)
#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF)
#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF)
#define SDCR_BLMR (1<<6)
#define SDCR_BLMT (1<<7)
#define SDCR_RIFB (1<<9)
#define SDCR_RC_OFF 2
#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
/* SDMA_CMD */
#define SDMA_CMD_AT (1<<31)
#define SDMA_CMD_TXDL (1<<24)
#define SDMA_CMD_TXDH (1<<23)
#define SDMA_CMD_AR (1<<15)
#define SDMA_CMD_ERD (1<<7)
/* Bit definitions of the Port Config Reg */
#define PCR_HS (1<<12)
#define PCR_EN (1<<7)
#define PCR_PM (1<<0)
/* Bit definitions of the Port Config Extend Reg */
#define PCXR_2BSM (1<<28)
#define PCXR_DSCP_EN (1<<21)
#define PCXR_MFL_1518 (0<<14)
#define PCXR_MFL_1536 (1<<14)
#define PCXR_MFL_2048 (2<<14)
#define PCXR_MFL_64K (3<<14)
#define PCXR_FLP (1<<11)
#define PCXR_PRIO_TX_OFF 3
#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF)
/*
* * Bit definitions of the Interrupt Cause Reg
* * and Interrupt MASK Reg is the same
* */
#define ICR_RXBUF (1<<0)
#define ICR_TXBUF_H (1<<2)
#define ICR_TXBUF_L (1<<3)
#define ICR_TXEND_H (1<<6)
#define ICR_TXEND_L (1<<7)
#define ICR_RXERR (1<<8)
#define ICR_TXERR_H (1<<10)
#define ICR_TXERR_L (1<<11)
#define ICR_TX_UDR (1<<13)
#define ICR_MII_CH (1<<28)
#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
ICR_TXERR_H | ICR_TXERR_L |\
ICR_TXEND_H | ICR_TXEND_L |\
ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
#define PHY_MASK 0x0000001f
#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
(((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
#define RX_BUF_OFFSET 0x2
#define RXQ 0x0 /* RX Queue 0 */
#define TXQ 0x1 /* TX Queue 1 */
struct addr_table_entry_t {
u32 lo;
u32 hi;
};
/* Bit fields of a Hash Table Entry */
enum hash_table_entry {
HTEVALID = 1,
HTESKIP = 2,
HTERD = 4,
HTERDBIT = 2
};
struct tx_desc {
u32 cmd_sts; /* Command/status field */
u16 reserved;
u16 byte_cnt; /* buffer byte count */
u8 *buf_ptr; /* pointer to buffer for this descriptor */
struct tx_desc *nextdesc_p; /* Pointer to next descriptor */
};
struct rx_desc {
u32 cmd_sts; /* Descriptor command status */
u16 byte_cnt; /* Descriptor buffer byte count */
u16 buf_size; /* Buffer size */
u8 *buf_ptr; /* Descriptor buffer pointer */
struct rx_desc *nxtdesc_p; /* Next descriptor pointer */
};
/*
* Armada100 Fast Ethernet controller Registers
* Refer Datasheet Appendix A.22
*/
struct armdfec_reg {
u32 phyadr; /* PHY Address */
u32 pad1[3];
u32 smi; /* SMI */
u32 pad2[0xFB];
u32 pconf; /* Port configuration */
u32 pad3;
u32 pconf_ext; /* Port configuration extend */
u32 pad4;
u32 pcmd; /* Port Command */
u32 pad5;
u32 pstatus; /* Port Status */
u32 pad6;
u32 spar; /* Serial Parameters */
u32 pad7;
u32 htpr; /* Hash table pointer */
u32 pad8;
u32 fcsal; /* Flow control source address low */
u32 pad9;
u32 fcsah; /* Flow control source address high */
u32 pad10;
u32 sdma_conf; /* SDMA configuration */
u32 pad11;
u32 sdma_cmd; /* SDMA command */
u32 pad12;
u32 ic; /* Interrupt cause */
u32 iwc; /* Interrupt write to clear */
u32 im; /* Interrupt mask */
u32 pad13;
u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code
Point to Priority 0 Low */
u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */
u32 pad14[3];
struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor
Pointer */
u32 pad15[4];
struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor
Pointer */
u32 pad16[0x0C];
struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor
Pointer */
};
struct armdfec_device {
struct eth_device dev;
struct armdfec_reg *regs;
struct tx_desc *p_txdesc;
struct rx_desc *p_rxdesc;
struct rx_desc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
u8 *htpr; /* hash pointer */
};
#endif /* __ARMADA100_FEC_H__ */
|
1001-study-uboot
|
drivers/net/armada100_fec.h
|
C
|
gpl3
| 7,044
|
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <command.h>
#include <config.h>
#include <net.h>
#include <miiphy.h>
#undef ET_DEBUG
#undef MII_DEBUG
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
#define PKT_MAXBUF_SIZE 1518
#define PKT_MINBUF_SIZE 64
#define PKT_MAXBLR_SIZE 1536
#define LAST_PKTBUFSRX PKTBUFSRX - 1
#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
/* RxBD bits definitions */
#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
BD_ENET_RX_OV | BD_ENET_RX_TR)
#include <asm/immap.h>
#include <asm/fsl_mcdmafec.h>
#include "MCD_dma.h"
DECLARE_GLOBAL_DATA_PTR;
struct fec_info_dma fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
{
0, /* index */
CONFIG_SYS_FEC0_IOBASE, /* io base */
CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
CONFIG_SYS_FEC0_MIIBASE, /* mii base */
-1, /* phy_addr */
0, /* duplex and speed */
0, /* phy name */
0, /* phyname init */
0, /* RX BD */
0, /* TX BD */
0, /* rx Index */
0, /* tx Index */
0, /* tx buffer */
0, /* initialized flag */
(struct fec_info_dma *)-1, /* next */
FEC0_RX_TASK, /* rxTask */
FEC0_TX_TASK, /* txTask */
FEC0_RX_PRIORITY, /* rxPri */
FEC0_TX_PRIORITY, /* txPri */
FEC0_RX_INIT, /* rxInit */
FEC0_TX_INIT, /* txInit */
0, /* usedTbdIndex */
0, /* cleanTbdNum */
},
#endif
#ifdef CONFIG_SYS_FEC1_IOBASE
{
1, /* index */
CONFIG_SYS_FEC1_IOBASE, /* io base */
CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
CONFIG_SYS_FEC1_MIIBASE, /* mii base */
-1, /* phy_addr */
0, /* duplex and speed */
0, /* phy name */
0, /* phy name init */
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
(cbd_t *)DBUF_LENGTH, /* RX BD */
#else
0, /* RX BD */
#endif
0, /* TX BD */
0, /* rx Index */
0, /* tx Index */
0, /* tx buffer */
0, /* initialized flag */
(struct fec_info_dma *)-1, /* next */
FEC1_RX_TASK, /* rxTask */
FEC1_TX_TASK, /* txTask */
FEC1_RX_PRIORITY, /* rxPri */
FEC1_TX_PRIORITY, /* txPri */
FEC1_RX_INIT, /* rxInit */
FEC1_TX_INIT, /* txInit */
0, /* usedTbdIndex */
0, /* cleanTbdNum */
}
#endif
};
static int fec_send(struct eth_device *dev, volatile void *packet, int length);
static int fec_recv(struct eth_device *dev);
static int fec_init(struct eth_device *dev, bd_t * bd);
static void fec_halt(struct eth_device *dev);
#ifdef ET_DEBUG
static void dbg_fec_regs(struct eth_device *dev)
{
struct fec_info_dma *info = dev->priv;
volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
printf("=====\n");
printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
}
#endif
static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
int dup_spd)
{
if ((dup_spd >> 16) == FULL) {
/* Set maximum frame length */
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
FEC_RCR_PROM | 0x100;
fecp->tcr = FEC_TCR_FDEN;
} else {
/* Half duplex mode */
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
FEC_RCR_MII_MODE | FEC_RCR_DRT;
fecp->tcr &= ~FEC_TCR_FDEN;
}
if ((dup_spd & 0xFFFF) == _100BASET) {
#ifdef MII_DEBUG
printf("100Mbps\n");
#endif
bd->bi_ethspeed = 100;
} else {
#ifdef MII_DEBUG
printf("10Mbps\n");
#endif
bd->bi_ethspeed = 10;
}
}
static int fec_send(struct eth_device *dev, volatile void *packet, int length)
{
struct fec_info_dma *info = dev->priv;
cbd_t *pTbd, *pUsedTbd;
u16 phyStatus;
miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
/* process all the consumed TBDs */
while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
pUsedTbd = &info->txbd[info->usedTbdIdx];
if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
#ifdef ET_DEBUG
printf("Cannot clean TBD %d, in use\n",
info->cleanTbdNum);
#endif
return 0;
}
/* clean this buffer descriptor */
if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
else
pUsedTbd->cbd_sc = 0;
/* update some indeces for a correct handling of the TBD ring */
info->cleanTbdNum++;
info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
}
/* Check for valid length of data. */
if ((length > 1500) || (length <= 0)) {
return -1;
}
/* Check the number of vacant TxBDs. */
if (info->cleanTbdNum < 1) {
printf("No available TxBDs ...\n");
return -1;
}
/* Get the first TxBD to send the mac header */
pTbd = &info->txbd[info->txIdx];
pTbd->cbd_datlen = length;
pTbd->cbd_bufaddr = (u32) packet;
pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
/* Enable DMA transmit task */
MCD_continDma(info->txTask);
info->cleanTbdNum -= 1;
/* wait until frame is sent . */
while (pTbd->cbd_sc & BD_ENET_TX_READY) {
udelay(10);
}
return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
}
static int fec_recv(struct eth_device *dev)
{
struct fec_info_dma *info = dev->priv;
volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
cbd_t *pRbd = &info->rxbd[info->rxIdx];
u32 ievent;
int frame_length, len = 0;
/* Check if any critical events have happened */
ievent = fecp->eir;
if (ievent != 0) {
fecp->eir = ievent;
if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
printf("fec_recv: error\n");
fec_halt(dev);
fec_init(dev, NULL);
return 0;
}
if (ievent & FEC_EIR_HBERR) {
/* Heartbeat error */
fecp->tcr |= FEC_TCR_GTS;
}
if (ievent & FEC_EIR_GRA) {
/* Graceful stop complete */
if (fecp->tcr & FEC_TCR_GTS) {
printf("fec_recv: tcr_gts\n");
fec_halt(dev);
fecp->tcr &= ~FEC_TCR_GTS;
fec_init(dev, NULL);
}
}
}
if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) {
if ((pRbd->cbd_sc & BD_ENET_RX_LAST)
&& !(pRbd->cbd_sc & BD_ENET_RX_ERR)
&& ((pRbd->cbd_datlen - 4) > 14)) {
/* Get buffer address and size */
frame_length = pRbd->cbd_datlen - 4;
/* Fill the buffer and pass it to upper layers */
NetReceive((volatile uchar *)pRbd->cbd_bufaddr,
frame_length);
len = frame_length;
}
/* Reset buffer descriptor as empty */
if ((info->rxIdx) == (PKTBUFSRX - 1))
pRbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
else
pRbd->cbd_sc = BD_ENET_RX_EMPTY;
pRbd->cbd_datlen = PKTSIZE_ALIGN;
/* Now, we have an empty RxBD, restart the DMA receive task */
MCD_continDma(info->rxTask);
/* Increment BD count */
info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
}
return len;
}
static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
{
u8 currByte; /* byte for which to compute the CRC */
int byte; /* loop - counter */
int bit; /* loop - counter */
u32 crc = 0xffffffff; /* initial value */
for (byte = 0; byte < 6; byte++) {
currByte = mac[byte];
for (bit = 0; bit < 8; bit++) {
if ((currByte & 0x01) ^ (crc & 0x01)) {
crc >>= 1;
crc = crc ^ 0xedb88320;
} else {
crc >>= 1;
}
currByte >>= 1;
}
}
crc = crc >> 26;
/* Set individual hash table register */
if (crc >= 32) {
fecp->ialr = (1 << (crc - 32));
fecp->iaur = 0;
} else {
fecp->ialr = 0;
fecp->iaur = (1 << crc);
}
/* Set physical address */
fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
/* Clear multicast address hash table */
fecp->gaur = 0;
fecp->galr = 0;
}
static int fec_init(struct eth_device *dev, bd_t * bd)
{
struct fec_info_dma *info = dev->priv;
volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
int i;
uchar enetaddr[6];
#ifdef ET_DEBUG
printf("fec_init: iobase 0x%08x ...\n", info->iobase);
#endif
fecpin_setclear(dev, 1);
fec_halt(dev);
#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
defined (CONFIG_SYS_DISCOVER_PHY)
mii_init();
set_fec_duplex_speed(fecp, bd, info->dup_spd);
#else
#ifndef CONFIG_SYS_DISCOVER_PHY
set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
#endif /* CONFIG_CMD_MII || CONFIG_MII */
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set station address */
if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
eth_getenv_enetaddr("ethaddr", enetaddr);
else
eth_getenv_enetaddr("eth1addr", enetaddr);
fec_set_hwaddr(fecp, enetaddr);
/* Set Opcode/Pause Duration Register */
fecp->opd = 0x00010020;
/* Setup Buffers and Buffer Desriptors */
info->rxIdx = 0;
info->txIdx = 0;
/* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings: Empty, Wrap */
for (i = 0; i < PKTBUFSRX; i++) {
info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
}
info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Settings: Last, Tx CRC */
for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
info->txbd[i].cbd_sc = 0;
info->txbd[i].cbd_datlen = 0;
info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
}
info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
info->usedTbdIdx = 0;
info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
/* Set Rx FIFO alarm and granularity value */
fecp->rfcr = 0x0c000000;
fecp->rfar = 0x0000030c;
/* Set Tx FIFO granularity value */
fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
fecp->tfar = 0x00000080;
fecp->tfwr = 0x2;
fecp->ctcwr = 0x03000000;
/* Enable DMA receive task */
MCD_startDma(info->rxTask, /* Dma channel */
(s8 *) info->rxbd, /*Source Address */
0, /* Source increment */
(s8 *) (&fecp->rfdr), /* dest */
4, /* dest increment */
0, /* DMA size */
4, /* xfer size */
info->rxInit, /* initiator */
info->rxPri, /* priority */
(MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
(MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
);
/* Enable DMA tx task with no ready buffer descriptors */
MCD_startDma(info->txTask, /* Dma channel */
(s8 *) info->txbd, /*Source Address */
0, /* Source increment */
(s8 *) (&fecp->tfdr), /* dest */
4, /* dest incr */
0, /* DMA size */
4, /* xfer size */
info->txInit, /* initiator */
info->txPri, /* priority */
(MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
(MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
);
/* Now enable the transmit and receive processing */
fecp->ecr |= FEC_ECR_ETHER_EN;
return 1;
}
static void fec_halt(struct eth_device *dev)
{
struct fec_info_dma *info = dev->priv;
volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
int counter = 0xffff;
/* issue graceful stop command to the FEC transmitter if necessary */
fecp->tcr |= FEC_TCR_GTS;
/* wait for graceful stop to register */
while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
/* Disable DMA tasks */
MCD_killDma(info->txTask);
MCD_killDma(info->rxTask);;
/* Disable the Ethernet Controller */
fecp->ecr &= ~FEC_ECR_ETHER_EN;
/* Clear FIFO status registers */
fecp->rfsr &= FIFO_ERRSTAT;
fecp->tfsr &= FIFO_ERRSTAT;
fecp->frst = 0x01000000;
/* Issue a reset command to the FEC chip */
fecp->ecr |= FEC_ECR_RESET;
/* wait at least 20 clock cycles */
udelay(10000);
#ifdef ET_DEBUG
printf("Ethernet task stopped\n");
#endif
}
int mcdmafec_initialize(bd_t * bis)
{
struct eth_device *dev;
int i;
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
#endif
for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
dev =
(struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
sizeof *dev);
if (dev == NULL)
hang();
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "FEC%d", fec_info[i].index);
dev->priv = &fec_info[i];
dev->init = fec_init;
dev->halt = fec_halt;
dev->send = fec_send;
dev->recv = fec_recv;
/* setup Receive and Transmit buffer descriptor */
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
tmp = (u32)fec_info[i].rxbd;
fec_info[i].txbd =
(cbd_t *)((u32)fec_info[i].txbd + tmp +
(PKTBUFSRX * sizeof(cbd_t)));
tmp = (u32)fec_info[i].txbd;
fec_info[i].txbuf =
(char *)((u32)fec_info[i].txbuf + tmp +
(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
tmp = (u32)fec_info[i].txbuf;
#else
fec_info[i].rxbd =
(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
(PKTBUFSRX * sizeof(cbd_t)));
fec_info[i].txbd =
(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
fec_info[i].txbuf =
(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif
#ifdef ET_DEBUG
printf("rxbd %x txbd %x\n",
(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
#endif
fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name,
mcffec_miiphy_read, mcffec_miiphy_write);
#endif
if (i > 0)
fec_info[i - 1].next = &fec_info[i];
}
fec_info[i - 1].next = &fec_info[0];
/* default speed */
bis->bi_ethspeed = 10;
return 0;
}
|
1001-study-uboot
|
drivers/net/fsl_mcdmafec.c
|
C
|
gpl3
| 16,651
|
/*
* Vitesse 7385 Switch Firmware Upload
*
* Author: Timur Tabi <timur@freescale.com>
*
* Copyright 2008 Freescale Semiconductor, Inc. This file is licensed
* under the terms of the GNU General Public License version 2. This
* program is licensed "as is" without any warranty of any kind, whether
* express or implied.
*
* This module uploads proprietary firmware for the Vitesse VSC7385 5-port
* switch.
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
/*
* Upload a Vitesse VSC7385 firmware image to the hardware
*
* This function takes a pointer to a VSC7385 firmware image and a size, and
* uploads that firmware to the VSC7385.
*
* This firmware is typically located at a board-specific flash address,
* and the size is typically 8KB.
*
* The firmware is Vitesse proprietary.
*
* Further details on the register information can be obtained from Vitesse.
*/
int vsc7385_upload_firmware(void *firmware, unsigned int size)
{
u8 *fw = firmware;
unsigned int i;
u32 *gloreset = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c050);
u32 *icpu_ctrl = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c040);
u32 *icpu_addr = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c044);
u32 *icpu_data = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c048);
u32 *icpu_rom_map = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c070);
#ifdef DEBUG
u32 *chipid = (u32 *) (CONFIG_SYS_VSC7385_BASE + 0x1c060);
#endif
out_be32(gloreset, 3);
udelay(200);
out_be32(icpu_ctrl, 0x8E);
udelay(20);
out_be32(icpu_rom_map, 1);
udelay(20);
/* Write the firmware to I-RAM */
out_be32(icpu_addr, 0);
udelay(20);
for (i = 0; i < size; i++) {
out_be32(icpu_data, fw[i]);
udelay(20);
if (ctrlc())
return -EINTR;
}
/* Read back and compare */
out_be32(icpu_addr, 0);
udelay(20);
for (i = 0; i < size; i++) {
u8 value;
value = (u8) in_be32(icpu_data);
udelay(20);
if (value != fw[i]) {
debug("VSC7385: Upload mismatch: address 0x%x, "
"read value 0x%x, image value 0x%x\n",
i, value, fw[i]);
return -EIO;
}
if (ctrlc())
break;
}
out_be32(icpu_ctrl, 0x0B);
udelay(20);
#ifdef DEBUG
printf("VSC7385: Chip ID is %08x\n", in_be32(chipid));
udelay(20);
#endif
return 0;
}
|
1001-study-uboot
|
drivers/net/vsc7385.c
|
C
|
gpl3
| 2,242
|
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#include <common.h>
#include <net.h>
#include <malloc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/types.h>
#include <asm/byteorder.h>
#include <linux/err.h>
#include <linux/mii.h>
#include <asm/io.h>
#include <asm/arch/armada100.h>
#include "armada100_fec.h"
#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
#ifdef DEBUG
static int eth_dump_regs(struct eth_device *dev)
{
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
unsigned int i = 0;
printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
printf("offset: smi, value: 0x%x\n", readl(®s->smi));
for (i = 0x400; i <= 0x4e4; i += 4)
printf("offset: 0x%x, value: 0x%x\n",
i, readl(ARMD1_FEC_BASE + i));
return 0;
}
#endif
static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
{
u32 timeout = PHY_WAIT_ITERATIONS;
u32 reg_val;
while (--timeout) {
reg_val = readl(reg);
if (cond && (reg_val & flag))
break;
else if (!cond && !(reg_val & flag))
break;
udelay(PHY_WAIT_MICRO_SECONDS);
}
return !timeout;
}
static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
u16 *value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
u32 val;
if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
val = readl(®s->phyadr);
*value = val & 0x1f;
return 0;
}
/* check parameters */
if (phy_addr > PHY_MASK) {
printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
__func__, phy_addr);
return -EINVAL;
}
if (phy_reg > PHY_MASK) {
printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
__func__, phy_reg);
return -EINVAL;
}
/* wait for the SMI register to become available */
if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
return -1;
}
writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi);
/* now wait for the data to be valid */
if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, TRUE)) {
val = readl(®s->smi);
printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
__func__, val);
return -1;
}
val = readl(®s->smi);
*value = val & 0xffff;
return 0;
}
static int smi_reg_write(const char *devname,
u8 phy_addr, u8 phy_reg, u16 value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f);
return 0;
}
/* check parameters */
if (phy_addr > PHY_MASK) {
printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
return -EINVAL;
}
if (phy_reg > PHY_MASK) {
printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
return -EINVAL;
}
/* wait for the SMI register to become available */
if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) {
printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
return -1;
}
writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
®s->smi);
return 0;
}
/*
* Abort any transmit and receive operations and put DMA
* in idle state. AT and AR bits are cleared upon entering
* in IDLE state. So poll those bits to verify operation.
*/
static void abortdma(struct eth_device *dev)
{
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
int delay;
int maxretries = 40;
u32 tmp;
while (--maxretries) {
writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
udelay(100);
delay = 10;
while (--delay) {
tmp = readl(®s->sdma_cmd);
if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
break;
udelay(10);
}
if (delay)
break;
}
if (!maxretries)
printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
}
static inline u32 nibble_swapping_32_bit(u32 x)
{
return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
}
static inline u32 nibble_swapping_16_bit(u32 x)
{
return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
}
static inline u32 flip_4_bits(u32 x)
{
return ((x & 0x01) << 3) | ((x & 0x002) << 1)
| ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
}
/*
* This function will calculate the hash function of the address.
* depends on the hash mode and hash size.
* Inputs
* mach - the 2 most significant bytes of the MAC address.
* macl - the 4 least significant bytes of the MAC address.
* Outputs
* return the calculated entry.
*/
static u32 hash_function(u32 mach, u32 macl)
{
u32 hashresult;
u32 addrh;
u32 addrl;
u32 addr0;
u32 addr1;
u32 addr2;
u32 addr3;
u32 addrhswapped;
u32 addrlswapped;
addrh = nibble_swapping_16_bit(mach);
addrl = nibble_swapping_32_bit(macl);
addrhswapped = flip_4_bits(addrh & 0xf)
+ ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
+ ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
+ ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
addrlswapped = flip_4_bits(addrl & 0xf)
+ ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
+ ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
+ ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
+ ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
+ ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
+ ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
+ ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
addrh = addrhswapped;
addrl = addrlswapped;
addr0 = (addrl >> 2) & 0x03f;
addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
addr2 = (addrl >> 15) & 0x1ff;
addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
hashresult = hashresult & 0x07ff;
return hashresult;
}
/*
* This function will add an entry to the address table.
* depends on the hash mode and hash size that was initialized.
* Inputs
* mach - the 2 most significant bytes of the MAC address.
* macl - the 4 least significant bytes of the MAC address.
* skip - if 1, skip this address.
* rd - the RD field in the address table.
* Outputs
* address table entry is added.
* 0 if success.
* -ENOSPC if table full
*/
static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
u32 macl, u32 rd, u32 skip, int del)
{
struct addr_table_entry_t *entry, *start;
u32 newhi;
u32 newlo;
u32 i;
newlo = (((mach >> 4) & 0xf) << 15)
| (((mach >> 0) & 0xf) << 11)
| (((mach >> 12) & 0xf) << 7)
| (((mach >> 8) & 0xf) << 3)
| (((macl >> 20) & 0x1) << 31)
| (((macl >> 16) & 0xf) << 27)
| (((macl >> 28) & 0xf) << 23)
| (((macl >> 24) & 0xf) << 19)
| (skip << HTESKIP) | (rd << HTERDBIT)
| HTEVALID;
newhi = (((macl >> 4) & 0xf) << 15)
| (((macl >> 0) & 0xf) << 11)
| (((macl >> 12) & 0xf) << 7)
| (((macl >> 8) & 0xf) << 3)
| (((macl >> 21) & 0x7) << 0);
/*
* Pick the appropriate table, start scanning for free/reusable
* entries at the index obtained by hashing the specified MAC address
*/
start = (struct addr_table_entry_t *)(darmdfec->htpr);
entry = start + hash_function(mach, macl);
for (i = 0; i < HOP_NUMBER; i++) {
if (!(entry->lo & HTEVALID)) {
break;
} else {
/* if same address put in same position */
if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
&& (entry->hi == newhi))
break;
}
if (entry == start + 0x7ff)
entry = start;
else
entry++;
}
if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
(entry->hi != newhi) && del)
return 0;
if (i == HOP_NUMBER) {
if (!del) {
printf("ARMD100 FEC: (%s) table section is full\n",
__func__);
return -ENOSPC;
} else {
return 0;
}
}
/*
* Update the selected entry
*/
if (del) {
entry->hi = 0;
entry->lo = 0;
} else {
entry->hi = newhi;
entry->lo = newlo;
}
return 0;
}
/*
* Create an addressTable entry from MAC address info
* found in the specifed net_device struct
*
* Input : pointer to ethernet interface network device structure
* Output : N/A
*/
static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
u8 *oaddr, u8 *addr)
{
u32 mach;
u32 macl;
/* Delete old entry */
if (oaddr) {
mach = (oaddr[0] << 8) | oaddr[1];
macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
(oaddr[4] << 8) | oaddr[5];
add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
}
/* Add new entry */
mach = (addr[0] << 8) | addr[1];
macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
}
/* Address Table Initialization */
static void init_hashtable(struct eth_device *dev)
{
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
writel((u32)darmdfec->htpr, ®s->htpr);
}
/*
* This detects PHY chip from address 0-31 by reading PHY status
* registers. PHY chip can be connected at any of this address.
*/
static int ethernet_phy_detect(struct eth_device *dev)
{
u32 val;
u16 tmp, mii_status;
u8 addr;
for (addr = 0; addr < 32; addr++) {
if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
/* try next phy */
continue;
/* invalid MII status. More validation required here... */
if (mii_status == 0 || mii_status == 0xffff)
/* try next phy */
continue;
if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
/* try next phy */
continue;
val = tmp << 16;
if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
/* try next phy */
continue;
val |= tmp;
if ((val & 0xfffffff0) != 0)
return addr;
}
return -1;
}
static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
{
struct rx_desc *p_rx_desc;
int i;
/* initialize the Rx descriptors ring */
p_rx_desc = darmdfec->p_rxdesc;
for (i = 0; i < RINGSZ; i++) {
p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
p_rx_desc->buf_size = PKTSIZE_ALIGN;
p_rx_desc->byte_cnt = 0;
p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
if (i == (RINGSZ - 1)) {
p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
} else {
p_rx_desc->nxtdesc_p = (struct rx_desc *)
((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
p_rx_desc = p_rx_desc->nxtdesc_p;
}
}
darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
}
static int armdfec_init(struct eth_device *dev, bd_t *bd)
{
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
int phy_adr;
u32 temp;
armdfec_init_rx_desc_ring(darmdfec);
/* Disable interrupts */
writel(0, ®s->im);
writel(0, ®s->ic);
/* Write to ICR to clear interrupts. */
writel(0, ®s->iwc);
/*
* Abort any transmit and receive operations and put DMA
* in idle state.
*/
abortdma(dev);
/* Initialize address hash table */
init_hashtable(dev);
/* SDMA configuration */
writel(SDCR_BSZ8 | /* Burst size = 32 bytes */
SDCR_RIFB | /* Rx interrupt on frame */
SDCR_BLMT | /* Little endian transmit */
SDCR_BLMR | /* Little endian receive */
SDCR_RC_MAX_RETRANS, /* Max retransmit count */
®s->sdma_conf);
/* Port Configuration */
writel(PCR_HS, ®s->pconf); /* Hash size is 1/2kb */
/* Set extended port configuration */
writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */
PCXR_DSCP_EN | /* Enable DSCP in IP */
PCXR_MFL_1536 | /* Set MTU = 1536 */
PCXR_FLP | /* do not force link pass */
PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
®s->pconf_ext);
update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
/* Update TX and RX queue descriptor register */
temp = (u32)®s->txcdp[TXQ];
writel((u32)darmdfec->p_txdesc, temp);
temp = (u32)®s->rxfdp[RXQ];
writel((u32)darmdfec->p_rxdesc, temp);
temp = (u32)®s->rxcdp[RXQ];
writel((u32)darmdfec->p_rxdesc_curr, temp);
/* Enable Interrupts */
writel(ALL_INTS, ®s->im);
/* Enable Ethernet Port */
setbits_le32(®s->pconf, PCR_EN);
/* Enable RX DMA engine */
setbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
#ifdef DEBUG
eth_dump_regs(dev);
#endif
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#if defined(CONFIG_PHY_BASE_ADR)
miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
#else
/* Search phy address from range 0-31 */
phy_adr = ethernet_phy_detect(dev);
if (phy_adr < 0) {
printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
return -1;
} else {
debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
}
#endif
#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
/* Wait up to 5s for the link status */
for (i = 0; i < 5; i++) {
u16 phy_adr;
miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
/* Return if we get link up */
if (miiphy_link(dev->name, phy_adr))
return 0;
udelay(1000000);
}
printf("ARMD100 FEC: No link on %s\n", dev->name);
return -1;
#endif
#endif
return 0;
}
static void armdfec_halt(struct eth_device *dev)
{
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
/* Stop RX DMA */
clrbits_le32(®s->sdma_cmd, SDMA_CMD_ERD);
/*
* Abort any transmit and receive operations and put DMA
* in idle state.
*/
abortdma(dev);
/* Disable interrupts */
writel(0, ®s->im);
writel(0, ®s->ic);
writel(0, ®s->iwc);
/* Disable Port */
clrbits_le32(®s->pconf, PCR_EN);
}
static int armdfec_send(struct eth_device *dev, volatile void *dataptr,
int datasize)
{
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
struct tx_desc *p_txdesc = darmdfec->p_txdesc;
void *p = (void *)dataptr;
int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
u32 cmd_sts;
/* Copy buffer if it's misaligned */
if ((u32)dataptr & 0x07) {
if (datasize > PKTSIZE_ALIGN) {
printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
datasize);
return -1;
}
memcpy(darmdfec->p_aligned_txbuf, p, datasize);
p = darmdfec->p_aligned_txbuf;
}
p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
p_txdesc->cmd_sts |= TX_EN_INT;
p_txdesc->buf_ptr = p;
p_txdesc->byte_cnt = datasize;
/* Apply send command using high priority TX queue */
writel((u32)p_txdesc, ®s->txcdp[TXQ]);
writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, ®s->sdma_cmd);
/*
* wait for packet xmit completion
*/
cmd_sts = readl(&p_txdesc->cmd_sts);
while (cmd_sts & BUF_OWNED_BY_DMA) {
/* return fail if error is detected */
if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
(TX_ERROR | TX_LAST_DESC)) {
printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
return -1;
}
cmd_sts = readl(&p_txdesc->cmd_sts);
if (!(retry--)) {
printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
__func__);
return -1;
}
}
return 0;
}
static int armdfec_recv(struct eth_device *dev)
{
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
u32 temp;
/* wait untill rx packet available or timeout */
do {
if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
timeout++;
} else {
debug("ARMD100 FEC: %s time out...\n", __func__);
return -1;
}
} while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
if (p_rxdesc_curr->byte_cnt != 0) {
debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
"(cmd_sts= %08x)\n", __func__,
(u32)p_rxdesc_curr->byte_cnt,
(u32)p_rxdesc_curr->buf_ptr,
(u32)p_rxdesc_curr->cmd_sts);
}
/*
* In case received a packet without first/last bits on
* OR the error summary bit is on,
* the packets needs to be dropeed.
*/
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
(RX_FIRST_DESC | RX_LAST_DESC)) {
printf("ARMD100 FEC: (%s) Dropping packet spread on"
" multiple descriptors\n", __func__);
} else if (cmd_sts & RX_ERROR) {
printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
__func__);
} else {
/* !!! call higher layer processing */
debug("ARMD100 FEC: (%s) Sending Received packet to"
" upper layer (NetReceive)\n", __func__);
/*
* let the upper layer handle the packet, subtract offset
* as two dummy bytes are added in received buffer see
* PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
*/
NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
(int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
}
/*
* free these descriptors and point next in the ring
*/
p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
temp = (u32)&darmdfec->p_rxdesc_curr;
writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
return 0;
}
int armada100_fec_register(unsigned long base_addr)
{
struct armdfec_device *darmdfec;
struct eth_device *dev;
darmdfec = malloc(sizeof(struct armdfec_device));
if (!darmdfec)
goto error;
memset(darmdfec, 0, sizeof(struct armdfec_device));
darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
if (!darmdfec->htpr)
goto error1;
darmdfec->p_rxdesc = memalign(PKTALIGN,
ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
if (!darmdfec->p_rxdesc)
goto error1;
darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
if (!darmdfec->p_rxbuf)
goto error1;
darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
if (!darmdfec->p_aligned_txbuf)
goto error1;
darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
if (!darmdfec->p_txdesc)
goto error1;
dev = &darmdfec->dev;
/* Assign ARMADA100 Fast Ethernet Controller Base Address */
darmdfec->regs = (void *)base_addr;
/* must be less than NAMESIZE (16) */
strcpy(dev->name, "armd-fec0");
dev->init = armdfec_init;
dev->halt = armdfec_halt;
dev->send = armdfec_send;
dev->recv = armdfec_recv;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, smi_reg_read, smi_reg_write);
#endif
return 0;
error1:
free(darmdfec->p_aligned_txbuf);
free(darmdfec->p_rxbuf);
free(darmdfec->p_rxdesc);
free(darmdfec->htpr);
error:
free(darmdfec);
printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
return -1;
}
|
1001-study-uboot
|
drivers/net/armada100_fec.c
|
C
|
gpl3
| 19,370
|
/*
* (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
* (C) Copyright 2008 Armadeus Systems, nc
* (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
* (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file is based on mpc4200fec.h
* (C) Copyright Motorola, Inc., 2000
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __FEC_MXC_H
#define __FEC_MXC_H
void imx_get_mac_from_fuse(unsigned char *mac);
/**
* Layout description of the FEC
*/
struct ethernet_regs {
/* [10:2]addr = 00 */
/* Control and status Registers (offset 000-1FF) */
uint32_t res0[1]; /* MBAR_ETH + 0x000 */
uint32_t ievent; /* MBAR_ETH + 0x004 */
uint32_t imask; /* MBAR_ETH + 0x008 */
uint32_t res1[1]; /* MBAR_ETH + 0x00C */
uint32_t r_des_active; /* MBAR_ETH + 0x010 */
uint32_t x_des_active; /* MBAR_ETH + 0x014 */
uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
uint32_t ecntrl; /* MBAR_ETH + 0x024 */
uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
uint32_t mii_data; /* MBAR_ETH + 0x040 */
uint32_t mii_speed; /* MBAR_ETH + 0x044 */
uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */
uint32_t mib_control; /* MBAR_ETH + 0x064 */
uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */
uint32_t r_cntrl; /* MBAR_ETH + 0x084 */
uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */
uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */
uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */
uint32_t paddr1; /* MBAR_ETH + 0x0E4 */
uint32_t paddr2; /* MBAR_ETH + 0x0E8 */
uint32_t op_pause; /* MBAR_ETH + 0x0EC */
uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */
uint32_t iaddr1; /* MBAR_ETH + 0x118 */
uint32_t iaddr2; /* MBAR_ETH + 0x11C */
uint32_t gaddr1; /* MBAR_ETH + 0x120 */
uint32_t gaddr2; /* MBAR_ETH + 0x124 */
uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */
uint32_t x_wmrk; /* MBAR_ETH + 0x144 */
uint32_t res10[1]; /* MBAR_ETH + 0x148 */
uint32_t r_bound; /* MBAR_ETH + 0x14C */
uint32_t r_fstart; /* MBAR_ETH + 0x150 */
uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */
uint32_t erdsr; /* MBAR_ETH + 0x180 */
uint32_t etdsr; /* MBAR_ETH + 0x184 */
uint32_t emrbr; /* MBAR_ETH + 0x188 */
uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */
/* MIB COUNTERS (Offset 200-2FF) */
uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */
uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */
uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */
uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */
uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */
uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */
uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */
uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */
uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */
uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */
uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */
uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */
uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */
uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */
uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */
uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */
uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */
uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */
uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */
uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */
uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */
uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */
uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */
uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */
uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */
uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */
uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */
uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */
uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */
uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */
uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */
uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */
uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */
uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */
uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */
uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */
uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */
uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */
uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */
uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */
#else
uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
#endif
};
#define FEC_IEVENT_HBERR 0x80000000
#define FEC_IEVENT_BABR 0x40000000
#define FEC_IEVENT_BABT 0x20000000
#define FEC_IEVENT_GRA 0x10000000
#define FEC_IEVENT_TXF 0x08000000
#define FEC_IEVENT_TXB 0x04000000
#define FEC_IEVENT_RXF 0x02000000
#define FEC_IEVENT_RXB 0x01000000
#define FEC_IEVENT_MII 0x00800000
#define FEC_IEVENT_EBERR 0x00400000
#define FEC_IEVENT_LC 0x00200000
#define FEC_IEVENT_RL 0x00100000
#define FEC_IEVENT_UN 0x00080000
#define FEC_IMASK_HBERR 0x80000000
#define FEC_IMASK_BABR 0x40000000
#define FEC_IMASKT_BABT 0x20000000
#define FEC_IMASK_GRA 0x10000000
#define FEC_IMASKT_TXF 0x08000000
#define FEC_IMASK_TXB 0x04000000
#define FEC_IMASKT_RXF 0x02000000
#define FEC_IMASK_RXB 0x01000000
#define FEC_IMASK_MII 0x00800000
#define FEC_IMASK_EBERR 0x00400000
#define FEC_IMASK_LC 0x00200000
#define FEC_IMASKT_RL 0x00100000
#define FEC_IMASK_UN 0x00080000
#define FEC_RCNTRL_MAX_FL_SHIFT 16
#define FEC_RCNTRL_LOOP 0x00000001
#define FEC_RCNTRL_DRT 0x00000002
#define FEC_RCNTRL_MII_MODE 0x00000004
#define FEC_RCNTRL_PROM 0x00000008
#define FEC_RCNTRL_BC_REJ 0x00000010
#define FEC_RCNTRL_FCE 0x00000020
#define FEC_RCNTRL_RMII 0x00000100
#define FEC_TCNTRL_GTS 0x00000001
#define FEC_TCNTRL_HBC 0x00000002
#define FEC_TCNTRL_FDEN 0x00000004
#define FEC_TCNTRL_TFC_PAUSE 0x00000008
#define FEC_TCNTRL_RFC_PAUSE 0x00000010
#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
/* defines for MIIGSK */
/* RMII frequency control: 0=50MHz, 1=5MHz */
#define MIIGSK_CFGR_FRCONT (1 << 6)
/* loopback mode */
#define MIIGSK_CFGR_LBMODE (1 << 4)
/* echo mode */
#define MIIGSK_CFGR_EMODE (1 << 3)
/* MII gasket mode field */
#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
/* MMI/7-Wire mode */
#define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
/* RMII mode */
#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
/* reflects MIIGSK Enable bit (RO) */
#define MIIGSK_ENR_READY (1 << 2)
/* enable MIGSK (set by default) */
#define MIIGSK_ENR_EN (1 << 1)
#endif
/**
* @brief Descriptor buffer alignment
*
* i.MX27 requires a 16 byte alignment (but for the first element only)
*/
#define DB_ALIGNMENT 16
/**
* @brief Data buffer alignment
*
* i.MX27 requires a four byte alignment for transmit and 16 bits
* alignment for receive so take 16
* Note: Valid for member data_pointer in struct buffer_descriptor
*/
#define DB_DATA_ALIGNMENT 16
/**
* @brief Receive & Transmit Buffer Descriptor definitions
*
* Note: The first BD must be aligned (see DB_ALIGNMENT)
*/
struct fec_bd {
uint16_t data_length; /* payload's length in bytes */
uint16_t status; /* BD's staus (see datasheet) */
uint32_t data_pointer; /* payload's buffer address */
};
/**
* Supported phy types on this platform
*/
enum xceiver_type {
SEVENWIRE, /* 7-wire */
MII10, /* MII 10Mbps */
MII100, /* MII 100Mbps */
RMII /* RMII */
};
/**
* @brief i.MX27-FEC private structure
*/
struct fec_priv {
struct ethernet_regs *eth; /* pointer to register'S base */
enum xceiver_type xcv_type; /* transceiver type */
struct fec_bd *rbd_base; /* RBD ring */
int rbd_index; /* next receive BD to read */
struct fec_bd *tbd_base; /* TBD ring */
int tbd_index; /* next transmit BD to write */
bd_t *bd;
void *rdb_ptr;
void *base_ptr;
int dev_id;
int phy_id;
int (*mii_postcall)(int);
};
/**
* @brief Numbers of buffer descriptors for receiving
*
* The number defines the stocked memory buffers for the receiving task.
* Larger values makes no sense in this limited environment.
*/
#define FEC_RBD_NUM 64
/**
* @brief Define the ethernet packet size limit in memory
*
* Note: Do not shrink this number. This will force the FEC to spread larger
* frames in more than one BD. This is nothing to worry about, but the current
* driver can't handle it.
*/
#define FEC_MAX_PKT_SIZE 1536
/* Receive BD status bits */
#define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */
#define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */
/* Receive BD status: Buffer is last in frame (useless here!) */
#define FEC_RBD_LAST 0x0800
#define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */
/* Receive BD status: The received frame is broadcast frame */
#define FEC_RBD_BC 0x0080
/* Receive BD status: The received frame is multicast frame */
#define FEC_RBD_MC 0x0040
#define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */
#define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */
#define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */
#define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */
#define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */
#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
FEC_RBD_OV | FEC_RBD_TR)
/* Transmit BD status bits */
#define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */
#define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */
#define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */
#define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */
#define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */
/* MII-related definitios */
#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
#endif /* __FEC_MXC_H */
|
1001-study-uboot
|
drivers/net/fec_mxc.h
|
C
|
gpl3
| 12,202
|
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <stdio_dev.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
static char input_buffer[512];
static int input_size = 0; /* char count in input buffer */
static int input_offset = 0; /* offset to valid chars in input buffer */
static int input_recursion = 0;
static int output_recursion = 0;
static int net_timeout;
static uchar nc_ether[6]; /* server enet address */
static IPaddr_t nc_ip; /* server ip */
static short nc_port; /* source/target port */
static const char *output_packet; /* used by first send udp */
static int output_packet_len = 0;
static void nc_wait_arp_handler(uchar *pkt, unsigned dest,
IPaddr_t sip, unsigned src,
unsigned len)
{
NetState = NETLOOP_SUCCESS; /* got arp reply - quit net loop */
}
static void nc_handler(uchar *pkt, unsigned dest, IPaddr_t sip, unsigned src,
unsigned len)
{
if (input_size)
NetState = NETLOOP_SUCCESS; /* got input - quit net loop */
}
static void nc_timeout (void)
{
NetState = NETLOOP_SUCCESS;
}
void NcStart (void)
{
if (!output_packet_len || memcmp (nc_ether, NetEtherNullAddr, 6)) {
/* going to check for input packet */
NetSetHandler (nc_handler);
NetSetTimeout (net_timeout, nc_timeout);
} else {
/* send arp request */
uchar *pkt;
NetSetHandler (nc_wait_arp_handler);
pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE;
memcpy (pkt, output_packet, output_packet_len);
NetSendUDPPacket (nc_ether, nc_ip, nc_port, nc_port, output_packet_len);
}
}
int nc_input_packet (uchar * pkt, unsigned dest, unsigned src, unsigned len)
{
int end, chunk;
if (dest != nc_port || !len)
return 0; /* not for us */
if (input_size == sizeof input_buffer)
return 1; /* no space */
if (len > sizeof input_buffer - input_size)
len = sizeof input_buffer - input_size;
end = input_offset + input_size;
if (end > sizeof input_buffer)
end -= sizeof input_buffer;
chunk = len;
if (end + len > sizeof input_buffer) {
chunk = sizeof input_buffer - end;
memcpy(input_buffer, pkt + chunk, len - chunk);
}
memcpy (input_buffer + end, pkt, chunk);
input_size += len;
return 1;
}
static void nc_send_packet (const char *buf, int len)
{
struct eth_device *eth;
int inited = 0;
uchar *pkt;
uchar *ether;
IPaddr_t ip;
if ((eth = eth_get_dev ()) == NULL) {
return;
}
if (!memcmp (nc_ether, NetEtherNullAddr, 6)) {
if (eth->state == ETH_STATE_ACTIVE)
return; /* inside net loop */
output_packet = buf;
output_packet_len = len;
NetLoop (NETCONS); /* wait for arp reply and send packet */
output_packet_len = 0;
return;
}
if (eth->state != ETH_STATE_ACTIVE) {
if (eth_init (gd->bd) < 0)
return;
inited = 1;
}
pkt = (uchar *) NetTxPacket + NetEthHdrSize () + IP_HDR_SIZE;
memcpy (pkt, buf, len);
ether = nc_ether;
ip = nc_ip;
NetSendUDPPacket (ether, ip, nc_port, nc_port, len);
if (inited)
eth_halt ();
}
static int nc_start(void)
{
int netmask, our_ip;
nc_port = 6666; /* default port */
if (getenv ("ncip")) {
char *p;
nc_ip = getenv_IPaddr ("ncip");
if (!nc_ip)
return -1; /* ncip is 0.0.0.0 */
if ((p = strchr (getenv ("ncip"), ':')) != NULL)
nc_port = simple_strtoul (p + 1, NULL, 10);
} else
nc_ip = ~0; /* ncip is not set */
our_ip = getenv_IPaddr ("ipaddr");
netmask = getenv_IPaddr ("netmask");
if (nc_ip == ~0 || /* 255.255.255.255 */
((netmask & our_ip) == (netmask & nc_ip) && /* on the same net */
(netmask | nc_ip) == ~0)) /* broadcast to our net */
memset (nc_ether, 0xff, sizeof nc_ether);
else
memset (nc_ether, 0, sizeof nc_ether); /* force arp request */
return 0;
}
static void nc_putc(char c)
{
if (output_recursion)
return;
output_recursion = 1;
nc_send_packet (&c, 1);
output_recursion = 0;
}
static void nc_puts(const char *s)
{
int len;
if (output_recursion)
return;
output_recursion = 1;
len = strlen(s);
while (len) {
int send_len = min(len, 512);
nc_send_packet(s, send_len);
len -= send_len;
s += send_len;
}
output_recursion = 0;
}
static int nc_getc(void)
{
uchar c;
input_recursion = 1;
net_timeout = 0; /* no timeout */
while (!input_size)
NetLoop (NETCONS);
input_recursion = 0;
c = input_buffer[input_offset++];
if (input_offset >= sizeof input_buffer)
input_offset -= sizeof input_buffer;
input_size--;
return c;
}
static int nc_tstc(void)
{
struct eth_device *eth;
if (input_recursion)
return 0;
if (input_size)
return 1;
eth = eth_get_dev ();
if (eth && eth->state == ETH_STATE_ACTIVE)
return 0; /* inside net loop */
input_recursion = 1;
net_timeout = 1;
NetLoop (NETCONS); /* kind of poll */
input_recursion = 0;
return input_size != 0;
}
int drv_nc_init (void)
{
struct stdio_dev dev;
int rc;
memset (&dev, 0, sizeof (dev));
strcpy (dev.name, "nc");
dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
dev.start = nc_start;
dev.putc = nc_putc;
dev.puts = nc_puts;
dev.getc = nc_getc;
dev.tstc = nc_tstc;
rc = stdio_register (&dev);
return (rc == 0) ? 1 : rc;
}
|
1001-study-uboot
|
drivers/net/netconsole.c
|
C
|
gpl3
| 5,951
|
/*
* Driver for Blackfin On-Chip MAC device
*
* Copyright (c) 2005-2008 Analog Device, Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <common.h>
#include <config.h>
#include <net.h>
#include <netdev.h>
#include <command.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mii.h>
#include <asm/blackfin.h>
#include <asm/portmux.h>
#include <asm/mach-common/bits/dma.h>
#include <asm/mach-common/bits/emac.h>
#include <asm/mach-common/bits/pll.h>
#include "bfin_mac.h"
#ifndef CONFIG_PHY_ADDR
# define CONFIG_PHY_ADDR 1
#endif
#ifndef CONFIG_PHY_CLOCK_FREQ
# define CONFIG_PHY_CLOCK_FREQ 2500000
#endif
#ifdef CONFIG_POST
#include <post.h>
#endif
#define RXBUF_BASE_ADDR 0xFF900000
#define TXBUF_BASE_ADDR 0xFF800000
#define TX_BUF_CNT 1
#define TOUT_LOOP 1000000
static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
static u16 txIdx; /* index of the current RX buffer */
static u16 rxIdx; /* index of the current TX buffer */
/* DMAx_CONFIG values at DMA Restart */
static const union {
u16 data;
ADI_DMA_CONFIG_REG reg;
} txdmacfg = {
.reg = {
.b_DMA_EN = 1, /* enabled */
.b_WNR = 0, /* read from memory */
.b_WDSIZE = 2, /* wordsize is 32 bits */
.b_DMA2D = 0,
.b_RESTART = 0,
.b_DI_SEL = 0,
.b_DI_EN = 0, /* no interrupt */
.b_NDSIZE = 5, /* 5 half words is desc size */
.b_FLOW = 7 /* large desc flow */
},
};
static int bfin_miiphy_wait(void)
{
/* poll the STABUSY bit */
while (bfin_read_EMAC_STAADD() & STABUSY)
continue;
return 0;
}
static int bfin_miiphy_read(const char *devname, uchar addr, uchar reg, ushort *val)
{
if (bfin_miiphy_wait())
return 1;
bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
if (bfin_miiphy_wait())
return 1;
*val = bfin_read_EMAC_STADAT();
return 0;
}
static int bfin_miiphy_write(const char *devname, uchar addr, uchar reg, ushort val)
{
if (bfin_miiphy_wait())
return 1;
bfin_write_EMAC_STADAT(val);
bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
return 0;
}
int bfin_EMAC_initialize(bd_t *bis)
{
struct eth_device *dev;
dev = malloc(sizeof(*dev));
if (dev == NULL)
hang();
memset(dev, 0, sizeof(*dev));
strcpy(dev->name, "bfin_mac");
dev->iobase = 0;
dev->priv = 0;
dev->init = bfin_EMAC_init;
dev->halt = bfin_EMAC_halt;
dev->send = bfin_EMAC_send;
dev->recv = bfin_EMAC_recv;
dev->write_hwaddr = bfin_EMAC_setup_addr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
#endif
return 0;
}
static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet,
int length)
{
int i;
int result = 0;
unsigned int *buf;
buf = (unsigned int *)packet;
if (length <= 0) {
printf("Ethernet: bad packet size: %d\n", length);
goto out;
}
if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
printf("Ethernet: tx DMA error\n");
goto out;
}
for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx time out\n");
goto out;
}
}
txbuf[txIdx]->FrmData->NoBytes = length;
memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
bfin_write_DMA2_CONFIG(txdmacfg.data);
bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
if (i > TOUT_LOOP) {
puts("Ethernet: tx error\n");
goto out;
}
}
result = txbuf[txIdx]->StatusWord;
txbuf[txIdx]->StatusWord = 0;
if ((txIdx + 1) >= TX_BUF_CNT)
txIdx = 0;
else
txIdx++;
out:
debug("BFIN EMAC send: length = %d\n", length);
return result;
}
static int bfin_EMAC_recv(struct eth_device *dev)
{
int length = 0;
for (;;) {
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
length = -1;
break;
}
if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
printf("Ethernet: rx dma overrun\n");
break;
}
if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
printf("Ethernet: rx error\n");
break;
}
length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
if (length <= 4) {
printf("Ethernet: bad frame\n");
break;
}
debug("%s: len = %d\n", __func__, length - 4);
NetRxPackets[rxIdx] =
(volatile uchar *)(rxbuf[rxIdx]->FrmData->Dest);
NetReceive(NetRxPackets[rxIdx], length - 4);
bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
rxbuf[rxIdx]->StatusWord = 0x00000000;
if ((rxIdx + 1) >= PKTBUFSRX)
rxIdx = 0;
else
rxIdx++;
}
return length;
}
/**************************************************************
*
* Ethernet Initialization Routine
*
*************************************************************/
/* MDC = SCLK / MDC_freq / 2 - 1 */
#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
#ifndef CONFIG_BFIN_MAC_PINS
# ifdef CONFIG_RMII
# define CONFIG_BFIN_MAC_PINS P_RMII0
# else
# define CONFIG_BFIN_MAC_PINS P_MII0
# endif
#endif
static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
{
const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
u16 phydat;
size_t count;
/* Enable PHY output */
bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
/* Set all the pins to peripheral mode */
peripheral_request_list(pins, "bfin_mac");
/* Odd word alignment for Receive Frame DMA word */
/* Configure checksum support and rcve frame word alignment */
bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
/* turn on auto-negotiation and wait for link to come up */
bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
count = 0;
while (1) {
++count;
if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
return -1;
if (phydat & BMSR_LSTATUS)
break;
if (count > 30000) {
printf("%s: link down, check cable\n", dev->name);
return -1;
}
udelay(100);
}
/* see what kind of link we have */
if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
return -1;
if (phydat & LPA_DUPLEX)
*opmode = FDMODE;
else
*opmode = 0;
bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
/* Initialize the TX DMA channel registers */
bfin_write_DMA2_X_COUNT(0);
bfin_write_DMA2_X_MODIFY(4);
bfin_write_DMA2_Y_COUNT(0);
bfin_write_DMA2_Y_MODIFY(0);
/* Initialize the RX DMA channel registers */
bfin_write_DMA1_X_COUNT(0);
bfin_write_DMA1_X_MODIFY(4);
bfin_write_DMA1_Y_COUNT(0);
bfin_write_DMA1_Y_MODIFY(0);
return 0;
}
static int bfin_EMAC_setup_addr(struct eth_device *dev)
{
bfin_write_EMAC_ADDRLO(
dev->enetaddr[0] |
dev->enetaddr[1] << 8 |
dev->enetaddr[2] << 16 |
dev->enetaddr[3] << 24
);
bfin_write_EMAC_ADDRHI(
dev->enetaddr[4] |
dev->enetaddr[5] << 8
);
return 0;
}
static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
{
u32 opmode;
int dat;
int i;
debug("Eth_init: ......\n");
txIdx = 0;
rxIdx = 0;
/* Initialize System Register */
if (bfin_miiphy_init(dev, &dat) < 0)
return -1;
/* Initialize EMAC address */
bfin_EMAC_setup_addr(dev);
/* Initialize TX and RX buffer */
for (i = 0; i < PKTBUFSRX; i++) {
rxbuf[i] = SetupRxBuffer(i);
if (i > 0) {
rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
if (i == (PKTBUFSRX - 1))
rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
}
}
for (i = 0; i < TX_BUF_CNT; i++) {
txbuf[i] = SetupTxBuffer(i);
if (i > 0) {
txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
if (i == (TX_BUF_CNT - 1))
txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
}
}
/* Set RX DMA */
bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
/* Wait MII done */
bfin_miiphy_wait();
/* We enable only RX here */
/* ASTP : Enable Automatic Pad Stripping
PR : Promiscuous Mode for test
PSF : Receive frames with total length less than 64 bytes.
FDMODE : Full Duplex Mode
LB : Internal Loopback for test
RE : Receiver Enable */
if (dat == FDMODE)
opmode = ASTP | FDMODE | PSF;
else
opmode = ASTP | PSF;
opmode |= RE;
#ifdef CONFIG_RMII
opmode |= TE | RMII;
#endif
/* Turn on the EMAC */
bfin_write_EMAC_OPMODE(opmode);
return 0;
}
static void bfin_EMAC_halt(struct eth_device *dev)
{
debug("Eth_halt: ......\n");
/* Turn off the EMAC */
bfin_write_EMAC_OPMODE(0);
/* Turn off the EMAC RX DMA */
bfin_write_DMA1_CONFIG(0);
bfin_write_DMA2_CONFIG(0);
}
ADI_ETHER_BUFFER *SetupRxBuffer(int no)
{
ADI_ETHER_FRAME_BUFFER *frmbuf;
ADI_ETHER_BUFFER *buf;
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
memset(frmbuf, 0xfe, RECV_BUFSIZE);
/* set up first desc to point to receive frame buffer */
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
/* set up second desc to point to status word */
buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
return buf;
}
ADI_ETHER_BUFFER *SetupTxBuffer(int no)
{
ADI_ETHER_FRAME_BUFFER *frmbuf;
ADI_ETHER_BUFFER *buf;
int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
int total_size = nobytes_buffer + RECV_BUFSIZE;
buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
memset(buf, 0x00, nobytes_buffer);
buf->FrmData = frmbuf;
memset(frmbuf, 0x00, RECV_BUFSIZE);
/* set up first desc to point to receive frame buffer */
buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
buf->Dma[0].START_ADDR = (u32) buf->FrmData;
buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
/* set up second desc to point to status word */
buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
return buf;
}
#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
int ether_post_test(int flags)
{
uchar buf[64];
int i, value = 0;
int length;
uint addr;
printf("\n--------");
bfin_EMAC_init(NULL, NULL);
/* construct the package */
addr = bfin_read_EMAC_ADDRLO();
buf[0] = buf[6] = addr;
buf[1] = buf[7] = addr >> 8;
buf[2] = buf[8] = addr >> 16;
buf[3] = buf[9] = addr >> 24;
addr = bfin_read_EMAC_ADDRHI();
buf[4] = buf[10] = addr;
buf[5] = buf[11] = addr >> 8;
buf[12] = 0x08; /* Type: ARP */
buf[13] = 0x06;
buf[14] = 0x00; /* Hardware type: Ethernet */
buf[15] = 0x01;
buf[16] = 0x08; /* Protocal type: IP */
buf[17] = 0x00;
buf[18] = 0x06; /* Hardware size */
buf[19] = 0x04; /* Protocol size */
buf[20] = 0x00; /* Opcode: request */
buf[21] = 0x01;
for (i = 0; i < 42; i++)
buf[i + 22] = i;
printf("--------Send 64 bytes......\n");
bfin_EMAC_send(NULL, (volatile void *)buf, 64);
for (i = 0; i < 100; i++) {
udelay(10000);
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
value = 1;
break;
}
}
if (value == 0) {
printf("--------EMAC can't receive any data\n");
eth_halt();
return -1;
}
length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
for (i = 0; i < length; i++) {
if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
printf("--------EMAC receive error data!\n");
eth_halt();
return -1;
}
}
printf("--------receive %d bytes, matched\n", length);
bfin_EMAC_halt(NULL);
return 0;
}
#endif
|
1001-study-uboot
|
drivers/net/bfin_mac.c
|
C
|
gpl3
| 12,706
|
/*
* AX88796L(NE2000) support
*
* (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __DRIVERS_AX88796L_H__
#define __DRIVERS_AX88796L_H__
#define DP_DATA (0x10 << 1)
#define START_PG 0x40 /* First page of TX buffer */
#define START_PG2 0x48
#define STOP_PG 0x80 /* Last page +1 of RX ring */
#define TX_PAGES 12
#define RX_START (START_PG+TX_PAGES)
#define RX_END STOP_PG
#define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE
#define AX88796L_BYTE_ACCESS 0x00001000
#define AX88796L_OFFSET 0x00000400
#define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \
AX88796L_BYTE_ACCESS + AX88796L_OFFSET
#define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1)
#define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1)
#define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR))
#define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR))
#define EECS_HIGH (AX88796L_MEMR |= 0x10)
#define EECS_LOW (AX88796L_MEMR &= 0xef)
#define EECLK_HIGH (AX88796L_MEMR |= 0x80)
#define EECLK_LOW (AX88796L_MEMR &= 0x7f)
#define EEDI_HIGH (AX88796L_MEMR |= 0x20)
#define EEDI_LOW (AX88796L_MEMR &= 0xdf)
#define EEDO ((AX88796L_MEMR & 0x40)>>6)
#define PAGE0_SET (AX88796L_CR &= 0x3f)
#define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40)
#define BIT_DUMMY 0
#define MAC_EEP_READ 1
#define MAC_EEP_WRITE 2
#define MAC_EEP_ERACE 3
#define MAC_EEP_EWEN 4
#define MAC_EEP_EWDS 5
/* R7780MP Specific code */
#if defined(CONFIG_R7780MP)
#define ISA_OFFSET 0x1400
#define DP_IN(_b_, _o_, _d_) (_d_) = \
*( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET))
#define DP_OUT(_b_, _o_, _d_) \
*((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_)
#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET))
#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
#else
/* Please change for your target boards */
#define ISA_OFFSET 0x0000
#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET))
#define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_)
#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET))
#define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_)
#endif
#endif /* __DRIVERS_AX88796L_H__ */
|
1001-study-uboot
|
drivers/net/ax88796.h
|
C
|
gpl3
| 2,956
|
/*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file is based on mpc4200fec.h
* (C) Copyright Motorola, Inc., 2000
*
* odin ethernet header file
*/
#ifndef __MPC5XXX_FEC_H
#define __MPC5XXX_FEC_H
typedef unsigned long uint32;
typedef unsigned short uint16;
typedef unsigned char uint8;
typedef struct ethernet_register_set {
/* [10:2]addr = 00 */
/* Control and status Registers (offset 000-1FF) */
volatile uint32 fec_id; /* MBAR_ETH + 0x000 */
volatile uint32 ievent; /* MBAR_ETH + 0x004 */
volatile uint32 imask; /* MBAR_ETH + 0x008 */
volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */
volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */
volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */
volatile uint32 r_des_active_cl; /* MBAR_ETH + 0x018 */
volatile uint32 x_des_active_cl; /* MBAR_ETH + 0x01C */
volatile uint32 ivent_set; /* MBAR_ETH + 0x020 */
volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */
volatile uint32 RES1[6]; /* MBAR_ETH + 0x028-03C */
volatile uint32 mii_data; /* MBAR_ETH + 0x040 */
volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */
volatile uint32 mii_status; /* MBAR_ETH + 0x048 */
volatile uint32 RES2[5]; /* MBAR_ETH + 0x04C-05C */
volatile uint32 mib_data; /* MBAR_ETH + 0x060 */
volatile uint32 mib_control; /* MBAR_ETH + 0x064 */
volatile uint32 RES3[6]; /* MBAR_ETH + 0x068-7C */
volatile uint32 r_activate; /* MBAR_ETH + 0x080 */
volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */
volatile uint32 r_hash; /* MBAR_ETH + 0x088 */
volatile uint32 r_data; /* MBAR_ETH + 0x08C */
volatile uint32 ar_done; /* MBAR_ETH + 0x090 */
volatile uint32 r_test; /* MBAR_ETH + 0x094 */
volatile uint32 r_mib; /* MBAR_ETH + 0x098 */
volatile uint32 r_da_low; /* MBAR_ETH + 0x09C */
volatile uint32 r_da_high; /* MBAR_ETH + 0x0A0 */
volatile uint32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */
volatile uint32 x_activate; /* MBAR_ETH + 0x0C0 */
volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */
volatile uint32 backoff; /* MBAR_ETH + 0x0C8 */
volatile uint32 x_data; /* MBAR_ETH + 0x0CC */
volatile uint32 x_status; /* MBAR_ETH + 0x0D0 */
volatile uint32 x_mib; /* MBAR_ETH + 0x0D4 */
volatile uint32 x_test; /* MBAR_ETH + 0x0D8 */
volatile uint32 fdxfc_da1; /* MBAR_ETH + 0x0DC */
volatile uint32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */
volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */
volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */
volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */
volatile uint32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */
volatile uint32 instr_reg; /* MBAR_ETH + 0x100 */
volatile uint32 context_reg; /* MBAR_ETH + 0x104 */
volatile uint32 test_cntrl; /* MBAR_ETH + 0x108 */
volatile uint32 acc_reg; /* MBAR_ETH + 0x10C */
volatile uint32 ones; /* MBAR_ETH + 0x110 */
volatile uint32 zeros; /* MBAR_ETH + 0x114 */
volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */
volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */
volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */
volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */
volatile uint32 random; /* MBAR_ETH + 0x128 */
volatile uint32 rand1; /* MBAR_ETH + 0x12C */
volatile uint32 tmp; /* MBAR_ETH + 0x130 */
volatile uint32 RES6[3]; /* MBAR_ETH + 0x134-13C */
volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */
volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */
volatile uint32 fcntrl; /* MBAR_ETH + 0x148 */
volatile uint32 r_bound; /* MBAR_ETH + 0x14C */
volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */
volatile uint32 r_count; /* MBAR_ETH + 0x154 */
volatile uint32 r_lag; /* MBAR_ETH + 0x158 */
volatile uint32 r_read; /* MBAR_ETH + 0x15C */
volatile uint32 r_write; /* MBAR_ETH + 0x160 */
volatile uint32 x_count; /* MBAR_ETH + 0x164 */
volatile uint32 x_lag; /* MBAR_ETH + 0x168 */
volatile uint32 x_retry; /* MBAR_ETH + 0x16C */
volatile uint32 x_write; /* MBAR_ETH + 0x170 */
volatile uint32 x_read; /* MBAR_ETH + 0x174 */
volatile uint32 RES7[2]; /* MBAR_ETH + 0x178-17C */
volatile uint32 fm_cntrl; /* MBAR_ETH + 0x180 */
volatile uint32 rfifo_data; /* MBAR_ETH + 0x184 */
volatile uint32 rfifo_status; /* MBAR_ETH + 0x188 */
volatile uint32 rfifo_cntrl; /* MBAR_ETH + 0x18C */
volatile uint32 rfifo_lrf_ptr; /* MBAR_ETH + 0x190 */
volatile uint32 rfifo_lwf_ptr; /* MBAR_ETH + 0x194 */
volatile uint32 rfifo_alarm; /* MBAR_ETH + 0x198 */
volatile uint32 rfifo_rdptr; /* MBAR_ETH + 0x19C */
volatile uint32 rfifo_wrptr; /* MBAR_ETH + 0x1A0 */
volatile uint32 tfifo_data; /* MBAR_ETH + 0x1A4 */
volatile uint32 tfifo_status; /* MBAR_ETH + 0x1A8 */
volatile uint32 tfifo_cntrl; /* MBAR_ETH + 0x1AC */
volatile uint32 tfifo_lrf_ptr; /* MBAR_ETH + 0x1B0 */
volatile uint32 tfifo_lwf_ptr; /* MBAR_ETH + 0x1B4 */
volatile uint32 tfifo_alarm; /* MBAR_ETH + 0x1B8 */
volatile uint32 tfifo_rdptr; /* MBAR_ETH + 0x1BC */
volatile uint32 tfifo_wrptr; /* MBAR_ETH + 0x1C0 */
volatile uint32 reset_cntrl; /* MBAR_ETH + 0x1C4 */
volatile uint32 xmit_fsm; /* MBAR_ETH + 0x1C8 */
volatile uint32 RES8[3]; /* MBAR_ETH + 0x1CC-1D4 */
volatile uint32 rdes_data0; /* MBAR_ETH + 0x1D8 */
volatile uint32 rdes_data1; /* MBAR_ETH + 0x1DC */
volatile uint32 r_length; /* MBAR_ETH + 0x1E0 */
volatile uint32 x_length; /* MBAR_ETH + 0x1E4 */
volatile uint32 x_addr; /* MBAR_ETH + 0x1E8 */
volatile uint32 cdes_data; /* MBAR_ETH + 0x1EC */
volatile uint32 status; /* MBAR_ETH + 0x1F0 */
volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */
volatile uint32 des_cmnd; /* MBAR_ETH + 0x1F8 */
volatile uint32 data; /* MBAR_ETH + 0x1FC */
/* MIB COUNTERS (Offset 200-2FF) */
volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */
volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */
volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */
volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */
volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */
volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */
volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */
volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */
volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */
volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */
volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */
volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */
volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */
volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */
volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */
volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */
volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */
volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */
volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */
volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */
volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */
volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */
volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */
volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
volatile uint32 RES9[2]; /* MBAR_ETH + 0x278-27C */
volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */
volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */
volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */
volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */
volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */
volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */
volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */
volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */
volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */
volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */
volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */
volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */
volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */
volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */
volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
volatile uint32 RES10[6]; /* MBAR_ETH + 0x2E4-2FC */
volatile uint32 RES11[64]; /* MBAR_ETH + 0x300-3FF */
} ethernet_regs;
/* Receive & Transmit Buffer Descriptor definitions */
typedef struct BufferDescriptor {
uint16 status;
uint16 dataLength;
uint32 dataPointer;
} FEC_RBD;
typedef struct {
uint16 status;
uint16 dataLength;
uint32 dataPointer;
} FEC_TBD;
/* private structure */
typedef enum {
SEVENWIRE, /* 7-wire */
MII10, /* MII 10Mbps */
MII100 /* MII 100Mbps */
} xceiver_type;
typedef struct {
ethernet_regs *eth;
xceiver_type xcv_type; /* transceiver type */
FEC_RBD *rbdBase; /* RBD ring */
FEC_TBD *tbdBase; /* TBD ring */
uint16 rbdIndex; /* next receive BD to read */
uint16 tbdIndex; /* next transmit BD to send */
uint16 usedTbdIndex; /* next transmit BD to clean */
uint16 cleanTbdNum; /* the number of available transmit BDs */
} mpc5xxx_fec_priv;
/* Ethernet parameter area */
#define FEC_TBD_BASE (FEC_PARAM_BASE + 0x00)
#define FEC_TBD_NEXT (FEC_PARAM_BASE + 0x04)
#define FEC_RBD_BASE (FEC_PARAM_BASE + 0x08)
#define FEC_RBD_NEXT (FEC_PARAM_BASE + 0x0c)
/* BD Numer definitions */
#define FEC_TBD_NUM 48 /* The user can adjust this value */
#define FEC_RBD_NUM 32 /* The user can adjust this value */
/* packet size limit */
#define FEC_MAX_PKT_SIZE 1536
/* RBD bits definitions */
#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
#define FEC_RBD_INT 0x1000 /* Interrupt */
#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
#define FEC_RBD_LG 0x0020 /* Frame length violation */
#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
#define FEC_RBD_SH 0x0008 /* Short frame */
#define FEC_RBD_CR 0x0004 /* CRC error */
#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
#define FEC_RBD_TR 0x0001 /* Frame is truncated */
#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
FEC_RBD_OV | FEC_RBD_TR)
/* TBD bits definitions */
#define FEC_TBD_READY 0x8000 /* Buffer is ready */
#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
#define FEC_TBD_INT 0x1000 /* Interrupt */
#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
#define FEC_TBD_TC 0x0400 /* Transmit the CRC */
#define FEC_TBD_ABC 0x0200 /* Append bad CRC */
/* MII-related definitios */
#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
#endif /* __MPC5XXX_FEC_H */
|
1001-study-uboot
|
drivers/net/mpc5xxx_fec.h
|
C
|
gpl3
| 11,951
|
/**************************************************************************
Intel Pro 1000 for ppcboot/das-u-boot
Drivers are port from Intel's Linux driver e1000-4.3.15
and from Etherboot pro 1000 driver by mrakes at vivato dot net
tested on both gig copper and gig fiber boards
***************************************************************************/
/*******************************************************************************
Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/*
* Copyright (C) Archway Digital Solutions.
*
* written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
* 2/9/2002
*
* Copyright (C) Linux Networx.
* Massive upgrade to work with the new intel gigabit NICs.
* <ebiederman at lnxi dot com>
*
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include "e1000.h"
#define TOUT_LOOP 100000
#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
#define E1000_DEFAULT_PCI_PBA 0x00000030
#define E1000_DEFAULT_PCIE_PBA 0x000a0026
/* NIC specific static variables go here */
static char tx_pool[128 + 16];
static char rx_pool[128 + 16];
static char packet[2096];
static struct e1000_tx_desc *tx_base;
static struct e1000_rx_desc *rx_base;
static int tx_tail;
static int rx_tail, rx_last;
static struct pci_device_id e1000_supported[] = {
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
/* E1000 PCIe card */
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
{}
};
/* Function forward declarations */
static int e1000_setup_link(struct eth_device *nic);
static int e1000_setup_fiber_link(struct eth_device *nic);
static int e1000_setup_copper_link(struct eth_device *nic);
static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
static void e1000_config_collision_dist(struct e1000_hw *hw);
static int e1000_config_mac_to_phy(struct e1000_hw *hw);
static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
static int e1000_check_for_link(struct eth_device *nic);
static int e1000_wait_autoneg(struct e1000_hw *hw);
static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
uint16_t * duplex);
static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
uint16_t * phy_data);
static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
uint16_t phy_data);
static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
static int e1000_phy_reset(struct e1000_hw *hw);
static int e1000_detect_gig_phy(struct e1000_hw *hw);
static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
static void e1000_set_media_type(struct e1000_hw *hw);
static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
#ifndef CONFIG_AP1000 /* remove for warnings */
static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
uint16_t words,
uint16_t *data);
/******************************************************************************
* Raises the EEPROM's clock input.
*
* hw - Struct containing variables accessed by shared code
* eecd - EECD's current value
*****************************************************************************/
void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
{
/* Raise the clock input to the EEPROM (by setting the SK bit), and then
* wait 50 microseconds.
*/
*eecd = *eecd | E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, *eecd);
E1000_WRITE_FLUSH(hw);
udelay(50);
}
/******************************************************************************
* Lowers the EEPROM's clock input.
*
* hw - Struct containing variables accessed by shared code
* eecd - EECD's current value
*****************************************************************************/
void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
{
/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
* wait 50 microseconds.
*/
*eecd = *eecd & ~E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, *eecd);
E1000_WRITE_FLUSH(hw);
udelay(50);
}
/******************************************************************************
* Shift data bits out to the EEPROM.
*
* hw - Struct containing variables accessed by shared code
* data - data to send to the EEPROM
* count - number of bits to shift out
*****************************************************************************/
static void
e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
{
uint32_t eecd;
uint32_t mask;
/* We need to shift "count" bits out to the EEPROM. So, value in the
* "data" parameter will be shifted out to the EEPROM one bit at a time.
* In order to do this, "data" must be broken down into bits.
*/
mask = 0x01 << (count - 1);
eecd = E1000_READ_REG(hw, EECD);
eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
do {
/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
* and then raising and then lowering the clock (the SK bit controls
* the clock input to the EEPROM). A "0" is shifted out to the EEPROM
* by setting "DI" to "0" and then raising and then lowering the clock.
*/
eecd &= ~E1000_EECD_DI;
if (data & mask)
eecd |= E1000_EECD_DI;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(50);
e1000_raise_ee_clk(hw, &eecd);
e1000_lower_ee_clk(hw, &eecd);
mask = mask >> 1;
} while (mask);
/* We leave the "DI" bit set to "0" when we leave this routine. */
eecd &= ~E1000_EECD_DI;
E1000_WRITE_REG(hw, EECD, eecd);
}
/******************************************************************************
* Shift data bits in from the EEPROM
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static uint16_t
e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
{
uint32_t eecd;
uint32_t i;
uint16_t data;
/* In order to read a register from the EEPROM, we need to shift 'count'
* bits in from the EEPROM. Bits are "shifted in" by raising the clock
* input to the EEPROM (setting the SK bit), and then reading the
* value of the "DO" bit. During this "shifting in" process the
* "DI" bit should always be clear.
*/
eecd = E1000_READ_REG(hw, EECD);
eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
data = 0;
for (i = 0; i < count; i++) {
data = data << 1;
e1000_raise_ee_clk(hw, &eecd);
eecd = E1000_READ_REG(hw, EECD);
eecd &= ~(E1000_EECD_DI);
if (eecd & E1000_EECD_DO)
data |= 1;
e1000_lower_ee_clk(hw, &eecd);
}
return data;
}
/******************************************************************************
* Returns EEPROM to a "standby" state
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
void e1000_standby_eeprom(struct e1000_hw *hw)
{
struct e1000_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd;
eecd = E1000_READ_REG(hw, EECD);
if (eeprom->type == e1000_eeprom_microwire) {
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(eeprom->delay_usec);
/* Clock high */
eecd |= E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(eeprom->delay_usec);
/* Select EEPROM */
eecd |= E1000_EECD_CS;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(eeprom->delay_usec);
/* Clock low */
eecd &= ~E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(eeprom->delay_usec);
} else if (eeprom->type == e1000_eeprom_spi) {
/* Toggle CS to flush commands */
eecd |= E1000_EECD_CS;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(eeprom->delay_usec);
eecd &= ~E1000_EECD_CS;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(eeprom->delay_usec);
}
}
/***************************************************************************
* Description: Determines if the onboard NVM is FLASH or EEPROM.
*
* hw - Struct containing variables accessed by shared code
****************************************************************************/
static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
{
uint32_t eecd = 0;
DEBUGFUNC();
if (hw->mac_type == e1000_ich8lan)
return FALSE;
if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
eecd = E1000_READ_REG(hw, EECD);
/* Isolate bits 15 & 16 */
eecd = ((eecd >> 15) & 0x03);
/* If both bits are set, device is Flash type */
if (eecd == 0x03)
return FALSE;
}
return TRUE;
}
/******************************************************************************
* Prepares EEPROM for access
*
* hw - Struct containing variables accessed by shared code
*
* Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
* function should be called before issuing a command to the EEPROM.
*****************************************************************************/
int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
{
struct e1000_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd, i = 0;
DEBUGFUNC();
if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
return -E1000_ERR_SWFW_SYNC;
eecd = E1000_READ_REG(hw, EECD);
if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
/* Request EEPROM Access */
if (hw->mac_type > e1000_82544) {
eecd |= E1000_EECD_REQ;
E1000_WRITE_REG(hw, EECD, eecd);
eecd = E1000_READ_REG(hw, EECD);
while ((!(eecd & E1000_EECD_GNT)) &&
(i < E1000_EEPROM_GRANT_ATTEMPTS)) {
i++;
udelay(5);
eecd = E1000_READ_REG(hw, EECD);
}
if (!(eecd & E1000_EECD_GNT)) {
eecd &= ~E1000_EECD_REQ;
E1000_WRITE_REG(hw, EECD, eecd);
DEBUGOUT("Could not acquire EEPROM grant\n");
return -E1000_ERR_EEPROM;
}
}
}
/* Setup EEPROM for Read/Write */
if (eeprom->type == e1000_eeprom_microwire) {
/* Clear SK and DI */
eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
E1000_WRITE_REG(hw, EECD, eecd);
/* Set CS */
eecd |= E1000_EECD_CS;
E1000_WRITE_REG(hw, EECD, eecd);
} else if (eeprom->type == e1000_eeprom_spi) {
/* Clear SK and CS */
eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
E1000_WRITE_REG(hw, EECD, eecd);
udelay(1);
}
return E1000_SUCCESS;
}
/******************************************************************************
* Sets up eeprom variables in the hw struct. Must be called after mac_type
* is configured. Additionally, if this is ICH8, the flash controller GbE
* registers must be mapped, or this will crash.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
{
struct e1000_eeprom_info *eeprom = &hw->eeprom;
uint32_t eecd = E1000_READ_REG(hw, EECD);
int32_t ret_val = E1000_SUCCESS;
uint16_t eeprom_size;
DEBUGFUNC();
switch (hw->mac_type) {
case e1000_82542_rev2_0:
case e1000_82542_rev2_1:
case e1000_82543:
case e1000_82544:
eeprom->type = e1000_eeprom_microwire;
eeprom->word_size = 64;
eeprom->opcode_bits = 3;
eeprom->address_bits = 6;
eeprom->delay_usec = 50;
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
break;
case e1000_82540:
case e1000_82545:
case e1000_82545_rev_3:
case e1000_82546:
case e1000_82546_rev_3:
eeprom->type = e1000_eeprom_microwire;
eeprom->opcode_bits = 3;
eeprom->delay_usec = 50;
if (eecd & E1000_EECD_SIZE) {
eeprom->word_size = 256;
eeprom->address_bits = 8;
} else {
eeprom->word_size = 64;
eeprom->address_bits = 6;
}
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
break;
case e1000_82541:
case e1000_82541_rev_2:
case e1000_82547:
case e1000_82547_rev_2:
if (eecd & E1000_EECD_TYPE) {
eeprom->type = e1000_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->page_size = 32;
eeprom->address_bits = 16;
} else {
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
} else {
eeprom->type = e1000_eeprom_microwire;
eeprom->opcode_bits = 3;
eeprom->delay_usec = 50;
if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->word_size = 256;
eeprom->address_bits = 8;
} else {
eeprom->word_size = 64;
eeprom->address_bits = 6;
}
}
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
break;
case e1000_82571:
case e1000_82572:
eeprom->type = e1000_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->page_size = 32;
eeprom->address_bits = 16;
} else {
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
break;
case e1000_82573:
case e1000_82574:
eeprom->type = e1000_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->page_size = 32;
eeprom->address_bits = 16;
} else {
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
eeprom->use_eerd = TRUE;
eeprom->use_eewr = TRUE;
if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
eeprom->type = e1000_eeprom_flash;
eeprom->word_size = 2048;
/* Ensure that the Autonomous FLASH update bit is cleared due to
* Flash update issue on parts which use a FLASH for NVM. */
eecd &= ~E1000_EECD_AUPDEN;
E1000_WRITE_REG(hw, EECD, eecd);
}
break;
case e1000_80003es2lan:
eeprom->type = e1000_eeprom_spi;
eeprom->opcode_bits = 8;
eeprom->delay_usec = 1;
if (eecd & E1000_EECD_ADDR_BITS) {
eeprom->page_size = 32;
eeprom->address_bits = 16;
} else {
eeprom->page_size = 8;
eeprom->address_bits = 8;
}
eeprom->use_eerd = TRUE;
eeprom->use_eewr = FALSE;
break;
/* ich8lan does not support currently. if needed, please
* add corresponding code and functions.
*/
#if 0
case e1000_ich8lan:
{
int32_t i = 0;
eeprom->type = e1000_eeprom_ich8;
eeprom->use_eerd = FALSE;
eeprom->use_eewr = FALSE;
eeprom->word_size = E1000_SHADOW_RAM_WORDS;
uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
ICH_FLASH_GFPREG);
/* Zero the shadow RAM structure. But don't load it from NVM
* so as to save time for driver init */
if (hw->eeprom_shadow_ram != NULL) {
for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
hw->eeprom_shadow_ram[i].modified = FALSE;
hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
}
}
hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
ICH_FLASH_SECTOR_SIZE;
hw->flash_bank_size = ((flash_size >> 16)
& ICH_GFPREG_BASE_MASK) + 1;
hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
hw->flash_bank_size /= 2 * sizeof(uint16_t);
break;
}
#endif
default:
break;
}
if (eeprom->type == e1000_eeprom_spi) {
/* eeprom_size will be an enum [0..8] that maps
* to eeprom sizes 128B to
* 32KB (incremented by powers of 2).
*/
if (hw->mac_type <= e1000_82547_rev_2) {
/* Set to default value for initial eeprom read. */
eeprom->word_size = 64;
ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
&eeprom_size);
if (ret_val)
return ret_val;
eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
>> EEPROM_SIZE_SHIFT;
/* 256B eeprom size was not supported in earlier
* hardware, so we bump eeprom_size up one to
* ensure that "1" (which maps to 256B) is never
* the result used in the shifting logic below. */
if (eeprom_size)
eeprom_size++;
} else {
eeprom_size = (uint16_t)((eecd &
E1000_EECD_SIZE_EX_MASK) >>
E1000_EECD_SIZE_EX_SHIFT);
}
eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
}
return ret_val;
}
/******************************************************************************
* Polls the status bit (bit 1) of the EERD to determine when the read is done.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static int32_t
e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
{
uint32_t attempts = 100000;
uint32_t i, reg = 0;
int32_t done = E1000_ERR_EEPROM;
for (i = 0; i < attempts; i++) {
if (eerd == E1000_EEPROM_POLL_READ)
reg = E1000_READ_REG(hw, EERD);
else
reg = E1000_READ_REG(hw, EEWR);
if (reg & E1000_EEPROM_RW_REG_DONE) {
done = E1000_SUCCESS;
break;
}
udelay(5);
}
return done;
}
/******************************************************************************
* Reads a 16 bit word from the EEPROM using the EERD register.
*
* hw - Struct containing variables accessed by shared code
* offset - offset of word in the EEPROM to read
* data - word read from the EEPROM
* words - number of words to read
*****************************************************************************/
static int32_t
e1000_read_eeprom_eerd(struct e1000_hw *hw,
uint16_t offset,
uint16_t words,
uint16_t *data)
{
uint32_t i, eerd = 0;
int32_t error = 0;
for (i = 0; i < words; i++) {
eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
E1000_EEPROM_RW_REG_START;
E1000_WRITE_REG(hw, EERD, eerd);
error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
if (error)
break;
data[i] = (E1000_READ_REG(hw, EERD) >>
E1000_EEPROM_RW_REG_DATA);
}
return error;
}
void e1000_release_eeprom(struct e1000_hw *hw)
{
uint32_t eecd;
DEBUGFUNC();
eecd = E1000_READ_REG(hw, EECD);
if (hw->eeprom.type == e1000_eeprom_spi) {
eecd |= E1000_EECD_CS; /* Pull CS high */
eecd &= ~E1000_EECD_SK; /* Lower SCK */
E1000_WRITE_REG(hw, EECD, eecd);
udelay(hw->eeprom.delay_usec);
} else if (hw->eeprom.type == e1000_eeprom_microwire) {
/* cleanup eeprom */
/* CS on Microwire is active-high */
eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
E1000_WRITE_REG(hw, EECD, eecd);
/* Rising edge of clock */
eecd |= E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(hw->eeprom.delay_usec);
/* Falling edge of clock */
eecd &= ~E1000_EECD_SK;
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(hw->eeprom.delay_usec);
}
/* Stop requesting EEPROM access */
if (hw->mac_type > e1000_82544) {
eecd &= ~E1000_EECD_REQ;
E1000_WRITE_REG(hw, EECD, eecd);
}
}
/******************************************************************************
* Reads a 16 bit word from the EEPROM.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static int32_t
e1000_spi_eeprom_ready(struct e1000_hw *hw)
{
uint16_t retry_count = 0;
uint8_t spi_stat_reg;
DEBUGFUNC();
/* Read "Status Register" repeatedly until the LSB is cleared. The
* EEPROM will signal that the command has been completed by clearing
* bit 0 of the internal status register. If it's not cleared within
* 5 milliseconds, then error out.
*/
retry_count = 0;
do {
e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
hw->eeprom.opcode_bits);
spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
break;
udelay(5);
retry_count += 5;
e1000_standby_eeprom(hw);
} while (retry_count < EEPROM_MAX_RETRY_SPI);
/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
* only 0-5mSec on 5V devices)
*/
if (retry_count >= EEPROM_MAX_RETRY_SPI) {
DEBUGOUT("SPI EEPROM Status error\n");
return -E1000_ERR_EEPROM;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Reads a 16 bit word from the EEPROM.
*
* hw - Struct containing variables accessed by shared code
* offset - offset of word in the EEPROM to read
* data - word read from the EEPROM
*****************************************************************************/
static int32_t
e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
uint16_t words, uint16_t *data)
{
struct e1000_eeprom_info *eeprom = &hw->eeprom;
uint32_t i = 0;
DEBUGFUNC();
/* If eeprom is not yet detected, do so now */
if (eeprom->word_size == 0)
e1000_init_eeprom_params(hw);
/* A check for invalid values: offset too large, too many words,
* and not enough words.
*/
if ((offset >= eeprom->word_size) ||
(words > eeprom->word_size - offset) ||
(words == 0)) {
DEBUGOUT("\"words\" parameter out of bounds."
"Words = %d, size = %d\n", offset, eeprom->word_size);
return -E1000_ERR_EEPROM;
}
/* EEPROM's that don't use EERD to read require us to bit-bang the SPI
* directly. In this case, we need to acquire the EEPROM so that
* FW or other port software does not interrupt.
*/
if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
hw->eeprom.use_eerd == FALSE) {
/* Prepare the EEPROM for bit-bang reading */
if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
return -E1000_ERR_EEPROM;
}
/* Eerd register EEPROM access requires no eeprom aquire/release */
if (eeprom->use_eerd == TRUE)
return e1000_read_eeprom_eerd(hw, offset, words, data);
/* ich8lan does not support currently. if needed, please
* add corresponding code and functions.
*/
#if 0
/* ICH EEPROM access is done via the ICH flash controller */
if (eeprom->type == e1000_eeprom_ich8)
return e1000_read_eeprom_ich8(hw, offset, words, data);
#endif
/* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
* acquired the EEPROM at this point, so any returns should relase it */
if (eeprom->type == e1000_eeprom_spi) {
uint16_t word_in;
uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
if (e1000_spi_eeprom_ready(hw)) {
e1000_release_eeprom(hw);
return -E1000_ERR_EEPROM;
}
e1000_standby_eeprom(hw);
/* Some SPI eeproms use the 8th address bit embedded in
* the opcode */
if ((eeprom->address_bits == 8) && (offset >= 128))
read_opcode |= EEPROM_A8_OPCODE_SPI;
/* Send the READ command (opcode + addr) */
e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
eeprom->address_bits);
/* Read the data. The address of the eeprom internally
* increments with each byte (spi) being read, saving on the
* overhead of eeprom setup and tear-down. The address
* counter will roll over if reading beyond the size of
* the eeprom, thus allowing the entire memory to be read
* starting from any offset. */
for (i = 0; i < words; i++) {
word_in = e1000_shift_in_ee_bits(hw, 16);
data[i] = (word_in >> 8) | (word_in << 8);
}
} else if (eeprom->type == e1000_eeprom_microwire) {
for (i = 0; i < words; i++) {
/* Send the READ command (opcode + addr) */
e1000_shift_out_ee_bits(hw,
EEPROM_READ_OPCODE_MICROWIRE,
eeprom->opcode_bits);
e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
eeprom->address_bits);
/* Read the data. For microwire, each word requires
* the overhead of eeprom setup and tear-down. */
data[i] = e1000_shift_in_ee_bits(hw, 16);
e1000_standby_eeprom(hw);
}
}
/* End this read operation */
e1000_release_eeprom(hw);
return E1000_SUCCESS;
}
/******************************************************************************
* Verifies that the EEPROM has a valid checksum
*
* hw - Struct containing variables accessed by shared code
*
* Reads the first 64 16 bit words of the EEPROM and sums the values read.
* If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
* valid.
*****************************************************************************/
static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
{
uint16_t i, checksum, checksum_reg, *buf;
DEBUGFUNC();
/* Allocate a temporary buffer */
buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
if (!buf) {
E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
return -E1000_ERR_EEPROM;
}
/* Read the EEPROM */
if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
return -E1000_ERR_EEPROM;
}
/* Compute the checksum */
checksum = 0;
for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
checksum += buf[i];
checksum = ((uint16_t)EEPROM_SUM) - checksum;
checksum_reg = buf[i];
/* Verify it! */
if (checksum == checksum_reg)
return 0;
/* Hrm, verification failed, print an error */
E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n",
checksum_reg, checksum);
return -E1000_ERR_EEPROM;
}
/*****************************************************************************
* Set PHY to class A mode
* Assumes the following operations will follow to enable the new class mode.
* 1. Do a PHY soft reset
* 2. Restart auto-negotiation or force link.
*
* hw - Struct containing variables accessed by shared code
****************************************************************************/
static int32_t
e1000_set_phy_mode(struct e1000_hw *hw)
{
int32_t ret_val;
uint16_t eeprom_data;
DEBUGFUNC();
if ((hw->mac_type == e1000_82545_rev_3) &&
(hw->media_type == e1000_media_type_copper)) {
ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1, &eeprom_data);
if (ret_val)
return ret_val;
if ((eeprom_data != EEPROM_RESERVED_WORD) &&
(eeprom_data & EEPROM_PHY_CLASS_A)) {
ret_val = e1000_write_phy_reg(hw,
M88E1000_PHY_PAGE_SELECT, 0x000B);
if (ret_val)
return ret_val;
ret_val = e1000_write_phy_reg(hw,
M88E1000_PHY_GEN_CONTROL, 0x8104);
if (ret_val)
return ret_val;
hw->phy_reset_disable = FALSE;
}
}
return E1000_SUCCESS;
}
#endif /* #ifndef CONFIG_AP1000 */
/***************************************************************************
*
* Obtaining software semaphore bit (SMBI) before resetting PHY.
*
* hw: Struct containing variables accessed by shared code
*
* returns: - E1000_ERR_RESET if fail to obtain semaphore.
* E1000_SUCCESS at any other case.
*
***************************************************************************/
static int32_t
e1000_get_software_semaphore(struct e1000_hw *hw)
{
int32_t timeout = hw->eeprom.word_size + 1;
uint32_t swsm;
DEBUGFUNC();
if (hw->mac_type != e1000_80003es2lan)
return E1000_SUCCESS;
while (timeout) {
swsm = E1000_READ_REG(hw, SWSM);
/* If SMBI bit cleared, it is now set and we hold
* the semaphore */
if (!(swsm & E1000_SWSM_SMBI))
break;
mdelay(1);
timeout--;
}
if (!timeout) {
DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
return -E1000_ERR_RESET;
}
return E1000_SUCCESS;
}
/***************************************************************************
* This function clears HW semaphore bits.
*
* hw: Struct containing variables accessed by shared code
*
* returns: - None.
*
***************************************************************************/
static void
e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
{
uint32_t swsm;
DEBUGFUNC();
if (!hw->eeprom_semaphore_present)
return;
swsm = E1000_READ_REG(hw, SWSM);
if (hw->mac_type == e1000_80003es2lan) {
/* Release both semaphores. */
swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
} else
swsm &= ~(E1000_SWSM_SWESMBI);
E1000_WRITE_REG(hw, SWSM, swsm);
}
/***************************************************************************
*
* Using the combination of SMBI and SWESMBI semaphore bits when resetting
* adapter or Eeprom access.
*
* hw: Struct containing variables accessed by shared code
*
* returns: - E1000_ERR_EEPROM if fail to access EEPROM.
* E1000_SUCCESS at any other case.
*
***************************************************************************/
static int32_t
e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
{
int32_t timeout;
uint32_t swsm;
DEBUGFUNC();
if (!hw->eeprom_semaphore_present)
return E1000_SUCCESS;
if (hw->mac_type == e1000_80003es2lan) {
/* Get the SW semaphore. */
if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
return -E1000_ERR_EEPROM;
}
/* Get the FW semaphore. */
timeout = hw->eeprom.word_size + 1;
while (timeout) {
swsm = E1000_READ_REG(hw, SWSM);
swsm |= E1000_SWSM_SWESMBI;
E1000_WRITE_REG(hw, SWSM, swsm);
/* if we managed to set the bit we got the semaphore. */
swsm = E1000_READ_REG(hw, SWSM);
if (swsm & E1000_SWSM_SWESMBI)
break;
udelay(50);
timeout--;
}
if (!timeout) {
/* Release semaphores */
e1000_put_hw_eeprom_semaphore(hw);
DEBUGOUT("Driver can't access the Eeprom - "
"SWESMBI bit is set.\n");
return -E1000_ERR_EEPROM;
}
return E1000_SUCCESS;
}
static int32_t
e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
{
uint32_t swfw_sync = 0;
uint32_t swmask = mask;
uint32_t fwmask = mask << 16;
int32_t timeout = 200;
DEBUGFUNC();
while (timeout) {
if (e1000_get_hw_eeprom_semaphore(hw))
return -E1000_ERR_SWFW_SYNC;
swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
if (!(swfw_sync & (fwmask | swmask)))
break;
/* firmware currently using resource (fwmask) */
/* or other software thread currently using resource (swmask) */
e1000_put_hw_eeprom_semaphore(hw);
mdelay(5);
timeout--;
}
if (!timeout) {
DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
return -E1000_ERR_SWFW_SYNC;
}
swfw_sync |= swmask;
E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
e1000_put_hw_eeprom_semaphore(hw);
return E1000_SUCCESS;
}
static boolean_t e1000_is_second_port(struct e1000_hw *hw)
{
switch (hw->mac_type) {
case e1000_80003es2lan:
case e1000_82546:
case e1000_82571:
if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
return TRUE;
/* Fallthrough */
default:
return FALSE;
}
}
/******************************************************************************
* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
* second function of dual function devices
*
* nic - Struct containing variables accessed by shared code
*****************************************************************************/
static int
e1000_read_mac_addr(struct eth_device *nic)
{
#ifndef CONFIG_AP1000
struct e1000_hw *hw = nic->priv;
uint16_t offset;
uint16_t eeprom_data;
int i;
DEBUGFUNC();
for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
offset = i >> 1;
if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
nic->enetaddr[i] = eeprom_data & 0xff;
nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
}
/* Invert the last bit if this is the second device */
if (e1000_is_second_port(hw))
nic->enetaddr[5] ^= 1;
#ifdef CONFIG_E1000_FALLBACK_MAC
if (!is_valid_ether_addr(nic->enetaddr)) {
unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
}
#endif
#else
/*
* The AP1000's e1000 has no eeprom; the MAC address is stored in the
* environment variables. Currently this does not support the addition
* of a PMC e1000 card, which is certainly a possibility, so this should
* be updated to properly use the env variable only for the onboard e1000
*/
int ii;
char *s, *e;
DEBUGFUNC();
s = getenv ("ethaddr");
if (s == NULL) {
return -E1000_ERR_EEPROM;
} else {
for(ii = 0; ii < 6; ii++) {
nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
if (s){
s = (*e) ? e + 1 : e;
}
}
}
#endif
return 0;
}
/******************************************************************************
* Initializes receive address filters.
*
* hw - Struct containing variables accessed by shared code
*
* Places the MAC address in receive address register 0 and clears the rest
* of the receive addresss registers. Clears the multicast table. Assumes
* the receiver is in reset when the routine is called.
*****************************************************************************/
static void
e1000_init_rx_addrs(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
uint32_t i;
uint32_t addr_low;
uint32_t addr_high;
DEBUGFUNC();
/* Setup the receive address. */
DEBUGOUT("Programming MAC Address into RAR[0]\n");
addr_low = (nic->enetaddr[0] |
(nic->enetaddr[1] << 8) |
(nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
/* Zero out the other 15 receive addresses. */
DEBUGOUT("Clearing RAR[1-15]\n");
for (i = 1; i < E1000_RAR_ENTRIES; i++) {
E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
}
}
/******************************************************************************
* Clears the VLAN filer table
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
e1000_clear_vfta(struct e1000_hw *hw)
{
uint32_t offset;
for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
}
/******************************************************************************
* Set the mac type member in the hw struct.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
int32_t
e1000_set_mac_type(struct e1000_hw *hw)
{
DEBUGFUNC();
switch (hw->device_id) {
case E1000_DEV_ID_82542:
switch (hw->revision_id) {
case E1000_82542_2_0_REV_ID:
hw->mac_type = e1000_82542_rev2_0;
break;
case E1000_82542_2_1_REV_ID:
hw->mac_type = e1000_82542_rev2_1;
break;
default:
/* Invalid 82542 revision ID */
return -E1000_ERR_MAC_TYPE;
}
break;
case E1000_DEV_ID_82543GC_FIBER:
case E1000_DEV_ID_82543GC_COPPER:
hw->mac_type = e1000_82543;
break;
case E1000_DEV_ID_82544EI_COPPER:
case E1000_DEV_ID_82544EI_FIBER:
case E1000_DEV_ID_82544GC_COPPER:
case E1000_DEV_ID_82544GC_LOM:
hw->mac_type = e1000_82544;
break;
case E1000_DEV_ID_82540EM:
case E1000_DEV_ID_82540EM_LOM:
case E1000_DEV_ID_82540EP:
case E1000_DEV_ID_82540EP_LOM:
case E1000_DEV_ID_82540EP_LP:
hw->mac_type = e1000_82540;
break;
case E1000_DEV_ID_82545EM_COPPER:
case E1000_DEV_ID_82545EM_FIBER:
hw->mac_type = e1000_82545;
break;
case E1000_DEV_ID_82545GM_COPPER:
case E1000_DEV_ID_82545GM_FIBER:
case E1000_DEV_ID_82545GM_SERDES:
hw->mac_type = e1000_82545_rev_3;
break;
case E1000_DEV_ID_82546EB_COPPER:
case E1000_DEV_ID_82546EB_FIBER:
case E1000_DEV_ID_82546EB_QUAD_COPPER:
hw->mac_type = e1000_82546;
break;
case E1000_DEV_ID_82546GB_COPPER:
case E1000_DEV_ID_82546GB_FIBER:
case E1000_DEV_ID_82546GB_SERDES:
case E1000_DEV_ID_82546GB_PCIE:
case E1000_DEV_ID_82546GB_QUAD_COPPER:
case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
hw->mac_type = e1000_82546_rev_3;
break;
case E1000_DEV_ID_82541EI:
case E1000_DEV_ID_82541EI_MOBILE:
case E1000_DEV_ID_82541ER_LOM:
hw->mac_type = e1000_82541;
break;
case E1000_DEV_ID_82541ER:
case E1000_DEV_ID_82541GI:
case E1000_DEV_ID_82541GI_LF:
case E1000_DEV_ID_82541GI_MOBILE:
hw->mac_type = e1000_82541_rev_2;
break;
case E1000_DEV_ID_82547EI:
case E1000_DEV_ID_82547EI_MOBILE:
hw->mac_type = e1000_82547;
break;
case E1000_DEV_ID_82547GI:
hw->mac_type = e1000_82547_rev_2;
break;
case E1000_DEV_ID_82571EB_COPPER:
case E1000_DEV_ID_82571EB_FIBER:
case E1000_DEV_ID_82571EB_SERDES:
case E1000_DEV_ID_82571EB_SERDES_DUAL:
case E1000_DEV_ID_82571EB_SERDES_QUAD:
case E1000_DEV_ID_82571EB_QUAD_COPPER:
case E1000_DEV_ID_82571PT_QUAD_COPPER:
case E1000_DEV_ID_82571EB_QUAD_FIBER:
case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
hw->mac_type = e1000_82571;
break;
case E1000_DEV_ID_82572EI_COPPER:
case E1000_DEV_ID_82572EI_FIBER:
case E1000_DEV_ID_82572EI_SERDES:
case E1000_DEV_ID_82572EI:
hw->mac_type = e1000_82572;
break;
case E1000_DEV_ID_82573E:
case E1000_DEV_ID_82573E_IAMT:
case E1000_DEV_ID_82573L:
hw->mac_type = e1000_82573;
break;
case E1000_DEV_ID_82574L:
hw->mac_type = e1000_82574;
break;
case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
hw->mac_type = e1000_80003es2lan;
break;
case E1000_DEV_ID_ICH8_IGP_M_AMT:
case E1000_DEV_ID_ICH8_IGP_AMT:
case E1000_DEV_ID_ICH8_IGP_C:
case E1000_DEV_ID_ICH8_IFE:
case E1000_DEV_ID_ICH8_IFE_GT:
case E1000_DEV_ID_ICH8_IFE_G:
case E1000_DEV_ID_ICH8_IGP_M:
hw->mac_type = e1000_ich8lan;
break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Reset the transmit and receive units; mask and clear all interrupts.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
void
e1000_reset_hw(struct e1000_hw *hw)
{
uint32_t ctrl;
uint32_t ctrl_ext;
uint32_t manc;
uint32_t pba = 0;
DEBUGFUNC();
/* get the correct pba value for both PCI and PCIe*/
if (hw->mac_type < e1000_82571)
pba = E1000_DEFAULT_PCI_PBA;
else
pba = E1000_DEFAULT_PCIE_PBA;
/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
pci_write_config_word(hw->pdev, PCI_COMMAND,
hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
}
/* Clear interrupt mask to stop board from generating interrupts */
DEBUGOUT("Masking off all interrupts\n");
E1000_WRITE_REG(hw, IMC, 0xffffffff);
/* Disable the Transmit and Receive units. Then delay to allow
* any pending transactions to complete before we hit the MAC with
* the global reset.
*/
E1000_WRITE_REG(hw, RCTL, 0);
E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
E1000_WRITE_FLUSH(hw);
/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
hw->tbi_compatibility_on = FALSE;
/* Delay to allow any outstanding PCI transactions to complete before
* resetting the device
*/
mdelay(10);
/* Issue a global reset to the MAC. This will reset the chip's
* transmit, receive, DMA, and link units. It will not effect
* the current PCI configuration. The global reset bit is self-
* clearing, and should clear within a microsecond.
*/
DEBUGOUT("Issuing a global reset to MAC\n");
ctrl = E1000_READ_REG(hw, CTRL);
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
/* Force a reload from the EEPROM if necessary */
if (hw->mac_type < e1000_82540) {
/* Wait for reset to complete */
udelay(10);
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
/* Wait for EEPROM reload */
mdelay(2);
} else {
/* Wait for EEPROM reload (it happens automatically) */
mdelay(4);
/* Dissable HW ARPs on ASF enabled adapters */
manc = E1000_READ_REG(hw, MANC);
manc &= ~(E1000_MANC_ARP_EN);
E1000_WRITE_REG(hw, MANC, manc);
}
/* Clear interrupt mask to stop board from generating interrupts */
DEBUGOUT("Masking off all interrupts\n");
E1000_WRITE_REG(hw, IMC, 0xffffffff);
/* Clear any pending interrupt events. */
E1000_READ_REG(hw, ICR);
/* If MWI was previously enabled, reenable it. */
if (hw->mac_type == e1000_82542_rev2_0) {
pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
}
E1000_WRITE_REG(hw, PBA, pba);
}
/******************************************************************************
*
* Initialize a number of hardware-dependent bits
*
* hw: Struct containing variables accessed by shared code
*
* This function contains hardware limitation workarounds for PCI-E adapters
*
*****************************************************************************/
static void
e1000_initialize_hardware_bits(struct e1000_hw *hw)
{
if ((hw->mac_type >= e1000_82571) &&
(!hw->initialize_hw_bits_disable)) {
/* Settings common to all PCI-express silicon */
uint32_t reg_ctrl, reg_ctrl_ext;
uint32_t reg_tarc0, reg_tarc1;
uint32_t reg_tctl;
uint32_t reg_txdctl, reg_txdctl1;
/* link autonegotiation/sync workarounds */
reg_tarc0 = E1000_READ_REG(hw, TARC0);
reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
/* Enable not-done TX descriptor counting */
reg_txdctl = E1000_READ_REG(hw, TXDCTL);
reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
switch (hw->mac_type) {
case e1000_82571:
case e1000_82572:
/* Clear PHY TX compatible mode bits */
reg_tarc1 = E1000_READ_REG(hw, TARC1);
reg_tarc1 &= ~((1 << 30)|(1 << 29));
/* link autonegotiation/sync workarounds */
reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
/* TX ring control fixes */
reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
/* Multiple read bit is reversed polarity */
reg_tctl = E1000_READ_REG(hw, TCTL);
if (reg_tctl & E1000_TCTL_MULR)
reg_tarc1 &= ~(1 << 28);
else
reg_tarc1 |= (1 << 28);
E1000_WRITE_REG(hw, TARC1, reg_tarc1);
break;
case e1000_82573:
case e1000_82574:
reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
reg_ctrl_ext &= ~(1 << 23);
reg_ctrl_ext |= (1 << 22);
/* TX byte count fix */
reg_ctrl = E1000_READ_REG(hw, CTRL);
reg_ctrl &= ~(1 << 29);
E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
E1000_WRITE_REG(hw, CTRL, reg_ctrl);
break;
case e1000_80003es2lan:
/* improve small packet performace for fiber/serdes */
if ((hw->media_type == e1000_media_type_fiber)
|| (hw->media_type ==
e1000_media_type_internal_serdes)) {
reg_tarc0 &= ~(1 << 20);
}
/* Multiple read bit is reversed polarity */
reg_tctl = E1000_READ_REG(hw, TCTL);
reg_tarc1 = E1000_READ_REG(hw, TARC1);
if (reg_tctl & E1000_TCTL_MULR)
reg_tarc1 &= ~(1 << 28);
else
reg_tarc1 |= (1 << 28);
E1000_WRITE_REG(hw, TARC1, reg_tarc1);
break;
case e1000_ich8lan:
/* Reduce concurrent DMA requests to 3 from 4 */
if ((hw->revision_id < 3) ||
((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
reg_tarc0 |= ((1 << 29)|(1 << 28));
reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
reg_ctrl_ext |= (1 << 22);
E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
/* workaround TX hang with TSO=on */
reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
/* Multiple read bit is reversed polarity */
reg_tctl = E1000_READ_REG(hw, TCTL);
reg_tarc1 = E1000_READ_REG(hw, TARC1);
if (reg_tctl & E1000_TCTL_MULR)
reg_tarc1 &= ~(1 << 28);
else
reg_tarc1 |= (1 << 28);
/* workaround TX hang with TSO=on */
reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
E1000_WRITE_REG(hw, TARC1, reg_tarc1);
break;
default:
break;
}
E1000_WRITE_REG(hw, TARC0, reg_tarc0);
}
}
/******************************************************************************
* Performs basic configuration of the adapter.
*
* hw - Struct containing variables accessed by shared code
*
* Assumes that the controller has previously been reset and is in a
* post-reset uninitialized state. Initializes the receive address registers,
* multicast table, and VLAN filter table. Calls routines to setup link
* configuration and flow control settings. Clears all on-chip counters. Leaves
* the transmit and receive units disabled and uninitialized.
*****************************************************************************/
static int
e1000_init_hw(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
uint32_t ctrl;
uint32_t i;
int32_t ret_val;
uint16_t pcix_cmd_word;
uint16_t pcix_stat_hi_word;
uint16_t cmd_mmrbc;
uint16_t stat_mmrbc;
uint32_t mta_size;
uint32_t reg_data;
uint32_t ctrl_ext;
DEBUGFUNC();
/* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
if ((hw->mac_type == e1000_ich8lan) &&
((hw->revision_id < 3) ||
((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
reg_data = E1000_READ_REG(hw, STATUS);
reg_data &= ~0x80000000;
E1000_WRITE_REG(hw, STATUS, reg_data);
}
/* Do not need initialize Identification LED */
/* Set the media type and TBI compatibility */
e1000_set_media_type(hw);
/* Must be called after e1000_set_media_type
* because media_type is used */
e1000_initialize_hardware_bits(hw);
/* Disabling VLAN filtering. */
DEBUGOUT("Initializing the IEEE VLAN\n");
/* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
if (hw->mac_type != e1000_ich8lan) {
if (hw->mac_type < e1000_82545_rev_3)
E1000_WRITE_REG(hw, VET, 0);
e1000_clear_vfta(hw);
}
/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
pci_write_config_word(hw->pdev, PCI_COMMAND,
hw->
pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
E1000_WRITE_FLUSH(hw);
mdelay(5);
}
/* Setup the receive address. This involves initializing all of the Receive
* Address Registers (RARs 0 - 15).
*/
e1000_init_rx_addrs(nic);
/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
if (hw->mac_type == e1000_82542_rev2_0) {
E1000_WRITE_REG(hw, RCTL, 0);
E1000_WRITE_FLUSH(hw);
mdelay(1);
pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
}
/* Zero out the Multicast HASH table */
DEBUGOUT("Zeroing the MTA\n");
mta_size = E1000_MC_TBL_SIZE;
if (hw->mac_type == e1000_ich8lan)
mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
for (i = 0; i < mta_size; i++) {
E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
/* use write flush to prevent Memory Write Block (MWB) from
* occuring when accessing our register space */
E1000_WRITE_FLUSH(hw);
}
#if 0
/* Set the PCI priority bit correctly in the CTRL register. This
* determines if the adapter gives priority to receives, or if it
* gives equal priority to transmits and receives. Valid only on
* 82542 and 82543 silicon.
*/
if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
ctrl = E1000_READ_REG(hw, CTRL);
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
}
#endif
switch (hw->mac_type) {
case e1000_82545_rev_3:
case e1000_82546_rev_3:
break;
default:
/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
if (hw->bus_type == e1000_bus_type_pcix) {
pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
&pcix_cmd_word);
pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
&pcix_stat_hi_word);
cmd_mmrbc =
(pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
PCIX_COMMAND_MMRBC_SHIFT;
stat_mmrbc =
(pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
PCIX_STATUS_HI_MMRBC_SHIFT;
if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
if (cmd_mmrbc > stat_mmrbc) {
pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
pcix_cmd_word);
}
}
break;
}
/* More time needed for PHY to initialize */
if (hw->mac_type == e1000_ich8lan)
mdelay(15);
/* Call a subroutine to configure the link and setup flow control. */
ret_val = e1000_setup_link(nic);
/* Set the transmit descriptor write-back policy */
if (hw->mac_type > e1000_82544) {
ctrl = E1000_READ_REG(hw, TXDCTL);
ctrl =
(ctrl & ~E1000_TXDCTL_WTHRESH) |
E1000_TXDCTL_FULL_TX_DESC_WB;
E1000_WRITE_REG(hw, TXDCTL, ctrl);
}
switch (hw->mac_type) {
default:
break;
case e1000_80003es2lan:
/* Enable retransmit on late collisions */
reg_data = E1000_READ_REG(hw, TCTL);
reg_data |= E1000_TCTL_RTLC;
E1000_WRITE_REG(hw, TCTL, reg_data);
/* Configure Gigabit Carry Extend Padding */
reg_data = E1000_READ_REG(hw, TCTL_EXT);
reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
/* Configure Transmit Inter-Packet Gap */
reg_data = E1000_READ_REG(hw, TIPG);
reg_data &= ~E1000_TIPG_IPGT_MASK;
reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
E1000_WRITE_REG(hw, TIPG, reg_data);
reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
reg_data &= ~0x00100000;
E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
/* Fall through */
case e1000_82571:
case e1000_82572:
case e1000_ich8lan:
ctrl = E1000_READ_REG(hw, TXDCTL1);
ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
| E1000_TXDCTL_FULL_TX_DESC_WB;
E1000_WRITE_REG(hw, TXDCTL1, ctrl);
break;
case e1000_82573:
case e1000_82574:
reg_data = E1000_READ_REG(hw, GCR);
reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
E1000_WRITE_REG(hw, GCR, reg_data);
}
#if 0
/* Clear all of the statistics registers (clear on read). It is
* important that we do this after we have tried to establish link
* because the symbol error count will increment wildly if there
* is no link.
*/
e1000_clear_hw_cntrs(hw);
/* ICH8 No-snoop bits are opposite polarity.
* Set to snoop by default after reset. */
if (hw->mac_type == e1000_ich8lan)
e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
#endif
if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
/* Relaxed ordering must be disabled to avoid a parity
* error crash in a PCI slot. */
ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
}
return ret_val;
}
/******************************************************************************
* Configures flow control and link settings.
*
* hw - Struct containing variables accessed by shared code
*
* Determines which flow control settings to use. Calls the apropriate media-
* specific link configuration function. Configures the flow control settings.
* Assuming the adapter has a valid link partner, a valid link should be
* established. Assumes the hardware has previously been reset and the
* transmitter and receiver are not enabled.
*****************************************************************************/
static int
e1000_setup_link(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
uint32_t ctrl_ext;
int32_t ret_val;
uint16_t eeprom_data;
DEBUGFUNC();
/* In the case of the phy reset being blocked, we already have a link.
* We do not have to set it up again. */
if (e1000_check_phy_reset_block(hw))
return E1000_SUCCESS;
#ifndef CONFIG_AP1000
/* Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
* a bit that determines whether the HW defaults to enabling or
* disabling auto-negotiation, and the direction of the
* SW defined pins. If there is no SW over-ride of the flow
* control setting, then the variable hw->fc will
* be initialized based on a value in the EEPROM.
*/
if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
&eeprom_data) < 0) {
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
#else
/* we have to hardcode the proper value for our hardware. */
/* this value is for the 82540EM pci card used for prototyping, and it works. */
eeprom_data = 0xb220;
#endif
if (hw->fc == e1000_fc_default) {
switch (hw->mac_type) {
case e1000_ich8lan:
case e1000_82573:
case e1000_82574:
hw->fc = e1000_fc_full;
break;
default:
#ifndef CONFIG_AP1000
ret_val = e1000_read_eeprom(hw,
EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
if (ret_val) {
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
#else
eeprom_data = 0xb220;
#endif
if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
hw->fc = e1000_fc_none;
else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
EEPROM_WORD0F_ASM_DIR)
hw->fc = e1000_fc_tx_pause;
else
hw->fc = e1000_fc_full;
break;
}
}
/* We want to save off the original Flow Control configuration just
* in case we get disconnected and then reconnected into a different
* hub or switch with different Flow Control capabilities.
*/
if (hw->mac_type == e1000_82542_rev2_0)
hw->fc &= (~e1000_fc_tx_pause);
if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
hw->fc &= (~e1000_fc_rx_pause);
hw->original_fc = hw->fc;
DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
/* Take the 4 bits from EEPROM word 0x0F that determine the initial
* polarity value for the SW controlled pins, and setup the
* Extended Device Control reg with that info.
* This is needed because one of the SW controlled pins is used for
* signal detection. So this should be done before e1000_setup_pcs_link()
* or e1000_phy_setup() is called.
*/
if (hw->mac_type == e1000_82543) {
ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
SWDPIO__EXT_SHIFT);
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
}
/* Call the necessary subroutine to configure the link. */
ret_val = (hw->media_type == e1000_media_type_fiber) ?
e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
if (ret_val < 0) {
return ret_val;
}
/* Initialize the flow control address, type, and PAUSE timer
* registers to their default values. This is done even if flow
* control is disabled, because it does not hurt anything to
* initialize these registers.
*/
DEBUGOUT("Initializing the Flow Control address, type"
"and timer regs\n");
/* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
if (hw->mac_type != e1000_ich8lan) {
E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
}
E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
/* Set the flow control receive threshold registers. Normally,
* these registers will be set to a default threshold that may be
* adjusted later by the driver's runtime code. However, if the
* ability to transmit pause frames in not enabled, then these
* registers will be set to 0.
*/
if (!(hw->fc & e1000_fc_tx_pause)) {
E1000_WRITE_REG(hw, FCRTL, 0);
E1000_WRITE_REG(hw, FCRTH, 0);
} else {
/* We need to set up the Receive Threshold high and low water marks
* as well as (optionally) enabling the transmission of XON frames.
*/
if (hw->fc_send_xon) {
E1000_WRITE_REG(hw, FCRTL,
(hw->fc_low_water | E1000_FCRTL_XONE));
E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
} else {
E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
}
}
return ret_val;
}
/******************************************************************************
* Sets up link for a fiber based adapter
*
* hw - Struct containing variables accessed by shared code
*
* Manipulates Physical Coding Sublayer functions in order to configure
* link. Assumes the hardware has been previously reset and the transmitter
* and receiver are not enabled.
*****************************************************************************/
static int
e1000_setup_fiber_link(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
uint32_t ctrl;
uint32_t status;
uint32_t txcw = 0;
uint32_t i;
uint32_t signal;
int32_t ret_val;
DEBUGFUNC();
/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
* cleared when there is a signal
*/
ctrl = E1000_READ_REG(hw, CTRL);
if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
signal = E1000_CTRL_SWDPIN1;
else
signal = 0;
printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
ctrl);
/* Take the link out of reset */
ctrl &= ~(E1000_CTRL_LRST);
e1000_config_collision_dist(hw);
/* Check for a software override of the flow control settings, and setup
* the device accordingly. If auto-negotiation is enabled, then software
* will have to set the "PAUSE" bits to the correct value in the Tranmsit
* Config Word Register (TXCW) and re-start auto-negotiation. However, if
* auto-negotiation is disabled, then software will have to manually
* configure the two flow control enable bits in the CTRL register.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames, but
* not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but we do
* not support receiving pause frames).
* 3: Both Rx and TX flow control (symmetric) are enabled.
*/
switch (hw->fc) {
case e1000_fc_none:
/* Flow control is completely disabled by a software over-ride. */
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
break;
case e1000_fc_rx_pause:
/* RX Flow control is enabled and TX Flow control is disabled by a
* software over-ride. Since there really isn't a way to advertise
* that we are capable of RX Pause ONLY, we will advertise that we
* support both symmetric and asymmetric RX PAUSE. Later, we will
* disable the adapter's ability to send PAUSE frames.
*/
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
break;
case e1000_fc_tx_pause:
/* TX Flow control is enabled, and RX Flow control is disabled, by a
* software over-ride.
*/
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
break;
case e1000_fc_full:
/* Flow control (both RX and TX) is enabled by a software over-ride. */
txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
return -E1000_ERR_CONFIG;
break;
}
/* Since auto-negotiation is enabled, take the link out of reset (the link
* will be in reset, because we previously reset the chip). This will
* restart auto-negotiation. If auto-neogtiation is successful then the
* link-up status bit will be set and the flow control enable bits (RFCE
* and TFCE) will be set according to their negotiated value.
*/
DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
E1000_WRITE_REG(hw, TXCW, txcw);
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
hw->txcw = txcw;
mdelay(1);
/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
* indication in the Device Status Register. Time-out if a link isn't
* seen in 500 milliseconds seconds (Auto-negotiation should complete in
* less than 500 milliseconds even if the other end is doing it in SW).
*/
if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
DEBUGOUT("Looking for Link\n");
for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
mdelay(10);
status = E1000_READ_REG(hw, STATUS);
if (status & E1000_STATUS_LU)
break;
}
if (i == (LINK_UP_TIMEOUT / 10)) {
/* AutoNeg failed to achieve a link, so we'll call
* e1000_check_for_link. This routine will force the link up if we
* detect a signal. This will allow us to communicate with
* non-autonegotiating link partners.
*/
DEBUGOUT("Never got a valid link from auto-neg!!!\n");
hw->autoneg_failed = 1;
ret_val = e1000_check_for_link(nic);
if (ret_val < 0) {
DEBUGOUT("Error while checking for link\n");
return ret_val;
}
hw->autoneg_failed = 0;
} else {
hw->autoneg_failed = 0;
DEBUGOUT("Valid Link Found\n");
}
} else {
DEBUGOUT("No Signal Detected\n");
return -E1000_ERR_NOLINK;
}
return 0;
}
/******************************************************************************
* Make sure we have a valid PHY and change PHY mode before link setup.
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int32_t
e1000_copper_link_preconfig(struct e1000_hw *hw)
{
uint32_t ctrl;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC();
ctrl = E1000_READ_REG(hw, CTRL);
/* With 82543, we need to force speed and duplex on the MAC equal to what
* the PHY speed and duplex configuration is. In addition, we need to
* perform a hardware reset on the PHY to take it out of reset.
*/
if (hw->mac_type > e1000_82543) {
ctrl |= E1000_CTRL_SLU;
ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
E1000_WRITE_REG(hw, CTRL, ctrl);
} else {
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
| E1000_CTRL_SLU);
E1000_WRITE_REG(hw, CTRL, ctrl);
ret_val = e1000_phy_hw_reset(hw);
if (ret_val)
return ret_val;
}
/* Make sure we have a valid PHY */
ret_val = e1000_detect_gig_phy(hw);
if (ret_val) {
DEBUGOUT("Error, did not detect valid phy.\n");
return ret_val;
}
DEBUGOUT("Phy ID = %x \n", hw->phy_id);
#ifndef CONFIG_AP1000
/* Set PHY to class A mode (if necessary) */
ret_val = e1000_set_phy_mode(hw);
if (ret_val)
return ret_val;
#endif
if ((hw->mac_type == e1000_82545_rev_3) ||
(hw->mac_type == e1000_82546_rev_3)) {
ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
&phy_data);
phy_data |= 0x00000008;
ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
phy_data);
}
if (hw->mac_type <= e1000_82543 ||
hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
hw->mac_type == e1000_82541_rev_2
|| hw->mac_type == e1000_82547_rev_2)
hw->phy_reset_disable = FALSE;
return E1000_SUCCESS;
}
/*****************************************************************************
*
* This function sets the lplu state according to the active flag. When
* activating lplu this function also disables smart speed and vise versa.
* lplu will not be activated unless the device autonegotiation advertisment
* meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
* hw: Struct containing variables accessed by shared code
* active - true to enable lplu false to disable lplu.
*
* returns: - E1000_ERR_PHY if fail to read/write the PHY
* E1000_SUCCESS at any other case.
*
****************************************************************************/
static int32_t
e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
{
uint32_t phy_ctrl = 0;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC();
if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
&& hw->phy_type != e1000_phy_igp_3)
return E1000_SUCCESS;
/* During driver activity LPLU should not be used or it will attain link
* from the lowest speeds starting from 10Mbps. The capability is used
* for Dx transitions and states */
if (hw->mac_type == e1000_82541_rev_2
|| hw->mac_type == e1000_82547_rev_2) {
ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
&phy_data);
if (ret_val)
return ret_val;
} else if (hw->mac_type == e1000_ich8lan) {
/* MAC writes into PHY register based on the state transition
* and start auto-negotiation. SW driver can overwrite the
* settings in CSR PHY power control E1000_PHY_CTRL register. */
phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
} else {
ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
&phy_data);
if (ret_val)
return ret_val;
}
if (!active) {
if (hw->mac_type == e1000_82541_rev_2 ||
hw->mac_type == e1000_82547_rev_2) {
phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
phy_data);
if (ret_val)
return ret_val;
} else {
if (hw->mac_type == e1000_ich8lan) {
phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
} else {
phy_data &= ~IGP02E1000_PM_D3_LPLU;
ret_val = e1000_write_phy_reg(hw,
IGP02E1000_PHY_POWER_MGMT, phy_data);
if (ret_val)
return ret_val;
}
}
/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
* Dx states where the power conservation is most important. During
* driver activity we should enable SmartSpeed, so performance is
* maintained. */
if (hw->smart_speed == e1000_smart_speed_on) {
ret_val = e1000_read_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, &phy_data);
if (ret_val)
return ret_val;
phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1000_write_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, phy_data);
if (ret_val)
return ret_val;
} else if (hw->smart_speed == e1000_smart_speed_off) {
ret_val = e1000_read_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, &phy_data);
if (ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1000_write_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, phy_data);
if (ret_val)
return ret_val;
}
} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
|| (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
if (hw->mac_type == e1000_82541_rev_2 ||
hw->mac_type == e1000_82547_rev_2) {
phy_data |= IGP01E1000_GMII_FLEX_SPD;
ret_val = e1000_write_phy_reg(hw,
IGP01E1000_GMII_FIFO, phy_data);
if (ret_val)
return ret_val;
} else {
if (hw->mac_type == e1000_ich8lan) {
phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
} else {
phy_data |= IGP02E1000_PM_D3_LPLU;
ret_val = e1000_write_phy_reg(hw,
IGP02E1000_PHY_POWER_MGMT, phy_data);
if (ret_val)
return ret_val;
}
}
/* When LPLU is enabled we should disable SmartSpeed */
ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
&phy_data);
if (ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
phy_data);
if (ret_val)
return ret_val;
}
return E1000_SUCCESS;
}
/*****************************************************************************
*
* This function sets the lplu d0 state according to the active flag. When
* activating lplu this function also disables smart speed and vise versa.
* lplu will not be activated unless the device autonegotiation advertisment
* meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
* hw: Struct containing variables accessed by shared code
* active - true to enable lplu false to disable lplu.
*
* returns: - E1000_ERR_PHY if fail to read/write the PHY
* E1000_SUCCESS at any other case.
*
****************************************************************************/
static int32_t
e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
{
uint32_t phy_ctrl = 0;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC();
if (hw->mac_type <= e1000_82547_rev_2)
return E1000_SUCCESS;
if (hw->mac_type == e1000_ich8lan) {
phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
} else {
ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
&phy_data);
if (ret_val)
return ret_val;
}
if (!active) {
if (hw->mac_type == e1000_ich8lan) {
phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
} else {
phy_data &= ~IGP02E1000_PM_D0_LPLU;
ret_val = e1000_write_phy_reg(hw,
IGP02E1000_PHY_POWER_MGMT, phy_data);
if (ret_val)
return ret_val;
}
/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
* Dx states where the power conservation is most important. During
* driver activity we should enable SmartSpeed, so performance is
* maintained. */
if (hw->smart_speed == e1000_smart_speed_on) {
ret_val = e1000_read_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, &phy_data);
if (ret_val)
return ret_val;
phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1000_write_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, phy_data);
if (ret_val)
return ret_val;
} else if (hw->smart_speed == e1000_smart_speed_off) {
ret_val = e1000_read_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, &phy_data);
if (ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1000_write_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, phy_data);
if (ret_val)
return ret_val;
}
} else {
if (hw->mac_type == e1000_ich8lan) {
phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
} else {
phy_data |= IGP02E1000_PM_D0_LPLU;
ret_val = e1000_write_phy_reg(hw,
IGP02E1000_PHY_POWER_MGMT, phy_data);
if (ret_val)
return ret_val;
}
/* When LPLU is enabled we should disable SmartSpeed */
ret_val = e1000_read_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, &phy_data);
if (ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1000_write_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, phy_data);
if (ret_val)
return ret_val;
}
return E1000_SUCCESS;
}
/********************************************************************
* Copper link setup for e1000_phy_igp series.
*
* hw - Struct containing variables accessed by shared code
*********************************************************************/
static int32_t
e1000_copper_link_igp_setup(struct e1000_hw *hw)
{
uint32_t led_ctrl;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC();
if (hw->phy_reset_disable)
return E1000_SUCCESS;
ret_val = e1000_phy_reset(hw);
if (ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
}
/* Wait 15ms for MAC to configure PHY from eeprom settings */
mdelay(15);
if (hw->mac_type != e1000_ich8lan) {
/* Configure activity LED after PHY reset */
led_ctrl = E1000_READ_REG(hw, LEDCTL);
led_ctrl &= IGP_ACTIVITY_LED_MASK;
led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
}
/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
if (hw->phy_type == e1000_phy_igp) {
/* disable lplu d3 during driver init */
ret_val = e1000_set_d3_lplu_state(hw, FALSE);
if (ret_val) {
DEBUGOUT("Error Disabling LPLU D3\n");
return ret_val;
}
}
/* disable lplu d0 during driver init */
ret_val = e1000_set_d0_lplu_state(hw, FALSE);
if (ret_val) {
DEBUGOUT("Error Disabling LPLU D0\n");
return ret_val;
}
/* Configure mdi-mdix settings */
ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
if (ret_val)
return ret_val;
if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
hw->dsp_config_state = e1000_dsp_config_disabled;
/* Force MDI for earlier revs of the IGP PHY */
phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
| IGP01E1000_PSCR_FORCE_MDI_MDIX);
hw->mdix = 1;
} else {
hw->dsp_config_state = e1000_dsp_config_enabled;
phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
switch (hw->mdix) {
case 1:
phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
break;
case 2:
phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
break;
case 0:
default:
phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
break;
}
}
ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
if (ret_val)
return ret_val;
/* set auto-master slave resolution settings */
if (hw->autoneg) {
e1000_ms_type phy_ms_setting = hw->master_slave;
if (hw->ffe_config_state == e1000_ffe_config_active)
hw->ffe_config_state = e1000_ffe_config_enabled;
if (hw->dsp_config_state == e1000_dsp_config_activated)
hw->dsp_config_state = e1000_dsp_config_enabled;
/* when autonegotiation advertisment is only 1000Mbps then we
* should disable SmartSpeed and enable Auto MasterSlave
* resolution as hardware default. */
if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
/* Disable SmartSpeed */
ret_val = e1000_read_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, &phy_data);
if (ret_val)
return ret_val;
phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ret_val = e1000_write_phy_reg(hw,
IGP01E1000_PHY_PORT_CONFIG, phy_data);
if (ret_val)
return ret_val;
/* Set auto Master/Slave resolution process */
ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
&phy_data);
if (ret_val)
return ret_val;
phy_data &= ~CR_1000T_MS_ENABLE;
ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
phy_data);
if (ret_val)
return ret_val;
}
ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
if (ret_val)
return ret_val;
/* load defaults for future use */
hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
((phy_data & CR_1000T_MS_VALUE) ?
e1000_ms_force_master :
e1000_ms_force_slave) :
e1000_ms_auto;
switch (phy_ms_setting) {
case e1000_ms_force_master:
phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
break;
case e1000_ms_force_slave:
phy_data |= CR_1000T_MS_ENABLE;
phy_data &= ~(CR_1000T_MS_VALUE);
break;
case e1000_ms_auto:
phy_data &= ~CR_1000T_MS_ENABLE;
default:
break;
}
ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
if (ret_val)
return ret_val;
}
return E1000_SUCCESS;
}
/*****************************************************************************
* This function checks the mode of the firmware.
*
* returns - TRUE when the mode is IAMT or FALSE.
****************************************************************************/
boolean_t
e1000_check_mng_mode(struct e1000_hw *hw)
{
uint32_t fwsm;
DEBUGFUNC();
fwsm = E1000_READ_REG(hw, FWSM);
if (hw->mac_type == e1000_ich8lan) {
if ((fwsm & E1000_FWSM_MODE_MASK) ==
(E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
return TRUE;
} else if ((fwsm & E1000_FWSM_MODE_MASK) ==
(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
return TRUE;
return FALSE;
}
static int32_t
e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
{
uint16_t swfw = E1000_SWFW_PHY0_SM;
uint32_t reg_val;
DEBUGFUNC();
if (e1000_is_second_port(hw))
swfw = E1000_SWFW_PHY1_SM;
if (e1000_swfw_sync_acquire(hw, swfw))
return -E1000_ERR_SWFW_SYNC;
reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
& E1000_KUMCTRLSTA_OFFSET) | data;
E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
udelay(2);
return E1000_SUCCESS;
}
static int32_t
e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
{
uint16_t swfw = E1000_SWFW_PHY0_SM;
uint32_t reg_val;
DEBUGFUNC();
if (e1000_is_second_port(hw))
swfw = E1000_SWFW_PHY1_SM;
if (e1000_swfw_sync_acquire(hw, swfw))
return -E1000_ERR_SWFW_SYNC;
/* Write register address */
reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
udelay(2);
/* Read the data returned */
reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
*data = (uint16_t)reg_val;
return E1000_SUCCESS;
}
/********************************************************************
* Copper link setup for e1000_phy_gg82563 series.
*
* hw - Struct containing variables accessed by shared code
*********************************************************************/
static int32_t
e1000_copper_link_ggp_setup(struct e1000_hw *hw)
{
int32_t ret_val;
uint16_t phy_data;
uint32_t reg_data;
DEBUGFUNC();
if (!hw->phy_reset_disable) {
/* Enable CRS on TX for half-duplex operation. */
ret_val = e1000_read_phy_reg(hw,
GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
if (ret_val)
return ret_val;
phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
/* Use 25MHz for both link down and 1000BASE-T for Tx clock */
phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
ret_val = e1000_write_phy_reg(hw,
GG82563_PHY_MAC_SPEC_CTRL, phy_data);
if (ret_val)
return ret_val;
/* Options:
* MDI/MDI-X = 0 (default)
* 0 - Auto for all speeds
* 1 - MDI mode
* 2 - MDI-X mode
* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
*/
ret_val = e1000_read_phy_reg(hw,
GG82563_PHY_SPEC_CTRL, &phy_data);
if (ret_val)
return ret_val;
phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
switch (hw->mdix) {
case 1:
phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
break;
case 2:
phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
break;
case 0:
default:
phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
break;
}
/* Options:
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
* 1 - Enabled
*/
phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
ret_val = e1000_write_phy_reg(hw,
GG82563_PHY_SPEC_CTRL, phy_data);
if (ret_val)
return ret_val;
/* SW Reset the PHY so all changes take effect */
ret_val = e1000_phy_reset(hw);
if (ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
}
} /* phy_reset_disable */
if (hw->mac_type == e1000_80003es2lan) {
/* Bypass RX and TX FIFO's */
ret_val = e1000_write_kmrn_reg(hw,
E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
| E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
if (ret_val)
return ret_val;
ret_val = e1000_read_phy_reg(hw,
GG82563_PHY_SPEC_CTRL_2, &phy_data);
if (ret_val)
return ret_val;
phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
ret_val = e1000_write_phy_reg(hw,
GG82563_PHY_SPEC_CTRL_2, phy_data);
if (ret_val)
return ret_val;
reg_data = E1000_READ_REG(hw, CTRL_EXT);
reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
ret_val = e1000_read_phy_reg(hw,
GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
if (ret_val)
return ret_val;
/* Do not init these registers when the HW is in IAMT mode, since the
* firmware will have already initialized them. We only initialize
* them if the HW is not in IAMT mode.
*/
if (e1000_check_mng_mode(hw) == FALSE) {
/* Enable Electrical Idle on the PHY */
phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
ret_val = e1000_write_phy_reg(hw,
GG82563_PHY_PWR_MGMT_CTRL, phy_data);
if (ret_val)
return ret_val;
ret_val = e1000_read_phy_reg(hw,
GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
if (ret_val)
return ret_val;
phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
ret_val = e1000_write_phy_reg(hw,
GG82563_PHY_KMRN_MODE_CTRL, phy_data);
if (ret_val)
return ret_val;
}
/* Workaround: Disable padding in Kumeran interface in the MAC
* and in the PHY to avoid CRC errors.
*/
ret_val = e1000_read_phy_reg(hw,
GG82563_PHY_INBAND_CTRL, &phy_data);
if (ret_val)
return ret_val;
phy_data |= GG82563_ICR_DIS_PADDING;
ret_val = e1000_write_phy_reg(hw,
GG82563_PHY_INBAND_CTRL, phy_data);
if (ret_val)
return ret_val;
}
return E1000_SUCCESS;
}
/********************************************************************
* Copper link setup for e1000_phy_m88 series.
*
* hw - Struct containing variables accessed by shared code
*********************************************************************/
static int32_t
e1000_copper_link_mgp_setup(struct e1000_hw *hw)
{
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC();
if (hw->phy_reset_disable)
return E1000_SUCCESS;
/* Enable CRS on TX. This must be set for half-duplex operation. */
ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
if (ret_val)
return ret_val;
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
/* Options:
* MDI/MDI-X = 0 (default)
* 0 - Auto for all speeds
* 1 - MDI mode
* 2 - MDI-X mode
* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
*/
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
switch (hw->mdix) {
case 1:
phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
break;
case 2:
phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
break;
case 3:
phy_data |= M88E1000_PSCR_AUTO_X_1000T;
break;
case 0:
default:
phy_data |= M88E1000_PSCR_AUTO_X_MODE;
break;
}
/* Options:
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
* 1 - Enabled
*/
phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
if (ret_val)
return ret_val;
if (hw->phy_revision < M88E1011_I_REV_4) {
/* Force TX_CLK in the Extended PHY Specific Control Register
* to 25MHz clock.
*/
ret_val = e1000_read_phy_reg(hw,
M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
if (ret_val)
return ret_val;
phy_data |= M88E1000_EPSCR_TX_CLK_25;
if ((hw->phy_revision == E1000_REVISION_2) &&
(hw->phy_id == M88E1111_I_PHY_ID)) {
/* Vidalia Phy, set the downshift counter to 5x */
phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
ret_val = e1000_write_phy_reg(hw,
M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
if (ret_val)
return ret_val;
} else {
/* Configure Master and Slave downshift values */
phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
| M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
| M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ret_val = e1000_write_phy_reg(hw,
M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
if (ret_val)
return ret_val;
}
}
/* SW Reset the PHY so all changes take effect */
ret_val = e1000_phy_reset(hw);
if (ret_val) {
DEBUGOUT("Error Resetting the PHY\n");
return ret_val;
}
return E1000_SUCCESS;
}
/********************************************************************
* Setup auto-negotiation and flow control advertisements,
* and then perform auto-negotiation.
*
* hw - Struct containing variables accessed by shared code
*********************************************************************/
static int32_t
e1000_copper_link_autoneg(struct e1000_hw *hw)
{
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC();
/* Perform some bounds checking on the hw->autoneg_advertised
* parameter. If this variable is zero, then set it to the default.
*/
hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
/* If autoneg_advertised is zero, we assume it was not defaulted
* by the calling code so we set to advertise full capability.
*/
if (hw->autoneg_advertised == 0)
hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
/* IFE phy only supports 10/100 */
if (hw->phy_type == e1000_phy_ife)
hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
ret_val = e1000_phy_setup_autoneg(hw);
if (ret_val) {
DEBUGOUT("Error Setting up Auto-Negotiation\n");
return ret_val;
}
DEBUGOUT("Restarting Auto-Neg\n");
/* Restart auto-negotiation by setting the Auto Neg Enable bit and
* the Auto Neg Restart bit in the PHY control register.
*/
ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
if (ret_val)
return ret_val;
phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
if (ret_val)
return ret_val;
/* Does the user want to wait for Auto-Neg to complete here, or
* check at a later time (for example, callback routine).
*/
/* If we do not wait for autonegtation to complete I
* do not see a valid link status.
* wait_autoneg_complete = 1 .
*/
if (hw->wait_autoneg_complete) {
ret_val = e1000_wait_autoneg(hw);
if (ret_val) {
DEBUGOUT("Error while waiting for autoneg"
"to complete\n");
return ret_val;
}
}
hw->get_link_status = TRUE;
return E1000_SUCCESS;
}
/******************************************************************************
* Config the MAC and the PHY after link is up.
* 1) Set up the MAC to the current PHY speed/duplex
* if we are on 82543. If we
* are on newer silicon, we only need to configure
* collision distance in the Transmit Control Register.
* 2) Set up flow control on the MAC to that established with
* the link partner.
* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int32_t
e1000_copper_link_postconfig(struct e1000_hw *hw)
{
int32_t ret_val;
DEBUGFUNC();
if (hw->mac_type >= e1000_82544) {
e1000_config_collision_dist(hw);
} else {
ret_val = e1000_config_mac_to_phy(hw);
if (ret_val) {
DEBUGOUT("Error configuring MAC to PHY settings\n");
return ret_val;
}
}
ret_val = e1000_config_fc_after_link_up(hw);
if (ret_val) {
DEBUGOUT("Error Configuring Flow Control\n");
return ret_val;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Detects which PHY is present and setup the speed and duplex
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int
e1000_setup_copper_link(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
int32_t ret_val;
uint16_t i;
uint16_t phy_data;
uint16_t reg_data;
DEBUGFUNC();
switch (hw->mac_type) {
case e1000_80003es2lan:
case e1000_ich8lan:
/* Set the mac to wait the maximum time between each
* iteration and increase the max iterations when
* polling the phy; this fixes erroneous timeouts at 10Mbps. */
ret_val = e1000_write_kmrn_reg(hw,
GG82563_REG(0x34, 4), 0xFFFF);
if (ret_val)
return ret_val;
ret_val = e1000_read_kmrn_reg(hw,
GG82563_REG(0x34, 9), ®_data);
if (ret_val)
return ret_val;
reg_data |= 0x3F;
ret_val = e1000_write_kmrn_reg(hw,
GG82563_REG(0x34, 9), reg_data);
if (ret_val)
return ret_val;
default:
break;
}
/* Check if it is a valid PHY and set PHY mode if necessary. */
ret_val = e1000_copper_link_preconfig(hw);
if (ret_val)
return ret_val;
switch (hw->mac_type) {
case e1000_80003es2lan:
/* Kumeran registers are written-only */
reg_data =
E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
ret_val = e1000_write_kmrn_reg(hw,
E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
if (ret_val)
return ret_val;
break;
default:
break;
}
if (hw->phy_type == e1000_phy_igp ||
hw->phy_type == e1000_phy_igp_3 ||
hw->phy_type == e1000_phy_igp_2) {
ret_val = e1000_copper_link_igp_setup(hw);
if (ret_val)
return ret_val;
} else if (hw->phy_type == e1000_phy_m88) {
ret_val = e1000_copper_link_mgp_setup(hw);
if (ret_val)
return ret_val;
} else if (hw->phy_type == e1000_phy_gg82563) {
ret_val = e1000_copper_link_ggp_setup(hw);
if (ret_val)
return ret_val;
}
/* always auto */
/* Setup autoneg and flow control advertisement
* and perform autonegotiation */
ret_val = e1000_copper_link_autoneg(hw);
if (ret_val)
return ret_val;
/* Check link status. Wait up to 100 microseconds for link to become
* valid.
*/
for (i = 0; i < 10; i++) {
ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
if (ret_val)
return ret_val;
ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
if (ret_val)
return ret_val;
if (phy_data & MII_SR_LINK_STATUS) {
/* Config the MAC and PHY after link is up */
ret_val = e1000_copper_link_postconfig(hw);
if (ret_val)
return ret_val;
DEBUGOUT("Valid link established!!!\n");
return E1000_SUCCESS;
}
udelay(10);
}
DEBUGOUT("Unable to establish link!!!\n");
return E1000_SUCCESS;
}
/******************************************************************************
* Configures PHY autoneg and flow control advertisement settings
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
int32_t
e1000_phy_setup_autoneg(struct e1000_hw *hw)
{
int32_t ret_val;
uint16_t mii_autoneg_adv_reg;
uint16_t mii_1000t_ctrl_reg;
DEBUGFUNC();
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
if (ret_val)
return ret_val;
if (hw->phy_type != e1000_phy_ife) {
/* Read the MII 1000Base-T Control Register (Address 9). */
ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
&mii_1000t_ctrl_reg);
if (ret_val)
return ret_val;
} else
mii_1000t_ctrl_reg = 0;
/* Need to parse both autoneg_advertised and fc and set up
* the appropriate PHY registers. First we will parse for
* autoneg_advertised software override. Since we can advertise
* a plethora of combinations, we need to check each bit
* individually.
*/
/* First we clear all the 10/100 mb speed bits in the Auto-Neg
* Advertisement Register (Address 4) and the 1000 mb speed bits in
* the 1000Base-T Control Register (Address 9).
*/
mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
/* Do we want to advertise 10 Mb Half Duplex? */
if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
DEBUGOUT("Advertise 10mb Half duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
}
/* Do we want to advertise 10 Mb Full Duplex? */
if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
DEBUGOUT("Advertise 10mb Full duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
}
/* Do we want to advertise 100 Mb Half Duplex? */
if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
DEBUGOUT("Advertise 100mb Half duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
}
/* Do we want to advertise 100 Mb Full Duplex? */
if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
DEBUGOUT("Advertise 100mb Full duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
}
/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
DEBUGOUT
("Advertise 1000mb Half duplex requested, request denied!\n");
}
/* Do we want to advertise 1000 Mb Full Duplex? */
if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
DEBUGOUT("Advertise 1000mb Full duplex\n");
mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
}
/* Check for a software override of the flow control settings, and
* setup the PHY advertisement registers accordingly. If
* auto-negotiation is enabled, then software will have to set the
* "PAUSE" bits to the correct value in the Auto-Negotiation
* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* but we do not support receiving pause frames).
* 3: Both Rx and TX flow control (symmetric) are enabled.
* other: No software override. The flow control configuration
* in the EEPROM is used.
*/
switch (hw->fc) {
case e1000_fc_none: /* 0 */
/* Flow control (RX & TX) is completely disabled by a
* software over-ride.
*/
mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_rx_pause: /* 1 */
/* RX Flow control is enabled, and TX Flow control is
* disabled, by a software over-ride.
*/
/* Since there really isn't a way to advertise that we are
* capable of RX Pause ONLY, we will advertise that we
* support both symmetric and asymmetric RX PAUSE. Later
* (in e1000_config_fc_after_link_up) we will disable the
*hw's ability to send PAUSE frames.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_tx_pause: /* 2 */
/* TX Flow control is enabled, and RX Flow control is
* disabled, by a software over-ride.
*/
mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
break;
case e1000_fc_full: /* 3 */
/* Flow control (both RX and TX) is enabled by a software
* over-ride.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
return -E1000_ERR_CONFIG;
}
ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
if (ret_val)
return ret_val;
DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
if (hw->phy_type != e1000_phy_ife) {
ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
mii_1000t_ctrl_reg);
if (ret_val)
return ret_val;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Sets the collision distance in the Transmit Control register
*
* hw - Struct containing variables accessed by shared code
*
* Link should have been established previously. Reads the speed and duplex
* information from the Device Status register.
******************************************************************************/
static void
e1000_config_collision_dist(struct e1000_hw *hw)
{
uint32_t tctl, coll_dist;
DEBUGFUNC();
if (hw->mac_type < e1000_82543)
coll_dist = E1000_COLLISION_DISTANCE_82542;
else
coll_dist = E1000_COLLISION_DISTANCE;
tctl = E1000_READ_REG(hw, TCTL);
tctl &= ~E1000_TCTL_COLD;
tctl |= coll_dist << E1000_COLD_SHIFT;
E1000_WRITE_REG(hw, TCTL, tctl);
E1000_WRITE_FLUSH(hw);
}
/******************************************************************************
* Sets MAC speed and duplex settings to reflect the those in the PHY
*
* hw - Struct containing variables accessed by shared code
* mii_reg - data to write to the MII control register
*
* The contents of the PHY register containing the needed information need to
* be passed in.
******************************************************************************/
static int
e1000_config_mac_to_phy(struct e1000_hw *hw)
{
uint32_t ctrl;
uint16_t phy_data;
DEBUGFUNC();
/* Read the Device Control Register and set the bits to Force Speed
* and Duplex.
*/
ctrl = E1000_READ_REG(hw, CTRL);
ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
/* Set up duplex in the Device Control and Transmit Control
* registers depending on negotiated values.
*/
if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
DEBUGOUT("PHY Read Error\n");
return -E1000_ERR_PHY;
}
if (phy_data & M88E1000_PSSR_DPLX)
ctrl |= E1000_CTRL_FD;
else
ctrl &= ~E1000_CTRL_FD;
e1000_config_collision_dist(hw);
/* Set up speed in the Device Control register depending on
* negotiated values.
*/
if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
ctrl |= E1000_CTRL_SPD_1000;
else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
ctrl |= E1000_CTRL_SPD_100;
/* Write the configured values back to the Device Control Reg. */
E1000_WRITE_REG(hw, CTRL, ctrl);
return 0;
}
/******************************************************************************
* Forces the MAC's flow control settings.
*
* hw - Struct containing variables accessed by shared code
*
* Sets the TFCE and RFCE bits in the device control register to reflect
* the adapter settings. TFCE and RFCE need to be explicitly set by
* software when a Copper PHY is used because autonegotiation is managed
* by the PHY rather than the MAC. Software must also configure these
* bits when link is forced on a fiber connection.
*****************************************************************************/
static int
e1000_force_mac_fc(struct e1000_hw *hw)
{
uint32_t ctrl;
DEBUGFUNC();
/* Get the current configuration of the Device Control Register */
ctrl = E1000_READ_REG(hw, CTRL);
/* Because we didn't get link via the internal auto-negotiation
* mechanism (we either forced link or we got link via PHY
* auto-neg), we have to manually enable/disable transmit an
* receive flow control.
*
* The "Case" statement below enables/disable flow control
* according to the "hw->fc" parameter.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause
* frames but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* frames but we do not receive pause frames).
* 3: Both Rx and TX flow control (symmetric) is enabled.
* other: No other values should be possible at this point.
*/
switch (hw->fc) {
case e1000_fc_none:
ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
break;
case e1000_fc_rx_pause:
ctrl &= (~E1000_CTRL_TFCE);
ctrl |= E1000_CTRL_RFCE;
break;
case e1000_fc_tx_pause:
ctrl &= (~E1000_CTRL_RFCE);
ctrl |= E1000_CTRL_TFCE;
break;
case e1000_fc_full:
ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
break;
default:
DEBUGOUT("Flow control param set incorrectly\n");
return -E1000_ERR_CONFIG;
}
/* Disable TX Flow Control for 82542 (rev 2.0) */
if (hw->mac_type == e1000_82542_rev2_0)
ctrl &= (~E1000_CTRL_TFCE);
E1000_WRITE_REG(hw, CTRL, ctrl);
return 0;
}
/******************************************************************************
* Configures flow control settings after link is established
*
* hw - Struct containing variables accessed by shared code
*
* Should be called immediately after a valid link has been established.
* Forces MAC flow control settings if link was forced. When in MII/GMII mode
* and autonegotiation is enabled, the MAC flow control settings will be set
* based on the flow control negotiated by the PHY. In TBI mode, the TFCE
* and RFCE bits will be automaticaly set to the negotiated flow control mode.
*****************************************************************************/
static int32_t
e1000_config_fc_after_link_up(struct e1000_hw *hw)
{
int32_t ret_val;
uint16_t mii_status_reg;
uint16_t mii_nway_adv_reg;
uint16_t mii_nway_lp_ability_reg;
uint16_t speed;
uint16_t duplex;
DEBUGFUNC();
/* Check for the case where we have fiber media and auto-neg failed
* so we had to force link. In this case, we need to force the
* configuration of the MAC to match the "fc" parameter.
*/
if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
|| ((hw->media_type == e1000_media_type_internal_serdes)
&& (hw->autoneg_failed))
|| ((hw->media_type == e1000_media_type_copper)
&& (!hw->autoneg))) {
ret_val = e1000_force_mac_fc(hw);
if (ret_val < 0) {
DEBUGOUT("Error forcing flow control settings\n");
return ret_val;
}
}
/* Check for the case where we have copper media and auto-neg is
* enabled. In this case, we need to check and see if Auto-Neg
* has completed, and if so, how the PHY and link partner has
* flow control configured.
*/
if (hw->media_type == e1000_media_type_copper) {
/* Read the MII Status Register and check to see if AutoNeg
* has completed. We read this twice because this reg has
* some "sticky" (latched) bits.
*/
if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
DEBUGOUT("PHY Read Error \n");
return -E1000_ERR_PHY;
}
if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
DEBUGOUT("PHY Read Error \n");
return -E1000_ERR_PHY;
}
if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
/* The AutoNeg process has completed, so we now need to
* read both the Auto Negotiation Advertisement Register
* (Address 4) and the Auto_Negotiation Base Page Ability
* Register (Address 5) to determine how flow control was
* negotiated.
*/
if (e1000_read_phy_reg
(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
DEBUGOUT("PHY Read Error\n");
return -E1000_ERR_PHY;
}
if (e1000_read_phy_reg
(hw, PHY_LP_ABILITY,
&mii_nway_lp_ability_reg) < 0) {
DEBUGOUT("PHY Read Error\n");
return -E1000_ERR_PHY;
}
/* Two bits in the Auto Negotiation Advertisement Register
* (Address 4) and two bits in the Auto Negotiation Base
* Page Ability Register (Address 5) determine flow control
* for both the PHY and the link partner. The following
* table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
* 1999, describes these PAUSE resolution bits and how flow
* control is determined based upon these settings.
* NOTE: DC = Don't Care
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
*-------|---------|-------|---------|--------------------
* 0 | 0 | DC | DC | e1000_fc_none
* 0 | 1 | 0 | DC | e1000_fc_none
* 0 | 1 | 1 | 0 | e1000_fc_none
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
* 1 | 0 | 0 | DC | e1000_fc_none
* 1 | DC | 1 | DC | e1000_fc_full
* 1 | 1 | 0 | 0 | e1000_fc_none
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
*
*/
/* Are both PAUSE bits set to 1? If so, this implies
* Symmetric Flow Control is enabled at both ends. The
* ASM_DIR bits are irrelevant per the spec.
*
* For Symmetric Flow Control:
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
*-------|---------|-------|---------|--------------------
* 1 | DC | 1 | DC | e1000_fc_full
*
*/
if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
/* Now we need to check if the user selected RX ONLY
* of pause frames. In this case, we had to advertise
* FULL flow control because we could not advertise RX
* ONLY. Hence, we must now check to see if we need to
* turn OFF the TRANSMISSION of PAUSE frames.
*/
if (hw->original_fc == e1000_fc_full) {
hw->fc = e1000_fc_full;
DEBUGOUT("Flow Control = FULL.\r\n");
} else {
hw->fc = e1000_fc_rx_pause;
DEBUGOUT
("Flow Control = RX PAUSE frames only.\r\n");
}
}
/* For receiving PAUSE frames ONLY.
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
*-------|---------|-------|---------|--------------------
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
*
*/
else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
{
hw->fc = e1000_fc_tx_pause;
DEBUGOUT
("Flow Control = TX PAUSE frames only.\r\n");
}
/* For transmitting PAUSE frames ONLY.
*
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
*-------|---------|-------|---------|--------------------
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
*
*/
else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
{
hw->fc = e1000_fc_rx_pause;
DEBUGOUT
("Flow Control = RX PAUSE frames only.\r\n");
}
/* Per the IEEE spec, at this point flow control should be
* disabled. However, we want to consider that we could
* be connected to a legacy switch that doesn't advertise
* desired flow control, but can be forced on the link
* partner. So if we advertised no flow control, that is
* what we will resolve to. If we advertised some kind of
* receive capability (Rx Pause Only or Full Flow Control)
* and the link partner advertised none, we will configure
* ourselves to enable Rx Flow Control only. We can do
* this safely for two reasons: If the link partner really
* didn't want flow control enabled, and we enable Rx, no
* harm done since we won't be receiving any PAUSE frames
* anyway. If the intent on the link partner was to have
* flow control enabled, then by us enabling RX only, we
* can at least receive pause frames and process them.
* This is a good idea because in most cases, since we are
* predominantly a server NIC, more times than not we will
* be asked to delay transmission of packets than asking
* our link partner to pause transmission of frames.
*/
else if (hw->original_fc == e1000_fc_none ||
hw->original_fc == e1000_fc_tx_pause) {
hw->fc = e1000_fc_none;
DEBUGOUT("Flow Control = NONE.\r\n");
} else {
hw->fc = e1000_fc_rx_pause;
DEBUGOUT
("Flow Control = RX PAUSE frames only.\r\n");
}
/* Now we need to do one last check... If we auto-
* negotiated to HALF DUPLEX, flow control should not be
* enabled per IEEE 802.3 spec.
*/
e1000_get_speed_and_duplex(hw, &speed, &duplex);
if (duplex == HALF_DUPLEX)
hw->fc = e1000_fc_none;
/* Now we call a subroutine to actually force the MAC
* controller to use the correct flow control settings.
*/
ret_val = e1000_force_mac_fc(hw);
if (ret_val < 0) {
DEBUGOUT
("Error forcing flow control settings\n");
return ret_val;
}
} else {
DEBUGOUT
("Copper PHY and Auto Neg has not completed.\r\n");
}
}
return E1000_SUCCESS;
}
/******************************************************************************
* Checks to see if the link status of the hardware has changed.
*
* hw - Struct containing variables accessed by shared code
*
* Called by any function that needs to check the link status of the adapter.
*****************************************************************************/
static int
e1000_check_for_link(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
uint32_t rxcw;
uint32_t ctrl;
uint32_t status;
uint32_t rctl;
uint32_t signal;
int32_t ret_val;
uint16_t phy_data;
uint16_t lp_capability;
DEBUGFUNC();
/* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
* set when the optics detect a signal. On older adapters, it will be
* cleared when there is a signal
*/
ctrl = E1000_READ_REG(hw, CTRL);
if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
signal = E1000_CTRL_SWDPIN1;
else
signal = 0;
status = E1000_READ_REG(hw, STATUS);
rxcw = E1000_READ_REG(hw, RXCW);
DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
/* If we have a copper PHY then we only want to go out to the PHY
* registers to see if Auto-Neg has completed and/or if our link
* status has changed. The get_link_status flag will be set if we
* receive a Link Status Change interrupt or we have Rx Sequence
* Errors.
*/
if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
/* First we want to see if the MII Status Register reports
* link. If so, then we want to get the current speed/duplex
* of the PHY.
* Read the register twice since the link bit is sticky.
*/
if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
DEBUGOUT("PHY Read Error\n");
return -E1000_ERR_PHY;
}
if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
DEBUGOUT("PHY Read Error\n");
return -E1000_ERR_PHY;
}
if (phy_data & MII_SR_LINK_STATUS) {
hw->get_link_status = FALSE;
} else {
/* No link detected */
return -E1000_ERR_NOLINK;
}
/* We have a M88E1000 PHY and Auto-Neg is enabled. If we
* have Si on board that is 82544 or newer, Auto
* Speed Detection takes care of MAC speed/duplex
* configuration. So we only need to configure Collision
* Distance in the MAC. Otherwise, we need to force
* speed/duplex on the MAC to the current PHY speed/duplex
* settings.
*/
if (hw->mac_type >= e1000_82544)
e1000_config_collision_dist(hw);
else {
ret_val = e1000_config_mac_to_phy(hw);
if (ret_val < 0) {
DEBUGOUT
("Error configuring MAC to PHY settings\n");
return ret_val;
}
}
/* Configure Flow Control now that Auto-Neg has completed. First, we
* need to restore the desired flow control settings because we may
* have had to re-autoneg with a different link partner.
*/
ret_val = e1000_config_fc_after_link_up(hw);
if (ret_val < 0) {
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
/* At this point we know that we are on copper and we have
* auto-negotiated link. These are conditions for checking the link
* parter capability register. We use the link partner capability to
* determine if TBI Compatibility needs to be turned on or off. If
* the link partner advertises any speed in addition to Gigabit, then
* we assume that they are GMII-based, and TBI compatibility is not
* needed. If no other speeds are advertised, we assume the link
* partner is TBI-based, and we turn on TBI Compatibility.
*/
if (hw->tbi_compatibility_en) {
if (e1000_read_phy_reg
(hw, PHY_LP_ABILITY, &lp_capability) < 0) {
DEBUGOUT("PHY Read Error\n");
return -E1000_ERR_PHY;
}
if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
NWAY_LPAR_10T_FD_CAPS |
NWAY_LPAR_100TX_HD_CAPS |
NWAY_LPAR_100TX_FD_CAPS |
NWAY_LPAR_100T4_CAPS)) {
/* If our link partner advertises anything in addition to
* gigabit, we do not need to enable TBI compatibility.
*/
if (hw->tbi_compatibility_on) {
/* If we previously were in the mode, turn it off. */
rctl = E1000_READ_REG(hw, RCTL);
rctl &= ~E1000_RCTL_SBP;
E1000_WRITE_REG(hw, RCTL, rctl);
hw->tbi_compatibility_on = FALSE;
}
} else {
/* If TBI compatibility is was previously off, turn it on. For
* compatibility with a TBI link partner, we will store bad
* packets. Some frames have an additional byte on the end and
* will look like CRC errors to to the hardware.
*/
if (!hw->tbi_compatibility_on) {
hw->tbi_compatibility_on = TRUE;
rctl = E1000_READ_REG(hw, RCTL);
rctl |= E1000_RCTL_SBP;
E1000_WRITE_REG(hw, RCTL, rctl);
}
}
}
}
/* If we don't have link (auto-negotiation failed or link partner cannot
* auto-negotiate), the cable is plugged in (we have signal), and our
* link partner is not trying to auto-negotiate with us (we are receiving
* idles or data), we need to force link up. We also need to give
* auto-negotiation time to complete, in case the cable was just plugged
* in. The autoneg_failed flag does this.
*/
else if ((hw->media_type == e1000_media_type_fiber) &&
(!(status & E1000_STATUS_LU)) &&
((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
(!(rxcw & E1000_RXCW_C))) {
if (hw->autoneg_failed == 0) {
hw->autoneg_failed = 1;
return 0;
}
DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
/* Disable auto-negotiation in the TXCW register */
E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
/* Force link-up and also force full-duplex. */
ctrl = E1000_READ_REG(hw, CTRL);
ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
E1000_WRITE_REG(hw, CTRL, ctrl);
/* Configure Flow Control after forcing link up. */
ret_val = e1000_config_fc_after_link_up(hw);
if (ret_val < 0) {
DEBUGOUT("Error configuring flow control\n");
return ret_val;
}
}
/* If we are forcing link and we are receiving /C/ ordered sets, re-enable
* auto-negotiation in the TXCW register and disable forced link in the
* Device Control register in an attempt to auto-negotiate with our link
* partner.
*/
else if ((hw->media_type == e1000_media_type_fiber) &&
(ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
DEBUGOUT
("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
E1000_WRITE_REG(hw, TXCW, hw->txcw);
E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
}
return 0;
}
/******************************************************************************
* Configure the MAC-to-PHY interface for 10/100Mbps
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int32_t
e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
{
int32_t ret_val = E1000_SUCCESS;
uint32_t tipg;
uint16_t reg_data;
DEBUGFUNC();
reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
ret_val = e1000_write_kmrn_reg(hw,
E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
if (ret_val)
return ret_val;
/* Configure Transmit Inter-Packet Gap */
tipg = E1000_READ_REG(hw, TIPG);
tipg &= ~E1000_TIPG_IPGT_MASK;
tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
E1000_WRITE_REG(hw, TIPG, tipg);
ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
if (ret_val)
return ret_val;
if (duplex == HALF_DUPLEX)
reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
else
reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
return ret_val;
}
static int32_t
e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
{
int32_t ret_val = E1000_SUCCESS;
uint16_t reg_data;
uint32_t tipg;
DEBUGFUNC();
reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
ret_val = e1000_write_kmrn_reg(hw,
E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
if (ret_val)
return ret_val;
/* Configure Transmit Inter-Packet Gap */
tipg = E1000_READ_REG(hw, TIPG);
tipg &= ~E1000_TIPG_IPGT_MASK;
tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
E1000_WRITE_REG(hw, TIPG, tipg);
ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
if (ret_val)
return ret_val;
reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
return ret_val;
}
/******************************************************************************
* Detects the current speed and duplex settings of the hardware.
*
* hw - Struct containing variables accessed by shared code
* speed - Speed of the connection
* duplex - Duplex setting of the connection
*****************************************************************************/
static int
e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
uint16_t *duplex)
{
uint32_t status;
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC();
if (hw->mac_type >= e1000_82543) {
status = E1000_READ_REG(hw, STATUS);
if (status & E1000_STATUS_SPEED_1000) {
*speed = SPEED_1000;
DEBUGOUT("1000 Mbs, ");
} else if (status & E1000_STATUS_SPEED_100) {
*speed = SPEED_100;
DEBUGOUT("100 Mbs, ");
} else {
*speed = SPEED_10;
DEBUGOUT("10 Mbs, ");
}
if (status & E1000_STATUS_FD) {
*duplex = FULL_DUPLEX;
DEBUGOUT("Full Duplex\r\n");
} else {
*duplex = HALF_DUPLEX;
DEBUGOUT(" Half Duplex\r\n");
}
} else {
DEBUGOUT("1000 Mbs, Full Duplex\r\n");
*speed = SPEED_1000;
*duplex = FULL_DUPLEX;
}
/* IGP01 PHY may advertise full duplex operation after speed downgrade
* even if it is operating at half duplex. Here we set the duplex
* settings to match the duplex in the link partner's capabilities.
*/
if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
if (ret_val)
return ret_val;
if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
*duplex = HALF_DUPLEX;
else {
ret_val = e1000_read_phy_reg(hw,
PHY_LP_ABILITY, &phy_data);
if (ret_val)
return ret_val;
if ((*speed == SPEED_100 &&
!(phy_data & NWAY_LPAR_100TX_FD_CAPS))
|| (*speed == SPEED_10
&& !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
*duplex = HALF_DUPLEX;
}
}
if ((hw->mac_type == e1000_80003es2lan) &&
(hw->media_type == e1000_media_type_copper)) {
if (*speed == SPEED_1000)
ret_val = e1000_configure_kmrn_for_1000(hw);
else
ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
if (ret_val)
return ret_val;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Blocks until autoneg completes or times out (~4.5 seconds)
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int
e1000_wait_autoneg(struct e1000_hw *hw)
{
uint16_t i;
uint16_t phy_data;
DEBUGFUNC();
DEBUGOUT("Waiting for Auto-Neg to complete.\n");
/* We will wait for autoneg to complete or 4.5 seconds to expire. */
for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
/* Read the MII Status Register and wait for Auto-Neg
* Complete bit to be set.
*/
if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
DEBUGOUT("PHY Read Error\n");
return -E1000_ERR_PHY;
}
if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
DEBUGOUT("PHY Read Error\n");
return -E1000_ERR_PHY;
}
if (phy_data & MII_SR_AUTONEG_COMPLETE) {
DEBUGOUT("Auto-Neg complete.\n");
return 0;
}
mdelay(100);
}
DEBUGOUT("Auto-Neg timedout.\n");
return -E1000_ERR_TIMEOUT;
}
/******************************************************************************
* Raises the Management Data Clock
*
* hw - Struct containing variables accessed by shared code
* ctrl - Device control register's current value
******************************************************************************/
static void
e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
{
/* Raise the clock input to the Management Data Clock (by setting the MDC
* bit), and then delay 2 microseconds.
*/
E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
E1000_WRITE_FLUSH(hw);
udelay(2);
}
/******************************************************************************
* Lowers the Management Data Clock
*
* hw - Struct containing variables accessed by shared code
* ctrl - Device control register's current value
******************************************************************************/
static void
e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
{
/* Lower the clock input to the Management Data Clock (by clearing the MDC
* bit), and then delay 2 microseconds.
*/
E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
E1000_WRITE_FLUSH(hw);
udelay(2);
}
/******************************************************************************
* Shifts data bits out to the PHY
*
* hw - Struct containing variables accessed by shared code
* data - Data to send out to the PHY
* count - Number of bits to shift out
*
* Bits are shifted out in MSB to LSB order.
******************************************************************************/
static void
e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
{
uint32_t ctrl;
uint32_t mask;
/* We need to shift "count" number of bits out to the PHY. So, the value
* in the "data" parameter will be shifted out to the PHY one bit at a
* time. In order to do this, "data" must be broken down into bits.
*/
mask = 0x01;
mask <<= (count - 1);
ctrl = E1000_READ_REG(hw, CTRL);
/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
while (mask) {
/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
* then raising and lowering the Management Data Clock. A "0" is
* shifted out to the PHY by setting the MDIO bit to "0" and then
* raising and lowering the clock.
*/
if (data & mask)
ctrl |= E1000_CTRL_MDIO;
else
ctrl &= ~E1000_CTRL_MDIO;
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
udelay(2);
e1000_raise_mdi_clk(hw, &ctrl);
e1000_lower_mdi_clk(hw, &ctrl);
mask = mask >> 1;
}
}
/******************************************************************************
* Shifts data bits in from the PHY
*
* hw - Struct containing variables accessed by shared code
*
* Bits are shifted in in MSB to LSB order.
******************************************************************************/
static uint16_t
e1000_shift_in_mdi_bits(struct e1000_hw *hw)
{
uint32_t ctrl;
uint16_t data = 0;
uint8_t i;
/* In order to read a register from the PHY, we need to shift in a total
* of 18 bits from the PHY. The first two bit (turnaround) times are used
* to avoid contention on the MDIO pin when a read operation is performed.
* These two bits are ignored by us and thrown away. Bits are "shifted in"
* by raising the input to the Management Data Clock (setting the MDC bit),
* and then reading the value of the MDIO bit.
*/
ctrl = E1000_READ_REG(hw, CTRL);
/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
ctrl &= ~E1000_CTRL_MDIO_DIR;
ctrl &= ~E1000_CTRL_MDIO;
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
/* Raise and Lower the clock before reading in the data. This accounts for
* the turnaround bits. The first clock occurred when we clocked out the
* last bit of the Register Address.
*/
e1000_raise_mdi_clk(hw, &ctrl);
e1000_lower_mdi_clk(hw, &ctrl);
for (data = 0, i = 0; i < 16; i++) {
data = data << 1;
e1000_raise_mdi_clk(hw, &ctrl);
ctrl = E1000_READ_REG(hw, CTRL);
/* Check to see if we shifted in a "1". */
if (ctrl & E1000_CTRL_MDIO)
data |= 1;
e1000_lower_mdi_clk(hw, &ctrl);
}
e1000_raise_mdi_clk(hw, &ctrl);
e1000_lower_mdi_clk(hw, &ctrl);
return data;
}
/*****************************************************************************
* Reads the value from a PHY register
*
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to read
******************************************************************************/
static int
e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
{
uint32_t i;
uint32_t mdic = 0;
const uint32_t phy_addr = 1;
if (reg_addr > MAX_PHY_REG_ADDRESS) {
DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
return -E1000_ERR_PARAM;
}
if (hw->mac_type > e1000_82543) {
/* Set up Op-code, Phy Address, and register address in the MDI
* Control register. The MAC will take care of interfacing with the
* PHY to retrieve the desired data.
*/
mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
(phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_READ));
E1000_WRITE_REG(hw, MDIC, mdic);
/* Poll the ready bit to see if the MDI read completed */
for (i = 0; i < 64; i++) {
udelay(10);
mdic = E1000_READ_REG(hw, MDIC);
if (mdic & E1000_MDIC_READY)
break;
}
if (!(mdic & E1000_MDIC_READY)) {
DEBUGOUT("MDI Read did not complete\n");
return -E1000_ERR_PHY;
}
if (mdic & E1000_MDIC_ERROR) {
DEBUGOUT("MDI Error\n");
return -E1000_ERR_PHY;
}
*phy_data = (uint16_t) mdic;
} else {
/* We must first send a preamble through the MDIO pin to signal the
* beginning of an MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/* Now combine the next few fields that are required for a read
* operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine five different times. The format of
* a MII read instruction consists of a shift out of 14 bits and is
* defined as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
* followed by a shift in of 18 bits. This first two bits shifted in
* are TurnAround bits used to avoid contention on the MDIO pin when a
* READ operation is performed. These two bits are thrown away
* followed by a shift in of 16 bits which contains the desired data.
*/
mdic = ((reg_addr) | (phy_addr << 5) |
(PHY_OP_READ << 10) | (PHY_SOF << 12));
e1000_shift_out_mdi_bits(hw, mdic, 14);
/* Now that we've shifted out the read command to the MII, we need to
* "shift in" the 16-bit value (18 total bits) of the requested PHY
* register address.
*/
*phy_data = e1000_shift_in_mdi_bits(hw);
}
return 0;
}
/******************************************************************************
* Writes a value to a PHY register
*
* hw - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to write
* data - data to write to the PHY
******************************************************************************/
static int
e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
{
uint32_t i;
uint32_t mdic = 0;
const uint32_t phy_addr = 1;
if (reg_addr > MAX_PHY_REG_ADDRESS) {
DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
return -E1000_ERR_PARAM;
}
if (hw->mac_type > e1000_82543) {
/* Set up Op-code, Phy Address, register address, and data intended
* for the PHY register in the MDI Control register. The MAC will take
* care of interfacing with the PHY to send the desired data.
*/
mdic = (((uint32_t) phy_data) |
(reg_addr << E1000_MDIC_REG_SHIFT) |
(phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_WRITE));
E1000_WRITE_REG(hw, MDIC, mdic);
/* Poll the ready bit to see if the MDI read completed */
for (i = 0; i < 64; i++) {
udelay(10);
mdic = E1000_READ_REG(hw, MDIC);
if (mdic & E1000_MDIC_READY)
break;
}
if (!(mdic & E1000_MDIC_READY)) {
DEBUGOUT("MDI Write did not complete\n");
return -E1000_ERR_PHY;
}
} else {
/* We'll need to use the SW defined pins to shift the write command
* out to the PHY. We first send a preamble to the PHY to signal the
* beginning of the MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/* Now combine the remaining required fields that will indicate a
* write operation. We use this method instead of calling the
* e1000_shift_out_mdi_bits routine for each field in the command. The
* format of a MII write instruction is as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
*/
mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
mdic <<= 16;
mdic |= (uint32_t) phy_data;
e1000_shift_out_mdi_bits(hw, mdic, 32);
}
return 0;
}
/******************************************************************************
* Checks if PHY reset is blocked due to SOL/IDER session, for example.
* Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
* the caller to figure out how to deal with it.
*
* hw - Struct containing variables accessed by shared code
*
* returns: - E1000_BLK_PHY_RESET
* E1000_SUCCESS
*
*****************************************************************************/
int32_t
e1000_check_phy_reset_block(struct e1000_hw *hw)
{
uint32_t manc = 0;
uint32_t fwsm = 0;
if (hw->mac_type == e1000_ich8lan) {
fwsm = E1000_READ_REG(hw, FWSM);
return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
: E1000_BLK_PHY_RESET;
}
if (hw->mac_type > e1000_82547_rev_2)
manc = E1000_READ_REG(hw, MANC);
return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
E1000_BLK_PHY_RESET : E1000_SUCCESS;
}
/***************************************************************************
* Checks if the PHY configuration is done
*
* hw: Struct containing variables accessed by shared code
*
* returns: - E1000_ERR_RESET if fail to reset MAC
* E1000_SUCCESS at any other case.
*
***************************************************************************/
static int32_t
e1000_get_phy_cfg_done(struct e1000_hw *hw)
{
int32_t timeout = PHY_CFG_TIMEOUT;
uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
DEBUGFUNC();
switch (hw->mac_type) {
default:
mdelay(10);
break;
case e1000_80003es2lan:
/* Separate *_CFG_DONE_* bit for each port */
if (e1000_is_second_port(hw))
cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
/* Fall Through */
case e1000_82571:
case e1000_82572:
while (timeout) {
if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
break;
else
mdelay(1);
timeout--;
}
if (!timeout) {
DEBUGOUT("MNG configuration cycle has not "
"completed.\n");
return -E1000_ERR_RESET;
}
break;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Returns the PHY to the power-on reset state
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
int32_t
e1000_phy_hw_reset(struct e1000_hw *hw)
{
uint16_t swfw = E1000_SWFW_PHY0_SM;
uint32_t ctrl, ctrl_ext;
uint32_t led_ctrl;
int32_t ret_val;
DEBUGFUNC();
/* In the case of the phy reset being blocked, it's not an error, we
* simply return success without performing the reset. */
ret_val = e1000_check_phy_reset_block(hw);
if (ret_val)
return E1000_SUCCESS;
DEBUGOUT("Resetting Phy...\n");
if (hw->mac_type > e1000_82543) {
if (e1000_is_second_port(hw))
swfw = E1000_SWFW_PHY1_SM;
if (e1000_swfw_sync_acquire(hw, swfw)) {
DEBUGOUT("Unable to acquire swfw sync\n");
return -E1000_ERR_SWFW_SYNC;
}
/* Read the device control register and assert the E1000_CTRL_PHY_RST
* bit. Then, take it out of reset.
*/
ctrl = E1000_READ_REG(hw, CTRL);
E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
E1000_WRITE_FLUSH(hw);
if (hw->mac_type < e1000_82571)
udelay(10);
else
udelay(100);
E1000_WRITE_REG(hw, CTRL, ctrl);
E1000_WRITE_FLUSH(hw);
if (hw->mac_type >= e1000_82571)
mdelay(10);
} else {
/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
* bit to put the PHY into reset. Then, take it out of reset.
*/
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
mdelay(10);
ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
}
udelay(150);
if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
/* Configure activity LED after PHY reset */
led_ctrl = E1000_READ_REG(hw, LEDCTL);
led_ctrl &= IGP_ACTIVITY_LED_MASK;
led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
}
/* Wait for FW to finish PHY configuration. */
ret_val = e1000_get_phy_cfg_done(hw);
if (ret_val != E1000_SUCCESS)
return ret_val;
return ret_val;
}
/******************************************************************************
* IGP phy init script - initializes the GbE PHY
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
e1000_phy_init_script(struct e1000_hw *hw)
{
uint32_t ret_val;
uint16_t phy_saved_data;
DEBUGFUNC();
if (hw->phy_init_script) {
mdelay(20);
/* Save off the current value of register 0x2F5B to be
* restored at the end of this routine. */
ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
/* Disabled the PHY transmitter */
e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
mdelay(20);
e1000_write_phy_reg(hw, 0x0000, 0x0140);
mdelay(5);
switch (hw->mac_type) {
case e1000_82541:
case e1000_82547:
e1000_write_phy_reg(hw, 0x1F95, 0x0001);
e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
e1000_write_phy_reg(hw, 0x1F79, 0x0018);
e1000_write_phy_reg(hw, 0x1F30, 0x1600);
e1000_write_phy_reg(hw, 0x1F31, 0x0014);
e1000_write_phy_reg(hw, 0x1F32, 0x161C);
e1000_write_phy_reg(hw, 0x1F94, 0x0003);
e1000_write_phy_reg(hw, 0x1F96, 0x003F);
e1000_write_phy_reg(hw, 0x2010, 0x0008);
break;
case e1000_82541_rev_2:
case e1000_82547_rev_2:
e1000_write_phy_reg(hw, 0x1F73, 0x0099);
break;
default:
break;
}
e1000_write_phy_reg(hw, 0x0000, 0x3300);
mdelay(20);
/* Now enable the transmitter */
if (!ret_val)
e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
if (hw->mac_type == e1000_82547) {
uint16_t fused, fine, coarse;
/* Move to analog registers page */
e1000_read_phy_reg(hw,
IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
e1000_read_phy_reg(hw,
IGP01E1000_ANALOG_FUSE_STATUS, &fused);
fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
coarse = fused
& IGP01E1000_ANALOG_FUSE_COARSE_MASK;
if (coarse >
IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
coarse -=
IGP01E1000_ANALOG_FUSE_COARSE_10;
fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
} else if (coarse
== IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
fused = (fused
& IGP01E1000_ANALOG_FUSE_POLY_MASK) |
(fine
& IGP01E1000_ANALOG_FUSE_FINE_MASK) |
(coarse
& IGP01E1000_ANALOG_FUSE_COARSE_MASK);
e1000_write_phy_reg(hw,
IGP01E1000_ANALOG_FUSE_CONTROL, fused);
e1000_write_phy_reg(hw,
IGP01E1000_ANALOG_FUSE_BYPASS,
IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
}
}
}
}
/******************************************************************************
* Resets the PHY
*
* hw - Struct containing variables accessed by shared code
*
* Sets bit 15 of the MII Control register
******************************************************************************/
int32_t
e1000_phy_reset(struct e1000_hw *hw)
{
int32_t ret_val;
uint16_t phy_data;
DEBUGFUNC();
/* In the case of the phy reset being blocked, it's not an error, we
* simply return success without performing the reset. */
ret_val = e1000_check_phy_reset_block(hw);
if (ret_val)
return E1000_SUCCESS;
switch (hw->phy_type) {
case e1000_phy_igp:
case e1000_phy_igp_2:
case e1000_phy_igp_3:
case e1000_phy_ife:
ret_val = e1000_phy_hw_reset(hw);
if (ret_val)
return ret_val;
break;
default:
ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
if (ret_val)
return ret_val;
phy_data |= MII_CR_RESET;
ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
if (ret_val)
return ret_val;
udelay(1);
break;
}
if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
e1000_phy_init_script(hw);
return E1000_SUCCESS;
}
static int e1000_set_phy_type (struct e1000_hw *hw)
{
DEBUGFUNC ();
if (hw->mac_type == e1000_undefined)
return -E1000_ERR_PHY_TYPE;
switch (hw->phy_id) {
case M88E1000_E_PHY_ID:
case M88E1000_I_PHY_ID:
case M88E1011_I_PHY_ID:
case M88E1111_I_PHY_ID:
hw->phy_type = e1000_phy_m88;
break;
case IGP01E1000_I_PHY_ID:
if (hw->mac_type == e1000_82541 ||
hw->mac_type == e1000_82541_rev_2 ||
hw->mac_type == e1000_82547 ||
hw->mac_type == e1000_82547_rev_2) {
hw->phy_type = e1000_phy_igp;
hw->phy_type = e1000_phy_igp;
break;
}
case IGP03E1000_E_PHY_ID:
hw->phy_type = e1000_phy_igp_3;
break;
case IFE_E_PHY_ID:
case IFE_PLUS_E_PHY_ID:
case IFE_C_E_PHY_ID:
hw->phy_type = e1000_phy_ife;
break;
case GG82563_E_PHY_ID:
if (hw->mac_type == e1000_80003es2lan) {
hw->phy_type = e1000_phy_gg82563;
break;
}
case BME1000_E_PHY_ID:
hw->phy_type = e1000_phy_bm;
break;
/* Fall Through */
default:
/* Should never have loaded on this device */
hw->phy_type = e1000_phy_undefined;
return -E1000_ERR_PHY_TYPE;
}
return E1000_SUCCESS;
}
/******************************************************************************
* Probes the expected PHY address for known PHY IDs
*
* hw - Struct containing variables accessed by shared code
******************************************************************************/
static int32_t
e1000_detect_gig_phy(struct e1000_hw *hw)
{
int32_t phy_init_status, ret_val;
uint16_t phy_id_high, phy_id_low;
boolean_t match = FALSE;
DEBUGFUNC();
/* The 82571 firmware may still be configuring the PHY. In this
* case, we cannot access the PHY until the configuration is done. So
* we explicitly set the PHY values. */
if (hw->mac_type == e1000_82571 ||
hw->mac_type == e1000_82572) {
hw->phy_id = IGP01E1000_I_PHY_ID;
hw->phy_type = e1000_phy_igp_2;
return E1000_SUCCESS;
}
/* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
* work- around that forces PHY page 0 to be set or the reads fail.
* The rest of the code in this routine uses e1000_read_phy_reg to
* read the PHY ID. So for ESB-2 we need to have this set so our
* reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
* the routines below will figure this out as well. */
if (hw->mac_type == e1000_80003es2lan)
hw->phy_type = e1000_phy_gg82563;
/* Read the PHY ID Registers to identify which PHY is onboard. */
ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
if (ret_val)
return ret_val;
hw->phy_id = (uint32_t) (phy_id_high << 16);
udelay(20);
ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
if (ret_val)
return ret_val;
hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
switch (hw->mac_type) {
case e1000_82543:
if (hw->phy_id == M88E1000_E_PHY_ID)
match = TRUE;
break;
case e1000_82544:
if (hw->phy_id == M88E1000_I_PHY_ID)
match = TRUE;
break;
case e1000_82540:
case e1000_82545:
case e1000_82545_rev_3:
case e1000_82546:
case e1000_82546_rev_3:
if (hw->phy_id == M88E1011_I_PHY_ID)
match = TRUE;
break;
case e1000_82541:
case e1000_82541_rev_2:
case e1000_82547:
case e1000_82547_rev_2:
if(hw->phy_id == IGP01E1000_I_PHY_ID)
match = TRUE;
break;
case e1000_82573:
if (hw->phy_id == M88E1111_I_PHY_ID)
match = TRUE;
break;
case e1000_82574:
if (hw->phy_id == BME1000_E_PHY_ID)
match = TRUE;
break;
case e1000_80003es2lan:
if (hw->phy_id == GG82563_E_PHY_ID)
match = TRUE;
break;
case e1000_ich8lan:
if (hw->phy_id == IGP03E1000_E_PHY_ID)
match = TRUE;
if (hw->phy_id == IFE_E_PHY_ID)
match = TRUE;
if (hw->phy_id == IFE_PLUS_E_PHY_ID)
match = TRUE;
if (hw->phy_id == IFE_C_E_PHY_ID)
match = TRUE;
break;
default:
DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
return -E1000_ERR_CONFIG;
}
phy_init_status = e1000_set_phy_type(hw);
if ((match) && (phy_init_status == E1000_SUCCESS)) {
DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
return 0;
}
DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
return -E1000_ERR_PHY;
}
/*****************************************************************************
* Set media type and TBI compatibility.
*
* hw - Struct containing variables accessed by shared code
* **************************************************************************/
void
e1000_set_media_type(struct e1000_hw *hw)
{
uint32_t status;
DEBUGFUNC();
if (hw->mac_type != e1000_82543) {
/* tbi_compatibility is only valid on 82543 */
hw->tbi_compatibility_en = FALSE;
}
switch (hw->device_id) {
case E1000_DEV_ID_82545GM_SERDES:
case E1000_DEV_ID_82546GB_SERDES:
case E1000_DEV_ID_82571EB_SERDES:
case E1000_DEV_ID_82571EB_SERDES_DUAL:
case E1000_DEV_ID_82571EB_SERDES_QUAD:
case E1000_DEV_ID_82572EI_SERDES:
case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
hw->media_type = e1000_media_type_internal_serdes;
break;
default:
switch (hw->mac_type) {
case e1000_82542_rev2_0:
case e1000_82542_rev2_1:
hw->media_type = e1000_media_type_fiber;
break;
case e1000_ich8lan:
case e1000_82573:
case e1000_82574:
/* The STATUS_TBIMODE bit is reserved or reused
* for the this device.
*/
hw->media_type = e1000_media_type_copper;
break;
default:
status = E1000_READ_REG(hw, STATUS);
if (status & E1000_STATUS_TBIMODE) {
hw->media_type = e1000_media_type_fiber;
/* tbi_compatibility not valid on fiber */
hw->tbi_compatibility_en = FALSE;
} else {
hw->media_type = e1000_media_type_copper;
}
break;
}
}
}
/**
* e1000_sw_init - Initialize general software structures (struct e1000_adapter)
*
* e1000_sw_init initializes the Adapter private data structure.
* Fields are initialized based on PCI device information and
* OS network device settings (MTU size).
**/
static int
e1000_sw_init(struct eth_device *nic)
{
struct e1000_hw *hw = (typeof(hw)) nic->priv;
int result;
/* PCI config space info */
pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
&hw->subsystem_vendor_id);
pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
/* identify the MAC */
result = e1000_set_mac_type(hw);
if (result) {
E1000_ERR(hw->nic, "Unknown MAC Type\n");
return result;
}
switch (hw->mac_type) {
default:
break;
case e1000_82541:
case e1000_82547:
case e1000_82541_rev_2:
case e1000_82547_rev_2:
hw->phy_init_script = 1;
break;
}
/* flow control settings */
hw->fc_high_water = E1000_FC_HIGH_THRESH;
hw->fc_low_water = E1000_FC_LOW_THRESH;
hw->fc_pause_time = E1000_FC_PAUSE_TIME;
hw->fc_send_xon = 1;
/* Media type - copper or fiber */
e1000_set_media_type(hw);
if (hw->mac_type >= e1000_82543) {
uint32_t status = E1000_READ_REG(hw, STATUS);
if (status & E1000_STATUS_TBIMODE) {
DEBUGOUT("fiber interface\n");
hw->media_type = e1000_media_type_fiber;
} else {
DEBUGOUT("copper interface\n");
hw->media_type = e1000_media_type_copper;
}
} else {
hw->media_type = e1000_media_type_fiber;
}
hw->tbi_compatibility_en = TRUE;
hw->wait_autoneg_complete = TRUE;
if (hw->mac_type < e1000_82543)
hw->report_tx_early = 0;
else
hw->report_tx_early = 1;
return E1000_SUCCESS;
}
void
fill_rx(struct e1000_hw *hw)
{
struct e1000_rx_desc *rd;
rx_last = rx_tail;
rd = rx_base + rx_tail;
rx_tail = (rx_tail + 1) % 8;
memset(rd, 0, 16);
rd->buffer_addr = cpu_to_le64((u32) & packet);
E1000_WRITE_REG(hw, RDT, rx_tail);
}
/**
* e1000_configure_tx - Configure 8254x Transmit Unit after Reset
* @adapter: board private structure
*
* Configure the Tx unit of the MAC after a reset.
**/
static void
e1000_configure_tx(struct e1000_hw *hw)
{
unsigned long ptr;
unsigned long tctl;
unsigned long tipg, tarc;
uint32_t ipgr1, ipgr2;
ptr = (u32) tx_pool;
if (ptr & 0xf)
ptr = (ptr + 0x10) & (~0xf);
tx_base = (typeof(tx_base)) ptr;
E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
E1000_WRITE_REG(hw, TDBAH, 0);
E1000_WRITE_REG(hw, TDLEN, 128);
/* Setup the HW Tx Head and Tail descriptor pointers */
E1000_WRITE_REG(hw, TDH, 0);
E1000_WRITE_REG(hw, TDT, 0);
tx_tail = 0;
/* Set the default values for the Tx Inter Packet Gap timer */
if (hw->mac_type <= e1000_82547_rev_2 &&
(hw->media_type == e1000_media_type_fiber ||
hw->media_type == e1000_media_type_internal_serdes))
tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
else
tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
/* Set the default values for the Tx Inter Packet Gap timer */
switch (hw->mac_type) {
case e1000_82542_rev2_0:
case e1000_82542_rev2_1:
tipg = DEFAULT_82542_TIPG_IPGT;
ipgr1 = DEFAULT_82542_TIPG_IPGR1;
ipgr2 = DEFAULT_82542_TIPG_IPGR2;
break;
case e1000_80003es2lan:
ipgr1 = DEFAULT_82543_TIPG_IPGR1;
ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
break;
default:
ipgr1 = DEFAULT_82543_TIPG_IPGR1;
ipgr2 = DEFAULT_82543_TIPG_IPGR2;
break;
}
tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
E1000_WRITE_REG(hw, TIPG, tipg);
/* Program the Transmit Control Register */
tctl = E1000_READ_REG(hw, TCTL);
tctl &= ~E1000_TCTL_CT;
tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
tarc = E1000_READ_REG(hw, TARC0);
/* set the speed mode bit, we'll clear it if we're not at
* gigabit link later */
/* git bit can be set to 1*/
} else if (hw->mac_type == e1000_80003es2lan) {
tarc = E1000_READ_REG(hw, TARC0);
tarc |= 1;
E1000_WRITE_REG(hw, TARC0, tarc);
tarc = E1000_READ_REG(hw, TARC1);
tarc |= 1;
E1000_WRITE_REG(hw, TARC1, tarc);
}
e1000_config_collision_dist(hw);
/* Setup Transmit Descriptor Settings for eop descriptor */
hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
/* Need to set up RS bit */
if (hw->mac_type < e1000_82543)
hw->txd_cmd |= E1000_TXD_CMD_RPS;
else
hw->txd_cmd |= E1000_TXD_CMD_RS;
E1000_WRITE_REG(hw, TCTL, tctl);
}
/**
* e1000_setup_rctl - configure the receive control register
* @adapter: Board private structure
**/
static void
e1000_setup_rctl(struct e1000_hw *hw)
{
uint32_t rctl;
rctl = E1000_READ_REG(hw, RCTL);
rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
| E1000_RCTL_RDMTS_HALF; /* |
(hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
if (hw->tbi_compatibility_on == 1)
rctl |= E1000_RCTL_SBP;
else
rctl &= ~E1000_RCTL_SBP;
rctl &= ~(E1000_RCTL_SZ_4096);
rctl |= E1000_RCTL_SZ_2048;
rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
E1000_WRITE_REG(hw, RCTL, rctl);
}
/**
* e1000_configure_rx - Configure 8254x Receive Unit after Reset
* @adapter: board private structure
*
* Configure the Rx unit of the MAC after a reset.
**/
static void
e1000_configure_rx(struct e1000_hw *hw)
{
unsigned long ptr;
unsigned long rctl, ctrl_ext;
rx_tail = 0;
/* make sure receives are disabled while setting up the descriptors */
rctl = E1000_READ_REG(hw, RCTL);
E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
if (hw->mac_type >= e1000_82540) {
/* Set the interrupt throttling rate. Value is calculated
* as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
#define MAX_INTS_PER_SEC 8000
#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
}
if (hw->mac_type >= e1000_82571) {
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
/* Reset delay timers after every interrupt */
ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
E1000_WRITE_FLUSH(hw);
}
/* Setup the Base and Length of the Rx Descriptor Ring */
ptr = (u32) rx_pool;
if (ptr & 0xf)
ptr = (ptr + 0x10) & (~0xf);
rx_base = (typeof(rx_base)) ptr;
E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
E1000_WRITE_REG(hw, RDBAH, 0);
E1000_WRITE_REG(hw, RDLEN, 128);
/* Setup the HW Rx Head and Tail Descriptor Pointers */
E1000_WRITE_REG(hw, RDH, 0);
E1000_WRITE_REG(hw, RDT, 0);
/* Enable Receives */
E1000_WRITE_REG(hw, RCTL, rctl);
fill_rx(hw);
}
/**************************************************************************
POLL - Wait for a frame
***************************************************************************/
static int
e1000_poll(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
struct e1000_rx_desc *rd;
/* return true if there's an ethernet packet ready to read */
rd = rx_base + rx_last;
if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
return 0;
/*DEBUGOUT("recv: packet len=%d \n", rd->length); */
NetReceive((uchar *)packet, le32_to_cpu(rd->length));
fill_rx(hw);
return 1;
}
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
static int
e1000_transmit(struct eth_device *nic, volatile void *packet, int length)
{
void * nv_packet = (void *)packet;
struct e1000_hw *hw = nic->priv;
struct e1000_tx_desc *txp;
int i = 0;
txp = tx_base + tx_tail;
tx_tail = (tx_tail + 1) % 8;
txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
txp->upper.data = 0;
E1000_WRITE_REG(hw, TDT, tx_tail);
E1000_WRITE_FLUSH(hw);
while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
if (i++ > TOUT_LOOP) {
DEBUGOUT("e1000: tx timeout\n");
return 0;
}
udelay(10); /* give the nic a chance to write to the register */
}
return 1;
}
/*reset function*/
static inline int
e1000_reset(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
e1000_reset_hw(hw);
if (hw->mac_type >= e1000_82544) {
E1000_WRITE_REG(hw, WUC, 0);
}
return e1000_init_hw(nic);
}
/**************************************************************************
DISABLE - Turn off ethernet interface
***************************************************************************/
static void
e1000_disable(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
/* Turn off the ethernet interface */
E1000_WRITE_REG(hw, RCTL, 0);
E1000_WRITE_REG(hw, TCTL, 0);
/* Clear the transmit ring */
E1000_WRITE_REG(hw, TDH, 0);
E1000_WRITE_REG(hw, TDT, 0);
/* Clear the receive ring */
E1000_WRITE_REG(hw, RDH, 0);
E1000_WRITE_REG(hw, RDT, 0);
/* put the card in its initial state */
#if 0
E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
#endif
mdelay(10);
}
/**************************************************************************
INIT - set up ethernet interface(s)
***************************************************************************/
static int
e1000_init(struct eth_device *nic, bd_t * bis)
{
struct e1000_hw *hw = nic->priv;
int ret_val = 0;
ret_val = e1000_reset(nic);
if (ret_val < 0) {
if ((ret_val == -E1000_ERR_NOLINK) ||
(ret_val == -E1000_ERR_TIMEOUT)) {
E1000_ERR(hw->nic, "Valid Link not detected\n");
} else {
E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
}
return 0;
}
e1000_configure_tx(hw);
e1000_setup_rctl(hw);
e1000_configure_rx(hw);
return 1;
}
/******************************************************************************
* Gets the current PCI bus type of hardware
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
void e1000_get_bus_type(struct e1000_hw *hw)
{
uint32_t status;
switch (hw->mac_type) {
case e1000_82542_rev2_0:
case e1000_82542_rev2_1:
hw->bus_type = e1000_bus_type_pci;
break;
case e1000_82571:
case e1000_82572:
case e1000_82573:
case e1000_82574:
case e1000_80003es2lan:
hw->bus_type = e1000_bus_type_pci_express;
break;
case e1000_ich8lan:
hw->bus_type = e1000_bus_type_pci_express;
break;
default:
status = E1000_READ_REG(hw, STATUS);
hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
e1000_bus_type_pcix : e1000_bus_type_pci;
break;
}
}
/* A list of all registered e1000 devices */
static LIST_HEAD(e1000_hw_list);
/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
You should omit the last argument struct pci_device * for a non-PCI NIC
***************************************************************************/
int
e1000_initialize(bd_t * bis)
{
unsigned int i;
pci_dev_t devno;
DEBUGFUNC();
/* Find and probe all the matching PCI devices */
for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
u32 val;
/*
* These will never get freed due to errors, this allows us to
* perform SPI EEPROM programming from U-boot, for example.
*/
struct eth_device *nic = malloc(sizeof(*nic));
struct e1000_hw *hw = malloc(sizeof(*hw));
if (!nic || !hw) {
printf("e1000#%u: Out of Memory!\n", i);
free(nic);
free(hw);
continue;
}
/* Make sure all of the fields are initially zeroed */
memset(nic, 0, sizeof(*nic));
memset(hw, 0, sizeof(*hw));
/* Assign the passed-in values */
hw->cardnum = i;
hw->pdev = devno;
hw->nic = nic;
nic->priv = hw;
/* Generate a card name */
sprintf(nic->name, "e1000#%u", hw->cardnum);
/* Print a debug message with the IO base address */
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
/* Try to enable I/O accesses and bus-mastering */
val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
pci_write_config_dword(devno, PCI_COMMAND, val);
/* Make sure it worked */
pci_read_config_dword(devno, PCI_COMMAND, &val);
if (!(val & PCI_COMMAND_MEMORY)) {
E1000_ERR(nic, "Can't enable I/O memory\n");
continue;
}
if (!(val & PCI_COMMAND_MASTER)) {
E1000_ERR(nic, "Can't enable bus-mastering\n");
continue;
}
/* Are these variables needed? */
hw->fc = e1000_fc_default;
hw->original_fc = e1000_fc_default;
hw->autoneg_failed = 0;
hw->autoneg = 1;
hw->get_link_status = TRUE;
hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
hw->mac_type = e1000_undefined;
/* MAC and Phy settings */
if (e1000_sw_init(nic) < 0) {
E1000_ERR(nic, "Software init failed\n");
continue;
}
if (e1000_check_phy_reset_block(hw))
E1000_ERR(nic, "PHY Reset is blocked!\n");
/* Basic init was OK, reset the hardware and allow SPI access */
e1000_reset_hw(hw);
list_add_tail(&hw->list_node, &e1000_hw_list);
/* Validate the EEPROM and get chipset information */
#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
if (e1000_init_eeprom_params(hw)) {
E1000_ERR(nic, "EEPROM is invalid!\n");
continue;
}
if (e1000_validate_eeprom_checksum(hw))
continue;
#endif
e1000_read_mac_addr(nic);
e1000_get_bus_type(hw);
printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
/* Set up the function pointers and register the device */
nic->init = e1000_init;
nic->recv = e1000_poll;
nic->send = e1000_transmit;
nic->halt = e1000_disable;
eth_register(nic);
}
return i;
}
struct e1000_hw *e1000_find_card(unsigned int cardnum)
{
struct e1000_hw *hw;
list_for_each_entry(hw, &e1000_hw_list, list_node)
if (hw->cardnum == cardnum)
return hw;
return NULL;
}
#ifdef CONFIG_CMD_E1000
static int do_e1000(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
struct e1000_hw *hw;
if (argc < 3) {
cmd_usage(cmdtp);
return 1;
}
/* Make sure we can find the requested e1000 card */
hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
if (!hw) {
printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
return 1;
}
if (!strcmp(argv[2], "print-mac-address")) {
unsigned char *mac = hw->nic->enetaddr;
printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
return 0;
}
#ifdef CONFIG_E1000_SPI
/* Handle the "SPI" subcommand */
if (!strcmp(argv[2], "spi"))
return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
#endif
cmd_usage(cmdtp);
return 1;
}
U_BOOT_CMD(
e1000, 7, 0, do_e1000,
"Intel e1000 controller management",
/* */"<card#> print-mac-address\n"
#ifdef CONFIG_E1000_SPI
"e1000 <card#> spi show [<offset> [<length>]]\n"
"e1000 <card#> spi dump <addr> <offset> <length>\n"
"e1000 <card#> spi program <addr> <offset> <length>\n"
"e1000 <card#> spi checksum [update]\n"
#endif
" - Manage the Intel E1000 PCI device"
);
#endif /* not CONFIG_CMD_E1000 */
|
1001-study-uboot
|
drivers/net/e1000.c
|
C
|
gpl3
| 158,256
|
/*
* Altera 10/100/1000 triple speed ethernet mac
*
* Copyright (C) 2008 Altera Corporation.
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _ALTERA_TSE_H_
#define _ALTERA_TSE_H_
#define __packed_1_ __attribute__ ((packed, aligned(1)))
/* PHY Stuff */
#define miim_end -2
#define miim_read -1
#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
#ifndef CONFIG_SYS_TBIPA_VALUE
#define CONFIG_SYS_TBIPA_VALUE 0x1f
#endif
#define MIIMCFG_INIT_VALUE 0x00000003
#define MIIMCFG_RESET 0x80000000
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
#define MIIM_CONTROL 0x00
#define MIIM_CONTROL_RESET 0x00009140
#define MIIM_CONTROL_INIT 0x00001140
#define MIIM_CONTROL_RESTART 0x00001340
#define MIIM_ANEN 0x00001000
#define MIIM_CR 0x00
#define MIIM_CR_RST 0x00008000
#define MIIM_CR_INIT 0x00001000
#define MIIM_STATUS 0x1
#define MIIM_STATUS_AN_DONE 0x00000020
#define MIIM_STATUS_LINK 0x0004
#define MIIM_PHYIR1 0x2
#define MIIM_PHYIR2 0x3
#define MIIM_ANAR 0x4
#define MIIM_ANAR_INIT 0x1e1
#define MIIM_TBI_ANLPBPA 0x5
#define MIIM_TBI_ANLPBPA_HALF 0x00000040
#define MIIM_TBI_ANLPBPA_FULL 0x00000020
#define MIIM_TBI_ANEX 0x6
#define MIIM_TBI_ANEX_NP 0x00000004
#define MIIM_TBI_ANEX_PRX 0x00000002
#define MIIM_GBIT_CONTROL 0x9
#define MIIM_GBIT_CONTROL_INIT 0xe00
#define MIIM_EXT_PAGE_ACCESS 0x1f
/* 88E1011 PHY Status Register */
#define MIIM_88E1011_PHY_STATUS 0x11
#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
#define MIIM_88E1011_PHYSTAT_100 0x4000
#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
#define MIIM_88E1011_PHYSTAT_LINK 0x0400
#define MIIM_88E1011_PHY_SCR 0x10
#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
#define MIIM_88E1111_PHY_EXT_CR 0x14
#define MIIM_88E1111_PHY_EXT_SR 0x1b
/* 88E1111 PHY LED Control Register */
#define MIIM_88E1111_PHY_LED_CONTROL 24
#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
#define MIIM_READ_COMMAND 0x00000001
/* struct phy_info: a structure which defines attributes for a PHY
* id will contain a number which represents the PHY. During
* startup, the driver will poll the PHY to find out what its
* UID--as defined by registers 2 and 3--is. The 32-bit result
* gotten from the PHY will be shifted right by "shift" bits to
* discard any bits which may change based on revision numbers
* unimportant to functionality
*
* The struct phy_cmd entries represent pointers to an arrays of
* commands which tell the driver what to do to the PHY.
*/
struct phy_info {
uint id;
char *name;
uint shift;
/* Called to configure the PHY, and modify the controller
* based on the results */
struct phy_cmd *config;
/* Called when starting up the controller */
struct phy_cmd *startup;
/* Called when bringing down the controller */
struct phy_cmd *shutdown;
};
/* SGDMA Stuff */
#define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001)
#define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002)
#define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004)
#define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008)
#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010)
#define ALT_SGDMA_CONTROL_IE_ERROR_MSK (0x00000001)
#define ALT_SGDMA_CONTROL_IE_EOP_ENCOUNTERED_MSK (0x00000002)
#define ALT_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK (0x00000004)
#define ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK (0x00000008)
#define ALT_SGDMA_CONTROL_IE_GLOBAL_MSK (0x00000010)
#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020)
#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040)
#define ALT_SGDMA_CONTROL_IE_MAX_DESC_PROCESSED_MSK (0x00000080)
#define ALT_SGDMA_CONTROL_MAX_DESC_PROCESSED_MSK (0x0000FF00)
#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000)
#define ALT_SGDMA_CONTROL_PARK_MSK (0x00020000)
#define ALT_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK (0x80000000)
#define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \
| ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \
| ALT_SGDMA_CONTROL_IE_GLOBAL_MSK)
/*
* Descriptor control bit masks & offsets
*
* Note: The control byte physically occupies bits [31:24] in memory.
* The following bit-offsets are expressed relative to the LSB of
* the control register bitfield.
*/
#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001)
#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002)
#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004)
#define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008)
#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080)
/*
* Descriptor status bit masks & offsets
*
* Note: The status byte physically occupies bits [23:16] in memory.
* The following bit-offsets are expressed relative to the LSB of
* the status register bitfield.
*/
#define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001)
#define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002)
#define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004)
#define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008)
#define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010)
#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020)
#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040)
#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080)
#define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F)
/*
* The SGDMA controller buffer descriptor allocates
* 64 bits for each address. To support ANSI C, the
* struct implementing a descriptor places 32-bits
* of padding directly above each address; each pad must
* be cleared when initializing a descriptor.
*/
/*
* Buffer Descriptor data structure
*
*/
struct alt_sgdma_descriptor {
unsigned int *source; /* the address of data to be read. */
unsigned int source_pad;
unsigned int *destination; /* the address to write data */
unsigned int destination_pad;
unsigned int *next; /* the next descriptor in the list. */
unsigned int next_pad;
unsigned short bytes_to_transfer; /* the number of bytes to transfer */
unsigned char read_burst;
unsigned char write_burst;
unsigned short actual_bytes_transferred;/* bytes transferred by DMA */
unsigned char descriptor_status;
unsigned char descriptor_control;
} __packed_1_;
/* SG-DMA Control/Status Slave registers map */
struct alt_sgdma_registers {
unsigned int status;
unsigned int status_pad[3];
unsigned int control;
unsigned int control_pad[3];
unsigned int next_descriptor_pointer;
unsigned int descriptor_pad[3];
};
/* TSE Stuff */
#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001)
#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002)
#define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004)
#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008)
#define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010)
#define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020)
#define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040)
#define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080)
#define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100)
#define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200)
#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400)
#define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800)
#define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000)
#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000)
#define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000)
#define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000)
/* Bits (18:16) = address select */
#define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000)
#define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000)
#define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000)
#define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000)
#define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000)
#define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000)
#define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000)
#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000)
#define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000)
/* Bits (30..27) reserved */
#define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000)
#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000)
#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000)
#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000)
#define ALT_TSE_SW_RESET_WATCHDOG_CNTR 10000
#define ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR 90000000
/* Command_Config Register Bit Definitions */
typedef volatile union __alt_tse_command_config {
unsigned int image;
struct {
unsigned int
transmit_enable:1, /* bit 0 */
receive_enable:1, /* bit 1 */
pause_frame_xon_gen:1, /* bit 2 */
ethernet_speed:1, /* bit 3 */
promiscuous_enable:1, /* bit 4 */
pad_enable:1, /* bit 5 */
crc_forward:1, /* bit 6 */
pause_frame_forward:1, /* bit 7 */
pause_frame_ignore:1, /* bit 8 */
set_mac_address_on_tx:1, /* bit 9 */
halfduplex_enable:1, /* bit 10 */
excessive_collision:1, /* bit 11 */
late_collision:1, /* bit 12 */
software_reset:1, /* bit 13 */
multicast_hash_mode_sel:1, /* bit 14 */
loopback_enable:1, /* bit 15 */
src_mac_addr_sel_on_tx:3, /* bit 18:16 */
magic_packet_detect:1, /* bit 19 */
sleep_mode_enable:1, /* bit 20 */
wake_up_request:1, /* bit 21 */
pause_frame_xoff_gen:1, /* bit 22 */
control_frame_enable:1, /* bit 23 */
payload_len_chk_disable:1, /* bit 24 */
enable_10mbps_intf:1, /* bit 25 */
rx_error_discard_enable:1, /* bit 26 */
reserved_bits:4, /* bit 30:27 */
self_clear_counter_reset:1; /* bit 31 */
} __packed_1_ bits;
} __packed_1_ alt_tse_command_config;
/* Tx_Cmd_Stat Register Bit Definitions */
typedef volatile union __alt_tse_tx_cmd_stat {
unsigned int image;
struct {
unsigned int reserved_lsbs:17, /* bit 16:0 */
omit_crc:1, /* bit 17 */
tx_shift16:1, /* bit 18 */
reserved_msbs:13; /* bit 31:19 */
} __packed_1_ bits;
} alt_tse_tx_cmd_stat;
/* Rx_Cmd_Stat Register Bit Definitions */
typedef volatile union __alt_tse_rx_cmd_stat {
unsigned int image;
struct {
unsigned int reserved_lsbs:25, /* bit 24:0 */
rx_shift16:1, /* bit 25 */
reserved_msbs:6; /* bit 31:26 */
} __packed_1_ bits;
} alt_tse_rx_cmd_stat;
struct alt_tse_mdio {
unsigned int control; /*PHY device operation control register */
unsigned int status; /*PHY device operation status register */
unsigned int phy_id1; /*Bits 31:16 of PHY identifier. */
unsigned int phy_id2; /*Bits 15:0 of PHY identifier. */
unsigned int auto_negotiation_advertisement;
unsigned int remote_partner_base_page_ability;
unsigned int reg6;
unsigned int reg7;
unsigned int reg8;
unsigned int reg9;
unsigned int rega;
unsigned int regb;
unsigned int regc;
unsigned int regd;
unsigned int rege;
unsigned int regf;
unsigned int reg10;
unsigned int reg11;
unsigned int reg12;
unsigned int reg13;
unsigned int reg14;
unsigned int reg15;
unsigned int reg16;
unsigned int reg17;
unsigned int reg18;
unsigned int reg19;
unsigned int reg1a;
unsigned int reg1b;
unsigned int reg1c;
unsigned int reg1d;
unsigned int reg1e;
unsigned int reg1f;
};
/* MAC register Space */
struct alt_tse_mac {
unsigned int megacore_revision;
unsigned int scratch_pad;
alt_tse_command_config command_config;
unsigned int mac_addr_0;
unsigned int mac_addr_1;
unsigned int max_frame_length;
unsigned int pause_quanta;
unsigned int rx_sel_empty_threshold;
unsigned int rx_sel_full_threshold;
unsigned int tx_sel_empty_threshold;
unsigned int tx_sel_full_threshold;
unsigned int rx_almost_empty_threshold;
unsigned int rx_almost_full_threshold;
unsigned int tx_almost_empty_threshold;
unsigned int tx_almost_full_threshold;
unsigned int mdio_phy0_addr;
unsigned int mdio_phy1_addr;
/* only if 100/1000 BaseX PCS, reserved otherwise */
unsigned int reservedx44[5];
unsigned int reg_read_access_status;
unsigned int min_tx_ipg_length;
/* IEEE 802.3 oEntity Managed Object Support */
unsigned int aMACID_1; /*The MAC addresses */
unsigned int aMACID_2;
unsigned int aFramesTransmittedOK;
unsigned int aFramesReceivedOK;
unsigned int aFramesCheckSequenceErrors;
unsigned int aAlignmentErrors;
unsigned int aOctetsTransmittedOK;
unsigned int aOctetsReceivedOK;
/* IEEE 802.3 oPausedEntity Managed Object Support */
unsigned int aTxPAUSEMACCtrlFrames;
unsigned int aRxPAUSEMACCtrlFrames;
/* IETF MIB (MIB-II) Object Support */
unsigned int ifInErrors;
unsigned int ifOutErrors;
unsigned int ifInUcastPkts;
unsigned int ifInMulticastPkts;
unsigned int ifInBroadcastPkts;
unsigned int ifOutDiscards;
unsigned int ifOutUcastPkts;
unsigned int ifOutMulticastPkts;
unsigned int ifOutBroadcastPkts;
/* IETF RMON MIB Object Support */
unsigned int etherStatsDropEvent;
unsigned int etherStatsOctets;
unsigned int etherStatsPkts;
unsigned int etherStatsUndersizePkts;
unsigned int etherStatsOversizePkts;
unsigned int etherStatsPkts64Octets;
unsigned int etherStatsPkts65to127Octets;
unsigned int etherStatsPkts128to255Octets;
unsigned int etherStatsPkts256to511Octets;
unsigned int etherStatsPkts512to1023Octets;
unsigned int etherStatsPkts1024to1518Octets;
unsigned int etherStatsPkts1519toXOctets;
unsigned int etherStatsJabbers;
unsigned int etherStatsFragments;
unsigned int reservedxE4;
/*FIFO control register. */
alt_tse_tx_cmd_stat tx_cmd_stat;
alt_tse_rx_cmd_stat rx_cmd_stat;
unsigned int ipaccTxConf;
unsigned int ipaccRxConf;
unsigned int ipaccRxStat;
unsigned int ipaccRxStatSum;
/*Multicast address resolution table */
unsigned int hash_table[64];
/*Registers 0 to 31 within PHY device 0/1 */
struct alt_tse_mdio mdio_phy0;
struct alt_tse_mdio mdio_phy1;
/*4 Supplemental MAC Addresses */
unsigned int supp_mac_addr_0_0;
unsigned int supp_mac_addr_0_1;
unsigned int supp_mac_addr_1_0;
unsigned int supp_mac_addr_1_1;
unsigned int supp_mac_addr_2_0;
unsigned int supp_mac_addr_2_1;
unsigned int supp_mac_addr_3_0;
unsigned int supp_mac_addr_3_1;
unsigned int reservedx320[56];
};
/* flags: TSE MII modes */
/* GMII/MII = 0 */
/* RGMII = 1 */
/* RGMII_ID = 2 */
/* RGMII_TXID = 3 */
/* RGMII_RXID = 4 */
/* SGMII = 5 */
struct altera_tse_priv {
char devname[16];
volatile struct alt_tse_mac *mac_dev;
volatile struct alt_sgdma_registers *sgdma_rx;
volatile struct alt_sgdma_registers *sgdma_tx;
unsigned int rx_sgdma_irq;
unsigned int tx_sgdma_irq;
unsigned int has_descriptor_mem;
unsigned int descriptor_mem_base;
unsigned int descriptor_mem_size;
volatile struct alt_sgdma_descriptor *rx_desc;
volatile struct alt_sgdma_descriptor *tx_desc;
volatile unsigned char *rx_buf;
struct phy_info *phyinfo;
unsigned int phyaddr;
unsigned int flags;
unsigned int link;
unsigned int duplexity;
unsigned int speed;
};
/* Phy stuff continued */
/*
* struct phy_cmd: A command for reading or writing a PHY register
*
* mii_reg: The register to read or write
*
* mii_data: For writes, the value to put in the register.
* A value of -1 indicates this is a read.
*
* funct: A function pointer which is invoked for each command.
* For reads, this function will be passed the value read
* from the PHY, and process it.
* For writes, the result of this function will be written
* to the PHY register
*/
struct phy_cmd {
uint mii_reg;
uint mii_data;
uint(*funct) (uint mii_reg, struct altera_tse_priv *priv);
};
#endif /* _ALTERA_TSE_H_ */
|
1001-study-uboot
|
drivers/net/altera_tse.h
|
C
|
gpl3
| 15,455
|
/*******************************************************************************
Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
Copyright 2011 Freescale Semiconductor, Inc.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/* e1000_hw.h
* Structures, enums, and macros for the MAC
*/
#ifndef _E1000_HW_H_
#define _E1000_HW_H_
#include <common.h>
#include <linux/list.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#ifdef CONFIG_E1000_SPI
#include <spi.h>
#endif
#define E1000_ERR(NIC, fmt, args...) \
printf("e1000: %s: ERROR: " fmt, (NIC)->name ,##args)
#ifdef E1000_DEBUG
#define E1000_DBG(NIC, fmt, args...) \
printf("e1000: %s: DEBUG: " fmt, (NIC)->name ,##args)
#define DEBUGOUT(fmt, args...) printf(fmt ,##args)
#define DEBUGFUNC() printf("%s\n", __func__);
#else
#define E1000_DBG(HW, args...) do { } while (0)
#define DEBUGFUNC() do { } while (0)
#define DEBUGOUT(fmt, args...) do { } while (0)
#endif
/* I/O wrapper functions */
#define E1000_WRITE_REG(a, reg, value) \
writel((value), ((a)->hw_addr + E1000_##reg))
#define E1000_READ_REG(a, reg) \
readl((a)->hw_addr + E1000_##reg)
#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))
#define E1000_READ_REG_ARRAY(a, reg, offset) \
readl((a)->hw_addr + E1000_##reg + ((offset) << 2))
#define E1000_WRITE_FLUSH(a) \
do { E1000_READ_REG(a, STATUS); } while (0)
/* Forward declarations of structures used by the shared code */
struct e1000_hw;
struct e1000_hw_stats;
/* Internal E1000 helper functions */
struct e1000_hw *e1000_find_card(unsigned int cardnum);
int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
void e1000_standby_eeprom(struct e1000_hw *hw);
void e1000_release_eeprom(struct e1000_hw *hw);
void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
#ifdef CONFIG_E1000_SPI
int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
int argc, char * const argv[]);
#endif
typedef enum {
FALSE = 0,
TRUE = 1
} boolean_t;
/* Enumerated types specific to the e1000 hardware */
/* Media Access Controlers */
typedef enum {
e1000_undefined = 0,
e1000_82542_rev2_0,
e1000_82542_rev2_1,
e1000_82543,
e1000_82544,
e1000_82540,
e1000_82545,
e1000_82545_rev_3,
e1000_82546,
e1000_82546_rev_3,
e1000_82541,
e1000_82541_rev_2,
e1000_82547,
e1000_82547_rev_2,
e1000_82571,
e1000_82572,
e1000_82573,
e1000_82574,
e1000_80003es2lan,
e1000_ich8lan,
e1000_num_macs
} e1000_mac_type;
/* Media Types */
typedef enum {
e1000_media_type_copper = 0,
e1000_media_type_fiber = 1,
e1000_media_type_internal_serdes = 2,
e1000_num_media_types
} e1000_media_type;
typedef enum {
e1000_eeprom_uninitialized = 0,
e1000_eeprom_spi,
e1000_eeprom_microwire,
e1000_eeprom_flash,
e1000_eeprom_ich8,
e1000_eeprom_none, /* No NVM support */
e1000_num_eeprom_types
} e1000_eeprom_type;
typedef enum {
e1000_10_half = 0,
e1000_10_full = 1,
e1000_100_half = 2,
e1000_100_full = 3
} e1000_speed_duplex_type;
/* Flow Control Settings */
typedef enum {
e1000_fc_none = 0,
e1000_fc_rx_pause = 1,
e1000_fc_tx_pause = 2,
e1000_fc_full = 3,
e1000_fc_default = 0xFF
} e1000_fc_type;
/* PCI bus types */
typedef enum {
e1000_bus_type_unknown = 0,
e1000_bus_type_pci,
e1000_bus_type_pcix,
e1000_bus_type_pci_express,
e1000_bus_type_reserved
} e1000_bus_type;
/* PCI bus speeds */
typedef enum {
e1000_bus_speed_unknown = 0,
e1000_bus_speed_33,
e1000_bus_speed_66,
e1000_bus_speed_100,
e1000_bus_speed_133,
e1000_bus_speed_reserved
} e1000_bus_speed;
/* PCI bus widths */
typedef enum {
e1000_bus_width_unknown = 0,
e1000_bus_width_32,
e1000_bus_width_64
} e1000_bus_width;
/* PHY status info structure and supporting enums */
typedef enum {
e1000_cable_length_50 = 0,
e1000_cable_length_50_80,
e1000_cable_length_80_110,
e1000_cable_length_110_140,
e1000_cable_length_140,
e1000_cable_length_undefined = 0xFF
} e1000_cable_length;
typedef enum {
e1000_10bt_ext_dist_enable_normal = 0,
e1000_10bt_ext_dist_enable_lower,
e1000_10bt_ext_dist_enable_undefined = 0xFF
} e1000_10bt_ext_dist_enable;
typedef enum {
e1000_rev_polarity_normal = 0,
e1000_rev_polarity_reversed,
e1000_rev_polarity_undefined = 0xFF
} e1000_rev_polarity;
typedef enum {
e1000_polarity_reversal_enabled = 0,
e1000_polarity_reversal_disabled,
e1000_polarity_reversal_undefined = 0xFF
} e1000_polarity_reversal;
typedef enum {
e1000_auto_x_mode_manual_mdi = 0,
e1000_auto_x_mode_manual_mdix,
e1000_auto_x_mode_auto1,
e1000_auto_x_mode_auto2,
e1000_auto_x_mode_undefined = 0xFF
} e1000_auto_x_mode;
typedef enum {
e1000_1000t_rx_status_not_ok = 0,
e1000_1000t_rx_status_ok,
e1000_1000t_rx_status_undefined = 0xFF
} e1000_1000t_rx_status;
typedef enum {
e1000_phy_m88 = 0,
e1000_phy_igp,
e1000_phy_igp_2,
e1000_phy_gg82563,
e1000_phy_igp_3,
e1000_phy_ife,
e1000_phy_bm,
e1000_phy_undefined = 0xFF
} e1000_phy_type;
struct e1000_phy_info {
e1000_cable_length cable_length;
e1000_10bt_ext_dist_enable extended_10bt_distance;
e1000_rev_polarity cable_polarity;
e1000_polarity_reversal polarity_correction;
e1000_auto_x_mode mdix_mode;
e1000_1000t_rx_status local_rx;
e1000_1000t_rx_status remote_rx;
};
struct e1000_phy_stats {
uint32_t idle_errors;
uint32_t receive_errors;
};
/* Error Codes */
#define E1000_SUCCESS 0
#define E1000_ERR_EEPROM 1
#define E1000_ERR_PHY 2
#define E1000_ERR_CONFIG 3
#define E1000_ERR_PARAM 4
#define E1000_ERR_MAC_TYPE 5
#define E1000_ERR_PHY_TYPE 6
#define E1000_ERR_NOLINK 7
#define E1000_ERR_TIMEOUT 8
#define E1000_ERR_RESET 9
#define E1000_ERR_MASTER_REQUESTS_PENDING 10
#define E1000_ERR_HOST_INTERFACE_COMMAND 11
#define E1000_BLK_PHY_RESET 12
#define E1000_ERR_SWFW_SYNC 13
/* PCI Device IDs */
#define E1000_DEV_ID_82542 0x1000
#define E1000_DEV_ID_82543GC_FIBER 0x1001
#define E1000_DEV_ID_82543GC_COPPER 0x1004
#define E1000_DEV_ID_82544EI_COPPER 0x1008
#define E1000_DEV_ID_82544EI_FIBER 0x1009
#define E1000_DEV_ID_82544GC_COPPER 0x100C
#define E1000_DEV_ID_82544GC_LOM 0x100D
#define E1000_DEV_ID_82540EM 0x100E
#define E1000_DEV_ID_82540EM_LOM 0x1015
#define E1000_DEV_ID_82540EP_LOM 0x1016
#define E1000_DEV_ID_82540EP 0x1017
#define E1000_DEV_ID_82540EP_LP 0x101E
#define E1000_DEV_ID_82545EM_COPPER 0x100F
#define E1000_DEV_ID_82545EM_FIBER 0x1011
#define E1000_DEV_ID_82545GM_COPPER 0x1026
#define E1000_DEV_ID_82545GM_FIBER 0x1027
#define E1000_DEV_ID_82545GM_SERDES 0x1028
#define E1000_DEV_ID_82546EB_COPPER 0x1010
#define E1000_DEV_ID_82546EB_FIBER 0x1012
#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
#define E1000_DEV_ID_82541EI 0x1013
#define E1000_DEV_ID_82541EI_MOBILE 0x1018
#define E1000_DEV_ID_82541ER_LOM 0x1014
#define E1000_DEV_ID_82541ER 0x1078
#define E1000_DEV_ID_82547GI 0x1075
#define E1000_DEV_ID_82541GI 0x1076
#define E1000_DEV_ID_82541GI_MOBILE 0x1077
#define E1000_DEV_ID_82541GI_LF 0x107C
#define E1000_DEV_ID_82546GB_COPPER 0x1079
#define E1000_DEV_ID_82546GB_FIBER 0x107A
#define E1000_DEV_ID_82546GB_SERDES 0x107B
#define E1000_DEV_ID_82546GB_PCIE 0x108A
#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
#define E1000_DEV_ID_82547EI 0x1019
#define E1000_DEV_ID_82547EI_MOBILE 0x101A
#define E1000_DEV_ID_82571EB_COPPER 0x105E
#define E1000_DEV_ID_82571EB_FIBER 0x105F
#define E1000_DEV_ID_82571EB_SERDES 0x1060
#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE 0x10BC
#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
#define E1000_DEV_ID_82572EI_COPPER 0x107D
#define E1000_DEV_ID_82572EI_FIBER 0x107E
#define E1000_DEV_ID_82572EI_SERDES 0x107F
#define E1000_DEV_ID_82572EI 0x10B9
#define E1000_DEV_ID_82573E 0x108B
#define E1000_DEV_ID_82573E_IAMT 0x108C
#define E1000_DEV_ID_82573L 0x109A
#define E1000_DEV_ID_82574L 0x10D3
#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
#define E1000_DEV_ID_ICH8_IGP_C 0x104B
#define E1000_DEV_ID_ICH8_IFE 0x104C
#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
#define E1000_DEV_ID_ICH8_IGP_M 0x104D
#define IGP03E1000_E_PHY_ID 0x02A80390
#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
#define IFE_PLUS_E_PHY_ID 0x02A80320
#define IFE_C_E_PHY_ID 0x02A80310
#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status,
Control and Address */
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special
control register */
#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False
Carrier Counter */
#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet
Counter */
#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error
Frame Counter */
#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error
Counter */
#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive
Premature End Of Frame
Error Counter */
#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of
Frame Error Counter */
#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber
Detect Counter */
#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and
Status */
#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and
LED configuration */
#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control
(HWI) */
#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Defaut 1 = Disable auto
reduced power down */
#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power
state of 100BASE-TX */
#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power
state of 10BASE-T */
#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T
polarity */
#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY
address */
#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed
result 1=100Mbs, 0=10Mbs */
#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation
duplex result 1=Full, 0=Half */
#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dyanmic Power Down
disabled */
#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity,
0=Normal */
#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity
Disabled, 0=Enabled */
#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled,
0=Normal Jabber Operation */
#define IFE_PSC_FORCE_POLARITY_SHIFT 5
#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X
feature, default 0=disabled */
#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X,
0=force MDI */
#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm
is completed */
#define IFE_PMC_MDIX_MODE_SHIFT 6
#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI
feature */
#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed,
0=failed */
#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses
on the wire */
#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication
type of problem on the line */
#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to
the cable problem, in 80cm granularity */
#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2
off */
#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
#define NUM_DEV_IDS 16
#define NODE_ADDRESS_SIZE 6
#define ETH_LENGTH_OF_ADDRESS 6
/* MAC decode size is 128K - This is the size of BAR0 */
#define MAC_DECODE_SIZE (128 * 1024)
#define E1000_82542_2_0_REV_ID 2
#define E1000_82542_2_1_REV_ID 3
#define E1000_REVISION_0 0
#define E1000_REVISION_1 1
#define E1000_REVISION_2 2
#define E1000_REVISION_3 3
#define SPEED_10 10
#define SPEED_100 100
#define SPEED_1000 1000
#define HALF_DUPLEX 1
#define FULL_DUPLEX 2
/* The sizes (in bytes) of a ethernet packet */
#define ENET_HEADER_SIZE 14
#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
#define ETHERNET_FCS_SIZE 4
#define MAXIMUM_ETHERNET_PACKET_SIZE \
(MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
#define MINIMUM_ETHERNET_PACKET_SIZE \
(MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
#define CRC_LENGTH ETHERNET_FCS_SIZE
#define MAX_JUMBO_FRAME_SIZE 0x3F00
/* 802.1q VLAN Packet Sizes */
#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
/* Ethertype field values */
#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
/* Packet Header defines */
#define IP_PROTOCOL_TCP 6
#define IP_PROTOCOL_UDP 0x11
/* This defines the bits that are set in the Interrupt Mask
* Set/Read Register. Each bit is documented below:
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
* o RXSEQ = Receive Sequence Error
*/
#define POLL_IMS_ENABLE_MASK ( \
E1000_IMS_RXDMT0 | \
E1000_IMS_RXSEQ)
/* This defines the bits that are set in the Interrupt Mask
* Set/Read Register. Each bit is documented below:
* o RXT0 = Receiver Timer Interrupt (ring 0)
* o TXDW = Transmit Descriptor Written Back
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
* o RXSEQ = Receive Sequence Error
* o LSC = Link Status Change
*/
#define IMS_ENABLE_MASK ( \
E1000_IMS_RXT0 | \
E1000_IMS_TXDW | \
E1000_IMS_RXDMT0 | \
E1000_IMS_RXSEQ | \
E1000_IMS_LSC)
/* The number of high/low register pairs in the RAR. The RAR (Receive Address
* Registers) holds the directed and multicast addresses that we monitor. We
* reserve one of these spots for our directed address, allowing us room for
* E1000_RAR_ENTRIES - 1 multicast addresses.
*/
#define E1000_RAR_ENTRIES 16
#define MIN_NUMBER_OF_DESCRIPTORS 8
#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
/* Receive Descriptor */
struct e1000_rx_desc {
uint64_t buffer_addr; /* Address of the descriptor's data buffer */
uint16_t length; /* Length of data DMAed into data buffer */
uint16_t csum; /* Packet checksum */
uint8_t status; /* Descriptor status */
uint8_t errors; /* Descriptor Errors */
uint16_t special;
};
/* Receive Decriptor bit definitions */
#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
/* mask to determine if packets should be dropped due to frame errors */
#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
E1000_RXD_ERR_CE | \
E1000_RXD_ERR_SE | \
E1000_RXD_ERR_SEQ | \
E1000_RXD_ERR_CXE | \
E1000_RXD_ERR_RXE)
/* Transmit Descriptor */
struct e1000_tx_desc {
uint64_t buffer_addr; /* Address of the descriptor's data buffer */
union {
uint32_t data;
struct {
uint16_t length; /* Data buffer length */
uint8_t cso; /* Checksum offset */
uint8_t cmd; /* Descriptor control */
} flags;
} lower;
union {
uint32_t data;
struct {
uint8_t status; /* Descriptor status */
uint8_t css; /* Checksum start */
uint16_t special;
} fields;
} upper;
};
/* Transmit Descriptor bit definitions */
#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
/* Offload Context Descriptor */
struct e1000_context_desc {
union {
uint32_t ip_config;
struct {
uint8_t ipcss; /* IP checksum start */
uint8_t ipcso; /* IP checksum offset */
uint16_t ipcse; /* IP checksum end */
} ip_fields;
} lower_setup;
union {
uint32_t tcp_config;
struct {
uint8_t tucss; /* TCP checksum start */
uint8_t tucso; /* TCP checksum offset */
uint16_t tucse; /* TCP checksum end */
} tcp_fields;
} upper_setup;
uint32_t cmd_and_length; /* */
union {
uint32_t data;
struct {
uint8_t status; /* Descriptor status */
uint8_t hdr_len; /* Header length */
uint16_t mss; /* Maximum segment size */
} fields;
} tcp_seg_setup;
};
/* Offload data descriptor */
struct e1000_data_desc {
uint64_t buffer_addr; /* Address of the descriptor's buffer address */
union {
uint32_t data;
struct {
uint16_t length; /* Data buffer length */
uint8_t typ_len_ext; /* */
uint8_t cmd; /* */
} flags;
} lower;
union {
uint32_t data;
struct {
uint8_t status; /* Descriptor status */
uint8_t popts; /* Packet Options */
uint16_t special; /* */
} fields;
} upper;
};
/* Filters */
#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
/* Receive Address Register */
struct e1000_rar {
volatile uint32_t low; /* receive address low */
volatile uint32_t high; /* receive address high */
};
/* The number of entries in the Multicast Table Array (MTA). */
#define E1000_NUM_MTA_REGISTERS 128
/* IPv4 Address Table Entry */
struct e1000_ipv4_at_entry {
volatile uint32_t ipv4_addr; /* IP Address (RW) */
volatile uint32_t reserved;
};
/* Four wakeup IP addresses are supported */
#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
#define E1000_IP6AT_SIZE 1
/* IPv6 Address Table Entry */
struct e1000_ipv6_at_entry {
volatile uint8_t ipv6_addr[16];
};
/* Flexible Filter Length Table Entry */
struct e1000_fflt_entry {
volatile uint32_t length; /* Flexible Filter Length (RW) */
volatile uint32_t reserved;
};
/* Flexible Filter Mask Table Entry */
struct e1000_ffmt_entry {
volatile uint32_t mask; /* Flexible Filter Mask (RW) */
volatile uint32_t reserved;
};
/* Flexible Filter Value Table Entry */
struct e1000_ffvt_entry {
volatile uint32_t value; /* Flexible Filter Value (RW) */
volatile uint32_t reserved;
};
/* Four Flexible Filters are supported */
#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
/* Each Flexible Filter is at most 128 (0x80) bytes in length */
#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
/* Register Set. (82543, 82544)
*
* Registers are defined to be 32 bits and should be accessed as 32 bit values.
* These registers are physically located on the NIC, but are mapped into the
* host memory address space.
*
* RW - register is both readable and writable
* RO - register is read only
* WO - register is write only
* R/clr - register is read only and is cleared when read
* A - register array
*/
#define E1000_CTRL 0x00000 /* Device Control - RW */
#define E1000_STATUS 0x00008 /* Device Status - RO */
#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
#define E1000_EERD 0x00014 /* EEPROM Read - RW */
#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
#define E1000_MDIC 0x00020 /* MDI Control - RW */
#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
#define E1000_RCTL 0x00100 /* RX Control - RW */
#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
#define E1000_TCTL 0x00400 /* TX Control - RW */
#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
#define FEXTNVM_SW_CONFIG 0x0001
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
#define E1000_PBS 0x01008 /* Packet Buffer Size */
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
#define E1000_FLASH_UPDATES 1000
#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
#define E1000_FLSWCTL 0x01030 /* FLASH control register */
#define E1000_FLSWDATA 0x01034 /* FLASH data register */
#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
#define E1000_COLC 0x04028 /* Collision Count - R/clr */
#define E1000_DC 0x04030 /* Defer Count - R/clr */
#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
#define E1000_RA 0x05400 /* Receive Address - RW Array */
#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
#define E1000_WUC 0x05800 /* Wakeup Control - RW */
#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
#define E1000_WUS 0x05810 /* Wakeup Status - RO */
#define E1000_MANC 0x05820 /* Management Control - RW */
#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
/* Register Set (82542)
*
* Some of the 82542 registers are located at different offsets than they are
* in more current versions of the 8254x. Despite the difference in location,
* the registers function in the same manner.
*/
#define E1000_82542_CTRL E1000_CTRL
#define E1000_82542_STATUS E1000_STATUS
#define E1000_82542_EECD E1000_EECD
#define E1000_82542_EERD E1000_EERD
#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
#define E1000_82542_MDIC E1000_MDIC
#define E1000_82542_FCAL E1000_FCAL
#define E1000_82542_FCAH E1000_FCAH
#define E1000_82542_FCT E1000_FCT
#define E1000_82542_VET E1000_VET
#define E1000_82542_RA 0x00040
#define E1000_82542_ICR E1000_ICR
#define E1000_82542_ITR E1000_ITR
#define E1000_82542_ICS E1000_ICS
#define E1000_82542_IMS E1000_IMS
#define E1000_82542_IMC E1000_IMC
#define E1000_82542_RCTL E1000_RCTL
#define E1000_82542_RDTR 0x00108
#define E1000_82542_RDBAL 0x00110
#define E1000_82542_RDBAH 0x00114
#define E1000_82542_RDLEN 0x00118
#define E1000_82542_RDH 0x00120
#define E1000_82542_RDT 0x00128
#define E1000_82542_FCRTH 0x00160
#define E1000_82542_FCRTL 0x00168
#define E1000_82542_FCTTV E1000_FCTTV
#define E1000_82542_TXCW E1000_TXCW
#define E1000_82542_RXCW E1000_RXCW
#define E1000_82542_MTA 0x00200
#define E1000_82542_TCTL E1000_TCTL
#define E1000_82542_TIPG E1000_TIPG
#define E1000_82542_TDBAL 0x00420
#define E1000_82542_TDBAH 0x00424
#define E1000_82542_TDLEN 0x00428
#define E1000_82542_TDH 0x00430
#define E1000_82542_TDT 0x00438
#define E1000_82542_TIDV 0x00440
#define E1000_82542_TBT E1000_TBT
#define E1000_82542_AIT E1000_AIT
#define E1000_82542_VFTA 0x00600
#define E1000_82542_LEDCTL E1000_LEDCTL
#define E1000_82542_PBA E1000_PBA
#define E1000_82542_RXDCTL E1000_RXDCTL
#define E1000_82542_RADV E1000_RADV
#define E1000_82542_RSRPD E1000_RSRPD
#define E1000_82542_TXDMAC E1000_TXDMAC
#define E1000_82542_TXDCTL E1000_TXDCTL
#define E1000_82542_TADV E1000_TADV
#define E1000_82542_TSPMT E1000_TSPMT
#define E1000_82542_CRCERRS E1000_CRCERRS
#define E1000_82542_ALGNERRC E1000_ALGNERRC
#define E1000_82542_SYMERRS E1000_SYMERRS
#define E1000_82542_RXERRC E1000_RXERRC
#define E1000_82542_MPC E1000_MPC
#define E1000_82542_SCC E1000_SCC
#define E1000_82542_ECOL E1000_ECOL
#define E1000_82542_MCC E1000_MCC
#define E1000_82542_LATECOL E1000_LATECOL
#define E1000_82542_COLC E1000_COLC
#define E1000_82542_DC E1000_DC
#define E1000_82542_TNCRS E1000_TNCRS
#define E1000_82542_SEC E1000_SEC
#define E1000_82542_CEXTERR E1000_CEXTERR
#define E1000_82542_RLEC E1000_RLEC
#define E1000_82542_XONRXC E1000_XONRXC
#define E1000_82542_XONTXC E1000_XONTXC
#define E1000_82542_XOFFRXC E1000_XOFFRXC
#define E1000_82542_XOFFTXC E1000_XOFFTXC
#define E1000_82542_FCRUC E1000_FCRUC
#define E1000_82542_PRC64 E1000_PRC64
#define E1000_82542_PRC127 E1000_PRC127
#define E1000_82542_PRC255 E1000_PRC255
#define E1000_82542_PRC511 E1000_PRC511
#define E1000_82542_PRC1023 E1000_PRC1023
#define E1000_82542_PRC1522 E1000_PRC1522
#define E1000_82542_GPRC E1000_GPRC
#define E1000_82542_BPRC E1000_BPRC
#define E1000_82542_MPRC E1000_MPRC
#define E1000_82542_GPTC E1000_GPTC
#define E1000_82542_GORCL E1000_GORCL
#define E1000_82542_GORCH E1000_GORCH
#define E1000_82542_GOTCL E1000_GOTCL
#define E1000_82542_GOTCH E1000_GOTCH
#define E1000_82542_RNBC E1000_RNBC
#define E1000_82542_RUC E1000_RUC
#define E1000_82542_RFC E1000_RFC
#define E1000_82542_ROC E1000_ROC
#define E1000_82542_RJC E1000_RJC
#define E1000_82542_MGTPRC E1000_MGTPRC
#define E1000_82542_MGTPDC E1000_MGTPDC
#define E1000_82542_MGTPTC E1000_MGTPTC
#define E1000_82542_TORL E1000_TORL
#define E1000_82542_TORH E1000_TORH
#define E1000_82542_TOTL E1000_TOTL
#define E1000_82542_TOTH E1000_TOTH
#define E1000_82542_TPR E1000_TPR
#define E1000_82542_TPT E1000_TPT
#define E1000_82542_PTC64 E1000_PTC64
#define E1000_82542_PTC127 E1000_PTC127
#define E1000_82542_PTC255 E1000_PTC255
#define E1000_82542_PTC511 E1000_PTC511
#define E1000_82542_PTC1023 E1000_PTC1023
#define E1000_82542_PTC1522 E1000_PTC1522
#define E1000_82542_MPTC E1000_MPTC
#define E1000_82542_BPTC E1000_BPTC
#define E1000_82542_TSCTC E1000_TSCTC
#define E1000_82542_TSCTFC E1000_TSCTFC
#define E1000_82542_RXCSUM E1000_RXCSUM
#define E1000_82542_WUC E1000_WUC
#define E1000_82542_WUFC E1000_WUFC
#define E1000_82542_WUS E1000_WUS
#define E1000_82542_MANC E1000_MANC
#define E1000_82542_IPAV E1000_IPAV
#define E1000_82542_IP4AT E1000_IP4AT
#define E1000_82542_IP6AT E1000_IP6AT
#define E1000_82542_WUPL E1000_WUPL
#define E1000_82542_WUPM E1000_WUPM
#define E1000_82542_FFLT E1000_FFLT
#define E1000_82542_FFMT E1000_FFMT
#define E1000_82542_FFVT E1000_FFVT
/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
uint64_t crcerrs;
uint64_t algnerrc;
uint64_t symerrs;
uint64_t rxerrc;
uint64_t mpc;
uint64_t scc;
uint64_t ecol;
uint64_t mcc;
uint64_t latecol;
uint64_t colc;
uint64_t dc;
uint64_t tncrs;
uint64_t sec;
uint64_t cexterr;
uint64_t rlec;
uint64_t xonrxc;
uint64_t xontxc;
uint64_t xoffrxc;
uint64_t xofftxc;
uint64_t fcruc;
uint64_t prc64;
uint64_t prc127;
uint64_t prc255;
uint64_t prc511;
uint64_t prc1023;
uint64_t prc1522;
uint64_t gprc;
uint64_t bprc;
uint64_t mprc;
uint64_t gptc;
uint64_t gorcl;
uint64_t gorch;
uint64_t gotcl;
uint64_t gotch;
uint64_t rnbc;
uint64_t ruc;
uint64_t rfc;
uint64_t roc;
uint64_t rjc;
uint64_t mgprc;
uint64_t mgpdc;
uint64_t mgptc;
uint64_t torl;
uint64_t torh;
uint64_t totl;
uint64_t toth;
uint64_t tpr;
uint64_t tpt;
uint64_t ptc64;
uint64_t ptc127;
uint64_t ptc255;
uint64_t ptc511;
uint64_t ptc1023;
uint64_t ptc1522;
uint64_t mptc;
uint64_t bptc;
uint64_t tsctc;
uint64_t tsctfc;
};
struct e1000_eeprom_info {
e1000_eeprom_type type;
uint16_t word_size;
uint16_t opcode_bits;
uint16_t address_bits;
uint16_t delay_usec;
uint16_t page_size;
boolean_t use_eerd;
boolean_t use_eewr;
};
typedef enum {
e1000_smart_speed_default = 0,
e1000_smart_speed_on,
e1000_smart_speed_off
} e1000_smart_speed;
typedef enum {
e1000_dsp_config_disabled = 0,
e1000_dsp_config_enabled,
e1000_dsp_config_activated,
e1000_dsp_config_undefined = 0xFF
} e1000_dsp_config;
typedef enum {
e1000_ms_hw_default = 0,
e1000_ms_force_master,
e1000_ms_force_slave,
e1000_ms_auto
} e1000_ms_type;
typedef enum {
e1000_ffe_config_enabled = 0,
e1000_ffe_config_active,
e1000_ffe_config_blocked
} e1000_ffe_config;
/* Structure containing variables used by the shared code (e1000_hw.c) */
struct e1000_hw {
struct list_head list_node;
struct eth_device *nic;
#ifdef CONFIG_E1000_SPI
struct spi_slave spi;
#endif
unsigned int cardnum;
pci_dev_t pdev;
uint8_t *hw_addr;
e1000_mac_type mac_type;
e1000_phy_type phy_type;
uint32_t phy_init_script;
uint32_t txd_cmd;
e1000_media_type media_type;
e1000_fc_type fc;
e1000_bus_type bus_type;
#if 0
e1000_bus_speed bus_speed;
e1000_bus_width bus_width;
uint32_t io_base;
#endif
uint32_t asf_firmware_present;
uint32_t eeprom_semaphore_present;
uint32_t swfw_sync_present;
uint32_t swfwhw_semaphore_present;
struct e1000_eeprom_info eeprom;
e1000_ms_type master_slave;
e1000_ms_type original_master_slave;
e1000_ffe_config ffe_config_state;
uint32_t phy_id;
uint32_t phy_revision;
uint32_t phy_addr;
uint32_t original_fc;
uint32_t txcw;
uint32_t autoneg_failed;
#if 0
uint32_t max_frame_size;
uint32_t min_frame_size;
uint32_t mc_filter_type;
uint32_t num_mc_addrs;
uint32_t collision_delta;
uint32_t tx_packet_delta;
uint32_t ledctl_default;
uint32_t ledctl_mode1;
uint32_t ledctl_mode2;
#endif
uint16_t autoneg_advertised;
uint16_t pci_cmd_word;
uint16_t fc_high_water;
uint16_t fc_low_water;
uint16_t fc_pause_time;
#if 0
uint16_t current_ifs_val;
uint16_t ifs_min_val;
uint16_t ifs_max_val;
uint16_t ifs_step_size;
uint16_t ifs_ratio;
#endif
uint16_t device_id;
uint16_t vendor_id;
uint16_t subsystem_id;
uint16_t subsystem_vendor_id;
uint8_t revision_id;
uint8_t autoneg;
uint8_t mdix;
uint8_t forced_speed_duplex;
uint8_t wait_autoneg_complete;
uint8_t dma_fairness;
#if 0
uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
#endif
boolean_t disable_polarity_correction;
boolean_t speed_downgraded;
boolean_t get_link_status;
boolean_t tbi_compatibility_en;
boolean_t tbi_compatibility_on;
boolean_t fc_strict_ieee;
boolean_t fc_send_xon;
boolean_t report_tx_early;
boolean_t phy_reset_disable;
boolean_t initialize_hw_bits_disable;
#if 0
boolean_t adaptive_ifs;
boolean_t ifs_params_forced;
boolean_t in_ifs_mode;
#endif
e1000_smart_speed smart_speed;
e1000_dsp_config dsp_config_state;
};
#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM
read/write registers */
#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start
operation */
#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write
complete */
#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
#define EEPROM_RESERVED_WORD 0xFFFF
/* Register Bit Masks */
/* Device Control */
#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
#define E1000_CTRL_RST 0x04000000 /* Global reset */
#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
/* Device Status */
#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
#define E1000_STATUS_SPEED_MASK 0x000000C0
#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
/* Constants used to intrepret the masked PCI-X bus speed. */
#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
/* EEPROM/Flash Control */
#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
#define E1000_EECD_FWE_MASK 0x00000030
#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
#define E1000_EECD_FWE_SHIFT 4
#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
* (0-small, 1-large) */
#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
#ifndef E1000_EEPROM_GRANT_ATTEMPTS
#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
#endif
#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
#define E1000_EECD_SIZE_EX_SHIFT 11
#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
#define E1000_EECD_SECVAL_SHIFT 22
#define E1000_STM_OPCODE 0xDB00
#define E1000_HICR_FW_RESET 0xC0
#define E1000_SHADOW_RAM_WORDS 2048
#define E1000_ICH_NVM_SIG_WORD 0x13
#define E1000_ICH_NVM_SIG_MASK 0xC0
/* EEPROM Read */
#define E1000_EERD_START 0x00000001 /* Start Read */
#define E1000_EERD_DONE 0x00000010 /* Read Done */
#define E1000_EERD_ADDR_SHIFT 8
#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
#define E1000_EERD_DATA_SHIFT 16
#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
/* EEPROM Commands - Microwire */
#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
/* EEPROM Commands - SPI */
#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
/* EEPROM Size definitions */
#define EEPROM_WORD_SIZE_SHIFT 6
#define EEPROM_SIZE_SHIFT 10
#define EEPROM_SIZE_MASK 0x1C00
/* EEPROM Word Offsets */
#define EEPROM_COMPAT 0x0003
#define EEPROM_ID_LED_SETTINGS 0x0004
#define EEPROM_VERSION 0x0005
#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude
adjustment. */
#define EEPROM_PHY_CLASS_WORD 0x0007
#define EEPROM_INIT_CONTROL1_REG 0x000A
#define EEPROM_INIT_CONTROL2_REG 0x000F
#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
#define EEPROM_INIT_3GIO_3 0x001A
#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
#define EEPROM_CFG 0x0012
#define EEPROM_FLASH_VERSION 0x0032
#define EEPROM_CHECKSUM_REG 0x003F
#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
/* Extended Device Control */
#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable
Pin 4 */
#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable
Pin 5 */
#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
#define E1000_CTRL_EXT_SWDPIN6 0x00000040 /* SWDPIN 6 value */
#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
#define E1000_CTRL_EXT_SWDPIN7 0x00000080 /* SWDPIN 7 value */
#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
#define E1000_CTRL_EXT_SWDPIO6 0x00000400 /* SWDPIN 6 Input or output */
#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
#define E1000_CTRL_EXT_SWDPIO7 0x00000800 /* SWDPIN 7 Input or output */
#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
/* MDI Control */
#define E1000_MDIC_DATA_MASK 0x0000FFFF
#define E1000_MDIC_REG_MASK 0x001F0000
#define E1000_MDIC_REG_SHIFT 16
#define E1000_MDIC_PHY_MASK 0x03E00000
#define E1000_MDIC_PHY_SHIFT 21
#define E1000_MDIC_OP_WRITE 0x04000000
#define E1000_MDIC_OP_READ 0x08000000
#define E1000_MDIC_READY 0x10000000
#define E1000_MDIC_INT_EN 0x20000000
#define E1000_MDIC_ERROR 0x40000000
#define E1000_PHY_CTRL_SPD_EN 0x00000001
#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
#define E1000_PHY_CTRL_B2B_EN 0x00000080
/* LED Control */
#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
#define E1000_LEDCTL_LED0_IVRT 0x00000040
#define E1000_LEDCTL_LED0_BLINK 0x00000080
#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
#define E1000_LEDCTL_LED1_MODE_SHIFT 8
#define E1000_LEDCTL_LED1_IVRT 0x00004000
#define E1000_LEDCTL_LED1_BLINK 0x00008000
#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
#define E1000_LEDCTL_LED2_MODE_SHIFT 16
#define E1000_LEDCTL_LED2_IVRT 0x00400000
#define E1000_LEDCTL_LED2_BLINK 0x00800000
#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
#define E1000_LEDCTL_LED3_MODE_SHIFT 24
#define E1000_LEDCTL_LED3_IVRT 0x40000000
#define E1000_LEDCTL_LED3_BLINK 0x80000000
#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
#define E1000_LEDCTL_MODE_LINK_UP 0x2
#define E1000_LEDCTL_MODE_ACTIVITY 0x3
#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
#define E1000_LEDCTL_MODE_LINK_10 0x5
#define E1000_LEDCTL_MODE_LINK_100 0x6
#define E1000_LEDCTL_MODE_LINK_1000 0x7
#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
#define E1000_LEDCTL_MODE_COLLISION 0xA
#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
#define E1000_LEDCTL_MODE_PAUSED 0xD
#define E1000_LEDCTL_MODE_LED_ON 0xE
#define E1000_LEDCTL_MODE_LED_OFF 0xF
/* Receive Address */
#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
/* Interrupt Cause Read */
#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
#define E1000_ICR_RXO 0x00000040 /* rx overrun */
#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
#define E1000_ICR_TXD_LOW 0x00008000
#define E1000_ICR_SRPD 0x00010000
/* Interrupt Cause Set */
#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
#define E1000_ICS_SRPD E1000_ICR_SRPD
/* Interrupt Mask Set */
#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
#define E1000_IMS_SRPD E1000_ICR_SRPD
/* Interrupt Mask Clear */
#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
#define E1000_IMC_SRPD E1000_ICR_SRPD
/* Receive Control */
#define E1000_RCTL_RST 0x00000001 /* Software reset */
#define E1000_RCTL_EN 0x00000002 /* enable */
#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
/* SW_W_SYNC definitions */
#define E1000_SWFW_EEP_SM 0x0001
#define E1000_SWFW_PHY0_SM 0x0002
#define E1000_SWFW_PHY1_SM 0x0004
#define E1000_SWFW_MAC_CSR_SM 0x0008
/* Receive Descriptor */
#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
/* Flow Control */
#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
/* Receive Descriptor Control */
#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
/* Transmit Descriptor Control */
#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
still to be processed. */
/* Transmit Configuration Word */
#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
/* Receive Configuration Word */
#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
#define E1000_RXCW_CC 0x10000000 /* Receive config change */
#define E1000_RXCW_C 0x20000000 /* Receive config */
#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
/* Transmit Control */
#define E1000_TCTL_RST 0x00000001 /* software reset */
#define E1000_TCTL_EN 0x00000002 /* enable tx */
#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
/* Receive Checksum Control */
#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
/* Definitions for power management and wakeup registers */
/* Wake Up Control */
#define E1000_WUC_APME 0x00000001 /* APM Enable */
#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
/* Wake Up Filter Control */
#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
/* Wake Up Status */
#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
/* Management Control */
#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
* Filtering */
#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
/* Wake Up Packet Length */
#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
#define E1000_MDALIGN 4096
/* EEPROM Commands */
#define EEPROM_READ_OPCODE 0x6 /* EERPOM read opcode */
#define EEPROM_WRITE_OPCODE 0x5 /* EERPOM write opcode */
#define EEPROM_ERASE_OPCODE 0x7 /* EERPOM erase opcode */
#define EEPROM_EWEN_OPCODE 0x13 /* EERPOM erase/write enable */
#define EEPROM_EWDS_OPCODE 0x10 /* EERPOM erast/write disable */
/* Word definitions for ID LED Settings */
#define ID_LED_RESERVED_0000 0x0000
#define ID_LED_RESERVED_FFFF 0xFFFF
#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
(ID_LED_OFF1_OFF2 << 8) | \
(ID_LED_DEF1_DEF2 << 4) | \
(ID_LED_DEF1_DEF2))
#define ID_LED_DEF1_DEF2 0x1
#define ID_LED_DEF1_ON2 0x2
#define ID_LED_DEF1_OFF2 0x3
#define ID_LED_ON1_DEF2 0x4
#define ID_LED_ON1_ON2 0x5
#define ID_LED_ON1_OFF2 0x6
#define ID_LED_OFF1_DEF2 0x7
#define ID_LED_OFF1_ON2 0x8
#define ID_LED_OFF1_OFF2 0x9
/* Mask bits for fields in Word 0x03 of the EEPROM */
#define EEPROM_COMPAT_SERVER 0x0400
#define EEPROM_COMPAT_CLIENT 0x0200
/* Mask bits for fields in Word 0x0a of the EEPROM */
#define EEPROM_WORD0A_ILOS 0x0010
#define EEPROM_WORD0A_SWDPIO 0x01E0
#define EEPROM_WORD0A_LRST 0x0200
#define EEPROM_WORD0A_FD 0x0400
#define EEPROM_WORD0A_66MHZ 0x0800
/* Mask bits for fields in Word 0x0f of the EEPROM */
#define EEPROM_WORD0F_PAUSE_MASK 0x3000
#define EEPROM_WORD0F_PAUSE 0x1000
#define EEPROM_WORD0F_ASM_DIR 0x2000
#define EEPROM_WORD0F_ANE 0x0800
#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
#define EEPROM_SUM 0xBABA
/* EEPROM Map defines (WORD OFFSETS)*/
#define EEPROM_NODE_ADDRESS_BYTE_0 0
#define EEPROM_PBA_BYTE_1 8
/* EEPROM Map Sizes (Byte Counts) */
#define PBA_SIZE 4
/* Collision related configuration parameters */
#define E1000_COLLISION_THRESHOLD 0xF
#define E1000_CT_SHIFT 4
#define E1000_COLLISION_DISTANCE 63
#define E1000_COLLISION_DISTANCE_82542 64
#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
#define E1000_GB_HDX_COLLISION_DISTANCE 512
#define E1000_COLD_SHIFT 12
/* The number of Transmit and Receive Descriptors must be a multiple of 8 */
#define REQ_TX_DESCRIPTOR_MULTIPLE 8
#define REQ_RX_DESCRIPTOR_MULTIPLE 8
/* Default values for the transmit IPG register */
#define DEFAULT_82542_TIPG_IPGT 10
#define DEFAULT_82543_TIPG_IPGT_FIBER 9
#define DEFAULT_82543_TIPG_IPGT_COPPER 8
#define E1000_TIPG_IPGT_MASK 0x000003FF
#define E1000_TIPG_IPGR1_MASK 0x000FFC00
#define E1000_TIPG_IPGR2_MASK 0x3FF00000
#define DEFAULT_82542_TIPG_IPGR1 2
#define DEFAULT_82543_TIPG_IPGR1 8
#define E1000_TIPG_IPGR1_SHIFT 10
#define DEFAULT_82542_TIPG_IPGR2 10
#define DEFAULT_82543_TIPG_IPGR2 6
#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
#define E1000_TIPG_IPGR2_SHIFT 20
#define E1000_TXDMAC_DPP 0x00000001
/* Adaptive IFS defines */
#define TX_THRESHOLD_START 8
#define TX_THRESHOLD_INCREMENT 10
#define TX_THRESHOLD_DECREMENT 1
#define TX_THRESHOLD_STOP 190
#define TX_THRESHOLD_DISABLE 0
#define TX_THRESHOLD_TIMER_MS 10000
#define MIN_NUM_XMITS 1000
#define IFS_MAX 80
#define IFS_STEP 10
#define IFS_MIN 40
#define IFS_RATIO 4
/* PBA constants */
#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
#define E1000_PBA_24K 0x0018
#define E1000_PBA_38K 0x0026
#define E1000_PBA_40K 0x0028
#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
/* Flow Control Constants */
#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
#define FLOW_CONTROL_TYPE 0x8808
/* The historical defaults for the flow control values are given below. */
#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
/* Flow Control High-Watermark: 43464 bytes */
#define E1000_FC_HIGH_THRESH 0xA9C8
/* Flow Control Low-Watermark: 43456 bytes */
#define E1000_FC_LOW_THRESH 0xA9C0
/* Flow Control Pause Time: 858 usec */
#define E1000_FC_PAUSE_TIME 0x0680
/* PCIX Config space */
#define PCIX_COMMAND_REGISTER 0xE6
#define PCIX_STATUS_REGISTER_LO 0xE8
#define PCIX_STATUS_REGISTER_HI 0xEA
#define PCIX_COMMAND_MMRBC_MASK 0x000C
#define PCIX_COMMAND_MMRBC_SHIFT 0x2
#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
#define PCIX_STATUS_HI_MMRBC_4K 0x3
#define PCIX_STATUS_HI_MMRBC_2K 0x2
/* The number of bits that we need to shift right to move the "pause"
* bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field
* in the TXCW register
*/
#define PAUSE_SHIFT 5
/* The number of bits that we need to shift left to move the "SWDPIO"
* bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field
* in the CTRL register
*/
#define SWDPIO_SHIFT 17
/* The number of bits that we need to shift left to move the "SWDPIO_EXT"
* bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The
* Extended CTRL register.
* in the CTRL register
*/
#define SWDPIO__EXT_SHIFT 4
/* The number of bits that we need to shift left to move the "ILOS"
* bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field
* in the CTRL register
*/
#define ILOS_SHIFT 3
#define RECEIVE_BUFFER_ALIGN_SIZE (256)
/* The number of milliseconds we wait for auto-negotiation to complete */
#define LINK_UP_TIMEOUT 500
#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
/* The carrier extension symbol, as received by the NIC. */
#define CARRIER_EXTENSION 0x0F
/* TBI_ACCEPT macro definition:
*
* This macro requires:
* adapter = a pointer to struct e1000_hw
* status = the 8 bit status field of the RX descriptor with EOP set
* error = the 8 bit error field of the RX descriptor with EOP set
* length = the sum of all the length fields of the RX descriptors that
* make up the current frame
* last_byte = the last byte of the frame DMAed by the hardware
* max_frame_length = the maximum frame length we want to accept.
* min_frame_length = the minimum frame length we want to accept.
*
* This macro is a conditional that should be used in the interrupt
* handler's Rx processing routine when RxErrors have been detected.
*
* Typical use:
* ...
* if (TBI_ACCEPT) {
* accept_frame = TRUE;
* e1000_tbi_adjust_stats(adapter, MacAddress);
* frame_length--;
* } else {
* accept_frame = FALSE;
* }
* ...
*/
#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
((adapter)->tbi_compatibility_on && \
(((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
((last_byte) == CARRIER_EXTENSION) && \
(((status) & E1000_RXD_STAT_VP) ? \
(((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
((length) <= ((adapter)->max_frame_size + 1))) : \
(((length) > (adapter)->min_frame_size) && \
((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
/* Structures, enums, and macros for the PHY */
/* Bit definitions for the Management Data IO (MDIO) and Management Data
* Clock (MDC) pins in the Device Control Register.
*/
#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
/* PHY 1000 MII Register/Bit Definitions */
/* PHY Registers defined by IEEE */
#define PHY_CTRL 0x00 /* Control Register */
#define PHY_STATUS 0x01 /* Status Regiser */
#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
/* M88E1000 Specific Registers */
#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
/* M88EC018 Rev 2 specific DownShift settings */
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
/* IGP01E1000 specifics */
#define IGP01E1000_IEEE_REGS_PAGE 0x0000
#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
/* IGP01E1000 Specific Registers */
#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
#define IGP02E1000_PHY_POWER_MGMT 0x19
#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
/* IGP01E1000 AGC Registers - stores the cable length values*/
#define IGP01E1000_PHY_AGC_A 0x1172
#define IGP01E1000_PHY_AGC_B 0x1272
#define IGP01E1000_PHY_AGC_C 0x1472
#define IGP01E1000_PHY_AGC_D 0x1872
/* IGP01E1000 Specific Port Config Register - R/W */
#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
#define IGP01E1000_PSCFR_PRE_EN 0x0020
#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
/* IGP02E1000 AGC Registers for cable length values */
#define IGP02E1000_PHY_AGC_A 0x11B1
#define IGP02E1000_PHY_AGC_B 0x12B1
#define IGP02E1000_PHY_AGC_C 0x14B1
#define IGP02E1000_PHY_AGC_D 0x18B1
#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in
non-D0a modes */
#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in
D0a mode */
/* IGP01E1000 DSP Reset Register */
#define IGP01E1000_PHY_DSP_RESET 0x1F33
#define IGP01E1000_PHY_DSP_SET 0x1F71
#define IGP01E1000_PHY_DSP_FFE 0x1F35
#define IGP01E1000_PHY_CHANNEL_NUM 4
#define IGP02E1000_PHY_CHANNEL_NUM 4
#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
/* IGP01E1000 PCS Initialization register - stores the polarity status when
* speed = 1000 Mbps. */
#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
/* IGP01E1000 GMII FIFO Register */
#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
* on Link-Up */
#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
/* IGP01E1000 Analog Register */
#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
/* IGP01E1000 Specific Port Control Register - R/W */
#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
#define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */
#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal
Disabled */
#define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */
#define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter
Disabled */
#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI
configuration */
#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX
configuration */
#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic
crossover */
#define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended
Distance */
#define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300
#define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */
#define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only
(Energy Detect) */
#define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */
#define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */
#define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */
#define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000
#define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12
/* PHY Specific Status Register (Page 0, Register 17) */
#define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */
#define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */
#define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */
#define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */
#define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */
#define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */
#define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */
#define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */
#define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */
#define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */
#define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */
#define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */
#define GG82563_PSSR_SPEED_MASK 0xC000
#define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */
#define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */
#define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */
/* PHY Specific Status Register 2 (Page 0, Register 19) */
#define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */
#define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */
#define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */
#define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */
#define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */
#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */
#define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */
#define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */
#define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */
#define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */
#define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */
#define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */
#define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */
/* PHY Specific Control Register 2 (Page 0, Register 26) */
#define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative
Polarity */
#define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C
#define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal
Operation */
#define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns
Sequence */
#define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns
Sequence */
#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse
Auto-Negotiation */
#define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable
1000BASE-T */
#define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000
#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */
#define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */
/* MAC Specific Control Register (Page 2, Register 21) */
/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
#define GG82563_MSCR_TX_CLK_MASK 0x0007
#define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004
#define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005
#define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006
#define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007
#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
/* DSP Distance Register (Page 5, Register 26) */
#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
1 = 50-80M;
2 = 80-110M;
3 = 110-140M;
4 = >140M */
/* Kumeran Mode Control Register (Page 193, Register 16) */
#define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs,
0=Kumeran Inband LEDs */
#define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */
#define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080
#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400
#define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz,
0=0.8MHz */
#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
/* Power Management Control Register (Page 193, Register 20) */
#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enalbe SERDES
Electrical Idle */
#define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */
#define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */
#define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse
Auto-Negotiation */
#define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps
Auto-Neg in non D0 */
#define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps
Auto-Neg Always */
#define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a
Reverse Auto-Negotiation */
#define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */
#define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */
/* In-Band Control Register (Page 194, Register 18) */
#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
/* Bits...
* 15-5: page
* 4-0: register offset
*/
#define GG82563_PAGE_SHIFT 5
#define GG82563_REG(page, reg) \
(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
#define GG82563_MIN_ALT_REG 30
/* GG82563 Specific Registers */
#define GG82563_PHY_SPEC_CTRL \
GG82563_REG(0, 16) /* PHY Specific Control */
#define GG82563_PHY_SPEC_STATUS \
GG82563_REG(0, 17) /* PHY Specific Status */
#define GG82563_PHY_INT_ENABLE \
GG82563_REG(0, 18) /* Interrupt Enable */
#define GG82563_PHY_SPEC_STATUS_2 \
GG82563_REG(0, 19) /* PHY Specific Status 2 */
#define GG82563_PHY_RX_ERR_CNTR \
GG82563_REG(0, 21) /* Receive Error Counter */
#define GG82563_PHY_PAGE_SELECT \
GG82563_REG(0, 22) /* Page Select */
#define GG82563_PHY_SPEC_CTRL_2 \
GG82563_REG(0, 26) /* PHY Specific Control 2 */
#define GG82563_PHY_PAGE_SELECT_ALT \
GG82563_REG(0, 29) /* Alternate Page Select */
#define GG82563_PHY_TEST_CLK_CTRL \
GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
#define GG82563_PHY_MAC_SPEC_CTRL \
GG82563_REG(2, 21) /* MAC Specific Control Register */
#define GG82563_PHY_MAC_SPEC_CTRL_2 \
GG82563_REG(2, 26) /* MAC Specific Control 2 */
#define GG82563_PHY_DSP_DISTANCE \
GG82563_REG(5, 26) /* DSP Distance */
/* Page 193 - Port Control Registers */
#define GG82563_PHY_KMRN_MODE_CTRL \
GG82563_REG(193, 16) /* Kumeran Mode Control */
#define GG82563_PHY_PORT_RESET \
GG82563_REG(193, 17) /* Port Reset */
#define GG82563_PHY_REVISION_ID \
GG82563_REG(193, 18) /* Revision ID */
#define GG82563_PHY_DEVICE_ID \
GG82563_REG(193, 19) /* Device ID */
#define GG82563_PHY_PWR_MGMT_CTRL \
GG82563_REG(193, 20) /* Power Management Control */
#define GG82563_PHY_RATE_ADAPT_CTRL \
GG82563_REG(193, 25) /* Rate Adaptation Control */
/* Page 194 - KMRN Registers */
#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
GG82563_REG(194, 16) /* FIFO's Control/Status */
#define GG82563_PHY_KMRN_CTRL \
GG82563_REG(194, 17) /* Control */
#define GG82563_PHY_INBAND_CTRL \
GG82563_REG(194, 18) /* Inband Control */
#define GG82563_PHY_KMRN_DIAGNOSTIC \
GG82563_REG(194, 19) /* Diagnostic */
#define GG82563_PHY_ACK_TIMEOUTS \
GG82563_REG(194, 20) /* Acknowledge Timeouts */
#define GG82563_PHY_ADV_ABILITY \
GG82563_REG(194, 21) /* Advertised Ability */
#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
GG82563_REG(194, 23) /* Link Partner Advertised Ability */
#define GG82563_PHY_ADV_NEXT_PAGE \
GG82563_REG(194, 24) /* Advertised Next Page */
#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
GG82563_REG(194, 25) /* Link Partner Advertised Next page */
#define GG82563_PHY_KMRN_MISC \
GG82563_REG(194, 26) /* Misc. */
/* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
/* PHY Status Register */
#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
/* Autoneg Advertisement Register */
#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
/* Link Partner Ability Register (Base Page) */
#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
/* Autoneg Expansion Register */
#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
/* Next Page TX Register */
#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
* of different NP
*/
#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
* 0 = cannot comply with msg
*/
#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
* 0 = sending last NP
*/
/* Link Partner Next Page Register */
#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
* of different NP
*/
#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
* 0 = cannot comply with msg
*/
#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
* 0 = sending last NP
*/
/* 1000BASE-T Control Register */
#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
/* 0=DTE device */
#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
/* 0=Configure PHY as Slave */
#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
/* 0=Automatic Master/Slave config */
#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
/* 1000BASE-T Status Register */
#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
/* Extended Status Register */
#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
/* (0=enable, 1=disable) */
/* M88E1000 PHY Specific Control Register */
#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
* 0=CLK125 toggling
*/
#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
/* Manual MDI configuration */
#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
* 100BASE-TX/10BASE-T:
* MDI Mode
*/
#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
* all speeds.
*/
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
/* 1=Enable Extended 10BASE-T distance
* (Lower 10BASE-T RX Threshold)
* 0=Normal 10BASE-T RX Threshold */
#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
/* 1=5-Bit interface in 100BASE-TX
* 0=MII interface in 100BASE-TX */
#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
/* M88E1000 PHY Specific Status Register */
#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
* 3=110-140M;4=>140M */
#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
#define M88E1000_PSSR_MDIX_SHIFT 6
#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
/* M88E1000 Extended PHY Specific Control Register */
#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
* Will assert lost lock and bring
* link down if idle not seen
* within 1ms in 1000BASE-T
*/
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the master */
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the slave */
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
/* Bit definitions for valid PHY IDs. */
#define M88E1000_E_PHY_ID 0x01410C50
#define M88E1000_I_PHY_ID 0x01410C30
#define M88E1011_I_PHY_ID 0x01410C20
#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
#define IGP01E1000_I_PHY_ID 0x02A80380
#define M88E1011_I_REV_4 0x04
#define M88E1111_I_PHY_ID 0x01410CC0
#define L1LXT971A_PHY_ID 0x001378E0
#define GG82563_E_PHY_ID 0x01410CA0
#define BME1000_E_PHY_ID 0x01410CB0
/* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF
#define PHY_SOF 0x01
#define PHY_OP_READ 0x02
#define PHY_OP_WRITE 0x01
#define PHY_TURNAROUND 0x02
#define PHY_PREAMBLE_SIZE 32
#define MII_CR_SPEED_1000 0x0040
#define MII_CR_SPEED_100 0x2000
#define MII_CR_SPEED_10 0x0000
#define E1000_PHY_ADDRESS 0x01
#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
#define PHY_REVISION_MASK 0xFFFFFFF0
#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
#define REG4_SPEED_MASK 0x01E0
#define REG9_SPEED_MASK 0x0300
#define ADVERTISE_10_HALF 0x0001
#define ADVERTISE_10_FULL 0x0002
#define ADVERTISE_100_HALF 0x0004
#define ADVERTISE_100_FULL 0x0008
#define ADVERTISE_1000_HALF 0x0010
#define ADVERTISE_1000_FULL 0x0020
#define ICH_FLASH_GFPREG 0x0000
#define ICH_FLASH_HSFSTS 0x0004
#define ICH_FLASH_HSFCTL 0x0006
#define ICH_FLASH_FADDR 0x0008
#define ICH_FLASH_FDATA0 0x0010
#define ICH_FLASH_FRACC 0x0050
#define ICH_FLASH_FREG0 0x0054
#define ICH_FLASH_FREG1 0x0058
#define ICH_FLASH_FREG2 0x005C
#define ICH_FLASH_FREG3 0x0060
#define ICH_FLASH_FPR0 0x0074
#define ICH_FLASH_FPR1 0x0078
#define ICH_FLASH_SSFSTS 0x0090
#define ICH_FLASH_SSFCTL 0x0092
#define ICH_FLASH_PREOP 0x0094
#define ICH_FLASH_OPTYPE 0x0096
#define ICH_FLASH_OPMENU 0x0098
#define ICH_FLASH_REG_MAPSIZE 0x00A0
#define ICH_FLASH_SECTOR_SIZE 4096
#define ICH_GFPREG_BASE_MASK 0x1FFF
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
/* SPI EEPROM Status Register */
#define EEPROM_STATUS_RDY_SPI 0x01
#define EEPROM_STATUS_WEN_SPI 0x02
#define EEPROM_STATUS_BP0_SPI 0x04
#define EEPROM_STATUS_BP1_SPI 0x08
#define EEPROM_STATUS_WPEN_SPI 0x80
/* SW Semaphore Register */
#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
/* FW Semaphore Register */
#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
#define E1000_FWSM_MODE_SHIFT 1
#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
#define E1000_FWSM_SKUEL_SHIFT 29
#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
#define E1000_GCR 0x05B00 /* PCI-Ex Control */
#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
#define E1000_SWSM 0x05B50 /* SW Semaphore */
#define E1000_FWSM 0x05B54 /* FW Semaphore */
#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
#define E1000_HICR 0x08F00 /* Host Inteface Control */
#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
#define IGP_ACTIVITY_LED_ENABLE 0x0300
#define IGP_LED3_MODE 0x07000000
/* Mask bit for PHY class in Word 7 of the EEPROM */
#define EEPROM_PHY_CLASS_A 0x8000
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
#define E1000_KUMCTRLSTA_REN 0x00200000
#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
/* FIFO Control */
#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
/* In-Band Control */
#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
/* Half-Duplex Control */
#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
#define E1000_MNG_ICH_IAMT_MODE 0x2
#define E1000_MNG_IAMT_MODE 0x3
#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
/* Number of milliseconds we wait for PHY configuration done after MAC reset */
#define PHY_CFG_TIMEOUT 100
#define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009
#define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008
#define AUTO_ALL_MODES 0
#ifndef E1000_MASTER_SLAVE
/* Switch to override PHY master/slave setting */
#define E1000_MASTER_SLAVE e1000_ms_hw_default
#endif
/* Extended Transmit Control */
#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
#define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000
#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
#define E1000_MC_TBL_SIZE_ICH8LAN 32
#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers
after IMS clear */
#endif /* _E1000_HW_H_ */
|
1001-study-uboot
|
drivers/net/e1000.h
|
C
|
gpl3
| 110,200
|
/*
* Opencore 10/100 ethernet mac driver
*
* Copyright (C) 2007-2008 Avionic Design Development GmbH
* Copyright (C) 2008-2009 Avionic Design GmbH
* Thierry Reding <thierry.reding@avionic-design.de>
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/cache.h>
/* register offsets */
#define MODER 0x00
#define INT_SOURCE 0x04
#define INT_MASK 0x08
#define IPGT 0x0c
#define IPGR1 0x10
#define IPGR2 0x14
#define PACKETLEN 0x18
#define COLLCONF 0x1c
#define TX_BD_NUM 0x20
#define CTRLMODER 0x24
#define MIIMODER 0x28
#define MIICOMMAND 0x2c
#define MIIADDRESS 0x30
#define MIITX_DATA 0x34
#define MIIRX_DATA 0x38
#define MIISTATUS 0x3c
#define MAC_ADDR0 0x40
#define MAC_ADDR1 0x44
#define ETH_HASH0 0x48
#define ETH_HASH1 0x4c
#define ETH_TXCTRL 0x50
/* mode register */
#define MODER_RXEN (1 << 0) /* receive enable */
#define MODER_TXEN (1 << 1) /* transmit enable */
#define MODER_NOPRE (1 << 2) /* no preamble */
#define MODER_BRO (1 << 3) /* broadcast address */
#define MODER_IAM (1 << 4) /* individual address mode */
#define MODER_PRO (1 << 5) /* promiscuous mode */
#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
#define MODER_LOOP (1 << 7) /* loopback */
#define MODER_NBO (1 << 8) /* no back-off */
#define MODER_EDE (1 << 9) /* excess defer enable */
#define MODER_FULLD (1 << 10) /* full duplex */
#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
#define MODER_DCRC (1 << 12) /* delayed CRC enable */
#define MODER_CRC (1 << 13) /* CRC enable */
#define MODER_HUGE (1 << 14) /* huge packets enable */
#define MODER_PAD (1 << 15) /* padding enabled */
#define MODER_RSM (1 << 16) /* receive small packets */
/* interrupt source and mask registers */
#define INT_MASK_TXF (1 << 0) /* transmit frame */
#define INT_MASK_TXE (1 << 1) /* transmit error */
#define INT_MASK_RXF (1 << 2) /* receive frame */
#define INT_MASK_RXE (1 << 3) /* receive error */
#define INT_MASK_BUSY (1 << 4)
#define INT_MASK_TXC (1 << 5) /* transmit control frame */
#define INT_MASK_RXC (1 << 6) /* receive control frame */
#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
#define INT_MASK_ALL ( \
INT_MASK_TXF | INT_MASK_TXE | \
INT_MASK_RXF | INT_MASK_RXE | \
INT_MASK_TXC | INT_MASK_RXC | \
INT_MASK_BUSY \
)
/* packet length register */
#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
PACKETLEN_MAX(max))
/* transmit buffer number register */
#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
/* control module mode register */
#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
/* MII mode register */
#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
#define MIIMODER_NOPRE (1 << 8) /* no preamble */
/* MII command register */
#define MIICOMMAND_SCAN (1 << 0) /* scan status */
#define MIICOMMAND_READ (1 << 1) /* read status */
#define MIICOMMAND_WRITE (1 << 2) /* write control data */
/* MII address register */
#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
MIIADDRESS_RGAD(reg))
/* MII transmit data register */
#define MIITX_DATA_VAL(x) ((x) & 0xffff)
/* MII receive data register */
#define MIIRX_DATA_VAL(x) ((x) & 0xffff)
/* MII status register */
#define MIISTATUS_LINKFAIL (1 << 0)
#define MIISTATUS_BUSY (1 << 1)
#define MIISTATUS_INVALID (1 << 2)
/* TX buffer descriptor */
#define TX_BD_CS (1 << 0) /* carrier sense lost */
#define TX_BD_DF (1 << 1) /* defer indication */
#define TX_BD_LC (1 << 2) /* late collision */
#define TX_BD_RL (1 << 3) /* retransmission limit */
#define TX_BD_RETRY_MASK (0x00f0)
#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
#define TX_BD_UR (1 << 8) /* transmitter underrun */
#define TX_BD_CRC (1 << 11) /* TX CRC enable */
#define TX_BD_PAD (1 << 12) /* pad enable */
#define TX_BD_WRAP (1 << 13)
#define TX_BD_IRQ (1 << 14) /* interrupt request enable */
#define TX_BD_READY (1 << 15) /* TX buffer ready */
#define TX_BD_LEN(x) (((x) & 0xffff) << 16)
#define TX_BD_LEN_MASK (0xffff << 16)
#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
/* RX buffer descriptor */
#define RX_BD_LC (1 << 0) /* late collision */
#define RX_BD_CRC (1 << 1) /* RX CRC error */
#define RX_BD_SF (1 << 2) /* short frame */
#define RX_BD_TL (1 << 3) /* too long */
#define RX_BD_DN (1 << 4) /* dribble nibble */
#define RX_BD_IS (1 << 5) /* invalid symbol */
#define RX_BD_OR (1 << 6) /* receiver overrun */
#define RX_BD_MISS (1 << 7)
#define RX_BD_CF (1 << 8) /* control frame */
#define RX_BD_WRAP (1 << 13)
#define RX_BD_IRQ (1 << 14) /* interrupt request enable */
#define RX_BD_EMPTY (1 << 15)
#define RX_BD_LEN(x) (((x) & 0xffff) << 16)
#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
#define ETHOC_BUFSIZ 1536
#define ETHOC_ZLEN 64
#define ETHOC_BD_BASE 0x400
#define ETHOC_TIMEOUT (HZ / 2)
#define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
/**
* struct ethoc - driver-private device structure
* @num_tx: number of send buffers
* @cur_tx: last send buffer written
* @dty_tx: last buffer actually sent
* @num_rx: number of receive buffers
* @cur_rx: current receive buffer
*/
struct ethoc {
u32 num_tx;
u32 cur_tx;
u32 dty_tx;
u32 num_rx;
u32 cur_rx;
};
/**
* struct ethoc_bd - buffer descriptor
* @stat: buffer statistics
* @addr: physical memory address
*/
struct ethoc_bd {
u32 stat;
u32 addr;
};
static inline u32 ethoc_read(struct eth_device *dev, loff_t offset)
{
return readl(dev->iobase + offset);
}
static inline void ethoc_write(struct eth_device *dev, loff_t offset, u32 data)
{
writel(data, dev->iobase + offset);
}
static inline void ethoc_read_bd(struct eth_device *dev, int index,
struct ethoc_bd *bd)
{
loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
bd->stat = ethoc_read(dev, offset + 0);
bd->addr = ethoc_read(dev, offset + 4);
}
static inline void ethoc_write_bd(struct eth_device *dev, int index,
const struct ethoc_bd *bd)
{
loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
ethoc_write(dev, offset + 0, bd->stat);
ethoc_write(dev, offset + 4, bd->addr);
}
static int ethoc_set_mac_address(struct eth_device *dev)
{
u8 *mac = dev->enetaddr;
ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
(mac[4] << 8) | (mac[5] << 0));
ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
return 0;
}
static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask)
{
ethoc_write(dev, INT_SOURCE, mask);
}
static inline void ethoc_enable_rx_and_tx(struct eth_device *dev)
{
u32 mode = ethoc_read(dev, MODER);
mode |= MODER_RXEN | MODER_TXEN;
ethoc_write(dev, MODER, mode);
}
static inline void ethoc_disable_rx_and_tx(struct eth_device *dev)
{
u32 mode = ethoc_read(dev, MODER);
mode &= ~(MODER_RXEN | MODER_TXEN);
ethoc_write(dev, MODER, mode);
}
static int ethoc_init_ring(struct eth_device *dev)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
struct ethoc_bd bd;
int i;
priv->cur_tx = 0;
priv->dty_tx = 0;
priv->cur_rx = 0;
/* setup transmission buffers */
bd.stat = TX_BD_IRQ | TX_BD_CRC;
for (i = 0; i < priv->num_tx; i++) {
if (i == priv->num_tx - 1)
bd.stat |= TX_BD_WRAP;
ethoc_write_bd(dev, i, &bd);
}
bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
for (i = 0; i < priv->num_rx; i++) {
bd.addr = (u32)NetRxPackets[i];
if (i == priv->num_rx - 1)
bd.stat |= RX_BD_WRAP;
flush_dcache(bd.addr, PKTSIZE_ALIGN);
ethoc_write_bd(dev, priv->num_tx + i, &bd);
}
return 0;
}
static int ethoc_reset(struct eth_device *dev)
{
u32 mode;
/* TODO: reset controller? */
ethoc_disable_rx_and_tx(dev);
/* TODO: setup registers */
/* enable FCS generation and automatic padding */
mode = ethoc_read(dev, MODER);
mode |= MODER_CRC | MODER_PAD;
ethoc_write(dev, MODER, mode);
/* set full-duplex mode */
mode = ethoc_read(dev, MODER);
mode |= MODER_FULLD;
ethoc_write(dev, MODER, mode);
ethoc_write(dev, IPGT, 0x15);
ethoc_ack_irq(dev, INT_MASK_ALL);
ethoc_enable_rx_and_tx(dev);
return 0;
}
static int ethoc_init(struct eth_device *dev, bd_t * bd)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
printf("ethoc\n");
priv->num_tx = 1;
priv->num_rx = PKTBUFSRX;
ethoc_write(dev, TX_BD_NUM, priv->num_tx);
ethoc_init_ring(dev);
ethoc_reset(dev);
return 0;
}
static int ethoc_update_rx_stats(struct ethoc_bd *bd)
{
int ret = 0;
if (bd->stat & RX_BD_TL) {
debug("ETHOC: " "RX: frame too long\n");
ret++;
}
if (bd->stat & RX_BD_SF) {
debug("ETHOC: " "RX: frame too short\n");
ret++;
}
if (bd->stat & RX_BD_DN)
debug("ETHOC: " "RX: dribble nibble\n");
if (bd->stat & RX_BD_CRC) {
debug("ETHOC: " "RX: wrong CRC\n");
ret++;
}
if (bd->stat & RX_BD_OR) {
debug("ETHOC: " "RX: overrun\n");
ret++;
}
if (bd->stat & RX_BD_LC) {
debug("ETHOC: " "RX: late collision\n");
ret++;
}
return ret;
}
static int ethoc_rx(struct eth_device *dev, int limit)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
int count;
for (count = 0; count < limit; ++count) {
u32 entry;
struct ethoc_bd bd;
entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
ethoc_read_bd(dev, entry, &bd);
if (bd.stat & RX_BD_EMPTY)
break;
debug("%s(): RX buffer %d, %x received\n",
__func__, priv->cur_rx, bd.stat);
if (ethoc_update_rx_stats(&bd) == 0) {
int size = bd.stat >> 16;
size -= 4; /* strip the CRC */
NetReceive((void *)bd.addr, size);
}
/* clear the buffer descriptor so it can be reused */
flush_dcache(bd.addr, PKTSIZE_ALIGN);
bd.stat &= ~RX_BD_STATS;
bd.stat |= RX_BD_EMPTY;
ethoc_write_bd(dev, entry, &bd);
priv->cur_rx++;
}
return count;
}
static int ethoc_update_tx_stats(struct ethoc_bd *bd)
{
if (bd->stat & TX_BD_LC)
debug("ETHOC: " "TX: late collision\n");
if (bd->stat & TX_BD_RL)
debug("ETHOC: " "TX: retransmit limit\n");
if (bd->stat & TX_BD_UR)
debug("ETHOC: " "TX: underrun\n");
if (bd->stat & TX_BD_CS)
debug("ETHOC: " "TX: carrier sense lost\n");
return 0;
}
static void ethoc_tx(struct eth_device *dev)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
u32 entry = priv->dty_tx % priv->num_tx;
struct ethoc_bd bd;
ethoc_read_bd(dev, entry, &bd);
if ((bd.stat & TX_BD_READY) == 0)
(void)ethoc_update_tx_stats(&bd);
}
static int ethoc_send(struct eth_device *dev, volatile void *packet, int length)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
struct ethoc_bd bd;
u32 entry;
u32 pending;
int tmo;
entry = priv->cur_tx % priv->num_tx;
ethoc_read_bd(dev, entry, &bd);
if (unlikely(length < ETHOC_ZLEN))
bd.stat |= TX_BD_PAD;
else
bd.stat &= ~TX_BD_PAD;
bd.addr = (u32)packet;
flush_dcache(bd.addr, length);
bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
bd.stat |= TX_BD_LEN(length);
ethoc_write_bd(dev, entry, &bd);
/* start transmit */
bd.stat |= TX_BD_READY;
ethoc_write_bd(dev, entry, &bd);
/* wait for transfer to succeed */
tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
while (1) {
pending = ethoc_read(dev, INT_SOURCE);
ethoc_ack_irq(dev, pending & ~INT_MASK_RX);
if (pending & INT_MASK_BUSY)
debug("%s(): packet dropped\n", __func__);
if (pending & INT_MASK_TX) {
ethoc_tx(dev);
break;
}
if (get_timer(0) >= tmo) {
debug("%s(): timed out\n", __func__);
return -1;
}
}
debug("%s(): packet sent\n", __func__);
return 0;
}
static void ethoc_halt(struct eth_device *dev)
{
ethoc_disable_rx_and_tx(dev);
}
static int ethoc_recv(struct eth_device *dev)
{
u32 pending;
pending = ethoc_read(dev, INT_SOURCE);
ethoc_ack_irq(dev, pending);
if (pending & INT_MASK_BUSY)
debug("%s(): packet dropped\n", __func__);
if (pending & INT_MASK_RX) {
debug("%s(): rx irq\n", __func__);
ethoc_rx(dev, PKTBUFSRX);
}
return 0;
}
int ethoc_initialize(u8 dev_num, int base_addr)
{
struct ethoc *priv;
struct eth_device *dev;
priv = malloc(sizeof(*priv));
if (!priv)
return 0;
dev = malloc(sizeof(*dev));
if (!dev) {
free(priv);
return 0;
}
memset(dev, 0, sizeof(*dev));
dev->priv = priv;
dev->iobase = base_addr;
dev->init = ethoc_init;
dev->halt = ethoc_halt;
dev->send = ethoc_send;
dev->recv = ethoc_recv;
dev->write_hwaddr = ethoc_set_mac_address;
sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
eth_register(dev);
return 1;
}
|
1001-study-uboot
|
drivers/net/ethoc.c
|
C
|
gpl3
| 13,051
|
/*
Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
are GPL, so this is, of course, GPL.
==========================================================================
dev/dp83902a.h
National Semiconductor DP83902a ethernet chip
==========================================================================
####ECOSGPLCOPYRIGHTBEGIN####
-------------------------------------------
This file is part of eCos, the Embedded Configurable Operating System.
Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
eCos is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 or (at your option) any later version.
eCos is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with eCos; if not, write to the Free Software Foundation, Inc.,
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
As a special exception, if other files instantiate templates or use macros
or inline functions from this file, or you compile this file and link it
with other works to produce a work based on this file, this file does not
by itself cause the resulting work to be covered by the GNU General Public
License. However the source code for this file must still be made available
in accordance with section (3) of the GNU General Public License.
This exception does not invalidate any other reasons why a work based on
this file might be covered by the GNU General Public License.
Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
at http://sources.redhat.com/ecos/ecos-license/
-------------------------------------------
####ECOSGPLCOPYRIGHTEND####
####BSDCOPYRIGHTBEGIN####
-------------------------------------------
Portions of this software may have been derived from OpenBSD or other sources,
and are covered by the appropriate copyright disclaimers included herein.
-------------------------------------------
####BSDCOPYRIGHTEND####
==========================================================================
#####DESCRIPTIONBEGIN####
Author(s): gthomas
Contributors: gthomas, jskov
Date: 2001-06-13
Purpose:
Description:
####DESCRIPTIONEND####
==========================================================================
*/
/*
* NE2000 support header file.
* Created by Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#ifndef __DRIVERS_NE2000_H__
#define __DRIVERS_NE2000_H__
/* Enable NE2000 basic init function */
#define NE2000_BASIC_INIT
#define DP_DATA 0x10
#define START_PG 0x50 /* First page of TX buffer */
#define START_PG2 0x48
#define STOP_PG 0x80 /* Last page +1 of RX ring */
#define RX_START 0x50
#define RX_END 0x80
#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_)))
#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_)
#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_)))
#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_)
#endif /* __DRIVERS_NE2000_H__ */
|
1001-study-uboot
|
drivers/net/ne2000.h
|
C
|
gpl3
| 3,388
|
/*------------------------------------------------------------------------
. smc91111.h - macros for the LAN91C111 Ethernet Driver
.
. (C) Copyright 2002
. Sysgo Real-Time Solutions, GmbH <www.elinos.com>
. Rolf Offermanns <rof@sysgo.de>
. Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
. Developed by Simple Network Magic Corporation (SNMC)
. Copyright (C) 1996 by Erik Stahlman (ES)
.
. This program is free software; you can redistribute it and/or modify
. it under the terms of the GNU General Public License as published by
. the Free Software Foundation; either version 2 of the License, or
. (at your option) any later version.
.
. This program is distributed in the hope that it will be useful,
. but WITHOUT ANY WARRANTY; without even the implied warranty of
. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
. GNU General Public License for more details.
.
. You should have received a copy of the GNU General Public License
. along with this program; if not, write to the Free Software
. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
.
. This file contains register information and access macros for
. the LAN91C111 single chip ethernet controller. It is a modified
. version of the smc9194.h file.
.
. Information contained in this file was obtained from the LAN91C111
. manual from SMC. To get a copy, if you really want one, you can find
. information under www.smsc.com.
.
. Authors
. Erik Stahlman ( erik@vt.edu )
. Daris A Nevil ( dnevil@snmc.com )
.
. History
. 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
.
---------------------------------------------------------------------------*/
#ifndef _SMC91111_H_
#define _SMC91111_H_
#include <asm/types.h>
#include <config.h>
/*
* This function may be called by the board specific initialisation code
* in order to override the default mac address.
*/
void smc_set_mac_addr (const unsigned char *addr);
/* I want some simple types */
typedef unsigned char byte;
typedef unsigned short word;
typedef unsigned long int dword;
struct smc91111_priv{
u8 dev_num;
};
/*
. DEBUGGING LEVELS
.
. 0 for normal operation
. 1 for slightly more details
. >2 for various levels of increasingly useless information
. 2 for interrupt tracking, status flags
. 3 for packet info
. 4 for complete packet dumps
*/
/*#define SMC_DEBUG 0 */
/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
#define SMC_IO_EXTENT 16
#ifdef CONFIG_CPU_PXA25X
#ifdef CONFIG_XSENGINE
#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1))))
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
#define SMC_inb(a,p) ({ \
unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \
if (__p & 2) __v >>= 8; \
else __v &= 0xff; \
__v; })
#elif defined(CONFIG_XAENIAX)
#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
#define SMC_inw(a,z) ({ \
unsigned int __p = (unsigned int)((a)->iobase + (z)); \
unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \
if (__p & 3) __v >>= 16; \
else __v &= 0xffff; \
__v; })
#define SMC_inb(a,p) ({ \
unsigned int ___v = SMC_inw((a),(p) & ~1); \
if ((p) & 1) ___v >>= 8; \
else ___v &= 0xff; \
___v; })
#else
#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
#define SMC_inb(a,p) ({ \
unsigned int __p = (unsigned int)((a)->iobase + (p)); \
unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \
if (__p & 1) __v >>= 8; \
else __v &= 0xff; \
__v; })
#endif
#ifdef CONFIG_XSENGINE
#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d)
#elif defined (CONFIG_XAENIAX)
#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
#define SMC_outw(a,d,p) ({ \
dword __dwo = SMC_inl((a),(p) & ~3); \
dword __dwn = (word)(d); \
__dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \
__dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \
SMC_outl((a), __dwo, (p) & ~3); \
})
#else
#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
#endif
#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
word __w = SMC_inw((a),(r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
SMC_outw((a),__w,(r)&~1); \
})
#define SMC_outsl(a,r,b,l) ({ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
SMC_outl((a), *(__b2 + __i), r); \
} \
})
#define SMC_outsw(a,r,b,l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
SMC_outw((a), *(__b2 + __i), r); \
} \
})
#define SMC_insl(a,r,b,l) ({ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inl((a),(r)); \
SMC_inl((a),0); \
}; \
})
#define SMC_insw(a,r,b,l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inw((a),(r)); \
SMC_inw((a),0); \
}; \
})
#define SMC_insb(a,r,b,l) ({ int __i ; \
byte *__b2; \
__b2 = (byte *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inb((a),(r)); \
SMC_inb((a),0); \
}; \
})
#elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */
#define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); })
#define SMC_LEON_SWAP32(_x_) \
({ dword _x = (_x_); \
((_x << 24) | \
((0x0000FF00UL & _x) << 8) | \
((0x00FF0000UL & _x) >> 8) | \
(_x >> 24)); })
#define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0)))))
#define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0))))
#define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0)))))
#define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0))))
#define SMC_inb(a,p) ({ \
word ___v = SMC_inw((a),(p) & ~1); \
if ((p) & 1) ___v >>= 8; \
else ___v &= 0xff; \
___v; })
#define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d))
#define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d))
#define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d))
#define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d))
#define SMC_outb(a,d,r) do{ word __d = (byte)(d); \
word __w = SMC_inw((a),(r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
SMC_outw((a),__w,(r)&~1); \
}while(0)
#define SMC_outsl(a,r,b,l) do{ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
SMC_outl_nosw((a), *(__b2 + __i), r); \
} \
}while(0)
#define SMC_outsw(a,r,b,l) do{ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
SMC_outw_nosw((a), *(__b2 + __i), r); \
} \
}while(0)
#define SMC_insl(a,r,b,l) do{ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inl_nosw((a),(r)); \
}; \
}while(0)
#define SMC_insw(a,r,b,l) do{ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inw_nosw((a),(r)); \
}; \
}while(0)
#define SMC_insb(a,r,b,l) do{ int __i ; \
byte *__b2; \
__b2 = (byte *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inb((a),(r)); \
}; \
}while(0)
#else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */
#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
/*
* We have only 16 Bit PCMCIA access on Socket 0
*/
#ifdef CONFIG_ADNPESC1
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
#elif CONFIG_BLACKFIN
#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;})
#else
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r))))
#endif
#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
#ifdef CONFIG_ADNPESC1
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d)
#elif CONFIG_BLACKFIN
#define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();}
#else
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d)
#endif
#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \
word __w = SMC_inw((a),(r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
SMC_outw((a),__w,(r)&~1); \
})
#if 0
#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l))
#else
#define SMC_outsw(a,r,b,l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
SMC_outw((a), *(__b2 + __i), r); \
} \
})
#endif
#if 0
#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l))
#else
#define SMC_insw(a,r,b,l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inw((a),(r)); \
SMC_inw((a),0); \
}; \
})
#endif
#endif /* CONFIG_SMC_USE_IOFUNCS */
#if defined(CONFIG_SMC_USE_32_BIT)
#ifdef CONFIG_XSENGINE
#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1))))
#else
#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r))))
#endif
#define SMC_insl(a,r,b,l) ({ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inl((a),(r)); \
SMC_inl((a),0); \
}; \
})
#ifdef CONFIG_XSENGINE
#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d)
#else
#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d)
#endif
#define SMC_outsl(a,r,b,l) ({ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
SMC_outl((a), *(__b2 + __i), r); \
} \
})
#endif /* CONFIG_SMC_USE_32_BIT */
#endif
/*---------------------------------------------------------------
.
. A description of the SMSC registers is probably in order here,
. although for details, the SMC datasheet is invaluable.
.
. Basically, the chip has 4 banks of registers ( 0 to 3 ), which
. are accessed by writing a number into the BANK_SELECT register
. ( I also use a SMC_SELECT_BANK macro for this ).
.
. The banks are configured so that for most purposes, bank 2 is all
. that is needed for simple run time tasks.
-----------------------------------------------------------------------*/
/*
. Bank Select Register:
.
. yyyy yyyy 0000 00xx
. xx = bank number
. yyyy yyyy = 0x33, for identification purposes.
*/
#define BANK_SELECT 14
/* Transmit Control Register */
/* BANK 0 */
#define TCR_REG 0x0000 /* transmit control register */
#define TCR_ENABLE 0x0001 /* When 1 we can transmit */
#define TCR_LOOP 0x0002 /* Controls output pin LBK */
#define TCR_FORCOL 0x0004 /* When 1 will force a collision */
#define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */
#define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */
#define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */
#define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */
#define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */
#define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */
#define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */
#define TCR_CLEAR 0 /* do NOTHING */
/* the default settings for the TCR register : */
/* QUESTION: do I want to enable padding of short packets ? */
#define TCR_DEFAULT TCR_ENABLE
/* EPH Status Register */
/* BANK 0 */
#define EPH_STATUS_REG 0x0002
#define ES_TX_SUC 0x0001 /* Last TX was successful */
#define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */
#define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */
#define ES_LTX_MULT 0x0008 /* Last tx was a multicast */
#define ES_16COL 0x0010 /* 16 Collisions Reached */
#define ES_SQET 0x0020 /* Signal Quality Error Test */
#define ES_LTXBRD 0x0040 /* Last tx was a broadcast */
#define ES_TXDEFR 0x0080 /* Transmit Deferred */
#define ES_LATCOL 0x0200 /* Late collision detected on last tx */
#define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */
#define ES_EXC_DEF 0x0800 /* Excessive Deferral */
#define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */
#define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */
#define ES_TXUNRN 0x8000 /* Tx Underrun */
/* Receive Control Register */
/* BANK 0 */
#define RCR_REG 0x0004
#define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */
#define RCR_PRMS 0x0002 /* Enable promiscuous mode */
#define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */
#define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */
#define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */
#define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */
#define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */
#define RCR_SOFTRST 0x8000 /* resets the chip */
/* the normal settings for the RCR register : */
#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
#define RCR_CLEAR 0x0 /* set it to a base state */
/* Counter Register */
/* BANK 0 */
#define COUNTER_REG 0x0006
/* Memory Information Register */
/* BANK 0 */
#define MIR_REG 0x0008
/* Receive/Phy Control Register */
/* BANK 0 */
#define RPC_REG 0x000A
#define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */
#define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */
#define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */
#define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */
#define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */
#define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */
#define RPC_LED_RES (0x01) /* LED = Reserved */
#define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */
#define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */
#define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */
#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */
#define RPC_LED_TX (0x06) /* LED = TX packet occurred */
#define RPC_LED_RX (0x07) /* LED = RX packet occurred */
#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
/* buggy schematic: LEDa -> yellow, LEDb --> green */
#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
| (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
| (RPC_LED_100_10 << RPC_LSXB_SHFT) )
#elif defined(CONFIG_ADNPESC1)
/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
| (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
| (RPC_LED_100_10 << RPC_LSXB_SHFT) )
#else
/* SMSC reference design: LEDa --> green, LEDb --> yellow */
#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
| (RPC_LED_100_10 << RPC_LSXA_SHFT) \
| (RPC_LED_TX_RX << RPC_LSXB_SHFT) )
#endif
/* Bank 0 0x000C is reserved */
/* Bank Select Register */
/* All Banks */
#define BSR_REG 0x000E
/* Configuration Reg */
/* BANK 1 */
#define CONFIG_REG 0x0000
#define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */
#define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */
#define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */
#define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */
/* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */
#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
/* Base Address Register */
/* BANK 1 */
#define BASE_REG 0x0002
/* Individual Address Registers */
/* BANK 1 */
#define ADDR0_REG 0x0004
#define ADDR1_REG 0x0006
#define ADDR2_REG 0x0008
/* General Purpose Register */
/* BANK 1 */
#define GP_REG 0x000A
/* Control Register */
/* BANK 1 */
#define CTL_REG 0x000C
#define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */
#define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */
#define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */
#define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */
#define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */
#define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */
#define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */
#define CTL_STORE 0x0001 /* When set stores registers into EEPROM */
#define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/
/* MMU Command Register */
/* BANK 2 */
#define MMU_CMD_REG 0x0000
#define MC_BUSY 1 /* When 1 the last release has not completed */
#define MC_NOP (0<<5) /* No Op */
#define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */
#define MC_RESET (2<<5) /* Reset MMU to initial state */
#define MC_REMOVE (3<<5) /* Remove the current rx packet */
#define MC_RELEASE (4<<5) /* Remove and release the current rx packet */
#define MC_FREEPKT (5<<5) /* Release packet in PNR register */
#define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */
#define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */
/* Packet Number Register */
/* BANK 2 */
#define PN_REG 0x0002
/* Allocation Result Register */
/* BANK 2 */
#define AR_REG 0x0003
#define AR_FAILED 0x80 /* Alocation Failed */
/* RX FIFO Ports Register */
/* BANK 2 */
#define RXFIFO_REG 0x0004 /* Must be read as a word */
#define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */
/* TX FIFO Ports Register */
/* BANK 2 */
#define TXFIFO_REG RXFIFO_REG /* Must be read as a word */
#define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */
/* Pointer Register */
/* BANK 2 */
#define PTR_REG 0x0006
#define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */
#define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */
#define PTR_READ 0x2000 /* When 1 the operation is a read */
#define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */
/* Data Register */
/* BANK 2 */
#define SMC91111_DATA_REG 0x0008
/* Interrupt Status/Acknowledge Register */
/* BANK 2 */
#define SMC91111_INT_REG 0x000C
/* Interrupt Mask Register */
/* BANK 2 */
#define IM_REG 0x000D
#define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */
#define IM_ERCV_INT 0x40 /* Early Receive Interrupt */
#define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */
#define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */
#define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */
#define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */
#define IM_TX_INT 0x02 /* Transmit Interrrupt */
#define IM_RCV_INT 0x01 /* Receive Interrupt */
/* Multicast Table Registers */
/* BANK 3 */
#define MCAST_REG1 0x0000
#define MCAST_REG2 0x0002
#define MCAST_REG3 0x0004
#define MCAST_REG4 0x0006
/* Management Interface Register (MII) */
/* BANK 3 */
#define MII_REG 0x0008
#define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */
#define MII_MDOE 0x0008 /* MII Output Enable */
#define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */
#define MII_MDI 0x0002 /* MII Input, pin MDI */
#define MII_MDO 0x0001 /* MII Output, pin MDO */
/* Revision Register */
/* BANK 3 */
#define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
/* Early RCV Register */
/* BANK 3 */
/* this is NOT on SMC9192 */
#define ERCV_REG 0x000C
#define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */
#define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */
/* External Register */
/* BANK 7 */
#define EXT_REG 0x0000
#define CHIP_9192 3
#define CHIP_9194 4
#define CHIP_9195 5
#define CHIP_9196 6
#define CHIP_91100 7
#define CHIP_91100FD 8
#define CHIP_91111FD 9
#if 0
static const char * chip_ids[ 15 ] = {
NULL, NULL, NULL,
/* 3 */ "SMC91C90/91C92",
/* 4 */ "SMC91C94",
/* 5 */ "SMC91C95",
/* 6 */ "SMC91C96",
/* 7 */ "SMC91C100",
/* 8 */ "SMC91C100FD",
/* 9 */ "SMC91C111",
NULL, NULL,
NULL, NULL, NULL};
#endif
/*
. Transmit status bits
*/
#define TS_SUCCESS 0x0001
#define TS_LOSTCAR 0x0400
#define TS_LATCOL 0x0200
#define TS_16COL 0x0010
/*
. Receive status bits
*/
#define RS_ALGNERR 0x8000
#define RS_BRODCAST 0x4000
#define RS_BADCRC 0x2000
#define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */
#define RS_TOOLONG 0x0800
#define RS_TOOSHORT 0x0400
#define RS_MULTICAST 0x0001
#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
/* PHY Types */
enum {
PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */
PHY_LAN83C180
};
/* PHY Register Addresses (LAN91C111 Internal PHY) */
/* PHY Control Register */
#define PHY_CNTL_REG 0x00
#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */
#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */
#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */
#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */
#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */
#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */
#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */
#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */
#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */
/* PHY Status Register */
#define PHY_STAT_REG 0x01
#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */
#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */
#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */
#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */
#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */
#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */
#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */
#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */
#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */
#define PHY_STAT_LINK 0x0004 /* 1=valid link */
#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */
#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */
/* PHY Identifier Registers */
#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */
#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */
/* PHY Auto-Negotiation Advertisement Register */
#define PHY_AD_REG 0x04
#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */
#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */
#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */
#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */
#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */
#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */
#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */
#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */
#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */
/* PHY Auto-negotiation Remote End Capability Register */
#define PHY_RMT_REG 0x05
/* Uses same bit definitions as PHY_AD_REG */
/* PHY Configuration Register 1 */
#define PHY_CFG1_REG 0x10
#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */
#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */
#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */
#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */
#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */
#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */
#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */
#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */
#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */
#define PHY_CFG1_TLVL_MASK 0x003C
#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */
/* PHY Configuration Register 2 */
#define PHY_CFG2_REG 0x11
#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */
#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */
#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */
#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */
/* PHY Status Output (and Interrupt status) Register */
#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */
#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */
#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */
#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */
#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */
#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */
#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */
#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */
#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */
#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */
#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */
/* PHY Interrupt/Status Mask Register */
#define PHY_MASK_REG 0x13 /* Interrupt Mask */
/* Uses the same bit definitions as PHY_INT_REG */
/*-------------------------------------------------------------------------
. I define some macros to make it easier to do somewhat common
. or slightly complicated, repeated tasks.
--------------------------------------------------------------------------*/
/* select a register bank, 0 to 3 */
#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); }
/* this enables an interrupt in the interrupt mask register */
#define SMC_ENABLE_INT(a,x) {\
unsigned char mask;\
SMC_SELECT_BANK((a),2);\
mask = SMC_inb((a), IM_REG );\
mask |= (x);\
SMC_outb( (a), mask, IM_REG ); \
}
/* this disables an interrupt from the interrupt mask register */
#define SMC_DISABLE_INT(a,x) {\
unsigned char mask;\
SMC_SELECT_BANK(2);\
mask = SMC_inb( (a), IM_REG );\
mask &= ~(x);\
SMC_outb( (a), mask, IM_REG ); \
}
/*----------------------------------------------------------------------
. Define the interrupts that I want to receive from the card
.
. I want:
. IM_EPH_INT, for nasty errors
. IM_RCV_INT, for happy received packets
. IM_RX_OVRN_INT, because I have to kick the receiver
. IM_MDINT, for PHY Register 18 Status Changes
--------------------------------------------------------------------------*/
#define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
IM_MDINT)
#endif /* _SMC_91111_H_ */
|
1001-study-uboot
|
drivers/net/smc91111.h
|
C
|
gpl3
| 26,722
|
/*
* Dave Ethernet Controller driver
*
* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#ifndef CONFIG_DNET_AUTONEG_TIMEOUT
#define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */
#endif
#include <net.h>
#include <malloc.h>
#include <linux/mii.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/unaligned.h>
#include "dnet.h"
struct dnet_device {
struct dnet_registers *regs;
const struct device *dev;
struct eth_device netdev;
unsigned short phy_addr;
};
/* get struct dnet_device from given struct netdev */
#define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev)
/* function for reading internal MAC register */
u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg)
{
u16 data_read;
/* issue a read */
writel(reg, &dnet->regs->MACREG_ADDR);
/* since a read/write op to the MAC is very slow,
* we must wait before reading the data */
udelay(1);
/* read data read from the MAC register */
data_read = readl(&dnet->regs->MACREG_DATA);
/* all done */
return data_read;
}
/* function for writing internal MAC register */
void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val)
{
/* load data to write */
writel(val, &dnet->regs->MACREG_DATA);
/* issue a write */
writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR);
/* since a read/write op to the MAC is very slow,
* we must wait before exiting */
udelay(1);
}
static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value)
{
u16 tmp;
debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n",
dnet->phy_addr, reg, value);
while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
DNET_INTERNAL_GMII_MNG_CMD_FIN))
;
/* prepare for a write operation */
tmp = (1 << 13);
/* only 5 bits allowed for register offset */
reg &= 0x1f;
/* prepare reg_value for a write */
tmp |= (dnet->phy_addr << 8);
tmp |= reg;
/* write data to write first */
dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
/* write control word */
dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
DNET_INTERNAL_GMII_MNG_CMD_FIN))
;
}
static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg)
{
u16 value;
while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
DNET_INTERNAL_GMII_MNG_CMD_FIN))
;
/* only 5 bits allowed for register offset*/
reg &= 0x1f;
/* prepare reg_value for a read */
value = (dnet->phy_addr << 8);
value |= reg;
/* write control word */
dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
/* wait for end of transfer */
while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
DNET_INTERNAL_GMII_MNG_CMD_FIN))
;
value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG);
debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n",
dnet->phy_addr, reg, value);
return value;
}
static int dnet_send(struct eth_device *netdev, volatile void *packet,
int length)
{
struct dnet_device *dnet = to_dnet(netdev);
int i, wrsz;
unsigned int *bufp;
unsigned int tx_cmd;
debug(DRIVERNAME "[%s] Sending %u bytes\n", __func__, length);
bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC);
wrsz = (u32)length + 3;
wrsz += ((u32)packet) & 0x3;
wrsz >>= 2;
tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length;
/* check if there is enough room for the current frame */
if (wrsz < (DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT))) {
for (i = 0; i < wrsz; i++)
writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
/*
* inform MAC that a packet's written and ready
* to be shipped out
*/
writel(tx_cmd, &dnet->regs->TX_LEN_FIFO);
} else {
printf(DRIVERNAME "No free space (actual %d, required %d "
"(words))\n", DNET_FIFO_SIZE -
readl(&dnet->regs->TX_FIFO_WCNT), wrsz);
}
/* No one cares anyway */
return 0;
}
static int dnet_recv(struct eth_device *netdev)
{
struct dnet_device *dnet = to_dnet(netdev);
unsigned int *data_ptr;
int pkt_len, poll, i;
u32 cmd_word;
debug("Waiting for pkt (polling)\n");
poll = 50;
while ((readl(&dnet->regs->RX_FIFO_WCNT) >> 16) == 0) {
udelay(10); /* wait 10 usec */
if (--poll == 0)
return 0; /* no pkt available */
}
cmd_word = readl(&dnet->regs->RX_LEN_FIFO);
pkt_len = cmd_word & 0xFFFF;
debug("Got pkt with size %d bytes\n", pkt_len);
if (cmd_word & 0xDF180000)
printf("%s packet receive error %x\n", __func__, cmd_word);
data_ptr = (unsigned int *) NetRxPackets[0];
for (i = 0; i < (pkt_len + 3) >> 2; i++)
*data_ptr++ = readl(&dnet->regs->RX_DATA_FIFO);
NetReceive(NetRxPackets[0], pkt_len + 5); /* ok + 5 ?? */
return 0;
}
static void dnet_set_hwaddr(struct eth_device *netdev)
{
struct dnet_device *dnet = to_dnet(netdev);
u16 tmp;
tmp = get_unaligned_be16(netdev->enetaddr);
dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
tmp = get_unaligned_be16(&netdev->enetaddr[2]);
dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
tmp = get_unaligned_be16(&netdev->enetaddr[4]);
dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
}
static void dnet_phy_reset(struct dnet_device *dnet)
{
struct eth_device *netdev = &dnet->netdev;
int i;
u16 status, adv;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
dnet_mdio_write(dnet, MII_ADVERTISE, adv);
printf("%s: Starting autonegotiation...\n", netdev->name);
dnet_mdio_write(dnet, MII_BMCR, (BMCR_ANENABLE
| BMCR_ANRESTART));
for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
status = dnet_mdio_read(dnet, MII_BMSR);
if (status & BMSR_ANEGCOMPLETE)
break;
udelay(100);
}
if (status & BMSR_ANEGCOMPLETE)
printf("%s: Autonegotiation complete\n", netdev->name);
else
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
netdev->name, status);
}
static int dnet_phy_init(struct dnet_device *dnet)
{
struct eth_device *netdev = &dnet->netdev;
u16 phy_id, status, adv, lpa;
int media, speed, duplex;
int i;
u32 ctl_reg;
/* Find a PHY */
for (i = 0; i < 32; i++) {
dnet->phy_addr = i;
phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
if (phy_id != 0xffff) {
/* ok we found it */
printf("Found PHY at address %d PHYID (%04x:%04x)\n",
i, phy_id,
dnet_mdio_read(dnet, MII_PHYSID2));
break;
}
}
/* Check if the PHY is up to snuff... */
phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
if (phy_id == 0xffff) {
printf("%s: No PHY present\n", netdev->name);
return -1;
}
status = dnet_mdio_read(dnet, MII_BMSR);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
dnet_phy_reset(dnet);
for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
status = dnet_mdio_read(dnet, MII_BMSR);
if (status & BMSR_LSTATUS)
break;
udelay(100);
}
}
if (!(status & BMSR_LSTATUS)) {
printf("%s: link down (status: 0x%04x)\n",
netdev->name, status);
return -1;
} else {
adv = dnet_mdio_read(dnet, MII_ADVERTISE);
lpa = dnet_mdio_read(dnet, MII_LPA);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
? 1 : 0);
duplex = (media & ADVERTISE_FULL) ? 1 : 0;
/* 1000BaseT ethernet is not supported */
printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
netdev->name,
speed ? "100" : "10",
duplex ? "full" : "half",
lpa);
ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
if (duplex)
ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
else
ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
return 0;
}
}
static int dnet_init(struct eth_device *netdev, bd_t *bd)
{
struct dnet_device *dnet = to_dnet(netdev);
u32 config;
/*
* dnet_halt should have been called at some point before now,
* so we'll assume the controller is idle.
*/
/* set hardware address */
dnet_set_hwaddr(netdev);
if (dnet_phy_init(dnet) < 0)
return -1;
/* flush rx/tx fifos */
writel(DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
&dnet->regs->SYS_CTL);
udelay(1000);
writel(0, &dnet->regs->SYS_CTL);
config = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, config);
/* Enable TX and RX */
dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG,
DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
return 0;
}
static void dnet_halt(struct eth_device *netdev)
{
struct dnet_device *dnet = to_dnet(netdev);
/* Disable TX and RX */
dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, 0);
}
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct dnet_device *dnet;
struct eth_device *netdev;
unsigned int dev_capa;
dnet = malloc(sizeof(struct dnet_device));
if (!dnet) {
printf("Error: Failed to allocate memory for DNET%d\n", id);
return -1;
}
memset(dnet, 0, sizeof(struct dnet_device));
netdev = &dnet->netdev;
dnet->regs = (struct dnet_registers *)regs;
dnet->phy_addr = phy_addr;
sprintf(netdev->name, "dnet%d", id);
netdev->init = dnet_init;
netdev->halt = dnet_halt;
netdev->send = dnet_send;
netdev->recv = dnet_recv;
dev_capa = readl(&dnet->regs->VERCAPS) & 0xFFFF;
debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev->name,
(dev_capa & DNET_HAS_MDIO) ? "" : "no ",
(dev_capa & DNET_HAS_IRQ) ? "" : "no ",
(dev_capa & DNET_HAS_GIGABIT) ? "" : "no ",
(dev_capa & DNET_HAS_DMA) ? "" : "no ");
eth_register(netdev);
return 0;
}
|
1001-study-uboot
|
drivers/net/dnet.c
|
C
|
gpl3
| 9,896
|
/*
* (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
*
* This driver for AMD PCnet network controllers is derived from the
* Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
#define PCNET_DEBUG1(fmt,args...) \
debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
#define PCNET_DEBUG2(fmt,args...) \
debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
#if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975)
#error "Macro for PCnet chip version is not defined!"
#endif
/*
* Set the number of Tx and Rx buffers, using Log_2(# buffers).
* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
*/
#define PCNET_LOG_TX_BUFFERS 0
#define PCNET_LOG_RX_BUFFERS 2
#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
#define PKT_BUF_SZ 1544
/* The PCNET Rx and Tx ring descriptors. */
struct pcnet_rx_head {
u32 base;
s16 buf_length;
s16 status;
u32 msg_length;
u32 reserved;
};
struct pcnet_tx_head {
u32 base;
s16 length;
s16 status;
u32 misc;
u32 reserved;
};
/* The PCNET 32-Bit initialization block, described in databook. */
struct pcnet_init_block {
u16 mode;
u16 tlen_rlen;
u8 phys_addr[6];
u16 reserved;
u32 filter[2];
/* Receive and transmit ring base, along with extra bits. */
u32 rx_ring;
u32 tx_ring;
u32 reserved2;
};
typedef struct pcnet_priv {
struct pcnet_rx_head rx_ring[RX_RING_SIZE];
struct pcnet_tx_head tx_ring[TX_RING_SIZE];
struct pcnet_init_block init_block;
/* Receive Buffer space */
unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
int cur_rx;
int cur_tx;
} pcnet_priv_t;
static pcnet_priv_t *lp;
/* Offsets from base I/O address for WIO mode */
#define PCNET_RDP 0x10
#define PCNET_RAP 0x12
#define PCNET_RESET 0x14
#define PCNET_BDP 0x16
static u16 pcnet_read_csr (struct eth_device *dev, int index)
{
outw (index, dev->iobase + PCNET_RAP);
return inw (dev->iobase + PCNET_RDP);
}
static void pcnet_write_csr (struct eth_device *dev, int index, u16 val)
{
outw (index, dev->iobase + PCNET_RAP);
outw (val, dev->iobase + PCNET_RDP);
}
static u16 pcnet_read_bcr (struct eth_device *dev, int index)
{
outw (index, dev->iobase + PCNET_RAP);
return inw (dev->iobase + PCNET_BDP);
}
static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val)
{
outw (index, dev->iobase + PCNET_RAP);
outw (val, dev->iobase + PCNET_BDP);
}
static void pcnet_reset (struct eth_device *dev)
{
inw (dev->iobase + PCNET_RESET);
}
static int pcnet_check (struct eth_device *dev)
{
outw (88, dev->iobase + PCNET_RAP);
return (inw (dev->iobase + PCNET_RAP) == 88);
}
static int pcnet_init (struct eth_device *dev, bd_t * bis);
static int pcnet_send (struct eth_device *dev, volatile void *packet,
int length);
static int pcnet_recv (struct eth_device *dev);
static void pcnet_halt (struct eth_device *dev);
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
#define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
{}
};
int pcnet_initialize (bd_t * bis)
{
pci_dev_t devbusfn;
struct eth_device *dev;
u16 command, status;
int dev_nr = 0;
PCNET_DEBUG1 ("\npcnet_initialize...\n");
for (dev_nr = 0;; dev_nr++) {
/*
* Find the PCnet PCI device(s).
*/
if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) {
break;
}
/*
* Allocate and pre-fill the device structure.
*/
dev = (struct eth_device *) malloc (sizeof *dev);
if (!dev) {
printf("pcnet: Can not allocate memory\n");
break;
}
memset(dev, 0, sizeof(*dev));
dev->priv = (void *) devbusfn;
sprintf (dev->name, "pcnet#%d", dev_nr);
/*
* Setup the PCI device.
*/
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
(unsigned int *) &dev->iobase);
dev->iobase=pci_io_to_phys (devbusfn, dev->iobase);
dev->iobase &= ~0xf;
PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ",
dev->name, devbusfn, dev->iobase);
command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
pci_write_config_word (devbusfn, PCI_COMMAND, command);
pci_read_config_word (devbusfn, PCI_COMMAND, &status);
if ((status & command) != command) {
printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name);
free (dev);
continue;
}
pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40);
/*
* Probe the PCnet chip.
*/
if (pcnet_probe (dev, bis, dev_nr) < 0) {
free (dev);
continue;
}
/*
* Setup device structure and register the driver.
*/
dev->init = pcnet_init;
dev->halt = pcnet_halt;
dev->send = pcnet_send;
dev->recv = pcnet_recv;
eth_register (dev);
}
udelay (10 * 1000);
return dev_nr;
}
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr)
{
int chip_version;
char *chipname;
#ifdef PCNET_HAS_PROM
int i;
#endif
/* Reset the PCnet controller */
pcnet_reset (dev);
/* Check if register access is working */
if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) {
printf ("%s: CSR register access check failed\n", dev->name);
return -1;
}
/* Identify the chip */
chip_version =
pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16);
if ((chip_version & 0xfff) != 0x003)
return -1;
chip_version = (chip_version >> 12) & 0xffff;
switch (chip_version) {
case 0x2621:
chipname = "PCnet/PCI II 79C970A"; /* PCI */
break;
#ifdef CONFIG_PCNET_79C973
case 0x2625:
chipname = "PCnet/FAST III 79C973"; /* PCI */
break;
#endif
#ifdef CONFIG_PCNET_79C975
case 0x2627:
chipname = "PCnet/FAST III 79C975"; /* PCI */
break;
#endif
default:
printf ("%s: PCnet version %#x not supported\n",
dev->name, chip_version);
return -1;
}
PCNET_DEBUG1 ("AMD %s\n", chipname);
#ifdef PCNET_HAS_PROM
/*
* In most chips, after a chip reset, the ethernet address is read from
* the station address PROM at the base address and programmed into the
* "Physical Address Registers" CSR12-14.
*/
for (i = 0; i < 3; i++) {
unsigned int val;
val = pcnet_read_csr (dev, i + 12) & 0x0ffff;
/* There may be endianness issues here. */
dev->enetaddr[2 * i] = val & 0x0ff;
dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
}
#endif /* PCNET_HAS_PROM */
return 0;
}
static int pcnet_init (struct eth_device *dev, bd_t * bis)
{
int i, val;
u32 addr;
PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name);
/* Switch pcnet to 32bit mode */
pcnet_write_bcr (dev, 20, 2);
#ifdef CONFIG_PN62
/* Setup LED registers */
val = pcnet_read_bcr (dev, 2) | 0x1000;
pcnet_write_bcr (dev, 2, val); /* enable LEDPE */
pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */
pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */
pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */
pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */
#endif
/* Set/reset autoselect bit */
val = pcnet_read_bcr (dev, 2) & ~2;
val |= 2;
pcnet_write_bcr (dev, 2, val);
/* Enable auto negotiate, setup, disable fd */
val = pcnet_read_bcr (dev, 32) & ~0x98;
val |= 0x20;
pcnet_write_bcr (dev, 32, val);
/*
* We only maintain one structure because the drivers will never
* be used concurrently. In 32bit mode the RX and TX ring entries
* must be aligned on 16-byte boundaries.
*/
if (lp == NULL) {
addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10);
addr = (addr + 0xf) & ~0xf;
lp = (pcnet_priv_t *) addr;
}
lp->init_block.mode = cpu_to_le16 (0x0000);
lp->init_block.filter[0] = 0x00000000;
lp->init_block.filter[1] = 0x00000000;
/*
* Initialize the Rx ring.
*/
lp->cur_rx = 0;
for (i = 0; i < RX_RING_SIZE; i++) {
lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]);
lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ);
lp->rx_ring[i].status = cpu_to_le16 (0x8000);
PCNET_DEBUG1
("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
lp->rx_ring[i].status);
}
/*
* Initialize the Tx ring. The Tx buffer address is filled in as
* needed, but we do need to clear the upper ownership bit.
*/
lp->cur_tx = 0;
for (i = 0; i < TX_RING_SIZE; i++) {
lp->tx_ring[i].base = 0;
lp->tx_ring[i].status = 0;
}
/*
* Setup Init Block.
*/
PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block);
for (i = 0; i < 6; i++) {
lp->init_block.phys_addr[i] = dev->enetaddr[i];
PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]);
}
lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS |
RX_RING_LEN_BITS);
lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring);
lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring);
PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
lp->init_block.tlen_rlen,
lp->init_block.rx_ring, lp->init_block.tx_ring);
/*
* Tell the controller where the Init Block is located.
*/
addr = PCI_TO_MEM (dev, &lp->init_block);
pcnet_write_csr (dev, 1, addr & 0xffff);
pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff);
pcnet_write_csr (dev, 4, 0x0915);
pcnet_write_csr (dev, 0, 0x0001); /* start */
/* Wait for Init Done bit */
for (i = 10000; i > 0; i--) {
if (pcnet_read_csr (dev, 0) & 0x0100)
break;
udelay (10);
}
if (i <= 0) {
printf ("%s: TIMEOUT: controller init failed\n", dev->name);
pcnet_reset (dev);
return -1;
}
/*
* Finally start network controller operation.
*/
pcnet_write_csr (dev, 0, 0x0002);
return 0;
}
static int pcnet_send (struct eth_device *dev, volatile void *packet,
int pkt_len)
{
int i, status;
struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
packet);
/* Wait for completion by testing the OWN bit */
for (i = 1000; i > 0; i--) {
status = le16_to_cpu (entry->status);
if ((status & 0x8000) == 0)
break;
udelay (100);
PCNET_DEBUG2 (".");
}
if (i <= 0) {
printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
dev->name, lp->cur_tx, status);
pkt_len = 0;
goto failure;
}
/*
* Setup Tx ring. Caution: the write order is important here,
* set the status with the "ownership" bits last.
*/
status = 0x8300;
entry->length = le16_to_cpu (-pkt_len);
entry->misc = 0x00000000;
entry->base = PCI_TO_MEM_LE (dev, packet);
entry->status = le16_to_cpu (status);
/* Trigger an immediate send poll. */
pcnet_write_csr (dev, 0, 0x0008);
failure:
if (++lp->cur_tx >= TX_RING_SIZE)
lp->cur_tx = 0;
PCNET_DEBUG2 ("done\n");
return pkt_len;
}
static int pcnet_recv (struct eth_device *dev)
{
struct pcnet_rx_head *entry;
int pkt_len = 0;
u16 status;
while (1) {
entry = &lp->rx_ring[lp->cur_rx];
/*
* If we own the next entry, it's a new packet. Send it up.
*/
if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) {
break;
}
status >>= 8;
if (status != 0x03) { /* There was an error. */
printf ("%s: Rx%d", dev->name, lp->cur_rx);
PCNET_DEBUG1 (" (status=0x%x)", status);
if (status & 0x20)
printf (" Frame");
if (status & 0x10)
printf (" Overflow");
if (status & 0x08)
printf (" CRC");
if (status & 0x04)
printf (" Fifo");
printf (" Error\n");
entry->status &= le16_to_cpu (0x03ff);
} else {
pkt_len =
(le32_to_cpu (entry->msg_length) & 0xfff) - 4;
if (pkt_len < 60) {
printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len);
} else {
NetReceive (lp->rx_buf[lp->cur_rx], pkt_len);
PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n",
lp->cur_rx, pkt_len,
lp->rx_buf[lp->cur_rx]);
}
}
entry->status |= cpu_to_le16 (0x8000);
if (++lp->cur_rx >= RX_RING_SIZE)
lp->cur_rx = 0;
}
return pkt_len;
}
static void pcnet_halt (struct eth_device *dev)
{
int i;
PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name);
/* Reset the PCnet controller */
pcnet_reset (dev);
/* Wait for Stop bit */
for (i = 1000; i > 0; i--) {
if (pcnet_read_csr (dev, 0) & 0x4)
break;
udelay (10);
}
if (i <= 0) {
printf ("%s: TIMEOUT: controller reset failed\n", dev->name);
}
}
|
1001-study-uboot
|
drivers/net/pcnet.c
|
C
|
gpl3
| 13,299
|
/*------------------------------------------------------------------------
* lan91c96.c
* This is a driver for SMSC's LAN91C96 single-chip Ethernet device, based
* on the SMC91111 driver from U-boot.
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Rolf Offermanns <rof@sysgo.de>
*
* Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
* Developed by Simple Network Magic Corporation (SNMC)
* Copyright (C) 1996 by Erik Stahlman (ES)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Information contained in this file was obtained from the LAN91C96
* manual from SMC. To get a copy, if you really want one, you can find
* information under www.smsc.com.
*
*
* "Features" of the SMC chip:
* 6144 byte packet memory. ( for the 91C96 )
* EEPROM for configuration
* AUI/TP selection ( mine has 10Base2/10BaseT select )
*
* Arguments:
* io = for the base address
* irq = for the IRQ
*
* author:
* Erik Stahlman ( erik@vt.edu )
* Daris A Nevil ( dnevil@snmc.com )
*
*
* Hardware multicast code from Peter Cammaert ( pc@denkart.be )
*
* Sources:
* o SMSC LAN91C96 databook (www.smsc.com)
* o smc91111.c (u-boot driver)
* o smc9194.c (linux kernel driver)
* o lan91c96.c (Intel Diagnostic Manager driver)
*
* History:
* 04/30/03 Mathijs Haarman Modified smc91111.c (u-boot version)
* for lan91c96
*---------------------------------------------------------------------------
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include "lan91c96.h"
#include <net.h>
#include <linux/compiler.h>
/*------------------------------------------------------------------------
*
* Configuration options, for the experienced user to change.
*
-------------------------------------------------------------------------*/
/* Use power-down feature of the chip */
#define POWER_DOWN 0
/*
* Wait time for memory to be free. This probably shouldn't be
* tuned that much, as waiting for this means nothing else happens
* in the system
*/
#define MEMORY_WAIT_TIME 16
#define SMC_DEBUG 0
#if (SMC_DEBUG > 2 )
#define PRINTK3(args...) printf(args)
#else
#define PRINTK3(args...)
#endif
#if SMC_DEBUG > 1
#define PRINTK2(args...) printf(args)
#else
#define PRINTK2(args...)
#endif
#ifdef SMC_DEBUG
#define PRINTK(args...) printf(args)
#else
#define PRINTK(args...)
#endif
/*------------------------------------------------------------------------
*
* The internal workings of the driver. If you are changing anything
* here with the SMC stuff, you should have the datasheet and know
* what you are doing.
*
*------------------------------------------------------------------------
*/
#define DRIVER_NAME "LAN91C96"
#define SMC_ALLOC_MAX_TRY 5
#define SMC_TX_TIMEOUT 30
#define ETH_ZLEN 60
#ifdef CONFIG_LAN91C96_USE_32_BIT
#define USE_32_BIT 1
#else
#undef USE_32_BIT
#endif
/* See if a MAC address is defined in the current environment. If so use it. If not
. print a warning and set the environment and other globals with the default.
. If an EEPROM is present it really should be consulted.
*/
static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev);
static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac);
/* ------------------------------------------------------------
* Internal routines
* ------------------------------------------------------------
*/
static unsigned char smc_mac_addr[] = { 0xc0, 0x00, 0x00, 0x1b, 0x62, 0x9c };
/*
* This function must be called before smc_open() if you want to override
* the default mac address.
*/
static void smc_set_mac_addr(const unsigned char *addr)
{
int i;
for (i = 0; i < sizeof (smc_mac_addr); i++) {
smc_mac_addr[i] = addr[i];
}
}
/***********************************************
* Show available memory *
***********************************************/
void dump_memory_info(struct eth_device *dev)
{
__maybe_unused word mem_info;
word old_bank;
old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT) & 0xF;
SMC_SELECT_BANK(dev, 0);
mem_info = SMC_inw(dev, LAN91C96_MIR);
PRINTK2 ("Memory: %4d available\n", (mem_info >> 8) * 2048);
SMC_SELECT_BANK(dev, old_bank);
}
/*
* A rather simple routine to print out a packet for debugging purposes.
*/
#if SMC_DEBUG > 2
static void print_packet (byte *, int);
#endif
static int poll4int (struct eth_device *dev, byte mask, int timeout)
{
int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
int is_timeout = 0;
word old_bank = SMC_inw(dev, LAN91C96_BANK_SELECT);
PRINTK2 ("Polling...\n");
SMC_SELECT_BANK(dev, 2);
while ((SMC_inw(dev, LAN91C96_INT_STATS) & mask) == 0) {
if (get_timer (0) >= tmo) {
is_timeout = 1;
break;
}
}
/* restore old bank selection */
SMC_SELECT_BANK(dev, old_bank);
if (is_timeout)
return 1;
else
return 0;
}
/*
* Function: smc_reset
* Purpose:
* This sets the SMC91111 chip to its normal state, hopefully from whatever
* mess that any other DOS driver has put it in.
*
* Maybe I should reset more registers to defaults in here? SOFTRST should
* do that for me.
*
* Method:
* 1. send a SOFT RESET
* 2. wait for it to finish
* 3. enable autorelease mode
* 4. reset the memory management unit
* 5. clear all interrupts
*
*/
static void smc_reset(struct eth_device *dev)
{
PRINTK2("%s:smc_reset\n", dev->name);
/* This resets the registers mostly to defaults, but doesn't
affect EEPROM. That seems unnecessary */
SMC_SELECT_BANK(dev, 0);
SMC_outw(dev, LAN91C96_RCR_SOFT_RST, LAN91C96_RCR);
udelay (10);
/* Disable transmit and receive functionality */
SMC_outw(dev, 0, LAN91C96_RCR);
SMC_outw(dev, 0, LAN91C96_TCR);
/* set the control register */
SMC_SELECT_BANK(dev, 1);
SMC_outw(dev, SMC_inw(dev, LAN91C96_CONTROL) | LAN91C96_CTR_BIT_8,
LAN91C96_CONTROL);
/* Disable all interrupts */
SMC_outb(dev, 0, LAN91C96_INT_MASK);
}
/*
* Function: smc_enable
* Purpose: let the chip talk to the outside work
* Method:
* 1. Initialize the Memory Configuration Register
* 2. Enable the transmitter
* 3. Enable the receiver
*/
static void smc_enable(struct eth_device *dev)
{
PRINTK2("%s:smc_enable\n", dev->name);
SMC_SELECT_BANK(dev, 0);
/* Initialize the Memory Configuration Register. See page
49 of the LAN91C96 data sheet for details. */
SMC_outw(dev, LAN91C96_MCR_TRANSMIT_PAGES, LAN91C96_MCR);
/* Initialize the Transmit Control Register */
SMC_outw(dev, LAN91C96_TCR_TXENA, LAN91C96_TCR);
/* Initialize the Receive Control Register
* FIXME:
* The promiscuous bit set because I could not receive ARP reply
* packets from the server when I send a ARP request. It only works
* when I set the promiscuous bit
*/
SMC_outw(dev, LAN91C96_RCR_RXEN | LAN91C96_RCR_PRMS, LAN91C96_RCR);
}
/*
* Function: smc_shutdown
* Purpose: closes down the SMC91xxx chip.
* Method:
* 1. zero the interrupt mask
* 2. clear the enable receive flag
* 3. clear the enable xmit flags
*
* TODO:
* (1) maybe utilize power down mode.
* Why not yet? Because while the chip will go into power down mode,
* the manual says that it will wake up in response to any I/O requests
* in the register space. Empirical results do not show this working.
*/
static void smc_shutdown(struct eth_device *dev)
{
PRINTK2("%s:smc_shutdown\n", dev->name);
/* no more interrupts for me */
SMC_SELECT_BANK(dev, 2);
SMC_outb(dev, 0, LAN91C96_INT_MASK);
/* and tell the card to stay away from that nasty outside world */
SMC_SELECT_BANK(dev, 0);
SMC_outb(dev, 0, LAN91C96_RCR);
SMC_outb(dev, 0, LAN91C96_TCR);
}
/*
* Function: smc_hardware_send_packet(struct net_device * )
* Purpose:
* This sends the actual packet to the SMC9xxx chip.
*
* Algorithm:
* First, see if a saved_skb is available.
* ( this should NOT be called if there is no 'saved_skb'
* Now, find the packet number that the chip allocated
* Point the data pointers at it in memory
* Set the length word in the chip's memory
* Dump the packet to chip memory
* Check if a last byte is needed ( odd length packet )
* if so, set the control flag right
* Tell the card to send it
* Enable the transmit interrupt, so I know if it failed
* Free the kernel data if I actually sent it.
*/
static int smc_send_packet(struct eth_device *dev, volatile void *packet,
int packet_length)
{
byte packet_no;
byte *buf;
int length;
int numPages;
int try = 0;
int time_out;
byte status;
PRINTK3("%s:smc_hardware_send_packet\n", dev->name);
length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
/* allocate memory
** The MMU wants the number of pages to be the number of 256 bytes
** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
**
** The 91C111 ignores the size bits, but the code is left intact
** for backwards and future compatibility.
**
** Pkt size for allocating is data length +6 (for additional status
** words, length and ctl!)
**
** If odd size then last byte is included in this header.
*/
numPages = ((length & 0xfffe) + 6);
numPages >>= 8; /* Divide by 256 */
if (numPages > 7) {
printf("%s: Far too big packet error. \n", dev->name);
return 0;
}
/* now, try to allocate the memory */
SMC_SELECT_BANK(dev, 2);
SMC_outw(dev, LAN91C96_MMUCR_ALLOC_TX | numPages, LAN91C96_MMU);
again:
try++;
time_out = MEMORY_WAIT_TIME;
do {
status = SMC_inb(dev, LAN91C96_INT_STATS);
if (status & LAN91C96_IST_ALLOC_INT) {
SMC_outb(dev, LAN91C96_IST_ALLOC_INT,
LAN91C96_INT_STATS);
break;
}
} while (--time_out);
if (!time_out) {
PRINTK2 ("%s: memory allocation, try %d failed ...\n",
dev->name, try);
if (try < SMC_ALLOC_MAX_TRY)
goto again;
else
return 0;
}
PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
dev->name, try);
/* I can send the packet now.. */
buf = (byte *) packet;
/* If I get here, I _know_ there is a packet slot waiting for me */
packet_no = SMC_inb(dev, LAN91C96_ARR);
if (packet_no & LAN91C96_ARR_FAILED) {
/* or isn't there? BAD CHIP! */
printf("%s: Memory allocation failed. \n", dev->name);
return 0;
}
/* we have a packet address, so tell the card to use it */
SMC_outb(dev, packet_no, LAN91C96_PNR);
/* point to the beginning of the packet */
SMC_outw(dev, LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
PRINTK3("%s: Trying to xmit packet of length %x\n",
dev->name, length);
#if SMC_DEBUG > 2
printf ("Transmitting Packet\n");
print_packet (buf, length);
#endif
/* send the packet length ( +6 for status, length and ctl byte )
and the status word ( set to zeros ) */
#ifdef USE_32_BIT
SMC_outl(dev, (length + 6) << 16, LAN91C96_DATA_HIGH);
#else
SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
/* send the packet length ( +6 for status words, length, and ctl */
SMC_outw(dev, (length + 6), LAN91C96_DATA_HIGH);
#endif /* USE_32_BIT */
/* send the actual data
* I _think_ it's faster to send the longs first, and then
* mop up by sending the last word. It depends heavily
* on alignment, at least on the 486. Maybe it would be
* a good idea to check which is optimal? But that could take
* almost as much time as is saved?
*/
#ifdef USE_32_BIT
SMC_outsl(dev, LAN91C96_DATA_HIGH, buf, length >> 2);
if (length & 0x2)
SMC_outw(dev, *((word *) (buf + (length & 0xFFFFFFFC))),
LAN91C96_DATA_HIGH);
#else
SMC_outsw(dev, LAN91C96_DATA_HIGH, buf, (length) >> 1);
#endif /* USE_32_BIT */
/* Send the last byte, if there is one. */
if ((length & 1) == 0) {
SMC_outw(dev, 0, LAN91C96_DATA_HIGH);
} else {
SMC_outw(dev, buf[length - 1] | 0x2000, LAN91C96_DATA_HIGH);
}
/* and let the chipset deal with it */
SMC_outw(dev, LAN91C96_MMUCR_ENQUEUE, LAN91C96_MMU);
/* poll for TX INT */
if (poll4int (dev, LAN91C96_MSK_TX_INT, SMC_TX_TIMEOUT)) {
/* sending failed */
PRINTK2("%s: TX timeout, sending failed...\n", dev->name);
/* release packet */
SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
/* wait for MMU getting ready (low) */
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
udelay (10);
PRINTK2("MMU ready\n");
return 0;
} else {
/* ack. int */
SMC_outw(dev, LAN91C96_IST_TX_INT, LAN91C96_INT_STATS);
PRINTK2("%s: Sent packet of length %d \n", dev->name, length);
/* release packet */
SMC_outw(dev, LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
/* wait for MMU getting ready (low) */
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
udelay (10);
PRINTK2 ("MMU ready\n");
}
return length;
}
/*
* Open and Initialize the board
*
* Set up everything, reset the card, etc ..
*
*/
static int smc_open(bd_t *bd, struct eth_device *dev)
{
int i, err; /* used to set hw ethernet address */
PRINTK2("%s:smc_open\n", dev->name);
/* reset the hardware */
smc_reset(dev);
smc_enable(dev);
SMC_SELECT_BANK(dev, 1);
/* set smc_mac_addr, and sync it with u-boot globals */
err = smc_get_ethaddr(bd, dev);
if (err < 0)
return -1;
#ifdef USE_32_BIT
for (i = 0; i < 6; i += 2) {
word address;
address = smc_mac_addr[i + 1] << 8;
address |= smc_mac_addr[i];
SMC_outw(dev, address, LAN91C96_IA0 + i);
}
#else
for (i = 0; i < 6; i++)
SMC_outb(dev, smc_mac_addr[i], LAN91C96_IA0 + i);
#endif
return 0;
}
/*-------------------------------------------------------------
*
* smc_rcv - receive a packet from the card
*
* There is ( at least ) a packet waiting to be read from
* chip-memory.
*
* o Read the status
* o If an error, record it
* o otherwise, read in the packet
*-------------------------------------------------------------
*/
static int smc_rcv(struct eth_device *dev)
{
int packet_number;
word status;
word packet_length;
int is_error = 0;
#ifdef USE_32_BIT
dword stat_len;
#endif
SMC_SELECT_BANK(dev, 2);
packet_number = SMC_inw(dev, LAN91C96_FIFO);
if (packet_number & LAN91C96_FIFO_RXEMPTY) {
return 0;
}
PRINTK3("%s:smc_rcv\n", dev->name);
/* start reading from the start of the packet */
SMC_outw(dev, LAN91C96_PTR_READ | LAN91C96_PTR_RCV |
LAN91C96_PTR_AUTO_INCR, LAN91C96_POINTER);
/* First two words are status and packet_length */
#ifdef USE_32_BIT
stat_len = SMC_inl(dev, LAN91C96_DATA_HIGH);
status = stat_len & 0xffff;
packet_length = stat_len >> 16;
#else
status = SMC_inw(dev, LAN91C96_DATA_HIGH);
packet_length = SMC_inw(dev, LAN91C96_DATA_HIGH);
#endif
packet_length &= 0x07ff; /* mask off top bits */
PRINTK2 ("RCV: STATUS %4x LENGTH %4x\n", status, packet_length);
if (!(status & FRAME_FILTER)) {
/* Adjust for having already read the first two words */
packet_length -= 4; /*4; */
/* set odd length for bug in LAN91C111, */
/* which never sets RS_ODDFRAME */
/* TODO ? */
#ifdef USE_32_BIT
PRINTK3 (" Reading %d dwords (and %d bytes) \n",
packet_length >> 2, packet_length & 3);
/* QUESTION: Like in the TX routine, do I want
to send the DWORDs or the bytes first, or some
mixture. A mixture might improve already slow PIO
performance */
SMC_insl(dev, LAN91C96_DATA_HIGH, NetRxPackets[0],
packet_length >> 2);
/* read the left over bytes */
if (packet_length & 3) {
int i;
byte *tail = (byte *) (NetRxPackets[0] + (packet_length & ~3));
dword leftover = SMC_inl(dev, LAN91C96_DATA_HIGH);
for (i = 0; i < (packet_length & 3); i++)
*tail++ = (byte) (leftover >> (8 * i)) & 0xff;
}
#else
PRINTK3 (" Reading %d words and %d byte(s) \n",
(packet_length >> 1), packet_length & 1);
SMC_insw(dev, LAN91C96_DATA_HIGH, NetRxPackets[0],
packet_length >> 1);
#endif /* USE_32_BIT */
#if SMC_DEBUG > 2
printf ("Receiving Packet\n");
print_packet((byte *)NetRxPackets[0], packet_length);
#endif
} else {
/* error ... */
/* TODO ? */
is_error = 1;
}
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
udelay (1); /* Wait until not busy */
/* error or good, tell the card to get rid of this packet */
SMC_outw(dev, LAN91C96_MMUCR_RELEASE_RX, LAN91C96_MMU);
while (SMC_inw(dev, LAN91C96_MMU) & LAN91C96_MMUCR_NO_BUSY)
udelay (1); /* Wait until not busy */
if (!is_error) {
/* Pass the packet up to the protocol layers. */
NetReceive (NetRxPackets[0], packet_length);
return packet_length;
} else {
return 0;
}
}
/*----------------------------------------------------
* smc_close
*
* this makes the board clean up everything that it can
* and not talk to the outside world. Caused by
* an 'ifconfig ethX down'
*
-----------------------------------------------------*/
static int smc_close(struct eth_device *dev)
{
PRINTK2("%s:smc_close\n", dev->name);
/* clear everything */
smc_shutdown(dev);
return 0;
}
#if SMC_DEBUG > 2
static void print_packet(byte *buf, int length)
{
#if 0
int i;
int remainder;
int lines;
printf ("Packet of length %d \n", length);
lines = length / 16;
remainder = length % 16;
for (i = 0; i < lines; i++) {
int cur;
for (cur = 0; cur < 8; cur++) {
byte a, b;
a = *(buf++);
b = *(buf++);
printf ("%02x%02x ", a, b);
}
printf ("\n");
}
for (i = 0; i < remainder / 2; i++) {
byte a, b;
a = *(buf++);
b = *(buf++);
printf ("%02x%02x ", a, b);
}
printf ("\n");
#endif /* 0 */
}
#endif /* SMC_DEBUG > 2 */
static int lan91c96_init(struct eth_device *dev, bd_t *bd)
{
return smc_open(bd, dev);
}
static void lan91c96_halt(struct eth_device *dev)
{
smc_close(dev);
}
static int lan91c96_recv(struct eth_device *dev)
{
return smc_rcv(dev);
}
static int lan91c96_send(struct eth_device *dev, volatile void *packet,
int length)
{
return smc_send_packet(dev, packet, length);
}
/* smc_get_ethaddr
*
* This checks both the environment and the ROM for an ethernet address. If
* found, the environment takes precedence.
*/
static int smc_get_ethaddr(bd_t *bd, struct eth_device *dev)
{
uchar v_mac[6];
if (!eth_getenv_enetaddr("ethaddr", v_mac)) {
/* get ROM mac value if any */
if (!get_rom_mac(dev, v_mac)) {
printf("\n*** ERROR: ethaddr is NOT set !!\n");
return -1;
}
eth_setenv_enetaddr("ethaddr", v_mac);
}
smc_set_mac_addr(v_mac); /* use old function to update smc default */
PRINTK("Using MAC Address %pM\n", v_mac);
return 0;
}
/*
* get_rom_mac()
* Note, this has omly been tested for the OMAP730 P2.
*/
static int get_rom_mac(struct eth_device *dev, unsigned char *v_rom_mac)
{
#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
memcpy (v_rom_mac, hw_mac_addr, 6);
return (1);
#else
int i;
SMC_SELECT_BANK(dev, 1);
for (i=0; i<6; i++)
{
v_rom_mac[i] = SMC_inb(dev, LAN91C96_IA0 + i);
}
return (1);
#endif
}
/* Structure to detect the device IDs */
struct id_type {
u8 id;
char *name;
};
static struct id_type supported_chips[] = {
{0, ""}, /* Dummy entry to prevent id check failure */
{9, "LAN91C110"},
{8, "LAN91C100FD"},
{7, "LAN91C100"},
{5, "LAN91C95"},
{4, "LAN91C94/96"},
{3, "LAN91C90/92"},
};
/* lan91c96_detect_chip
* See:
* http://www.embeddedsys.com/subpages/resources/images/documents/LAN91C96_datasheet.pdf
* page 71 - that is the closest we get to detect this device
*/
static int lan91c96_detect_chip(struct eth_device *dev)
{
u8 chip_id;
int r;
SMC_SELECT_BANK(dev, 3);
chip_id = (SMC_inw(dev, 0xA) & LAN91C96_REV_CHIPID) >> 4;
SMC_SELECT_BANK(dev, 0);
for (r = 0; r < sizeof(supported_chips) / sizeof(struct id_type); r++)
if (chip_id == supported_chips[r].id)
return r;
return 0;
}
int lan91c96_initialize(u8 dev_num, int base_addr)
{
struct eth_device *dev;
int r = 0;
dev = malloc(sizeof(*dev));
if (!dev) {
return 0;
}
memset(dev, 0, sizeof(*dev));
dev->iobase = base_addr;
/* Try to detect chip. Will fail if not present. */
r = lan91c96_detect_chip(dev);
if (!r) {
free(dev);
return 0;
}
get_rom_mac(dev, dev->enetaddr);
dev->init = lan91c96_init;
dev->halt = lan91c96_halt;
dev->send = lan91c96_send;
dev->recv = lan91c96_recv;
sprintf(dev->name, "%s-%hu", supported_chips[r].name, dev_num);
eth_register(dev);
return 0;
}
|
1001-study-uboot
|
drivers/net/lan91c96.c
|
C
|
gpl3
| 20,805
|
/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <pci.h>
#undef DEBUG_SROM
#undef DEBUG_SROM2
#undef UPDATE_SROM
/* PCI Registers.
*/
#define PCI_CFDA_PSM 0x43
#define CFRV_RN 0x000000f0 /* Revision Number */
#define WAKEUP 0x00 /* Power Saving Wakeup */
#define SLEEP 0x80 /* Power Saving Sleep Mode */
#define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
/* Ethernet chip registers.
*/
#define DE4X5_BMR 0x000 /* Bus Mode Register */
#define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
#define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
#define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
#define DE4X5_STS 0x028 /* Status Register */
#define DE4X5_OMR 0x030 /* Operation Mode Register */
#define DE4X5_SICR 0x068 /* SIA Connectivity Register */
#define DE4X5_APROM 0x048 /* Ethernet Address PROM */
/* Register bits.
*/
#define BMR_SWR 0x00000001 /* Software Reset */
#define STS_TS 0x00700000 /* Transmit Process State */
#define STS_RS 0x000e0000 /* Receive Process State */
#define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
#define OMR_SR 0x00000002 /* Start/Stop Receive */
#define OMR_PS 0x00040000 /* Port Select */
#define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
#define OMR_PM 0x00000080 /* Pass All Multicast */
/* Descriptor bits.
*/
#define R_OWN 0x80000000 /* Own Bit */
#define RD_RER 0x02000000 /* Receive End Of Ring */
#define RD_LS 0x00000100 /* Last Descriptor */
#define RD_ES 0x00008000 /* Error Summary */
#define TD_TER 0x02000000 /* Transmit End Of Ring */
#define T_OWN 0x80000000 /* Own Bit */
#define TD_LS 0x40000000 /* Last Segment */
#define TD_FS 0x20000000 /* First Segment */
#define TD_ES 0x00008000 /* Error Summary */
#define TD_SET 0x08000000 /* Setup Packet */
/* The EEPROM commands include the alway-set leading bit. */
#define SROM_WRITE_CMD 5
#define SROM_READ_CMD 6
#define SROM_ERASE_CMD 7
#define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
#define SROM_RD 0x00004000 /* Read from Boot ROM */
#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
#define EE_WRITE_0 0x4801
#define EE_WRITE_1 0x4805
#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
#define SROM_SR 0x00000800 /* Select Serial ROM when set */
#define DT_IN 0x00000004 /* Serial Data In */
#define DT_CLK 0x00000002 /* Serial ROM Clock */
#define DT_CS 0x00000001 /* Serial ROM Chip Select */
#define POLL_DEMAND 1
#ifdef CONFIG_TULIP_FIX_DAVICOM
#define RESET_DM9102(dev) {\
unsigned long i;\
i=INL(dev, 0x0);\
udelay(1000);\
OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
udelay(1000);\
}
#else
#define RESET_DE4X5(dev) {\
int i;\
i=INL(dev, DE4X5_BMR);\
udelay(1000);\
OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
udelay(1000);\
OUTL(dev, i, DE4X5_BMR);\
udelay(1000);\
for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
udelay(1000);\
}
#endif
#define START_DE4X5(dev) {\
s32 omr; \
omr = INL(dev, DE4X5_OMR);\
omr |= OMR_ST | OMR_SR;\
OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
}
#define STOP_DE4X5(dev) {\
s32 omr; \
omr = INL(dev, DE4X5_OMR);\
omr &= ~(OMR_ST|OMR_SR);\
OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
}
#define NUM_RX_DESC PKTBUFSRX
#ifndef CONFIG_TULIP_FIX_DAVICOM
#define NUM_TX_DESC 1 /* Number of TX descriptors */
#else
#define NUM_TX_DESC 4
#endif
#define RX_BUFF_SZ PKTSIZE_ALIGN
#define TOUT_LOOP 1000000
#define SETUP_FRAME_LEN 192
#define ETH_ALEN 6
struct de4x5_desc {
volatile s32 status;
u32 des1;
u32 buf;
u32 next;
};
static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
static int rx_new; /* RX descriptor ring pointer */
static int tx_new; /* TX descriptor ring pointer */
static char rxRingSize;
static char txRingSize;
#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
static int getfrom_srom(struct eth_device* dev, u_long addr);
static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
#ifdef UPDATE_SROM
static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
static void update_srom(struct eth_device *dev, bd_t *bis);
#endif
#ifndef CONFIG_TULIP_FIX_DAVICOM
static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
static void read_hw_addr(struct eth_device* dev, bd_t * bis);
#endif /* CONFIG_TULIP_FIX_DAVICOM */
static void send_setup_frame(struct eth_device* dev, bd_t * bis);
static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length);
static int dc21x4x_recv(struct eth_device* dev);
static void dc21x4x_halt(struct eth_device* dev);
#ifdef CONFIG_TULIP_SELECT_MEDIA
extern void dc21x4x_select_media(struct eth_device* dev);
#endif
#if defined(CONFIG_E500)
#define phys_to_bus(a) (a)
#else
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
#endif
static int INL(struct eth_device* dev, u_long addr)
{
return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
}
static void OUTL(struct eth_device* dev, int command, u_long addr)
{
*(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
}
static struct pci_device_id supported[] = {
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
#ifdef CONFIG_TULIP_FIX_DAVICOM
{ PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
#endif
{ }
};
int dc21x4x_initialize(bd_t *bis)
{
int idx=0;
int card_number = 0;
unsigned int cfrv;
unsigned char timer;
pci_dev_t devbusfn;
unsigned int iobase;
unsigned short status;
struct eth_device* dev;
while(1) {
devbusfn = pci_find_devices(supported, idx++);
if (devbusfn == -1) {
break;
}
/* Get the chip configuration revision register. */
pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
#ifndef CONFIG_TULIP_FIX_DAVICOM
if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
printf("Error: The chip is not DC21143.\n");
continue;
}
#endif
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
status |=
#ifdef CONFIG_TULIP_USE_IO
PCI_COMMAND_IO |
#else
PCI_COMMAND_MEMORY |
#endif
PCI_COMMAND_MASTER;
pci_write_config_word(devbusfn, PCI_COMMAND, status);
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
#ifdef CONFIG_TULIP_USE_IO
if (!(status & PCI_COMMAND_IO)) {
printf("Error: Can not enable I/O access.\n");
continue;
}
#else
if (!(status & PCI_COMMAND_MEMORY)) {
printf("Error: Can not enable MEMORY access.\n");
continue;
}
#endif
if (!(status & PCI_COMMAND_MASTER)) {
printf("Error: Can not enable Bus Mastering.\n");
continue;
}
/* Check the latency timer for values >= 0x60. */
pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
if (timer < 0x60) {
pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
}
#ifdef CONFIG_TULIP_USE_IO
/* read BAR for memory space access */
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
iobase &= PCI_BASE_ADDRESS_IO_MASK;
#else
/* read BAR for memory space access */
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
#endif
debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
dev = (struct eth_device*) malloc(sizeof *dev);
if (!dev) {
printf("Can not allocalte memory of dc21x4x\n");
break;
}
memset(dev, 0, sizeof(*dev));
#ifdef CONFIG_TULIP_FIX_DAVICOM
sprintf(dev->name, "Davicom#%d", card_number);
#else
sprintf(dev->name, "dc21x4x#%d", card_number);
#endif
#ifdef CONFIG_TULIP_USE_IO
dev->iobase = pci_io_to_phys(devbusfn, iobase);
#else
dev->iobase = pci_mem_to_phys(devbusfn, iobase);
#endif
dev->priv = (void*) devbusfn;
dev->init = dc21x4x_init;
dev->halt = dc21x4x_halt;
dev->send = dc21x4x_send;
dev->recv = dc21x4x_recv;
/* Ensure we're not sleeping. */
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
udelay(10 * 1000);
#ifndef CONFIG_TULIP_FIX_DAVICOM
read_hw_addr(dev, bis);
#endif
eth_register(dev);
card_number++;
}
return card_number;
}
static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
{
int i;
int devbusfn = (int) dev->priv;
/* Ensure we're not sleeping. */
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
#ifdef CONFIG_TULIP_FIX_DAVICOM
RESET_DM9102(dev);
#else
RESET_DE4X5(dev);
#endif
if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
printf("Error: Cannot reset ethernet controller.\n");
return -1;
}
#ifdef CONFIG_TULIP_SELECT_MEDIA
dc21x4x_select_media(dev);
#else
OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
#endif
for (i = 0; i < NUM_RX_DESC; i++) {
rx_ring[i].status = cpu_to_le32(R_OWN);
rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i]));
#ifdef CONFIG_TULIP_FIX_DAVICOM
rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
#else
rx_ring[i].next = 0;
#endif
}
for (i=0; i < NUM_TX_DESC; i++) {
tx_ring[i].status = 0;
tx_ring[i].des1 = 0;
tx_ring[i].buf = 0;
#ifdef CONFIG_TULIP_FIX_DAVICOM
tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
#else
tx_ring[i].next = 0;
#endif
}
rxRingSize = NUM_RX_DESC;
txRingSize = NUM_TX_DESC;
/* Write the end of list marker to the descriptor lists. */
rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
/* Tell the adapter where the TX/RX rings are located. */
OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
START_DE4X5(dev);
tx_new = 0;
rx_new = 0;
send_setup_frame(dev, bis);
return 0;
}
static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length)
{
int status = -1;
int i;
if (length <= 0) {
printf("%s: bad packet size: %d\n", dev->name, length);
goto Done;
}
for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
if (i >= TOUT_LOOP) {
printf("%s: tx error buffer not ready\n", dev->name);
goto Done;
}
}
tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet));
tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
tx_ring[tx_new].status = cpu_to_le32(T_OWN);
OUTL(dev, POLL_DEMAND, DE4X5_TPD);
for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
if (i >= TOUT_LOOP) {
printf(".%s: tx buffer not ready\n", dev->name);
goto Done;
}
}
if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
#if 0 /* test-only */
printf("TX error status = 0x%08X\n",
le32_to_cpu(tx_ring[tx_new].status));
#endif
tx_ring[tx_new].status = 0x0;
goto Done;
}
status = length;
Done:
tx_new = (tx_new+1) % NUM_TX_DESC;
return status;
}
static int dc21x4x_recv(struct eth_device* dev)
{
s32 status;
int length = 0;
for ( ; ; ) {
status = (s32)le32_to_cpu(rx_ring[rx_new].status);
if (status & R_OWN) {
break;
}
if (status & RD_LS) {
/* Valid frame status.
*/
if (status & RD_ES) {
/* There was an error.
*/
printf("RX error status = 0x%08X\n", status);
} else {
/* A valid frame received.
*/
length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
/* Pass the packet up to the protocol
* layers.
*/
NetReceive(NetRxPackets[rx_new], length - 4);
}
/* Change buffer ownership for this frame, back
* to the adapter.
*/
rx_ring[rx_new].status = cpu_to_le32(R_OWN);
}
/* Update entry information.
*/
rx_new = (rx_new + 1) % rxRingSize;
}
return length;
}
static void dc21x4x_halt(struct eth_device* dev)
{
int devbusfn = (int) dev->priv;
STOP_DE4X5(dev);
OUTL(dev, 0, DE4X5_SICR);
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
}
static void send_setup_frame(struct eth_device* dev, bd_t *bis)
{
int i;
char setup_frame[SETUP_FRAME_LEN];
char *pa = &setup_frame[0];
memset(pa, 0xff, SETUP_FRAME_LEN);
for (i = 0; i < ETH_ALEN; i++) {
*(pa + (i & 1)) = dev->enetaddr[i];
if (i & 0x01) {
pa += 4;
}
}
for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
if (i >= TOUT_LOOP) {
printf("%s: tx error buffer not ready\n", dev->name);
goto Done;
}
}
tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
tx_ring[tx_new].status = cpu_to_le32(T_OWN);
OUTL(dev, POLL_DEMAND, DE4X5_TPD);
for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
if (i >= TOUT_LOOP) {
printf("%s: tx buffer not ready\n", dev->name);
goto Done;
}
}
if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
}
tx_new = (tx_new+1) % NUM_TX_DESC;
Done:
return;
}
#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
/* SROM Read and write routines.
*/
static void
sendto_srom(struct eth_device* dev, u_int command, u_long addr)
{
OUTL(dev, command, addr);
udelay(1);
}
static int
getfrom_srom(struct eth_device* dev, u_long addr)
{
s32 tmp;
tmp = INL(dev, addr);
udelay(1);
return tmp;
}
/* Note: this routine returns extra data bits for size detection. */
static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
{
int i;
unsigned retval = 0;
int read_cmd = location | (SROM_READ_CMD << addr_len);
sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
#ifdef DEBUG_SROM
printf(" EEPROM read at %d ", location);
#endif
/* Shift the read command bits out. */
for (i = 4 + addr_len; i >= 0; i--) {
short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
udelay(10);
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
udelay(10);
#ifdef DEBUG_SROM2
printf("%X", getfrom_srom(dev, ioaddr) & 15);
#endif
retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
}
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
#ifdef DEBUG_SROM2
printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
#endif
for (i = 16; i > 0; i--) {
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
udelay(10);
#ifdef DEBUG_SROM2
printf("%X", getfrom_srom(dev, ioaddr) & 15);
#endif
retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
udelay(10);
}
/* Terminate the EEPROM access. */
sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
#ifdef DEBUG_SROM2
printf(" EEPROM value at %d is %5.5x.\n", location, retval);
#endif
return retval;
}
#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
/* This executes a generic EEPROM command, typically a write or write
* enable. It returns the data output from the EEPROM, and thus may
* also be used for reads.
*/
#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
{
unsigned retval = 0;
#ifdef DEBUG_SROM
printf(" EEPROM op 0x%x: ", cmd);
#endif
sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
/* Shift the command bits out. */
do {
short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
sendto_srom(dev,dataval, ioaddr);
udelay(10);
#ifdef DEBUG_SROM2
printf("%X", getfrom_srom(dev,ioaddr) & 15);
#endif
sendto_srom(dev,dataval | DT_CLK, ioaddr);
udelay(10);
retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
} while (--cmd_len >= 0);
sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
/* Terminate the EEPROM access. */
sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
#ifdef DEBUG_SROM
printf(" EEPROM result is 0x%5.5x.\n", retval);
#endif
return retval;
}
#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
#ifndef CONFIG_TULIP_FIX_DAVICOM
static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
{
int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
return do_eeprom_cmd(dev, ioaddr,
(((SROM_READ_CMD << ee_addr_size) | index) << 16)
| 0xffff, 3 + ee_addr_size + 16);
}
#endif /* CONFIG_TULIP_FIX_DAVICOM */
#ifdef UPDATE_SROM
static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
{
int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
int i;
unsigned short newval;
udelay(10*1000); /* test-only */
#ifdef DEBUG_SROM
printf("ee_addr_size=%d.\n", ee_addr_size);
printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
#endif
/* Enable programming modes. */
do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
/* Do the actual write. */
do_eeprom_cmd(dev, ioaddr,
(((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
3 + ee_addr_size + 16);
/* Poll for write finished. */
sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
break;
#ifdef DEBUG_SROM
printf(" Write finished after %d ticks.\n", i);
#endif
/* Disable programming. */
do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
/* And read the result. */
newval = do_eeprom_cmd(dev, ioaddr,
(((SROM_READ_CMD<<ee_addr_size)|index) << 16)
| 0xffff, 3 + ee_addr_size + 16);
#ifdef DEBUG_SROM
printf(" New value at offset %d is %4.4x.\n", index, newval);
#endif
return 1;
}
#endif
#ifndef CONFIG_TULIP_FIX_DAVICOM
static void read_hw_addr(struct eth_device *dev, bd_t *bis)
{
u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
int i, j = 0;
for (i = 0; i < (ETH_ALEN >> 1); i++) {
tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
*p = le16_to_cpu(tmp);
j += *p++;
}
if ((j == 0) || (j == 0x2fffd)) {
memset (dev->enetaddr, 0, ETH_ALEN);
debug ("Warning: can't read HW address from SROM.\n");
goto Done;
}
return;
Done:
#ifdef UPDATE_SROM
update_srom(dev, bis);
#endif
return;
}
#endif /* CONFIG_TULIP_FIX_DAVICOM */
#ifdef UPDATE_SROM
static void update_srom(struct eth_device *dev, bd_t *bis)
{
int i;
static unsigned short eeprom[0x40] = {
0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
};
uchar enetaddr[6];
/* Ethernet Addr... */
if (!eth_getenv_enetaddr("ethaddr", enetaddr))
return;
eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
for (i=0; i<0x40; i++) {
write_srom(dev, DE4X5_APROM, i, eeprom[i]);
}
}
#endif /* UPDATE_SROM */
|
1001-study-uboot
|
drivers/net/dc2114x.c
|
C
|
gpl3
| 20,713
|
/*
* Cirrus Logic EP93xx ethernet MAC / MII driver.
*
* Copyright (C) 2010, 2009
* Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
*
* Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
* which is
*
* (C) Copyright 2002 2003
* Adam Bezanson, Network Audio Technologies, Inc.
* <bezanson@netaudiotech.com>
*
* See file CREDITS for list of people who contributed to this project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <command.h>
#include <common.h>
#include <asm/arch/ep93xx.h>
#include <asm/io.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/types.h>
#include "ep93xx_eth.h"
#define GET_PRIV(eth_dev) ((struct ep93xx_priv *)(eth_dev)->priv)
#define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs)
/* ep93xx_miiphy ops forward declarations */
static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr,
unsigned char const reg, unsigned short * const value);
static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr,
unsigned char const reg, unsigned short const value);
#if defined(EP93XX_MAC_DEBUG)
/**
* Dump ep93xx_mac values to the terminal.
*/
static void dump_dev(struct eth_device *dev)
{
struct ep93xx_priv *priv = GET_PRIV(dev);
int i;
printf("\ndump_dev()\n");
printf(" rx_dq.base %p\n", priv->rx_dq.base);
printf(" rx_dq.current %p\n", priv->rx_dq.current);
printf(" rx_dq.end %p\n", priv->rx_dq.end);
printf(" rx_sq.base %p\n", priv->rx_sq.base);
printf(" rx_sq.current %p\n", priv->rx_sq.current);
printf(" rx_sq.end %p\n", priv->rx_sq.end);
for (i = 0; i < NUMRXDESC; i++)
printf(" rx_buffer[%2.d] %p\n", i, NetRxPackets[i]);
printf(" tx_dq.base %p\n", priv->tx_dq.base);
printf(" tx_dq.current %p\n", priv->tx_dq.current);
printf(" tx_dq.end %p\n", priv->tx_dq.end);
printf(" tx_sq.base %p\n", priv->tx_sq.base);
printf(" tx_sq.current %p\n", priv->tx_sq.current);
printf(" tx_sq.end %p\n", priv->tx_sq.end);
}
/**
* Dump all RX status queue entries to the terminal.
*/
static void dump_rx_status_queue(struct eth_device *dev)
{
struct ep93xx_priv *priv = GET_PRIV(dev);
int i;
printf("\ndump_rx_status_queue()\n");
printf(" descriptor address word1 word2\n");
for (i = 0; i < NUMRXDESC; i++) {
printf(" [ %p ] %08X %08X\n",
priv->rx_sq.base + i,
(priv->rx_sq.base + i)->word1,
(priv->rx_sq.base + i)->word2);
}
}
/**
* Dump all RX descriptor queue entries to the terminal.
*/
static void dump_rx_descriptor_queue(struct eth_device *dev)
{
struct ep93xx_priv *priv = GET_PRIV(dev);
int i;
printf("\ndump_rx_descriptor_queue()\n");
printf(" descriptor address word1 word2\n");
for (i = 0; i < NUMRXDESC; i++) {
printf(" [ %p ] %08X %08X\n",
priv->rx_dq.base + i,
(priv->rx_dq.base + i)->word1,
(priv->rx_dq.base + i)->word2);
}
}
/**
* Dump all TX descriptor queue entries to the terminal.
*/
static void dump_tx_descriptor_queue(struct eth_device *dev)
{
struct ep93xx_priv *priv = GET_PRIV(dev);
int i;
printf("\ndump_tx_descriptor_queue()\n");
printf(" descriptor address word1 word2\n");
for (i = 0; i < NUMTXDESC; i++) {
printf(" [ %p ] %08X %08X\n",
priv->tx_dq.base + i,
(priv->tx_dq.base + i)->word1,
(priv->tx_dq.base + i)->word2);
}
}
/**
* Dump all TX status queue entries to the terminal.
*/
static void dump_tx_status_queue(struct eth_device *dev)
{
struct ep93xx_priv *priv = GET_PRIV(dev);
int i;
printf("\ndump_tx_status_queue()\n");
printf(" descriptor address word1\n");
for (i = 0; i < NUMTXDESC; i++) {
printf(" [ %p ] %08X\n",
priv->rx_sq.base + i,
(priv->rx_sq.base + i)->word1);
}
}
#else
#define dump_dev(x)
#define dump_rx_descriptor_queue(x)
#define dump_rx_status_queue(x)
#define dump_tx_descriptor_queue(x)
#define dump_tx_status_queue(x)
#endif /* defined(EP93XX_MAC_DEBUG) */
/**
* Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
* it's cleared.
*/
static void ep93xx_mac_reset(struct eth_device *dev)
{
struct mac_regs *mac = GET_REGS(dev);
uint32_t value;
debug("+ep93xx_mac_reset");
value = readl(&mac->selfctl);
value |= SELFCTL_RESET;
writel(value, &mac->selfctl);
while (readl(&mac->selfctl) & SELFCTL_RESET)
; /* noop */
debug("-ep93xx_mac_reset");
}
/* Eth device open */
static int ep93xx_eth_open(struct eth_device *dev, bd_t *bd)
{
struct ep93xx_priv *priv = GET_PRIV(dev);
struct mac_regs *mac = GET_REGS(dev);
uchar *mac_addr = dev->enetaddr;
int i;
debug("+ep93xx_eth_open");
/* Reset the MAC */
ep93xx_mac_reset(dev);
/* Reset the descriptor queues' current and end address values */
priv->tx_dq.current = priv->tx_dq.base;
priv->tx_dq.end = (priv->tx_dq.base + NUMTXDESC);
priv->tx_sq.current = priv->tx_sq.base;
priv->tx_sq.end = (priv->tx_sq.base + NUMTXDESC);
priv->rx_dq.current = priv->rx_dq.base;
priv->rx_dq.end = (priv->rx_dq.base + NUMRXDESC);
priv->rx_sq.current = priv->rx_sq.base;
priv->rx_sq.end = (priv->rx_sq.base + NUMRXDESC);
/*
* Set the transmit descriptor and status queues' base address,
* current address, and length registers. Set the maximum frame
* length and threshold. Enable the transmit descriptor processor.
*/
writel((uint32_t)priv->tx_dq.base, &mac->txdq.badd);
writel((uint32_t)priv->tx_dq.base, &mac->txdq.curadd);
writel(sizeof(struct tx_descriptor) * NUMTXDESC, &mac->txdq.blen);
writel((uint32_t)priv->tx_sq.base, &mac->txstsq.badd);
writel((uint32_t)priv->tx_sq.base, &mac->txstsq.curadd);
writel(sizeof(struct tx_status) * NUMTXDESC, &mac->txstsq.blen);
writel(0x00040000, &mac->txdthrshld);
writel(0x00040000, &mac->txststhrshld);
writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), &mac->maxfrmlen);
writel(BMCTL_TXEN, &mac->bmctl);
/*
* Set the receive descriptor and status queues' base address,
* current address, and length registers. Enable the receive
* descriptor processor.
*/
writel((uint32_t)priv->rx_dq.base, &mac->rxdq.badd);
writel((uint32_t)priv->rx_dq.base, &mac->rxdq.curadd);
writel(sizeof(struct rx_descriptor) * NUMRXDESC, &mac->rxdq.blen);
writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.badd);
writel((uint32_t)priv->rx_sq.base, &mac->rxstsq.curadd);
writel(sizeof(struct rx_status) * NUMRXDESC, &mac->rxstsq.blen);
writel(0x00040000, &mac->rxdthrshld);
writel(BMCTL_RXEN, &mac->bmctl);
writel(0x00040000, &mac->rxststhrshld);
/* Wait until the receive descriptor processor is active */
while (!(readl(&mac->bmsts) & BMSTS_RXACT))
; /* noop */
/*
* Initialize the RX descriptor queue. Clear the TX descriptor queue.
* Clear the RX and TX status queues. Enqueue the RX descriptor and
* status entries to the MAC.
*/
for (i = 0; i < NUMRXDESC; i++) {
/* set buffer address */
(priv->rx_dq.base + i)->word1 = (uint32_t)NetRxPackets[i];
/* set buffer length, clear buffer index and NSOF */
(priv->rx_dq.base + i)->word2 = PKTSIZE_ALIGN;
}
memset(priv->tx_dq.base, 0,
(sizeof(struct tx_descriptor) * NUMTXDESC));
memset(priv->rx_sq.base, 0,
(sizeof(struct rx_status) * NUMRXDESC));
memset(priv->tx_sq.base, 0,
(sizeof(struct tx_status) * NUMTXDESC));
writel(NUMRXDESC, &mac->rxdqenq);
writel(NUMRXDESC, &mac->rxstsqenq);
/* Set the primary MAC address */
writel(AFP_IAPRIMARY, &mac->afp);
writel(mac_addr[0] | (mac_addr[1] << 8) |
(mac_addr[2] << 16) | (mac_addr[3] << 24),
&mac->indad);
writel(mac_addr[4] | (mac_addr[5] << 8), &mac->indad_upper);
/* Turn on RX and TX */
writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
RXCTL_RCRCA | RXCTL_MA, &mac->rxctl);
writel(TXCTL_STXON, &mac->txctl);
/* Dump data structures if we're debugging */
dump_dev(dev);
dump_rx_descriptor_queue(dev);
dump_rx_status_queue(dev);
dump_tx_descriptor_queue(dev);
dump_tx_status_queue(dev);
debug("-ep93xx_eth_open");
return 1;
}
/**
* Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
* registers.
*/
static void ep93xx_eth_close(struct eth_device *dev)
{
struct mac_regs *mac = GET_REGS(dev);
debug("+ep93xx_eth_close");
writel(0x00000000, &mac->rxctl);
writel(0x00000000, &mac->txctl);
debug("-ep93xx_eth_close");
}
/**
* Copy a frame of data from the MAC into the protocol layer for further
* processing.
*/
static int ep93xx_eth_rcv_packet(struct eth_device *dev)
{
struct mac_regs *mac = GET_REGS(dev);
struct ep93xx_priv *priv = GET_PRIV(dev);
int len = -1;
debug("+ep93xx_eth_rcv_packet");
if (RX_STATUS_RFP(priv->rx_sq.current)) {
if (RX_STATUS_RWE(priv->rx_sq.current)) {
/*
* We have a good frame. Extract the frame's length
* from the current rx_status_queue entry, and copy
* the frame's data into NetRxPackets[] of the
* protocol stack. We track the total number of
* bytes in the frame (nbytes_frame) which will be
* used when we pass the data off to the protocol
* layer via NetReceive().
*/
len = RX_STATUS_FRAME_LEN(priv->rx_sq.current);
NetReceive((uchar *)priv->rx_dq.current->word1, len);
debug("reporting %d bytes...\n", len);
} else {
/* Do we have an erroneous packet? */
error("packet rx error, status %08X %08X",
priv->rx_sq.current->word1,
priv->rx_sq.current->word2);
dump_rx_descriptor_queue(dev);
dump_rx_status_queue(dev);
}
/*
* Clear the associated status queue entry, and
* increment our current pointers to the next RX
* descriptor and status queue entries (making sure
* we wrap properly).
*/
memset((void *)priv->rx_sq.current, 0,
sizeof(struct rx_status));
priv->rx_sq.current++;
if (priv->rx_sq.current >= priv->rx_sq.end)
priv->rx_sq.current = priv->rx_sq.base;
priv->rx_dq.current++;
if (priv->rx_dq.current >= priv->rx_dq.end)
priv->rx_dq.current = priv->rx_dq.base;
/*
* Finally, return the RX descriptor and status entries
* back to the MAC engine, and loop again, checking for
* more descriptors to process.
*/
writel(1, &mac->rxdqenq);
writel(1, &mac->rxstsqenq);
} else {
len = 0;
}
debug("-ep93xx_eth_rcv_packet %d", len);
return len;
}
/**
* Send a block of data via ethernet.
*/
static int ep93xx_eth_send_packet(struct eth_device *dev,
volatile void * const packet, int const length)
{
struct mac_regs *mac = GET_REGS(dev);
struct ep93xx_priv *priv = GET_PRIV(dev);
int ret = -1;
debug("+ep93xx_eth_send_packet");
/* Parameter check */
BUG_ON(packet == NULL);
/*
* Initialize the TX descriptor queue with the new packet's info.
* Clear the associated status queue entry. Enqueue the packet
* to the MAC for transmission.
*/
/* set buffer address */
priv->tx_dq.current->word1 = (uint32_t)packet;
/* set buffer length and EOF bit */
priv->tx_dq.current->word2 = length | TX_DESC_EOF;
/* clear tx status */
priv->tx_sq.current->word1 = 0;
/* enqueue the TX descriptor */
writel(1, &mac->txdqenq);
/* wait for the frame to become processed */
while (!TX_STATUS_TXFP(priv->tx_sq.current))
; /* noop */
if (!TX_STATUS_TXWE(priv->tx_sq.current)) {
error("packet tx error, status %08X",
priv->tx_sq.current->word1);
dump_tx_descriptor_queue(dev);
dump_tx_status_queue(dev);
/* TODO: Add better error handling? */
goto eth_send_out;
}
ret = 0;
/* Fall through */
eth_send_out:
debug("-ep93xx_eth_send_packet %d", ret);
return ret;
}
#if defined(CONFIG_MII)
int ep93xx_miiphy_initialize(bd_t * const bd)
{
miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write);
return 0;
}
#endif
/**
* Initialize the EP93xx MAC. The MAC hardware is reset. Buffers are
* allocated, if necessary, for the TX and RX descriptor and status queues,
* as well as for received packets. The EP93XX MAC hardware is initialized.
* Transmit and receive operations are enabled.
*/
int ep93xx_eth_initialize(u8 dev_num, int base_addr)
{
int ret = -1;
struct eth_device *dev;
struct ep93xx_priv *priv;
debug("+ep93xx_eth_initialize");
priv = malloc(sizeof(*priv));
if (!priv) {
error("malloc() failed");
goto eth_init_failed_0;
}
memset(priv, 0, sizeof(*priv));
priv->regs = (struct mac_regs *)base_addr;
priv->tx_dq.base = calloc(NUMTXDESC,
sizeof(struct tx_descriptor));
if (priv->tx_dq.base == NULL) {
error("calloc() failed");
goto eth_init_failed_1;
}
priv->tx_sq.base = calloc(NUMTXDESC,
sizeof(struct tx_status));
if (priv->tx_sq.base == NULL) {
error("calloc() failed");
goto eth_init_failed_2;
}
priv->rx_dq.base = calloc(NUMRXDESC,
sizeof(struct rx_descriptor));
if (priv->rx_dq.base == NULL) {
error("calloc() failed");
goto eth_init_failed_3;
}
priv->rx_sq.base = calloc(NUMRXDESC,
sizeof(struct rx_status));
if (priv->rx_sq.base == NULL) {
error("calloc() failed");
goto eth_init_failed_4;
}
dev = malloc(sizeof *dev);
if (dev == NULL) {
error("malloc() failed");
goto eth_init_failed_5;
}
memset(dev, 0, sizeof *dev);
dev->iobase = base_addr;
dev->priv = priv;
dev->init = ep93xx_eth_open;
dev->halt = ep93xx_eth_close;
dev->send = ep93xx_eth_send_packet;
dev->recv = ep93xx_eth_rcv_packet;
sprintf(dev->name, "ep93xx_eth-%hu", dev_num);
eth_register(dev);
/* Done! */
ret = 1;
goto eth_init_done;
eth_init_failed_5:
free(priv->rx_sq.base);
/* Fall through */
eth_init_failed_4:
free(priv->rx_dq.base);
/* Fall through */
eth_init_failed_3:
free(priv->tx_sq.base);
/* Fall through */
eth_init_failed_2:
free(priv->tx_dq.base);
/* Fall through */
eth_init_failed_1:
free(priv);
/* Fall through */
eth_init_failed_0:
/* Fall through */
eth_init_done:
debug("-ep93xx_eth_initialize %d", ret);
return ret;
}
#if defined(CONFIG_MII)
/**
* Maximum MII address we support
*/
#define MII_ADDRESS_MAX 31
/**
* Maximum MII register address we support
*/
#define MII_REGISTER_MAX 31
/**
* Read a 16-bit value from an MII register.
*/
static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr,
unsigned char const reg, unsigned short * const value)
{
struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
int ret = -1;
uint32_t self_ctl;
debug("+ep93xx_miiphy_read");
/* Parameter checks */
BUG_ON(dev == NULL);
BUG_ON(addr > MII_ADDRESS_MAX);
BUG_ON(reg > MII_REGISTER_MAX);
BUG_ON(value == NULL);
/*
* Save the current SelfCTL register value. Set MAC to suppress
* preamble bits. Wait for any previous MII command to complete
* before issuing the new command.
*/
self_ctl = readl(&mac->selfctl);
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
writel(self_ctl & ~(1 << 8), &mac->selfctl);
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
while (readl(&mac->miists) & MIISTS_BUSY)
; /* noop */
/*
* Issue the MII 'read' command. Wait for the command to complete.
* Read the MII data value.
*/
writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
&mac->miicmd);
while (readl(&mac->miists) & MIISTS_BUSY)
; /* noop */
*value = (unsigned short)readl(&mac->miidata);
/* Restore the saved SelfCTL value and return. */
writel(self_ctl, &mac->selfctl);
ret = 0;
/* Fall through */
debug("-ep93xx_miiphy_read");
return ret;
}
/**
* Write a 16-bit value to an MII register.
*/
static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr,
unsigned char const reg, unsigned short const value)
{
struct mac_regs *mac = (struct mac_regs *)MAC_BASE;
int ret = -1;
uint32_t self_ctl;
debug("+ep93xx_miiphy_write");
/* Parameter checks */
BUG_ON(dev == NULL);
BUG_ON(addr > MII_ADDRESS_MAX);
BUG_ON(reg > MII_REGISTER_MAX);
/*
* Save the current SelfCTL register value. Set MAC to suppress
* preamble bits. Wait for any previous MII command to complete
* before issuing the new command.
*/
self_ctl = readl(&mac->selfctl);
#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
writel(self_ctl & ~(1 << 8), &mac->selfctl);
#endif /* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
while (readl(&mac->miists) & MIISTS_BUSY)
; /* noop */
/* Issue the MII 'write' command. Wait for the command to complete. */
writel((uint32_t)value, &mac->miidata);
writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
&mac->miicmd);
while (readl(&mac->miists) & MIISTS_BUSY)
; /* noop */
/* Restore the saved SelfCTL value and return. */
writel(self_ctl, &mac->selfctl);
ret = 0;
/* Fall through */
debug("-ep93xx_miiphy_write");
return ret;
}
#endif /* defined(CONFIG_MII) */
|
1001-study-uboot
|
drivers/net/ep93xx_eth.c
|
C
|
gpl3
| 17,263
|
/*
* Dave Ethernet Controller driver
*
* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DRIVERS_DNET_H__
#define __DRIVERS_DNET_H__
#define DRIVERNAME "dnet"
struct dnet_registers {
/* ALL DNET FIFO REGISTERS */
u32 RX_LEN_FIFO;
u32 RX_DATA_FIFO;
u32 TX_LEN_FIFO;
u32 TX_DATA_FIFO;
u32 pad1[0x3c];
/* ALL DNET CONTROL/STATUS REGISTERS */
u32 VERCAPS;
u32 INTR_SRC;
u32 INTR_ENB;
u32 RX_STATUS;
u32 TX_STATUS;
u32 RX_FRAMES_CNT;
u32 TX_FRAMES_CNT;
u32 RX_FIFO_TH;
u32 TX_FIFO_TH;
u32 SYS_CTL;
u32 PAUSE_TMR;
u32 RX_FIFO_WCNT;
u32 TX_FIFO_WCNT;
u32 pad2[0x33];
/* ALL DNET MAC REGISTERS */
u32 MACREG_DATA; /* Mac-Reg Data */
u32 MACREG_ADDR; /* Mac-Reg Addr */
u32 pad3[0x3e];
/* ALL DNET RX STATISTICS COUNTERS */
u32 RX_PKT_IGNR_CNT;
u32 RX_LEN_CHK_ERR_CNT;
u32 RX_LNG_FRM_CNT;
u32 RX_SHRT_FRM_CNT;
u32 RX_IPG_VIOL_CNT;
u32 RX_CRC_ERR_CNT;
u32 RX_OK_PKT_CNT;
u32 RX_CTL_FRM_CNT;
u32 RX_PAUSE_FRM_CNT;
u32 RX_MULTICAST_CNT;
u32 RX_BROADCAST_CNT;
u32 RX_VLAN_TAG_CNT;
u32 RX_PRE_SHRINK_CNT;
u32 RX_DRIB_NIB_CNT;
u32 RX_UNSUP_OPCD_CNT;
u32 RX_BYTE_CNT;
u32 pad4[0x30];
/* DNET TX STATISTICS COUNTERS */
u32 TX_UNICAST_CNT;
u32 TX_PAUSE_FRM_CNT;
u32 TX_MULTICAST_CNT;
u32 TX_BRDCAST_CNT;
u32 TX_VLAN_TAG_CNT;
u32 TX_BAD_FCS_CNT;
u32 TX_JUMBO_CNT;
u32 TX_BYTE_CNT;
};
/* SOME INTERNAL MAC-CORE REGISTER */
#define DNET_INTERNAL_MODE_REG 0x0
#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
#define DNET_INTERNAL_IGP_REG 0x8
#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
#define DNET_INTERNAL_TX_RX_STS_REG 0x12
#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
#define DNET_INTERNAL_WRITE (1 << 31)
/* MAC-CORE REGISTER FIELDS */
/* MAC-CORE MODE REGISTER FIELDS */
#define DNET_INTERNAL_MODE_GBITEN (1 << 0)
#define DNET_INTERNAL_MODE_FCEN (1 << 1)
#define DNET_INTERNAL_MODE_RXEN (1 << 2)
#define DNET_INTERNAL_MODE_TXEN (1 << 3)
/* MAC-CORE RXTX CONTROL REGISTER FIELDS */
#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
/* SYSTEM CONTROL REGISTER FIELDS */
#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
#define DNET_SYS_CTL_SENDPAUSE (1 << 2)
#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
/* TX STATUS REGISTER FIELDS */
#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
/* INTERRUPT SOURCE REGISTER FIELDS */
#define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
#define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
#define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
#define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
#define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
#define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
#define DNET_INTR_SRC_PHY (1 << 19)
/* INTERRUPT ENABLE REGISTER FIELDS */
#define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
#define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
#define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
#define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
#define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
#define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
#define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
#define DNET_INTR_ENB_RX_ERROR (1 << 11)
#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
#define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
#define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
#define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
/*
* Capabilities. Used by the driver to know the capabilities that
* the ethernet controller inside the FPGA have.
*/
#define DNET_HAS_MDIO (1 << 0)
#define DNET_HAS_IRQ (1 << 1)
#define DNET_HAS_GIGABIT (1 << 2)
#define DNET_HAS_DMA (1 << 3)
#define DNET_HAS_MII (1 << 4) /* or GMII */
#define DNET_HAS_RMII (1 << 5) /* or RGMII */
#define DNET_CAPS_MASK 0xFFFF
#define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */
#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
#define DNET_FIFO_TX_DATA_AE_TH (384)
#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
#endif
|
1001-study-uboot
|
drivers/net/dnet.h
|
C
|
gpl3
| 5,043
|
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <command.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/fec.h>
#include <asm/immap.h>
#undef ET_DEBUG
#undef MII_DEBUG
/* Ethernet Transmit and Receive Buffers */
#define DBUF_LENGTH 1520
#define TX_BUF_CNT 2
#define PKT_MAXBUF_SIZE 1518
#define PKT_MINBUF_SIZE 64
#define PKT_MAXBLR_SIZE 1520
#define LAST_PKTBUFSRX PKTBUFSRX - 1
#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
DECLARE_GLOBAL_DATA_PTR;
struct fec_info_s fec_info[] = {
#ifdef CONFIG_SYS_FEC0_IOBASE
{
0, /* index */
CONFIG_SYS_FEC0_IOBASE, /* io base */
CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
CONFIG_SYS_FEC0_MIIBASE, /* mii base */
-1, /* phy_addr */
0, /* duplex and speed */
0, /* phy name */
0, /* phyname init */
0, /* RX BD */
0, /* TX BD */
0, /* rx Index */
0, /* tx Index */
0, /* tx buffer */
0, /* initialized flag */
(struct fec_info_s *)-1,
},
#endif
#ifdef CONFIG_SYS_FEC1_IOBASE
{
1, /* index */
CONFIG_SYS_FEC1_IOBASE, /* io base */
CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
CONFIG_SYS_FEC1_MIIBASE, /* mii base */
-1, /* phy_addr */
0, /* duplex and speed */
0, /* phy name */
0, /* phy name init */
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
(cbd_t *)DBUF_LENGTH, /* RX BD */
#else
0, /* RX BD */
#endif
0, /* TX BD */
0, /* rx Index */
0, /* tx Index */
0, /* tx buffer */
0, /* initialized flag */
(struct fec_info_s *)-1,
}
#endif
};
int fec_send(struct eth_device *dev, volatile void *packet, int length);
int fec_recv(struct eth_device *dev);
int fec_init(struct eth_device *dev, bd_t * bd);
void fec_halt(struct eth_device *dev);
void fec_reset(struct eth_device *dev);
void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
{
if ((dup_spd >> 16) == FULL) {
/* Set maximum frame length */
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
FEC_RCR_PROM | 0x100;
fecp->tcr = FEC_TCR_FDEN;
} else {
/* Half duplex mode */
fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
FEC_RCR_MII_MODE | FEC_RCR_DRT;
fecp->tcr &= ~FEC_TCR_FDEN;
}
if ((dup_spd & 0xFFFF) == _100BASET) {
#ifdef CONFIG_MCF5445x
fecp->rcr &= ~0x200; /* disabled 10T base */
#endif
#ifdef MII_DEBUG
printf("100Mbps\n");
#endif
bd->bi_ethspeed = 100;
} else {
#ifdef CONFIG_MCF5445x
fecp->rcr |= 0x200; /* enabled 10T base */
#endif
#ifdef MII_DEBUG
printf("10Mbps\n");
#endif
bd->bi_ethspeed = 10;
}
}
int fec_send(struct eth_device *dev, volatile void *packet, int length)
{
struct fec_info_s *info = dev->priv;
volatile fec_t *fecp = (fec_t *) (info->iobase);
int j, rc;
u16 phyStatus;
miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
/* section 16.9.23.3
* Wait for ready
*/
j = 0;
while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
(j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("TX not ready\n");
}
info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
info->txbd[info->txIdx].cbd_datlen = length;
info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
/* Activate transmit Buffer Descriptor polling */
fecp->tdar = 0x01000000; /* Descriptor polling active */
#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
/*
* FEC unable to initial transmit data packet.
* A nop will ensure the descriptor polling active completed.
* CF Internal RAM has shorter cycle access than DRAM. If use
* DRAM as Buffer descriptor and data, a nop is a must.
* Affect only V2 and V3.
*/
__asm__ ("nop");
#endif
#ifdef CONFIG_SYS_UNIFY_CACHE
icache_invalid();
#endif
j = 0;
while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
(j < MCFFEC_TOUT_LOOP)) {
udelay(1);
j++;
}
if (j >= MCFFEC_TOUT_LOOP) {
printf("TX timeout\n");
}
#ifdef ET_DEBUG
printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
__FILE__, __LINE__, __FUNCTION__, j,
info->txbd[info->txIdx].cbd_sc,
(info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
#endif
/* return only status bits */
rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
return rc;
}
int fec_recv(struct eth_device *dev)
{
struct fec_info_s *info = dev->priv;
volatile fec_t *fecp = (fec_t *) (info->iobase);
int length;
for (;;) {
#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
#endif
#ifdef CONFIG_SYS_UNIFY_CACHE
icache_invalid();
#endif
/* section 16.9.23.2 */
if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1;
break; /* nothing received - leave for() loop */
}
length = info->rxbd[info->rxIdx].cbd_datlen;
if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
printf("%s[%d] err: %x\n",
__FUNCTION__, __LINE__,
info->rxbd[info->rxIdx].cbd_sc);
#ifdef ET_DEBUG
printf("%s[%d] err: %x\n",
__FUNCTION__, __LINE__,
info->rxbd[info->rxIdx].cbd_sc);
#endif
} else {
length -= 4;
/* Pass the packet up to the protocol layers. */
NetReceive(NetRxPackets[info->rxIdx], length);
fecp->eir |= FEC_EIR_RXF;
}
/* Give the buffer back to the FEC. */
info->rxbd[info->rxIdx].cbd_datlen = 0;
/* wrap around buffer index when necessary */
if (info->rxIdx == LAST_PKTBUFSRX) {
info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
info->rxIdx = 0;
} else {
info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
info->rxIdx++;
}
/* Try to fill Buffer Descriptors */
fecp->rdar = 0x01000000; /* Descriptor polling active */
}
return length;
}
#ifdef ET_DEBUG
void dbgFecRegs(struct eth_device *dev)
{
struct fec_info_s *info = dev->priv;
volatile fec_t *fecp = (fec_t *) (info->iobase);
printf("=====\n");
printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
printf("\n");
printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
fecp->rmon_t_drop);
printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
fecp->rmon_t_packets);
printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
fecp->rmon_t_bc_pkt);
printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
fecp->rmon_t_mc_pkt);
printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
fecp->rmon_t_crc_align);
printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
fecp->rmon_t_undersize);
printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
fecp->rmon_t_oversize);
printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
fecp->rmon_t_frag);
printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
fecp->rmon_t_jab);
printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
fecp->rmon_t_col);
printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
fecp->rmon_t_p64);
printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
fecp->rmon_t_p65to127);
printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
fecp->rmon_t_p128to255);
printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
fecp->rmon_t_p256to511);
printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
fecp->rmon_t_p512to1023);
printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
fecp->rmon_t_p1024to2047);
printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
fecp->rmon_t_p_gte2048);
printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
fecp->rmon_t_octets);
printf("\n");
printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
fecp->ieee_t_drop);
printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
fecp->ieee_t_frame_ok);
printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
fecp->ieee_t_1col);
printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
fecp->ieee_t_mcol);
printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
fecp->ieee_t_def);
printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
fecp->ieee_t_lcol);
printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
fecp->ieee_t_excol);
printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
fecp->ieee_t_macerr);
printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
fecp->ieee_t_cserr);
printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
fecp->ieee_t_sqe);
printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
fecp->ieee_t_fdxfc);
printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
fecp->ieee_t_octets_ok);
printf("\n");
printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
fecp->rmon_r_drop);
printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
fecp->rmon_r_packets);
printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
fecp->rmon_r_bc_pkt);
printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
fecp->rmon_r_mc_pkt);
printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
fecp->rmon_r_crc_align);
printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
fecp->rmon_r_undersize);
printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
fecp->rmon_r_oversize);
printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
fecp->rmon_r_frag);
printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
fecp->rmon_r_jab);
printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
fecp->rmon_r_p64);
printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
fecp->rmon_r_p65to127);
printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
fecp->rmon_r_p128to255);
printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
fecp->rmon_r_p256to511);
printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
fecp->rmon_r_p512to1023);
printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
fecp->rmon_r_p1024to2047);
printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
fecp->rmon_r_p_gte2048);
printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
fecp->rmon_r_octets);
printf("\n");
printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
fecp->ieee_r_drop);
printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
fecp->ieee_r_frame_ok);
printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
fecp->ieee_r_crc);
printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
fecp->ieee_r_align);
printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
fecp->ieee_r_macerr);
printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
fecp->ieee_r_fdxfc);
printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
fecp->ieee_r_octets_ok);
printf("\n\n\n");
}
#endif
int fec_init(struct eth_device *dev, bd_t * bd)
{
struct fec_info_s *info = dev->priv;
volatile fec_t *fecp = (fec_t *) (info->iobase);
int i;
uchar ea[6];
fecpin_setclear(dev, 1);
fec_reset(dev);
#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
defined (CONFIG_SYS_DISCOVER_PHY)
mii_init();
setFecDuplexSpeed(fecp, bd, info->dup_spd);
#else
#ifndef CONFIG_SYS_DISCOVER_PHY
setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
#endif /* CONFIG_CMD_MII || CONFIG_MII */
/* We use strictly polling mode only */
fecp->eimr = 0;
/* Clear any pending interrupt */
fecp->eir = 0xffffffff;
/* Set station address */
if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
#ifdef CONFIG_SYS_FEC1_IOBASE
volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
eth_getenv_enetaddr("eth1addr", ea);
fecp1->palr =
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
eth_getenv_enetaddr("ethaddr", ea);
fecp->palr =
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp->paur = (ea[4] << 24) | (ea[5] << 16);
} else {
#ifdef CONFIG_SYS_FEC0_IOBASE
volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
eth_getenv_enetaddr("ethaddr", ea);
fecp0->palr =
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
#ifdef CONFIG_SYS_FEC1_IOBASE
eth_getenv_enetaddr("eth1addr", ea);
fecp->palr =
(ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
fecp->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
}
/* Clear unicast address hash table */
fecp->iaur = 0;
fecp->ialr = 0;
/* Clear multicast address hash table */
fecp->gaur = 0;
fecp->galr = 0;
/* Set maximum receive buffer size. */
fecp->emrbr = PKT_MAXBLR_SIZE;
/*
* Setup Buffers and Buffer Desriptors
*/
info->rxIdx = 0;
info->txIdx = 0;
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:
* Empty, Wrap
*/
for (i = 0; i < PKTBUFSRX; i++) {
info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
info->rxbd[i].cbd_datlen = 0; /* Reset */
info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
}
info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
/*
* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
* Settings:
* Last, Tx CRC
*/
for (i = 0; i < TX_BUF_CNT; i++) {
info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
info->txbd[i].cbd_datlen = 0; /* Reset */
info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
}
info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
/* Set receive and transmit descriptor base */
fecp->erdsr = (unsigned int)(&info->rxbd[0]);
fecp->etdsr = (unsigned int)(&info->txbd[0]);
/* Now enable the transmit and receive processing */
fecp->ecr |= FEC_ECR_ETHER_EN;
/* And last, try to fill Rx Buffer Descriptors */
fecp->rdar = 0x01000000; /* Descriptor polling active */
return 1;
}
void fec_reset(struct eth_device *dev)
{
struct fec_info_s *info = dev->priv;
volatile fec_t *fecp = (fec_t *) (info->iobase);
int i;
fecp->ecr = FEC_ECR_RESET;
for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
udelay(1);
}
if (i == FEC_RESET_DELAY) {
printf("FEC_RESET_DELAY timeout\n");
}
}
void fec_halt(struct eth_device *dev)
{
struct fec_info_s *info = dev->priv;
fec_reset(dev);
fecpin_setclear(dev, 0);
info->rxIdx = info->txIdx = 0;
memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
memset(info->txbuf, 0, DBUF_LENGTH);
}
int mcffec_initialize(bd_t * bis)
{
struct eth_device *dev;
int i;
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
#endif
for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
dev =
(struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
sizeof *dev);
if (dev == NULL)
hang();
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "FEC%d", fec_info[i].index);
dev->priv = &fec_info[i];
dev->init = fec_init;
dev->halt = fec_halt;
dev->send = fec_send;
dev->recv = fec_recv;
/* setup Receive and Transmit buffer descriptor */
#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
tmp = (u32)fec_info[i].rxbd;
fec_info[i].txbd =
(cbd_t *)((u32)fec_info[i].txbd + tmp +
(PKTBUFSRX * sizeof(cbd_t)));
tmp = (u32)fec_info[i].txbd;
fec_info[i].txbuf =
(char *)((u32)fec_info[i].txbuf + tmp +
(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
tmp = (u32)fec_info[i].txbuf;
#else
fec_info[i].rxbd =
(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
(PKTBUFSRX * sizeof(cbd_t)));
fec_info[i].txbd =
(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
(TX_BUF_CNT * sizeof(cbd_t)));
fec_info[i].txbuf =
(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
#endif
#ifdef ET_DEBUG
printf("rxbd %x txbd %x\n",
(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
#endif
fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name,
mcffec_miiphy_read, mcffec_miiphy_write);
#endif
if (i > 0)
fec_info[i - 1].next = &fec_info[i];
}
fec_info[i - 1].next = &fec_info[0];
/* default speed */
bis->bi_ethspeed = 10;
return 0;
}
|
1001-study-uboot
|
drivers/net/mcffec.c
|
C
|
gpl3
| 19,151
|
/*
* (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
* (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
* (C) Copyright 2008 Armadeus Systems nc
* (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
* (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include "fec_mxc.h"
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <asm/errno.h>
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_MII
#error "CONFIG_MII has to be defined!"
#endif
#ifndef CONFIG_FEC_XCV_TYPE
#define CONFIG_FEC_XCV_TYPE MII100
#endif
/*
* The i.MX28 operates with packets in big endian. We need to swap them before
* sending and after receiving.
*/
#ifdef CONFIG_MX28
#define CONFIG_FEC_MXC_SWAP_PACKET
#endif
#undef DEBUG
struct nbuf {
uint8_t data[1500]; /**< actual data */
int length; /**< actual length */
int used; /**< buffer in use or not */
uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */
};
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
static void swap_packet(uint32_t *packet, int length)
{
int i;
for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
packet[i] = __swab32(packet[i]);
}
#endif
/*
* The i.MX28 has two ethernet interfaces, but they are not equal.
* Only the first one can access the MDIO bus.
*/
#ifdef CONFIG_MX28
static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
{
return (struct ethernet_regs *)MXS_ENET0_BASE;
}
#else
static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec)
{
return fec->eth;
}
#endif
/*
* MII-interface related functions
*/
static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr,
uint16_t *retVal)
{
struct eth_device *edev = eth_get_dev_by_name(dev);
struct fec_priv *fec = (struct fec_priv *)edev->priv;
struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
uint32_t start;
/*
* reading from any PHY's register is done by properly
* programming the FEC's MII data register.
*/
writel(FEC_IEVENT_MII, ð->ievent);
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
phy | reg, ð->mii_data);
/*
* wait for the related interrupt
*/
start = get_timer(0);
while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
printf("Read MDIO failed...\n");
return -1;
}
}
/*
* clear mii interrupt bit
*/
writel(FEC_IEVENT_MII, ð->ievent);
/*
* it's now safe to read the PHY's register
*/
*retVal = readl(ð->mii_data);
debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
regAddr, *retVal);
return 0;
}
static void fec_mii_setspeed(struct fec_priv *fec)
{
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
&fec->eth->mii_speed);
debug("fec_init: mii_speed %08x\n",
readl(&fec->eth->mii_speed));
}
static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr,
uint16_t data)
{
struct eth_device *edev = eth_get_dev_by_name(dev);
struct fec_priv *fec = (struct fec_priv *)edev->priv;
struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec);
uint32_t reg; /* convenient holder for the PHY register */
uint32_t phy; /* convenient holder for the PHY */
uint32_t start;
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
/*
* wait for the MII interrupt
*/
start = get_timer(0);
while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
printf("Write MDIO failed...\n");
return -1;
}
}
/*
* clear MII interrupt bit
*/
writel(FEC_IEVENT_MII, ð->ievent);
debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
regAddr, data);
return 0;
}
static int miiphy_restart_aneg(struct eth_device *dev)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
int ret = 0;
/*
* Wake up from sleep if necessary
* Reset PHY, then delay 300ns
*/
#ifdef CONFIG_MX27
miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF);
#endif
miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_RESET);
udelay(1000);
/*
* Set the auto-negotiation advertisement register bits
*/
miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
LPA_100FULL | LPA_100HALF | LPA_10FULL |
LPA_10HALF | PHY_ANLPAR_PSB_802_3);
miiphy_write(dev->name, fec->phy_id, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);
if (fec->mii_postcall)
ret = fec->mii_postcall(fec->phy_id);
return ret;
}
static int miiphy_wait_aneg(struct eth_device *dev)
{
uint32_t start;
uint16_t status;
struct fec_priv *fec = (struct fec_priv *)dev->priv;
/*
* Wait for AN completion
*/
start = get_timer(0);
do {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("%s: Autonegotiation timeout\n", dev->name);
return -1;
}
if (miiphy_read(dev->name, fec->phy_id,
MII_BMSR, &status)) {
printf("%s: Autonegotiation failed. status: 0x%04x\n",
dev->name, status);
return -1;
}
} while (!(status & BMSR_LSTATUS));
return 0;
}
static int fec_rx_task_enable(struct fec_priv *fec)
{
writel(1 << 24, &fec->eth->r_des_active);
return 0;
}
static int fec_rx_task_disable(struct fec_priv *fec)
{
return 0;
}
static int fec_tx_task_enable(struct fec_priv *fec)
{
writel(1 << 24, &fec->eth->x_des_active);
return 0;
}
static int fec_tx_task_disable(struct fec_priv *fec)
{
return 0;
}
/**
* Initialize receive task's buffer descriptors
* @param[in] fec all we know about the device yet
* @param[in] count receive buffer count to be allocated
* @param[in] size size of each receive buffer
* @return 0 on success
*
* For this task we need additional memory for the data buffers. And each
* data buffer requires some alignment. Thy must be aligned to a specific
* boundary each (DB_DATA_ALIGNMENT).
*/
static int fec_rbd_init(struct fec_priv *fec, int count, int size)
{
int ix;
uint32_t p = 0;
/* reserve data memory and consider alignment */
if (fec->rdb_ptr == NULL)
fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT);
p = (uint32_t)fec->rdb_ptr;
if (!p) {
puts("fec_mxc: not enough malloc memory\n");
return -ENOMEM;
}
memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
p += DB_DATA_ALIGNMENT-1;
p &= ~(DB_DATA_ALIGNMENT-1);
for (ix = 0; ix < count; ix++) {
writel(p, &fec->rbd_base[ix].data_pointer);
p += size;
writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
writew(0, &fec->rbd_base[ix].data_length);
}
/*
* mark the last RBD to close the ring
*/
writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
fec->rbd_index = 0;
return 0;
}
/**
* Initialize transmit task's buffer descriptors
* @param[in] fec all we know about the device yet
*
* Transmit buffers are created externally. We only have to init the BDs here.\n
* Note: There is a race condition in the hardware. When only one BD is in
* use it must be marked with the WRAP bit to use it for every transmitt.
* This bit in combination with the READY bit results into double transmit
* of each data buffer. It seems the state machine checks READY earlier then
* resetting it after the first transfer.
* Using two BDs solves this issue.
*/
static void fec_tbd_init(struct fec_priv *fec)
{
writew(0x0000, &fec->tbd_base[0].status);
writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
fec->tbd_index = 0;
}
/**
* Mark the given read buffer descriptor as free
* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
* @param[in] pRbd buffer descriptor to mark free again
*/
static void fec_rbd_clean(int last, struct fec_bd *pRbd)
{
/*
* Reset buffer descriptor as empty
*/
if (last)
writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
else
writew(FEC_RBD_EMPTY, &pRbd->status);
/*
* no data in it
*/
writew(0, &pRbd->data_length);
}
static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
{
imx_get_mac_from_fuse(mac);
return !is_valid_ether_addr(mac);
}
static int fec_set_hwaddr(struct eth_device *dev)
{
uchar *mac = dev->enetaddr;
struct fec_priv *fec = (struct fec_priv *)dev->priv;
writel(0, &fec->eth->iaddr1);
writel(0, &fec->eth->iaddr2);
writel(0, &fec->eth->gaddr1);
writel(0, &fec->eth->gaddr2);
/*
* Set physical address
*/
writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
&fec->eth->paddr1);
writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
return 0;
}
/**
* Start the FEC engine
* @param[in] dev Our device to handle
*/
static int fec_open(struct eth_device *edev)
{
struct fec_priv *fec = (struct fec_priv *)edev->priv;
debug("fec_open: fec_open(dev)\n");
/* full-duplex, heartbeat disabled */
writel(1 << 2, &fec->eth->x_cntrl);
fec->rbd_index = 0;
/*
* Enable FEC-Lite controller
*/
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
&fec->eth->ecntrl);
#if defined(CONFIG_MX25) || defined(CONFIG_MX53)
udelay(100);
/*
* setup the MII gasket for RMII mode
*/
/* disable the gasket */
writew(0, &fec->eth->miigsk_enr);
/* wait for the gasket to be disabled */
while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
udelay(2);
/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
/* re-enable the gasket */
writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
/* wait until MII gasket is ready */
int max_loops = 10;
while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
if (--max_loops <= 0) {
printf("WAIT for MII Gasket ready timed out\n");
break;
}
}
#endif
miiphy_wait_aneg(edev);
miiphy_speed(edev->name, fec->phy_id);
miiphy_duplex(edev->name, fec->phy_id);
/*
* Enable SmartDMA receive task
*/
fec_rx_task_enable(fec);
udelay(100000);
return 0;
}
static int fec_init(struct eth_device *dev, bd_t* bd)
{
uint32_t base;
struct fec_priv *fec = (struct fec_priv *)dev->priv;
uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop;
uint32_t rcntrl;
int i;
/* Initialize MAC address */
fec_set_hwaddr(dev);
/*
* reserve memory for both buffer descriptor chains at once
* Datasheet forces the startaddress of each chain is 16 byte
* aligned
*/
if (fec->base_ptr == NULL)
fec->base_ptr = malloc((2 + FEC_RBD_NUM) *
sizeof(struct fec_bd) + DB_ALIGNMENT);
base = (uint32_t)fec->base_ptr;
if (!base) {
puts("fec_mxc: not enough malloc memory\n");
return -ENOMEM;
}
memset((void *)base, 0, (2 + FEC_RBD_NUM) *
sizeof(struct fec_bd) + DB_ALIGNMENT);
base += (DB_ALIGNMENT-1);
base &= ~(DB_ALIGNMENT-1);
fec->rbd_base = (struct fec_bd *)base;
base += FEC_RBD_NUM * sizeof(struct fec_bd);
fec->tbd_base = (struct fec_bd *)base;
/*
* Set interrupt mask register
*/
writel(0x00000000, &fec->eth->imask);
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
writel(0xffffffff, &fec->eth->ievent);
/*
* Set FEC-Lite receive control register(R_CNTRL):
*/
/* Start with frame length = 1518, common for all modes. */
rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
if (fec->xcv_type == SEVENWIRE)
rcntrl |= FEC_RCNTRL_FCE;
else if (fec->xcv_type == RMII)
rcntrl |= FEC_RCNTRL_RMII;
else /* MII mode */
rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
writel(rcntrl, &fec->eth->r_cntrl);
if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
fec_mii_setspeed(fec);
/*
* Set Opcode/Pause Duration Register
*/
writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
writel(0x2, &fec->eth->x_wmrk);
/*
* Set multicast address filter
*/
writel(0x00000000, &fec->eth->gaddr1);
writel(0x00000000, &fec->eth->gaddr2);
/* clear MIB RAM */
for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
writel(0, i);
/* FIFO receive start register */
writel(0x520, &fec->eth->r_fstart);
/* size and address of each buffer */
writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
writel((uint32_t)fec->tbd_base, &fec->eth->etdsr);
writel((uint32_t)fec->rbd_base, &fec->eth->erdsr);
/*
* Initialize RxBD/TxBD rings
*/
if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) {
free(fec->base_ptr);
fec->base_ptr = NULL;
return -ENOMEM;
}
fec_tbd_init(fec);
if (fec->xcv_type != SEVENWIRE)
miiphy_restart_aneg(dev);
fec_open(dev);
return 0;
}
/**
* Halt the FEC engine
* @param[in] dev Our device to handle
*/
static void fec_halt(struct eth_device *dev)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
int counter = 0xffff;
/*
* issue graceful stop command to the FEC transmitter if necessary
*/
writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
&fec->eth->x_cntrl);
debug("eth_halt: wait for stop regs\n");
/*
* wait for graceful stop to register
*/
while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
udelay(1);
/*
* Disable SmartDMA tasks
*/
fec_tx_task_disable(fec);
fec_rx_task_disable(fec);
/*
* Disable the Ethernet Controller
* Note: this will also reset the BD index counter!
*/
writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
&fec->eth->ecntrl);
fec->rbd_index = 0;
fec->tbd_index = 0;
debug("eth_halt: done\n");
}
/**
* Transmit one frame
* @param[in] dev Our ethernet device to handle
* @param[in] packet Pointer to the data to be transmitted
* @param[in] length Data count in bytes
* @return 0 on success
*/
static int fec_send(struct eth_device *dev, volatile void* packet, int length)
{
unsigned int status;
/*
* This routine transmits one frame. This routine only accepts
* 6-byte Ethernet addresses.
*/
struct fec_priv *fec = (struct fec_priv *)dev->priv;
/*
* Check for valid length of data.
*/
if ((length > 1500) || (length <= 0)) {
printf("Payload (%d) too large\n", length);
return -1;
}
/*
* Setup the transmit buffer
* Note: We are always using the first buffer for transmission,
* the second will be empty and only used to stop the DMA engine
*/
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)packet, length);
#endif
writew(length, &fec->tbd_base[fec->tbd_index].data_length);
writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer);
/*
* update BD's status now
* This block:
* - is always the last in a chain (means no chain)
* - should transmitt the CRC
* - might be the last BD in the list, so the address counter should
* wrap (-> keep the WRAP flag)
*/
status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
writew(status, &fec->tbd_base[fec->tbd_index].status);
/*
* Enable SmartDMA transmit task
*/
fec_tx_task_enable(fec);
/*
* wait until frame is sent .
*/
while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
udelay(1);
}
debug("fec_send: status 0x%x index %d\n",
readw(&fec->tbd_base[fec->tbd_index].status),
fec->tbd_index);
/* for next transmission use the other buffer */
if (fec->tbd_index)
fec->tbd_index = 0;
else
fec->tbd_index = 1;
return 0;
}
/**
* Pull one frame from the card
* @param[in] dev Our ethernet device to handle
* @return Length of packet read
*/
static int fec_recv(struct eth_device *dev)
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
unsigned long ievent;
int frame_length, len = 0;
struct nbuf *frame;
uint16_t bd_status;
uchar buff[FEC_MAX_PKT_SIZE];
/*
* Check if any critical events have happened
*/
ievent = readl(&fec->eth->ievent);
writel(ievent, &fec->eth->ievent);
debug("fec_recv: ievent 0x%lx\n", ievent);
if (ievent & FEC_IEVENT_BABR) {
fec_halt(dev);
fec_init(dev, fec->bd);
printf("some error: 0x%08lx\n", ievent);
return 0;
}
if (ievent & FEC_IEVENT_HBERR) {
/* Heartbeat error */
writel(0x00000001 | readl(&fec->eth->x_cntrl),
&fec->eth->x_cntrl);
}
if (ievent & FEC_IEVENT_GRA) {
/* Graceful stop complete */
if (readl(&fec->eth->x_cntrl) & 0x00000001) {
fec_halt(dev);
writel(~0x00000001 & readl(&fec->eth->x_cntrl),
&fec->eth->x_cntrl);
fec_init(dev, fec->bd);
}
}
/*
* ensure reading the right buffer status
*/
bd_status = readw(&rbd->status);
debug("fec_recv: status 0x%x\n", bd_status);
if (!(bd_status & FEC_RBD_EMPTY)) {
if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
((readw(&rbd->data_length) - 4) > 14)) {
/*
* Get buffer address and size
*/
frame = (struct nbuf *)readl(&rbd->data_pointer);
frame_length = readw(&rbd->data_length) - 4;
/*
* Fill the buffer and pass it to upper layers
*/
#ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet((uint32_t *)frame->data, frame_length);
#endif
memcpy(buff, frame->data, frame_length);
NetReceive(buff, frame_length);
len = frame_length;
} else {
if (bd_status & FEC_RBD_ERR)
printf("error frame: 0x%08lx 0x%08x\n",
(ulong)rbd->data_pointer,
bd_status);
}
/*
* free the current buffer, restart the engine
* and move forward to the next buffer
*/
fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
fec_rx_task_enable(fec);
fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
}
debug("fec_recv: stop\n");
return len;
}
static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
{
struct eth_device *edev;
struct fec_priv *fec;
unsigned char ethaddr[6];
uint32_t start;
int ret = 0;
/* create and fill edev struct */
edev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!edev) {
puts("fec_mxc: not enough malloc memory for eth_device\n");
ret = -ENOMEM;
goto err1;
}
fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
if (!fec) {
puts("fec_mxc: not enough malloc memory for fec_priv\n");
ret = -ENOMEM;
goto err2;
}
memset(edev, 0, sizeof(*edev));
memset(fec, 0, sizeof(*fec));
edev->priv = fec;
edev->init = fec_init;
edev->send = fec_send;
edev->recv = fec_recv;
edev->halt = fec_halt;
edev->write_hwaddr = fec_set_hwaddr;
fec->eth = (struct ethernet_regs *)base_addr;
fec->bd = bd;
fec->xcv_type = CONFIG_FEC_XCV_TYPE;
/* Reset chip. */
writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
start = get_timer(0);
while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
printf("FEC MXC: Timeout reseting chip\n");
goto err3;
}
udelay(10);
}
/*
* Set interrupt mask register
*/
writel(0x00000000, &fec->eth->imask);
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
writel(0xffffffff, &fec->eth->ievent);
/*
* Set FEC-Lite receive control register(R_CNTRL):
*/
/*
* Frame length=1518; MII mode;
*/
writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE |
FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl);
fec_mii_setspeed(fec);
if (dev_id == -1) {
sprintf(edev->name, "FEC");
fec->dev_id = 0;
} else {
sprintf(edev->name, "FEC%i", dev_id);
fec->dev_id = dev_id;
}
fec->phy_id = phy_id;
miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
eth_register(edev);
if (fec_get_hwaddr(edev, ethaddr) == 0) {
debug("got MAC address from fuse: %pM\n", ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
}
return ret;
err3:
free(fec);
err2:
free(edev);
err1:
return ret;
}
#ifndef CONFIG_FEC_MXC_MULTI
int fecmxc_initialize(bd_t *bd)
{
int lout = 1;
debug("eth_init: fec_probe(bd)\n");
lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
return lout;
}
#endif
int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
{
int lout = 1;
debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
lout = fec_probe(bd, dev_id, phy_id, addr);
return lout;
}
int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
{
struct fec_priv *fec = (struct fec_priv *)dev->priv;
fec->mii_postcall = cb;
return 0;
}
|
1001-study-uboot
|
drivers/net/fec_mxc.c
|
C
|
gpl3
| 21,089
|
/*
* (C) Copyright 2003-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Derived from the MPC8xx FEC driver.
* Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include <asm/io.h>
#include "mpc512x_fec.h"
DECLARE_GLOBAL_DATA_PTR;
#define DEBUG 0
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data);
int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
static uchar rx_buff[FEC_BUFFER_SIZE];
static int rx_buff_idx = 0;
/********************************************************************/
#if (DEBUG & 0x2)
static void mpc512x_fec_phydump (char *devname)
{
u16 phyStatus, i;
u8 phyAddr = CONFIG_PHY_ADDR;
u8 reg_mask[] = {
/* regs to print: 0...8, 21,27,31 */
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
};
for (i = 0; i < 32; i++) {
if (reg_mask[i]) {
miiphy_read (devname, phyAddr, i, &phyStatus);
printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
}
}
}
#endif
/********************************************************************/
static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
{
int ix;
/*
* Receive BDs init
*/
for (ix = 0; ix < FEC_RBD_NUM; ix++) {
fec->bdBase->rbd[ix].dataPointer =
(u32)&fec->bdBase->recv_frames[ix];
fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
fec->bdBase->rbd[ix].dataLength = 0;
}
/*
* have the last RBD to close the ring
*/
fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
fec->rbdIndex = 0;
/*
* Trasmit BDs init
*/
for (ix = 0; ix < FEC_TBD_NUM; ix++) {
fec->bdBase->tbd[ix].status = 0;
}
/*
* Have the last TBD to close the ring
*/
fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
/*
* Initialize some indices
*/
fec->tbdIndex = 0;
fec->usedTbdIndex = 0;
fec->cleanTbdNum = FEC_TBD_NUM;
return 0;
}
/********************************************************************/
static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
{
/*
* Reset buffer descriptor as empty
*/
if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
else
pRbd->status = FEC_RBD_EMPTY;
pRbd->dataLength = 0;
/*
* Increment BD count
*/
fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
/*
* Now, we have an empty RxBD, notify FEC
* Set Descriptor polling active
*/
out_be32(&fec->eth->r_des_active, 0x01000000);
}
/********************************************************************/
static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
{
volatile FEC_TBD *pUsedTbd;
#if (DEBUG & 0x1)
printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
fec->cleanTbdNum, fec->usedTbdIndex);
#endif
/*
* process all the consumed TBDs
*/
while (fec->cleanTbdNum < FEC_TBD_NUM) {
pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
if (pUsedTbd->status & FEC_TBD_READY) {
#if (DEBUG & 0x20)
printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
#endif
return;
}
/*
* clean this buffer descriptor
*/
if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
pUsedTbd->status = FEC_TBD_WRAP;
else
pUsedTbd->status = 0;
/*
* update some indeces for a correct handling of the TBD ring
*/
fec->cleanTbdNum++;
fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
}
}
/********************************************************************/
static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, unsigned char *mac)
{
u8 currByte; /* byte for which to compute the CRC */
int byte; /* loop - counter */
int bit; /* loop - counter */
u32 crc = 0xffffffff; /* initial value */
/*
* The algorithm used is the following:
* we loop on each of the six bytes of the provided address,
* and we compute the CRC by left-shifting the previous
* value by one position, so that each bit in the current
* byte of the address may contribute the calculation. If
* the latter and the MSB in the CRC are different, then
* the CRC value so computed is also ex-ored with the
* "polynomium generator". The current byte of the address
* is also shifted right by one bit at each iteration.
* This is because the CRC generatore in hardware is implemented
* as a shift-register with as many ex-ores as the radixes
* in the polynomium. This suggests that we represent the
* polynomiumm itself as a 32-bit constant.
*/
for (byte = 0; byte < 6; byte++) {
currByte = mac[byte];
for (bit = 0; bit < 8; bit++) {
if ((currByte & 0x01) ^ (crc & 0x01)) {
crc >>= 1;
crc = crc ^ 0xedb88320;
} else {
crc >>= 1;
}
currByte >>= 1;
}
}
crc = crc >> 26;
/*
* Set individual hash table register
*/
if (crc >= 32) {
out_be32(&fec->eth->iaddr1, (1 << (crc - 32)));
out_be32(&fec->eth->iaddr2, 0);
} else {
out_be32(&fec->eth->iaddr1, 0);
out_be32(&fec->eth->iaddr2, (1 << crc));
}
/*
* Set physical address
*/
out_be32(&fec->eth->paddr1, (mac[0] << 24) + (mac[1] << 16) +
(mac[2] << 8) + mac[3]);
out_be32(&fec->eth->paddr2, (mac[4] << 24) + (mac[5] << 16) +
0x8808);
}
/********************************************************************/
static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
{
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_init... Begin\n");
#endif
mpc512x_fec_set_hwaddr (fec, dev->enetaddr);
out_be32(&fec->eth->gaddr1, 0x00000000);
out_be32(&fec->eth->gaddr2, 0x00000000);
mpc512x_fec_init_phy (dev, bis);
/* Set interrupt mask register */
out_be32(&fec->eth->imask, 0x00000000);
/* Clear FEC-Lite interrupt event register(IEVENT) */
out_be32(&fec->eth->ievent, 0xffffffff);
/* Set transmit fifo watermark register(X_WMRK), default = 64 */
out_be32(&fec->eth->x_wmrk, 0x0);
/* Set Opcode/Pause Duration Register */
out_be32(&fec->eth->op_pause, 0x00010020);
/* Frame length=1522; MII mode */
out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
/* Half-duplex, heartbeat disabled */
out_be32(&fec->eth->x_cntrl, 0x00000000);
/* Enable MIB counters */
out_be32(&fec->eth->mib_control, 0x0);
/* Setup recv fifo start and buff size */
out_be32(&fec->eth->r_fstart, 0x500);
out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
/* Setup BD base addresses */
out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
/* DMA Control */
out_be32(&fec->eth->dma_control, 0xc0000000);
/* Enable FEC */
setbits_be32(&fec->eth->ecntrl, 0x00000006);
/* Initilize addresses and status words of BDs */
mpc512x_fec_bd_init (fec);
/* Descriptor polling active */
out_be32(&fec->eth->r_des_active, 0x01000000);
#if (DEBUG & 0x1)
printf("mpc512x_fec_init... Done \n");
#endif
return 1;
}
/********************************************************************/
int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
{
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
const u8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
int timeout = 1;
u16 phyStatus;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_init_phy... Begin\n");
#endif
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
out_be32(&fec->eth->ievent, 0xffffffff);
/*
* Set interrupt mask register
*/
out_be32(&fec->eth->imask, 0x00000000);
if (fec->xcv_type != SEVENWIRE) {
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
out_be32(&fec->eth->mii_speed,
(((gd->ips_clk / 1000000) / 5) + 1) << 1);
/*
* Reset PHY, then delay 300ns
*/
miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
udelay (1000);
if (fec->xcv_type == MII10) {
/*
* Force 10Base-T, FDX operation
*/
#if (DEBUG & 0x2)
printf ("Forcing 10 Mbps ethernet link... ");
#endif
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
do { /* wait for link status to go down */
udelay (10000);
if ((timeout--) == 0) {
#if (DEBUG & 0x2)
printf ("hmmm, should not have waited...");
#endif
break;
}
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf ("=");
#endif
} while ((phyStatus & 0x0004)); /* !link up */
timeout = 1000;
do { /* wait for link status to come back up */
udelay (10000);
if ((timeout--) == 0) {
printf ("failed. Link is down.\n");
break;
}
miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf ("+");
#endif
} while (!(phyStatus & 0x0004)); /* !link up */
#if (DEBUG & 0x2)
printf ("done.\n");
#endif
} else { /* MII100 */
/*
* Set the auto-negotiation advertisement register bits
*/
miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
*/
miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
/*
* Wait for AN completion
*/
timeout = 2500;
do {
udelay (1000);
if ((timeout--) == 0) {
#if (DEBUG & 0x2)
printf ("PHY auto neg 0 failed...\n");
#endif
return -1;
}
if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
#if (DEBUG & 0x2)
printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
#endif
return -1;
}
} while (!(phyStatus & 0x0004));
#if (DEBUG & 0x2)
printf ("PHY auto neg complete! \n");
#endif
}
}
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc512x_fec_phydump (dev->name);
#endif
#if (DEBUG & 0x1)
printf ("mpc512x_fec_init_phy... Done \n");
#endif
return 1;
}
/********************************************************************/
static void mpc512x_fec_halt (struct eth_device *dev)
{
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
int counter = 0xffff;
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc512x_fec_phydump (dev->name);
#endif
/*
* mask FEC chip interrupts
*/
out_be32(&fec->eth->imask, 0);
/*
* issue graceful stop command to the FEC transmitter if necessary
*/
setbits_be32(&fec->eth->x_cntrl, 0x00000001);
/*
* wait for graceful stop to register
*/
while ((counter--) && (!(in_be32(&fec->eth->ievent) & 0x10000000)))
;
/*
* Disable the Ethernet Controller
*/
clrbits_be32(&fec->eth->ecntrl, 0x00000002);
/*
* Issue a reset command to the FEC chip
*/
setbits_be32(&fec->eth->ecntrl, 0x1);
/*
* wait at least 16 clock cycles
*/
udelay (10);
#if (DEBUG & 0x3)
printf ("Ethernet task stopped\n");
#endif
}
/********************************************************************/
static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
int data_length)
{
/*
* This routine transmits one frame. This routine only accepts
* 6-byte Ethernet addresses.
*/
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
volatile FEC_TBD *pTbd;
#if (DEBUG & 0x20)
printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
#endif
/*
* Clear Tx BD ring at first
*/
mpc512x_fec_tbd_scrub (fec);
/*
* Check for valid length of data.
*/
if ((data_length > 1500) || (data_length <= 0)) {
return -1;
}
/*
* Check the number of vacant TxBDs.
*/
if (fec->cleanTbdNum < 1) {
#if (DEBUG & 0x20)
printf ("No available TxBDs ...\n");
#endif
return -1;
}
/*
* Get the first TxBD to send the mac header
*/
pTbd = &fec->bdBase->tbd[fec->tbdIndex];
pTbd->dataLength = data_length;
pTbd->dataPointer = (u32)eth_data;
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
/* Activate transmit Buffer Descriptor polling */
out_be32(&fec->eth->x_des_active, 0x01000000);
#if (DEBUG & 0x8)
printf ( "+" );
#endif
fec->cleanTbdNum -= 1;
/*
* wait until frame is sent .
*/
while (pTbd->status & FEC_TBD_READY) {
udelay (10);
#if (DEBUG & 0x8)
printf ("TDB status = %04x\n", pTbd->status);
#endif
}
return 0;
}
/********************************************************************/
static int mpc512x_fec_recv (struct eth_device *dev)
{
/*
* This command pulls one frame from the card
*/
mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
unsigned long ievent;
int frame_length = 0;
#if (DEBUG & 0x1)
printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
#endif
#if (DEBUG & 0x8)
printf( "-" );
#endif
/*
* Check if any critical events have happened
*/
ievent = in_be32(&fec->eth->ievent);
out_be32(&fec->eth->ievent, ievent);
if (ievent & 0x20060000) {
/* BABT, Rx/Tx FIFO errors */
mpc512x_fec_halt (dev);
mpc512x_fec_init (dev, NULL);
return 0;
}
if (ievent & 0x80000000) {
/* Heartbeat error */
setbits_be32(&fec->eth->x_cntrl, 0x00000001);
}
if (ievent & 0x10000000) {
/* Graceful stop complete */
if (in_be32(&fec->eth->x_cntrl) & 0x00000001) {
mpc512x_fec_halt (dev);
clrbits_be32(&fec->eth->x_cntrl, 0x00000001);;
mpc512x_fec_init (dev, NULL);
}
}
if (!(pRbd->status & FEC_RBD_EMPTY)) {
if (!(pRbd->status & FEC_RBD_ERR) &&
((pRbd->dataLength - 4) > 14)) {
/*
* Get buffer size
*/
if (pRbd->status & FEC_RBD_LAST)
frame_length = pRbd->dataLength - 4;
else
frame_length = pRbd->dataLength;
#if (DEBUG & 0x20)
{
int i;
printf ("recv data length 0x%08x data hdr: ",
pRbd->dataLength);
for (i = 0; i < 14; i++)
printf ("%x ", *((u8*)pRbd->dataPointer + i));
printf("\n");
}
#endif
/*
* Fill the buffer and pass it to upper layers
*/
memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
frame_length - rx_buff_idx);
rx_buff_idx = frame_length;
if (pRbd->status & FEC_RBD_LAST) {
NetReceive ((uchar*)rx_buff, frame_length);
rx_buff_idx = 0;
}
}
/*
* Reset buffer descriptor as empty
*/
mpc512x_fec_rbd_clean (fec, pRbd);
}
/* Try to fill Buffer Descriptors */
out_be32(&fec->eth->r_des_active, 0x01000000);
return frame_length;
}
/********************************************************************/
int mpc512x_fec_initialize (bd_t * bis)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
mpc512x_fec_priv *fec;
struct eth_device *dev;
void * bd;
fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
dev = (struct eth_device *) malloc (sizeof(*dev));
memset (dev, 0, sizeof *dev);
fec->eth = &im->fec;
# ifndef CONFIG_FEC_10MBIT
fec->xcv_type = MII100;
# else
fec->xcv_type = MII10;
# endif
dev->priv = (void *)fec;
dev->iobase = (int)&im->fec;
dev->init = mpc512x_fec_init;
dev->halt = mpc512x_fec_halt;
dev->send = mpc512x_fec_send;
dev->recv = mpc512x_fec_recv;
sprintf (dev->name, "FEC");
eth_register (dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register (dev->name,
fec512x_miiphy_read, fec512x_miiphy_write);
#endif
/* Clean up space FEC's MIB and FIFO RAM ...*/
memset ((void *)&im->fec.mib, 0x00, sizeof(im->fec.mib));
memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
/*
* Malloc space for BDs (must be quad word-aligned)
* this pointer is lost, so cannot be freed
*/
bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
/*
* Set interrupt mask register
*/
out_be32(&fec->eth->imask, 0x00000000);
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
out_be32(&fec->eth->ievent, 0xffffffff);
return 1;
}
/* MII-interface related functions */
/********************************************************************/
int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fec512x_t *eth = &im->fec;
u32 reg; /* convenient holder for the PHY register */
u32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
/*
* reading from any PHY's register is done by properly
* programming the FEC's MII data register.
*/
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
out_be32(ð->mii_data, FEC_MII_DATA_ST |
FEC_MII_DATA_OP_RD |
FEC_MII_DATA_TA |
phy | reg);
/*
* wait for the related interrupt
*/
while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
;
if (timeout == 0) {
#if (DEBUG & 0x2)
printf ("Read MDIO failed...\n");
#endif
return -1;
}
/*
* clear mii interrupt bit
*/
out_be32(ð->ievent, 0x00800000);
/*
* it's now safe to read the PHY's register
*/
*retVal = (u16) in_be32(ð->mii_data);
return 0;
}
/********************************************************************/
int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fec512x_t *eth = &im->fec;
u32 reg; /* convenient holder for the PHY register */
u32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
out_be32(ð->mii_data, FEC_MII_DATA_ST |
FEC_MII_DATA_OP_WR |
FEC_MII_DATA_TA |
phy | reg | data);
/*
* wait for the MII interrupt
*/
while ((timeout--) && (!(in_be32(ð->ievent) & 0x00800000)))
;
if (timeout == 0) {
#if (DEBUG & 0x2)
printf ("Write MDIO failed...\n");
#endif
return -1;
}
/*
* clear MII interrupt bit
*/
out_be32(ð->ievent, 0x00800000);
return 0;
}
|
1001-study-uboot
|
drivers/net/mpc512x_fec.c
|
C
|
gpl3
| 17,825
|
/*
* INCA-IP internal switch ethernet driver.
*
* (C) Copyright 2003-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/inca-ip.h>
#include <asm/addrspace.h>
#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 3
#define TOUT_LOOP 1000000
#define DELAY udelay(10000)
/* Sometimes the store word instruction hangs while writing to one
* of the Switch registers. Moving the instruction into a separate
* function somehow makes the problem go away.
*/
static void SWORD(volatile u32 * reg, u32 value)
{
*reg = value;
}
#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
#define SW_WRITE_REG(reg, value) \
SWORD(reg, value);\
DELAY;\
SWORD(reg, value);
#define SW_READ_REG(reg, value) \
value = (u32)*((volatile u32*)reg);\
DELAY;\
value = (u32)*((volatile u32*)reg);
#define INCA_DMA_TX_POLLING_TIME 0x07
#define INCA_DMA_RX_POLLING_TIME 0x07
#define INCA_DMA_TX_HOLD 0x80000000
#define INCA_DMA_TX_EOP 0x40000000
#define INCA_DMA_TX_SOP 0x20000000
#define INCA_DMA_TX_ICPT 0x10000000
#define INCA_DMA_TX_IEOP 0x08000000
#define INCA_DMA_RX_C 0x80000000
#define INCA_DMA_RX_SOP 0x40000000
#define INCA_DMA_RX_EOP 0x20000000
#define INCA_SWITCH_PHY_SPEED_10H 0x1
#define INCA_SWITCH_PHY_SPEED_10F 0x5
#define INCA_SWITCH_PHY_SPEED_100H 0x2
#define INCA_SWITCH_PHY_SPEED_100F 0x6
/************************ Auto MDIX settings ************************/
#define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
#define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
#define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
#define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
#define WAIT_SIGNAL_RETRIES 100
#define WAIT_LINK_RETRIES 100
#define LINK_RETRY_DELAY 2000 /* ms */
/********************************************************************/
typedef struct
{
union {
struct {
volatile u32 HOLD :1;
volatile u32 ICpt :1;
volatile u32 IEop :1;
volatile u32 offset :3;
volatile u32 reserved0 :4;
volatile u32 NFB :22;
}field;
volatile u32 word;
}params;
volatile u32 nextRxDescPtr;
volatile u32 RxDataPtr;
union {
struct {
volatile u32 C :1;
volatile u32 Sop :1;
volatile u32 Eop :1;
volatile u32 reserved3 :12;
volatile u32 NBT :17;
}field;
volatile u32 word;
}status;
} inca_rx_descriptor_t;
typedef struct
{
union {
struct {
volatile u32 HOLD :1;
volatile u32 Eop :1;
volatile u32 Sop :1;
volatile u32 ICpt :1;
volatile u32 IEop :1;
volatile u32 reserved0 :5;
volatile u32 NBA :22;
}field;
volatile u32 word;
}params;
volatile u32 nextTxDescPtr;
volatile u32 TxDataPtr;
volatile u32 C :1;
volatile u32 reserved3 :31;
} inca_tx_descriptor_t;
static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
static int tx_new, rx_new, tx_hold, rx_hold;
static int tx_old_hold = -1;
static int initialized = 0;
static int inca_switch_init(struct eth_device *dev, bd_t * bis);
static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length);
static int inca_switch_recv(struct eth_device *dev);
static void inca_switch_halt(struct eth_device *dev);
static void inca_init_switch_chip(void);
static void inca_dma_init(void);
static int inca_amdix(void);
int inca_switch_initialize(bd_t * bis)
{
struct eth_device *dev;
#if 0
printf("Entered inca_switch_initialize()\n");
#endif
if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
printf("Failed to allocate memory\n");
return 0;
}
memset(dev, 0, sizeof(*dev));
inca_dma_init();
inca_init_switch_chip();
#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
inca_amdix();
#endif
sprintf(dev->name, "INCA-IP Switch");
dev->init = inca_switch_init;
dev->halt = inca_switch_halt;
dev->send = inca_switch_send;
dev->recv = inca_switch_recv;
eth_register(dev);
#if 0
printf("Leaving inca_switch_initialize()\n");
#endif
return 0;
}
static int inca_switch_init(struct eth_device *dev, bd_t * bis)
{
int i;
u32 v, regValue;
u16 wTmp;
#if 0
printf("Entering inca_switch_init()\n");
#endif
/* Set MAC address.
*/
wTmp = (u16)dev->enetaddr[0];
regValue = (wTmp << 8) | dev->enetaddr[1];
SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
wTmp = (u16)dev->enetaddr[2];
regValue = (wTmp << 8) | dev->enetaddr[3];
regValue = regValue << 16;
wTmp = (u16)dev->enetaddr[4];
regValue |= (wTmp<<8) | dev->enetaddr[5];
SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
/* Initialize the descriptor rings.
*/
for (i = 0; i < NUM_RX_DESC; i++) {
inca_rx_descriptor_t * rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[i]);
memset(rx_desc, 0, sizeof(rx_ring[i]));
/* Set maximum size of receive buffer.
*/
rx_desc->params.field.NFB = PKTSIZE_ALIGN;
/* Set the offset of the receive buffer. Zero means
* that the offset mechanism is not used.
*/
rx_desc->params.field.offset = 0;
/* Check if it is the last descriptor.
*/
if (i == (NUM_RX_DESC - 1)) {
/* Let the last descriptor point to the first
* one.
*/
rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(rx_ring);
} else {
/* Set the address of the next descriptor.
*/
rx_desc->nextRxDescPtr = (u32)CKSEG1ADDR(&rx_ring[i+1]);
}
rx_desc->RxDataPtr = (u32)CKSEG1ADDR(NetRxPackets[i]);
}
#if 0
printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
#endif
for (i = 0; i < NUM_TX_DESC; i++) {
inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[i]);
memset(tx_desc, 0, sizeof(tx_ring[i]));
tx_desc->params.word = 0;
tx_desc->params.field.HOLD = 1;
tx_desc->C = 1;
/* Check if it is the last descriptor.
*/
if (i == (NUM_TX_DESC - 1)) {
/* Let the last descriptor point to the
* first one.
*/
tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(tx_ring);
} else {
/* Set the address of the next descriptor.
*/
tx_desc->nextTxDescPtr = (u32)CKSEG1ADDR(&tx_ring[i+1]);
}
}
/* Initialize RxDMA.
*/
DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
debug("RX status = 0x%08X\n", v);
/* Writing to the FRDA of CHANNEL.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
/* Writing to the COMMAND REG.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
/* Initialize TxDMA.
*/
DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
debug("TX status = 0x%08X\n", v);
/* Writing to the FRDA of CHANNEL.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
tx_new = rx_new = 0;
tx_hold = NUM_TX_DESC - 1;
rx_hold = NUM_RX_DESC - 1;
#if 0
rx_ring[rx_hold].params.field.HOLD = 1;
#endif
/* enable spanning tree forwarding, enable the CPU port */
/* ST_PT:
* CPS (CPU port status) 0x3 (forwarding)
* LPS (LAN port status) 0x3 (forwarding)
* PPS (PC port status) 0x3 (forwarding)
*/
SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
#if 0
printf("Leaving inca_switch_init()\n");
#endif
return 0;
}
static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length)
{
int i;
int res = -1;
u32 command;
u32 regValue;
inca_tx_descriptor_t * tx_desc = (inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_new]);
#if 0
printf("Entered inca_switch_send()\n");
#endif
if (length <= 0) {
printf ("%s: bad packet size: %d\n", dev->name, length);
goto Done;
}
for(i = 0; tx_desc->C == 0; i++) {
if (i >= TOUT_LOOP) {
printf("%s: tx error buffer not ready\n", dev->name);
goto Done;
}
}
if (tx_old_hold >= 0) {
((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_old_hold]))->params.field.HOLD = 1;
}
tx_old_hold = tx_hold;
tx_desc->params.word =
(INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
tx_desc->C = 0;
tx_desc->TxDataPtr = (u32)packet;
tx_desc->params.field.NBA = length;
((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->params.field.HOLD = 0;
tx_hold = tx_new;
tx_new = (tx_new + 1) % NUM_TX_DESC;
if (! initialized) {
command = INCA_IP_DMA_DMA_TXCCR0_INIT;
initialized = 1;
} else {
command = INCA_IP_DMA_DMA_TXCCR0_HR;
}
DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
regValue |= command;
#if 0
printf("regValue = 0x%x\n", regValue);
#endif
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
#if 1
for(i = 0; ((inca_tx_descriptor_t *)CKSEG1ADDR(&tx_ring[tx_hold]))->C == 0; i++) {
if (i >= TOUT_LOOP) {
printf("%s: tx buffer not ready\n", dev->name);
goto Done;
}
}
#endif
res = length;
Done:
#if 0
printf("Leaving inca_switch_send()\n");
#endif
return res;
}
static int inca_switch_recv(struct eth_device *dev)
{
int length = 0;
inca_rx_descriptor_t * rx_desc;
#if 0
printf("Entered inca_switch_recv()\n");
#endif
for (;;) {
rx_desc = (inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_new]);
if (rx_desc->status.field.C == 0) {
break;
}
#if 0
rx_ring[rx_new].params.field.HOLD = 1;
#endif
if (! rx_desc->status.field.Eop) {
printf("Partly received packet!!!\n");
break;
}
length = rx_desc->status.field.NBT;
rx_desc->status.word &=
~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
#if 0
{
int i;
for (i=0;i<length - 4;i++) {
if (i % 16 == 0) printf("\n%04x: ", i);
printf("%02X ", NetRxPackets[rx_new][i]);
}
printf("\n");
}
#endif
if (length) {
#if 0
printf("Received %d bytes\n", length);
#endif
NetReceive((void*)CKSEG1ADDR(NetRxPackets[rx_new]), length - 4);
} else {
#if 1
printf("Zero length!!!\n");
#endif
}
((inca_rx_descriptor_t *)CKSEG1ADDR(&rx_ring[rx_hold]))->params.field.HOLD = 0;
rx_hold = rx_new;
rx_new = (rx_new + 1) % NUM_RX_DESC;
}
#if 0
printf("Leaving inca_switch_recv()\n");
#endif
return length;
}
static void inca_switch_halt(struct eth_device *dev)
{
#if 0
printf("Entered inca_switch_halt()\n");
#endif
#if 1
initialized = 0;
#endif
#if 1
/* Disable forwarding to the CPU port.
*/
SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
/* Close RxDMA channel.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
/* Close TxDMA channel.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
#endif
#if 0
printf("Leaving inca_switch_halt()\n");
#endif
}
static void inca_init_switch_chip(void)
{
u32 regValue;
/* To workaround a problem with collision counter
* (see Errata sheet).
*/
SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
#if 1
/* init MDIO configuration:
* MDS (Poll speed): 0x01 (4ms)
* PHY_LAN_ADDR: 0x06
* PHY_PC_ADDR: 0x05
* UEP (Use External PHY): 0x00 (Internal PHY is used)
* PS (Port Select): 0x00 (PT/UMM for LAN)
* PT (PHY Test): 0x00 (no test mode)
* UMM (Use MDIO Mode): 0x00 (state machine is disabled)
*/
SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
/* init PHY:
* SL (Auto Neg. Speed for LAN)
* SP (Auto Neg. Speed for PC)
* LL (Link Status for LAN)
* LP (Link Status for PC)
* DL (Duplex Status for LAN)
* DP (Duplex Status for PC)
* PL (Auto Neg. Pause Status for LAN)
* PP (Auto Neg. Pause Status for PC)
*/
SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
/* MDIO_ACC:
* RA (Request/Ack) 0x01 (Request)
* RW (Read/Write) 0x01 (Write)
* PHY_ADDR 0x05 (PC)
* REG_ADDR 0x00 (PHY_BCR: basic control register)
* PHY_DATA 0x8000
* Reset - software reset
* LB (loop back) - normal
* SS (speed select) - 10 Mbit/s
* ANE (auto neg. enable) - enable
* PD (power down) - normal
* ISO (isolate) - normal
* RAN (restart auto neg.) - normal
* DM (duplex mode) - half duplex
* CT (collision test) - enable
*/
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
/* MDIO_ACC:
* RA (Request/Ack) 0x01 (Request)
* RW (Read/Write) 0x01 (Write)
* PHY_ADDR 0x06 (LAN)
* REG_ADDR 0x00 (PHY_BCR: basic control register)
* PHY_DATA 0x8000
* Reset - software reset
* LB (loop back) - normal
* SS (speed select) - 10 Mbit/s
* ANE (auto neg. enable) - enable
* PD (power down) - normal
* ISO (isolate) - normal
* RAN (restart auto neg.) - normal
* DM (duplex mode) - half duplex
* CT (collision test) - enable
*/
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
#endif
/* Make sure the CPU port is disabled for now. We
* don't want packets to get stacked for us until
* we enable DMA and are prepared to receive them.
*/
SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
/* CRC GEN is enabled.
*/
regValue |= 0x00000200;
SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
/* ADD TAG is disabled.
*/
SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
regValue &= ~0x00000002;
SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
}
static void inca_dma_init(void)
{
/* Switch off all DMA channels.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
/* Setup TX channel polling time.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
/* Setup RX channel polling time.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
/* ERRATA: write reset value into the DMA RX IMR register.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
/* Just in case: disable all transmit interrupts also.
*/
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
}
#if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
static int inca_amdix(void)
{
u32 phyReg1 = 0;
u32 phyReg4 = 0;
u32 phyReg5 = 0;
u32 phyReg6 = 0;
u32 phyReg31 = 0;
u32 regEphy = 0;
int mdi_flag;
int retries;
/* Setup GPIO pins.
*/
*INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
*INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
#if 0
/* Wait for signal.
*/
retries = WAIT_SIGNAL_RETRIES;
while (--retries) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(17 << 16)); /* PHY_MCSR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
} while (phyReg1 & (1 << 31));
if (phyReg1 & (1 << 1)) {
/* Signal detected */
break;
}
}
if (!retries)
goto Fail;
#endif
/* Set MDI mode.
*/
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
mdi_flag = 1;
/* Wait for link.
*/
retries = WAIT_LINK_RETRIES;
while (--retries) {
udelay(LINK_RETRY_DELAY * 1000);
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(1 << 16)); /* PHY_BSR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
} while (phyReg1 & (1 << 31));
if (phyReg1 & (1 << 2)) {
/* Link is up */
break;
} else if (mdi_flag) {
/* Set MDIX mode */
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
mdi_flag = 0;
} else {
/* Set MDI mode */
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
mdi_flag = 1;
}
}
if (!retries) {
goto Fail;
} else {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(1 << 16)); /* PHY_BSR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
} while (phyReg1 & (1 << 31));
/* Auto-negotiation / Parallel detection complete
*/
if (phyReg1 & (1 << 5)) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(31 << 16)); /* PHY_SCSR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
} while (phyReg31 & (1 << 31));
switch ((phyReg31 >> 2) & 0x7) {
case INCA_SWITCH_PHY_SPEED_10H:
/* 10Base-T Half-duplex */
regEphy = 0;
break;
case INCA_SWITCH_PHY_SPEED_10F:
/* 10Base-T Full-duplex */
regEphy = INCA_IP_Switch_EPHY_DL;
break;
case INCA_SWITCH_PHY_SPEED_100H:
/* 100Base-TX Half-duplex */
regEphy = INCA_IP_Switch_EPHY_SL;
break;
case INCA_SWITCH_PHY_SPEED_100F:
/* 100Base-TX Full-duplex */
regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
break;
}
/* In case of Auto-negotiation,
* update the negotiated PAUSE support status
*/
if (phyReg1 & (1 << 3)) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(6 << 16)); /* MII_EXPANSION */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
} while (phyReg6 & (1 << 31));
/* We are Autoneg-able.
* Is Link partner also able to autoneg?
*/
if (phyReg6 & (1 << 0)) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(4 << 16)); /* MII_ADVERTISE */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
} while (phyReg4 & (1 << 31));
/* We advertise PAUSE capab.
* Does link partner also advertise it?
*/
if (phyReg4 & (1 << 10)) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(5 << 16)); /* MII_LPA */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
} while (phyReg5 & (1 << 31));
/* Link partner is PAUSE capab.
*/
if (phyReg5 & (1 << 10)) {
regEphy |= INCA_IP_Switch_EPHY_PL;
}
}
}
}
/* Link is up */
regEphy |= INCA_IP_Switch_EPHY_LL;
SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
}
}
return 0;
Fail:
printf("No Link on LAN port\n");
return -1;
}
#endif /* CONFIG_INCA_IP_SWITCH_AMDIX */
|
1001-study-uboot
|
drivers/net/inca-ip_sw.c
|
C
|
gpl3
| 19,411
|
/*
* Faraday FTMAC100 Ethernet
*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __FTMAC100_H
#define __FTMAC100_H
struct ftmac100 {
unsigned int isr; /* 0x00 */
unsigned int imr; /* 0x04 */
unsigned int mac_madr; /* 0x08 */
unsigned int mac_ladr; /* 0x0c */
unsigned int maht0; /* 0x10 */
unsigned int maht1; /* 0x14 */
unsigned int txpd; /* 0x18 */
unsigned int rxpd; /* 0x1c */
unsigned int txr_badr; /* 0x20 */
unsigned int rxr_badr; /* 0x24 */
unsigned int itc; /* 0x28 */
unsigned int aptc; /* 0x2c */
unsigned int dblac; /* 0x30 */
unsigned int pad1[3]; /* 0x34 - 0x3c */
unsigned int pad2[16]; /* 0x40 - 0x7c */
unsigned int pad3[2]; /* 0x80 - 0x84 */
unsigned int maccr; /* 0x88 */
unsigned int macsr; /* 0x8c */
unsigned int phycr; /* 0x90 */
unsigned int phywdata; /* 0x94 */
unsigned int fcr; /* 0x98 */
unsigned int bpr; /* 0x9c */
unsigned int pad4[8]; /* 0xa0 - 0xbc */
unsigned int pad5; /* 0xc0 */
unsigned int ts; /* 0xc4 */
unsigned int dmafifos; /* 0xc8 */
unsigned int tm; /* 0xcc */
unsigned int pad6; /* 0xd0 */
unsigned int tx_mcol_scol; /* 0xd4 */
unsigned int rpf_aep; /* 0xd8 */
unsigned int xm_pg; /* 0xdc */
unsigned int runt_tlcc; /* 0xe0 */
unsigned int crcer_ftl; /* 0xe4 */
unsigned int rlc_rcc; /* 0xe8 */
unsigned int broc; /* 0xec */
unsigned int mulca; /* 0xf0 */
unsigned int rp; /* 0xf4 */
unsigned int xp; /* 0xf8 */
};
/*
* Interrupt status register & interrupt mask register
*/
#define FTMAC100_INT_RPKT_FINISH (1 << 0)
#define FTMAC100_INT_NORXBUF (1 << 1)
#define FTMAC100_INT_XPKT_FINISH (1 << 2)
#define FTMAC100_INT_NOTXBUF (1 << 3)
#define FTMAC100_INT_XPKT_OK (1 << 4)
#define FTMAC100_INT_XPKT_LOST (1 << 5)
#define FTMAC100_INT_RPKT_SAV (1 << 6)
#define FTMAC100_INT_RPKT_LOST (1 << 7)
#define FTMAC100_INT_AHB_ERR (1 << 8)
#define FTMAC100_INT_PHYSTS_CHG (1 << 9)
/*
* Automatic polling timer control register
*/
#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0)
#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8)
#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
/*
* MAC control register
*/
#define FTMAC100_MACCR_XDMA_EN (1 << 0)
#define FTMAC100_MACCR_RDMA_EN (1 << 1)
#define FTMAC100_MACCR_SW_RST (1 << 2)
#define FTMAC100_MACCR_LOOP_EN (1 << 3)
#define FTMAC100_MACCR_CRC_DIS (1 << 4)
#define FTMAC100_MACCR_XMT_EN (1 << 5)
#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6)
#define FTMAC100_MACCR_RCV_EN (1 << 8)
#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9)
#define FTMAC100_MACCR_RX_RUNT (1 << 10)
#define FTMAC100_MACCR_RX_FTL (1 << 11)
#define FTMAC100_MACCR_RCV_ALL (1 << 12)
#define FTMAC100_MACCR_CRC_APD (1 << 14)
#define FTMAC100_MACCR_FULLDUP (1 << 15)
#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16)
#define FTMAC100_MACCR_RX_BROADPKT (1 << 17)
/*
* Transmit descriptor, aligned to 16 bytes
*/
struct ftmac100_txdes {
unsigned int txdes0;
unsigned int txdes1;
unsigned int txdes2; /* TXBUF_BADR */
unsigned int txdes3; /* not used by HW */
} __attribute__ ((aligned(16)));
#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0)
#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1)
#define FTMAC100_TXDES0_TXDMA_OWN (1 << 31)
#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff)
#define FTMAC100_TXDES1_LTS (1 << 27)
#define FTMAC100_TXDES1_FTS (1 << 28)
#define FTMAC100_TXDES1_TX2FIC (1 << 29)
#define FTMAC100_TXDES1_TXIC (1 << 30)
#define FTMAC100_TXDES1_EDOTR (1 << 31)
/*
* Receive descriptor, aligned to 16 bytes
*/
struct ftmac100_rxdes {
unsigned int rxdes0;
unsigned int rxdes1;
unsigned int rxdes2; /* RXBUF_BADR */
unsigned int rxdes3; /* not used by HW */
} __attribute__ ((aligned(16)));
#define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff)
#define FTMAC100_RXDES0_MULTICAST (1 << 16)
#define FTMAC100_RXDES0_BROADCAST (1 << 17)
#define FTMAC100_RXDES0_RX_ERR (1 << 18)
#define FTMAC100_RXDES0_CRC_ERR (1 << 19)
#define FTMAC100_RXDES0_FTL (1 << 20)
#define FTMAC100_RXDES0_RUNT (1 << 21)
#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22)
#define FTMAC100_RXDES0_LRS (1 << 28)
#define FTMAC100_RXDES0_FRS (1 << 29)
#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31)
#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff)
#define FTMAC100_RXDES1_EDORR (1 << 31)
#endif /* __FTMAC100_H */
|
1001-study-uboot
|
drivers/net/ftmac100.h
|
C
|
gpl3
| 5,053
|
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include <miiphy.h>
#undef DEBUG
/* Ethernet chip registers.
*/
#define SCBStatus 0 /* Rx/Command Unit Status *Word* */
#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
#define SCBCmd 2 /* Rx/Command Unit Command *Word* */
#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
#define SCBPointer 4 /* General purpose pointer. */
#define SCBPort 8 /* Misc. commands and operands. */
#define SCBflash 12 /* Flash memory control. */
#define SCBeeprom 14 /* EEPROM memory control. */
#define SCBCtrlMDI 16 /* MDI interface control. */
#define SCBEarlyRx 20 /* Early receive byte count. */
#define SCBGenControl 28 /* 82559 General Control Register */
#define SCBGenStatus 29 /* 82559 General Status register */
/* 82559 SCB status word defnitions
*/
#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
#define SCB_STATUS_FR 0x4000 /* frame received */
#define SCB_STATUS_CNA 0x2000 /* CU left active state */
#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
#define SCB_INTACK_MASK 0xFD00 /* all the above */
#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
/* System control block commands
*/
/* CU Commands */
#define CU_NOP 0x0000
#define CU_START 0x0010
#define CU_RESUME 0x0020
#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
/* RUC Commands */
#define RUC_NOP 0x0000
#define RUC_START 0x0001
#define RUC_RESUME 0x0002
#define RUC_ABORT 0x0004
#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
#define RUC_RESUMENR 0x0007
#define CU_CMD_MASK 0x00f0
#define RU_CMD_MASK 0x0007
#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
#define CU_STATUS_MASK 0x00C0
#define RU_STATUS_MASK 0x003C
#define RU_STATUS_IDLE (0<<2)
#define RU_STATUS_SUS (1<<2)
#define RU_STATUS_NORES (2<<2)
#define RU_STATUS_READY (4<<2)
#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
/* 82559 Port interface commands.
*/
#define I82559_RESET 0x00000000 /* Software reset */
#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
#define I82559_SELECTIVE_RESET 0x00000002
#define I82559_DUMP 0x00000003
#define I82559_DUMP_WAKEUP 0x00000007
/* 82559 Eeprom interface.
*/
#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
#define EE_CS 0x02 /* EEPROM chip select. */
#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
#define EE_WRITE_0 0x01
#define EE_WRITE_1 0x05
#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
#define EE_ENB (0x4800 | EE_CS)
#define EE_CMD_BITS 3
#define EE_DATA_BITS 16
/* The EEPROM commands include the alway-set leading bit.
*/
#define EE_EWENB_CMD (4 << addr_len)
#define EE_WRITE_CMD (5 << addr_len)
#define EE_READ_CMD (6 << addr_len)
#define EE_ERASE_CMD (7 << addr_len)
/* Receive frame descriptors.
*/
struct RxFD {
volatile u16 status;
volatile u16 control;
volatile u32 link; /* struct RxFD * */
volatile u32 rx_buf_addr; /* void * */
volatile u32 count;
volatile u8 data[PKTSIZE_ALIGN];
};
#define RFD_STATUS_C 0x8000 /* completion of received frame */
#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
#define RFD_COUNT_MASK 0x3fff
#define RFD_COUNT_F 0x4000
#define RFD_COUNT_EOF 0x8000
#define RFD_RX_CRC 0x0800 /* crc error */
#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
#define RFD_RX_SHORT 0x0080 /* short frame error */
#define RFD_RX_LENGTH 0x0020
#define RFD_RX_ERROR 0x0010 /* receive error */
#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
#define RFD_RX_TCO 0x0001 /* TCO indication */
/* Transmit frame descriptors
*/
struct TxFD { /* Transmit frame descriptor set. */
volatile u16 status;
volatile u16 command;
volatile u32 link; /* void * */
volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
volatile s32 count;
volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
volatile s32 tx_buf_size0; /* Length of Tx frame. */
volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
volatile s32 tx_buf_size1; /* Length of Tx frame. */
};
#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
#define TxCB_CMD_S 0x4000 /* suspend on completion */
#define TxCB_CMD_EL 0x8000 /* last command block in CBL */
#define TxCB_COUNT_MASK 0x3fff
#define TxCB_COUNT_EOF 0x8000
/* The Speedo3 Rx and Tx frame/buffer descriptors.
*/
struct descriptor { /* A generic descriptor. */
volatile u16 status;
volatile u16 command;
volatile u32 link; /* struct descriptor * */
unsigned char params[0];
};
#define CONFIG_SYS_CMD_EL 0x8000
#define CONFIG_SYS_CMD_SUSPEND 0x4000
#define CONFIG_SYS_CMD_INT 0x2000
#define CONFIG_SYS_CMD_IAS 0x0001 /* individual address setup */
#define CONFIG_SYS_CMD_CONFIGURE 0x0002 /* configure */
#define CONFIG_SYS_STATUS_C 0x8000
#define CONFIG_SYS_STATUS_OK 0x2000
/* Misc.
*/
#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 1 /* Number of TX descriptors */
#define TOUT_LOOP 1000000
#define ETH_ALEN 6
static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
static int rx_next; /* RX descriptor ring pointer */
static int tx_next; /* TX descriptor ring pointer */
static int tx_threshold;
/*
* The parameters for a CmdConfigure operation.
* There are so many options that it would be difficult to document
* each bit. We mostly use the default or recommended settings.
*/
static const char i82557_config_cmd[] = {
22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
0, 0x2E, 0, 0x60, 0,
0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
0x3f, 0x05,
};
static const char i82558_config_cmd[] = {
22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
0, 0x2E, 0, 0x60, 0x08, 0x88,
0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
0x31, 0x05,
};
static void init_rx_ring (struct eth_device *dev);
static void purge_tx_ring (struct eth_device *dev);
static void read_hw_addr (struct eth_device *dev, bd_t * bis);
static int eepro100_init (struct eth_device *dev, bd_t * bis);
static int eepro100_send (struct eth_device *dev, volatile void *packet,
int length);
static int eepro100_recv (struct eth_device *dev);
static void eepro100_halt (struct eth_device *dev);
#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460)
#define bus_to_phys(a) (a)
#define phys_to_bus(a) (a)
#else
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
#endif
static inline int INW (struct eth_device *dev, u_long addr)
{
return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
}
static inline void OUTW (struct eth_device *dev, int command, u_long addr)
{
*(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
}
static inline void OUTL (struct eth_device *dev, int command, u_long addr)
{
*(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static inline int INL (struct eth_device *dev, u_long addr)
{
return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase));
}
static int get_phyreg (struct eth_device *dev, unsigned char addr,
unsigned char reg, unsigned short *value)
{
int cmd;
int timeout = 50;
/* read requested data */
cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
OUTL (dev, cmd, SCBCtrlMDI);
do {
udelay(1000);
cmd = INL (dev, SCBCtrlMDI);
} while (!(cmd & (1 << 28)) && (--timeout));
if (timeout == 0)
return -1;
*value = (unsigned short) (cmd & 0xffff);
return 0;
}
static int set_phyreg (struct eth_device *dev, unsigned char addr,
unsigned char reg, unsigned short value)
{
int cmd;
int timeout = 50;
/* write requested data */
cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
OUTL (dev, cmd | value, SCBCtrlMDI);
while (!(INL (dev, SCBCtrlMDI) & (1 << 28)) && (--timeout))
udelay(1000);
if (timeout == 0)
return -1;
return 0;
}
/* Check if given phyaddr is valid, i.e. there is a PHY connected.
* Do this by checking model value field from ID2 register.
*/
static struct eth_device* verify_phyaddr (const char *devname,
unsigned char addr)
{
struct eth_device *dev;
unsigned short value;
unsigned char model;
dev = eth_get_dev_by_name(devname);
if (dev == NULL) {
printf("%s: no such device\n", devname);
return NULL;
}
/* read id2 register */
if (get_phyreg(dev, addr, MII_PHYSID2, &value) != 0) {
printf("%s: mii read timeout!\n", devname);
return NULL;
}
/* get model */
model = (unsigned char)((value >> 4) & 0x003f);
if (model == 0) {
printf("%s: no PHY at address %d\n", devname, addr);
return NULL;
}
return dev;
}
static int eepro100_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
struct eth_device *dev;
dev = verify_phyaddr(devname, addr);
if (dev == NULL)
return -1;
if (get_phyreg(dev, addr, reg, value) != 0) {
printf("%s: mii read timeout!\n", devname);
return -1;
}
return 0;
}
static int eepro100_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
struct eth_device *dev;
dev = verify_phyaddr(devname, addr);
if (dev == NULL)
return -1;
if (set_phyreg(dev, addr, reg, value) != 0) {
printf("%s: mii write timeout!\n", devname);
return -1;
}
return 0;
}
#endif
/* Wait for the chip get the command.
*/
static int wait_for_eepro100 (struct eth_device *dev)
{
int i;
for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
if (i >= TOUT_LOOP) {
return 0;
}
}
return 1;
}
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
{}
};
int eepro100_initialize (bd_t * bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase, status;
int idx = 0;
while (1) {
/* Find PCI device
*/
if ((devno = pci_find_devices (supported, idx++)) < 0) {
break;
}
pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
iobase &= ~0xf;
#ifdef DEBUG
printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
iobase);
#endif
pci_write_config_dword (devno,
PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled.
*/
pci_read_config_dword (devno, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_MEMORY)) {
printf ("Error: Can not enable MEM access.\n");
continue;
}
if (!(status & PCI_COMMAND_MASTER)) {
printf ("Error: Can not enable Bus Mastering.\n");
continue;
}
dev = (struct eth_device *) malloc (sizeof *dev);
if (!dev) {
printf("eepro100: Can not allocate memory\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "i82559#%d", card_number);
dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
dev->iobase = bus_to_phys (iobase);
dev->init = eepro100_init;
dev->halt = eepro100_halt;
dev->send = eepro100_send;
dev->recv = eepro100_recv;
eth_register (dev);
#if defined (CONFIG_MII) || defined(CONFIG_CMD_MII)
/* register mii command access routines */
miiphy_register(dev->name,
eepro100_miiphy_read, eepro100_miiphy_write);
#endif
card_number++;
/* Set the latency timer for value.
*/
pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
udelay (10 * 1000);
read_hw_addr (dev, bis);
}
return card_number;
}
static int eepro100_init (struct eth_device *dev, bd_t * bis)
{
int i, status = -1;
int tx_cur;
struct descriptor *ias_cmd, *cfg_cmd;
/* Reset the ethernet controller
*/
OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
udelay (20);
OUTL (dev, I82559_RESET, SCBPort);
udelay (20);
if (!wait_for_eepro100 (dev)) {
printf ("Error: Can not reset ethernet controller.\n");
goto Done;
}
OUTL (dev, 0, SCBPointer);
OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
if (!wait_for_eepro100 (dev)) {
printf ("Error: Can not reset ethernet controller.\n");
goto Done;
}
OUTL (dev, 0, SCBPointer);
OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
/* Initialize Rx and Tx rings.
*/
init_rx_ring (dev);
purge_tx_ring (dev);
/* Tell the adapter where the RX ring is located.
*/
if (!wait_for_eepro100 (dev)) {
printf ("Error: Can not reset ethernet controller.\n");
goto Done;
}
OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
OUTW (dev, SCB_M | RUC_START, SCBCmd);
/* Send the Configure frame */
tx_cur = tx_next;
tx_next = ((tx_next + 1) % NUM_TX_DESC);
cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
cfg_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_CONFIGURE));
cfg_cmd->status = 0;
cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
memcpy (cfg_cmd->params, i82558_config_cmd,
sizeof (i82558_config_cmd));
if (!wait_for_eepro100 (dev)) {
printf ("Error---CONFIG_SYS_CMD_CONFIGURE: Can not reset ethernet controller.\n");
goto Done;
}
OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
OUTW (dev, SCB_M | CU_START, SCBCmd);
for (i = 0;
!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
i++) {
if (i >= TOUT_LOOP) {
printf ("%s: Tx error buffer not ready\n", dev->name);
goto Done;
}
}
if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
printf ("TX error status = 0x%08X\n",
le16_to_cpu (tx_ring[tx_cur].status));
goto Done;
}
/* Send the Individual Address Setup frame
*/
tx_cur = tx_next;
tx_next = ((tx_next + 1) % NUM_TX_DESC);
ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
ias_cmd->command = cpu_to_le16 ((CONFIG_SYS_CMD_SUSPEND | CONFIG_SYS_CMD_IAS));
ias_cmd->status = 0;
ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
memcpy (ias_cmd->params, dev->enetaddr, 6);
/* Tell the adapter where the TX ring is located.
*/
if (!wait_for_eepro100 (dev)) {
printf ("Error: Can not reset ethernet controller.\n");
goto Done;
}
OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
OUTW (dev, SCB_M | CU_START, SCBCmd);
for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
i++) {
if (i >= TOUT_LOOP) {
printf ("%s: Tx error buffer not ready\n",
dev->name);
goto Done;
}
}
if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
printf ("TX error status = 0x%08X\n",
le16_to_cpu (tx_ring[tx_cur].status));
goto Done;
}
status = 0;
Done:
return status;
}
static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
{
int i, status = -1;
int tx_cur;
if (length <= 0) {
printf ("%s: bad packet size: %d\n", dev->name, length);
goto Done;
}
tx_cur = tx_next;
tx_next = (tx_next + 1) % NUM_TX_DESC;
tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
TxCB_CMD_SF |
TxCB_CMD_S |
TxCB_CMD_EL );
tx_ring[tx_cur].status = 0;
tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
tx_ring[tx_cur].link =
cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
tx_ring[tx_cur].tx_desc_addr =
cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
tx_ring[tx_cur].tx_buf_addr0 =
cpu_to_le32 (phys_to_bus ((u_long) packet));
tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
if (!wait_for_eepro100 (dev)) {
printf ("%s: Tx error ethernet controller not ready.\n",
dev->name);
goto Done;
}
/* Send the packet.
*/
OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
OUTW (dev, SCB_M | CU_START, SCBCmd);
for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_C);
i++) {
if (i >= TOUT_LOOP) {
printf ("%s: Tx error buffer not ready\n", dev->name);
goto Done;
}
}
if (!(le16_to_cpu (tx_ring[tx_cur].status) & CONFIG_SYS_STATUS_OK)) {
printf ("TX error status = 0x%08X\n",
le16_to_cpu (tx_ring[tx_cur].status));
goto Done;
}
status = length;
Done:
return status;
}
static int eepro100_recv (struct eth_device *dev)
{
u16 status, stat;
int rx_prev, length = 0;
stat = INW (dev, SCBStatus);
OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
for (;;) {
status = le16_to_cpu (rx_ring[rx_next].status);
if (!(status & RFD_STATUS_C)) {
break;
}
/* Valid frame status.
*/
if ((status & RFD_STATUS_OK)) {
/* A valid frame received.
*/
length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
/* Pass the packet up to the protocol
* layers.
*/
NetReceive (rx_ring[rx_next].data, length);
} else {
/* There was an error.
*/
printf ("RX error status = 0x%08X\n", status);
}
rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
rx_ring[rx_next].status = 0;
rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
rx_ring[rx_prev].control = 0;
/* Update entry information.
*/
rx_next = (rx_next + 1) % NUM_RX_DESC;
}
if (stat & SCB_STATUS_RNR) {
printf ("%s: Receiver is not ready, restart it !\n", dev->name);
/* Reinitialize Rx ring.
*/
init_rx_ring (dev);
if (!wait_for_eepro100 (dev)) {
printf ("Error: Can not restart ethernet controller.\n");
goto Done;
}
OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
OUTW (dev, SCB_M | RUC_START, SCBCmd);
}
Done:
return length;
}
static void eepro100_halt (struct eth_device *dev)
{
/* Reset the ethernet controller
*/
OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
udelay (20);
OUTL (dev, I82559_RESET, SCBPort);
udelay (20);
if (!wait_for_eepro100 (dev)) {
printf ("Error: Can not reset ethernet controller.\n");
goto Done;
}
OUTL (dev, 0, SCBPointer);
OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
if (!wait_for_eepro100 (dev)) {
printf ("Error: Can not reset ethernet controller.\n");
goto Done;
}
OUTL (dev, 0, SCBPointer);
OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
Done:
return;
}
/* SROM Read.
*/
static int read_eeprom (struct eth_device *dev, int location, int addr_len)
{
unsigned short retval = 0;
int read_cmd = location | EE_READ_CMD;
int i;
OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
OUTW (dev, EE_ENB, SCBeeprom);
/* Shift the read command bits out. */
for (i = 12; i >= 0; i--) {
short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
OUTW (dev, EE_ENB | dataval, SCBeeprom);
udelay (1);
OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
udelay (1);
}
OUTW (dev, EE_ENB, SCBeeprom);
for (i = 15; i >= 0; i--) {
OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
udelay (1);
retval = (retval << 1) |
((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
OUTW (dev, EE_ENB, SCBeeprom);
udelay (1);
}
/* Terminate the EEPROM access. */
OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
return retval;
}
#ifdef CONFIG_EEPRO100_SROM_WRITE
int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
{
unsigned short dataval;
int enable_cmd = 0x3f | EE_EWENB_CMD;
int write_cmd = location | EE_WRITE_CMD;
int i;
unsigned long datalong, tmplong;
OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
udelay(1);
OUTW(dev, EE_ENB, SCBeeprom);
/* Shift the enable command bits out. */
for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
{
dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
OUTW(dev, EE_ENB | dataval, SCBeeprom);
udelay(1);
OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
udelay(1);
}
OUTW(dev, EE_ENB, SCBeeprom);
udelay(1);
OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
udelay(1);
OUTW(dev, EE_ENB, SCBeeprom);
/* Shift the write command bits out. */
for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
{
dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
OUTW(dev, EE_ENB | dataval, SCBeeprom);
udelay(1);
OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
udelay(1);
}
/* Write the data */
datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
for (i = 0; i< EE_DATA_BITS; i++)
{
/* Extract and move data bit to bit DI */
dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
OUTW(dev, EE_ENB | dataval, SCBeeprom);
udelay(1);
OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
udelay(1);
OUTW(dev, EE_ENB | dataval, SCBeeprom);
udelay(1);
datalong = datalong << 1; /* Adjust significant data bit*/
}
/* Finish up command (toggle CS) */
OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
udelay(1); /* delay for more than 250 ns */
OUTW(dev, EE_ENB, SCBeeprom);
/* Wait for programming ready (D0 = 1) */
tmplong = 10;
do
{
dataval = INW(dev, SCBeeprom);
if (dataval & EE_DATA_READ)
break;
udelay(10000);
}
while (-- tmplong);
if (tmplong == 0)
{
printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
return -1;
}
/* Terminate the EEPROM access. */
OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
return 0;
}
#endif
static void init_rx_ring (struct eth_device *dev)
{
int i;
for (i = 0; i < NUM_RX_DESC; i++) {
rx_ring[i].status = 0;
rx_ring[i].control =
(i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
rx_ring[i].link =
cpu_to_le32 (phys_to_bus
((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
rx_ring[i].rx_buf_addr = 0xffffffff;
rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
}
rx_next = 0;
}
static void purge_tx_ring (struct eth_device *dev)
{
int i;
tx_next = 0;
tx_threshold = 0x01208000;
for (i = 0; i < NUM_TX_DESC; i++) {
tx_ring[i].status = 0;
tx_ring[i].command = 0;
tx_ring[i].link = 0;
tx_ring[i].tx_desc_addr = 0;
tx_ring[i].count = 0;
tx_ring[i].tx_buf_addr0 = 0;
tx_ring[i].tx_buf_size0 = 0;
tx_ring[i].tx_buf_addr1 = 0;
tx_ring[i].tx_buf_size1 = 0;
}
}
static void read_hw_addr (struct eth_device *dev, bd_t * bis)
{
u16 sum = 0;
int i, j;
int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
for (j = 0, i = 0; i < 0x40; i++) {
u16 value = read_eeprom (dev, i, addr_len);
sum += value;
if (i < 3) {
dev->enetaddr[j++] = value;
dev->enetaddr[j++] = value >> 8;
}
}
if (sum != 0xBABA) {
memset (dev->enetaddr, 0, ETH_ALEN);
#ifdef DEBUG
printf ("%s: Invalid EEPROM checksum %#4.4x, "
"check settings before activating this device!\n",
dev->name, sum);
#endif
}
}
|
1001-study-uboot
|
drivers/net/eepro100.c
|
C
|
gpl3
| 24,817
|
/*
* dm9000 Ethernet
*/
#ifdef CONFIG_DRIVER_DM9000
#define DM9000_ID 0x90000A46
#define DM9000_PKT_MAX 1536 /* Received packet max size */
#define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
/* although the registers are 16 bit, they are 32-bit aligned.
*/
#define DM9000_NCR 0x00
#define DM9000_NSR 0x01
#define DM9000_TCR 0x02
#define DM9000_TSR1 0x03
#define DM9000_TSR2 0x04
#define DM9000_RCR 0x05
#define DM9000_RSR 0x06
#define DM9000_ROCR 0x07
#define DM9000_BPTR 0x08
#define DM9000_FCTR 0x09
#define DM9000_FCR 0x0A
#define DM9000_EPCR 0x0B
#define DM9000_EPAR 0x0C
#define DM9000_EPDRL 0x0D
#define DM9000_EPDRH 0x0E
#define DM9000_WCR 0x0F
#define DM9000_PAR 0x10
#define DM9000_MAR 0x16
#define DM9000_GPCR 0x1e
#define DM9000_GPR 0x1f
#define DM9000_TRPAL 0x22
#define DM9000_TRPAH 0x23
#define DM9000_RWPAL 0x24
#define DM9000_RWPAH 0x25
#define DM9000_VIDL 0x28
#define DM9000_VIDH 0x29
#define DM9000_PIDL 0x2A
#define DM9000_PIDH 0x2B
#define DM9000_CHIPR 0x2C
#define DM9000_SMCR 0x2F
#define DM9000_PHY 0x40 /* PHY address 0x01 */
#define DM9000_MRCMDX 0xF0
#define DM9000_MRCMD 0xF2
#define DM9000_MRRL 0xF4
#define DM9000_MRRH 0xF5
#define DM9000_MWCMDX 0xF6
#define DM9000_MWCMD 0xF8
#define DM9000_MWRL 0xFA
#define DM9000_MWRH 0xFB
#define DM9000_TXPLL 0xFC
#define DM9000_TXPLH 0xFD
#define DM9000_ISR 0xFE
#define DM9000_IMR 0xFF
#define NCR_EXT_PHY (1<<7)
#define NCR_WAKEEN (1<<6)
#define NCR_FCOL (1<<4)
#define NCR_FDX (1<<3)
#define NCR_LBK (3<<1)
#define NCR_LBK_INT_MAC (1<<1)
#define NCR_LBK_INT_PHY (2<<1)
#define NCR_RST (1<<0)
#define NSR_SPEED (1<<7)
#define NSR_LINKST (1<<6)
#define NSR_WAKEST (1<<5)
#define NSR_TX2END (1<<3)
#define NSR_TX1END (1<<2)
#define NSR_RXOV (1<<1)
#define TCR_TJDIS (1<<6)
#define TCR_EXCECM (1<<5)
#define TCR_PAD_DIS2 (1<<4)
#define TCR_CRC_DIS2 (1<<3)
#define TCR_PAD_DIS1 (1<<2)
#define TCR_CRC_DIS1 (1<<1)
#define TCR_TXREQ (1<<0)
#define TSR_TJTO (1<<7)
#define TSR_LC (1<<6)
#define TSR_NC (1<<5)
#define TSR_LCOL (1<<4)
#define TSR_COL (1<<3)
#define TSR_EC (1<<2)
#define RCR_WTDIS (1<<6)
#define RCR_DIS_LONG (1<<5)
#define RCR_DIS_CRC (1<<4)
#define RCR_ALL (1<<3)
#define RCR_RUNT (1<<2)
#define RCR_PRMSC (1<<1)
#define RCR_RXEN (1<<0)
#define RSR_RF (1<<7)
#define RSR_MF (1<<6)
#define RSR_LCS (1<<5)
#define RSR_RWTO (1<<4)
#define RSR_PLE (1<<3)
#define RSR_AE (1<<2)
#define RSR_CE (1<<1)
#define RSR_FOE (1<<0)
#define EPCR_EPOS_PHY (1<<3)
#define EPCR_EPOS_EE (0<<3)
#define EPCR_ERPRR (1<<2)
#define EPCR_ERPRW (1<<1)
#define EPCR_ERRE (1<<0)
#define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
#define FCTR_LWOT(ot) ( ot & 0xf )
#define BPTR_BPHW(x) ((x) << 4)
#define BPTR_JPT_200US (0x07)
#define BPTR_JPT_600US (0x0f)
#define IMR_PAR (1<<7)
#define IMR_ROOM (1<<3)
#define IMR_ROM (1<<2)
#define IMR_PTM (1<<1)
#define IMR_PRM (1<<0)
#define ISR_ROOS (1<<3)
#define ISR_ROS (1<<2)
#define ISR_PTS (1<<1)
#define ISR_PRS (1<<0)
#define GPCR_GPIO0_OUT (1<<0)
#define GPR_PHY_PWROFF (1<<0)
#endif
|
1001-study-uboot
|
drivers/net/dm9000x.h
|
C
|
gpl3
| 3,538
|
/*
Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
are GPL, so this is, of course, GPL.
==========================================================================
dev/if_dp83902a.c
Ethernet device driver for NS DP83902a ethernet controller
==========================================================================
####ECOSGPLCOPYRIGHTBEGIN####
-------------------------------------------
This file is part of eCos, the Embedded Configurable Operating System.
Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
eCos is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 or (at your option) any later version.
eCos is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with eCos; if not, write to the Free Software Foundation, Inc.,
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
As a special exception, if other files instantiate templates or use macros
or inline functions from this file, or you compile this file and link it
with other works to produce a work based on this file, this file does not
by itself cause the resulting work to be covered by the GNU General Public
License. However the source code for this file must still be made available
in accordance with section (3) of the GNU General Public License.
This exception does not invalidate any other reasons why a work based on
this file might be covered by the GNU General Public License.
Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
at http://sources.redhat.com/ecos/ecos-license/
-------------------------------------------
####ECOSGPLCOPYRIGHTEND####
####BSDCOPYRIGHTBEGIN####
-------------------------------------------
Portions of this software may have been derived from OpenBSD or other sources,
and are covered by the appropriate copyright disclaimers included herein.
-------------------------------------------
####BSDCOPYRIGHTEND####
==========================================================================
#####DESCRIPTIONBEGIN####
Author(s): gthomas
Contributors: gthomas, jskov, rsandifo
Date: 2001-06-13
Purpose:
Description:
FIXME: Will fail if pinged with large packets (1520 bytes)
Add promisc config
Add SNMP
####DESCRIPTIONEND####
==========================================================================
*/
#include <common.h>
#include <command.h>
/* NE2000 base header file */
#include "ne2000_base.h"
/* find prom (taken from pc_net_cs.c from Linux) */
#include "8390.h"
/*
typedef struct hw_info_t {
u_int offset;
u_char a0, a1, a2;
u_int flags;
} hw_info_t;
*/
#define DELAY_OUTPUT 0x01
#define HAS_MISC_REG 0x02
#define USE_BIG_BUF 0x04
#define HAS_IBM_MISC 0x08
#define IS_DL10019 0x10
#define IS_DL10022 0x20
#define HAS_MII 0x40
#define USE_SHMEM 0x80 /* autodetected */
#define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */
#define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */
#define MII_PHYID_REV_MASK 0xfffffff0
#define MII_PHYID_REG1 0x02
#define MII_PHYID_REG2 0x03
static hw_info_t hw_info[] = {
{ /* Accton EN2212 */ 0x0ff0, 0x00, 0x00, 0xe8, DELAY_OUTPUT },
{ /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 },
{ /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 },
{ /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94,
DELAY_OUTPUT | HAS_IBM_MISC },
{ /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 },
{ /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 },
{ /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 },
{ /* D-Link DE-650 */ 0x0040, 0x00, 0x80, 0xc8, 0 },
{ /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 },
{ /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 },
{ /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 },
{ /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 },
{ /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* IBM FME */ 0x0374, 0x00, 0x04, 0xac,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 },
{ /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 },
{ /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 },
{ /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 },
{ /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 },
{ /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 },
{ /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45,
HAS_MISC_REG | HAS_IBM_MISC },
{ /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 },
{ /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 },
{ /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 },
{ /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b,
DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF },
{ /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 },
{ /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 },
{ /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 },
{ /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 },
{ /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 },
{ /* Qemu */ 0x0, 0x52, 0x54, 0x00, 0 },
{ /* RTL8019AS */ 0x0, 0x0, 0x18, 0x5f, 0 }
};
#define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t))
#define PCNET_CMD 0x00
#define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */
#define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */
#define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */
static void pcnet_reset_8390(u8* addr)
{
int i, r;
n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD);
PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
for (i = 0; i < 100; i++) {
if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
break;
PRINTK("got %x in reset\n", r);
udelay(100);
}
n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
if (i == 100)
printf("pcnet_reset_8390() did not complete.\n");
} /* pcnet_reset_8390 */
int get_prom(u8* mac_addr, u8* base_addr)
{
u8 prom[32];
int i, j;
struct {
u_char value, offset;
} program_seq[] = {
{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
{0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */
{0x00, EN0_RCNTLO}, /* Clear the count regs. */
{0x00, EN0_RCNTHI},
{0x00, EN0_IMR}, /* Mask completion irq. */
{0xFF, EN0_ISR},
{E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */
{E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */
{32, EN0_RCNTLO},
{0x00, EN0_RCNTHI},
{0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */
{0x00, EN0_RSARHI},
{E8390_RREAD+E8390_START, E8390_CMD},
};
PRINTK ("trying to get MAC via prom reading\n");
pcnet_reset_8390 (base_addr);
mdelay (10);
for (i = 0; i < sizeof (program_seq) / sizeof (program_seq[0]); i++)
n2k_outb (program_seq[i].value, program_seq[i].offset);
PRINTK ("PROM:");
for (i = 0; i < 32; i++) {
prom[i] = n2k_inb (PCNET_DATAPORT);
PRINTK (" %02x", prom[i]);
}
PRINTK ("\n");
for (i = 0; i < NR_INFO; i++) {
if ((prom[0] == hw_info[i].a0) &&
(prom[2] == hw_info[i].a1) &&
(prom[4] == hw_info[i].a2)) {
PRINTK ("matched board %d\n", i);
break;
}
}
if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
PRINTK ("on exit i is %d/%ld\n", i, NR_INFO);
PRINTK ("MAC address is ");
for (j = 0; j < 6; j++) {
mac_addr[j] = prom[j << 1];
PRINTK ("%02x:", mac_addr[i]);
}
PRINTK ("\n");
return (i < NR_INFO) ? i : 0;
}
return 0;
}
|
1001-study-uboot
|
drivers/net/ne2000.c
|
C
|
gpl3
| 9,047
|
/*------------------------------------------------------------------------
. smc91111.c
. This is a driver for SMSC's 91C111 single-chip Ethernet device.
.
. (C) Copyright 2002
. Sysgo Real-Time Solutions, GmbH <www.elinos.com>
. Rolf Offermanns <rof@sysgo.de>
.
. Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
. Developed by Simple Network Magic Corporation (SNMC)
. Copyright (C) 1996 by Erik Stahlman (ES)
.
. This program is free software; you can redistribute it and/or modify
. it under the terms of the GNU General Public License as published by
. the Free Software Foundation; either version 2 of the License, or
. (at your option) any later version.
.
. This program is distributed in the hope that it will be useful,
. but WITHOUT ANY WARRANTY; without even the implied warranty of
. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
. GNU General Public License for more details.
.
. You should have received a copy of the GNU General Public License
. along with this program; if not, write to the Free Software
. Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
.
. Information contained in this file was obtained from the LAN91C111
. manual from SMC. To get a copy, if you really want one, you can find
. information under www.smsc.com.
.
.
. "Features" of the SMC chip:
. Integrated PHY/MAC for 10/100BaseT Operation
. Supports internal and external MII
. Integrated 8K packet memory
. EEPROM interface for configuration
.
. Arguments:
. io = for the base address
. irq = for the IRQ
.
. author:
. Erik Stahlman ( erik@vt.edu )
. Daris A Nevil ( dnevil@snmc.com )
.
.
. Hardware multicast code from Peter Cammaert ( pc@denkart.be )
.
. Sources:
. o SMSC LAN91C111 databook (www.smsc.com)
. o smc9194.c by Erik Stahlman
. o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
.
. History:
. 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
. 10/17/01 Marco Hasewinkel Modify for DNP/1110
. 07/25/01 Woojung Huh Modify for ADS Bitsy
. 04/25/01 Daris A Nevil Initial public release through SMSC
. 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
----------------------------------------------------------------------------*/
#include <common.h>
#include <command.h>
#include <config.h>
#include <malloc.h>
#include "smc91111.h"
#include <net.h>
/* Use power-down feature of the chip */
#define POWER_DOWN 0
#define NO_AUTOPROBE
#define SMC_DEBUG 0
#if SMC_DEBUG > 1
static const char version[] =
"smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
#endif
/* Autonegotiation timeout in seconds */
#ifndef CONFIG_SMC_AUTONEG_TIMEOUT
#define CONFIG_SMC_AUTONEG_TIMEOUT 10
#endif
/*------------------------------------------------------------------------
.
. Configuration options, for the experienced user to change.
.
-------------------------------------------------------------------------*/
/*
. Wait time for memory to be free. This probably shouldn't be
. tuned that much, as waiting for this means nothing else happens
. in the system
*/
#define MEMORY_WAIT_TIME 16
#if (SMC_DEBUG > 2 )
#define PRINTK3(args...) printf(args)
#else
#define PRINTK3(args...)
#endif
#if SMC_DEBUG > 1
#define PRINTK2(args...) printf(args)
#else
#define PRINTK2(args...)
#endif
#ifdef SMC_DEBUG
#define PRINTK(args...) printf(args)
#else
#define PRINTK(args...)
#endif
/*------------------------------------------------------------------------
.
. The internal workings of the driver. If you are changing anything
. here with the SMC stuff, you should have the datasheet and know
. what you are doing.
.
-------------------------------------------------------------------------*/
/* Memory sizing constant */
#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
#ifndef CONFIG_SMC91111_BASE
#error "SMC91111 Base address must be passed to initialization funciton"
/* #define CONFIG_SMC91111_BASE 0x20000300 */
#endif
#define SMC_DEV_NAME "SMC91111"
#define SMC_PHY_ADDR 0x0000
#define SMC_ALLOC_MAX_TRY 5
#define SMC_TX_TIMEOUT 30
#define SMC_PHY_CLOCK_DELAY 1000
#define ETH_ZLEN 60
#ifdef CONFIG_SMC_USE_32_BIT
#define USE_32_BIT 1
#else
#undef USE_32_BIT
#endif
#ifdef SHARED_RESOURCES
extern void swap_to(int device_id);
#else
# define swap_to(x)
#endif
#ifndef CONFIG_SMC91111_EXT_PHY
static void smc_phy_configure(struct eth_device *dev);
#endif /* !CONFIG_SMC91111_EXT_PHY */
/*
------------------------------------------------------------
.
. Internal routines
.
------------------------------------------------------------
*/
#ifdef CONFIG_SMC_USE_IOFUNCS
/*
* input and output functions
*
* Implemented due to inx,outx macros accessing the device improperly
* and putting the device into an unkown state.
*
* For instance, on Sharp LPD7A400 SDK, affects were chip memory
* could not be free'd (hence the alloc failures), duplicate packets,
* packets being corrupt (shifted) on the wire, etc. Switching to the
* inx,outx functions fixed this problem.
*/
#define barrier() __asm__ __volatile__("": : :"memory")
static inline word SMC_inw(struct eth_device *dev, dword offset)
{
word v;
v = *((volatile word*)(dev->iobase + offset));
barrier(); *(volatile u32*)(0xc0000000);
return v;
}
static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
{
*((volatile word*)(dev->iobase + offset)) = value;
barrier(); *(volatile u32*)(0xc0000000);
}
static inline byte SMC_inb(struct eth_device *dev, dword offset)
{
word _w;
_w = SMC_inw(dev, offset & ~((dword)1));
return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
}
static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
{
word _w;
_w = SMC_inw(dev, offset & ~((dword)1));
if (offset & 1)
*((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
(value<<8) | (_w & 0x00ff);
else
*((volatile word*)(dev->iobase + offset)) =
value | (_w & 0xff00);
}
static inline void SMC_insw(struct eth_device *dev, dword offset,
volatile uchar* buf, dword len)
{
volatile word *p = (volatile word *)buf;
while (len-- > 0) {
*p++ = SMC_inw(dev, offset);
barrier();
*((volatile u32*)(0xc0000000));
}
}
static inline void SMC_outsw(struct eth_device *dev, dword offset,
uchar* buf, dword len)
{
volatile word *p = (volatile word *)buf;
while (len-- > 0) {
SMC_outw(dev, *p++, offset);
barrier();
*(volatile u32*)(0xc0000000);
}
}
#endif /* CONFIG_SMC_USE_IOFUNCS */
/*
. A rather simple routine to print out a packet for debugging purposes.
*/
#if SMC_DEBUG > 2
static void print_packet( byte *, int );
#endif
#define tx_done(dev) 1
static int poll4int (struct eth_device *dev, byte mask, int timeout)
{
int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
int is_timeout = 0;
word old_bank = SMC_inw (dev, BSR_REG);
PRINTK2 ("Polling...\n");
SMC_SELECT_BANK (dev, 2);
while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
if (get_timer (0) >= tmo) {
is_timeout = 1;
break;
}
}
/* restore old bank selection */
SMC_SELECT_BANK (dev, old_bank);
if (is_timeout)
return 1;
else
return 0;
}
/* Only one release command at a time, please */
static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
{
int count = 0;
/* assume bank 2 selected */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
udelay (1); /* Wait until not busy */
if (++count > 200)
break;
}
}
/*
. Function: smc_reset( void )
. Purpose:
. This sets the SMC91111 chip to its normal state, hopefully from whatever
. mess that any other DOS driver has put it in.
.
. Maybe I should reset more registers to defaults in here? SOFTRST should
. do that for me.
.
. Method:
. 1. send a SOFT RESET
. 2. wait for it to finish
. 3. enable autorelease mode
. 4. reset the memory management unit
. 5. clear all interrupts
.
*/
static void smc_reset (struct eth_device *dev)
{
PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
/* This resets the registers mostly to defaults, but doesn't
affect EEPROM. That seems unnecessary */
SMC_SELECT_BANK (dev, 0);
SMC_outw (dev, RCR_SOFTRST, RCR_REG);
/* Setup the Configuration Register */
/* This is necessary because the CONFIG_REG is not affected */
/* by a soft reset */
SMC_SELECT_BANK (dev, 1);
#if defined(CONFIG_SMC91111_EXT_PHY)
SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
#else
SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
#endif
/* Release from possible power-down state */
/* Configuration register is not affected by Soft Reset */
SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
CONFIG_REG);
SMC_SELECT_BANK (dev, 0);
/* this should pause enough for the chip to be happy */
udelay (10);
/* Disable transmit and receive functionality */
SMC_outw (dev, RCR_CLEAR, RCR_REG);
SMC_outw (dev, TCR_CLEAR, TCR_REG);
/* set the control register */
SMC_SELECT_BANK (dev, 1);
SMC_outw (dev, CTL_DEFAULT, CTL_REG);
/* Reset the MMU */
SMC_SELECT_BANK (dev, 2);
smc_wait_mmu_release_complete (dev);
SMC_outw (dev, MC_RESET, MMU_CMD_REG);
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
udelay (1); /* Wait until not busy */
/* Note: It doesn't seem that waiting for the MMU busy is needed here,
but this is a place where future chipsets _COULD_ break. Be wary
of issuing another MMU command right after this */
/* Disable all interrupts */
SMC_outb (dev, 0, IM_REG);
}
/*
. Function: smc_enable
. Purpose: let the chip talk to the outside work
. Method:
. 1. Enable the transmitter
. 2. Enable the receiver
. 3. Enable interrupts
*/
static void smc_enable(struct eth_device *dev)
{
PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
SMC_SELECT_BANK( dev, 0 );
/* see the header file for options in TCR/RCR DEFAULT*/
SMC_outw( dev, TCR_DEFAULT, TCR_REG );
SMC_outw( dev, RCR_DEFAULT, RCR_REG );
/* clear MII_DIS */
/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
}
/*
. Function: smc_halt
. Purpose: closes down the SMC91xxx chip.
. Method:
. 1. zero the interrupt mask
. 2. clear the enable receive flag
. 3. clear the enable xmit flags
.
. TODO:
. (1) maybe utilize power down mode.
. Why not yet? Because while the chip will go into power down mode,
. the manual says that it will wake up in response to any I/O requests
. in the register space. Empirical results do not show this working.
*/
static void smc_halt(struct eth_device *dev)
{
PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
/* no more interrupts for me */
SMC_SELECT_BANK( dev, 2 );
SMC_outb( dev, 0, IM_REG );
/* and tell the card to stay away from that nasty outside world */
SMC_SELECT_BANK( dev, 0 );
SMC_outb( dev, RCR_CLEAR, RCR_REG );
SMC_outb( dev, TCR_CLEAR, TCR_REG );
swap_to(FLASH);
}
/*
. Function: smc_send(struct net_device * )
. Purpose:
. This sends the actual packet to the SMC9xxx chip.
.
. Algorithm:
. First, see if a saved_skb is available.
. ( this should NOT be called if there is no 'saved_skb'
. Now, find the packet number that the chip allocated
. Point the data pointers at it in memory
. Set the length word in the chip's memory
. Dump the packet to chip memory
. Check if a last byte is needed ( odd length packet )
. if so, set the control flag right
. Tell the card to send it
. Enable the transmit interrupt, so I know if it failed
. Free the kernel data if I actually sent it.
*/
static int smc_send(struct eth_device *dev, volatile void *packet,
int packet_length)
{
byte packet_no;
byte *buf;
int length;
int numPages;
int try = 0;
int time_out;
byte status;
byte saved_pnr;
word saved_ptr;
/* save PTR and PNR registers before manipulation */
SMC_SELECT_BANK (dev, 2);
saved_pnr = SMC_inb( dev, PN_REG );
saved_ptr = SMC_inw( dev, PTR_REG );
PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
/* allocate memory
** The MMU wants the number of pages to be the number of 256 bytes
** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
**
** The 91C111 ignores the size bits, but the code is left intact
** for backwards and future compatibility.
**
** Pkt size for allocating is data length +6 (for additional status
** words, length and ctl!)
**
** If odd size then last byte is included in this header.
*/
numPages = ((length & 0xfffe) + 6);
numPages >>= 8; /* Divide by 256 */
if (numPages > 7) {
printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
return 0;
}
/* now, try to allocate the memory */
SMC_SELECT_BANK (dev, 2);
SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
/* FIXME: the ALLOC_INT bit never gets set *
* so the following will always give a *
* memory allocation error. *
* same code works in armboot though *
* -ro
*/
again:
try++;
time_out = MEMORY_WAIT_TIME;
do {
status = SMC_inb (dev, SMC91111_INT_REG);
if (status & IM_ALLOC_INT) {
/* acknowledge the interrupt */
SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
break;
}
} while (--time_out);
if (!time_out) {
PRINTK2 ("%s: memory allocation, try %d failed ...\n",
SMC_DEV_NAME, try);
if (try < SMC_ALLOC_MAX_TRY)
goto again;
else
return 0;
}
PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
SMC_DEV_NAME, try);
buf = (byte *) packet;
/* If I get here, I _know_ there is a packet slot waiting for me */
packet_no = SMC_inb (dev, AR_REG);
if (packet_no & AR_FAILED) {
/* or isn't there? BAD CHIP! */
printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
return 0;
}
/* we have a packet address, so tell the card to use it */
#ifndef CONFIG_XAENIAX
SMC_outb (dev, packet_no, PN_REG);
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
* the Allocate MMU command will end up written to the command register
* as well, which will lead to a problem.
*/
SMC_outl (dev, packet_no << 16, 0);
#endif
/* do not write new ptr value if Write data fifo not empty */
while ( saved_ptr & PTR_NOTEMPTY )
printf ("Write data fifo not empty!\n");
/* point to the beginning of the packet */
SMC_outw (dev, PTR_AUTOINC, PTR_REG);
PRINTK3 ("%s: Trying to xmit packet of length %x\n",
SMC_DEV_NAME, length);
#if SMC_DEBUG > 2
printf ("Transmitting Packet\n");
print_packet (buf, length);
#endif
/* send the packet length ( +6 for status, length and ctl byte )
and the status word ( set to zeros ) */
#ifdef USE_32_BIT
SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
#else
SMC_outw (dev, 0, SMC91111_DATA_REG);
/* send the packet length ( +6 for status words, length, and ctl */
SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
#endif
/* send the actual data
. I _think_ it's faster to send the longs first, and then
. mop up by sending the last word. It depends heavily
. on alignment, at least on the 486. Maybe it would be
. a good idea to check which is optimal? But that could take
. almost as much time as is saved?
*/
#ifdef USE_32_BIT
SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
#ifndef CONFIG_XAENIAX
if (length & 0x2)
SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
SMC91111_DATA_REG);
#else
/* On XANEIAX, we can only use 32-bit writes, so we need to handle
* unaligned tail part specially. The standard code doesn't work.
*/
if ((length & 3) == 3) {
u16 * ptr = (u16*) &buf[length-3];
SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
SMC91111_DATA_REG);
} else if ((length & 2) == 2) {
u16 * ptr = (u16*) &buf[length-2];
SMC_outl(dev, *ptr, SMC91111_DATA_REG);
} else if (length & 1) {
SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
} else {
SMC_outl(dev, 0, SMC91111_DATA_REG);
}
#endif
#else
SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
#endif /* USE_32_BIT */
#ifndef CONFIG_XAENIAX
/* Send the last byte, if there is one. */
if ((length & 1) == 0) {
SMC_outw (dev, 0, SMC91111_DATA_REG);
} else {
SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
}
#endif
/* and let the chipset deal with it */
SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
/* poll for TX INT */
/* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
/* poll for TX_EMPTY INT - autorelease enabled */
if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
/* sending failed */
PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
/* release packet */
/* no need to release, MMU does that now */
#ifdef CONFIG_XAENIAX
SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
#endif
/* wait for MMU getting ready (low) */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
udelay (10);
}
PRINTK2 ("MMU ready\n");
return 0;
} else {
/* ack. int */
SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
/* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
length);
/* release packet */
/* no need to release, MMU does that now */
#ifdef CONFIG_XAENIAX
SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
#endif
/* wait for MMU getting ready (low) */
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
udelay (10);
}
PRINTK2 ("MMU ready\n");
}
/* restore previously saved registers */
#ifndef CONFIG_XAENIAX
SMC_outb( dev, saved_pnr, PN_REG );
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
* the Allocate MMU command will end up written to the command register
* as well, which will lead to a problem.
*/
SMC_outl(dev, saved_pnr << 16, 0);
#endif
SMC_outw( dev, saved_ptr, PTR_REG );
return length;
}
static int smc_write_hwaddr(struct eth_device *dev)
{
int i;
swap_to(ETHERNET);
SMC_SELECT_BANK (dev, 1);
#ifdef USE_32_BIT
for (i = 0; i < 6; i += 2) {
word address;
address = dev->enetaddr[i + 1] << 8;
address |= dev->enetaddr[i];
SMC_outw(dev, address, (ADDR0_REG + i));
}
#else
for (i = 0; i < 6; i++)
SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
#endif
swap_to(FLASH);
return 0;
}
/*
* Open and Initialize the board
*
* Set up everything, reset the card, etc ..
*
*/
static int smc_init(struct eth_device *dev, bd_t *bd)
{
swap_to(ETHERNET);
PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
/* reset the hardware */
smc_reset (dev);
smc_enable (dev);
/* Configure the PHY */
#ifndef CONFIG_SMC91111_EXT_PHY
smc_phy_configure (dev);
#endif
/* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
/* SMC_SELECT_BANK(dev, 0); */
/* SMC_outw(dev, 0, RPC_REG); */
printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
return 0;
}
/*-------------------------------------------------------------
.
. smc_rcv - receive a packet from the card
.
. There is ( at least ) a packet waiting to be read from
. chip-memory.
.
. o Read the status
. o If an error, record it
. o otherwise, read in the packet
--------------------------------------------------------------
*/
static int smc_rcv(struct eth_device *dev)
{
int packet_number;
word status;
word packet_length;
int is_error = 0;
#ifdef USE_32_BIT
dword stat_len;
#endif
byte saved_pnr;
word saved_ptr;
SMC_SELECT_BANK(dev, 2);
/* save PTR and PTR registers */
saved_pnr = SMC_inb( dev, PN_REG );
saved_ptr = SMC_inw( dev, PTR_REG );
packet_number = SMC_inw( dev, RXFIFO_REG );
if ( packet_number & RXFIFO_REMPTY ) {
return 0;
}
PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
/* start reading from the start of the packet */
SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
/* First two words are status and packet_length */
#ifdef USE_32_BIT
stat_len = SMC_inl(dev, SMC91111_DATA_REG);
status = stat_len & 0xffff;
packet_length = stat_len >> 16;
#else
status = SMC_inw( dev, SMC91111_DATA_REG );
packet_length = SMC_inw( dev, SMC91111_DATA_REG );
#endif
packet_length &= 0x07ff; /* mask off top bits */
PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
if ( !(status & RS_ERRORS ) ){
/* Adjust for having already read the first two words */
packet_length -= 4; /*4; */
/* set odd length for bug in LAN91C111, */
/* which never sets RS_ODDFRAME */
/* TODO ? */
#ifdef USE_32_BIT
PRINTK3(" Reading %d dwords (and %d bytes) \n",
packet_length >> 2, packet_length & 3 );
/* QUESTION: Like in the TX routine, do I want
to send the DWORDs or the bytes first, or some
mixture. A mixture might improve already slow PIO
performance */
SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0],
packet_length >> 2 );
/* read the left over bytes */
if (packet_length & 3) {
int i;
byte *tail = (byte *)(NetRxPackets[0] +
(packet_length & ~3));
dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
for (i=0; i<(packet_length & 3); i++)
*tail++ = (byte) (leftover >> (8*i)) & 0xff;
}
#else
PRINTK3(" Reading %d words and %d byte(s) \n",
(packet_length >> 1 ), packet_length & 1 );
SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0],
packet_length >> 1);
#endif /* USE_32_BIT */
#if SMC_DEBUG > 2
printf("Receiving Packet\n");
print_packet( NetRxPackets[0], packet_length );
#endif
} else {
/* error ... */
/* TODO ? */
is_error = 1;
}
while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
udelay(1); /* Wait until not busy */
/* error or good, tell the card to get rid of this packet */
SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
udelay(1); /* Wait until not busy */
/* restore saved registers */
#ifndef CONFIG_XAENIAX
SMC_outb( dev, saved_pnr, PN_REG );
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
* the Allocate MMU command will end up written to the command register
* as well, which will lead to a problem.
*/
SMC_outl( dev, saved_pnr << 16, 0);
#endif
SMC_outw( dev, saved_ptr, PTR_REG );
if (!is_error) {
/* Pass the packet up to the protocol layers. */
NetReceive(NetRxPackets[0], packet_length);
return packet_length;
} else {
return 0;
}
}
#if 0
/*------------------------------------------------------------
. Modify a bit in the LAN91C111 register set
.-------------------------------------------------------------*/
static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
unsigned int bit, int val)
{
word regval;
SMC_SELECT_BANK( dev, bank );
regval = SMC_inw( dev, reg );
if (val)
regval |= bit;
else
regval &= ~bit;
SMC_outw( dev, regval, 0 );
return(regval);
}
/*------------------------------------------------------------
. Retrieve a bit in the LAN91C111 register set
.-------------------------------------------------------------*/
static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
{
SMC_SELECT_BANK( dev, bank );
if ( SMC_inw( dev, reg ) & bit)
return(1);
else
return(0);
}
/*------------------------------------------------------------
. Modify a LAN91C111 register (word access only)
.-------------------------------------------------------------*/
static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
{
SMC_SELECT_BANK( dev, bank );
SMC_outw( dev, val, reg );
}
/*------------------------------------------------------------
. Retrieve a LAN91C111 register (word access only)
.-------------------------------------------------------------*/
static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
{
SMC_SELECT_BANK( dev, bank );
return(SMC_inw( dev, reg ));
}
#endif /* 0 */
/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
#if (SMC_DEBUG > 2 )
/*------------------------------------------------------------
. Debugging function for viewing MII Management serial bitstream
.-------------------------------------------------------------*/
static void smc_dump_mii_stream (byte * bits, int size)
{
int i;
printf ("BIT#:");
for (i = 0; i < size; ++i) {
printf ("%d", i % 10);
}
printf ("\nMDOE:");
for (i = 0; i < size; ++i) {
if (bits[i] & MII_MDOE)
printf ("1");
else
printf ("0");
}
printf ("\nMDO :");
for (i = 0; i < size; ++i) {
if (bits[i] & MII_MDO)
printf ("1");
else
printf ("0");
}
printf ("\nMDI :");
for (i = 0; i < size; ++i) {
if (bits[i] & MII_MDI)
printf ("1");
else
printf ("0");
}
printf ("\n");
}
#endif
/*------------------------------------------------------------
. Reads a register from the MII Management serial interface
.-------------------------------------------------------------*/
#ifndef CONFIG_SMC91111_EXT_PHY
static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
{
int oldBank;
int i;
byte mask;
word mii_reg;
byte bits[64];
int clk_idx = 0;
int input_idx;
word phydata;
byte phyaddr = SMC_PHY_ADDR;
/* 32 consecutive ones on MDO to establish sync */
for (i = 0; i < 32; ++i)
bits[clk_idx++] = MII_MDOE | MII_MDO;
/* Start code <01> */
bits[clk_idx++] = MII_MDOE;
bits[clk_idx++] = MII_MDOE | MII_MDO;
/* Read command <10> */
bits[clk_idx++] = MII_MDOE | MII_MDO;
bits[clk_idx++] = MII_MDOE;
/* Output the PHY address, msb first */
mask = (byte) 0x10;
for (i = 0; i < 5; ++i) {
if (phyaddr & mask)
bits[clk_idx++] = MII_MDOE | MII_MDO;
else
bits[clk_idx++] = MII_MDOE;
/* Shift to next lowest bit */
mask >>= 1;
}
/* Output the phy register number, msb first */
mask = (byte) 0x10;
for (i = 0; i < 5; ++i) {
if (phyreg & mask)
bits[clk_idx++] = MII_MDOE | MII_MDO;
else
bits[clk_idx++] = MII_MDOE;
/* Shift to next lowest bit */
mask >>= 1;
}
/* Tristate and turnaround (2 bit times) */
bits[clk_idx++] = 0;
/*bits[clk_idx++] = 0; */
/* Input starts at this bit time */
input_idx = clk_idx;
/* Will input 16 bits */
for (i = 0; i < 16; ++i)
bits[clk_idx++] = 0;
/* Final clock bit */
bits[clk_idx++] = 0;
/* Save the current bank */
oldBank = SMC_inw (dev, BANK_SELECT);
/* Select bank 3 */
SMC_SELECT_BANK (dev, 3);
/* Get the current MII register value */
mii_reg = SMC_inw (dev, MII_REG);
/* Turn off all MII Interface bits */
mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
/* Clock all 64 cycles */
for (i = 0; i < sizeof bits; ++i) {
/* Clock Low - output data */
SMC_outw (dev, mii_reg | bits[i], MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Clock Hi - input data */
SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
}
/* Return to idle state */
/* Set clock to low, data to low, and output tristated */
SMC_outw (dev, mii_reg, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Restore original bank select */
SMC_SELECT_BANK (dev, oldBank);
/* Recover input data */
phydata = 0;
for (i = 0; i < 16; ++i) {
phydata <<= 1;
if (bits[input_idx++] & MII_MDI)
phydata |= 0x0001;
}
#if (SMC_DEBUG > 2 )
printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
phyaddr, phyreg, phydata);
smc_dump_mii_stream (bits, sizeof bits);
#endif
return (phydata);
}
/*------------------------------------------------------------
. Writes a register to the MII Management serial interface
.-------------------------------------------------------------*/
static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
word phydata)
{
int oldBank;
int i;
word mask;
word mii_reg;
byte bits[65];
int clk_idx = 0;
byte phyaddr = SMC_PHY_ADDR;
/* 32 consecutive ones on MDO to establish sync */
for (i = 0; i < 32; ++i)
bits[clk_idx++] = MII_MDOE | MII_MDO;
/* Start code <01> */
bits[clk_idx++] = MII_MDOE;
bits[clk_idx++] = MII_MDOE | MII_MDO;
/* Write command <01> */
bits[clk_idx++] = MII_MDOE;
bits[clk_idx++] = MII_MDOE | MII_MDO;
/* Output the PHY address, msb first */
mask = (byte) 0x10;
for (i = 0; i < 5; ++i) {
if (phyaddr & mask)
bits[clk_idx++] = MII_MDOE | MII_MDO;
else
bits[clk_idx++] = MII_MDOE;
/* Shift to next lowest bit */
mask >>= 1;
}
/* Output the phy register number, msb first */
mask = (byte) 0x10;
for (i = 0; i < 5; ++i) {
if (phyreg & mask)
bits[clk_idx++] = MII_MDOE | MII_MDO;
else
bits[clk_idx++] = MII_MDOE;
/* Shift to next lowest bit */
mask >>= 1;
}
/* Tristate and turnaround (2 bit times) */
bits[clk_idx++] = 0;
bits[clk_idx++] = 0;
/* Write out 16 bits of data, msb first */
mask = 0x8000;
for (i = 0; i < 16; ++i) {
if (phydata & mask)
bits[clk_idx++] = MII_MDOE | MII_MDO;
else
bits[clk_idx++] = MII_MDOE;
/* Shift to next lowest bit */
mask >>= 1;
}
/* Final clock bit (tristate) */
bits[clk_idx++] = 0;
/* Save the current bank */
oldBank = SMC_inw (dev, BANK_SELECT);
/* Select bank 3 */
SMC_SELECT_BANK (dev, 3);
/* Get the current MII register value */
mii_reg = SMC_inw (dev, MII_REG);
/* Turn off all MII Interface bits */
mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
/* Clock all cycles */
for (i = 0; i < sizeof bits; ++i) {
/* Clock Low - output data */
SMC_outw (dev, mii_reg | bits[i], MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Clock Hi - input data */
SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
}
/* Return to idle state */
/* Set clock to low, data to low, and output tristated */
SMC_outw (dev, mii_reg, MII_REG);
udelay (SMC_PHY_CLOCK_DELAY);
/* Restore original bank select */
SMC_SELECT_BANK (dev, oldBank);
#if (SMC_DEBUG > 2 )
printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
phyaddr, phyreg, phydata);
smc_dump_mii_stream (bits, sizeof bits);
#endif
}
#endif /* !CONFIG_SMC91111_EXT_PHY */
/*------------------------------------------------------------
. Waits the specified number of milliseconds - kernel friendly
.-------------------------------------------------------------*/
#ifndef CONFIG_SMC91111_EXT_PHY
static void smc_wait_ms(unsigned int ms)
{
udelay(ms*1000);
}
#endif /* !CONFIG_SMC91111_EXT_PHY */
/*------------------------------------------------------------
. Configures the specified PHY using Autonegotiation. Calls
. smc_phy_fixed() if the user has requested a certain config.
.-------------------------------------------------------------*/
#ifndef CONFIG_SMC91111_EXT_PHY
static void smc_phy_configure (struct eth_device *dev)
{
int timeout;
word my_phy_caps; /* My PHY capabilities */
word my_ad_caps; /* My Advertised capabilities */
word status = 0; /*;my status = 0 */
PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
/* Reset the PHY, setting all other bits to zero */
smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
/* Wait for the reset to complete, or time out */
timeout = 6; /* Wait up to 3 seconds */
while (timeout--) {
if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
& PHY_CNTL_RST)) {
/* reset complete */
break;
}
smc_wait_ms (500); /* wait 500 millisecs */
}
if (timeout < 1) {
printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
goto smc_phy_configure_exit;
}
/* Read PHY Register 18, Status Output */
/* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
/* Enable PHY Interrupts (for register 18) */
/* Interrupts listed here are disabled */
smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
/* Configure the Receive/Phy Control register */
SMC_SELECT_BANK (dev, 0);
SMC_outw (dev, RPC_DEFAULT, RPC_REG);
/* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
if (my_phy_caps & PHY_STAT_CAP_T4)
my_ad_caps |= PHY_AD_T4;
if (my_phy_caps & PHY_STAT_CAP_TXF)
my_ad_caps |= PHY_AD_TX_FDX;
if (my_phy_caps & PHY_STAT_CAP_TXH)
my_ad_caps |= PHY_AD_TX_HDX;
if (my_phy_caps & PHY_STAT_CAP_TF)
my_ad_caps |= PHY_AD_10_FDX;
if (my_phy_caps & PHY_STAT_CAP_TH)
my_ad_caps |= PHY_AD_10_HDX;
/* Update our Auto-Neg Advertisement Register */
smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
/* Read the register back. Without this, it appears that when */
/* auto-negotiation is restarted, sometimes it isn't ready and */
/* the link does not come up. */
smc_read_phy_register(dev, PHY_AD_REG);
PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
/* Restart auto-negotiation process in order to advertise my caps */
smc_write_phy_register (dev, PHY_CNTL_REG,
PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
/* Wait for the auto-negotiation to complete. This may take from */
/* 2 to 3 seconds. */
/* Wait for the reset to complete, or time out */
timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
while (timeout--) {
status = smc_read_phy_register (dev, PHY_STAT_REG);
if (status & PHY_STAT_ANEG_ACK) {
/* auto-negotiate complete */
break;
}
smc_wait_ms (500); /* wait 500 millisecs */
/* Restart auto-negotiation if remote fault */
if (status & PHY_STAT_REM_FLT) {
printf ("%s: PHY remote fault detected\n",
SMC_DEV_NAME);
/* Restart auto-negotiation */
printf ("%s: PHY restarting auto-negotiation\n",
SMC_DEV_NAME);
smc_write_phy_register (dev, PHY_CNTL_REG,
PHY_CNTL_ANEG_EN |
PHY_CNTL_ANEG_RST |
PHY_CNTL_SPEED |
PHY_CNTL_DPLX);
}
}
if (timeout < 1) {
printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
}
/* Fail if we detected an auto-negotiate remote fault */
if (status & PHY_STAT_REM_FLT) {
printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
}
/* Re-Configure the Receive/Phy Control register */
SMC_outw (dev, RPC_DEFAULT, RPC_REG);
smc_phy_configure_exit: ;
}
#endif /* !CONFIG_SMC91111_EXT_PHY */
#if SMC_DEBUG > 2
static void print_packet( byte * buf, int length )
{
int i;
int remainder;
int lines;
printf("Packet of length %d \n", length );
#if SMC_DEBUG > 3
lines = length / 16;
remainder = length % 16;
for ( i = 0; i < lines ; i ++ ) {
int cur;
for ( cur = 0; cur < 8; cur ++ ) {
byte a, b;
a = *(buf ++ );
b = *(buf ++ );
printf("%02x%02x ", a, b );
}
printf("\n");
}
for ( i = 0; i < remainder/2 ; i++ ) {
byte a, b;
a = *(buf ++ );
b = *(buf ++ );
printf("%02x%02x ", a, b );
}
printf("\n");
#endif
}
#endif
int smc91111_initialize(u8 dev_num, int base_addr)
{
struct smc91111_priv *priv;
struct eth_device *dev;
int i;
priv = malloc(sizeof(*priv));
if (!priv)
return 0;
dev = malloc(sizeof(*dev));
if (!dev) {
free(priv);
return 0;
}
memset(dev, 0, sizeof(*dev));
priv->dev_num = dev_num;
dev->priv = priv;
dev->iobase = base_addr;
swap_to(ETHERNET);
SMC_SELECT_BANK(dev, 1);
for (i = 0; i < 6; ++i)
dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
swap_to(FLASH);
dev->init = smc_init;
dev->halt = smc_halt;
dev->send = smc_send;
dev->recv = smc_rcv;
dev->write_hwaddr = smc_write_hwaddr;
sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
eth_register(dev);
return 0;
}
|
1001-study-uboot
|
drivers/net/smc91111.c
|
C
|
gpl3
| 35,165
|
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libnet.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
COBJS-$(CONFIG_CS8900) += cs8900.o
COBJS-$(CONFIG_TULIP) += dc2114x.o
COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o
COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
COBJS-$(CONFIG_DNET) += dnet.o
COBJS-$(CONFIG_E1000) += e1000.o
COBJS-$(CONFIG_E1000_SPI) += e1000_spi.o
COBJS-$(CONFIG_EEPRO100) += eepro100.o
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
COBJS-$(CONFIG_ETHOC) += ethoc.o
COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o
COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
COBJS-$(CONFIG_FTGMAC100) += ftgmac100.o
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
COBJS-$(CONFIG_GRETH) += greth.o
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
COBJS-$(CONFIG_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_MACB) += macb.o
COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
COBJS-$(CONFIG_MVGBE) += mvgbe.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_NETARMETH) += netarm_eth.o
COBJS-$(CONFIG_NETCONSOLE) += netconsole.o
COBJS-$(CONFIG_NS8382X) += ns8382x.o
COBJS-$(CONFIG_PCNET) += pcnet.o
COBJS-$(CONFIG_PLB2800_ETHER) += plb2800_eth.o
COBJS-$(CONFIG_RTL8139) += rtl8139.o
COBJS-$(CONFIG_RTL8169) += rtl8169.o
COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
COBJS-$(CONFIG_SMC91111) += smc91111.o
COBJS-$(CONFIG_SMC911X) += smc911x.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
COBJS-$(CONFIG_FMAN_ENET) += fsl_mdio.o
COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
COBJS-$(CONFIG_ULI526X) += uli526x.o
COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o
COBJS-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
COBJS := $(sort $(COBJS-y))
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/net/Makefile
|
Makefile
|
gpl3
| 3,438
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* based on - Driver for MV64360X ethernet ports
* Copyright (C) 2002 rabeeh@galileo.co.il
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __MVGBE_H__
#define __MVGBE_H__
/* PHY_BASE_ADR is board specific and can be configured */
#if defined (CONFIG_PHY_BASE_ADR)
#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
#else
#define PHY_BASE_ADR 0x08 /* default phy base addr */
#endif
/* Constants */
#define INT_CAUSE_UNMASK_ALL 0x0007ffff
#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
#define MRU_MASK 0xfff1ffff
#define PHYADR_MASK 0x0000001f
#define PHYREG_MASK 0x0000001f
#define QTKNBKT_DEF_VAL 0x3fffffff
#define QMTBS_DEF_VAL 0x000003ff
#define QTKNRT_DEF_VAL 0x0000fcff
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
#define MVGBE_REG_WR(adr, val) writel(val, &adr)
#define MVGBE_REG_RD(adr) readl(&adr)
#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
/* Default port configuration value */
#define PRT_CFG_VAL ( \
MVGBE_UCAST_MOD_NRML | \
MVGBE_DFLT_RXQ(RXUQ) | \
MVGBE_DFLT_RX_ARPQ(RXUQ) | \
MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \
MVGBE_RX_BC_IF_IP | \
MVGBE_RX_BC_IF_ARP | \
MVGBE_CPTR_TCP_FRMS_DIS | \
MVGBE_CPTR_UDP_FRMS_DIS | \
MVGBE_DFLT_RX_TCPQ(RXUQ) | \
MVGBE_DFLT_RX_UDPQ(RXUQ) | \
MVGBE_DFLT_RX_BPDUQ(RXUQ))
/* Default port extend configuration value */
#define PORT_CFG_EXTEND_VALUE \
MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
MVGBE_PARTITION_DIS | \
MVGBE_TX_CRC_GENERATION_EN
#define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
/* Default sdma control value */
#define PORT_SDMA_CFG_VALUE ( \
MVGBE_RX_BURST_SIZE_16_64BIT | \
MVGBE_BLM_RX_NO_SWAP | \
MVGBE_BLM_TX_NO_SWAP | \
GT_MVGBE_IPG_INT_RX(RXUQ) | \
MVGBE_TX_BURST_SIZE_16_64BIT)
/* Default port serial control value */
#ifndef PORT_SERIAL_CONTROL_VALUE
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_EN_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
#endif
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
/* MAC accepet/reject macros */
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
#define MV_RXQ_DESC_ALIGNED_SIZE \
(((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Port serial status reg (PSR) */
#define MVGBE_INTERFACE_GMII_MII 0
#define MVGBE_INTERFACE_PCM 1
#define MVGBE_LINK_IS_DOWN 0
#define MVGBE_LINK_IS_UP (1 << 1)
#define MVGBE_PORT_AT_HALF_DUPLEX 0
#define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2)
#define MVGBE_RX_FLOW_CTRL_DISD 0
#define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
#define MVGBE_GMII_SPEED_100_10 0
#define MVGBE_GMII_SPEED_1000 (1 << 4)
#define MVGBE_MII_SPEED_10 0
#define MVGBE_MII_SPEED_100 (1 << 5)
#define MVGBE_NO_TX 0
#define MVGBE_TX_IN_PROGRESS (1 << 7)
#define MVGBE_BYPASS_NO_ACTIVE 0
#define MVGBE_BYPASS_ACTIVE (1 << 8)
#define MVGBE_PORT_NOT_AT_PARTN_STT 0
#define MVGBE_PORT_AT_PARTN_STT (1 << 9)
#define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0
#define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10)
/* These macros describes the Port configuration reg (Px_cR) bits */
#define MVGBE_UCAST_MOD_NRML 0
#define MVGBE_UNICAST_PROMISCUOUS_MODE 1
#define MVGBE_DFLT_RXQ(_x) (_x << 1)
#define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4)
#define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0
#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
#define MVGBE_RX_BC_IF_IP 0
#define MVGBE_REJECT_BC_IF_IP (1 << 8)
#define MVGBE_RX_BC_IF_ARP 0
#define MVGBE_REJECT_BC_IF_ARP (1 << 9)
#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
#define MVGBE_CPTR_TCP_FRMS_DIS 0
#define MVGBE_CPTR_TCP_FRMS_EN (1 << 14)
#define MVGBE_CPTR_UDP_FRMS_DIS 0
#define MVGBE_CPTR_UDP_FRMS_EN (1 << 15)
#define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16)
#define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19)
#define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
#define MVGBE_CLASSIFY_EN 1
#define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
#define MVGBE_PARTITION_DIS 0
#define MVGBE_PARTITION_EN (1 << 2)
#define MVGBE_TX_CRC_GENERATION_EN 0
#define MVGBE_TX_CRC_GENERATION_DIS (1 << 3)
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
#define MVGBE_RIFB 1
#define MVGBE_RX_BURST_SIZE_1_64BIT 0
#define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
#define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
#define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
#define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
#define MVGBE_BLM_RX_NO_SWAP (1 << 4)
#define MVGBE_BLM_RX_BYTE_SWAP 0
#define MVGBE_BLM_TX_NO_SWAP (1 << 5)
#define MVGBE_BLM_TX_BYTE_SWAP 0
#define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
#define MVGBE_DESCRIPTORS_NO_SWAP 0
#define MVGBE_TX_BURST_SIZE_1_64BIT 0
#define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
#define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
#define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
#define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
/* These macros describes the Port serial control reg (PSCR) bits */
#define MVGBE_SERIAL_PORT_DIS 0
#define MVGBE_SERIAL_PORT_EN 1
#define MVGBE_FORCE_LINK_PASS (1 << 1)
#define MVGBE_DO_NOT_FORCE_LINK_PASS 0
#define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0
#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
#define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
#define MVGBE_ADV_NO_FLOW_CTRL 0
#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
#define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
#define MVGBE_FORCE_BP_MODE_NO_JAM 0
#define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
#define MVGBE_FORCE_LINK_FAIL 0
#define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
#define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
#define MVGBE_EN_AUTO_NEG_SPEED_GMII 0
#define MVGBE_DTE_ADV_0 0
#define MVGBE_DTE_ADV_1 (1 << 14)
#define MVGBE_MIIPHY_MAC_MODE 0
#define MVGBE_MIIPHY_PHY_MODE (1 << 15)
#define MVGBE_AUTO_NEG_NO_CHANGE 0
#define MVGBE_RESTART_AUTO_NEG (1 << 16)
#define MVGBE_MAX_RX_PACKET_1518BYTE 0
#define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
#define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
#define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
#define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
#define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
#define MVGBE_SET_EXT_LOOPBACK (1 << 20)
#define MVGBE_CLR_EXT_LOOPBACK 0
#define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21)
#define MVGBE_SET_HALF_DUPLEX_MODE 0
#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
#define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
#define MVGBE_SET_GMII_SPEED_TO_10_100 0
#define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
#define MVGBE_SET_MII_SPEED_TO_10 0
#define MVGBE_SET_MII_SPEED_TO_100 (1 << 24)
/* SMI register fields */
#define MVGBE_PHY_SMI_TIMEOUT 10000
#define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */
#define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS)
#define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
#define MVGBE_PHY_SMI_DEV_ADDR_MASK \
(PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
#define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
#define MVGBE_SMI_REG_ADDR_MASK \
(PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
#define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
#define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS)
#define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS)
#define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS)
#define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
#define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
#define MVGBE_ERROR_SUMMARY 1
/* Tx & Rx descriptors command */
#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31)
/* Tx descriptors status */
#define MVGBE_LC_ERROR 0
#define MVGBE_UR_ERROR (1 << 1)
#define MVGBE_RL_ERROR (1 << 2)
#define MVGBE_LLC_SNAP_FORMAT (1 << 9)
#define MVGBE_TX_LAST_FRAME (1 << 20)
/* Rx descriptors status */
#define MVGBE_CRC_ERROR 0
#define MVGBE_OVERRUN_ERROR (1 << 1)
#define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
#define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
#define MVGBE_VLAN_TAGGED (1 << 19)
#define MVGBE_BPDU_FRAME (1 << 20)
#define MVGBE_TCP_FRAME_OVER_IP_V_4 0
#define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
#define MVGBE_OTHER_FRAME_TYPE (1 << 22)
#define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23)
#define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24)
#define MVGBE_FRAME_HEADER_OK (1 << 25)
#define MVGBE_RX_LAST_DESC (1 << 26)
#define MVGBE_RX_FIRST_DESC (1 << 27)
#define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
#define MVGBE_RX_EN_INTERRUPT (1 << 29)
#define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30)
/* Rx descriptors byte count */
#define MVGBE_FRAME_FRAGMENTED (1 << 2)
/* Tx descriptors command */
#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
#define MVGBE_FRAME_SET_TO_VLAN (1 << 15)
#define MVGBE_TCP_FRAME 0
#define MVGBE_UDP_FRAME (1 << 16)
#define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
#define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
#define MVGBE_ZERO_PADDING (1 << 19)
#define MVGBE_TX_LAST_DESC (1 << 20)
#define MVGBE_TX_FIRST_DESC (1 << 21)
#define MVGBE_GEN_CRC (1 << 22)
#define MVGBE_TX_EN_INTERRUPT (1 << 23)
#define MVGBE_AUTO_MODE (1 << 30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
#define EBAR_TARGET_DRAM 0x00000000
#define EBAR_TARGET_DEVICE 0x00000001
#define EBAR_TARGET_CBS 0x00000002
#define EBAR_TARGET_PCI0 0x00000003
#define EBAR_TARGET_PCI1 0x00000004
#define EBAR_TARGET_CUNIT 0x00000005
#define EBAR_TARGET_AUNIT 0x00000006
#define EBAR_TARGET_GUNIT 0x00000007
/* Window attrib */
#define EBAR_DRAM_CS0 0x00000E00
#define EBAR_DRAM_CS1 0x00000D00
#define EBAR_DRAM_CS2 0x00000B00
#define EBAR_DRAM_CS3 0x00000700
/* DRAM Target interface */
#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
/* Device Bus Target interface */
#define EBAR_DEVICE_DEVCS0 0x00001E00
#define EBAR_DEVICE_DEVCS1 0x00001D00
#define EBAR_DEVICE_DEVCS2 0x00001B00
#define EBAR_DEVICE_DEVCS3 0x00001700
#define EBAR_DEVICE_BOOTCS3 0x00000F00
/* PCI Target interface */
#define EBAR_PCI_BYTE_SWAP 0x00000000
#define EBAR_PCI_NO_SWAP 0x00000100
#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
#define EBAR_PCI_WORD_SWAP 0x00000300
#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
#define EBAR_PCI_IO_SPACE 0x00000000
#define EBAR_PCI_MEMORY_SPACE 0x00000800
#define EBAR_PCI_REQ64_FORCE 0x00000000
#define EBAR_PCI_REQ64_SIZE 0x00001000
/* Window access control */
#define EWIN_ACCESS_NOT_ALLOWED 0
#define EWIN_ACCESS_READ_ONLY 1
#define EWIN_ACCESS_FULL ((1 << 1) | 1)
/* structures represents Controller registers */
struct mvgbe_barsz {
u32 bar;
u32 size;
};
struct mvgbe_rxcdp {
struct mvgbe_rxdesc *rxcdp;
u32 rxcdp_pad[3];
};
struct mvgbe_tqx {
u32 qxttbc;
u32 tqxtbc;
u32 tqxac;
u32 tqxpad;
};
struct mvgbe_registers {
u32 phyadr;
u32 smi;
u32 euda;
u32 eudid;
u8 pad1[0x080 - 0x00c - 4];
u32 euic;
u32 euim;
u8 pad2[0x094 - 0x084 - 4];
u32 euea;
u32 euiae;
u8 pad3[0x0b0 - 0x098 - 4];
u32 euc;
u8 pad3a[0x200 - 0x0b0 - 4];
struct mvgbe_barsz barsz[6];
u8 pad4[0x280 - 0x22c - 4];
u32 ha_remap[4];
u32 bare;
u32 epap;
u8 pad5[0x400 - 0x294 - 4];
u32 pxc;
u32 pxcx;
u32 mii_ser_params;
u8 pad6[0x410 - 0x408 - 4];
u32 evlane;
u32 macal;
u32 macah;
u32 sdc;
u32 dscp[7];
u32 psc0;
u32 vpt2p;
u32 ps0;
u32 tqc;
u32 psc1;
u32 ps1;
u32 mrvl_header;
u8 pad7[0x460 - 0x454 - 4];
u32 ic;
u32 ice;
u32 pim;
u32 peim;
u8 pad8[0x474 - 0x46c - 4];
u32 pxtfut;
u32 pad9;
u32 pxmfs;
u32 pad10;
u32 pxdfc;
u32 pxofc;
u8 pad11[0x494 - 0x488 - 4];
u32 peuiae;
u8 pad12[0x4bc - 0x494 - 4];
u32 eth_type_prio;
u8 pad13[0x4dc - 0x4bc - 4];
u32 tqfpc;
u32 pttbrc;
u32 tqc1;
u32 pmtu;
u32 pmtbs;
u8 pad14[0x60c - 0x4ec - 4];
struct mvgbe_rxcdp rxcdp[7];
struct mvgbe_rxdesc *rxcdp7;
u32 rqc;
struct mvgbe_txdesc *tcsdp;
u8 pad15[0x6c0 - 0x684 - 4];
struct mvgbe_txdesc *tcqdp[8];
u8 pad16[0x700 - 0x6dc - 4];
struct mvgbe_tqx tqx[8];
u32 pttbc;
u8 pad17[0x7a8 - 0x780 - 4];
u32 tqxipg0;
u32 pad18[3];
u32 tqxipg1;
u8 pad19[0x7c0 - 0x7b8 - 4];
u32 hitkninlopkt;
u32 hitkninasyncpkt;
u32 lotkninasyncpkt;
u32 pad20;
u32 ts;
u8 pad21[0x3000 - 0x27d0 - 4];
u32 pad20_1[32]; /* mib counter registes */
u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
u32 dfsmt[64];
u32 dfomt[64];
u32 dfut[4];
u8 pad23[0xe20c0 - 0x7360c - 4];
u32 pmbus_top_arbiter;
};
/* structures/enums needed by driver */
enum mvgbe_adrwin {
MVGBE_WIN0,
MVGBE_WIN1,
MVGBE_WIN2,
MVGBE_WIN3,
MVGBE_WIN4,
MVGBE_WIN5
};
enum mvgbe_target {
MVGBE_TARGET_DRAM,
MVGBE_TARGET_DEV,
MVGBE_TARGET_CBS,
MVGBE_TARGET_PCI0,
MVGBE_TARGET_PCI1
};
struct mvgbe_winparam {
enum mvgbe_adrwin win; /* Window number */
enum mvgbe_target target; /* System targets */
u16 attrib; /* BAR attrib. See above macros */
u32 base_addr; /* Window base address in u32 form */
u32 high_addr; /* Window high address in u32 form */
u32 size; /* Size in MBytes. Must be % 64Kbyte. */
int enable; /* Enable/disable access to the window. */
u16 access_ctrl; /*Access ctrl register. see above macros */
};
struct mvgbe_rxdesc {
u32 cmd_sts; /* Descriptor command status */
u16 buf_size; /* Buffer size */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer pointer */
struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
struct mvgbe_txdesc {
u32 cmd_sts; /* Descriptor command status */
u16 l4i_chk; /* CPU provided TCP Checksum */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer ptr */
struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
struct mvgbe_device {
struct eth_device dev;
struct mvgbe_registers *regs;
struct mvgbe_txdesc *p_txdesc;
struct mvgbe_rxdesc *p_rxdesc;
struct mvgbe_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
};
#endif /* __MVGBE_H__ */
|
1001-study-uboot
|
drivers/net/mvgbe.h
|
C
|
gpl3
| 16,087
|
/*
* (C) Copyright 2003 - 2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Derived from the MPC8xx driver's header file.
*/
#ifndef __MPC512X_FEC_H
#define __MPC512X_FEC_H
#include <common.h>
/* Receive & Transmit Buffer Descriptor definitions */
typedef struct BufferDescriptor {
u16 status;
u16 dataLength;
u32 dataPointer;
} FEC_RBD;
typedef struct {
u16 status;
u16 dataLength;
u32 dataPointer;
} FEC_TBD;
/* private structure */
typedef enum {
SEVENWIRE, /* 7-wire */
MII10, /* MII 10Mbps */
MII100 /* MII 100Mbps */
} xceiver_type;
/* BD Numer definitions */
#define FEC_TBD_NUM 48 /* The user can adjust this value */
#define FEC_RBD_NUM 32 /* The user can adjust this value */
/* packet size limit */
#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */
/* Buffer size must be evenly divisible by 16 */
#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
typedef struct {
u8 frame[FEC_BUFFER_SIZE];
} mpc512x_frame;
typedef struct {
FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */
FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */
mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */
} mpc512x_buff_descs;
typedef struct {
volatile fec512x_t *eth;
xceiver_type xcv_type; /* transceiver type */
mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */
u16 rbdIndex; /* next receive BD to read */
u16 tbdIndex; /* next transmit BD to send */
u16 usedTbdIndex; /* next transmit BD to clean */
u16 cleanTbdNum; /* the number of available transmit BDs */
} mpc512x_fec_priv;
/* RBD bits definitions */
#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */
#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */
#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */
#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */
#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */
#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */
#define FEC_RBD_LG 0x0020 /* Frame length violation */
#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */
#define FEC_RBD_SH 0x0008 /* Short frame */
#define FEC_RBD_CR 0x0004 /* CRC error */
#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */
#define FEC_RBD_TR 0x0001 /* Frame is truncated */
#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
FEC_RBD_OV | FEC_RBD_TR)
/* TBD bits definitions */
#define FEC_TBD_READY 0x8000 /* Buffer is ready */
#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */
#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */
#define FEC_TBD_TC 0x0400 /* Transmit the CRC */
#define FEC_TBD_ABC 0x0200 /* Append bad CRC */
/* MII-related definitios */
#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
#endif /* __MPC512X_FEC_H */
|
1001-study-uboot
|
drivers/net/mpc512x_fec.h
|
C
|
gpl3
| 3,301
|