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/*
* Cirrus Logic CS8900A Ethernet
*
* (C) 2009 Ben Warren , biggerbadderben@gmail.com
* Converted to use CONFIG_NET_MULTI API
*
* (C) 2003 Wolfgang Denk, wd@denx.de
* Extension to synchronize ethaddr environment variable
* against value in EEPROM
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Copyright (C) 1999 Ben Williamson <benw@pobox.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is loaded into SRAM in bootstrap mode, where it waits
* for commands on UART1 to read and write memory, jump to code etc.
* A design goal for this program is to be entirely independent of the
* target board. Anything with a CL-PS7111 or EP7211 should be able to run
* this code in bootstrap mode. All the board specifics can be handled on
* the host.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <net.h>
#include <malloc.h>
#include "cs8900.h"
#undef DEBUG
/* packet page register access functions */
#ifdef CONFIG_CS8900_BUS32
#define REG_WRITE(v, a) writel((v),(a))
#define REG_READ(a) readl((a))
/* we don't need 16 bit initialisation on 32 bit bus */
#define get_reg_init_bus(r,d) get_reg((r),(d))
#else
#define REG_WRITE(v, a) writew((v),(a))
#define REG_READ(a) readw((a))
static u16 get_reg_init_bus(struct eth_device *dev, int regno)
{
/* force 16 bit busmode */
struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
readb(iob);
readb(iob + 1);
readb(iob);
readb(iob + 1);
readb(iob);
REG_WRITE(regno, &priv->regs->pptr);
return REG_READ(&priv->regs->pdata);
}
#endif
static u16 get_reg(struct eth_device *dev, int regno)
{
struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
REG_WRITE(regno, &priv->regs->pptr);
return REG_READ(&priv->regs->pdata);
}
static void put_reg(struct eth_device *dev, int regno, u16 val)
{
struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
REG_WRITE(regno, &priv->regs->pptr);
REG_WRITE(val, &priv->regs->pdata);
}
static void cs8900_reset(struct eth_device *dev)
{
int tmo;
u16 us;
/* reset NIC */
put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
/* wait for 200ms */
udelay(200000);
/* Wait until the chip is reset */
tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
/*NOP*/;
}
static void cs8900_reginit(struct eth_device *dev)
{
/* receive only error free packets addressed to this card */
put_reg(dev, PP_RxCTL,
PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
/* do not generate any interrupts on receive operations */
put_reg(dev, PP_RxCFG, 0);
/* do not generate any interrupts on transmit operations */
put_reg(dev, PP_TxCFG, 0);
/* do not generate any interrupts on buffer operations */
put_reg(dev, PP_BufCFG, 0);
/* enable transmitter/receiver mode */
put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
}
void cs8900_get_enetaddr(struct eth_device *dev)
{
int i;
/* verify chip id */
if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
return;
cs8900_reset(dev);
if ((get_reg(dev, PP_SelfSTAT) &
(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
(PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
/* Load the MAC from EEPROM */
for (i = 0; i < 3; i++) {
u32 Addr;
Addr = get_reg(dev, PP_IA + i * 2);
dev->enetaddr[i * 2] = Addr & 0xFF;
dev->enetaddr[i * 2 + 1] = Addr >> 8;
}
}
}
void cs8900_halt(struct eth_device *dev)
{
/* disable transmitter/receiver mode */
put_reg(dev, PP_LineCTL, 0);
/* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
get_reg_init_bus(dev, PP_ChipID);
}
static int cs8900_init(struct eth_device *dev, bd_t * bd)
{
uchar *enetaddr = dev->enetaddr;
u16 id;
/* verify chip id */
id = get_reg_init_bus(dev, PP_ChipID);
if (id != 0x630e) {
printf ("CS8900 Ethernet chip not found: "
"ID=0x%04x instead 0x%04x\n", id, 0x630e);
return 1;
}
cs8900_reset (dev);
/* set the ethernet address */
put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
cs8900_reginit(dev);
return 0;
}
/* Get a data block via Ethernet */
static int cs8900_recv(struct eth_device *dev)
{
int i;
u16 rxlen;
u16 *addr;
u16 status;
struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
status = get_reg(dev, PP_RER);
if ((status & PP_RER_RxOK) == 0)
return 0;
status = REG_READ(&priv->regs->rtdata);
rxlen = REG_READ(&priv->regs->rtdata);
if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
debug("packet too big!\n");
for (addr = (u16 *) NetRxPackets[0], i = rxlen >> 1; i > 0;
i--)
*addr++ = REG_READ(&priv->regs->rtdata);
if (rxlen & 1)
*addr++ = REG_READ(&priv->regs->rtdata);
/* Pass the packet up to the protocol layers. */
NetReceive (NetRxPackets[0], rxlen);
return rxlen;
}
/* Send a data block via Ethernet. */
static int cs8900_send(struct eth_device *dev,
volatile void *packet, int length)
{
volatile u16 *addr;
int tmo;
u16 s;
struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
retry:
/* initiate a transmit sequence */
REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
REG_WRITE(length, &priv->regs->txlen);
/* Test to see if the chip has allocated memory for the packet */
if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
/* Oops... this should not happen! */
debug("cs: unable to send packet; retrying...\n");
for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
get_timer(0) < tmo;)
/*NOP*/;
cs8900_reset(dev);
cs8900_reginit(dev);
goto retry;
}
/* Write the contents of the packet */
/* assume even number of bytes */
for (addr = packet; length > 0; length -= 2)
REG_WRITE(*addr++, &priv->regs->rtdata);
/* wait for transfer to succeed */
tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
if (get_timer(0) >= tmo)
break;
}
/* nothing */ ;
if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
debug("\ntransmission error %#x\n", s);
}
return 0;
}
static void cs8900_e2prom_ready(struct eth_device *dev)
{
while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
;
}
/***********************************************************/
/* read a 16-bit word out of the EEPROM */
/***********************************************************/
int cs8900_e2prom_read(struct eth_device *dev,
u8 addr, u16 *value)
{
cs8900_e2prom_ready(dev);
put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
cs8900_e2prom_ready(dev);
*value = get_reg(dev, PP_EEData);
return 0;
}
/***********************************************************/
/* write a 16-bit word into the EEPROM */
/***********************************************************/
int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
{
cs8900_e2prom_ready(dev);
put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
cs8900_e2prom_ready(dev);
put_reg(dev, PP_EEData, value);
put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
cs8900_e2prom_ready(dev);
put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
cs8900_e2prom_ready(dev);
return 0;
}
int cs8900_initialize(u8 dev_num, int base_addr)
{
struct eth_device *dev;
struct cs8900_priv *priv;
dev = malloc(sizeof(*dev));
if (!dev) {
return 0;
}
memset(dev, 0, sizeof(*dev));
priv = malloc(sizeof(*priv));
if (!priv) {
free(dev);
return 0;
}
memset(priv, 0, sizeof(*priv));
priv->regs = (struct cs8900_regs *)base_addr;
dev->iobase = base_addr;
dev->priv = priv;
dev->init = cs8900_init;
dev->halt = cs8900_halt;
dev->send = cs8900_send;
dev->recv = cs8900_recv;
/* Load MAC address from EEPROM */
cs8900_get_enetaddr(dev);
sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
eth_register(dev);
return 0;
}
|
1001-study-uboot
|
drivers/net/cs8900.c
|
C
|
gpl3
| 8,725
|
/*
* SMSC LAN9[12]1[567] Network driver
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SMC911X_H_
#define _SMC911X_H_
#include <linux/types.h>
#define DRIVERNAME "smc911x"
#if defined (CONFIG_SMC911X_32_BIT) && \
defined (CONFIG_SMC911X_16_BIT)
#error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
CONFIG_SMC911X_16_BIT shall be set"
#endif
#if defined (CONFIG_SMC911X_32_BIT)
static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
{
return *(volatile u32*)(dev->iobase + offset);
}
u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
__attribute__((weak, alias("__smc911x_reg_read")));
static inline void __smc911x_reg_write(struct eth_device *dev,
u32 offset, u32 val)
{
*(volatile u32*)(dev->iobase + offset) = val;
}
void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
__attribute__((weak, alias("__smc911x_reg_write")));
#elif defined (CONFIG_SMC911X_16_BIT)
static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
{
volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
}
static inline void smc911x_reg_write(struct eth_device *dev,
u32 offset, u32 val)
{
*(volatile u16 *)(dev->iobase + offset) = (u16)val;
*(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
}
#else
#error "SMC911X: undefined bus width"
#endif /* CONFIG_SMC911X_16_BIT */
/* Below are the register offsets and bit definitions
* of the Lan911x memory space
*/
#define RX_DATA_FIFO 0x00
#define TX_DATA_FIFO 0x20
#define TX_CMD_A_INT_ON_COMP 0x80000000
#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
#define TX_CMD_A_INT_FIRST_SEG 0x00002000
#define TX_CMD_A_INT_LAST_SEG 0x00001000
#define TX_CMD_A_BUF_SIZE 0x000007FF
#define TX_CMD_B_PKT_TAG 0xFFFF0000
#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
#define TX_CMD_B_DISABLE_PADDING 0x00001000
#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
#define RX_STATUS_FIFO 0x40
#define RX_STS_PKT_LEN 0x3FFF0000
#define RX_STS_ES 0x00008000
#define RX_STS_BCST 0x00002000
#define RX_STS_LEN_ERR 0x00001000
#define RX_STS_RUNT_ERR 0x00000800
#define RX_STS_MCAST 0x00000400
#define RX_STS_TOO_LONG 0x00000080
#define RX_STS_COLL 0x00000040
#define RX_STS_ETH_TYPE 0x00000020
#define RX_STS_WDOG_TMT 0x00000010
#define RX_STS_MII_ERR 0x00000008
#define RX_STS_DRIBBLING 0x00000004
#define RX_STS_CRC_ERR 0x00000002
#define RX_STATUS_FIFO_PEEK 0x44
#define TX_STATUS_FIFO 0x48
#define TX_STS_TAG 0xFFFF0000
#define TX_STS_ES 0x00008000
#define TX_STS_LOC 0x00000800
#define TX_STS_NO_CARR 0x00000400
#define TX_STS_LATE_COLL 0x00000200
#define TX_STS_MANY_COLL 0x00000100
#define TX_STS_COLL_CNT 0x00000078
#define TX_STS_MANY_DEFER 0x00000004
#define TX_STS_UNDERRUN 0x00000002
#define TX_STS_DEFERRED 0x00000001
#define TX_STATUS_FIFO_PEEK 0x4C
#define ID_REV 0x50
#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
#define ID_REV_REV_ID 0x0000FFFF /* RO */
#define INT_CFG 0x54
#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
#define INT_CFG_INT_DEAS_CLR 0x00004000
#define INT_CFG_INT_DEAS_STS 0x00002000
#define INT_CFG_IRQ_INT 0x00001000 /* RO */
#define INT_CFG_IRQ_EN 0x00000100 /* R/W */
/* R/W Not Affected by SW Reset */
#define INT_CFG_IRQ_POL 0x00000010
/* R/W Not Affected by SW Reset */
#define INT_CFG_IRQ_TYPE 0x00000001
#define INT_STS 0x58
#define INT_STS_SW_INT 0x80000000 /* R/WC */
#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
#define INT_STS_RXDF_INT 0x00400000 /* R/WC */
#define INT_STS_TX_IOC 0x00200000 /* R/WC */
#define INT_STS_RXD_INT 0x00100000 /* R/WC */
#define INT_STS_GPT_INT 0x00080000 /* R/WC */
#define INT_STS_PHY_INT 0x00040000 /* RO */
#define INT_STS_PME_INT 0x00020000 /* R/WC */
#define INT_STS_TXSO 0x00010000 /* R/WC */
#define INT_STS_RWT 0x00008000 /* R/WC */
#define INT_STS_RXE 0x00004000 /* R/WC */
#define INT_STS_TXE 0x00002000 /* R/WC */
/*#define INT_STS_ERX 0x00001000*/ /* R/WC */
#define INT_STS_TDFU 0x00000800 /* R/WC */
#define INT_STS_TDFO 0x00000400 /* R/WC */
#define INT_STS_TDFA 0x00000200 /* R/WC */
#define INT_STS_TSFF 0x00000100 /* R/WC */
#define INT_STS_TSFL 0x00000080 /* R/WC */
/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */
#define INT_STS_RDFO 0x00000040 /* R/WC */
#define INT_STS_RDFL 0x00000020 /* R/WC */
#define INT_STS_RSFF 0x00000010 /* R/WC */
#define INT_STS_RSFL 0x00000008 /* R/WC */
#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
#define INT_EN 0x5C
#define INT_EN_SW_INT_EN 0x80000000 /* R/W */
#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
#define INT_EN_PME_INT_EN 0x00020000 /* R/W */
#define INT_EN_TXSO_EN 0x00010000 /* R/W */
#define INT_EN_RWT_EN 0x00008000 /* R/W */
#define INT_EN_RXE_EN 0x00004000 /* R/W */
#define INT_EN_TXE_EN 0x00002000 /* R/W */
/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */
#define INT_EN_TDFU_EN 0x00000800 /* R/W */
#define INT_EN_TDFO_EN 0x00000400 /* R/W */
#define INT_EN_TDFA_EN 0x00000200 /* R/W */
#define INT_EN_TSFF_EN 0x00000100 /* R/W */
#define INT_EN_TSFL_EN 0x00000080 /* R/W */
/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */
#define INT_EN_RDFO_EN 0x00000040 /* R/W */
#define INT_EN_RDFL_EN 0x00000020 /* R/W */
#define INT_EN_RSFF_EN 0x00000010 /* R/W */
#define INT_EN_RSFL_EN 0x00000008 /* R/W */
#define INT_EN_GPIO2_INT 0x00000004 /* R/W */
#define INT_EN_GPIO1_INT 0x00000002 /* R/W */
#define INT_EN_GPIO0_INT 0x00000001 /* R/W */
#define BYTE_TEST 0x64
#define FIFO_INT 0x68
#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
#define RX_CFG 0x6C
#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
#define RX_CFG_RX_DUMP 0x00008000 /* R/W */
#define RX_CFG_RXDOFF 0x00001F00 /* R/W */
/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
#define TX_CFG 0x70
/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
/* R/W Self Clearing */
/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/
#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
#define TX_CFG_TXSAO 0x00000004 /* R/W */
#define TX_CFG_TX_ON 0x00000002 /* R/W */
#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
#define HW_CFG 0x74
#define HW_CFG_TTM 0x00200000 /* R/W */
#define HW_CFG_SF 0x00100000 /* R/W */
#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
#define HW_CFG_TR 0x00003000 /* R/W */
#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
#define HW_CFG_SMI_SEL 0x00000010 /* R/W */
#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
#define HW_CFG_SRST_TO 0x00000002 /* RO */
#define HW_CFG_SRST 0x00000001 /* Self Clearing */
#define RX_DP_CTRL 0x78
#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
#define RX_FIFO_INF 0x7C
#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
#define TX_FIFO_INF 0x80
#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
#define PMT_CTRL 0x84
#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
#define PMT_CTRL_ED_EN 0x00000100 /* R/W */
/* R/W Not Affected by SW Reset */
#define PMT_CTRL_PME_TYPE 0x00000040
#define PMT_CTRL_WUPS 0x00000030 /* R/WC */
#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
#define PMT_CTRL_PME_IND 0x00000008 /* R/W */
#define PMT_CTRL_PME_POL 0x00000004 /* R/W */
/* R/W Not Affected by SW Reset */
#define PMT_CTRL_PME_EN 0x00000002
#define PMT_CTRL_READY 0x00000001 /* RO */
#define GPIO_CFG 0x88
#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
#define GPT_CFG 0x8C
#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
#define GPT_CNT 0x90
#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
#define ENDIAN 0x98
#define FREE_RUN 0x9C
#define RX_DROP 0xA0
#define MAC_CSR_CMD 0xA4
#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
#define MAC_CSR_DATA 0xA8
#define AFC_CFG 0xAC
#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
#define AFC_CFG_FCMULT 0x00000008 /* R/W */
#define AFC_CFG_FCBRD 0x00000004 /* R/W */
#define AFC_CFG_FCADD 0x00000002 /* R/W */
#define AFC_CFG_FCANY 0x00000001 /* R/W */
#define E2P_CMD 0xB0
#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
#define E2P_DATA 0xB4
#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
/* end of LAN register offsets and bit definitions */
/* MAC Control and Status registers */
#define MAC_CR 0x01 /* R/W */
/* MAC_CR - MAC Control Register */
#define MAC_CR_RXALL 0x80000000
/* TODO: delete this bit? It is not described in the data sheet. */
#define MAC_CR_HBDIS 0x10000000
#define MAC_CR_RCVOWN 0x00800000
#define MAC_CR_LOOPBK 0x00200000
#define MAC_CR_FDPX 0x00100000
#define MAC_CR_MCPAS 0x00080000
#define MAC_CR_PRMS 0x00040000
#define MAC_CR_INVFILT 0x00020000
#define MAC_CR_PASSBAD 0x00010000
#define MAC_CR_HFILT 0x00008000
#define MAC_CR_HPFILT 0x00002000
#define MAC_CR_LCOLL 0x00001000
#define MAC_CR_BCAST 0x00000800
#define MAC_CR_DISRTY 0x00000400
#define MAC_CR_PADSTR 0x00000100
#define MAC_CR_BOLMT_MASK 0x000000C0
#define MAC_CR_DFCHK 0x00000020
#define MAC_CR_TXEN 0x00000008
#define MAC_CR_RXEN 0x00000004
#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
#define HASHH 0x04 /* R/W */
#define HASHL 0x05 /* R/W */
#define MII_ACC 0x06 /* R/W */
#define MII_ACC_PHY_ADDR 0x0000F800
#define MII_ACC_MIIRINDA 0x000007C0
#define MII_ACC_MII_WRITE 0x00000002
#define MII_ACC_MII_BUSY 0x00000001
#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
#define FLOW 0x08 /* R/W */
#define FLOW_FCPT 0xFFFF0000
#define FLOW_FCPASS 0x00000004
#define FLOW_FCEN 0x00000002
#define FLOW_FCBSY 0x00000001
#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
#define VLAN1_VTI1 0x0000ffff
#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
#define VLAN2_VTI2 0x0000ffff
#define WUFF 0x0B /* WO */
#define WUCSR 0x0C /* R/W */
#define WUCSR_GUE 0x00000200
#define WUCSR_WUFR 0x00000040
#define WUCSR_MPR 0x00000020
#define WUCSR_WAKE_EN 0x00000004
#define WUCSR_MPEN 0x00000002
/* Chip ID values */
#define CHIP_89218 0x218a
#define CHIP_9115 0x115
#define CHIP_9116 0x116
#define CHIP_9117 0x117
#define CHIP_9118 0x118
#define CHIP_9211 0x9211
#define CHIP_9215 0x115a
#define CHIP_9216 0x116a
#define CHIP_9217 0x117a
#define CHIP_9218 0x118a
#define CHIP_9220 0x9220
#define CHIP_9221 0x9221
struct chip_id {
u16 id;
char *name;
};
static const struct chip_id chip_ids[] = {
{ CHIP_89218, "LAN89218" },
{ CHIP_9115, "LAN9115" },
{ CHIP_9116, "LAN9116" },
{ CHIP_9117, "LAN9117" },
{ CHIP_9118, "LAN9118" },
{ CHIP_9211, "LAN9211" },
{ CHIP_9215, "LAN9215" },
{ CHIP_9216, "LAN9216" },
{ CHIP_9217, "LAN9217" },
{ CHIP_9218, "LAN9218" },
{ CHIP_9220, "LAN9220" },
{ CHIP_9221, "LAN9221" },
{ 0, NULL },
};
static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
{
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
smc911x_reg_write(dev, MAC_CSR_CMD,
MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
return smc911x_reg_read(dev, MAC_CSR_DATA);
}
static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
{
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
smc911x_reg_write(dev, MAC_CSR_DATA, data);
smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
;
}
static int smc911x_detect_chip(struct eth_device *dev)
{
unsigned long val, i;
val = smc911x_reg_read(dev, BYTE_TEST);
if (val == 0xffffffff) {
/* Special case -- no chip present */
return -1;
} else if (val != 0x87654321) {
printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
return -1;
}
val = smc911x_reg_read(dev, ID_REV) >> 16;
for (i = 0; chip_ids[i].id != 0; i++) {
if (chip_ids[i].id == val) break;
}
if (!chip_ids[i].id) {
printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
return -1;
}
dev->priv = (void *)&chip_ids[i];
return 0;
}
static void smc911x_reset(struct eth_device *dev)
{
int timeout;
/*
* Take out of PM setting first
* Device is already wake up if PMT_CTRL_READY bit is set
*/
if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(dev, BYTE_TEST, 0x0);
timeout = 10;
while (timeout-- &&
!(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
udelay(10);
if (!timeout) {
printf(DRIVERNAME
": timeout waiting for PM restore\n");
return;
}
}
/* Disable interrupts */
smc911x_reg_write(dev, INT_EN, 0);
smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
timeout = 1000;
while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
udelay(10);
if (!timeout) {
printf(DRIVERNAME ": reset timeout\n");
return;
}
/* Reset the FIFO level and flow control settings */
smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
/* Set to LED outputs */
smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
}
#endif
|
1001-study-uboot
|
drivers/net/smc911x.h
|
C
|
gpl3
| 17,802
|
/*
* ax88180: ASIX AX88180 Non-PCI Gigabit Ethernet u-boot driver
*
* This program is free software; you can distribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
* This program is distributed in the hope it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
* USA.
*/
/*
* ========================================================================
* ASIX AX88180 Non-PCI 16/32-bit Gigabit Ethernet Linux Driver
*
* The AX88180 Ethernet controller is a high performance and highly
* integrated local CPU bus Ethernet controller with embedded 40K bytes
* SRAM and supports both 16-bit and 32-bit SRAM-Like interfaces for any
* embedded systems.
* The AX88180 is a single chip 10/100/1000Mbps Gigabit Ethernet
* controller that supports both MII and RGMII interfaces and is
* compliant to IEEE 802.3, IEEE 802.3u and IEEE 802.3z standards.
*
* Please visit ASIX's web site (http://www.asix.com.tw) for more
* details.
*
* Module Name : ax88180.c
* Date : 2008-07-07
* History
* 09/06/2006 : New release for AX88180 US2 chip.
* 07/07/2008 : Fix up the coding style and using inline functions
* instead of macros
* ========================================================================
*/
#include <common.h>
#include <command.h>
#include <net.h>
#include <malloc.h>
#include <linux/mii.h>
#include "ax88180.h"
/*
* ===========================================================================
* Local SubProgram Declaration
* ===========================================================================
*/
static void ax88180_rx_handler (struct eth_device *dev);
static int ax88180_phy_initial (struct eth_device *dev);
static void ax88180_media_config (struct eth_device *dev);
static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev);
static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev);
static unsigned short ax88180_mdio_read (struct eth_device *dev,
unsigned long regaddr);
static void ax88180_mdio_write (struct eth_device *dev,
unsigned long regaddr, unsigned short regdata);
/*
* ===========================================================================
* Local SubProgram Bodies
* ===========================================================================
*/
static int ax88180_mdio_check_complete (struct eth_device *dev)
{
int us_cnt = 10000;
unsigned short tmpval;
/* MDIO read/write should not take more than 10 ms */
while (--us_cnt) {
tmpval = INW (dev, MDIOCTRL);
if (((tmpval & READ_PHY) == 0) && ((tmpval & WRITE_PHY) == 0))
break;
}
return us_cnt;
}
static unsigned short
ax88180_mdio_read (struct eth_device *dev, unsigned long regaddr)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned long tmpval = 0;
OUTW (dev, (READ_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
if (ax88180_mdio_check_complete (dev))
tmpval = INW (dev, MDIODP);
else
printf ("Failed to read PHY register!\n");
return (unsigned short)(tmpval & 0xFFFF);
}
static void
ax88180_mdio_write (struct eth_device *dev, unsigned long regaddr,
unsigned short regdata)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
OUTW (dev, regdata, MDIODP);
OUTW (dev, (WRITE_PHY | (regaddr << 8) | priv->PhyAddr), MDIOCTRL);
if (!ax88180_mdio_check_complete (dev))
printf ("Failed to write PHY register!\n");
}
static int ax88180_phy_reset (struct eth_device *dev)
{
unsigned short delay_cnt = 500;
ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE));
/* Wait for the reset to complete, or time out (500 ms) */
while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) {
udelay (1000);
if (--delay_cnt == 0) {
printf ("Failed to reset PHY!\n");
return -1;
}
}
return 0;
}
static void ax88180_mac_reset (struct eth_device *dev)
{
unsigned long tmpval;
unsigned char i;
struct {
unsigned short offset, value;
} program_seq[] = {
{
MISC, MISC_NORMAL}, {
RXINDICATOR, DEFAULT_RXINDICATOR}, {
TXCMD, DEFAULT_TXCMD}, {
TXBS, DEFAULT_TXBS}, {
TXDES0, DEFAULT_TXDES0}, {
TXDES1, DEFAULT_TXDES1}, {
TXDES2, DEFAULT_TXDES2}, {
TXDES3, DEFAULT_TXDES3}, {
TXCFG, DEFAULT_TXCFG}, {
MACCFG2, DEFAULT_MACCFG2}, {
MACCFG3, DEFAULT_MACCFG3}, {
TXLEN, DEFAULT_TXLEN}, {
RXBTHD0, DEFAULT_RXBTHD0}, {
RXBTHD1, DEFAULT_RXBTHD1}, {
RXFULTHD, DEFAULT_RXFULTHD}, {
DOGTHD0, DEFAULT_DOGTHD0}, {
DOGTHD1, DEFAULT_DOGTHD1},};
OUTW (dev, MISC_RESET_MAC, MISC);
tmpval = INW (dev, MISC);
for (i = 0; i < (sizeof (program_seq) / sizeof (program_seq[0])); i++)
OUTW (dev, program_seq[i].value, program_seq[i].offset);
}
static int ax88180_poll_tx_complete (struct eth_device *dev)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned long tmpval, txbs_txdp;
int TimeOutCnt = 10000;
txbs_txdp = 1 << priv->NextTxDesc;
while (TimeOutCnt--) {
tmpval = INW (dev, TXBS);
if ((tmpval & txbs_txdp) == 0)
break;
udelay (100);
}
if (TimeOutCnt)
return 0;
else
return -TimeOutCnt;
}
static void ax88180_rx_handler (struct eth_device *dev)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned long data_size;
unsigned short rxcurt_ptr, rxbound_ptr, next_ptr;
int i;
#if defined (CONFIG_DRIVER_AX88180_16BIT)
unsigned short *rxdata = (unsigned short *)NetRxPackets[0];
#else
unsigned long *rxdata = (unsigned long *)NetRxPackets[0];
#endif
unsigned short count;
rxcurt_ptr = INW (dev, RXCURT);
rxbound_ptr = INW (dev, RXBOUND);
next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
debug ("ax88180: RX original RXBOUND=0x%04x,"
" RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
while (next_ptr != rxcurt_ptr) {
OUTW (dev, RX_START_READ, RXINDICATOR);
data_size = READ_RXBUF (dev) & 0xFFFF;
if ((data_size == 0) || (data_size > MAX_RX_SIZE)) {
OUTW (dev, RX_STOP_READ, RXINDICATOR);
ax88180_mac_reset (dev);
printf ("ax88180: Invalid Rx packet length!"
" (len=0x%04lx)\n", data_size);
debug ("ax88180: RX RXBOUND=0x%04x,"
"RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
return;
}
rxbound_ptr += (((data_size + 0xF) & 0xFFF0) >> 4) + 1;
rxbound_ptr &= RX_PAGE_NUM_MASK;
/* Comput access times */
count = (data_size + priv->PadSize) >> priv->BusWidth;
for (i = 0; i < count; i++) {
*(rxdata + i) = READ_RXBUF (dev);
}
OUTW (dev, RX_STOP_READ, RXINDICATOR);
/* Pass the packet up to the protocol layers. */
NetReceive (NetRxPackets[0], data_size);
OUTW (dev, rxbound_ptr, RXBOUND);
rxcurt_ptr = INW (dev, RXCURT);
rxbound_ptr = INW (dev, RXBOUND);
next_ptr = (rxbound_ptr + 1) & RX_PAGE_NUM_MASK;
debug ("ax88180: RX updated RXBOUND=0x%04x,"
"RXCURT=0x%04x\n", rxbound_ptr, rxcurt_ptr);
}
return;
}
static int ax88180_phy_initial (struct eth_device *dev)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned long tmp_regval;
unsigned short phyaddr;
/* Search for first avaliable PHY chipset */
#ifdef CONFIG_PHY_ADDR
phyaddr = CONFIG_PHY_ADDR;
#else
for (phyaddr = 0; phyaddr < 32; ++phyaddr)
#endif
{
priv->PhyAddr = phyaddr;
priv->PhyID0 = ax88180_mdio_read(dev, MII_PHYSID1);
priv->PhyID1 = ax88180_mdio_read(dev, MII_PHYSID2);
switch (priv->PhyID0) {
case MARVELL_ALASKA_PHYSID0:
debug("ax88180: Found Marvell Alaska PHY family."
" (PHY Addr=0x%x)\n", priv->PhyAddr);
switch (priv->PhyID1) {
case MARVELL_88E1118_PHYSID1:
ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 2);
ax88180_mdio_write(dev, M88E1118_CR,
M88E1118_CR_DEFAULT);
ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 3);
ax88180_mdio_write(dev, M88E1118_LEDCTL,
M88E1118_LEDCTL_DEFAULT);
ax88180_mdio_write(dev, M88E1118_LEDMIX,
M88E1118_LEDMIX_LED050 | M88E1118_LEDMIX_LED150 | 0x15);
ax88180_mdio_write(dev, M88E1118_PAGE_SEL, 0);
default: /* Default to 88E1111 Phy */
tmp_regval = ax88180_mdio_read(dev, M88E1111_EXT_SSR);
if ((tmp_regval & HWCFG_MODE_MASK) != RGMII_COPPER_MODE)
ax88180_mdio_write(dev, M88E1111_EXT_SCR,
DEFAULT_EXT_SCR);
}
if (ax88180_phy_reset(dev) < 0)
return 0;
ax88180_mdio_write(dev, M88_IER, LINK_CHANGE_INT);
return 1;
case CICADA_CIS8201_PHYSID0:
debug("ax88180: Found CICADA CIS8201 PHY"
" chipset. (PHY Addr=0x%x)\n", priv->PhyAddr);
ax88180_mdio_write(dev, CIS_IMR,
(CIS_INT_ENABLE | LINK_CHANGE_INT));
/* Set CIS_SMI_PRIORITY bit before force the media mode */
tmp_regval = ax88180_mdio_read(dev, CIS_AUX_CTRL_STATUS);
tmp_regval &= ~CIS_SMI_PRIORITY;
ax88180_mdio_write(dev, CIS_AUX_CTRL_STATUS, tmp_regval);
return 1;
case 0xffff:
/* No PHY at this addr */
break;
default:
printf("ax88180: Unknown PHY chipset %#x at addr %#x\n",
priv->PhyID0, priv->PhyAddr);
break;
}
}
printf("ax88180: Unknown PHY chipset!!\n");
return 0;
}
static void ax88180_media_config (struct eth_device *dev)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned long bmcr_val, bmsr_val;
unsigned long rxcfg_val, maccfg0_val, maccfg1_val;
unsigned long RealMediaMode;
int i;
/* Waiting 2 seconds for PHY link stable */
for (i = 0; i < 20000; i++) {
bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
if (bmsr_val & BMSR_LSTATUS) {
break;
}
udelay (100);
}
bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
debug ("ax88180: BMSR=0x%04x\n", (unsigned int)bmsr_val);
if (bmsr_val & BMSR_LSTATUS) {
bmcr_val = ax88180_mdio_read (dev, MII_BMCR);
if (bmcr_val & BMCR_ANENABLE) {
/*
* Waiting for Auto-negotiation completion, this may
* take up to 5 seconds.
*/
debug ("ax88180: Auto-negotiation is "
"enabled. Waiting for NWay completion..\n");
for (i = 0; i < 50000; i++) {
bmsr_val = ax88180_mdio_read (dev, MII_BMSR);
if (bmsr_val & BMSR_ANEGCOMPLETE) {
break;
}
udelay (100);
}
} else
debug ("ax88180: Auto-negotiation is disabled.\n");
debug ("ax88180: BMCR=0x%04x, BMSR=0x%04x\n",
(unsigned int)bmcr_val, (unsigned int)bmsr_val);
/* Get real media mode here */
switch (priv->PhyID0) {
case MARVELL_ALASKA_PHYSID0:
RealMediaMode = get_MarvellPHY_media_mode(dev);
break;
case CICADA_CIS8201_PHYSID0:
RealMediaMode = get_CicadaPHY_media_mode(dev);
break;
default:
RealMediaMode = MEDIA_1000FULL;
break;
}
priv->LinkState = INS_LINK_UP;
switch (RealMediaMode) {
case MEDIA_1000FULL:
debug ("ax88180: 1000Mbps Full-duplex mode.\n");
rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
maccfg1_val = GIGA_MODE_EN | RXFLOW_EN |
FULLDUPLEX | DEFAULT_MACCFG1;
break;
case MEDIA_1000HALF:
debug ("ax88180: 1000Mbps Half-duplex mode.\n");
rxcfg_val = DEFAULT_RXCFG;
maccfg0_val = DEFAULT_MACCFG0;
maccfg1_val = GIGA_MODE_EN | DEFAULT_MACCFG1;
break;
case MEDIA_100FULL:
debug ("ax88180: 100Mbps Full-duplex mode.\n");
rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
maccfg0_val = SPEED100 | TXFLOW_ENABLE
| DEFAULT_MACCFG0;
maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
break;
case MEDIA_100HALF:
debug ("ax88180: 100Mbps Half-duplex mode.\n");
rxcfg_val = DEFAULT_RXCFG;
maccfg0_val = SPEED100 | DEFAULT_MACCFG0;
maccfg1_val = DEFAULT_MACCFG1;
break;
case MEDIA_10FULL:
debug ("ax88180: 10Mbps Full-duplex mode.\n");
rxcfg_val = RXFLOW_ENABLE | DEFAULT_RXCFG;
maccfg0_val = TXFLOW_ENABLE | DEFAULT_MACCFG0;
maccfg1_val = RXFLOW_EN | FULLDUPLEX | DEFAULT_MACCFG1;
break;
case MEDIA_10HALF:
debug ("ax88180: 10Mbps Half-duplex mode.\n");
rxcfg_val = DEFAULT_RXCFG;
maccfg0_val = DEFAULT_MACCFG0;
maccfg1_val = DEFAULT_MACCFG1;
break;
default:
debug ("ax88180: Unknow media mode.\n");
rxcfg_val = DEFAULT_RXCFG;
maccfg0_val = DEFAULT_MACCFG0;
maccfg1_val = DEFAULT_MACCFG1;
priv->LinkState = INS_LINK_DOWN;
break;
}
} else {
rxcfg_val = DEFAULT_RXCFG;
maccfg0_val = DEFAULT_MACCFG0;
maccfg1_val = DEFAULT_MACCFG1;
priv->LinkState = INS_LINK_DOWN;
}
OUTW (dev, rxcfg_val, RXCFG);
OUTW (dev, maccfg0_val, MACCFG0);
OUTW (dev, maccfg1_val, MACCFG1);
return;
}
static unsigned long get_MarvellPHY_media_mode (struct eth_device *dev)
{
unsigned long m88_ssr;
unsigned long MediaMode;
m88_ssr = ax88180_mdio_read (dev, M88_SSR);
switch (m88_ssr & SSR_MEDIA_MASK) {
case SSR_1000FULL:
MediaMode = MEDIA_1000FULL;
break;
case SSR_1000HALF:
MediaMode = MEDIA_1000HALF;
break;
case SSR_100FULL:
MediaMode = MEDIA_100FULL;
break;
case SSR_100HALF:
MediaMode = MEDIA_100HALF;
break;
case SSR_10FULL:
MediaMode = MEDIA_10FULL;
break;
case SSR_10HALF:
MediaMode = MEDIA_10HALF;
break;
default:
MediaMode = MEDIA_UNKNOWN;
break;
}
return MediaMode;
}
static unsigned long get_CicadaPHY_media_mode (struct eth_device *dev)
{
unsigned long tmp_regval;
unsigned long MediaMode;
tmp_regval = ax88180_mdio_read (dev, CIS_AUX_CTRL_STATUS);
switch (tmp_regval & CIS_MEDIA_MASK) {
case CIS_1000FULL:
MediaMode = MEDIA_1000FULL;
break;
case CIS_1000HALF:
MediaMode = MEDIA_1000HALF;
break;
case CIS_100FULL:
MediaMode = MEDIA_100FULL;
break;
case CIS_100HALF:
MediaMode = MEDIA_100HALF;
break;
case CIS_10FULL:
MediaMode = MEDIA_10FULL;
break;
case CIS_10HALF:
MediaMode = MEDIA_10HALF;
break;
default:
MediaMode = MEDIA_UNKNOWN;
break;
}
return MediaMode;
}
static void ax88180_halt (struct eth_device *dev)
{
/* Disable AX88180 TX/RX functions */
OUTW (dev, WAKEMOD, CMD);
}
static int ax88180_init (struct eth_device *dev, bd_t * bd)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned short tmp_regval;
ax88180_mac_reset (dev);
/* Disable interrupt */
OUTW (dev, CLEAR_IMR, IMR);
/* Disable AX88180 TX/RX functions */
OUTW (dev, WAKEMOD, CMD);
/* Fill the MAC address */
tmp_regval =
dev->enetaddr[0] | (((unsigned short)dev->enetaddr[1]) << 8);
OUTW (dev, tmp_regval, MACID0);
tmp_regval =
dev->enetaddr[2] | (((unsigned short)dev->enetaddr[3]) << 8);
OUTW (dev, tmp_regval, MACID1);
tmp_regval =
dev->enetaddr[4] | (((unsigned short)dev->enetaddr[5]) << 8);
OUTW (dev, tmp_regval, MACID2);
ax88180_media_config (dev);
OUTW (dev, DEFAULT_RXFILTER, RXFILTER);
/* Initial variables here */
priv->FirstTxDesc = TXDP0;
priv->NextTxDesc = TXDP0;
/* Check if there is any invalid interrupt status and clear it. */
OUTW (dev, INW (dev, ISR), ISR);
/* Start AX88180 TX/RX functions */
OUTW (dev, (RXEN | TXEN | WAKEMOD), CMD);
return 0;
}
/* Get a data block via Ethernet */
static int ax88180_recv (struct eth_device *dev)
{
unsigned short ISR_Status;
unsigned short tmp_regval;
/* Read and check interrupt status here. */
ISR_Status = INW (dev, ISR);
while (ISR_Status) {
/* Clear the interrupt status */
OUTW (dev, ISR_Status, ISR);
debug ("\nax88180: The interrupt status = 0x%04x\n",
ISR_Status);
if (ISR_Status & ISR_PHY) {
/* Read ISR register once to clear PHY interrupt bit */
tmp_regval = ax88180_mdio_read (dev, M88_ISR);
ax88180_media_config (dev);
}
if ((ISR_Status & ISR_RX) || (ISR_Status & ISR_RXBUFFOVR)) {
ax88180_rx_handler (dev);
}
/* Read and check interrupt status again */
ISR_Status = INW (dev, ISR);
}
return 0;
}
/* Send a data block via Ethernet. */
static int
ax88180_send (struct eth_device *dev, volatile void *packet, int length)
{
struct ax88180_private *priv = (struct ax88180_private *)dev->priv;
unsigned short TXDES_addr;
unsigned short txcmd_txdp, txbs_txdp;
unsigned short tmp_data;
int i;
#if defined (CONFIG_DRIVER_AX88180_16BIT)
volatile unsigned short *txdata = (volatile unsigned short *)packet;
#else
volatile unsigned long *txdata = (volatile unsigned long *)packet;
#endif
unsigned short count;
if (priv->LinkState != INS_LINK_UP) {
return 0;
}
priv->FirstTxDesc = priv->NextTxDesc;
txbs_txdp = 1 << priv->FirstTxDesc;
debug ("ax88180: TXDP%d is available\n", priv->FirstTxDesc);
txcmd_txdp = priv->FirstTxDesc << 13;
TXDES_addr = TXDES0 + (priv->FirstTxDesc << 2);
OUTW (dev, (txcmd_txdp | length | TX_START_WRITE), TXCMD);
/* Comput access times */
count = (length + priv->PadSize) >> priv->BusWidth;
for (i = 0; i < count; i++) {
WRITE_TXBUF (dev, *(txdata + i));
}
OUTW (dev, txcmd_txdp | length, TXCMD);
OUTW (dev, txbs_txdp, TXBS);
OUTW (dev, (TXDPx_ENABLE | length), TXDES_addr);
priv->NextTxDesc = (priv->NextTxDesc + 1) & TXDP_MASK;
/*
* Check the available transmit descriptor, if we had exhausted all
* transmit descriptor ,then we have to wait for at least one free
* descriptor
*/
txbs_txdp = 1 << priv->NextTxDesc;
tmp_data = INW (dev, TXBS);
if (tmp_data & txbs_txdp) {
if (ax88180_poll_tx_complete (dev) < 0) {
ax88180_mac_reset (dev);
priv->FirstTxDesc = TXDP0;
priv->NextTxDesc = TXDP0;
printf ("ax88180: Transmit time out occurred!\n");
}
}
return 0;
}
static void ax88180_read_mac_addr (struct eth_device *dev)
{
unsigned short macid0_val, macid1_val, macid2_val;
unsigned short tmp_regval;
unsigned short i;
/* Reload MAC address from EEPROM */
OUTW (dev, RELOAD_EEPROM, PROMCTRL);
/* Waiting for reload eeprom completion */
for (i = 0; i < 500; i++) {
tmp_regval = INW (dev, PROMCTRL);
if ((tmp_regval & RELOAD_EEPROM) == 0)
break;
udelay (1000);
}
/* Get MAC addresses */
macid0_val = INW (dev, MACID0);
macid1_val = INW (dev, MACID1);
macid2_val = INW (dev, MACID2);
if (((macid0_val | macid1_val | macid2_val) != 0) &&
((macid0_val & 0x01) == 0)) {
dev->enetaddr[0] = (unsigned char)macid0_val;
dev->enetaddr[1] = (unsigned char)(macid0_val >> 8);
dev->enetaddr[2] = (unsigned char)macid1_val;
dev->enetaddr[3] = (unsigned char)(macid1_val >> 8);
dev->enetaddr[4] = (unsigned char)macid2_val;
dev->enetaddr[5] = (unsigned char)(macid2_val >> 8);
}
}
/*
===========================================================================
<<<<<< Exported SubProgram Bodies >>>>>>
===========================================================================
*/
int ax88180_initialize (bd_t * bis)
{
struct eth_device *dev;
struct ax88180_private *priv;
dev = (struct eth_device *)malloc (sizeof *dev);
if (NULL == dev)
return 0;
memset (dev, 0, sizeof *dev);
priv = (struct ax88180_private *)malloc (sizeof (*priv));
if (NULL == priv)
return 0;
memset (priv, 0, sizeof *priv);
sprintf (dev->name, "ax88180");
dev->iobase = AX88180_BASE;
dev->priv = priv;
dev->init = ax88180_init;
dev->halt = ax88180_halt;
dev->send = ax88180_send;
dev->recv = ax88180_recv;
priv->BusWidth = BUS_WIDTH_32;
priv->PadSize = 3;
#if defined (CONFIG_DRIVER_AX88180_16BIT)
OUTW (dev, (START_BASE >> 8), BASE);
OUTW (dev, DECODE_EN, DECODE);
priv->BusWidth = BUS_WIDTH_16;
priv->PadSize = 1;
#endif
ax88180_mac_reset (dev);
/* Disable interrupt */
OUTW (dev, CLEAR_IMR, IMR);
/* Disable AX88180 TX/RX functions */
OUTW (dev, WAKEMOD, CMD);
ax88180_read_mac_addr (dev);
eth_register (dev);
return ax88180_phy_initial (dev);
}
|
1001-study-uboot
|
drivers/net/ax88180.c
|
C
|
gpl3
| 19,681
|
/*-----------------------------------------------------------------------------+
* This source code is dual-licensed. You may use it under the terms of the
* GNU General Public License version 2, or under the license below.
*
* This source code has been made available to you by IBM on an AS-IS
* basis. Anyone receiving this source is licensed under IBM
* copyrights to use it in any way he or she deems fit, including
* copying it, modifying it, compiling it, and redistributing it either
* with or without modifications. No license under IBM patents or
* patent applications is to be implied by the copyright license.
*
* Any user of this software should understand that IBM cannot provide
* technical support for this software and will not be responsible for
* any consequences resulting from the use of this software.
*
* Any person who transfers this source code or any derivative work
* must include the IBM copyright notice, this paragraph, and the
* preceding two paragraphs in the transferred software.
*
* COPYRIGHT I B M CORPORATION 1995
* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
*-----------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------+
*
* File Name: enetemac.c
*
* Function: Device driver for the ethernet EMAC3 macro on the 405GP.
*
* Author: Mark Wisner
*
* Change Activity-
*
* Date Description of Change BY
* --------- --------------------- ---
* 05-May-99 Created MKW
* 27-Jun-99 Clean up JWB
* 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
* 29-Jul-99 Added Full duplex support MKW
* 06-Aug-99 Changed names for Mal CR reg MKW
* 23-Aug-99 Turned off SYE when running at 10Mbs MKW
* 24-Aug-99 Marked descriptor empty after call_xlc MKW
* 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
* to avoid chaining maximum sized packets. Push starting
* RX descriptor address up to the next cache line boundary.
* 16-Jan-00 Added support for booting with IP of 0x0 MKW
* 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
* EMAC0_RXM register. JWB
* 12-Mar-01 anne-sophie.harnois@nextream.fr
* - Variables are compatible with those already defined in
* include/net.h
* - Receive buffer descriptor ring is used to send buffers
* to the user
* - Info print about send/received/handled packet number if
* INFO_405_ENET is set
* 17-Apr-01 stefan.roese@esd-electronics.com
* - MAL reset in "eth_halt" included
* - Enet speed and duplex output now in one line
* 08-May-01 stefan.roese@esd-electronics.com
* - MAL error handling added (eth_init called again)
* 13-Nov-01 stefan.roese@esd-electronics.com
* - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
* 04-Jan-02 stefan.roese@esd-electronics.com
* - Wait for PHY auto negotiation to complete added
* 06-Feb-02 stefan.roese@esd-electronics.com
* - Bug fixed in waiting for auto negotiation to complete
* 26-Feb-02 stefan.roese@esd-electronics.com
* - rx and tx buffer descriptors now allocated (no fixed address
* used anymore)
* 17-Jun-02 stefan.roese@esd-electronics.com
* - MAL error debug printf 'M' removed (rx de interrupt may
* occur upon many incoming packets with only 4 rx buffers).
*-----------------------------------------------------------------------------*
* 17-Nov-03 travis.sawyer@sandburst.com
* - ported from 405gp_enet.c to utilized upto 4 EMAC ports
* in the 440GX. This port should work with the 440GP
* (2 EMACs) also
* 15-Aug-05 sr@denx.de
* - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
now handling all 4xx cpu's.
*-----------------------------------------------------------------------------*/
#include <config.h>
#include <common.h>
#include <net.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <commproc.h>
#include <asm/ppc4xx.h>
#include <asm/ppc4xx-emac.h>
#include <asm/ppc4xx-mal.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/compiler.h>
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
/* Ethernet Transmit and Receive Buffers */
/* AS.HARNOIS
* In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
* PKTSIZE and PKTSIZE_ALIGN (include/net.h)
*/
#define ENET_MAX_MTU PKTSIZE
#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
/*-----------------------------------------------------------------------------+
* Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
* Interrupt Controller).
*-----------------------------------------------------------------------------*/
#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
#if defined(CONFIG_HAS_ETH3)
#if !defined(CONFIG_440GX)
#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
#else
/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
#endif /* !defined(CONFIG_440GX) */
#elif defined(CONFIG_HAS_ETH2)
#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
UIC_MASK(ETH_IRQ_NUM(2)))
#elif defined(CONFIG_HAS_ETH1)
#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
#else
#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
#endif
/*
* Define a default version for UIC_ETHxB for non 440GX so that we can
* use common code for all 4xx variants
*/
#if !defined(UIC_ETHxB)
#define UIC_ETHxB 0
#endif
#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
/*
* We have 3 different interrupt types:
* - MAL interrupts indicating successful transfer
* - MAL error interrupts indicating MAL related errors
* - EMAC interrupts indicating EMAC related errors
*
* All those interrupts can be on different UIC's, but since
* now at least all interrupts from one type are on the same
* UIC. Only exception is 440GX where the EMAC interrupts are
* spread over two UIC's!
*/
#if defined(CONFIG_440GX)
#define UIC_BASE_MAL UIC1_DCR_BASE
#define UIC_BASE_MAL_ERR UIC2_DCR_BASE
#define UIC_BASE_EMAC UIC2_DCR_BASE
#define UIC_BASE_EMAC_B UIC3_DCR_BASE
#else
#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
#endif
#undef INFO_4XX_ENET
#define BI_PHYMODE_NONE 0
#define BI_PHYMODE_ZMII 1
#define BI_PHYMODE_RGMII 2
#define BI_PHYMODE_GMII 3
#define BI_PHYMODE_RTBI 4
#define BI_PHYMODE_TBI 5
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
#define BI_PHYMODE_SMII 6
#define BI_PHYMODE_MII 7
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define BI_PHYMODE_RMII 8
#endif
#endif
#define BI_PHYMODE_SGMII 9
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
#else
#define MAL_RX_CHAN_MUL 1
#endif
/*--------------------------------------------------------------------+
* Fixed PHY (PHY-less) support for Ethernet Ports.
*--------------------------------------------------------------------*/
/*
* Some boards do not have a PHY for each ethernet port. These ports
* are known as Fixed PHY (or PHY-less) ports. For such ports, set
* the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
* then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
* duplex should be for these ports in the board configuration
* file.
*
* For Example:
* #define CONFIG_FIXED_PHY 0xFFFFFFFF
*
* #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
* #define CONFIG_PHY1_ADDR 1
* #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
* #define CONFIG_PHY3_ADDR 3
*
* #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
* {devnum, speed, duplex},
*
* #define CONFIG_SYS_FIXED_PHY_PORTS \
* CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
* CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
*/
#ifndef CONFIG_FIXED_PHY
#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
#endif
#ifndef CONFIG_SYS_FIXED_PHY_PORTS
#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
#endif
struct fixed_phy_port {
unsigned int devnum; /* ethernet port */
unsigned int speed; /* specified speed 10,100 or 1000 */
unsigned int duplex; /* specified duplex FULL or HALF */
};
static const struct fixed_phy_port fixed_phy_port[] = {
CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
};
/*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers.
*-----------------------------------------------------------------------------*/
/*
* Get count of EMAC devices (doesn't have to be the max. possible number
* supported by the cpu)
*
* CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
* EMAC count is possible. As it is needed for the Kilauea/Haleakala
* 405EX/405EXr eval board, using the same binary.
*/
#if defined(CONFIG_BOARD_EMAC_COUNT)
#define LAST_EMAC_NUM board_emac_count()
#else /* CONFIG_BOARD_EMAC_COUNT */
#if defined(CONFIG_HAS_ETH3)
#define LAST_EMAC_NUM 4
#elif defined(CONFIG_HAS_ETH2)
#define LAST_EMAC_NUM 3
#elif defined(CONFIG_HAS_ETH1)
#define LAST_EMAC_NUM 2
#else
#define LAST_EMAC_NUM 1
#endif
#endif /* CONFIG_BOARD_EMAC_COUNT */
/* normal boards start with EMAC0 */
#if !defined(CONFIG_EMAC_NR_START)
#define CONFIG_EMAC_NR_START 0
#endif
#define MAL_RX_DESC_SIZE 2048
#define MAL_TX_DESC_SIZE 2048
#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
static void enet_rcv (struct eth_device *dev, unsigned long malisr);
int enetInt (struct eth_device *dev);
static void mal_err (struct eth_device *dev, unsigned long isr,
unsigned long uic, unsigned long maldef,
unsigned long mal_errr);
static void emac_err (struct eth_device *dev, unsigned long isr);
extern int phy_setup_aneg (char *devname, unsigned char addr);
extern int emac4xx_miiphy_read (const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
extern int emac4xx_miiphy_write (const char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
int board_emac_count(void);
static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
{
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
u32 val;
mfsdr(SDR0_MFR, val);
val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
mtsdr(SDR0_MFR, val);
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
u32 val;
mfsdr(SDR0_ETH_CFG, val);
val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
mtsdr(SDR0_ETH_CFG, val);
#endif
}
static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
{
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
u32 val;
mfsdr(SDR0_MFR, val);
val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
mtsdr(SDR0_MFR, val);
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
u32 val;
mfsdr(SDR0_ETH_CFG, val);
val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
mtsdr(SDR0_ETH_CFG, val);
#endif
}
/*-----------------------------------------------------------------------------+
| ppc_4xx_eth_halt
| Disable MAL channel, and EMACn
+-----------------------------------------------------------------------------*/
static void ppc_4xx_eth_halt (struct eth_device *dev)
{
EMAC_4XX_HW_PST hw_p = dev->priv;
u32 val = 10000;
out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
#else
mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum));
#endif
mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum));
/* wait for reset */
while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) {
udelay (1000); /* Delay 1 MS so as not to hammer the register */
val--;
if (val == 0)
break;
}
/* provide clocks for EMAC internal loopback */
emac_loopback_enable(hw_p);
/* EMAC RESET */
out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
/* remove clocks for EMAC internal loopback */
emac_loopback_disable(hw_p);
#ifndef CONFIG_NETCONSOLE
hw_p->print_speed = 1; /* print speed message again next time */
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
/* don't bypass the TAHOE0/TAHOE1 cores for Linux */
mfsdr(SDR0_ETH_CFG, val);
val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
mtsdr(SDR0_ETH_CFG, val);
#endif
return;
}
#if defined (CONFIG_440GX)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long pfc1;
unsigned long zmiifer;
unsigned long rmiifer;
mfsdr(SDR0_PFC1, pfc1);
pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
zmiifer = 0;
rmiifer = 0;
switch (pfc1) {
case 1:
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
bis->bi_phymode[0] = BI_PHYMODE_ZMII;
bis->bi_phymode[1] = BI_PHYMODE_ZMII;
bis->bi_phymode[2] = BI_PHYMODE_ZMII;
bis->bi_phymode[3] = BI_PHYMODE_ZMII;
break;
case 2:
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
bis->bi_phymode[0] = BI_PHYMODE_ZMII;
bis->bi_phymode[1] = BI_PHYMODE_ZMII;
bis->bi_phymode[2] = BI_PHYMODE_ZMII;
bis->bi_phymode[3] = BI_PHYMODE_ZMII;
break;
case 3:
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
bis->bi_phymode[0] = BI_PHYMODE_ZMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
bis->bi_phymode[2] = BI_PHYMODE_RGMII;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 4:
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
bis->bi_phymode[0] = BI_PHYMODE_ZMII;
bis->bi_phymode[1] = BI_PHYMODE_ZMII;
bis->bi_phymode[2] = BI_PHYMODE_RGMII;
bis->bi_phymode[3] = BI_PHYMODE_RGMII;
break;
case 5:
zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
bis->bi_phymode[0] = BI_PHYMODE_ZMII;
bis->bi_phymode[1] = BI_PHYMODE_ZMII;
bis->bi_phymode[2] = BI_PHYMODE_ZMII;
bis->bi_phymode[3] = BI_PHYMODE_RGMII;
break;
case 6:
zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
bis->bi_phymode[0] = BI_PHYMODE_ZMII;
bis->bi_phymode[1] = BI_PHYMODE_ZMII;
bis->bi_phymode[2] = BI_PHYMODE_RGMII;
break;
case 0:
default:
zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
rmiifer = 0x0;
bis->bi_phymode[0] = BI_PHYMODE_ZMII;
bis->bi_phymode[1] = BI_PHYMODE_ZMII;
bis->bi_phymode[2] = BI_PHYMODE_ZMII;
bis->bi_phymode[3] = BI_PHYMODE_ZMII;
break;
}
/* Ensure we setup mdio for this devnum and ONLY this devnum */
zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
out_be32((void *)ZMII0_FER, zmiifer);
out_be32((void *)RGMII_FER, rmiifer);
return ((int)pfc1);
}
#endif /* CONFIG_440_GX */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long zmiifer=0x0;
unsigned long pfc1;
mfsdr(SDR0_PFC1, pfc1);
pfc1 &= SDR0_PFC1_SELECT_MASK;
switch (pfc1) {
case SDR0_PFC1_SELECT_CONFIG_2:
/* 1 x GMII port */
out_be32((void *)ZMII0_FER, 0x00);
out_be32((void *)RGMII_FER, 0x00000037);
bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
case SDR0_PFC1_SELECT_CONFIG_4:
/* 2 x RGMII ports */
out_be32((void *)ZMII0_FER, 0x00);
out_be32((void *)RGMII_FER, 0x00000055);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
case SDR0_PFC1_SELECT_CONFIG_6:
/* 2 x SMII ports */
out_be32((void *)ZMII0_FER,
((ZMII_FER_SMII) << ZMII_FER_V(0)) |
((ZMII_FER_SMII) << ZMII_FER_V(1)));
out_be32((void *)RGMII_FER, 0x00000000);
bis->bi_phymode[0] = BI_PHYMODE_SMII;
bis->bi_phymode[1] = BI_PHYMODE_SMII;
break;
case SDR0_PFC1_SELECT_CONFIG_1_2:
/* only 1 x MII supported */
out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
out_be32((void *)RGMII_FER, 0x00000000);
bis->bi_phymode[0] = BI_PHYMODE_MII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
default:
break;
}
/* Ensure we setup mdio for this devnum and ONLY this devnum */
zmiifer = in_be32((void *)ZMII0_FER);
zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
out_be32((void *)ZMII0_FER, zmiifer);
return ((int)0x0);
}
#endif /* CONFIG_440EPX */
#if defined(CONFIG_405EX)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
u32 rgmiifer = 0;
/*
* The 405EX(r)'s RGMII bridge can operate in one of several
* modes, only one of which (2 x RGMII) allows the
* simultaneous use of both EMACs on the 405EX.
*/
switch (CONFIG_EMAC_PHY_MODE) {
case EMAC_PHY_MODE_NONE:
/* No ports */
rgmiifer |= RGMII_FER_DIS << 0;
rgmiifer |= RGMII_FER_DIS << 4;
out_be32((void *)RGMII_FER, rgmiifer);
bis->bi_phymode[0] = BI_PHYMODE_NONE;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
case EMAC_PHY_MODE_NONE_RGMII:
/* 1 x RGMII port on channel 0 */
rgmiifer |= RGMII_FER_RGMII << 0;
rgmiifer |= RGMII_FER_DIS << 4;
out_be32((void *)RGMII_FER, rgmiifer);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
case EMAC_PHY_MODE_RGMII_NONE:
/* 1 x RGMII port on channel 1 */
rgmiifer |= RGMII_FER_DIS << 0;
rgmiifer |= RGMII_FER_RGMII << 4;
out_be32((void *)RGMII_FER, rgmiifer);
bis->bi_phymode[0] = BI_PHYMODE_NONE;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
case EMAC_PHY_MODE_RGMII_RGMII:
/* 2 x RGMII ports */
rgmiifer |= RGMII_FER_RGMII << 0;
rgmiifer |= RGMII_FER_RGMII << 4;
out_be32((void *)RGMII_FER, rgmiifer);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
case EMAC_PHY_MODE_NONE_GMII:
/* 1 x GMII port on channel 0 */
rgmiifer |= RGMII_FER_GMII << 0;
rgmiifer |= RGMII_FER_DIS << 4;
out_be32((void *)RGMII_FER, rgmiifer);
bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
case EMAC_PHY_MODE_NONE_MII:
/* 1 x MII port on channel 0 */
rgmiifer |= RGMII_FER_MII << 0;
rgmiifer |= RGMII_FER_DIS << 4;
out_be32((void *)RGMII_FER, rgmiifer);
bis->bi_phymode[0] = BI_PHYMODE_MII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
case EMAC_PHY_MODE_GMII_NONE:
/* 1 x GMII port on channel 1 */
rgmiifer |= RGMII_FER_DIS << 0;
rgmiifer |= RGMII_FER_GMII << 4;
out_be32((void *)RGMII_FER, rgmiifer);
bis->bi_phymode[0] = BI_PHYMODE_NONE;
bis->bi_phymode[1] = BI_PHYMODE_GMII;
break;
case EMAC_PHY_MODE_MII_NONE:
/* 1 x MII port on channel 1 */
rgmiifer |= RGMII_FER_DIS << 0;
rgmiifer |= RGMII_FER_MII << 4;
out_be32((void *)RGMII_FER, rgmiifer);
bis->bi_phymode[0] = BI_PHYMODE_NONE;
bis->bi_phymode[1] = BI_PHYMODE_MII;
break;
default:
break;
}
/* Ensure we setup mdio for this devnum and ONLY this devnum */
rgmiifer = in_be32((void *)RGMII_FER);
rgmiifer |= (1 << (19-devnum));
out_be32((void *)RGMII_FER, rgmiifer);
return ((int)0x0);
}
#endif /* CONFIG_405EX */
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
u32 eth_cfg;
u32 zmiifer; /* ZMII0_FER reg. */
u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
int mode;
zmiifer = 0;
rmiifer = 0;
rmiifer1 = 0;
#if defined(CONFIG_460EX)
mode = 9;
mfsdr(SDR0_ETH_CFG, eth_cfg);
if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
mode = 11; /* config SGMII */
#else
mode = 10;
mfsdr(SDR0_ETH_CFG, eth_cfg);
if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
mode = 12; /* config SGMII */
#endif
/* TODO:
* NOTE: 460GT has 2 RGMII bridge cores:
* emac0 ------ RGMII0_BASE
* |
* emac1 -----+
*
* emac2 ------ RGMII1_BASE
* |
* emac3 -----+
*
* 460EX has 1 RGMII bridge core:
* and RGMII1_BASE is disabled
* emac0 ------ RGMII0_BASE
* |
* emac1 -----+
*/
/*
* Right now only 2*RGMII is supported. Please extend when needed.
* sr - 2008-02-19
* Add SGMII support.
* vg - 2008-07-28
*/
switch (mode) {
case 1:
/* 1 MII - 460EX */
/* GMC0 EMAC4_0, ZMII Bridge */
zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
bis->bi_phymode[0] = BI_PHYMODE_MII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
bis->bi_phymode[2] = BI_PHYMODE_NONE;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 2:
/* 2 MII - 460GT */
/* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
bis->bi_phymode[0] = BI_PHYMODE_MII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
bis->bi_phymode[2] = BI_PHYMODE_MII;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 3:
/* 2 RMII - 460EX */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
bis->bi_phymode[0] = BI_PHYMODE_RMII;
bis->bi_phymode[1] = BI_PHYMODE_RMII;
bis->bi_phymode[2] = BI_PHYMODE_NONE;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 4:
/* 4 RMII - 460GT */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
/* ZMII Bridge */
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
bis->bi_phymode[0] = BI_PHYMODE_RMII;
bis->bi_phymode[1] = BI_PHYMODE_RMII;
bis->bi_phymode[2] = BI_PHYMODE_RMII;
bis->bi_phymode[3] = BI_PHYMODE_RMII;
break;
case 5:
/* 2 SMII - 460EX */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
bis->bi_phymode[0] = BI_PHYMODE_SMII;
bis->bi_phymode[1] = BI_PHYMODE_SMII;
bis->bi_phymode[2] = BI_PHYMODE_NONE;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 6:
/* 4 SMII - 460GT */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
/* ZMII Bridge */
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
bis->bi_phymode[0] = BI_PHYMODE_SMII;
bis->bi_phymode[1] = BI_PHYMODE_SMII;
bis->bi_phymode[2] = BI_PHYMODE_SMII;
bis->bi_phymode[3] = BI_PHYMODE_SMII;
break;
case 7:
/* This is the default mode that we want for board bringup - Maple */
/* 1 GMII - 460EX */
/* GMC0 EMAC4_0, RGMII Bridge 0 */
rmiifer |= RGMII_FER_MDIO(0);
if (devnum == 0) {
rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
bis->bi_phymode[2] = BI_PHYMODE_NONE;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
} else {
rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
bis->bi_phymode[0] = BI_PHYMODE_NONE;
bis->bi_phymode[1] = BI_PHYMODE_GMII;
bis->bi_phymode[2] = BI_PHYMODE_NONE;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
}
break;
case 8:
/* 2 GMII - 460GT */
/* GMC0 EMAC4_0, RGMII Bridge 0 */
/* GMC1 EMAC4_2, RGMII Bridge 1 */
rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
bis->bi_phymode[2] = BI_PHYMODE_GMII;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 9:
/* 2 RGMII - 460EX */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
bis->bi_phymode[2] = BI_PHYMODE_NONE;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 10:
/* 4 RGMII - 460GT */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
/* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
bis->bi_phymode[2] = BI_PHYMODE_RGMII;
bis->bi_phymode[3] = BI_PHYMODE_RGMII;
break;
case 11:
/* 2 SGMII - 460EX */
bis->bi_phymode[0] = BI_PHYMODE_SGMII;
bis->bi_phymode[1] = BI_PHYMODE_SGMII;
bis->bi_phymode[2] = BI_PHYMODE_NONE;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
case 12:
/* 3 SGMII - 460GT */
bis->bi_phymode[0] = BI_PHYMODE_SGMII;
bis->bi_phymode[1] = BI_PHYMODE_SGMII;
bis->bi_phymode[2] = BI_PHYMODE_SGMII;
bis->bi_phymode[3] = BI_PHYMODE_NONE;
break;
default:
break;
}
/* Set EMAC for MDIO */
mfsdr(SDR0_ETH_CFG, eth_cfg);
eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
mtsdr(SDR0_ETH_CFG, eth_cfg);
out_be32((void *)RGMII_FER, rmiifer);
#if defined(CONFIG_460GT)
out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
#endif
/* bypass the TAHOE0/TAHOE1 cores for U-Boot */
mfsdr(SDR0_ETH_CFG, eth_cfg);
eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
mtsdr(SDR0_ETH_CFG, eth_cfg);
return 0;
}
#endif /* CONFIG_460EX || CONFIG_460GT */
static inline void *malloc_aligned(u32 size, u32 align)
{
return (void *)(((u32)malloc(size + align) + align - 1) &
~(align - 1));
}
static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
{
int i;
unsigned long reg = 0;
unsigned long msr;
unsigned long speed;
unsigned long duplex;
unsigned long failsafe;
unsigned mode_reg;
unsigned short devnum;
unsigned short reg_short;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
u32 opbfreq;
sys_info_t sysinfo;
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
__maybe_unused int ethgroup = -1;
#endif
#endif
u32 bd_cached;
u32 bd_uncached = 0;
#ifdef CONFIG_4xx_DCACHE
static u32 last_used_ea = 0;
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
int rgmii_channel;
#endif
EMAC_4XX_HW_PST hw_p = dev->priv;
/* before doing anything, figure out if we have a MAC address */
/* if not, bail */
if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
printf("ERROR: ethaddr not set!\n");
return -1;
}
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
/* Need to get the OPB frequency so we can access the PHY */
get_sys_info (&sysinfo);
#endif
msr = mfmsr ();
mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
devnum = hw_p->devnum;
#ifdef INFO_4XX_ENET
/* AS.HARNOIS
* We should have :
* hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
* In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
* is possible that new packets (without relationship with
* current transfer) have got the time to arrived before
* netloop calls eth_halt
*/
printf ("About preceeding transfer (eth%d):\n"
"- Sent packet number %d\n"
"- Received packet number %d\n"
"- Handled packet number %d\n",
hw_p->devnum,
hw_p->stats.pkts_tx,
hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
hw_p->stats.pkts_tx = 0;
hw_p->stats.pkts_rx = 0;
hw_p->stats.pkts_handled = 0;
hw_p->print_speed = 1; /* print speed message again next time */
#endif
hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
hw_p->rx_slot = 0; /* MAL Receive Slot */
hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
hw_p->rx_u_index = 0; /* Receive User Queue Index */
hw_p->tx_slot = 0; /* MAL Transmit Slot */
hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
hw_p->tx_u_index = 0; /* Transmit User Queue Index */
#if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
/* set RMII mode */
/* NOTE: 440GX spec states that mode is mutually exclusive */
/* NOTE: Therefore, disable all other EMACS, since we handle */
/* NOTE: only one emac at a time */
reg = 0;
out_be32((void *)ZMII0_FER, 0);
udelay (100);
#if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
#elif defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
#endif
out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
#if defined(CONFIG_405EX)
ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
#endif
sync();
/* provide clocks for EMAC internal loopback */
emac_loopback_enable(hw_p);
/* EMAC RESET */
out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
/* remove clocks for EMAC internal loopback */
emac_loopback_disable(hw_p);
failsafe = 1000;
while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
udelay (1000);
failsafe--;
}
if (failsafe <= 0)
printf("\nProblem resetting EMAC!\n");
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
/* Whack the M1 register */
mode_reg = 0x0;
mode_reg &= ~0x00000038;
opbfreq = sysinfo.freqOPB / 1000000;
if (opbfreq <= 50);
else if (opbfreq <= 66)
mode_reg |= EMAC_MR1_OBCI_66;
else if (opbfreq <= 83)
mode_reg |= EMAC_MR1_OBCI_83;
else if (opbfreq <= 100)
mode_reg |= EMAC_MR1_OBCI_100;
else
mode_reg |= EMAC_MR1_OBCI_GT100;
out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
/*
* In SGMII mode, GPCS access is needed for
* communication with the internal SGMII SerDes.
*/
switch (devnum) {
#if defined(CONFIG_GPCS_PHY_ADDR)
case 0:
reg = CONFIG_GPCS_PHY_ADDR;
break;
#endif
#if defined(CONFIG_GPCS_PHY1_ADDR)
case 1:
reg = CONFIG_GPCS_PHY1_ADDR;
break;
#endif
#if defined(CONFIG_GPCS_PHY2_ADDR)
case 2:
reg = CONFIG_GPCS_PHY2_ADDR;
break;
#endif
#if defined(CONFIG_GPCS_PHY3_ADDR)
case 3:
reg = CONFIG_GPCS_PHY3_ADDR;
break;
#endif
}
mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
/* Configure GPCS interface to recommended setting for SGMII */
miiphy_reset(dev->name, reg);
miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
}
#endif /* defined(CONFIG_GPCS_PHY_ADDR) */
/* wait for PHY to complete auto negotiation */
reg_short = 0;
switch (devnum) {
case 0:
reg = CONFIG_PHY_ADDR;
break;
#if defined (CONFIG_PHY1_ADDR)
case 1:
reg = CONFIG_PHY1_ADDR;
break;
#endif
#if defined (CONFIG_PHY2_ADDR)
case 2:
reg = CONFIG_PHY2_ADDR;
break;
#endif
#if defined (CONFIG_PHY3_ADDR)
case 3:
reg = CONFIG_PHY3_ADDR;
break;
#endif
default:
reg = CONFIG_PHY_ADDR;
break;
}
bis->bi_phynum[devnum] = reg;
if (reg == CONFIG_FIXED_PHY)
goto get_speed;
#if defined(CONFIG_PHY_RESET)
/*
* Reset the phy, only if its the first time through
* otherwise, just check the speeds & feeds
*/
if (hw_p->first_init == 0) {
#if defined(CONFIG_M88E1111_PHY)
miiphy_write (dev->name, reg, 0x14, 0x0ce3);
miiphy_write (dev->name, reg, 0x18, 0x4101);
miiphy_write (dev->name, reg, 0x09, 0x0e00);
miiphy_write (dev->name, reg, 0x04, 0x01e1);
#if defined(CONFIG_M88E1111_DISABLE_FIBER)
miiphy_read(dev->name, reg, 0x1b, ®_short);
reg_short |= 0x8000;
miiphy_write(dev->name, reg, 0x1b, reg_short);
#endif
#endif
#if defined(CONFIG_M88E1112_PHY)
if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
/*
* Marvell 88E1112 PHY needs to have the SGMII MAC
* interace (page 2) properly configured to
* communicate with the 460EX/GT GPCS interface.
*/
/* Set access to Page 2 */
miiphy_write(dev->name, reg, 0x16, 0x0002);
miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
miiphy_read(dev->name, reg, 0x1a, ®_short);
reg_short |= 0x8000; /* bypass Auto-Negotiation */
miiphy_write(dev->name, reg, 0x1a, reg_short);
miiphy_reset(dev->name, reg); /* reset MAC interface */
/* Reset access to Page 0 */
miiphy_write(dev->name, reg, 0x16, 0x0000);
}
#endif /* defined(CONFIG_M88E1112_PHY) */
miiphy_reset (dev->name, reg);
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
#if defined(CONFIG_CIS8201_PHY)
/*
* Cicada 8201 PHY needs to have an extended register whacked
* for RGMII mode.
*/
if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
#if defined(CONFIG_CIS8201_SHORT_ETCH)
miiphy_write (dev->name, reg, 23, 0x1300);
#else
miiphy_write (dev->name, reg, 23, 0x1000);
#endif
/*
* Vitesse VSC8201/Cicada CIS8201 errata:
* Interoperability problem with Intel 82547EI phys
* This work around (provided by Vitesse) changes
* the default timer convergence from 8ms to 12ms
*/
miiphy_write (dev->name, reg, 0x1f, 0x2a30);
miiphy_write (dev->name, reg, 0x08, 0x0200);
miiphy_write (dev->name, reg, 0x1f, 0x52b5);
miiphy_write (dev->name, reg, 0x02, 0x0004);
miiphy_write (dev->name, reg, 0x01, 0x0671);
miiphy_write (dev->name, reg, 0x00, 0x8fae);
miiphy_write (dev->name, reg, 0x1f, 0x2a30);
miiphy_write (dev->name, reg, 0x08, 0x0000);
miiphy_write (dev->name, reg, 0x1f, 0x0000);
/* end Vitesse/Cicada errata */
}
#endif /* defined(CONFIG_CIS8201_PHY) */
#if defined(CONFIG_ET1011C_PHY)
/*
* Agere ET1011c PHY needs to have an extended register whacked
* for RGMII mode.
*/
if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
miiphy_read (dev->name, reg, 0x16, ®_short);
reg_short &= ~(0x7);
reg_short |= 0x6; /* RGMII DLL Delay*/
miiphy_write (dev->name, reg, 0x16, reg_short);
miiphy_read (dev->name, reg, 0x17, ®_short);
reg_short &= ~(0x40);
miiphy_write (dev->name, reg, 0x17, reg_short);
miiphy_write(dev->name, reg, 0x1c, 0x74f0);
}
#endif /* defined(CONFIG_ET1011C_PHY) */
#endif /* defined(CONFIG_440GX) ... */
/* Start/Restart autonegotiation */
phy_setup_aneg (dev->name, reg);
udelay (1000);
}
#endif /* defined(CONFIG_PHY_RESET) */
miiphy_read (dev->name, reg, MII_BMSR, ®_short);
/*
* Wait if PHY is capable of autonegotiation and autonegotiation is not complete
*/
if ((reg_short & BMSR_ANEGCAPABLE)
&& !(reg_short & BMSR_ANEGCOMPLETE)) {
puts ("Waiting for PHY auto negotiation to complete");
i = 0;
while (!(reg_short & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
puts (" TIMEOUT !\n");
break;
}
if ((i++ % 1000) == 0) {
putc ('.');
}
udelay (1000); /* 1 ms */
miiphy_read (dev->name, reg, MII_BMSR, ®_short);
}
puts (" done\n");
udelay (500000); /* another 500 ms (results in faster booting) */
}
get_speed:
if (reg == CONFIG_FIXED_PHY) {
for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
if (devnum == fixed_phy_port[i].devnum) {
speed = fixed_phy_port[i].speed;
duplex = fixed_phy_port[i].duplex;
break;
}
}
if (i == ARRAY_SIZE(fixed_phy_port)) {
printf("ERROR: PHY (%s) not configured correctly!\n",
dev->name);
return -1;
}
} else {
speed = miiphy_speed(dev->name, reg);
duplex = miiphy_duplex(dev->name, reg);
}
if (hw_p->print_speed) {
hw_p->print_speed = 0;
printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
(int) speed, (duplex == HALF) ? "HALF" : "FULL",
hw_p->devnum);
}
#if defined(CONFIG_440) && \
!defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
!defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
!defined(CONFIG_460EX) && !defined(CONFIG_460GT)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
mfsdr(SDR0_MFR, reg);
if (speed == 100) {
reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
} else {
reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
}
mtsdr(SDR0_MFR, reg);
#endif
/* Set ZMII/RGMII speed according to the phy link speed */
reg = in_be32((void *)ZMII0_SSR);
if ( (speed == 100) || (speed == 1000) )
out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
else
out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
if ((devnum == 2) || (devnum == 3)) {
if (speed == 1000)
reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
else if (speed == 100)
reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
else if (speed == 10)
reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
else {
printf("Error in RGMII Speed\n");
return -1;
}
out_be32((void *)RGMII_SSR, reg);
}
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
if (devnum >= 2)
rgmii_channel = devnum - 2;
else
rgmii_channel = devnum;
if (speed == 1000)
reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
else if (speed == 100)
reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
else if (speed == 10)
reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
else {
printf("Error in RGMII Speed\n");
return -1;
}
out_be32((void *)RGMII_SSR, reg);
#if defined(CONFIG_460GT)
if ((devnum == 2) || (devnum == 3))
out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
#endif
#endif
/* set the Mal configuration reg */
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
/* Errata 1.12: MAL_1 -- Disable MAL bursting */
if (get_pvr() == PVR_440GP_RB) {
mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
}
#endif
/*
* Malloc MAL buffer desciptors, make sure they are
* aligned on cache line boundary size
* (401/403/IOP480 = 16, 405 = 32)
* and doesn't cross cache block boundaries.
*/
if (hw_p->first_init == 0) {
debug("*** Allocating descriptor memory ***\n");
bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
if (!bd_cached) {
printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
return -1;
}
#ifdef CONFIG_4xx_DCACHE
flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
if (!last_used_ea)
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
#else
bd_uncached = bis->bi_memsize;
#endif
else
bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
last_used_ea = bd_uncached;
program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
TLB_WORD2_I_ENABLE);
#else
bd_uncached = bd_cached;
#endif
hw_p->tx_phys = bd_cached;
hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
hw_p->tx = (mal_desc_t *)(bd_uncached);
hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
}
for (i = 0; i < NUM_TX_BUFF; i++) {
hw_p->tx[i].ctrl = 0;
hw_p->tx[i].data_len = 0;
if (hw_p->first_init == 0)
hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
L1_CACHE_BYTES);
hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
if ((NUM_TX_BUFF - 1) == i)
hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
hw_p->tx_run[i] = -1;
debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr);
}
for (i = 0; i < NUM_RX_BUFF; i++) {
hw_p->rx[i].ctrl = 0;
hw_p->rx[i].data_len = 0;
hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
if ((NUM_RX_BUFF - 1) == i)
hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
hw_p->rx_ready[i] = -1;
debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr);
}
reg = 0x00000000;
reg |= dev->enetaddr[0]; /* set high address */
reg = reg << 8;
reg |= dev->enetaddr[1];
out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
reg = 0x00000000;
reg |= dev->enetaddr[2]; /* set low address */
reg = reg << 8;
reg |= dev->enetaddr[3];
reg = reg << 8;
reg |= dev->enetaddr[4];
reg = reg << 8;
reg |= dev->enetaddr[5];
out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
#else
mtdcr (MAL0_TXCTP1R, hw_p->tx_phys);
#endif
#if defined(CONFIG_440)
mtdcr (MAL0_TXBADDR, 0x0);
mtdcr (MAL0_RXBADDR, 0x0);
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
mtdcr (MAL0_RXCTP8R, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16);
#else
mtdcr (MAL0_RXCTP1R, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16);
#endif
break;
#if defined (CONFIG_440GX)
case 2:
/* setup MAL tx & rx channel pointers */
mtdcr (MAL0_TXBADDR, 0x0);
mtdcr (MAL0_RXBADDR, 0x0);
mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
mtdcr (MAL0_RXCTP2R, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16);
break;
case 3:
/* setup MAL tx & rx channel pointers */
mtdcr (MAL0_TXBADDR, 0x0);
mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
mtdcr (MAL0_RXBADDR, 0x0);
mtdcr (MAL0_RXCTP3R, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16);
break;
#endif /* CONFIG_440GX */
#if defined (CONFIG_460GT)
case 2:
/* setup MAL tx & rx channel pointers */
mtdcr (MAL0_TXBADDR, 0x0);
mtdcr (MAL0_RXBADDR, 0x0);
mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
mtdcr (MAL0_RXCTP16R, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16);
break;
case 3:
/* setup MAL tx & rx channel pointers */
mtdcr (MAL0_TXBADDR, 0x0);
mtdcr (MAL0_RXBADDR, 0x0);
mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
mtdcr (MAL0_RXCTP24R, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16);
break;
#endif /* CONFIG_460GT */
case 0:
default:
/* setup MAL tx & rx channel pointers */
#if defined(CONFIG_440)
mtdcr (MAL0_TXBADDR, 0x0);
mtdcr (MAL0_RXBADDR, 0x0);
#endif
mtdcr (MAL0_TXCTP0R, hw_p->tx_phys);
mtdcr (MAL0_RXCTP0R, hw_p->rx_phys);
/* set RX buffer size */
mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16);
break;
}
/* Enable MAL transmit and receive channels */
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
#endif
mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
/* set transmit enable & receive enable */
out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
/* set rx-/tx-fifo size */
mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
/* set speed */
if (speed == _1000BASET) {
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
unsigned long pfc1;
mfsdr (SDR0_PFC1, pfc1);
pfc1 |= SDR0_PFC1_EM_1000;
mtsdr (SDR0_PFC1, pfc1);
#endif
mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
} else if (speed == _100BASET)
mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
else
mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
if (duplex == FULL)
mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
/* Enable broadcast and indvidual address */
/* TBS: enabling runts as some misbehaved nics will send runts */
out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
/* we probably need to set the tx mode1 reg? maybe at tx time */
/* set transmit request threshold register */
out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440s has a 64 byte burst length */
out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
#else
/* 405s have a 16 byte burst length */
out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
#endif /* defined(CONFIG_440) */
out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
/* Set fifo limit entry in tx mode 0 */
out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
/* Frame gap set */
out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
/* Set EMAC IER */
hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
if (speed == _100BASET)
hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
if (hw_p->first_init == 0) {
/*
* Connect interrupt service routines
*/
irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
(interrupt_handler_t *) enetInt, dev);
}
mtmsr (msr); /* enable interrupts again */
hw_p->bis = bis;
hw_p->first_init = 1;
return 0;
}
static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
int len)
{
struct enet_frame *ef_ptr;
ulong time_start, time_now;
unsigned long temp_txm0;
EMAC_4XX_HW_PST hw_p = dev->priv;
ef_ptr = (struct enet_frame *) ptr;
/*-----------------------------------------------------------------------+
* Copy in our address into the frame.
*-----------------------------------------------------------------------*/
(void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
/*-----------------------------------------------------------------------+
* If frame is too long or too short, modify length.
*-----------------------------------------------------------------------*/
/* TBS: where does the fragment go???? */
if (len > ENET_MAX_MTU)
len = ENET_MAX_MTU;
/* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
/*-----------------------------------------------------------------------+
* set TX Buffer busy, and send it
*-----------------------------------------------------------------------*/
hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
hw_p->tx[hw_p->tx_slot].data_len = (short) len;
hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
sync();
out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
#ifdef INFO_4XX_ENET
hw_p->stats.pkts_tx++;
#endif
/*-----------------------------------------------------------------------+
* poll unitl the packet is sent and then make sure it is OK
*-----------------------------------------------------------------------*/
time_start = get_timer (0);
while (1) {
temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
/* loop until either TINT turns on or 3 seconds elapse */
if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
/* transmit is done, so now check for errors
* If there is an error, an interrupt should
* happen when we return
*/
time_now = get_timer (0);
if ((time_now - time_start) > 3000) {
return (-1);
}
} else {
return (len);
}
}
}
int enetInt (struct eth_device *dev)
{
int serviced;
int rc = -1; /* default to not us */
u32 mal_isr;
u32 emac_isr = 0;
u32 mal_eob;
u32 uic_mal;
u32 uic_mal_err;
u32 uic_emac;
u32 uic_emac_b;
EMAC_4XX_HW_PST hw_p;
/*
* Because the mal is generic, we need to get the current
* eth device
*/
dev = eth_get_dev();
hw_p = dev->priv;
/* enter loop that stays in interrupt code until nothing to service */
do {
serviced = 0;
uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
&& !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
&& !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
/* not for us */
return (rc);
}
/* get and clear controller status interrupts */
/* look at MAL and EMAC error interrupts */
if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
/* we have a MAL error interrupt */
mal_isr = mfdcr(MAL0_ESR);
mal_err(dev, mal_isr, uic_mal_err,
MAL_UIC_DEF, MAL_UIC_ERR);
/* clear MAL error interrupt status bits */
mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
return -1;
}
/* look for EMAC errors */
if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
emac_err(dev, emac_isr);
/* clear EMAC error interrupt status bits */
mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
return -1;
}
/* handle MAX TX EOB interrupt from a tx */
if (uic_mal & UIC_MAL_TXEOB) {
/* clear MAL interrupt status bits */
mal_eob = mfdcr(MAL0_TXEOBISR);
mtdcr(MAL0_TXEOBISR, mal_eob);
mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
/* indicate that we serviced an interrupt */
serviced = 1;
rc = 0;
}
/* handle MAL RX EOB interrupt from a receive */
/* check for EOB on valid channels */
if (uic_mal & UIC_MAL_RXEOB) {
mal_eob = mfdcr(MAL0_RXEOBISR);
if (mal_eob &
(0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
/* push packet to upper layer */
enet_rcv(dev, emac_isr);
/* clear MAL interrupt status bits */
mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
/* indicate that we serviced an interrupt */
serviced = 1;
rc = 0;
}
}
#if defined(CONFIG_405EZ)
/*
* On 405EZ the RX-/TX-interrupts are coalesced into
* one IRQ bit in the UIC. We need to acknowledge the
* RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
*/
mtsdr(SDR0_ICINTSTAT,
SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
#endif /* defined(CONFIG_405EZ) */
} while (serviced);
return (rc);
}
/*-----------------------------------------------------------------------------+
* MAL Error Routine
*-----------------------------------------------------------------------------*/
static void mal_err (struct eth_device *dev, unsigned long isr,
unsigned long uic, unsigned long maldef,
unsigned long mal_errr)
{
EMAC_4XX_HW_PST hw_p = dev->priv;
mtdcr (MAL0_ESR, isr); /* clear interrupt */
/* clear DE interrupt */
mtdcr (MAL0_TXDEIR, 0xC0000000);
mtdcr (MAL0_RXDEIR, 0x80000000);
#ifdef INFO_4XX_ENET
printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
#endif
eth_init (hw_p->bis); /* start again... */
}
/*-----------------------------------------------------------------------------+
* EMAC Error Routine
*-----------------------------------------------------------------------------*/
static void emac_err (struct eth_device *dev, unsigned long isr)
{
EMAC_4XX_HW_PST hw_p = dev->priv;
printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
}
/*-----------------------------------------------------------------------------+
* enet_rcv() handles the ethernet receive data
*-----------------------------------------------------------------------------*/
static void enet_rcv (struct eth_device *dev, unsigned long malisr)
{
unsigned long data_len;
unsigned long rx_eob_isr;
EMAC_4XX_HW_PST hw_p = dev->priv;
int handled = 0;
int i;
int loop_count = 0;
rx_eob_isr = mfdcr (MAL0_RXEOBISR);
if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
/* clear EOB */
mtdcr (MAL0_RXEOBISR, rx_eob_isr);
/* EMAC RX done */
while (1) { /* do all */
i = hw_p->rx_slot;
if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
|| (loop_count >= NUM_RX_BUFF))
break;
loop_count++;
handled++;
data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
if (data_len) {
if (data_len > ENET_MAX_MTU) /* Check len */
data_len = 0;
else {
if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
data_len = 0;
hw_p->stats.rx_err_log[hw_p->
rx_err_index]
= hw_p->rx[i].ctrl;
hw_p->rx_err_index++;
if (hw_p->rx_err_index ==
MAX_ERR_LOG)
hw_p->rx_err_index =
0;
} /* emac_erros */
} /* data_len < max mtu */
} /* if data_len */
if (!data_len) { /* no data */
hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
hw_p->stats.data_len_err++; /* Error at Rx */
}
/* !data_len */
/* AS.HARNOIS */
/* Check if user has already eaten buffer */
/* if not => ERROR */
else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
if (hw_p->is_receiving)
printf ("ERROR : Receive buffers are full!\n");
break;
} else {
hw_p->stats.rx_frames++;
hw_p->stats.rx += data_len;
#ifdef INFO_4XX_ENET
hw_p->stats.pkts_rx++;
#endif
/* AS.HARNOIS
* use ring buffer
*/
hw_p->rx_ready[hw_p->rx_i_index] = i;
hw_p->rx_i_index++;
if (NUM_RX_BUFF == hw_p->rx_i_index)
hw_p->rx_i_index = 0;
hw_p->rx_slot++;
if (NUM_RX_BUFF == hw_p->rx_slot)
hw_p->rx_slot = 0;
/* AS.HARNOIS
* free receive buffer only when
* buffer has been handled (eth_rx)
rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
*/
} /* if data_len */
} /* while */
} /* if EMACK_RXCHL */
}
static int ppc_4xx_eth_rx (struct eth_device *dev)
{
int length;
int user_index;
unsigned long msr;
EMAC_4XX_HW_PST hw_p = dev->priv;
hw_p->is_receiving = 1; /* tell driver */
for (;;) {
/* AS.HARNOIS
* use ring buffer and
* get index from rx buffer desciptor queue
*/
user_index = hw_p->rx_ready[hw_p->rx_u_index];
if (user_index == -1) {
length = -1;
break; /* nothing received - leave for() loop */
}
msr = mfmsr ();
mtmsr (msr & ~(MSR_EE));
length = hw_p->rx[user_index].data_len & 0x0fff;
/* Pass the packet up to the protocol layers. */
/* NetReceive(NetRxPackets[rxIdx], length - 4); */
/* NetReceive(NetRxPackets[i], length); */
invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
(u32)hw_p->rx[user_index].data_ptr +
length - 4);
NetReceive (NetRxPackets[user_index], length - 4);
/* Free Recv Buffer */
hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
/* Free rx buffer descriptor queue */
hw_p->rx_ready[hw_p->rx_u_index] = -1;
hw_p->rx_u_index++;
if (NUM_RX_BUFF == hw_p->rx_u_index)
hw_p->rx_u_index = 0;
#ifdef INFO_4XX_ENET
hw_p->stats.pkts_handled++;
#endif
mtmsr (msr); /* Enable IRQ's */
}
hw_p->is_receiving = 0; /* tell driver */
return length;
}
int ppc_4xx_eth_initialize (bd_t * bis)
{
static int virgin = 0;
struct eth_device *dev;
int eth_num = 0;
EMAC_4XX_HW_PST hw = NULL;
u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
u32 hw_addr[4];
u32 mal_ier;
#if defined(CONFIG_440GX)
unsigned long pfc1;
mfsdr (SDR0_PFC1, pfc1);
pfc1 &= ~(0x01e00000);
pfc1 |= 0x01200000;
mtsdr (SDR0_PFC1, pfc1);
#endif
/* first clear all mac-addresses */
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
switch (eth_num) {
default: /* fall through */
case 0:
eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
hw_addr[eth_num] = 0x0;
break;
#ifdef CONFIG_HAS_ETH1
case 1:
eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
hw_addr[eth_num] = 0x100;
break;
#endif
#ifdef CONFIG_HAS_ETH2
case 2:
eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
#if defined(CONFIG_460GT)
hw_addr[eth_num] = 0x300;
#else
hw_addr[eth_num] = 0x400;
#endif
break;
#endif
#ifdef CONFIG_HAS_ETH3
case 3:
eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
#if defined(CONFIG_460GT)
hw_addr[eth_num] = 0x400;
#else
hw_addr[eth_num] = 0x600;
#endif
break;
#endif
}
}
/* set phy num and mode */
bis->bi_phynum[0] = CONFIG_PHY_ADDR;
bis->bi_phymode[0] = 0;
#if defined(CONFIG_PHY1_ADDR)
bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
bis->bi_phymode[1] = 0;
#endif
#if defined(CONFIG_440GX)
bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
bis->bi_phymode[2] = 2;
bis->bi_phymode[3] = 2;
#endif
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
ppc_4xx_eth_setup_bridge(0, bis);
#endif
for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
/*
* See if we can actually bring up the interface,
* otherwise, skip it
*/
if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
continue;
}
/* Allocate device structure */
dev = (struct eth_device *) malloc (sizeof (*dev));
if (dev == NULL) {
printf ("ppc_4xx_eth_initialize: "
"Cannot allocate eth_device %d\n", eth_num);
return (-1);
}
memset(dev, 0, sizeof(*dev));
/* Allocate our private use data */
hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
if (hw == NULL) {
printf ("ppc_4xx_eth_initialize: "
"Cannot allocate private hw data for eth_device %d",
eth_num);
free (dev);
return (-1);
}
memset(hw, 0, sizeof(*hw));
hw->hw_addr = hw_addr[eth_num];
memcpy (dev->enetaddr, ethaddr[eth_num], 6);
hw->devnum = eth_num;
hw->print_speed = 1;
sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
dev->priv = (void *) hw;
dev->init = ppc_4xx_eth_init;
dev->halt = ppc_4xx_eth_halt;
dev->send = ppc_4xx_eth_send;
dev->recv = ppc_4xx_eth_rx;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name,
emac4xx_miiphy_read, emac4xx_miiphy_write);
#endif
if (0 == virgin) {
/* set the MAL IER ??? names may change with new spec ??? */
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
mal_ier =
MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
#else
mal_ier =
MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
MAL_IER_OPBE | MAL_IER_PLBE;
#endif
mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */
mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */
mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */
mtdcr (MAL0_IER, mal_ier);
/* install MAL interrupt handler */
irq_install_handler (VECNUM_MAL_SERR,
(interrupt_handler_t *) enetInt,
dev);
irq_install_handler (VECNUM_MAL_TXEOB,
(interrupt_handler_t *) enetInt,
dev);
irq_install_handler (VECNUM_MAL_RXEOB,
(interrupt_handler_t *) enetInt,
dev);
irq_install_handler (VECNUM_MAL_TXDE,
(interrupt_handler_t *) enetInt,
dev);
irq_install_handler (VECNUM_MAL_RXDE,
(interrupt_handler_t *) enetInt,
dev);
virgin = 1;
}
} /* end for each supported device */
return 0;
}
|
1001-study-uboot
|
drivers/net/4xx_enet.c
|
C
|
gpl3
| 63,317
|
#include "e1000.h"
#include <linux/compiler.h>
/*-----------------------------------------------------------------------
* SPI transfer
*
* This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
* "bitlen" bits in the SPI MISO port. That's just the way SPI works.
*
* The source of the outgoing bits is the "dout" parameter and the
* destination of the input bits is the "din" parameter. Note that "dout"
* and "din" can point to the same memory location, in which case the
* input data overwrites the output data (since both are buffered by
* temporary variables, this is OK).
*
* This may be interrupted with Ctrl-C if "intr" is true, otherwise it will
* never return an error.
*/
static int e1000_spi_xfer(struct e1000_hw *hw, unsigned int bitlen,
const void *dout_mem, void *din_mem, boolean_t intr)
{
const uint8_t *dout = dout_mem;
uint8_t *din = din_mem;
uint8_t mask = 0;
uint32_t eecd;
unsigned long i;
/* Pre-read the control register */
eecd = E1000_READ_REG(hw, EECD);
/* Iterate over each bit */
for (i = 0, mask = 0x80; i < bitlen; i++, mask = (mask >> 1)?:0x80) {
/* Check for interrupt */
if (intr && ctrlc())
return -1;
/* Determine the output bit */
if (dout && dout[i >> 3] & mask)
eecd |= E1000_EECD_DI;
else
eecd &= ~E1000_EECD_DI;
/* Write the output bit and wait 50us */
E1000_WRITE_REG(hw, EECD, eecd);
E1000_WRITE_FLUSH(hw);
udelay(50);
/* Poke the clock (waits 50us) */
e1000_raise_ee_clk(hw, &eecd);
/* Now read the input bit */
eecd = E1000_READ_REG(hw, EECD);
if (din) {
if (eecd & E1000_EECD_DO)
din[i >> 3] |= mask;
else
din[i >> 3] &= ~mask;
}
/* Poke the clock again (waits 50us) */
e1000_lower_ee_clk(hw, &eecd);
}
/* Now clear any remaining bits of the input */
if (din && (i & 7))
din[i >> 3] &= ~((mask << 1) - 1);
return 0;
}
#ifdef CONFIG_E1000_SPI_GENERIC
static inline struct e1000_hw *e1000_hw_from_spi(struct spi_slave *spi)
{
return container_of(spi, struct e1000_hw, spi);
}
/* Not sure why all of these are necessary */
void spi_init_r(void) { /* Nothing to do */ }
void spi_init_f(void) { /* Nothing to do */ }
void spi_init(void) { /* Nothing to do */ }
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
/* Find the right PCI device */
struct e1000_hw *hw = e1000_find_card(bus);
if (!hw) {
printf("ERROR: No such e1000 device: e1000#%u\n", bus);
return NULL;
}
/* Make sure it has an SPI chip */
if (hw->eeprom.type != e1000_eeprom_spi) {
E1000_ERR(hw->nic, "No attached SPI EEPROM found!\n");
return NULL;
}
/* Argument sanity checks */
if (cs != 0) {
E1000_ERR(hw->nic, "No such SPI chip: %u\n", cs);
return NULL;
}
if (mode != SPI_MODE_0) {
E1000_ERR(hw->nic, "Only SPI MODE-0 is supported!\n");
return NULL;
}
/* TODO: Use max_hz somehow */
E1000_DBG(hw->nic, "EEPROM SPI access requested\n");
return &hw->spi;
}
void spi_free_slave(struct spi_slave *spi)
{
__maybe_unused struct e1000_hw *hw = e1000_hw_from_spi(spi);
E1000_DBG(hw->nic, "EEPROM SPI access released\n");
}
int spi_claim_bus(struct spi_slave *spi)
{
struct e1000_hw *hw = e1000_hw_from_spi(spi);
if (e1000_acquire_eeprom(hw)) {
E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n");
return -1;
}
return 0;
}
void spi_release_bus(struct spi_slave *spi)
{
struct e1000_hw *hw = e1000_hw_from_spi(spi);
e1000_release_eeprom(hw);
}
/* Skinny wrapper around e1000_spi_xfer */
int spi_xfer(struct spi_slave *spi, unsigned int bitlen,
const void *dout_mem, void *din_mem, unsigned long flags)
{
struct e1000_hw *hw = e1000_hw_from_spi(spi);
int ret;
if (flags & SPI_XFER_BEGIN)
e1000_standby_eeprom(hw);
ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, TRUE);
if (flags & SPI_XFER_END)
e1000_standby_eeprom(hw);
return ret;
}
#endif /* not CONFIG_E1000_SPI_GENERIC */
#ifdef CONFIG_CMD_E1000
/* The EEPROM opcodes */
#define SPI_EEPROM_ENABLE_WR 0x06
#define SPI_EEPROM_DISABLE_WR 0x04
#define SPI_EEPROM_WRITE_STATUS 0x01
#define SPI_EEPROM_READ_STATUS 0x05
#define SPI_EEPROM_WRITE_PAGE 0x02
#define SPI_EEPROM_READ_PAGE 0x03
/* The EEPROM status bits */
#define SPI_EEPROM_STATUS_BUSY 0x01
#define SPI_EEPROM_STATUS_WREN 0x02
static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, boolean_t intr)
{
u8 op[] = { SPI_EEPROM_ENABLE_WR };
e1000_standby_eeprom(hw);
return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
}
/*
* These have been tested to perform correctly, but they are not used by any
* of the EEPROM commands at this time.
*/
#if 0
static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, boolean_t intr)
{
u8 op[] = { SPI_EEPROM_DISABLE_WR };
e1000_standby_eeprom(hw);
return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
}
static int e1000_spi_eeprom_write_status(struct e1000_hw *hw,
u8 status, boolean_t intr)
{
u8 op[] = { SPI_EEPROM_WRITE_STATUS, status };
e1000_standby_eeprom(hw);
return e1000_spi_xfer(hw, 8*sizeof(op), op, NULL, intr);
}
#endif
static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, boolean_t intr)
{
u8 op[] = { SPI_EEPROM_READ_STATUS, 0 };
e1000_standby_eeprom(hw);
if (e1000_spi_xfer(hw, 8*sizeof(op), op, op, intr))
return -1;
return op[1];
}
static int e1000_spi_eeprom_write_page(struct e1000_hw *hw,
const void *data, u16 off, u16 len, boolean_t intr)
{
u8 op[] = {
SPI_EEPROM_WRITE_PAGE,
(off >> (hw->eeprom.address_bits - 8)) & 0xff, off & 0xff
};
e1000_standby_eeprom(hw);
if (e1000_spi_xfer(hw, 8 + hw->eeprom.address_bits, op, NULL, intr))
return -1;
if (e1000_spi_xfer(hw, len << 3, data, NULL, intr))
return -1;
return 0;
}
static int e1000_spi_eeprom_read_page(struct e1000_hw *hw,
void *data, u16 off, u16 len, boolean_t intr)
{
u8 op[] = {
SPI_EEPROM_READ_PAGE,
(off >> (hw->eeprom.address_bits - 8)) & 0xff, off & 0xff
};
e1000_standby_eeprom(hw);
if (e1000_spi_xfer(hw, 8 + hw->eeprom.address_bits, op, NULL, intr))
return -1;
if (e1000_spi_xfer(hw, len << 3, NULL, data, intr))
return -1;
return 0;
}
static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, boolean_t intr)
{
int status;
while ((status = e1000_spi_eeprom_read_status(hw, intr)) >= 0) {
if (!(status & SPI_EEPROM_STATUS_BUSY))
return 0;
}
return -1;
}
static int e1000_spi_eeprom_dump(struct e1000_hw *hw,
void *data, u16 off, unsigned int len, boolean_t intr)
{
/* Interruptibly wait for the EEPROM to be ready */
if (e1000_spi_eeprom_poll_ready(hw, intr))
return -1;
/* Dump each page in sequence */
while (len) {
/* Calculate the data bytes on this page */
u16 pg_off = off & (hw->eeprom.page_size - 1);
u16 pg_len = hw->eeprom.page_size - pg_off;
if (pg_len > len)
pg_len = len;
/* Now dump the page */
if (e1000_spi_eeprom_read_page(hw, data, off, pg_len, intr))
return -1;
/* Otherwise go on to the next page */
len -= pg_len;
off += pg_len;
data += pg_len;
}
/* We're done! */
return 0;
}
static int e1000_spi_eeprom_program(struct e1000_hw *hw,
const void *data, u16 off, u16 len, boolean_t intr)
{
/* Program each page in sequence */
while (len) {
/* Calculate the data bytes on this page */
u16 pg_off = off & (hw->eeprom.page_size - 1);
u16 pg_len = hw->eeprom.page_size - pg_off;
if (pg_len > len)
pg_len = len;
/* Interruptibly wait for the EEPROM to be ready */
if (e1000_spi_eeprom_poll_ready(hw, intr))
return -1;
/* Enable write access */
if (e1000_spi_eeprom_enable_wr(hw, intr))
return -1;
/* Now program the page */
if (e1000_spi_eeprom_write_page(hw, data, off, pg_len, intr))
return -1;
/* Otherwise go on to the next page */
len -= pg_len;
off += pg_len;
data += pg_len;
}
/* Wait for the last write to complete */
if (e1000_spi_eeprom_poll_ready(hw, intr))
return -1;
/* We're done! */
return 0;
}
static int do_e1000_spi_show(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
int argc, char * const argv[])
{
unsigned int length = 0;
u16 i, offset = 0;
u8 *buffer;
int err;
if (argc > 2) {
cmd_usage(cmdtp);
return 1;
}
/* Parse the offset and length */
if (argc >= 1)
offset = simple_strtoul(argv[0], NULL, 0);
if (argc == 2)
length = simple_strtoul(argv[1], NULL, 0);
else if (offset < (hw->eeprom.word_size << 1))
length = (hw->eeprom.word_size << 1) - offset;
/* Extra sanity checks */
if (!length) {
E1000_ERR(hw->nic, "Requested zero-sized dump!\n");
return 1;
}
if ((0x10000 < length) || (0x10000 - length < offset)) {
E1000_ERR(hw->nic, "Can't dump past 0xFFFF!\n");
return 1;
}
/* Allocate a buffer to hold stuff */
buffer = malloc(length);
if (!buffer) {
E1000_ERR(hw->nic, "Out of Memory!\n");
return 1;
}
/* Acquire the EEPROM and perform the dump */
if (e1000_acquire_eeprom(hw)) {
E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n");
free(buffer);
return 1;
}
err = e1000_spi_eeprom_dump(hw, buffer, offset, length, TRUE);
e1000_release_eeprom(hw);
if (err) {
E1000_ERR(hw->nic, "Interrupted!\n");
free(buffer);
return 1;
}
/* Now hexdump the result */
printf("%s: ===== Intel e1000 EEPROM (0x%04hX - 0x%04hX) =====",
hw->nic->name, offset, offset + length - 1);
for (i = 0; i < length; i++) {
if ((i & 0xF) == 0)
printf("\n%s: %04hX: ", hw->nic->name, offset + i);
else if ((i & 0xF) == 0x8)
printf(" ");
printf(" %02hx", buffer[i]);
}
printf("\n");
/* Success! */
free(buffer);
return 0;
}
static int do_e1000_spi_dump(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
int argc, char * const argv[])
{
unsigned int length;
u16 offset;
void *dest;
if (argc != 3) {
cmd_usage(cmdtp);
return 1;
}
/* Parse the arguments */
dest = (void *)simple_strtoul(argv[0], NULL, 16);
offset = simple_strtoul(argv[1], NULL, 0);
length = simple_strtoul(argv[2], NULL, 0);
/* Extra sanity checks */
if (!length) {
E1000_ERR(hw->nic, "Requested zero-sized dump!\n");
return 1;
}
if ((0x10000 < length) || (0x10000 - length < offset)) {
E1000_ERR(hw->nic, "Can't dump past 0xFFFF!\n");
return 1;
}
/* Acquire the EEPROM */
if (e1000_acquire_eeprom(hw)) {
E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n");
return 1;
}
/* Perform the programming operation */
if (e1000_spi_eeprom_dump(hw, dest, offset, length, TRUE) < 0) {
E1000_ERR(hw->nic, "Interrupted!\n");
e1000_release_eeprom(hw);
return 1;
}
e1000_release_eeprom(hw);
printf("%s: ===== EEPROM DUMP COMPLETE =====\n", hw->nic->name);
return 0;
}
static int do_e1000_spi_program(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
int argc, char * const argv[])
{
unsigned int length;
const void *source;
u16 offset;
if (argc != 3) {
cmd_usage(cmdtp);
return 1;
}
/* Parse the arguments */
source = (const void *)simple_strtoul(argv[0], NULL, 16);
offset = simple_strtoul(argv[1], NULL, 0);
length = simple_strtoul(argv[2], NULL, 0);
/* Acquire the EEPROM */
if (e1000_acquire_eeprom(hw)) {
E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n");
return 1;
}
/* Perform the programming operation */
if (e1000_spi_eeprom_program(hw, source, offset, length, TRUE) < 0) {
E1000_ERR(hw->nic, "Interrupted!\n");
e1000_release_eeprom(hw);
return 1;
}
e1000_release_eeprom(hw);
printf("%s: ===== EEPROM PROGRAMMED =====\n", hw->nic->name);
return 0;
}
static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
int argc, char * const argv[])
{
uint16_t i, length, checksum = 0, checksum_reg;
uint16_t *buffer;
boolean_t upd;
if (argc == 0)
upd = 0;
else if ((argc == 1) && !strcmp(argv[0], "update"))
upd = 1;
else {
cmd_usage(cmdtp);
return 1;
}
/* Allocate a temporary buffer */
length = sizeof(uint16_t) * (EEPROM_CHECKSUM_REG + 1);
buffer = malloc(length);
if (!buffer) {
E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
return 1;
}
/* Acquire the EEPROM */
if (e1000_acquire_eeprom(hw)) {
E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n");
return 1;
}
/* Read the EEPROM */
if (e1000_spi_eeprom_dump(hw, buffer, 0, length, TRUE) < 0) {
E1000_ERR(hw->nic, "Interrupted!\n");
e1000_release_eeprom(hw);
return 1;
}
/* Compute the checksum and read the expected value */
for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
checksum += le16_to_cpu(buffer[i]);
checksum = ((uint16_t)EEPROM_SUM) - checksum;
checksum_reg = le16_to_cpu(buffer[i]);
/* Verify it! */
if (checksum_reg == checksum) {
printf("%s: INFO: EEPROM checksum is correct! (0x%04hx)\n",
hw->nic->name, checksum);
e1000_release_eeprom(hw);
return 0;
}
/* Hrm, verification failed, print an error */
E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n",
checksum_reg, checksum);
/* If they didn't ask us to update it, just return an error */
if (!upd) {
e1000_release_eeprom(hw);
return 1;
}
/* Ok, correct it! */
printf("%s: Reprogramming the EEPROM checksum...\n", hw->nic->name);
buffer[i] = cpu_to_le16(checksum);
if (e1000_spi_eeprom_program(hw, &buffer[i], i * sizeof(uint16_t),
sizeof(uint16_t), TRUE)) {
E1000_ERR(hw->nic, "Interrupted!\n");
e1000_release_eeprom(hw);
return 1;
}
e1000_release_eeprom(hw);
return 0;
}
int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw,
int argc, char * const argv[])
{
if (argc < 1) {
cmd_usage(cmdtp);
return 1;
}
/* Make sure it has an SPI chip */
if (hw->eeprom.type != e1000_eeprom_spi) {
E1000_ERR(hw->nic, "No attached SPI EEPROM found!\n");
return 1;
}
/* Check the eeprom sub-sub-command arguments */
if (!strcmp(argv[0], "show"))
return do_e1000_spi_show(cmdtp, hw, argc - 1, argv + 1);
if (!strcmp(argv[0], "dump"))
return do_e1000_spi_dump(cmdtp, hw, argc - 1, argv + 1);
if (!strcmp(argv[0], "program"))
return do_e1000_spi_program(cmdtp, hw, argc - 1, argv + 1);
if (!strcmp(argv[0], "checksum"))
return do_e1000_spi_checksum(cmdtp, hw, argc - 1, argv + 1);
cmd_usage(cmdtp);
return 1;
}
#endif /* not CONFIG_CMD_E1000 */
|
1001-study-uboot
|
drivers/net/e1000_spi.c
|
C
|
gpl3
| 14,112
|
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Designware ethernet IP driver for u-boot
*/
#include <common.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/err.h>
#include <asm/io.h>
#include "designware.h"
static void tx_descs_init(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
char *txbuffs = &priv->txbuffs[0];
struct dmamacdescr *desc_p;
u32 idx;
for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
desc_p->dmamac_next = &desc_table_p[idx + 1];
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
DESC_TXSTS_TXCHECKINSCTRL | \
DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
desc_p->dmamac_cntl = 0;
desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
#else
desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
desc_p->txrx_status = 0;
#endif
}
/* Correcting the last pointer of the chain */
desc_p->dmamac_next = &desc_table_p[0];
writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
}
static void rx_descs_init(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
char *rxbuffs = &priv->rxbuffs[0];
struct dmamacdescr *desc_p;
u32 idx;
for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
desc_p = &desc_table_p[idx];
desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
desc_p->dmamac_next = &desc_table_p[idx + 1];
desc_p->dmamac_cntl =
(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
DESC_RXCTRL_RXCHAIN;
desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
}
/* Correcting the last pointer of the chain */
desc_p->dmamac_next = &desc_table_p[0];
writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
}
static void descs_init(struct eth_device *dev)
{
tx_descs_init(dev);
rx_descs_init(dev);
}
static int mac_reset(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
int timeout = CONFIG_MACRESET_TIMEOUT;
writel(DMAMAC_SRST, &dma_p->busmode);
writel(MII_PORTSELECT, &mac_p->conf);
do {
if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
return 0;
udelay(1000);
} while (timeout--);
return -1;
}
static int dw_write_hwaddr(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 macid_lo, macid_hi;
u8 *mac_id = &dev->enetaddr[0];
macid_lo = mac_id[0] + (mac_id[1] << 8) + \
(mac_id[2] << 16) + (mac_id[3] << 24);
macid_hi = mac_id[4] + (mac_id[5] << 8);
writel(macid_hi, &mac_p->macaddr0hi);
writel(macid_lo, &mac_p->macaddr0lo);
return 0;
}
static int dw_eth_init(struct eth_device *dev, bd_t *bis)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 conf;
/* Reset ethernet hardware */
if (mac_reset(dev) < 0)
return -1;
writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
&dma_p->busmode);
writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
conf = FRAMEBURSTENABLE | DISABLERXOWN;
if (priv->speed != SPEED_1000M)
conf |= MII_PORTSELECT;
if (priv->duplex == FULL_DUPLEX)
conf |= FULLDPLXMODE;
writel(conf, &mac_p->conf);
descs_init(dev);
/*
* Start/Enable xfer at dma as well as mac level
*/
writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf);
writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf);
return 0;
}
static int dw_eth_send(struct eth_device *dev, volatile void *packet,
int length)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_dma_regs *dma_p = priv->dma_regs_p;
u32 desc_num = priv->tx_currdescnum;
struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
/* Check if the descriptor is owned by CPU */
if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
printf("CPU not owner of tx frame\n");
return -1;
}
memcpy((void *)desc_p->dmamac_addr, (void *)packet, length);
#if defined(CONFIG_DW_ALTDESCRIPTOR)
desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
DESC_TXCTRL_SIZE1MASK;
desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
#else
desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
DESC_TXCTRL_TXFIRST;
desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
#endif
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_TX_DESCR_NUM)
desc_num = 0;
priv->tx_currdescnum = desc_num;
/* Start the transmission */
writel(POLL_DATA, &dma_p->txpolldemand);
return 0;
}
static int dw_eth_recv(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
u32 desc_num = priv->rx_currdescnum;
struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
u32 status = desc_p->txrx_status;
int length = 0;
/* Check if the owner is the CPU */
if (!(status & DESC_RXSTS_OWNBYDMA)) {
length = (status & DESC_RXSTS_FRMLENMSK) >> \
DESC_RXSTS_FRMLENSHFT;
NetReceive(desc_p->dmamac_addr, length);
/*
* Make the current descriptor valid again and go to
* the next one
*/
desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
/* Test the wrap-around condition. */
if (++desc_num >= CONFIG_RX_DESCR_NUM)
desc_num = 0;
}
priv->rx_currdescnum = desc_num;
return length;
}
static void dw_eth_halt(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
mac_reset(dev);
priv->tx_currdescnum = priv->rx_currdescnum = 0;
}
static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 miiaddr;
int timeout = CONFIG_MDIO_TIMEOUT;
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
((reg << MIIREGSHIFT) & MII_REGMSK);
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
do {
if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
*val = readl(&mac_p->miidata);
return 0;
}
udelay(1000);
} while (timeout--);
return -1;
}
static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
{
struct dw_eth_dev *priv = dev->priv;
struct eth_mac_regs *mac_p = priv->mac_regs_p;
u32 miiaddr;
int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
u16 value;
writel(val, &mac_p->miidata);
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
do {
if (!(readl(&mac_p->miiaddr) & MII_BUSY))
ret = 0;
udelay(1000);
} while (timeout--);
/* Needed as a fix for ST-Phy */
eth_mdio_read(dev, addr, reg, &value);
return ret;
}
#if defined(CONFIG_DW_SEARCH_PHY)
static int find_phy(struct eth_device *dev)
{
int phy_addr = 0;
u16 ctrl, oldctrl;
do {
eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
oldctrl = ctrl & BMCR_ANENABLE;
ctrl ^= BMCR_ANENABLE;
eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
ctrl &= BMCR_ANENABLE;
if (ctrl == oldctrl) {
phy_addr++;
} else {
ctrl ^= BMCR_ANENABLE;
eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
return phy_addr;
}
} while (phy_addr < 32);
return -1;
}
#endif
static int dw_reset_phy(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
u16 ctrl;
int timeout = CONFIG_PHYRESET_TIMEOUT;
u32 phy_addr = priv->address;
eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
do {
eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
if (!(ctrl & BMCR_RESET))
break;
udelay(1000);
} while (timeout--);
if (timeout < 0)
return -1;
#ifdef CONFIG_PHY_RESET_DELAY
udelay(CONFIG_PHY_RESET_DELAY);
#endif
return 0;
}
static int configure_phy(struct eth_device *dev)
{
struct dw_eth_dev *priv = dev->priv;
int phy_addr;
u16 bmcr;
#if defined(CONFIG_DW_AUTONEG)
u16 bmsr;
u32 timeout;
u16 anlpar, btsr;
#else
u16 ctrl;
#endif
#if defined(CONFIG_DW_SEARCH_PHY)
phy_addr = find_phy(dev);
if (phy_addr > 0)
priv->address = phy_addr;
else
return -1;
#else
phy_addr = priv->address;
#endif
if (dw_reset_phy(dev) < 0)
return -1;
#if defined(CONFIG_DW_AUTONEG)
bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100 | \
BMCR_FULLDPLX | BMCR_SPEED1000;
#else
bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
#if defined(CONFIG_DW_SPEED10M)
bmcr &= ~BMCR_SPEED100;
#endif
#if defined(CONFIG_DW_DUPLEXHALF)
bmcr &= ~BMCR_FULLDPLX;
#endif
#endif
if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
return -1;
/* Read the phy status register and populate priv structure */
#if defined(CONFIG_DW_AUTONEG)
timeout = CONFIG_AUTONEG_TIMEOUT;
do {
eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
if (bmsr & BMSR_ANEGCOMPLETE)
break;
udelay(1000);
} while (timeout--);
eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar);
eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr);
if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
priv->speed = SPEED_1000M;
if (btsr & PHY_1000BTSR_1000FD)
priv->duplex = FULL_DUPLEX;
else
priv->duplex = HALF_DUPLEX;
} else {
if (anlpar & LPA_100)
priv->speed = SPEED_100M;
else
priv->speed = SPEED_10M;
if (anlpar & (LPA_10FULL | LPA_100FULL))
priv->duplex = FULL_DUPLEX;
else
priv->duplex = HALF_DUPLEX;
}
#else
if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0)
return -1;
if (ctrl & BMCR_FULLDPLX)
priv->duplex = FULL_DUPLEX;
else
priv->duplex = HALF_DUPLEX;
if (ctrl & BMCR_SPEED1000)
priv->speed = SPEED_1000M;
else if (ctrl & BMCR_SPEED100)
priv->speed = SPEED_100M;
else
priv->speed = SPEED_10M;
#endif
return 0;
}
#if defined(CONFIG_MII)
static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
{
struct eth_device *dev;
dev = eth_get_dev_by_name(devname);
if (dev)
eth_mdio_read(dev, addr, reg, val);
return 0;
}
static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
{
struct eth_device *dev;
dev = eth_get_dev_by_name(devname);
if (dev)
eth_mdio_write(dev, addr, reg, val);
return 0;
}
#endif
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr)
{
struct eth_device *dev;
struct dw_eth_dev *priv;
dev = (struct eth_device *) malloc(sizeof(struct eth_device));
if (!dev)
return -ENOMEM;
/*
* Since the priv structure contains the descriptors which need a strict
* buswidth alignment, memalign is used to allocate memory
*/
priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
if (!priv) {
free(dev);
return -ENOMEM;
}
memset(dev, 0, sizeof(struct eth_device));
memset(priv, 0, sizeof(struct dw_eth_dev));
sprintf(dev->name, "mii%d", id);
dev->iobase = (int)base_addr;
dev->priv = priv;
eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
priv->dev = dev;
priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
DW_DMA_BASE_OFFSET);
priv->address = phy_addr;
if (mac_reset(dev) < 0)
return -1;
if (configure_phy(dev) < 0) {
printf("Phy could not be configured\n");
return -1;
}
dev->init = dw_eth_init;
dev->send = dw_eth_send;
dev->recv = dw_eth_recv;
dev->halt = dw_eth_halt;
dev->write_hwaddr = dw_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_MII)
miiphy_register(dev->name, dw_mii_read, dw_mii_write);
#endif
return 1;
}
|
1001-study-uboot
|
drivers/net/designware.c
|
C
|
gpl3
| 12,780
|
/*
natsemi.c: A U-Boot driver for the NatSemi DP8381x series.
Author: Mark A. Rakes (mark_rakes@vivato.net)
Adapted from an Etherboot driver written by:
Copyright (C) 2001 Entity Cyber, Inc.
This development of this Etherboot driver was funded by
Sicom Systems: http://www.sicompos.com/
Author: Marty Connor (mdc@thinguin.org)
Adapted from a Linux driver which was written by Donald Becker
This software may be used and distributed according to the terms
of the GNU Public License (GPL), incorporated herein by reference.
Original Copyright Notice:
Written/copyright 1999-2001 by Donald Becker.
This software may be used and distributed according to the terms of
the GNU General Public License (GPL), incorporated herein by reference.
Drivers based on or derived from this code fall under the GPL and must
retain the authorship, copyright and license notice. This file is not
a complete program and may only be used when the entire operating
system is licensed under the GPL. License for under other terms may be
available. Contact the original author for details.
The original author may be reached as becker@scyld.com, or at
Scyld Computing Corporation
410 Severn Ave., Suite 210
Annapolis MD 21403
Support information and updates available at
http://www.scyld.com/network/netsemi.html
References:
http://www.scyld.com/expert/100mbps.html
http://www.scyld.com/expert/NWay.html
Datasheet is available from:
http://www.national.com/pf/DP/DP83815.html
*/
/* Revision History
* October 2002 mar 1.0
* Initial U-Boot Release. Tested with Netgear FA311 board
* and dp83815 chipset on custom board
*/
/* Includes */
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
/* defines */
#define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
#define DSIZE 0x00000FFF
#define ETH_ALEN 6
#define CRC_SIZE 4
#define TOUT_LOOP 500000
#define TX_BUF_SIZE 1536
#define RX_BUF_SIZE 1536
#define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
/* Offsets to the device registers.
Unlike software-only systems, device drivers interact with complex hardware.
It's not useful to define symbolic names for every register bit in the
device. */
enum register_offsets {
ChipCmd = 0x00,
ChipConfig = 0x04,
EECtrl = 0x08,
IntrMask = 0x14,
IntrEnable = 0x18,
TxRingPtr = 0x20,
TxConfig = 0x24,
RxRingPtr = 0x30,
RxConfig = 0x34,
ClkRun = 0x3C,
RxFilterAddr = 0x48,
RxFilterData = 0x4C,
SiliconRev = 0x58,
PCIPM = 0x44,
BasicControl = 0x80,
BasicStatus = 0x84,
/* These are from the spec, around page 78... on a separate table. */
PGSEL = 0xCC,
PMDCSR = 0xE4,
TSTDAT = 0xFC,
DSPCFG = 0xF4,
SDCFG = 0x8C
};
/* Bit in ChipCmd. */
enum ChipCmdBits {
ChipReset = 0x100,
RxReset = 0x20,
TxReset = 0x10,
RxOff = 0x08,
RxOn = 0x04,
TxOff = 0x02,
TxOn = 0x01
};
enum ChipConfigBits {
LinkSts = 0x80000000,
HundSpeed = 0x40000000,
FullDuplex = 0x20000000,
TenPolarity = 0x10000000,
AnegDone = 0x08000000,
AnegEnBothBoth = 0x0000E000,
AnegDis100Full = 0x0000C000,
AnegEn100Both = 0x0000A000,
AnegDis100Half = 0x00008000,
AnegEnBothHalf = 0x00006000,
AnegDis10Full = 0x00004000,
AnegEn10Both = 0x00002000,
DuplexMask = 0x00008000,
SpeedMask = 0x00004000,
AnegMask = 0x00002000,
AnegDis10Half = 0x00000000,
ExtPhy = 0x00001000,
PhyRst = 0x00000400,
PhyDis = 0x00000200,
BootRomDisable = 0x00000004,
BEMode = 0x00000001,
};
enum TxConfig_bits {
TxDrthMask = 0x3f,
TxFlthMask = 0x3f00,
TxMxdmaMask = 0x700000,
TxMxdma_512 = 0x0,
TxMxdma_4 = 0x100000,
TxMxdma_8 = 0x200000,
TxMxdma_16 = 0x300000,
TxMxdma_32 = 0x400000,
TxMxdma_64 = 0x500000,
TxMxdma_128 = 0x600000,
TxMxdma_256 = 0x700000,
TxCollRetry = 0x800000,
TxAutoPad = 0x10000000,
TxMacLoop = 0x20000000,
TxHeartIgn = 0x40000000,
TxCarrierIgn = 0x80000000
};
enum RxConfig_bits {
RxDrthMask = 0x3e,
RxMxdmaMask = 0x700000,
RxMxdma_512 = 0x0,
RxMxdma_4 = 0x100000,
RxMxdma_8 = 0x200000,
RxMxdma_16 = 0x300000,
RxMxdma_32 = 0x400000,
RxMxdma_64 = 0x500000,
RxMxdma_128 = 0x600000,
RxMxdma_256 = 0x700000,
RxAcceptLong = 0x8000000,
RxAcceptTx = 0x10000000,
RxAcceptRunt = 0x40000000,
RxAcceptErr = 0x80000000
};
/* Bits in the RxMode register. */
enum rx_mode_bits {
AcceptErr = 0x20,
AcceptRunt = 0x10,
AcceptBroadcast = 0xC0000000,
AcceptMulticast = 0x00200000,
AcceptAllMulticast = 0x20000000,
AcceptAllPhys = 0x10000000,
AcceptMyPhys = 0x08000000
};
typedef struct _BufferDesc {
u32 link;
vu_long cmdsts;
u32 bufptr;
u32 software_use;
} BufferDesc;
/* Bits in network_desc.status */
enum desc_status_bits {
DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
DescSizeMask = 0xfff,
DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
DescRxDest = 0x01800000, DescRxLong = 0x00400000,
DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
};
/* Globals */
#ifdef NATSEMI_DEBUG
static int natsemi_debug = 0; /* 1 verbose debugging, 0 normal */
#endif
static u32 SavedClkRun;
static unsigned int cur_rx;
static unsigned int advertising;
static unsigned int rx_config;
static unsigned int tx_config;
/* Note: transmit and receive buffers and descriptors must be
longword aligned */
static BufferDesc txd __attribute__ ((aligned(4)));
static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(4)));
static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(4)));
static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
__attribute__ ((aligned(4)));
/* Function Prototypes */
#if 0
static void write_eeprom(struct eth_device *dev, long addr, int location,
short value);
#endif
static int read_eeprom(struct eth_device *dev, long addr, int location);
static int mdio_read(struct eth_device *dev, int phy_id, int location);
static int natsemi_init(struct eth_device *dev, bd_t * bis);
static void natsemi_reset(struct eth_device *dev);
static void natsemi_init_rxfilter(struct eth_device *dev);
static void natsemi_init_txd(struct eth_device *dev);
static void natsemi_init_rxd(struct eth_device *dev);
static void natsemi_set_rx_mode(struct eth_device *dev);
static void natsemi_check_duplex(struct eth_device *dev);
static int natsemi_send(struct eth_device *dev, volatile void *packet,
int length);
static int natsemi_poll(struct eth_device *dev);
static void natsemi_disable(struct eth_device *dev);
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815},
{}
};
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
static inline int
INW(struct eth_device *dev, u_long addr)
{
return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
}
static int
INL(struct eth_device *dev, u_long addr)
{
return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
}
static inline void
OUTW(struct eth_device *dev, int command, u_long addr)
{
*(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
}
static inline void
OUTL(struct eth_device *dev, int command, u_long addr)
{
*(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
}
/*
* Function: natsemi_initialize
*
* Description: Retrieves the MAC address of the card, and sets up some
* globals required by other routines, and initializes the NIC, making it
* ready to send and receive packets.
*
* Side effects:
* leaves the natsemi initialized, and ready to receive packets.
*
* Returns: struct eth_device *: pointer to NIC data structure
*/
int
natsemi_initialize(bd_t * bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase, status, chip_config;
int i, idx = 0;
int prev_eedata;
u32 tmp;
while (1) {
/* Find PCI device(s) */
if ((devno = pci_find_devices(supported, idx++)) < 0) {
break;
}
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */
pci_write_config_dword(devno, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled. */
pci_read_config_dword(devno, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_MEMORY)) {
printf("Error: Can not enable MEM access.\n");
continue;
} else if (!(status & PCI_COMMAND_MASTER)) {
printf("Error: Can not enable Bus Mastering.\n");
continue;
}
dev = (struct eth_device *) malloc(sizeof *dev);
if (!dev) {
printf("natsemi: Can not allocate memory\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "dp83815#%d", card_number);
dev->iobase = bus_to_phys(iobase);
#ifdef NATSEMI_DEBUG
printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase);
#endif
dev->priv = (void *) devno;
dev->init = natsemi_init;
dev->halt = natsemi_disable;
dev->send = natsemi_send;
dev->recv = natsemi_poll;
eth_register(dev);
card_number++;
/* Set the latency timer for value. */
pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
udelay(10 * 1000);
/* natsemi has a non-standard PM control register
* in PCI config space. Some boards apparently need
* to be brought to D0 in this manner. */
pci_read_config_dword(devno, PCIPM, &tmp);
if (tmp & (0x03 | 0x100)) {
/* D0 state, disable PME assertion */
u32 newtmp = tmp & ~(0x03 | 0x100);
pci_write_config_dword(devno, PCIPM, newtmp);
}
printf("natsemi: EEPROM contents:\n");
for (i = 0; i <= EEPROM_SIZE; i++) {
short eedata = read_eeprom(dev, EECtrl, i);
printf(" %04hx", eedata);
}
printf("\n");
/* get MAC address */
prev_eedata = read_eeprom(dev, EECtrl, 6);
for (i = 0; i < 3; i++) {
int eedata = read_eeprom(dev, EECtrl, i + 7);
dev->enetaddr[i*2] = (eedata << 1) + (prev_eedata >> 15);
dev->enetaddr[i*2+1] = eedata >> 7;
prev_eedata = eedata;
}
/* Reset the chip to erase any previous misconfiguration. */
OUTL(dev, ChipReset, ChipCmd);
advertising = mdio_read(dev, 1, 4);
chip_config = INL(dev, ChipConfig);
#ifdef NATSEMI_DEBUG
printf("%s: Transceiver status %#08X advertising %#08X\n",
dev->name, (int) INL(dev, BasicStatus), advertising);
printf("%s: Transceiver default autoneg. %s 10%s %s duplex.\n",
dev->name, chip_config & AnegMask ? "enabled, advertise" :
"disabled, force", chip_config & SpeedMask ? "0" : "",
chip_config & DuplexMask ? "full" : "half");
#endif
chip_config |= AnegEnBothBoth;
#ifdef NATSEMI_DEBUG
printf("%s: changed to autoneg. %s 10%s %s duplex.\n",
dev->name, chip_config & AnegMask ? "enabled, advertise" :
"disabled, force", chip_config & SpeedMask ? "0" : "",
chip_config & DuplexMask ? "full" : "half");
#endif
/*write new autoneg bits, reset phy*/
OUTL(dev, (chip_config | PhyRst), ChipConfig);
/*un-reset phy*/
OUTL(dev, chip_config, ChipConfig);
/* Disable PME:
* The PME bit is initialized from the EEPROM contents.
* PCI cards probably have PME disabled, but motherboard
* implementations may have PME set to enable WakeOnLan.
* With PME set the chip will scan incoming packets but
* nothing will be written to memory. */
SavedClkRun = INL(dev, ClkRun);
OUTL(dev, SavedClkRun & ~0x100, ClkRun);
}
return card_number;
}
/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces.
The EEPROM code is for common 93c06/46 EEPROMs w/ 6bit addresses. */
/* Delay between EEPROM clock transitions.
No extra delay is needed with 33MHz PCI, but future 66MHz
access may need a delay. */
#define eeprom_delay(ee_addr) INL(dev, ee_addr)
enum EEPROM_Ctrl_Bits {
EE_ShiftClk = 0x04,
EE_DataIn = 0x01,
EE_ChipSelect = 0x08,
EE_DataOut = 0x02
};
#define EE_Write0 (EE_ChipSelect)
#define EE_Write1 (EE_ChipSelect | EE_DataIn)
/* The EEPROM commands include the alway-set leading bit. */
enum EEPROM_Cmds {
EE_WrEnCmd = (4 << 6), EE_WriteCmd = (5 << 6),
EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6),
};
#if 0
static void
write_eeprom(struct eth_device *dev, long addr, int location, short value)
{
int i;
int ee_addr = (typeof(ee_addr))addr;
short wren_cmd = EE_WrEnCmd | 0x30; /*wren is 100 + 11XXXX*/
short write_cmd = location | EE_WriteCmd;
#ifdef NATSEMI_DEBUG
printf("write_eeprom: %08x, %04hx, %04hx\n",
dev->iobase + ee_addr, write_cmd, value);
#endif
/* Shift the write enable command bits out. */
for (i = 9; i >= 0; i--) {
short cmdval = (wren_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
OUTL(dev, cmdval, ee_addr);
eeprom_delay(ee_addr);
OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
eeprom_delay(ee_addr);
}
OUTL(dev, 0, ee_addr); /*bring chip select low*/
OUTL(dev, EE_ShiftClk, ee_addr);
eeprom_delay(ee_addr);
/* Shift the write command bits out. */
for (i = 9; i >= 0; i--) {
short cmdval = (write_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
OUTL(dev, cmdval, ee_addr);
eeprom_delay(ee_addr);
OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
eeprom_delay(ee_addr);
}
for (i = 0; i < 16; i++) {
short cmdval = (value & (1 << i)) ? EE_Write1 : EE_Write0;
OUTL(dev, cmdval, ee_addr);
eeprom_delay(ee_addr);
OUTL(dev, cmdval | EE_ShiftClk, ee_addr);
eeprom_delay(ee_addr);
}
OUTL(dev, 0, ee_addr); /*bring chip select low*/
OUTL(dev, EE_ShiftClk, ee_addr);
for (i = 0; i < 200000; i++) {
OUTL(dev, EE_Write0, ee_addr); /*poll for done*/
if (INL(dev, ee_addr) & EE_DataOut) {
break; /*finished*/
}
}
eeprom_delay(ee_addr);
/* Terminate the EEPROM access. */
OUTL(dev, EE_Write0, ee_addr);
OUTL(dev, 0, ee_addr);
return;
}
#endif
static int
read_eeprom(struct eth_device *dev, long addr, int location)
{
int i;
int retval = 0;
int ee_addr = (typeof(ee_addr))addr;
int read_cmd = location | EE_ReadCmd;
OUTL(dev, EE_Write0, ee_addr);
/* Shift the read command bits out. */
for (i = 10; i >= 0; i--) {
short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
OUTL(dev, dataval, ee_addr);
eeprom_delay(ee_addr);
OUTL(dev, dataval | EE_ShiftClk, ee_addr);
eeprom_delay(ee_addr);
}
OUTL(dev, EE_ChipSelect, ee_addr);
eeprom_delay(ee_addr);
for (i = 0; i < 16; i++) {
OUTL(dev, EE_ChipSelect | EE_ShiftClk, ee_addr);
eeprom_delay(ee_addr);
retval |= (INL(dev, ee_addr) & EE_DataOut) ? 1 << i : 0;
OUTL(dev, EE_ChipSelect, ee_addr);
eeprom_delay(ee_addr);
}
/* Terminate the EEPROM access. */
OUTL(dev, EE_Write0, ee_addr);
OUTL(dev, 0, ee_addr);
#ifdef NATSEMI_DEBUG
if (natsemi_debug)
printf("read_eeprom: %08x, %08x, retval %08x\n",
dev->iobase + ee_addr, read_cmd, retval);
#endif
return retval;
}
/* MII transceiver control section.
The 83815 series has an internal transceiver, and we present the
management registers as if they were MII connected. */
static int
mdio_read(struct eth_device *dev, int phy_id, int location)
{
if (phy_id == 1 && location < 32)
return INL(dev, BasicControl+(location<<2))&0xffff;
else
return 0xffff;
}
/* Function: natsemi_init
*
* Description: resets the ethernet controller chip and configures
* registers and data structures required for sending and receiving packets.
*
* Arguments: struct eth_device *dev: NIC data structure
*
* returns: int.
*/
static int
natsemi_init(struct eth_device *dev, bd_t * bis)
{
natsemi_reset(dev);
/* Disable PME:
* The PME bit is initialized from the EEPROM contents.
* PCI cards probably have PME disabled, but motherboard
* implementations may have PME set to enable WakeOnLan.
* With PME set the chip will scan incoming packets but
* nothing will be written to memory. */
OUTL(dev, SavedClkRun & ~0x100, ClkRun);
natsemi_init_rxfilter(dev);
natsemi_init_txd(dev);
natsemi_init_rxd(dev);
/* Configure the PCI bus bursts and FIFO thresholds. */
tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | (0x1002);
rx_config = RxMxdma_256 | 0x20;
#ifdef NATSEMI_DEBUG
printf("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
printf("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
#endif
OUTL(dev, tx_config, TxConfig);
OUTL(dev, rx_config, RxConfig);
natsemi_check_duplex(dev);
natsemi_set_rx_mode(dev);
OUTL(dev, (RxOn | TxOn), ChipCmd);
return 1;
}
/*
* Function: natsemi_reset
*
* Description: soft resets the controller chip
*
* Arguments: struct eth_device *dev: NIC data structure
*
* Returns: void.
*/
static void
natsemi_reset(struct eth_device *dev)
{
OUTL(dev, ChipReset, ChipCmd);
/* On page 78 of the spec, they recommend some settings for "optimum
performance" to be done in sequence. These settings optimize some
of the 100Mbit autodetection circuitry. Also, we only want to do
this for rev C of the chip. */
if (INL(dev, SiliconRev) == 0x302) {
OUTW(dev, 0x0001, PGSEL);
OUTW(dev, 0x189C, PMDCSR);
OUTW(dev, 0x0000, TSTDAT);
OUTW(dev, 0x5040, DSPCFG);
OUTW(dev, 0x008C, SDCFG);
}
/* Disable interrupts using the mask. */
OUTL(dev, 0, IntrMask);
OUTL(dev, 0, IntrEnable);
}
/* Function: natsemi_init_rxfilter
*
* Description: sets receive filter address to our MAC address
*
* Arguments: struct eth_device *dev: NIC data structure
*
* returns: void.
*/
static void
natsemi_init_rxfilter(struct eth_device *dev)
{
int i;
for (i = 0; i < ETH_ALEN; i += 2) {
OUTL(dev, i, RxFilterAddr);
OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
RxFilterData);
}
}
/*
* Function: natsemi_init_txd
*
* Description: initializes the Tx descriptor
*
* Arguments: struct eth_device *dev: NIC data structure
*
* returns: void.
*/
static void
natsemi_init_txd(struct eth_device *dev)
{
txd.link = (u32) 0;
txd.cmdsts = (u32) 0;
txd.bufptr = (u32) & txb[0];
/* load Transmit Descriptor Register */
OUTL(dev, (u32) & txd, TxRingPtr);
#ifdef NATSEMI_DEBUG
printf("natsemi_init_txd: TX descriptor reg loaded with: %#08X\n",
INL(dev, TxRingPtr));
#endif
}
/* Function: natsemi_init_rxd
*
* Description: initializes the Rx descriptor ring
*
* Arguments: struct eth_device *dev: NIC data structure
*
* Returns: void.
*/
static void
natsemi_init_rxd(struct eth_device *dev)
{
int i;
cur_rx = 0;
/* init RX descriptor */
for (i = 0; i < NUM_RX_DESC; i++) {
rxd[i].link =
cpu_to_le32((i + 1 <
NUM_RX_DESC) ? (u32) & rxd[i +
1] : (u32) &
rxd[0]);
rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
#ifdef NATSEMI_DEBUG
printf
("natsemi_init_rxd: rxd[%d]=%p link=%X cmdsts=%lX bufptr=%X\n",
i, &rxd[i], le32_to_cpu(rxd[i].link),
rxd[i].cmdsts, rxd[i].bufptr);
#endif
}
/* load Receive Descriptor Register */
OUTL(dev, (u32) & rxd[0], RxRingPtr);
#ifdef NATSEMI_DEBUG
printf("natsemi_init_rxd: RX descriptor register loaded with: %X\n",
INL(dev, RxRingPtr));
#endif
}
/* Function: natsemi_set_rx_mode
*
* Description:
* sets the receive mode to accept all broadcast packets and packets
* with our MAC address, and reject all multicast packets.
*
* Arguments: struct eth_device *dev: NIC data structure
*
* Returns: void.
*/
static void
natsemi_set_rx_mode(struct eth_device *dev)
{
u32 rx_mode = AcceptBroadcast | AcceptMyPhys;
OUTL(dev, rx_mode, RxFilterAddr);
}
static void
natsemi_check_duplex(struct eth_device *dev)
{
int duplex = INL(dev, ChipConfig) & FullDuplex ? 1 : 0;
#ifdef NATSEMI_DEBUG
printf("%s: Setting %s-duplex based on negotiated link"
" capability.\n", dev->name, duplex ? "full" : "half");
#endif
if (duplex) {
rx_config |= RxAcceptTx;
tx_config |= (TxCarrierIgn | TxHeartIgn);
} else {
rx_config &= ~RxAcceptTx;
tx_config &= ~(TxCarrierIgn | TxHeartIgn);
}
OUTL(dev, tx_config, TxConfig);
OUTL(dev, rx_config, RxConfig);
}
/* Function: natsemi_send
*
* Description: transmits a packet and waits for completion or timeout.
*
* Returns: void. */
static int
natsemi_send(struct eth_device *dev, volatile void *packet, int length)
{
u32 i, status = 0;
u32 tx_status = 0;
u32 *tx_ptr = &tx_status;
vu_long *res = (vu_long *)tx_ptr;
/* Stop the transmitter */
OUTL(dev, TxOff, ChipCmd);
#ifdef NATSEMI_DEBUG
if (natsemi_debug)
printf("natsemi_send: sending %d bytes\n", (int) length);
#endif
/* set the transmit buffer descriptor and enable Transmit State Machine */
txd.link = cpu_to_le32(0);
txd.bufptr = cpu_to_le32(phys_to_bus((u32) packet));
txd.cmdsts = cpu_to_le32(DescOwn | length);
/* load Transmit Descriptor Register */
OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
#ifdef NATSEMI_DEBUG
if (natsemi_debug)
printf("natsemi_send: TX descriptor register loaded with: %#08X\n",
INL(dev, TxRingPtr));
#endif
/* restart the transmitter */
OUTL(dev, TxOn, ChipCmd);
for (i = 0;
(*res = le32_to_cpu(txd.cmdsts)) & DescOwn;
i++) {
if (i >= TOUT_LOOP) {
printf
("%s: tx error buffer not ready: txd.cmdsts == %#X\n",
dev->name, tx_status);
goto Done;
}
}
if (!(tx_status & DescPktOK)) {
printf("natsemi_send: Transmit error, Tx status %X.\n",
tx_status);
goto Done;
}
status = 1;
Done:
return status;
}
/* Function: natsemi_poll
*
* Description: checks for a received packet and returns it if found.
*
* Arguments: struct eth_device *dev: NIC data structure
*
* Returns: 1 if packet was received.
* 0 if no packet was received.
*
* Side effects:
* Returns (copies) the packet to the array dev->packet.
* Returns the length of the packet.
*/
static int
natsemi_poll(struct eth_device *dev)
{
int retstat = 0;
int length = 0;
u32 rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
if (!(rx_status & (u32) DescOwn))
return retstat;
#ifdef NATSEMI_DEBUG
if (natsemi_debug)
printf("natsemi_poll: got a packet: cur_rx:%d, status:%X\n",
cur_rx, rx_status);
#endif
length = (rx_status & DSIZE) - CRC_SIZE;
if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
printf
("natsemi_poll: Corrupted packet received, buffer status = %X\n",
rx_status);
retstat = 0;
} else { /* give packet to higher level routine */
NetReceive((rxb + cur_rx * RX_BUF_SIZE), length);
retstat = 1;
}
/* return the descriptor and buffer to receive ring */
rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
if (++cur_rx == NUM_RX_DESC)
cur_rx = 0;
/* re-enable the potentially idle receive state machine */
OUTL(dev, RxOn, ChipCmd);
return retstat;
}
/* Function: natsemi_disable
*
* Description: Turns off interrupts and stops Tx and Rx engines
*
* Arguments: struct eth_device *dev: NIC data structure
*
* Returns: void.
*/
static void
natsemi_disable(struct eth_device *dev)
{
/* Disable interrupts using the mask. */
OUTL(dev, 0, IntrMask);
OUTL(dev, 0, IntrEnable);
/* Stop the chip's Tx and Rx processes. */
OUTL(dev, RxOff | TxOff, ChipCmd);
/* Restore PME enable bit */
OUTL(dev, SavedClkRun, ClkRun);
}
|
1001-study-uboot
|
drivers/net/natsemi.c
|
C
|
gpl3
| 23,498
|
/*
* (X) extracted from enc28j60.c
* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _enc28j60_h
#define _enc28j60_h
/*
* SPI Commands
*
* Bits 7-5: Command
* Bits 4-0: Register
*/
#define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */
#define CMD_RBM 0x3a /* Read Buffer Memory */
#define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */
#define CMD_WBM 0x7a /* Write Buffer Memory */
#define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */
#define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */
#define CMD_SRC 0xff /* System Reset Command */
/* NEW: encode (bank number+1) in upper byte */
/* Common Control Registers accessible in all Banks */
#define CTL_REG_EIE 0x01B
#define CTL_REG_EIR 0x01C
#define CTL_REG_ESTAT 0x01D
#define CTL_REG_ECON2 0x01E
#define CTL_REG_ECON1 0x01F
/* Control Registers accessible in Bank 0 */
#define CTL_REG_ERDPTL 0x100
#define CTL_REG_ERDPTH 0x101
#define CTL_REG_EWRPTL 0x102
#define CTL_REG_EWRPTH 0x103
#define CTL_REG_ETXSTL 0x104
#define CTL_REG_ETXSTH 0x105
#define CTL_REG_ETXNDL 0x106
#define CTL_REG_ETXNDH 0x107
#define CTL_REG_ERXSTL 0x108
#define CTL_REG_ERXSTH 0x109
#define CTL_REG_ERXNDL 0x10A
#define CTL_REG_ERXNDH 0x10B
#define CTL_REG_ERXRDPTL 0x10C
#define CTL_REG_ERXRDPTH 0x10D
#define CTL_REG_ERXWRPTL 0x10E
#define CTL_REG_ERXWRPTH 0x10F
#define CTL_REG_EDMASTL 0x110
#define CTL_REG_EDMASTH 0x111
#define CTL_REG_EDMANDL 0x112
#define CTL_REG_EDMANDH 0x113
#define CTL_REG_EDMADSTL 0x114
#define CTL_REG_EDMADSTH 0x115
#define CTL_REG_EDMACSL 0x116
#define CTL_REG_EDMACSH 0x117
/* Control Registers accessible in Bank 1 */
#define CTL_REG_EHT0 0x200
#define CTL_REG_EHT1 0x201
#define CTL_REG_EHT2 0x202
#define CTL_REG_EHT3 0x203
#define CTL_REG_EHT4 0x204
#define CTL_REG_EHT5 0x205
#define CTL_REG_EHT6 0x206
#define CTL_REG_EHT7 0x207
#define CTL_REG_EPMM0 0x208
#define CTL_REG_EPMM1 0x209
#define CTL_REG_EPMM2 0x20A
#define CTL_REG_EPMM3 0x20B
#define CTL_REG_EPMM4 0x20C
#define CTL_REG_EPMM5 0x20D
#define CTL_REG_EPMM6 0x20E
#define CTL_REG_EPMM7 0x20F
#define CTL_REG_EPMCSL 0x210
#define CTL_REG_EPMCSH 0x211
#define CTL_REG_EPMOL 0x214
#define CTL_REG_EPMOH 0x215
#define CTL_REG_EWOLIE 0x216
#define CTL_REG_EWOLIR 0x217
#define CTL_REG_ERXFCON 0x218
#define CTL_REG_EPKTCNT 0x219
/* Control Registers accessible in Bank 2 */
#define CTL_REG_MACON1 0x300
#define CTL_REG_MACON2 0x301
#define CTL_REG_MACON3 0x302
#define CTL_REG_MACON4 0x303
#define CTL_REG_MABBIPG 0x304
#define CTL_REG_MAIPGL 0x306
#define CTL_REG_MAIPGH 0x307
#define CTL_REG_MACLCON1 0x308
#define CTL_REG_MACLCON2 0x309
#define CTL_REG_MAMXFLL 0x30A
#define CTL_REG_MAMXFLH 0x30B
#define CTL_REG_MAPHSUP 0x30D
#define CTL_REG_MICON 0x311
#define CTL_REG_MICMD 0x312
#define CTL_REG_MIREGADR 0x314
#define CTL_REG_MIWRL 0x316
#define CTL_REG_MIWRH 0x317
#define CTL_REG_MIRDL 0x318
#define CTL_REG_MIRDH 0x319
/* Control Registers accessible in Bank 3 */
#define CTL_REG_MAADR1 0x400
#define CTL_REG_MAADR0 0x401
#define CTL_REG_MAADR3 0x402
#define CTL_REG_MAADR2 0x403
#define CTL_REG_MAADR5 0x404
#define CTL_REG_MAADR4 0x405
#define CTL_REG_EBSTSD 0x406
#define CTL_REG_EBSTCON 0x407
#define CTL_REG_EBSTCSL 0x408
#define CTL_REG_EBSTCSH 0x409
#define CTL_REG_MISTAT 0x40A
#define CTL_REG_EREVID 0x412
#define CTL_REG_ECOCON 0x415
#define CTL_REG_EFLOCON 0x417
#define CTL_REG_EPAUSL 0x418
#define CTL_REG_EPAUSH 0x419
/* PHY Register */
#define PHY_REG_PHCON1 0x00
#define PHY_REG_PHSTAT1 0x01
#define PHY_REG_PHID1 0x02
#define PHY_REG_PHID2 0x03
#define PHY_REG_PHCON2 0x10
#define PHY_REG_PHSTAT2 0x11
#define PHY_REG_PHLCON 0x14
/* Receive Filter Register (ERXFCON) bits */
#define ENC_RFR_UCEN 0x80
#define ENC_RFR_ANDOR 0x40
#define ENC_RFR_CRCEN 0x20
#define ENC_RFR_PMEN 0x10
#define ENC_RFR_MPEN 0x08
#define ENC_RFR_HTEN 0x04
#define ENC_RFR_MCEN 0x02
#define ENC_RFR_BCEN 0x01
/* ECON1 Register Bits */
#define ENC_ECON1_TXRST 0x80
#define ENC_ECON1_RXRST 0x40
#define ENC_ECON1_DMAST 0x20
#define ENC_ECON1_CSUMEN 0x10
#define ENC_ECON1_TXRTS 0x08
#define ENC_ECON1_RXEN 0x04
#define ENC_ECON1_BSEL1 0x02
#define ENC_ECON1_BSEL0 0x01
/* ECON2 Register Bits */
#define ENC_ECON2_AUTOINC 0x80
#define ENC_ECON2_PKTDEC 0x40
#define ENC_ECON2_PWRSV 0x20
#define ENC_ECON2_VRPS 0x08
/* EIR Register Bits */
#define ENC_EIR_PKTIF 0x40
#define ENC_EIR_DMAIF 0x20
#define ENC_EIR_LINKIF 0x10
#define ENC_EIR_TXIF 0x08
#define ENC_EIR_WOLIF 0x04
#define ENC_EIR_TXERIF 0x02
#define ENC_EIR_RXERIF 0x01
/* ESTAT Register Bits */
#define ENC_ESTAT_INT 0x80
#define ENC_ESTAT_LATECOL 0x10
#define ENC_ESTAT_RXBUSY 0x04
#define ENC_ESTAT_TXABRT 0x02
#define ENC_ESTAT_CLKRDY 0x01
/* EIE Register Bits */
#define ENC_EIE_INTIE 0x80
#define ENC_EIE_PKTIE 0x40
#define ENC_EIE_DMAIE 0x20
#define ENC_EIE_LINKIE 0x10
#define ENC_EIE_TXIE 0x08
#define ENC_EIE_WOLIE 0x04
#define ENC_EIE_TXERIE 0x02
#define ENC_EIE_RXERIE 0x01
/* MACON1 Register Bits */
#define ENC_MACON1_LOOPBK 0x10
#define ENC_MACON1_TXPAUS 0x08
#define ENC_MACON1_RXPAUS 0x04
#define ENC_MACON1_PASSALL 0x02
#define ENC_MACON1_MARXEN 0x01
/* MACON2 Register Bits */
#define ENC_MACON2_MARST 0x80
#define ENC_MACON2_RNDRST 0x40
#define ENC_MACON2_MARXRST 0x08
#define ENC_MACON2_RFUNRST 0x04
#define ENC_MACON2_MATXRST 0x02
#define ENC_MACON2_TFUNRST 0x01
/* MACON3 Register Bits */
#define ENC_MACON3_PADCFG2 0x80
#define ENC_MACON3_PADCFG1 0x40
#define ENC_MACON3_PADCFG0 0x20
#define ENC_MACON3_TXCRCEN 0x10
#define ENC_MACON3_PHDRLEN 0x08
#define ENC_MACON3_HFRMEN 0x04
#define ENC_MACON3_FRMLNEN 0x02
#define ENC_MACON3_FULDPX 0x01
/* MACON4 Register Bits */
#define ENC_MACON4_DEFER 0x40
/* MICMD Register Bits */
#define ENC_MICMD_MIISCAN 0x02
#define ENC_MICMD_MIIRD 0x01
/* MISTAT Register Bits */
#define ENC_MISTAT_NVALID 0x04
#define ENC_MISTAT_SCAN 0x02
#define ENC_MISTAT_BUSY 0x01
/* PHID1 and PHID2 values */
#define ENC_PHID1_VALUE 0x0083
#define ENC_PHID2_VALUE 0x1400
#define ENC_PHID2_MASK 0xFC00
/* PHCON1 values */
#define ENC_PHCON1_PDPXMD 0x0100
/* PHSTAT1 values */
#define ENC_PHSTAT1_LLSTAT 0x0004
/* PHSTAT2 values */
#define ENC_PHSTAT2_LSTAT 0x0400
#define ENC_PHSTAT2_DPXSTAT 0x0200
#endif
|
1001-study-uboot
|
drivers/net/enc28j60.h
|
C
|
gpl3
| 7,076
|
/*
* sh_eth.h - Driver for Renesas SuperH ethernet controler.
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (c) 2008 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <netdev.h>
#include <asm/types.h>
#define SHETHER_NAME "sh_eth"
/* Malloc returns addresses in the P1 area (cacheable). However we need to
use area P2 (non-cacheable) */
#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) | 0xa0000000))
/* The ethernet controller needs to use physical addresses */
#if defined(CONFIG_SH_32BIT)
#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) | 0x40000000))
#else
#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
#endif
/* Number of supported ports */
#define MAX_PORT_NUM 2
/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
buffers must be a multiple of 32 bytes */
#define MAX_BUF_SIZE (48 * 32)
/* The number of tx descriptors must be large enough to point to 5 or more
frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
We use one descriptor per frame */
#define NUM_TX_DESC 8
/* The size of the tx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
#define TX_DESC_PADDING 4
#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
volatile u32 td0;
u32 td1;
u32 td2; /* Buffer start */
u32 padding;
};
/* There is no limitation in the number of rx descriptors */
#define NUM_RX_DESC 8
/* The size of the rx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
#define RX_DESC_PADDING 4
#define RX_DESC_SIZE (12 + RX_DESC_PADDING)
/* Rx descriptor. We always use 4 bytes of padding */
struct rx_desc_s {
volatile u32 rd0;
volatile u32 rd1;
u32 rd2; /* Buffer start */
u32 padding;
};
struct sh_eth_info {
struct tx_desc_s *tx_desc_malloc;
struct tx_desc_s *tx_desc_base;
struct tx_desc_s *tx_desc_cur;
struct rx_desc_s *rx_desc_malloc;
struct rx_desc_s *rx_desc_base;
struct rx_desc_s *rx_desc_cur;
u8 *rx_buf_malloc;
u8 *rx_buf_base;
u8 mac_addr[6];
u8 phy_addr;
struct eth_device *dev;
struct phy_device *phydev;
};
struct sh_eth_dev {
int port;
struct sh_eth_info port_info[MAX_PORT_NUM];
};
/* Register Address */
#ifdef CONFIG_CPU_SH7763
#define BASE_IO_ADDR 0xfee00000
#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
#define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014)
#define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
#define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c)
#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
#define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034)
#define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
#define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c)
#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400)
#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408)
#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410)
#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428)
#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430)
#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438)
#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448)
#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450)
#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458)
#define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460)
#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468)
#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500)
#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508)
#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518)
#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520)
#define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c)
#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554)
#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558)
#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564)
#define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
#elif defined(CONFIG_CPU_SH7757)
#define BASE_IO_ADDR 0xfef00000
#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020)
#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008)
#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028)
#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048)
#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050)
#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058)
#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070)
#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100)
#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108)
#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118)
#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120)
#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154)
#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158)
#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164)
#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
#endif
/*
* Register's bits
* Copy from Linux driver source code
*/
#ifdef CONFIG_CPU_SH7763
/* EDSR */
enum EDSR_BIT {
EDSR_ENT = 0x01, EDSR_ENR = 0x02,
};
#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
#endif
/* EDMR */
enum DMAC_M_BIT {
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
#ifdef CONFIG_CPU_SH7763
EDMR_SRST = 0x03,
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
#elif defined CONFIG_CPU_SH7757
EDMR_SRST = 0x01,
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
#else /* CONFIG_CPU_SH7763 */
EDMR_SRST = 0x01,
#endif
};
/* RFLR */
#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
/* EDTRR */
enum DMAC_T_BIT {
#ifdef CONFIG_CPU_SH7763
EDTRR_TRNS = 0x03,
#else
EDTRR_TRNS = 0x01,
#endif
};
/* GECMR */
enum GECMR_BIT {
GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
};
/* EDRRR*/
enum EDRRR_R_BIT {
EDRRR_R = 0x01,
};
/* TPAUSER */
enum TPAUSER_BIT {
TPAUSER_TPAUSE = 0x0000ffff,
TPAUSER_UNLIMITED = 0,
};
/* BCFR */
enum BCFR_BIT {
BCFR_RPAUSE = 0x0000ffff,
BCFR_UNLIMITED = 0,
};
/* PIR */
enum PIR_BIT {
PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
};
/* PSR */
enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
/* EESR */
enum EESR_BIT {
#ifndef CONFIG_CPU_SH7763
EESR_TWB = 0x40000000,
#else
EESR_TWB = 0xC0000000,
EESR_TC1 = 0x20000000,
EESR_TUC = 0x10000000,
EESR_ROC = 0x80000000,
#endif
EESR_TABT = 0x04000000,
EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
#ifndef CONFIG_CPU_SH7763
EESR_ADE = 0x00800000,
#endif
EESR_ECI = 0x00400000,
EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
#ifndef CONFIG_CPU_SH7763
EESR_CND = 0x00000800,
#endif
EESR_DLC = 0x00000400,
EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
};
#ifdef CONFIG_CPU_SH7763
# define TX_CHECK (EESR_TC1 | EESR_FTC)
# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
#else
# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
#endif
/* EESIPR */
enum DMAC_IM_BIT {
DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
DMAC_M_RABT = 0x02000000,
DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
DMAC_M_RINT1 = 0x00000001,
};
/* Receive descriptor bit */
enum RD_STS_BIT {
RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
RD_RFS1 = 0x00000001,
};
#define RDF1ST RD_RFP1
#define RDFEND RD_RFP0
#define RD_RFP (RD_RFP1|RD_RFP0)
/* RDFFR*/
enum RDFFR_BIT {
RDFFR_RDLF = 0x01,
};
/* FCFTR */
enum FCFTR_BIT {
FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
};
#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
/* Transfer descriptor bit */
enum TD_STS_BIT {
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757)
TD_TACT = 0x80000000,
#else
TD_TACT = 0x7fffffff,
#endif
TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
TD_TFP0 = 0x10000000,
};
#define TDF1ST TD_TFP1
#define TDFEND TD_TFP0
#define TD_TFP (TD_TFP1|TD_TFP0)
/* RMCR */
enum RECV_RST_BIT { RMCR_RST = 0x01, };
/* ECMR */
enum FELIC_MODE_BIT {
#ifdef CONFIG_CPU_SH7763
ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
ECMR_RZPF = 0x00100000,
#endif
ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
ECMR_PRM = 0x00000001,
};
#ifdef CONFIG_CPU_SH7763
#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
ECMR_TXF | ECMR_MCT)
#elif CONFIG_CPU_SH7757
#define ECMR_CHG_DM (ECMR_ZPF)
#else
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
#endif
/* ECSR */
enum ECSR_STATUS_BIT {
#ifndef CONFIG_CPU_SH7763
ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
#endif
ECSR_LCHNG = 0x04,
ECSR_MPD = 0x02, ECSR_ICD = 0x01,
};
#ifdef CONFIG_CPU_SH7763
# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
#else
# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
#endif
/* ECSIPR */
enum ECSIPR_STATUS_MASK_BIT {
#ifndef CONFIG_CPU_SH7763
ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
#endif
ECSIPR_LCHNGIP = 0x04,
ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
};
#ifdef CONFIG_CPU_SH7763
# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
#else
# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
ECSIPR_ICDIP | ECSIPR_MPDIP)
#endif
/* APR */
enum APR_BIT {
#ifdef CONFIG_CPU_SH7757
APR_AP = 0x00000001,
#else
APR_AP = 0x00000004,
#endif
};
/* MPR */
enum MPR_BIT {
#ifdef CONFIG_CPU_SH7757
MPR_MP = 0x00000001,
#else
MPR_MP = 0x00000006,
#endif
};
/* TRSCER */
enum DESC_I_BIT {
DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
DESC_I_RINT1 = 0x0001,
};
/* RPADIR */
enum RPADIR_BIT {
RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
RPADIR_PADR = 0x0003f,
};
#ifdef CONFIG_CPU_SH7763
# define RPADIR_INIT (0x00)
#else
# define RPADIR_INIT (RPADIR_PADS1)
#endif
/* FDR */
enum FIFO_SIZE_BIT {
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
};
|
1001-study-uboot
|
drivers/net/sh_eth.h
|
C
|
gpl3
| 13,177
|
/****************************************************************************
* Copyright(c) 2000-2001 Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* Name: nicext.h
*
* Description: Broadcom Network Interface Card Extension (NICE) is an
* extension to Linux NET device kernel mode drivers.
* NICE is designed to provide additional functionalities,
* such as receive packet intercept. To support Broadcom NICE,
* the network device driver can be modified by adding an
* device ioctl handler and by indicating receiving packets
* to the NICE receive handler. Broadcom NICE will only be
* enabled by a NICE-aware intermediate driver, such as
* Broadcom Advanced Server Program Driver (BASP). When NICE
* is not enabled, the modified network device drivers
* functions exactly as other non-NICE aware drivers.
*
* Author: Frankie Fan
*
* Created: September 17, 2000
*
****************************************************************************/
#ifndef _nicext_h_
#define _nicext_h_
/*
* ioctl for NICE
*/
#define SIOCNICE SIOCDEVPRIVATE+7
/*
* SIOCNICE:
*
* The following structure needs to be less than IFNAMSIZ (16 bytes) because
* we're overloading ifreq.ifr_ifru.
*
* If 16 bytes is not enough, we should consider relaxing this because
* this is no field after ifr_ifru in the ifreq structure. But we may
* run into future compatiability problem in case of changing struct ifreq.
*/
struct nice_req
{
__u32 cmd;
union
{
#ifdef __KERNEL__
/* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */
struct
{
void (*nrqus1_rx)( struct sk_buff*, void* );
void* nrqus1_ctx;
} nrqu_nrqus1;
/* cmd = NICE_CMD_QUERY_SUPPORT */
struct
{
__u32 nrqus2_magic;
__u32 nrqus2_support_rx:1;
__u32 nrqus2_support_vlan:1;
__u32 nrqus2_support_get_speed:1;
} nrqu_nrqus2;
#endif
/* cmd = NICE_CMD_GET_SPEED */
struct
{
unsigned int nrqus3_speed; /* 0 if link is down, */
/* otherwise speed in Mbps */
} nrqu_nrqus3;
/* cmd = NICE_CMD_BLINK_LED */
struct
{
unsigned int nrqus4_blink_time; /* blink duration in seconds */
} nrqu_nrqus4;
} nrq_nrqu;
};
#define nrq_rx nrq_nrqu.nrqu_nrqus1.nrqus1_rx
#define nrq_ctx nrq_nrqu.nrqu_nrqus1.nrqus1_ctx
#define nrq_support_rx nrq_nrqu.nrqu_nrqus2.nrqus2_support_rx
#define nrq_magic nrq_nrqu.nrqu_nrqus2.nrqus2_magic
#define nrq_support_vlan nrq_nrqu.nrqu_nrqus2.nrqus2_support_vlan
#define nrq_support_get_speed nrq_nrqu.nrqu_nrqus2.nrqus2_support_get_speed
#define nrq_speed nrq_nrqu.nrqu_nrqus3.nrqus3_speed
#define nrq_blink_time nrq_nrqu.nrqu_nrqus4.nrqus4_blink_time
/*
* magic constants
*/
#define NICE_REQUESTOR_MAGIC 0x4543494E /* NICE in ascii */
#define NICE_DEVICE_MAGIC 0x4E494345 /* ECIN in ascii */
/*
* command field
*/
#define NICE_CMD_QUERY_SUPPORT 0x00000001
#define NICE_CMD_SET_RX 0x00000002
#define NICE_CMD_GET_RX 0x00000003
#define NICE_CMD_GET_SPEED 0x00000004
#define NICE_CMD_BLINK_LED 0x00000005
#endif /* _nicext_h_ */
|
1001-study-uboot
|
drivers/net/nicext.h
|
C
|
gpl3
| 3,446
|
/*
* rtl8169.c : U-Boot driver for the RealTek RTL8169
*
* Masami Komiya (mkomiya@sonare.it)
*
* Most part is taken from r8169.c of etherboot
*
*/
/**************************************************************************
* r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
* Written 2003 by Timothy Legge <tlegge@rogers.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Portions of this code based on:
* r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
* for Linux kernel 2.4.x.
*
* Written 2002 ShuChen <shuchen@realtek.com.tw>
* See Linux Driver for full information
*
* Linux Driver Version 1.27a, 10.02.2002
*
* Thanks to:
* Jean Chen of RealTek Semiconductor Corp. for
* providing the evaluation NIC used to develop
* this driver. RealTek's support for Etherboot
* is appreciated.
*
* REVISION HISTORY:
* ================
*
* v1.0 11-26-2003 timlegge Initial port of Linux driver
* v1.5 01-17-2004 timlegge Initial driver output cleanup
*
* Indent Options: indent -kr -i8
***************************************************************************/
/*
* 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk>
* Modified to use le32_to_cpu and cpu_to_le32 properly
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#undef DEBUG_RTL8169
#undef DEBUG_RTL8169_TX
#undef DEBUG_RTL8169_RX
#define drv_version "v1.5"
#define drv_date "01-17-2004"
static u32 ioaddr;
/* Condensed operations for readability. */
#define currticks() get_timer(0)
/* media options */
#define MAX_UNITS 8
static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
/* MAC address length*/
#define MAC_ADDR_LEN 6
/* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
#define MAX_ETH_FRAME_SIZE 1536
#define TX_FIFO_THRESH 256 /* In bytes */
#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
#define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
#define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
#define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
#define RX_BUF_SIZE 1536 /* Rx Buffer size */
#define RX_BUF_LEN 8192
#define RTL_MIN_IO_SIZE 0x80
#define TX_TIMEOUT (6*HZ)
/* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
#define RTL_R8(reg) readb (ioaddr + (reg))
#define RTL_R16(reg) readw (ioaddr + (reg))
#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
#define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE
#define ETH_ALEN MAC_ADDR_LEN
#define ETH_ZLEN 60
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a)
enum RTL8169_registers {
MAC0 = 0, /* Ethernet hardware address. */
MAR0 = 8, /* Multicast filter. */
TxDescStartAddrLow = 0x20,
TxDescStartAddrHigh = 0x24,
TxHDescStartAddrLow = 0x28,
TxHDescStartAddrHigh = 0x2c,
FLASH = 0x30,
ERSR = 0x36,
ChipCmd = 0x37,
TxPoll = 0x38,
IntrMask = 0x3C,
IntrStatus = 0x3E,
TxConfig = 0x40,
RxConfig = 0x44,
RxMissed = 0x4C,
Cfg9346 = 0x50,
Config0 = 0x51,
Config1 = 0x52,
Config2 = 0x53,
Config3 = 0x54,
Config4 = 0x55,
Config5 = 0x56,
MultiIntr = 0x5C,
PHYAR = 0x60,
TBICSR = 0x64,
TBI_ANAR = 0x68,
TBI_LPAR = 0x6A,
PHYstatus = 0x6C,
RxMaxSize = 0xDA,
CPlusCmd = 0xE0,
RxDescStartAddrLow = 0xE4,
RxDescStartAddrHigh = 0xE8,
EarlyTxThres = 0xEC,
FuncEvent = 0xF0,
FuncEventMask = 0xF4,
FuncPresetState = 0xF8,
FuncForceEvent = 0xFC,
};
enum RTL8169_register_content {
/*InterruptStatusBits */
SYSErr = 0x8000,
PCSTimeout = 0x4000,
SWInt = 0x0100,
TxDescUnavail = 0x80,
RxFIFOOver = 0x40,
RxUnderrun = 0x20,
RxOverflow = 0x10,
TxErr = 0x08,
TxOK = 0x04,
RxErr = 0x02,
RxOK = 0x01,
/*RxStatusDesc */
RxRES = 0x00200000,
RxCRC = 0x00080000,
RxRUNT = 0x00100000,
RxRWT = 0x00400000,
/*ChipCmdBits */
CmdReset = 0x10,
CmdRxEnb = 0x08,
CmdTxEnb = 0x04,
RxBufEmpty = 0x01,
/*Cfg9346Bits */
Cfg9346_Lock = 0x00,
Cfg9346_Unlock = 0xC0,
/*rx_mode_bits */
AcceptErr = 0x20,
AcceptRunt = 0x10,
AcceptBroadcast = 0x08,
AcceptMulticast = 0x04,
AcceptMyPhys = 0x02,
AcceptAllPhys = 0x01,
/*RxConfigBits */
RxCfgFIFOShift = 13,
RxCfgDMAShift = 8,
/*TxConfigBits */
TxInterFrameGapShift = 24,
TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
/*rtl8169_PHYstatus */
TBI_Enable = 0x80,
TxFlowCtrl = 0x40,
RxFlowCtrl = 0x20,
_1000bpsF = 0x10,
_100bps = 0x08,
_10bps = 0x04,
LinkStatus = 0x02,
FullDup = 0x01,
/*GIGABIT_PHY_registers */
PHY_CTRL_REG = 0,
PHY_STAT_REG = 1,
PHY_AUTO_NEGO_REG = 4,
PHY_1000_CTRL_REG = 9,
/*GIGABIT_PHY_REG_BIT */
PHY_Restart_Auto_Nego = 0x0200,
PHY_Enable_Auto_Nego = 0x1000,
/* PHY_STAT_REG = 1; */
PHY_Auto_Nego_Comp = 0x0020,
/* PHY_AUTO_NEGO_REG = 4; */
PHY_Cap_10_Half = 0x0020,
PHY_Cap_10_Full = 0x0040,
PHY_Cap_100_Half = 0x0080,
PHY_Cap_100_Full = 0x0100,
/* PHY_1000_CTRL_REG = 9; */
PHY_Cap_1000_Full = 0x0200,
PHY_Cap_Null = 0x0,
/*_MediaType*/
_10_Half = 0x01,
_10_Full = 0x02,
_100_Half = 0x04,
_100_Full = 0x08,
_1000_Full = 0x10,
/*_TBICSRBit*/
TBILinkOK = 0x02000000,
};
static struct {
const char *name;
u8 version; /* depend on RTL8169 docs */
u32 RxConfigMask; /* should clear the bits supported by this chip */
} rtl_chip_info[] = {
{"RTL-8169", 0x00, 0xff7e1880,},
{"RTL-8169", 0x04, 0xff7e1880,},
{"RTL-8169", 0x00, 0xff7e1880,},
{"RTL-8169s/8110s", 0x02, 0xff7e1880,},
{"RTL-8169s/8110s", 0x04, 0xff7e1880,},
{"RTL-8169sb/8110sb", 0x10, 0xff7e1880,},
{"RTL-8169sc/8110sc", 0x18, 0xff7e1880,},
{"RTL-8168b/8111sb", 0x30, 0xff7e1880,},
{"RTL-8168b/8111sb", 0x38, 0xff7e1880,},
{"RTL-8101e", 0x34, 0xff7e1880,},
{"RTL-8100e", 0x32, 0xff7e1880,},
};
enum _DescStatusBit {
OWNbit = 0x80000000,
EORbit = 0x40000000,
FSbit = 0x20000000,
LSbit = 0x10000000,
};
struct TxDesc {
u32 status;
u32 vlan_tag;
u32 buf_addr;
u32 buf_Haddr;
};
struct RxDesc {
u32 status;
u32 vlan_tag;
u32 buf_addr;
u32 buf_Haddr;
};
/* Define the TX Descriptor */
static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256];
/* __attribute__ ((aligned(256))); */
/* Create a static buffer of size RX_BUF_SZ for each
TX Descriptor. All descriptors point to a
part of this buffer */
static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
/* Define the RX Descriptor */
static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256];
/* __attribute__ ((aligned(256))); */
/* Create a static buffer of size RX_BUF_SZ for each
RX Descriptor All descriptors point to a
part of this buffer */
static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
struct rtl8169_private {
void *mmio_addr; /* memory map physical address */
int chipset;
unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
unsigned long dirty_tx;
unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
unsigned char *RxBufferRings; /* Index of Rx Buffer */
unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
unsigned char *Tx_skbuff[NUM_TX_DESC];
} tpx;
static struct rtl8169_private *tpc;
static const u16 rtl8169_intr_mask =
SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
TxOK | RxErr | RxOK;
static const unsigned int rtl8169_rx_config =
(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_REALTEK, 0x8167},
{PCI_VENDOR_ID_REALTEK, 0x8169},
{}
};
void mdio_write(int RegAddr, int value)
{
int i;
RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
udelay(1000);
for (i = 2000; i > 0; i--) {
/* Check if the RTL8169 has completed writing to the specified MII register */
if (!(RTL_R32(PHYAR) & 0x80000000)) {
break;
} else {
udelay(100);
}
}
}
int mdio_read(int RegAddr)
{
int i, value = -1;
RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
udelay(1000);
for (i = 2000; i > 0; i--) {
/* Check if the RTL8169 has completed retrieving data from the specified MII register */
if (RTL_R32(PHYAR) & 0x80000000) {
value = (int) (RTL_R32(PHYAR) & 0xFFFF);
break;
} else {
udelay(100);
}
}
return value;
}
static int rtl8169_init_board(struct eth_device *dev)
{
int i;
u32 tmp;
#ifdef DEBUG_RTL8169
printf ("%s\n", __FUNCTION__);
#endif
ioaddr = dev->iobase;
/* Soft reset the chip. */
RTL_W8(ChipCmd, CmdReset);
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--)
if ((RTL_R8(ChipCmd) & CmdReset) == 0)
break;
else
udelay(10);
/* identify chip attached to board */
tmp = RTL_R32(TxConfig);
tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){
if (tmp == rtl_chip_info[i].version) {
tpc->chipset = i;
goto match;
}
}
/* if unknown chip, assume array element #0, original RTL-8169 in this case */
printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name);
printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig));
tpc->chipset = 0;
match:
return 0;
}
/**************************************************************************
RECV - Receive a frame
***************************************************************************/
static int rtl_recv(struct eth_device *dev)
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
/* nic->packetlen should contain length of data */
int cur_rx;
int length = 0;
#ifdef DEBUG_RTL8169_RX
printf ("%s\n", __FUNCTION__);
#endif
ioaddr = dev->iobase;
cur_rx = tpc->cur_rx;
flush_cache((unsigned long)&tpc->RxDescArray[cur_rx],
sizeof(struct RxDesc));
if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
unsigned char rxdata[RX_BUF_LEN];
length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx].
status) & 0x00001FFF) - 4;
memcpy(rxdata, tpc->RxBufferRing[cur_rx], length);
NetReceive(rxdata, length);
if (cur_rx == NUM_RX_DESC - 1)
tpc->RxDescArray[cur_rx].status =
cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
else
tpc->RxDescArray[cur_rx].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxDescArray[cur_rx].buf_addr =
cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx]));
flush_cache((unsigned long)tpc->RxBufferRing[cur_rx],
RX_BUF_SIZE);
} else {
puts("Error Rx");
}
cur_rx = (cur_rx + 1) % NUM_RX_DESC;
tpc->cur_rx = cur_rx;
return 1;
} else {
ushort sts = RTL_R8(IntrStatus);
RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr));
udelay(100); /* wait */
}
tpc->cur_rx = cur_rx;
return (0); /* initially as this is called to flush the input */
}
#define HZ 1000
/**************************************************************************
SEND - Transmit a frame
***************************************************************************/
static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
{
/* send the packet to destination */
u32 to;
u8 *ptxb;
int entry = tpc->cur_tx % NUM_TX_DESC;
u32 len = length;
int ret;
#ifdef DEBUG_RTL8169_TX
int stime = currticks();
printf ("%s\n", __FUNCTION__);
printf("sending %d bytes\n", len);
#endif
ioaddr = dev->iobase;
/* point to the current txb incase multiple tx_rings are used */
ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
memcpy(ptxb, (char *)packet, (int)length);
flush_cache((unsigned long)ptxb, length);
while (len < ETH_ZLEN)
ptxb[len++] = '\0';
tpc->TxDescArray[entry].buf_Haddr = 0;
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb));
if (entry != (NUM_TX_DESC - 1)) {
tpc->TxDescArray[entry].status =
cpu_to_le32((OWNbit | FSbit | LSbit) |
((len > ETH_ZLEN) ? len : ETH_ZLEN));
} else {
tpc->TxDescArray[entry].status =
cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) |
((len > ETH_ZLEN) ? len : ETH_ZLEN));
}
RTL_W8(TxPoll, 0x40); /* set polling bit */
tpc->cur_tx++;
to = currticks() + TX_TIMEOUT;
do {
flush_cache((unsigned long)&tpc->TxDescArray[entry],
sizeof(struct TxDesc));
} while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
&& (currticks() < to)); /* wait */
if (currticks() >= to) {
#ifdef DEBUG_RTL8169_TX
puts ("tx timeout/error\n");
printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
#endif
ret = 0;
} else {
#ifdef DEBUG_RTL8169_TX
puts("tx done\n");
#endif
ret = length;
}
/* Delay to make net console (nc) work properly */
udelay(20);
return ret;
}
static void rtl8169_set_rx_mode(struct eth_device *dev)
{
u32 mc_filter[2]; /* Multicast hash filter */
int rx_mode;
u32 tmp = 0;
#ifdef DEBUG_RTL8169
printf ("%s\n", __FUNCTION__);
#endif
/* IFF_ALLMULTI */
/* Too many to filter perfectly -- accept all multicasts. */
rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
mc_filter[1] = mc_filter[0] = 0xffffffff;
tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
rtl_chip_info[tpc->chipset].RxConfigMask);
RTL_W32(RxConfig, tmp);
RTL_W32(MAR0 + 0, mc_filter[0]);
RTL_W32(MAR0 + 4, mc_filter[1]);
}
static void rtl8169_hw_start(struct eth_device *dev)
{
u32 i;
#ifdef DEBUG_RTL8169
int stime = currticks();
printf ("%s\n", __FUNCTION__);
#endif
#if 0
/* Soft reset the chip. */
RTL_W8(ChipCmd, CmdReset);
/* Check that the chip has finished the reset. */
for (i = 1000; i > 0; i--) {
if ((RTL_R8(ChipCmd) & CmdReset) == 0)
break;
else
udelay(10);
}
#endif
RTL_W8(Cfg9346, Cfg9346_Unlock);
/* RTL-8169sb/8110sb or previous version */
if (tpc->chipset <= 5)
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
RTL_W8(EarlyTxThres, EarlyTxThld);
/* For gigabit rtl8169 */
RTL_W16(RxMaxSize, RxPacketMaxSize);
/* Set Rx Config register */
i = rtl8169_rx_config | (RTL_R32(RxConfig) &
rtl_chip_info[tpc->chipset].RxConfigMask);
RTL_W32(RxConfig, i);
/* Set DMA burst size and Interframe Gap Time */
RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
(InterFrameGap << TxInterFrameGapShift));
tpc->cur_rx = 0;
RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray));
RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray));
RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
/* RTL-8169sc/8110sc or later version */
if (tpc->chipset > 5)
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
RTL_W8(Cfg9346, Cfg9346_Lock);
udelay(10);
RTL_W32(RxMissed, 0);
rtl8169_set_rx_mode(dev);
/* no early-rx interrupts */
RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
#ifdef DEBUG_RTL8169
printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
#endif
}
static void rtl8169_init_ring(struct eth_device *dev)
{
int i;
#ifdef DEBUG_RTL8169
int stime = currticks();
printf ("%s\n", __FUNCTION__);
#endif
tpc->cur_rx = 0;
tpc->cur_tx = 0;
tpc->dirty_tx = 0;
memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
for (i = 0; i < NUM_TX_DESC; i++) {
tpc->Tx_skbuff[i] = &txb[i];
}
for (i = 0; i < NUM_RX_DESC; i++) {
if (i == (NUM_RX_DESC - 1))
tpc->RxDescArray[i].status =
cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE);
else
tpc->RxDescArray[i].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
tpc->RxDescArray[i].buf_addr =
cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i]));
flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE);
}
#ifdef DEBUG_RTL8169
printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
#endif
}
/**************************************************************************
RESET - Finish setting up the ethernet interface
***************************************************************************/
static int rtl_reset(struct eth_device *dev, bd_t *bis)
{
int i;
#ifdef DEBUG_RTL8169
int stime = currticks();
printf ("%s\n", __FUNCTION__);
#endif
tpc->TxDescArrays = tx_ring;
/* Tx Desscriptor needs 256 bytes alignment; */
tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays +
255) & ~255);
tpc->RxDescArrays = rx_ring;
/* Rx Desscriptor needs 256 bytes alignment; */
tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays +
255) & ~255);
rtl8169_init_ring(dev);
rtl8169_hw_start(dev);
/* Construct a perfect filter frame with the mac address as first match
* and broadcast for all others */
for (i = 0; i < 192; i++)
txb[i] = 0xFF;
txb[0] = dev->enetaddr[0];
txb[1] = dev->enetaddr[1];
txb[2] = dev->enetaddr[2];
txb[3] = dev->enetaddr[3];
txb[4] = dev->enetaddr[4];
txb[5] = dev->enetaddr[5];
#ifdef DEBUG_RTL8169
printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime);
#endif
return 0;
}
/**************************************************************************
HALT - Turn off ethernet interface
***************************************************************************/
static void rtl_halt(struct eth_device *dev)
{
int i;
#ifdef DEBUG_RTL8169
printf ("%s\n", __FUNCTION__);
#endif
ioaddr = dev->iobase;
/* Stop the chip's Tx and Rx DMA processes. */
RTL_W8(ChipCmd, 0x00);
/* Disable interrupts by clearing the interrupt mask. */
RTL_W16(IntrMask, 0x0000);
RTL_W32(RxMissed, 0);
tpc->TxDescArrays = NULL;
tpc->RxDescArrays = NULL;
tpc->TxDescArray = NULL;
tpc->RxDescArray = NULL;
for (i = 0; i < NUM_RX_DESC; i++) {
tpc->RxBufferRing[i] = NULL;
}
}
/**************************************************************************
INIT - Look for an adapter, this routine's visible to the outside
***************************************************************************/
#define board_found 1
#define valid_link 0
static int rtl_init(struct eth_device *dev, bd_t *bis)
{
static int board_idx = -1;
int i, rc;
int option = -1, Cap10_100 = 0, Cap1000 = 0;
#ifdef DEBUG_RTL8169
printf ("%s\n", __FUNCTION__);
#endif
ioaddr = dev->iobase;
board_idx++;
/* point to private storage */
tpc = &tpx;
rc = rtl8169_init_board(dev);
if (rc)
return rc;
/* Get MAC address. FIXME: read EEPROM */
for (i = 0; i < MAC_ADDR_LEN; i++)
dev->enetaddr[i] = RTL_R8(MAC0 + i);
#ifdef DEBUG_RTL8169
printf("chipset = %d\n", tpc->chipset);
printf("MAC Address");
for (i = 0; i < MAC_ADDR_LEN; i++)
printf(":%02x", dev->enetaddr[i]);
putc('\n');
#endif
#ifdef DEBUG_RTL8169
/* Print out some hardware info */
printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr);
#endif
/* if TBI is not endbled */
if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
int val = mdio_read(PHY_AUTO_NEGO_REG);
option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
/* Force RTL8169 in 10/100/1000 Full/Half mode. */
if (option > 0) {
#ifdef DEBUG_RTL8169
printf("%s: Force-mode Enabled.\n", dev->name);
#endif
Cap10_100 = 0, Cap1000 = 0;
switch (option) {
case _10_Half:
Cap10_100 = PHY_Cap_10_Half;
Cap1000 = PHY_Cap_Null;
break;
case _10_Full:
Cap10_100 = PHY_Cap_10_Full;
Cap1000 = PHY_Cap_Null;
break;
case _100_Half:
Cap10_100 = PHY_Cap_100_Half;
Cap1000 = PHY_Cap_Null;
break;
case _100_Full:
Cap10_100 = PHY_Cap_100_Full;
Cap1000 = PHY_Cap_Null;
break;
case _1000_Full:
Cap10_100 = PHY_Cap_Null;
Cap1000 = PHY_Cap_1000_Full;
break;
default:
break;
}
mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
mdio_write(PHY_1000_CTRL_REG, Cap1000);
} else {
#ifdef DEBUG_RTL8169
printf("%s: Auto-negotiation Enabled.\n",
dev->name);
#endif
/* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
mdio_write(PHY_AUTO_NEGO_REG,
PHY_Cap_10_Half | PHY_Cap_10_Full |
PHY_Cap_100_Half | PHY_Cap_100_Full |
(val & 0x1F));
/* enable 1000 Full Mode */
mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
}
/* Enable auto-negotiation and restart auto-nigotiation */
mdio_write(PHY_CTRL_REG,
PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
udelay(100);
/* wait for auto-negotiation process */
for (i = 10000; i > 0; i--) {
/* check if auto-negotiation complete */
if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) {
udelay(100);
option = RTL_R8(PHYstatus);
if (option & _1000bpsF) {
#ifdef DEBUG_RTL8169
printf("%s: 1000Mbps Full-duplex operation.\n",
dev->name);
#endif
} else {
#ifdef DEBUG_RTL8169
printf("%s: %sMbps %s-duplex operation.\n",
dev->name,
(option & _100bps) ? "100" :
"10",
(option & FullDup) ? "Full" :
"Half");
#endif
}
break;
} else {
udelay(100);
}
} /* end for-loop to wait for auto-negotiation process */
} else {
udelay(100);
#ifdef DEBUG_RTL8169
printf
("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
dev->name,
(RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
#endif
}
return 1;
}
int rtl8169_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
/* Find RTL8169 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("Can not allocate memory of rtl8169\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8169#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)pci_mem_to_phys(devno, iobase);
dev->init = rtl_reset;
dev->halt = rtl_halt;
dev->send = rtl_send;
dev->recv = rtl_recv;
eth_register (dev);
rtl_init(dev, bis);
card_number++;
}
return card_number;
}
|
1001-study-uboot
|
drivers/net/rtl8169.c
|
C
|
gpl3
| 23,522
|
/*
Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
are GPL, so this is, of course, GPL.
*/
/* Generic NS8390 register definitions. */
/* This file is part of Donald Becker's 8390 drivers, and is distributed
under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
Some of these names and comments originated from the Crynwr
packet drivers, which are distributed under the GPL. */
#ifndef _8390_h
#define _8390_h
/* Some generic ethernet register configurations. */
#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
#define E8390_RX_IRQ_MASK 0x5
#define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */
#define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */
#define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */
#define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */
/* Register accessed at EN_CMD, the 8390 base addr. */
#define E8390_STOP 0x01 /* Stop and reset the chip */
#define E8390_START 0x02 /* Start the chip, clear reset */
#define E8390_TRANS 0x04 /* Transmit a frame */
#define E8390_RREAD 0x08 /* Remote read */
#define E8390_RWRITE 0x10 /* Remote write */
#define E8390_NODMA 0x20 /* Remote DMA */
#define E8390_PAGE0 0x00 /* Select page chip registers */
#define E8390_PAGE1 0x40 /* using the two high-order bits */
#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
/*
* Only generate indirect loads given a machine that needs them.
* - removed AMIGA_PCMCIA from this list, handled as ISA io now
*/
#define n2k_inb(port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)))
#define n2k_outb(val,port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)) = val)
#define EI_SHIFT(x) (x)
#define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */
/* Page 0 register offsets. */
#define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */
#define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
#define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */
#define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
#define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
#define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */
#define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
#define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */
#define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
#define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */
#define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
#define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
#define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */
#define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */
#define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */
#define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */
#define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
#define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
#define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */
#define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
#define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
#define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */
#define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
#define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */
#define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
#define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */
/* Bits in EN0_ISR - Interrupt status register */
#define ENISR_RX 0x01 /* Receiver, no error */
#define ENISR_TX 0x02 /* Transmitter, no error */
#define ENISR_RX_ERR 0x04 /* Receiver, with error */
#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
#define ENISR_COUNTERS 0x20 /* Counters need emptying */
#define ENISR_RDC 0x40 /* remote dma complete */
#define ENISR_RESET 0x80 /* Reset completed */
#define ENISR_ALL 0x3f /* Interrupts we will enable */
/* Bits in EN0_DCFG - Data config register */
#define ENDCFG_WTS 0x01 /* word transfer mode selection */
#define ENDCFG_BOS 0x02 /* byte order selection */
#define ENDCFG_AUTO_INIT 0x10 /* Auto-init to remove packets from ring */
#define ENDCFG_FIFO 0x40 /* 8 bytes */
/* Page 1 register offsets. */
#define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */
#define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
#define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */
/* Bits in received packet status byte and EN0_RSR*/
#define ENRSR_RXOK 0x01 /* Received a good packet */
#define ENRSR_CRC 0x02 /* CRC error */
#define ENRSR_FAE 0x04 /* frame alignment error */
#define ENRSR_FO 0x08 /* FIFO overrun */
#define ENRSR_MPA 0x10 /* missed pkt */
#define ENRSR_PHY 0x20 /* physical/multicast address */
#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
#define ENRSR_DEF 0x80 /* deferring */
/* Transmitted packet status, EN0_TSR. */
#define ENTSR_PTX 0x01 /* Packet transmitted without error */
#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
#define ENTSR_COL 0x04 /* The transmit collided at least once. */
#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
#define NIC_RECEIVE_MONITOR_MODE 0x20
#endif /* _8390_h */
|
1001-study-uboot
|
drivers/net/8390.h
|
C
|
gpl3
| 6,026
|
/*------------------------------------------------------------------------
* lan91c96.h
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Rolf Offermanns <rof@sysgo.de>
* Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
* Developed by Simple Network Magic Corporation (SNMC)
* Copyright (C) 1996 by Erik Stahlman (ES)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This file contains register information and access macros for
* the LAN91C96 single chip ethernet controller. It is a modified
* version of the smc9111.h file.
*
* Information contained in this file was obtained from the LAN91C96
* manual from SMC. To get a copy, if you really want one, you can find
* information under www.smsc.com.
*
* Authors
* Erik Stahlman ( erik@vt.edu )
* Daris A Nevil ( dnevil@snmc.com )
*
* History
* 04/30/03 Mathijs Haarman Modified smc91111.h (u-boot version)
* for lan91c96
*-------------------------------------------------------------------------
*/
#ifndef _LAN91C96_H_
#define _LAN91C96_H_
#include <asm/types.h>
#include <asm/io.h>
#include <config.h>
/* I want some simple types */
typedef unsigned char byte;
typedef unsigned short word;
typedef unsigned long int dword;
/*
* DEBUGGING LEVELS
*
* 0 for normal operation
* 1 for slightly more details
* >2 for various levels of increasingly useless information
* 2 for interrupt tracking, status flags
* 3 for packet info
* 4 for complete packet dumps
*/
/*#define SMC_DEBUG 0 */
/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
#define SMC_IO_EXTENT 16
#ifdef CONFIG_CPU_PXA25X
#ifdef CONFIG_LUBBOCK
#define SMC_IO_SHIFT 2
#undef USE_32_BIT
#else
#define SMC_IO_SHIFT 0
#endif
#define SMCREG(edev, r) ((edev)->iobase+((r)<<SMC_IO_SHIFT))
#define SMC_inl(edev, r) (*((volatile dword *)SMCREG(edev, r)))
#define SMC_inw(edev, r) (*((volatile word *)SMCREG(edev, r)))
#define SMC_inb(edev, p) ({ \
unsigned int __p = p; \
unsigned int __v = SMC_inw(edev, __p & ~1); \
if (__p & 1) __v >>= 8; \
else __v &= 0xff; \
__v; })
#define SMC_outl(edev, d, r) (*((volatile dword *)SMCREG(edev, r)) = d)
#define SMC_outw(edev, d, r) (*((volatile word *)SMCREG(edev, r)) = d)
#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
word __w = SMC_inw(edev, (r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
SMC_outw(edev, __w, (r)&~1); \
})
#define SMC_outsl(edev, r, b, l) ({ int __i; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
SMC_outl(edev, *(__b2 + __i),\
r); \
} \
})
#define SMC_outsw(edev, r, b, l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
SMC_outw(edev, *(__b2 + __i),\
r); \
} \
})
#define SMC_insl(edev, r, b, l) ({ int __i ; \
dword *__b2; \
__b2 = (dword *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inl(edev,\
r); \
SMC_inl(edev, 0); \
}; \
})
#define SMC_insw(edev, r, b, l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inw(edev,\
r); \
SMC_inw(edev, 0); \
}; \
})
#define SMC_insb(edev, r, b, l) ({ int __i ; \
byte *__b2; \
__b2 = (byte *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inb(edev,\
r); \
SMC_inb(edev, 0); \
}; \
})
#else /* if not CONFIG_CPU_PXA25X */
/*
* We have only 16 Bit PCMCIA access on Socket 0
*/
#define SMC_inw(edev, r) (*((volatile word *)((edev)->iobase+(r))))
#define SMC_inb(edev, r) (((r)&1) ? SMC_inw(edev, (r)&~1)>>8 :\
SMC_inw(edev, r)&0xFF)
#define SMC_outw(edev, d, r) (*((volatile word *)((edev)->iobase+(r))) = d)
#define SMC_outb(edev, d, r) ({ word __d = (byte)(d); \
word __w = SMC_inw(edev, (r)&~1); \
__w &= ((r)&1) ? 0x00FF : 0xFF00; \
__w |= ((r)&1) ? __d<<8 : __d; \
SMC_outw(edev, __w, (r)&~1); \
})
#define SMC_outsw(edev, r, b, l) ({ int __i; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
SMC_outw(edev, *(__b2 + __i),\
r); \
} \
})
#define SMC_insw(edev, r, b, l) ({ int __i ; \
word *__b2; \
__b2 = (word *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = SMC_inw(edev,\
r); \
SMC_inw(edev, 0); \
}; \
})
#endif
/*
****************************************************************************
* Bank Select Field
****************************************************************************
*/
#define LAN91C96_BANK_SELECT 14 /* Bank Select Register */
#define LAN91C96_BANKSELECT (0x3UC << 0)
#define BANK0 0x00
#define BANK1 0x01
#define BANK2 0x02
#define BANK3 0x03
#define BANK4 0x04
/*
****************************************************************************
* EEPROM Addresses.
****************************************************************************
*/
#define EEPROM_MAC_OFFSET_1 0x6020
#define EEPROM_MAC_OFFSET_2 0x6021
#define EEPROM_MAC_OFFSET_3 0x6022
/*
****************************************************************************
* Bank 0 Register Map in I/O Space
****************************************************************************
*/
#define LAN91C96_TCR 0 /* Transmit Control Register */
#define LAN91C96_EPH_STATUS 2 /* EPH Status Register */
#define LAN91C96_RCR 4 /* Receive Control Register */
#define LAN91C96_COUNTER 6 /* Counter Register */
#define LAN91C96_MIR 8 /* Memory Information Register */
#define LAN91C96_MCR 10 /* Memory Configuration Register */
/*
****************************************************************************
* Transmit Control Register - Bank 0 - Offset 0
****************************************************************************
*/
#define LAN91C96_TCR_TXENA (0x1U << 0)
#define LAN91C96_TCR_LOOP (0x1U << 1)
#define LAN91C96_TCR_FORCOL (0x1U << 2)
#define LAN91C96_TCR_TXP_EN (0x1U << 3)
#define LAN91C96_TCR_PAD_EN (0x1U << 7)
#define LAN91C96_TCR_NOCRC (0x1U << 8)
#define LAN91C96_TCR_MON_CSN (0x1U << 10)
#define LAN91C96_TCR_FDUPLX (0x1U << 11)
#define LAN91C96_TCR_STP_SQET (0x1U << 12)
#define LAN91C96_TCR_EPH_LOOP (0x1U << 13)
#define LAN91C96_TCR_ETEN_TYPE (0x1U << 14)
#define LAN91C96_TCR_FDSE (0x1U << 15)
/*
****************************************************************************
* EPH Status Register - Bank 0 - Offset 2
****************************************************************************
*/
#define LAN91C96_EPHSR_TX_SUC (0x1U << 0)
#define LAN91C96_EPHSR_SNGL_COL (0x1U << 1)
#define LAN91C96_EPHSR_MUL_COL (0x1U << 2)
#define LAN91C96_EPHSR_LTX_MULT (0x1U << 3)
#define LAN91C96_EPHSR_16COL (0x1U << 4)
#define LAN91C96_EPHSR_SQET (0x1U << 5)
#define LAN91C96_EPHSR_LTX_BRD (0x1U << 6)
#define LAN91C96_EPHSR_TX_DEFR (0x1U << 7)
#define LAN91C96_EPHSR_WAKEUP (0x1U << 8)
#define LAN91C96_EPHSR_LATCOL (0x1U << 9)
#define LAN91C96_EPHSR_LOST_CARR (0x1U << 10)
#define LAN91C96_EPHSR_EXC_DEF (0x1U << 11)
#define LAN91C96_EPHSR_CTR_ROL (0x1U << 12)
#define LAN91C96_EPHSR_LINK_OK (0x1U << 14)
#define LAN91C96_EPHSR_TX_UNRN (0x1U << 15)
#define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \
LAN91C96_EPHSR_MUL_COL | \
LAN91C96_EPHSR_16COL | \
LAN91C96_EPHSR_SQET | \
LAN91C96_EPHSR_TX_DEFR | \
LAN91C96_EPHSR_LATCOL | \
LAN91C96_EPHSR_LOST_CARR | \
LAN91C96_EPHSR_EXC_DEF | \
LAN91C96_EPHSR_LINK_OK | \
LAN91C96_EPHSR_TX_UNRN)
/*
****************************************************************************
* Receive Control Register - Bank 0 - Offset 4
****************************************************************************
*/
#define LAN91C96_RCR_RX_ABORT (0x1U << 0)
#define LAN91C96_RCR_PRMS (0x1U << 1)
#define LAN91C96_RCR_ALMUL (0x1U << 2)
#define LAN91C96_RCR_RXEN (0x1U << 8)
#define LAN91C96_RCR_STRIP_CRC (0x1U << 9)
#define LAN91C96_RCR_FILT_CAR (0x1U << 14)
#define LAN91C96_RCR_SOFT_RST (0x1U << 15)
/*
****************************************************************************
* Counter Register - Bank 0 - Offset 6
****************************************************************************
*/
#define LAN91C96_ECR_SNGL_COL (0xFU << 0)
#define LAN91C96_ECR_MULT_COL (0xFU << 5)
#define LAN91C96_ECR_DEF_TX (0xFU << 8)
#define LAN91C96_ECR_EXC_DEF_TX (0xFU << 12)
/*
****************************************************************************
* Memory Information Register - Bank 0 - OFfset 8
****************************************************************************
*/
#define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */
/*
****************************************************************************
* Memory Configuration Register - Bank 0 - Offset 10
****************************************************************************
*/
#define LAN91C96_MCR_MEM_RES (0xFFU << 0)
#define LAN91C96_MCR_MEM_MULT (0x3U << 9)
#define LAN91C96_MCR_HIGH_ID (0x3U << 12)
#define LAN91C96_MCR_TRANSMIT_PAGES 0x6
/*
****************************************************************************
* Bank 1 Register Map in I/O Space
****************************************************************************
*/
#define LAN91C96_CONFIG 0 /* Configuration Register */
#define LAN91C96_BASE 2 /* Base Address Register */
#define LAN91C96_IA0 4 /* Individual Address Register - 0 */
#define LAN91C96_IA1 5 /* Individual Address Register - 1 */
#define LAN91C96_IA2 6 /* Individual Address Register - 2 */
#define LAN91C96_IA3 7 /* Individual Address Register - 3 */
#define LAN91C96_IA4 8 /* Individual Address Register - 4 */
#define LAN91C96_IA5 9 /* Individual Address Register - 5 */
#define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */
#define LAN91C96_CONTROL 12 /* Control Register */
/*
****************************************************************************
* Configuration Register - Bank 1 - Offset 0
****************************************************************************
*/
#define LAN91C96_CR_INT_SEL0 (0x1U << 1)
#define LAN91C96_CR_INT_SEL1 (0x1U << 2)
#define LAN91C96_CR_RES (0x3U << 3)
#define LAN91C96_CR_DIS_LINK (0x1U << 6)
#define LAN91C96_CR_16BIT (0x1U << 7)
#define LAN91C96_CR_AUI_SELECT (0x1U << 8)
#define LAN91C96_CR_SET_SQLCH (0x1U << 9)
#define LAN91C96_CR_FULL_STEP (0x1U << 10)
#define LAN91C96_CR_NO_WAIT (0x1U << 12)
/*
****************************************************************************
* Base Address Register - Bank 1 - Offset 2
****************************************************************************
*/
#define LAN91C96_BAR_RA_BITS (0x27U << 0)
#define LAN91C96_BAR_ROM_SIZE (0x1U << 6)
#define LAN91C96_BAR_A_BITS (0xFFU << 8)
/*
****************************************************************************
* Control Register - Bank 1 - Offset 12
****************************************************************************
*/
#define LAN91C96_CTR_STORE (0x1U << 0)
#define LAN91C96_CTR_RELOAD (0x1U << 1)
#define LAN91C96_CTR_EEPROM (0x1U << 2)
#define LAN91C96_CTR_TE_ENABLE (0x1U << 5)
#define LAN91C96_CTR_CR_ENABLE (0x1U << 6)
#define LAN91C96_CTR_LE_ENABLE (0x1U << 7)
#define LAN91C96_CTR_BIT_8 (0x1U << 8)
#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
#define LAN91C96_CTR_WAKEUP_EN (0x1U << 12)
#define LAN91C96_CTR_PWRDN (0x1U << 13)
#define LAN91C96_CTR_RCV_BAD (0x1U << 14)
/*
****************************************************************************
* Bank 2 Register Map in I/O Space
****************************************************************************
*/
#define LAN91C96_MMU 0 /* MMU Command Register */
#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */
#define LAN91C96_PNR 2 /* Packet Number Register */
#define LAN91C96_ARR 3 /* Allocation Result Register */
#define LAN91C96_FIFO 4 /* FIFO Ports Register */
#define LAN91C96_POINTER 6 /* Pointer Register */
#define LAN91C96_DATA_HIGH 8 /* Data High Register */
#define LAN91C96_DATA_LOW 10 /* Data Low Register */
#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */
#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */
#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */
/*
****************************************************************************
* MMU Command Register - Bank 2 - Offset 0
****************************************************************************
*/
#define LAN91C96_MMUCR_NO_BUSY (0x1U << 0)
#define LAN91C96_MMUCR_N1 (0x1U << 1)
#define LAN91C96_MMUCR_N2 (0x1U << 2)
#define LAN91C96_MMUCR_COMMAND (0xFU << 4)
#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */
#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */
#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */
#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */
#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */
#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */
#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */
#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */
/*
****************************************************************************
* Auto Tx Start Register - Bank 2 - Offset 1
****************************************************************************
*/
#define LAN91C96_AUTOTX (0xFFU << 0)
/*
****************************************************************************
* Packet Number Register - Bank 2 - Offset 2
****************************************************************************
*/
#define LAN91C96_PNR_TX (0x1FU << 0)
/*
****************************************************************************
* Allocation Result Register - Bank 2 - Offset 3
****************************************************************************
*/
#define LAN91C96_ARR_ALLOC_PN (0x7FU << 0)
#define LAN91C96_ARR_FAILED (0x1U << 7)
/*
****************************************************************************
* FIFO Ports Register - Bank 2 - Offset 4
****************************************************************************
*/
#define LAN91C96_FIFO_TX_DONE_PN (0x1FU << 0)
#define LAN91C96_FIFO_TEMPTY (0x1U << 7)
#define LAN91C96_FIFO_RX_DONE_PN (0x1FU << 8)
#define LAN91C96_FIFO_RXEMPTY (0x1U << 15)
/*
****************************************************************************
* Pointer Register - Bank 2 - Offset 6
****************************************************************************
*/
#define LAN91C96_PTR_LOW (0xFFU << 0)
#define LAN91C96_PTR_HIGH (0x7U << 8)
#define LAN91C96_PTR_AUTO_TX (0x1U << 11)
#define LAN91C96_PTR_ETEN (0x1U << 12)
#define LAN91C96_PTR_READ (0x1U << 13)
#define LAN91C96_PTR_AUTO_INCR (0x1U << 14)
#define LAN91C96_PTR_RCV (0x1U << 15)
#define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \
LAN91C96_PTR_AUTO_INCR | \
LAN91C96_PTR_READ)
/*
****************************************************************************
* Data Register - Bank 2 - Offset 8
****************************************************************************
*/
#define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */
#define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */
/*
****************************************************************************
* Interrupt Status Register - Bank 2 - Offset 12
****************************************************************************
*/
#define LAN91C96_IST_RCV_INT (0x1U << 0)
#define LAN91C96_IST_TX_INT (0x1U << 1)
#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
#define LAN91C96_IST_ALLOC_INT (0x1U << 3)
#define LAN91C96_IST_RX_OVRN_INT (0x1U << 4)
#define LAN91C96_IST_EPH_INT (0x1U << 5)
#define LAN91C96_IST_ERCV_INT (0x1U << 6)
#define LAN91C96_IST_RX_IDLE_INT (0x1U << 7)
/*
****************************************************************************
* Interrupt Acknowledge Register - Bank 2 - Offset 12
****************************************************************************
*/
#define LAN91C96_ACK_TX_INT (0x1U << 1)
#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
#define LAN91C96_ACK_RX_OVRN_INT (0x1U << 4)
#define LAN91C96_ACK_ERCV_INT (0x1U << 6)
/*
****************************************************************************
* Interrupt Mask Register - Bank 2 - Offset 13
****************************************************************************
*/
#define LAN91C96_MSK_RCV_INT (0x1U << 0)
#define LAN91C96_MSK_TX_INT (0x1U << 1)
#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
#define LAN91C96_MSK_ALLOC_INT (0x1U << 3)
#define LAN91C96_MSK_RX_OVRN_INT (0x1U << 4)
#define LAN91C96_MSK_EPH_INT (0x1U << 5)
#define LAN91C96_MSK_ERCV_INT (0x1U << 6)
#define LAN91C96_MSK_TX_IDLE_INT (0x1U << 7)
/*
****************************************************************************
* Bank 3 Register Map in I/O Space
**************************************************************************
*/
#define LAN91C96_MGMT_MDO (0x1U << 0)
#define LAN91C96_MGMT_MDI (0x1U << 1)
#define LAN91C96_MGMT_MCLK (0x1U << 2)
#define LAN91C96_MGMT_MDOE (0x1U << 3)
#define LAN91C96_MGMT_LOW_ID (0x3U << 4)
#define LAN91C96_MGMT_IOS0 (0x1U << 8)
#define LAN91C96_MGMT_IOS1 (0x1U << 9)
#define LAN91C96_MGMT_IOS2 (0x1U << 10)
#define LAN91C96_MGMT_nXNDEC (0x1U << 11)
#define LAN91C96_MGMT_HIGH_ID (0x3U << 12)
/*
****************************************************************************
* Revision Register - Bank 3 - Offset 10
****************************************************************************
*/
#define LAN91C96_REV_REVID (0xFU << 0)
#define LAN91C96_REV_CHIPID (0xFU << 4)
/*
****************************************************************************
* Early RCV Register - Bank 3 - Offset 12
****************************************************************************
*/
#define LAN91C96_ERCV_THRESHOLD (0x1FU << 0)
#define LAN91C96_ERCV_RCV_DISCRD (0x1U << 7)
/*
****************************************************************************
* PCMCIA Configuration Registers
****************************************************************************
*/
#define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */
#define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */
/*
****************************************************************************
* PCMCIA Ethernet Configuration Option Register (ECOR)
****************************************************************************
*/
#define LAN91C96_ECOR_ENABLE (0x1U << 0)
#define LAN91C96_ECOR_WR_ATTRIB (0x1U << 2)
#define LAN91C96_ECOR_LEVEL_REQ (0x1U << 6)
#define LAN91C96_ECOR_SRESET (0x1U << 7)
/*
****************************************************************************
* PCMCIA Ethernet Configuration and Status Register (ECSR)
****************************************************************************
*/
#define LAN91C96_ECSR_INTR (0x1U << 1)
#define LAN91C96_ECSR_PWRDWN (0x1U << 2)
#define LAN91C96_ECSR_IOIS8 (0x1U << 5)
/*
****************************************************************************
* Receive Frame Status Word - See page 38 of the LAN91C96 specification.
****************************************************************************
*/
#define LAN91C96_TOO_SHORT (0x1U << 10)
#define LAN91C96_TOO_LONG (0x1U << 11)
#define LAN91C96_ODD_FRM (0x1U << 12)
#define LAN91C96_BAD_CRC (0x1U << 13)
#define LAN91C96_BROD_CAST (0x1U << 14)
#define LAN91C96_ALGN_ERR (0x1U << 15)
#define FRAME_FILTER (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG | LAN91C96_BAD_CRC | LAN91C96_ALGN_ERR)
/*
****************************************************************************
* Default MAC Address
****************************************************************************
*/
#define MAC_DEF_HI 0x0800
#define MAC_DEF_MED 0x3333
#define MAC_DEF_LO 0x0100
/*
****************************************************************************
* Default I/O Signature - 0x33
****************************************************************************
*/
#define LAN91C96_LOW_SIGNATURE (0x33U << 0)
#define LAN91C96_HIGH_SIGNATURE (0x33U << 8)
#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)
#define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */
#define ETHERNET_MAX_LENGTH 1514
/*-------------------------------------------------------------------------
* I define some macros to make it easier to do somewhat common
* or slightly complicated, repeated tasks.
*-------------------------------------------------------------------------
*/
/* select a register bank, 0 to 3 */
#define SMC_SELECT_BANK(edev, x) { SMC_outw(edev, x, LAN91C96_BANK_SELECT); }
/* this enables an interrupt in the interrupt mask register */
#define SMC_ENABLE_INT(edev, x) {\
unsigned char mask;\
SMC_SELECT_BANK(edev, 2);\
mask = SMC_inb(edev, LAN91C96_INT_MASK);\
mask |= (x);\
SMC_outb(edev, mask, LAN91C96_INT_MASK); \
}
/* this disables an interrupt from the interrupt mask register */
#define SMC_DISABLE_INT(edev, x) {\
unsigned char mask;\
SMC_SELECT_BANK(edev, 2);\
mask = SMC_inb(edev, LAN91C96_INT_MASK);\
mask &= ~(x);\
SMC_outb(edev, mask, LAN91C96_INT_MASK); \
}
/*----------------------------------------------------------------------
* Define the interrupts that I want to receive from the card
*
* I want:
* LAN91C96_IST_EPH_INT, for nasty errors
* LAN91C96_IST_RCV_INT, for happy received packets
* LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
*-------------------------------------------------------------------------
*/
#define SMC_INTERRUPT_MASK (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)
#endif /* _LAN91C96_H_ */
|
1001-study-uboot
|
drivers/net/lan91c96.h
|
C
|
gpl3
| 23,793
|
/*
* SMSC LAN9[12]1[567] Network driver
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <malloc.h>
#include <net.h>
#include <miiphy.h>
#include "smc911x.h"
u32 pkt_data_pull(struct eth_device *dev, u32 addr) \
__attribute__ ((weak, alias ("smc911x_reg_read")));
void pkt_data_push(struct eth_device *dev, u32 addr, u32 val) \
__attribute__ ((weak, alias ("smc911x_reg_write")));
static void smc911x_handle_mac_address(struct eth_device *dev)
{
unsigned long addrh, addrl;
uchar *m = dev->enetaddr;
addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
addrh = m[4] | (m[5] << 8);
smc911x_set_mac_csr(dev, ADDRL, addrl);
smc911x_set_mac_csr(dev, ADDRH, addrh);
printf(DRIVERNAME ": MAC %pM\n", m);
}
static int smc911x_eth_phy_read(struct eth_device *dev,
u8 phy, u8 reg, u16 *val)
{
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 |
MII_ACC_MII_BUSY);
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
*val = smc911x_get_mac_csr(dev, MII_DATA);
return 0;
}
static int smc911x_eth_phy_write(struct eth_device *dev,
u8 phy, u8 reg, u16 val)
{
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
smc911x_set_mac_csr(dev, MII_DATA, val);
smc911x_set_mac_csr(dev, MII_ACC,
phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
;
return 0;
}
static int smc911x_phy_reset(struct eth_device *dev)
{
u32 reg;
reg = smc911x_reg_read(dev, PMT_CTRL);
reg &= ~0xfffff030;
reg |= PMT_CTRL_PHY_RST;
smc911x_reg_write(dev, PMT_CTRL, reg);
mdelay(100);
return 0;
}
static void smc911x_phy_configure(struct eth_device *dev)
{
int timeout;
u16 status;
smc911x_phy_reset(dev);
smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
mdelay(1);
smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1);
smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE |
BMCR_ANRESTART);
timeout = 5000;
do {
mdelay(1);
if ((timeout--) == 0)
goto err_out;
if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0)
goto err_out;
} while (!(status & BMSR_LSTATUS));
printf(DRIVERNAME ": phy initialized\n");
return;
err_out:
printf(DRIVERNAME ": autonegotiation timed out\n");
}
static void smc911x_enable(struct eth_device *dev)
{
/* Enable TX */
smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
/* no padding to start of packets */
smc911x_reg_write(dev, RX_CFG, 0);
smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
MAC_CR_HBDIS);
}
static int smc911x_init(struct eth_device *dev, bd_t * bd)
{
struct chip_id *id = dev->priv;
printf(DRIVERNAME ": detected %s controller\n", id->name);
smc911x_reset(dev);
/* Configure the PHY, initialize the link state */
smc911x_phy_configure(dev);
smc911x_handle_mac_address(dev);
/* Turn on Tx + Rx */
smc911x_enable(dev);
return 0;
}
static int smc911x_send(struct eth_device *dev,
volatile void *packet, int length)
{
u32 *data = (u32*)packet;
u32 tmplen;
u32 status;
smc911x_reg_write(dev, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG |
TX_CMD_A_INT_LAST_SEG | length);
smc911x_reg_write(dev, TX_DATA_FIFO, length);
tmplen = (length + 3) / 4;
while (tmplen--)
pkt_data_push(dev, TX_DATA_FIFO, *data++);
/* wait for transmission */
while (!((smc911x_reg_read(dev, TX_FIFO_INF) &
TX_FIFO_INF_TSUSED) >> 16));
/* get status. Ignore 'no carrier' error, it has no meaning for
* full duplex operation
*/
status = smc911x_reg_read(dev, TX_STATUS_FIFO) &
(TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
if (!status)
return 0;
printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
status & TX_STS_LOC ? "TX_STS_LOC " : "",
status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
return -1;
}
static void smc911x_halt(struct eth_device *dev)
{
smc911x_reset(dev);
}
static int smc911x_rx(struct eth_device *dev)
{
u32 *data = (u32 *)NetRxPackets[0];
u32 pktlen, tmplen;
u32 status;
if ((smc911x_reg_read(dev, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16) {
status = smc911x_reg_read(dev, RX_STATUS_FIFO);
pktlen = (status & RX_STS_PKT_LEN) >> 16;
smc911x_reg_write(dev, RX_CFG, 0);
tmplen = (pktlen + 3) / 4;
while (tmplen--)
*data++ = pkt_data_pull(dev, RX_DATA_FIFO);
if (status & RX_STS_ES)
printf(DRIVERNAME
": dropped bad packet. Status: 0x%08x\n",
status);
else
NetReceive(NetRxPackets[0], pktlen);
}
return 0;
}
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* wrapper for smc911x_eth_phy_read */
static int smc911x_miiphy_read(const char *devname, u8 phy, u8 reg, u16 *val)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
if (dev)
return smc911x_eth_phy_read(dev, phy, reg, val);
return -1;
}
/* wrapper for smc911x_eth_phy_write */
static int smc911x_miiphy_write(const char *devname, u8 phy, u8 reg, u16 val)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
if (dev)
return smc911x_eth_phy_write(dev, phy, reg, val);
return -1;
}
#endif
int smc911x_initialize(u8 dev_num, int base_addr)
{
unsigned long addrl, addrh;
struct eth_device *dev;
dev = malloc(sizeof(*dev));
if (!dev) {
return -1;
}
memset(dev, 0, sizeof(*dev));
dev->iobase = base_addr;
/* Try to detect chip. Will fail if not present. */
if (smc911x_detect_chip(dev)) {
free(dev);
return 0;
}
addrh = smc911x_get_mac_csr(dev, ADDRH);
addrl = smc911x_get_mac_csr(dev, ADDRL);
if (!(addrl == 0xffffffff && addrh == 0x0000ffff)) {
/* address is obtained from optional eeprom */
dev->enetaddr[0] = addrl;
dev->enetaddr[1] = addrl >> 8;
dev->enetaddr[2] = addrl >> 16;
dev->enetaddr[3] = addrl >> 24;
dev->enetaddr[4] = addrh;
dev->enetaddr[5] = addrh >> 8;
}
dev->init = smc911x_init;
dev->halt = smc911x_halt;
dev->send = smc911x_send;
dev->recv = smc911x_rx;
sprintf(dev->name, "%s-%hu", DRIVERNAME, dev_num);
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, smc911x_miiphy_read, smc911x_miiphy_write);
#endif
return 1;
}
|
1001-study-uboot
|
drivers/net/smc911x.c
|
C
|
gpl3
| 7,310
|
/*
* Faraday FTMAC100 Ethernet
*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include "ftmac100.h"
#define ETH_ZLEN 60
struct ftmac100_data {
struct ftmac100_txdes txdes[1];
struct ftmac100_rxdes rxdes[PKTBUFSRX];
int rx_index;
};
/*
* Reset MAC
*/
static void ftmac100_reset (struct eth_device *dev)
{
struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
debug ("%s()\n", __func__);
writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr);
while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST)
;
}
/*
* Set MAC address
*/
static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac)
{
struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
unsigned int maddr = mac[0] << 8 | mac[1];
unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
debug ("%s(%x %x)\n", __func__, maddr, laddr);
writel (maddr, &ftmac100->mac_madr);
writel (laddr, &ftmac100->mac_ladr);
}
static void ftmac100_set_mac_from_env (struct eth_device *dev)
{
eth_getenv_enetaddr ("ethaddr", dev->enetaddr);
ftmac100_set_mac (dev, dev->enetaddr);
}
/*
* disable transmitter, receiver
*/
static void ftmac100_halt (struct eth_device *dev)
{
struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
debug ("%s()\n", __func__);
writel (0, &ftmac100->maccr);
}
static int ftmac100_init (struct eth_device *dev, bd_t *bd)
{
struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
struct ftmac100_data *priv = dev->priv;
struct ftmac100_txdes *txdes = priv->txdes;
struct ftmac100_rxdes *rxdes = priv->rxdes;
unsigned int maccr;
int i;
debug ("%s()\n", __func__);
ftmac100_reset (dev);
/* set the ethernet address */
ftmac100_set_mac_from_env (dev);
/* disable all interrupts */
writel (0, &ftmac100->imr);
/* initialize descriptors */
priv->rx_index = 0;
txdes[0].txdes1 = FTMAC100_TXDES1_EDOTR;
rxdes[PKTBUFSRX - 1].rxdes1 = FTMAC100_RXDES1_EDORR;
for (i = 0; i < PKTBUFSRX; i++) {
/* RXBUF_BADR */
rxdes[i].rxdes2 = (unsigned int)NetRxPackets[i];
rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN);
rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN;
}
/* transmit ring */
writel ((unsigned int)txdes, &ftmac100->txr_badr);
/* receive ring */
writel ((unsigned int)rxdes, &ftmac100->rxr_badr);
/* poll receive descriptor automatically */
writel (FTMAC100_APTC_RXPOLL_CNT (1), &ftmac100->aptc);
/* enable transmitter, receiver */
maccr = FTMAC100_MACCR_XMT_EN |
FTMAC100_MACCR_RCV_EN |
FTMAC100_MACCR_XDMA_EN |
FTMAC100_MACCR_RDMA_EN |
FTMAC100_MACCR_CRC_APD |
FTMAC100_MACCR_ENRX_IN_HALFTX |
FTMAC100_MACCR_RX_RUNT |
FTMAC100_MACCR_RX_BROADPKT;
writel (maccr, &ftmac100->maccr);
return 0;
}
/*
* Get a data block via Ethernet
*/
static int ftmac100_recv (struct eth_device *dev)
{
struct ftmac100_data *priv = dev->priv;
struct ftmac100_rxdes *curr_des;
unsigned short rxlen;
curr_des = &priv->rxdes[priv->rx_index];
if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN)
return -1;
if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR |
FTMAC100_RXDES0_CRC_ERR |
FTMAC100_RXDES0_FTL |
FTMAC100_RXDES0_RUNT |
FTMAC100_RXDES0_RX_ODD_NB)) {
return -1;
}
rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0);
debug ("%s(): RX buffer %d, %x received\n",
__func__, priv->rx_index, rxlen);
/* pass the packet up to the protocol layers. */
NetReceive ((void *)curr_des->rxdes2, rxlen);
/* release buffer to DMA */
curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN;
priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
return 0;
}
/*
* Send a data block via Ethernet
*/
static int
ftmac100_send (struct eth_device *dev, volatile void *packet, int length)
{
struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase;
struct ftmac100_data *priv = dev->priv;
struct ftmac100_txdes *curr_des = priv->txdes;
ulong start;
if (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
debug ("%s(): no TX descriptor available\n", __func__);
return -1;
}
debug ("%s(%x, %x)\n", __func__, (int)packet, length);
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
/* initiate a transmit sequence */
curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */
curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR;
curr_des->txdes1 |= FTMAC100_TXDES1_FTS |
FTMAC100_TXDES1_LTS |
FTMAC100_TXDES1_TXBUF_SIZE (length);
curr_des->txdes0 = FTMAC100_TXDES0_TXDMA_OWN;
/* start transmit */
writel (1, &ftmac100->txpd);
/* wait for transfer to succeed */
start = get_timer(0);
while (curr_des->txdes0 & FTMAC100_TXDES0_TXDMA_OWN) {
if (get_timer(start) >= 5) {
debug ("%s(): timed out\n", __func__);
return -1;
}
}
debug ("%s(): packet sent\n", __func__);
return 0;
}
int ftmac100_initialize (bd_t *bd)
{
struct eth_device *dev;
struct ftmac100_data *priv;
dev = malloc (sizeof *dev);
if (!dev) {
printf ("%s(): failed to allocate dev\n", __func__);
goto out;
}
/* Transmit and receive descriptors should align to 16 bytes */
priv = memalign (16, sizeof (struct ftmac100_data));
if (!priv) {
printf ("%s(): failed to allocate priv\n", __func__);
goto free_dev;
}
memset (dev, 0, sizeof (*dev));
memset (priv, 0, sizeof (*priv));
sprintf (dev->name, "FTMAC100");
dev->iobase = CONFIG_FTMAC100_BASE;
dev->init = ftmac100_init;
dev->halt = ftmac100_halt;
dev->send = ftmac100_send;
dev->recv = ftmac100_recv;
dev->priv = priv;
eth_register (dev);
return 1;
free_dev:
free (dev);
out:
return 0;
}
|
1001-study-uboot
|
drivers/net/ftmac100.c
|
C
|
gpl3
| 6,357
|
/*
* Copyright 2007, 2010 Freescale Semiconductor, Inc.
*
* Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
*
* Description:
* ULI 526x Ethernet port driver.
* Based on the Linux driver: drivers/net/tulip/uli526x.c
*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <pci.h>
#include <miiphy.h>
/* some kernel function compatible define */
#undef DEBUG
/* Board/System/Debug information/definition */
#define ULI_VENDOR_ID 0x10B9
#define ULI5261_DEVICE_ID 0x5261
#define ULI5263_DEVICE_ID 0x5263
/* ULi M5261 ID*/
#define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
/* ULi M5263 ID*/
#define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
#define ULI526X_IO_SIZE 0x100
#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
#define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
#define TX_BUF_ALLOC 0x300
#define RX_ALLOC_SIZE PKTSIZE
#define ULI526X_RESET 1
#define CR0_DEFAULT 0
#define CR6_DEFAULT 0x22200000
#define CR7_DEFAULT 0x180c1
#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
#define MAX_PACKET_SIZE 1514
#define ULI5261_MAX_MULTICAST 14
#define RX_COPY_SIZE 100
#define MAX_CHECK_PACKET 0x8000
#define ULI526X_10MHF 0
#define ULI526X_100MHF 1
#define ULI526X_10MFD 4
#define ULI526X_100MFD 5
#define ULI526X_AUTO 8
#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
/* CR9 definition: SROM/MII */
#define CR9_SROM_READ 0x4800
#define CR9_SRCS 0x1
#define CR9_SRCLK 0x2
#define CR9_CRDOUT 0x8
#define SROM_DATA_0 0x0
#define SROM_DATA_1 0x4
#define PHY_DATA_1 0x20000
#define PHY_DATA_0 0x00000
#define MDCLKH 0x10000
#define PHY_POWER_DOWN 0x800
#define SROM_V41_CODE 0x14
#define SROM_CLK_WRITE(data, ioaddr) do { \
outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
udelay(5); \
outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
udelay(5); \
outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
udelay(5); \
} while (0)
/* Structure/enum declaration */
struct tx_desc {
u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
char *tx_buf_ptr; /* Data for us */
struct tx_desc *next_tx_desc;
};
struct rx_desc {
u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
char *rx_buf_ptr; /* Data for us */
struct rx_desc *next_rx_desc;
};
struct uli526x_board_info {
u32 chip_id; /* Chip vendor/Device ID */
pci_dev_t pdev;
long ioaddr; /* I/O base address */
u32 cr0_data;
u32 cr5_data;
u32 cr6_data;
u32 cr7_data;
u32 cr15_data;
/* pointer for memory physical address */
dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
dma_addr_t first_tx_desc_dma;
dma_addr_t first_rx_desc_dma;
/* descriptor pointer */
unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
unsigned char *buf_pool_start; /* Tx buffer pool align dword */
unsigned char *desc_pool_ptr; /* descriptor pool memory */
struct tx_desc *first_tx_desc;
struct tx_desc *tx_insert_ptr;
struct tx_desc *tx_remove_ptr;
struct rx_desc *first_rx_desc;
struct rx_desc *rx_ready_ptr; /* packet come pointer */
unsigned long tx_packet_cnt; /* transmitted packet count */
u16 PHY_reg4; /* Saved Phyxcer register 4 value */
u8 media_mode; /* user specify media mode */
u8 op_mode; /* real work dedia mode */
u8 phy_addr;
/* NIC SROM data */
unsigned char srom[128];
};
enum uli526x_offsets {
DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
DCR15 = 0x78
};
enum uli526x_CR6_bits {
CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
};
/* Global variable declaration -- */
static unsigned char uli526x_media_mode = ULI526X_AUTO;
static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
__attribute__ ((aligned(32)));
static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
/* For module input parameter */
static int mode = 8;
/* function declaration -- */
static int uli526x_start_xmit(struct eth_device *dev,
volatile void *packet, int length);
static const struct ethtool_ops netdev_ethtool_ops;
static u16 read_srom_word(long, int);
static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
static void allocate_rx_buffer(struct uli526x_board_info *);
static void update_cr6(u32, unsigned long);
static u16 uli_phy_read(unsigned long, u8, u8, u32);
static u16 phy_readby_cr10(unsigned long, u8, u8);
static void uli_phy_write(unsigned long, u8, u8, u16, u32);
static void phy_writeby_cr10(unsigned long, u8, u8, u16);
static void phy_write_1bit(unsigned long, u32, u32);
static u16 phy_read_1bit(unsigned long, u32);
static int uli526x_rx_packet(struct eth_device *);
static void uli526x_free_tx_pkt(struct eth_device *,
struct uli526x_board_info *);
static void uli526x_reuse_buf(struct rx_desc *);
static void uli526x_init(struct eth_device *);
static void uli526x_set_phyxcer(struct uli526x_board_info *);
static int uli526x_init_one(struct eth_device *, bd_t *);
static void uli526x_disable(struct eth_device *);
static void set_mac_addr(struct eth_device *);
static struct pci_device_id uli526x_pci_tbl[] = {
{ ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
{ ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
{}
};
/* ULI526X network board routine */
/*
* Search ULI526X board, register it
*/
int uli526x_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
struct uli526x_board_info *db; /* board information structure */
u32 iobase;
int idx = 0;
while (1) {
/* Find PCI device */
devno = pci_find_devices(uli526x_pci_tbl, idx++);
if (devno < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("uli526x: Can not allocate memory\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "uli526x#%d", card_number);
db = (struct uli526x_board_info *)
malloc(sizeof(struct uli526x_board_info));
dev->priv = db;
db->pdev = devno;
dev->iobase = iobase;
dev->init = uli526x_init_one;
dev->halt = uli526x_disable;
dev->send = uli526x_start_xmit;
dev->recv = uli526x_rx_packet;
/* init db */
db->ioaddr = dev->iobase;
/* get chip id */
pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
#ifdef DEBUG
printf("uli526x: uli526x @0x%x\n", iobase);
printf("uli526x: chip_id%x\n", db->chip_id);
#endif
eth_register(dev);
card_number++;
pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
udelay(10 * 1000);
}
return card_number;
}
static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
{
struct uli526x_board_info *db = dev->priv;
int i;
switch (mode) {
case ULI526X_10MHF:
case ULI526X_100MHF:
case ULI526X_10MFD:
case ULI526X_100MFD:
uli526x_media_mode = mode;
break;
default:
uli526x_media_mode = ULI526X_AUTO;
break;
}
/* Allocate Tx/Rx descriptor memory */
db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
if (db->desc_pool_ptr == NULL)
return -1;
db->buf_pool_ptr = (uchar *)&buf_pool[0];
db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
if (db->buf_pool_ptr == NULL)
return -1;
db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
db->first_tx_desc_dma = db->desc_pool_dma_ptr;
db->buf_pool_start = db->buf_pool_ptr;
db->buf_pool_dma_start = db->buf_pool_dma_ptr;
#ifdef DEBUG
printf("%s(): db->ioaddr= 0x%x\n",
__FUNCTION__, db->ioaddr);
printf("%s(): media_mode= 0x%x\n",
__FUNCTION__, uli526x_media_mode);
printf("%s(): db->desc_pool_ptr= 0x%x\n",
__FUNCTION__, db->desc_pool_ptr);
printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
__FUNCTION__, db->desc_pool_dma_ptr);
printf("%s(): db->buf_pool_ptr= 0x%x\n",
__FUNCTION__, db->buf_pool_ptr);
printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
__FUNCTION__, db->buf_pool_dma_ptr);
#endif
/* read 64 word srom data */
for (i = 0; i < 64; i++)
((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
i));
/* Set Node address */
if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
/* SROM absent, so write MAC address to ID Table */
set_mac_addr(dev);
else { /*Exist SROM*/
for (i = 0; i < 6; i++)
dev->enetaddr[i] = db->srom[20 + i];
}
#ifdef DEBUG
for (i = 0; i < 6; i++)
printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
#endif
db->PHY_reg4 = 0x1e0;
/* system variable init */
db->cr6_data = CR6_DEFAULT ;
db->cr6_data |= ULI526X_TXTH_256;
db->cr0_data = CR0_DEFAULT;
uli526x_init(dev);
return 0;
}
static void uli526x_disable(struct eth_device *dev)
{
#ifdef DEBUG
printf("uli526x_disable\n");
#endif
struct uli526x_board_info *db = dev->priv;
if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
/* Reset & stop ULI526X board */
outl(ULI526X_RESET, db->ioaddr + DCR0);
udelay(5);
uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
/* reset the board */
db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
update_cr6(db->cr6_data, dev->iobase);
outl(0, dev->iobase + DCR7); /* Disable Interrupt */
outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
}
}
/* Initialize ULI526X board
* Reset ULI526X board
* Initialize TX/Rx descriptor chain structure
* Send the set-up frame
* Enable Tx/Rx machine
*/
static void uli526x_init(struct eth_device *dev)
{
struct uli526x_board_info *db = dev->priv;
u8 phy_tmp;
u16 phy_value;
u16 phy_reg_reset;
/* Reset M526x MAC controller */
outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
udelay(100);
outl(db->cr0_data, db->ioaddr + DCR0);
udelay(5);
/* Phy addr : In some boards,M5261/M5263 phy address != 1 */
db->phy_addr = 1;
db->tx_packet_cnt = 0;
for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
/* peer add */
phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
if (phy_value != 0xffff && phy_value != 0) {
db->phy_addr = phy_tmp;
break;
}
}
#ifdef DEBUG
printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
#endif
if (phy_tmp == 32)
printf("Can not find the phy address!!!");
/* Parser SROM and media mode */
db->media_mode = uli526x_media_mode;
if (!(inl(db->ioaddr + DCR12) & 0x8)) {
/* Phyxcer capability setting */
phy_reg_reset = uli_phy_read(db->ioaddr,
db->phy_addr, 0, db->chip_id);
phy_reg_reset = (phy_reg_reset | 0x8000);
uli_phy_write(db->ioaddr, db->phy_addr, 0,
phy_reg_reset, db->chip_id);
udelay(500);
/* Process Phyxcer Media Mode */
uli526x_set_phyxcer(db);
}
/* Media Mode Process */
if (!(db->media_mode & ULI526X_AUTO))
db->op_mode = db->media_mode; /* Force Mode */
/* Initialize Transmit/Receive decriptor and CR3/4 */
uli526x_descriptor_init(db, db->ioaddr);
/* Init CR6 to program M526X operation */
update_cr6(db->cr6_data, db->ioaddr);
/* Init CR7, interrupt active bit */
db->cr7_data = CR7_DEFAULT;
outl(db->cr7_data, db->ioaddr + DCR7);
/* Init CR15, Tx jabber and Rx watchdog timer */
outl(db->cr15_data, db->ioaddr + DCR15);
/* Enable ULI526X Tx/Rx function */
db->cr6_data |= CR6_RXSC | CR6_TXSC;
update_cr6(db->cr6_data, db->ioaddr);
while (!(inl(db->ioaddr + DCR12) & 0x8))
udelay(10);
}
/*
* Hardware start transmission.
* Send a packet to media from the upper layer.
*/
static int uli526x_start_xmit(struct eth_device *dev,
volatile void *packet, int length)
{
struct uli526x_board_info *db = dev->priv;
struct tx_desc *txptr;
unsigned int len = length;
/* Too large packet check */
if (len > MAX_PACKET_SIZE) {
printf(": big packet = %d\n", len);
return 0;
}
/* No Tx resource check, it never happen nromally */
if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
printf("No Tx resource %ld\n", db->tx_packet_cnt);
return 0;
}
/* Disable NIC interrupt */
outl(0, dev->iobase + DCR7);
/* transmit this packet */
txptr = db->tx_insert_ptr;
memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
/* Point to next transmit free descriptor */
db->tx_insert_ptr = txptr->next_tx_desc;
/* Transmit Packet Process */
if ((db->tx_packet_cnt < TX_DESC_CNT)) {
txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
db->tx_packet_cnt++; /* Ready to send */
outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
}
/* Got ULI526X status */
db->cr5_data = inl(db->ioaddr + DCR5);
outl(db->cr5_data, db->ioaddr + DCR5);
#ifdef TX_DEBUG
printf("%s(): length = 0x%x\n", __FUNCTION__, length);
printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
#endif
outl(db->cr7_data, dev->iobase + DCR7);
uli526x_free_tx_pkt(dev, db);
return length;
}
/*
* Free TX resource after TX complete
*/
static void uli526x_free_tx_pkt(struct eth_device *dev,
struct uli526x_board_info *db)
{
struct tx_desc *txptr;
u32 tdes0;
txptr = db->tx_remove_ptr;
while (db->tx_packet_cnt) {
tdes0 = le32_to_cpu(txptr->tdes0);
/* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
if (tdes0 & 0x80000000)
break;
/* A packet sent completed */
db->tx_packet_cnt--;
if (tdes0 != 0x7fffffff) {
#ifdef TX_DEBUG
printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
#endif
if (tdes0 & TDES0_ERR_MASK) {
if (tdes0 & 0x0002) { /* UnderRun */
if (!(db->cr6_data & CR6_SFT)) {
db->cr6_data = db->cr6_data |
CR6_SFT;
update_cr6(db->cr6_data,
db->ioaddr);
}
}
}
}
txptr = txptr->next_tx_desc;
}/* End of while */
/* Update TX remove pointer to next */
db->tx_remove_ptr = txptr;
}
/*
* Receive the come packet and pass to upper layer
*/
static int uli526x_rx_packet(struct eth_device *dev)
{
struct uli526x_board_info *db = dev->priv;
struct rx_desc *rxptr;
int rxlen = 0;
u32 rdes0;
rxptr = db->rx_ready_ptr;
rdes0 = le32_to_cpu(rxptr->rdes0);
#ifdef RX_DEBUG
printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
#endif
if (!(rdes0 & 0x80000000)) { /* packet owner check */
if ((rdes0 & 0x300) != 0x300) {
/* A packet without First/Last flag */
/* reuse this buf */
printf("A packet without First/Last flag");
uli526x_reuse_buf(rxptr);
} else {
/* A packet with First/Last flag */
rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
#ifdef RX_DEBUG
printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
#endif
/* error summary bit check */
if (rdes0 & 0x8000) {
/* This is a error packet */
printf("Error: rdes0: %x\n", rdes0);
}
if (!(rdes0 & 0x8000) ||
((db->cr6_data & CR6_PM) && (rxlen > 6))) {
#ifdef RX_DEBUG
printf("%s(): rx_skb_ptr =%x\n",
__FUNCTION__, rxptr->rx_buf_ptr);
printf("%s(): rxlen =%x\n",
__FUNCTION__, rxlen);
printf("%s(): buf addr =%x\n",
__FUNCTION__, rxptr->rx_buf_ptr);
printf("%s(): rxlen =%x\n",
__FUNCTION__, rxlen);
int i;
for (i = 0; i < 0x20; i++)
printf("%s(): data[%x] =%x\n",
__FUNCTION__, i, rxptr->rx_buf_ptr[i]);
#endif
NetReceive((uchar *)rxptr->rx_buf_ptr, rxlen);
uli526x_reuse_buf(rxptr);
} else {
/* Reuse SKB buffer when the packet is error */
printf("Reuse buffer, rdes0");
uli526x_reuse_buf(rxptr);
}
}
rxptr = rxptr->next_rx_desc;
}
db->rx_ready_ptr = rxptr;
return rxlen;
}
/*
* Reuse the RX buffer
*/
static void uli526x_reuse_buf(struct rx_desc *rxptr)
{
if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
rxptr->rdes0 = cpu_to_le32(0x80000000);
else
printf("Buffer reuse method error");
}
/*
* Initialize transmit/Receive descriptor
* Using Chain structure, and allocate Tx/Rx buffer
*/
static void uli526x_descriptor_init(struct uli526x_board_info *db,
unsigned long ioaddr)
{
struct tx_desc *tmp_tx;
struct rx_desc *tmp_rx;
unsigned char *tmp_buf;
dma_addr_t tmp_tx_dma, tmp_rx_dma;
dma_addr_t tmp_buf_dma;
int i;
/* tx descriptor start pointer */
db->tx_insert_ptr = db->first_tx_desc;
db->tx_remove_ptr = db->first_tx_desc;
outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
/* rx descriptor start pointer */
db->first_rx_desc = (void *)db->first_tx_desc +
sizeof(struct tx_desc) * TX_DESC_CNT;
db->first_rx_desc_dma = db->first_tx_desc_dma +
sizeof(struct tx_desc) * TX_DESC_CNT;
db->rx_ready_ptr = db->first_rx_desc;
outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
#ifdef DEBUG
printf("%s(): db->first_tx_desc= 0x%x\n",
__FUNCTION__, db->first_tx_desc);
printf("%s(): db->first_rx_desc_dma= 0x%x\n",
__FUNCTION__, db->first_rx_desc_dma);
#endif
/* Init Transmit chain */
tmp_buf = db->buf_pool_start;
tmp_buf_dma = db->buf_pool_dma_start;
tmp_tx_dma = db->first_tx_desc_dma;
for (tmp_tx = db->first_tx_desc, i = 0;
i < TX_DESC_CNT; i++, tmp_tx++) {
tmp_tx->tx_buf_ptr = (char *)tmp_buf;
tmp_tx->tdes0 = cpu_to_le32(0);
tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
tmp_tx_dma += sizeof(struct tx_desc);
tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
tmp_tx->next_tx_desc = tmp_tx + 1;
tmp_buf = tmp_buf + TX_BUF_ALLOC;
tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
}
(--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
tmp_tx->next_tx_desc = db->first_tx_desc;
/* Init Receive descriptor chain */
tmp_rx_dma = db->first_rx_desc_dma;
for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
i++, tmp_rx++) {
tmp_rx->rdes0 = cpu_to_le32(0);
tmp_rx->rdes1 = cpu_to_le32(0x01000600);
tmp_rx_dma += sizeof(struct rx_desc);
tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
tmp_rx->next_rx_desc = tmp_rx + 1;
}
(--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
tmp_rx->next_rx_desc = db->first_rx_desc;
/* pre-allocate Rx buffer */
allocate_rx_buffer(db);
}
/*
* Update CR6 value
* Firstly stop ULI526X, then written value and start
*/
static void update_cr6(u32 cr6_data, unsigned long ioaddr)
{
outl(cr6_data, ioaddr + DCR6);
udelay(5);
}
/*
* Allocate rx buffer,
*/
static void allocate_rx_buffer(struct uli526x_board_info *db)
{
int index;
struct rx_desc *rxptr;
rxptr = db->first_rx_desc;
u32 addr;
for (index = 0; index < RX_DESC_CNT; index++) {
addr = (u32)NetRxPackets[index];
addr += (16 - (addr & 15));
rxptr->rx_buf_ptr = (char *) addr;
rxptr->rdes2 = cpu_to_le32(addr);
rxptr->rdes0 = cpu_to_le32(0x80000000);
#ifdef DEBUG
printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
printf("%s(): rxptr buf address = 0x%x\n", \
__FUNCTION__, rxptr->rx_buf_ptr);
printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
#endif
rxptr = rxptr->next_rx_desc;
}
}
/*
* Read one word data from the serial ROM
*/
static u16 read_srom_word(long ioaddr, int offset)
{
int i;
u16 srom_data = 0;
long cr9_ioaddr = ioaddr + DCR9;
outl(CR9_SROM_READ, cr9_ioaddr);
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
/* Send the Read Command 110b */
SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
/* Send the offset */
for (i = 5; i >= 0; i--) {
srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
SROM_CLK_WRITE(srom_data, cr9_ioaddr);
}
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
for (i = 16; i > 0; i--) {
outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
udelay(5);
srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
? 1 : 0);
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
udelay(5);
}
outl(CR9_SROM_READ, cr9_ioaddr);
return srom_data;
}
/*
* Set 10/100 phyxcer capability
* AUTO mode : phyxcer register4 is NIC capability
* Force mode: phyxcer register4 is the force media
*/
static void uli526x_set_phyxcer(struct uli526x_board_info *db)
{
u16 phy_reg;
/* Phyxcer capability setting */
phy_reg = uli_phy_read(db->ioaddr,
db->phy_addr, 4, db->chip_id) & ~0x01e0;
if (db->media_mode & ULI526X_AUTO) {
/* AUTO Mode */
phy_reg |= db->PHY_reg4;
} else {
/* Force Mode */
switch (db->media_mode) {
case ULI526X_10MHF: phy_reg |= 0x20; break;
case ULI526X_10MFD: phy_reg |= 0x40; break;
case ULI526X_100MHF: phy_reg |= 0x80; break;
case ULI526X_100MFD: phy_reg |= 0x100; break;
}
}
/* Write new capability to Phyxcer Reg4 */
if (!(phy_reg & 0x01e0)) {
phy_reg |= db->PHY_reg4;
db->media_mode |= ULI526X_AUTO;
}
uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
/* Restart Auto-Negotiation */
uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
udelay(50);
}
/*
* Write a word to Phy register
*/
static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
u16 phy_data, u32 chip_id)
{
u16 i;
unsigned long ioaddr;
if (chip_id == PCI_ULI5263_ID) {
phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
return;
}
/* M5261/M5263 Chip */
ioaddr = iobase + DCR9;
/* Send 33 synchronization clock to Phy controller */
for (i = 0; i < 35; i++)
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send start command(01) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send write command(01) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, phy_addr & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
/* Send register address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, offset & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
/* written trasnition */
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
/* Write a word data to PHY controller */
for (i = 0x8000; i > 0; i >>= 1)
phy_write_1bit(ioaddr, phy_data & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
}
/*
* Read a word data from phy register
*/
static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
u32 chip_id)
{
int i;
u16 phy_data;
unsigned long ioaddr;
if (chip_id == PCI_ULI5263_ID)
return phy_readby_cr10(iobase, phy_addr, offset);
/* M5261/M5263 Chip */
ioaddr = iobase + DCR9;
/* Send 33 synchronization clock to Phy controller */
for (i = 0; i < 35; i++)
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send start command(01) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
/* Send read command(10) to Phy */
phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
/* Send Phy address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, phy_addr & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
/* Send register address */
for (i = 0x10; i > 0; i = i >> 1)
phy_write_1bit(ioaddr, offset & i ?
PHY_DATA_1 : PHY_DATA_0, chip_id);
/* Skip transition state */
phy_read_1bit(ioaddr, chip_id);
/* read 16bit data */
for (phy_data = 0, i = 0; i < 16; i++) {
phy_data <<= 1;
phy_data |= phy_read_1bit(ioaddr, chip_id);
}
return phy_data;
}
static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
{
unsigned long ioaddr, cr10_value;
ioaddr = iobase + DCR10;
cr10_value = phy_addr;
cr10_value = (cr10_value<<5) + offset;
cr10_value = (cr10_value<<16) + 0x08000000;
outl(cr10_value, ioaddr);
udelay(1);
while (1) {
cr10_value = inl(ioaddr);
if (cr10_value & 0x10000000)
break;
}
return (cr10_value&0x0ffff);
}
static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
u8 offset, u16 phy_data)
{
unsigned long ioaddr, cr10_value;
ioaddr = iobase + DCR10;
cr10_value = phy_addr;
cr10_value = (cr10_value<<5) + offset;
cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
outl(cr10_value, ioaddr);
udelay(1);
}
/*
* Write one bit data to Phy Controller
*/
static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
{
outl(phy_data , ioaddr); /* MII Clock Low */
udelay(1);
outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
udelay(1);
outl(phy_data , ioaddr); /* MII Clock Low */
udelay(1);
}
/*
* Read one bit phy data from PHY controller
*/
static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
{
u16 phy_data;
outl(0x50000 , ioaddr);
udelay(1);
phy_data = (inl(ioaddr) >> 19) & 0x1;
outl(0x40000 , ioaddr);
udelay(1);
return phy_data;
}
/*
* Set MAC address to ID Table
*/
static void set_mac_addr(struct eth_device *dev)
{
int i;
u16 addr;
struct uli526x_board_info *db = dev->priv;
outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
/* Reset dianostic pointer port */
outl(0x1c0, db->ioaddr + DCR13);
outl(0, db->ioaddr + DCR14); /* Clear reset port */
outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
outl(0, db->ioaddr + DCR14); /* Clear reset port */
outl(0, db->ioaddr + DCR13); /* Clear CR13 */
/* Select ID Table access port */
outl(0x1b0, db->ioaddr + DCR13);
/* Read MAC address from CR14 */
for (i = 0; i < 3; i++) {
addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
outl(addr, db->ioaddr + DCR14);
}
/* write end */
outl(0, db->ioaddr + DCR13); /* Clear CR13 */
outl(0, db->ioaddr + DCR0); /* Clear CR0 */
udelay(10);
return;
}
|
1001-study-uboot
|
drivers/net/uli526x.c
|
C
|
gpl3
| 26,421
|
/*
* Faraday FTGMAC100 Ethernet
*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* (C) Copyright 2010 Andes Technology
* Macpaul Lin <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include <linux/mii.h>
#include "ftgmac100.h"
#define ETH_ZLEN 60
/* RBSR - hw default init value is also 0x640 */
#define RBSR_DEFAULT_VALUE 0x640
/* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
#define PKTBUFSTX 4 /* must be power of 2 */
struct ftgmac100_data {
struct ftgmac100_txdes txdes[PKTBUFSTX];
struct ftgmac100_rxdes rxdes[PKTBUFSRX];
int tx_index;
int rx_index;
int phy_addr;
};
/*
* struct mii_bus functions
*/
static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
int regnum)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
int phycr;
int i;
phycr = readl(&ftgmac100->phycr);
/* preserve MDC cycle threshold */
phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
| FTGMAC100_PHYCR_REGAD(regnum)
| FTGMAC100_PHYCR_MIIRD;
writel(phycr, &ftgmac100->phycr);
for (i = 0; i < 10; i++) {
phycr = readl(&ftgmac100->phycr);
if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
int data;
data = readl(&ftgmac100->phydata);
return FTGMAC100_PHYDATA_MIIRDATA(data);
}
mdelay(10);
}
debug("mdio read timed out\n");
return -1;
}
static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
int regnum, u16 value)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
int phycr;
int data;
int i;
phycr = readl(&ftgmac100->phycr);
/* preserve MDC cycle threshold */
phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
| FTGMAC100_PHYCR_REGAD(regnum)
| FTGMAC100_PHYCR_MIIWR;
data = FTGMAC100_PHYDATA_MIIWDATA(value);
writel(data, &ftgmac100->phydata);
writel(phycr, &ftgmac100->phycr);
for (i = 0; i < 10; i++) {
phycr = readl(&ftgmac100->phycr);
if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0) {
debug("(phycr & FTGMAC100_PHYCR_MIIWR) == 0: " \
"phy_addr: %x\n", phy_addr);
return 0;
}
mdelay(1);
}
debug("mdio write timed out\n");
return -1;
}
int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
{
*value = ftgmac100_mdiobus_read(dev , addr, reg);
if (*value == -1)
return -1;
return 0;
}
int ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
{
if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
return -1;
return 0;
}
static int ftgmac100_phy_reset(struct eth_device *dev)
{
struct ftgmac100_data *priv = dev->priv;
int i;
u16 status, adv;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
printf("%s: Starting autonegotiation...\n", dev->name);
ftgmac100_phy_write(dev, priv->phy_addr,
MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
for (i = 0; i < 100000 / 100; i++) {
ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
if (status & BMSR_ANEGCOMPLETE)
break;
mdelay(1);
}
if (status & BMSR_ANEGCOMPLETE) {
printf("%s: Autonegotiation complete\n", dev->name);
} else {
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
dev->name, status);
return 0;
}
return 1;
}
static int ftgmac100_phy_init(struct eth_device *dev)
{
struct ftgmac100_data *priv = dev->priv;
int phy_addr;
u16 phy_id, status, adv, lpa, stat_ge;
int media, speed, duplex;
int i;
/* Check if the PHY is up to snuff... */
for (phy_addr = 0; phy_addr < CONFIG_PHY_MAX_ADDR; phy_addr++) {
ftgmac100_phy_read(dev, phy_addr, MII_PHYSID1, &phy_id);
/*
* When it is unable to found PHY,
* the interface usually return 0xffff or 0x0000
*/
if (phy_id != 0xffff && phy_id != 0x0) {
printf("%s: found PHY at 0x%02x\n",
dev->name, phy_addr);
priv->phy_addr = phy_addr;
break;
}
}
if (phy_id == 0xffff || phy_id == 0x0) {
printf("%s: no PHY present\n", dev->name);
return 0;
}
ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &status);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
ftgmac100_phy_reset(dev);
for (i = 0; i < 100000 / 100; i++) {
ftgmac100_phy_read(dev, priv->phy_addr,
MII_BMSR, &status);
if (status & BMSR_LSTATUS)
break;
udelay(100);
}
}
if (!(status & BMSR_LSTATUS)) {
printf("%s: link down\n", dev->name);
return 0;
}
#ifdef CONFIG_FTGMAC100_EGIGA
/* 1000 Base-T Status Register */
ftgmac100_phy_read(dev, priv->phy_addr,
MII_STAT1000, &stat_ge);
speed = (stat_ge & (LPA_1000FULL | LPA_1000HALF)
? 1 : 0);
duplex = ((stat_ge & LPA_1000FULL)
? 1 : 0);
if (speed) { /* Speed is 1000 */
printf("%s: link up, 1000bps %s-duplex\n",
dev->name, duplex ? "full" : "half");
return 0;
}
#endif
ftgmac100_phy_read(dev, priv->phy_addr, MII_ADVERTISE, &adv);
ftgmac100_phy_read(dev, priv->phy_addr, MII_LPA, &lpa);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 1 : 0);
duplex = (media & ADVERTISE_FULL) ? 1 : 0;
printf("%s: link up, %sMbps %s-duplex\n",
dev->name, speed ? "100" : "10", duplex ? "full" : "half");
return 1;
}
static int ftgmac100_update_link_speed(struct eth_device *dev)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
struct ftgmac100_data *priv = dev->priv;
unsigned short stat_fe;
unsigned short stat_ge;
unsigned int maccr;
#ifdef CONFIG_FTGMAC100_EGIGA
/* 1000 Base-T Status Register */
ftgmac100_phy_read(dev, priv->phy_addr, MII_STAT1000, &stat_ge);
#endif
ftgmac100_phy_read(dev, priv->phy_addr, MII_BMSR, &stat_fe);
if (!(stat_fe & BMSR_LSTATUS)) /* link status up? */
return 0;
/* read MAC control register and clear related bits */
maccr = readl(&ftgmac100->maccr) &
~(FTGMAC100_MACCR_GIGA_MODE |
FTGMAC100_MACCR_FAST_MODE |
FTGMAC100_MACCR_FULLDUP);
#ifdef CONFIG_FTGMAC100_EGIGA
if (stat_ge & LPA_1000FULL) {
/* set gmac for 1000BaseTX and Full Duplex */
maccr |= FTGMAC100_MACCR_GIGA_MODE | FTGMAC100_MACCR_FULLDUP;
}
if (stat_ge & LPA_1000HALF) {
/* set gmac for 1000BaseTX and Half Duplex */
maccr |= FTGMAC100_MACCR_GIGA_MODE;
}
#endif
if (stat_fe & BMSR_100FULL) {
/* set MII for 100BaseTX and Full Duplex */
maccr |= FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_FULLDUP;
}
if (stat_fe & BMSR_10FULL) {
/* set MII for 10BaseT and Full Duplex */
maccr |= FTGMAC100_MACCR_FULLDUP;
}
if (stat_fe & BMSR_100HALF) {
/* set MII for 100BaseTX and Half Duplex */
maccr |= FTGMAC100_MACCR_FAST_MODE;
}
if (stat_fe & BMSR_10HALF) {
/* set MII for 10BaseT and Half Duplex */
/* we have already clear these bits, do nothing */
;
}
/* update MII config into maccr */
writel(maccr, &ftgmac100->maccr);
return 1;
}
/*
* Reset MAC
*/
static void ftgmac100_reset(struct eth_device *dev)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
debug("%s()\n", __func__);
writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
;
}
/*
* Set MAC address
*/
static void ftgmac100_set_mac(struct eth_device *dev,
const unsigned char *mac)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
unsigned int maddr = mac[0] << 8 | mac[1];
unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
debug("%s(%x %x)\n", __func__, maddr, laddr);
writel(maddr, &ftgmac100->mac_madr);
writel(laddr, &ftgmac100->mac_ladr);
}
static void ftgmac100_set_mac_from_env(struct eth_device *dev)
{
eth_getenv_enetaddr("ethaddr", dev->enetaddr);
ftgmac100_set_mac(dev, dev->enetaddr);
}
/*
* disable transmitter, receiver
*/
static void ftgmac100_halt(struct eth_device *dev)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
debug("%s()\n", __func__);
writel(0, &ftgmac100->maccr);
}
static int ftgmac100_init(struct eth_device *dev, bd_t *bd)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
struct ftgmac100_data *priv = dev->priv;
struct ftgmac100_txdes *txdes = priv->txdes;
struct ftgmac100_rxdes *rxdes = priv->rxdes;
unsigned int maccr;
int i;
debug("%s()\n", __func__);
/* set the ethernet address */
ftgmac100_set_mac_from_env(dev);
/* disable all interrupts */
writel(0, &ftgmac100->ier);
/* initialize descriptors */
priv->tx_index = 0;
priv->rx_index = 0;
txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
for (i = 0; i < PKTBUFSTX; i++) {
/* TXBUF_BADR */
txdes[i].txdes3 = 0;
txdes[i].txdes1 = 0;
}
for (i = 0; i < PKTBUFSRX; i++) {
/* RXBUF_BADR */
rxdes[i].rxdes3 = (unsigned int)NetRxPackets[i];
rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
}
/* transmit ring */
writel((unsigned int)txdes, &ftgmac100->txr_badr);
/* receive ring */
writel((unsigned int)rxdes, &ftgmac100->rxr_badr);
/* poll receive descriptor automatically */
writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
/* config receive buffer size register */
writel(FTGMAC100_RBSR_SIZE(RBSR_DEFAULT_VALUE), &ftgmac100->rbsr);
/* enable transmitter, receiver */
maccr = FTGMAC100_MACCR_TXMAC_EN |
FTGMAC100_MACCR_RXMAC_EN |
FTGMAC100_MACCR_TXDMA_EN |
FTGMAC100_MACCR_RXDMA_EN |
FTGMAC100_MACCR_CRC_APD |
FTGMAC100_MACCR_FULLDUP |
FTGMAC100_MACCR_RX_RUNT |
FTGMAC100_MACCR_RX_BROADPKT;
writel(maccr, &ftgmac100->maccr);
if (!ftgmac100_phy_init(dev)) {
if (!ftgmac100_update_link_speed(dev))
return -1;
}
return 0;
}
/*
* Get a data block via Ethernet
*/
static int ftgmac100_recv(struct eth_device *dev)
{
struct ftgmac100_data *priv = dev->priv;
struct ftgmac100_rxdes *curr_des;
unsigned short rxlen;
curr_des = &priv->rxdes[priv->rx_index];
if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
return -1;
if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
FTGMAC100_RXDES0_CRC_ERR |
FTGMAC100_RXDES0_FTL |
FTGMAC100_RXDES0_RUNT |
FTGMAC100_RXDES0_RX_ODD_NB)) {
return -1;
}
rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
debug("%s(): RX buffer %d, %x received\n",
__func__, priv->rx_index, rxlen);
/* pass the packet up to the protocol layers. */
NetReceive((void *)curr_des->rxdes3, rxlen);
/* release buffer to DMA */
curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
return 0;
}
/*
* Send a data block via Ethernet
*/
static int
ftgmac100_send(struct eth_device *dev, void *packet, int length)
{
struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
struct ftgmac100_data *priv = dev->priv;
struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
int start;
if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
debug("%s(): no TX descriptor available\n", __func__);
return -1;
}
debug("%s(%x, %x)\n", __func__, (int)packet, length);
length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
/* initiate a transmit sequence */
curr_des->txdes3 = (unsigned int)packet; /* TXBUF_BADR */
/* only one descriptor on TXBUF */
curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
FTGMAC100_TXDES0_LTS |
FTGMAC100_TXDES0_TXBUF_SIZE(length) |
FTGMAC100_TXDES0_TXDMA_OWN ;
/* start transmit */
writel(1, &ftgmac100->txpd);
/* wait for transfer to succeed */
start = get_timer(0);
while (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
if (get_timer(0) >= 5) {
debug("%s(): timed out\n", __func__);
return -1;
}
}
debug("%s(): packet sent\n", __func__);
priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
return 0;
}
int ftgmac100_initialize(bd_t *bd)
{
struct eth_device *dev;
struct ftgmac100_data *priv;
dev = malloc(sizeof *dev);
if (!dev) {
printf("%s(): failed to allocate dev\n", __func__);
goto out;
}
/* Transmit and receive descriptors should align to 16 bytes */
priv = memalign(16, sizeof(struct ftgmac100_data));
if (!priv) {
printf("%s(): failed to allocate priv\n", __func__);
goto free_dev;
}
memset(dev, 0, sizeof(*dev));
memset(priv, 0, sizeof(*priv));
sprintf(dev->name, "FTGMAC100");
dev->iobase = CONFIG_FTGMAC100_BASE;
dev->init = ftgmac100_init;
dev->halt = ftgmac100_halt;
dev->send = ftgmac100_send;
dev->recv = ftgmac100_recv;
dev->priv = priv;
eth_register(dev);
ftgmac100_reset(dev);
return 1;
free_dev:
free(dev);
out:
return 0;
}
|
1001-study-uboot
|
drivers/net/ftgmac100.c
|
C
|
gpl3
| 13,297
|
/*
* (C) Copyright 2007-2009 Michal Simek
* (C) Copyright 2003 Xilinx Inc.
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <net.h>
#include <config.h>
#include <malloc.h>
#include <asm/io.h>
#undef DEBUG
#define ENET_ADDR_LENGTH 6
/* EmacLite constants */
#define XEL_BUFFER_OFFSET 0x0800 /* Next buffer's offset */
#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */
#define XEL_TSR_OFFSET 0x07FC /* Tx status */
#define XEL_RSR_OFFSET 0x17FC /* Rx status */
#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */
/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
/* Buffer is active, SW bit only */
#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK 0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
/* Transmit packet length upper byte */
#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
/* Transmit packet length lower byte */
#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
/* Recv complete */
#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK 0x00000008UL
struct xemaclite {
u32 nexttxbuffertouse; /* Next TX buffer to write to */
u32 nextrxbuffertouse; /* Next RX buffer to read from */
u32 txpp; /* TX ping pong buffer */
u32 rxpp; /* RX ping pong buffer */
};
static u32 etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
{
u32 i;
u32 alignbuffer;
u32 *to32ptr;
u32 *from32ptr;
u8 *to8ptr;
u8 *from8ptr;
from32ptr = (u32 *) srcptr;
/* Word aligned buffer, no correction needed. */
to32ptr = (u32 *) destptr;
while (bytecount > 3) {
*to32ptr++ = *from32ptr++;
bytecount -= 4;
}
to8ptr = (u8 *) to32ptr;
alignbuffer = *from32ptr++;
from8ptr = (u8 *) &alignbuffer;
for (i = 0; i < bytecount; i++)
*to8ptr++ = *from8ptr++;
}
static void xemaclite_alignedwrite(void *srcptr, u32 destptr, u32 bytecount)
{
u32 i;
u32 alignbuffer;
u32 *to32ptr = (u32 *) destptr;
u32 *from32ptr;
u8 *to8ptr;
u8 *from8ptr;
from32ptr = (u32 *) srcptr;
while (bytecount > 3) {
*to32ptr++ = *from32ptr++;
bytecount -= 4;
}
alignbuffer = 0;
to8ptr = (u8 *) &alignbuffer;
from8ptr = (u8 *) from32ptr;
for (i = 0; i < bytecount; i++)
*to8ptr++ = *from8ptr++;
*to32ptr++ = alignbuffer;
}
static void emaclite_halt(struct eth_device *dev)
{
debug("eth_halt\n");
}
static int emaclite_init(struct eth_device *dev, bd_t *bis)
{
struct xemaclite *emaclite = dev->priv;
debug("EmacLite Initialization Started\n");
/*
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
/* Copy MAC address */
xemaclite_alignedwrite(dev->enetaddr, dev->iobase, ENET_ADDR_LENGTH);
/* Set the length */
out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
/* Update the MAC address in the EMAC Lite */
out_be32 (dev->iobase + XEL_TSR_OFFSET, XEL_TSR_PROG_MAC_ADDR);
/* Wait for EMAC Lite to finish with the MAC address update */
while ((in_be32 (dev->iobase + XEL_TSR_OFFSET) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
if (emaclite->txpp) {
/* The same operation with PONG TX */
out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET, 0);
xemaclite_alignedwrite(dev->enetaddr, dev->iobase +
XEL_BUFFER_OFFSET, ENET_ADDR_LENGTH);
out_be32 (dev->iobase + XEL_TPLR_OFFSET, ENET_ADDR_LENGTH);
out_be32 (dev->iobase + XEL_TSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_TSR_PROG_MAC_ADDR);
while ((in_be32 (dev->iobase + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET) & XEL_TSR_PROG_MAC_ADDR) != 0)
;
}
/*
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
out_be32 (dev->iobase + XEL_RSR_OFFSET, XEL_RSR_RECV_IE_MASK);
if (emaclite->rxpp)
out_be32 (dev->iobase + XEL_RSR_OFFSET + XEL_BUFFER_OFFSET,
XEL_RSR_RECV_IE_MASK);
debug("EmacLite Initialization complete\n");
return 0;
}
static int xemaclite_txbufferavailable(struct eth_device *dev)
{
u32 reg;
u32 txpingbusy;
u32 txpongbusy;
struct xemaclite *emaclite = dev->priv;
/*
* Read the other buffer register
* and determine if the other buffer is available
*/
reg = in_be32 (dev->iobase +
emaclite->nexttxbuffertouse + 0);
txpingbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
reg = in_be32 (dev->iobase +
(emaclite->nexttxbuffertouse ^ XEL_TSR_OFFSET) + 0);
txpongbusy = ((reg & XEL_TSR_XMIT_BUSY_MASK) ==
XEL_TSR_XMIT_BUSY_MASK);
return !(txpingbusy && txpongbusy);
}
static int emaclite_send(struct eth_device *dev, volatile void *ptr, int len)
{
u32 reg;
u32 baseaddress;
struct xemaclite *emaclite = dev->priv;
u32 maxtry = 1000;
if (len > PKTSIZE)
len = PKTSIZE;
while (!xemaclite_txbufferavailable(dev) && maxtry) {
udelay(10);
maxtry--;
}
if (!maxtry) {
printf("Error: Timeout waiting for ethernet TX buffer\n");
/* Restart PING TX */
out_be32 (dev->iobase + XEL_TSR_OFFSET, 0);
if (emaclite->txpp) {
out_be32 (dev->iobase + XEL_TSR_OFFSET +
XEL_BUFFER_OFFSET, 0);
}
return -1;
}
/* Determine the expected TX buffer address */
baseaddress = (dev->iobase + emaclite->nexttxbuffertouse);
/* Determine if the expected buffer address is empty */
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
if (emaclite->txpp)
emaclite->nexttxbuffertouse ^= XEL_BUFFER_OFFSET;
debug("Send packet from 0x%x\n", baseaddress);
/* Write the frame to the buffer */
xemaclite_alignedwrite((void *) ptr, baseaddress, len);
out_be32 (baseaddress + XEL_TPLR_OFFSET,(len &
(XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO)));
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
reg |= XEL_TSR_XMIT_BUSY_MASK;
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
return 0;
}
if (emaclite->txpp) {
/* Switch to second buffer */
baseaddress ^= XEL_BUFFER_OFFSET;
/* Determine if the expected buffer address is empty */
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
if (((reg & XEL_TSR_XMIT_BUSY_MASK) == 0)
&& ((in_be32 ((baseaddress) + XEL_TSR_OFFSET)
& XEL_TSR_XMIT_ACTIVE_MASK) == 0)) {
debug("Send packet from 0x%x\n", baseaddress);
/* Write the frame to the buffer */
xemaclite_alignedwrite((void *) ptr, baseaddress, len);
out_be32 (baseaddress + XEL_TPLR_OFFSET, (len &
(XEL_TPLR_LENGTH_MASK_HI |
XEL_TPLR_LENGTH_MASK_LO)));
reg = in_be32 (baseaddress + XEL_TSR_OFFSET);
reg |= XEL_TSR_XMIT_BUSY_MASK;
if ((reg & XEL_TSR_XMIT_IE_MASK) != 0)
reg |= XEL_TSR_XMIT_ACTIVE_MASK;
out_be32 (baseaddress + XEL_TSR_OFFSET, reg);
return 0;
}
}
puts("Error while sending frame\n");
return -1;
}
static int emaclite_recv(struct eth_device *dev)
{
u32 length;
u32 reg;
u32 baseaddress;
struct xemaclite *emaclite = dev->priv;
baseaddress = dev->iobase + emaclite->nextrxbuffertouse;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
debug("Testing data at address 0x%x\n", baseaddress);
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
if (emaclite->rxpp)
emaclite->nextrxbuffertouse ^= XEL_BUFFER_OFFSET;
} else {
if (!emaclite->rxpp) {
debug("No data was available - address 0x%x\n",
baseaddress);
return 0;
} else {
baseaddress ^= XEL_BUFFER_OFFSET;
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
if ((reg & XEL_RSR_RECV_DONE_MASK) !=
XEL_RSR_RECV_DONE_MASK) {
debug("No data was available - address 0x%x\n",
baseaddress);
return 0;
}
}
}
/* Get the length of the frame that arrived */
switch(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET + 0xC))) &
0xFFFF0000 ) >> 16) {
case 0x806:
length = 42 + 20; /* FIXME size of ARP */
debug("ARP Packet\n");
break;
case 0x800:
length = 14 + 14 +
(((ntohl(in_be32 (baseaddress + XEL_RXBUFF_OFFSET +
0x10))) & 0xFFFF0000) >> 16);
/* FIXME size of IP packet */
debug ("IP Packet\n");
break;
default:
debug("Other Packet\n");
length = PKTSIZE;
break;
}
xemaclite_alignedread((u32 *) (baseaddress + XEL_RXBUFF_OFFSET),
etherrxbuff, length);
/* Acknowledge the frame */
reg = in_be32 (baseaddress + XEL_RSR_OFFSET);
reg &= ~XEL_RSR_RECV_DONE_MASK;
out_be32 (baseaddress + XEL_RSR_OFFSET, reg);
debug("Packet receive from 0x%x, length %dB\n", baseaddress, length);
NetReceive((uchar *) etherrxbuff, length);
return length;
}
int xilinx_emaclite_initialize(bd_t *bis, unsigned long base_addr,
int txpp, int rxpp)
{
struct eth_device *dev;
struct xemaclite *emaclite;
dev = calloc(1, sizeof(*dev));
if (dev == NULL)
return -1;
emaclite = calloc(1, sizeof(struct xemaclite));
if (emaclite == NULL) {
free(dev);
return -1;
}
dev->priv = emaclite;
emaclite->txpp = txpp;
emaclite->rxpp = rxpp;
sprintf(dev->name, "Xelite.%lx", base_addr);
dev->iobase = base_addr;
dev->init = emaclite_init;
dev->halt = emaclite_halt;
dev->send = emaclite_send;
dev->recv = emaclite_recv;
eth_register(dev);
return 1;
}
|
1001-study-uboot
|
drivers/net/xilinx_emaclite.c
|
C
|
gpl3
| 10,190
|
/*
* Altera 10/100/1000 triple speed ethernet mac driver
*
* Copyright (C) 2008 Altera Corporation.
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <asm/cache.h>
#include <asm/dma-mapping.h>
#include <miiphy.h>
#include "altera_tse.h"
/* sgdma debug - print descriptor */
static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc)
{
debug("SGDMA DEBUG :\n");
debug("desc->source : 0x%x \n", (unsigned int)desc->source);
debug("desc->destination : 0x%x \n", (unsigned int)desc->destination);
debug("desc->next : 0x%x \n", (unsigned int)desc->next);
debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad);
debug("desc->destination_pad : 0x%x \n",
(unsigned int)desc->destination_pad);
debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad);
debug("desc->bytes_to_transfer : 0x%x \n",
(unsigned int)desc->bytes_to_transfer);
debug("desc->actual_bytes_transferred : 0x%x \n",
(unsigned int)desc->actual_bytes_transferred);
debug("desc->descriptor_status : 0x%x \n",
(unsigned int)desc->descriptor_status);
debug("desc->descriptor_control : 0x%x \n",
(unsigned int)desc->descriptor_control);
}
/* This is a generic routine that the SGDMA mode-specific routines
* call to populate a descriptor.
* arg1 :pointer to first SGDMA descriptor.
* arg2 :pointer to next SGDMA descriptor.
* arg3 :Address to where data to be written.
* arg4 :Address from where data to be read.
* arg5 :no of byte to transaction.
* arg6 :variable indicating to generate start of packet or not
* arg7 :read fixed
* arg8 :write fixed
* arg9 :read burst
* arg10 :write burst
* arg11 :atlantic_channel number
*/
static void alt_sgdma_construct_descriptor_burst(
volatile struct alt_sgdma_descriptor *desc,
volatile struct alt_sgdma_descriptor *next,
unsigned int *read_addr,
unsigned int *write_addr,
unsigned short length_or_eop,
int generate_eop,
int read_fixed,
int write_fixed_or_sop,
int read_burst,
int write_burst,
unsigned char atlantic_channel)
{
/*
* Mark the "next" descriptor as "not" owned by hardware. This prevents
* The SGDMA controller from continuing to process the chain. This is
* done as a single IO write to bypass cache, without flushing
* the entire descriptor, since only the 8-bit descriptor status must
* be flushed.
*/
if (!next)
debug("Next descriptor not defined!!\n");
next->descriptor_control = (next->descriptor_control &
~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK);
desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF);
desc->destination =
(unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF);
desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF);
desc->source_pad = 0x0;
desc->destination_pad = 0x0;
desc->next_pad = 0x0;
desc->bytes_to_transfer = length_or_eop;
desc->actual_bytes_transferred = 0;
desc->descriptor_status = 0x0;
/* SGDMA burst not currently supported */
desc->read_burst = 0;
desc->write_burst = 0;
/*
* Set the descriptor control block as follows:
* - Set "owned by hardware" bit
* - Optionally set "generate EOP" bit
* - Optionally set the "read from fixed address" bit
* - Optionally set the "write to fixed address bit (which serves
* serves as a "generate SOP" control bit in memory-to-stream mode).
* - Set the 4-bit atlantic channel, if specified
*
* Note this step is performed after all other descriptor information
* has been filled out so that, if the controller already happens to be
* pointing at this descriptor, it will not run (via the "owned by
* hardware" bit) until all other descriptor has been set up.
*/
desc->descriptor_control =
((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) |
(generate_eop ?
ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) |
(read_fixed ?
ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) |
(write_fixed_or_sop ?
ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) |
(atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0)
);
}
static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev,
volatile struct alt_sgdma_descriptor *desc)
{
unsigned int status;
int counter = 0;
/* Wait for any pending transfers to complete */
alt_sgdma_print_desc(desc);
status = dev->status;
counter = 0;
while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
break;
}
if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
debug("Timeout waiting sgdma in do sync!\n");
/*
* Clear any (previous) status register information
* that might occlude our error checking later.
*/
dev->status = 0xFF;
/* Point the controller at the descriptor */
dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF;
debug("next desc in sgdma 0x%x\n",
(unsigned int)dev->next_descriptor_pointer);
/*
* Set up SGDMA controller to:
* - Disable interrupt generation
* - Run once a valid descriptor is written to controller
* - Stop on an error with any particular descriptor
*/
dev->control = (ALT_SGDMA_CONTROL_RUN_MSK |
ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK);
/* Wait for the descriptor (chain) to complete */
status = dev->status;
debug("wait for sgdma....");
while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK)
;
debug("done\n");
/* Clear Run */
dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK));
/* Get & clear status register contents */
status = dev->status;
dev->status = 0xFF;
/* we really should check if the transfer completes properly */
debug("tx sgdma status = 0x%x", status);
return 0;
}
static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev,
volatile struct alt_sgdma_descriptor *desc)
{
unsigned int status;
int counter = 0;
/* Wait for any pending transfers to complete */
alt_sgdma_print_desc(desc);
status = dev->status;
counter = 0;
while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) {
if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
break;
}
if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
debug("Timeout waiting sgdma in do async!\n");
/*
* Clear the RUN bit in the control register. This is needed
* to restart the SGDMA engine later on.
*/
dev->control = 0;
/*
* Clear any (previous) status register information
* that might occlude our error checking later.
*/
dev->status = 0xFF;
/* Point the controller at the descriptor */
dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF;
/*
* Set up SGDMA controller to:
* - Disable interrupt generation
* - Run once a valid descriptor is written to controller
* - Stop on an error with any particular descriptor
*/
dev->control = (ALT_SGDMA_CONTROL_RUN_MSK |
ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK);
/* we really should check if the transfer completes properly */
return 0;
}
/* u-boot interface */
static int tse_adjust_link(struct altera_tse_priv *priv)
{
unsigned int refvar;
refvar = priv->mac_dev->command_config.image;
if (!(priv->duplexity))
refvar |= ALTERA_TSE_CMD_HD_ENA_MSK;
else
refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK;
switch (priv->speed) {
case 1000:
refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK;
refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
break;
case 100:
refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK;
break;
case 10:
refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK;
refvar |= ALTERA_TSE_CMD_ENA_10_MSK;
break;
}
priv->mac_dev->command_config.image = refvar;
return 0;
}
static int tse_eth_send(struct eth_device *dev,
volatile void *packet, int length)
{
struct altera_tse_priv *priv = dev->priv;
volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
volatile struct alt_sgdma_descriptor *tx_desc =
(volatile struct alt_sgdma_descriptor *)priv->tx_desc;
volatile struct alt_sgdma_descriptor *tx_desc_cur =
(volatile struct alt_sgdma_descriptor *)&tx_desc[0];
flush_dcache((unsigned long)packet, length);
alt_sgdma_construct_descriptor_burst(
(volatile struct alt_sgdma_descriptor *)&tx_desc[0],
(volatile struct alt_sgdma_descriptor *)&tx_desc[1],
(unsigned int *)packet, /* read addr */
(unsigned int *)0,
length, /* length or EOP ,will change for each tx */
0x1, /* gen eop */
0x0, /* read fixed */
0x1, /* write fixed or sop */
0x0, /* read burst */
0x0, /* write burst */
0x0 /* channel */
);
debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length);
/* send the packet */
debug("sending packet\n");
alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur);
debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred);
return tx_desc_cur->actual_bytes_transferred;
}
static int tse_eth_rx(struct eth_device *dev)
{
int packet_length = 0;
struct altera_tse_priv *priv = dev->priv;
volatile struct alt_sgdma_descriptor *rx_desc =
(volatile struct alt_sgdma_descriptor *)priv->rx_desc;
volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0];
if (rx_desc_cur->descriptor_status &
ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
debug("got packet\n");
packet_length = rx_desc->actual_bytes_transferred;
NetReceive(NetRxPackets[0], packet_length);
/* start descriptor again */
flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN);
alt_sgdma_construct_descriptor_burst(
(volatile struct alt_sgdma_descriptor *)&rx_desc[0],
(volatile struct alt_sgdma_descriptor *)&rx_desc[1],
(unsigned int)0x0, /* read addr */
(unsigned int *)NetRxPackets[0],
0x0, /* length or EOP */
0x0, /* gen eop */
0x0, /* read fixed */
0x0, /* write fixed or sop */
0x0, /* read burst */
0x0, /* write burst */
0x0 /* channel */
);
/* setup the sgdma */
alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]);
return packet_length;
}
return -1;
}
static void tse_eth_halt(struct eth_device *dev)
{
/* don't do anything! */
/* this gets called after each uboot */
/* network command. don't need to reset the thing all of the time */
}
static void tse_eth_reset(struct eth_device *dev)
{
/* stop sgdmas, disable tse receive */
struct altera_tse_priv *priv = dev->priv;
volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
volatile struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx;
volatile struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx;
int counter;
volatile struct alt_sgdma_descriptor *rx_desc =
(volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0];
/* clear rx desc & wait for sgdma to complete */
rx_desc->descriptor_control = 0;
rx_sgdma->control = 0;
counter = 0;
while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) {
if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
break;
}
if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) {
debug("Timeout waiting for rx sgdma!\n");
rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
rx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
}
counter = 0;
tx_sgdma->control = 0;
while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) {
if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR)
break;
}
if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) {
debug("Timeout waiting for tx sgdma!\n");
tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
tx_sgdma->control = ALT_SGDMA_CONTROL_SOFTWARERESET_MSK;
}
/* reset the mac */
mac_dev->command_config.bits.transmit_enable = 1;
mac_dev->command_config.bits.receive_enable = 1;
mac_dev->command_config.bits.software_reset = 1;
counter = 0;
while (mac_dev->command_config.bits.software_reset) {
if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR)
break;
}
if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR)
debug("TSEMAC SW reset bit never cleared!\n");
}
static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum)
{
volatile struct alt_tse_mac *mac_dev;
unsigned int *mdio_regs;
unsigned int data;
u16 value;
mac_dev = priv->mac_dev;
/* set mdio address */
mac_dev->mdio_phy1_addr = priv->phyaddr;
mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
/* get the data */
data = mdio_regs[regnum];
value = data & 0xffff;
return value;
}
static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum,
unsigned int value)
{
volatile struct alt_tse_mac *mac_dev;
unsigned int *mdio_regs;
unsigned int data;
mac_dev = priv->mac_dev;
/* set mdio address */
mac_dev->mdio_phy1_addr = priv->phyaddr;
mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
/* get the data */
data = (unsigned int)value;
mdio_regs[regnum] = data;
return 0;
}
/* MDIO access to phy */
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
static int altera_tse_miiphy_write(const char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
struct eth_device *dev;
struct altera_tse_priv *priv;
dev = eth_get_dev_by_name(devname);
priv = dev->priv;
tse_mdio_write(priv, (uint) reg, (uint) value);
return 0;
}
static int altera_tse_miiphy_read(const char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
struct eth_device *dev;
struct altera_tse_priv *priv;
volatile struct alt_tse_mac *mac_dev;
unsigned int *mdio_regs;
dev = eth_get_dev_by_name(devname);
priv = dev->priv;
mac_dev = priv->mac_dev;
mac_dev->mdio_phy1_addr = (int)addr;
mdio_regs = (unsigned int *)&mac_dev->mdio_phy1;
*value = 0xffff & mdio_regs[reg];
return 0;
}
#endif
/*
* Also copied from tsec.c
*/
/* Parse the status register for link, and then do
* auto-negotiation
*/
static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv)
{
/*
* Wait if the link is up, and autonegotiation is in progress
* (ie - we're capable and it's not done)
*/
mii_reg = tse_mdio_read(priv, MIIM_STATUS);
if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & BMSR_ANEGCAPABLE)
&& !(mii_reg & BMSR_ANEGCOMPLETE)) {
int i = 0;
puts("Waiting for PHY auto negotiation to complete");
while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
puts(" TIMEOUT !\n");
priv->link = 0;
return 0;
}
if ((i++ % 1000) == 0)
putc('.');
udelay(1000); /* 1 ms */
mii_reg = tse_mdio_read(priv, MIIM_STATUS);
}
puts(" done\n");
priv->link = 1;
udelay(500000); /* another 500 ms (results in faster booting) */
} else {
if (mii_reg & MIIM_STATUS_LINK) {
debug("Link is up\n");
priv->link = 1;
} else {
debug("Link is down\n");
priv->link = 0;
}
}
return 0;
}
/* Parse the 88E1011's status register for speed and duplex
* information
*/
static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv)
{
uint speed;
mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS);
if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
int i = 0;
puts("Waiting for PHY realtime link");
while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
/* Timeout reached ? */
if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
puts(" TIMEOUT !\n");
priv->link = 0;
break;
}
if ((i++ == 1000) == 0) {
i = 0;
puts(".");
}
udelay(1000); /* 1 ms */
mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS);
}
puts(" done\n");
udelay(500000); /* another 500 ms (results in faster booting) */
} else {
if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
priv->link = 1;
else
priv->link = 0;
}
if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
priv->duplexity = 1;
else
priv->duplexity = 0;
speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
switch (speed) {
case MIIM_88E1011_PHYSTAT_GBIT:
priv->speed = 1000;
debug("PHY Speed is 1000Mbit\n");
break;
case MIIM_88E1011_PHYSTAT_100:
debug("PHY Speed is 100Mbit\n");
priv->speed = 100;
break;
default:
debug("PHY Speed is 10Mbit\n");
priv->speed = 10;
}
return 0;
}
static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv)
{
uint mii_data = tse_mdio_read(priv, mii_reg);
mii_data &= 0xfff0;
if ((priv->flags >= 1) && (priv->flags <= 4))
mii_data |= 0xb;
else if (priv->flags == 5)
mii_data |= 0x4;
return mii_data;
}
static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv)
{
uint mii_data = tse_mdio_read(priv, mii_reg);
mii_data &= ~0x82;
if ((priv->flags >= 1) && (priv->flags <= 4))
mii_data |= 0x82;
return mii_data;
}
/*
* Returns which value to write to the control register.
* For 10/100, the value is slightly different
*/
static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv)
{
return MIIM_CONTROL_INIT;
}
/*
* PHY & MDIO code
* Need to add SGMII stuff
*
*/
static struct phy_info phy_info_M88E1111S = {
0x01410cc,
"Marvell 88E1111S",
4,
(struct phy_cmd[]){ /* config */
/* Reset and configure the PHY */
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
{MIIM_88E1111_PHY_EXT_SR, 0x848f,
&mii_m88e1111s_setmode_sr},
/* Delay RGMII TX and RX */
{MIIM_88E1111_PHY_EXT_CR, 0x0cd2,
&mii_m88e1111s_setmode_cr},
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
{miim_end,}
},
(struct phy_cmd[]){ /* startup */
/* Status is read once to clear old link state */
{MIIM_STATUS, miim_read, NULL},
/* Auto-negotiate */
{MIIM_STATUS, miim_read, &mii_parse_sr},
/* Read the status */
{MIIM_88E1011_PHY_STATUS, miim_read,
&mii_parse_88E1011_psr},
{miim_end,}
},
(struct phy_cmd[]){ /* shutdown */
{miim_end,}
},
};
/* a generic flavor. */
static struct phy_info phy_info_generic = {
0,
"Unknown/Generic PHY",
32,
(struct phy_cmd[]){ /* config */
{MII_BMCR, BMCR_RESET, NULL},
{MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART, NULL},
{miim_end,}
},
(struct phy_cmd[]){ /* startup */
{MII_BMSR, miim_read, NULL},
{MII_BMSR, miim_read, &mii_parse_sr},
{miim_end,}
},
(struct phy_cmd[]){ /* shutdown */
{miim_end,}
}
};
static struct phy_info *phy_info[] = {
&phy_info_M88E1111S,
NULL
};
/* Grab the identifier of the device's PHY, and search through
* all of the known PHYs to see if one matches. If so, return
* it, if not, return NULL
*/
static struct phy_info *get_phy_info(struct eth_device *dev)
{
struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv;
uint phy_reg, phy_ID;
int i;
struct phy_info *theInfo = NULL;
/* Grab the bits from PHYIR1, and put them in the upper half */
phy_reg = tse_mdio_read(priv, MIIM_PHYIR1);
phy_ID = (phy_reg & 0xffff) << 16;
/* Grab the bits from PHYIR2, and put them in the lower half */
phy_reg = tse_mdio_read(priv, MIIM_PHYIR2);
phy_ID |= (phy_reg & 0xffff);
/* loop through all the known PHY types, and find one that */
/* matches the ID we read from the PHY. */
for (i = 0; phy_info[i]; i++) {
if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
theInfo = phy_info[i];
break;
}
}
if (theInfo == NULL) {
theInfo = &phy_info_generic;
debug("%s: No support for PHY id %x; assuming generic\n",
dev->name, phy_ID);
} else
debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
return theInfo;
}
/* Execute the given series of commands on the given device's
* PHY, running functions as necessary
*/
static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd)
{
int i;
uint result;
for (i = 0; cmd->mii_reg != miim_end; i++) {
if (cmd->mii_data == miim_read) {
result = tse_mdio_read(priv, cmd->mii_reg);
if (cmd->funct != NULL)
(*(cmd->funct)) (result, priv);
} else {
if (cmd->funct != NULL)
result = (*(cmd->funct)) (cmd->mii_reg, priv);
else
result = cmd->mii_data;
tse_mdio_write(priv, cmd->mii_reg, result);
}
cmd++;
}
}
/* Phy init code */
static int init_phy(struct eth_device *dev)
{
struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv;
struct phy_info *curphy;
/* Get the cmd structure corresponding to the attached
* PHY */
curphy = get_phy_info(dev);
if (curphy == NULL) {
priv->phyinfo = NULL;
debug("%s: No PHY found\n", dev->name);
return 0;
} else
debug("%s found\n", curphy->name);
priv->phyinfo = curphy;
phy_run_commands(priv, priv->phyinfo->config);
return 1;
}
static int tse_set_mac_address(struct eth_device *dev)
{
struct altera_tse_priv *priv = dev->priv;
volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
debug("Setting MAC address to 0x%02x%02x%02x%02x%02x%02x\n",
dev->enetaddr[5], dev->enetaddr[4],
dev->enetaddr[3], dev->enetaddr[2],
dev->enetaddr[1], dev->enetaddr[0]);
mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 |
(dev->enetaddr[2]) << 16 |
(dev->enetaddr[1]) << 8 | (dev->enetaddr[0]));
mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 |
(dev->enetaddr[4])) & 0xFFFF);
/* Set the MAC address */
mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0;
mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1;
/* Set the MAC address */
mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0;
mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1;
/* Set the MAC address */
mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0;
mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1;
/* Set the MAC address */
mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0;
mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1;
return 0;
}
static int tse_eth_init(struct eth_device *dev, bd_t * bd)
{
int dat;
struct altera_tse_priv *priv = dev->priv;
volatile struct alt_tse_mac *mac_dev = priv->mac_dev;
volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
volatile struct alt_sgdma_descriptor *rx_desc_cur =
(volatile struct alt_sgdma_descriptor *)&rx_desc[0];
/* stop controller */
debug("Reseting TSE & SGDMAs\n");
tse_eth_reset(dev);
/* start the phy */
debug("Configuring PHY\n");
phy_run_commands(priv, priv->phyinfo->startup);
/* need to create sgdma */
debug("Configuring tx desc\n");
alt_sgdma_construct_descriptor_burst(
(volatile struct alt_sgdma_descriptor *)&tx_desc[0],
(volatile struct alt_sgdma_descriptor *)&tx_desc[1],
(unsigned int *)NULL, /* read addr */
(unsigned int *)0,
0, /* length or EOP ,will change for each tx */
0x1, /* gen eop */
0x0, /* read fixed */
0x1, /* write fixed or sop */
0x0, /* read burst */
0x0, /* write burst */
0x0 /* channel */
);
debug("Configuring rx desc\n");
flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN);
alt_sgdma_construct_descriptor_burst(
(volatile struct alt_sgdma_descriptor *)&rx_desc[0],
(volatile struct alt_sgdma_descriptor *)&rx_desc[1],
(unsigned int)0x0, /* read addr */
(unsigned int *)NetRxPackets[0],
0x0, /* length or EOP */
0x0, /* gen eop */
0x0, /* read fixed */
0x0, /* write fixed or sop */
0x0, /* read burst */
0x0, /* write burst */
0x0 /* channel */
);
/* start rx async transfer */
debug("Starting rx sgdma\n");
alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur);
/* start TSE */
debug("Configuring TSE Mac\n");
/* Initialize MAC registers */
mac_dev->max_frame_length = PKTSIZE_ALIGN;
mac_dev->rx_almost_empty_threshold = 8;
mac_dev->rx_almost_full_threshold = 8;
mac_dev->tx_almost_empty_threshold = 8;
mac_dev->tx_almost_full_threshold = 3;
mac_dev->tx_sel_empty_threshold =
CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16;
mac_dev->tx_sel_full_threshold = 0;
mac_dev->rx_sel_empty_threshold =
CONFIG_SYS_ALTERA_TSE_TX_FIFO - 16;
mac_dev->rx_sel_full_threshold = 0;
/* NO Shift */
mac_dev->rx_cmd_stat.bits.rx_shift16 = 0;
mac_dev->tx_cmd_stat.bits.tx_shift16 = 0;
/* enable MAC */
dat = 0;
dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK;
mac_dev->command_config.image = dat;
/* configure the TSE core */
/* -- output clocks, */
/* -- and later config stuff for SGMII */
if (priv->link) {
debug("Adjusting TSE to link speed\n");
tse_adjust_link(priv);
}
return priv->link ? 0 : -1;
}
/* TSE init code */
int altera_tse_initialize(u8 dev_num, int mac_base,
int sgdma_rx_base, int sgdma_tx_base,
u32 sgdma_desc_base, u32 sgdma_desc_size)
{
struct altera_tse_priv *priv;
struct eth_device *dev;
struct alt_sgdma_descriptor *rx_desc;
struct alt_sgdma_descriptor *tx_desc;
unsigned long dma_handle;
dev = (struct eth_device *)malloc(sizeof *dev);
if (NULL == dev)
return 0;
memset(dev, 0, sizeof *dev);
priv = malloc(sizeof(*priv));
if (!priv) {
free(dev);
return 0;
}
if (sgdma_desc_size) {
if (sgdma_desc_size < (sizeof(*tx_desc) * (3 + PKTBUFSRX))) {
printf("ALTERA_TSE-%hu: "
"descriptor memory is too small\n", dev_num);
free(priv);
free(dev);
return 0;
}
tx_desc = (struct alt_sgdma_descriptor *)sgdma_desc_base;
} else {
tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX),
&dma_handle);
}
rx_desc = tx_desc + 2;
debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc);
debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc);
if (!tx_desc) {
free(priv);
free(dev);
return 0;
}
memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1));
memset(tx_desc, 0, (sizeof *tx_desc) * 2);
/* initialize tse priv */
priv->mac_dev = (volatile struct alt_tse_mac *)mac_base;
priv->sgdma_rx = (volatile struct alt_sgdma_registers *)sgdma_rx_base;
priv->sgdma_tx = (volatile struct alt_sgdma_registers *)sgdma_tx_base;
priv->phyaddr = CONFIG_SYS_ALTERA_TSE_PHY_ADDR;
priv->flags = CONFIG_SYS_ALTERA_TSE_FLAGS;
priv->rx_desc = rx_desc;
priv->tx_desc = tx_desc;
/* init eth structure */
dev->priv = priv;
dev->init = tse_eth_init;
dev->halt = tse_eth_halt;
dev->send = tse_eth_send;
dev->recv = tse_eth_rx;
dev->write_hwaddr = tse_set_mac_address;
sprintf(dev->name, "%s-%hu", "ALTERA_TSE", dev_num);
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
miiphy_register(dev->name, altera_tse_miiphy_read,
altera_tse_miiphy_write);
#endif
init_phy(dev);
return 1;
}
|
1001-study-uboot
|
drivers/net/altera_tse.c
|
C
|
gpl3
| 26,668
|
/*
Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
are GPL, so this is, of course, GPL.
==========================================================================
dev/if_dp83902a.c
Ethernet device driver for NS DP83902a ethernet controller
==========================================================================
####ECOSGPLCOPYRIGHTBEGIN####
-------------------------------------------
This file is part of eCos, the Embedded Configurable Operating System.
Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
eCos is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 or (at your option) any later version.
eCos is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with eCos; if not, write to the Free Software Foundation, Inc.,
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
As a special exception, if other files instantiate templates or use macros
or inline functions from this file, or you compile this file and link it
with other works to produce a work based on this file, this file does not
by itself cause the resulting work to be covered by the GNU General Public
License. However the source code for this file must still be made available
in accordance with section (3) of the GNU General Public License.
This exception does not invalidate any other reasons why a work based on
this file might be covered by the GNU General Public License.
Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
at http://sources.redhat.com/ecos/ecos-license/
-------------------------------------------
####ECOSGPLCOPYRIGHTEND####
####BSDCOPYRIGHTBEGIN####
-------------------------------------------
Portions of this software may have been derived from OpenBSD or other sources,
and are covered by the appropriate copyright disclaimers included herein.
-------------------------------------------
####BSDCOPYRIGHTEND####
==========================================================================
#####DESCRIPTIONBEGIN####
Author(s): gthomas
Contributors: gthomas, jskov, rsandifo
Date: 2001-06-13
Purpose:
Description:
FIXME: Will fail if pinged with large packets (1520 bytes)
Add promisc config
Add SNMP
####DESCRIPTIONEND####
==========================================================================
*/
#include <common.h>
#include <command.h>
#include <net.h>
#include <malloc.h>
#include <linux/compiler.h>
/* forward definition of function used for the uboot interface */
void uboot_push_packet_len(int len);
void uboot_push_tx_done(int key, int val);
/* NE2000 base header file */
#include "ne2000_base.h"
#if defined(CONFIG_DRIVER_AX88796L)
/* AX88796L support */
#include "ax88796.h"
#else
/* Basic NE2000 chip support */
#include "ne2000.h"
#endif
static dp83902a_priv_data_t nic; /* just one instance of the card supported */
/**
* This function reads the MAC address from the serial EEPROM,
* used if PROM read fails. Does nothing for ax88796 chips (sh boards)
*/
static bool
dp83902a_init(unsigned char *enetaddr)
{
dp83902a_priv_data_t *dp = &nic;
u8* base;
#if defined(NE2000_BASIC_INIT)
int i;
#endif
DEBUG_FUNCTION();
base = dp->base;
if (!base)
return false; /* No device found */
DEBUG_LINE();
#if defined(NE2000_BASIC_INIT)
/* AX88796L doesn't need */
/* Prepare ESA */
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */
/* Use the address from the serial EEPROM */
for (i = 0; i < 6; i++)
DP_IN(base, DP_P1_PAR0+i, dp->esa[i]);
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */
printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
"eeprom",
dp->esa[0],
dp->esa[1],
dp->esa[2],
dp->esa[3],
dp->esa[4],
dp->esa[5] );
memcpy(enetaddr, dp->esa, 6); /* Use MAC from serial EEPROM */
#endif /* NE2000_BASIC_INIT */
return true;
}
static void
dp83902a_stop(void)
{
dp83902a_priv_data_t *dp = &nic;
u8 *base = dp->base;
DEBUG_FUNCTION();
DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */
DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */
dp->running = false;
}
/*
* This function is called to "start up" the interface. It may be called
* multiple times, even when the hardware is already running. It will be
* called whenever something "hardware oriented" changes and should leave
* the hardware ready to send/receive packets.
*/
static void
dp83902a_start(u8 * enaddr)
{
dp83902a_priv_data_t *dp = &nic;
u8 *base = dp->base;
int i;
debug("The MAC is %pM\n", enaddr);
DEBUG_FUNCTION();
DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
DP_OUT(base, DP_DCR, DP_DCR_INIT);
DP_OUT(base, DP_RBCH, 0); /* Remote byte count */
DP_OUT(base, DP_RBCL, 0);
DP_OUT(base, DP_RCR, DP_RCR_MON); /* Accept no packets */
DP_OUT(base, DP_TCR, DP_TCR_LOCAL); /* Transmitter [virtually] off */
DP_OUT(base, DP_TPSR, dp->tx_buf1); /* Transmitter start page */
dp->tx1 = dp->tx2 = 0;
dp->tx_next = dp->tx_buf1;
dp->tx_started = false;
dp->running = true;
DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */
DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */
dp->rx_next = dp->rx_buf_start - 1;
dp->running = true;
DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */
DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */
DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */
dp->running = true;
for (i = 0; i < ETHER_ADDR_LEN; i++) {
/* FIXME */
/*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) +
* 0x1400)) = enaddr[i];*/
DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
}
/* Enable and start device */
DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */
dp->running = true;
}
/*
* This routine is called to start the transmitter. It is split out from the
* data handling routine so it may be called either when data becomes first
* available or when an Tx interrupt occurs
*/
static void
dp83902a_start_xmit(int start_page, int len)
{
dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
u8 *base = dp->base;
DEBUG_FUNCTION();
#if DEBUG & 1
printf("Tx pkt %d len %d\n", start_page, len);
if (dp->tx_started)
printf("TX already started?!?\n");
#endif
DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE));
DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
DP_OUT(base, DP_TBCL, len & 0xFF);
DP_OUT(base, DP_TBCH, len >> 8);
DP_OUT(base, DP_TPSR, start_page);
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
dp->tx_started = true;
}
/*
* This routine is called to send data to the hardware. It is known a-priori
* that there is free buffer space (dp->tx_next).
*/
static void
dp83902a_send(u8 *data, int total_len, u32 key)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
u8 *base = dp->base;
int len, start_page, pkt_len, i, isr;
#if DEBUG & 4
int dx;
#endif
DEBUG_FUNCTION();
len = pkt_len = total_len;
if (pkt_len < IEEE_8023_MIN_FRAME)
pkt_len = IEEE_8023_MIN_FRAME;
start_page = dp->tx_next;
if (dp->tx_next == dp->tx_buf1) {
dp->tx1 = start_page;
dp->tx1_len = pkt_len;
dp->tx1_key = key;
dp->tx_next = dp->tx_buf2;
} else {
dp->tx2 = start_page;
dp->tx2_len = pkt_len;
dp->tx2_key = key;
dp->tx_next = dp->tx_buf1;
}
#if DEBUG & 5
printf("TX prep page %d len %d\n", start_page, pkt_len);
#endif
DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
{
/*
* Dummy read. The manual sez something slightly different,
* but the code is extended a bit to do what Hitachi's monitor
* does (i.e., also read data).
*/
__maybe_unused u16 tmp;
int len = 1;
DP_OUT(base, DP_RSAL, 0x100 - len);
DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff);
DP_OUT(base, DP_RBCL, len);
DP_OUT(base, DP_RBCH, 0);
DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START);
DP_IN_DATA(dp->data, tmp);
}
#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
/*
* Stall for a bit before continuing to work around random data
* corruption problems on some platforms.
*/
CYGACC_CALL_IF_DELAY_US(1);
#endif
/* Send data to device buffer(s) */
DP_OUT(base, DP_RSAL, 0);
DP_OUT(base, DP_RSAH, start_page);
DP_OUT(base, DP_RBCL, pkt_len & 0xFF);
DP_OUT(base, DP_RBCH, pkt_len >> 8);
DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START);
/* Put data into buffer */
#if DEBUG & 4
printf(" sg buf %08lx len %08x\n ", (u32)data, len);
dx = 0;
#endif
while (len > 0) {
#if DEBUG & 4
printf(" %02x", *data);
if (0 == (++dx % 16)) printf("\n ");
#endif
DP_OUT_DATA(dp->data, *data++);
len--;
}
#if DEBUG & 4
printf("\n");
#endif
if (total_len < pkt_len) {
#if DEBUG & 4
printf(" + %d bytes of padding\n", pkt_len - total_len);
#endif
/* Padding to 802.3 length was required */
for (i = total_len; i < pkt_len;) {
i++;
DP_OUT_DATA(dp->data, 0);
}
}
#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
/*
* After last data write, delay for a bit before accessing the
* device again, or we may get random data corruption in the last
* datum (on some platforms).
*/
CYGACC_CALL_IF_DELAY_US(1);
#endif
/* Wait for DMA to complete */
do {
DP_IN(base, DP_ISR, isr);
} while ((isr & DP_ISR_RDC) == 0);
/* Then disable DMA */
DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
/* Start transmit if not already going */
if (!dp->tx_started) {
if (start_page == dp->tx1) {
dp->tx_int = 1; /* Expecting interrupt from BUF1 */
} else {
dp->tx_int = 2; /* Expecting interrupt from BUF2 */
}
dp83902a_start_xmit(start_page, pkt_len);
}
}
/*
* This function is called when a packet has been received. It's job is
* to prepare to unload the packet from the hardware. Once the length of
* the packet is known, the upper layer of the driver can be told. When
* the upper layer is ready to unload the packet, the internal function
* 'dp83902a_recv' will be called to actually fetch it from the hardware.
*/
static void
dp83902a_RxEvent(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
u8 *base = dp->base;
__maybe_unused u8 rsr;
u8 rcv_hdr[4];
int i, len, pkt, cur;
DEBUG_FUNCTION();
DP_IN(base, DP_RSR, rsr);
while (true) {
/* Read incoming packet header */
DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START);
DP_IN(base, DP_P1_CURP, cur);
DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
DP_IN(base, DP_BNDRY, pkt);
pkt += 1;
if (pkt == dp->rx_buf_end)
pkt = dp->rx_buf_start;
if (pkt == cur) {
break;
}
DP_OUT(base, DP_RBCL, sizeof(rcv_hdr));
DP_OUT(base, DP_RBCH, 0);
DP_OUT(base, DP_RSAL, 0);
DP_OUT(base, DP_RSAH, pkt);
if (dp->rx_next == pkt) {
if (cur == dp->rx_buf_start)
DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
else
DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */
return;
}
dp->rx_next = pkt;
DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
CYGACC_CALL_IF_DELAY_US(10);
#endif
/* read header (get data size)*/
for (i = 0; i < sizeof(rcv_hdr);) {
DP_IN_DATA(dp->data, rcv_hdr[i++]);
}
#if DEBUG & 5
printf("rx hdr %02x %02x %02x %02x\n",
rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
#endif
len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
/* data read */
uboot_push_packet_len(len);
if (rcv_hdr[1] == dp->rx_buf_start)
DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
else
DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */
}
}
/*
* This function is called as a result of the "eth_drv_recv()" call above.
* It's job is to actually fetch data for a packet from the hardware once
* memory buffers have been allocated for the packet. Note that the buffers
* may come in pieces, using a scatter-gather list. This allows for more
* efficient processing in the upper layers of the stack.
*/
static void
dp83902a_recv(u8 *data, int len)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
u8 *base = dp->base;
int i, mlen;
u8 saved_char = 0;
bool saved;
#if DEBUG & 4
int dx;
#endif
DEBUG_FUNCTION();
#if DEBUG & 5
printf("Rx packet %d length %d\n", dp->rx_next, len);
#endif
/* Read incoming packet data */
DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
DP_OUT(base, DP_RBCL, len & 0xFF);
DP_OUT(base, DP_RBCH, len >> 8);
DP_OUT(base, DP_RSAL, 4); /* Past header */
DP_OUT(base, DP_RSAH, dp->rx_next);
DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
CYGACC_CALL_IF_DELAY_US(10);
#endif
saved = false;
for (i = 0; i < 1; i++) {
if (data) {
mlen = len;
#if DEBUG & 4
printf(" sg buf %08lx len %08x \n", (u32) data, mlen);
dx = 0;
#endif
while (0 < mlen) {
/* Saved byte from previous loop? */
if (saved) {
*data++ = saved_char;
mlen--;
saved = false;
continue;
}
{
u8 tmp;
DP_IN_DATA(dp->data, tmp);
#if DEBUG & 4
printf(" %02x", tmp);
if (0 == (++dx % 16)) printf("\n ");
#endif
*data++ = tmp;;
mlen--;
}
}
#if DEBUG & 4
printf("\n");
#endif
}
}
}
static void
dp83902a_TxEvent(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
u8 *base = dp->base;
__maybe_unused u8 tsr;
u32 key;
DEBUG_FUNCTION();
DP_IN(base, DP_TSR, tsr);
if (dp->tx_int == 1) {
key = dp->tx1_key;
dp->tx1 = 0;
} else {
key = dp->tx2_key;
dp->tx2 = 0;
}
/* Start next packet if one is ready */
dp->tx_started = false;
if (dp->tx1) {
dp83902a_start_xmit(dp->tx1, dp->tx1_len);
dp->tx_int = 1;
} else if (dp->tx2) {
dp83902a_start_xmit(dp->tx2, dp->tx2_len);
dp->tx_int = 2;
} else {
dp->tx_int = 0;
}
/* Tell higher level we sent this packet */
uboot_push_tx_done(key, 0);
}
/*
* Read the tally counters to clear them. Called in response to a CNT
* interrupt.
*/
static void
dp83902a_ClearCounters(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
u8 *base = dp->base;
__maybe_unused u8 cnt1, cnt2, cnt3;
DP_IN(base, DP_FER, cnt1);
DP_IN(base, DP_CER, cnt2);
DP_IN(base, DP_MISSED, cnt3);
DP_OUT(base, DP_ISR, DP_ISR_CNT);
}
/*
* Deal with an overflow condition. This code follows the procedure set
* out in section 7.0 of the datasheet.
*/
static void
dp83902a_Overflow(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
u8 *base = dp->base;
u8 isr;
/* Issue a stop command and wait 1.6ms for it to complete. */
DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
CYGACC_CALL_IF_DELAY_US(1600);
/* Clear the remote byte counter registers. */
DP_OUT(base, DP_RBCL, 0);
DP_OUT(base, DP_RBCH, 0);
/* Enter loopback mode while we clear the buffer. */
DP_OUT(base, DP_TCR, DP_TCR_LOCAL);
DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA);
/*
* Read in as many packets as we can and acknowledge any and receive
* interrupts. Since the buffer has overflowed, a receive event of
* some kind will have occured.
*/
dp83902a_RxEvent();
DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
/* Clear the overflow condition and leave loopback mode. */
DP_OUT(base, DP_ISR, DP_ISR_OFLW);
DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
/*
* If a transmit command was issued, but no transmit event has occured,
* restart it here.
*/
DP_IN(base, DP_ISR, isr);
if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) {
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
}
}
static void
dp83902a_poll(void)
{
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
u8 *base = dp->base;
u8 isr;
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
DP_IN(base, DP_ISR, isr);
while (0 != isr) {
/*
* The CNT interrupt triggers when the MSB of one of the error
* counters is set. We don't much care about these counters, but
* we should read their values to reset them.
*/
if (isr & DP_ISR_CNT) {
dp83902a_ClearCounters();
}
/*
* Check for overflow. It's a special case, since there's a
* particular procedure that must be followed to get back into
* a running state.a
*/
if (isr & DP_ISR_OFLW) {
dp83902a_Overflow();
} else {
/*
* Other kinds of interrupts can be acknowledged simply by
* clearing the relevant bits of the ISR. Do that now, then
* handle the interrupts we care about.
*/
DP_OUT(base, DP_ISR, isr); /* Clear set bits */
if (!dp->running) break; /* Is this necessary? */
/*
* Check for tx_started on TX event since these may happen
* spuriously it seems.
*/
if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) {
dp83902a_TxEvent();
}
if (isr & (DP_ISR_RxP|DP_ISR_RxE)) {
dp83902a_RxEvent();
}
}
DP_IN(base, DP_ISR, isr);
}
}
/* U-boot specific routines */
static u8 *pbuf = NULL;
static int pkey = -1;
static int initialized = 0;
void uboot_push_packet_len(int len) {
PRINTK("pushed len = %d\n", len);
if (len >= 2000) {
printf("NE2000: packet too big\n");
return;
}
dp83902a_recv(&pbuf[0], len);
/*Just pass it to the upper layer*/
NetReceive(&pbuf[0], len);
}
void uboot_push_tx_done(int key, int val) {
PRINTK("pushed key = %d\n", key);
pkey = key;
}
/**
* Setup the driver and init MAC address according to doc/README.enetaddr
* Called by ne2k_register() before registering the driver @eth layer
*
* @param struct ethdevice of this instance of the driver for dev->enetaddr
* @return 0 on success, -1 on error (causing caller to print error msg)
*/
static int ne2k_setup_driver(struct eth_device *dev)
{
PRINTK("### ne2k_setup_driver\n");
if (!pbuf) {
pbuf = malloc(2000);
if (!pbuf) {
printf("Cannot allocate rx buffer\n");
return -1;
}
}
#ifdef CONFIG_DRIVER_NE2000_CCR
{
vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
PRINTK("CCR before is %x\n", *p);
*p = CONFIG_DRIVER_NE2000_VAL;
PRINTK("CCR after is %x\n", *p);
}
#endif
nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
nic.data = nic.base + DP_DATA;
nic.tx_buf1 = START_PG;
nic.tx_buf2 = START_PG2;
nic.rx_buf_start = RX_START;
nic.rx_buf_end = RX_END;
/*
* According to doc/README.enetaddr, drivers shall give priority
* to the MAC address value in the environment, so we do not read
* it from the prom or eeprom if it is specified in the environment.
*/
if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) {
/* If the MAC address is not in the environment, get it: */
if (!get_prom(dev->enetaddr, nic.base)) /* get MAC from prom */
dp83902a_init(dev->enetaddr); /* fallback: seeprom */
/* And write it into the environment otherwise eth_write_hwaddr
* returns -1 due to eth_getenv_enetaddr_by_index() failing,
* and this causes "Warning: failed to set MAC address", and
* cmd_bdinfo has no ethaddr value which it can show: */
eth_setenv_enetaddr("ethaddr", dev->enetaddr);
}
return 0;
}
static int ne2k_init(struct eth_device *dev, bd_t *bd)
{
dp83902a_start(dev->enetaddr);
initialized = 1;
return 0;
}
static void ne2k_halt(struct eth_device *dev)
{
debug("### ne2k_halt\n");
if(initialized)
dp83902a_stop();
initialized = 0;
}
static int ne2k_recv(struct eth_device *dev)
{
dp83902a_poll();
return 1;
}
static int ne2k_send(struct eth_device *dev, volatile void *packet, int length)
{
int tmo;
debug("### ne2k_send\n");
pkey = -1;
dp83902a_send((u8 *) packet, length, 666);
tmo = get_timer (0) + TOUT * CONFIG_SYS_HZ;
while(1) {
dp83902a_poll();
if (pkey != -1) {
PRINTK("Packet sucesfully sent\n");
return 0;
}
if (get_timer (0) >= tmo) {
printf("transmission error (timoeut)\n");
return 0;
}
}
return 0;
}
/**
* Setup the driver for use and register it with the eth layer
* @return 0 on success, -1 on error (causing caller to print error msg)
*/
int ne2k_register(void)
{
struct eth_device *dev;
dev = calloc(sizeof(*dev), 1);
if (dev == NULL)
return -1;
if (ne2k_setup_driver(dev))
return -1;
dev->init = ne2k_init;
dev->halt = ne2k_halt;
dev->send = ne2k_send;
dev->recv = ne2k_recv;
sprintf(dev->name, "NE2000");
return eth_register(dev);
}
|
1001-study-uboot
|
drivers/net/ne2000_base.c
|
C
|
gpl3
| 21,066
|
/*
Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
are GPL, so this is, of course, GPL.
==========================================================================
dev/dp83902a.h
National Semiconductor DP83902a ethernet chip
==========================================================================
####ECOSGPLCOPYRIGHTBEGIN####
-------------------------------------------
This file is part of eCos, the Embedded Configurable Operating System.
Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
eCos is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 or (at your option) any later version.
eCos is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License along
with eCos; if not, write to the Free Software Foundation, Inc.,
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
As a special exception, if other files instantiate templates or use macros
or inline functions from this file, or you compile this file and link it
with other works to produce a work based on this file, this file does not
by itself cause the resulting work to be covered by the GNU General Public
License. However the source code for this file must still be made available
in accordance with section (3) of the GNU General Public License.
This exception does not invalidate any other reasons why a work based on
this file might be covered by the GNU General Public License.
Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
at http://sources.redhat.com/ecos/ecos-license/
-------------------------------------------
####ECOSGPLCOPYRIGHTEND####
####BSDCOPYRIGHTBEGIN####
-------------------------------------------
Portions of this software may have been derived from OpenBSD or other sources,
and are covered by the appropriate copyright disclaimers included herein.
-------------------------------------------
####BSDCOPYRIGHTEND####
==========================================================================
#####DESCRIPTIONBEGIN####
Author(s): gthomas
Contributors: gthomas, jskov
Date: 2001-06-13
Purpose:
Description:
####DESCRIPTIONEND####
==========================================================================
*/
/*
------------------------------------------------------------------------
Macros for accessing DP registers
These can be overridden by the platform header
*/
#ifndef __NE2000_BASE_H__
#define __NE2000_BASE_H__
#define bool int
#define false 0
#define true 1
/*
* Debugging details
*
* Set to perms of:
* 0 disables all debug output
* 1 for process debug output
* 2 for added data IO output: get_reg, put_reg
* 4 for packet allocation/free output
* 8 for only startup status, so we can tell we're installed OK
*/
#if 0
#define DEBUG 0xf
#else
#define DEBUG 0
#endif
#if DEBUG & 1
#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
#define PRINTK(args...) printf(args)
#else
#define DEBUG_FUNCTION() do {} while(0)
#define DEBUG_LINE() do {} while(0)
#define PRINTK(args...)
#endif
/* timeout for tx/rx in s */
#define TOUT 5
/* Ether MAC address size */
#define ETHER_ADDR_LEN 6
#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
#define CYGACC_CALL_IF_DELAY_US(X) udelay(X)
/* H/W infomation struct */
typedef struct hw_info_t {
u32 offset;
u8 a0, a1, a2;
u32 flags;
} hw_info_t;
typedef struct dp83902a_priv_data {
u8* base;
u8* data;
u8* reset;
int tx_next; /* First free Tx page */
int tx_int; /* Expecting interrupt from this buffer */
int rx_next; /* First free Rx page */
int tx1, tx2; /* Page numbers for Tx buffers */
u32 tx1_key, tx2_key; /* Used to ack when packet sent */
int tx1_len, tx2_len;
bool tx_started, running, hardwired_esa;
u8 esa[6];
void* plf_priv;
/* Buffer allocation */
int tx_buf1, tx_buf2;
int rx_buf_start, rx_buf_end;
} dp83902a_priv_data_t;
/* ------------------------------------------------------------------------ */
/* Register offsets */
#define DP_CR 0x00
#define DP_CLDA0 0x01
#define DP_PSTART 0x01 /* write */
#define DP_CLDA1 0x02
#define DP_PSTOP 0x02 /* write */
#define DP_BNDRY 0x03
#define DP_TSR 0x04
#define DP_TPSR 0x04 /* write */
#define DP_NCR 0x05
#define DP_TBCL 0x05 /* write */
#define DP_FIFO 0x06
#define DP_TBCH 0x06 /* write */
#define DP_ISR 0x07
#define DP_CRDA0 0x08
#define DP_RSAL 0x08 /* write */
#define DP_CRDA1 0x09
#define DP_RSAH 0x09 /* write */
#define DP_RBCL 0x0a /* write */
#define DP_RBCH 0x0b /* write */
#define DP_RSR 0x0c
#define DP_RCR 0x0c /* write */
#define DP_FER 0x0d
#define DP_TCR 0x0d /* write */
#define DP_CER 0x0e
#define DP_DCR 0x0e /* write */
#define DP_MISSED 0x0f
#define DP_IMR 0x0f /* write */
#define DP_DATAPORT 0x10 /* "eprom" data port */
#define DP_P1_CR 0x00
#define DP_P1_PAR0 0x01
#define DP_P1_PAR1 0x02
#define DP_P1_PAR2 0x03
#define DP_P1_PAR3 0x04
#define DP_P1_PAR4 0x05
#define DP_P1_PAR5 0x06
#define DP_P1_CURP 0x07
#define DP_P1_MAR0 0x08
#define DP_P1_MAR1 0x09
#define DP_P1_MAR2 0x0a
#define DP_P1_MAR3 0x0b
#define DP_P1_MAR4 0x0c
#define DP_P1_MAR5 0x0d
#define DP_P1_MAR6 0x0e
#define DP_P1_MAR7 0x0f
#define DP_P2_CR 0x00
#define DP_P2_PSTART 0x01
#define DP_P2_CLDA0 0x01 /* write */
#define DP_P2_PSTOP 0x02
#define DP_P2_CLDA1 0x02 /* write */
#define DP_P2_RNPP 0x03
#define DP_P2_TPSR 0x04
#define DP_P2_LNPP 0x05
#define DP_P2_ACH 0x06
#define DP_P2_ACL 0x07
#define DP_P2_RCR 0x0c
#define DP_P2_TCR 0x0d
#define DP_P2_DCR 0x0e
#define DP_P2_IMR 0x0f
/* Command register - common to all pages */
#define DP_CR_STOP 0x01 /* Stop: software reset */
#define DP_CR_START 0x02 /* Start: initialize device */
#define DP_CR_TXPKT 0x04 /* Transmit packet */
#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */
#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */
#define DP_CR_SEND 0x18 /* Send packet */
#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */
#define DP_CR_PAGE0 0x00 /* Page select */
#define DP_CR_PAGE1 0x40
#define DP_CR_PAGE2 0x80
#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */
/* Data configuration register */
#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */
#define DP_DCR_BOS 0x02 /* 1=Little Endian */
#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */
#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */
#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */
#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */
#define DP_DCR_FIFO_2 0x20
#define DP_DCR_FIFO_4 0x40
#define DP_DCR_FIFO_6 0x60
#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4)
/* Interrupt status register */
#define DP_ISR_RxP 0x01 /* Packet received */
#define DP_ISR_TxP 0x02 /* Packet transmitted */
#define DP_ISR_RxE 0x04 /* Receive error */
#define DP_ISR_TxE 0x08 /* Transmit error */
#define DP_ISR_OFLW 0x10 /* Receive overflow */
#define DP_ISR_CNT 0x20 /* Tally counters need emptying */
#define DP_ISR_RDC 0x40 /* Remote DMA complete */
#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */
/* Interrupt mask register */
#define DP_IMR_RxP 0x01 /* Packet received */
#define DP_IMR_TxP 0x02 /* Packet transmitted */
#define DP_IMR_RxE 0x04 /* Receive error */
#define DP_IMR_TxE 0x08 /* Transmit error */
#define DP_IMR_OFLW 0x10 /* Receive overflow */
#define DP_IMR_CNT 0x20 /* Tall counters need emptying */
#define DP_IMR_RDC 0x40 /* Remote DMA complete */
#define DP_IMR_All 0x3F /* Everything but remote DMA */
/* Receiver control register */
#define DP_RCR_SEP 0x01 /* Save bad(error) packets */
#define DP_RCR_AR 0x02 /* Accept runt packets */
#define DP_RCR_AB 0x04 /* Accept broadcast packets */
#define DP_RCR_AM 0x08 /* Accept multicast packets */
#define DP_RCR_PROM 0x10 /* Promiscuous mode */
#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */
/* Receiver status register */
#define DP_RSR_RxP 0x01 /* Packet received */
#define DP_RSR_CRC 0x02 /* CRC error */
#define DP_RSR_FRAME 0x04 /* Framing error */
#define DP_RSR_FO 0x08 /* FIFO overrun */
#define DP_RSR_MISS 0x10 /* Missed packet */
#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */
#define DP_RSR_DIS 0x40 /* Receiver disabled */
#define DP_RSR_DFR 0x80 /* Receiver processing deferred */
/* Transmitter control register */
#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */
#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */
#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */
#define DP_TCR_INLOOP 0x04 /* Full internal loopback */
#define DP_TCR_OUTLOOP 0x08 /* External loopback */
#define DP_TCR_ATD 0x10 /* Auto transmit disable */
#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */
/* Transmit status register */
#define DP_TSR_TxP 0x01 /* Packet transmitted */
#define DP_TSR_COL 0x04 /* Collision (at least one) */
#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */
#define DP_TSR_CRS 0x10 /* Lost carrier */
#define DP_TSR_FU 0x20 /* FIFO underrun */
#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */
#define DP_TSR_OWC 0x80 /* Collision outside normal window */
#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */
#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */
/* Functions */
int get_prom(u8* mac_addr, u8* base_addr);
#endif /* __NE2000_BASE_H__ */
|
1001-study-uboot
|
drivers/net/ne2000_base.h
|
C
|
gpl3
| 9,776
|
/*
* Copyright (C) 2005-2006 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
/*
* The u-boot networking stack is a little weird. It seems like the
* networking core allocates receive buffers up front without any
* regard to the hardware that's supposed to actually receive those
* packets.
*
* The MACB receives packets into 128-byte receive buffers, so the
* buffers allocated by the core isn't very practical to use. We'll
* allocate our own, but we need one such buffer in case a packet
* wraps around the DMA ring so that we have to copy it.
*
* Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
* configuration header. This way, the core allocates one RX buffer
* and one TX buffer, each of which can hold a ethernet packet of
* maximum size.
*
* For some reason, the networking core unconditionally specifies a
* 32-byte packet "alignment" (which really should be called
* "padding"). MACB shouldn't need that, but we'll refrain from any
* core modifications here...
*/
#include <net.h>
#include <netdev.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mii.h>
#include <asm/io.h>
#include <asm/dma-mapping.h>
#include <asm/arch/clk.h>
#include "macb.h"
#define barrier() asm volatile("" ::: "memory")
#define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
#define CONFIG_SYS_MACB_TX_RING_SIZE 16
#define CONFIG_SYS_MACB_TX_TIMEOUT 1000
#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
struct macb_dma_desc {
u32 addr;
u32 ctrl;
};
#define RXADDR_USED 0x00000001
#define RXADDR_WRAP 0x00000002
#define RXBUF_FRMLEN_MASK 0x00000fff
#define RXBUF_FRAME_START 0x00004000
#define RXBUF_FRAME_END 0x00008000
#define RXBUF_TYPEID_MATCH 0x00400000
#define RXBUF_ADDR4_MATCH 0x00800000
#define RXBUF_ADDR3_MATCH 0x01000000
#define RXBUF_ADDR2_MATCH 0x02000000
#define RXBUF_ADDR1_MATCH 0x04000000
#define RXBUF_BROADCAST 0x80000000
#define TXBUF_FRMLEN_MASK 0x000007ff
#define TXBUF_FRAME_END 0x00008000
#define TXBUF_NOCRC 0x00010000
#define TXBUF_EXHAUSTED 0x08000000
#define TXBUF_UNDERRUN 0x10000000
#define TXBUF_MAXRETRY 0x20000000
#define TXBUF_WRAP 0x40000000
#define TXBUF_USED 0x80000000
struct macb_device {
void *regs;
unsigned int rx_tail;
unsigned int tx_head;
unsigned int tx_tail;
void *rx_buffer;
void *tx_buffer;
struct macb_dma_desc *rx_ring;
struct macb_dma_desc *tx_ring;
unsigned long rx_buffer_dma;
unsigned long rx_ring_dma;
unsigned long tx_ring_dma;
const struct device *dev;
struct eth_device netdev;
unsigned short phy_addr;
};
#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
{
unsigned long netctl;
unsigned long netstat;
unsigned long frame;
netctl = macb_readl(macb, NCR);
netctl |= MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
frame = (MACB_BF(SOF, 1)
| MACB_BF(RW, 1)
| MACB_BF(PHYA, macb->phy_addr)
| MACB_BF(REGA, reg)
| MACB_BF(CODE, 2)
| MACB_BF(DATA, value));
macb_writel(macb, MAN, frame);
do {
netstat = macb_readl(macb, NSR);
} while (!(netstat & MACB_BIT(IDLE)));
netctl = macb_readl(macb, NCR);
netctl &= ~MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
}
static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
{
unsigned long netctl;
unsigned long netstat;
unsigned long frame;
netctl = macb_readl(macb, NCR);
netctl |= MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
frame = (MACB_BF(SOF, 1)
| MACB_BF(RW, 2)
| MACB_BF(PHYA, macb->phy_addr)
| MACB_BF(REGA, reg)
| MACB_BF(CODE, 2));
macb_writel(macb, MAN, frame);
do {
netstat = macb_readl(macb, NSR);
} while (!(netstat & MACB_BIT(IDLE)));
frame = macb_readl(macb, MAN);
netctl = macb_readl(macb, NCR);
netctl &= ~MACB_BIT(MPE);
macb_writel(macb, NCR, netctl);
return MACB_BFEXT(DATA, frame);
}
#if defined(CONFIG_CMD_MII)
int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
if ( macb->phy_addr != phy_adr )
return -1;
*value = macb_mdio_read(macb, reg);
return 0;
}
int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
if ( macb->phy_addr != phy_adr )
return -1;
macb_mdio_write(macb, reg, value);
return 0;
}
#endif
#if defined(CONFIG_CMD_NET)
static int macb_send(struct eth_device *netdev, volatile void *packet,
int length)
{
struct macb_device *macb = to_macb(netdev);
unsigned long paddr, ctrl;
unsigned int tx_head = macb->tx_head;
int i;
paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
ctrl = length & TXBUF_FRMLEN_MASK;
ctrl |= TXBUF_FRAME_END;
if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) {
ctrl |= TXBUF_WRAP;
macb->tx_head = 0;
} else
macb->tx_head++;
macb->tx_ring[tx_head].ctrl = ctrl;
macb->tx_ring[tx_head].addr = paddr;
barrier();
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
/*
* I guess this is necessary because the networking core may
* re-use the transmit buffer as soon as we return...
*/
for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) {
barrier();
ctrl = macb->tx_ring[tx_head].ctrl;
if (ctrl & TXBUF_USED)
break;
udelay(1);
}
dma_unmap_single(packet, length, paddr);
if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) {
if (ctrl & TXBUF_UNDERRUN)
printf("%s: TX underrun\n", netdev->name);
if (ctrl & TXBUF_EXHAUSTED)
printf("%s: TX buffers exhausted in mid frame\n",
netdev->name);
} else {
printf("%s: TX timeout\n", netdev->name);
}
/* No one cares anyway */
return 0;
}
static void reclaim_rx_buffers(struct macb_device *macb,
unsigned int new_tail)
{
unsigned int i;
i = macb->rx_tail;
while (i > new_tail) {
macb->rx_ring[i].addr &= ~RXADDR_USED;
i++;
if (i > CONFIG_SYS_MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
macb->rx_ring[i].addr &= ~RXADDR_USED;
i++;
}
barrier();
macb->rx_tail = new_tail;
}
static int macb_recv(struct eth_device *netdev)
{
struct macb_device *macb = to_macb(netdev);
unsigned int rx_tail = macb->rx_tail;
void *buffer;
int length;
int wrapped = 0;
u32 status;
for (;;) {
if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
return -1;
status = macb->rx_ring[rx_tail].ctrl;
if (status & RXBUF_FRAME_START) {
if (rx_tail != macb->rx_tail)
reclaim_rx_buffers(macb, rx_tail);
wrapped = 0;
}
if (status & RXBUF_FRAME_END) {
buffer = macb->rx_buffer + 128 * macb->rx_tail;
length = status & RXBUF_FRMLEN_MASK;
if (wrapped) {
unsigned int headlen, taillen;
headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE
- macb->rx_tail);
taillen = length - headlen;
memcpy((void *)NetRxPackets[0],
buffer, headlen);
memcpy((void *)NetRxPackets[0] + headlen,
macb->rx_buffer, taillen);
buffer = (void *)NetRxPackets[0];
}
NetReceive(buffer, length);
if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE)
rx_tail = 0;
reclaim_rx_buffers(macb, rx_tail);
} else {
if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) {
wrapped = 1;
rx_tail = 0;
}
}
barrier();
}
return 0;
}
static void macb_phy_reset(struct macb_device *macb)
{
struct eth_device *netdev = &macb->netdev;
int i;
u16 status, adv;
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
macb_mdio_write(macb, MII_ADVERTISE, adv);
printf("%s: Starting autonegotiation...\n", netdev->name);
macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
| BMCR_ANRESTART));
for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
status = macb_mdio_read(macb, MII_BMSR);
if (status & BMSR_ANEGCOMPLETE)
break;
udelay(100);
}
if (status & BMSR_ANEGCOMPLETE)
printf("%s: Autonegotiation complete\n", netdev->name);
else
printf("%s: Autonegotiation timed out (status=0x%04x)\n",
netdev->name, status);
}
#ifdef CONFIG_MACB_SEARCH_PHY
static int macb_phy_find(struct macb_device *macb)
{
int i;
u16 phy_id;
/* Search for PHY... */
for (i = 0; i < 32; i++) {
macb->phy_addr = i;
phy_id = macb_mdio_read(macb, MII_PHYSID1);
if (phy_id != 0xffff) {
printf("%s: PHY present at %d\n", macb->netdev.name, i);
return 1;
}
}
/* PHY isn't up to snuff */
printf("%s: PHY not found", macb->netdev.name);
return 0;
}
#endif /* CONFIG_MACB_SEARCH_PHY */
static int macb_phy_init(struct macb_device *macb)
{
struct eth_device *netdev = &macb->netdev;
u32 ncfgr;
u16 phy_id, status, adv, lpa;
int media, speed, duplex;
int i;
#ifdef CONFIG_MACB_SEARCH_PHY
/* Auto-detect phy_addr */
if (!macb_phy_find(macb)) {
return 0;
}
#endif /* CONFIG_MACB_SEARCH_PHY */
/* Check if the PHY is up to snuff... */
phy_id = macb_mdio_read(macb, MII_PHYSID1);
if (phy_id == 0xffff) {
printf("%s: No PHY present\n", netdev->name);
return 0;
}
status = macb_mdio_read(macb, MII_BMSR);
if (!(status & BMSR_LSTATUS)) {
/* Try to re-negotiate if we don't have link already. */
macb_phy_reset(macb);
for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
status = macb_mdio_read(macb, MII_BMSR);
if (status & BMSR_LSTATUS)
break;
udelay(100);
}
}
if (!(status & BMSR_LSTATUS)) {
printf("%s: link down (status: 0x%04x)\n",
netdev->name, status);
return 0;
} else {
adv = macb_mdio_read(macb, MII_ADVERTISE);
lpa = macb_mdio_read(macb, MII_LPA);
media = mii_nway_result(lpa & adv);
speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
? 1 : 0);
duplex = (media & ADVERTISE_FULL) ? 1 : 0;
printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
netdev->name,
speed ? "100" : "10",
duplex ? "full" : "half",
lpa);
ncfgr = macb_readl(macb, NCFGR);
ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
if (speed)
ncfgr |= MACB_BIT(SPD);
if (duplex)
ncfgr |= MACB_BIT(FD);
macb_writel(macb, NCFGR, ncfgr);
return 1;
}
}
static int macb_init(struct eth_device *netdev, bd_t *bd)
{
struct macb_device *macb = to_macb(netdev);
unsigned long paddr;
int i;
/*
* macb_halt should have been called at some point before now,
* so we'll assume the controller is idle.
*/
/* initialize DMA descriptors */
paddr = macb->rx_buffer_dma;
for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) {
if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1))
paddr |= RXADDR_WRAP;
macb->rx_ring[i].addr = paddr;
macb->rx_ring[i].ctrl = 0;
paddr += 128;
}
for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) {
macb->tx_ring[i].addr = 0;
if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1))
macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
else
macb->tx_ring[i].ctrl = TXBUF_USED;
}
macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
macb_writel(macb, RBQP, macb->rx_ring_dma);
macb_writel(macb, TBQP, macb->tx_ring_dma);
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_RMII
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
defined(CONFIG_AT91SAM9XE)
macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, 0);
#endif
#else
#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
defined(CONFIG_AT91SAM9XE)
macb_writel(macb, USRIO, MACB_BIT(CLKEN));
#else
macb_writel(macb, USRIO, MACB_BIT(MII));
#endif
#endif /* CONFIG_RMII */
if (!macb_phy_init(macb))
return -1;
/* Enable TX and RX */
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
return 0;
}
static void macb_halt(struct eth_device *netdev)
{
struct macb_device *macb = to_macb(netdev);
u32 ncr, tsr;
/* Halt the controller and wait for any ongoing transmission to end. */
ncr = macb_readl(macb, NCR);
ncr |= MACB_BIT(THALT);
macb_writel(macb, NCR, ncr);
do {
tsr = macb_readl(macb, TSR);
} while (tsr & MACB_BIT(TGO));
/* Disable TX and RX, and clear statistics */
macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
}
static int macb_write_hwaddr(struct eth_device *dev)
{
struct macb_device *macb = to_macb(dev);
u32 hwaddr_bottom;
u16 hwaddr_top;
/* set hardware address */
hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 |
dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24;
macb_writel(macb, SA1B, hwaddr_bottom);
hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8;
macb_writel(macb, SA1T, hwaddr_top);
return 0;
}
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
struct eth_device *netdev;
unsigned long macb_hz;
u32 ncfgr;
macb = malloc(sizeof(struct macb_device));
if (!macb) {
printf("Error: Failed to allocate memory for MACB%d\n", id);
return -1;
}
memset(macb, 0, sizeof(struct macb_device));
netdev = &macb->netdev;
macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE,
&macb->rx_buffer_dma);
macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE
* sizeof(struct macb_dma_desc),
&macb->rx_ring_dma);
macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE
* sizeof(struct macb_dma_desc),
&macb->tx_ring_dma);
macb->regs = regs;
macb->phy_addr = phy_addr;
sprintf(netdev->name, "macb%d", id);
netdev->init = macb_init;
netdev->halt = macb_halt;
netdev->send = macb_send;
netdev->recv = macb_recv;
netdev->write_hwaddr = macb_write_hwaddr;
/*
* Do some basic initialization so that we at least can talk
* to the PHY
*/
macb_hz = get_macb_pclk_rate(id);
if (macb_hz < 20000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
else if (macb_hz < 40000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
else if (macb_hz < 80000000)
ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
else
ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
macb_writel(macb, NCFGR, ncfgr);
eth_register(netdev);
#if defined(CONFIG_CMD_MII)
miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write);
#endif
return 0;
}
#endif
|
1001-study-uboot
|
drivers/net/macb.c
|
C
|
gpl3
| 15,026
|
/*
* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
*
* Copyright (C) 2004, 2005
* Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _EP93XX_ETH_H
#define _EP93XX_ETH_H
#include <net.h>
/**
* #define this to dump device status and queue info during initialization and
* following errors.
*/
#undef EP93XX_MAC_DEBUG
/**
* Number of descriptor and status entries in our RX queues.
* It must be power of 2 !
*/
#define NUMRXDESC PKTBUFSRX
/**
* Number of descriptor and status entries in our TX queues.
*/
#define NUMTXDESC 1
/**
* 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
*/
#define TXSTARTMAX 944
/**
* Receive descriptor queue entry
*/
struct rx_descriptor {
uint32_t word1;
uint32_t word2;
};
/**
* Receive status queue entry
*/
struct rx_status {
uint32_t word1;
uint32_t word2;
};
#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
/**
* Transmit descriptor queue entry
*/
struct tx_descriptor {
uint32_t word1;
uint32_t word2;
};
#define TX_DESC_EOF (1 << 31)
/**
* Transmit status queue entry
*/
struct tx_status {
uint32_t word1;
};
#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
/**
* Transmit descriptor queue
*/
struct tx_descriptor_queue {
struct tx_descriptor *base;
struct tx_descriptor *current;
struct tx_descriptor *end;
};
/**
* Transmit status queue
*/
struct tx_status_queue {
struct tx_status *base;
volatile struct tx_status *current;
struct tx_status *end;
};
/**
* Receive descriptor queue
*/
struct rx_descriptor_queue {
struct rx_descriptor *base;
struct rx_descriptor *current;
struct rx_descriptor *end;
};
/**
* Receive status queue
*/
struct rx_status_queue {
struct rx_status *base;
volatile struct rx_status *current;
struct rx_status *end;
};
/**
* EP93xx MAC private data structure
*/
struct ep93xx_priv {
struct rx_descriptor_queue rx_dq;
struct rx_status_queue rx_sq;
void *rx_buffer[NUMRXDESC];
struct tx_descriptor_queue tx_dq;
struct tx_status_queue tx_sq;
struct mac_regs *regs;
};
#endif
|
1001-study-uboot
|
drivers/net/ep93xx_eth.h
|
C
|
gpl3
| 3,122
|
/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
*
* (C) Copyright 2007
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define GRETH_FD 0x10
#define GRETH_RESET 0x40
#define GRETH_MII_BUSY 0x8
#define GRETH_MII_NVALID 0x10
/* MII registers */
#define GRETH_MII_EXTADV_1000FD 0x00000200
#define GRETH_MII_EXTADV_1000HD 0x00000100
#define GRETH_MII_EXTPRT_1000FD 0x00000800
#define GRETH_MII_EXTPRT_1000HD 0x00000400
#define GRETH_MII_100T4 0x00000200
#define GRETH_MII_100TXFD 0x00000100
#define GRETH_MII_100TXHD 0x00000080
#define GRETH_MII_10FD 0x00000040
#define GRETH_MII_10HD 0x00000020
#define GRETH_BD_EN 0x800
#define GRETH_BD_WR 0x1000
#define GRETH_BD_IE 0x2000
#define GRETH_BD_LEN 0x7FF
#define GRETH_TXEN 0x1
#define GRETH_INT_TX 0x8
#define GRETH_TXI 0x4
#define GRETH_TXBD_STATUS 0x0001C000
#define GRETH_TXBD_MORE 0x20000
#define GRETH_TXBD_IPCS 0x40000
#define GRETH_TXBD_TCPCS 0x80000
#define GRETH_TXBD_UDPCS 0x100000
#define GRETH_TXBD_ERR_LC 0x10000
#define GRETH_TXBD_ERR_UE 0x4000
#define GRETH_TXBD_ERR_AL 0x8000
#define GRETH_TXBD_NUM 128
#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1)
#define GRETH_TX_BUF_SIZE 2048
#define GRETH_INT_RX 0x4
#define GRETH_RXEN 0x2
#define GRETH_RXI 0x8
#define GRETH_RXBD_STATUS 0xFFFFC000
#define GRETH_RXBD_ERR_AE 0x4000
#define GRETH_RXBD_ERR_FT 0x8000
#define GRETH_RXBD_ERR_CRC 0x10000
#define GRETH_RXBD_ERR_OE 0x20000
#define GRETH_RXBD_ERR_LE 0x40000
#define GRETH_RXBD_IP_DEC 0x80000
#define GRETH_RXBD_IP_CSERR 0x100000
#define GRETH_RXBD_UDP_DEC 0x200000
#define GRETH_RXBD_UDP_CSERR 0x400000
#define GRETH_RXBD_TCP_DEC 0x800000
#define GRETH_RXBD_TCP_CSERR 0x1000000
#define GRETH_RXBD_NUM 128
#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1)
#define GRETH_RX_BUF_SIZE 2048
/* Ethernet configuration registers */
typedef struct _greth_regs {
volatile unsigned int control;
volatile unsigned int status;
volatile unsigned int esa_msb;
volatile unsigned int esa_lsb;
volatile unsigned int mdio;
volatile unsigned int tx_desc_p;
volatile unsigned int rx_desc_p;
} greth_regs;
/* Ethernet buffer descriptor */
typedef struct _greth_bd {
volatile unsigned int stat;
unsigned int addr; /* Buffer address not changed by HW */
} greth_bd;
|
1001-study-uboot
|
drivers/net/greth.h
|
C
|
gpl3
| 3,088
|
/*
* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
*
* Based on: mach-davinci/emac_defs.h
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _DAVINCI_EMAC_H_
#define _DAVINCI_EMAC_H_
/* Ethernet Min/Max packet size */
#define EMAC_MIN_ETHERNET_PKT_SIZE 60
#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
/* Buffer size (should be aligned on 32 byte and cache line) */
#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
ARCH_DMA_MINALIGN)
/* Number of RX packet buffers
* NOTE: Only 1 buffer supported as of now
*/
#define EMAC_MAX_RX_BUFFERS 10
/***********************************************
******** Internally used macros ***************
***********************************************/
#define EMAC_CH_TX 1
#define EMAC_CH_RX 0
/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
* reserve space for 64 descriptors max
*/
#define EMAC_RX_DESC_BASE 0x0
#define EMAC_TX_DESC_BASE 0x1000
/* EMAC Teardown value */
#define EMAC_TEARDOWN_VALUE 0xfffffffc
/* MII Status Register */
#define MII_STATUS_REG 1
/* Number of statistics registers */
#define EMAC_NUM_STATS 36
/* EMAC Descriptor */
typedef volatile struct _emac_desc
{
u_int32_t next; /* Pointer to next descriptor
in chain */
u_int8_t *buffer; /* Pointer to data buffer */
u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
} emac_desc;
/* CPPI bit positions */
#define EMAC_CPPI_SOP_BIT (0x80000000)
#define EMAC_CPPI_EOP_BIT (0x40000000)
#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
#define EMAC_CPPI_EOQ_BIT (0x10000000)
#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
#define EMAC_MAC_ADDR_MATCH (1 << 19)
#define EMAC_MAC_ADDR_IS_VALID (1 << 20)
#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
#define MDIO_CONTROL_IDLE (0x80000000)
#define MDIO_CONTROL_ENABLE (0x40000000)
#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
#define MDIO_CONTROL_FAULT (0x80000)
#define MDIO_USERACCESS0_GO (0x80000000)
#define MDIO_USERACCESS0_WRITE_READ (0x0)
#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
#define MDIO_USERACCESS0_ACK (0x20000000)
/* Ethernet MAC Registers Structure */
typedef struct {
dv_reg TXIDVER;
dv_reg TXCONTROL;
dv_reg TXTEARDOWN;
u_int8_t RSVD0[4];
dv_reg RXIDVER;
dv_reg RXCONTROL;
dv_reg RXTEARDOWN;
u_int8_t RSVD1[100];
dv_reg TXINTSTATRAW;
dv_reg TXINTSTATMASKED;
dv_reg TXINTMASKSET;
dv_reg TXINTMASKCLEAR;
dv_reg MACINVECTOR;
u_int8_t RSVD2[12];
dv_reg RXINTSTATRAW;
dv_reg RXINTSTATMASKED;
dv_reg RXINTMASKSET;
dv_reg RXINTMASKCLEAR;
dv_reg MACINTSTATRAW;
dv_reg MACINTSTATMASKED;
dv_reg MACINTMASKSET;
dv_reg MACINTMASKCLEAR;
u_int8_t RSVD3[64];
dv_reg RXMBPENABLE;
dv_reg RXUNICASTSET;
dv_reg RXUNICASTCLEAR;
dv_reg RXMAXLEN;
dv_reg RXBUFFEROFFSET;
dv_reg RXFILTERLOWTHRESH;
u_int8_t RSVD4[8];
dv_reg RX0FLOWTHRESH;
dv_reg RX1FLOWTHRESH;
dv_reg RX2FLOWTHRESH;
dv_reg RX3FLOWTHRESH;
dv_reg RX4FLOWTHRESH;
dv_reg RX5FLOWTHRESH;
dv_reg RX6FLOWTHRESH;
dv_reg RX7FLOWTHRESH;
dv_reg RX0FREEBUFFER;
dv_reg RX1FREEBUFFER;
dv_reg RX2FREEBUFFER;
dv_reg RX3FREEBUFFER;
dv_reg RX4FREEBUFFER;
dv_reg RX5FREEBUFFER;
dv_reg RX6FREEBUFFER;
dv_reg RX7FREEBUFFER;
dv_reg MACCONTROL;
dv_reg MACSTATUS;
dv_reg EMCONTROL;
dv_reg FIFOCONTROL;
dv_reg MACCONFIG;
dv_reg SOFTRESET;
u_int8_t RSVD5[88];
dv_reg MACSRCADDRLO;
dv_reg MACSRCADDRHI;
dv_reg MACHASH1;
dv_reg MACHASH2;
dv_reg BOFFTEST;
dv_reg TPACETEST;
dv_reg RXPAUSE;
dv_reg TXPAUSE;
u_int8_t RSVD6[16];
dv_reg RXGOODFRAMES;
dv_reg RXBCASTFRAMES;
dv_reg RXMCASTFRAMES;
dv_reg RXPAUSEFRAMES;
dv_reg RXCRCERRORS;
dv_reg RXALIGNCODEERRORS;
dv_reg RXOVERSIZED;
dv_reg RXJABBER;
dv_reg RXUNDERSIZED;
dv_reg RXFRAGMENTS;
dv_reg RXFILTERED;
dv_reg RXQOSFILTERED;
dv_reg RXOCTETS;
dv_reg TXGOODFRAMES;
dv_reg TXBCASTFRAMES;
dv_reg TXMCASTFRAMES;
dv_reg TXPAUSEFRAMES;
dv_reg TXDEFERRED;
dv_reg TXCOLLISION;
dv_reg TXSINGLECOLL;
dv_reg TXMULTICOLL;
dv_reg TXEXCESSIVECOLL;
dv_reg TXLATECOLL;
dv_reg TXUNDERRUN;
dv_reg TXCARRIERSENSE;
dv_reg TXOCTETS;
dv_reg FRAME64;
dv_reg FRAME65T127;
dv_reg FRAME128T255;
dv_reg FRAME256T511;
dv_reg FRAME512T1023;
dv_reg FRAME1024TUP;
dv_reg NETOCTETS;
dv_reg RXSOFOVERRUNS;
dv_reg RXMOFOVERRUNS;
dv_reg RXDMAOVERRUNS;
u_int8_t RSVD7[624];
dv_reg MACADDRLO;
dv_reg MACADDRHI;
dv_reg MACINDEX;
u_int8_t RSVD8[244];
dv_reg TX0HDP;
dv_reg TX1HDP;
dv_reg TX2HDP;
dv_reg TX3HDP;
dv_reg TX4HDP;
dv_reg TX5HDP;
dv_reg TX6HDP;
dv_reg TX7HDP;
dv_reg RX0HDP;
dv_reg RX1HDP;
dv_reg RX2HDP;
dv_reg RX3HDP;
dv_reg RX4HDP;
dv_reg RX5HDP;
dv_reg RX6HDP;
dv_reg RX7HDP;
dv_reg TX0CP;
dv_reg TX1CP;
dv_reg TX2CP;
dv_reg TX3CP;
dv_reg TX4CP;
dv_reg TX5CP;
dv_reg TX6CP;
dv_reg TX7CP;
dv_reg RX0CP;
dv_reg RX1CP;
dv_reg RX2CP;
dv_reg RX3CP;
dv_reg RX4CP;
dv_reg RX5CP;
dv_reg RX6CP;
dv_reg RX7CP;
} emac_regs;
/* EMAC Wrapper Registers Structure */
typedef struct {
#ifdef DAVINCI_EMAC_VERSION2
dv_reg idver;
dv_reg softrst;
dv_reg emctrl;
dv_reg c0rxthreshen;
dv_reg c0rxen;
dv_reg c0txen;
dv_reg c0miscen;
dv_reg c1rxthreshen;
dv_reg c1rxen;
dv_reg c1txen;
dv_reg c1miscen;
dv_reg c2rxthreshen;
dv_reg c2rxen;
dv_reg c2txen;
dv_reg c2miscen;
dv_reg c0rxthreshstat;
dv_reg c0rxstat;
dv_reg c0txstat;
dv_reg c0miscstat;
dv_reg c1rxthreshstat;
dv_reg c1rxstat;
dv_reg c1txstat;
dv_reg c1miscstat;
dv_reg c2rxthreshstat;
dv_reg c2rxstat;
dv_reg c2txstat;
dv_reg c2miscstat;
dv_reg c0rximax;
dv_reg c0tximax;
dv_reg c1rximax;
dv_reg c1tximax;
dv_reg c2rximax;
dv_reg c2tximax;
#else
u_int8_t RSVD0[4100];
dv_reg EWCTL;
dv_reg EWINTTCNT;
#endif
} ewrap_regs;
/* EMAC MDIO Registers Structure */
typedef struct {
dv_reg VERSION;
dv_reg CONTROL;
dv_reg ALIVE;
dv_reg LINK;
dv_reg LINKINTRAW;
dv_reg LINKINTMASKED;
u_int8_t RSVD0[8];
dv_reg USERINTRAW;
dv_reg USERINTMASKED;
dv_reg USERINTMASKSET;
dv_reg USERINTMASKCLEAR;
u_int8_t RSVD1[80];
dv_reg USERACCESS0;
dv_reg USERPHYSEL0;
dv_reg USERACCESS1;
dv_reg USERPHYSEL1;
} mdio_regs;
int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
typedef struct {
char name[64];
int (*init)(int phy_addr);
int (*is_phy_connected)(int phy_addr);
int (*get_link_speed)(int phy_addr);
int (*auto_negotiate)(int phy_addr);
} phy_t;
#endif /* _DAVINCI_EMAC_H_ */
|
1001-study-uboot
|
drivers/net/davinci_emac.h
|
C
|
gpl3
| 7,771
|
/* Gaisler.com GRETH 10/100/1000 Ethernet MAC driver
*
* Driver use polling mode (no Interrupt)
*
* (C) Copyright 2007
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* #define DEBUG */
#include <common.h>
#include <command.h>
#include <net.h>
#include <netdev.h>
#include <malloc.h>
#include <asm/processor.h>
#include <ambapp.h>
#include <asm/leon.h>
#include "greth.h"
/* Default to 3s timeout on autonegotiation */
#ifndef GRETH_PHY_TIMEOUT_MS
#define GRETH_PHY_TIMEOUT_MS 3000
#endif
/* Default to PHY adrress 0 not not specified */
#ifdef CONFIG_SYS_GRLIB_GRETH_PHYADDR
#define GRETH_PHY_ADR_DEFAULT CONFIG_SYS_GRLIB_GRETH_PHYADDR
#else
#define GRETH_PHY_ADR_DEFAULT 0
#endif
/* ByPass Cache when reading regs */
#define GRETH_REGLOAD(addr) SPARC_NOCACHE_READ(addr)
/* Write-through cache ==> no bypassing needed on writes */
#define GRETH_REGSAVE(addr,data) (*(volatile unsigned int *)(addr) = (data))
#define GRETH_REGORIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)|data)
#define GRETH_REGANDIN(addr,data) GRETH_REGSAVE(addr,GRETH_REGLOAD(addr)&data)
#define GRETH_RXBD_CNT 4
#define GRETH_TXBD_CNT 1
#define GRETH_RXBUF_SIZE 1540
#define GRETH_BUF_ALIGN 4
#define GRETH_RXBUF_EFF_SIZE \
( (GRETH_RXBUF_SIZE&~(GRETH_BUF_ALIGN-1))+GRETH_BUF_ALIGN )
typedef struct {
greth_regs *regs;
int irq;
struct eth_device *dev;
/* Hardware info */
unsigned char phyaddr;
int gbit_mac;
/* Current operating Mode */
int gb; /* GigaBit */
int fd; /* Full Duplex */
int sp; /* 10/100Mbps speed (1=100,0=10) */
int auto_neg; /* Auto negotiate done */
unsigned char hwaddr[6]; /* MAC Address */
/* Descriptors */
greth_bd *rxbd_base, *rxbd_max;
greth_bd *txbd_base, *txbd_max;
greth_bd *rxbd_curr;
/* rx buffers in rx descriptors */
void *rxbuf_base; /* (GRETH_RXBUF_SIZE+ALIGNBYTES) * GRETH_RXBD_CNT */
/* unused for gbit_mac, temp buffer for sending packets with unligned
* start.
* Pointer to packet allocated with malloc.
*/
void *txbuf;
struct {
/* rx status */
unsigned int rx_packets,
rx_crc_errors, rx_frame_errors, rx_length_errors, rx_errors;
/* tx stats */
unsigned int tx_packets,
tx_latecol_errors,
tx_underrun_errors, tx_limit_errors, tx_errors;
} stats;
} greth_priv;
/* Read MII register 'addr' from core 'regs' */
static int read_mii(int phyaddr, int regaddr, volatile greth_regs * regs)
{
while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
}
GRETH_REGSAVE(®s->mdio, ((phyaddr & 0x1F) << 11) | ((regaddr & 0x1F) << 6) | 2);
while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
}
if (!(GRETH_REGLOAD(®s->mdio) & GRETH_MII_NVALID)) {
return (GRETH_REGLOAD(®s->mdio) >> 16) & 0xFFFF;
} else {
return -1;
}
}
static void write_mii(int phyaddr, int regaddr, int data, volatile greth_regs * regs)
{
while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
}
GRETH_REGSAVE(®s->mdio,
((data & 0xFFFF) << 16) | ((phyaddr & 0x1F) << 11) |
((regaddr & 0x1F) << 6) | 1);
while (GRETH_REGLOAD(®s->mdio) & GRETH_MII_BUSY) {
}
}
/* init/start hardware and allocate descriptor buffers for rx side
*
*/
int greth_init(struct eth_device *dev, bd_t * bis)
{
int i;
greth_priv *greth = dev->priv;
greth_regs *regs = greth->regs;
debug("greth_init\n");
/* Reset core */
GRETH_REGSAVE(®s->control, (GRETH_RESET | (greth->gb << 8) |
(greth->sp << 7) | (greth->fd << 4)));
/* Wait for Reset to complete */
while ( GRETH_REGLOAD(®s->control) & GRETH_RESET) ;
GRETH_REGSAVE(®s->control,
((greth->gb << 8) | (greth->sp << 7) | (greth->fd << 4)));
if (!greth->rxbd_base) {
/* allocate descriptors */
greth->rxbd_base = (greth_bd *)
memalign(0x1000, GRETH_RXBD_CNT * sizeof(greth_bd));
greth->txbd_base = (greth_bd *)
memalign(0x1000, GRETH_TXBD_CNT * sizeof(greth_bd));
/* allocate buffers to all descriptors */
greth->rxbuf_base =
malloc(GRETH_RXBUF_EFF_SIZE * GRETH_RXBD_CNT);
}
/* initate rx decriptors */
for (i = 0; i < GRETH_RXBD_CNT; i++) {
greth->rxbd_base[i].addr = (unsigned int)
greth->rxbuf_base + (GRETH_RXBUF_EFF_SIZE * i);
/* enable desciptor & set wrap bit if last descriptor */
if (i >= (GRETH_RXBD_CNT - 1)) {
greth->rxbd_base[i].stat = GRETH_BD_EN | GRETH_BD_WR;
} else {
greth->rxbd_base[i].stat = GRETH_BD_EN;
}
}
/* initiate indexes */
greth->rxbd_curr = greth->rxbd_base;
greth->rxbd_max = greth->rxbd_base + (GRETH_RXBD_CNT - 1);
greth->txbd_max = greth->txbd_base + (GRETH_TXBD_CNT - 1);
/*
* greth->txbd_base->addr = 0;
* greth->txbd_base->stat = GRETH_BD_WR;
*/
/* initate tx decriptors */
for (i = 0; i < GRETH_TXBD_CNT; i++) {
greth->txbd_base[i].addr = 0;
/* enable desciptor & set wrap bit if last descriptor */
if (i >= (GRETH_TXBD_CNT - 1)) {
greth->txbd_base[i].stat = GRETH_BD_WR;
} else {
greth->txbd_base[i].stat = 0;
}
}
/**** SET HARDWARE REGS ****/
/* Set pointer to tx/rx descriptor areas */
GRETH_REGSAVE(®s->rx_desc_p, (unsigned int)&greth->rxbd_base[0]);
GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)&greth->txbd_base[0]);
/* Enable Transmitter, GRETH will now scan descriptors for packets
* to transmitt */
debug("greth_init: enabling receiver\n");
GRETH_REGORIN(®s->control, GRETH_RXEN);
return 0;
}
/* Initiate PHY to a relevant speed
* return:
* - 0 = success
* - 1 = timeout/fail
*/
int greth_init_phy(greth_priv * dev, bd_t * bis)
{
greth_regs *regs = dev->regs;
int tmp, tmp1, tmp2, i;
unsigned int start, timeout;
int phyaddr = GRETH_PHY_ADR_DEFAULT;
#ifndef CONFIG_SYS_GRLIB_GRETH_PHYADDR
/* If BSP doesn't provide a hardcoded PHY address the driver will
* try to autodetect PHY address by stopping the search on the first
* PHY address which has REG0 implemented.
*/
for (i=0; i<32; i++) {
tmp = read_mii(i, 0, regs);
if ( (tmp != 0) && (tmp != 0xffff) ) {
phyaddr = i;
break;
}
}
#endif
/* Save PHY Address */
dev->phyaddr = phyaddr;
debug("GRETH PHY ADDRESS: %d\n", phyaddr);
/* X msecs to ticks */
timeout = usec2ticks(GRETH_PHY_TIMEOUT_MS * 1000);
/* Get system timer0 current value
* Total timeout is 5s
*/
start = get_timer(0);
/* get phy control register default values */
while ((tmp = read_mii(phyaddr, 0, regs)) & 0x8000) {
if (get_timer(start) > timeout) {
debug("greth_init_phy: PHY read 1 failed\n");
return 1; /* Fail */
}
}
/* reset PHY and wait for completion */
write_mii(phyaddr, 0, 0x8000 | tmp, regs);
while (((tmp = read_mii(phyaddr, 0, regs))) & 0x8000) {
if (get_timer(start) > timeout) {
debug("greth_init_phy: PHY read 2 failed\n");
return 1; /* Fail */
}
}
/* Check if PHY is autoneg capable and then determine operating
* mode, otherwise force it to 10 Mbit halfduplex
*/
dev->gb = 0;
dev->fd = 0;
dev->sp = 0;
dev->auto_neg = 0;
if (!((tmp >> 12) & 1)) {
write_mii(phyaddr, 0, 0, regs);
} else {
/* wait for auto negotiation to complete and then check operating mode */
dev->auto_neg = 1;
i = 0;
while (!(((tmp = read_mii(phyaddr, 1, regs)) >> 5) & 1)) {
if (get_timer(start) > timeout) {
printf("Auto negotiation timed out. "
"Selecting default config\n");
tmp = read_mii(phyaddr, 0, regs);
dev->gb = ((tmp >> 6) & 1)
&& !((tmp >> 13) & 1);
dev->sp = !((tmp >> 6) & 1)
&& ((tmp >> 13) & 1);
dev->fd = (tmp >> 8) & 1;
goto auto_neg_done;
}
}
if ((tmp >> 8) & 1) {
tmp1 = read_mii(phyaddr, 9, regs);
tmp2 = read_mii(phyaddr, 10, regs);
if ((tmp1 & GRETH_MII_EXTADV_1000FD) &&
(tmp2 & GRETH_MII_EXTPRT_1000FD)) {
dev->gb = 1;
dev->fd = 1;
}
if ((tmp1 & GRETH_MII_EXTADV_1000HD) &&
(tmp2 & GRETH_MII_EXTPRT_1000HD)) {
dev->gb = 1;
dev->fd = 0;
}
}
if ((dev->gb == 0) || ((dev->gb == 1) && (dev->gbit_mac == 0))) {
tmp1 = read_mii(phyaddr, 4, regs);
tmp2 = read_mii(phyaddr, 5, regs);
if ((tmp1 & GRETH_MII_100TXFD) &&
(tmp2 & GRETH_MII_100TXFD)) {
dev->sp = 1;
dev->fd = 1;
}
if ((tmp1 & GRETH_MII_100TXHD) &&
(tmp2 & GRETH_MII_100TXHD)) {
dev->sp = 1;
dev->fd = 0;
}
if ((tmp1 & GRETH_MII_10FD) && (tmp2 & GRETH_MII_10FD)) {
dev->fd = 1;
}
if ((dev->gb == 1) && (dev->gbit_mac == 0)) {
dev->gb = 0;
dev->fd = 0;
write_mii(phyaddr, 0, dev->sp << 13, regs);
}
}
}
auto_neg_done:
debug("%s GRETH Ethermac at [0x%x] irq %d. Running \
%d Mbps %s duplex\n", dev->gbit_mac ? "10/100/1000" : "10/100", (unsigned int)(regs), (unsigned int)(dev->irq), dev->gb ? 1000 : (dev->sp ? 100 : 10), dev->fd ? "full" : "half");
/* Read out PHY info if extended registers are available */
if (tmp & 1) {
tmp1 = read_mii(phyaddr, 2, regs);
tmp2 = read_mii(phyaddr, 3, regs);
tmp1 = (tmp1 << 6) | ((tmp2 >> 10) & 0x3F);
tmp = tmp2 & 0xF;
tmp2 = (tmp2 >> 4) & 0x3F;
debug("PHY: Vendor %x Device %x Revision %d\n", tmp1,
tmp2, tmp);
} else {
printf("PHY info not available\n");
}
/* set speed and duplex bits in control register */
GRETH_REGORIN(®s->control,
(dev->gb << 8) | (dev->sp << 7) | (dev->fd << 4));
return 0;
}
void greth_halt(struct eth_device *dev)
{
greth_priv *greth;
greth_regs *regs;
int i;
debug("greth_halt\n");
if (!dev || !dev->priv)
return;
greth = dev->priv;
regs = greth->regs;
if (!regs)
return;
/* disable receiver/transmitter by clearing the enable bits */
GRETH_REGANDIN(®s->control, ~(GRETH_RXEN | GRETH_TXEN));
/* reset rx/tx descriptors */
if (greth->rxbd_base) {
for (i = 0; i < GRETH_RXBD_CNT; i++) {
greth->rxbd_base[i].stat =
(i >= (GRETH_RXBD_CNT - 1)) ? GRETH_BD_WR : 0;
}
}
if (greth->txbd_base) {
for (i = 0; i < GRETH_TXBD_CNT; i++) {
greth->txbd_base[i].stat =
(i >= (GRETH_TXBD_CNT - 1)) ? GRETH_BD_WR : 0;
}
}
}
int greth_send(struct eth_device *dev, volatile void *eth_data, int data_length)
{
greth_priv *greth = dev->priv;
greth_regs *regs = greth->regs;
greth_bd *txbd;
void *txbuf;
unsigned int status;
debug("greth_send\n");
/* send data, wait for data to be sent, then return */
if (((unsigned int)eth_data & (GRETH_BUF_ALIGN - 1))
&& !greth->gbit_mac) {
/* data not aligned as needed by GRETH 10/100, solve this by allocating 4 byte aligned buffer
* and copy data to before giving it to GRETH.
*/
if (!greth->txbuf) {
greth->txbuf = malloc(GRETH_RXBUF_SIZE);
}
txbuf = greth->txbuf;
/* copy data info buffer */
memcpy((char *)txbuf, (char *)eth_data, data_length);
/* keep buffer to next time */
} else {
txbuf = (void *)eth_data;
}
/* get descriptor to use, only 1 supported... hehe easy */
txbd = greth->txbd_base;
/* setup descriptor to wrap around to it self */
txbd->addr = (unsigned int)txbuf;
txbd->stat = GRETH_BD_EN | GRETH_BD_WR | data_length;
/* Remind Core which descriptor to use when sending */
GRETH_REGSAVE(®s->tx_desc_p, (unsigned int)txbd);
/* initate send by enabling transmitter */
GRETH_REGORIN(®s->control, GRETH_TXEN);
/* Wait for data to be sent */
while ((status = GRETH_REGLOAD(&txbd->stat)) & GRETH_BD_EN) {
;
}
/* was the packet transmitted succesfully? */
if (status & GRETH_TXBD_ERR_AL) {
greth->stats.tx_limit_errors++;
}
if (status & GRETH_TXBD_ERR_UE) {
greth->stats.tx_underrun_errors++;
}
if (status & GRETH_TXBD_ERR_LC) {
greth->stats.tx_latecol_errors++;
}
if (status &
(GRETH_TXBD_ERR_LC | GRETH_TXBD_ERR_UE | GRETH_TXBD_ERR_AL)) {
/* any error */
greth->stats.tx_errors++;
return -1;
}
/* bump tx packet counter */
greth->stats.tx_packets++;
/* return succefully */
return 0;
}
int greth_recv(struct eth_device *dev)
{
greth_priv *greth = dev->priv;
greth_regs *regs = greth->regs;
greth_bd *rxbd;
unsigned int status, len = 0, bad;
unsigned char *d;
int enable = 0;
int i;
/* Receive One packet only, but clear as many error packets as there are
* available.
*/
{
/* current receive descriptor */
rxbd = greth->rxbd_curr;
/* get status of next received packet */
status = GRETH_REGLOAD(&rxbd->stat);
bad = 0;
/* stop if no more packets received */
if (status & GRETH_BD_EN) {
goto done;
}
debug("greth_recv: packet 0x%lx, 0x%lx, len: %d\n",
(unsigned int)rxbd, status, status & GRETH_BD_LEN);
/* Check status for errors.
*/
if (status & GRETH_RXBD_ERR_FT) {
greth->stats.rx_length_errors++;
bad = 1;
}
if (status & (GRETH_RXBD_ERR_AE | GRETH_RXBD_ERR_OE)) {
greth->stats.rx_frame_errors++;
bad = 1;
}
if (status & GRETH_RXBD_ERR_CRC) {
greth->stats.rx_crc_errors++;
bad = 1;
}
if (bad) {
greth->stats.rx_errors++;
printf
("greth_recv: Bad packet (%d, %d, %d, 0x%08x, %d)\n",
greth->stats.rx_length_errors,
greth->stats.rx_frame_errors,
greth->stats.rx_crc_errors, status,
greth->stats.rx_packets);
/* print all rx descriptors */
for (i = 0; i < GRETH_RXBD_CNT; i++) {
printf("[%d]: Stat=0x%lx, Addr=0x%lx\n", i,
GRETH_REGLOAD(&greth->rxbd_base[i].stat),
GRETH_REGLOAD(&greth->rxbd_base[i].addr));
}
} else {
/* Process the incoming packet. */
len = status & GRETH_BD_LEN;
d = (char *)rxbd->addr;
debug
("greth_recv: new packet, length: %d. data: %x %x %x %x %x %x %x %x\n",
len, d[0], d[1], d[2], d[3], d[4], d[5], d[6],
d[7]);
/* flush all data cache to make sure we're not reading old packet data */
sparc_dcache_flush_all();
/* pass packet on to network subsystem */
NetReceive((void *)d, len);
/* bump stats counters */
greth->stats.rx_packets++;
/* bad is now 0 ==> will stop loop */
}
/* reenable descriptor to receive more packet with this descriptor, wrap around if needed */
rxbd->stat =
GRETH_BD_EN |
(((unsigned int)greth->rxbd_curr >=
(unsigned int)greth->rxbd_max) ? GRETH_BD_WR : 0);
enable = 1;
/* increase index */
greth->rxbd_curr =
((unsigned int)greth->rxbd_curr >=
(unsigned int)greth->rxbd_max) ? greth->
rxbd_base : (greth->rxbd_curr + 1);
}
if (enable) {
GRETH_REGORIN(®s->control, GRETH_RXEN);
}
done:
/* return positive length of packet or 0 if non received */
return len;
}
void greth_set_hwaddr(greth_priv * greth, unsigned char *mac)
{
/* save new MAC address */
greth->dev->enetaddr[0] = greth->hwaddr[0] = mac[0];
greth->dev->enetaddr[1] = greth->hwaddr[1] = mac[1];
greth->dev->enetaddr[2] = greth->hwaddr[2] = mac[2];
greth->dev->enetaddr[3] = greth->hwaddr[3] = mac[3];
greth->dev->enetaddr[4] = greth->hwaddr[4] = mac[4];
greth->dev->enetaddr[5] = greth->hwaddr[5] = mac[5];
greth->regs->esa_msb = (mac[0] << 8) | mac[1];
greth->regs->esa_lsb =
(mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5];
debug("GRETH: New MAC address: %02x:%02x:%02x:%02x:%02x:%02x\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
}
int greth_initialize(bd_t * bis)
{
greth_priv *greth;
ambapp_apbdev apbdev;
struct eth_device *dev;
int i;
char *addr_str, *end;
unsigned char addr[6];
debug("Scanning for GRETH\n");
/* Find Device & IRQ via AMBA Plug&Play information */
if (ambapp_apb_first(VENDOR_GAISLER, GAISLER_ETHMAC, &apbdev) != 1) {
return -1; /* GRETH not found */
}
greth = (greth_priv *) malloc(sizeof(greth_priv));
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
memset(dev, 0, sizeof(struct eth_device));
memset(greth, 0, sizeof(greth_priv));
greth->regs = (greth_regs *) apbdev.address;
greth->irq = apbdev.irq;
debug("Found GRETH at 0x%lx, irq %d\n", greth->regs, greth->irq);
dev->priv = (void *)greth;
dev->iobase = (unsigned int)greth->regs;
dev->init = greth_init;
dev->halt = greth_halt;
dev->send = greth_send;
dev->recv = greth_recv;
greth->dev = dev;
/* Reset Core */
GRETH_REGSAVE(&greth->regs->control, GRETH_RESET);
/* Wait for core to finish reset cycle */
while (GRETH_REGLOAD(&greth->regs->control) & GRETH_RESET) ;
/* Get the phy address which assumed to have been set
correctly with the reset value in hardware */
greth->phyaddr = (GRETH_REGLOAD(&greth->regs->mdio) >> 11) & 0x1F;
/* Check if mac is gigabit capable */
greth->gbit_mac = (GRETH_REGLOAD(&greth->regs->control) >> 27) & 1;
/* Make descriptor string */
if (greth->gbit_mac) {
sprintf(dev->name, "GRETH_10/100/GB");
} else {
sprintf(dev->name, "GRETH_10/100");
}
/* initiate PHY, select speed/duplex depending on connected PHY */
if (greth_init_phy(greth, bis)) {
/* Failed to init PHY (timedout) */
debug("GRETH[0x%08x]: Failed to init PHY\n", greth->regs);
return -1;
}
/* Register Device to EtherNet subsystem */
eth_register(dev);
/* Get MAC address */
if ((addr_str = getenv("ethaddr")) != NULL) {
for (i = 0; i < 6; i++) {
addr[i] =
addr_str ? simple_strtoul(addr_str, &end, 16) : 0;
if (addr_str) {
addr_str = (*end) ? end + 1 : end;
}
}
} else {
/* HW Address not found in environment, Set default HW address */
addr[0] = GRETH_HWADDR_0; /* MSB */
addr[1] = GRETH_HWADDR_1;
addr[2] = GRETH_HWADDR_2;
addr[3] = GRETH_HWADDR_3;
addr[4] = GRETH_HWADDR_4;
addr[5] = GRETH_HWADDR_5; /* LSB */
}
/* set and remember MAC address */
greth_set_hwaddr(greth, addr);
debug("GRETH[0x%08x]: Initialized successfully\n", greth->regs);
return 0;
}
|
1001-study-uboot
|
drivers/net/greth.c
|
C
|
gpl3
| 18,257
|
/*
* Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2011 PetaLogix
* Copyright (C) 2010 Xilinx, Inc. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <net.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#if !defined(CONFIG_PHYLIB)
# error AXI_ETHERNET requires PHYLIB
#endif
/* Link setup */
#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
/* Interrupt Status/Enable/Mask Registers bit definitions */
#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
/* Receive Configuration Word 1 (RCW1) Register bit definitions */
#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
/* Transmitter Configuration (TC) Register bit definitions */
#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
/* MDIO Management Configuration (MC) Register bit definitions */
#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
/* MDIO Management Control Register (MCR) Register bit definitions */
#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
/* DMA macros */
/* Bitmasks of XAXIDMA_CR_OFFSET register */
#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
/* Bitmasks of XAXIDMA_SR_OFFSET register */
#define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
/* Bitmask for interrupts */
#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
#define DMAALIGN 128
static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
/* Reflect dma offsets */
struct axidma_reg {
u32 control; /* DMACR */
u32 status; /* DMASR */
u32 current; /* CURDESC */
u32 reserved;
u32 tail; /* TAILDESC */
};
/* Private driver structures */
struct axidma_priv {
struct axidma_reg *dmatx;
struct axidma_reg *dmarx;
int phyaddr;
struct phy_device *phydev;
struct mii_dev *bus;
};
/* BD descriptors */
struct axidma_bd {
u32 next; /* Next descriptor pointer */
u32 reserved1;
u32 phys; /* Buffer address */
u32 reserved2;
u32 reserved3;
u32 reserved4;
u32 cntrl; /* Control */
u32 status; /* Status */
u32 app0;
u32 app1; /* TX start << 16 | insert */
u32 app2; /* TX csum seed */
u32 app3;
u32 app4;
u32 sw_id_offset;
u32 reserved5;
u32 reserved6;
};
/* Static BDs - driver uses only one BD */
static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
struct axi_regs {
u32 reserved[3];
u32 is; /* 0xC: Interrupt status */
u32 reserved2;
u32 ie; /* 0x14: Interrupt enable */
u32 reserved3[251];
u32 rcw1; /* 0x404: Rx Configuration Word 1 */
u32 tc; /* 0x408: Tx Configuration */
u32 reserved4;
u32 emmc; /* 0x410: EMAC mode configuration */
u32 reserved5[59];
u32 mdio_mc; /* 0x500: MII Management Config */
u32 mdio_mcr; /* 0x504: MII Management Control */
u32 mdio_mwd; /* 0x508: MII Management Write Data */
u32 mdio_mrd; /* 0x50C: MII Management Read Data */
u32 reserved6[124];
u32 uaw0; /* 0x700: Unicast address word 0 */
u32 uaw1; /* 0x704: Unicast address word 1 */
};
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
/*
* Mask used to verify certain PHY features (or register contents)
* in the register above:
* 0x1000: 10Mbps full duplex support
* 0x0800: 10Mbps half duplex support
* 0x0008: Auto-negotiation support
*/
#define PHY_DETECT_MASK 0x1808
static inline int mdio_wait(struct eth_device *dev)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 timeout = 200;
/* Wait till MDIO interface is ready to accept a new transaction. */
while (timeout && (!(in_be32(®s->mdio_mcr)
& XAE_MDIO_MCR_READY_MASK))) {
timeout--;
udelay(1);
}
if (!timeout) {
printf("%s: Timeout\n", __func__);
return 1;
}
return 0;
}
static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
u16 *val)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 mdioctrlreg = 0;
if (mdio_wait(dev))
return 1;
mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
XAE_MDIO_MCR_PHYAD_MASK) |
((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
& XAE_MDIO_MCR_REGAD_MASK) |
XAE_MDIO_MCR_INITIATE_MASK |
XAE_MDIO_MCR_OP_READ_MASK;
out_be32(®s->mdio_mcr, mdioctrlreg);
if (mdio_wait(dev))
return 1;
/* Read data */
*val = in_be32(®s->mdio_mrd);
return 0;
}
static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
u32 data)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 mdioctrlreg = 0;
if (mdio_wait(dev))
return 1;
mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
XAE_MDIO_MCR_PHYAD_MASK) |
((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
& XAE_MDIO_MCR_REGAD_MASK) |
XAE_MDIO_MCR_INITIATE_MASK |
XAE_MDIO_MCR_OP_WRITE_MASK;
/* Write data */
out_be32(®s->mdio_mwd, data);
out_be32(®s->mdio_mcr, mdioctrlreg);
if (mdio_wait(dev))
return 1;
return 0;
}
/* Setting axi emac and phy to proper setting */
static int setup_phy(struct eth_device *dev)
{
u16 phyreg;
u32 i, speed, emmc_reg, ret;
struct axidma_priv *priv = dev->priv;
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
struct phy_device *phydev;
u32 supported = SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full;
if (priv->phyaddr == -1) {
/* Detect the PHY address */
for (i = 31; i >= 0; i--) {
ret = phyread(dev, i, PHY_DETECT_REG, &phyreg);
if (!ret && (phyreg != 0xFFFF) &&
((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
/* Found a valid PHY address */
priv->phyaddr = i;
debug("axiemac: Found valid phy address, %x\n",
phyreg);
break;
}
}
}
/* Interface - look at tsec */
phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
phydev->supported &= supported;
phydev->advertising = phydev->supported;
priv->phydev = phydev;
phy_config(phydev);
phy_startup(phydev);
switch (phydev->speed) {
case 1000:
speed = XAE_EMMC_LINKSPD_1000;
break;
case 100:
speed = XAE_EMMC_LINKSPD_100;
break;
case 10:
speed = XAE_EMMC_LINKSPD_10;
break;
default:
return 0;
}
/* Setup the emac for the phy speed */
emmc_reg = in_be32(®s->emmc);
emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
emmc_reg |= speed;
/* Write new speed setting out to Axi Ethernet */
out_be32(®s->emmc, emmc_reg);
/*
* Setting the operating speed of the MAC needs a delay. There
* doesn't seem to be register to poll, so please consider this
* during your application design.
*/
udelay(1);
return 1;
}
/* STOP DMA transfers */
static void axiemac_halt(struct eth_device *dev)
{
struct axidma_priv *priv = dev->priv;
u32 temp;
/* Stop the hardware */
temp = in_be32(&priv->dmatx->control);
temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
out_be32(&priv->dmatx->control, temp);
temp = in_be32(&priv->dmarx->control);
temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
out_be32(&priv->dmarx->control, temp);
debug("axiemac: Halted\n");
}
static int axi_ethernet_init(struct eth_device *dev)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 timeout = 200;
/*
* Check the status of the MgtRdy bit in the interrupt status
* registers. This must be done to allow the MGT clock to become stable
* for the Sgmii and 1000BaseX PHY interfaces. No other register reads
* will be valid until this bit is valid.
* The bit is always a 1 for all other PHY interfaces.
*/
while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) {
timeout--;
udelay(1);
}
if (!timeout) {
printf("%s: Timeout\n", __func__);
return 1;
}
/* Stop the device and reset HW */
/* Disable interrupts */
out_be32(®s->ie, 0);
/* Disable the receiver */
out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK);
/*
* Stopping the receiver in mid-packet causes a dropped packet
* indication from HW. Clear it.
*/
/* Set the interrupt status register to clear the interrupt */
out_be32(®s->is, XAE_INT_RXRJECT_MASK);
/* Setup HW */
/* Set default MDIO divisor */
out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
debug("axiemac: InitHw done\n");
return 0;
}
static int axiemac_setup_mac(struct eth_device *dev)
{
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
/* Set the MAC address */
int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
(dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
out_be32(®s->uaw0, val);
val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ;
val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
out_be32(®s->uaw1, val);
return 0;
}
/* Reset DMA engine */
static void axi_dma_init(struct eth_device *dev)
{
struct axidma_priv *priv = dev->priv;
u32 timeout = 500;
/* Reset the engine so the hardware starts from a known state */
out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
/* At the initialization time, hardware should finish reset quickly */
while (timeout--) {
/* Check transmit/receive channel */
/* Reset is done when the reset bit is low */
if (!(in_be32(&priv->dmatx->control) |
in_be32(&priv->dmarx->control))
& XAXIDMA_CR_RESET_MASK) {
break;
}
}
if (!timeout)
printf("%s: Timeout\n", __func__);
}
static int axiemac_init(struct eth_device *dev, bd_t * bis)
{
struct axidma_priv *priv = dev->priv;
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 temp;
debug("axiemac: Init started\n");
/*
* Initialize AXIDMA engine. AXIDMA engine must be initialized before
* AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
* reset, and since AXIDMA reset line is connected to AxiEthernet, this
* would ensure a reset of AxiEthernet.
*/
axi_dma_init(dev);
/* Initialize AxiEthernet hardware. */
if (axi_ethernet_init(dev))
return -1;
/* Disable all RX interrupts before RxBD space setup */
temp = in_be32(&priv->dmarx->control);
temp &= ~XAXIDMA_IRQ_ALL_MASK;
out_be32(&priv->dmarx->control, temp);
/* Start DMA RX channel. Now it's ready to receive data.*/
out_be32(&priv->dmarx->current, (u32)&rx_bd);
/* Setup the BD. */
memset(&rx_bd, 0, sizeof(rx_bd));
rx_bd.next = (u32)&rx_bd;
rx_bd.phys = (u32)&rxframe;
rx_bd.cntrl = sizeof(rxframe);
/* Flush the last BD so DMA core could see the updates */
flush_cache((u32)&rx_bd, sizeof(rx_bd));
/* It is necessary to flush rxframe because if you don't do it
* then cache can contain uninitialized data */
flush_cache((u32)&rxframe, sizeof(rxframe));
/* Start the hardware */
temp = in_be32(&priv->dmarx->control);
temp |= XAXIDMA_CR_RUNSTOP_MASK;
out_be32(&priv->dmarx->control, temp);
/* Rx BD is ready - start */
out_be32(&priv->dmarx->tail, (u32)&rx_bd);
/* Enable TX */
out_be32(®s->tc, XAE_TC_TX_MASK);
/* Enable RX */
out_be32(®s->rcw1, XAE_RCW1_RX_MASK);
/* PHY setup */
if (!setup_phy(dev)) {
axiemac_halt(dev);
return -1;
}
debug("axiemac: Init complete\n");
return 0;
}
static int axiemac_send(struct eth_device *dev, volatile void *ptr, int len)
{
struct axidma_priv *priv = dev->priv;
u32 timeout;
if (len > PKTSIZE_ALIGN)
len = PKTSIZE_ALIGN;
/* Flush packet to main memory to be trasfered by DMA */
flush_cache((u32)ptr, len);
/* Setup Tx BD */
memset(&tx_bd, 0, sizeof(tx_bd));
/* At the end of the ring, link the last BD back to the top */
tx_bd.next = (u32)&tx_bd;
tx_bd.phys = (u32)ptr;
/* Save len */
tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
XAXIDMA_BD_CTRL_TXEOF_MASK;
/* Flush the last BD so DMA core could see the updates */
flush_cache((u32)&tx_bd, sizeof(tx_bd));
if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
u32 temp;
out_be32(&priv->dmatx->current, (u32)&tx_bd);
/* Start the hardware */
temp = in_be32(&priv->dmatx->control);
temp |= XAXIDMA_CR_RUNSTOP_MASK;
out_be32(&priv->dmatx->control, temp);
}
/* Start transfer */
out_be32(&priv->dmatx->tail, (u32)&tx_bd);
/* Wait for transmission to complete */
debug("axiemac: Waiting for tx to be done\n");
timeout = 200;
while (timeout && (!in_be32(&priv->dmatx->status) &
(XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK))) {
timeout--;
udelay(1);
}
if (!timeout) {
printf("%s: Timeout\n", __func__);
return 1;
}
debug("axiemac: Sending complete\n");
return 0;
}
static int isrxready(struct eth_device *dev)
{
u32 status;
struct axidma_priv *priv = dev->priv;
/* Read pending interrupts */
status = in_be32(&priv->dmarx->status);
/* Acknowledge pending interrupts */
out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
/*
* If Reception done interrupt is asserted, call RX call back function
* to handle the processed BDs and then raise the according flag.
*/
if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
return 1;
return 0;
}
static int axiemac_recv(struct eth_device *dev)
{
u32 length;
struct axidma_priv *priv = dev->priv;
u32 temp;
/* Wait for an incoming packet */
if (!isrxready(dev))
return 0;
debug("axiemac: RX data ready\n");
/* Disable IRQ for a moment till packet is handled */
temp = in_be32(&priv->dmarx->control);
temp &= ~XAXIDMA_IRQ_ALL_MASK;
out_be32(&priv->dmarx->control, temp);
length = rx_bd.app4 & 0xFFFF; /* max length mask */
#ifdef DEBUG
print_buffer(&rxframe, &rxframe[0], 1, length, 16);
#endif
/* Pass the received frame up for processing */
if (length)
NetReceive(rxframe, length);
#ifdef DEBUG
/* It is useful to clear buffer to be sure that it is consistent */
memset(rxframe, 0, sizeof(rxframe));
#endif
/* Setup RxBD */
/* Clear the whole buffer and setup it again - all flags are cleared */
memset(&rx_bd, 0, sizeof(rx_bd));
rx_bd.next = (u32)&rx_bd;
rx_bd.phys = (u32)&rxframe;
rx_bd.cntrl = sizeof(rxframe);
/* Write bd to HW */
flush_cache((u32)&rx_bd, sizeof(rx_bd));
/* It is necessary to flush rxframe because if you don't do it
* then cache will contain previous packet */
flush_cache((u32)&rxframe, sizeof(rxframe));
/* Rx BD is ready - start again */
out_be32(&priv->dmarx->tail, (u32)&rx_bd);
debug("axiemac: RX completed, framelength = %d\n", length);
return length;
}
static int axiemac_miiphy_read(const char *devname, uchar addr,
uchar reg, ushort *val)
{
struct eth_device *dev = eth_get_dev();
u32 ret;
ret = phyread(dev, addr, reg, val);
debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
return ret;
}
static int axiemac_miiphy_write(const char *devname, uchar addr,
uchar reg, ushort val)
{
struct eth_device *dev = eth_get_dev();
debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
return phywrite(dev, addr, reg, val);
}
static int axiemac_bus_reset(struct mii_dev *bus)
{
debug("axiemac: Bus reset\n");
return 0;
}
int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
unsigned long dma_addr)
{
struct eth_device *dev;
struct axidma_priv *priv;
dev = calloc(1, sizeof(struct eth_device));
if (dev == NULL)
return -1;
dev->priv = calloc(1, sizeof(struct axidma_priv));
if (dev->priv == NULL) {
free(dev);
return -1;
}
priv = dev->priv;
sprintf(dev->name, "aximac.%lx", base_addr);
dev->iobase = base_addr;
priv->dmatx = (struct axidma_reg *)dma_addr;
/* RX channel offset is 0x30 */
priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30);
dev->init = axiemac_init;
dev->halt = axiemac_halt;
dev->send = axiemac_send;
dev->recv = axiemac_recv;
dev->write_hwaddr = axiemac_setup_mac;
#ifdef CONFIG_PHY_ADDR
priv->phyaddr = CONFIG_PHY_ADDR;
#else
priv->phyaddr = -1;
#endif
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write);
priv->bus = miiphy_get_dev_by_name(dev->name);
priv->bus->reset = axiemac_bus_reset;
#endif
return 1;
}
|
1001-study-uboot
|
drivers/net/xilinx_axi_emac.c
|
C
|
gpl3
| 18,001
|
/*
* Ethernet driver for TI TMS320DM644x (DaVinci) chips.
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright
* follows:
*
* ----------------------------------------------------------------------------
*
* dm644x_emac.c
*
* TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM
*
* Copyright (C) 2005 Texas Instruments.
*
* ----------------------------------------------------------------------------
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
* ----------------------------------------------------------------------------
* Modifications:
* ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot.
* ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors
*
*/
#include <common.h>
#include <command.h>
#include <net.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/compiler.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
#include "davinci_emac.h"
unsigned int emac_dbg = 0;
#define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
#ifdef EMAC_HW_RAM_ADDR
static inline unsigned long BD_TO_HW(unsigned long x)
{
if (x == 0)
return 0;
return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR;
}
static inline unsigned long HW_TO_BD(unsigned long x)
{
if (x == 0)
return 0;
return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR;
}
#else
#define BD_TO_HW(x) (x)
#define HW_TO_BD(x) (x)
#endif
#ifdef DAVINCI_EMAC_GIG_ENABLE
#define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr)
#else
#define emac_gigabit_enable(phy_addr) /* no gigabit to enable */
#endif
#if !defined(CONFIG_SYS_EMAC_TI_CLKDIV)
#define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \
EMAC_MDIO_CLOCK_FREQ) - 1)
#endif
static void davinci_eth_mdio_enable(void);
static int gen_init_phy(int phy_addr);
static int gen_is_phy_connected(int phy_addr);
static int gen_get_link_speed(int phy_addr);
static int gen_auto_negotiate(int phy_addr);
void eth_mdio_enable(void)
{
davinci_eth_mdio_enable();
}
/* EMAC Addresses */
static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR;
static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR;
static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR;
/* EMAC descriptors */
static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE);
static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
static volatile emac_desc *emac_rx_active_head = 0;
static volatile emac_desc *emac_rx_active_tail = 0;
static int emac_rx_queue_active = 0;
/* Receive packet buffers */
static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE]
__aligned(ARCH_DMA_MINALIGN);
#ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT
#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3
#endif
/* PHY address for a discovered PHY (0xff - not found) */
static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
/* number of PHY found active */
static u_int8_t num_phy;
phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
static inline void davinci_flush_rx_descs(void)
{
/* flush the whole RX descs area */
flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
}
static inline void davinci_invalidate_rx_descs(void)
{
/* invalidate the whole RX descs area */
invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE,
EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE);
}
static inline void davinci_flush_desc(emac_desc *desc)
{
flush_dcache_range((unsigned long)desc,
(unsigned long)desc + sizeof(*desc));
}
static int davinci_eth_set_mac_addr(struct eth_device *dev)
{
unsigned long mac_hi;
unsigned long mac_lo;
/*
* Set MAC Addresses & Init multicast Hash to 0 (disable any multicast
* receive)
* Using channel 0 only - other channels are disabled
* */
writel(0, &adap_emac->MACINDEX);
mac_hi = (dev->enetaddr[3] << 24) |
(dev->enetaddr[2] << 16) |
(dev->enetaddr[1] << 8) |
(dev->enetaddr[0]);
mac_lo = (dev->enetaddr[5] << 8) |
(dev->enetaddr[4]);
writel(mac_hi, &adap_emac->MACADDRHI);
#if defined(DAVINCI_EMAC_VERSION2)
writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH,
&adap_emac->MACADDRLO);
#else
writel(mac_lo, &adap_emac->MACADDRLO);
#endif
writel(0, &adap_emac->MACHASH1);
writel(0, &adap_emac->MACHASH2);
/* Set source MAC address - REQUIRED */
writel(mac_hi, &adap_emac->MACSRCADDRHI);
writel(mac_lo, &adap_emac->MACSRCADDRLO);
return 0;
}
static void davinci_eth_mdio_enable(void)
{
u_int32_t clkdiv;
clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) |
MDIO_CONTROL_ENABLE |
MDIO_CONTROL_FAULT |
MDIO_CONTROL_FAULT_ENABLE,
&adap_mdio->CONTROL);
while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE)
;
}
/*
* Tries to find an active connected PHY. Returns 1 if address if found.
* If no active PHY (or more than one PHY) found returns 0.
* Sets active_phy_addr variable.
*/
static int davinci_eth_phy_detect(void)
{
u_int32_t phy_act_state;
int i;
int j;
unsigned int count = 0;
for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++)
active_phy_addr[i] = 0xff;
udelay(1000);
phy_act_state = readl(&adap_mdio->ALIVE);
if (phy_act_state == 0)
return 0; /* No active PHYs */
debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state);
for (i = 0, j = 0; i < 32; i++)
if (phy_act_state & (1 << i)) {
count++;
if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) {
active_phy_addr[j++] = i;
} else {
printf("%s: to many PHYs detected.\n",
__func__);
count = 0;
break;
}
}
num_phy = count;
return count;
}
/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
{
int tmp;
while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
;
writel(MDIO_USERACCESS0_GO |
MDIO_USERACCESS0_WRITE_READ |
((reg_num & 0x1f) << 21) |
((phy_addr & 0x1f) << 16),
&adap_mdio->USERACCESS0);
/* Wait for command to complete */
while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO)
;
if (tmp & MDIO_USERACCESS0_ACK) {
*data = tmp & 0xffff;
return(1);
}
*data = -1;
return(0);
}
/* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */
int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
{
while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
;
writel(MDIO_USERACCESS0_GO |
MDIO_USERACCESS0_WRITE_WRITE |
((reg_num & 0x1f) << 21) |
((phy_addr & 0x1f) << 16) |
(data & 0xffff),
&adap_mdio->USERACCESS0);
/* Wait for command to complete */
while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO)
;
return(1);
}
/* PHY functions for a generic PHY */
static int gen_init_phy(int phy_addr)
{
int ret = 1;
if (gen_get_link_speed(phy_addr)) {
/* Try another time */
ret = gen_get_link_speed(phy_addr);
}
return(ret);
}
static int gen_is_phy_connected(int phy_addr)
{
u_int16_t dummy;
return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy);
}
static int get_active_phy(void)
{
int i;
for (i = 0; i < num_phy; i++)
if (phy[i].get_link_speed(active_phy_addr[i]))
return i;
return -1; /* Return error if no link */
}
static int gen_get_link_speed(int phy_addr)
{
u_int16_t tmp;
if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) &&
(tmp & 0x04)) {
#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
defined(CONFIG_MACH_DAVINCI_DA850_EVM)
davinci_eth_phy_read(phy_addr, MII_LPA, &tmp);
/* Speed doesn't matter, there is no setting for it in EMAC. */
if (tmp & (LPA_100FULL | LPA_10FULL)) {
/* set EMAC for Full Duplex */
writel(EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE,
&adap_emac->MACCONTROL);
} else {
/*set EMAC for Half Duplex */
writel(EMAC_MACCONTROL_MIIEN_ENABLE,
&adap_emac->MACCONTROL);
}
if (tmp & (LPA_100FULL | LPA_100HALF))
writel(readl(&adap_emac->MACCONTROL) |
EMAC_MACCONTROL_RMIISPEED_100,
&adap_emac->MACCONTROL);
else
writel(readl(&adap_emac->MACCONTROL) &
~EMAC_MACCONTROL_RMIISPEED_100,
&adap_emac->MACCONTROL);
#endif
return(1);
}
return(0);
}
static int gen_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
u_int16_t val;
unsigned long cntr = 0;
if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
return 0;
val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
BMCR_SPEED100;
davinci_eth_phy_write(phy_addr, MII_BMCR, val);
if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
return 0;
val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
ADVERTISE_10HALF);
davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
return(0);
/* Restart Auto_negotiation */
tmp |= BMCR_ANRESTART;
davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
/*check AutoNegotiate complete */
do {
udelay(40000);
if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
return 0;
if (tmp & BMSR_ANEGCOMPLETE)
break;
cntr++;
} while (cntr < 200);
if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
return(0);
if (!(tmp & BMSR_ANEGCOMPLETE))
return(0);
return(gen_get_link_speed(phy_addr));
}
/* End of generic PHY functions */
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value)
{
return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1);
}
static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
{
return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
}
#endif
static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
{
u_int16_t data;
if (davinci_eth_phy_read(phy_addr, 0, &data)) {
if (data & (1 << 6)) { /* speed selection MSB */
/*
* Check if link detected is giga-bit
* If Gigabit mode detected, enable gigbit in MAC
*/
writel(readl(&adap_emac->MACCONTROL) |
EMAC_MACCONTROL_GIGFORCE |
EMAC_MACCONTROL_GIGABIT_ENABLE,
&adap_emac->MACCONTROL);
}
}
}
/* Eth device open */
static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
{
dv_reg_p addr;
u_int32_t clkdiv, cnt;
volatile emac_desc *rx_desc;
int index;
debug_emac("+ emac_open\n");
/* Reset EMAC module and disable interrupts in wrapper */
writel(1, &adap_emac->SOFTRESET);
while (readl(&adap_emac->SOFTRESET) != 0)
;
#if defined(DAVINCI_EMAC_VERSION2)
writel(1, &adap_ewrap->softrst);
while (readl(&adap_ewrap->softrst) != 0)
;
#else
writel(0, &adap_ewrap->EWCTL);
for (cnt = 0; cnt < 5; cnt++) {
clkdiv = readl(&adap_ewrap->EWCTL);
}
#endif
#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
defined(CONFIG_MACH_DAVINCI_DA850_EVM)
adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
#endif
rx_desc = emac_rx_desc;
writel(1, &adap_emac->TXCONTROL);
writel(1, &adap_emac->RXCONTROL);
davinci_eth_set_mac_addr(dev);
/* Set DMA 8 TX / 8 RX Head pointers to 0 */
addr = &adap_emac->TX0HDP;
for(cnt = 0; cnt < 16; cnt++)
writel(0, addr++);
addr = &adap_emac->RX0HDP;
for(cnt = 0; cnt < 16; cnt++)
writel(0, addr++);
/* Clear Statistics (do this before setting MacControl register) */
addr = &adap_emac->RXGOODFRAMES;
for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++)
writel(0, addr++);
/* No multicast addressing */
writel(0, &adap_emac->MACHASH1);
writel(0, &adap_emac->MACHASH2);
/* Create RX queue and set receive process in place */
emac_rx_active_head = emac_rx_desc;
for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) {
rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1));
rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE];
rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
rx_desc++;
}
/* Finalize the rx desc list */
rx_desc--;
rx_desc->next = 0;
emac_rx_active_tail = rx_desc;
emac_rx_queue_active = 1;
davinci_flush_rx_descs();
/* Enable TX/RX */
writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN);
writel(0, &adap_emac->RXBUFFEROFFSET);
/*
* No fancy configs - Use this for promiscous debug
* - EMAC_RXMBPENABLE_RXCAFEN_ENABLE
*/
writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE);
/* Enable ch 0 only */
writel(1, &adap_emac->RXUNICASTSET);
/* Enable MII interface and Full duplex mode */
#if defined(CONFIG_SOC_DA8XX) || \
(defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII))
writel((EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE |
EMAC_MACCONTROL_RMIISPEED_100),
&adap_emac->MACCONTROL);
#else
writel((EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE),
&adap_emac->MACCONTROL);
#endif
/* Init MDIO & get link state */
clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV;
writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
&adap_mdio->CONTROL);
/* We need to wait for MDIO to start */
udelay(1000);
index = get_active_phy();
if (index == -1)
return(0);
emac_gigabit_enable(active_phy_addr[index]);
/* Start receive process */
writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP);
debug_emac("- emac_open\n");
return(1);
}
/* EMAC Channel Teardown */
static void davinci_eth_ch_teardown(int ch)
{
dv_reg dly = 0xff;
dv_reg cnt;
debug_emac("+ emac_ch_teardown\n");
if (ch == EMAC_CH_TX) {
/* Init TX channel teardown */
writel(0, &adap_emac->TXTEARDOWN);
do {
/*
* Wait here for Tx teardown completion interrupt to
* occur. Note: A task delay can be called here to pend
* rather than occupying CPU cycles - anyway it has
* been found that teardown takes very few cpu cycles
* and does not affect functionality
*/
dly--;
udelay(1);
if (dly == 0)
break;
cnt = readl(&adap_emac->TX0CP);
} while (cnt != 0xfffffffc);
writel(cnt, &adap_emac->TX0CP);
writel(0, &adap_emac->TX0HDP);
} else {
/* Init RX channel teardown */
writel(0, &adap_emac->RXTEARDOWN);
do {
/*
* Wait here for Rx teardown completion interrupt to
* occur. Note: A task delay can be called here to pend
* rather than occupying CPU cycles - anyway it has
* been found that teardown takes very few cpu cycles
* and does not affect functionality
*/
dly--;
udelay(1);
if (dly == 0)
break;
cnt = readl(&adap_emac->RX0CP);
} while (cnt != 0xfffffffc);
writel(cnt, &adap_emac->RX0CP);
writel(0, &adap_emac->RX0HDP);
}
debug_emac("- emac_ch_teardown\n");
}
/* Eth device close */
static void davinci_eth_close(struct eth_device *dev)
{
debug_emac("+ emac_close\n");
davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */
davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */
/* Reset EMAC module and disable interrupts in wrapper */
writel(1, &adap_emac->SOFTRESET);
#if defined(DAVINCI_EMAC_VERSION2)
writel(1, &adap_ewrap->softrst);
#else
writel(0, &adap_ewrap->EWCTL);
#endif
#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
defined(CONFIG_MACH_DAVINCI_DA850_EVM)
adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0;
adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0;
adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0;
#endif
debug_emac("- emac_close\n");
}
static int tx_send_loop = 0;
/*
* This function sends a single packet on the network and returns
* positive number (number of bytes transmitted) or negative for error
*/
static int davinci_eth_send_packet (struct eth_device *dev,
volatile void *packet, int length)
{
int ret_status = -1;
int index;
tx_send_loop = 0;
index = get_active_phy();
if (index == -1) {
printf(" WARN: emac_send_packet: No link\n");
return (ret_status);
}
emac_gigabit_enable(active_phy_addr[index]);
/* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */
if (length < EMAC_MIN_ETHERNET_PKT_SIZE) {
length = EMAC_MIN_ETHERNET_PKT_SIZE;
}
/* Populate the TX descriptor */
emac_tx_desc->next = 0;
emac_tx_desc->buffer = (u_int8_t *) packet;
emac_tx_desc->buff_off_len = (length & 0xffff);
emac_tx_desc->pkt_flag_len = ((length & 0xffff) |
EMAC_CPPI_SOP_BIT |
EMAC_CPPI_OWNERSHIP_BIT |
EMAC_CPPI_EOP_BIT);
flush_dcache_range((unsigned long)packet,
(unsigned long)packet + length);
davinci_flush_desc(emac_tx_desc);
/* Send the packet */
writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP);
/* Wait for packet to complete or link down */
while (1) {
if (!phy[index].get_link_speed(active_phy_addr[index])) {
davinci_eth_ch_teardown (EMAC_CH_TX);
return (ret_status);
}
emac_gigabit_enable(active_phy_addr[index]);
if (readl(&adap_emac->TXINTSTATRAW) & 0x01) {
ret_status = length;
break;
}
tx_send_loop++;
}
return (ret_status);
}
/*
* This function handles receipt of a packet from the network
*/
static int davinci_eth_rcv_packet (struct eth_device *dev)
{
volatile emac_desc *rx_curr_desc;
volatile emac_desc *curr_desc;
volatile emac_desc *tail_desc;
int status, ret = -1;
davinci_invalidate_rx_descs();
rx_curr_desc = emac_rx_active_head;
status = rx_curr_desc->pkt_flag_len;
if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) {
if (status & EMAC_CPPI_RX_ERROR_FRAME) {
/* Error in packet - discard it and requeue desc */
printf ("WARN: emac_rcv_pkt: Error in packet\n");
} else {
unsigned long tmp = (unsigned long)rx_curr_desc->buffer;
invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE);
NetReceive (rx_curr_desc->buffer,
(rx_curr_desc->buff_off_len & 0xffff));
ret = rx_curr_desc->buff_off_len & 0xffff;
}
/* Ack received packet descriptor */
writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP);
curr_desc = rx_curr_desc;
emac_rx_active_head =
(volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next));
if (status & EMAC_CPPI_EOQ_BIT) {
if (emac_rx_active_head) {
writel(BD_TO_HW((ulong)emac_rx_active_head),
&adap_emac->RX0HDP);
} else {
emac_rx_queue_active = 0;
printf ("INFO:emac_rcv_packet: RX Queue not active\n");
}
}
/* Recycle RX descriptor */
rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE;
rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT;
rx_curr_desc->next = 0;
davinci_flush_desc(rx_curr_desc);
if (emac_rx_active_head == 0) {
printf ("INFO: emac_rcv_pkt: active queue head = 0\n");
emac_rx_active_head = curr_desc;
emac_rx_active_tail = curr_desc;
if (emac_rx_queue_active != 0) {
writel(BD_TO_HW((ulong)emac_rx_active_head),
&adap_emac->RX0HDP);
printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n");
emac_rx_queue_active = 1;
}
} else {
tail_desc = emac_rx_active_tail;
emac_rx_active_tail = curr_desc;
tail_desc->next = BD_TO_HW((ulong) curr_desc);
status = tail_desc->pkt_flag_len;
if (status & EMAC_CPPI_EOQ_BIT) {
davinci_flush_desc(tail_desc);
writel(BD_TO_HW((ulong)curr_desc),
&adap_emac->RX0HDP);
status &= ~EMAC_CPPI_EOQ_BIT;
tail_desc->pkt_flag_len = status;
}
davinci_flush_desc(tail_desc);
}
return (ret);
}
return (0);
}
/*
* This function initializes the emac hardware. It does NOT initialize
* EMAC modules power or pin multiplexors, that is done by board_init()
* much earlier in bootup process. Returns 1 on success, 0 otherwise.
*/
int davinci_emac_initialize(void)
{
u_int32_t phy_id;
u_int16_t tmp;
int i;
int ret;
struct eth_device *dev;
dev = malloc(sizeof *dev);
if (dev == NULL)
return -1;
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "DaVinci-EMAC");
dev->iobase = 0;
dev->init = davinci_eth_open;
dev->halt = davinci_eth_close;
dev->send = davinci_eth_send_packet;
dev->recv = davinci_eth_rcv_packet;
dev->write_hwaddr = davinci_eth_set_mac_addr;
eth_register(dev);
davinci_eth_mdio_enable();
/* let the EMAC detect the PHYs */
udelay(5000);
for (i = 0; i < 256; i++) {
if (readl(&adap_mdio->ALIVE))
break;
udelay(1000);
}
if (i >= 256) {
printf("No ETH PHY detected!!!\n");
return(0);
}
/* Find if PHY(s) is/are connected */
ret = davinci_eth_phy_detect();
if (!ret)
return(0);
else
debug_emac(" %d ETH PHY detected\n", ret);
/* Get PHY ID and initialize phy_ops for a detected PHY */
for (i = 0; i < num_phy; i++) {
if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
&tmp)) {
active_phy_addr[i] = 0xff;
continue;
}
phy_id = (tmp << 16) & 0xffff0000;
if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
&tmp)) {
active_phy_addr[i] = 0xff;
continue;
}
phy_id |= tmp & 0x0000ffff;
switch (phy_id) {
#ifdef PHY_KSZ8873
case PHY_KSZ8873:
sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
active_phy_addr[i]);
phy[i].init = ksz8873_init_phy;
phy[i].is_phy_connected = ksz8873_is_phy_connected;
phy[i].get_link_speed = ksz8873_get_link_speed;
phy[i].auto_negotiate = ksz8873_auto_negotiate;
break;
#endif
#ifdef PHY_LXT972
case PHY_LXT972:
sprintf(phy[i].name, "LXT972 @ 0x%02x",
active_phy_addr[i]);
phy[i].init = lxt972_init_phy;
phy[i].is_phy_connected = lxt972_is_phy_connected;
phy[i].get_link_speed = lxt972_get_link_speed;
phy[i].auto_negotiate = lxt972_auto_negotiate;
break;
#endif
#ifdef PHY_DP83848
case PHY_DP83848:
sprintf(phy[i].name, "DP83848 @ 0x%02x",
active_phy_addr[i]);
phy[i].init = dp83848_init_phy;
phy[i].is_phy_connected = dp83848_is_phy_connected;
phy[i].get_link_speed = dp83848_get_link_speed;
phy[i].auto_negotiate = dp83848_auto_negotiate;
break;
#endif
#ifdef PHY_ET1011C
case PHY_ET1011C:
sprintf(phy[i].name, "ET1011C @ 0x%02x",
active_phy_addr[i]);
phy[i].init = gen_init_phy;
phy[i].is_phy_connected = gen_is_phy_connected;
phy[i].get_link_speed = et1011c_get_link_speed;
phy[i].auto_negotiate = gen_auto_negotiate;
break;
#endif
default:
sprintf(phy[i].name, "GENERIC @ 0x%02x",
active_phy_addr[i]);
phy[i].init = gen_init_phy;
phy[i].is_phy_connected = gen_is_phy_connected;
phy[i].get_link_speed = gen_get_link_speed;
phy[i].auto_negotiate = gen_auto_negotiate;
}
debug("Ethernet PHY: %s\n", phy[i].name);
miiphy_register(phy[i].name, davinci_mii_phy_read,
davinci_mii_phy_write);
}
return(1);
}
|
1001-study-uboot
|
drivers/net/davinci_emac.c
|
C
|
gpl3
| 23,532
|
/*
* bfin_mac.h - some defines/structures for the Blackfin on-chip MAC.
*
* Copyright (c) 2005-2008 Analog Device, Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MAC_H__
#define __BFIN_MAC_H__
#define RECV_BUFSIZE (0x614)
typedef struct ADI_DMA_CONFIG_REG {
u16 b_DMA_EN:1; /* 0 Enabled */
u16 b_WNR:1; /* 1 Direction */
u16 b_WDSIZE:2; /* 2:3 Transfer word size */
u16 b_DMA2D:1; /* 4 DMA mode */
u16 b_RESTART:1; /* 5 Retain FIFO */
u16 b_DI_SEL:1; /* 6 Data interrupt timing select */
u16 b_DI_EN:1; /* 7 Data interrupt enabled */
u16 b_NDSIZE:4; /* 8:11 Flex descriptor size */
u16 b_FLOW:3; /* 12:14Flow */
} ADI_DMA_CONFIG_REG;
typedef struct adi_ether_frame_buffer {
u16 NoBytes; /* the no. of following bytes */
u8 Dest[6]; /* destination MAC address */
u8 Srce[6]; /* source MAC address */
u16 LTfield; /* length/type field */
u8 Data[0]; /* payload bytes */
} ADI_ETHER_FRAME_BUFFER;
/* 16 bytes/struct */
typedef struct dma_descriptor {
struct dma_descriptor *NEXT_DESC_PTR;
u32 START_ADDR;
union {
u16 CONFIG_DATA;
ADI_DMA_CONFIG_REG CONFIG;
};
} DMA_DESCRIPTOR;
/* 10 bytes/struct in 12 bytes */
typedef struct adi_ether_buffer {
DMA_DESCRIPTOR Dma[2]; /* first for the frame, second for the status */
ADI_ETHER_FRAME_BUFFER *FrmData;/* pointer to data */
struct adi_ether_buffer *pNext; /* next buffer */
struct adi_ether_buffer *pPrev; /* prev buffer */
u16 IPHdrChksum; /* the IP header checksum */
u16 IPPayloadChksum; /* the IP header and payload checksum */
volatile u32 StatusWord; /* the frame status word */
} ADI_ETHER_BUFFER;
/* 40 bytes/struct in 44 bytes */
static ADI_ETHER_BUFFER *SetupRxBuffer(int no);
static ADI_ETHER_BUFFER *SetupTxBuffer(int no);
static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd);
static void bfin_EMAC_halt(struct eth_device *dev);
static int bfin_EMAC_send(struct eth_device *dev, volatile void *packet, int length);
static int bfin_EMAC_recv(struct eth_device *dev);
static int bfin_EMAC_setup_addr(struct eth_device *dev);
#endif
|
1001-study-uboot
|
drivers/net/bfin_mac.h
|
C
|
gpl3
| 2,088
|
/*
* ks8695eth.c -- KS8695 ethernet driver
*
* (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/****************************************************************************/
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <asm/io.h>
#include <asm/arch/platform.h>
/****************************************************************************/
/*
* Hardware register access to the KS8695 LAN ethernet port
* (well, it is the 4 port switch really).
*/
#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a)))
#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v)
/****************************************************************************/
/*
* Define the descriptor in-memory data structures.
*/
struct ks8695_txdesc {
uint32_t owner;
uint32_t ctrl;
uint32_t addr;
uint32_t next;
};
struct ks8695_rxdesc {
uint32_t status;
uint32_t ctrl;
uint32_t addr;
uint32_t next;
};
/****************************************************************************/
/*
* Allocate local data structures to use for receiving and sending
* packets. Just to keep it all nice and simple.
*/
#define TXDESCS 4
#define RXDESCS 4
#define BUFSIZE 2048
volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256)));
volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256)));
volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));;
/****************************************************************************/
/*
* Ideally we want to use the MAC address stored in flash.
* But we do some sanity checks in case they are not present
* first.
*/
unsigned char eth_mac[] = {
0x00, 0x13, 0xc6, 0x00, 0x00, 0x00
};
void ks8695_getmac(void)
{
unsigned char *fp;
int i;
/* Check if flash MAC is valid */
fp = (unsigned char *) 0x0201c000;
for (i = 0; (i < 6); i++) {
if ((fp[i] != 0) && (fp[i] != 0xff))
break;
}
/* If we found a valid looking MAC address then use it */
if (i < 6)
memcpy(ð_mac[0], fp, 6);
}
/****************************************************************************/
static int ks8695_eth_init(struct eth_device *dev, bd_t *bd)
{
int i;
debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__);
/* Reset the ethernet engines first */
ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
ks8695_getmac();
/* Set MAC address */
ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) |
(eth_mac[3] << 16) | (eth_mac[2] << 24)));
ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8)));
/* Turn the 4 port switch on */
i = ks8695_read(KS8695_SWITCH_CTRL0);
ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1));
/* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */
/* Initialize descriptor rings */
for (i = 0; (i < TXDESCS); i++) {
ks8695_tx[i].owner = 0;
ks8695_tx[i].ctrl = 0;
ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE];
ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1];
}
ks8695_tx[TXDESCS-1].ctrl = 0x02000000;
ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0];
for (i = 0; (i < RXDESCS); i++) {
ks8695_rx[i].status = 0x80000000;
ks8695_rx[i].ctrl = BUFSIZE - 4;
ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE];
ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1];
}
ks8695_rx[RXDESCS-1].ctrl |= 0x00080000;
ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0];
/* The KS8695 is pretty slow reseting the ethernets... */
udelay(2000000);
/* Enable the ethernet engine */
ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]);
ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]);
ks8695_write(KS8695_LAN_DMA_TX, 0x3);
ks8695_write(KS8695_LAN_DMA_RX, 0x71);
ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
printf("KS8695 ETHERNET: %pM\n", eth_mac);
return 0;
}
/****************************************************************************/
static void ks8695_eth_halt(struct eth_device *dev)
{
debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__);
/* Reset the ethernet engines */
ks8695_write(KS8695_LAN_DMA_TX, 0x80000000);
ks8695_write(KS8695_LAN_DMA_RX, 0x80000000);
}
/****************************************************************************/
static int ks8695_eth_recv(struct eth_device *dev)
{
volatile struct ks8695_rxdesc *dp;
int i, len = 0;
debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__);
for (i = 0; (i < RXDESCS); i++) {
dp= &ks8695_rx[i];
if ((dp->status & 0x80000000) == 0) {
len = (dp->status & 0x7ff) - 4;
NetReceive((void *) dp->addr, len);
dp->status = 0x80000000;
ks8695_write(KS8695_LAN_DMA_RX_START, 0x1);
break;
}
}
return len;
}
/****************************************************************************/
static int ks8695_eth_send(struct eth_device *dev, volatile void *packet,
int len)
{
volatile struct ks8695_txdesc *dp;
static int next = 0;
debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__,
packet, len);
dp = &ks8695_tx[next];
memcpy((void *) dp->addr, (void *) packet, len);
if (len < 64) {
memset((void *) (dp->addr + len), 0, 64-len);
len = 64;
}
dp->ctrl = len | 0xe0000000;
dp->owner = 0x80000000;
ks8695_write(KS8695_LAN_DMA_TX, 0x3);
ks8695_write(KS8695_LAN_DMA_TX_START, 0x1);
if (++next >= TXDESCS)
next = 0;
return 0;
}
/****************************************************************************/
int ks8695_eth_initialize(void)
{
struct eth_device *dev;
dev = malloc(sizeof(*dev));
if (dev == NULL)
return -1;
memset(dev, 0, sizeof(*dev));
dev->iobase = KS8695_IO_BASE + KS8695_LAN_DMA_TX;
dev->init = ks8695_eth_init;
dev->halt = ks8695_eth_halt;
dev->send = ks8695_eth_send;
dev->recv = ks8695_eth_recv;
strcpy(dev->name, "ks8695eth");
eth_register(dev);
return 0;
}
|
1001-study-uboot
|
drivers/net/ks8695eth.c
|
C
|
gpl3
| 6,591
|
/*
* Copyright (C) 2003 IMMS gGmbH <www.imms.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* author(s): Thomas Elste, <info@elste.org>
*/
#include <asm/types.h>
#include <config.h>
#ifdef CONFIG_DRIVER_NETARMETH
#define SET_EADDR(ad,val) *(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE) = val
#define GET_EADDR(ad) (*(volatile unsigned int*)(ad + NETARM_ETH_MODULE_BASE))
#define NA_MII_POLL_BUSY_DELAY 900
/* MII negotiation timeout value
500 jiffies = 5 seconds */
#define NA_MII_NEGOTIATE_DELAY 30
/* Registers in the physical layer chip */
#define MII_PHY_CONTROL 0
#define MII_PHY_STATUS 1
#define MII_PHY_ID 2
#define MII_PHY_AUTONEGADV 4
#endif /* CONFIG_DRIVER_NETARMETH */
|
1001-study-uboot
|
drivers/net/netarm_eth.h
|
C
|
gpl3
| 1,394
|
/*
* Freescale Three Speed Ethernet Controller driver
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* Copyright 2004-2011 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* author Andy Fleming
*
*/
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <net.h>
#include <command.h>
#include <tsec.h>
#include <fsl_mdio.h>
#include <asm/errno.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
#define TX_BUF_CNT 2
static uint rxIdx; /* index of the current RX buffer */
static uint txIdx; /* index of the current TX buffer */
typedef volatile struct rtxbd {
txbd8_t txbd[TX_BUF_CNT];
rxbd8_t rxbd[PKTBUFSRX];
} RTXBD;
#define MAXCONTROLLERS (8)
static struct tsec_private *privlist[MAXCONTROLLERS];
static int num_tsecs = 0;
#ifdef __GNUC__
static RTXBD rtx __attribute__ ((aligned(8)));
#else
#error "rtx must be 64-bit aligned"
#endif
static int tsec_send(struct eth_device *dev,
volatile void *packet, int length);
/* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = {
#ifdef CONFIG_TSEC1
STD_TSEC_INFO(1), /* TSEC1 */
#endif
#ifdef CONFIG_TSEC2
STD_TSEC_INFO(2), /* TSEC2 */
#endif
#ifdef CONFIG_MPC85XX_FEC
{
.regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
.devname = CONFIG_MPC85XX_FEC_NAME,
.phyaddr = FEC_PHY_ADDR,
.flags = FEC_FLAGS,
.mii_devname = DEFAULT_MII_NAME
}, /* FEC */
#endif
#ifdef CONFIG_TSEC3
STD_TSEC_INFO(3), /* TSEC3 */
#endif
#ifdef CONFIG_TSEC4
STD_TSEC_INFO(4), /* TSEC4 */
#endif
};
#define TBIANA_SETTINGS ( \
TBIANA_ASYMMETRIC_PAUSE \
| TBIANA_SYMMETRIC_PAUSE \
| TBIANA_FULL_DUPLEX \
)
/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
#ifndef CONFIG_TSEC_TBICR_SETTINGS
#define CONFIG_TSEC_TBICR_SETTINGS ( \
TBICR_PHY_RESET \
| TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
#endif /* CONFIG_TSEC_TBICR_SETTINGS */
/* Configure the TBI for SGMII operation */
static void tsec_configure_serdes(struct tsec_private *priv)
{
/* Access TBI PHY registers at given TSEC register offset as opposed
* to the register offset used for external PHY accesses */
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
0, TBI_ANA, TBIANA_SETTINGS);
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
0, TBI_TBICON, TBICON_CLK_SELECT);
tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
}
#ifdef CONFIG_MCAST_TFTP
/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
/* Set the appropriate hash bit for the given addr */
/* The algorithm works like so:
* 1) Take the Destination Address (ie the multicast address), and
* do a CRC on it (little endian), and reverse the bits of the
* result.
* 2) Use the 8 most significant bits as a hash into a 256-entry
* table. The table is controlled through 8 32-bit registers:
* gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
* gaddr7. This means that the 3 most significant bits in the
* hash index which gaddr register to use, and the 5 other bits
* indicate which bit (assuming an IBM numbering scheme, which
* for PowerPC (tm) is usually the case) in the tregister holds
* the entry. */
static int
tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set)
{
struct tsec_private *priv = privlist[1];
volatile tsec_t *regs = priv->regs;
volatile u32 *reg_array, value;
u8 result, whichbit, whichreg;
result = (u8)((ether_crc(MAC_ADDR_LEN,mcast_mac) >> 24) & 0xff);
whichbit = result & 0x1f; /* the 5 LSB = which bit to set */
whichreg = result >> 5; /* the 3 MSB = which reg to set it in */
value = (1 << (31-whichbit));
reg_array = &(regs->hash.gaddr0);
if (set) {
reg_array[whichreg] |= value;
} else {
reg_array[whichreg] &= ~value;
}
return 0;
}
#endif /* Multicast TFTP ? */
/* Initialized required registers to appropriate values, zeroing
* those we don't care about (unless zero is bad, in which case,
* choose a more appropriate value)
*/
static void init_registers(tsec_t *regs)
{
/* Clear IEVENT */
out_be32(®s->ievent, IEVENT_INIT_CLEAR);
out_be32(®s->imask, IMASK_INIT_CLEAR);
out_be32(®s->hash.iaddr0, 0);
out_be32(®s->hash.iaddr1, 0);
out_be32(®s->hash.iaddr2, 0);
out_be32(®s->hash.iaddr3, 0);
out_be32(®s->hash.iaddr4, 0);
out_be32(®s->hash.iaddr5, 0);
out_be32(®s->hash.iaddr6, 0);
out_be32(®s->hash.iaddr7, 0);
out_be32(®s->hash.gaddr0, 0);
out_be32(®s->hash.gaddr1, 0);
out_be32(®s->hash.gaddr2, 0);
out_be32(®s->hash.gaddr3, 0);
out_be32(®s->hash.gaddr4, 0);
out_be32(®s->hash.gaddr5, 0);
out_be32(®s->hash.gaddr6, 0);
out_be32(®s->hash.gaddr7, 0);
out_be32(®s->rctrl, 0x00000000);
/* Init RMON mib registers */
memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
out_be32(®s->rmon.cam1, 0xffffffff);
out_be32(®s->rmon.cam2, 0xffffffff);
out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
out_be32(®s->attr, ATTR_INIT_SETTINGS);
out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
}
/* Configure maccfg2 based on negotiated speed and duplex
* reported by PHY handling code
*/
static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
{
tsec_t *regs = priv->regs;
u32 ecntrl, maccfg2;
if (!phydev->link) {
printf("%s: No link.\n", phydev->dev->name);
return;
}
/* clear all bits relative with interface mode */
ecntrl = in_be32(®s->ecntrl);
ecntrl &= ~ECNTRL_R100;
maccfg2 = in_be32(®s->maccfg2);
maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
if (phydev->duplex)
maccfg2 |= MACCFG2_FULL_DUPLEX;
switch (phydev->speed) {
case 1000:
maccfg2 |= MACCFG2_GMII;
break;
case 100:
case 10:
maccfg2 |= MACCFG2_MII;
/* Set R100 bit in all modes although
* it is only used in RGMII mode
*/
if (phydev->speed == 100)
ecntrl |= ECNTRL_R100;
break;
default:
printf("%s: Speed was bad\n", phydev->dev->name);
break;
}
out_be32(®s->ecntrl, ecntrl);
out_be32(®s->maccfg2, maccfg2);
printf("Speed: %d, %s duplex%s\n", phydev->speed,
(phydev->duplex) ? "full" : "half",
(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
}
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
/*
* When MACCFG1[Rx_EN] is enabled during system boot as part
* of the eTSEC port initialization sequence,
* the eTSEC Rx logic may not be properly initialized.
*/
void redundant_init(struct eth_device *dev)
{
struct tsec_private *priv = dev->priv;
tsec_t *regs = priv->regs;
uint t, count = 0;
int fail = 1;
static const u8 pkt[] = {
0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
0x71, 0x72};
/* Enable promiscuous mode */
setbits_be32(®s->rctrl, 0x8);
/* Enable loopback mode */
setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
/* Enable transmit and receive */
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
/* Tell the DMA it is clear to go */
setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
do {
tsec_send(dev, (void *)pkt, sizeof(pkt));
/* Wait for buffer to be received */
for (t = 0; rtx.rxbd[rxIdx].status & RXBD_EMPTY; t++) {
if (t >= 10 * TOUT_LOOP) {
printf("%s: tsec: rx error\n", dev->name);
break;
}
}
if (!memcmp(pkt, (void *)NetRxPackets[rxIdx], sizeof(pkt)))
fail = 0;
rtx.rxbd[rxIdx].length = 0;
rtx.rxbd[rxIdx].status =
RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
rxIdx = (rxIdx + 1) % PKTBUFSRX;
if (in_be32(®s->ievent) & IEVENT_BSY) {
out_be32(®s->ievent, IEVENT_BSY);
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
}
if (fail) {
printf("loopback recv packet error!\n");
clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
udelay(1000);
setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
}
} while ((count++ < 4) && (fail == 1));
if (fail)
panic("eTSEC init fail!\n");
/* Disable promiscuous mode */
clrbits_be32(®s->rctrl, 0x8);
/* Disable loopback mode */
clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
}
#endif
/* Set up the buffers and their descriptors, and bring up the
* interface
*/
static void startup_tsec(struct eth_device *dev)
{
int i;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
/* reset the indices to zero */
rxIdx = 0;
txIdx = 0;
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
uint svr;
#endif
/* Point to the buffer descriptors */
out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx]));
out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx]));
/* Initialize the Rx Buffer descriptors */
for (i = 0; i < PKTBUFSRX; i++) {
rtx.rxbd[i].status = RXBD_EMPTY;
rtx.rxbd[i].length = 0;
rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
}
rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
/* Initialize the TX Buffer Descriptors */
for (i = 0; i < TX_BUF_CNT; i++) {
rtx.txbd[i].status = 0;
rtx.txbd[i].length = 0;
rtx.txbd[i].bufPtr = 0;
}
rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
svr = get_svr();
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
redundant_init(dev);
#endif
/* Enable Transmit and Receive */
setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
/* Tell the DMA it is clear to go */
setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
}
/* This returns the status bits of the device. The return value
* is never checked, and this is what the 8260 driver did, so we
* do the same. Presumably, this would be zero if there were no
* errors
*/
static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
{
int i;
int result = 0;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
/* Find an empty buffer descriptor */
for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
debug("%s: tsec: tx buffers full\n", dev->name);
return result;
}
}
rtx.txbd[txIdx].bufPtr = (uint) packet;
rtx.txbd[txIdx].length = length;
rtx.txbd[txIdx].status |=
(TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
/* Tell the DMA to go */
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
/* Wait for buffer to be transmitted */
for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
if (i >= TOUT_LOOP) {
debug("%s: tsec: tx error\n", dev->name);
return result;
}
}
txIdx = (txIdx + 1) % TX_BUF_CNT;
result = rtx.txbd[txIdx].status & TXBD_STATS;
return result;
}
static int tsec_recv(struct eth_device *dev)
{
int length;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
length = rtx.rxbd[rxIdx].length;
/* Send the packet up if there were no errors */
if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
NetReceive(NetRxPackets[rxIdx], length - 4);
} else {
printf("Got error %x\n",
(rtx.rxbd[rxIdx].status & RXBD_STATS));
}
rtx.rxbd[rxIdx].length = 0;
/* Set the wrap bit if this is the last element in the list */
rtx.rxbd[rxIdx].status =
RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
rxIdx = (rxIdx + 1) % PKTBUFSRX;
}
if (in_be32(®s->ievent) & IEVENT_BSY) {
out_be32(®s->ievent, IEVENT_BSY);
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
}
return -1;
}
/* Stop the interface */
static void tsec_halt(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
!= (IEVENT_GRSC | IEVENT_GTSC))
;
clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
/* Shut down the PHY, as needed */
phy_shutdown(priv->phydev);
}
/* Initializes data structures and registers for the controller,
* and brings the interface up. Returns the link status, meaning
* that it returns success if the link is up, failure otherwise.
* This allows u-boot to find the first active controller.
*/
static int tsec_init(struct eth_device *dev, bd_t * bd)
{
uint tempval;
char tmpbuf[MAC_ADDR_LEN];
int i;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
/* Make sure the controller is stopped */
tsec_halt(dev);
/* Init MACCFG2. Defaults to GMII */
out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
/* Init ECNTRL */
out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
/* Copy the station address into the address registers.
* Backwards, because little endian MACS are dumb */
for (i = 0; i < MAC_ADDR_LEN; i++)
tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
tmpbuf[3];
out_be32(®s->macstnaddr1, tempval);
tempval = *((uint *) (tmpbuf + 4));
out_be32(®s->macstnaddr2, tempval);
/* Clear out (for the most part) the other registers */
init_registers(regs);
/* Ready the device for tx/rx */
startup_tsec(dev);
/* Start up the PHY */
phy_startup(priv->phydev);
adjust_link(priv, priv->phydev);
/* If there's no link, fail */
return priv->phydev->link ? 0 : -1;
}
static phy_interface_t tsec_get_interface(struct tsec_private *priv)
{
tsec_t *regs = priv->regs;
u32 ecntrl;
ecntrl = in_be32(®s->ecntrl);
if (ecntrl & ECNTRL_SGMII_MODE)
return PHY_INTERFACE_MODE_SGMII;
if (ecntrl & ECNTRL_TBI_MODE) {
if (ecntrl & ECNTRL_REDUCED_MODE)
return PHY_INTERFACE_MODE_RTBI;
else
return PHY_INTERFACE_MODE_TBI;
}
if (ecntrl & ECNTRL_REDUCED_MODE) {
if (ecntrl & ECNTRL_REDUCED_MII_MODE)
return PHY_INTERFACE_MODE_RMII;
else {
phy_interface_t interface = priv->interface;
/*
* This isn't autodetected, so it must
* be set by the platform code.
*/
if ((interface == PHY_INTERFACE_MODE_RGMII_ID) ||
(interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
(interface == PHY_INTERFACE_MODE_RGMII_RXID))
return interface;
return PHY_INTERFACE_MODE_RGMII;
}
}
if (priv->flags & TSEC_GIGABIT)
return PHY_INTERFACE_MODE_GMII;
return PHY_INTERFACE_MODE_MII;
}
/* Discover which PHY is attached to the device, and configure it
* properly. If the PHY is not recognized, then return 0
* (failure). Otherwise, return 1
*/
static int init_phy(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct phy_device *phydev;
tsec_t *regs = priv->regs;
u32 supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full);
if (priv->flags & TSEC_GIGABIT)
supported |= SUPPORTED_1000baseT_Full;
/* Assign a Physical address to the TBI */
out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE);
priv->interface = tsec_get_interface(priv);
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
phydev->supported &= supported;
phydev->advertising = phydev->supported;
priv->phydev = phydev;
phy_config(phydev);
return 1;
}
/* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
*/
static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
{
struct eth_device *dev;
int i;
struct tsec_private *priv;
dev = (struct eth_device *)malloc(sizeof *dev);
if (NULL == dev)
return 0;
memset(dev, 0, sizeof *dev);
priv = (struct tsec_private *)malloc(sizeof(*priv));
if (NULL == priv)
return 0;
privlist[num_tsecs++] = priv;
priv->regs = tsec_info->regs;
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
priv->flags = tsec_info->flags;
sprintf(dev->name, tsec_info->devname);
priv->interface = tsec_info->interface;
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
dev->iobase = 0;
dev->priv = priv;
dev->init = tsec_init;
dev->halt = tsec_halt;
dev->send = tsec_send;
dev->recv = tsec_recv;
#ifdef CONFIG_MCAST_TFTP
dev->mcast = tsec_mcast_addr;
#endif
/* Tell u-boot to get the addr from the env */
for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
eth_register(dev);
/* Reset the MAC */
setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
/* Try to initialize PHY here, and return */
return init_phy(dev);
}
/*
* Initialize all the TSEC devices
*
* Returns the number of TSEC devices that were initialized
*/
int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
{
int i;
int ret, count = 0;
for (i = 0; i < num; i++) {
ret = tsec_initialize(bis, &tsecs[i]);
if (ret > 0)
count += ret;
}
return count;
}
int tsec_standard_init(bd_t *bis)
{
struct fsl_pq_mdio_info info;
info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &info);
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
}
|
1001-study-uboot
|
drivers/net/tsec.c
|
C
|
gpl3
| 18,165
|
#ifndef CS8900_H
#define CS8900_H
/*
* Cirrus Logic CS8900A Ethernet
*
* (C) 2009 Ben Warren , biggerbadderben@gmail.com
* Converted to use CONFIG_NET_MULTI API
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* Copyright (C) 1999 Ben Williamson <benw@pobox.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is loaded into SRAM in bootstrap mode, where it waits
* for commands on UART1 to read and write memory, jump to code etc.
* A design goal for this program is to be entirely independent of the
* target board. Anything with a CL-PS7111 or EP7211 should be able to run
* this code in bootstrap mode. All the board specifics can be handled on
* the host.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/types.h>
#include <config.h>
#define CS8900_DRIVERNAME "CS8900"
/* although the registers are 16 bit, they are 32-bit aligned on the
EDB7111. so we have to read them as 32-bit registers and ignore the
upper 16-bits. i'm not sure if this holds for the EDB7211. */
#ifdef CONFIG_CS8900_BUS16
/* 16 bit aligned registers, 16 bit wide */
#define CS8900_REG u16
#elif defined(CONFIG_CS8900_BUS32)
/* 32 bit aligned registers, 16 bit wide (we ignore upper 16 bits) */
#define CS8900_REG u32
#else
#error unknown bussize ...
#endif
struct cs8900_regs {
CS8900_REG rtdata;
CS8900_REG pad0;
CS8900_REG txcmd;
CS8900_REG txlen;
CS8900_REG isq;
CS8900_REG pptr;
CS8900_REG pdata;
};
struct cs8900_priv {
struct cs8900_regs *regs;
};
#define ISQ_RxEvent 0x04
#define ISQ_TxEvent 0x08
#define ISQ_BufEvent 0x0C
#define ISQ_RxMissEvent 0x10
#define ISQ_TxColEvent 0x12
#define ISQ_EventMask 0x3F
/* packet page register offsets */
/* bus interface registers */
#define PP_ChipID 0x0000 /* Chip identifier - must be 0x630E */
#define PP_ChipRev 0x0002 /* Chip revision, model codes */
#define PP_IntReg 0x0022 /* Interrupt configuration */
#define PP_IntReg_IRQ0 0x0000 /* Use INTR0 pin */
#define PP_IntReg_IRQ1 0x0001 /* Use INTR1 pin */
#define PP_IntReg_IRQ2 0x0002 /* Use INTR2 pin */
#define PP_IntReg_IRQ3 0x0003 /* Use INTR3 pin */
/* status and control registers */
#define PP_RxCFG 0x0102 /* Receiver configuration */
#define PP_RxCFG_Skip1 0x0040 /* Skip (i.e. discard) current frame */
#define PP_RxCFG_Stream 0x0080 /* Enable streaming mode */
#define PP_RxCFG_RxOK 0x0100 /* RxOK interrupt enable */
#define PP_RxCFG_RxDMAonly 0x0200 /* Use RxDMA for all frames */
#define PP_RxCFG_AutoRxDMA 0x0400 /* Select RxDMA automatically */
#define PP_RxCFG_BufferCRC 0x0800 /* Include CRC characters in frame */
#define PP_RxCFG_CRC 0x1000 /* Enable interrupt on CRC error */
#define PP_RxCFG_RUNT 0x2000 /* Enable interrupt on RUNT frames */
#define PP_RxCFG_EXTRA 0x4000 /* Enable interrupt on frames with extra data */
#define PP_RxCTL 0x0104 /* Receiver control */
#define PP_RxCTL_IAHash 0x0040 /* Accept frames that match hash */
#define PP_RxCTL_Promiscuous 0x0080 /* Accept any frame */
#define PP_RxCTL_RxOK 0x0100 /* Accept well formed frames */
#define PP_RxCTL_Multicast 0x0200 /* Accept multicast frames */
#define PP_RxCTL_IA 0x0400 /* Accept frame that matches IA */
#define PP_RxCTL_Broadcast 0x0800 /* Accept broadcast frames */
#define PP_RxCTL_CRC 0x1000 /* Accept frames with bad CRC */
#define PP_RxCTL_RUNT 0x2000 /* Accept runt frames */
#define PP_RxCTL_EXTRA 0x4000 /* Accept frames that are too long */
#define PP_TxCFG 0x0106 /* Transmit configuration */
#define PP_TxCFG_CRS 0x0040 /* Enable interrupt on loss of carrier */
#define PP_TxCFG_SQE 0x0080 /* Enable interrupt on Signal Quality Error */
#define PP_TxCFG_TxOK 0x0100 /* Enable interrupt on successful xmits */
#define PP_TxCFG_Late 0x0200 /* Enable interrupt on "out of window" */
#define PP_TxCFG_Jabber 0x0400 /* Enable interrupt on jabber detect */
#define PP_TxCFG_Collision 0x0800 /* Enable interrupt if collision */
#define PP_TxCFG_16Collisions 0x8000 /* Enable interrupt if > 16 collisions */
#define PP_TxCmd 0x0108 /* Transmit command status */
#define PP_TxCmd_TxStart_5 0x0000 /* Start after 5 bytes in buffer */
#define PP_TxCmd_TxStart_381 0x0040 /* Start after 381 bytes in buffer */
#define PP_TxCmd_TxStart_1021 0x0080 /* Start after 1021 bytes in buffer */
#define PP_TxCmd_TxStart_Full 0x00C0 /* Start after all bytes loaded */
#define PP_TxCmd_Force 0x0100 /* Discard any pending packets */
#define PP_TxCmd_OneCollision 0x0200 /* Abort after a single collision */
#define PP_TxCmd_NoCRC 0x1000 /* Do not add CRC */
#define PP_TxCmd_NoPad 0x2000 /* Do not pad short packets */
#define PP_BufCFG 0x010A /* Buffer configuration */
#define PP_BufCFG_SWI 0x0040 /* Force interrupt via software */
#define PP_BufCFG_RxDMA 0x0080 /* Enable interrupt on Rx DMA */
#define PP_BufCFG_TxRDY 0x0100 /* Enable interrupt when ready for Tx */
#define PP_BufCFG_TxUE 0x0200 /* Enable interrupt in Tx underrun */
#define PP_BufCFG_RxMiss 0x0400 /* Enable interrupt on missed Rx packets */
#define PP_BufCFG_Rx128 0x0800 /* Enable Rx interrupt after 128 bytes */
#define PP_BufCFG_TxCol 0x1000 /* Enable int on Tx collision ctr overflow */
#define PP_BufCFG_Miss 0x2000 /* Enable int on Rx miss ctr overflow */
#define PP_BufCFG_RxDest 0x8000 /* Enable int on Rx dest addr match */
#define PP_LineCTL 0x0112 /* Line control */
#define PP_LineCTL_Rx 0x0040 /* Enable receiver */
#define PP_LineCTL_Tx 0x0080 /* Enable transmitter */
#define PP_LineCTL_AUIonly 0x0100 /* AUI interface only */
#define PP_LineCTL_AutoAUI10BT 0x0200 /* Autodetect AUI or 10BaseT interface */
#define PP_LineCTL_ModBackoffE 0x0800 /* Enable modified backoff algorithm */
#define PP_LineCTL_PolarityDis 0x1000 /* Disable Rx polarity autodetect */
#define PP_LineCTL_2partDefDis 0x2000 /* Disable two-part defferal */
#define PP_LineCTL_LoRxSquelch 0x4000 /* Reduce receiver squelch threshold */
#define PP_SelfCTL 0x0114 /* Chip self control */
#define PP_SelfCTL_Reset 0x0040 /* Self-clearing reset */
#define PP_SelfCTL_SWSuspend 0x0100 /* Initiate suspend mode */
#define PP_SelfCTL_HWSleepE 0x0200 /* Enable SLEEP input */
#define PP_SelfCTL_HWStandbyE 0x0400 /* Enable standby mode */
#define PP_SelfCTL_HC0E 0x1000 /* use HCB0 for LINK LED */
#define PP_SelfCTL_HC1E 0x2000 /* use HCB1 for BSTATUS LED */
#define PP_SelfCTL_HCB0 0x4000 /* control LINK LED if HC0E set */
#define PP_SelfCTL_HCB1 0x8000 /* control BSTATUS LED if HC1E set */
#define PP_BusCTL 0x0116 /* Bus control */
#define PP_BusCTL_ResetRxDMA 0x0040 /* Reset RxDMA pointer */
#define PP_BusCTL_DMAextend 0x0100 /* Extend DMA cycle */
#define PP_BusCTL_UseSA 0x0200 /* Assert MEMCS16 on address decode */
#define PP_BusCTL_MemoryE 0x0400 /* Enable memory mode */
#define PP_BusCTL_DMAburst 0x0800 /* Limit DMA access burst */
#define PP_BusCTL_IOCHRDYE 0x1000 /* Set IOCHRDY high impedence */
#define PP_BusCTL_RxDMAsize 0x2000 /* Set DMA buffer size 64KB */
#define PP_BusCTL_EnableIRQ 0x8000 /* Generate interrupt on interrupt event */
#define PP_TestCTL 0x0118 /* Test control */
#define PP_TestCTL_DisableLT 0x0080 /* Disable link status */
#define PP_TestCTL_ENDECloop 0x0200 /* Internal loopback */
#define PP_TestCTL_AUIloop 0x0400 /* AUI loopback */
#define PP_TestCTL_DisBackoff 0x0800 /* Disable backoff algorithm */
#define PP_TestCTL_FDX 0x4000 /* Enable full duplex mode */
#define PP_ISQ 0x0120 /* Interrupt Status Queue */
#define PP_RER 0x0124 /* Receive event */
#define PP_RER_IAHash 0x0040 /* Frame hash match */
#define PP_RER_Dribble 0x0080 /* Frame had 1-7 extra bits after last byte */
#define PP_RER_RxOK 0x0100 /* Frame received with no errors */
#define PP_RER_Hashed 0x0200 /* Frame address hashed OK */
#define PP_RER_IA 0x0400 /* Frame address matched IA */
#define PP_RER_Broadcast 0x0800 /* Broadcast frame */
#define PP_RER_CRC 0x1000 /* Frame had CRC error */
#define PP_RER_RUNT 0x2000 /* Runt frame */
#define PP_RER_EXTRA 0x4000 /* Frame was too long */
#define PP_TER 0x0128 /* Transmit event */
#define PP_TER_CRS 0x0040 /* Carrier lost */
#define PP_TER_SQE 0x0080 /* Signal Quality Error */
#define PP_TER_TxOK 0x0100 /* Packet sent without error */
#define PP_TER_Late 0x0200 /* Out of window */
#define PP_TER_Jabber 0x0400 /* Stuck transmit? */
#define PP_TER_NumCollisions 0x7800 /* Number of collisions */
#define PP_TER_16Collisions 0x8000 /* > 16 collisions */
#define PP_BER 0x012C /* Buffer event */
#define PP_BER_SWint 0x0040 /* Software interrupt */
#define PP_BER_RxDMAFrame 0x0080 /* Received framed DMAed */
#define PP_BER_Rdy4Tx 0x0100 /* Ready for transmission */
#define PP_BER_TxUnderrun 0x0200 /* Transmit underrun */
#define PP_BER_RxMiss 0x0400 /* Received frame missed */
#define PP_BER_Rx128 0x0800 /* 128 bytes received */
#define PP_BER_RxDest 0x8000 /* Received framed passed address filter */
#define PP_RxMiss 0x0130 /* Receiver miss counter */
#define PP_TxCol 0x0132 /* Transmit collision counter */
#define PP_LineSTAT 0x0134 /* Line status */
#define PP_LineSTAT_LinkOK 0x0080 /* Line is connected and working */
#define PP_LineSTAT_AUI 0x0100 /* Connected via AUI */
#define PP_LineSTAT_10BT 0x0200 /* Connected via twisted pair */
#define PP_LineSTAT_Polarity 0x1000 /* Line polarity OK (10BT only) */
#define PP_LineSTAT_CRS 0x4000 /* Frame being received */
#define PP_SelfSTAT 0x0136 /* Chip self status */
#define PP_SelfSTAT_33VActive 0x0040 /* supply voltage is 3.3V */
#define PP_SelfSTAT_InitD 0x0080 /* Chip initialization complete */
#define PP_SelfSTAT_SIBSY 0x0100 /* EEPROM is busy */
#define PP_SelfSTAT_EEPROM 0x0200 /* EEPROM present */
#define PP_SelfSTAT_EEPROM_OK 0x0400 /* EEPROM checks out */
#define PP_SelfSTAT_ELPresent 0x0800 /* External address latch logic available */
#define PP_SelfSTAT_EEsize 0x1000 /* Size of EEPROM */
#define PP_BusSTAT 0x0138 /* Bus status */
#define PP_BusSTAT_TxBid 0x0080 /* Tx error */
#define PP_BusSTAT_TxRDY 0x0100 /* Ready for Tx data */
#define PP_TDR 0x013C /* AUI Time Domain Reflectometer */
/* initiate transmit registers */
#define PP_TxCommand 0x0144 /* Tx Command */
#define PP_TxLength 0x0146 /* Tx Length */
/* address filter registers */
#define PP_LAF 0x0150 /* Logical address filter (6 bytes) */
#define PP_IA 0x0158 /* Individual address (MAC) */
/* EEPROM Kram */
#define SI_BUSY 0x0100
#define PP_EECMD 0x0040 /* NVR Interface Command register */
#define PP_EEData 0x0042 /* NVR Interface Data Register */
#define EEPROM_WRITE_EN 0x00F0
#define EEPROM_WRITE_DIS 0x0000
#define EEPROM_WRITE_CMD 0x0100
#define EEPROM_READ_CMD 0x0200
#define EEPROM_ERASE_CMD 0x0300
/* Exported functions */
int cs8900_e2prom_read(struct eth_device *dev, uchar, ushort *);
int cs8900_e2prom_write(struct eth_device *dev, uchar, ushort);
#endif /* CS8900_H */
|
1001-study-uboot
|
drivers/net/cs8900.h
|
C
|
gpl3
| 12,424
|
/*
* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _DW_ETH_H
#define _DW_ETH_H
#define CONFIG_TX_DESCR_NUM 16
#define CONFIG_RX_DESCR_NUM 16
#define CONFIG_ETH_BUFSIZE 2048
#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
struct eth_mac_regs {
u32 conf; /* 0x00 */
u32 framefilt; /* 0x04 */
u32 hashtablehigh; /* 0x08 */
u32 hashtablelow; /* 0x0c */
u32 miiaddr; /* 0x10 */
u32 miidata; /* 0x14 */
u32 flowcontrol; /* 0x18 */
u32 vlantag; /* 0x1c */
u32 version; /* 0x20 */
u8 reserved_1[20];
u32 intreg; /* 0x38 */
u32 intmask; /* 0x3c */
u32 macaddr0hi; /* 0x40 */
u32 macaddr0lo; /* 0x44 */
};
/* MAC configuration register definitions */
#define FRAMEBURSTENABLE (1 << 21)
#define MII_PORTSELECT (1 << 15)
#define FES_100 (1 << 14)
#define DISABLERXOWN (1 << 13)
#define FULLDPLXMODE (1 << 11)
#define RXENABLE (1 << 2)
#define TXENABLE (1 << 3)
/* MII address register definitions */
#define MII_BUSY (1 << 0)
#define MII_WRITE (1 << 1)
#define MII_CLKRANGE_60_100M (0)
#define MII_CLKRANGE_100_150M (0x4)
#define MII_CLKRANGE_20_35M (0x8)
#define MII_CLKRANGE_35_60M (0xC)
#define MII_CLKRANGE_150_250M (0x10)
#define MII_CLKRANGE_250_300M (0x14)
#define MIIADDRSHIFT (11)
#define MIIREGSHIFT (6)
#define MII_REGMSK (0x1F << 6)
#define MII_ADDRMSK (0x1F << 11)
struct eth_dma_regs {
u32 busmode; /* 0x00 */
u32 txpolldemand; /* 0x04 */
u32 rxpolldemand; /* 0x08 */
u32 rxdesclistaddr; /* 0x0c */
u32 txdesclistaddr; /* 0x10 */
u32 status; /* 0x14 */
u32 opmode; /* 0x18 */
u32 intenable; /* 0x1c */
u8 reserved[40];
u32 currhosttxdesc; /* 0x48 */
u32 currhostrxdesc; /* 0x4c */
u32 currhosttxbuffaddr; /* 0x50 */
u32 currhostrxbuffaddr; /* 0x54 */
};
#define DW_DMA_BASE_OFFSET (0x1000)
/* Bus mode register definitions */
#define FIXEDBURST (1 << 16)
#define PRIORXTX_41 (3 << 14)
#define PRIORXTX_31 (2 << 14)
#define PRIORXTX_21 (1 << 14)
#define PRIORXTX_11 (0 << 14)
#define BURST_1 (1 << 8)
#define BURST_2 (2 << 8)
#define BURST_4 (4 << 8)
#define BURST_8 (8 << 8)
#define BURST_16 (16 << 8)
#define BURST_32 (32 << 8)
#define RXHIGHPRIO (1 << 1)
#define DMAMAC_SRST (1 << 0)
/* Poll demand definitions */
#define POLL_DATA (0xFFFFFFFF)
/* Operation mode definitions */
#define STOREFORWARD (1 << 21)
#define FLUSHTXFIFO (1 << 20)
#define TXSTART (1 << 13)
#define TXSECONDFRAME (1 << 2)
#define RXSTART (1 << 1)
/* Descriptior related definitions */
#define MAC_MAX_FRAME_SZ (2048)
struct dmamacdescr {
u32 txrx_status;
u32 dmamac_cntl;
void *dmamac_addr;
struct dmamacdescr *dmamac_next;
};
/*
* txrx_status definitions
*/
/* tx status bits definitions */
#if defined(CONFIG_DW_ALTDESCRIPTOR)
#define DESC_TXSTS_OWNBYDMA (1 << 31)
#define DESC_TXSTS_TXINT (1 << 30)
#define DESC_TXSTS_TXLAST (1 << 29)
#define DESC_TXSTS_TXFIRST (1 << 28)
#define DESC_TXSTS_TXCRCDIS (1 << 27)
#define DESC_TXSTS_TXPADDIS (1 << 26)
#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22)
#define DESC_TXSTS_TXRINGEND (1 << 21)
#define DESC_TXSTS_TXCHAIN (1 << 20)
#define DESC_TXSTS_MSK (0x1FFFF << 0)
#else
#define DESC_TXSTS_OWNBYDMA (1 << 31)
#define DESC_TXSTS_MSK (0x1FFFF << 0)
#endif
/* rx status bits definitions */
#define DESC_RXSTS_OWNBYDMA (1 << 31)
#define DESC_RXSTS_DAFILTERFAIL (1 << 30)
#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16)
#define DESC_RXSTS_FRMLENSHFT (16)
#define DESC_RXSTS_ERROR (1 << 15)
#define DESC_RXSTS_RXTRUNCATED (1 << 14)
#define DESC_RXSTS_SAFILTERFAIL (1 << 13)
#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12)
#define DESC_RXSTS_RXDAMAGED (1 << 11)
#define DESC_RXSTS_RXVLANTAG (1 << 10)
#define DESC_RXSTS_RXFIRST (1 << 9)
#define DESC_RXSTS_RXLAST (1 << 8)
#define DESC_RXSTS_RXIPC_GIANT (1 << 7)
#define DESC_RXSTS_RXCOLLISION (1 << 6)
#define DESC_RXSTS_RXFRAMEETHER (1 << 5)
#define DESC_RXSTS_RXWATCHDOG (1 << 4)
#define DESC_RXSTS_RXMIIERROR (1 << 3)
#define DESC_RXSTS_RXDRIBBLING (1 << 2)
#define DESC_RXSTS_RXCRC (1 << 1)
/*
* dmamac_cntl definitions
*/
/* tx control bits definitions */
#if defined(CONFIG_DW_ALTDESCRIPTOR)
#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0)
#define DESC_TXCTRL_SIZE1SHFT (0)
#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16)
#define DESC_TXCTRL_SIZE2SHFT (16)
#else
#define DESC_TXCTRL_TXINT (1 << 31)
#define DESC_TXCTRL_TXLAST (1 << 30)
#define DESC_TXCTRL_TXFIRST (1 << 29)
#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27)
#define DESC_TXCTRL_TXCRCDIS (1 << 26)
#define DESC_TXCTRL_TXRINGEND (1 << 25)
#define DESC_TXCTRL_TXCHAIN (1 << 24)
#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0)
#define DESC_TXCTRL_SIZE1SHFT (0)
#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11)
#define DESC_TXCTRL_SIZE2SHFT (11)
#endif
/* rx control bits definitions */
#if defined(CONFIG_DW_ALTDESCRIPTOR)
#define DESC_RXCTRL_RXINTDIS (1 << 31)
#define DESC_RXCTRL_RXRINGEND (1 << 15)
#define DESC_RXCTRL_RXCHAIN (1 << 14)
#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0)
#define DESC_RXCTRL_SIZE1SHFT (0)
#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16)
#define DESC_RXCTRL_SIZE2SHFT (16)
#else
#define DESC_RXCTRL_RXINTDIS (1 << 31)
#define DESC_RXCTRL_RXRINGEND (1 << 25)
#define DESC_RXCTRL_RXCHAIN (1 << 24)
#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0)
#define DESC_RXCTRL_SIZE1SHFT (0)
#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11)
#define DESC_RXCTRL_SIZE2SHFT (11)
#endif
struct dw_eth_dev {
u32 address;
u32 speed;
u32 duplex;
u32 tx_currdescnum;
u32 rx_currdescnum;
u32 padding;
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
char txbuffs[TX_TOTAL_BUFSIZE];
char rxbuffs[RX_TOTAL_BUFSIZE];
struct eth_mac_regs *mac_regs_p;
struct eth_dma_regs *dma_regs_p;
struct eth_device *dev;
} __attribute__ ((aligned(8)));
/* Speed specific definitions */
#define SPEED_10M 1
#define SPEED_100M 2
#define SPEED_1000M 3
/* Duplex mode specific definitions */
#define HALF_DUPLEX 1
#define FULL_DUPLEX 2
#endif
|
1001-study-uboot
|
drivers/net/designware.h
|
C
|
gpl3
| 7,126
|
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
* Jun-jie Zhang <b18070@freescale.com>
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <miiphy.h>
#include <phy.h>
#include <fsl_mdio.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/fsl_enet.h>
void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
int dev_addr, int regnum, int value)
{
int timeout = 1000000;
out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
out_be32(&phyregs->miimcon, value);
asm("sync");
while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
;
}
int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
int dev_addr, int regnum)
{
int value;
int timeout = 1000000;
/* Put the address of the phy, and the register
* number into MIIMADD */
out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
/* Clear the command register, and wait */
out_be32(&phyregs->miimcom, 0);
asm("sync");
/* Initiate a read command, and wait */
out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
asm("sync");
/* Wait for the the indication that the read is done */
while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
&& timeout--)
;
/* Grab the value read from the PHY */
value = in_be32(&phyregs->miimstat);
return value;
}
static int fsl_pq_mdio_reset(struct mii_dev *bus)
{
struct tsec_mii_mng *regs = bus->priv;
/* Reset MII (due to new addresses) */
out_be32(®s->miimcfg, MIIMCFG_RESET_MGMT);
out_be32(®s->miimcfg, MIIMCFG_INIT_VALUE);
while (in_be32(®s->miimind) & MIIMIND_BUSY)
;
return 0;
}
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
{
struct tsec_mii_mng *phyregs = bus->priv;
return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
}
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
u16 value)
{
struct tsec_mii_mng *phyregs = bus->priv;
tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
return 0;
}
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
{
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate FSL MDIO bus\n");
return -1;
}
bus->read = tsec_phy_read;
bus->write = tsec_phy_write;
bus->reset = fsl_pq_mdio_reset;
sprintf(bus->name, info->name);
bus->priv = info->regs;
return mdio_register(bus);
}
|
1001-study-uboot
|
drivers/net/fsl_mdio.c
|
C
|
gpl3
| 3,122
|
/*
* (C) Copyright 2003-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file is based on mpc4200fec.c,
* (C) Copyright Motorola, Inc., 2000
*/
#include <common.h>
#include <mpc5xxx.h>
#include <mpc5xxx_sdma.h>
#include <malloc.h>
#include <net.h>
#include <netdev.h>
#include <miiphy.h>
#include "mpc5xxx_fec.h"
DECLARE_GLOBAL_DATA_PTR;
/* #define DEBUG 0x28 */
#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
#error "CONFIG_MII has to be defined!"
#endif
#if (DEBUG & 0x60)
static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
#endif /* DEBUG */
typedef struct {
uint8 data[1500]; /* actual data */
int length; /* actual length */
int used; /* buffer in use or not */
uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
} NBUF;
int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 *retVal);
int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis);
/********************************************************************/
#if (DEBUG & 0x2)
static void mpc5xxx_fec_phydump (char *devname)
{
uint16 phyStatus, i;
uint8 phyAddr = CONFIG_PHY_ADDR;
uint8 reg_mask[] = {
#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
/* regs to print: 0...7, 16...19, 21, 23, 24 */
1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
#else
/* regs to print: 0...8, 16...20 */
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
#endif
};
for (i = 0; i < 32; i++) {
if (reg_mask[i]) {
miiphy_read(devname, phyAddr, i, &phyStatus);
printf("Mii reg %d: 0x%04x\n", i, phyStatus);
}
}
}
#endif
/********************************************************************/
static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
{
int ix;
char *data;
static int once = 0;
for (ix = 0; ix < FEC_RBD_NUM; ix++) {
if (!once) {
data = (char *)malloc(FEC_MAX_PKT_SIZE);
if (data == NULL) {
printf ("RBD INIT FAILED\n");
return -1;
}
fec->rbdBase[ix].dataPointer = (uint32)data;
}
fec->rbdBase[ix].status = FEC_RBD_EMPTY;
fec->rbdBase[ix].dataLength = 0;
}
once ++;
/*
* have the last RBD to close the ring
*/
fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
fec->rbdIndex = 0;
return 0;
}
/********************************************************************/
static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
{
int ix;
for (ix = 0; ix < FEC_TBD_NUM; ix++) {
fec->tbdBase[ix].status = 0;
}
/*
* Have the last TBD to close the ring
*/
fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
/*
* Initialize some indices
*/
fec->tbdIndex = 0;
fec->usedTbdIndex = 0;
fec->cleanTbdNum = FEC_TBD_NUM;
}
/********************************************************************/
static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
{
/*
* Reset buffer descriptor as empty
*/
if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
else
pRbd->status = FEC_RBD_EMPTY;
pRbd->dataLength = 0;
/*
* Now, we have an empty RxBD, restart the SmartDMA receive task
*/
SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
/*
* Increment BD count
*/
fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
}
/********************************************************************/
static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
{
volatile FEC_TBD *pUsedTbd;
#if (DEBUG & 0x1)
printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
fec->cleanTbdNum, fec->usedTbdIndex);
#endif
/*
* process all the consumed TBDs
*/
while (fec->cleanTbdNum < FEC_TBD_NUM) {
pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
if (pUsedTbd->status & FEC_TBD_READY) {
#if (DEBUG & 0x20)
printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
#endif
return;
}
/*
* clean this buffer descriptor
*/
if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
pUsedTbd->status = FEC_TBD_WRAP;
else
pUsedTbd->status = 0;
/*
* update some indeces for a correct handling of the TBD ring
*/
fec->cleanTbdNum++;
fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
}
}
/********************************************************************/
static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
{
uint8 currByte; /* byte for which to compute the CRC */
int byte; /* loop - counter */
int bit; /* loop - counter */
uint32 crc = 0xffffffff; /* initial value */
/*
* The algorithm used is the following:
* we loop on each of the six bytes of the provided address,
* and we compute the CRC by left-shifting the previous
* value by one position, so that each bit in the current
* byte of the address may contribute the calculation. If
* the latter and the MSB in the CRC are different, then
* the CRC value so computed is also ex-ored with the
* "polynomium generator". The current byte of the address
* is also shifted right by one bit at each iteration.
* This is because the CRC generatore in hardware is implemented
* as a shift-register with as many ex-ores as the radixes
* in the polynomium. This suggests that we represent the
* polynomiumm itself as a 32-bit constant.
*/
for (byte = 0; byte < 6; byte++) {
currByte = mac[byte];
for (bit = 0; bit < 8; bit++) {
if ((currByte & 0x01) ^ (crc & 0x01)) {
crc >>= 1;
crc = crc ^ 0xedb88320;
} else {
crc >>= 1;
}
currByte >>= 1;
}
}
crc = crc >> 26;
/*
* Set individual hash table register
*/
if (crc >= 32) {
fec->eth->iaddr1 = (1 << (crc - 32));
fec->eth->iaddr2 = 0;
} else {
fec->eth->iaddr1 = 0;
fec->eth->iaddr2 = (1 << crc);
}
/*
* Set physical address
*/
fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
}
/********************************************************************/
static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
{
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
#if (DEBUG & 0x1)
printf ("mpc5xxx_fec_init... Begin\n");
#endif
mpc5xxx_fec_init_phy(dev, bis);
/*
* Call board-specific PHY fixups (if any)
*/
#ifdef CONFIG_RESET_PHY_R
reset_phy();
#endif
/*
* Initialize RxBD/TxBD rings
*/
mpc5xxx_fec_rbd_init(fec);
mpc5xxx_fec_tbd_init(fec);
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
fec->eth->ievent = 0xffffffff;
/*
* Set interrupt mask register
*/
fec->eth->imask = 0x00000000;
/*
* Set FEC-Lite receive control register(R_CNTRL):
*/
if (fec->xcv_type == SEVENWIRE) {
/*
* Frame length=1518; 7-wire mode
*/
fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
} else {
/*
* Frame length=1518; MII mode;
*/
fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
}
fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
/*
* Set Opcode/Pause Duration Register
*/
fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
/*
* Set Rx FIFO alarm and granularity value
*/
fec->eth->rfifo_cntrl = 0x0c000000
| (fec->eth->rfifo_cntrl & ~0x0f000000);
fec->eth->rfifo_alarm = 0x0000030c;
#if (DEBUG & 0x22)
if (fec->eth->rfifo_status & 0x00700000 ) {
printf("mpc5xxx_fec_init() RFIFO error\n");
}
#endif
/*
* Set Tx FIFO granularity value
*/
fec->eth->tfifo_cntrl = 0x0c000000
| (fec->eth->tfifo_cntrl & ~0x0f000000);
#if (DEBUG & 0x2)
printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
#endif
/*
* Set transmit fifo watermark register(X_WMRK), default = 64
*/
fec->eth->tfifo_alarm = 0x00000080;
fec->eth->x_wmrk = 0x2;
/*
* Set individual address filter for unicast address
* and set physical address registers.
*/
mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
/*
* Set multicast address filter
*/
fec->eth->gaddr1 = 0x00000000;
fec->eth->gaddr2 = 0x00000000;
/*
* Turn ON cheater FSM: ????
*/
fec->eth->xmit_fsm = 0x03000000;
/*
* Turn off COMM bus prefetch in the MPC5200 BestComm. It doesn't
* work w/ the current receive task.
*/
sdma->PtdCntrl |= 0x00000001;
/*
* Set priority of different initiators
*/
sdma->IPR0 = 7; /* always */
sdma->IPR3 = 6; /* Eth RX */
sdma->IPR4 = 5; /* Eth Tx */
/*
* Clear SmartDMA task interrupt pending bits
*/
SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
/*
* Initialize SmartDMA parameters stored in SRAM
*/
*(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
*(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
*(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
*(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
/*
* Enable FEC-Lite controller
*/
fec->eth->ecntrl |= 0x00000006;
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc5xxx_fec_phydump (dev->name);
#endif
/*
* Enable SmartDMA receive task
*/
SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
#if (DEBUG & 0x1)
printf("mpc5xxx_fec_init... Done \n");
#endif
return 1;
}
/********************************************************************/
static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
{
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
static int initialized = 0;
if(initialized)
return 0;
initialized = 1;
#if (DEBUG & 0x1)
printf ("mpc5xxx_fec_init_phy... Begin\n");
#endif
/*
* Initialize GPIO pins
*/
if (fec->xcv_type == SEVENWIRE) {
/* 10MBit with 7-wire operation */
#if defined(CONFIG_TOTAL5200)
/* 7-wire and USB2 on Ethernet */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
#else /* !CONFIG_TOTAL5200 */
/* 7-wire only */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
#endif /* CONFIG_TOTAL5200 */
} else {
/* 100MBit with MD operation */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
}
/*
* Clear FEC-Lite interrupt event register(IEVENT)
*/
fec->eth->ievent = 0xffffffff;
/*
* Set interrupt mask register
*/
fec->eth->imask = 0x00000000;
/*
* In original Promess-provided code PHY initialization is disabled with the
* following comment: "Phy initialization is DISABLED for now. There was a
* problem with running 100 Mbps on PRO board". Thus we temporarily disable
* PHY initialization for the Motion-PRO board, until a proper fix is found.
*/
if (fec->xcv_type != SEVENWIRE) {
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
}
if (fec->xcv_type != SEVENWIRE) {
/*
* Initialize PHY(LXT971A):
*
* Generally, on power up, the LXT971A reads its configuration
* pins to check for forced operation, If not cofigured for
* forced operation, it uses auto-negotiation/parallel detection
* to automatically determine line operating conditions.
* If the PHY device on the other side of the link supports
* auto-negotiation, the LXT971A auto-negotiates with it
* using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
* support auto-negotiation, the LXT971A automatically detects
* the presence of either link pulses(10Mbps PHY) or Idle
* symbols(100Mbps) and sets its operating conditions accordingly.
*
* When auto-negotiation is controlled by software, the following
* steps are recommended.
*
* Note:
* The physical address is dependent on hardware configuration.
*
*/
int timeout = 1;
uint16 phyStatus;
/*
* Reset PHY, then delay 300ns
*/
miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
udelay(1000);
#if defined(CONFIG_UC101) || defined(CONFIG_MUCMC52)
/* Set the LED configuration Register for the UC101
and MUCMC52 Board */
miiphy_write(dev->name, phyAddr, 0x14, 0x4122);
#endif
if (fec->xcv_type == MII10) {
/*
* Force 10Base-T, FDX operation
*/
#if (DEBUG & 0x2)
printf("Forcing 10 Mbps ethernet link... ");
#endif
miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
/*
miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
*/
miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
timeout = 20;
do { /* wait for link status to go down */
udelay(10000);
if ((timeout--) == 0) {
#if (DEBUG & 0x2)
printf("hmmm, should not have waited...");
#endif
break;
}
miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf("=");
#endif
} while ((phyStatus & 0x0004)); /* !link up */
timeout = 1000;
do { /* wait for link status to come back up */
udelay(10000);
if ((timeout--) == 0) {
printf("failed. Link is down.\n");
break;
}
miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
#if (DEBUG & 0x2)
printf("+");
#endif
} while (!(phyStatus & 0x0004)); /* !link up */
#if (DEBUG & 0x2)
printf ("done.\n");
#endif
} else { /* MII100 */
/*
* Set the auto-negotiation advertisement register bits
*/
miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
/*
* Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
*/
miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
/*
* Wait for AN completion
*/
timeout = 5000;
do {
udelay(1000);
if ((timeout--) == 0) {
#if (DEBUG & 0x2)
printf("PHY auto neg 0 failed...\n");
#endif
return -1;
}
if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
#if (DEBUG & 0x2)
printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
#endif
return -1;
}
} while (!(phyStatus & 0x0004));
#if (DEBUG & 0x2)
printf("PHY auto neg complete! \n");
#endif
}
}
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc5xxx_fec_phydump (dev->name);
#endif
#if (DEBUG & 0x1)
printf("mpc5xxx_fec_init_phy... Done \n");
#endif
return 1;
}
/********************************************************************/
static void mpc5xxx_fec_halt(struct eth_device *dev)
{
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
int counter = 0xffff;
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)
mpc5xxx_fec_phydump (dev->name);
#endif
/*
* mask FEC chip interrupts
*/
fec->eth->imask = 0;
/*
* issue graceful stop command to the FEC transmitter if necessary
*/
fec->eth->x_cntrl |= 0x00000001;
/*
* wait for graceful stop to register
*/
while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
/*
* Disable SmartDMA tasks
*/
SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
/*
* Turn on COMM bus prefetch in the MPC5200 BestComm after we're
* done. It doesn't work w/ the current receive task.
*/
sdma->PtdCntrl &= ~0x00000001;
/*
* Disable the Ethernet Controller
*/
fec->eth->ecntrl &= 0xfffffffd;
/*
* Clear FIFO status registers
*/
fec->eth->rfifo_status &= 0x00700000;
fec->eth->tfifo_status &= 0x00700000;
fec->eth->reset_cntrl = 0x01000000;
/*
* Issue a reset command to the FEC chip
*/
fec->eth->ecntrl |= 0x1;
/*
* wait at least 16 clock cycles
*/
udelay(10);
/* don't leave the MII speed set to zero */
if (fec->xcv_type != SEVENWIRE) {
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
}
#if (DEBUG & 0x3)
printf("Ethernet task stopped\n");
#endif
}
#if (DEBUG & 0x60)
/********************************************************************/
static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
{
uint16 phyAddr = CONFIG_PHY_ADDR;
uint16 phyStatus;
if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
miiphy_read(devname, phyAddr, 0x1, &phyStatus);
printf("\nphyStatus: 0x%04x\n", phyStatus);
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf("ievent: 0x%08x\n", fec->eth->ievent);
printf("x_status: 0x%08x\n", fec->eth->x_status);
printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
}
}
static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
{
uint16 phyAddr = CONFIG_PHY_ADDR;
uint16 phyStatus;
if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
miiphy_read(devname, phyAddr, 0x1, &phyStatus);
printf("\nphyStatus: 0x%04x\n", phyStatus);
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
printf("ievent: 0x%08x\n", fec->eth->ievent);
printf("x_status: 0x%08x\n", fec->eth->x_status);
printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
}
}
#endif /* DEBUG */
/********************************************************************/
static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
int data_length)
{
/*
* This routine transmits one frame. This routine only accepts
* 6-byte Ethernet addresses.
*/
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
volatile FEC_TBD *pTbd;
#if (DEBUG & 0x20)
printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
tfifo_print(dev->name, fec);
#endif
/*
* Clear Tx BD ring at first
*/
mpc5xxx_fec_tbd_scrub(fec);
/*
* Check for valid length of data.
*/
if ((data_length > 1500) || (data_length <= 0)) {
return -1;
}
/*
* Check the number of vacant TxBDs.
*/
if (fec->cleanTbdNum < 1) {
#if (DEBUG & 0x20)
printf("No available TxBDs ...\n");
#endif
return -1;
}
/*
* Get the first TxBD to send the mac header
*/
pTbd = &fec->tbdBase[fec->tbdIndex];
pTbd->dataLength = data_length;
pTbd->dataPointer = (uint32)eth_data;
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
#if (DEBUG & 0x100)
printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
#endif
/*
* Kick the MII i/f
*/
if (fec->xcv_type != SEVENWIRE) {
uint16 phyStatus;
miiphy_read(dev->name, 0, 0x1, &phyStatus);
}
/*
* Enable SmartDMA transmit task
*/
#if (DEBUG & 0x20)
tfifo_print(dev->name, fec);
#endif
SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
#if (DEBUG & 0x20)
tfifo_print(dev->name, fec);
#endif
#if (DEBUG & 0x8)
printf( "+" );
#endif
fec->cleanTbdNum -= 1;
#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
printf ("smartDMA ethernet Tx task enabled\n");
#endif
/*
* wait until frame is sent .
*/
while (pTbd->status & FEC_TBD_READY) {
udelay(10);
#if (DEBUG & 0x8)
printf ("TDB status = %04x\n", pTbd->status);
#endif
}
return 0;
}
/********************************************************************/
static int mpc5xxx_fec_recv(struct eth_device *dev)
{
/*
* This command pulls one frame from the card
*/
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
unsigned long ievent;
int frame_length, len = 0;
NBUF *frame;
uchar buff[FEC_MAX_PKT_SIZE];
#if (DEBUG & 0x1)
printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
#endif
#if (DEBUG & 0x8)
printf( "-" );
#endif
/*
* Check if any critical events have happened
*/
ievent = fec->eth->ievent;
fec->eth->ievent = ievent;
if (ievent & 0x20060000) {
/* BABT, Rx/Tx FIFO errors */
mpc5xxx_fec_halt(dev);
mpc5xxx_fec_init(dev, NULL);
return 0;
}
if (ievent & 0x80000000) {
/* Heartbeat error */
fec->eth->x_cntrl |= 0x00000001;
}
if (ievent & 0x10000000) {
/* Graceful stop complete */
if (fec->eth->x_cntrl & 0x00000001) {
mpc5xxx_fec_halt(dev);
fec->eth->x_cntrl &= ~0x00000001;
mpc5xxx_fec_init(dev, NULL);
}
}
if (!(pRbd->status & FEC_RBD_EMPTY)) {
if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
((pRbd->dataLength - 4) > 14)) {
/*
* Get buffer address and size
*/
frame = (NBUF *)pRbd->dataPointer;
frame_length = pRbd->dataLength - 4;
#if (DEBUG & 0x20)
{
int i;
printf("recv data hdr:");
for (i = 0; i < 14; i++)
printf("%x ", *(frame->head + i));
printf("\n");
}
#endif
/*
* Fill the buffer and pass it to upper layers
*/
memcpy(buff, frame->head, 14);
memcpy(buff + 14, frame->data, frame_length);
NetReceive(buff, frame_length);
len = frame_length;
}
/*
* Reset buffer descriptor as empty
*/
mpc5xxx_fec_rbd_clean(fec, pRbd);
}
SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
return len;
}
/********************************************************************/
int mpc5xxx_fec_initialize(bd_t * bis)
{
mpc5xxx_fec_priv *fec;
struct eth_device *dev;
char *tmp, *end;
char env_enetaddr[6];
int i;
fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
dev = (struct eth_device *)malloc(sizeof(*dev));
memset(dev, 0, sizeof *dev);
fec->eth = (ethernet_regs *)MPC5XXX_FEC;
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
#if defined(CONFIG_MPC5xxx_FEC_MII100)
fec->xcv_type = MII100;
#elif defined(CONFIG_MPC5xxx_FEC_MII10)
fec->xcv_type = MII10;
#elif defined(CONFIG_MPC5xxx_FEC_SEVENWIRE)
fec->xcv_type = SEVENWIRE;
#else
#error fec->xcv_type not initialized.
#endif
if (fec->xcv_type != SEVENWIRE) {
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
}
dev->priv = (void *)fec;
dev->iobase = MPC5XXX_FEC;
dev->init = mpc5xxx_fec_init;
dev->halt = mpc5xxx_fec_halt;
dev->send = mpc5xxx_fec_send;
dev->recv = mpc5xxx_fec_recv;
sprintf(dev->name, "FEC");
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register (dev->name,
fec5xxx_miiphy_read, fec5xxx_miiphy_write);
#endif
/*
* Try to set the mac address now. The fec mac address is
* a garbage after reset. When not using fec for booting
* the Linux fec driver will try to work with this garbage.
*/
tmp = getenv("ethaddr");
if (tmp) {
for (i=0; i<6; i++) {
env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
if (tmp)
tmp = (*end) ? end+1 : end;
}
mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
}
return 1;
}
/* MII-interface related functions */
/********************************************************************/
int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */
uint32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
/*
* reading from any PHY's register is done by properly
* programming the FEC's MII data register.
*/
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
/*
* wait for the related interrupt
*/
while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
if (timeout == 0) {
#if (DEBUG & 0x2)
printf ("Read MDIO failed...\n");
#endif
return -1;
}
/*
* clear mii interrupt bit
*/
eth->ievent = 0x00800000;
/*
* it's now safe to read the PHY's register
*/
*retVal = (uint16) eth->mii_data;
return 0;
}
/********************************************************************/
int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
{
ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
uint32 reg; /* convenient holder for the PHY register */
uint32 phy; /* convenient holder for the PHY */
int timeout = 0xffff;
reg = regAddr << FEC_MII_DATA_RA_SHIFT;
phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
FEC_MII_DATA_TA | phy | reg | data);
/*
* wait for the MII interrupt
*/
while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
if (timeout == 0) {
#if (DEBUG & 0x2)
printf ("Write MDIO failed...\n");
#endif
return -1;
}
/*
* clear MII interrupt bit
*/
eth->ievent = 0x00800000;
return 0;
}
|
1001-study-uboot
|
drivers/net/mpc5xxx_fec.c
|
C
|
gpl3
| 25,095
|
/*
* (C) Copyright 2010
* Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
* Martin Krause, Martin.Krause@tqs.de
* reworked original enc28j60.c
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <net.h>
#include <spi.h>
#include <malloc.h>
#include <netdev.h>
#include <miiphy.h>
#include "enc28j60.h"
/*
* IMPORTANT: spi_claim_bus() and spi_release_bus()
* are called at begin and end of each of the following functions:
* enc_miiphy_read(), enc_miiphy_write(), enc_write_hwaddr(),
* enc_init(), enc_recv(), enc_send(), enc_halt()
* ALL other functions assume that the bus has already been claimed!
* Since NetReceive() might call enc_send() in return, the bus must be
* released, NetReceive() called and claimed again.
*/
/*
* Controller memory layout.
* We only allow 1 frame for transmission and reserve the rest
* for reception to handle as many broadcast packets as possible.
* Also use the memory from 0x0000 for receiver buffer. See errata pt. 5
* 0x0000 - 0x19ff 6656 bytes receive buffer
* 0x1a00 - 0x1fff 1536 bytes transmit buffer =
* control(1)+frame(1518)+status(7)+reserve(10).
*/
#define ENC_RX_BUF_START 0x0000
#define ENC_RX_BUF_END 0x19ff
#define ENC_TX_BUF_START 0x1a00
#define ENC_TX_BUF_END 0x1fff
#define ENC_MAX_FRM_LEN 1518
#define RX_RESET_COUNTER 1000
/*
* For non data transfer functions, like phy read/write, set hwaddr, init
* we do not need a full, time consuming init including link ready wait.
* This enum helps to bring the chip through the minimum necessary inits.
*/
enum enc_initstate {none=0, setupdone, linkready};
typedef struct enc_device {
struct eth_device *dev; /* back pointer */
struct spi_slave *slave;
int rx_reset_counter;
u16 next_pointer;
u8 bank; /* current bank in enc28j60 */
enum enc_initstate initstate;
} enc_dev_t;
/*
* enc_bset: set bits in a common register
* enc_bclr: clear bits in a common register
*
* making the reg parameter u8 will give a compile time warning if the
* functions are called with a register not accessible in all Banks
*/
static void enc_bset(enc_dev_t *enc, const u8 reg, const u8 data)
{
u8 dout[2];
dout[0] = CMD_BFS(reg);
dout[1] = data;
spi_xfer(enc->slave, 2 * 8, dout, NULL,
SPI_XFER_BEGIN | SPI_XFER_END);
}
static void enc_bclr(enc_dev_t *enc, const u8 reg, const u8 data)
{
u8 dout[2];
dout[0] = CMD_BFC(reg);
dout[1] = data;
spi_xfer(enc->slave, 2 * 8, dout, NULL,
SPI_XFER_BEGIN | SPI_XFER_END);
}
/*
* high byte of the register contains bank number:
* 0: no bank switch necessary
* 1: switch to bank 0
* 2: switch to bank 1
* 3: switch to bank 2
* 4: switch to bank 3
*/
static void enc_set_bank(enc_dev_t *enc, const u16 reg)
{
u8 newbank = reg >> 8;
if (newbank == 0 || newbank == enc->bank)
return;
switch (newbank) {
case 1:
enc_bclr(enc, CTL_REG_ECON1,
ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
break;
case 2:
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
break;
case 3:
enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_BSEL0);
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_BSEL1);
break;
case 4:
enc_bset(enc, CTL_REG_ECON1,
ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1);
break;
}
enc->bank = newbank;
}
/*
* local functions to access SPI
*
* reg: register inside ENC28J60
* data: 8/16 bits to write
* c: number of retries
*
* enc_r8: read 8 bits
* enc_r16: read 16 bits
* enc_w8: write 8 bits
* enc_w16: write 16 bits
* enc_w8_retry: write 8 bits, verify and retry
* enc_rbuf: read from ENC28J60 into buffer
* enc_wbuf: write from buffer into ENC28J60
*/
/*
* MAC and MII registers need a 3 byte SPI transfer to read,
* all other registers need a 2 byte SPI transfer.
*/
static int enc_reg2nbytes(const u16 reg)
{
/* check if MAC or MII register */
return ((reg >= CTL_REG_MACON1 && reg <= CTL_REG_MIRDH) ||
(reg >= CTL_REG_MAADR1 && reg <= CTL_REG_MAADR4) ||
(reg == CTL_REG_MISTAT)) ? 3 : 2;
}
/*
* Read a byte register
*/
static u8 enc_r8(enc_dev_t *enc, const u16 reg)
{
u8 dout[3];
u8 din[3];
int nbytes = enc_reg2nbytes(reg);
enc_set_bank(enc, reg);
dout[0] = CMD_RCR(reg);
spi_xfer(enc->slave, nbytes * 8, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END);
return din[nbytes-1];
}
/*
* Read a L/H register pair and return a word.
* Must be called with the L register's address.
*/
static u16 enc_r16(enc_dev_t *enc, const u16 reg)
{
u8 dout[3];
u8 din[3];
u16 result;
int nbytes = enc_reg2nbytes(reg);
enc_set_bank(enc, reg);
dout[0] = CMD_RCR(reg);
spi_xfer(enc->slave, nbytes * 8, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END);
result = din[nbytes-1];
dout[0]++; /* next register */
spi_xfer(enc->slave, nbytes * 8, dout, din,
SPI_XFER_BEGIN | SPI_XFER_END);
result |= din[nbytes-1] << 8;
return result;
}
/*
* Write a byte register
*/
static void enc_w8(enc_dev_t *enc, const u16 reg, const u8 data)
{
u8 dout[2];
enc_set_bank(enc, reg);
dout[0] = CMD_WCR(reg);
dout[1] = data;
spi_xfer(enc->slave, 2 * 8, dout, NULL,
SPI_XFER_BEGIN | SPI_XFER_END);
}
/*
* Write a L/H register pair.
* Must be called with the L register's address.
*/
static void enc_w16(enc_dev_t *enc, const u16 reg, const u16 data)
{
u8 dout[2];
enc_set_bank(enc, reg);
dout[0] = CMD_WCR(reg);
dout[1] = data;
spi_xfer(enc->slave, 2 * 8, dout, NULL,
SPI_XFER_BEGIN | SPI_XFER_END);
dout[0]++; /* next register */
dout[1] = data >> 8;
spi_xfer(enc->slave, 2 * 8, dout, NULL,
SPI_XFER_BEGIN | SPI_XFER_END);
}
/*
* Write a byte register, verify and retry
*/
static void enc_w8_retry(enc_dev_t *enc, const u16 reg, const u8 data, const int c)
{
u8 dout[2];
u8 readback;
int i;
enc_set_bank(enc, reg);
for (i = 0; i < c; i++) {
dout[0] = CMD_WCR(reg);
dout[1] = data;
spi_xfer(enc->slave, 2 * 8, dout, NULL,
SPI_XFER_BEGIN | SPI_XFER_END);
readback = enc_r8(enc, reg);
if (readback == data)
break;
/* wait 1ms */
udelay(1000);
}
if (i == c) {
printf("%s: write reg 0x%03x failed\n", enc->dev->name, reg);
}
}
/*
* Read ENC RAM into buffer
*/
static void enc_rbuf(enc_dev_t *enc, const u16 length, u8 *buf)
{
u8 dout[1];
dout[0] = CMD_RBM;
spi_xfer(enc->slave, 8, dout, NULL, SPI_XFER_BEGIN);
spi_xfer(enc->slave, length * 8, NULL, buf, SPI_XFER_END);
#ifdef DEBUG
puts("Rx:\n");
print_buffer(0, buf, 1, length, 0);
#endif
}
/*
* Write buffer into ENC RAM
*/
static void enc_wbuf(enc_dev_t *enc, const u16 length, const u8 *buf, const u8 control)
{
u8 dout[2];
dout[0] = CMD_WBM;
dout[1] = control;
spi_xfer(enc->slave, 2 * 8, dout, NULL, SPI_XFER_BEGIN);
spi_xfer(enc->slave, length * 8, buf, NULL, SPI_XFER_END);
#ifdef DEBUG
puts("Tx:\n");
print_buffer(0, buf, 1, length, 0);
#endif
}
/*
* Try to claim the SPI bus.
* Print error message on failure.
*/
static int enc_claim_bus(enc_dev_t *enc)
{
int rc = spi_claim_bus(enc->slave);
if (rc)
printf("%s: failed to claim SPI bus\n", enc->dev->name);
return rc;
}
/*
* Release previously claimed SPI bus.
* This function is mainly for symmetry to enc_claim_bus().
* Let the toolchain decide to inline it...
*/
static void enc_release_bus(enc_dev_t *enc)
{
spi_release_bus(enc->slave);
}
/*
* Read PHY register
*/
static u16 enc_phy_read(enc_dev_t *enc, const u8 addr)
{
uint64_t etime;
u8 status;
enc_w8(enc, CTL_REG_MIREGADR, addr);
enc_w8(enc, CTL_REG_MICMD, ENC_MICMD_MIIRD);
/* 1 second timeout - only happens on hardware problem */
etime = get_ticks() + get_tbclk();
/* poll MISTAT.BUSY bit until operation is complete */
do
{
status = enc_r8(enc, CTL_REG_MISTAT);
} while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
if (status & ENC_MISTAT_BUSY) {
printf("%s: timeout reading phy\n", enc->dev->name);
return 0;
}
enc_w8(enc, CTL_REG_MICMD, 0);
return enc_r16(enc, CTL_REG_MIRDL);
}
/*
* Write PHY register
*/
static void enc_phy_write(enc_dev_t *enc, const u8 addr, const u16 data)
{
uint64_t etime;
u8 status;
enc_w8(enc, CTL_REG_MIREGADR, addr);
enc_w16(enc, CTL_REG_MIWRL, data);
/* 1 second timeout - only happens on hardware problem */
etime = get_ticks() + get_tbclk();
/* poll MISTAT.BUSY bit until operation is complete */
do
{
status = enc_r8(enc, CTL_REG_MISTAT);
} while (get_ticks() <= etime && (status & ENC_MISTAT_BUSY));
if (status & ENC_MISTAT_BUSY) {
printf("%s: timeout writing phy\n", enc->dev->name);
return;
}
}
/*
* Verify link status, wait if necessary
*
* Note: with a 10 MBit/s only PHY there is no autonegotiation possible,
* half/full duplex is a pure setup matter. For the time being, this driver
* will setup in half duplex mode only.
*/
static int enc_phy_link_wait(enc_dev_t *enc)
{
u16 status;
int duplex;
uint64_t etime;
#ifdef CONFIG_ENC_SILENTLINK
/* check if we have a link, then just return */
status = enc_phy_read(enc, PHY_REG_PHSTAT1);
if (status & ENC_PHSTAT1_LLSTAT)
return 0;
#endif
/* wait for link with 1 second timeout */
etime = get_ticks() + get_tbclk();
while (get_ticks() <= etime) {
status = enc_phy_read(enc, PHY_REG_PHSTAT1);
if (status & ENC_PHSTAT1_LLSTAT) {
/* now we have a link */
status = enc_phy_read(enc, PHY_REG_PHSTAT2);
duplex = (status & ENC_PHSTAT2_DPXSTAT) ? 1 : 0;
printf("%s: link up, 10Mbps %s-duplex\n",
enc->dev->name, duplex ? "full" : "half");
return 0;
}
udelay(1000);
}
/* timeout occured */
printf("%s: link down\n", enc->dev->name);
return 1;
}
/*
* This function resets the receiver only.
*/
static void enc_reset_rx(enc_dev_t *enc)
{
u8 econ1;
econ1 = enc_r8(enc, CTL_REG_ECON1);
if ((econ1 & ENC_ECON1_RXRST) == 0) {
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
enc->rx_reset_counter = RX_RESET_COUNTER;
}
}
/*
* Reset receiver and reenable it.
*/
static void enc_reset_rx_call(enc_dev_t *enc)
{
enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXRST);
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
}
/*
* Copy a packet from the receive ring and forward it to
* the protocol stack.
*/
static void enc_receive(enc_dev_t *enc)
{
u8 *packet = (u8 *)NetRxPackets[0];
u16 pkt_len;
u16 copy_len;
u16 status;
u8 pkt_cnt = 0;
u16 rxbuf_rdpt;
u8 hbuf[6];
enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
do {
enc_rbuf(enc, 6, hbuf);
enc->next_pointer = hbuf[0] | (hbuf[1] << 8);
pkt_len = hbuf[2] | (hbuf[3] << 8);
status = hbuf[4] | (hbuf[5] << 8);
debug("next_pointer=$%04x pkt_len=%u status=$%04x\n",
enc->next_pointer, pkt_len, status);
if (pkt_len <= ENC_MAX_FRM_LEN)
copy_len = pkt_len;
else
copy_len = 0;
if ((status & (1L << 7)) == 0) /* check Received Ok bit */
copy_len = 0;
/* check if next pointer is resonable */
if (enc->next_pointer >= ENC_TX_BUF_START)
copy_len = 0;
if (copy_len > 0) {
enc_rbuf(enc, copy_len, packet);
}
/* advance read pointer to next pointer */
enc_w16(enc, CTL_REG_ERDPTL, enc->next_pointer);
/* decrease packet counter */
enc_bset(enc, CTL_REG_ECON2, ENC_ECON2_PKTDEC);
/*
* Only odd values should be written to ERXRDPTL,
* see errata B4 pt.13
*/
rxbuf_rdpt = enc->next_pointer - 1;
if ((rxbuf_rdpt < enc_r16(enc, CTL_REG_ERXSTL)) ||
(rxbuf_rdpt > enc_r16(enc, CTL_REG_ERXNDL))) {
enc_w16(enc, CTL_REG_ERXRDPTL,
enc_r16(enc, CTL_REG_ERXNDL));
} else {
enc_w16(enc, CTL_REG_ERXRDPTL, rxbuf_rdpt);
}
/* read pktcnt */
pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
if (copy_len == 0) {
(void)enc_r8(enc, CTL_REG_EIR);
enc_reset_rx(enc);
printf("%s: receive copy_len=0\n", enc->dev->name);
continue;
}
/*
* Because NetReceive() might call enc_send(), we need to
* release the SPI bus, call NetReceive(), reclaim the bus
*/
enc_release_bus(enc);
NetReceive(packet, pkt_len);
if (enc_claim_bus(enc))
return;
(void)enc_r8(enc, CTL_REG_EIR);
} while (pkt_cnt);
/* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
}
/*
* Poll for completely received packets.
*/
static void enc_poll(enc_dev_t *enc)
{
u8 eir_reg;
u8 pkt_cnt;
#ifdef CONFIG_USE_IRQ
/* clear global interrupt enable bit in enc28j60 */
enc_bclr(enc, CTL_REG_EIE, ENC_EIE_INTIE);
#endif
(void)enc_r8(enc, CTL_REG_ESTAT);
eir_reg = enc_r8(enc, CTL_REG_EIR);
if (eir_reg & ENC_EIR_TXIF) {
/* clear TXIF bit in EIR */
enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXIF);
}
/* We have to use pktcnt and not pktif bit, see errata pt. 6 */
pkt_cnt = enc_r8(enc, CTL_REG_EPKTCNT);
if (pkt_cnt > 0) {
if ((eir_reg & ENC_EIR_PKTIF) == 0) {
debug("enc_poll: pkt cnt > 0, but pktif not set\n");
}
enc_receive(enc);
/*
* clear PKTIF bit in EIR, this should not need to be done
* but it seems like we get problems if we do not
*/
enc_bclr(enc, CTL_REG_EIR, ENC_EIR_PKTIF);
}
if (eir_reg & ENC_EIR_RXERIF) {
printf("%s: rx error\n", enc->dev->name);
enc_bclr(enc, CTL_REG_EIR, ENC_EIR_RXERIF);
}
if (eir_reg & ENC_EIR_TXERIF) {
printf("%s: tx error\n", enc->dev->name);
enc_bclr(enc, CTL_REG_EIR, ENC_EIR_TXERIF);
}
#ifdef CONFIG_USE_IRQ
/* set global interrupt enable bit in enc28j60 */
enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
#endif
}
/*
* Completely Reset the ENC
*/
static void enc_reset(enc_dev_t *enc)
{
u8 dout[1];
dout[0] = CMD_SRC;
spi_xfer(enc->slave, 8, dout, NULL,
SPI_XFER_BEGIN | SPI_XFER_END);
/* sleep 1 ms. See errata pt. 2 */
udelay(1000);
}
/*
* Initialisation data for most of the ENC registers
*/
static const u16 enc_initdata[] = {
/*
* Setup the buffer space. The reset values are valid for the
* other pointers.
*
* We shall not write to ERXST, see errata pt. 5. Instead we
* have to make sure that ENC_RX_BUS_START is 0.
*/
CTL_REG_ERXSTL, ENC_RX_BUF_START,
CTL_REG_ERXSTH, ENC_RX_BUF_START >> 8,
CTL_REG_ERXNDL, ENC_RX_BUF_END,
CTL_REG_ERXNDH, ENC_RX_BUF_END >> 8,
CTL_REG_ERDPTL, ENC_RX_BUF_START,
CTL_REG_ERDPTH, ENC_RX_BUF_START >> 8,
/*
* Set the filter to receive only good-CRC, unicast and broadcast
* frames.
* Note: some DHCP servers return their answers as broadcasts!
* So its unwise to remove broadcast from this. This driver
* might incur receiver overruns with packet loss on a broadcast
* flooded network.
*/
CTL_REG_ERXFCON, ENC_RFR_BCEN | ENC_RFR_UCEN | ENC_RFR_CRCEN,
/* enable MAC to receive frames */
CTL_REG_MACON1,
ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS,
/* configure pad, tx-crc and duplex */
CTL_REG_MACON3,
ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN |
ENC_MACON3_FRMLNEN,
/* Allow infinite deferals if the medium is continously busy */
CTL_REG_MACON4, ENC_MACON4_DEFER,
/* Late collisions occur beyond 63 bytes */
CTL_REG_MACLCON2, 63,
/*
* Set (low byte) Non-Back-to_Back Inter-Packet Gap.
* Recommended 0x12
*/
CTL_REG_MAIPGL, 0x12,
/*
* Set (high byte) Non-Back-to_Back Inter-Packet Gap.
* Recommended 0x0c for half-duplex. Nothing for full-duplex
*/
CTL_REG_MAIPGH, 0x0C,
/* set maximum frame length */
CTL_REG_MAMXFLL, ENC_MAX_FRM_LEN,
CTL_REG_MAMXFLH, ENC_MAX_FRM_LEN >> 8,
/*
* Set MAC back-to-back inter-packet gap.
* Recommended 0x12 for half duplex
* and 0x15 for full duplex.
*/
CTL_REG_MABBIPG, 0x12,
/* end of table */
0xffff
};
/*
* Wait for the XTAL oscillator to become ready
*/
static int enc_clock_wait(enc_dev_t *enc)
{
uint64_t etime;
/* one second timeout */
etime = get_ticks() + get_tbclk();
/*
* Wait for CLKRDY to become set (i.e., check that we can
* communicate with the ENC)
*/
do
{
if (enc_r8(enc, CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY)
return 0;
} while (get_ticks() <= etime);
printf("%s: timeout waiting for CLKRDY\n", enc->dev->name);
return -1;
}
/*
* Write the MAC address into the ENC
*/
static int enc_write_macaddr(enc_dev_t *enc)
{
unsigned char *p = enc->dev->enetaddr;
enc_w8_retry(enc, CTL_REG_MAADR5, *p++, 5);
enc_w8_retry(enc, CTL_REG_MAADR4, *p++, 5);
enc_w8_retry(enc, CTL_REG_MAADR3, *p++, 5);
enc_w8_retry(enc, CTL_REG_MAADR2, *p++, 5);
enc_w8_retry(enc, CTL_REG_MAADR1, *p++, 5);
enc_w8_retry(enc, CTL_REG_MAADR0, *p, 5);
return 0;
}
/*
* Setup most of the ENC registers
*/
static int enc_setup(enc_dev_t *enc)
{
u16 phid1 = 0;
u16 phid2 = 0;
const u16 *tp;
/* reset enc struct values */
enc->next_pointer = ENC_RX_BUF_START;
enc->rx_reset_counter = RX_RESET_COUNTER;
enc->bank = 0xff; /* invalidate current bank in enc28j60 */
/* verify PHY identification */
phid1 = enc_phy_read(enc, PHY_REG_PHID1);
phid2 = enc_phy_read(enc, PHY_REG_PHID2) & ENC_PHID2_MASK;
if (phid1 != ENC_PHID1_VALUE || phid2 != ENC_PHID2_VALUE) {
printf("%s: failed to identify PHY. Found %04x:%04x\n",
enc->dev->name, phid1, phid2);
return -1;
}
/* now program registers */
for (tp = enc_initdata; *tp != 0xffff; tp += 2)
enc_w8_retry(enc, tp[0], tp[1], 10);
/*
* Prevent automatic loopback of data beeing transmitted by setting
* ENC_PHCON2_HDLDIS
*/
enc_phy_write(enc, PHY_REG_PHCON2, (1<<8));
/*
* LEDs configuration
* LEDA: LACFG = 0100 -> display link status
* LEDB: LBCFG = 0111 -> display TX & RX activity
* STRCH = 1 -> LED pulses
*/
enc_phy_write(enc, PHY_REG_PHLCON, 0x0472);
/* Reset PDPXMD-bit => half duplex */
enc_phy_write(enc, PHY_REG_PHCON1, 0);
#ifdef CONFIG_USE_IRQ
/* enable interrupts */
enc_bset(enc, CTL_REG_EIE, ENC_EIE_PKTIE);
enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXIE);
enc_bset(enc, CTL_REG_EIE, ENC_EIE_RXERIE);
enc_bset(enc, CTL_REG_EIE, ENC_EIE_TXERIE);
enc_bset(enc, CTL_REG_EIE, ENC_EIE_INTIE);
#endif
return 0;
}
/*
* Check if ENC has been initialized.
* If not, try to initialize it.
* Remember initialized state in struct.
*/
static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate)
{
if (enc->initstate >= requiredstate)
return 0;
if (enc->initstate < setupdone) {
/* Initialize the ENC only */
enc_reset(enc);
/* if any of functions fails, skip the rest and return an error */
if (enc_clock_wait(enc) || enc_setup(enc) || enc_write_macaddr(enc)) {
return -1;
}
enc->initstate = setupdone;
}
/* if that's all we need, return here */
if (enc->initstate >= requiredstate)
return 0;
/* now wait for link ready condition */
if (enc_phy_link_wait(enc)) {
return -1;
}
enc->initstate = linkready;
return 0;
}
#if defined(CONFIG_CMD_MII)
/*
* Read a PHY register.
*
* This function is registered with miiphy_register().
*/
int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
enc_dev_t *enc;
if (!dev || phy_adr != 0)
return -1;
enc = dev->priv;
if (enc_claim_bus(enc))
return -1;
if (enc_initcheck(enc, setupdone)) {
enc_release_bus(enc);
return -1;
}
*value = enc_phy_read(enc, reg);
enc_release_bus(enc);
return 0;
}
/*
* Write a PHY register.
*
* This function is registered with miiphy_register().
*/
int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
enc_dev_t *enc;
if (!dev || phy_adr != 0)
return -1;
enc = dev->priv;
if (enc_claim_bus(enc))
return -1;
if (enc_initcheck(enc, setupdone)) {
enc_release_bus(enc);
return -1;
}
enc_phy_write(enc, reg, value);
enc_release_bus(enc);
return 0;
}
#endif
/*
* Write hardware (MAC) address.
*
* This function entered into eth_device structure.
*/
static int enc_write_hwaddr(struct eth_device *dev)
{
enc_dev_t *enc = dev->priv;
if (enc_claim_bus(enc))
return -1;
if (enc_initcheck(enc, setupdone)) {
enc_release_bus(enc);
return -1;
}
enc_release_bus(enc);
return 0;
}
/*
* Initialize ENC28J60 for use.
*
* This function entered into eth_device structure.
*/
static int enc_init(struct eth_device *dev, bd_t *bis)
{
enc_dev_t *enc = dev->priv;
if (enc_claim_bus(enc))
return -1;
if (enc_initcheck(enc, linkready)) {
enc_release_bus(enc);
return -1;
}
/* enable receive */
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
enc_release_bus(enc);
return 0;
}
/*
* Check for received packets.
*
* This function entered into eth_device structure.
*/
static int enc_recv(struct eth_device *dev)
{
enc_dev_t *enc = dev->priv;
if (enc_claim_bus(enc))
return -1;
if (enc_initcheck(enc, linkready)) {
enc_release_bus(enc);
return -1;
}
/* Check for dead receiver */
if (enc->rx_reset_counter > 0)
enc->rx_reset_counter--;
else
enc_reset_rx_call(enc);
enc_poll(enc);
enc_release_bus(enc);
return 0;
}
/*
* Send a packet.
*
* This function entered into eth_device structure.
*
* Should we wait here until we have a Link? Or shall we leave that to
* protocol retries?
*/
static int enc_send(
struct eth_device *dev,
volatile void *packet,
int length)
{
enc_dev_t *enc = dev->priv;
if (enc_claim_bus(enc))
return -1;
if (enc_initcheck(enc, linkready)) {
enc_release_bus(enc);
return -1;
}
/* setup transmit pointers */
enc_w16(enc, CTL_REG_EWRPTL, ENC_TX_BUF_START);
enc_w16(enc, CTL_REG_ETXNDL, length + ENC_TX_BUF_START);
enc_w16(enc, CTL_REG_ETXSTL, ENC_TX_BUF_START);
/* write packet to ENC */
enc_wbuf(enc, length, (u8 *) packet, 0x00);
/*
* Check that the internal transmit logic has not been altered
* by excessive collisions. Reset transmitter if so.
* See Errata B4 12 and 14.
*/
if (enc_r8(enc, CTL_REG_EIR) & ENC_EIR_TXERIF) {
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_TXRST);
}
enc_bclr(enc, CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
/* start transmitting */
enc_bset(enc, CTL_REG_ECON1, ENC_ECON1_TXRTS);
enc_release_bus(enc);
return 0;
}
/*
* Finish use of ENC.
*
* This function entered into eth_device structure.
*/
static void enc_halt(struct eth_device *dev)
{
enc_dev_t *enc = dev->priv;
if (enc_claim_bus(enc))
return;
/* Just disable receiver */
enc_bclr(enc, CTL_REG_ECON1, ENC_ECON1_RXEN);
enc_release_bus(enc);
}
/*
* This is the only exported function.
*
* It may be called several times with different bus:cs combinations.
*/
int enc28j60_initialize(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct eth_device *dev;
enc_dev_t *enc;
/* try to allocate, check and clear eth_device object */
dev = malloc(sizeof(*dev));
if (!dev) {
return -1;
}
memset(dev, 0, sizeof(*dev));
/* try to allocate, check and clear enc_dev_t object */
enc = malloc(sizeof(*enc));
if (!enc) {
free(dev);
return -1;
}
memset(enc, 0, sizeof(*enc));
/* try to setup the SPI slave */
enc->slave = spi_setup_slave(bus, cs, max_hz, mode);
if (!enc->slave) {
printf("enc28j60: invalid SPI device %i:%i\n", bus, cs);
free(enc);
free(dev);
return -1;
}
enc->dev = dev;
/* now fill the eth_device object */
dev->priv = enc;
dev->init = enc_init;
dev->halt = enc_halt;
dev->send = enc_send;
dev->recv = enc_recv;
dev->write_hwaddr = enc_write_hwaddr;
sprintf(dev->name, "enc%i.%i", bus, cs);
eth_register(dev);
#if defined(CONFIG_CMD_MII)
miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write);
#endif
return 0;
}
|
1001-study-uboot
|
drivers/net/enc28j60.c
|
C
|
gpl3
| 23,766
|
/*
* Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <asm/fsl_serdes.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
*
* Initialize controller and call the common driver/pci pci_hose_scan to
* scan for bridges and devices.
*
* Hose fields which need to be pre-initialized by board specific code:
* regions[]
* first_busno
*
* Fields updated:
* last_busno
*/
#include <pci.h>
#include <asm/io.h>
#include <asm/fsl_pci.h>
/* Freescale-specific PCI config registers */
#define FSL_PCI_PBFR 0x44
#define FSL_PCIE_CAP_ID 0x4c
#define FSL_PCIE_CFG_RDY 0x4b0
#define FSL_PROG_IF_AGENT 0x1
void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus);
void pciauto_config_init(struct pci_controller *hose);
#ifndef CONFIG_SYS_PCI_MEMORY_BUS
#define CONFIG_SYS_PCI_MEMORY_BUS 0
#endif
#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
#define CONFIG_SYS_PCI_MEMORY_PHYS 0
#endif
#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
#endif
/* Setup one inbound ATMU window.
*
* We let the caller decide what the window size should be
*/
static void set_inbound_window(volatile pit_t *pi,
struct pci_region *r,
u64 size)
{
u32 sz = (__ilog2_u64(size) - 1);
u32 flag = PIWAR_EN | PIWAR_LOCAL |
PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
out_be32(&pi->pitar, r->phys_start >> 12);
out_be32(&pi->piwbar, r->bus_start >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
out_be32(&pi->piwbear, r->bus_start >> 44);
#else
out_be32(&pi->piwbear, 0);
#endif
if (r->flags & PCI_REGION_PREFETCH)
flag |= PIWAR_PF;
out_be32(&pi->piwar, flag | sz);
}
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
/* Reset hose to make sure its in a clean state */
memset(hose, 0, sizeof(struct pci_controller));
pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
return fsl_is_pci_agent(hose);
}
static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
u64 out_lo, u8 pcie_cap,
volatile pit_t *pi)
{
struct pci_region *r = hose->regions + hose->region_count;
u64 sz = min((u64)gd->ram_size, (1ull << 32));
phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
pci_size_t pci_sz;
/* we have no space available for inbound memory mapping */
if (bus_start > out_lo) {
printf ("no space for inbound mapping of memory\n");
return 0;
}
/* limit size */
if ((bus_start + sz) > out_lo) {
sz = out_lo - bus_start;
debug ("limiting size to %llx\n", sz);
}
pci_sz = 1ull << __ilog2_u64(sz);
/*
* we can overlap inbound/outbound windows on PCI-E since RX & TX
* links a separate
*/
if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)sz);
pci_set_region(r, bus_start, phys_start, sz,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
/* if we aren't an exact power of two match, pci_sz is smaller
* round it up to the next power of two. We report the actual
* size to pci region tracking.
*/
if (pci_sz != sz)
sz = 2ull << __ilog2_u64(sz);
set_inbound_window(pi--, r++, sz);
sz = 0; /* make sure we dont set the R2 window */
} else {
debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)pci_sz);
pci_set_region(r, bus_start, phys_start, pci_sz,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
set_inbound_window(pi--, r++, pci_sz);
sz -= pci_sz;
bus_start += pci_sz;
phys_start += pci_sz;
pci_sz = 1ull << __ilog2_u64(sz);
if (sz) {
debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)pci_sz);
pci_set_region(r, bus_start, phys_start, pci_sz,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
set_inbound_window(pi--, r++, pci_sz);
sz -= pci_sz;
bus_start += pci_sz;
phys_start += pci_sz;
}
}
#if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
/*
* On 64-bit capable systems, set up a mapping for all of DRAM
* in high pci address space.
*/
pci_sz = 1ull << __ilog2_u64(gd->ram_size);
/* round up to the next largest power of two */
if (gd->ram_size > pci_sz)
pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)CONFIG_SYS_PCI64_MEMORY_BUS,
(u64)CONFIG_SYS_PCI_MEMORY_PHYS,
(u64)pci_sz);
pci_set_region(r,
CONFIG_SYS_PCI64_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
pci_sz,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
set_inbound_window(pi--, r++, pci_sz);
#else
pci_sz = 1ull << __ilog2_u64(sz);
if (sz) {
debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
(u64)bus_start, (u64)phys_start, (u64)pci_sz);
pci_set_region(r, bus_start, phys_start, pci_sz,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
PCI_REGION_PREFETCH);
sz -= pci_sz;
bus_start += pci_sz;
phys_start += pci_sz;
set_inbound_window(pi--, r++, pci_sz);
}
#endif
#ifdef CONFIG_PHYS_64BIT
if (sz && (((u64)gd->ram_size) < (1ull << 32)))
printf("Was not able to map all of memory via "
"inbound windows -- %lld remaining\n", sz);
#endif
hose->region_count = r - hose->regions;
return 1;
}
void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
{
u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
u16 temp16;
u32 temp32;
u32 block_rev;
int enabled, r, inbound = 0;
u16 ltssm;
u8 temp8, pcie_cap;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
struct pci_region *reg = hose->regions + hose->region_count;
pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
/* Initialize ATMU registers based on hose regions and flags */
volatile pot_t *po = &pci->pot[1]; /* skip 0 */
volatile pit_t *pi;
u64 out_hi = 0, out_lo = -1ULL;
u32 pcicsrbar, pcicsrbar_sz;
pci_setup_indirect(hose, cfg_addr, cfg_data);
block_rev = in_be32(&pci->block_rev1);
if (PEX_IP_BLK_REV_2_2 <= block_rev) {
pi = &pci->pit[2]; /* 0xDC0 */
} else {
pi = &pci->pit[3]; /* 0xDE0 */
}
/* Handle setup of outbound windows first */
for (r = 0; r < hose->region_count; r++) {
unsigned long flags = hose->regions[r].flags;
u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
if (flags != PCI_REGION_SYS_MEMORY) {
u64 start = hose->regions[r].bus_start;
u64 end = start + hose->regions[r].size;
out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
out_be32(&po->potar, start >> 12);
#ifdef CONFIG_SYS_PCI_64BIT
out_be32(&po->potear, start >> 44);
#else
out_be32(&po->potear, 0);
#endif
if (hose->regions[r].flags & PCI_REGION_IO) {
out_be32(&po->powar, POWAR_EN | sz |
POWAR_IO_READ | POWAR_IO_WRITE);
} else {
out_be32(&po->powar, POWAR_EN | sz |
POWAR_MEM_READ | POWAR_MEM_WRITE);
out_lo = min(start, out_lo);
out_hi = max(end, out_hi);
}
po++;
}
}
debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
/* setup PCSRBAR/PEXCSRBAR */
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
pcicsrbar_sz = ~pcicsrbar_sz + 1;
if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
(out_lo > 0x100000000ull))
pcicsrbar = 0x100000000ull - pcicsrbar_sz;
else
pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
out_lo = min(out_lo, (u64)pcicsrbar);
debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
hose->region_count++;
/* see if we are a PCIe or PCI controller */
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
/* inbound */
inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
for (r = 0; r < hose->region_count; r++)
debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
(u64)hose->regions[r].phys_start,
(u64)hose->regions[r].bus_start,
(u64)hose->regions[r].size,
hose->regions[r].flags);
pci_register_hose(hose);
pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
hose->current_busno = hose->first_busno;
out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
* - Master abort (pci)
* - Master PERR (pci)
* - ICCA (PCIe)
*/
pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
temp32 = 0;
pci_hose_read_config_dword(hose, dev, PCI_LCR, &temp32);
temp32 &= ~0x03; /* Disable ASPM */
pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32);
udelay(1);
#endif
if (pcie_cap == PCI_CAP_ID_EXP) {
pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
enabled = ltssm >= PCI_LTSSM_L0;
#ifdef CONFIG_FSL_PCIE_RESET
if (ltssm == 1) {
int i;
debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
/* assert PCIe reset */
setbits_be32(&pci->pdb_stat, 0x08000000);
(void) in_be32(&pci->pdb_stat);
udelay(100);
debug(" Asserting PCIe reset @%p = %x\n",
&pci->pdb_stat, in_be32(&pci->pdb_stat));
/* clear PCIe reset */
clrbits_be32(&pci->pdb_stat, 0x08000000);
asm("sync;isync");
for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
pci_hose_read_config_word(hose, dev, PCI_LTSSM,
<ssm);
udelay(1000);
debug("....PCIe link error. "
"LTSSM=0x%02x.\n", ltssm);
}
enabled = ltssm >= PCI_LTSSM_L0;
/* we need to re-write the bar0 since a reset will
* clear it
*/
pci_hose_write_config_dword(hose, dev,
PCI_BASE_ADDRESS_0, pcicsrbar);
}
#endif
if (!enabled) {
/* Let the user know there's no PCIe link */
printf("no link, regs @ 0x%lx\n", pci_info->regs);
hose->last_busno = hose->first_busno;
return;
}
out_be32(&pci->pme_msg_det, 0xffffffff);
out_be32(&pci->pme_msg_int_en, 0xffffffff);
/* Print the negotiated PCIe link width */
pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4,
pci_info->regs);
hose->current_busno++; /* Start scan with secondary */
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
}
/* Use generic setup_device to initialize standard pci regs,
* but do not allocate any windows since any BAR found (such
* as PCSRBAR) is not in this cpu's memory space.
*/
pciauto_setup_device(hose, dev, 0, hose->pci_mem,
hose->pci_prefetch, hose->pci_io);
if (inbound) {
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
pci_hose_write_config_word(hose, dev, PCI_COMMAND,
temp16 | PCI_COMMAND_MEMORY);
}
#ifndef CONFIG_PCI_NOSCAN
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
/* Programming Interface (PCI_CLASS_PROG)
* 0 == pci host or pcie root-complex,
* 1 == pci agent or pcie end-point
*/
if (!temp8) {
debug(" Scanning PCI bus %02x\n",
hose->current_busno);
hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
} else {
debug(" Not scanning PCI bus %02x. PI=%x\n",
hose->current_busno, temp8);
hose->last_busno = hose->current_busno;
}
/* if we are PCIe - update limit regs and subordinate busno
* for the virtual P2P bridge
*/
if (pcie_cap == PCI_CAP_ID_EXP) {
pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
}
#else
hose->last_busno = hose->current_busno;
#endif
/* Clear all error indications */
if (pcie_cap == PCI_CAP_ID_EXP)
out_be32(&pci->pme_msg_det, 0xffffffff);
out_be32(&pci->pedr, 0xffffffff);
pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
if (temp16) {
pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
}
pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
if (temp16) {
pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
}
}
int fsl_is_pci_agent(struct pci_controller *hose)
{
u8 prog_if;
pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
return (prog_if == FSL_PROG_IF_AGENT);
}
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
struct pci_controller *hose, int busno)
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
pci_dev_t dev = PCI_BDF(busno,0,0);
u8 pcie_cap;
pci = (ccsr_fsl_pci_t *) pci_info->regs;
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/
if (in_be32(&pci->pme_msg_det)) {
out_be32(&pci->pme_msg_det, 0xffffffff);
debug (" with errors. Clearing. Now 0x%08x",
pci->pme_msg_det);
}
r = hose->regions + hose->region_count;
/* outbound memory */
pci_set_region(r++,
pci_info->mem_bus,
pci_info->mem_phys,
pci_info->mem_size,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
pci_info->io_bus,
pci_info->io_phys,
pci_info->io_size,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = busno;
fsl_pci_init(hose, pci_info);
if (fsl_is_pci_agent(hose)) {
fsl_pci_config_unlock(hose);
hose->last_busno = hose->first_busno;
}
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
"e" : "", pci_info->pci_num,
hose->first_busno, hose->last_busno);
return(hose->last_busno + 1);
}
/* Enable inbound PCI config cycles for agent/endpoint interface */
void fsl_pci_config_unlock(struct pci_controller *hose)
{
pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
u8 agent;
u8 pcie_cap;
u16 pbfr;
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
if (!agent)
return;
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
if (pcie_cap != 0x0) {
/* PCIe - set CFG_READY bit of Configuration Ready Register */
pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
} else {
/* PCI - clear ACL bit of PBFR */
pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
pbfr &= ~0x20;
pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
}
}
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
int fsl_configure_pcie(struct fsl_pci_info *info,
struct pci_controller *hose,
const char *connected, int busno)
{
int is_endpoint;
set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
is_endpoint = fsl_setup_hose(hose, info->regs);
printf("PCIe%u: %s", info->pci_num,
is_endpoint ? "Endpoint" : "Root Complex");
if (connected)
printf(" of %s", connected);
puts(", ");
return fsl_pci_init_port(info, hose, busno);
}
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
#define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
#define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
#define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC85xx)
#define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
#define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
#define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
#define _DEVDISR_PCIE4 0
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
#elif defined(CONFIG_MPC86xx)
#define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
#define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
#define _DEVDISR_PCIE3 0
#define _DEVDISR_PCIE4 0
#define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
(&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
#else
#error "No defines for DEVDISR_PCIE"
#endif
/* Implement a dummy function for those platforms w/o SERDES */
static const char *__board_serdes_name(enum srds_prtcl device)
{
switch (device) {
#ifdef CONFIG_SYS_PCIE1_NAME
case PCIE1:
return CONFIG_SYS_PCIE1_NAME;
#endif
#ifdef CONFIG_SYS_PCIE2_NAME
case PCIE2:
return CONFIG_SYS_PCIE2_NAME;
#endif
#ifdef CONFIG_SYS_PCIE3_NAME
case PCIE3:
return CONFIG_SYS_PCIE3_NAME;
#endif
#ifdef CONFIG_SYS_PCIE4_NAME
case PCIE4:
return CONFIG_SYS_PCIE4_NAME;
#endif
default:
return NULL;
}
return NULL;
}
__attribute__((weak, alias("__board_serdes_name"))) const char *
board_serdes_name(enum srds_prtcl device);
static u32 devdisr_mask[] = {
_DEVDISR_PCIE1,
_DEVDISR_PCIE2,
_DEVDISR_PCIE3,
_DEVDISR_PCIE4,
};
int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
struct fsl_pci_info *pci_info)
{
struct pci_controller *hose;
int num = dev - PCIE1;
hose = calloc(1, sizeof(struct pci_controller));
if (!hose)
return busno;
if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
busno = fsl_configure_pcie(pci_info, hose,
board_serdes_name(dev), busno);
} else {
printf("PCIe%d: disabled\n", num + 1);
}
return busno;
}
int fsl_pcie_init_board(int busno)
{
struct fsl_pci_info pci_info;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
u32 devdisr = in_be32(&gur->devdisr);
#ifdef CONFIG_PCIE1
SET_STD_PCIE_INFO(pci_info, 1);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
#else
setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
#endif
#ifdef CONFIG_PCIE2
SET_STD_PCIE_INFO(pci_info, 2);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
#else
setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE3
SET_STD_PCIE_INFO(pci_info, 3);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
#else
setbits_be32(&gur->devdisr, _DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE4
SET_STD_PCIE_INFO(pci_info, 4);
busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
#else
setbits_be32(&gur->devdisr, _DEVDISR_PCIE4); /* disable */
#endif
return busno;
}
#else
int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
struct fsl_pci_info *pci_info)
{
return busno;
}
int fsl_pcie_init_board(int busno)
{
return busno;
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>
void ft_fsl_pci_setup(void *blob, const char *pci_compat,
unsigned long ctrl_addr)
{
int off;
u32 bus_range[2];
phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
struct pci_controller *hose;
hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
/* convert ctrl_addr to true physical address */
p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
if (off < 0)
return;
/* We assume a cfg_addr not being set means we didn't setup the controller */
if ((hose == NULL) || (hose->cfg_addr == NULL)) {
fdt_del_node(blob, off);
} else {
bus_range[0] = 0;
bus_range[1] = hose->last_busno - hose->first_busno;
fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
fdt_pci_dma_ranges(blob, off, hose);
}
}
#endif
|
1001-study-uboot
|
drivers/pci/fsl_pci_init.c
|
C
|
gpl3
| 20,233
|
/*
* Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
*
* Copyright (C) 2011 Andes Technology Corporation
* Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/types.h> /* u32, u16.... used by pci.h */
#include "pci_ftpci100.h"
struct ftpci100_data {
unsigned int reg_base;
unsigned int io_base;
unsigned int mem_base;
unsigned int mmio_base;
unsigned int ndevs;
};
static struct pci_config devs[FTPCI100_MAX_FUNCTIONS];
static struct pci_controller local_hose;
static void setup_pci_bar(unsigned int bus, unsigned int dev, unsigned func,
unsigned char header, struct ftpci100_data *priv)
{
struct pci_controller *hose = (struct pci_controller *)&local_hose;
unsigned int i, tmp32, bar_no, iovsmem = 1;
pci_dev_t dev_nu;
/* A device is present, add an entry to the array */
devs[priv->ndevs].bus = bus;
devs[priv->ndevs].dev = dev;
devs[priv->ndevs].func = func;
dev_nu = PCI_BDF(bus, dev, func);
if ((header & 0x7f) == 0x01)
/* PCI-PCI Bridge */
bar_no = 2;
else
bar_no = 6;
/* Allocate address spaces by configuring BARs */
for (i = 0; i < bar_no; i++) {
pci_hose_write_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4, 0xffffffff);
pci_hose_read_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4, &tmp32);
if (tmp32 == 0x0)
continue;
/* IO space */
if (tmp32 & 0x1) {
iovsmem = 0;
unsigned int size_mask = ~(tmp32 & 0xfffffffc);
if (priv->io_base & size_mask)
priv->io_base = (priv->io_base & ~size_mask) + \
size_mask + 1;
devs[priv->ndevs].bar[i].addr = priv->io_base;
devs[priv->ndevs].bar[i].size = size_mask + 1;
pci_hose_write_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4,
priv->io_base);
debug("Allocated IO address 0x%X-" \
"0x%X for Bus %d, Device %d, Function %d\n",
priv->io_base,
priv->io_base + size_mask, bus, dev, func);
priv->io_base += size_mask + 1;
} else {
/* Memory space */
unsigned int is_64bit = ((tmp32 & 0x6) == 0x4);
unsigned int is_pref = tmp32 & 0x8;
unsigned int size_mask = ~(tmp32 & 0xfffffff0);
unsigned int alloc_base;
unsigned int *addr_mem_base;
if (is_pref)
addr_mem_base = &priv->mem_base;
else
addr_mem_base = &priv->mmio_base;
alloc_base = *addr_mem_base;
if (alloc_base & size_mask)
alloc_base = (alloc_base & ~size_mask) \
+ size_mask + 1;
pci_hose_write_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4, alloc_base);
debug("Allocated %s address 0x%X-" \
"0x%X for Bus %d, Device %d, Function %d\n",
is_pref ? "MEM" : "MMIO", alloc_base,
alloc_base + size_mask, bus, dev, func);
devs[priv->ndevs].bar[i].addr = alloc_base;
devs[priv->ndevs].bar[i].size = size_mask + 1;
debug("BAR address BAR size\n");
debug("%010x %08d\n",
devs[priv->ndevs].bar[0].addr,
devs[priv->ndevs].bar[0].size);
alloc_base += size_mask + 1;
*addr_mem_base = alloc_base;
if (is_64bit) {
i++;
pci_hose_write_config_dword(hose, dev_nu,
PCI_BASE_ADDRESS_0 + i * 4, 0x0);
}
}
}
/* Enable Bus Master, Memory Space, and IO Space */
pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
pci_hose_write_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, 0x08);
pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
pci_hose_read_config_dword(hose, dev_nu, PCI_COMMAND, &tmp32);
tmp32 &= 0xffff;
if (iovsmem == 0)
tmp32 |= 0x5;
else
tmp32 |= 0x6;
pci_hose_write_config_dword(hose, dev_nu, PCI_COMMAND, tmp32);
}
static void pci_bus_scan(struct ftpci100_data *priv)
{
struct pci_controller *hose = (struct pci_controller *)&local_hose;
unsigned int bus, dev, func;
pci_dev_t dev_nu;
unsigned int data32;
unsigned int tmp;
unsigned char header;
unsigned char int_pin;
unsigned int niobars;
unsigned int nmbars;
priv->ndevs = 1;
nmbars = 0;
niobars = 0;
for (bus = 0; bus < MAX_BUS_NUM; bus++)
for (dev = 0; dev < MAX_DEV_NUM; dev++)
for (func = 0; func < MAX_FUN_NUM; func++) {
dev_nu = PCI_BDF(bus, dev, func);
pci_hose_read_config_dword(hose, dev_nu,
PCI_VENDOR_ID, &data32);
/*
* some broken boards return 0 or ~0,
* if a slot is empty.
*/
if (data32 == 0xffffffff ||
data32 == 0x00000000 ||
data32 == 0x0000ffff ||
data32 == 0xffff0000)
continue;
pci_hose_read_config_dword(hose, dev_nu,
PCI_HEADER_TYPE, &tmp);
header = (unsigned char)tmp;
setup_pci_bar(bus, dev, func, header, priv);
devs[priv->ndevs].v_id = (u16)(data32 & \
0x0000ffff);
devs[priv->ndevs].d_id = (u16)((data32 & \
0xffff0000) >> 16);
/* Figure out what INTX# line the card uses */
pci_hose_read_config_byte(hose, dev_nu,
PCI_INTERRUPT_PIN, &int_pin);
/* assign the appropriate irq line */
if (int_pin > PCI_IRQ_LINES) {
printf("more irq lines than expect\n");
} else if (int_pin != 0) {
/* This device uses an interrupt line */
devs[priv->ndevs].pin = int_pin;
}
pci_hose_read_config_dword(hose, dev_nu,
PCI_CLASS_DEVICE, &data32);
debug("%06d %03d %03d " \
"%04d %08x %08x " \
"%03d %08x %06d %08x\n",
priv->ndevs, devs[priv->ndevs].bus,
devs[priv->ndevs].dev,
devs[priv->ndevs].func,
devs[priv->ndevs].d_id,
devs[priv->ndevs].v_id,
devs[priv->ndevs].pin,
devs[priv->ndevs].bar[0].addr,
devs[priv->ndevs].bar[0].size,
data32 >> 8);
priv->ndevs++;
}
}
static void ftpci_preinit(struct ftpci100_data *priv)
{
struct ftpci100_ahbc *ftpci100;
struct pci_controller *hose = (struct pci_controller *)&local_hose;
u32 pci_config_addr;
u32 pci_config_data;
priv->reg_base = CONFIG_FTPCI100_BASE;
priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE;
priv->mmio_base = CONFIG_FTPCI100_MEM_BASE;
priv->mem_base = CONFIG_FTPCI100_MEM_BASE + CONFIG_FTPCI100_MEM_SIZE;
ftpci100 = (struct ftpci100_ahbc *)priv->reg_base;
pci_config_addr = (u32) &ftpci100->conf;
pci_config_data = (u32) &ftpci100->data;
/* print device name */
printf("FTPCI100\n");
/* dump basic configuration */
debug("%s: Config addr is %08X, data port is %08X\n",
__func__, pci_config_addr, pci_config_data);
/* PCI memory space */
pci_set_region(hose->regions + 0,
CONFIG_PCI_MEM_BUS,
CONFIG_PCI_MEM_PHYS,
CONFIG_PCI_MEM_SIZE,
PCI_REGION_MEM);
hose->region_count++;
/* PCI IO space */
pci_set_region(hose->regions + 1,
CONFIG_PCI_IO_BUS,
CONFIG_PCI_IO_PHYS,
CONFIG_PCI_IO_SIZE,
PCI_REGION_IO);
hose->region_count++;
#if defined(CONFIG_PCI_SYS_BUS)
/* PCI System Memory space */
pci_set_region(hose->regions + 2,
CONFIG_PCI_SYS_BUS,
CONFIG_PCI_SYS_PHYS,
CONFIG_PCI_SYS_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count++;
#endif
/* setup indirect read/write function */
pci_setup_indirect(hose, pci_config_addr, pci_config_data);
/* register hose */
pci_register_hose(hose);
}
void pci_ftpci_init(void)
{
struct ftpci100_data *priv = NULL;
struct pci_controller *hose = (struct pci_controller *)&local_hose;
pci_dev_t bridge_num;
struct pci_device_id bridge_ids[] = {
{FTPCI100_BRIDGE_VENDORID, FTPCI100_BRIDGE_DEVICEID},
{0, 0}
};
priv = malloc(sizeof(struct ftpci100_data));
if (!priv) {
printf("%s(): failed to malloc priv\n", __func__);
return;
}
memset(priv, 0, sizeof(struct ftpci100_data));
ftpci_preinit(priv);
debug("Device bus dev func deviceID vendorID pin address" \
" size class\n");
pci_bus_scan(priv);
/*
* Setup the PCI Bridge Window to 1GB,
* it will cause USB OHCI Host controller Unrecoverable Error
* if it is not set.
*/
bridge_num = pci_find_devices(bridge_ids, 0);
if (bridge_num == -1) {
printf("PCI Bridge not found\n");
return;
}
pci_hose_write_config_dword(hose, bridge_num, PCI_MEM_BASE_SIZE1,
FTPCI100_BASE_ADR_SIZE(1024));
}
|
1001-study-uboot
|
drivers/pci/pci_ftpci100.c
|
C
|
gpl3
| 8,853
|
/*
* SH7780 PCI Controller (PCIC) for U-Boot.
* (C) Dustin McIntire (dustin@sensoria.com)
* (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/pci.h>
#include <asm/io.h>
#define SH7780_VENDOR_ID 0x1912
#define SH7780_DEVICE_ID 0x0002
#define SH7780_PCICR_PREFIX 0xA5000000
#define SH7780_PCICR_PFCS 0x00000800
#define SH7780_PCICR_FTO 0x00000400
#define SH7780_PCICR_PFE 0x00000200
#define SH7780_PCICR_TBS 0x00000100
#define SH7780_PCICR_ARBM 0x00000040
#define SH7780_PCICR_IOCS 0x00000004
#define SH7780_PCICR_PRST 0x00000002
#define SH7780_PCICR_CFIN 0x00000001
#define p4_in(addr) (*(vu_long *)addr)
#define p4_out(data, addr) (*(vu_long *)addr) = (data)
#define p4_inw(addr) (*(vu_short *)addr)
#define p4_outw(data, addr) (*(vu_short *)addr) = (data)
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 *value)
{
u32 par_data = 0x80000000 | dev;
p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
*value = p4_in(SH7780_PCIPDR);
return 0;
}
int pci_sh4_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
u32 par_data = 0x80000000 | dev;
p4_out(par_data | (offset & 0xfc), SH7780_PCIPAR);
p4_out(value, SH7780_PCIPDR);
return 0;
}
int pci_sh7780_init(struct pci_controller *hose)
{
p4_out(0x01, SH7780_PCIECR);
if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID
&& p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) {
printf("PCI: Unknown PCI host bridge.\n");
return -1;
}
printf("PCI: SH7780 PCI host bridge found.\n");
/* Toggle PCI reset pin */
p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR);
udelay(100000);
p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
p4_outw(0x0047, SH7780_PCICMD);
p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0);
p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0);
p4_out(0x00000000, SH7780_PCILSR1);
p4_out(0, SH7780_PCILAR1);
p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0);
p4_out(0x00000000, SH7780_PCIMBAR1);
p4_out(0xFD000000, SH7780_PCIMBR0);
p4_out(0x00FC0000, SH7780_PCIMBMR0);
/* if use Operand Cache then enable PCICSCR Soonp bits. */
p4_out(0x08000000, SH7780_PCICSAR0);
p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */
p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM
| SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE),
SH7780_PCICR);
pci_sh4_init(hose);
return 0;
}
|
1001-study-uboot
|
drivers/pci/pci_sh7780.c
|
C
|
gpl3
| 3,339
|
/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* (C) Copyright 2002, 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCI routines
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#define PCI_HOSE_OP(rw, size, type) \
int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, \
int offset, type value) \
{ \
return hose->rw##_##size(hose, dev, offset, value); \
}
PCI_HOSE_OP(read, byte, u8 *)
PCI_HOSE_OP(read, word, u16 *)
PCI_HOSE_OP(read, dword, u32 *)
PCI_HOSE_OP(write, byte, u8)
PCI_HOSE_OP(write, word, u16)
PCI_HOSE_OP(write, dword, u32)
#define PCI_OP(rw, size, type, error_code) \
int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
{ \
struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
\
if (!hose) \
{ \
error_code; \
return -1; \
} \
\
return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
}
PCI_OP(read, byte, u8 *, *value = 0xff)
PCI_OP(read, word, u16 *, *value = 0xffff)
PCI_OP(read, dword, u32 *, *value = 0xffffffff)
PCI_OP(write, byte, u8, )
PCI_OP(write, word, u16, )
PCI_OP(write, dword, u32, )
#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
pci_dev_t dev, \
int offset, type val) \
{ \
u32 val32; \
\
if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
*val = -1; \
return -1; \
} \
\
*val = (val32 >> ((offset & (int)off_mask) * 8)); \
\
return 0; \
}
#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
pci_dev_t dev, \
int offset, type val) \
{ \
u32 val32, mask, ldata, shift; \
\
if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
return -1; \
\
shift = ((offset & (int)off_mask) * 8); \
ldata = (((unsigned long)val) & val_mask) << shift; \
mask = val_mask << shift; \
val32 = (val32 & ~mask) | ldata; \
\
if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
return -1; \
\
return 0; \
}
PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
/* Get a virtual address associated with a BAR region */
void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
{
pci_addr_t pci_bus_addr;
u32 bar_response;
/* read BAR address */
pci_read_config_dword(pdev, bar, &bar_response);
pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
/*
* Pass "0" as the length argument to pci_bus_to_virt. The arg
* isn't actualy used on any platform because u-boot assumes a static
* linear mapping. In the future, this could read the BAR size
* and pass that as the size if needed.
*/
return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
}
/*
*
*/
static struct pci_controller* hose_head;
void pci_register_hose(struct pci_controller* hose)
{
struct pci_controller **phose = &hose_head;
while(*phose)
phose = &(*phose)->next;
hose->next = NULL;
*phose = hose;
}
struct pci_controller *pci_bus_to_hose (int bus)
{
struct pci_controller *hose;
for (hose = hose_head; hose; hose = hose->next)
if (bus >= hose->first_busno && bus <= hose->last_busno)
return hose;
printf("pci_bus_to_hose() failed\n");
return NULL;
}
struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
{
struct pci_controller *hose;
for (hose = hose_head; hose; hose = hose->next) {
if (hose->cfg_addr == cfg_addr)
return hose;
}
return NULL;
}
int pci_last_busno(void)
{
struct pci_controller *hose = hose_head;
if (!hose)
return -1;
while (hose->next)
hose = hose->next;
return hose->last_busno;
}
pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
{
struct pci_controller * hose;
u16 vendor, device;
u8 header_type;
pci_dev_t bdf;
int i, bus, found_multi = 0;
for (hose = hose_head; hose; hose = hose->next)
{
#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
#else
for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
#endif
for (bdf = PCI_BDF(bus,0,0);
#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
#else
bdf < PCI_BDF(bus+1,0,0);
#endif
bdf += PCI_BDF(0,0,1))
{
if (!PCI_FUNC(bdf)) {
pci_read_config_byte(bdf,
PCI_HEADER_TYPE,
&header_type);
found_multi = header_type & 0x80;
} else {
if (!found_multi)
continue;
}
pci_read_config_word(bdf,
PCI_VENDOR_ID,
&vendor);
pci_read_config_word(bdf,
PCI_DEVICE_ID,
&device);
for (i=0; ids[i].vendor != 0; i++)
if (vendor == ids[i].vendor &&
device == ids[i].device)
{
if (index <= 0)
return bdf;
index--;
}
}
}
return (-1);
}
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
{
static struct pci_device_id ids[2] = {{}, {0, 0}};
ids[0].vendor = vendor;
ids[0].device = device;
return pci_find_devices(ids, index);
}
/*
*
*/
int __pci_hose_phys_to_bus (struct pci_controller *hose,
phys_addr_t phys_addr,
unsigned long flags,
unsigned long skip_mask,
pci_addr_t *ba)
{
struct pci_region *res;
pci_addr_t bus_addr;
int i;
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
continue;
if (res->flags & skip_mask)
continue;
bus_addr = phys_addr - res->phys_start + res->bus_start;
if (bus_addr >= res->bus_start &&
bus_addr < res->bus_start + res->size) {
*ba = bus_addr;
return 0;
}
}
return 1;
}
pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
phys_addr_t phys_addr,
unsigned long flags)
{
pci_addr_t bus_addr = 0;
int ret;
if (!hose) {
puts ("pci_hose_phys_to_bus: invalid hose\n");
return bus_addr;
}
/* if PCI_REGION_MEM is set we do a two pass search with preference
* on matches that don't have PCI_REGION_SYS_MEMORY set */
if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
ret = __pci_hose_phys_to_bus(hose, phys_addr,
flags, PCI_REGION_SYS_MEMORY, &bus_addr);
if (!ret)
return bus_addr;
}
ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
if (ret)
puts ("pci_hose_phys_to_bus: invalid physical address\n");
return bus_addr;
}
int __pci_hose_bus_to_phys (struct pci_controller *hose,
pci_addr_t bus_addr,
unsigned long flags,
unsigned long skip_mask,
phys_addr_t *pa)
{
struct pci_region *res;
int i;
for (i = 0; i < hose->region_count; i++) {
res = &hose->regions[i];
if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
continue;
if (res->flags & skip_mask)
continue;
if (bus_addr >= res->bus_start &&
bus_addr < res->bus_start + res->size) {
*pa = (bus_addr - res->bus_start + res->phys_start);
return 0;
}
}
return 1;
}
phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
pci_addr_t bus_addr,
unsigned long flags)
{
phys_addr_t phys_addr = 0;
int ret;
if (!hose) {
puts ("pci_hose_bus_to_phys: invalid hose\n");
return phys_addr;
}
/* if PCI_REGION_MEM is set we do a two pass search with preference
* on matches that don't have PCI_REGION_SYS_MEMORY set */
if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
ret = __pci_hose_bus_to_phys(hose, bus_addr,
flags, PCI_REGION_SYS_MEMORY, &phys_addr);
if (!ret)
return phys_addr;
}
ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
if (ret)
puts ("pci_hose_bus_to_phys: invalid physical address\n");
return phys_addr;
}
/*
*
*/
int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
unsigned long io,
pci_addr_t mem,
unsigned long command)
{
unsigned int bar_response, old_command;
pci_addr_t bar_value;
pci_size_t bar_size;
unsigned char pin;
int bar, found_mem64;
debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
io, (u64)mem, command);
pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
pci_hose_read_config_dword (hose, dev, bar, &bar_response);
if (!bar_response)
continue;
found_mem64 = 0;
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
/* round up region base address to a multiple of size */
io = ((io - 1) | (bar_size - 1)) + 1;
bar_value = io;
/* compute new region base address */
io = io + bar_size;
} else {
if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) | bar_response;
bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
found_mem64 = 1;
} else {
bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
}
/* round up region base address to multiple of size */
mem = ((mem - 1) | (bar_size - 1)) + 1;
bar_value = mem;
/* compute new region base address */
mem = mem + bar_size;
}
/* Write it out and update our limit */
pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
if (found_mem64) {
bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
#else
pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
#endif
}
}
/* Configure Cache Line Size Register */
pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
/* Configure Latency Timer */
pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
/* Disable interrupt line, if device says it wants to use interrupts */
pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
if (pin != 0) {
pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
}
pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
(old_command & 0xffff0000) | command);
return 0;
}
/*
*
*/
struct pci_config_table *pci_find_config(struct pci_controller *hose,
unsigned short class,
unsigned int vendor,
unsigned int device,
unsigned int bus,
unsigned int dev,
unsigned int func)
{
struct pci_config_table *table;
for (table = hose->config_table; table && table->vendor; table++) {
if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
(table->device == PCI_ANY_ID || table->device == device) &&
(table->class == PCI_ANY_ID || table->class == class) &&
(table->bus == PCI_ANY_ID || table->bus == bus) &&
(table->dev == PCI_ANY_ID || table->dev == dev) &&
(table->func == PCI_ANY_ID || table->func == func)) {
return table;
}
}
return NULL;
}
void pci_cfgfunc_config_device(struct pci_controller *hose,
pci_dev_t dev,
struct pci_config_table *entry)
{
pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
}
void pci_cfgfunc_do_nothing(struct pci_controller *hose,
pci_dev_t dev, struct pci_config_table *entry)
{
}
/*
*
*/
/* HJF: Changed this to return int. I think this is required
* to get the correct result when scanning bridges
*/
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern void pciauto_config_init(struct pci_controller *hose);
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
const char * pci_class_str(u8 class)
{
switch (class) {
case PCI_CLASS_NOT_DEFINED:
return "Build before PCI Rev2.0";
break;
case PCI_BASE_CLASS_STORAGE:
return "Mass storage controller";
break;
case PCI_BASE_CLASS_NETWORK:
return "Network controller";
break;
case PCI_BASE_CLASS_DISPLAY:
return "Display controller";
break;
case PCI_BASE_CLASS_MULTIMEDIA:
return "Multimedia device";
break;
case PCI_BASE_CLASS_MEMORY:
return "Memory controller";
break;
case PCI_BASE_CLASS_BRIDGE:
return "Bridge device";
break;
case PCI_BASE_CLASS_COMMUNICATION:
return "Simple comm. controller";
break;
case PCI_BASE_CLASS_SYSTEM:
return "Base system peripheral";
break;
case PCI_BASE_CLASS_INPUT:
return "Input device";
break;
case PCI_BASE_CLASS_DOCKING:
return "Docking station";
break;
case PCI_BASE_CLASS_PROCESSOR:
return "Processor";
break;
case PCI_BASE_CLASS_SERIAL:
return "Serial bus controller";
break;
case PCI_BASE_CLASS_INTELLIGENT:
return "Intelligent controller";
break;
case PCI_BASE_CLASS_SATELLITE:
return "Satellite controller";
break;
case PCI_BASE_CLASS_CRYPT:
return "Cryptographic device";
break;
case PCI_BASE_CLASS_SIGNAL_PROCESSING:
return "DSP";
break;
case PCI_CLASS_OTHERS:
return "Does not fit any class";
break;
default:
return "???";
break;
};
}
#endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
/*
* Check if pci device should be skipped in configuration
*/
if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
/*
* Only skip configuration if "pciconfighost" is not set
*/
if (getenv("pciconfighost") == NULL)
return 1;
#else
return 1;
#endif
}
return 0;
}
int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
__attribute__((weak, alias("__pci_skip_dev")));
#ifdef CONFIG_PCI_SCAN_SHOW
int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
{
if (dev == PCI_BDF(hose->first_busno, 0, 0))
return 0;
return 1;
}
int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
__attribute__((weak, alias("__pci_print_dev")));
#endif /* CONFIG_PCI_SCAN_SHOW */
int pci_hose_scan_bus(struct pci_controller *hose, int bus)
{
unsigned int sub_bus, found_multi=0;
unsigned short vendor, device, class;
unsigned char header_type;
struct pci_config_table *cfg;
pci_dev_t dev;
#ifdef CONFIG_PCI_SCAN_SHOW
static int indent = 0;
#endif
sub_bus = bus;
for (dev = PCI_BDF(bus,0,0);
dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
dev += PCI_BDF(0,0,1)) {
if (pci_skip_dev(hose, dev))
continue;
if (PCI_FUNC(dev) && !found_multi)
continue;
pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
if (vendor == 0xffff || vendor == 0x0000)
continue;
if (!PCI_FUNC(dev))
found_multi = header_type & 0x80;
debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
#ifdef CONFIG_PCI_SCAN_SHOW
indent++;
/* Print leading space, including bus indentation */
printf("%*c", indent + 1, ' ');
if (pci_print_dev(hose, dev)) {
printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
vendor, device, pci_class_str(class >> 8));
}
#endif
cfg = pci_find_config(hose, class, vendor, device,
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
if (cfg) {
cfg->config_device(hose, dev, cfg);
sub_bus = max(sub_bus, hose->current_busno);
#ifdef CONFIG_PCI_PNP
} else {
int n = pciauto_config_device(hose, dev);
sub_bus = max(sub_bus, n);
#endif
}
#ifdef CONFIG_PCI_SCAN_SHOW
indent--;
#endif
if (hose->fixup_irq)
hose->fixup_irq(hose, dev);
}
return sub_bus;
}
int pci_hose_scan(struct pci_controller *hose)
{
#if defined(CONFIG_PCI_BOOTDELAY)
static int pcidelay_done;
char *s;
int i;
if (!pcidelay_done) {
/* wait "pcidelay" ms (if defined)... */
s = getenv("pcidelay");
if (s) {
int val = simple_strtoul(s, NULL, 10);
for (i = 0; i < val; i++)
udelay(1000);
}
pcidelay_done = 1;
}
#endif /* CONFIG_PCI_BOOTDELAY */
/* Start scan at current_busno.
* PCIe will start scan at first_busno+1.
*/
/* For legacy support, ensure current>=first */
if (hose->first_busno > hose->current_busno)
hose->current_busno = hose->first_busno;
#ifdef CONFIG_PCI_PNP
pciauto_config_init(hose);
#endif
return pci_hose_scan_bus(hose, hose->current_busno);
}
void pci_init(void)
{
hose_head = NULL;
/* now call board specific pci_init()... */
pci_init_board();
}
|
1001-study-uboot
|
drivers/pci/pci.c
|
C
|
gpl3
| 18,005
|
/*
* (C) Copyright 2004 Tundra Semiconductor Corp.
* Alex Bounine <alexandreb@tundra.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* PCI initialisation for the Tsi108 EMU board.
*/
#include <config.h>
#include <common.h>
#include <pci.h>
#include <asm/io.h>
#include <tsi108.h>
#if defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#include <fdt_support.h>
#endif
struct pci_controller local_hose;
void tsi108_clear_pci_error (void)
{
u32 err_stat, err_addr, pci_stat;
/*
* Quietly clear errors signalled as result of PCI/X configuration read
* requests.
*/
/* Read PB Error Log Registers */
err_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PB_REG_OFFSET + PB_ERRCS);
err_addr = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PB_REG_OFFSET + PB_AERR);
if (err_stat & PB_ERRCS_ES) {
/* Clear PCI/X bus errors if applicable */
if ((err_addr & 0xFF000000) == CONFIG_SYS_PCI_CFG_BASE) {
/* Clear error flag */
*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PB_REG_OFFSET + PB_ERRCS) =
PB_ERRCS_ES;
/* Clear read error reported in PB_ISR */
*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PB_REG_OFFSET + PB_ISR) =
PB_ISR_PBS_RD_ERR;
/* Clear errors reported by PCI CSR (Normally Master Abort) */
pci_stat = *(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET +
PCI_CSR);
*(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_CSR) =
pci_stat;
*(volatile u32 *)(CONFIG_SYS_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET +
PCI_IRP_STAT) = PCI_IRP_STAT_P_CSR;
}
}
return;
}
unsigned int __get_pci_config_dword (u32 addr)
{
unsigned int retval;
__asm__ __volatile__ (" lwbrx %0,0,%1\n"
"1: eieio\n"
"2:\n"
".section .fixup,\"ax\"\n"
"3: li %0,-1\n"
" b 2b\n"
".section __ex_table,\"a\"\n"
" .align 2\n"
" .long 1b,3b\n"
".section .text.__get_pci_config_dword"
: "=r"(retval) : "r"(addr));
return (retval);
}
static int tsi108_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
{
dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
*value = __get_pci_config_dword(dev);
if (0xFFFFFFFF == *value)
tsi108_clear_pci_error ();
return 0;
}
static int tsi108_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
dev &= (CONFIG_SYS_PCI_CFG_SIZE - 1);
dev |= (CONFIG_SYS_PCI_CFG_BASE | (offset & 0xfc));
out_le32 ((volatile unsigned *)dev, value);
return 0;
}
void pci_init_board (void)
{
struct pci_controller *hose = (struct pci_controller *)&local_hose;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region (hose->regions + 0,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region (hose->regions + 1,
CONFIG_SYS_PCI_MEM_BUS,
CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region (hose->regions + 2,
CONFIG_SYS_PCI_IO_BUS,
CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
hose->region_count = 3;
pci_set_ops (hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
tsi108_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
tsi108_write_config_dword);
pci_register_hose (hose);
hose->last_busno = pci_hose_scan (hose);
debug ("Done PCI initialization\n");
return;
}
#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{
int nodeoffset;
int tmp[2];
const char *path;
nodeoffset = fdt_path_offset(blob, "/aliases");
if (nodeoffset >= 0) {
path = fdt_getprop(blob, nodeoffset, "pci", NULL);
if (path) {
tmp[0] = cpu_to_be32(local_hose.first_busno);
tmp[1] = cpu_to_be32(local_hose.last_busno);
do_fixup_by_path(blob, path, "bus-range",
&tmp, sizeof(tmp), 1);
}
}
}
#endif /* CONFIG_OF_LIBFDT */
|
1001-study-uboot
|
drivers/pci/tsi108_pci.c
|
C
|
gpl3
| 5,008
|
/*
* Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
*
* Copyright (C) 2010 Andes Technology Corporation
* Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __FTPCI100_H
#define __FTPCI100_H
/* AHB Control Registers */
struct ftpci100_ahbc {
unsigned int iosize; /* 0x00 - I/O Space Size Signal */
unsigned int prot; /* 0x04 - AHB Protection */
unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
unsigned int conf; /* 0x28 - PCI Configuration */
unsigned int data; /* 0x2c - PCI Configuration DATA */
};
/*
* FTPCI100_IOSIZE_REG's constant definitions
*/
#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
/*
* PCI Configuration Register
*/
#define PCI_INT_MASK 0x4c
#define PCI_MEM_BASE_SIZE1 0x50
#define PCI_MEM_BASE_SIZE2 0x54
#define PCI_MEM_BASE_SIZE3 0x58
/*
* PCI_INT_MASK's bit definitions
*/
#define PCI_INTA_ENABLE (1 << 22)
#define PCI_INTB_ENABLE (1 << 23)
#define PCI_INTC_ENABLE (1 << 24)
#define PCI_INTD_ENABLE (1 << 25)
/*
* PCI_MEM_BASE_SIZE1's constant definitions
*/
#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */
#define FTPCI100_MAX_FUNCTIONS 20
#define PCI_IRQ_LINES 4
#define MAX_BUS_NUM 256
#define MAX_DEV_NUM 32
#define MAX_FUN_NUM 8
#define PCI_MAX_BAR_PER_FUNC 6
/*
* PCI_MEM_SIZE
*/
#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24)
/* This definition is used by pci_ftpci_init() */
#define FTPCI100_BRIDGE_VENDORID 0x159b
#define FTPCI100_BRIDGE_DEVICEID 0x4321
struct pcibar {
unsigned int size;
unsigned int addr;
};
struct pci_config {
unsigned int bus;
unsigned int dev; /* device */
unsigned int func;
unsigned int pin;
unsigned short v_id; /* vendor id */
unsigned short d_id; /* device id */
struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
};
#endif
|
1001-study-uboot
|
drivers/pci/pci_ftpci100.h
|
C
|
gpl3
| 2,627
|
/*
* arch/powerpc/kernel/pci_auto.c
*
* PCI autoconfiguration library
*
* Author: Matt Porter <mporter@mvista.com>
*
* Copyright 2000 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <common.h>
#include <pci.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define PCIAUTO_IDE_MODE_MASK 0x05
/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
#endif
/*
*
*/
void pciauto_region_init(struct pci_region* res)
{
/*
* Avoid allocating PCI resources from address 0 -- this is illegal
* according to PCI 2.1 and moreover, this is known to cause Linux IDE
* drivers to fail. Use a reasonable starting value of 0x1000 instead.
*/
res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
}
void pciauto_region_align(struct pci_region *res, pci_size_t size)
{
res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}
int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar)
{
pci_addr_t addr;
if (!res) {
DEBUGF("No resource");
goto error;
}
addr = ((res->bus_lower - 1) | (size - 1)) + 1;
if (addr - res->bus_start + size > res->size) {
DEBUGF("No room in resource");
goto error;
}
res->bus_lower = addr + size;
DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
*bar = addr;
return 0;
error:
*bar = (pci_addr_t)-1;
return -1;
}
/*
*
*/
void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
struct pci_region *prefetch,
struct pci_region *io)
{
unsigned int bar_response;
pci_addr_t bar_value;
pci_size_t bar_size;
unsigned int cmdstat = 0;
struct pci_region *bar_res;
int bar, bar_nr = 0;
int found_mem64 = 0;
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
/* Tickle the BAR and get the response */
pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
pci_hose_read_config_dword(hose, dev, bar, &bar_response);
/* If BAR is not implemented go to the next BAR */
if (!bar_response)
continue;
found_mem64 = 0;
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
& 0xffff) + 1;
bar_res = io;
DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
} else {
if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
bar64 = ((u64)bar_response_upper << 32) | bar_response;
bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
found_mem64 = 1;
} else {
bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
}
if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
bar_res = prefetch;
else
bar_res = mem;
DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
}
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
/* Write it out and update our limit */
pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
if (found_mem64) {
bar += 4;
#ifdef CONFIG_SYS_PCI_64BIT
pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
#else
/*
* If we are a 64-bit decoder then increment to the
* upper 32 bits of the bar and force it to locate
* in the lower 4GB of memory.
*/
pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
#endif
}
cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
}
DEBUGF("\n");
bar_nr++;
}
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
CONFIG_SYS_PCI_CACHE_LINE_SIZE);
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}
void pciauto_prescan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus)
{
struct pci_region *pci_mem = hose->pci_mem;
struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
unsigned int cmdstat;
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
PCI_BUS(dev) - hose->first_busno);
pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
sub_bus - hose->first_busno);
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
(pci_mem->bus_lower & 0xfff00000) >> 16);
cmdstat |= PCI_COMMAND_MEMORY;
}
if (pci_prefetch) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x100000);
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
(pci_prefetch->bus_lower & 0xfff00000) >> 16);
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
}
if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
(pci_io->bus_lower & 0x0000f000) >> 8);
pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
(pci_io->bus_lower & 0xffff0000) >> 16);
cmdstat |= PCI_COMMAND_IO;
}
/* Enable memory and I/O accesses, enable bus master */
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
}
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
pci_dev_t dev, int sub_bus)
{
struct pci_region *pci_mem = hose->pci_mem;
struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
sub_bus - hose->first_busno);
if (pci_mem) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
(pci_mem->bus_lower-1) >> 16);
}
if (pci_prefetch) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
(pci_prefetch->bus_lower-1) >> 16);
}
if (pci_io) {
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
((pci_io->bus_lower-1) & 0x0000f000) >> 8);
pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
((pci_io->bus_lower-1) & 0xffff0000) >> 16);
}
}
/*
*
*/
void pciauto_config_init(struct pci_controller *hose)
{
int i;
hose->pci_io = hose->pci_mem = NULL;
for (i=0; i<hose->region_count; i++) {
switch(hose->regions[i].flags) {
case PCI_REGION_IO:
if (!hose->pci_io ||
hose->pci_io->size < hose->regions[i].size)
hose->pci_io = hose->regions + i;
break;
case PCI_REGION_MEM:
if (!hose->pci_mem ||
hose->pci_mem->size < hose->regions[i].size)
hose->pci_mem = hose->regions + i;
break;
case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
if (!hose->pci_prefetch ||
hose->pci_prefetch->size < hose->regions[i].size)
hose->pci_prefetch = hose->regions + i;
break;
}
}
if (hose->pci_mem) {
pciauto_region_init(hose->pci_mem);
DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
"\t\tPhysical Memory [%llx-%llxx]\n",
(u64)hose->pci_mem->bus_start,
(u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
(u64)hose->pci_mem->phys_start,
(u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
}
if (hose->pci_prefetch) {
pciauto_region_init(hose->pci_prefetch);
DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
"\t\tPhysical Memory [%llx-%llx]\n",
(u64)hose->pci_prefetch->bus_start,
(u64)(hose->pci_prefetch->bus_start +
hose->pci_prefetch->size - 1),
(u64)hose->pci_prefetch->phys_start,
(u64)(hose->pci_prefetch->phys_start +
hose->pci_prefetch->size - 1));
}
if (hose->pci_io) {
pciauto_region_init(hose->pci_io);
DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
"\t\tPhysical Memory: [%llx-%llx]\n",
(u64)hose->pci_io->bus_start,
(u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
(u64)hose->pci_io->phys_start,
(u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
}
}
/* HJF: Changed this to return int. I think this is required
* to get the correct result when scanning bridges
*/
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
{
unsigned int sub_bus = PCI_BUS(dev);
unsigned short class;
unsigned char prg_iface;
int n;
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
switch(class) {
case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
DEBUGF("PCI AutoConfig: Found PowerPC device\n");
pciauto_setup_device(hose, dev, 6, hose->pci_mem,
hose->pci_prefetch, hose->pci_io);
break;
case PCI_CLASS_BRIDGE_PCI:
hose->current_busno++;
pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
/* Passing in current_busno allows for sibling P2P bridges */
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
/*
* need to figure out if this is a subordinate bridge on the bus
* to be able to properly set the pri/sec/sub bridge registers.
*/
n = pci_hose_scan_bus(hose, hose->current_busno);
/* figure out the deepest we've gone for this leg */
sub_bus = max(n, sub_bus);
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
sub_bus = hose->current_busno;
break;
case PCI_CLASS_STORAGE_IDE:
pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
return sub_bus;
}
pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
break;
case PCI_CLASS_BRIDGE_CARDBUS:
/* just do a minimal setup of the bridge, let the OS take care of the rest */
pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
hose->current_busno++;
break;
#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
case PCI_CLASS_BRIDGE_OTHER:
DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
PCI_DEV(dev));
break;
#endif
#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
* device claiming resources io/mem/irq.. we only allow for
* the PIMMR window to be allocated (BAR0 - 1MB size)
*/
DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
break;
#endif
default:
pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
break;
}
return sub_bus;
}
|
1001-study-uboot
|
drivers/pci/pci_auto.c
|
C
|
gpl3
| 12,303
|
/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Initialisation of the PCI-to-ISA bridge and disabling the BIOS
* write protection (for flash) in function 0 of the chip.
* Enabling function 1 (IDE controller of the chip.
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <pci.h>
#include <w83c553f.h>
#define out8(addr,val) do { \
out_8((u8*) (addr),(val)); udelay(1); \
} while (0)
#define out16(addr,val) do { \
out_be16((u16*) (addr),(val)); udelay(1); \
} while (0)
extern uint ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
void initialise_pic(void);
void initialise_dma(void);
void initialise_w83c553f(void)
{
pci_dev_t devbusfn;
unsigned char reg8;
unsigned short reg16;
unsigned int reg32;
devbusfn = pci_find_device(W83C553F_VID, W83C553F_DID, 0);
if (devbusfn == -1)
{
printf("Error: Cannot find W83C553F controller on any PCI bus.");
return;
}
pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
pci_read_config_byte(devbusfn, WINBOND_IPADCR, ®8);
/* 16 MB ISA memory space */
reg8 |= (IPADCR_IPATOM4 | IPADCR_IPATOM5 | IPADCR_IPATOM6 | IPADCR_IPATOM7);
reg8 &= ~IPADCR_MBE512;
pci_write_config_byte(devbusfn, WINBOND_IPADCR, reg8);
pci_read_config_byte(devbusfn, WINBOND_CSCR, ®8);
/* switch off BIOS write protection */
reg8 |= CSCR_UBIOSCSE;
reg8 &= ~CSCR_BIOSWP;
pci_write_config_byte(devbusfn, WINBOND_CSCR, reg8);
/*
* Interrupt routing:
* - IDE -> IRQ 9/0
* - INTA -> IRQ 10
* - INTB -> IRQ 11
* - INTC -> IRQ 14
* - INTD -> IRQ 15
*/
pci_write_config_byte(devbusfn, WINBOND_IDEIRCR, 0x90);
pci_write_config_word(devbusfn, WINBOND_PCIIRCR, 0xABEF);
/*
* Read IDE bus offsets from function 1 device.
* We must unmask the LSB indicating that ist is an IO address.
*/
devbusfn |= PCI_BDF(0,0,1);
/*
* Switch off legacy IRQ for IDE and IDE port 1.
*/
pci_write_config_byte(devbusfn, 0x09, 0x8F);
pci_read_config_dword(devbusfn, WINDOND_IDECSR, ®32);
reg32 &= ~(IDECSR_LEGIRQ | IDECSR_P1EN | IDECSR_P1F16);
pci_write_config_dword(devbusfn, WINDOND_IDECSR, reg32);
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &ide_bus_offset[0]);
ide_bus_offset[0] &= ~1;
#if CONFIG_SYS_IDE_MAXBUS > 1
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_2, &ide_bus_offset[1]);
ide_bus_offset[1] &= ~1;
#endif
/*
* Enable function 1, IDE -> busmastering and IO space access
*/
pci_read_config_word(devbusfn, PCI_COMMAND, ®16);
reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
pci_write_config_word(devbusfn, PCI_COMMAND, reg16);
/*
* Initialise ISA interrupt controller
*/
initialise_pic();
/*
* Initialise DMA controller
*/
initialise_dma();
}
void initialise_pic(void)
{
out8(W83C553F_PIC1_ICW1, 0x11);
out8(W83C553F_PIC1_ICW2, 0x08);
out8(W83C553F_PIC1_ICW3, 0x04);
out8(W83C553F_PIC1_ICW4, 0x01);
out8(W83C553F_PIC1_OCW1, 0xfb);
out8(W83C553F_PIC1_ELC, 0x20);
out8(W83C553F_PIC2_ICW1, 0x11);
out8(W83C553F_PIC2_ICW2, 0x08);
out8(W83C553F_PIC2_ICW3, 0x02);
out8(W83C553F_PIC2_ICW4, 0x01);
out8(W83C553F_PIC2_OCW1, 0xff);
out8(W83C553F_PIC2_ELC, 0xce);
out8(W83C553F_TMR1_CMOD, 0x74);
out8(W83C553F_PIC2_OCW1, 0x20);
out8(W83C553F_PIC1_OCW1, 0x20);
out8(W83C553F_PIC2_OCW1, 0x2b);
out8(W83C553F_PIC1_OCW1, 0x2b);
}
void initialise_dma(void)
{
unsigned int channel;
unsigned int rvalue1, rvalue2;
/* perform a H/W reset of the devices */
out8(W83C553F_DMA1 + W83C553F_DMA1_MC, 0x00);
out16(W83C553F_DMA2 + W83C553F_DMA2_MC, 0x0000);
/* initialise all channels to a sane state */
for (channel = 0; channel < 4; channel++) {
/*
* dependent upon the channel, setup the specifics:
*
* demand
* address-increment
* autoinitialize-disable
* verify-transfer
*/
switch (channel) {
case 0:
rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH0SEL|W83C553F_MODE_TT_VERIFY);
rvalue2 = (W83C553F_MODE_TM_CASCADE|W83C553F_MODE_CH0SEL);
break;
case 1:
rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH1SEL|W83C553F_MODE_TT_VERIFY);
break;
case 2:
rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH2SEL|W83C553F_MODE_TT_VERIFY);
break;
case 3:
rvalue1 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
rvalue2 = (W83C553F_MODE_TM_DEMAND|W83C553F_MODE_CH3SEL|W83C553F_MODE_TT_VERIFY);
break;
default:
rvalue1 = 0x00;
rvalue2 = 0x00;
break;
}
/* write to write mode registers */
out8(W83C553F_DMA1 + W83C553F_DMA1_WM, rvalue1 & 0xFF);
out16(W83C553F_DMA2 + W83C553F_DMA2_WM, rvalue2 & 0x00FF);
}
/* enable all channels */
out8(W83C553F_DMA1 + W83C553F_DMA1_CM, 0x00);
out16(W83C553F_DMA2 + W83C553F_DMA2_CM, 0x0000);
/*
* initialize the global DMA configuration
*
* DACK# active low
* DREQ active high
* fixed priority
* channel group enable
*/
out8(W83C553F_DMA1 + W83C553F_DMA1_CS, 0x00);
out16(W83C553F_DMA2 + W83C553F_DMA2_CS, 0x0000);
}
|
1001-study-uboot
|
drivers/pci/w83c553f.c
|
C
|
gpl3
| 6,100
|
#
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libpci.o
COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
COBJS-$(CONFIG_PCI) += pci.o pci_auto.o pci_indirect.o
COBJS-$(CONFIG_FTPCI100) += pci_ftpci100.o
COBJS-$(CONFIG_IXP_PCI) += pci_ixp.o
COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
COBJS-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
COBJS-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
COBJS-$(CONFIG_TSI108_PCI) += tsi108_pci.o
COBJS-$(CONFIG_WINBOND_83C553) += w83c553f.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
drivers/pci/Makefile
|
Makefile
|
gpl3
| 1,701
|
/*
* SH7751 PCI Controller (PCIC) for U-Boot.
* (C) Dustin McIntire (dustin@sensoria.com)
* (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/pci.h>
/* Register addresses and such */
#define SH7751_BCR1 (vu_long *)0xFF800000
#define SH7751_BCR2 (vu_short *)0xFF800004
#define SH7751_WCR1 (vu_long *)0xFF800008
#define SH7751_WCR2 (vu_long *)0xFF80000C
#define SH7751_WCR3 (vu_long *)0xFF800010
#define SH7751_MCR (vu_long *)0xFF800014
#define SH7751_BCR3 (vu_short *)0xFF800050
#define SH7751_PCICONF0 (vu_long *)0xFE200000
#define SH7751_PCICONF1 (vu_long *)0xFE200004
#define SH7751_PCICONF2 (vu_long *)0xFE200008
#define SH7751_PCICONF3 (vu_long *)0xFE20000C
#define SH7751_PCICONF4 (vu_long *)0xFE200010
#define SH7751_PCICONF5 (vu_long *)0xFE200014
#define SH7751_PCICONF6 (vu_long *)0xFE200018
#define SH7751_PCICR (vu_long *)0xFE200100
#define SH7751_PCILSR0 (vu_long *)0xFE200104
#define SH7751_PCILSR1 (vu_long *)0xFE200108
#define SH7751_PCILAR0 (vu_long *)0xFE20010C
#define SH7751_PCILAR1 (vu_long *)0xFE200110
#define SH7751_PCIMBR (vu_long *)0xFE2001C4
#define SH7751_PCIIOBR (vu_long *)0xFE2001C8
#define SH7751_PCIPINT (vu_long *)0xFE2001CC
#define SH7751_PCIPINTM (vu_long *)0xFE2001D0
#define SH7751_PCICLKR (vu_long *)0xFE2001D4
#define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
#define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
#define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
#define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
#define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
#define SH7751_PCIMCR (vu_long *)0xFE2001F4
#define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
#define BCR1_BREQEN 0x00080000
#define PCI_SH7751_ID 0x35051054
#define PCI_SH7751R_ID 0x350E1054
#define SH7751_PCICONF1_WCC 0x00000080
#define SH7751_PCICONF1_PER 0x00000040
#define SH7751_PCICONF1_BUM 0x00000004
#define SH7751_PCICONF1_MES 0x00000002
#define SH7751_PCICONF1_CMDS 0x000000C6
#define SH7751_PCI_HOST_BRIDGE 0x6
#define SH7751_PCICR_PREFIX 0xa5000000
#define SH7751_PCICR_PRST 0x00000002
#define SH7751_PCICR_CFIN 0x00000001
#define SH7751_PCIPINT_D3 0x00000002
#define SH7751_PCIPINT_D0 0x00000001
#define SH7751_PCICLKR_PREFIX 0xa5000000
#define SH7751_PCI_MEM_BASE 0xFD000000
#define SH7751_PCI_MEM_SIZE 0x01000000
#define SH7751_PCI_IO_BASE 0xFE240000
#define SH7751_PCI_IO_SIZE 0x00040000
#define SH7751_CS3_BASE_ADDR 0x0C000000
#define SH7751_P2CS3_BASE_ADDR 0xAC000000
#define SH7751_PCIPAR (vu_long *)0xFE2001C0
#define SH7751_PCIPDR (vu_long *)0xFE200220
#define p4_in(addr) (*addr)
#define p4_out(data, addr) (*addr) = (data)
/* Double word */
int pci_sh4_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 *value)
{
u32 par_data = 0x80000000 | dev;
p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
*value = p4_in(SH7751_PCIPDR);
return 0;
}
int pci_sh4_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
u32 par_data = 0x80000000 | dev;
p4_out(par_data | (offset & 0xfc), SH7751_PCIPAR);
p4_out(value, SH7751_PCIPDR);
return 0;
}
int pci_sh7751_init(struct pci_controller *hose)
{
/* Double-check that we're a 7751 or 7751R chip */
if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
&& p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
printf("PCI: Unknown PCI host bridge.\n");
return 1;
}
printf("PCI: SH7751 PCI host bridge found.\n");
/* Double-check some BSC config settings */
/* (Area 3 non-MPX 32-bit, PCI bus pins) */
if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
printf("SH7751_BCR1 value is wrong(0x%08X)\n",
(unsigned int)p4_in(SH7751_BCR1));
return 2;
}
if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
printf("SH7751_BCR2 value is wrong(0x%08X)\n",
(unsigned int)p4_in(SH7751_BCR2));
return 3;
}
if (p4_in(SH7751_BCR2) & 0x01) {
printf("SH7751_BCR2 value is wrong(0x%08X)\n",
(unsigned int)p4_in(SH7751_BCR2));
return 4;
}
/* Force BREQEN in BCR1 to allow PCIC access */
p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
/* Toggle PCI reset pin */
p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
udelay(32);
p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
/* Set cmd bits: WCC, PER, BUM, MES */
/* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
/* Define this host as the host bridge */
p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
/* Force PCI clock(s) on */
p4_out(0, SH7751_PCICLKR);
p4_out(0x03, SH7751_PCICLKR);
/* Clear powerdown IRQs, also mask them (unused) */
p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
p4_out(0, SH7751_PCIPINTM);
p4_out(0xab000001, SH7751_PCICONF4);
/* Set up target memory mappings (for external DMA access) */
/* Map both P0 and P2 range to Area 3 RAM for ease of use */
p4_out((64 - 1) << 20, SH7751_PCILSR0);
p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCILAR0);
p4_out(0, SH7751_PCILSR1);
p4_out(0, SH7751_PCILAR1);
p4_out(SH7751_CS3_BASE_ADDR, SH7751_PCICONF5);
p4_out(0xd0000000, SH7751_PCICONF6);
/* Map memory window to same address on PCI bus */
p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
/* Map IO window to same address on PCI bus */
p4_out(0x2000 & 0xfffc0000, SH7751_PCIIOBR);
/* set BREQEN */
p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
/* Copy BSC registers into PCI BSC */
p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
/* Finally, set central function init complete */
p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
pci_sh4_init(hose);
return 0;
}
|
1001-study-uboot
|
drivers/pci/pci_sh7751.c
|
C
|
gpl3
| 6,733
|
/*
* IXP PCI Init
*
* (C) Copyright 2011
* Michael Schwingen, michael@schwingen.org
* (C) Copyright 2004 eslab.whut.edu.cn
* Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <asm/arch/ixp425.h>
#include <asm/arch/ixp425pci.h>
DECLARE_GLOBAL_DATA_PTR;
static void non_prefetch_read(unsigned int addr, unsigned int cmd,
unsigned int *data);
static void non_prefetch_write(unsigned int addr, unsigned int cmd,
unsigned int data);
/*define the sub vendor and subsystem to be used */
#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
#define PCI_MEMORY_BUS 0x00000000
#define PCI_MEMORY_PHY 0x00000000
#define PCI_MEMORY_SIZE 0x04000000
#define PCI_MEM_BUS 0x48000000
#define PCI_MEM_PHY 0x00000000
#define PCI_MEM_SIZE 0x04000000
#define PCI_IO_BUS 0x00000000
#define PCI_IO_PHY 0x00000000
#define PCI_IO_SIZE 0x00010000
/* build address value for config sycle */
static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg)
{
unsigned int bus = PCI_BUS(bdf);
unsigned int dev = PCI_DEV(bdf);
unsigned int func = PCI_FUNC(bdf);
unsigned int addr;
if (bus) { /* secondary bus, use type 1 config cycle */
addr = bdf | (reg & ~3) | 1;
} else {
/*
primary bus, type 0 config cycle. address bits 31:28
specify the device 10:8 specify the function
*/
addr = BIT((31 - dev)) | (func << 8) | (reg & ~3);
}
return addr;
}
static int pci_config_status(void)
{
unsigned int regval;
regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET);
if ((regval & PCI_ISR_PFE) == 0)
return OK;
/* no device present, make sure that the master abort bit is reset */
writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET);
return ERROR;
}
static int pci_ixp_hose_read_config_dword(struct pci_controller *hose,
pci_dev_t bdf, int where, unsigned int *val)
{
unsigned int retval;
unsigned int addr;
int stat;
debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where);
/*Set the address to be read */
addr = pci_config_addr(bdf, where);
non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval);
*val = retval;
stat = pci_config_status();
if (stat < 0)
*val = -1;
debug("-> val %x, status %x\n", *val, stat);
return stat;
}
static int pci_ixp_hose_read_config_word(struct pci_controller *hose,
pci_dev_t bdf, int where, unsigned short *val)
{
unsigned int n;
unsigned int retval;
unsigned int addr;
unsigned int byteEnables;
int stat;
debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where);
n = where % 4;
/*byte enables are 4 bits active low, the position of each
bit maps to the byte that it enables */
byteEnables =
(~(BIT(n) | BIT((n + 1)))) &
IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
byteEnables = byteEnables << PCI_NP_CBE_BESL;
/*Set the address to be read */
addr = pci_config_addr(bdf, where);
non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
/*Pick out the word we are interested in */
*val = retval >> (8 * n);
stat = pci_config_status();
if (stat < 0)
*val = -1;
debug("-> val %x, status %x\n", *val, stat);
return stat;
}
static int pci_ixp_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t bdf, int where, unsigned char *val)
{
unsigned int retval;
unsigned int n;
unsigned int byteEnables;
unsigned int addr;
int stat;
debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where);
n = where % 4;
/*byte enables are 4 bits, active low, the position of each
bit maps to the byte that it enables */
byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
byteEnables = byteEnables << PCI_NP_CBE_BESL;
/*Set the address to be read */
addr = pci_config_addr(bdf, where);
non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
/*Pick out the byte we are interested in */
*val = retval >> (8 * n);
stat = pci_config_status();
if (stat < 0)
*val = -1;
debug("-> val %x, status %x\n", *val, stat);
return stat;
}
static int pci_ixp_hose_write_config_byte(struct pci_controller *hose,
pci_dev_t bdf, int where, unsigned char val)
{
unsigned int addr;
unsigned int byteEnables;
unsigned int n;
unsigned int ldata;
int stat;
debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x",
bdf, where, val);
n = where % 4;
/*byte enables are 4 bits active low, the position of each
bit maps to the byte that it enables */
byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
byteEnables = byteEnables << PCI_NP_CBE_BESL;
ldata = val << (8 * n);
/*Set the address to be written */
addr = pci_config_addr(bdf, where);
non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
stat = pci_config_status();
debug("-> status %x\n", stat);
return stat;
}
static int pci_ixp_hose_write_config_word(struct pci_controller *hose,
pci_dev_t bdf, int where, unsigned short val)
{
unsigned int addr;
unsigned int byteEnables;
unsigned int n;
unsigned int ldata;
int stat;
debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x",
bdf, where, val);
n = where % 4;
/*byte enables are 4 bits active low, the position of each
bit maps to the byte that it enables */
byteEnables =
(~(BIT(n) | BIT((n + 1)))) &
IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
byteEnables = byteEnables << PCI_NP_CBE_BESL;
ldata = val << (8 * n);
/*Set the address to be written */
addr = pci_config_addr(bdf, where);
non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
stat = pci_config_status();
debug("-> status %x\n", stat);
return stat;
}
static int pci_ixp_hose_write_config_dword(struct pci_controller *hose,
pci_dev_t bdf, int where, unsigned int val)
{
unsigned int addr;
int stat;
debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x",
bdf, where, val);
/*Set the address to be written */
addr = pci_config_addr(bdf, where);
non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val);
stat = pci_config_status();
debug("-> status %x\n", stat);
return stat;
}
static void non_prefetch_read(unsigned int addr,
unsigned int cmd, unsigned int *data)
{
writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
/*set up and execute the read */
writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
/*The result of the read is now in np_rdata */
*data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET);
return;
}
static void non_prefetch_write(unsigned int addr,
unsigned int cmd, unsigned int data)
{
writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET);
/*set up the write */
writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET);
/*Execute the write by writing to NP_WDATA */
writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET);
return;
}
static void crp_write(unsigned int offset, unsigned int data)
{
/*
* The CRP address register bit 16 indicates that we want to do a
* write
*/
writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET);
writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET);
}
void pci_ixp_init(struct pci_controller *hose)
{
unsigned int csr;
/*
* Specify that the AHB bus is operating in big endian mode. Set up
* byte lane swapping between little-endian PCI and the big-endian
* AHB bus
*/
#ifdef __ARMEB__
csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS;
#else
csr = PCI_CSR_ABE;
#endif
writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET);
/*
* We configure the PCI inbound memory windows to be
* 1:1 mapped to SDRAM
*/
crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000);
crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000);
crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000);
crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000);
/*
* Enable CSR window at 64 MiB to allow PCI masters
* to continue prefetching past 64 MiB boundary.
*/
crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000);
/*
* Enable the IO window to be way up high, at 0xfffffc00
*/
crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01);
/*Setup PCI-AHB and AHB-PCI address mappings */
writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET);
writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET);
writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET);
crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
udelay(1000);
/* clear error bits in status register */
writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE,
PCI_CSR_BASE + PCI_ISR_OFFSET);
/*
* Set Initialize Complete in PCI Control Register: allow IXP4XX to
* respond to PCI configuration cycles.
*/
csr |= PCI_CSR_IC;
writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET);
hose->first_busno = 0;
hose->last_busno = 0;
/* System memory space */
pci_set_region(hose->regions + 0,
PCI_MEMORY_BUS,
PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
PCI_MEM_BUS,
PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region(hose->regions + 2,
PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
hose->region_count = 3;
pci_set_ops(hose,
pci_ixp_hose_read_config_byte,
pci_ixp_hose_read_config_word,
pci_ixp_hose_read_config_dword,
pci_ixp_hose_write_config_byte,
pci_ixp_hose_write_config_word,
pci_ixp_hose_write_config_dword);
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
|
1001-study-uboot
|
drivers/pci/pci_ixp.c
|
C
|
gpl3
| 10,309
|
/*
* SH4 PCI Controller (PCIC) for U-Boot.
* (C) Dustin McIntire (dustin@sensoria.com)
* (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* u-boot/arch/sh/cpu/sh4/pci-sh4.c
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <pci.h>
int pci_sh4_init(struct pci_controller *hose)
{
hose->first_busno = 0;
hose->region_count = 0;
hose->last_busno = 0xff;
/* PCI memory space */
pci_set_region(hose->regions + 0,
CONFIG_PCI_MEM_BUS,
CONFIG_PCI_MEM_PHYS,
CONFIG_PCI_MEM_SIZE,
PCI_REGION_MEM);
hose->region_count++;
/* PCI IO space */
pci_set_region(hose->regions + 1,
CONFIG_PCI_IO_BUS,
CONFIG_PCI_IO_PHYS,
CONFIG_PCI_IO_SIZE,
PCI_REGION_IO);
hose->region_count++;
#if defined(CONFIG_PCI_SYS_BUS)
/* PCI System Memory space */
pci_set_region(hose->regions + 2,
CONFIG_PCI_SYS_BUS,
CONFIG_PCI_SYS_PHYS,
CONFIG_PCI_SYS_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count++;
#endif
udelay(1000);
pci_set_ops(hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
pci_sh4_read_config_dword,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
pci_sh4_write_config_dword);
pci_register_hose(hose);
udelay(1000);
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
hose->last_busno = pci_hose_scan(hose);
return 0;
}
int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
{
return 0;
}
#ifdef CONFIG_PCI_SCAN_SHOW
int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
{
return 1;
}
#endif /* CONFIG_PCI_SCAN_SHOW */
|
1001-study-uboot
|
drivers/pci/pci_sh4.c
|
C
|
gpl3
| 2,517
|
/*
* Support for indirect PCI bridges.
*
* Copyright (C) 1998 Gabriel Paubert.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <common.h>
#if !defined(__I386__)
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#define cfg_read(val, addr, type, op) *val = op((type)(addr))
#define cfg_write(val, addr, type, op) op((type *)(addr), (val))
#if defined(CONFIG_MPC8260)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
u32 b, d,f; \
b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
b = b - hose->first_busno; \
dev = PCI_BDF(b, d, f); \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
sync(); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
u32 b, d,f; \
b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
b = b - hose->first_busno; \
dev = PCI_BDF(b, d, f); \
*(hose->cfg_addr) = dev | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000; \
sync(); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#elif defined(CONFIG_440GX) || defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
u32 b, d,f; \
b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
b = b - hose->first_busno; \
dev = PCI_BDF(b, d, f); \
if (PCI_BUS(dev) > 0) \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001); \
else \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#else
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
u32 b, d,f; \
b = PCI_BUS(dev); d = PCI_DEV(dev); f = PCI_FUNC(dev); \
b = b - hose->first_busno; \
dev = PCI_BDF(b, d, f); \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
#endif
#define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask) \
static int \
indirect_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, type val) \
{ \
unsigned int msr = mfmsr(); \
mtmsr(msr & ~(MSR_EE | MSR_CE)); \
out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
out_le32(hose->cfg_addr, 0x00000000); \
mtmsr(msr); \
return 0; \
}
INDIRECT_PCI_OP(read, byte, u8 *, in_8, 3)
INDIRECT_PCI_OP(read, word, u16 *, in_le16, 2)
INDIRECT_PCI_OP(read, dword, u32 *, in_le32, 0)
#ifdef CONFIG_405GP
INDIRECT_PCI_OP_ERRATA6(write, byte, u8, out_8, 3)
INDIRECT_PCI_OP_ERRATA6(write, word, u16, out_le16, 2)
INDIRECT_PCI_OP_ERRATA6(write, dword, u32, out_le32, 0)
#else
INDIRECT_PCI_OP(write, byte, u8, out_8, 3)
INDIRECT_PCI_OP(write, word, u16, out_le16, 2)
INDIRECT_PCI_OP(write, dword, u32, out_le32, 0)
#endif
void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
{
pci_set_ops(hose,
indirect_read_config_byte,
indirect_read_config_word,
indirect_read_config_dword,
indirect_write_config_byte,
indirect_write_config_word,
indirect_write_config_dword);
hose->cfg_addr = (unsigned int *) cfg_addr;
hose->cfg_data = (unsigned char *) cfg_data;
}
#endif /* !__I386__ */
|
1001-study-uboot
|
drivers/pci/pci_indirect.c
|
C
|
gpl3
| 4,761
|
#!/bin/sh
echo "------server pull--------"
cd /home/wang/MyGitServer/uboot_src/
git pull /home/wang/port_uboot
echo "-----pull done---------"
|
1001-study-uboot
|
mypull_server.sh
|
Shell
|
gpl3
| 142
|
/*
* (C) Copyright 2005-2009 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/string.h>
#include "onenand_ipl.h"
#define onenand_block_address(block) (block)
#define onenand_sector_address(page) (page << 2)
#define onenand_buffer_address() ((1 << 3) << 8)
#define onenand_bufferram_address(block) (0)
#ifdef __HAVE_ARCH_MEMCPY32
extern void *memcpy32(void *dest, void *src, int size);
#endif
int (*onenand_read_page)(ulong block, ulong page, u_char *buf, int pagesize);
/* read a page with ECC */
static int generic_onenand_read_page(ulong block, ulong page,
u_char * buf, int pagesize)
{
unsigned long *base;
#ifndef __HAVE_ARCH_MEMCPY32
unsigned int offset, value;
unsigned long *p;
#endif
onenand_writew(onenand_block_address(block),
ONENAND_REG_START_ADDRESS1);
onenand_writew(onenand_bufferram_address(block),
ONENAND_REG_START_ADDRESS2);
onenand_writew(onenand_sector_address(page),
ONENAND_REG_START_ADDRESS8);
onenand_writew(onenand_buffer_address(),
ONENAND_REG_START_BUFFER);
onenand_writew(ONENAND_INT_CLEAR, ONENAND_REG_INTERRUPT);
onenand_writew(ONENAND_CMD_READ, ONENAND_REG_COMMAND);
#ifndef __HAVE_ARCH_MEMCPY32
p = (unsigned long *) buf;
#endif
base = (unsigned long *) (CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM);
while (!(READ_INTERRUPT() & ONENAND_INT_READ))
continue;
/* Check for invalid block mark */
if (page < 2 && (onenand_readw(ONENAND_SPARERAM) != 0xffff))
return 1;
#ifdef __HAVE_ARCH_MEMCPY32
/* 32 bytes boundary memory copy */
memcpy32(buf, base, pagesize);
#else
for (offset = 0; offset < (pagesize >> 2); offset++) {
value = *(base + offset);
*p++ = value;
}
#endif
return 0;
}
#ifndef CONFIG_ONENAND_START_PAGE
#define CONFIG_ONENAND_START_PAGE 1
#endif
#define ONENAND_PAGES_PER_BLOCK 64
static void onenand_generic_init(int *page_is_4KiB, int *page)
{
int dev_id, density;
if (onenand_readw(ONENAND_REG_TECHNOLOGY))
*page_is_4KiB = 1;
dev_id = onenand_readw(ONENAND_REG_DEVICE_ID);
density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT;
density &= ONENAND_DEVICE_DENSITY_MASK;
if (density >= ONENAND_DEVICE_DENSITY_4Gb &&
!(dev_id & ONENAND_DEVICE_IS_DDP))
*page_is_4KiB = 1;
}
/**
* onenand_read_block - Read CONFIG_SYS_MONITOR_LEN from begining
* of OneNAND, skipping bad blocks
* @return 0 on success
*/
int onenand_read_block(unsigned char *buf)
{
int block, nblocks;
int page = CONFIG_ONENAND_START_PAGE, offset = 0;
int pagesize, erasesize, erase_shift;
int page_is_4KiB = 0;
onenand_read_page = generic_onenand_read_page;
onenand_generic_init(&page_is_4KiB, &page);
if (page_is_4KiB) {
pagesize = 4096; /* OneNAND has 4KiB pagesize */
erase_shift = 18;
} else {
pagesize = 2048; /* OneNAND has 2KiB pagesize */
erase_shift = 17;
}
erasesize = (1 << erase_shift);
nblocks = (CONFIG_SYS_MONITOR_LEN + erasesize - 1) >> erase_shift;
/* NOTE: you must read page from page 1 of block 0 */
/* read the block page by page */
for (block = 0; block < nblocks; block++) {
for (; page < ONENAND_PAGES_PER_BLOCK; page++) {
if (onenand_read_page(block, page, buf + offset,
pagesize)) {
/* This block is bad. Skip it
* and read next block */
offset -= page * pagesize;
nblocks++;
break;
}
offset += pagesize;
}
page = 0;
}
return 0;
}
|
1001-study-uboot
|
onenand_ipl/onenand_read.c
|
C
|
gpl3
| 4,212
|
/*
* (C) Copyright 2005-2008 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from x-loader
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "onenand_ipl.h"
typedef int (init_fnc_t)(void);
void start_oneboot(void)
{
uchar *buf;
buf = (uchar *) CONFIG_SYS_LOAD_ADDR;
onenand_read_block(buf);
((init_fnc_t *)CONFIG_SYS_LOAD_ADDR)();
/* should never come here */
}
void hang(void)
{
for (;;);
}
|
1001-study-uboot
|
onenand_ipl/onenand_boot.c
|
C
|
gpl3
| 1,223
|
/*
* Board specific setup info
*
* (C) Copyright 2005-2008 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from board/omap2420h4/platform.S
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/arch/omap2420.h>
#include <asm/arch/mem.h>
#include <asm/arch/clocks.h>
#define APOLLON_CS0_BASE 0x00000000
#ifdef PRCM_CONFIG_I
#define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
#define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
#define SDRC_RFR_CTRL_0_VAL 0x00044C01
/* GPMC */
#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
#define APOLLON_GPMC_CONFIG2_0 0x000c1000
#define APOLLON_GPMC_CONFIG3_0 0x00030400
#define APOLLON_GPMC_CONFIG4_0 0x0B841006
#define APOLLON_GPMC_CONFIG5_0 0x020F0C11
#define APOLLON_GPMC_CONFIG6_0 0x00000000
#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
#elif defined(PRCM_CONFIG_II)
#define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
#define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
#define SDRC_RFR_CTRL_0_VAL 0x00030001
/* GPMC */
#define APOLLON_GPMC_CONFIG1_0 0xe30d1201
#define APOLLON_GPMC_CONFIG2_0 0x00080E81
#define APOLLON_GPMC_CONFIG3_0 0x00030400
#define APOLLON_GPMC_CONFIG4_0 0x08041586
#define APOLLON_GPMC_CONFIG5_0 0x020C090E
#define APOLLON_GPMC_CONFIG6_0 0x00000000
#define APOLLON_GPMC_CONFIG7_0 (0x00000e40 | (APOLLON_CS0_BASE >> 24))
#else
#error "Please configure PRCM schecm"
#endif
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
.globl lowlevel_init
lowlevel_init:
mov r3, r0 /* save skip information */
/* Disable watchdog */
ldr r0, =WD2_BASE
ldr r1, =WD_UNLOCK1
str r1, [r0, #WSPR]
ldr r1, =WD_UNLOCK2
str r1, [r0, #WSPR]
#ifdef DEBUG_LED
/* LED0 OFF */
ldr r0, =0x480000E5 /* ball AA10, mode 3 */
mov r1, #0x0b
strb r1, [r0]
#endif
/* Pin muxing for SDRC */
mov r1, #0x00
ldr r0, =0x480000A1 /* ball C12, mode 0 */
strb r1, [r0]
ldr r0, =0x48000032 /* ball D11, mode 0 */
strb r1, [r0]
ldr r0, =0x480000A3 /* ball B13, mode 0 */
strb r1, [r0]
/* SDRC setting */
ldr r0, =OMAP2420_SDRC_BASE
ldr r1, =0x00000010
str r1, [r0, #0x10]
ldr r1, =0x00000100
str r1, [r0, #0x44]
/* SDRC CS0 configuration */
#ifdef CONFIG_APOLLON_PLUS
ldr r1, =0x01702011
#else
ldr r1, =0x00d04011
#endif
str r1, [r0, #0x80]
ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
str r1, [r0, #0x9C]
ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
str r1, [r0, #0xA0]
ldr r1, =SDRC_RFR_CTRL_0_VAL
str r1, [r0, #0xA4]
ldr r1, =0x00000041
str r1, [r0, #0x70]
/* Manual command sequence */
ldr r1, =0x00000007
str r1, [r0, #0xA8]
ldr r1, =0x00000000
str r1, [r0, #0xA8]
ldr r1, =0x00000001
str r1, [r0, #0xA8]
ldr r1, =0x00000002
str r1, [r0, #0xA8]
str r1, [r0, #0xA8]
/*
* CS0 SDRC Mode register
* Burst length = 4 - DDR memory
* Serial mode
* CAS latency = 3
*/
ldr r1, =0x00000032
str r1, [r0, #0x84]
/* Note: You MUST set EMR values */
/* EMR1 & EMR2 */
ldr r1, =0x00000000
str r1, [r0, #0x88]
str r1, [r0, #0x8C]
#ifdef OLD_SDRC_DLLA_CTRL
/* SDRC_DLLA_CTRL */
ldr r1, =0x00007306
str r1, [r0, #0x60]
ldr r1, =0x00007303
str r1, [r0, #0x60]
#else
/* SDRC_DLLA_CTRL */
ldr r1, =0x00000506
str r1, [r0, #0x60]
ldr r1, =0x00000503
str r1, [r0, #0x60]
#endif
#ifdef __BROKEN_FEATURE__
/* SDRC_DLLB_CTRL */
ldr r1, =0x00000506
str r1, [r0, #0x68]
ldr r1, =0x00000503
str r1, [r0, #0x68]
#endif
/* little delay after init */
mov r2, #0x1800
1:
subs r2, r2, #0x1
bne 1b
ldr sp, SRAM_STACK
str ip, [sp] /* stash old link register */
mov ip, lr /* save link reg across call */
mov r0, r3 /* pass skip info to s_init */
bl s_init /* go setup pll,mux,memory */
ldr ip, [sp] /* restore save ip */
mov lr, ip /* restore link reg */
/* back to arch calling code */
mov pc, lr
/* the literal pools origin */
.ltorg
SRAM_STACK:
.word LOW_LEVEL_SRAM_STACK
|
1001-study-uboot
|
onenand_ipl/board/apollon/low_levelinit.S
|
Unix Assembly
|
gpl3
| 4,613
|
include $(TOPDIR)/config.mk
include $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/config.mk
LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds
LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_ONENAND_IPL
OBJCFLAGS += --gap-fill=0x00
SOBJS := low_levelinit.o
SOBJS += start.o
COBJS := apollon.o
COBJS += onenand_read.o
COBJS += onenand_boot.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(OBJTREE)/onenand_ipl/board/$(BOARDDIR)
onenandobj := $(OBJTREE)/onenand_ipl/
ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand-ipl-2k.bin $(onenandobj)onenand-ipl-4k.bin
all: $(obj).depend $(ALL)
$(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=0x800 -O binary $< $@
$(onenandobj)onenand-ipl-4k.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=0x1000 -O binary $< $@
$(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(onenandobj)onenand-ipl: $(OBJS) $(onenandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-Map $@.map -o $@
$(onenandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links from common files
# from cpu directory
$(obj)start.S:
@rm -f $@
ln -s $(SRCTREE)/$(CPUDIR)/start.S $@
# from onenand_ipl directory
$(obj)onenand_ipl.h:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/onenand_ipl.h $@
$(obj)onenand_boot.c: $(obj)onenand_ipl.h
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/onenand_boot.c $@
$(obj)onenand_read.c: $(obj)onenand_ipl.h
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/onenand_read.c $@
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)apollon.c:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/apollon.c $@
$(obj)low_levelinit.S:
@rm -f $@
ln -s $(SRCTREE)/onenand_ipl/board/$(BOARDDIR)/low_levelinit.S $@
endif
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)$.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
onenand_ipl/board/apollon/Makefile
|
Makefile
|
gpl3
| 2,444
|
#
# (C) Copyright 2005-2008 Samsung Electronics
# Kyungmin Park <kyungmin.park@samsung.com>
#
# Samsung Apollon board with OMAP2420 (ARM1136) cpu
#
# Apollon has 1 bank of 128MB mDDR-SDRAM on CS0
# Physical Address:
# 8000'0000 (bank0)
# 8800'0000 (bank1)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
CONFIG_SYS_TEXT_BASE = 0x00000000
|
1001-study-uboot
|
onenand_ipl/board/apollon/config.mk
|
Makefile
|
gpl3
| 378
|
/*
* (C) Copyright 2005-2008 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/mux.h>
#define write_config_reg(reg, value) \
do { \
writeb(value, reg); \
} while (0)
/*****************************************
* Routine: board_init
* Description: Early hardware init.
*****************************************/
int board_init(void)
{
return 0;
}
#ifdef CONFIG_SYS_PRINTF
/* Pin Muxing registers used for UART1 */
/****************************************
* Routine: muxSetupUART1 (ostboot)
* Description: Set up uart1 muxing
*****************************************/
static void muxSetupUART1(void)
{
/* UART1_CTS pin configuration, PIN = D21 */
write_config_reg(CONTROL_PADCONF_UART1_CTS, 0);
/* UART1_RTS pin configuration, PIN = H21 */
write_config_reg(CONTROL_PADCONF_UART1_RTS, 0);
/* UART1_TX pin configuration, PIN = L20 */
write_config_reg(CONTROL_PADCONF_UART1_TX, 0);
/* UART1_RX pin configuration, PIN = T21 */
write_config_reg(CONTROL_PADCONF_UART1_RX, 0);
}
#endif
/**********************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
* - Called at time when only stack is available.
**********************************************************/
int s_init(int skip)
{
#ifdef CONFIG_SYS_PRINTF
muxSetupUART1();
#endif
return 0;
}
|
1001-study-uboot
|
onenand_ipl/board/apollon/apollon.c
|
C
|
gpl3
| 2,336
|
/*
* (C) Copyright 2005-2008 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ONENAND_IPL_H
#define _ONENAND_IPL_H
#include <linux/mtd/onenand_regs.h>
#define onenand_readw(a) readw(THIS_ONENAND(a))
#define onenand_writew(v, a) writew(v, THIS_ONENAND(a))
#define THIS_ONENAND(a) (CONFIG_SYS_ONENAND_BASE + (a))
#define READ_INTERRUPT() onenand_readw(ONENAND_REG_INTERRUPT)
extern int (*onenand_read_page)(ulong block, ulong page,
u_char *buf, int pagesize);
extern int onenand_read_block(unsigned char *buf);
#endif
|
1001-study-uboot
|
onenand_ipl/onenand_ipl.h
|
C
|
gpl3
| 1,291
|
/*
* (C) Copyright 2007-2008 Semihalf, Rafal Jaworowski <raj@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <linux/types.h>
#include <api_public.h>
#include "glue.h"
static int valid_sig(struct api_signature *sig)
{
uint32_t checksum;
struct api_signature s;
if (sig == NULL)
return 0;
/*
* Clear the checksum field (in the local copy) so as to calculate the
* CRC with the same initial contents as at the time when the sig was
* produced
*/
s = *sig;
s.checksum = 0;
checksum = crc32(0, (unsigned char *)&s, sizeof(struct api_signature));
if (checksum != sig->checksum)
return 0;
return 1;
}
/*
* Searches for the U-Boot API signature
*
* returns 1/0 depending on found/not found result
*/
int api_search_sig(struct api_signature **sig)
{
unsigned char *sp;
uint32_t search_start = 0;
uint32_t search_end = 0;
if (sig == NULL)
return 0;
if (search_hint == 0)
search_hint = 255 * 1024 * 1024;
search_start = search_hint & ~0x000fffff;
search_end = search_start + API_SEARCH_LEN - API_SIG_MAGLEN;
sp = (unsigned char *)search_start;
while ((sp + API_SIG_MAGLEN) < (unsigned char *)search_end) {
if (!memcmp(sp, API_SIG_MAGIC, API_SIG_MAGLEN)) {
*sig = (struct api_signature *)sp;
if (valid_sig(*sig))
return 1;
}
sp += API_SIG_MAGLEN;
}
*sig = NULL;
return 0;
}
/****************************************
*
* console
*
****************************************/
int ub_getc(void)
{
int c;
if (!syscall(API_GETC, NULL, (uint32_t)&c))
return -1;
return c;
}
int ub_tstc(void)
{
int t;
if (!syscall(API_TSTC, NULL, (uint32_t)&t))
return -1;
return t;
}
void ub_putc(char c)
{
syscall(API_PUTC, NULL, (uint32_t)&c);
}
void ub_puts(const char *s)
{
syscall(API_PUTS, NULL, (uint32_t)s);
}
/****************************************
*
* system
*
****************************************/
void ub_reset(void)
{
syscall(API_RESET, NULL);
}
static struct mem_region mr[UB_MAX_MR];
static struct sys_info si;
struct sys_info * ub_get_sys_info(void)
{
int err = 0;
memset(&si, 0, sizeof(struct sys_info));
si.mr = mr;
si.mr_no = UB_MAX_MR;
memset(&mr, 0, sizeof(mr));
if (!syscall(API_GET_SYS_INFO, &err, (u_int32_t)&si))
return NULL;
return ((err) ? NULL : &si);
}
/****************************************
*
* timing
*
****************************************/
void ub_udelay(unsigned long usec)
{
syscall(API_UDELAY, NULL, &usec);
}
unsigned long ub_get_timer(unsigned long base)
{
unsigned long cur;
if (!syscall(API_GET_TIMER, NULL, &cur, &base))
return 0;
return cur;
}
/****************************************************************************
*
* devices
*
* Devices are identified by handles: numbers 0, 1, 2, ..., UB_MAX_DEV-1
*
***************************************************************************/
static struct device_info devices[UB_MAX_DEV];
struct device_info * ub_dev_get(int i)
{
return ((i < 0 || i >= UB_MAX_DEV) ? NULL : &devices[i]);
}
/*
* Enumerates the devices: fills out device_info elements in the devices[]
* array.
*
* returns: number of devices found
*/
int ub_dev_enum(void)
{
struct device_info *di;
int n = 0;
memset(&devices, 0, sizeof(struct device_info) * UB_MAX_DEV);
di = &devices[0];
if (!syscall(API_DEV_ENUM, NULL, di))
return 0;
while (di->cookie != NULL) {
if (++n >= UB_MAX_DEV)
break;
/* take another device_info */
di++;
/* pass on the previous cookie */
di->cookie = devices[n - 1].cookie;
if (!syscall(API_DEV_ENUM, NULL, di))
return 0;
}
return n;
}
/*
* handle: 0-based id of the device
*
* returns: 0 when OK, err otherwise
*/
int ub_dev_open(int handle)
{
struct device_info *di;
int err = 0;
if (handle < 0 || handle >= UB_MAX_DEV)
return API_EINVAL;
di = &devices[handle];
if (!syscall(API_DEV_OPEN, &err, di))
return -1;
return err;
}
int ub_dev_close(int handle)
{
struct device_info *di;
if (handle < 0 || handle >= UB_MAX_DEV)
return API_EINVAL;
di = &devices[handle];
if (!syscall(API_DEV_CLOSE, NULL, di))
return -1;
return 0;
}
/*
*
* Validates device for read/write, it has to:
*
* - have sane handle
* - be opened
*
* returns: 0/1 accordingly
*/
static int dev_valid(int handle)
{
if (handle < 0 || handle >= UB_MAX_DEV)
return 0;
if (devices[handle].state != DEV_STA_OPEN)
return 0;
return 1;
}
static int dev_stor_valid(int handle)
{
if (!dev_valid(handle))
return 0;
if (!(devices[handle].type & DEV_TYP_STOR))
return 0;
return 1;
}
int ub_dev_read(int handle, void *buf, lbasize_t len, lbastart_t start,
lbasize_t *rlen)
{
struct device_info *di;
lbasize_t act_len;
int err = 0;
if (!dev_stor_valid(handle))
return API_ENODEV;
di = &devices[handle];
if (!syscall(API_DEV_READ, &err, di, buf, &len, &start, &act_len))
return API_ESYSC;
if (!err && rlen)
*rlen = act_len;
return err;
}
static int dev_net_valid(int handle)
{
if (!dev_valid(handle))
return 0;
if (devices[handle].type != DEV_TYP_NET)
return 0;
return 1;
}
int ub_dev_recv(int handle, void *buf, int len, int *rlen)
{
struct device_info *di;
int err = 0, act_len;
if (!dev_net_valid(handle))
return API_ENODEV;
di = &devices[handle];
if (!syscall(API_DEV_READ, &err, di, buf, &len, &act_len))
return API_ESYSC;
if (!err && rlen)
*rlen = act_len;
return (err);
}
int ub_dev_send(int handle, void *buf, int len)
{
struct device_info *di;
int err = 0;
if (!dev_net_valid(handle))
return API_ENODEV;
di = &devices[handle];
if (!syscall(API_DEV_WRITE, &err, di, buf, &len))
return API_ESYSC;
return err;
}
/****************************************
*
* env vars
*
****************************************/
char * ub_env_get(const char *name)
{
char *value;
if (!syscall(API_ENV_GET, NULL, (uint32_t)name, (uint32_t)&value))
return NULL;
return value;
}
void ub_env_set(const char *name, char *value)
{
syscall(API_ENV_SET, NULL, (uint32_t)name, (uint32_t)value);
}
static char env_name[256];
const char * ub_env_enum(const char *last)
{
const char *env, *str;
int i;
env = NULL;
/*
* It's OK to pass only the name piece as last (and not the whole
* 'name=val' string), since the API_ENUM_ENV call uses envmatch()
* internally, which handles such case
*/
if (!syscall(API_ENV_ENUM, NULL, (uint32_t)last, (uint32_t)&env))
return NULL;
if (!env)
/* no more env. variables to enumerate */
return NULL;
/* next enumerated env var */
memset(env_name, 0, 256);
for (i = 0, str = env; *str != '=' && *str != '\0';)
env_name[i++] = *str++;
env_name[i] = '\0';
return env_name;
}
/****************************************
*
* display
*
****************************************/
int ub_display_get_info(int type, struct display_info *di)
{
int err = 0;
if (!syscall(API_DISPLAY_GET_INFO, &err, (uint32_t)type, (uint32_t)di))
return API_ESYSC;
return err;
}
int ub_display_draw_bitmap(ulong bitmap, int x, int y)
{
int err = 0;
if (!syscall(API_DISPLAY_DRAW_BITMAP, &err, bitmap, x, y))
return API_ESYSC;
return err;
}
void ub_display_clear(void)
{
syscall(API_DISPLAY_CLEAR, NULL);
}
|
1001-study-uboot
|
examples/api/glue.c
|
C
|
gpl3
| 7,972
|
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
/*
* This is the header file for conveniency wrapper routines (API glue)
*/
#ifndef _API_GLUE_H_
#define _API_GLUE_H_
#define API_SEARCH_LEN (3 * 1024 * 1024) /* 3MB search range */
#define UB_MAX_MR 5 /* max mem regions number */
#define UB_MAX_DEV 6 /* max devices number */
extern void *syscall_ptr;
extern uint32_t search_hint;
int syscall(int, int *, ...);
int api_search_sig(struct api_signature **sig);
/*
* The ub_ library calls are part of the application, not U-Boot code! They
* are front-end wrappers that are used by the consumer application: they
* prepare arguments for particular syscall and jump to the low level
* syscall()
*/
/* console */
int ub_getc(void);
int ub_tstc(void);
void ub_putc(char c);
void ub_puts(const char *s);
/* system */
void ub_reset(void);
struct sys_info * ub_get_sys_info(void);
/* time */
void ub_udelay(unsigned long);
unsigned long ub_get_timer(unsigned long);
/* env vars */
char * ub_env_get(const char *name);
void ub_env_set(const char *name, char *value);
const char * ub_env_enum(const char *last);
/* devices */
int ub_dev_enum(void);
int ub_dev_open(int handle);
int ub_dev_close(int handle);
int ub_dev_read(int handle, void *buf, lbasize_t len,
lbastart_t start, lbasize_t *rlen);
int ub_dev_send(int handle, void *buf, int len);
int ub_dev_recv(int handle, void *buf, int len, int *rlen);
struct device_info * ub_dev_get(int);
/* display */
int ub_display_get_info(int type, struct display_info *di);
int ub_display_draw_bitmap(ulong bitmap, int x, int y);
void ub_display_clear(void);
#endif /* _API_GLUE_H_ */
|
1001-study-uboot
|
examples/api/glue.h
|
C
|
gpl3
| 2,504
|
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#if defined(CONFIG_PPC)
.text
.globl _start
_start:
lis %r11, search_hint@ha
addi %r11, %r11, search_hint@l
stw %r1, 0(%r11)
b main
.globl syscall
syscall:
lis %r11, syscall_ptr@ha
addi %r11, %r11, syscall_ptr@l
lwz %r11, 0(%r11)
mtctr %r11
bctr
#elif defined(CONFIG_ARM)
.text
.globl _start
_start:
ldr ip, =search_hint
str sp, [ip]
b main
.globl syscall
syscall:
ldr ip, =syscall_ptr
ldr pc, [ip]
#else
#error No support for this arch!
#endif
.globl syscall_ptr
syscall_ptr:
.align 4
.long 0
.globl search_hint
search_hint:
.long 0
|
1001-study-uboot
|
examples/api/crt0.S
|
Unix Assembly
|
gpl3
| 1,462
|
#
# (C) Copyright 2007 Semihalf
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundatio; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
ifeq ($(ARCH),powerpc)
LOAD_ADDR = 0x40000
endif
ifeq ($(ARCH),arm)
LOAD_ADDR = 0x1000000
endif
include $(TOPDIR)/config.mk
# Resulting ELF and binary exectuables will be named demo and demo.bin
OUTPUT-$(CONFIG_API) = $(obj)demo
OUTPUT = $(OUTPUT-y)
# Source files located in the examples/api directory
SOBJ_FILES-$(CONFIG_API) += crt0.o
COBJ_FILES-$(CONFIG_API) += demo.o
COBJ_FILES-$(CONFIG_API) += glue.o
COBJ_FILES-$(CONFIG_API) += libgenwrap.o
# Source files which exist outside the examples/api directory
EXT_COBJ_FILES-$(CONFIG_API) += lib/crc32.o
EXT_COBJ_FILES-$(CONFIG_API) += lib/ctype.o
EXT_COBJ_FILES-$(CONFIG_API) += lib/div64.o
EXT_COBJ_FILES-$(CONFIG_API) += lib/string.o
EXT_COBJ_FILES-$(CONFIG_API) += lib/time.o
EXT_COBJ_FILES-$(CONFIG_API) += lib/vsprintf.o
ifeq ($(ARCH),powerpc)
EXT_SOBJ_FILES-$(CONFIG_API) += arch/powerpc/lib/ppcstring.o
endif
# Create a list of source files so their dependencies can be auto-generated
SRCS += $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c))
SRCS += $(addprefix $(SRCTREE)/,$(EXT_SOBJ_FILES-y:.o=.S))
SRCS += $(addprefix $(SRCTREE)/examples/api/,$(COBJ_FILES-y:.o=.c))
SRCS += $(addprefix $(SRCTREE)/examples/api/,$(SOBJ_FILES-y:.o=.S))
# Create a list of object files to be compiled
OBJS += $(addprefix $(obj),$(SOBJ_FILES-y))
OBJS += $(addprefix $(obj),$(COBJ_FILES-y))
OBJS += $(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y)))
OBJS += $(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y)))
CPPFLAGS += -I..
all: $(obj).depend $(OUTPUT)
#########################################################################
$(OUTPUT): $(OBJS)
$(LD) -Ttext $(LOAD_ADDR) -o $@ $^ $(PLATFORM_LIBS)
$(OBJCOPY) -O binary $@ $(OUTPUT).bin 2>/dev/null
# Rule to build generic library C files
$(obj)%.o: $(SRCTREE)/lib/%.c
$(CC) -g $(CFLAGS) -c -o $@ $<
# Rule to build architecture-specific library assembly files
$(obj)%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S
$(CC) -g $(CFLAGS) -c -o $@ $<
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
examples/api/Makefile
|
Makefile
|
gpl3
| 2,989
|
/*
* (C) Copyright 2007 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*
* This is is a set of wrappers/stubs that allow to use certain routines from
* U-Boot's lib in the standalone app. This way way we can re-use
* existing code e.g. operations on strings and similar.
*
*/
#include <common.h>
#include <linux/types.h>
#include <api_public.h>
#include "glue.h"
/*
* printf() and vprintf() are stolen from u-boot/common/console.c
*/
int printf (const char *fmt, ...)
{
va_list args;
uint i;
char printbuffer[256];
va_start (args, fmt);
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
i = vsprintf (printbuffer, fmt, args);
va_end (args);
/* Print the string */
ub_puts (printbuffer);
return i;
}
int vprintf (const char *fmt, va_list args)
{
uint i;
char printbuffer[256];
/* For this to work, printbuffer must be larger than
* anything we ever want to print.
*/
i = vsprintf (printbuffer, fmt, args);
/* Print the string */
ub_puts (printbuffer);
return i;
}
void putc (const char c)
{
ub_putc(c);
}
void __udelay(unsigned long usec)
{
ub_udelay(usec);
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ub_reset();
return 0;
}
void *malloc (size_t len)
{
return NULL;
}
void hang (void)
{
while (1) ;
}
|
1001-study-uboot
|
examples/api/libgenwrap.c
|
C
|
gpl3
| 2,141
|
/*
* (C) Copyright 2007-2008 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <linux/types.h>
#include <api_public.h>
#include "glue.h"
#define errf(fmt, args...) do { printf("ERROR @ %s(): ", __func__); printf(fmt, ##args); } while (0)
#define BUF_SZ 2048
#define WAIT_SECS 5
void test_dump_buf(void *, int);
void test_dump_di(int);
void test_dump_si(struct sys_info *);
void test_dump_sig(struct api_signature *);
static char buf[BUF_SZ];
int main(int argc, char * const argv[])
{
int rv = 0, h, i, j, devs_no;
struct api_signature *sig = NULL;
ulong start, now;
struct device_info *di;
lbasize_t rlen;
struct display_info disinfo;
if (!api_search_sig(&sig))
return -1;
syscall_ptr = sig->syscall;
if (syscall_ptr == NULL)
return -2;
if (sig->version > API_SIG_VERSION)
return -3;
printf("API signature found @%x\n", (unsigned int)sig);
test_dump_sig(sig);
printf("\n*** Consumer API test ***\n");
printf("syscall ptr 0x%08x@%08x\n", (unsigned int)syscall_ptr,
(unsigned int)&syscall_ptr);
/* console activities */
ub_putc('B');
printf("*** Press any key to continue ***\n");
printf("got char 0x%x\n", ub_getc());
/* system info */
test_dump_si(ub_get_sys_info());
/* timing */
printf("\n*** Timing - wait a couple of secs ***\n");
start = ub_get_timer(0);
printf("\ntime: start %lu\n\n", start);
for (i = 0; i < WAIT_SECS; i++)
for (j = 0; j < 1000; j++)
ub_udelay(1000); /* wait 1 ms */
/* this is the number of milliseconds that passed from ub_get_timer(0) */
now = ub_get_timer(start);
printf("\ntime: now %lu\n\n", now);
/* enumerate devices */
printf("\n*** Enumerate devices ***\n");
devs_no = ub_dev_enum();
printf("Number of devices found: %d\n", devs_no);
if (devs_no == 0)
return -1;
printf("\n*** Show devices ***\n");
for (i = 0; i < devs_no; i++) {
test_dump_di(i);
printf("\n");
}
printf("\n*** Operations on devices ***\n");
/* test opening a device already opened */
h = 0;
if ((rv = ub_dev_open(h)) != 0) {
errf("open device %d error %d\n", h, rv);
return -1;
}
if ((rv = ub_dev_open(h)) != 0)
errf("open device %d error %d\n", h, rv);
ub_dev_close(h);
/* test storage */
printf("Trying storage devices...\n");
for (i = 0; i < devs_no; i++) {
di = ub_dev_get(i);
if (di->type & DEV_TYP_STOR)
break;
}
if (i == devs_no)
printf("No storage devices available\n");
else {
memset(buf, 0, BUF_SZ);
if ((rv = ub_dev_open(i)) != 0)
errf("open device %d error %d\n", i, rv);
else if ((rv = ub_dev_read(i, buf, 1, 0, &rlen)) != 0)
errf("could not read from device %d, error %d\n", i, rv);
else {
printf("Sector 0 dump (512B):\n");
test_dump_buf(buf, 512);
}
ub_dev_close(i);
}
/* test networking */
printf("Trying network devices...\n");
for (i = 0; i < devs_no; i++) {
di = ub_dev_get(i);
if (di->type == DEV_TYP_NET)
break;
}
if (i == devs_no)
printf("No network devices available\n");
else {
if ((rv = ub_dev_open(i)) != 0)
errf("open device %d error %d\n", i, rv);
else if ((rv = ub_dev_send(i, &buf, 2048)) != 0)
errf("could not send to device %d, error %d\n", i, rv);
ub_dev_close(i);
}
if (ub_dev_close(h) != 0)
errf("could not close device %d\n", h);
printf("\n*** Env vars ***\n");
printf("ethact = %s\n", ub_env_get("ethact"));
printf("old fileaddr = %s\n", ub_env_get("fileaddr"));
ub_env_set("fileaddr", "deadbeef");
printf("new fileaddr = %s\n", ub_env_get("fileaddr"));
const char *env = NULL;
while ((env = ub_env_enum(env)) != NULL)
printf("%s = %s\n", env, ub_env_get(env));
printf("\n*** Display ***\n");
if (ub_display_get_info(DISPLAY_TYPE_LCD, &disinfo)) {
printf("LCD info: failed\n");
} else {
printf("LCD info:\n");
printf(" pixel width: %d\n", disinfo.pixel_width);
printf(" pixel height: %d\n", disinfo.pixel_height);
printf(" screen rows: %d\n", disinfo.screen_rows);
printf(" screen cols: %d\n", disinfo.screen_cols);
}
if (ub_display_get_info(DISPLAY_TYPE_VIDEO, &disinfo)) {
printf("video info: failed\n");
} else {
printf("video info:\n");
printf(" pixel width: %d\n", disinfo.pixel_width);
printf(" pixel height: %d\n", disinfo.pixel_height);
printf(" screen rows: %d\n", disinfo.screen_rows);
printf(" screen cols: %d\n", disinfo.screen_cols);
}
printf("*** Press any key to continue ***\n");
printf("got char 0x%x\n", ub_getc());
/*
* This only clears messages on screen, not on serial port. It is
* equivalent to a no-op if no display is available.
*/
ub_display_clear();
/* reset */
printf("\n*** Resetting board ***\n");
ub_reset();
printf("\nHmm, reset returned...?!\n");
return rv;
}
void test_dump_sig(struct api_signature *sig)
{
printf("signature:\n");
printf(" version\t= %d\n", sig->version);
printf(" checksum\t= 0x%08x\n", sig->checksum);
printf(" sc entry\t= 0x%08x\n", (unsigned int)sig->syscall);
}
void test_dump_si(struct sys_info *si)
{
int i;
printf("sys info:\n");
printf(" clkbus\t= 0x%08x\n", (unsigned int)si->clk_bus);
printf(" clkcpu\t= 0x%08x\n", (unsigned int)si->clk_cpu);
printf(" bar\t\t= 0x%08x\n", (unsigned int)si->bar);
printf("---\n");
for (i = 0; i < si->mr_no; i++) {
if (si->mr[i].flags == 0)
break;
printf(" start\t= 0x%08lx\n", si->mr[i].start);
printf(" size\t= 0x%08lx\n", si->mr[i].size);
switch(si->mr[i].flags & 0x000F) {
case MR_ATTR_FLASH:
printf(" type FLASH\n");
break;
case MR_ATTR_DRAM:
printf(" type DRAM\n");
break;
case MR_ATTR_SRAM:
printf(" type SRAM\n");
break;
default:
printf(" type UNKNOWN\n");
}
printf("---\n");
}
}
static char *test_stor_typ(int type)
{
if (type & DT_STOR_IDE)
return "IDE";
if (type & DT_STOR_MMC)
return "MMC";
if (type & DT_STOR_SATA)
return "SATA";
if (type & DT_STOR_SCSI)
return "SCSI";
if (type & DT_STOR_USB)
return "USB";
return "Unknown";
}
void test_dump_buf(void *buf, int len)
{
int i;
int line_counter = 0;
int sep_flag = 0;
int addr = 0;
printf("%07x:\t", addr);
for (i = 0; i < len; i++) {
if (line_counter++ > 15) {
line_counter = 0;
sep_flag = 0;
addr += 16;
i--;
printf("\n%07x:\t", addr);
continue;
}
if (sep_flag++ > 1) {
sep_flag = 1;
printf(" ");
}
printf("%02x", *((char *)buf++));
}
printf("\n");
}
void test_dump_di(int handle)
{
int i;
struct device_info *di = ub_dev_get(handle);
printf("device info (%d):\n", handle);
printf(" cookie\t= 0x%08x\n", (uint32_t)di->cookie);
printf(" type\t\t= 0x%08x\n", di->type);
if (di->type == DEV_TYP_NET) {
printf(" hwaddr\t= ");
for (i = 0; i < 6; i++)
printf("%02x ", di->di_net.hwaddr[i]);
printf("\n");
} else if (di->type & DEV_TYP_STOR) {
printf(" type\t\t= %s\n", test_stor_typ(di->type));
printf(" blk size\t\t= %d\n", (unsigned int)di->di_stor.block_size);
printf(" blk count\t\t= %d\n", (unsigned int)di->di_stor.block_count);
}
}
|
1001-study-uboot
|
examples/api/demo.c
|
C
|
gpl3
| 7,818
|
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <exports.h>
int hello_world (int argc, char * const argv[])
{
int i;
/* Print the ABI version */
app_startup(argv);
printf ("Example expects ABI version %d\n", XF_VERSION);
printf ("Actual U-Boot ABI version %d\n", (int)get_version());
printf ("Hello World\n");
printf ("argc = %d\n", argc);
for (i=0; i<=argc; ++i) {
printf ("argv[%d] = \"%s\"\n",
i,
argv[i] ? argv[i] : "<NULL>");
}
printf ("Hit any key to exit ... ");
while (!tstc())
;
/* consume input */
(void) getc();
printf ("\n\n");
return (0);
}
|
1001-study-uboot
|
examples/standalone/hello_world.c
|
C
|
gpl3
| 1,449
|
/*
* Copyright 1998-2001 by Donald Becker.
* This software may be used and distributed according to the terms of
* the GNU General Public License (GPL), incorporated herein by reference.
* Contact the author for use under other terms.
*
* This program must be compiled with "-O"!
* See the bottom of this file for the suggested compile-command.
*
* The author may be reached as becker@scyld.com, or C/O
* Scyld Computing Corporation
* 410 Severn Ave., Suite 210
* Annapolis MD 21403
*
* Common-sense licensing statement: Using any portion of this program in
* your own program means that you must give credit to the original author
* and release the resulting code under the GPL.
*/
#define _PPC_STRING_H_ /* avoid unnecessary str/mem functions */
#include <common.h>
#include <exports.h>
#include <asm/io.h>
/* Default EEPROM for i82559 */
static unsigned short default_eeprom[64] = {
0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
};
static unsigned short eeprom[256];
static int eeprom_size = 64;
static int eeprom_addr_size = 6;
static int debug = 0;
static inline unsigned short swap16(unsigned short x)
{
return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
}
void * memcpy(void * dest,const void *src,size_t count)
{
char *tmp = (char *) dest, *s = (char *) src;
while (count--)
*tmp++ = *s++;
return dest;
}
/* The EEPROM commands include the alway-set leading bit. */
#define EE_WRITE_CMD (5)
#define EE_READ_CMD (6)
#define EE_ERASE_CMD (7)
/* Serial EEPROM section. */
#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
#define EE_CS 0x02 /* EEPROM chip select. */
#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
#define EE_ENB (0x4800 | EE_CS)
#define EE_WRITE_0 0x4802
#define EE_WRITE_1 0x4806
#define EE_OFFSET 14
/* Delay between EEPROM clock transitions. */
#define eeprom_delay(ee_addr) inw(ee_addr)
/* Wait for the EEPROM to finish the previous operation. */
static int eeprom_busy_poll(long ee_ioaddr)
{
int i;
outw(EE_ENB, ee_ioaddr);
for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
if (inw(ee_ioaddr) & EE_DATA_READ)
break;
return i;
}
/* This executes a generic EEPROM command, typically a write or write enable.
It returns the data output from the EEPROM, and thus may also be used for
reads. */
static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len)
{
unsigned retval = 0;
long ee_addr = ioaddr + EE_OFFSET;
if (debug > 1)
printf(" EEPROM op 0x%x: ", cmd);
outw(EE_ENB | EE_SHIFT_CLK, ee_addr);
/* Shift the command bits out. */
do {
short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
outw(dataval, ee_addr);
eeprom_delay(ee_addr);
if (debug > 2)
printf("%X", inw(ee_addr) & 15);
outw(dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay(ee_addr);
retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
} while (--cmd_len >= 0);
#if 0
outw(EE_ENB, ee_addr);
#endif
/* Terminate the EEPROM access. */
outw(EE_ENB & ~EE_CS, ee_addr);
if (debug > 1)
printf(" EEPROM result is 0x%5.5x.\n", retval);
return retval;
}
static int read_eeprom(long ioaddr, int location, int addr_len)
{
return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location)
<< 16 , 3 + addr_len + 16) & 0xffff;
}
static void write_eeprom(long ioaddr, int index, int value, int addr_len)
{
long ee_ioaddr = ioaddr + EE_OFFSET;
int i;
/* Poll for previous op finished. */
eeprom_busy_poll(ee_ioaddr); /* Typical 0 ticks */
/* Enable programming modes. */
do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len);
/* Do the actual write. */
do_eeprom_cmd(ioaddr,
(((EE_WRITE_CMD<<addr_len) | index)<<16) | (value & 0xffff),
3 + addr_len + 16);
/* Poll for write finished. */
i = eeprom_busy_poll(ee_ioaddr); /* Typical 2000 ticks */
if (debug)
printf(" Write finished after %d ticks.\n", i);
/* Disable programming. This command is not instantaneous, so we check
for busy before the next op. */
do_eeprom_cmd(ioaddr, (0x40 << (addr_len-4)), 3 + addr_len);
eeprom_busy_poll(ee_ioaddr);
}
static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr)
{
unsigned short checksum = 0;
int size_test;
int i;
printf("Resetting i82559 EEPROM @ 0x%08lx ... ", ioaddr);
size_test = do_eeprom_cmd(ioaddr, (EE_READ_CMD << 8) << 16, 27);
eeprom_addr_size = (size_test & 0xffe0000) == 0xffe0000 ? 8 : 6;
eeprom_size = 1 << eeprom_addr_size;
memcpy(eeprom, default_eeprom, sizeof default_eeprom);
for (i = 0; i < 3; i++)
eeprom[i] = (hwaddr[i*2+1]<<8) + hwaddr[i*2];
/* Recalculate the checksum. */
for (i = 0; i < eeprom_size - 1; i++)
checksum += eeprom[i];
eeprom[i] = 0xBABA - checksum;
for (i = 0; i < eeprom_size; i++)
write_eeprom(ioaddr, i, eeprom[i], eeprom_addr_size);
for (i = 0; i < eeprom_size; i++)
if (read_eeprom(ioaddr, i, eeprom_addr_size) != eeprom[i]) {
printf("failed\n");
return 1;
}
printf("done\n");
return 0;
}
static unsigned int hatoi(char *p, char **errp)
{
unsigned int res = 0;
while (1) {
switch (*p) {
case 'a':
case 'b':
case 'c':
case 'd':
case 'e':
case 'f':
res |= (*p - 'a' + 10);
break;
case 'A':
case 'B':
case 'C':
case 'D':
case 'E':
case 'F':
res |= (*p - 'A' + 10);
break;
case '0':
case '1':
case '2':
case '3':
case '4':
case '5':
case '6':
case '7':
case '8':
case '9':
res |= (*p - '0');
break;
default:
if (errp) {
*errp = p;
}
return res;
}
p++;
if (*p == 0) {
break;
}
res <<= 4;
}
if (errp) {
*errp = NULL;
}
return res;
}
static unsigned char *gethwaddr(char *in, unsigned char *out)
{
char tmp[3];
int i;
char *err;
for (i=0;i<6;i++) {
if (in[i*3+2] == 0 && i == 5) {
out[i] = hatoi(&in[i*3], &err);
if (err) {
return NULL;
}
} else if (in[i*3+2] == ':' && i < 5) {
tmp[0] = in[i*3];
tmp[1] = in[i*3+1];
tmp[2] = 0;
out[i] = hatoi(tmp, &err);
if (err) {
return NULL;
}
} else {
return NULL;
}
}
return out;
}
static u32
read_config_dword(int bus, int dev, int func, int reg)
{
u32 res;
outl(0x80000000|(bus&0xff)<<16|(dev&0x1f)<<11|(func&7)<<8|(reg&0xfc),
0xcf8);
res = inl(0xcfc);
outl(0, 0xcf8);
return res;
}
static u16
read_config_word(int bus, int dev, int func, int reg)
{
u32 res;
outl(0x80000000|(bus&0xff)<<16|(dev&0x1f)<<11|(func&7)<<8|(reg&0xfc),
0xcf8);
res = inw(0xcfc + (reg & 2));
outl(0, 0xcf8);
return res;
}
static void
write_config_word(int bus, int dev, int func, int reg, u16 data)
{
outl(0x80000000|(bus&0xff)<<16|(dev&0x1f)<<11|(func&7)<<8|(reg&0xfc),
0xcf8);
outw(data, 0xcfc + (reg & 2));
outl(0, 0xcf8);
}
int main (int argc, char * const argv[])
{
unsigned char *eth_addr;
uchar buf[6];
int instance;
app_startup(argv);
if (argc != 2) {
printf ("call with base Ethernet address\n");
return 1;
}
eth_addr = gethwaddr(argv[1], buf);
if (NULL == eth_addr) {
printf ("Can not parse ethernet address\n");
return 1;
}
if (eth_addr[5] & 0x01) {
printf("Base Ethernet address must be even\n");
}
for (instance = 0; instance < 2; instance ++) {
unsigned int io_addr;
unsigned char mac[6];
int bar1 = read_config_dword(0, 6+instance, 0, 0x14);
if (! (bar1 & 1)) {
printf("ETH%d is disabled %x\n", instance, bar1);
} else {
printf("ETH%d IO=0x%04x\n", instance, bar1 & ~3);
}
io_addr = (bar1 & (~3L));
write_config_word(0, 6+instance, 0, 4,
read_config_word(0, 6+instance, 0, 4) | 1);
printf("ETH%d CMD %04x\n", instance,
read_config_word(0, 6+instance, 0, 4));
memcpy(mac, eth_addr, 6);
mac[5] += instance;
printf("got io=%04x, ha=%02x:%02x:%02x:%02x:%02x:%02x\n",
io_addr, mac[0], mac[1], mac[2],
mac[3], mac[4], mac[5]);
reset_eeprom(io_addr, mac);
}
return 0;
}
|
1001-study-uboot
|
examples/standalone/82559_eeprom.c
|
C
|
gpl3
| 8,361
|
/*
* (C) Copyright 2004
* Robin Getz rgetz@blacfin.uclinux.org
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Heavily borrowed from the following peoples GPL'ed software:
* - Wolfgang Denk, DENX Software Engineering, wd@denx.de
* Das U-boot
* - Ladislav Michl ladis@linux-mips.org
* A rejected patch on the U-Boot mailing list
*/
#include <common.h>
#include <exports.h>
#include "../drivers/net/smc91111.h"
#ifndef SMC91111_EEPROM_INIT
# define SMC91111_EEPROM_INIT()
#endif
#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
#define EEPROM 0x1
#define MAC 0x2
#define UNKNOWN 0x4
void dump_reg (struct eth_device *dev);
void dump_eeprom (struct eth_device *dev);
int write_eeprom_reg (struct eth_device *dev, int value, int reg);
void copy_from_eeprom (struct eth_device *dev);
void print_MAC (struct eth_device *dev);
int read_eeprom_reg (struct eth_device *dev, int reg);
void print_macaddr (struct eth_device *dev);
int smc91111_eeprom (int argc, char * const argv[])
{
int c, i, j, done, line, reg, value, start, what;
char input[50];
struct eth_device dev;
dev.iobase = CONFIG_SMC91111_BASE;
/* Print the ABI version */
app_startup (argv);
if (XF_VERSION != (int) get_version ()) {
printf ("Expects ABI version %d\n", XF_VERSION);
printf ("Actual U-Boot ABI version %d\n",
(int) get_version ());
printf ("Can't run\n\n");
return (0);
}
SMC91111_EEPROM_INIT();
if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
printf ("Can't find SMSC91111\n");
return (0);
}
done = 0;
what = UNKNOWN;
printf ("\n");
while (!done) {
/* print the prompt */
printf ("SMC91111> ");
line = 0;
i = 0;
start = 1;
while (!line) {
/* Wait for a keystroke */
while (!tstc ());
c = getc ();
/* Make Uppercase */
if (c >= 'Z')
c -= ('a' - 'A');
/* printf(" |%02x| ",c); */
switch (c) {
case '\r': /* Enter */
case '\n':
input[i] = 0;
puts ("\r\n");
line = 1;
break;
case '\0': /* nul */
continue;
case 0x03: /* ^C - break */
input[0] = 0;
i = 0;
line = 1;
done = 1;
break;
case 0x5F:
case 0x08: /* ^H - backspace */
case 0x7F: /* DEL - backspace */
if (i > 0) {
puts ("\b \b");
i--;
}
break;
default:
if (start) {
if ((c == 'W') || (c == 'D')
|| (c == 'M') || (c == 'C')
|| (c == 'P')) {
putc (c);
input[i] = c;
if (i <= 45)
i++;
start = 0;
}
} else {
if ((c >= '0' && c <= '9')
|| (c >= 'A' && c <= 'F')
|| (c == 'E') || (c == 'M')
|| (c == ' ')) {
putc (c);
input[i] = c;
if (i <= 45)
i++;
break;
}
}
break;
}
}
for (; i < 49; i++)
input[i] = 0;
switch (input[0]) {
case ('W'):
/* Line should be w reg value */
i = 0;
reg = 0;
value = 0;
/* Skip to the next space or end) */
while ((input[i] != ' ') && (input[i] != 0))
i++;
if (input[i] != 0)
i++;
/* Are we writing to EEPROM or MAC */
switch (input[i]) {
case ('E'):
what = EEPROM;
break;
case ('M'):
what = MAC;
break;
default:
what = UNKNOWN;
break;
}
/* skip to the next space or end */
while ((input[i] != ' ') && (input[i] != 0))
i++;
if (input[i] != 0)
i++;
/* Find register to write into */
j = 0;
while ((input[i] != ' ') && (input[i] != 0)) {
j = input[i] - 0x30;
if (j >= 0xA) {
j -= 0x07;
}
reg = (reg * 0x10) + j;
i++;
}
while ((input[i] != ' ') && (input[i] != 0))
i++;
if (input[i] != 0)
i++;
else
what = UNKNOWN;
/* Get the value to write */
j = 0;
while ((input[i] != ' ') && (input[i] != 0)) {
j = input[i] - 0x30;
if (j >= 0xA) {
j -= 0x07;
}
value = (value * 0x10) + j;
i++;
}
switch (what) {
case 1:
printf ("Writing EEPROM register %02x with %04x\n", reg, value);
write_eeprom_reg (&dev, value, reg);
break;
case 2:
printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
SMC_SELECT_BANK (&dev, reg >> 4);
SMC_outw (&dev, value, reg & 0xE);
break;
default:
printf ("Wrong\n");
break;
}
break;
case ('D'):
dump_eeprom (&dev);
break;
case ('M'):
dump_reg (&dev);
break;
case ('C'):
copy_from_eeprom (&dev);
break;
case ('P'):
print_macaddr (&dev);
break;
default:
break;
}
}
return (0);
}
void copy_from_eeprom (struct eth_device *dev)
{
int i;
SMC_SELECT_BANK (dev, 1);
SMC_outw (dev, (SMC_inw (dev, CTL_REG) & !CTL_EEPROM_SELECT) |
CTL_RELOAD, CTL_REG);
i = 100;
while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i)
udelay (100);
if (i == 0) {
printf ("Timeout Refreshing EEPROM registers\n");
} else {
printf ("EEPROM contents copied to MAC\n");
}
}
void print_macaddr (struct eth_device *dev)
{
int i, j, k, mac[6];
printf ("Current MAC Address in SMSC91111 ");
SMC_SELECT_BANK (dev, 1);
for (i = 0; i < 5; i++) {
printf ("%02x:", SMC_inb (dev, ADDR0_REG + i));
}
printf ("%02x\n", SMC_inb (dev, ADDR0_REG + 5));
i = 0;
for (j = 0x20; j < 0x23; j++) {
k = read_eeprom_reg (dev, j);
mac[i] = k & 0xFF;
i++;
mac[i] = k >> 8;
i++;
}
printf ("Current MAC Address in EEPROM ");
for (i = 0; i < 5; i++)
printf ("%02x:", mac[i]);
printf ("%02x\n", mac[5]);
}
void dump_eeprom (struct eth_device *dev)
{
int j, k;
printf ("IOS2-0 ");
for (j = 0; j < 8; j++) {
printf ("%03x ", j);
}
printf ("\n");
for (k = 0; k < 4; k++) {
if (k == 0)
printf ("CONFIG ");
if (k == 1)
printf ("BASE ");
if ((k == 2) || (k == 3))
printf (" ");
for (j = 0; j < 0x20; j += 4) {
printf ("%02x:%04x ", j + k,
read_eeprom_reg (dev, j + k));
}
printf ("\n");
}
for (j = 0x20; j < 0x40; j++) {
if ((j & 0x07) == 0)
printf ("\n");
printf ("%02x:%04x ", j, read_eeprom_reg (dev, j));
}
printf ("\n");
}
int read_eeprom_reg (struct eth_device *dev, int reg)
{
int timeout;
SMC_SELECT_BANK (dev, 2);
SMC_outw (dev, reg, PTR_REG);
SMC_SELECT_BANK (dev, 1);
SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
CTL_RELOAD, CTL_REG);
timeout = 100;
while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay (100);
if (timeout == 0) {
printf ("Timeout Reading EEPROM register %02x\n", reg);
return 0;
}
return SMC_inw (dev, GP_REG);
}
int write_eeprom_reg (struct eth_device *dev, int value, int reg)
{
int timeout;
SMC_SELECT_BANK (dev, 2);
SMC_outw (dev, reg, PTR_REG);
SMC_SELECT_BANK (dev, 1);
SMC_outw (dev, value, GP_REG);
SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT |
CTL_STORE, CTL_REG);
timeout = 100;
while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
if (timeout == 0) {
printf ("Timeout Writing EEPROM register %02x\n", reg);
return 0;
}
return 1;
}
void dump_reg (struct eth_device *dev)
{
int i, j;
printf (" ");
for (j = 0; j < 4; j++) {
printf ("Bank%i ", j);
}
printf ("\n");
for (i = 0; i < 0xF; i += 2) {
printf ("%02x ", i);
for (j = 0; j < 4; j++) {
SMC_SELECT_BANK (dev, j);
printf ("%04x ", SMC_inw (dev, i));
}
printf ("\n");
}
}
|
1001-study-uboot
|
examples/standalone/smc91111_eeprom.c
|
C
|
gpl3
| 8,097
|
#include <common.h>
#include <exports.h>
#ifndef GCC_VERSION
#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__)
#endif /* GCC_VERSION */
#if defined(CONFIG_X86)
/*
* x86 does not have a dedicated register to store the pointer to
* the global_data. Thus the jump table address is stored in a
* global variable, but such approach does not allow for execution
* from flash memory. The global_data address is passed as argv[-1]
* to the application program.
*/
static void **jt;
gd_t *global_data;
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" movl %0, %%eax\n" \
" movl jt, %%ecx\n" \
" jmp *(%%ecx, %%eax)\n" \
: : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx");
#elif defined(CONFIG_PPC)
/*
* r2 holds the pointer to the global_data, r11 is a call-clobbered
* register
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" lwz %%r11, %0(%%r2)\n" \
" lwz %%r11, %1(%%r11)\n" \
" mtctr %%r11\n" \
" bctr\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r11");
#elif defined(CONFIG_ARM)
/*
* r8 holds the pointer to the global_data, ip is a call-clobbered
* register
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" ldr ip, [r8, %0]\n" \
" ldr pc, [ip, %1]\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "ip");
#elif defined(CONFIG_MIPS)
/*
* k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
* clobbered register that is also used to set gp ($26). Note that the
* jr instruction also executes the instruction immediately following
* it; however, GCC/mips generates an additional `nop' after each asm
* statement
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" lw $25, %0($26)\n" \
" lw $25, %1($25)\n" \
" jr $25\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "t9");
#elif defined(CONFIG_NIOS2)
/*
* gp holds the pointer to the global_data, r8 is call-clobbered
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" movhi r8, %%hi(%0)\n" \
" ori r8, r0, %%lo(%0)\n" \
" add r8, r8, gp\n" \
" ldw r8, 0(r8)\n" \
" ldw r8, %1(r8)\n" \
" jmp r8\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "gp");
#elif defined(CONFIG_M68K)
/*
* d7 holds the pointer to the global_data, a0 is a call-clobbered
* register
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" move.l %%d7, %%a0\n" \
" adda.l %0, %%a0\n" \
" move.l (%%a0), %%a0\n" \
" adda.l %1, %%a0\n" \
" move.l (%%a0), %%a0\n" \
" jmp (%%a0)\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "a0");
#elif defined(CONFIG_MICROBLAZE)
/*
* r31 holds the pointer to the global_data. r5 is a call-clobbered.
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" lwi r5, r31, %0\n" \
" lwi r5, r5, %1\n" \
" bra r5\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5");
#elif defined(CONFIG_BLACKFIN)
/*
* P3 holds the pointer to the global_data, P0 is a call-clobbered
* register
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl _" #x "\n_" \
#x ":\n" \
" P0 = [P3 + %0]\n" \
" P0 = [P0 + %1]\n" \
" JUMP (P0)\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0");
#elif defined(CONFIG_AVR32)
/*
* r6 holds the pointer to the global_data. r8 is call clobbered.
*/
#define EXPORT_FUNC(x) \
asm volatile( \
" .globl\t" #x "\n" \
#x ":\n" \
" ld.w r8, r6[%0]\n" \
" ld.w pc, r8[%1]\n" \
: \
: "i"(offsetof(gd_t, jt)), "i"(XF_ ##x) \
: "r8");
#elif defined(CONFIG_SH)
/*
* r13 holds the pointer to the global_data. r1 is a call clobbered.
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .align 2\n" \
" .globl " #x "\n" \
#x ":\n" \
" mov r13, r1\n" \
" add %0, r1\n" \
" mov.l @r1, r2\n" \
" add %1, r2\n" \
" mov.l @r2, r1\n" \
" jmp @r1\n" \
" nop\n" \
" nop\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1", "r2");
#elif defined(CONFIG_SPARC)
/*
* g7 holds the pointer to the global_data. g1 is call clobbered.
*/
#define EXPORT_FUNC(x) \
asm volatile( \
" .globl\t" #x "\n" \
#x ":\n" \
" set %0, %%g1\n" \
" or %%g1, %%g7, %%g1\n" \
" ld [%%g1], %%g1\n" \
" ld [%%g1 + %1], %%g1\n" \
" jmp %%g1\n" \
" nop\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" );
#elif defined(CONFIG_NDS32)
/*
* r16 holds the pointer to the global_data. gp is call clobbered.
* not support reduced register (16 GPR).
*/
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl " #x "\n" \
#x ":\n" \
" lwi $r16, [$gp + (%0)]\n" \
" lwi $r16, [$r16 + (%1)]\n" \
" jr $r16\n" \
: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "$r16");
#else
/*" addi $sp, $sp, -24\n" \
" br $r16\n" \*/
#error stubs definition missing for this architecture
#endif
/* This function is necessary to prevent the compiler from
* generating prologue/epilogue, preparing stack frame etc.
* The stub functions are special, they do not use the stack
* frame passed to them, but pass it intact to the actual
* implementation. On the other hand, asm() statements with
* arguments can be used only inside the functions (gcc limitation)
*/
#if GCC_VERSION < 3004
static
#endif /* GCC_VERSION */
void __attribute__((unused)) dummy(void)
{
#include <_exports.h>
}
extern unsigned long __bss_start, _end;
void app_startup(char * const *argv)
{
unsigned char * cp = (unsigned char *) &__bss_start;
/* Zero out BSS */
while (cp < (unsigned char *)&_end) {
*cp++ = 0;
}
#if defined(CONFIG_X86)
/* x86 does not have a dedicated register for passing global_data */
global_data = (gd_t *)argv[-1];
jt = global_data->jt;
#endif
}
#undef EXPORT_FUNC
|
1001-study-uboot
|
examples/standalone/stubs.c
|
C
|
gpl3
| 5,941
|
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <commproc.h>
#include <mpc8xx_irq.h>
#include <exports.h>
DECLARE_GLOBAL_DATA_PTR;
#undef DEBUG
#define TIMER_PERIOD 1000000 /* 1 second clock */
static void timer_handler (void *arg);
/* Access functions for the Machine State Register */
static __inline__ unsigned long get_msr(void)
{
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr;
}
static __inline__ void set_msr(unsigned long msr)
{
asm volatile("mtmsr %0" : : "r" (msr));
}
/*
* Definitions to access the CPM Timer registers
* See 8xx_immap.h for Internal Memory Map layout,
* and commproc.h for CPM Interrupt vectors (aka "IRQ"s)
*/
typedef struct tid_8xx_cpmtimer_s {
int cpm_vec; /* CPM Interrupt Vector for this timer */
ushort *tgcrp; /* Pointer to Timer Global Config Reg. */
ushort *tmrp; /* Pointer to Timer Mode Register */
ushort *trrp; /* Pointer to Timer Reference Register */
ushort *tcrp; /* Pointer to Timer Capture Register */
ushort *tcnp; /* Pointer to Timer Counter Register */
ushort *terp; /* Pointer to Timer Event Register */
} tid_8xx_cpmtimer_t;
#ifndef CLOCKRATE
# define CLOCKRATE 64
#endif
#define CPMT_CLOCK_DIV 16
#define CPMT_MAX_PRESCALER 256
#define CPMT_MAX_REFERENCE 65535 /* max. unsigned short */
#define CPMT_MAX_TICKS (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER)
#define CPMT_MAX_TICKS_WITH_DIV (CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER * CPMT_CLOCK_DIV)
#define CPMT_MAX_INTERVAL (CPMT_MAX_TICKS_WITH_DIV / CLOCKRATE)
/* For now: always use max. prescaler value */
#define CPMT_PRESCALER (CPMT_MAX_PRESCALER)
/* CPM Timer Event Register Bits */
#define CPMT_EVENT_CAP 0x0001 /* Capture Event */
#define CPMT_EVENT_REF 0x0002 /* Reference Counter Event */
/* CPM Timer Global Config Register */
#define CPMT_GCR_RST 0x0001 /* Reset Timer */
#define CPMT_GCR_STP 0x0002 /* Stop Timer */
#define CPMT_GCR_FRZ 0x0004 /* Freeze Timer */
#define CPMT_GCR_GM_CAS 0x0008 /* Gate Mode / Cascade Timers */
#define CPMT_GCR_MASK (CPMT_GCR_RST|CPMT_GCR_STP|CPMT_GCR_FRZ|CPMT_GCR_GM_CAS)
/* CPM Timer Mode register */
#define CPMT_MR_GE 0x0001 /* Gate Enable */
#define CPMT_MR_ICLK_CASC 0x0000 /* Clock internally cascaded */
#define CPMT_MR_ICLK_CLK 0x0002 /* Clock = system clock */
#define CPMT_MR_ICLK_CLKDIV 0x0004 /* Clock = system clock / 16 */
#define CPMT_MR_ICLK_TIN 0x0006 /* Clock = TINx signal */
#define CPMT_MR_FRR 0x0008 /* Free Run / Restart */
#define CPMT_MR_ORI 0x0010 /* Out. Reference Interrupt En. */
#define CPMT_MR_OM 0x0020 /* Output Mode */
#define CPMT_MR_CE_DIS 0x0000 /* Capture/Interrupt disabled */
#define CPMT_MR_CE_RISE 0x0040 /* Capt./Interr. on rising TIN */
#define CPMT_MR_CE_FALL 0x0080 /* Capt./Interr. on falling TIN */
#define CPMT_MR_CE_ANY 0x00C0 /* Capt./Interr. on any TIN edge*/
/*
* which CPM timer to use - index starts at 0 (= timer 1)
*/
#define TID_TIMER_ID 0 /* use CPM timer 1 */
void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval);
static const char usage[] = "\n[q, b, e, ?] ";
int timer (int argc, char * const argv[])
{
cpmtimer8xx_t *cpmtimerp; /* Pointer to the CPM Timer structure */
tid_8xx_cpmtimer_t hw;
tid_8xx_cpmtimer_t *hwp = &hw;
int c;
int running;
app_startup(argv);
/* Pointer to CPM Timer structure */
cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer;
printf ("TIMERS=0x%x\n", (unsigned) cpmtimerp);
/* Initialize pointers depending on which timer we use */
switch (TID_TIMER_ID) {
case 0:
hwp->tmrp = &(cpmtimerp->cpmt_tmr1);
hwp->trrp = &(cpmtimerp->cpmt_trr1);
hwp->tcrp = &(cpmtimerp->cpmt_tcr1);
hwp->tcnp = &(cpmtimerp->cpmt_tcn1);
hwp->terp = &(cpmtimerp->cpmt_ter1);
hwp->cpm_vec = CPMVEC_TIMER1;
break;
case 1:
hwp->tmrp = &(cpmtimerp->cpmt_tmr2);
hwp->trrp = &(cpmtimerp->cpmt_trr2);
hwp->tcrp = &(cpmtimerp->cpmt_tcr2);
hwp->tcnp = &(cpmtimerp->cpmt_tcn2);
hwp->terp = &(cpmtimerp->cpmt_ter2);
hwp->cpm_vec = CPMVEC_TIMER2;
break;
case 2:
hwp->tmrp = &(cpmtimerp->cpmt_tmr3);
hwp->trrp = &(cpmtimerp->cpmt_trr3);
hwp->tcrp = &(cpmtimerp->cpmt_tcr3);
hwp->tcnp = &(cpmtimerp->cpmt_tcn3);
hwp->terp = &(cpmtimerp->cpmt_ter3);
hwp->cpm_vec = CPMVEC_TIMER3;
break;
case 3:
hwp->tmrp = &(cpmtimerp->cpmt_tmr4);
hwp->trrp = &(cpmtimerp->cpmt_trr4);
hwp->tcrp = &(cpmtimerp->cpmt_tcr4);
hwp->tcnp = &(cpmtimerp->cpmt_tcn4);
hwp->terp = &(cpmtimerp->cpmt_ter4);
hwp->cpm_vec = CPMVEC_TIMER4;
break;
}
hwp->tgcrp = &cpmtimerp->cpmt_tgcr;
printf ("Using timer %d\n"
"tgcr @ 0x%x, tmr @ 0x%x, trr @ 0x%x,"
" tcr @ 0x%x, tcn @ 0x%x, ter @ 0x%x\n",
TID_TIMER_ID + 1,
(unsigned) hwp->tgcrp,
(unsigned) hwp->tmrp,
(unsigned) hwp->trrp,
(unsigned) hwp->tcrp,
(unsigned) hwp->tcnp,
(unsigned) hwp->terp
);
/* reset timer */
*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
/* clear all events */
*hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF);
puts(usage);
running = 0;
while ((c = getc()) != 'q') {
if (c == 'b') {
setPeriod (hwp, TIMER_PERIOD); /* Set period and start ticking */
/* Install interrupt handler (enable timer in CIMR) */
install_hdlr (hwp->cpm_vec, timer_handler, hwp);
printf ("Enabling timer\n");
/* enable timer */
*hwp->tgcrp |= (CPMT_GCR_RST << TID_TIMER_ID);
running = 1;
#ifdef DEBUG
printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
*hwp->tcrp, *hwp->tcnp, *hwp->terp
);
#endif
} else if (c == 'e') {
printf ("Stopping timer\n");
*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
running = 0;
#ifdef DEBUG
printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
*hwp->tcrp, *hwp->tcnp, *hwp->terp
);
#endif
/* Uninstall interrupt handler */
free_hdlr (hwp->cpm_vec);
} else if (c == '?') {
#ifdef DEBUG
cpic8xx_t *cpm_icp = &((immap_t *) gd->bd->bi_immr_base)->im_cpic;
sysconf8xx_t *siup = &((immap_t *) gd->bd->bi_immr_base)->im_siu_conf;
#endif
printf ("\ntgcr=0x%x, tmr=0x%x, trr=0x%x,"
" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
*hwp->tcrp, *hwp->tcnp, *hwp->terp
);
#ifdef DEBUG
printf ("SIUMCR=0x%08lx, SYPCR=0x%08lx,"
" SIMASK=0x%08lx, SIPEND=0x%08lx\n",
siup->sc_siumcr,
siup->sc_sypcr,
siup->sc_simask,
siup->sc_sipend
);
printf ("CIMR=0x%08lx, CICR=0x%08lx, CIPR=0x%08lx\n",
cpm_icp->cpic_cimr,
cpm_icp->cpic_cicr,
cpm_icp->cpic_cipr
);
#endif
} else {
printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n");
}
puts(usage);
}
if (running) {
printf ("Stopping timer\n");
*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
free_hdlr (hwp->cpm_vec);
}
return (0);
}
/* Set period in microseconds and start.
* Truncate to maximum period if more than this is requested - but warn about it.
*/
void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval)
{
unsigned short prescaler;
unsigned long ticks;
printf ("Set interval %ld us\n", interval);
/* Warn if requesting longer period than possible */
if (interval > CPMT_MAX_INTERVAL) {
printf ("Truncate interval %ld to maximum (%d)\n",
interval, CPMT_MAX_INTERVAL);
interval = CPMT_MAX_INTERVAL;
}
/*
* Check if we want to use clock divider:
* Since the reference counter can be incremented only in integer steps,
* we try to keep it as big as possible to allow the resulting period to be
* as precise as possible.
*/
/* prescaler, enable interrupt, restart after ref count is reached */
prescaler = (ushort) ((CPMT_PRESCALER - 1) << 8) |
CPMT_MR_ORI |
CPMT_MR_FRR;
ticks = ((ulong) CLOCKRATE * interval);
if (ticks > CPMT_MAX_TICKS) {
ticks /= CPMT_CLOCK_DIV;
prescaler |= CPMT_MR_ICLK_CLKDIV; /* use system clock divided by 16 */
} else {
prescaler |= CPMT_MR_ICLK_CLK; /* use system clock without divider */
}
#ifdef DEBUG
printf ("clock/%d, prescale factor %d, reference %ld, ticks %ld\n",
(ticks > CPMT_MAX_TICKS) ? CPMT_CLOCK_DIV : 1,
CPMT_PRESCALER,
(ticks / CPMT_PRESCALER),
ticks
);
#endif
/* set prescaler register */
*hwp->tmrp = prescaler;
/* clear timer counter */
*hwp->tcnp = 0;
/* set reference register */
*hwp->trrp = (unsigned short) (ticks / CPMT_PRESCALER);
#ifdef DEBUG
printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
*hwp->tcrp, *hwp->tcnp, *hwp->terp
);
#endif
}
/*
* Handler for CPMVEC_TIMER1 interrupt
*/
static
void timer_handler (void *arg)
{
tid_8xx_cpmtimer_t *hwp = (tid_8xx_cpmtimer_t *)arg;
/* printf ("** TER1=%04x ** ", *hwp->terp); */
/* just for demonstration */
printf (".");
/* clear all possible events: Ref. and Cap. */
*hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF);
}
|
1001-study-uboot
|
examples/standalone/timer.c
|
C
|
gpl3
| 9,830
|
/* setjmp for PowerPC.
Copyright (C) 1995, 1996, 1997, 1999, 2000 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
#include <ppc_asm.tmpl>
# define JB_GPR1 0 /* Also known as the stack pointer */
# define JB_GPR2 1
# define JB_LR 2 /* The address we will return to */
# define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18 in total */
# define JB_CR 21 /* Condition code registers. */
# define JB_FPRS 22 /* FPRs 14 through 31 are saved, 18*2 words total */
# define JB_SIZE (58*4)
#define FP(x...) x
.globl setctxsp;
setctxsp:
mr r1, r3
blr
.globl ppc_setjmp;
ppc_setjmp:
stw r1,(JB_GPR1*4)(3)
mflr r0
stw r2,(JB_GPR2*4)(3)
stw r14,((JB_GPRS+0)*4)(3)
FP( stfd 14,((JB_FPRS+0*2)*4)(3))
stw r0,(JB_LR*4)(3)
stw r15,((JB_GPRS+1)*4)(3)
FP( stfd 15,((JB_FPRS+1*2)*4)(3))
mfcr r0
stw r16,((JB_GPRS+2)*4)(3)
FP( stfd 16,((JB_FPRS+2*2)*4)(3))
stw r0,(JB_CR*4)(3)
stw r17,((JB_GPRS+3)*4)(3)
FP( stfd 17,((JB_FPRS+3*2)*4)(3))
stw r18,((JB_GPRS+4)*4)(3)
FP( stfd 18,((JB_FPRS+4*2)*4)(3))
stw r19,((JB_GPRS+5)*4)(3)
FP( stfd 19,((JB_FPRS+5*2)*4)(3))
stw r20,((JB_GPRS+6)*4)(3)
FP( stfd 20,((JB_FPRS+6*2)*4)(3))
stw r21,((JB_GPRS+7)*4)(3)
FP( stfd 21,((JB_FPRS+7*2)*4)(3))
stw r22,((JB_GPRS+8)*4)(3)
FP( stfd 22,((JB_FPRS+8*2)*4)(3))
stw r23,((JB_GPRS+9)*4)(3)
FP( stfd 23,((JB_FPRS+9*2)*4)(3))
stw r24,((JB_GPRS+10)*4)(3)
FP( stfd 24,((JB_FPRS+10*2)*4)(3))
stw r25,((JB_GPRS+11)*4)(3)
FP( stfd 25,((JB_FPRS+11*2)*4)(3))
stw r26,((JB_GPRS+12)*4)(3)
FP( stfd 26,((JB_FPRS+12*2)*4)(3))
stw r27,((JB_GPRS+13)*4)(3)
FP( stfd 27,((JB_FPRS+13*2)*4)(3))
stw r28,((JB_GPRS+14)*4)(3)
FP( stfd 28,((JB_FPRS+14*2)*4)(3))
stw r29,((JB_GPRS+15)*4)(3)
FP( stfd 29,((JB_FPRS+15*2)*4)(3))
stw r30,((JB_GPRS+16)*4)(3)
FP( stfd 30,((JB_FPRS+16*2)*4)(3))
stw r31,((JB_GPRS+17)*4)(3)
FP( stfd 31,((JB_FPRS+17*2)*4)(3))
li 3, 0
blr
|
1001-study-uboot
|
examples/standalone/ppc_setjmp.S
|
Unix Assembly
|
gpl3
| 2,669
|
/* The dpalloc function used and implemented in this file was derieved
* from PPCBoot/U-Boot file "arch/powerpc/cpu/mpc8260/commproc.c".
*/
/* Author: Arun Dharankar <ADharankar@ATTBI.Com>
* This example is meant to only demonstrate how the IDMA could be used.
*/
/*
* This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
* copyright notice:
*
* General Purpose functions for the global management of the
* 8260 Communication Processor Module.
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
* 2.3.99 Updates
*
* In addition to the individual control of the communication
* channels, there are a few functions that globally affect the
* communication processor.
*
* Buffer descriptors must be allocated from the dual ported memory
* space. The allocator for that is here. When the communication
* process is reset, we reclaim the memory available. There is
* currently no deallocator for this memory.
*/
#include <common.h>
#include <exports.h>
DECLARE_GLOBAL_DATA_PTR;
#define STANDALONE
#ifndef STANDALONE /* Linked into/Part of PPCBoot */
#include <command.h>
#include <watchdog.h>
#else /* Standalone app of PPCBoot */
#define WATCHDOG_RESET() { \
*(ushort *)(CONFIG_SYS_IMMR + 0x1000E) = 0x556c; \
*(ushort *)(CONFIG_SYS_IMMR + 0x1000E) = 0xaa39; \
}
#endif /* STANDALONE */
static int debug = 1;
#define DEBUG(fmt, args...) { \
if(debug != 0) { \
printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__); \
printf(fmt, ##args); \
} \
}
#define CPM_CR_IDMA1_SBLOCK (0x14)
#define CPM_CR_IDMA2_SBLOCK (0x15)
#define CPM_CR_IDMA3_SBLOCK (0x16)
#define CPM_CR_IDMA4_SBLOCK (0x17)
#define CPM_CR_IDMA1_PAGE (0x07)
#define CPM_CR_IDMA2_PAGE (0x08)
#define CPM_CR_IDMA3_PAGE (0x09)
#define CPM_CR_IDMA4_PAGE (0x0a)
#define PROFF_IDMA1_BASE ((uint)0x87fe)
#define PROFF_IDMA2_BASE ((uint)0x88fe)
#define PROFF_IDMA3_BASE ((uint)0x89fe)
#define PROFF_IDMA4_BASE ((uint)0x8afe)
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_FLG ((ushort)0x0001)
#define mk_cr_cmd(PG, SBC, MCN, OP) \
((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
#pragma pack(1)
typedef struct ibdbits {
unsigned b_valid:1;
unsigned b_resv1:1;
unsigned b_wrap:1;
unsigned b_interrupt:1;
unsigned b_last:1;
unsigned b_resv2:1;
unsigned b_cm:1;
unsigned b_resv3:2;
unsigned b_sdn:1;
unsigned b_ddn:1;
unsigned b_dgbl:1;
unsigned b_dbo:2;
unsigned b_resv4:1;
unsigned b_ddtb:1;
unsigned b_resv5:2;
unsigned b_sgbl:1;
unsigned b_sbo:2;
unsigned b_resv6:1;
unsigned b_sdtb:1;
unsigned b_resv7:9;
} ibdbits_t;
#pragma pack(1)
typedef union ibdbitsu {
ibdbits_t b;
uint i;
} ibdbitsu_t;
#pragma pack(1)
typedef struct idma_buf_desc {
ibdbitsu_t ibd_bits; /* Status and Control */
uint ibd_datlen; /* Data length in buffer */
uint ibd_sbuf; /* Source buffer addr in host mem */
uint ibd_dbuf; /* Destination buffer addr in host mem */
} ibd_t;
#pragma pack(1)
typedef struct dcmbits {
unsigned b_fb:1;
unsigned b_lp:1;
unsigned b_resv1:3;
unsigned b_tc2:1;
unsigned b_resv2:1;
unsigned b_wrap:3;
unsigned b_sinc:1;
unsigned b_dinc:1;
unsigned b_erm:1;
unsigned b_dt:1;
unsigned b_sd:2;
} dcmbits_t;
#pragma pack(1)
typedef union dcmbitsu {
dcmbits_t b;
ushort i;
} dcmbitsu_t;
#pragma pack(1)
typedef struct pram_idma {
ushort pi_ibase;
dcmbitsu_t pi_dcmbits;
ushort pi_ibdptr;
ushort pi_dprbuf;
ushort pi_bufinv; /* internal to CPM */
ushort pi_ssmax;
ushort pi_dprinptr; /* internal to CPM */
ushort pi_sts;
ushort pi_dproutptr; /* internal to CPM */
ushort pi_seob;
ushort pi_deob;
ushort pi_dts;
ushort pi_retadd;
ushort pi_resv1; /* internal to CPM */
uint pi_bdcnt;
uint pi_sptr;
uint pi_dptr;
uint pi_istate;
} pram_idma_t;
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ibd_t *bdf;
volatile pram_idma_t *piptr;
volatile int dmadone;
volatile int *dmadonep = &dmadone;
void dmadone_handler (void *);
int idma_init (void);
void idma_start (int, int, int, uint, uint, int);
uint dpalloc (uint, uint);
uint dpinit_done = 0;
#ifdef STANDALONE
int ctrlc (void)
{
if (tstc()) {
switch (getc ()) {
case 0x03: /* ^C - Control C */
return 1;
default:
break;
}
}
return 0;
}
void * memset(void * s,int c,size_t count)
{
char *xs = (char *) s;
while (count--)
*xs++ = c;
return s;
}
int memcmp(const void * cs,const void * ct,size_t count)
{
const unsigned char *su1, *su2;
int res = 0;
for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--)
if ((res = *su1 - *su2) != 0)
break;
return res;
}
#endif /* STANDALONE */
#ifdef STANDALONE
int mem_to_mem_idma2intr (int argc, char * const argv[])
#else
int do_idma (bd_t * bd, int argc, char * const argv[])
#endif /* STANDALONE */
{
int i;
app_startup(argv);
dpinit_done = 0;
idma_init ();
DEBUG ("Installing dma handler\n");
install_hdlr (7, dmadone_handler, (void *) bdf);
memset ((void *) 0x100000, 'a', 512);
memset ((void *) 0x200000, 'b', 512);
for (i = 0; i < 32; i++) {
printf ("Startin IDMA, iteration=%d\n", i);
idma_start (1, 1, 512, 0x100000, 0x200000, 3);
}
DEBUG ("Uninstalling dma handler\n");
free_hdlr (7);
return 0;
}
void
idma_start (int sinc, int dinc, int sz, uint sbuf, uint dbuf, int ttype)
{
/* ttype is for M-M, M-P, P-M or P-P: not used for now */
piptr->pi_istate = 0; /* manual says: clear it before every START_IDMA */
piptr->pi_dcmbits.b.b_resv1 = 0;
if (sinc == 1)
piptr->pi_dcmbits.b.b_sinc = 1;
else
piptr->pi_dcmbits.b.b_sinc = 0;
if (dinc == 1)
piptr->pi_dcmbits.b.b_dinc = 1;
else
piptr->pi_dcmbits.b.b_dinc = 0;
piptr->pi_dcmbits.b.b_erm = 0;
piptr->pi_dcmbits.b.b_sd = 0x00; /* M-M */
bdf->ibd_sbuf = sbuf;
bdf->ibd_dbuf = dbuf;
bdf->ibd_bits.b.b_cm = 0;
bdf->ibd_bits.b.b_interrupt = 1;
bdf->ibd_bits.b.b_wrap = 1;
bdf->ibd_bits.b.b_last = 1;
bdf->ibd_bits.b.b_sdn = 0;
bdf->ibd_bits.b.b_ddn = 0;
bdf->ibd_bits.b.b_dgbl = 0;
bdf->ibd_bits.b.b_ddtb = 0;
bdf->ibd_bits.b.b_sgbl = 0;
bdf->ibd_bits.b.b_sdtb = 0;
bdf->ibd_bits.b.b_dbo = 1;
bdf->ibd_bits.b.b_sbo = 1;
bdf->ibd_bits.b.b_valid = 1;
bdf->ibd_datlen = 512;
*dmadonep = 0;
immap->im_sdma.sdma_idmr2 = (uchar) 0xf;
immap->im_cpm.cp_cpcr = mk_cr_cmd (CPM_CR_IDMA2_PAGE,
CPM_CR_IDMA2_SBLOCK, 0x0,
0x9) | 0x00010000;
while (*dmadonep != 1) {
if (ctrlc ()) {
DEBUG ("\nInterrupted waiting for DMA interrupt.\n");
goto done;
}
printf ("Waiting for DMA interrupt (dmadone=%d b_valid = %d)...\n",
dmadone, bdf->ibd_bits.b.b_valid);
udelay (1000000);
}
printf ("DMA complete notification received!\n");
done:
DEBUG ("memcmp(0x%08x, 0x%08x, 512) = %d\n",
sbuf, dbuf, memcmp ((void *) sbuf, (void *) dbuf, 512));
return;
}
#define MAX_INT_BUFSZ 64
#define DCM_WRAP 0 /* MUST be consistant with MAX_INT_BUFSZ */
int idma_init (void)
{
uint memaddr;
immap->im_cpm.cp_rccr &= ~0x00F3FFFF;
immap->im_cpm.cp_rccr |= 0x00A00A00;
memaddr = dpalloc (sizeof (pram_idma_t), 64);
*(volatile ushort *) &immap->im_dprambase[PROFF_IDMA2_BASE] = memaddr;
piptr = (volatile pram_idma_t *) ((uint) (immap) + memaddr);
piptr->pi_resv1 = 0; /* manual says: clear it */
piptr->pi_dcmbits.b.b_fb = 0;
piptr->pi_dcmbits.b.b_lp = 1;
piptr->pi_dcmbits.b.b_erm = 0;
piptr->pi_dcmbits.b.b_dt = 0;
memaddr = (uint) dpalloc (sizeof (ibd_t), 64);
piptr->pi_ibase = piptr->pi_ibdptr = (volatile short) memaddr;
bdf = (volatile ibd_t *) ((uint) (immap) + memaddr);
bdf->ibd_bits.b.b_valid = 0;
memaddr = (uint) dpalloc (64, 64);
piptr->pi_dprbuf = (volatile ushort) memaddr;
piptr->pi_dcmbits.b.b_wrap = 4;
piptr->pi_ssmax = 32;
piptr->pi_sts = piptr->pi_ssmax;
piptr->pi_dts = piptr->pi_ssmax;
return 1;
}
void dmadone_handler (void *arg)
{
immap->im_sdma.sdma_idmr2 = (uchar) 0x0;
*dmadonep = 1;
return;
}
static uint dpbase = 0;
uint dpalloc (uint size, uint align)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
uint retloc;
uint align_mask, off;
uint savebase;
/* Pointer to initial global data area */
if (dpinit_done == 0) {
dpbase = gd->dp_alloc_base;
dpinit_done = 1;
}
align_mask = align - 1;
savebase = dpbase;
if ((off = (dpbase & align_mask)) != 0)
dpbase += (align - off);
if ((off = size & align_mask) != 0)
size += align - off;
if ((dpbase + size) >= gd->dp_alloc_top) {
dpbase = savebase;
printf ("dpalloc: ran out of dual port ram!");
return 0;
}
retloc = dpbase;
dpbase += size;
memset ((void *) &immr->im_dprambase[retloc], 0, size);
return (retloc);
}
|
1001-study-uboot
|
examples/standalone/mem_to_mem_idma2intr.c
|
C
|
gpl3
| 8,682
|
/*
* Copyright 1998-2001 by Donald Becker.
* This software may be used and distributed according to the terms of
* the GNU General Public License (GPL), incorporated herein by reference.
* Contact the author for use under other terms.
*
* This program must be compiled with "-O"!
* See the bottom of this file for the suggested compile-command.
*
* The author may be reached as becker@scyld.com, or C/O
* Scyld Computing Corporation
* 410 Severn Ave., Suite 210
* Annapolis MD 21403
*
* Common-sense licensing statement: Using any portion of this program in
* your own program means that you must give credit to the original author
* and release the resulting code under the GPL.
*/
/* avoid unnecessary memcpy function */
#define _PPC_STRING_H_
#include <common.h>
#include <exports.h>
static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr);
int eepro100_eeprom(int argc, char * const argv[])
{
int ret = 0;
unsigned char hwaddr1[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x05 };
unsigned char hwaddr2[6] = { 0x00, 0x00, 0x02, 0x03, 0x04, 0x06 };
app_startup(argv);
#if defined(CONFIG_OXC)
ret |= reset_eeprom(0x80000000, hwaddr1);
ret |= reset_eeprom(0x81000000, hwaddr2);
#endif
return ret;
}
/* Default EEPROM for i82559 */
static unsigned short default_eeprom[64] = {
0x0100, 0x0302, 0x0504, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0x40c0, 0x0000, 0x0000, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff
};
static unsigned short eeprom[256];
static int eeprom_size = 64;
static int eeprom_addr_size = 6;
static int debug = 0;
static inline unsigned short swap16(unsigned short x)
{
return (((x & 0xff) << 8) | ((x & 0xff00) >> 8));
}
static inline void outw(short data, long addr)
{
*(volatile short *)(addr) = swap16(data);
}
static inline short inw(long addr)
{
return swap16(*(volatile short *)(addr));
}
void *memcpy(void *dst, const void *src, unsigned int len)
{
char *ret = dst;
while (len-- > 0) {
*ret++ = *((char *)src);
src++;
}
return (void *)ret;
}
/* The EEPROM commands include the alway-set leading bit. */
#define EE_WRITE_CMD (5)
#define EE_READ_CMD (6)
#define EE_ERASE_CMD (7)
/* Serial EEPROM section. */
#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
#define EE_CS 0x02 /* EEPROM chip select. */
#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
#define EE_ENB (0x4800 | EE_CS)
#define EE_WRITE_0 0x4802
#define EE_WRITE_1 0x4806
#define EE_OFFSET 14
/* Delay between EEPROM clock transitions. */
#define eeprom_delay(ee_addr) inw(ee_addr)
/* Wait for the EEPROM to finish the previous operation. */
static int eeprom_busy_poll(long ee_ioaddr)
{
int i;
outw(EE_ENB, ee_ioaddr);
for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
if (inw(ee_ioaddr) & EE_DATA_READ)
break;
return i;
}
/* This executes a generic EEPROM command, typically a write or write enable.
It returns the data output from the EEPROM, and thus may also be used for
reads. */
static int do_eeprom_cmd(long ioaddr, int cmd, int cmd_len)
{
unsigned retval = 0;
long ee_addr = ioaddr + EE_OFFSET;
if (debug > 1)
printf(" EEPROM op 0x%x: ", cmd);
outw(EE_ENB | EE_SHIFT_CLK, ee_addr);
/* Shift the command bits out. */
do {
short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
outw(dataval, ee_addr);
eeprom_delay(ee_addr);
if (debug > 2)
printf("%X", inw(ee_addr) & 15);
outw(dataval | EE_SHIFT_CLK, ee_addr);
eeprom_delay(ee_addr);
retval = (retval << 1) | ((inw(ee_addr) & EE_DATA_READ) ? 1 : 0);
} while (--cmd_len >= 0);
#if 0
outw(EE_ENB, ee_addr);
#endif
/* Terminate the EEPROM access. */
outw(EE_ENB & ~EE_CS, ee_addr);
if (debug > 1)
printf(" EEPROM result is 0x%5.5x.\n", retval);
return retval;
}
static int read_eeprom(long ioaddr, int location, int addr_len)
{
return do_eeprom_cmd(ioaddr, ((EE_READ_CMD << addr_len) | location)
<< 16 , 3 + addr_len + 16) & 0xffff;
}
static void write_eeprom(long ioaddr, int index, int value, int addr_len)
{
long ee_ioaddr = ioaddr + EE_OFFSET;
int i;
/* Poll for previous op finished. */
eeprom_busy_poll(ee_ioaddr); /* Typical 0 ticks */
/* Enable programming modes. */
do_eeprom_cmd(ioaddr, (0x4f << (addr_len-4)), 3 + addr_len);
/* Do the actual write. */
do_eeprom_cmd(ioaddr,
(((EE_WRITE_CMD<<addr_len) | index)<<16) | (value & 0xffff),
3 + addr_len + 16);
/* Poll for write finished. */
i = eeprom_busy_poll(ee_ioaddr); /* Typical 2000 ticks */
if (debug)
printf(" Write finished after %d ticks.\n", i);
/* Disable programming. This command is not instantaneous, so we check
for busy before the next op. */
do_eeprom_cmd(ioaddr, (0x40 << (addr_len-4)), 3 + addr_len);
eeprom_busy_poll(ee_ioaddr);
}
static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr)
{
unsigned short checksum = 0;
int size_test;
int i;
printf("Resetting i82559 EEPROM @ 0x%08lX ... ", ioaddr);
size_test = do_eeprom_cmd(ioaddr, (EE_READ_CMD << 8) << 16, 27);
eeprom_addr_size = (size_test & 0xffe0000) == 0xffe0000 ? 8 : 6;
eeprom_size = 1 << eeprom_addr_size;
memcpy(eeprom, default_eeprom, sizeof default_eeprom);
for (i = 0; i < 3; i++)
eeprom[i] = (hwaddr[i*2+1]<<8) + hwaddr[i*2];
/* Recalculate the checksum. */
for (i = 0; i < eeprom_size - 1; i++)
checksum += eeprom[i];
eeprom[i] = 0xBABA - checksum;
for (i = 0; i < eeprom_size; i++)
write_eeprom(ioaddr, i, eeprom[i], eeprom_addr_size);
for (i = 0; i < eeprom_size; i++)
if (read_eeprom(ioaddr, i, eeprom_addr_size) != eeprom[i]) {
printf("failed\n");
return 1;
}
printf("done\n");
return 0;
}
|
1001-study-uboot
|
examples/standalone/eepro100_eeprom.c
|
C
|
gpl3
| 6,062
|
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ELF-$(ARCH) :=
ELF-$(BOARD) :=
ELF-$(CPU) :=
ELF-y := hello_world
ELF-$(CONFIG_SMC91111) += smc91111_eeprom
ELF-$(CONFIG_SMC911X) += smc911x_eeprom
ELF-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
ELF-i386 += 82559_eeprom
ELF-mpc5xxx += interrupt
ELF-mpc8xx += test_burst timer
ELF-mpc8260 += mem_to_mem_idma2intr
ELF-ppc += sched
ELF-oxc += eepro100_eeprom
#
# Some versions of make do not handle trailing white spaces properly;
# leading to build failures. The problem was found with GNU Make 3.80.
# Using 'strip' as a workaround for the problem.
#
ELF := $(strip $(ELF-y) $(ELF-$(ARCH)) $(ELF-$(BOARD)) $(ELF-$(CPU)))
SREC := $(addsuffix .srec,$(ELF))
BIN := $(addsuffix .bin,$(ELF))
COBJS := $(ELF:=.o)
LIB = $(obj)libstubs.o
LIBAOBJS-$(ARCH) :=
LIBAOBJS-$(CPU) :=
LIBAOBJS-ppc += $(ARCH)_longjmp.o $(ARCH)_setjmp.o
LIBAOBJS-mpc8xx += test_burst_lib.o
LIBAOBJS := $(LIBAOBJS-$(ARCH)) $(LIBAOBJS-$(CPU))
LIBCOBJS = stubs.o
LIBOBJS = $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS))
SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S)
OBJS := $(addprefix $(obj),$(COBJS))
ELF := $(addprefix $(obj),$(ELF))
BIN := $(addprefix $(obj),$(BIN))
SREC := $(addprefix $(obj),$(SREC))
gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
CPPFLAGS += -I..
# For PowerPC there's no need to compile standalone applications as a
# relocatable executable. The relocation data is not needed, and
# also causes the entry point of the standalone application to be
# inconsistent.
ifeq ($(ARCH),powerpc)
AFLAGS := $(filter-out $(RELFLAGS),$(AFLAGS))
CFLAGS := $(filter-out $(RELFLAGS),$(CFLAGS))
CPPFLAGS := $(filter-out $(RELFLAGS),$(CPPFLAGS))
endif
# We don't want gcc reordering functions if possible. This ensures that an
# application's entry point will be the first function in the application's
# source file.
CFLAGS_NTR := $(call cc-option,-fno-toplevel-reorder)
CFLAGS += $(CFLAGS_NTR)
all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF)
#########################################################################
$(LIB): $(obj).depend $(LIBOBJS)
$(call cmd_link_o_target, $(LIBOBJS))
$(ELF):
$(obj)%: $(obj)%.o $(LIB)
$(LD) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \
-o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \
-L$(gcclibdir) -lgcc
$(SREC):
$(obj)%.srec: $(obj)%
$(OBJCOPY) -O srec $< $@ 2>/dev/null
$(BIN):
$(obj)%.bin: $(obj)%
$(OBJCOPY) -O binary $< $@ 2>/dev/null
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
examples/standalone/Makefile
|
Makefile
|
gpl3
| 3,739
|
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEST_BURST_H
#define _TEST_BURST_H
/* Cache line size */
#define CACHE_LINE_SIZE 16
/* Binary logarithm of the cache line size */
#define LG_CACHE_LINE_SIZE 4
#ifndef __ASSEMBLY__
extern void mmu_init(void);
extern void caches_init(void);
extern void flush_dcache_range(unsigned long start, unsigned long stop);
#endif
#endif /* _TEST_BURST_H */
|
1001-study-uboot
|
examples/standalone/test_burst.h
|
C
|
gpl3
| 1,241
|
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include "test_burst.h"
.text
/*
* void mmu_init(void);
*
* This function turns the MMU on
*
* Three 8 MByte regions are mapped 1:1, uncached
* - SDRAM lower 8 MByte
* - SDRAM higher 8 MByte
* - IMMR
*/
.global mmu_init
mmu_init:
tlbia /* Invalidate all TLB entries */
li r8, 0
mtspr MI_CTR, r8 /* Set instruction control to zero */
lis r8, MD_RESETVAL@h
mtspr MD_CTR, r8 /* Set data TLB control */
/* Now map the lower 8 Meg into the TLBs. For this quick hack,
* we can load the instruction and data TLB registers with the
* same values.
*/
li r8, MI_EVALID /* Create EPN for address 0 */
mtspr MI_EPN, r8
mtspr MD_EPN, r8
li r8, MI_PS8MEG /* Set 8M byte page */
ori r8, r8, MI_SVALID /* Make it valid */
mtspr MI_TWC, r8
mtspr MD_TWC, r8
li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */
mtspr MI_RPN, r8 /* Store TLB entry */
mtspr MD_RPN, r8
lis r8, MI_Kp@h /* Set the protection mode */
mtspr MI_AP, r8
mtspr MD_AP, r8
/* Now map the higher 8 Meg into the TLBs. For this quick hack,
* we can load the instruction and data TLB registers with the
* same values.
*/
lwz r9,20(r2) /* gd->ram_size */
addis r9,r9,-0x80
mr r8, r9 /* Higher 8 Meg in SDRAM */
ori r8, r8, MI_EVALID /* Mark page valid */
mtspr MI_EPN, r8
mtspr MD_EPN, r8
li r8, MI_PS8MEG /* Set 8M byte page */
ori r8, r8, MI_SVALID /* Make it valid */
mtspr MI_TWC, r8
mtspr MD_TWC, r8
mr r8, r9
ori r8, r8, MI_BOOTINIT|0x2
mtspr MI_RPN, r8 /* Store TLB entry */
mtspr MD_RPN, r8
lis r8, MI_Kp@h /* Set the protection mode */
mtspr MI_AP, r8
mtspr MD_AP, r8
/* Map another 8 MByte at the IMMR to get the processor
* internal registers (among other things).
*/
mfspr r9, 638 /* Get current IMMR */
andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
mr r8, r9 /* Create vaddr for TLB */
ori r8, r8, MD_EVALID /* Mark it valid */
mtspr MD_EPN, r8
li r8, MD_PS8MEG /* Set 8M byte page */
ori r8, r8, MD_SVALID /* Make it valid */
mtspr MD_TWC, r8
mr r8, r9 /* Create paddr for TLB */
ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
mtspr MD_RPN, r8
/* We now have the lower and higher 8 Meg mapped into TLB entries,
* and the caches ready to work.
*/
mfmsr r0
ori r0,r0,MSR_DR|MSR_IR
mtspr SRR1,r0
mflr r0
mtspr SRR0,r0
SYNC
rfi /* enables MMU */
/*
* void caches_init(void);
*/
.globl caches_init
caches_init:
sync
mfspr r3, IC_CST /* Clear error bits */
mfspr r3, DC_CST
lis r3, IDC_UNALL@h /* Unlock all */
mtspr IC_CST, r3
mtspr DC_CST, r3
lis r3, IDC_INVALL@h /* Invalidate all */
mtspr IC_CST, r3
mtspr DC_CST, r3
lis r3, IDC_ENABLE@h /* Enable all */
mtspr IC_CST, r3
mtspr DC_CST, r3
blr
/*
* void flush_dcache_range(unsigned long start, unsigned long stop);
*/
.global flush_dcache_range
flush_dcache_range:
li r5,CACHE_LINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,LG_CACHE_LINE_SIZE
beqlr
mtctr r4
1: dcbf 0,r3
addi r3,r3,CACHE_LINE_SIZE
bdnz 1b
sync /* wait for dcbf's to get to ram */
blr
/*
* void disable_interrupts(void);
*/
.global disable_interrupts
disable_interrupts:
mfmsr r0
rlwinm r0,r0,0,17,15
mtmsr r0
blr
|
1001-study-uboot
|
examples/standalone/test_burst_lib.S
|
Unix Assembly
|
gpl3
| 4,181
|
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <exports.h>
/*
* Author: Arun Dharankar <ADharankar@ATTBI.Com>
*
* A very simple thread/schedular model:
* - only one master thread, and no parent child relation maintained
* - parent thread cannot be stopped or deleted
* - no permissions or credentials
* - no elaborate safety checks
* - cooperative multi threading
* - Simple round-robin scheduleing with no priorities
* - no metering/statistics collection
*
* Basic idea of implementing this is to allow more than one tests to
* execute "simultaneously".
*
* This may be modified such thread_yield may be called in syscalls, and
* timer interrupts.
*/
#define MAX_THREADS 8
#define CTX_SIZE 512
#define STK_SIZE 8*1024
#define STATE_EMPTY 0
#define STATE_RUNNABLE 1
#define STATE_STOPPED 2
#define STATE_TERMINATED 2
#define MASTER_THREAD 0
#define RC_FAILURE (-1)
#define RC_SUCCESS (0)
typedef vu_char *jmp_ctx;
unsigned long setctxsp (vu_char *sp);
int ppc_setjmp(jmp_ctx env);
void ppc_longjmp(jmp_ctx env, int val);
#define setjmp ppc_setjmp
#define longjmp ppc_longjmp
struct lthread {
int state;
int retval;
char stack[STK_SIZE];
uchar context[CTX_SIZE];
int (*func) (void *);
void *arg;
};
static volatile struct lthread lthreads[MAX_THREADS];
static volatile int current_tid = MASTER_THREAD;
static uchar dbg = 0;
#define PDEBUG(fmt, args...) { \
if(dbg != 0) { \
printf("[%s %d %s]: ",__FILE__,__LINE__,__FUNCTION__);\
printf(fmt, ##args); \
printf("\n"); \
} \
}
static int testthread (void *);
static void sched_init (void);
static int thread_create (int (*func) (void *), void *arg);
static int thread_start (int id);
static void thread_yield (void);
static int thread_delete (int id);
static int thread_join (int *ret);
#if 0 /* not used yet */
static int thread_stop (int id);
#endif /* not used yet */
/* An example of schedular test */
#define NUMTHREADS 7
int sched (int ac, char *av[])
{
int i, j;
int tid[NUMTHREADS];
int names[NUMTHREADS];
app_startup(av);
sched_init ();
for (i = 0; i < NUMTHREADS; i++) {
names[i] = i;
j = thread_create (testthread, (void *) &names[i]);
if (j == RC_FAILURE)
printf ("schedtest: Failed to create thread %d\n", i);
if (j > 0) {
printf ("schedtest: Created thread with id %d, name %d\n",
j, i);
tid[i] = j;
}
}
printf ("schedtest: Threads created\n");
printf ("sched_test: function=0x%08x\n", (unsigned)testthread);
for (i = 0; i < NUMTHREADS; i++) {
printf ("schedtest: Setting thread %d runnable\n", tid[i]);
thread_start (tid[i]);
thread_yield ();
}
printf ("schedtest: Started %d threads\n", NUMTHREADS);
while (1) {
printf ("schedtest: Waiting for threads to complete\n");
if (tstc () && getc () == 0x3) {
printf ("schedtest: Aborting threads...\n");
for (i = 0; i < NUMTHREADS; i++) {
printf ("schedtest: Deleting thread %d\n", tid[i]);
thread_delete (tid[i]);
}
return RC_SUCCESS;
}
j = -1;
i = thread_join (&j);
if (i == RC_FAILURE) {
printf ("schedtest: No threads pending, "
"exiting schedular test\n");
return RC_SUCCESS;
}
printf ("schedtest: thread is %d returned %d\n", i, j);
thread_yield ();
}
return RC_SUCCESS;
}
static int testthread (void *name)
{
int i;
printf ("testthread: Begin executing thread, myname %d, &i=0x%08x\n",
*(int *) name, (unsigned)&i);
printf ("Thread %02d, i=%d\n", *(int *) name, i);
for (i = 0; i < 0xffff * (*(int *) name + 1); i++) {
if (tstc () && getc () == 0x3) {
printf ("testthread: myname %d terminating.\n",
*(int *) name);
return *(int *) name + 1;
}
if (i % 100 == 0)
thread_yield ();
}
printf ("testthread: returning %d, i=0x%x\n",
*(int *) name + 1, i);
return *(int *) name + 1;
}
static void sched_init (void)
{
int i;
for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++)
lthreads[i].state = STATE_EMPTY;
current_tid = MASTER_THREAD;
lthreads[current_tid].state = STATE_RUNNABLE;
PDEBUG ("sched_init: master context = 0x%08x",
(unsigned)lthreads[current_tid].context);
return;
}
static void thread_yield (void)
{
static int i;
PDEBUG ("thread_yield: current tid=%d", current_tid);
#define SWITCH(new) \
if(lthreads[new].state == STATE_RUNNABLE) { \
PDEBUG("thread_yield: %d match, ctx=0x%08x", \
new, \
(unsigned)lthreads[current_tid].context); \
if(setjmp(lthreads[current_tid].context) == 0) { \
current_tid = new; \
PDEBUG("thread_yield: tid %d returns 0", \
new); \
longjmp(lthreads[new].context, 1); \
} else { \
PDEBUG("thread_yield: tid %d returns 1", \
new); \
return; \
} \
}
for (i = current_tid + 1; i < MAX_THREADS; i++) {
SWITCH (i);
}
if (current_tid != 0) {
for (i = 0; i <= current_tid; i++) {
SWITCH (i);
}
}
PDEBUG ("thread_yield: returning from thread_yield");
return;
}
static int thread_create (int (*func) (void *), void *arg)
{
int i;
for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++) {
if (lthreads[i].state == STATE_EMPTY) {
lthreads[i].state = STATE_STOPPED;
lthreads[i].func = func;
lthreads[i].arg = arg;
PDEBUG ("thread_create: returns new tid %d", i);
return i;
}
}
PDEBUG ("thread_create: returns failure");
return RC_FAILURE;
}
static int thread_delete (int id)
{
if (id <= MASTER_THREAD || id > MAX_THREADS)
return RC_FAILURE;
if (current_tid == id)
return RC_FAILURE;
lthreads[id].state = STATE_EMPTY;
return RC_SUCCESS;
}
static void thread_launcher (void)
{
PDEBUG ("thread_launcher: invoking func=0x%08x",
(unsigned)lthreads[current_tid].func);
lthreads[current_tid].retval =
lthreads[current_tid].func (lthreads[current_tid].arg);
PDEBUG ("thread_launcher: tid %d terminated", current_tid);
lthreads[current_tid].state = STATE_TERMINATED;
thread_yield ();
printf ("thread_launcher: should NEVER get here!\n");
return;
}
static int thread_start (int id)
{
PDEBUG ("thread_start: id=%d", id);
if (id <= MASTER_THREAD || id > MAX_THREADS) {
return RC_FAILURE;
}
if (lthreads[id].state != STATE_STOPPED)
return RC_FAILURE;
if (setjmp (lthreads[current_tid].context) == 0) {
lthreads[id].state = STATE_RUNNABLE;
current_tid = id;
PDEBUG ("thread_start: to be stack=0%08x",
(unsigned)lthreads[id].stack);
setctxsp ((vu_char *)<hreads[id].stack[STK_SIZE]);
thread_launcher ();
}
PDEBUG ("thread_start: Thread id=%d started, parent returns", id);
return RC_SUCCESS;
}
#if 0 /* not used so far */
static int thread_stop (int id)
{
if (id <= MASTER_THREAD || id >= MAX_THREADS)
return RC_FAILURE;
if (current_tid == id)
return RC_FAILURE;
lthreads[id].state = STATE_STOPPED;
return RC_SUCCESS;
}
#endif /* not used so far */
static int thread_join (int *ret)
{
int i, j = 0;
PDEBUG ("thread_join: *ret = %d", *ret);
if (!(*ret == -1 || *ret > MASTER_THREAD || *ret < MAX_THREADS)) {
PDEBUG ("thread_join: invalid tid %d", *ret);
return RC_FAILURE;
}
if (*ret == -1) {
PDEBUG ("Checking for tid = -1");
while (1) {
/* PDEBUG("thread_join: start while-loopn"); */
j = 0;
for (i = MASTER_THREAD + 1; i < MAX_THREADS; i++) {
if (lthreads[i].state == STATE_TERMINATED) {
*ret = lthreads[i].retval;
lthreads[i].state = STATE_EMPTY;
/* PDEBUG("thread_join: returning retval %d of tid %d",
ret, i); */
return RC_SUCCESS;
}
if (lthreads[i].state != STATE_EMPTY) {
PDEBUG ("thread_join: %d used slots tid %d state=%d",
j, i, lthreads[i].state);
j++;
}
}
if (j == 0) {
PDEBUG ("thread_join: all slots empty!");
return RC_FAILURE;
}
/* PDEBUG("thread_join: yielding"); */
thread_yield ();
/* PDEBUG("thread_join: back from yield"); */
}
}
if (lthreads[*ret].state == STATE_TERMINATED) {
i = *ret;
*ret = lthreads[*ret].retval;
lthreads[*ret].state = STATE_EMPTY;
PDEBUG ("thread_join: returing %d for tid %d", *ret, i);
return RC_SUCCESS;
}
PDEBUG ("thread_join: thread %d is not terminated!", *ret);
return RC_FAILURE;
}
|
1001-study-uboot
|
examples/standalone/sched.c
|
C
|
gpl3
| 8,847
|
/*
* atmel_df_pow2.c - convert Atmel Dataflashes to Power of 2 mode
*
* Copyright 2009 Analog Devices Inc.
*
* Licensed under the 2-clause BSD.
*/
#include <common.h>
#include <exports.h>
#include <spi.h>
#define CMD_ID 0x9f
#define CMD_STAT 0xd7
#define CMD_CFG 0x3d
static int flash_cmd(struct spi_slave *slave, uchar cmd, uchar *buf, int len)
{
buf[0] = cmd;
return spi_xfer(slave, 8 * len, buf, buf, SPI_XFER_BEGIN | SPI_XFER_END);
}
static int flash_status(struct spi_slave *slave)
{
uchar buf[2];
if (flash_cmd(slave, CMD_STAT, buf, sizeof(buf)))
return -1;
return buf[1];
}
static int flash_set_pow2(struct spi_slave *slave)
{
int ret;
uchar buf[4];
buf[1] = 0x2a;
buf[2] = 0x80;
buf[3] = 0xa6;
ret = flash_cmd(slave, CMD_CFG, buf, sizeof(buf));
if (ret)
return ret;
/* wait Tp, or 6 msec */
udelay(6000);
ret = flash_status(slave);
if (ret == -1)
return 1;
return ret & 0x1 ? 0 : 1;
}
static int flash_check(struct spi_slave *slave)
{
int ret;
uchar buf[4];
ret = flash_cmd(slave, CMD_ID, buf, sizeof(buf));
if (ret)
return ret;
if (buf[1] != 0x1F) {
printf("atmel flash not found (id[0] = %#x)\n", buf[1]);
return 1;
}
if ((buf[2] >> 5) != 0x1) {
printf("AT45 flash not found (id[0] = %#x)\n", buf[2]);
return 2;
}
return 0;
}
static char *getline(void)
{
static char buffer[100];
char c;
size_t i;
i = 0;
while (1) {
buffer[i] = '\0';
c = getc();
switch (c) {
case '\r': /* Enter/Return key */
case '\n':
puts("\n");
return buffer;
case 0x03: /* ^C - break */
return NULL;
case 0x5F:
case 0x08: /* ^H - backspace */
case 0x7F: /* DEL - backspace */
if (i) {
puts("\b \b");
i--;
}
break;
default:
/* Ignore control characters */
if (c < 0x20)
break;
/* Queue up all other characters */
buffer[i++] = c;
printf("%c", c);
break;
}
}
}
int atmel_df_pow2(int argc, char * const argv[])
{
/* Print the ABI version */
app_startup(argv);
if (XF_VERSION != get_version()) {
printf("Expects ABI version %d\n", XF_VERSION);
printf("Actual U-Boot ABI version %lu\n", get_version());
printf("Can't run\n\n");
return 1;
}
spi_init();
while (1) {
struct spi_slave *slave;
char *line, *p;
int bus, cs, status;
puts("\nenter the [BUS:]CS of the SPI flash: ");
line = getline();
/* CTRL+C */
if (!line)
return 0;
if (line[0] == '\0')
continue;
bus = cs = simple_strtoul(line, &p, 10);
if (*p) {
if (*p == ':') {
++p;
cs = simple_strtoul(p, &p, 10);
}
if (*p) {
puts("invalid format, please try again\n");
continue;
}
} else
bus = 0;
printf("\ngoing to work with dataflash at %i:%i\n", bus, cs);
/* use a low speed -- it'll work with all devices, and
* speed here doesn't really matter.
*/
slave = spi_setup_slave(bus, cs, 1000, SPI_MODE_3);
if (!slave) {
puts("unable to setup slave\n");
continue;
}
if (spi_claim_bus(slave)) {
spi_free_slave(slave);
continue;
}
if (flash_check(slave)) {
puts("no flash found\n");
goto done;
}
status = flash_status(slave);
if (status == -1) {
puts("unable to read status register\n");
goto done;
}
if (status & 0x1) {
puts("flash is already in power-of-2 mode!\n");
goto done;
}
puts("are you sure you wish to set power-of-2 mode?\n");
puts("this operation is permanent and irreversible\n");
printf("enter YES to continue: ");
line = getline();
if (!line || strcmp(line, "YES"))
goto done;
if (flash_set_pow2(slave)) {
puts("setting pow2 mode failed\n");
goto done;
}
puts(
"Configuration should be updated now. You will have to\n"
"power cycle the part in order to finish the conversion.\n"
);
done:
spi_release_bus(slave);
spi_free_slave(slave);
}
}
|
1001-study-uboot
|
examples/standalone/atmel_df_pow2.c
|
C
|
gpl3
| 3,824
|
/*
* smc911x_eeprom.c - EEPROM interface to SMC911x parts.
* Only tested on SMSC9118 though ...
*
* Copyright 2004-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*
* Based on smc91111_eeprom.c which:
* Heavily borrowed from the following peoples GPL'ed software:
* - Wolfgang Denk, DENX Software Engineering, wd@denx.de
* Das U-boot
* - Ladislav Michl ladis@linux-mips.org
* A rejected patch on the U-Boot mailing list
*/
#include <common.h>
#include <exports.h>
#include <linux/ctype.h>
#include "../drivers/net/smc911x.h"
/**
* smsc_ctrlc - detect press of CTRL+C (common ctrlc() isnt exported!?)
*/
static int smsc_ctrlc(void)
{
return (tstc() && getc() == 0x03);
}
/**
* usage - dump usage information
*/
static void usage(void)
{
puts(
"MAC/EEPROM Commands:\n"
" P : Print the MAC addresses\n"
" D : Dump the EEPROM contents\n"
" M : Dump the MAC contents\n"
" C : Copy the MAC address from the EEPROM to the MAC\n"
" W : Write a register in the EEPROM or in the MAC\n"
" Q : Quit\n"
"\n"
"Some commands take arguments:\n"
" W <E|M> <register> <value>\n"
" E: EEPROM M: MAC\n"
);
}
/**
* dump_regs - dump the MAC registers
*
* Registers 0x00 - 0x50 are FIFOs. The 0x50+ are the control registers
* and they're all 32bits long. 0xB8+ are reserved, so don't bother.
*/
static void dump_regs(struct eth_device *dev)
{
u8 i, j = 0;
for (i = 0x50; i < 0xB8; i += sizeof(u32))
printf("%02x: 0x%08x %c", i,
smc911x_reg_read(dev, i),
(j++ % 2 ? '\n' : ' '));
}
/**
* do_eeprom_cmd - handle eeprom communication
*/
static int do_eeprom_cmd(struct eth_device *dev, int cmd, u8 reg)
{
if (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY) {
printf("eeprom_cmd: busy at start (E2P_CMD = 0x%08x)\n",
smc911x_reg_read(dev, E2P_CMD));
return -1;
}
smc911x_reg_write(dev, E2P_CMD, E2P_CMD_EPC_BUSY | cmd | reg);
while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
if (smsc_ctrlc()) {
printf("eeprom_cmd: timeout (E2P_CMD = 0x%08x)\n",
smc911x_reg_read(dev, E2P_CMD));
return -1;
}
return 0;
}
/**
* read_eeprom_reg - read specified register in EEPROM
*/
static u8 read_eeprom_reg(struct eth_device *dev, u8 reg)
{
int ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_READ, reg);
return (ret ? : smc911x_reg_read(dev, E2P_DATA));
}
/**
* write_eeprom_reg - write specified value into specified register in EEPROM
*/
static int write_eeprom_reg(struct eth_device *dev, u8 value, u8 reg)
{
int ret;
/* enable erasing/writing */
ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWEN, reg);
if (ret)
goto done;
/* erase the eeprom reg */
ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_ERASE, reg);
if (ret)
goto done;
/* write the eeprom reg */
smc911x_reg_write(dev, E2P_DATA, value);
ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_WRITE, reg);
if (ret)
goto done;
/* disable erasing/writing */
ret = do_eeprom_cmd(dev, E2P_CMD_EPC_CMD_EWDS, reg);
done:
return ret;
}
/**
* skip_space - find first non-whitespace in given pointer
*/
static char *skip_space(char *buf)
{
while (isblank(buf[0]))
++buf;
return buf;
}
/**
* write_stuff - handle writing of MAC registers / eeprom
*/
static void write_stuff(struct eth_device *dev, char *line)
{
char dest;
char *endp;
u8 reg;
u32 value;
/* Skip over the "W " part of the command */
line = skip_space(line + 1);
/* Figure out destination */
switch (line[0]) {
case 'E':
case 'M':
dest = line[0];
break;
default:
invalid_usage:
printf("ERROR: Invalid write usage\n");
usage();
return;
}
/* Get the register to write */
line = skip_space(line + 1);
reg = simple_strtoul(line, &endp, 16);
if (line == endp)
goto invalid_usage;
/* Get the value to write */
line = skip_space(endp);
value = simple_strtoul(line, &endp, 16);
if (line == endp)
goto invalid_usage;
/* Check for trailing cruft */
line = skip_space(endp);
if (line[0])
goto invalid_usage;
/* Finally, execute the command */
if (dest == 'E') {
printf("Writing EEPROM register %02x with %02x\n", reg, value);
write_eeprom_reg(dev, value, reg);
} else {
printf("Writing MAC register %02x with %08x\n", reg, value);
smc911x_reg_write(dev, reg, value);
}
}
/**
* copy_from_eeprom - copy MAC address in eeprom to address registers
*/
static void copy_from_eeprom(struct eth_device *dev)
{
ulong addrl =
read_eeprom_reg(dev, 0x01) |
read_eeprom_reg(dev, 0x02) << 8 |
read_eeprom_reg(dev, 0x03) << 16 |
read_eeprom_reg(dev, 0x04) << 24;
ulong addrh =
read_eeprom_reg(dev, 0x05) |
read_eeprom_reg(dev, 0x06) << 8;
smc911x_set_mac_csr(dev, ADDRL, addrl);
smc911x_set_mac_csr(dev, ADDRH, addrh);
puts("EEPROM contents copied to MAC\n");
}
/**
* print_macaddr - print MAC address registers and MAC address in eeprom
*/
static void print_macaddr(struct eth_device *dev)
{
puts("Current MAC Address in MAC: ");
ulong addrl = smc911x_get_mac_csr(dev, ADDRL);
ulong addrh = smc911x_get_mac_csr(dev, ADDRH);
printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
(u8)(addrl), (u8)(addrl >> 8), (u8)(addrl >> 16),
(u8)(addrl >> 24), (u8)(addrh), (u8)(addrh >> 8));
puts("Current MAC Address in EEPROM: ");
int i;
for (i = 1; i < 6; ++i)
printf("%02x:", read_eeprom_reg(dev, i));
printf("%02x\n", read_eeprom_reg(dev, i));
}
/**
* dump_eeprom - dump the whole content of the EEPROM
*/
static void dump_eeprom(struct eth_device *dev)
{
int i;
puts("EEPROM:\n");
for (i = 0; i < 7; ++i)
printf("%02x: 0x%02x\n", i, read_eeprom_reg(dev, i));
}
/**
* smc911x_init - get the MAC/EEPROM up and ready for use
*/
static int smc911x_init(struct eth_device *dev)
{
/* See if there is anything there */
if (smc911x_detect_chip(dev))
return 1;
smc911x_reset(dev);
/* Make sure we set EEDIO/EECLK to the EEPROM */
if (smc911x_reg_read(dev, GPIO_CFG) & GPIO_CFG_EEPR_EN) {
while (smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
if (smsc_ctrlc()) {
printf("init: timeout (E2P_CMD = 0x%08x)\n",
smc911x_reg_read(dev, E2P_CMD));
return 1;
}
smc911x_reg_write(dev, GPIO_CFG,
smc911x_reg_read(dev, GPIO_CFG) & ~GPIO_CFG_EEPR_EN);
}
return 0;
}
/**
* getline - consume a line of input and handle some escape sequences
*/
static char *getline(void)
{
static char buffer[100];
char c;
size_t i;
i = 0;
while (1) {
buffer[i] = '\0';
while (!tstc())
continue;
c = getc();
/* Convert to uppercase */
if (c >= 'a' && c <= 'z')
c -= ('a' - 'A');
switch (c) {
case '\r': /* Enter/Return key */
case '\n':
puts("\n");
return buffer;
case 0x03: /* ^C - break */
return NULL;
case 0x5F:
case 0x08: /* ^H - backspace */
case 0x7F: /* DEL - backspace */
if (i) {
puts("\b \b");
i--;
}
break;
default:
/* Ignore control characters */
if (c < 0x20)
break;
/* Queue up all other characters */
buffer[i++] = c;
printf("%c", c);
break;
}
}
}
/**
* smc911x_eeprom - our application's main() function
*/
int smc911x_eeprom(int argc, char * const argv[])
{
/* Avoid initializing on stack as gcc likes to call memset() */
struct eth_device dev;
dev.iobase = CONFIG_SMC911X_BASE;
/* Print the ABI version */
app_startup(argv);
if (XF_VERSION != get_version()) {
printf("Expects ABI version %d\n", XF_VERSION);
printf("Actual U-Boot ABI version %lu\n", get_version());
printf("Can't run\n\n");
return 1;
}
/* Initialize the MAC/EEPROM somewhat */
puts("\n");
if (smc911x_init(&dev))
return 1;
/* Dump helpful usage information */
puts("\n");
usage();
puts("\n");
while (1) {
char *line;
/* Send the prompt and wait for a line */
puts("eeprom> ");
line = getline();
/* Got a ctrl+c */
if (!line)
return 0;
/* Eat leading space */
line = skip_space(line);
/* Empty line, try again */
if (!line[0])
continue;
/* Only accept 1 letter commands */
if (line[0] && line[1] && !isblank(line[1]))
goto unknown_cmd;
/* Now parse the command */
switch (line[0]) {
case 'W': write_stuff(&dev, line); break;
case 'D': dump_eeprom(&dev); break;
case 'M': dump_regs(&dev); break;
case 'C': copy_from_eeprom(&dev); break;
case 'P': print_macaddr(&dev); break;
unknown_cmd:
default: puts("ERROR: Unknown command!\n\n");
case '?':
case 'H': usage(); break;
case 'Q': return 0;
}
}
}
|
1001-study-uboot
|
examples/standalone/smc911x_eeprom.c
|
C
|
gpl3
| 8,410
|
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* The test exercises SDRAM accesses in burst mode
*/
#include <common.h>
#include <exports.h>
#include <commproc.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <serial.h>
#include <watchdog.h>
#include "test_burst.h"
/* 8 MB test region of physical RAM */
#define TEST_PADDR 0x00800000
/* The uncached virtual region */
#define TEST_VADDR_NC 0x00800000
/* The cached virtual region */
#define TEST_VADDR_C 0x01000000
/* When an error is detected, the address where the error has been found,
and also the current and the expected data will be written to
the following flash address
*/
#define TEST_FLASH_ADDR 0x40100000
/* Define GPIO ports to signal start of burst transfers and errors */
#ifdef CONFIG_LWMON
/* Use PD.8 to signal start of burst transfers */
#define GPIO1_DAT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
#define GPIO1_BIT 0x0080
/* Configure PD.8 as general purpose output */
#define GPIO1_INIT \
((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar &= ~GPIO1_BIT; \
((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir |= GPIO1_BIT;
/* Use PD.9 to signal error */
#define GPIO2_DAT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
#define GPIO2_BIT 0x0040
/* Configure PD.9 as general purpose output */
#define GPIO2_INIT \
((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar &= ~GPIO2_BIT; \
((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir |= GPIO2_BIT;
#endif /* CONFIG_LWMON */
static void test_prepare (void);
static int test_burst_start (unsigned long size, unsigned long pattern);
static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
static int test_mmu_is_on(void);
static void test_desc(unsigned long size);
static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern);
static void signal_init(void);
static void signal_start(void);
static void signal_error(void);
static void test_usage(void);
static unsigned long test_pattern [] = {
0x00000000,
0xffffffff,
0x55555555,
0xaaaaaaaa,
};
int test_burst (int argc, char * const argv[])
{
unsigned long size = CACHE_LINE_SIZE;
unsigned int pass = 0;
int res = 0;
int i, j;
if (argc == 3) {
char * d;
for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) {
size *= 10;
size += *d - '0';
}
if (size == 0 || *d) {
test_usage();
return 1;
}
for (d = argv[2]; *d >= '0' && *d <= '9'; d++) {
pass *= 10;
pass += *d - '0';
}
if (*d) {
test_usage();
return 1;
}
} else if (argc > 3) {
test_usage();
return 1;
}
size += (CACHE_LINE_SIZE - 1);
size &= ~(CACHE_LINE_SIZE - 1);
if (!test_mmu_is_on()) {
test_prepare();
}
test_desc(size);
for (j = 0; !pass || j < pass; j++) {
for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]);
i++) {
res = test_burst_start(size, test_pattern[i]);
if (res != 0) {
goto Done;
}
}
printf ("Iteration #%d passed\n", j + 1);
if (tstc() && 0x03 == getc())
break;
}
Done:
return res;
}
static void test_prepare (void)
{
printf ("\n");
caches_init();
disable_interrupts();
mmu_init();
printf ("Interrupts are disabled\n");
printf ("I-Cache is ON\n");
printf ("D-Cache is ON\n");
printf ("MMU is ON\n");
printf ("\n");
test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0);
test_map_8M (TEST_PADDR, TEST_VADDR_C, 1);
test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0);
/* Configure GPIO ports */
signal_init();
}
static int test_burst_start (unsigned long size, unsigned long pattern)
{
volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C;
volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC;
int i, n;
int res = 1;
printf ("Test pattern %08lx ...", pattern);
n = size / 4;
for (i = 0; i < n; i ++) {
vaddr_c [i] = pattern;
}
signal_start();
flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1);
for (i = 0; i < n; i ++) {
register unsigned long tmp = vaddr_nc [i];
if (tmp != pattern) {
test_error("2a", vaddr_nc + i, tmp, pattern);
goto Done;
}
}
for (i = 0; i < n; i ++) {
register unsigned long tmp = vaddr_c [i];
if (tmp != pattern) {
test_error("2b", vaddr_c + i, tmp, pattern);
goto Done;
}
}
for (i = 0; i < n; i ++) {
vaddr_nc [i] = pattern;
}
for (i = 0; i < n; i ++) {
register unsigned long tmp = vaddr_nc [i];
if (tmp != pattern) {
test_error("3a", vaddr_nc + i, tmp, pattern);
goto Done;
}
}
signal_start();
for (i = 0; i < n; i ++) {
register unsigned long tmp = vaddr_c [i];
if (tmp != pattern) {
test_error("3b", vaddr_c + i, tmp, pattern);
goto Done;
}
}
res = 0;
Done:
printf(" %s\n", res == 0 ? "OK" : "");
return res;
}
static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached)
{
mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID);
mtspr (MD_TWC, MI_PS8MEG | MI_SVALID);
mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2));
mtspr (MD_AP, MI_Kp);
}
static int test_mmu_is_on(void)
{
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr & MSR_DR;
}
static void test_desc(unsigned long size)
{
printf(
"The following tests will be conducted:\n"
"1) Map %ld-byte region of physical RAM at 0x%08x\n"
" into two virtual regions:\n"
" one cached at 0x%08x and\n"
" the the other uncached at 0x%08x.\n",
size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C);
puts(
"2) Fill the cached region with a pattern, and flush the cache\n"
"2a) Check the uncached region to match the pattern\n"
"2b) Check the cached region to match the pattern\n"
"3) Fill the uncached region with a pattern\n"
"3a) Check the cached region to match the pattern\n"
"3b) Check the uncached region to match the pattern\n"
"2b) Change the patterns and go to step 2\n"
"\n"
);
}
static void test_error(
char * step, volatile void * addr, unsigned long val, unsigned long pattern)
{
volatile unsigned long * p = (void *)TEST_FLASH_ADDR;
signal_error();
p[0] = (unsigned long)addr;
p[1] = val;
p[2] = pattern;
printf ("\nError at step %s, addr %08lx: read %08lx, pattern %08lx",
step, (unsigned long)addr, val, pattern);
}
static void signal_init(void)
{
#if defined(GPIO1_INIT)
GPIO1_INIT;
#endif
#if defined(GPIO2_INIT)
GPIO2_INIT;
#endif
}
static void signal_start(void)
{
#if defined(GPIO1_INIT)
if (GPIO1_DAT & GPIO1_BIT) {
GPIO1_DAT &= ~GPIO1_BIT;
} else {
GPIO1_DAT |= GPIO1_BIT;
}
#endif
}
static void signal_error(void)
{
#if defined(GPIO2_INIT)
if (GPIO2_DAT & GPIO2_BIT) {
GPIO2_DAT &= ~GPIO2_BIT;
} else {
GPIO2_DAT |= GPIO2_BIT;
}
#endif
}
static void test_usage(void)
{
printf("Usage: go 0x40004 [size] [count]\n");
}
|
1001-study-uboot
|
examples/standalone/test_burst.c
|
C
|
gpl3
| 7,663
|
#include <stddef.h>
#include <stdio.h>
#include <string.h>
void *func[8], **pfunc;
typedef struct xxx xxx_t;
struct xxx {
int dummy;
void **pfunc;
} q;
#define XF_strcpy 3
#define XF_printf 4
#define LABEL(x) \
asm volatile ( \
#if defined(__i386__)
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl mon_" #x "\n" \
"mon_" #x ":\n" \
" movl %0, %%eax\n" \
" movl pfunc, %%ecx\n" \
" jmp *(%%ecx,%%eax)\n" \
: : "i"(XF_ ## x * sizeof(void *)) : "eax", "ecx");
#elif defined(__powerpc__)
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl mon_" #x "\n" \
"mon_" #x ":\n" \
" lwz %%r11, %0(%%r2)\n" \
" lwz %%r11, %1(%%r11)\n" \
" mtctr %%r11\n" \
" bctr\n" \
: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "r11", "r2");
#elif defined(__arm__)
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl mon_" #x "\n" \
"mon_" #x ":\n" \
" ldr ip, [r8, %0]\n" \
" ldr pc, [ip, %1]\n" \
: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "ip");
#elif defined(__mips__)
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl mon_" #x "\n" \
"mon_" #x ":\n" \
" lw $25, %0($26)\n" \
" lw $25, %1($25)\n" \
" jr $25\n" \
: : "i"(offsetof(xxx_t, pfunc)), "i"(XF_ ## x * sizeof(void *)) : "t9");
#elif defined(__nds32__)
#define EXPORT_FUNC(x) \
asm volatile ( \
" .globl mon_" #x "\n" \
"mon_" #x ":\n" \
" lwi $r16, [$gp + (%0)]\n" \
" lwi $r16, [$r16 + (%1)]\n" \
" jr $r16\n" \
: : "i"(offsetof(xxx_t, pfunc)), \
"i"(XF_ ## x * sizeof(void *)) : "$r16");
#else
#error [No stub code for this arch]
#endif
void dummy(void)
{
EXPORT_FUNC(printf)
EXPORT_FUNC(strcpy)
}
int main(void)
{
#if defined(__i386__)
xxx_t *pq;
#elif defined(__powerpc__)
register volatile xxx_t *pq asm("r2");
#elif defined(__arm__)
register volatile xxx_t *pq asm("r8");
#elif defined(__mips__)
register volatile xxx_t *pq asm("k0");
#elif defined(__nds32__)
register volatile xxx_t *pq asm("$r16");
#endif
char buf[32];
func[XF_strcpy] = strcpy;
func[XF_printf] = printf;
pq = &q;
pq->pfunc = pfunc = func;
mon_strcpy(buf, "test");
mon_printf("hi %s %d z\n", buf, 444);
return 0;
}
|
1001-study-uboot
|
examples/standalone/x86-testapp.c
|
C
|
gpl3
| 2,241
|
/*
* (C) Copyright 2006
* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This is a very simple standalone application demonstrating
* catching IRQs on the MPC52xx architecture.
*
* The interrupt to be intercepted can be specified as an argument
* to the application. Specifying nothing will intercept IRQ1 on the
* MPC5200 platform. On the CR825 carrier board from MicroSys this
* maps to the ABORT switch :)
*
* Note that the specified vector is only a logical number specified
* by the respective header file.
*/
#include <common.h>
#include <exports.h>
#include <config.h>
#if defined(CONFIG_MPC5xxx)
#define DFL_IRQ MPC5XXX_IRQ1
#else
#define DFL_IRQ 0
#endif
static void irq_handler (void *arg);
int interrupt (int argc, char * const argv[])
{
int c, irq = -1;
app_startup (argv);
if (argc > 1)
irq = simple_strtoul (argv[1], NULL, 0);
if ((irq < 0) || (irq > NR_IRQS))
irq = DFL_IRQ;
printf ("Installing handler for irq vector %d and doing busy wait\n",
irq);
printf ("Press 'q' to quit\n");
/* Install interrupt handler */
install_hdlr (irq, irq_handler, NULL);
while ((c = getc ()) != 'q') {
printf ("Ok, ok, I am still alive!\n");
}
free_hdlr (irq);
printf ("\nInterrupt handler has been uninstalled\n");
return (0);
}
/*
* Handler for interrupt
*/
static void irq_handler (void *arg)
{
/* just for demonstration */
printf ("+");
}
|
1001-study-uboot
|
examples/standalone/interrupt.c
|
C
|
gpl3
| 2,200
|
/* longjmp for PowerPC.
Copyright (C) 1995, 1996, 1997, 1999, 2000 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
02111-1307 USA. */
#include <ppc_asm.tmpl>
# define JB_GPR1 0 /* Also known as the stack pointer */
# define JB_GPR2 1
# define JB_LR 2 /* The address we will return to */
# define JB_GPRS 3 /* GPRs 14 through 31 are saved, 18 in total */
# define JB_CR 21 /* Condition code registers. */
# define JB_FPRS 22 /* FPRs 14 through 31 are saved, 18*2 words total */
# define JB_SIZE (58*4)
#define FP(x...) x
#define FP(x...) x
.globl ppc_longjmp;
ppc_longjmp:
lwz r1,(JB_GPR1*4)(r3)
lwz r2,(JB_GPR2*4)(r3)
lwz r0,(JB_LR*4)(r3)
lwz r14,((JB_GPRS+0)*4)(r3)
FP( lfd 14,((JB_FPRS+0*2)*4)(r3))
lwz r15,((JB_GPRS+1)*4)(r3)
FP( lfd 15,((JB_FPRS+1*2)*4)(r3))
lwz r16,((JB_GPRS+2)*4)(r3)
FP( lfd 16,((JB_FPRS+2*2)*4)(r3))
lwz r17,((JB_GPRS+3)*4)(r3)
FP( lfd 17,((JB_FPRS+3*2)*4)(r3))
lwz r18,((JB_GPRS+4)*4)(r3)
FP( lfd 18,((JB_FPRS+4*2)*4)(r3))
lwz r19,((JB_GPRS+5)*4)(r3)
FP( lfd 19,((JB_FPRS+5*2)*4)(r3))
lwz r20,((JB_GPRS+6)*4)(r3)
FP( lfd 20,((JB_FPRS+6*2)*4)(r3))
mtlr r0
lwz r21,((JB_GPRS+7)*4)(r3)
FP( lfd 21,((JB_FPRS+7*2)*4)(r3))
lwz r22,((JB_GPRS+8)*4)(r3)
FP( lfd 22,((JB_FPRS+8*2)*4)(r3))
lwz r0,(JB_CR*4)(r3)
lwz r23,((JB_GPRS+9)*4)(r3)
FP( lfd 23,((JB_FPRS+9*2)*4)(r3))
lwz r24,((JB_GPRS+10)*4)(r3)
FP( lfd 24,((JB_FPRS+10*2)*4)(r3))
lwz r25,((JB_GPRS+11)*4)(r3)
FP( lfd 25,((JB_FPRS+11*2)*4)(r3))
mtcrf 0xFF,r0
lwz r26,((JB_GPRS+12)*4)(r3)
FP( lfd 26,((JB_FPRS+12*2)*4)(r3))
lwz r27,((JB_GPRS+13)*4)(r3)
FP( lfd 27,((JB_FPRS+13*2)*4)(r3))
lwz r28,((JB_GPRS+14)*4)(r3)
FP( lfd 28,((JB_FPRS+14*2)*4)(r3))
lwz r29,((JB_GPRS+15)*4)(r3)
FP( lfd 29,((JB_FPRS+15*2)*4)(r3))
lwz r30,((JB_GPRS+16)*4)(r3)
FP( lfd 30,((JB_FPRS+16*2)*4)(r3))
lwz r31,((JB_GPRS+17)*4)(r3)
FP( lfd 31,((JB_FPRS+17*2)*4)(r3))
mr r3,r4
blr
|
1001-study-uboot
|
examples/standalone/ppc_longjmp.S
|
Unix Assembly
|
gpl3
| 2,648
|
/*
* NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
*
* (C) Copyright 2006-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Copyright (c) 2008 Freescale Semiconductor, Inc.
* Author: Scott Wood <scottwood@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_lbc.h>
#include <linux/mtd/nand.h>
#define WINDOW_SIZE 8192
static void nand_wait(void)
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
for (;;) {
uint32_t status = in_be32(®s->ltesr);
if (status == 1)
return;
if (status & 1) {
puts("read failed (ltesr)\n");
for (;;);
}
}
}
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
{
fsl_lbc_t *regs = LBC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
const int block_shift = large ? 17 : 14;
const int block_size = 1 << block_shift;
const int page_size = large ? 2048 : 512;
const int bad_marker = large ? page_size + 0 : page_size + 5;
int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
int pos = 0;
if (offs & (block_size - 1)) {
puts("bad offset\n");
for (;;);
}
if (large) {
fmr |= FMR_ECCM;
out_be32(®s->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
(NAND_CMD_READSTART << FCR_CMD1_SHIFT));
out_be32(®s->fir,
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_CW1 << FIR_OP3_SHIFT) |
(FIR_OP_RBW << FIR_OP4_SHIFT));
} else {
out_be32(®s->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
out_be32(®s->fir,
(FIR_OP_CW0 << FIR_OP0_SHIFT) |
(FIR_OP_CA << FIR_OP1_SHIFT) |
(FIR_OP_PA << FIR_OP2_SHIFT) |
(FIR_OP_RBW << FIR_OP3_SHIFT));
}
out_be32(®s->fbcr, 0);
clrsetbits_be32(®s->bank[0].br, BR_DECC, BR_DECC_CHK_GEN);
while (pos < uboot_size) {
int i = 0;
out_be32(®s->fbar, offs >> block_shift);
do {
int j;
unsigned int page_offs = (offs & (block_size - 1)) << 1;
out_be32(®s->ltesr, ~0);
out_be32(®s->lteatr, 0);
out_be32(®s->fpar, page_offs);
out_be32(®s->fmr, fmr);
out_be32(®s->lsor, 0);
nand_wait();
page_offs %= WINDOW_SIZE;
/*
* If either of the first two pages are marked bad,
* continue to the next block.
*/
if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
puts("skipping\n");
offs = (offs + block_size) & ~(block_size - 1);
pos &= ~(block_size - 1);
break;
}
for (j = 0; j < page_size; j++)
dst[pos + j] = buf[page_offs + j];
pos += page_size;
offs += page_size;
} while ((offs & (block_size - 1)) && (pos < uboot_size));
}
}
/*
* The main entry for NAND booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
* from NAND into SDRAM and starts it from there.
*/
void nand_boot(void)
{
__attribute__((noreturn)) void (*uboot)(void);
/*
* Load U-Boot image from NAND into RAM
*/
nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
/*
* Jump to U-Boot image
*/
puts("transfering control\n");
/*
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot();
}
|
1001-study-uboot
|
nand_spl/nand_boot_fsl_elbc.c
|
C
|
gpl3
| 4,220
|
/*
* (C) Copyright 2009
* Magnus Lilja <lilja.magnus@gmail.com>
*
* (C) Copyright 2008
* Maxim Artamonov, <scn1874 at yandex.ru>
*
* (C) Copyright 2006-2008
* Stefan Roese, DENX Software Engineering, sr at denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <nand.h>
#include <asm/arch/imx-regs.h>
#include <asm/io.h>
#include <fsl_nfc.h>
static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR;
static void nfc_wait_ready(void)
{
uint32_t tmp;
while (!(readw(&nfc->nand_flash_config2) & NFC_INT))
;
/* Reset interrupt flag */
tmp = readw(&nfc->nand_flash_config2);
tmp &= ~NFC_INT;
writew(tmp, &nfc->nand_flash_config2);
}
void nfc_nand_init(void)
{
#if defined(MXC_NFC_V1_1)
int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
int config1;
writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
/* unlocking RAM Buff */
writew(0x2, &nfc->configuration);
/* hardware ECC checking and correct */
config1 = readw(&nfc->nand_flash_config1) | NFC_ECC_EN | 0x800;
/*
* if spare size is larger that 16 bytes per 512 byte hunk
* then use 8 symbol correction instead of 4
*/
if ((CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page) > 16)
config1 &= ~NFC_4_8N_ECC;
else
config1 |= NFC_4_8N_ECC;
writew(config1, &nfc->nand_flash_config1);
#elif defined(MXC_NFC_V1)
/* unlocking RAM Buff */
writew(0x2, &nfc->configuration);
/* hardware ECC checking and correct */
writew(NFC_ECC_EN, &nfc->nand_flash_config1);
#endif
}
static void nfc_nand_command(unsigned short command)
{
writew(command, &nfc->flash_cmd);
writew(NFC_CMD, &nfc->nand_flash_config2);
nfc_wait_ready();
}
static void nfc_nand_page_address(unsigned int page_address)
{
unsigned int page_count;
writew(0x00, &nfc->flash_add);
writew(NFC_ADDR, &nfc->nand_flash_config2);
nfc_wait_ready();
/* code only for large page flash */
if (CONFIG_SYS_NAND_PAGE_SIZE > 512) {
writew(0x00, &nfc->flash_add);
writew(NFC_ADDR, &nfc->nand_flash_config2);
nfc_wait_ready();
}
page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
if (page_address <= page_count) {
page_count--; /* transform 0x01000000 to 0x00ffffff */
do {
writew(page_address & 0xff, &nfc->flash_add);
writew(NFC_ADDR, &nfc->nand_flash_config2);
nfc_wait_ready();
page_address = page_address >> 8;
page_count = page_count >> 8;
} while (page_count);
}
writew(0x00, &nfc->flash_add);
writew(NFC_ADDR, &nfc->nand_flash_config2);
nfc_wait_ready();
}
static void nfc_nand_data_output(void)
{
int config1 = readw(&nfc->nand_flash_config1);
#ifdef NAND_MXC_2K_MULTI_CYCLE
int i;
#endif
config1 |= NFC_ECC_EN | NFC_INT_MSK;
writew(config1, &nfc->nand_flash_config1);
writew(0, &nfc->buffer_address);
writew(NFC_OUTPUT, &nfc->nand_flash_config2);
nfc_wait_ready();
#ifdef NAND_MXC_2K_MULTI_CYCLE
/*
* This NAND controller requires multiple input commands
* for pages larger than 512 bytes.
*/
for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
config1 = readw(&nfc->nand_flash_config1);
config1 |= NFC_ECC_EN | NFC_INT_MSK;
writew(config1, &nfc->nand_flash_config1);
writew(i, &nfc->buffer_address);
writew(NFC_OUTPUT, &nfc->nand_flash_config2);
nfc_wait_ready();
}
#endif
}
static int nfc_nand_check_ecc(void)
{
return readw(&nfc->ecc_status_result);
}
static int nfc_read_page(unsigned int page_address, unsigned char *buf)
{
int i;
u32 *src;
u32 *dst;
writew(0, &nfc->buffer_address); /* read in first 0 buffer */
nfc_nand_command(NAND_CMD_READ0);
nfc_nand_page_address(page_address);
if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
nfc_nand_command(NAND_CMD_READSTART);
nfc_nand_data_output(); /* fill the main buffer 0 */
if (nfc_nand_check_ecc())
return -1;
src = &nfc->main_area[0][0];
dst = (u32 *)buf;
/* main copy loop from NAND-buffer to SDRAM memory */
for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) {
writel(readl(src), dst);
src++;
dst++;
}
return 0;
}
static int is_badblock(int pagenumber)
{
int page = pagenumber;
u32 badblock;
u32 *src;
/* Check the first two pages for bad block markers */
for (page = pagenumber; page < pagenumber + 2; page++) {
writew(0, &nfc->buffer_address); /* read in first 0 buffer */
nfc_nand_command(NAND_CMD_READ0);
nfc_nand_page_address(page);
if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
nfc_nand_command(NAND_CMD_READSTART);
nfc_nand_data_output(); /* fill the main buffer 0 */
src = &nfc->spare_area[0][0];
/*
* IMPORTANT NOTE: The nand flash controller uses a non-
* standard layout for large page devices. This can
* affect the position of the bad block marker.
*/
/* Get the bad block marker */
badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
badblock &= 0xff;
/* bad block marker verify */
if (badblock != 0xff)
return 1; /* potential bad block */
}
return 0;
}
static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
{
int i;
unsigned int page;
unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
CONFIG_SYS_NAND_PAGE_SIZE;
nfc_nand_init();
/* Convert to page number */
page = from / CONFIG_SYS_NAND_PAGE_SIZE;
i = 0;
while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) {
if (nfc_read_page(page, buf) < 0)
return -1;
page++;
i++;
buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;
/*
* Check if we have crossed a block boundary, and if so
* check for bad block.
*/
if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
/*
* Yes, new block. See if this block is good. If not,
* loop until we find a good block.
*/
while (is_badblock(page)) {
page = page + CONFIG_SYS_NAND_PAGE_COUNT;
/* Check i we've reached the end of flash. */
if (page >= maxpages)
return -1;
}
}
}
return 0;
}
#if defined(CONFIG_ARM)
void board_init_f (ulong bootflag)
{
relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL,
CONFIG_SYS_TEXT_BASE);
}
#endif
/*
* The main entry for NAND booting. It's necessary that SDRAM is already
* configured and available since this code loads the main U-Boot image
* from NAND into SDRAM and starts it from there.
*/
void nand_boot(void)
{
__attribute__((noreturn)) void (*uboot)(void);
/*
* CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
* be aligned to full pages
*/
if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
/* Copy from NAND successful, start U-boot */
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot();
} else {
/* Unrecoverable error when copying from NAND */
hang();
}
}
/*
* Called in case of an exception.
*/
void hang(void)
{
/* Loop forever */
while (1) ;
}
|
1001-study-uboot
|
nand_spl/nand_boot_fsl_nfc.c
|
C
|
gpl3
| 7,466
|
/*
* NAND boot for FSL Integrated Flash Controller, NAND Flash Control Machine
*
* Copyright 2011 Freescale Semiconductor, Inc.
* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_ifc.h>
#include <linux/mtd/nand.h>
static inline int is_blank(uchar *addr, int page_size)
{
int i;
for (i = 0; i < page_size; i++) {
if (__raw_readb(&addr[i]) != 0xff)
return 0;
}
/*
* For the SPL, don't worry about uncorrectable errors
* where the main area is all FFs but shouldn't be.
*/
return 1;
}
/* returns nonzero if entire page is blank */
static inline int check_read_ecc(uchar *buf, u32 *eccstat,
unsigned int bufnum, int page_size)
{
u32 reg = eccstat[bufnum / 4];
int errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
if (errors == 15) { /* uncorrectable */
/* Blank pages fail hw ECC checks */
if (is_blank(buf, page_size))
return 1;
puts("ecc error\n");
for (;;)
;
}
return 0;
}
static inline void nand_wait(uchar *buf, int bufnum, int page_size)
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
u32 status;
u32 eccstat[4];
int bufperpage = page_size / 512;
int bufnum_end, i;
bufnum *= bufperpage;
bufnum_end = bufnum + bufperpage - 1;
do {
status = in_be32(&ifc->ifc_nand.nand_evter_stat);
} while (!(status & IFC_NAND_EVTER_STAT_OPC));
if (status & IFC_NAND_EVTER_STAT_FTOER) {
puts("flash time out error\n");
for (;;)
;
}
for (i = bufnum / 4; i <= bufnum_end / 4; i++)
eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
for (i = bufnum; i <= bufnum_end; i++) {
if (check_read_ecc(buf, eccstat, i, page_size))
break;
}
out_be32(&ifc->ifc_nand.nand_evter_stat, status);
}
static inline int bad_block(uchar *marker, int port_size)
{
if (port_size == 8)
return __raw_readb(marker) != 0xff;
else
return __raw_readw((u16 *)marker) != 0xffff;
}
static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
{
struct fsl_ifc *ifc = IFC_BASE_ADDR;
uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
int page_size;
int port_size;
int pages_per_blk;
int blk_size;
int bad_marker = 0;
int bufnum_mask, bufnum;
int csor, cspr;
int pos = 0;
int j = 0;
int sram_addr;
int pg_no;
/* Get NAND Flash configuration */
csor = CONFIG_SYS_NAND_CSOR;
cspr = CONFIG_SYS_NAND_CSPR;
if (!(csor & CSOR_NAND_ECC_DEC_EN)) {
/* soft ECC in SPL is unimplemented */
puts("WARNING: soft ECC not checked in SPL\n");
} else {
u32 hwcsor;
/* make sure board is configured with ECC on boot */
hwcsor = in_be32(&ifc->csor_cs[0].csor);
if (!(hwcsor & CSOR_NAND_ECC_DEC_EN))
puts("WARNING: ECC not checked in SPL, "
"check board cfg\n");
}
port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
if (csor & CSOR_NAND_PGS_4K) {
page_size = 4096;
bufnum_mask = 1;
} else if (csor & CSOR_NAND_PGS_2K) {
page_size = 2048;
bufnum_mask = 3;
} else {
page_size = 512;
bufnum_mask = 15;
if (port_size == 8)
bad_marker = 5;
}
pages_per_blk =
32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
blk_size = pages_per_blk * page_size;
/* Open Full SRAM mapping for spare are access */
out_be32(&ifc->ifc_nand.ncfgr, 0x0);
/* Clear Boot events */
out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
/* Program FIR/FCR for Large/Small page */
if (page_size > 512) {
out_be32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
out_be32(&ifc->ifc_nand.nand_fcr0,
(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
} else {
out_be32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
out_be32(&ifc->ifc_nand.nand_fcr0,
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
}
/* Program FBCR = 0 for full page read */
out_be32(&ifc->ifc_nand.nand_fbcr, 0);
/* Read and copy u-boot on SDRAM from NAND device, In parallel
* check for Bad block if found skip it and read continue to
* next Block
*/
while (pos < uboot_size) {
int i = 0;
do {
pg_no = offs / page_size;
bufnum = pg_no & bufnum_mask;
sram_addr = bufnum * page_size * 2;
out_be32(&ifc->ifc_nand.row0, pg_no);
out_be32(&ifc->ifc_nand.col0, 0);
/* start read */
out_be32(&ifc->ifc_nand.nandseq_strt,
IFC_NAND_SEQ_STRT_FIR_STRT);
/* wait for read to complete */
nand_wait(&buf[sram_addr], bufnum, page_size);
/*
* If either of the first two pages are marked bad,
* continue to the next block.
*/
if (i++ < 2 &&
bad_block(&buf[sram_addr + page_size + bad_marker],
port_size)) {
puts("skipping\n");
offs = (offs + blk_size) & ~(blk_size - 1);
pos &= ~(blk_size - 1);
break;
}
for (j = 0; j < page_size; j++)
dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
pos += page_size;
offs += page_size;
} while ((offs & (blk_size - 1)) && (pos < uboot_size));
}
}
/*
* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
* configured and available since this code loads the main U-boot image
* from NAND into SDRAM and starts from there.
*/
void nand_boot(void)
{
__attribute__((noreturn)) void (*uboot)(void);
/*
* Load U-Boot image from NAND into RAM
*/
nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
#ifdef CONFIG_NAND_ENV_DST
nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_NAND_ENV_DST);
#ifdef CONFIG_ENV_OFFSET_REDUND
nand_load(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
(uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
#endif
#endif
/*
* Jump to U-Boot image
*/
/*
* Clean d-cache and invalidate i-cache, to
* make sure that no stale data is executed.
*/
flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
uboot();
}
|
1001-study-uboot
|
nand_spl/nand_boot_fsl_ifc.c
|
C
|
gpl3
| 7,031
|
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
@rm -f $(obj)init.S
ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S
# from nand_spl directory
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)sdram.c:
@rm -f $(obj)sdram.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $(obj)sdram.c
endif
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
nand_spl/board/amcc/bamboo/Makefile
|
Makefile
|
gpl3
| 3,259
|
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 440EP Reference Platform (Bamboo) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into instruction-cache in start.S. So we set
# CONFIG_SYS_TEXT_BASE to starting address in i-cache here.
#
CONFIG_SYS_TEXT_BASE = 0x00800000
# PAD_TO used to generate a 16kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0x00804000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
|
1001-study-uboot
|
nand_spl/board/amcc/bamboo/config.mk
|
Makefile
|
gpl3
| 1,537
|
/*
* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
static void wait_init_complete(void)
{
u32 val;
do {
mfsdram(SDRAM0_MCSTS, val);
} while (!(val & 0x80000000));
}
/*
* phys_size_t initdram(int board_type)
*
* As the name already indicates, this function is called very early
* from start.S and configures the SDRAM with fixed values. This is needed,
* since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
* not enough free space to implement the complete I2C SPD DDR autodetection
* routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
* when booting from NAND flash.
*
* Note:
* As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
* DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
* modules are still plugged in. So it is recommended to remove the DIMM
* modules while using the NAND booting code with the fixed SDRAM setup!
*/
phys_size_t initdram(int board_type)
{
/*
* Soft-reset SDRAM controller.
*/
mtsdr(SDR0_SRST, SDR0_SRST_DMC);
mtsdr(SDR0_SRST, 0x00000000);
/*
* Disable memory controller.
*/
mtsdram(SDRAM0_CFG0, 0x00000000);
/*
* Setup some default
*/
mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(SDRAM0_B0CR, 0x00082001);
mtsdram(SDRAM0_TR0, 0x41094012);
mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
/*
* Enable the controller, then wait for DCEN to complete
*/
mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
wait_init_complete();
return CONFIG_SYS_MBYTES_SDRAM << 20;
}
|
1001-study-uboot
|
nand_spl/board/amcc/bamboo/sdram.c
|
C
|
gpl3
| 2,954
|
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o cache.o
COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
$(nandobj)System.map
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
$(nandobj)System.map: $(nandobj)u-boot-spl
@$(NM) $< | \
grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
sort > $(nandobj)System.map
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)cache.S:
@rm -f $(obj)cache.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S
$(obj)gpio.c:
@rm -f $(obj)gpio.c
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $(obj)gpio.c
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)memory.c:
@rm -f $(obj)memory.c
ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c
$(obj)pll.c:
@rm -f $(obj)pll.c
ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c
# from nand_spl directory
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
nand_spl/board/amcc/acadia/Makefile
|
Makefile
|
gpl3
| 3,625
|
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 405EZ Reference Platform (Acadia) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into internal SRAM in start.S. So we set
# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
#
CONFIG_SYS_TEXT_BASE = 0xf8004000
# PAD_TO used to generate a 16kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0xf8008000
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
|
1001-study-uboot
|
nand_spl/board/amcc/acadia/config.mk
|
Makefile
|
gpl3
| 1,497
|
#
# (C) Copyright 2006-2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)denali_data_eye.c:
@rm -f $(obj)denali_data_eye.c
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $(obj)denali_data_eye.c
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
@rm -f $(obj)init.S
ln -s $(SRCTREE)/board/amcc/sequoia/init.S $(obj)init.S
$(obj)sdram.c:
@rm -f $(obj)sdram.c
@rm -f $(obj)sdram.h
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $(obj)sdram.c
ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h
# from nand_spl directory
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
nand_spl/board/amcc/sequoia/Makefile
|
Makefile
|
gpl3
| 3,461
|
#
# (C) Copyright 2006
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 440EPx Reference Platform (Sequoia) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into internal SRAM in start.S. So we set
# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
#
CONFIG_SYS_TEXT_BASE = 0xE0013000
# PAD_TO used to generate a 16kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0xE0017000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
|
1001-study-uboot
|
nand_spl/board/amcc/sequoia/config.mk
|
Makefile
|
gpl3
| 1,541
|
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o resetvec.o cache.o
COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)44x_spd_ddr2.c: $(obj)ecc.h
@rm -f $(obj)44x_spd_ddr2.c
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $(obj)44x_spd_ddr2.c
$(obj)cache.S:
@rm -f $(obj)cache.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $(obj)cache.S
$(obj)ecc.h:
@rm -f $(obj)ecc.h
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $(obj)ecc.h
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from nand_spl directory
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
# from drivers/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
nand_spl/board/amcc/kilauea/Makefile
|
Makefile
|
gpl3
| 3,344
|
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 405EX Reference Platform (Kilauea) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into SDRAM since we can't access the NAND
# controller at CS0 while running from this location. So we set
# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here.
#
CONFIG_SYS_TEXT_BASE = 0x00800000
# PAD_TO used to generate a 16kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000
PAD_TO = 0x00804000
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
|
1001-study-uboot
|
nand_spl/board/amcc/kilauea/config.mk
|
Makefile
|
gpl3
| 1,555
|
#
# (C) Copyright 2008
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS := start.o
SOBJS += init.o
SOBJS += resetvec.o
COBJS := ddr2_fixed.o
COBJS += nand_boot.o
COBJS += nand_ecc.o
COBJS += ndfc.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)ndfc.c:
@rm -f $(obj)ndfc.c
ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $(obj)ndfc.c
$(obj)resetvec.S:
@rm -f $(obj)resetvec.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
$(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $(obj)start.S
# from board directory
$(obj)init.S:
@rm -f $(obj)init.S
ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $(obj)init.S
# from nand_spl directory
$(obj)nand_boot.c:
@rm -f $(obj)nand_boot.c
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $(obj)nand_ecc.c
ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $(obj)nand_ecc.c
ifneq ($(OBJTREE), $(SRCTREE))
$(obj)ddr2_fixed.c:
@rm -f $(obj)ddr2_fixed.c
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $(obj)ddr2_fixed.c
endif
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
nand_spl/board/amcc/canyonlands/Makefile
|
Makefile
|
gpl3
| 3,336
|
#
# (C) Copyright 2008
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 460EX Reference Platform (Canyonlands) board
#
#
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff,
# in the last 4kBytes of memory space in cache.
# We will copy this SPL into internal SRAM in start.S. So we set
# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here.
#
CONFIG_SYS_TEXT_BASE = 0xE3003000
# PAD_TO used to generate a 128kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000
PAD_TO = 0xE3023000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
endif
|
1001-study-uboot
|
nand_spl/board/amcc/canyonlands/config.mk
|
Makefile
|
gpl3
| 1,543
|
/*
* (C) Copyright 2008-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/ppc4xx.h>
#include <asm/io.h>
#include <asm/processor.h>
/*
* This code can configure those two Crucial SODIMM's:
*
* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
* Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
*
*/
#define TEST_ADDR 0x10000000
#define TEST_MAGIC 0x11223344
static void wait_init_complete(void)
{
u32 val;
do {
mfsdram(SDRAM_MCSTAT, val);
} while (!(val & 0x80000000));
}
static void ddr_start(void)
{
mtsdram(SDRAM_MCOPT2, 0x28000000);
wait_init_complete();
}
static void ddr_init_common(void)
{
/*
* Reset the DDR-SDRAM controller.
*/
mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
mtsdr(SDR0_SRST, 0x00000000);
/*
* These values are cloned from a running NOR booting
* Canyonlands with SPD-DDR2 detection and calibration
* enabled. This will only work for the same memory
* configuration as used here:
*
*/
mtsdram(SDRAM_MCOPT2, 0x00000000);
mtsdram(SDRAM_MODT0, 0x01000000);
mtsdram(SDRAM_WRDTR, 0x82000823);
mtsdram(SDRAM_CLKTR, 0x40000000);
mtsdram(SDRAM_MB0CF, 0x00000201);
mtsdram(SDRAM_RTR, 0x06180000);
mtsdram(SDRAM_SDTR1, 0x80201000);
mtsdram(SDRAM_SDTR2, 0x42103243);
mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
mtsdram(SDRAM_MMODE, 0x00000632);
mtsdram(SDRAM_MEMODE, 0x00000040);
mtsdram(SDRAM_INITPLR0, 0xB5380000);
mtsdram(SDRAM_INITPLR1, 0x82100400);
mtsdram(SDRAM_INITPLR2, 0x80820000);
mtsdram(SDRAM_INITPLR3, 0x80830000);
mtsdram(SDRAM_INITPLR4, 0x80810040);
mtsdram(SDRAM_INITPLR5, 0x80800532);
mtsdram(SDRAM_INITPLR6, 0x82100400);
mtsdram(SDRAM_INITPLR7, 0x8A080000);
mtsdram(SDRAM_INITPLR8, 0x8A080000);
mtsdram(SDRAM_INITPLR9, 0x8A080000);
mtsdram(SDRAM_INITPLR10, 0x8A080000);
mtsdram(SDRAM_INITPLR11, 0x80000432);
mtsdram(SDRAM_INITPLR12, 0x808103C0);
mtsdram(SDRAM_INITPLR13, 0x80810040);
mtsdram(SDRAM_INITPLR14, 0x00000000);
mtsdram(SDRAM_INITPLR15, 0x00000000);
mtsdram(SDRAM_RDCC, 0x40000000);
mtsdram(SDRAM_RQDC, 0x80000038);
mtsdram(SDRAM_RFDC, 0x00000257);
mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
}
phys_size_t initdram(int board_type)
{
/*
* First try init for this module:
*
* Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
*/
ddr_init_common();
/*
* Crucial CT6464AC667.8FB - 512MB SO-DIMM
*/
mtdcr(SDRAM_R0BAS, 0x0000F800);
mtdcr(SDRAM_R1BAS, 0x0400F800);
mtsdram(SDRAM_MCOPT1, 0x05122000);
mtsdram(SDRAM_CODT, 0x02800021);
mtsdram(SDRAM_MB1CF, 0x00000201);
ddr_start();
/*
* Now test if the dual-ranked module is really installed
* by checking an address in the upper 256MByte region
*/
out_be32((void *)TEST_ADDR, TEST_MAGIC);
if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
/*
* The test failed, so we assume that the single
* ranked module is installed:
*
* Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
*/
ddr_init_common();
mtdcr(SDRAM_R0BAS, 0x0000F000);
mtsdram(SDRAM_MCOPT1, 0x05322000);
mtsdram(SDRAM_CODT, 0x00800021);
ddr_start();
}
return CONFIG_SYS_MBYTES_SDRAM << 20;
}
|
1001-study-uboot
|
nand_spl/board/amcc/canyonlands/ddr2_fixed.c
|
C
|
gpl3
| 3,964
|
#
# (C) Copyright 2006-2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# (C) Copyright 2008
# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
CONFIG_NAND_SPL = y
include $(TOPDIR)/config.mk
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL) -gc-sections
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL -ffunction-sections
SOBJS = start.o cpu_init.o lowlevel_init.o
COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o nand_base.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
# from cpu directory
$(obj)start.S:
@rm -f $@
@ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@
# from SoC directory
$(obj)cpu_init.S:
@rm -f $@
@ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@
# from board directory
$(obj)lowlevel_init.S:
@rm -f $@
@ln -s $(TOPDIR)/board/samsung/smdk6400/lowlevel_init.S $@
# from nand_spl directory
$(obj)nand_boot.c:
@rm -f $@
@ln -s $(TOPDIR)/nand_spl/nand_boot.c $@
# from drivers/mtd/nand directory
$(obj)nand_ecc.c:
@rm -f $@
@ln -s $(TOPDIR)/drivers/mtd/nand/nand_ecc.c $@
$(obj)s3c64xx.c:
@rm -f $@
@ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@
$(obj)smdk6400_nand_spl.c:
@rm -f $@
@ln -s $(TOPDIR)/board/samsung/smdk6400/smdk6400_nand_spl.c $@
$(obj)nand_base.c:
@rm -f $@
@ln -s $(TOPDIR)/drivers/mtd/nand/nand_base.c $@
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
nand_spl/board/samsung/smdk6400/Makefile
|
Makefile
|
gpl3
| 3,367
|
#
# (C) Copyright 2006
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Samsung S3C64xx Reference Platform (smdk6400) board
# CONFIG_SYS_TEXT_BASE for SPL:
#
# On S3C64xx platforms the SPL is located in SRAM at 0.
#
# CONFIG_SYS_TEXT_BASE = 0
include $(TOPDIR)/board/$(BOARDDIR)/config.mk
# PAD_TO used to generate a 4kByte binary needed for the combined image
# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 4096
PAD_TO := $(shell expr $$[$(CONFIG_SYS_TEXT_BASE) + 4096])
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
|
1001-study-uboot
|
nand_spl/board/samsung/smdk6400/config.mk
|
Makefile
|
gpl3
| 1,308
|
#
# (C) Copyright 2007
# Stefan Roese, DENX Software Engineering, sr@denx.de.
# (C) Copyright 2008 Freescale Semiconductor
# (C) Copyright Sheldon Instruments, Inc. 2008
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
NAND_SPL := y
include $(TOPDIR)/config.mk
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o ticks.o
COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o nand_init.o \
time.o cache.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
__OBJS := $(SOBJS) $(COBJS)
LNDIR := $(nandobj)board/$(BOARDDIR)
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
all: $(obj).depend $(ALL)
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
$(nandobj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
# create symbolic links for common files
$(obj)start.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@
$(obj)nand_boot_fsl_elbc.c:
@rm -f $@
ln -s $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@
$(obj)sdram.c:
@rm -f $@
ln -s $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@
$(obj)$(BOARD).c:
@rm -f $@
ln -s $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@
$(obj)ns16550.c:
@rm -f $@
ln -s $(SRCTREE)/drivers/serial/ns16550.c $@
$(obj)nand_init.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/nand_init.c $@
$(obj)cache.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/lib/cache.c $@
$(obj)time.c:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/lib/time.c $@
$(obj)ticks.S:
@rm -f $@
ln -s $(SRCTREE)/arch/powerpc/lib/ticks.S $@
#########################################################################
$(obj)%.o: $(obj)%.S
$(CC) $(AFLAGS) -c -o $@ $<
$(obj)%.o: $(obj)%.c
$(CC) $(CFLAGS) -c -o $@ $<
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
|
1001-study-uboot
|
nand_spl/board/sheldon/simpc8313/Makefile
|
Makefile
|
gpl3
| 3,201
|