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stringlengths 1
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stringlengths 3
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/*
* Header file for AT91/AT32 LCD Controller
*
* Data structure and register user interface
*
* Copyright (C) 2007 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ATMEL_LCDC_H__
#define __ATMEL_LCDC_H__
#define ATMEL_LCDC_DMABADDR1 0x00
#define ATMEL_LCDC_DMABADDR2 0x04
#define ATMEL_LCDC_DMAFRMPT1 0x08
#define ATMEL_LCDC_DMAFRMPT2 0x0c
#define ATMEL_LCDC_DMAFRMADD1 0x10
#define ATMEL_LCDC_DMAFRMADD2 0x14
#define ATMEL_LCDC_DMAFRMCFG 0x18
#define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
#define ATMEL_LCDC_BLENGTH_OFFSET 24
#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
#define ATMEL_LCDC_DMACON 0x1c
#define ATMEL_LCDC_DMAEN (0x1 << 0)
#define ATMEL_LCDC_DMARST (0x1 << 1)
#define ATMEL_LCDC_DMABUSY (0x1 << 2)
#define ATMEL_LCDC_DMAUPDT (0x1 << 3)
#define ATMEL_LCDC_DMA2DEN (0x1 << 4)
#define ATMEL_LCDC_DMA2DCFG 0x20
#define ATMEL_LCDC_ADDRINC_OFFSET 0
#define ATMEL_LCDC_ADDRINC (0xffff)
#define ATMEL_LCDC_PIXELOFF_OFFSET 24
#define ATMEL_LCDC_PIXELOFF (0x1f << 24)
#define ATMEL_LCDC_LCDCON1 0x0800
#define ATMEL_LCDC_BYPASS (1 << 0)
#define ATMEL_LCDC_CLKVAL_OFFSET 12
#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
#define ATMEL_LCDC_LINCNT (0x7ff << 21)
#define ATMEL_LCDC_LCDCON2 0x0804
#define ATMEL_LCDC_DISTYPE (3 << 0)
#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0)
#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0)
#define ATMEL_LCDC_DISTYPE_TFT (2 << 0)
#define ATMEL_LCDC_SCANMOD (1 << 2)
#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2)
#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2)
#define ATMEL_LCDC_IFWIDTH (3 << 3)
#define ATMEL_LCDC_IFWIDTH_4 (0 << 3)
#define ATMEL_LCDC_IFWIDTH_8 (1 << 3)
#define ATMEL_LCDC_IFWIDTH_16 (2 << 3)
#define ATMEL_LCDC_PIXELSIZE (7 << 5)
#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5)
#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5)
#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5)
#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5)
#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5)
#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5)
#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5)
#define ATMEL_LCDC_INVVD (1 << 8)
#define ATMEL_LCDC_INVVD_NORMAL (0 << 8)
#define ATMEL_LCDC_INVVD_INVERTED (1 << 8)
#define ATMEL_LCDC_INVFRAME (1 << 9 )
#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9)
#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9)
#define ATMEL_LCDC_INVLINE (1 << 10)
#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10)
#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10)
#define ATMEL_LCDC_INVCLK (1 << 11)
#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11)
#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11)
#define ATMEL_LCDC_INVDVAL (1 << 12)
#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12)
#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12)
#define ATMEL_LCDC_CLKMOD (1 << 15)
#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
#define ATMEL_LCDC_MEMOR (1 << 31)
#define ATMEL_LCDC_MEMOR_BIG (0 << 31)
#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31)
#define ATMEL_LCDC_TIM1 0x0808
#define ATMEL_LCDC_VFP (0xffU << 0)
#define ATMEL_LCDC_VBP_OFFSET 8
#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET)
#define ATMEL_LCDC_VPW_OFFSET 16
#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET)
#define ATMEL_LCDC_VHDLY_OFFSET 24
#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET)
#define ATMEL_LCDC_TIM2 0x080c
#define ATMEL_LCDC_HBP (0xffU << 0)
#define ATMEL_LCDC_HPW_OFFSET 8
#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET)
#define ATMEL_LCDC_HFP_OFFSET 21
#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET)
#define ATMEL_LCDC_LCDFRMCFG 0x0810
#define ATMEL_LCDC_LINEVAL (0x7ff << 0)
#define ATMEL_LCDC_HOZVAL_OFFSET 21
#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
#define ATMEL_LCDC_FIFO 0x0814
#define ATMEL_LCDC_FIFOTH (0xffff)
#define ATMEL_LCDC_MVAL 0x0818
#define ATMEL_LCDC_DP1_2 0x081c
#define ATMEL_LCDC_DP4_7 0x0820
#define ATMEL_LCDC_DP3_5 0x0824
#define ATMEL_LCDC_DP2_3 0x0828
#define ATMEL_LCDC_DP5_7 0x082c
#define ATMEL_LCDC_DP3_4 0x0830
#define ATMEL_LCDC_DP4_5 0x0834
#define ATMEL_LCDC_DP6_7 0x0838
#define ATMEL_LCDC_DP1_2_VAL (0xff)
#define ATMEL_LCDC_DP4_7_VAL (0xfffffff)
#define ATMEL_LCDC_DP3_5_VAL (0xfffff)
#define ATMEL_LCDC_DP2_3_VAL (0xfff)
#define ATMEL_LCDC_DP5_7_VAL (0xfffffff)
#define ATMEL_LCDC_DP3_4_VAL (0xffff)
#define ATMEL_LCDC_DP4_5_VAL (0xfffff)
#define ATMEL_LCDC_DP6_7_VAL (0xfffffff)
#define ATMEL_LCDC_PWRCON 0x083c
#define ATMEL_LCDC_PWR (1 << 0)
#define ATMEL_LCDC_GUARDT_OFFSET 1
#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET)
#define ATMEL_LCDC_BUSY (1 << 31)
#define ATMEL_LCDC_CONTRAST_CTR 0x0840
#define ATMEL_LCDC_PS (3 << 0)
#define ATMEL_LCDC_PS_DIV1 (0 << 0)
#define ATMEL_LCDC_PS_DIV2 (1 << 0)
#define ATMEL_LCDC_PS_DIV4 (2 << 0)
#define ATMEL_LCDC_PS_DIV8 (3 << 0)
#define ATMEL_LCDC_POL (1 << 2)
#define ATMEL_LCDC_POL_NEGATIVE (0 << 2)
#define ATMEL_LCDC_POL_POSITIVE (1 << 2)
#define ATMEL_LCDC_ENA (1 << 3)
#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3)
#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3)
#define ATMEL_LCDC_CONTRAST_VAL 0x0844
#define ATMEL_LCDC_CVAL (0xff)
#define ATMEL_LCDC_IER 0x0848
#define ATMEL_LCDC_IDR 0x084c
#define ATMEL_LCDC_IMR 0x0850
#define ATMEL_LCDC_ISR 0x0854
#define ATMEL_LCDC_ICR 0x0858
#define ATMEL_LCDC_LNI (1 << 0)
#define ATMEL_LCDC_LSTLNI (1 << 1)
#define ATMEL_LCDC_EOFI (1 << 2)
#define ATMEL_LCDC_UFLWI (1 << 4)
#define ATMEL_LCDC_OWRI (1 << 5)
#define ATMEL_LCDC_MERI (1 << 6)
#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4))
#endif /* __ATMEL_LCDC_H__ */
|
1001-study-uboot
|
include/atmel_lcdc.h
|
C
|
gpl3
| 6,265
|
/*
* config_defaults.h - sane defaults for everyone
*
* Copyright (c) 2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _CONFIG_DEFAULTS_H_
#define _CONFIG_DEFAULTS_H_
/* Support bootm-ing different OSes */
#define CONFIG_BOOTM_LINUX 1
#define CONFIG_BOOTM_NETBSD 1
#define CONFIG_BOOTM_RTEMS 1
#define CONFIG_GZIP 1
#define CONFIG_ZLIB 1
#define CONFIG_PARTITIONS 1
#endif
|
1001-study-uboot
|
include/config_defaults.h
|
C
|
gpl3
| 409
|
/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $
* include/linux/linux_logo.h: This is a linux logo
* to be displayed on boot.
*
* Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu)
* Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
*
* You can put anything here, but:
* LINUX_LOGO_COLORS has to be less than 224
* image size has to be 80x80
* values have to start from 0x20
* (i.e. RGB(linux_logo_red[0],
* linux_logo_green[0],
* linux_logo_blue[0]) is color 0x20)
* BW image has to be 80x80 as well, with MS bit
* on the left
* Serial_console ascii image can be any size,
* but should contain %s to display the version
*/
#if LINUX_LOGO_COLORS == 214
unsigned char linux_logo_red[] __initdata = {
0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9,
0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6,
0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2,
0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54,
0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74,
0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E,
0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38,
0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3,
0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA,
0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC,
0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B,
0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52,
0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2,
0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6,
0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF,
0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46,
0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6,
0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA,
0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E,
0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7,
0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4,
0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA,
0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59,
0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB,
0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6,
0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72,
0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4
};
unsigned char linux_logo_green[] __initdata = {
0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5,
0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86,
0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96,
0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54,
0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74,
0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42,
0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24,
0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C,
0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2,
0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D,
0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E,
0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A,
0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE,
0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE,
0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB,
0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E,
0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E,
0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A,
0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62,
0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6,
0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA,
0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6,
0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45,
0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92,
0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA,
0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56,
0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE
};
unsigned char linux_logo_blue[] __initdata = {
0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7,
0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20,
0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40,
0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56,
0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74,
0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11,
0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A,
0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11,
0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C,
0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C,
0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E,
0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C,
0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94,
0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC,
0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91,
0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C,
0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C,
0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74,
0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04,
0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2,
0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10,
0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C,
0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E,
0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C,
0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C,
0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24,
0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7
};
unsigned char linux_logo[] __initdata = {
0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C,
0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95,
0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C,
0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6,
0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55,
0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A,
0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1,
0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95,
0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6,
0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A,
0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95,
0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB,
0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C,
0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C,
0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C,
0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6,
0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C,
0x2C, 0x95, 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55,
0x55, 0xCB, 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6,
0xA1, 0x2C, 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6,
0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1, 0x2C, 0x95,
0x55, 0x55, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x70,
0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
0x95, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
0x95, 0x55, 0xCB, 0x95, 0xD6, 0xA1, 0x2C, 0x95,
0xA1, 0xD6, 0xD6, 0xA1, 0xA1, 0xD6, 0xA1, 0xA1,
0xA1, 0x2C, 0x90, 0x47, 0x47, 0x70, 0x2C, 0xA1,
0x2C, 0x95, 0x55, 0x55, 0x90, 0xCB, 0x55, 0x55,
0x55, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xD6, 0xD6,
0xA1, 0x2C, 0x95, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0xCB,
0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C,
0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
0x55, 0x55, 0x2C, 0x3F, 0x80, 0x20, 0x88, 0x88,
0x88, 0x20, 0x88, 0xB1, 0x2C, 0xA1, 0x2C, 0x2C,
0x95, 0xCB, 0x94, 0xA0, 0x47, 0x55, 0x2C, 0xD6,
0xA1, 0x95, 0x55, 0x55, 0xCB, 0xCB, 0x55, 0x55,
0xCB, 0xCB, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6,
0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x2C, 0x94, 0x80, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x88, 0x92, 0xA1, 0x95,
0x55, 0x90, 0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6,
0xA1, 0x2C, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x55,
0x55, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xD6, 0xA1,
0x2C, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95,
0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
0xA1, 0xD6, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x55,
0x55, 0x55, 0x95, 0x95, 0x2C, 0x95, 0x95, 0xD6,
0xB1, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0x80, 0x34, 0x88, 0x43, 0x47,
0x95, 0xCB, 0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
0xA1, 0x95, 0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55,
0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
0x55, 0x55, 0x55, 0x55, 0x2C, 0x95, 0x2C, 0x2C,
0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
0x90, 0x70, 0x90, 0x55, 0x95, 0x95, 0xA1, 0xA1,
0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x95,
0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD5,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x88, 0x7D, 0x3F, 0xB1, 0x80, 0x20,
0x99, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0xA1, 0xA1,
0x2C, 0x55, 0x90, 0x70, 0x90, 0x55, 0x95, 0x95,
0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1, 0x95, 0xCB,
0x70, 0x94, 0x90, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
0x2C, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x88,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0xB1, 0x47, 0xD5, 0x7D, 0x43,
0x20, 0x70, 0x95, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
0x95, 0xCB, 0x70, 0x94, 0x90, 0x55, 0x95, 0xA1,
0xA1, 0xA1, 0x2C, 0x95, 0x2C, 0x2C, 0x95, 0x95,
0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
0x95, 0x90, 0x55, 0x2C, 0xD6, 0xD6, 0x2C, 0x90,
0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6, 0xD6, 0xA1,
0x95, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x55,
0xCB, 0xCB, 0xCB, 0x55, 0xCB, 0x55, 0x47, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x88, 0xB1, 0x3F, 0x92, 0x2B, 0x80,
0x20, 0x80, 0xD6, 0x70, 0x55, 0x2C, 0xD6, 0xD6,
0x2C, 0x90, 0x94, 0x70, 0x55, 0x95, 0x2C, 0xD6,
0xD6, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x95,
0x95, 0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55,
0xD6, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x55, 0x70,
0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x95,
0x55, 0x55, 0x55, 0x95, 0x55, 0x55, 0xCB, 0x90,
0x70, 0x90, 0xCB, 0x55, 0x55, 0xA1, 0xD8, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x88, 0xD8, 0xE1, 0x88, 0x20, 0x20,
0x88, 0x88, 0xE6, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
0x55, 0x70, 0x94, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
0xA1, 0x95, 0x55, 0x55, 0x95, 0x95, 0x55, 0x55,
0x90, 0x90, 0x90, 0x90, 0xCB, 0x55, 0x55, 0x55,
0xD6, 0x2C, 0xA1, 0xD6, 0xD6, 0xA1, 0xCB, 0x70,
0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x55,
0xCB, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55,
0x55, 0x95, 0x2C, 0x95, 0x2C, 0xD6, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x80, 0xD6, 0xA1, 0xD6, 0xD6, 0xA1,
0xCB, 0x70, 0x70, 0x95, 0x2C, 0xA1, 0xA1, 0x2C,
0x2C, 0x55, 0xCB, 0xCB, 0x55, 0x55, 0x55, 0x55,
0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x94,
0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95, 0xCB, 0x55,
0x90, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x95, 0xA1,
0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x95, 0x20, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x88, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x88, 0x95, 0xA1, 0xA1, 0xA1, 0x55,
0x70, 0x94, 0xCB, 0x95, 0xA1, 0xA1, 0x2C, 0x95,
0xCB, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0x55, 0x55,
0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
0x2C, 0x2C, 0x2C, 0x95, 0x95, 0xCB, 0x70, 0x70,
0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x70, 0x90, 0xCB,
0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x2C, 0xD6,
0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x70, 0x20, 0x20,
0x88, 0x43, 0xD8, 0x43, 0x20, 0x20, 0x20, 0x20,
0x20, 0x88, 0x88, 0x43, 0x2B, 0xD8, 0x20, 0x20,
0x20, 0x20, 0x20, 0x3F, 0x2C, 0x95, 0x95, 0xCB,
0x70, 0x70, 0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90,
0x90, 0xCB, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x95,
0x2C, 0xD6, 0xD6, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C,
0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x90, 0x55,
0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70, 0x55, 0x95,
0x95, 0xCB, 0x90, 0x90, 0x90, 0x95, 0x2C, 0xA1,
0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x70, 0x20, 0x20,
0x80, 0x2B, 0x34, 0x2B, 0x88, 0x20, 0x20, 0x20,
0x88, 0xB1, 0x28, 0x28, 0x2B, 0x7D, 0x80, 0x20,
0x20, 0x20, 0x20, 0x92, 0x95, 0x55, 0xCB, 0x70,
0x90, 0x55, 0x2C, 0x2C, 0x2C, 0x55, 0x70, 0x70,
0x55, 0x95, 0x55, 0x55, 0x90, 0x90, 0x90, 0x55,
0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x95,
0xA1, 0x95, 0x55, 0xCB, 0x90, 0x70, 0xCB, 0x95,
0xA1, 0x95, 0x95, 0xCB, 0x90, 0xCB, 0x95, 0x2C,
0x95, 0x70, 0x70, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
0x2C, 0x2C, 0x55, 0xCB, 0x55, 0x90, 0x20, 0x34,
0x90, 0x6D, 0x70, 0xD8, 0x43, 0x20, 0x20, 0x88,
0x3F, 0x55, 0xA1, 0x2A, 0xD6, 0x7D, 0x43, 0x20,
0x20, 0x20, 0x88, 0x7D, 0x55, 0xCB, 0x90, 0x70,
0xCB, 0x95, 0xA1, 0x95, 0x95, 0xCB, 0x70, 0xCB,
0x95, 0xA1, 0x95, 0x70, 0x70, 0xCB, 0x55, 0x2C,
0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
0x2C, 0x55, 0x90, 0x70, 0x94, 0x90, 0x95, 0x2C,
0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95, 0xA1, 0xA1,
0x95, 0x90, 0x90, 0x95, 0xA1, 0xD6, 0xD6, 0x6D,
0xA1, 0x95, 0x55, 0xCB, 0x55, 0xCB, 0x20, 0x99,
0xBF, 0xA3, 0xA3, 0x90, 0x20, 0x20, 0x20, 0x92,
0x83, 0x6B, 0x6B, 0x6B, 0xA3, 0x70, 0x88, 0x20,
0x20, 0x20, 0x20, 0x2B, 0x90, 0x70, 0x94, 0x90,
0x95, 0x2C, 0x2C, 0x95, 0xCB, 0x90, 0x55, 0x95,
0xA1, 0x2C, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xD6,
0xD6, 0x6D, 0xA1, 0x95, 0x55, 0xCB, 0x55, 0x55,
0x2C, 0x55, 0x70, 0x70, 0x94, 0x90, 0x95, 0x2C,
0x2C, 0x55, 0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x2C,
0x55, 0x55, 0x95, 0xA1, 0x6D, 0xBF, 0x6D, 0xD6,
0x95, 0x55, 0x90, 0xCB, 0x55, 0x95, 0x88, 0x95,
0x2C, 0x3F, 0x6D, 0x6B, 0x34, 0x20, 0x20, 0x47,
0x65, 0xD6, 0xE1, 0x3F, 0x2A, 0x6B, 0x2B, 0x20,
0x20, 0x20, 0x20, 0x43, 0x70, 0x70, 0x94, 0x90,
0x95, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x95, 0x2C,
0xA1, 0x2C, 0x55, 0xCB, 0x95, 0xA1, 0x6D, 0xBF,
0x6D, 0xD6, 0x2C, 0x55, 0x90, 0xCB, 0x95, 0x95,
0x95, 0x55, 0x70, 0x94, 0x70, 0x55, 0x2C, 0xA1,
0x2C, 0x55, 0xCB, 0x55, 0x2C, 0x95, 0x2C, 0x95,
0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6, 0x95,
0x70, 0x94, 0x94, 0x70, 0x55, 0x55, 0x20, 0xBF,
0xC9, 0xB1, 0x99, 0x42, 0xB1, 0x61, 0x7D, 0x94,
0x65, 0xB1, 0x88, 0x99, 0xD5, 0xE5, 0x7F, 0x20,
0x20, 0x20, 0x20, 0x43, 0x70, 0x94, 0x70, 0x55,
0x2C, 0xA1, 0x2C, 0x55, 0x90, 0x55, 0x2C, 0x95,
0x2C, 0x95, 0x95, 0x2C, 0xA1, 0x6D, 0xBF, 0xBF,
0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
0x55, 0xCB, 0x70, 0x94, 0x70, 0x95, 0xA1, 0xA1,
0x95, 0x55, 0x55, 0x95, 0x2C, 0x95, 0x95, 0x95,
0x95, 0xA1, 0x6D, 0x2A, 0x2A, 0xD6, 0x55, 0x94,
0xE6, 0xE6, 0x47, 0x70, 0x55, 0x95, 0x20, 0x2A,
0xD8, 0x43, 0xC9, 0x83, 0x98, 0x79, 0x34, 0x9F,
0x6B, 0x43, 0x20, 0x88, 0x2B, 0x65, 0xA0, 0x20,
0x20, 0x20, 0x20, 0xE1, 0x70, 0x94, 0x70, 0x95,
0xA1, 0xA1, 0x95, 0x55, 0x55, 0x95, 0x2C, 0x95,
0x95, 0x95, 0x95, 0xA1, 0x6D, 0xBF, 0x2A, 0xD6,
0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
0x94, 0x70, 0x94, 0x47, 0x70, 0x95, 0x2C, 0x2C,
0x95, 0xCB, 0x95, 0x2C, 0x2C, 0xA1, 0x2C, 0x2C,
0xA1, 0xD6, 0x6D, 0x6D, 0xA1, 0xCB, 0x47, 0x28,
0xE6, 0x47, 0x70, 0x55, 0x95, 0xA1, 0x20, 0x2C,
0x7F, 0x88, 0xF0, 0xC6, 0x25, 0x5E, 0xCF, 0x2F,
0xE7, 0x9A, 0x20, 0x88, 0x99, 0x65, 0x3F, 0x20,
0x20, 0x20, 0x20, 0x34, 0x94, 0x47, 0x70, 0x95,
0xA1, 0x2C, 0x55, 0xCB, 0x95, 0x2C, 0x2C, 0xA1,
0x2C, 0x2C, 0xA1, 0xD6, 0x6D, 0x6D, 0xA1, 0xCB,
0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95,
0x47, 0x70, 0x90, 0x94, 0x70, 0x95, 0xA1, 0x2C,
0x55, 0x55, 0x2C, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C,
0xA1, 0x6D, 0x2A, 0xD6, 0x55, 0x47, 0x28, 0x28,
0x47, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0x20, 0x28,
0xEC, 0x86, 0xBE, 0x48, 0x3E, 0x3E, 0x3A, 0x25,
0x4E, 0xAE, 0x93, 0xD7, 0xEC, 0xD1, 0x34, 0x20,
0x20, 0x20, 0x20, 0x43, 0x55, 0x94, 0x70, 0x95,
0xA1, 0xA1, 0x55, 0xCB, 0x2C, 0xA1, 0xA1, 0xA1,
0xA1, 0x2C, 0xA1, 0x6D, 0x6D, 0xD6, 0x55, 0x47,
0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C,
0x95, 0x95, 0x55, 0x90, 0xCB, 0x2C, 0xA1, 0xA1,
0x55, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0xA1, 0x2C,
0xD6, 0x6D, 0x6D, 0xA1, 0x70, 0x28, 0xD5, 0xE6,
0x70, 0x55, 0x95, 0x2C, 0xA1, 0xD6, 0x20, 0xE1,
0x26, 0x84, 0x76, 0x73, 0x9C, 0x22, 0x4E, 0x35,
0x8C, 0x7A, 0x4E, 0xDC, 0x8E, 0x7E, 0x3D, 0x88,
0x20, 0x20, 0x20, 0x88, 0x2C, 0x90, 0x90, 0x95,
0xA1, 0x2C, 0x55, 0x55, 0x2C, 0xD6, 0xD6, 0xD6,
0x2C, 0x2C, 0xD6, 0x2A, 0x6D, 0x2C, 0x70, 0x28,
0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1,
0xBF, 0xA1, 0x95, 0xCB, 0xCB, 0x2C, 0xA1, 0xA1,
0x95, 0x95, 0xA1, 0xD6, 0xD6, 0xA1, 0x2C, 0x95,
0xD6, 0x6D, 0xD6, 0x95, 0x94, 0x28, 0xE6, 0x70,
0x55, 0x95, 0xA1, 0xA1, 0xA1, 0xD6, 0x20, 0x57,
0xE4, 0xDF, 0x50, 0x3E, 0x22, 0x4E, 0x35, 0x8C,
0x8C, 0x52, 0x52, 0x7A, 0x4E, 0x58, 0xD7, 0x20,
0x20, 0x20, 0x20, 0x88, 0x2C, 0xCB, 0x55, 0x2C,
0xA1, 0xA1, 0x95, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
0x2C, 0x95, 0xA1, 0x6D, 0x6D, 0x95, 0x47, 0xA0,
0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1,
0xD2, 0x95, 0x55, 0x90, 0x55, 0x2C, 0xD6, 0xA1,
0x95, 0x95, 0xA1, 0xD6, 0xD6, 0x2C, 0x95, 0x2C,
0xA1, 0x6D, 0xA1, 0x55, 0x94, 0x47, 0x94, 0xCB,
0x55, 0x95, 0x2C, 0xA1, 0xD6, 0xD6, 0x59, 0xC8,
0xE3, 0x76, 0x2D, 0x3E, 0x22, 0x4E, 0x8C, 0x35,
0x52, 0x52, 0xEE, 0x3A, 0x4D, 0xED, 0x24, 0x20,
0x20, 0x20, 0x20, 0x20, 0x28, 0xCB, 0x55, 0x2C,
0xD6, 0xA1, 0x95, 0x95, 0xA1, 0xD6, 0xA1, 0x2C,
0x95, 0x2C, 0xD6, 0x6D, 0xA1, 0x55, 0x94, 0xE6,
0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
0xD0, 0x94, 0x94, 0x90, 0x55, 0x2C, 0xA1, 0xA1,
0x55, 0x95, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x2C,
0xA1, 0xD6, 0x2C, 0x70, 0x94, 0x94, 0x94, 0x94,
0x70, 0x55, 0xA1, 0xD6, 0xA1, 0xD6, 0x88, 0x77,
0x38, 0xC4, 0x3E, 0x69, 0x4E, 0x35, 0x8C, 0xEE,
0x35, 0x89, 0x30, 0x30, 0x4A, 0x48, 0x3C, 0x20,
0x20, 0x88, 0x20, 0x20, 0xD8, 0x2C, 0x55, 0x2C,
0xD6, 0xA1, 0x95, 0x95, 0x2C, 0xD6, 0xA1, 0x2C,
0x95, 0x2C, 0xA1, 0xD6, 0x2C, 0x90, 0x94, 0x47,
0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C,
0x95, 0x55, 0x95, 0xA1, 0xD6, 0xA1, 0x2C, 0x2C,
0xA1, 0xA1, 0x55, 0x70, 0x94, 0x47, 0x94, 0x94,
0x70, 0x2C, 0xD6, 0xD6, 0x2C, 0xA1, 0x43, 0x98,
0x54, 0x48, 0x3E, 0x22, 0x35, 0xEE, 0xEE, 0x9C,
0x4D, 0x45, 0x75, 0x4A, 0xDF, 0x7B, 0x3D, 0x20,
0xD8, 0x28, 0x2B, 0x88, 0x20, 0x95, 0x95, 0x2C,
0xA1, 0x2C, 0x55, 0x55, 0x2C, 0xA1, 0xD6, 0xA1,
0x2C, 0x95, 0xA1, 0x2C, 0x55, 0x70, 0x94, 0x94,
0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95,
0x70, 0x28, 0x47, 0x55, 0x95, 0x2C, 0x2C, 0x2C,
0x95, 0x95, 0x95, 0xA1, 0xA1, 0xA1, 0x95, 0x55,
0x95, 0x95, 0x55, 0x70, 0x70, 0x70, 0x94, 0x70,
0x55, 0xD6, 0x6D, 0xD6, 0x95, 0x2C, 0x20, 0x43,
0xBB, 0xC8, 0x36, 0x30, 0x30, 0x38, 0x45, 0x6E,
0xE3, 0x75, 0x78, 0x37, 0xBD, 0xD9, 0x3F, 0x20,
0x88, 0xD5, 0x70, 0xB1, 0x88, 0xA0, 0x95, 0x2C,
0x2C, 0xA1, 0x95, 0x55, 0x95, 0xA1, 0xA1, 0xA1,
0x2C, 0x55, 0x95, 0x2C, 0x55, 0x70, 0x70, 0x70,
0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
0x94, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C, 0x55,
0x55, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0x95,
0xA1, 0x6D, 0x4B, 0xD6, 0x55, 0xD6, 0x20, 0xD8,
0xD6, 0x67, 0xDA, 0x4D, 0xED, 0x62, 0x78, 0x78,
0x23, 0x84, 0x67, 0xF5, 0x4B, 0xBF, 0x90, 0x88,
0x88, 0x2B, 0x47, 0x99, 0x20, 0x43, 0xD6, 0x2C,
0x2C, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
0x95, 0x95, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x95,
0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
0x6D, 0x2A, 0x2A, 0xA1, 0x55, 0x55, 0x20, 0xD8,
0x6D, 0xAB, 0x96, 0x7E, 0x64, 0x53, 0x36, 0x36,
0xC6, 0x63, 0x6D, 0xD0, 0x6B, 0xE5, 0xA3, 0x7D,
0x20, 0x88, 0x80, 0x88, 0x20, 0x20, 0xC9, 0xA1,
0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1,
0x95, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
0xA1, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x95,
0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
0x6D, 0x6D, 0xA1, 0x55, 0x2C, 0xD8, 0x20, 0xB1,
0xA3, 0x4B, 0x6D, 0xD9, 0xA7, 0x6C, 0xAF, 0xB2,
0x6D, 0x2A, 0x83, 0x42, 0xE5, 0xE5, 0x65, 0x2C,
0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x88, 0x95,
0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55,
0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x95, 0x2C,
0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95,
0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xA1,
0xA1, 0x2C, 0x55, 0x55, 0x28, 0x88, 0x43, 0x2A,
0xE5, 0xA3, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D, 0x6D,
0xBF, 0xA3, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0x65,
0xB1, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0xD8,
0xD6, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x2C,
0x95, 0x95, 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1,
0xA1, 0xA1, 0xA1, 0x2C, 0x95, 0x90, 0x90, 0x55,
0x90, 0xCB, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95,
0x2C, 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x55,
0x55, 0xCB, 0x55, 0x2C, 0x95, 0x95, 0x95, 0x95,
0x55, 0x90, 0x90, 0x90, 0xE1, 0x43, 0x28, 0xE5,
0xE5, 0x65, 0xD0, 0x6D, 0x6D, 0x6D, 0x2A, 0xD2,
0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xD6, 0x20, 0x20, 0x20, 0x20, 0x20, 0x88, 0x88,
0xD5, 0x2C, 0x2C, 0x2C, 0x95, 0x55, 0x95, 0x95,
0x95, 0x55, 0x55, 0xCB, 0x55, 0x95, 0x2C, 0x95,
0x95, 0x95, 0x55, 0x90, 0x70, 0x70, 0x70, 0x90,
0x70, 0x70, 0xCB, 0x55, 0x55, 0x95, 0x95, 0x95,
0x2C, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0xCB,
0x70, 0x70, 0x70, 0xCB, 0x90, 0x90, 0x70, 0x94,
0x94, 0x94, 0x2C, 0x80, 0x20, 0xE1, 0xA3, 0xE5,
0xE5, 0xE5, 0x42, 0xEC, 0xD0, 0x83, 0xA3, 0x65,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0x65, 0x7D, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x88, 0x2C, 0x95, 0x95, 0x95, 0x55, 0x55, 0x55,
0x55, 0xCB, 0x70, 0x70, 0x90, 0x90, 0x90, 0x90,
0x70, 0x94, 0x94, 0x94, 0x70, 0x70, 0x70, 0x70,
0x70, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95, 0x95,
0x2C, 0x2C, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55,
0x90, 0x70, 0x90, 0x55, 0x55, 0xCB, 0x70, 0x94,
0x94, 0x95, 0xD8, 0x20, 0x88, 0x70, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0x47, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0xE1, 0x6D, 0x2C, 0x95, 0x55, 0x55, 0x55,
0x55, 0x55, 0x90, 0x70, 0x70, 0x55, 0x55, 0xCB,
0x70, 0x94, 0x94, 0x94, 0x70, 0x90, 0x70, 0x94,
0x55, 0x2C, 0x2C, 0x2C, 0x95, 0x2C, 0x95, 0x95,
0x2C, 0x2C, 0x2C, 0x55, 0x55, 0x55, 0x55, 0x55,
0xCB, 0xCB, 0x95, 0x2C, 0x2C, 0x95, 0x55, 0x90,
0x55, 0x99, 0x20, 0x20, 0xE1, 0xA3, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xD6, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x2B, 0x6D, 0x95, 0x95, 0x55, 0x55,
0x55, 0x55, 0xCB, 0x55, 0x95, 0x2C, 0x2C, 0x95,
0x55, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x90, 0x70,
0x2C, 0xD6, 0xD6, 0x2C, 0x2C, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x55, 0x95,
0xE6, 0x88, 0x20, 0x20, 0x3F, 0xA3, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0x42, 0xA3, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x20, 0x88, 0x2B, 0xD6, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x95,
0x55, 0x55, 0x95, 0x95, 0x95, 0x55, 0x55, 0x55,
0xA1, 0xD6, 0xD6, 0xA1, 0x2C, 0x2C, 0x95, 0x2C,
0x2C, 0x2C, 0x95, 0x2C, 0x95, 0x95, 0x55, 0x95,
0x95, 0x2C, 0x2C, 0x2C, 0x95, 0xCB, 0xCB, 0x94,
0x20, 0x20, 0x20, 0x20, 0xE6, 0x83, 0x65, 0xE5,
0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0x6B, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0x6B, 0xA3, 0xD2,
0xD2, 0x6B, 0xC9, 0x20, 0x20, 0x88, 0x20, 0x20,
0x20, 0x20, 0x20, 0x88, 0x8A, 0xA1, 0x95, 0x95,
0x95, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95, 0xCB,
0xCB, 0x55, 0x95, 0x95, 0x95, 0x55, 0x55, 0x95,
0x6D, 0x6D, 0x6D, 0xD6, 0xA1, 0x2C, 0x2C, 0x95,
0x2C, 0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x55, 0x70, 0x70, 0x2C, 0x80,
0x88, 0x20, 0x20, 0x80, 0x94, 0xD6, 0x32, 0x6B,
0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xA3, 0xD2, 0xD0, 0xBF, 0x2A,
0x2A, 0xD0, 0x6D, 0x34, 0x20, 0xE1, 0x88, 0x20,
0x20, 0x20, 0x20, 0x20, 0x88, 0xA1, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0x55, 0x70, 0x70,
0x70, 0x90, 0xCB, 0xCB, 0xCB, 0x95, 0x95, 0x2C,
0xD0, 0x6D, 0xD6, 0xD6, 0xA1, 0xA1, 0xA1, 0x2C,
0x2C, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x55, 0x95,
0x95, 0x2C, 0x95, 0x55, 0xCB, 0xCB, 0x95, 0x88,
0x20, 0x20, 0x88, 0xD8, 0x2C, 0xD1, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x42, 0x6B, 0xEC,
0xBF, 0x2A, 0xEC, 0x95, 0x20, 0x34, 0x2B, 0xE1,
0x20, 0x20, 0x20, 0x20, 0x20, 0x99, 0x95, 0x55,
0x55, 0x55, 0x95, 0x95, 0x95, 0x55, 0xCB, 0xCB,
0x55, 0x55, 0xCB, 0xCB, 0xCB, 0x55, 0x95, 0x95,
0x32, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
0xA1, 0x95, 0x95, 0x95, 0x55, 0xCB, 0xCB, 0x55,
0x95, 0x95, 0x95, 0x95, 0x95, 0x55, 0x99, 0x20,
0xE1, 0xE1, 0x43, 0x47, 0x6B, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0x42, 0xEC, 0xBF, 0xA3, 0x8A, 0x20, 0x88, 0xD8,
0x2B, 0x20, 0x20, 0x20, 0x88, 0x88, 0x2C, 0xCB,
0xCB, 0x95, 0x95, 0x2C, 0x95, 0x95, 0x55, 0x95,
0x55, 0x55, 0x55, 0x55, 0x55, 0x95, 0x55, 0x95,
0x6D, 0x55, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x95,
0x2C, 0x95, 0x95, 0x55, 0x55, 0x55, 0x55, 0x95,
0x95, 0x95, 0x95, 0x95, 0x95, 0xA1, 0x34, 0x20,
0xC9, 0x20, 0xE1, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xA3, 0x83, 0x6D, 0x20, 0x88, 0x88,
0x2B, 0x34, 0x20, 0x20, 0x20, 0x88, 0xD5, 0x55,
0x55, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
0x95, 0x95, 0x95, 0x95, 0x55, 0x55, 0x95, 0x95,
0x2C, 0x55, 0xCB, 0x55, 0xCB, 0x55, 0x55, 0x95,
0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C,
0x2C, 0x95, 0x95, 0x55, 0x95, 0x2C, 0x20, 0xD8,
0xE1, 0x20, 0x70, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0x65, 0xA3, 0x92, 0x43, 0x7D,
0xD8, 0xC9, 0x88, 0x20, 0x20, 0x20, 0x43, 0xD6,
0x2C, 0x2C, 0x95, 0x95, 0x95, 0x55, 0x95, 0x2C,
0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95, 0x2C,
0xA1, 0x55, 0x55, 0x55, 0x55, 0x95, 0x95, 0x55,
0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0xA1, 0x2C,
0xA1, 0x2C, 0x2C, 0x95, 0x2C, 0x99, 0x88, 0xB1,
0x20, 0xD8, 0x42, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x34, 0x8A,
0xC9, 0x34, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x90,
0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x95, 0x95, 0x2C,
0x2C, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
0xD6, 0x2C, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C,
0x55, 0xCB, 0x55, 0x2C, 0x2C, 0xA1, 0x2C, 0xA1,
0xA1, 0xA1, 0x2C, 0x2C, 0x6D, 0x43, 0xD8, 0x80,
0x88, 0xCB, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x32, 0x80, 0xE1,
0x80, 0x20, 0xB1, 0x20, 0x20, 0x20, 0x20, 0xC9,
0xD6, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1, 0x2C, 0x2C,
0x2C, 0x55, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55,
0xD6, 0x95, 0x95, 0x95, 0x2C, 0xA1, 0x2C, 0x2C,
0x95, 0x95, 0x95, 0x95, 0x95, 0x2C, 0x95, 0x2C,
0x2C, 0x2C, 0x2C, 0x95, 0xCB, 0x20, 0xC9, 0x20,
0xE1, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xD8, 0x20,
0x20, 0x20, 0x2B, 0x43, 0x20, 0x20, 0x20, 0x88,
0xD6, 0x2C, 0x2C, 0x2C, 0x95, 0x95, 0x95, 0x55,
0x95, 0x55, 0x55, 0xCB, 0x55, 0xCB, 0xCB, 0x55,
0x2C, 0x55, 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0x95,
0x55, 0x95, 0x55, 0x95, 0x95, 0x95, 0x95, 0x95,
0x55, 0xCB, 0x70, 0xCB, 0xC9, 0x80, 0x2B, 0x20,
0xA0, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0x42, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x92, 0x20,
0x20, 0x20, 0xE1, 0xD8, 0x20, 0x20, 0x20, 0x20,
0x95, 0x95, 0x55, 0xCB, 0x90, 0x90, 0x70, 0x90,
0x90, 0x90, 0xCB, 0xCB, 0xCB, 0xCB, 0x55, 0x95,
0x95, 0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
0x95, 0x95, 0x55, 0x55, 0x55, 0x95, 0x95, 0x55,
0x90, 0x47, 0xA0, 0x55, 0x20, 0x2B, 0x43, 0x88,
0x6D, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x28, 0x20,
0x20, 0x20, 0xE1, 0xE1, 0x20, 0x20, 0x20, 0x20,
0x28, 0x55, 0x90, 0x47, 0xA0, 0x47, 0x94, 0x70,
0x55, 0x95, 0x95, 0x55, 0xCB, 0x55, 0x55, 0x2C,
0x2C, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
0x95, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x55,
0x94, 0xE6, 0x70, 0x2B, 0x88, 0x2B, 0x88, 0xE1,
0x65, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x47, 0x20,
0x20, 0x20, 0xE1, 0x34, 0x20, 0x20, 0x20, 0x20,
0xB1, 0x95, 0x94, 0xE6, 0xA0, 0x47, 0x70, 0x55,
0x2C, 0xA1, 0x2C, 0x55, 0x90, 0xCB, 0x2C, 0xD6,
0x6D, 0xA1, 0x2C, 0x95, 0x95, 0xA1, 0x2C, 0xA1,
0x2C, 0x2C, 0x95, 0x95, 0x95, 0x95, 0x95, 0x55,
0x70, 0xE6, 0x70, 0x20, 0x20, 0x7D, 0x20, 0x8A,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0x65, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0x94, 0x20,
0x20, 0x20, 0xD8, 0x88, 0x20, 0x20, 0x20, 0x20,
0xD8, 0x2C, 0x94, 0x47, 0x47, 0x90, 0x95, 0x95,
0xA1, 0x6D, 0xA1, 0x90, 0x94, 0x55, 0x2C, 0xD6,
0xD0, 0xA1, 0x95, 0x95, 0x2C, 0x2C, 0xA1, 0x2C,
0x95, 0x95, 0x55, 0x55, 0x55, 0x95, 0x2C, 0x2C,
0xCB, 0x95, 0xD8, 0x20, 0x20, 0xB1, 0x88, 0x28,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE2, 0xA3, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xCB, 0x20,
0x20, 0x20, 0x2B, 0x20, 0x20, 0x20, 0x20, 0x20,
0x88, 0xD6, 0x55, 0x47, 0x94, 0x55, 0x2C, 0xA1,
0xA1, 0xD6, 0x95, 0x94, 0x94, 0x55, 0xD6, 0x6D,
0xBF, 0x95, 0x90, 0xCB, 0x2C, 0x2C, 0x2C, 0x2C,
0x55, 0x95, 0xCB, 0x90, 0x90, 0x95, 0x2C, 0x95,
0x90, 0x70, 0x20, 0x20, 0x34, 0x8A, 0x20, 0x94,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0x65, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
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0x94, 0x94, 0x70, 0x2C, 0xA1, 0xD6, 0xA1, 0x2C,
0x55, 0x55, 0xCB, 0x55, 0x55, 0x55, 0x55, 0x55,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x43, 0x99, 0xE1,
0x70, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xD6, 0xA1,
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0x70, 0x70, 0x55, 0x2C, 0xD6, 0xD6, 0xA1, 0x95,
0x55, 0x90, 0xCB, 0xCB, 0x55, 0x55, 0x2C, 0x2C,
0x32, 0x9D, 0xEB, 0x5D, 0x69, 0x49, 0x84, 0xF0,
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0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0xC1, 0x4E, 0x21, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x34, 0xC9, 0xD8,
0xBB, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
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0x55, 0xCB, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x55,
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0x59, 0x7D, 0xBF, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
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0xE5, 0xE5, 0xE5, 0xE5, 0xEA, 0xC7, 0x7E, 0x66,
0x20, 0x20, 0x20, 0x20, 0x20, 0x34, 0x43, 0x5A,
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0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95, 0x95,
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0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0x42, 0x73, 0x50, 0xBE, 0x79,
0x20, 0x20, 0x20, 0x20, 0x66, 0xCC, 0x37, 0x9C,
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0xE5, 0xE5, 0xEC, 0x4A, 0x2D, 0x50, 0x78, 0x2E,
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0x90, 0x90, 0x70, 0x90, 0xCB, 0x55, 0x55, 0x55,
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0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
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0x55, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
0xD6, 0xA1, 0xA1, 0xA1, 0xA1, 0x55, 0x70, 0x70,
0xCB, 0x68, 0x75, 0x50, 0x82, 0x49, 0x49, 0x49,
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0x65, 0xD0, 0x63, 0x5F, 0x29, 0x2D, 0x2D, 0xEA,
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0xA1, 0x95, 0x95, 0x55, 0xCB, 0x70, 0x70, 0x55,
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0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x5D, 0x89, 0xDC, 0x8B, 0x20, 0x20, 0x20,
0x20, 0x95, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
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0x49, 0x49, 0x82, 0x73, 0x5C, 0x9E, 0x2C, 0x55,
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0x2C, 0x6D, 0x41, 0x6F, 0x3E, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
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0x20, 0x55, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
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0x42, 0xA0, 0xD4, 0xE3, 0x29, 0x2D, 0x82, 0x5D,
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0x49, 0x3E, 0x49, 0x49, 0x49, 0x5C, 0x56, 0xD6,
0xA1, 0xA1, 0xA1, 0x95, 0x55, 0x55, 0x55, 0x95,
0xA1, 0x55, 0x90, 0x70, 0x94, 0x70, 0x95, 0x2C,
0x2C, 0xD6, 0xDD, 0x6F, 0x33, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x5D, 0x5D, 0x82, 0x69, 0x22, 0x62, 0x80, 0x34,
0x94, 0x6B, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0xE5, 0x65, 0x6B,
0xD5, 0x88, 0x5B, 0xE3, 0x29, 0x5D, 0x5D, 0x5D,
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0x49, 0x49, 0x89, 0x49, 0x82, 0x49, 0x71, 0xBA,
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0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x5D, 0x82, 0x5D, 0x89, 0x5E, 0x96, 0x65,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0xE5, 0xE5, 0xE5, 0xE5, 0x65, 0x65, 0xEC, 0xB1,
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0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x3E, 0x9C, 0x2F, 0x68,
0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
0x65, 0xE5, 0x65, 0xE5, 0x6B, 0x90, 0x80, 0x20,
0x20, 0x20, 0x4F, 0x81, 0x50, 0x3E, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x69, 0x69, 0x49, 0x5D, 0x2D, 0xC4, 0x46, 0xA3,
0xD6, 0x55, 0x70, 0x94, 0x94, 0x70, 0xCB, 0x55,
0x55, 0xCB, 0x70, 0x47, 0x70, 0x95, 0xA1, 0xA1,
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0x49, 0x49, 0x5D, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x5D, 0x2D, 0xB5, 0xDB,
0xD6, 0x65, 0xE5, 0x65, 0xE5, 0xE5, 0x65, 0xE5,
0x65, 0x65, 0x6B, 0x95, 0x2B, 0x88, 0x20, 0x20,
0x20, 0x20, 0x8B, 0x81, 0x29, 0x33, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x3E, 0x3E, 0x5E, 0x41, 0x97, 0x27, 0xD6,
0x55, 0x94, 0xE6, 0xE6, 0x47, 0x70, 0x55, 0x55,
0x94, 0x70, 0x94, 0x94, 0x70, 0x55, 0xA1, 0x2C,
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0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49, 0x49,
0x49, 0x49, 0x49, 0x49, 0x3E, 0xEA, 0x30, 0x77,
0xE1, 0xC9, 0x94, 0x2C, 0xD6, 0xD6, 0xA1, 0x55,
0x47, 0x9F, 0x43, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x80, 0x91, 0x81, 0x6A, 0x2D, 0x49, 0x49,
0x49, 0x5D, 0x5D, 0x49, 0x49, 0x5D, 0x5D, 0x82,
0xEB, 0x4A, 0x41, 0xC2, 0x8F, 0xF5, 0xA1, 0x55,
0x94, 0x28, 0xA0, 0x47, 0x70, 0x55, 0x95, 0x95,
0x47, 0x70, 0x70, 0x94, 0x90, 0x95, 0xA1, 0x2C,
0xE8, 0xA6, 0x39, 0x76, 0x50, 0x50, 0x2D, 0x2D,
0x3E, 0x3E, 0x5D, 0x3E, 0x5D, 0x5D, 0x49, 0x82,
0x49, 0x49, 0x49, 0x82, 0x82, 0x50, 0x75, 0xE0,
0x57, 0x20, 0x88, 0x88, 0x20, 0x20, 0x88, 0x20,
0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x79, 0x91, 0x81, 0x76, 0x33, 0x49, 0x49,
0x5D, 0x82, 0x49, 0x49, 0x3E, 0x6A, 0xEA, 0x29,
0xDF, 0x97, 0xBF, 0x6D, 0x6D, 0xD6, 0x55, 0x47,
0x28, 0x28, 0x47, 0x70, 0x55, 0x95, 0x2C, 0x2C,
0x95, 0x95, 0x55, 0x90, 0x90, 0x95, 0xA1, 0xA1,
0xD6, 0x26, 0x45, 0x81, 0x5F, 0x30, 0x48, 0x6F,
0x6F, 0x29, 0x29, 0x6A, 0x2D, 0x2D, 0x5D, 0x49,
0x49, 0x49, 0x49, 0x49, 0x2D, 0x76, 0x6E, 0x77,
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0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
0x20, 0x79, 0xA9, 0xB8, 0x39, 0x50, 0x5D, 0x5D,
0x5D, 0x5D, 0x3E, 0x2D, 0x29, 0x76, 0xCD, 0x37,
0xB9, 0xA1, 0xA1, 0x6D, 0x6D, 0x2C, 0x94, 0x28,
0xD5, 0xE6, 0x70, 0x55, 0x95, 0xA1, 0x2C, 0xA1,
0xBF, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0xA1, 0x2C,
0x95, 0x83, 0xDE, 0x87, 0xB6, 0xBE, 0x40, 0x6E,
0x81, 0x81, 0x78, 0x78, 0x39, 0x6F, 0xEA, 0x2D,
0x2D, 0x33, 0x33, 0x33, 0x76, 0x30, 0x64, 0x54,
0x5B, 0x66, 0x20, 0x20, 0x66, 0x20, 0x88, 0x20,
0x20, 0x20, 0x88, 0x20, 0x20, 0x20, 0x20, 0x20,
0x88, 0x34, 0x8B, 0xF1, 0x23, 0x6F, 0x50, 0x2D,
0x2D, 0x6A, 0x29, 0x6F, 0x78, 0x84, 0x9B, 0xD2,
0x2C, 0x2C, 0xD6, 0x6D, 0x6D, 0x2C, 0x47, 0xA0,
0xE6, 0x70, 0x55, 0x95, 0x2C, 0xA1, 0xA1, 0xA1,
0xD2, 0x95, 0x55, 0xCB, 0x55, 0x2C, 0xD6, 0xA1,
0x95, 0x95, 0xA1, 0xD6, 0x6D, 0x6D, 0xBA, 0xF3,
0x8D, 0x36, 0x74, 0x36, 0xF1, 0xB8, 0x23, 0x78,
0x62, 0x4A, 0x29, 0x62, 0x23, 0xF1, 0x54, 0x31,
0x57, 0x2B, 0x90, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C, 0xCB,
0xE6, 0x7D, 0xCA, 0xB7, 0xB8, 0x75, 0x6F, 0x6F,
0x76, 0x6F, 0x78, 0x81, 0x53, 0xBD, 0x6D, 0x2C,
0x95, 0x95, 0xA1, 0x6D, 0xA1, 0x55, 0x94, 0xE6,
0x70, 0xCB, 0x55, 0x95, 0xA1, 0xD6, 0xD6, 0xA1,
0xD0, 0x94, 0x94, 0x90, 0x95, 0x2C, 0xD6, 0xA1,
0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x2C,
0xD6, 0x68, 0xAB, 0x6C, 0xA4, 0x77, 0x77, 0xAD,
0x40, 0x53, 0x6E, 0x40, 0xB7, 0x54, 0x31, 0xD7,
0xAC, 0xD6, 0x55, 0x55, 0x95, 0x95, 0x95, 0x55,
0x95, 0x2C, 0x2C, 0xA1, 0x95, 0x95, 0x2C, 0xA1,
0x6D, 0xD2, 0x7C, 0x54, 0xAD, 0x40, 0x6E, 0x81,
0x81, 0x6E, 0x36, 0xDA, 0xE8, 0xD6, 0xD6, 0x2C,
0x2C, 0x2C, 0xA1, 0xD6, 0x95, 0x90, 0x94, 0x47,
0x94, 0x94, 0x70, 0x55, 0x2C, 0xD6, 0xA1, 0x95,
0x95, 0x28, 0x47, 0x90, 0x95, 0x2C, 0xA1, 0x2C,
0x55, 0x95, 0x2C, 0xA1, 0xA1, 0x2C, 0x2C, 0x2C,
0x2C, 0xA1, 0x55, 0x70, 0x95, 0x2C, 0xB2, 0xB4,
0xC3, 0xC3, 0x54, 0x54, 0xA9, 0x31, 0xCA, 0x2A,
0x95, 0x90, 0x55, 0x95, 0x2C, 0xA1, 0x2C, 0x95,
0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xD6,
0x6D, 0x2A, 0xB2, 0x4F, 0x31, 0x2E, 0xE0, 0xAD,
0xB7, 0xC8, 0xB4, 0xF5, 0x2C, 0xA1, 0xA1, 0xA1,
0x95, 0x2C, 0xA1, 0x2C, 0x95, 0x70, 0x94, 0x94,
0x94, 0x94, 0x70, 0x95, 0xD6, 0xD6, 0x2C, 0x95,
0x94, 0x28, 0x47, 0xCB, 0x95, 0x2C, 0xA1, 0xA1,
0x95, 0x55, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x95,
0x95, 0x2C, 0x55, 0x70, 0x70, 0x70, 0x94, 0x2C,
0x63, 0xBB, 0xA5, 0xD7, 0xCA, 0xB3, 0x6D, 0x2C,
0x55, 0x55, 0x95, 0x2C, 0x2C, 0x2C, 0x95, 0x95,
0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
0xD6, 0x2C, 0x70, 0x95, 0xAC, 0xC0, 0xDB, 0xEF,
0xEF, 0xA2, 0xE8, 0x95, 0x95, 0xA1, 0xD6, 0xA1,
0x95, 0x55, 0x2C, 0x95, 0x55, 0x70, 0x70, 0x70,
0x94, 0x70, 0x55, 0xD6, 0x6D, 0x6D, 0x95, 0x55,
0x70, 0x47, 0x70, 0x95, 0x2C, 0x2C, 0x2C, 0xA1,
0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, 0x95, 0x55,
0x55, 0x95, 0x55, 0x55, 0x55, 0x55, 0x55, 0x95,
0xA1, 0xF5, 0xBF, 0xBF, 0xA1, 0x95, 0x95, 0x95,
0x95, 0x55, 0x2C, 0x2C, 0x95, 0x55, 0x55, 0x95,
0x95, 0x95, 0xA1, 0xA1, 0xA1, 0xA1, 0x2C, 0xA1,
0x2C, 0x55, 0x70, 0x94, 0x90, 0x2C, 0x6D, 0x6D,
0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1,
0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55,
0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB,
0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95,
0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1,
0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95,
0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95,
0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C,
0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C,
0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C,
0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55,
0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C,
0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95,
0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6,
0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55,
0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95,
0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1,
0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C,
0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C,
0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1,
0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55
};
#endif
#ifdef INCLUDE_LINUX_LOGOBW
unsigned char linux_logo_bw[] __initdata = {
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F,
0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF,
0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF,
0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x87, 0x81, 0xF9,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xA7,
0x99, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xF9, 0xF3, 0xBC, 0xF9, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xF9, 0xE3, 0xBC, 0xF9, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0, 0x3C, 0xF9,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xB0,
0x19, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xF9, 0xC0, 0x03, 0xF0, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80, 0x01, 0xF8,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0x80,
0x01, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xF9, 0xC0, 0x21, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xF9, 0xB1, 0x80, 0xEC, 0xC0, 0x1F,
0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x90, 0x00, 0xE4,
0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0xF1, 0x8C,
0xC0, 0x7C, 0x04, 0x81, 0xFF, 0xFF, 0xFF, 0xFF,
0xE3, 0x80, 0x00, 0x7C, 0x40, 0x11, 0xFF, 0xFF,
0xFF, 0xFF, 0xE3, 0x80, 0x00, 0x7F, 0xD2, 0x29,
0xFF, 0xFF, 0xFF, 0xFF, 0x87, 0x00, 0x00, 0x3F,
0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0x00,
0x00, 0x3F, 0x80, 0x19, 0xFF, 0xFF, 0xFF, 0xFF,
0x1E, 0x00, 0x00, 0x1F, 0x80, 0x19, 0xFF, 0xFF,
0xFF, 0xFE, 0x1C, 0x00, 0x00, 0x1E, 0x80, 0x19,
0xFF, 0xFF, 0xFF, 0xFE, 0x3C, 0x00, 0x00, 0x1E,
0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC, 0x7C, 0x00,
0x00, 0x0F, 0x80, 0x11, 0xFF, 0xFF, 0xFF, 0xFC,
0xF8, 0x00, 0x00, 0x0E, 0x80, 0x11, 0xFF, 0xFF,
0xFF, 0xFC, 0xF8, 0x00, 0x00, 0x06, 0x00, 0x11,
0xFF, 0xFF, 0xFF, 0xF8, 0xF8, 0x00, 0x00, 0x06,
0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xF9, 0xF0, 0x00,
0x00, 0x02, 0x00, 0x09, 0xFF, 0xFF, 0xFF, 0xF1,
0xF0, 0x00, 0x00, 0x02, 0x80, 0x10, 0xFF, 0xFF,
0xFF, 0xF1, 0xE0, 0x00, 0x00, 0x00, 0x97, 0x10,
0xFF, 0xFF, 0xFF, 0xE3, 0xE0, 0x00, 0x00, 0x00,
0xDF, 0xF0, 0xFF, 0xFF, 0xFF, 0xE3, 0xC0, 0x00,
0x00, 0x00, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xC7,
0xC0, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
0xFF, 0xC7, 0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8,
0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00, 0x00, 0x01,
0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x8F, 0x80, 0x00,
0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0x9F,
0x80, 0x00, 0x00, 0x01, 0xFF, 0xF8, 0xFF, 0xFF,
0xFF, 0x9F, 0x80, 0x00, 0x00, 0x01, 0x80, 0x18,
0xFF, 0xFF, 0xFF, 0x9E, 0x80, 0x00, 0x00, 0x03,
0xA8, 0x11, 0xFF, 0xFF, 0xFF, 0x9F, 0x80, 0x00,
0x00, 0x02, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0x99,
0x80, 0x00, 0x00, 0x00, 0x00, 0x09, 0xFF, 0xFF,
0xFF, 0x00, 0x80, 0x00, 0x00, 0x01, 0xC0, 0x01,
0xFF, 0xFF, 0xFE, 0x20, 0x60, 0x00, 0x00, 0x00,
0xFF, 0xC3, 0xFF, 0xFF, 0xF8, 0x00, 0x30, 0x00,
0x00, 0x00, 0xFF, 0x0F, 0xFF, 0xFF, 0xC0, 0x40,
0x38, 0x00, 0x00, 0x00, 0xFE, 0x47, 0xFF, 0xFF,
0x81, 0x00, 0x1C, 0x00, 0x00, 0x00, 0xFC, 0x23,
0xFF, 0xFF, 0x90, 0x00, 0x1E, 0x00, 0x00, 0x00,
0x78, 0x11, 0xFF, 0xFF, 0x80, 0x00, 0x0F, 0x80,
0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x80, 0x00,
0x07, 0xC0, 0x00, 0x00, 0x00, 0x08, 0xFF, 0xFF,
0xC0, 0x00, 0x07, 0xC0, 0x00, 0x00, 0x00, 0x04,
0x7F, 0xFF, 0x80, 0x00, 0x03, 0xC0, 0x00, 0x10,
0x00, 0x00, 0x1F, 0xFF, 0x80, 0x00, 0x01, 0x80,
0x00, 0x30, 0x00, 0x00, 0x0F, 0xFF, 0x80, 0x00,
0x00, 0x00, 0x00, 0x70, 0x00, 0x01, 0x4F, 0xFF,
0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0x00,
0x0F, 0xFF, 0xC0, 0x00, 0x00, 0x80, 0x03, 0xF0,
0x00, 0x00, 0x8F, 0xFF, 0x80, 0x00, 0x00, 0x40,
0x0F, 0xF0, 0x00, 0x04, 0x1F, 0xFF, 0x80, 0x00,
0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x10, 0x1F, 0xFF,
0xC0, 0x00, 0x00, 0x7F, 0xFF, 0xF0, 0x00, 0x40,
0xFF, 0xFF, 0x98, 0x00, 0x00, 0xFF, 0xFF, 0xF0,
0x00, 0x83, 0xFF, 0xFF, 0x81, 0xE0, 0x01, 0xFF,
0xFF, 0xF8, 0x02, 0x07, 0xFF, 0xFF, 0x80, 0x3F,
0x07, 0xE0, 0x00, 0x1C, 0x0C, 0x1F, 0xFF, 0xFF,
0xF8, 0x03, 0xFF, 0x80, 0x00, 0x1F, 0x78, 0x1F,
0xFF, 0xFF, 0xFF, 0x80, 0x7F, 0x00, 0x07, 0x0F,
0xF0, 0x7F, 0xFF, 0xFF, 0xFF, 0xFE, 0x0C, 0x07,
0xFF, 0x83, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x1F, 0xFF, 0xC0, 0x03, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x07, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
};
#endif
#ifdef INCLUDE_LINUX_LOGO16
unsigned char linux_logo16_red[] __initdata = {
0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x35, 0x83, 0xa5,
0x65, 0x8f, 0x98, 0xc9, 0xdb, 0xe1, 0xe7, 0xf8
};
unsigned char linux_logo16_green[] __initdata = {
0x00, 0x90, 0xb0, 0x9c, 0xf7, 0x2e, 0x83, 0xa5,
0x65, 0x6e, 0x98, 0x89, 0xbf, 0xac, 0xda, 0xf8
};
unsigned char linux_logo16_blue[] __initdata = {
0x00, 0x90, 0xaf, 0x9c, 0xf7, 0x2b, 0x82, 0xa5,
0x65, 0x41, 0x97, 0x1e, 0x60, 0x29, 0xa5, 0xf8
};
unsigned char linux_logo16[] __initdata = {
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa1, 0x11, 0x11,
0x61, 0x16, 0x66, 0x66, 0x11, 0x11, 0x11, 0x11,
0x11, 0x11, 0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0xa8, 0x00, 0x00,
0x00, 0x00, 0x00, 0x87, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x73, 0x33, 0x33, 0x3a, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x77, 0x77,
0x77, 0x27, 0x77, 0x77, 0x77, 0x33, 0x3a, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xa3, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00,
0x00, 0x00, 0x55, 0x50, 0x08, 0x33, 0x77, 0x77,
0x77, 0x72, 0x72, 0x27, 0x77, 0x77, 0x33, 0x33,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xa3, 0x33, 0x33, 0x77, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x58, 0x85, 0x00, 0x11, 0x11, 0xaa,
0xa3, 0x37, 0x77, 0x72, 0x22, 0x22, 0x77, 0x73,
0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3,
0x33, 0x37, 0x77, 0x33, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x56, 0x85, 0x00, 0x06, 0x66, 0x11,
0x11, 0x1a, 0xa3, 0x37, 0x77, 0x72, 0x22, 0x77,
0x73, 0x33, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33,
0x33, 0x33, 0x33, 0x30, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x55, 0x00, 0x00, 0x06, 0x66, 0x66,
0x66, 0x66, 0x11, 0x1a, 0xa3, 0x77, 0x72, 0x22,
0x77, 0x73, 0x3a, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33,
0x33, 0x33, 0x33, 0xa0, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x11,
0x66, 0x66, 0x66, 0x66, 0x11, 0xa3, 0x77, 0x22,
0x22, 0x77, 0x33, 0x33, 0xaa, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33,
0x33, 0x3a, 0xa1, 0x10, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x33,
0xaa, 0x11, 0x16, 0x66, 0x66, 0x61, 0x1a, 0x37,
0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0x33,
0x3a, 0xa1, 0x11, 0x10, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x22,
0x22, 0x77, 0x3a, 0x11, 0x66, 0x66, 0x66, 0x1a,
0x37, 0x22, 0x22, 0x77, 0x33, 0x3a, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x33, 0x3a,
0xa1, 0x11, 0x11, 0x10, 0x00, 0x00, 0x50, 0x00,
0x00, 0x05, 0x80, 0x50, 0x00, 0x00, 0x07, 0x72,
0x22, 0x22, 0x22, 0x73, 0xa1, 0x66, 0x66, 0x61,
0x1a, 0x77, 0x22, 0x27, 0x73, 0x33, 0xaa, 0xaa,
0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x33, 0x3a, 0xaa,
0x11, 0x11, 0x1a, 0xa0, 0x08, 0x71, 0x05, 0x00,
0x00, 0x12, 0x22, 0x50, 0x00, 0x00, 0x07, 0x77,
0x77, 0x72, 0x22, 0x22, 0x27, 0x31, 0x16, 0x66,
0x61, 0x13, 0x77, 0x22, 0x77, 0x33, 0x3a, 0xaa,
0xaa, 0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xa1,
0x11, 0x1a, 0x33, 0x70, 0x07, 0x2e, 0x70, 0x00,
0x01, 0x44, 0x42, 0x60, 0x00, 0x00, 0x02, 0x22,
0x22, 0x22, 0x22, 0x22, 0x22, 0x27, 0x31, 0x66,
0x66, 0x61, 0xa3, 0x72, 0x22, 0x77, 0x33, 0xaa,
0xaa, 0xaa, 0xa3, 0x33, 0x33, 0xaa, 0xaa, 0x11,
0x1a, 0x33, 0x77, 0x30, 0x04, 0x82, 0x40, 0x00,
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0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0x3a,
0x11, 0xa7, 0x33, 0x10, 0x04, 0x09, 0xbd, 0xdd,
0xbd, 0xd0, 0x04, 0x45, 0x00, 0x0e, 0xee, 0xee,
0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0x22,
0x22, 0x22, 0x71, 0x66, 0x66, 0x13, 0x72, 0x27,
0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0x33, 0x11,
0xa3, 0x73, 0xa1, 0x60, 0x08, 0xbd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdb, 0x90, 0x00, 0x02, 0xec, 0xee,
0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xce, 0x22,
0x22, 0x22, 0x27, 0xa6, 0x66, 0x61, 0x37, 0x27,
0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x1a,
0x33, 0xa1, 0x16, 0x60, 0x0b, 0xbd, 0xdd, 0xdd,
0xcd, 0xdd, 0xdd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xce, 0xa2,
0x22, 0x22, 0x22, 0x7a, 0x66, 0x66, 0x13, 0x77,
0x1a, 0xaa, 0xaa, 0xaa, 0xaa, 0x3a, 0x11, 0x33,
0xaa, 0x11, 0x66, 0x60, 0x9b, 0xdd, 0xdd, 0xdd,
0xcd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0xec, 0xcc,
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x61,
0x72, 0x22, 0x22, 0x22, 0xa1, 0x66, 0x61, 0x37,
0x1a, 0xaa, 0xaa, 0xaa, 0xa3, 0xa1, 0x13, 0x3a,
0x11, 0x11, 0x11, 0x10, 0x5b, 0xdd, 0xdd, 0xdc,
0xdd, 0xdd, 0xbd, 0xd9, 0x00, 0x00, 0xec, 0xcc,
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xee, 0x86,
0x17, 0x22, 0x22, 0x22, 0x23, 0x16, 0x66, 0xaa,
0xaa, 0xa3, 0x3a, 0xaa, 0xaa, 0x1a, 0x3a, 0xa1,
0x11, 0x11, 0x1a, 0x70, 0x05, 0xbd, 0xdd, 0xdd,
0xdb, 0x5b, 0xdd, 0xb0, 0x00, 0x60, 0x2e, 0xcc,
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe6, 0x88,
0x66, 0x32, 0x22, 0x22, 0x22, 0x36, 0x66, 0x11,
0x33, 0x33, 0x3a, 0xaa, 0x11, 0xaa, 0xaa, 0xa1,
0x11, 0x1a, 0x3a, 0x60, 0x02, 0x99, 0xbb, 0xb9,
0x9b, 0xbb, 0xbc, 0x22, 0x00, 0x86, 0x5e, 0xcc,
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xe1, 0x68,
0x86, 0x63, 0x22, 0x22, 0x22, 0x2a, 0x66, 0x66,
0x33, 0x33, 0xaa, 0xaa, 0x1a, 0xaa, 0xaa, 0x11,
0x1a, 0xa7, 0x68, 0x80, 0x02, 0x2b, 0xbd, 0xbb,
0xbb, 0xb9, 0x22, 0x22, 0x00, 0x06, 0x6e, 0xcc,
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc7, 0xa6,
0x88, 0x86, 0x32, 0x22, 0x22, 0x27, 0xa6, 0x66,
0x33, 0x3a, 0xaa, 0xa1, 0xaa, 0xaa, 0xa1, 0x11,
0xa3, 0xa6, 0x88, 0x80, 0x02, 0x22, 0x9b, 0xbb,
0xbb, 0x22, 0x24, 0xf4, 0x60, 0x00, 0x0c, 0xcc,
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xc2, 0x21,
0x68, 0x88, 0x63, 0x22, 0x22, 0x22, 0x71, 0x66,
0x33, 0x3a, 0x11, 0x11, 0xaa, 0xaa, 0x11, 0xaa,
0x71, 0x88, 0x88, 0x00, 0x02, 0xe2, 0x26, 0x99,
0x22, 0x22, 0x4f, 0xf4, 0x40, 0x00, 0x0c, 0xcc,
0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x22, 0x22,
0x16, 0x88, 0x86, 0xa2, 0x22, 0x22, 0x27, 0x11,
0x33, 0xa1, 0x11, 0x11, 0xaa, 0x31, 0x1a, 0xa3,
0x68, 0x88, 0x81, 0x00, 0x54, 0x42, 0x22, 0x22,
0x22, 0x44, 0xff, 0xff, 0x48, 0x00, 0x00, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x22,
0x21, 0x88, 0x88, 0x6a, 0x22, 0x22, 0x22, 0x31,
0x3a, 0xa1, 0x11, 0x1a, 0xa3, 0x11, 0x33, 0x36,
0x88, 0x86, 0x30, 0x00, 0x4f, 0x44, 0x22, 0x22,
0x24, 0xff, 0xff, 0xff, 0x44, 0x00, 0x00, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x95, 0x22, 0x72,
0x22, 0x18, 0x88, 0x86, 0x32, 0x22, 0x22, 0x27,
0xaa, 0x11, 0x11, 0x1a, 0x31, 0x13, 0x33, 0x68,
0x88, 0x6a, 0x00, 0x02, 0x4f, 0x4f, 0x42, 0x24,
0x4f, 0xff, 0xff, 0xff, 0xf4, 0x50, 0x00, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x22, 0x73,
0x72, 0x26, 0x88, 0x88, 0x63, 0x22, 0x22, 0x22,
0x11, 0x11, 0x11, 0xa3, 0xa1, 0x73, 0xa6, 0x88,
0x81, 0xa5, 0x00, 0x04, 0x4f, 0x4f, 0x44, 0x4f,
0xff, 0xff, 0xff, 0xff, 0xf4, 0x40, 0x00, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x12, 0x27,
0xaa, 0x22, 0x68, 0x55, 0x86, 0x72, 0x22, 0x22,
0x11, 0x11, 0x1a, 0x33, 0x13, 0x3a, 0x18, 0x88,
0x1a, 0x10, 0x00, 0x44, 0x4f, 0x4f, 0xff, 0x4f,
0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0x00, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x61, 0x22,
0x3a, 0xa2, 0x26, 0x85, 0x58, 0x67, 0x22, 0x22,
0x61, 0x61, 0x1a, 0x7a, 0x37, 0x31, 0x88, 0x81,
0x11, 0x00, 0x05, 0xe4, 0x44, 0xff, 0xff, 0xff,
0x4f, 0xf4, 0x44, 0xff, 0xff, 0xf5, 0x00, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x88, 0x12,
0x2a, 0xaa, 0x72, 0x68, 0x55, 0x81, 0x22, 0x22,
0x66, 0x61, 0xa3, 0x33, 0x73, 0x16, 0x88, 0x11,
0x10, 0x00, 0x08, 0x74, 0x44, 0x4f, 0x44, 0x44,
0xf4, 0xf4, 0x44, 0x44, 0xe2, 0x44, 0x00, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x88, 0x81,
0x22, 0xaa, 0xa7, 0x26, 0x85, 0x88, 0x12, 0x22,
0x66, 0x61, 0x37, 0xa7, 0x3a, 0x66, 0x66, 0x11,
0x80, 0x00, 0x0a, 0x72, 0x44, 0x4f, 0x44, 0x4f,
0xff, 0x44, 0x44, 0x22, 0x22, 0x24, 0x00, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0x85, 0x88,
0x12, 0x2a, 0xaa, 0x22, 0x68, 0x58, 0x63, 0x22,
0x66, 0x1a, 0x73, 0x77, 0x31, 0x66, 0x61, 0x11,
0x00, 0x00, 0x07, 0x44, 0xff, 0x4f, 0xf4, 0x4f,
0xff, 0x4f, 0x44, 0xf4, 0x42, 0x22, 0x40, 0x9b,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x85, 0x55,
0x81, 0x27, 0xaa, 0xa2, 0x78, 0x88, 0x86, 0x72,
0x66, 0x13, 0x77, 0x73, 0x11, 0x66, 0x61, 0x76,
0x00, 0x50, 0x84, 0xf4, 0xff, 0x4f, 0xf4, 0xff,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x42, 0x40, 0x9b,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x68, 0x55,
0x58, 0x12, 0x3a, 0xaa, 0x23, 0x88, 0x88, 0xa7,
0x66, 0xa7, 0x77, 0x7a, 0x16, 0x66, 0x1a, 0x15,
0x05, 0x00, 0x4f, 0xf4, 0xff, 0x4f, 0xf4, 0xff,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0x24, 0x9b,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0xb9, 0x26, 0x55,
0x55, 0x81, 0x23, 0xaa, 0x32, 0x18, 0x88, 0x6a,
0x61, 0x37, 0x77, 0x31, 0x66, 0x66, 0x17, 0x60,
0x05, 0x08, 0x4f, 0xf4, 0xff, 0x4f, 0xf4, 0xff,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x4e, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x99, 0xa2, 0x65,
0x55, 0x58, 0xa2, 0x7a, 0xa2, 0x26, 0x88, 0x61,
0x61, 0x32, 0x27, 0xa1, 0x66, 0x61, 0x31, 0x60,
0x00, 0x04, 0x4f, 0xf4, 0xff, 0x44, 0x44, 0xff,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0xf4, 0x99,
0xbb, 0xbb, 0xbb, 0xbb, 0xbb, 0x9b, 0xaa, 0x26,
0x55, 0x55, 0x87, 0x27, 0x33, 0x27, 0x68, 0x61,
0x1a, 0x72, 0x27, 0xa6, 0x66, 0x6a, 0x71, 0x00,
0x80, 0x84, 0xff, 0xf4, 0xff, 0x44, 0x44, 0xff,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x44, 0xf4, 0x99,
0x9b, 0x9b, 0x99, 0xb9, 0xb9, 0x99, 0xaa, 0xa2,
0x85, 0x55, 0x56, 0x22, 0x27, 0x22, 0x36, 0x66,
0x13, 0x22, 0x23, 0x16, 0x86, 0x63, 0x73, 0x00,
0x00, 0x44, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0xff,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x4f, 0x99,
0x9b, 0x99, 0x99, 0x99, 0xb9, 0x99, 0xaa, 0xaa,
0x28, 0x55, 0x58, 0x12, 0x22, 0x22, 0x21, 0x11,
0xa3, 0x27, 0x7a, 0x66, 0x86, 0x17, 0x75, 0x05,
0x05, 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0xff,
0xff, 0x4f, 0x44, 0x4f, 0x4f, 0x44, 0x4f, 0x99,
0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x3a, 0xaa,
0xa2, 0x85, 0x58, 0x67, 0x72, 0x22, 0x27, 0xa1,
0x37, 0x27, 0x7a, 0x68, 0x86, 0xa2, 0x70, 0x00,
0x02, 0xff, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0x4f,
0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0xf4, 0x99,
0x99, 0x99, 0x99, 0x99, 0x99, 0x99, 0x23, 0xaa,
0xa7, 0x78, 0x88, 0x81, 0x77, 0x22, 0x27, 0x3a,
0x72, 0x73, 0x71, 0x68, 0x66, 0x32, 0x50, 0x00,
0x04, 0x4f, 0xf4, 0xf4, 0xff, 0x44, 0x44, 0x4f,
0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0x44, 0x95,
0x99, 0x99, 0x99, 0x99, 0x99, 0x55, 0x12, 0x3a,
0xaa, 0x21, 0x88, 0x81, 0x77, 0x27, 0x73, 0x73,
0x72, 0x33, 0x36, 0x86, 0x61, 0x72, 0x00, 0x00,
0x04, 0x44, 0xf4, 0xf4, 0xf4, 0x44, 0x44, 0x4f,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x44, 0x55,
0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x8a, 0x27,
0xaa, 0x77, 0x68, 0x61, 0x23, 0x71, 0x11, 0x3a,
0x27, 0xa3, 0x36, 0x86, 0x61, 0x20, 0x00, 0x00,
0x04, 0xf4, 0xf4, 0xf4, 0xf4, 0x44, 0x44, 0x4f,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x41, 0x59,
0x99, 0x99, 0x99, 0x99, 0x99, 0x95, 0x58, 0x77,
0x27, 0x32, 0x36, 0x63, 0x23, 0x71, 0x66, 0x11,
0x27, 0x13, 0xa6, 0x86, 0x6a, 0x20, 0x00, 0x50,
0x04, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x41, 0x99,
0x9b, 0xbb, 0xbb, 0xbb, 0xb9, 0x99, 0x68, 0x13,
0x32, 0x22, 0x73, 0xa7, 0x2a, 0x31, 0x88, 0x66,
0x7a, 0x13, 0x18, 0x66, 0x63, 0x20, 0x00, 0x06,
0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
0xff, 0x4f, 0x44, 0xff, 0x4f, 0x4f, 0x49, 0x95,
0xa9, 0xa9, 0x99, 0x97, 0x92, 0x99, 0x65, 0x6a,
0x17, 0x22, 0x23, 0x72, 0x27, 0xaa, 0x88, 0x88,
0xa1, 0x17, 0x68, 0x66, 0x67, 0x70, 0x00, 0x05,
0x0f, 0x4f, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
0xff, 0x4f, 0x44, 0xff, 0xf4, 0xf4, 0x49, 0x9c,
0x2e, 0xee, 0xee, 0xee, 0xee, 0xa9, 0x65, 0x8a,
0x1a, 0xaa, 0x37, 0x72, 0x27, 0x37, 0x88, 0x88,
0x11, 0x17, 0x68, 0x66, 0x67, 0x10, 0x9d, 0xd0,
0x84, 0x44, 0xff, 0x4f, 0x4f, 0x44, 0xf4, 0x4f,
0xff, 0x4f, 0x44, 0xff, 0xf4, 0xf4, 0x4f, 0x69,
0xcc, 0xee, 0xee, 0xee, 0xec, 0x99, 0x88, 0x63,
0x61, 0x68, 0x61, 0x72, 0x22, 0x7a, 0x68, 0x88,
0x11, 0x17, 0x88, 0x66, 0x12, 0x1b, 0xdd, 0xdd,
0x02, 0x44, 0x4f, 0x4f, 0x4f, 0x44, 0x44, 0x4f,
0xff, 0x4f, 0x44, 0xff, 0xff, 0x4f, 0x4c, 0xc5,
0x0c, 0xc1, 0x11, 0x1c, 0xc0, 0x26, 0x66, 0x17,
0x66, 0x88, 0x88, 0x12, 0x22, 0x23, 0xa8, 0x88,
0x11, 0x13, 0x88, 0x66, 0x17, 0xbb, 0xdd, 0xdd,
0xd0, 0x8f, 0xff, 0xf4, 0xf4, 0x44, 0xf4, 0x4f,
0xff, 0x4f, 0x44, 0xf4, 0x4f, 0x44, 0xdd, 0xdd,
0x00, 0x00, 0x00, 0x05, 0x9d, 0x21, 0x66, 0x27,
0xa6, 0x65, 0x58, 0x67, 0x22, 0x27, 0x28, 0x88,
0x11, 0xaa, 0x86, 0x68, 0x1a, 0xbb, 0xdd, 0xdd,
0xdb, 0x05, 0xf4, 0xf4, 0xf4, 0xf4, 0x44, 0x4f,
0xff, 0x4f, 0x44, 0xf4, 0xf4, 0xf4, 0xdd, 0xdb,
0x00, 0x00, 0x00, 0x00, 0xdd, 0xda, 0x66, 0x22,
0x71, 0x15, 0x55, 0x81, 0x22, 0x22, 0x76, 0x88,
0x11, 0x31, 0x88, 0x88, 0xab, 0xbd, 0xdd, 0xdd,
0xdd, 0x00, 0x04, 0x44, 0xff, 0xff, 0x4f, 0x4f,
0xff, 0x4f, 0x44, 0xf4, 0xf4, 0x44, 0xdd, 0xdb,
0x00, 0x00, 0x00, 0x0b, 0xdd, 0xda, 0x11, 0x22,
0x23, 0x68, 0x55, 0x86, 0x22, 0x22, 0x7a, 0x88,
0x1a, 0x71, 0x88, 0x89, 0xbb, 0xdd, 0xdd, 0xdd,
0xdd, 0xd0, 0x00, 0x4f, 0x44, 0xff, 0x4f, 0x4f,
0xff, 0x4f, 0x44, 0xf4, 0xff, 0xe2, 0xdd, 0xdb,
0x90, 0x00, 0x05, 0xbd, 0xdd, 0xb8, 0x63, 0x22,
0x27, 0xa6, 0x55, 0x88, 0x77, 0x22, 0x22, 0x88,
0x1a, 0x28, 0xbd, 0xdb, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdb, 0x00, 0x07, 0x44, 0x4f, 0x4f, 0x4f,
0xff, 0x4f, 0x44, 0x4f, 0x4f, 0x22, 0xdd, 0xdb,
0xbb, 0x9b, 0xbb, 0xbd, 0xdd, 0xd5, 0x86, 0x22,
0x22, 0x77, 0x85, 0x88, 0x17, 0x22, 0x22, 0x88,
0xaa, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0x00, 0x00, 0x54, 0x4f, 0x4f, 0x4f,
0xff, 0x4f, 0x44, 0xf4, 0x44, 0x22, 0xbd, 0xdd,
0xbb, 0xbb, 0xbb, 0xdd, 0xdd, 0xdd, 0x88, 0x72,
0x27, 0x22, 0x88, 0x88, 0x67, 0x72, 0x22, 0x18,
0x33, 0x2d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xd0, 0x00, 0x05, 0x4f, 0x4f, 0x4f,
0xff, 0x4f, 0x44, 0x44, 0x4f, 0x22, 0xbd, 0xdd,
0xdb, 0xbb, 0xdd, 0xdd, 0xdd, 0xdd, 0x88, 0x17,
0x27, 0x72, 0x68, 0x88, 0x87, 0x32, 0x22, 0x36,
0x37, 0x2d, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xd5, 0x00, 0x00, 0x4f, 0x4f, 0x4f,
0xff, 0xf4, 0xf4, 0xf4, 0xf4, 0x22, 0xbb, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x67,
0x72, 0x77, 0x38, 0x88, 0x83, 0x37, 0x22, 0x26,
0x72, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0x00, 0x00, 0x4f, 0x4f, 0x4f,
0xff, 0xf4, 0xf4, 0xf4, 0x44, 0x25, 0xbb, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd3,
0x32, 0x73, 0x76, 0x88, 0x81, 0x33, 0x22, 0x2a,
0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xb0, 0x54, 0x4f, 0x4f, 0x4f,
0xff, 0xf4, 0xf4, 0xff, 0x44, 0x00, 0xbb, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xa7, 0x73, 0x26, 0x88, 0x86, 0x7a, 0x72, 0x27,
0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0xff, 0x4f, 0x4f,
0xff, 0xf4, 0xf4, 0x44, 0x40, 0x05, 0xbb, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0x13, 0x23, 0x21, 0x68, 0x86, 0x17, 0x72, 0x22,
0x22, 0x2b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdb, 0x44, 0x4f, 0x4f, 0x4f,
0xff, 0xff, 0x44, 0x42, 0x00, 0x05, 0xbd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0x87, 0x27, 0x27, 0x16, 0x66, 0x67, 0x22, 0x22,
0x72, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0x94, 0x44, 0x44, 0x44,
0x44, 0x44, 0x44, 0x00, 0x00, 0x05, 0xbb, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb8,
0x86, 0x22, 0x22, 0x7a, 0x68, 0x81, 0x22, 0x22,
0x37, 0x7b, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x44, 0x44, 0x44,
0x44, 0x47, 0x00, 0x00, 0x00, 0x05, 0xbd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xd8, 0x68,
0x58, 0x72, 0x22, 0x27, 0x18, 0x86, 0x72, 0x22,
0x1a, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdb, 0xb5, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x18, 0x85,
0x58, 0x12, 0x22, 0x36, 0x18, 0x88, 0x32, 0x22,
0x61, 0x3b, 0xbb, 0xbb, 0xbd, 0xdd, 0xdd, 0xdd,
0xdd, 0xdd, 0xdd, 0xdb, 0xb9, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0xbb, 0xdd,
0xdd, 0xdd, 0xdd, 0xdd, 0xb9, 0x7a, 0x68, 0x85,
0x88, 0x62, 0x27, 0x16, 0x18, 0x88, 0x12, 0x27,
0x86, 0x18, 0x9b, 0xbb, 0xbb, 0xbb, 0xbb, 0xbd,
0xdd, 0xdd, 0xdd, 0xbb, 0xb5, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0xbb, 0xbd,
0xdd, 0xdd, 0xdb, 0xbb, 0x87, 0x31, 0x68, 0x65,
0x88, 0x82, 0x23, 0x16, 0x18, 0x88, 0x12, 0x23,
0x88, 0x67, 0x27, 0xa8, 0x9b, 0xbb, 0xbb, 0xbb,
0xbd, 0xdd, 0xbb, 0xbb, 0x95, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x9b, 0xbb,
0xbb, 0xbb, 0xbb, 0x96, 0x87, 0x16, 0x68, 0x18,
0x88, 0x62, 0x31, 0x66, 0x18, 0x88, 0x62, 0x73,
0x88, 0x63, 0x27, 0x33, 0x65, 0x55, 0x99, 0x9b,
0xbb, 0xbb, 0xbb, 0x99, 0x55, 0x0a, 0xa1, 0x86,
0x81, 0x68, 0x88, 0x55, 0x58, 0x85, 0x9b, 0xbb,
0xbb, 0xbb, 0x95, 0x88, 0x83, 0x66, 0x66, 0x18,
0x66, 0x82, 0xa1, 0x66, 0x18, 0x88, 0x62, 0x33,
0x88, 0x81, 0x27, 0x7a, 0x18, 0x58, 0x86, 0x85,
0x99, 0x99, 0x99, 0x95, 0x53, 0x2a, 0xaa, 0x88,
0x67, 0x31, 0x68, 0x55, 0x58, 0x85, 0x59, 0xbb,
0xbb, 0xb9, 0x58, 0x68, 0x83, 0x66, 0x61, 0x16,
0x66, 0x62, 0x16, 0x66, 0x68, 0x88, 0x62, 0xaa,
0x88, 0x86, 0x27, 0x77, 0x78, 0x55, 0x88, 0x22,
0x25, 0x55, 0x95, 0x55, 0x6a, 0xa2, 0x2a, 0x88,
0x62, 0x27, 0x37, 0x38, 0x88, 0x87, 0x55, 0x59,
0x95, 0x58, 0x16, 0x88, 0x8a, 0x66, 0x63, 0x68,
0x86, 0x67, 0x66, 0x66, 0x68, 0x88, 0x12, 0x11,
0x88, 0x88, 0x72, 0x77, 0x78, 0x85, 0x58, 0x17,
0x23, 0x32, 0x55, 0x55, 0x81, 0x13, 0x73, 0x66,
0x62, 0x7a, 0xaa, 0x38, 0x88, 0x58, 0x27, 0x55,
0x58, 0x32, 0x38, 0x88, 0x81, 0x66, 0xa2, 0x88,
0x86, 0x61, 0x66, 0x61, 0x66, 0x68, 0x13, 0x11,
0x88, 0x88, 0x12, 0x22, 0x71, 0x85, 0x58, 0x62,
0x23, 0xa2, 0x68, 0x88, 0x81, 0x66, 0x88, 0x88,
0x63, 0x2a, 0xaa, 0x28, 0x88, 0x55, 0x86, 0x61,
0x66, 0x66, 0x68, 0x88, 0x66, 0x66, 0x77, 0x88,
0x68, 0x16, 0x66, 0x62, 0x66, 0x68, 0xa1, 0x61,
0x88, 0x88, 0x62, 0x22, 0x22, 0x85, 0x55, 0x83,
0x72, 0x37, 0xa8, 0x88, 0x61, 0x66, 0x85, 0x55,
0x86, 0x23, 0xaa, 0x71, 0x88, 0x85, 0x88, 0x66,
0x88, 0x86, 0x88, 0x88, 0x16, 0x61, 0x21, 0x88,
0x66, 0xa6, 0x86, 0x17, 0x66, 0x66, 0x31, 0x61,
0x88, 0x88, 0x87, 0x72, 0x22, 0x68, 0x55, 0x86,
0x77, 0x77, 0x36, 0x88, 0x13, 0x68, 0x85, 0x55,
0x58, 0x12, 0x73, 0x72, 0x76, 0x88, 0x88, 0x68,
0x88, 0x88, 0x88, 0x66, 0x36, 0x63, 0x26, 0x86,
0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61,
0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58,
0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55,
0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68,
0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68,
0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66,
0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88,
0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55,
0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66,
0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68,
0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66,
0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88,
0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85,
0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68,
0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88,
0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a
};
#endif
|
1001-study-uboot
|
include/linux_logo.h
|
C
|
gpl3
| 71,398
|
/*
* R/O (V)FAT 12/16/32 filesystem implementation by Marcus Sundberg
*
* 2002-07-28 - rjones@nexus-tech.net - ported to ppcboot v1.1.6
* 2003-03-10 - kharris@nexus-tech.net - ported to u-boot
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _FAT_H_
#define _FAT_H_
#include <asm/byteorder.h>
#define CONFIG_SUPPORT_VFAT
/* Maximum Long File Name length supported here is 128 UTF-16 code units */
#define VFAT_MAXLEN_BYTES 256 /* Maximum LFN buffer in bytes */
#define VFAT_MAXSEQ 9 /* Up to 9 of 13 2-byte UTF-16 entries */
#define PREFETCH_BLOCKS 2
#define MAX_CLUSTSIZE 65536
#define DIRENTSPERBLOCK (mydata->sect_size / sizeof(dir_entry))
#define DIRENTSPERCLUST ((mydata->clust_size * mydata->sect_size) / \
sizeof(dir_entry))
#define FATBUFBLOCKS 6
#define FATBUFSIZE (mydata->sect_size * FATBUFBLOCKS)
#define FAT12BUFSIZE ((FATBUFSIZE*2)/3)
#define FAT16BUFSIZE (FATBUFSIZE/2)
#define FAT32BUFSIZE (FATBUFSIZE/4)
/* Filesystem identifiers */
#define FAT12_SIGN "FAT12 "
#define FAT16_SIGN "FAT16 "
#define FAT32_SIGN "FAT32 "
#define SIGNLEN 8
/* File attributes */
#define ATTR_RO 1
#define ATTR_HIDDEN 2
#define ATTR_SYS 4
#define ATTR_VOLUME 8
#define ATTR_DIR 16
#define ATTR_ARCH 32
#define ATTR_VFAT (ATTR_RO | ATTR_HIDDEN | ATTR_SYS | ATTR_VOLUME)
#define DELETED_FLAG ((char)0xe5) /* Marks deleted files when in name[0] */
#define aRING 0x05 /* Used as special character in name[0] */
/*
* Indicates that the entry is the last long entry in a set of long
* dir entries
*/
#define LAST_LONG_ENTRY_MASK 0x40
/* Flags telling whether we should read a file or list a directory */
#define LS_NO 0
#define LS_YES 1
#define LS_DIR 1
#define LS_ROOT 2
#define ISDIRDELIM(c) ((c) == '/' || (c) == '\\')
#define FSTYPE_NONE (-1)
#if defined(__linux__) && defined(__KERNEL__)
#define FAT2CPU16 le16_to_cpu
#define FAT2CPU32 le32_to_cpu
#else
#if __LITTLE_ENDIAN
#define FAT2CPU16(x) (x)
#define FAT2CPU32(x) (x)
#else
#define FAT2CPU16(x) ((((x) & 0x00ff) << 8) | (((x) & 0xff00) >> 8))
#define FAT2CPU32(x) ((((x) & 0x000000ff) << 24) | \
(((x) & 0x0000ff00) << 8) | \
(((x) & 0x00ff0000) >> 8) | \
(((x) & 0xff000000) >> 24))
#endif
#endif
#define TOLOWER(c) if((c) >= 'A' && (c) <= 'Z'){(c)+=('a' - 'A');}
#define TOUPPER(c) if ((c) >= 'a' && (c) <= 'z') \
(c) -= ('a' - 'A');
#define START(dent) (FAT2CPU16((dent)->start) \
+ (mydata->fatsize != 32 ? 0 : \
(FAT2CPU16((dent)->starthi) << 16)))
#define CHECK_CLUST(x, fatsize) ((x) <= 1 || \
(x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0))
typedef struct boot_sector {
__u8 ignored[3]; /* Bootstrap code */
char system_id[8]; /* Name of fs */
__u8 sector_size[2]; /* Bytes/sector */
__u8 cluster_size; /* Sectors/cluster */
__u16 reserved; /* Number of reserved sectors */
__u8 fats; /* Number of FATs */
__u8 dir_entries[2]; /* Number of root directory entries */
__u8 sectors[2]; /* Number of sectors */
__u8 media; /* Media code */
__u16 fat_length; /* Sectors/FAT */
__u16 secs_track; /* Sectors/track */
__u16 heads; /* Number of heads */
__u32 hidden; /* Number of hidden sectors */
__u32 total_sect; /* Number of sectors (if sectors == 0) */
/* FAT32 only */
__u32 fat32_length; /* Sectors/FAT */
__u16 flags; /* Bit 8: fat mirroring, low 4: active fat */
__u8 version[2]; /* Filesystem version */
__u32 root_cluster; /* First cluster in root directory */
__u16 info_sector; /* Filesystem info sector */
__u16 backup_boot; /* Backup boot sector */
__u16 reserved2[6]; /* Unused */
} boot_sector;
typedef struct volume_info
{
__u8 drive_number; /* BIOS drive number */
__u8 reserved; /* Unused */
__u8 ext_boot_sign; /* 0x29 if fields below exist (DOS 3.3+) */
__u8 volume_id[4]; /* Volume ID number */
char volume_label[11]; /* Volume label */
char fs_type[8]; /* Typically FAT12, FAT16, or FAT32 */
/* Boot code comes next, all but 2 bytes to fill up sector */
/* Boot sign comes last, 2 bytes */
} volume_info;
typedef struct dir_entry {
char name[8],ext[3]; /* Name and extension */
__u8 attr; /* Attribute bits */
__u8 lcase; /* Case for base and extension */
__u8 ctime_ms; /* Creation time, milliseconds */
__u16 ctime; /* Creation time */
__u16 cdate; /* Creation date */
__u16 adate; /* Last access date */
__u16 starthi; /* High 16 bits of cluster in FAT32 */
__u16 time,date,start;/* Time, date and first cluster */
__u32 size; /* File size in bytes */
} dir_entry;
typedef struct dir_slot {
__u8 id; /* Sequence number for slot */
__u8 name0_4[10]; /* First 5 characters in name */
__u8 attr; /* Attribute byte */
__u8 reserved; /* Unused */
__u8 alias_checksum;/* Checksum for 8.3 alias */
__u8 name5_10[12]; /* 6 more characters in name */
__u16 start; /* Unused */
__u8 name11_12[4]; /* Last 2 characters in name */
} dir_slot;
/*
* Private filesystem parameters
*
* Note: FAT buffer has to be 32 bit aligned
* (see FAT32 accesses)
*/
typedef struct {
__u8 *fatbuf; /* Current FAT buffer */
int fatsize; /* Size of FAT in bits */
__u16 fatlength; /* Length of FAT in sectors */
__u16 fat_sect; /* Starting sector of the FAT */
__u16 rootdir_sect; /* Start sector of root directory */
__u16 sect_size; /* Size of sectors in bytes */
__u16 clust_size; /* Size of clusters in sectors */
short data_begin; /* The sector of the first cluster, can be negative */
int fatbufnum; /* Used by get_fatent, init to -1 */
} fsdata;
typedef int (file_detectfs_func)(void);
typedef int (file_ls_func)(const char *dir);
typedef long (file_read_func)(const char *filename, void *buffer,
unsigned long maxsize);
struct filesystem {
file_detectfs_func *detect;
file_ls_func *ls;
file_read_func *read;
const char name[12];
};
/* FAT tables */
file_detectfs_func file_fat_detectfs;
file_ls_func file_fat_ls;
file_read_func file_fat_read;
/* Currently this doesn't check if the dir exists or is valid... */
int file_cd(const char *path);
int file_fat_detectfs(void);
int file_fat_ls(const char *dir);
long file_fat_read(const char *filename, void *buffer, unsigned long maxsize);
const char *file_getfsname(int idx);
int fat_register_device(block_dev_desc_t *dev_desc, int part_no);
int file_fat_write(const char *filename, void *buffer, unsigned long maxsize);
#endif /* _FAT_H_ */
|
1001-study-uboot
|
include/fat.h
|
C
|
gpl3
| 7,081
|
/************************************************
* NAME : arm925t.h
* Version : 23 June 2003 *
************************************************/
#ifndef __ARM925T_H__
#define __ARM925T_H__
void archflashwp(void *archdata, int wp);
#endif /*__ARM925T_H__*/
|
1001-study-uboot
|
include/arm925t.h
|
C
|
gpl3
| 270
|
/*
* (C) Copyright 2007
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FDT_SUPPORT_H
#define __FDT_SUPPORT_H
#ifdef CONFIG_OF_LIBFDT
#include <fdt.h>
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
const char *prop, const u32 dflt);
int fdt_chosen(void *fdt, int force);
int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
const void *val, int len, int create);
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
u32 val, int create);
static inline void do_fixup_by_path_string(void *fdt, const char *path,
const char *prop, const char *status)
{
do_fixup_by_path(fdt, path, prop, status, strlen(status) + 1, 1);
}
void do_fixup_by_prop(void *fdt,
const char *pname, const void *pval, int plen,
const char *prop, const void *val, int len,
int create);
void do_fixup_by_prop_u32(void *fdt,
const char *pname, const void *pval, int plen,
const char *prop, u32 val, int create);
void do_fixup_by_compat(void *fdt, const char *compat,
const char *prop, const void *val, int len, int create);
void do_fixup_by_compat_u32(void *fdt, const char *compat,
const char *prop, u32 val, int create);
int fdt_fixup_memory(void *blob, u64 start, u64 size);
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
void fdt_fixup_ethernet(void *fdt);
int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
const void *val, int len, int create);
void fdt_fixup_qe_firmware(void *fdt);
#ifdef CONFIG_HAS_FSL_DR_USB
void fdt_fixup_dr_usb(void *blob, bd_t *bd);
#else
static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
#endif /* CONFIG_HAS_FSL_DR_USB */
#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
void fdt_fixup_crypto_node(void *blob, int sec_rev);
#else
static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
#endif
#ifdef CONFIG_PCI
#include <pci.h>
int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
#endif
#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup(void *blob, bd_t *bd);
void ft_cpu_setup(void *blob, bd_t *bd);
void ft_pci_setup(void *blob, bd_t *bd);
#endif
void set_working_fdt_addr(void *addr);
int fdt_resize(void *blob);
int fdt_increase_size(void *fdt, int add_len);
int fdt_fixup_nor_flash_size(void *blob);
void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
void fdt_del_node_and_alias(void *blob, const char *alias);
u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
phys_addr_t compat_off);
int fdt_alloc_phandle(void *blob);
int fdt_set_phandle(void *fdt, int nodeoffset, uint32_t phandle);
unsigned int fdt_create_phandle(void *fdt, int nodeoffset);
int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
u64 addr);
u64 fdt_get_base_address(void *fdt, int node);
enum fdt_status {
FDT_STATUS_OKAY,
FDT_STATUS_DISABLED,
FDT_STATUS_FAIL,
FDT_STATUS_FAIL_ERROR_CODE,
};
int fdt_set_node_status(void *fdt, int nodeoffset,
enum fdt_status status, unsigned int error_code);
static inline int fdt_status_okay(void *fdt, int nodeoffset)
{
return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_OKAY, 0);
}
static inline int fdt_status_disabled(void *fdt, int nodeoffset)
{
return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_DISABLED, 0);
}
int fdt_set_status_by_alias(void *fdt, const char* alias,
enum fdt_status status, unsigned int error_code);
static inline int fdt_status_okay_by_alias(void *fdt, const char* alias)
{
return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_OKAY, 0);
}
static inline int fdt_status_disabled_by_alias(void *fdt, const char* alias)
{
return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_DISABLED, 0);
}
#endif /* ifdef CONFIG_OF_LIBFDT */
#endif /* ifndef __FDT_SUPPORT_H */
|
1001-study-uboot
|
include/fdt_support.h
|
C
|
gpl3
| 4,864
|
#ifndef __EXPORTS_H__
#define __EXPORTS_H__
#ifndef __ASSEMBLY__
/* These are declarations of exported functions available in C code */
unsigned long get_version(void);
int getc(void);
int tstc(void);
void putc(const char);
void puts(const char*);
int printf(const char* fmt, ...);
void install_hdlr(int, void (*interrupt_handler_t)(void *), void*);
void free_hdlr(int);
void *malloc(size_t);
void free(void*);
void __udelay(unsigned long);
unsigned long get_timer(unsigned long);
int vprintf(const char *, va_list);
unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base);
int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
char *getenv (const char *name);
int setenv (const char *varname, const char *varvalue);
long simple_strtol(const char *cp,char **endp,unsigned int base);
int strcmp(const char * cs,const char * ct);
int ustrtoul(const char *cp, char **endp, unsigned int base);
#if defined(CONFIG_CMD_I2C)
int i2c_write (uchar, uint, int , uchar* , int);
int i2c_read (uchar, uint, int , uchar* , int);
#endif
void app_startup(char * const *);
#endif /* ifndef __ASSEMBLY__ */
enum {
#define EXPORT_FUNC(x) XF_ ## x ,
#include <_exports.h>
#undef EXPORT_FUNC
XF_MAX
};
#define XF_VERSION 6
#if defined(CONFIG_X86)
extern gd_t *global_data;
#endif
#endif /* __EXPORTS_H__ */
|
1001-study-uboot
|
include/exports.h
|
C
|
gpl3
| 1,341
|
/*
* (C) Copyright 2011
* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __PCA9698_H_
#define __PCA9698_H_
int pca9698_request(unsigned gpio, const char *label);
void pca9698_free(unsigned gpio);
int pca9698_direction_input(u8 addr, unsigned gpio);
int pca9698_direction_output(u8 addr, unsigned gpio, int value);
int pca9698_get_value(u8 addr, unsigned gpio);
int pca9698_set_value(u8 addr, unsigned gpio, int value);
#endif /* __PCA9698_H_ */
|
1001-study-uboot
|
include/pca9698.h
|
C
|
gpl3
| 1,266
|
/*
* (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __COMMON_H_
#define __COMMON_H_ 1
#undef _LINUX_CONFIG_H
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
typedef unsigned char uchar;
typedef volatile unsigned long vu_long;
typedef volatile unsigned short vu_short;
typedef volatile unsigned char vu_char;
#include <config.h>
#include <asm-offsets.h>
#include <linux/bitops.h>
#include <linux/types.h>
#include <linux/string.h>
#include <asm/ptrace.h>
#include <stdarg.h>
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
#include <pci.h>
#endif
#if defined(CONFIG_8xx)
#include <asm/8xx_immap.h>
#if defined(CONFIG_MPC852) || defined(CONFIG_MPC852T) || \
defined(CONFIG_MPC859) || defined(CONFIG_MPC859T) || \
defined(CONFIG_MPC859DSL) || \
defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \
defined(CONFIG_MPC866P)
# define CONFIG_MPC866_FAMILY 1
#elif defined(CONFIG_MPC870) \
|| defined(CONFIG_MPC875) \
|| defined(CONFIG_MPC880) \
|| defined(CONFIG_MPC885)
# define CONFIG_MPC885_FAMILY 1
#endif
#if defined(CONFIG_MPC860) \
|| defined(CONFIG_MPC860T) \
|| defined(CONFIG_MPC866_FAMILY) \
|| defined(CONFIG_MPC885_FAMILY)
# define CONFIG_MPC86x 1
#endif
#elif defined(CONFIG_5xx)
#include <asm/5xx_immap.h>
#elif defined(CONFIG_MPC5xxx)
#include <mpc5xxx.h>
#elif defined(CONFIG_MPC512X)
#include <asm/immap_512x.h>
#elif defined(CONFIG_MPC8220)
#include <asm/immap_8220.h>
#elif defined(CONFIG_8260)
#if defined(CONFIG_MPC8247) \
|| defined(CONFIG_MPC8248) \
|| defined(CONFIG_MPC8271) \
|| defined(CONFIG_MPC8272)
#define CONFIG_MPC8272_FAMILY 1
#endif
#if defined(CONFIG_MPC8272_FAMILY)
#define CONFIG_MPC8260 1
#endif
#include <asm/immap_8260.h>
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
#include <asm/immap_86xx.h>
#endif
#ifdef CONFIG_MPC85xx
#include <mpc85xx.h>
#include <asm/immap_85xx.h>
#endif
#ifdef CONFIG_MPC83xx
#include <mpc83xx.h>
#include <asm/immap_83xx.h>
#endif
#ifdef CONFIG_4xx
#include <asm/ppc4xx.h>
#endif
#ifdef CONFIG_HYMOD
#include <board/hymod/hymod.h>
#endif
#ifdef CONFIG_ARM
#define asmlinkage /* nothing */
#endif
#ifdef CONFIG_BLACKFIN
#include <asm/blackfin.h>
#endif
#ifdef CONFIG_SOC_DA8XX
#include <asm/arch/hardware.h>
#endif
#include <part.h>
#include <flash.h>
#include <image.h>
#ifdef DEBUG
#define _DEBUG 1
#else
#define _DEBUG 0
#endif
/*
* Output a debug text when condition "cond" is met. The "cond" should be
* computed by a preprocessor in the best case, allowing for the best
* optimization.
*/
#define debug_cond(cond, fmt, args...) \
do { \
if (cond) \
printf(fmt, ##args); \
} while (0)
#define debug(fmt, args...) \
debug_cond(_DEBUG, fmt, ##args)
/*
* An assertion is run-time check done in debug mode only. If DEBUG is not
* defined then it is skipped. If DEBUG is defined and the assertion fails,
* then it calls panic*( which may or may not reset/halt U-Boot (see
* CONFIG_PANIC_HANG), It is hoped that all failing assertions are found
* before release, and after release it is hoped that they don't matter. But
* in any case these failing assertions cannot be fixed with a reset (which
* may just do the same assertion again).
*/
void __assert_fail(const char *assertion, const char *file, unsigned line,
const char *function);
#define assert(x) \
({ if (!(x) && _DEBUG) \
__assert_fail(#x, __FILE__, __LINE__, __func__); })
#define error(fmt, args...) do { \
printf("ERROR: " fmt "\nat %s:%d/%s()\n", \
##args, __FILE__, __LINE__, __func__); \
} while (0)
#ifndef BUG
#define BUG() do { \
printf("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
panic("BUG!"); \
} while (0)
#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
#endif /* BUG */
/* Force a compilation error if condition is true */
#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
typedef void (interrupt_handler_t)(void *);
#include <asm/u-boot.h> /* boot information for Linux kernel */
#include <asm/global_data.h> /* global data used for startup functions */
/*
* enable common handling for all TQM8xxL/M boards:
* - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
* - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
* and for the TQM885D board
*/
#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
# ifndef CONFIG_TQM8xxM
# define CONFIG_TQM8xxM
# endif
#endif
#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) || \
defined(CONFIG_TQM855L) || defined(CONFIG_TQM860L) || \
defined(CONFIG_TQM862L) || defined(CONFIG_TQM8xxM) || \
defined(CONFIG_TQM885D)
# ifndef CONFIG_TQM8xxL
# define CONFIG_TQM8xxL
# endif
#endif
#ifndef CONFIG_SERIAL_MULTI
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \
|| defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
#define CONFIG_SERIAL_MULTI 1
#endif
#endif /* CONFIG_SERIAL_MULTI */
/*
* General Purpose Utilities
*/
#define min(X, Y) \
({ typeof (X) __x = (X); \
typeof (Y) __y = (Y); \
(__x < __y) ? __x : __y; })
#define max(X, Y) \
({ typeof (X) __x = (X); \
typeof (Y) __y = (Y); \
(__x > __y) ? __x : __y; })
#define MIN(x, y) min(x, y)
#define MAX(x, y) max(x, y)
#if defined(CONFIG_ENV_IS_EMBEDDED)
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
(CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
defined(CONFIG_ENV_IS_IN_NVRAM)
#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
#else
#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
#endif
/**
* container_of - cast a member of a structure out to the containing structure
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*
*/
#define container_of(ptr, type, member) ({ \
const typeof( ((type *)0)->member ) *__mptr = (ptr); \
(type *)( (char *)__mptr - offsetof(type,member) );})
/*
* Function Prototypes
*/
void hang (void) __attribute__ ((noreturn));
int timer_init(void);
int cpu_init(void);
/* */
phys_size_t initdram (int);
int display_options (void);
void print_size(unsigned long long, const char *);
int print_buffer (ulong addr, void* data, uint width, uint count, uint linelen);
/* common/main.c */
void main_loop (void);
int run_command (const char *cmd, int flag);
#ifdef CONFIG_CMD_PXE
int run_command2(const char *cmd, int flag);
#endif
int readline (const char *const prompt);
int readline_into_buffer (const char *const prompt, char * buffer);
int parse_line (char *, char *[]);
void init_cmd_timeout(void);
void reset_cmd_timeout(void);
#ifdef CONFIG_MENU
int abortboot(int bootdelay);
#endif
extern char console_buffer[];
/* arch/$(ARCH)/lib/board.c */
void board_init_f (ulong) __attribute__ ((noreturn));
void board_init_r (gd_t *, ulong) __attribute__ ((noreturn));
int checkboard (void);
int checkflash (void);
int checkdram (void);
int last_stage_init(void);
extern ulong monitor_flash_len;
int mac_read_from_eeprom(void);
extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */
/*
* Called when console output is requested before the console is available.
* The board should do its best to get the character out to the user any way
* it can.
*/
void board_pre_console_putc(int ch);
/* common/flash.c */
void flash_perror (int);
/* common/cmd_source.c */
int source (ulong addr, const char *fit_uname);
extern ulong load_addr; /* Default Load Address */
extern ulong save_addr; /* Default Save Address */
extern ulong save_size; /* Default Save Size */
/* common/cmd_doc.c */
void doc_probe(unsigned long physadr);
/* common/cmd_net.c */
int do_tftpb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
/* common/cmd_nvedit.c */
int env_init (void);
void env_relocate (void);
int envmatch (uchar *, int);
char *getenv (const char *);
int getenv_f (const char *name, char *buf, unsigned len);
ulong getenv_ulong(const char *name, int base, ulong default_val);
int saveenv (void);
#ifdef CONFIG_PPC /* ARM version to be fixed! */
int inline setenv (const char *, const char *);
#else
int setenv (const char *, const char *);
int setenv_ulong(const char *varname, ulong value);
int setenv_addr(const char *varname, const void *addr);
#endif /* CONFIG_PPC */
#ifdef CONFIG_ARM
# include <asm/mach-types.h>
# include <asm/setup.h>
# include <asm/u-boot-arm.h> /* ARM version to be fixed! */
#endif /* CONFIG_ARM */
#ifdef CONFIG_X86 /* x86 version to be fixed! */
# include <asm/u-boot-x86.h>
#endif /* CONFIG_X86 */
#ifdef CONFIG_SANDBOX
# include <asm/u-boot-sandbox.h> /* TODO(sjg) what needs to be fixed? */
#endif
#ifdef CONFIG_NDS32
# include <asm/mach-types.h>
# include <asm/u-boot-nds32.h>
#endif /* CONFIG_NDS32 */
#ifdef CONFIG_AUTO_COMPLETE
int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
#endif
int get_env_id (void);
void pci_init (void);
void pci_init_board(void);
void pciinfo (int, int);
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
int pci_pre_init (struct pci_controller *);
int is_pci_host (struct pci_controller *);
#endif
#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX))
# if defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif
# if defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init (struct pci_controller *);
# endif
#if defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_405EX)
void pcie_setup_hoses(int busno);
#endif
#endif
int misc_init_f (void);
int misc_init_r (void);
/* common/exports.c */
void jumptable_init(void);
/* common/kallsysm.c */
const char *symbol_lookup(unsigned long addr, unsigned long *caddr);
/* api/api.c */
void api_init (void);
/* common/memsize.c */
long get_ram_size (long *, long);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
void fdc_hw_init (void);
/* $(BOARD)/eeprom.c */
void eeprom_init (void);
#ifndef CONFIG_SPI
int eeprom_probe (unsigned dev_addr, unsigned offset);
#endif
int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
#ifdef CONFIG_LWMON
extern uchar pic_read (uchar reg);
extern void pic_write (uchar reg, uchar val);
#endif
/*
* Set this up regardless of board
* type, to prevent errors.
*/
#if defined(CONFIG_SPI) || !defined(CONFIG_SYS_I2C_EEPROM_ADDR)
# define CONFIG_SYS_DEF_EEPROM_ADDR 0
#else
#if !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
# define CONFIG_SYS_DEF_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
#endif
#endif /* CONFIG_SPI || !defined(CONFIG_SYS_I2C_EEPROM_ADDR) */
#if defined(CONFIG_SPI)
extern void spi_init_f (void);
extern void spi_init_r (void);
extern ssize_t spi_read (uchar *, int, uchar *, int);
extern ssize_t spi_write (uchar *, int, uchar *, int);
#endif
#ifdef CONFIG_RPXCLASSIC
void rpxclassic_init (void);
#endif
void rpxlite_init (void);
#ifdef CONFIG_MBX
/* $(BOARD)/mbx8xx.c */
void mbx_init (void);
void board_serial_init (void);
void board_ether_init (void);
#endif
#ifdef CONFIG_HERMES
/* $(BOARD)/hermes.c */
void hermes_start_lxt980 (int speed);
#endif
#ifdef CONFIG_EVB64260
void evb64260_init(void);
void debug_led(int, int);
void display_mem_map(void);
void perform_soft_reset(void);
#endif
/* $(BOARD)/$(BOARD).c */
int board_early_init_f (void);
int board_late_init (void);
int board_postclk_init (void); /* after clocks/timebase, before env/serial */
int board_early_init_r (void);
void board_poweroff (void);
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram(void);
#endif /* CONFIG_SYS_DRAM_TEST */
/* $(CPU)/start.S */
#if defined(CONFIG_5xx) || \
defined(CONFIG_8xx)
uint get_immr (uint);
#endif
uint get_pir (void);
#if defined(CONFIG_MPC5xxx)
uint get_svr (void);
#endif
uint get_pvr (void);
uint get_svr (void);
uint rd_ic_cst (void);
void wr_ic_cst (uint);
void wr_ic_adr (uint);
uint rd_dc_cst (void);
void wr_dc_cst (uint);
void wr_dc_adr (uint);
int icache_status (void);
void icache_enable (void);
void icache_disable(void);
int dcache_status (void);
void dcache_enable (void);
void dcache_disable(void);
void mmu_disable(void);
void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn));
ulong get_endaddr (void);
void trap_init (ulong);
#if defined (CONFIG_4xx) || \
defined (CONFIG_MPC5xxx) || \
defined (CONFIG_74xx_7xx) || \
defined (CONFIG_74x) || \
defined (CONFIG_75x) || \
defined (CONFIG_74xx) || \
defined (CONFIG_MPC8220) || \
defined (CONFIG_MPC85xx) || \
defined (CONFIG_MPC86xx) || \
defined (CONFIG_MPC83xx)
unsigned char in8(unsigned int);
void out8(unsigned int, unsigned char);
unsigned short in16(unsigned int);
unsigned short in16r(unsigned int);
void out16(unsigned int, unsigned short value);
void out16r(unsigned int, unsigned short value);
unsigned long in32(unsigned int);
unsigned long in32r(unsigned int);
void out32(unsigned int, unsigned long value);
void out32r(unsigned int, unsigned long value);
void ppcDcbf(unsigned long value);
void ppcDcbi(unsigned long value);
void ppcSync(void);
void ppcDcbz(unsigned long value);
#endif
#if defined (CONFIG_MICROBLAZE)
unsigned short in16(unsigned int);
void out16(unsigned int, unsigned short value);
#endif
#if defined (CONFIG_MPC83xx)
void ppcDWload(unsigned int *addr, unsigned int *ret);
void ppcDWstore(unsigned int *addr, unsigned int *value);
void disable_addr_trans(void);
void enable_addr_trans(void);
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
void ddr_enable_ecc(unsigned int dram_size);
#endif
#endif
/* $(CPU)/cpu.c */
static inline int cpumask_next(int cpu, unsigned int mask)
{
for (cpu++; !((1 << cpu) & mask); cpu++)
;
return cpu;
}
#define for_each_cpu(iter, cpu, num_cpus, mask) \
for (iter = 0, cpu = cpumask_next(-1, mask); \
iter < num_cpus; \
iter++, cpu = cpumask_next(cpu, mask)) \
int cpu_numcores (void);
u32 cpu_mask (void);
int is_core_valid (unsigned int);
int probecpu (void);
int checkcpu (void);
int checkicache (void);
int checkdcache (void);
void upmconfig (unsigned int, unsigned int *, unsigned int);
ulong get_tbclk (void);
void reset_cpu (ulong addr);
#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
void ft_cpu_setup(void *blob, bd_t *bd);
#ifdef CONFIG_PCI
void ft_pci_setup(void *blob, bd_t *bd);
#endif
#endif
/* $(CPU)/serial.c */
int serial_init (void);
void serial_setbrg (void);
void serial_putc (const char);
void serial_putc_raw(const char);
void serial_puts (const char *);
int serial_getc (void);
int serial_tstc (void);
void _serial_setbrg (const int);
void _serial_putc (const char, const int);
void _serial_putc_raw(const char, const int);
void _serial_puts (const char *, const int);
int _serial_getc (const int);
int _serial_tstc (const int);
/* $(CPU)/speed.c */
int get_clocks (void);
int get_clocks_866 (void);
int sdram_adjust_866 (void);
int adjust_sdram_tbs_8xx (void);
#if defined(CONFIG_8260)
int prt_8260_clks (void);
#elif defined(CONFIG_MPC5xxx)
int prt_mpc5xxx_clks (void);
#endif
#if defined(CONFIG_MPC512X)
int prt_mpc512xxx_clks (void);
#endif
#if defined(CONFIG_MPC8220)
int prt_mpc8220_clks (void);
#endif
#ifdef CONFIG_4xx
ulong get_OPB_freq (void);
ulong get_PCI_freq (void);
#endif
#if defined(CONFIG_S3C24X0) || \
defined(CONFIG_LH7A40X) || \
defined(CONFIG_S3C6400) || \
defined(CONFIG_EP93XX)
ulong get_FCLK (void);
ulong get_HCLK (void);
ulong get_PCLK (void);
ulong get_UCLK (void);
#endif
#if defined(CONFIG_LH7A40X)
ulong get_PLLCLK (void);
#endif
#if defined CONFIG_INCA_IP
uint incaip_get_cpuclk (void);
#endif
#if defined(CONFIG_IMX)
ulong get_systemPLLCLK(void);
ulong get_FCLK(void);
ulong get_HCLK(void);
ulong get_BCLK(void);
ulong get_PERCLK1(void);
ulong get_PERCLK2(void);
ulong get_PERCLK3(void);
#endif
ulong get_bus_freq (ulong);
int get_serial_clock(void);
#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
ulong get_ddr_freq(ulong);
#endif
#if defined(CONFIG_MPC85xx)
typedef MPC85xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
#endif
#if defined(CONFIG_MPC86xx)
typedef MPC86xx_SYS_INFO sys_info_t;
void get_sys_info ( sys_info_t * );
static inline ulong get_ddr_freq(ulong dummy)
{
return get_bus_freq(dummy);
}
#endif
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
# endif
# endif
typedef PPC4xx_SYS_INFO sys_info_t;
int ppc440spe_revB(void);
void get_sys_info ( sys_info_t * );
#endif
/* $(CPU)/cpu_init.c */
#if defined(CONFIG_8xx) || defined(CONFIG_8260)
void cpu_init_f (volatile immap_t *immr);
#endif
#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx)
void cpu_init_f (void);
#endif
int cpu_init_r (void);
#if defined(CONFIG_8260)
int prt_8260_rsr (void);
#elif defined(CONFIG_MPC83xx)
int prt_83xx_rsr (void);
#endif
/* $(CPU)/interrupts.c */
int interrupt_init (void);
void timer_interrupt (struct pt_regs *);
void external_interrupt (struct pt_regs *);
void irq_install_handler(int, interrupt_handler_t *, void *);
void irq_free_handler (int);
void reset_timer (void);
ulong get_timer (ulong base);
void enable_interrupts (void);
int disable_interrupts (void);
/* $(CPU)/.../commproc.c */
int dpram_init (void);
uint dpram_base(void);
uint dpram_base_align(uint align);
uint dpram_alloc(uint size);
uint dpram_alloc_align(uint size,uint align);
void bootcount_store (ulong);
ulong bootcount_load (void);
#define BOOTCOUNT_MAGIC 0xB001C041
/* $(CPU)/.../<eth> */
void mii_init (void);
/* $(CPU)/.../lcd.c */
ulong lcd_setmem (ulong);
/* $(CPU)/.../video.c */
ulong video_setmem (ulong);
/* arch/$(ARCH)/lib/cache.c */
void enable_caches(void);
void flush_cache (unsigned long, unsigned long);
void flush_dcache_all(void);
void flush_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_range(unsigned long start, unsigned long stop);
void invalidate_dcache_all(void);
void invalidate_icache_all(void);
/* arch/$(ARCH)/lib/ticks.S */
unsigned long long get_ticks(void);
void wait_ticks (unsigned long);
/* arch/$(ARCH)/lib/time.c */
void __udelay (unsigned long);
ulong usec2ticks (unsigned long usec);
ulong ticks2usec (unsigned long ticks);
int init_timebase (void);
/* lib/gunzip.c */
int gunzip(void *, int, unsigned char *, unsigned long *);
int zunzip(void *dst, int dstlen, unsigned char *src, unsigned long *lenp,
int stoponerr, int offset);
/* lib/net_utils.c */
#include <net.h>
static inline IPaddr_t getenv_IPaddr (char *var)
{
return (string_to_ip(getenv(var)));
}
/* lib/qsort.c */
void qsort(void *base, size_t nmemb, size_t size,
int(*compar)(const void *, const void *));
int strcmp_compar(const void *, const void *);
/* lib/time.c */
void udelay (unsigned long);
void mdelay(unsigned long);
/* lib/uuid.c */
void uuid_str_to_bin(const char *uuid, unsigned char *out);
int uuid_str_valid(const char *uuid);
/* lib/vsprintf.c */
ulong simple_strtoul(const char *cp,char **endp,unsigned int base);
int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base);
long simple_strtol(const char *cp,char **endp,unsigned int base);
void panic(const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2), noreturn));
int sprintf(char * buf, const char *fmt, ...)
__attribute__ ((format (__printf__, 2, 3)));
int vsprintf(char *buf, const char *fmt, va_list args);
char *simple_itoa(ulong i);
/* lib/strmhz.c */
char * strmhz(char *buf, unsigned long hz);
/* lib/crc32.c */
#include <u-boot/crc.h>
/* common/console.c */
int console_init_f(void); /* Before relocation; uses the serial stuff */
int console_init_r(void); /* After relocation; uses the console stuff */
int console_assign(int file, const char *devname); /* Assign the console */
int ctrlc (void);
int had_ctrlc (void); /* have we had a Control-C since last clear? */
void clear_ctrlc (void); /* clear the Control-C condition */
int disable_ctrlc (int); /* 1 to disable, 0 to enable Control-C detect */
/*
* STDIO based functions (can always be used)
*/
/* serial stuff */
int serial_printf (const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2)));
/* stdin */
int getc(void);
int tstc(void);
/* stdout */
void putc(const char c);
void puts(const char *s);
int printf(const char *fmt, ...)
__attribute__ ((format (__printf__, 1, 2)));
int vprintf(const char *fmt, va_list args);
/* stderr */
#define eputc(c) fputc(stderr, c)
#define eputs(s) fputs(stderr, s)
#define eprintf(fmt,args...) fprintf(stderr,fmt ,##args)
/*
* FILE based functions (can only be used AFTER relocation!)
*/
#define stdin 0
#define stdout 1
#define stderr 2
#define MAX_FILES 3
int fprintf(int file, const char *fmt, ...)
__attribute__ ((format (__printf__, 2, 3)));
void fputs(int file, const char *s);
void fputc(int file, const char c);
int ftstc(int file);
int fgetc(int file);
/*
* CONSOLE multiplexing.
*/
#ifdef CONFIG_CONSOLE_MUX
#include <iomux.h>
#endif
int pcmcia_init (void);
#ifdef CONFIG_STATUS_LED
# include <status_led.h>
#endif
/*
* Board-specific Platform code can reimplement show_boot_progress () if needed
*/
void show_boot_progress(int val);
/* Multicore arch functions */
#ifdef CONFIG_MP
int cpu_status(int nr);
int cpu_reset(int nr);
int cpu_disable(int nr);
int cpu_release(int nr, int argc, char * const argv[]);
#endif
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_PPC
/*
* Has to be included outside of the #ifndef __ASSEMBLY__ section.
* Otherwise might lead to compilation errors in assembler files.
*/
#include <asm/cache.h>
#endif
/* Put only stuff here that the assembler can digest */
#ifdef CONFIG_POST
#define CONFIG_HAS_POST
#ifndef CONFIG_POST_ALT_LIST
#define CONFIG_POST_STD_LIST
#endif
#endif
#ifdef CONFIG_INIT_CRITICAL
#error CONFIG_INIT_CRITICAL is deprecated!
#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
#endif
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define ROUND(a,b) (((a) + (b) - 1) & ~((b) - 1))
#define DIV_ROUND(n,d) (((n) + ((d)/2)) / (d))
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
/*
* ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture. It
* is used to align DMA buffers.
*/
#ifndef __ASSEMBLY__
#include <asm/cache.h>
#endif
/*
* The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
* stack that meets the minimum architecture alignment requirements for DMA.
* Such a buffer is useful for DMA operations where flushing and invalidating
* the cache before and after a read and/or write operation is required for
* correct operations.
*
* When called the macro creates an array on the stack that is sized such
* that:
*
* 1) The beginning of the array can be advanced enough to be aligned.
*
* 2) The size of the aligned portion of the array is a multiple of the minimum
* architecture alignment required for DMA.
*
* 3) The aligned portion contains enough space for the original number of
* elements requested.
*
* The macro then creates a pointer to the aligned portion of this array and
* assigns to the pointer the address of the first element in the aligned
* portion of the array.
*
* Calling the macro as:
*
* ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
*
* Will result in something similar to saying:
*
* uint32_t buffer[1024];
*
* The following differences exist:
*
* 1) The resulting buffer is guaranteed to be aligned to the value of
* ARCH_DMA_MINALIGN.
*
* 2) The buffer variable created by the macro is a pointer to the specified
* type, and NOT an array of the specified type. This can be very important
* if you want the address of the buffer, which you probably do, to pass it
* to the DMA hardware. The value of &buffer is different in the two cases.
* In the macro case it will be the address of the pointer, not the address
* of the space reserved for the buffer. However, in the second case it
* would be the address of the buffer. So if you are replacing hard coded
* stack buffers with this macro you need to make sure you remove the & from
* the locations where you are taking the address of the buffer.
*
* Note that the size parameter is the number of array elements to allocate,
* not the number of bytes.
*
* This macro can not be used outside of function scope, or for the creation
* of a function scoped static buffer. It can not be used to create a cache
* line aligned global buffer.
*/
#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size) \
char __##name[ROUND(size * sizeof(type), ARCH_DMA_MINALIGN) + \
ARCH_DMA_MINALIGN - 1]; \
\
type *name = (type *) ALIGN((uintptr_t)__##name, ARCH_DMA_MINALIGN)
/* Pull in stuff for the build system */
#ifdef DO_DEPS_ONLY
# include <environment.h>
#endif
#endif /* __COMMON_H_ */
|
1001-study-uboot
|
include/common.h
|
C
|
gpl3
| 26,815
|
/*
* (C) Copyright 2003
* Orbacom Systems, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __LYNXKDI_H__
#define __LYNXKDI_H__
/* Boot parameter struct passed to kernel
*/
typedef struct lynxos_bootparms_t {
uint8_t rsvd1[2]; /* Reserved */
uint8_t ethaddr[6]; /* Ethernet address */
uint16_t flags; /* Boot flags */
uint32_t rate; /* System frequency */
uint32_t clock_ref; /* Time reference */
uint32_t dramsz; /* DRAM size */
uint32_t rsvd2; /* Reserved */
} lynxos_bootparms_t;
#endif /* __LYNXKDI_H__ */
|
1001-study-uboot
|
include/lynxkdi.h
|
C
|
gpl3
| 1,305
|
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006.
* Author: Jason Jin<Jason.jin@freescale.com>
* Zhang Wei<wei.zhang@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _AHCI_H_
#define _AHCI_H_
#include <pci.h>
#define AHCI_PCI_BAR 0x24
#define AHCI_MAX_SG 56 /* hardware max is 64K */
#define AHCI_CMD_SLOT_SZ 32
#define AHCI_RX_FIS_SZ 256
#define AHCI_CMD_TBL_HDR 0x80
#define AHCI_CMD_TBL_CDB 0x40
#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \
+ AHCI_RX_FIS_SZ
#define AHCI_CMD_ATAPI (1 << 5)
#define AHCI_CMD_WRITE (1 << 6)
#define AHCI_CMD_PREFETCH (1 << 7)
#define AHCI_CMD_RESET (1 << 8)
#define AHCI_CMD_CLR_BUSY (1 << 10)
#define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
/* Global controller registers */
#define HOST_CAP 0x00 /* host capabilities */
#define HOST_CTL 0x04 /* global host control */
#define HOST_IRQ_STAT 0x08 /* interrupt status */
#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
#define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
/* HOST_CTL bits */
#define HOST_RESET (1 << 0) /* reset controller; self-clear */
#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
/* Registers for each SATA port */
#define PORT_LST_ADDR 0x00 /* command list DMA addr */
#define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
#define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
#define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
#define PORT_IRQ_STAT 0x10 /* interrupt status */
#define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
#define PORT_CMD 0x18 /* port command */
#define PORT_TFDATA 0x20 /* taskfile data */
#define PORT_SIG 0x24 /* device TF signature */
#define PORT_CMD_ISSUE 0x38 /* command issue */
#define PORT_SCR 0x28 /* SATA phy register block */
#define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
#define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
#define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
#define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
/* PORT_IRQ_{STAT,MASK} bits */
#define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
#define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
#define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
#define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
#define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
#define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
#define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
#define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
#define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
#define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
| PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
#define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
| PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
| PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
| PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
| PORT_IRQ_D2H_REG_FIS
/* PORT_CMD bits */
#define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
#define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
#define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
#define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
#define PORT_CMD_CLO (1 << 3) /* Command list override */
#define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
#define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
#define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
#define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
#define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
#define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
#define AHCI_MAX_PORTS 32
/* SETFEATURES stuff */
#define SETFEATURES_XFER 0x03
#define XFER_UDMA_7 0x47
#define XFER_UDMA_6 0x46
#define XFER_UDMA_5 0x45
#define XFER_UDMA_4 0x44
#define XFER_UDMA_3 0x43
#define XFER_UDMA_2 0x42
#define XFER_UDMA_1 0x41
#define XFER_UDMA_0 0x40
#define XFER_MW_DMA_2 0x22
#define XFER_MW_DMA_1 0x21
#define XFER_MW_DMA_0 0x20
#define XFER_SW_DMA_2 0x12
#define XFER_SW_DMA_1 0x11
#define XFER_SW_DMA_0 0x10
#define XFER_PIO_4 0x0C
#define XFER_PIO_3 0x0B
#define XFER_PIO_2 0x0A
#define XFER_PIO_1 0x09
#define XFER_PIO_0 0x08
#define XFER_PIO_SLOW 0x00
#define ATA_FLAG_SATA (1 << 3)
#define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
#define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
#define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
#define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
#define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
struct ahci_cmd_hdr {
u32 opts;
u32 status;
u32 tbl_addr;
u32 tbl_addr_hi;
u32 reserved[4];
};
struct ahci_sg {
u32 addr;
u32 addr_hi;
u32 reserved;
u32 flags_size;
};
struct ahci_ioports {
u32 cmd_addr;
u32 scr_addr;
u32 port_mmio;
struct ahci_cmd_hdr *cmd_slot;
struct ahci_sg *cmd_tbl_sg;
u32 cmd_tbl;
u32 rx_fis;
};
struct ahci_probe_ent {
pci_dev_t dev;
struct ahci_ioports port[AHCI_MAX_PORTS];
u32 n_ports;
u32 hard_port_no;
u32 host_flags;
u32 host_set_flags;
u32 mmio_base;
u32 pio_mask;
u32 udma_mask;
u32 flags;
u32 cap; /* cache of HOST_CAP register */
u32 port_map; /* cache of HOST_PORTS_IMPL reg */
u32 link_port_map; /*linkup port map*/
};
int ahci_init(u32 base);
#endif
|
1001-study-uboot
|
include/ahci.h
|
C
|
gpl3
| 6,778
|
#ifndef _ASM_GENERIC_DIV64_H
#define _ASM_GENERIC_DIV64_H
/*
* Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
* Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
*
* The semantics of do_div() are:
*
* uint32_t do_div(uint64_t *n, uint32_t base)
* {
* uint32_t remainder = *n % base;
* *n = *n / base;
* return remainder;
* }
*
* NOTE: macro parameter n is evaluated multiple times,
* beware of side effects!
*/
#include <linux/types.h>
extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor);
/* The unnecessary pointer compare is there
* to check for type safety (n must be 64bit)
*/
# define do_div(n,base) ({ \
uint32_t __base = (base); \
uint32_t __rem; \
(void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
if (((n) >> 32) == 0) { \
__rem = (uint32_t)(n) % __base; \
(n) = (uint32_t)(n) / __base; \
} else \
__rem = __div64_32(&(n), __base); \
__rem; \
})
/* Wrapper for do_div(). Doesn't modify dividend and returns
* the result, not reminder.
*/
static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor)
{
uint64_t __res = dividend;
do_div(__res, divisor);
return(__res);
}
#endif /* _ASM_GENERIC_DIV64_H */
|
1001-study-uboot
|
include/div64.h
|
C
|
gpl3
| 1,218
|
/*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MC13892_H__
#define __MC13892_H__
/* REG_CHARGE */
#define VCHRG0 (1 << 0)
#define VCHRG1 (1 << 1)
#define VCHRG2 (1 << 2)
#define ICHRG0 (1 << 3)
#define ICHRG1 (1 << 4)
#define ICHRG2 (1 << 5)
#define ICHRG3 (1 << 6)
#define TREN (1 << 7)
#define ACKLPB (1 << 8)
#define THCHKB (1 << 9)
#define FETOVRD (1 << 10)
#define FETCTRL (1 << 11)
#define RVRSMODE (1 << 13)
#define PLIM0 (1 << 15)
#define PLIM1 (1 << 16)
#define PLIMDIS (1 << 17)
#define CHRGLEDEN (1 << 18)
#define CHGTMRRST (1 << 19)
#define CHGRESTART (1 << 20)
#define CHGAUTOB (1 << 21)
#define CYCLB (1 << 22)
#define CHGAUTOVIB (1 << 23)
/* REG_SETTING_0/1 */
#define VO_1_20V 0
#define VO_1_30V 1
#define VO_1_50V 2
#define VO_1_80V 3
#define VO_1_10V 4
#define VO_2_00V 5
#define VO_2_77V 6
#define VO_2_40V 7
#define VIOL 2
#define VDIG 4
#define VGEN 6
/* SWxMode for Normal/Standby Mode */
#define SWMODE_OFF_OFF 0
#define SWMODE_PWM_OFF 1
#define SWMODE_PWMPS_OFF 2
#define SWMODE_PFM_OFF 3
#define SWMODE_AUTO_OFF 4
#define SWMODE_PWM_PWM 5
#define SWMODE_PWM_AUTO 6
#define SWMODE_AUTO_AUTO 8
#define SWMODE_PWM_PWMPS 9
#define SWMODE_PWMS_PWMPS 10
#define SWMODE_PWMS_AUTO 11
#define SWMODE_AUTO_PFM 12
#define SWMODE_PWM_PFM 13
#define SWMODE_PWMS_PFM 14
#define SWMODE_PFM_PFM 15
#define SWMODE_MASK 0x0F
#define SWMODE1_SHIFT 0
#define SWMODE2_SHIFT 10
#define SWMODE3_SHIFT 0
#define SWMODE4_SHIFT 8
/* Fields in REG_SETTING_1 */
#define VVIDEO_2_7 (0 << 2)
#define VVIDEO_2_775 (1 << 2)
#define VVIDEO_2_5 (2 << 2)
#define VVIDEO_2_6 (3 << 2)
#define VVIDEO_MASK (3 << 2)
#define VAUDIO_2_3 (0 << 4)
#define VAUDIO_2_5 (1 << 4)
#define VAUDIO_2_775 (2 << 4)
#define VAUDIO_3_0 (3 << 4)
#define VAUDIO_MASK (3 << 4)
#define VSD_1_8 (0 << 6)
#define VSD_2_0 (1 << 6)
#define VSD_2_6 (2 << 6)
#define VSD_2_7 (3 << 6)
#define VSD_2_8 (4 << 6)
#define VSD_2_9 (5 << 6)
#define VSD_3_0 (6 << 6)
#define VSD_3_15 (7 << 6)
#define VSD_MASK (7 << 6)
#define VGEN1_1_2 0
#define VGEN1_1_5 1
#define VGEN1_2_775 2
#define VGEN1_3_15 3
#define VGEN1_MASK 3
#define VGEN2_1_2 (0 << 6)
#define VGEN2_1_5 (1 << 6)
#define VGEN2_1_6 (2 << 6)
#define VGEN2_1_8 (3 << 6)
#define VGEN2_2_7 (4 << 6)
#define VGEN2_2_8 (5 << 6)
#define VGEN2_3_0 (6 << 6)
#define VGEN2_3_15 (7 << 6)
#define VGEN2_MASK (7 << 6)
/* Fields in REG_SETTING_1 */
#define VGEN3_1_8 (0 << 14)
#define VGEN3_2_9 (1 << 14)
#define VGEN3_MASK (1 << 14)
#define VDIG_1_05 (0 << 4)
#define VDIG_1_25 (1 << 4)
#define VDIG_1_65 (2 << 4)
#define VDIG_1_8 (3 << 4)
#define VDIG_MASK (3 << 4)
#define VCAM_2_5 (0 << 16)
#define VCAM_2_6 (1 << 16)
#define VCAM_2_75 (2 << 16)
#define VCAM_3_0 (3 << 16)
#define VCAM_MASK (3 << 16)
/* Reg Mode 0 */
#define VGEN1EN (1 << 0)
#define VGEN1STBY (1 << 1)
#define VGEN1MODE (1 << 2)
#define VIOHIEN (1 << 3)
#define VIOHISTBY (1 << 4)
#define VDIGEN (1 << 9)
#define VDIGSTBY (1 << 10)
#define VGEN2EN (1 << 12)
#define VGEN2STBY (1 << 13)
#define VGEN2MODE (1 << 14)
#define VPLLEN (1 << 15)
#define VPLLSTBY (1 << 16)
#define VUSBEN (1 << 18)
#define VUSBSTBY (1 << 19)
/* Reg Mode 1 */
#define VGEN3EN (1 << 0)
#define VGEN3STBY (1 << 1)
#define VGEN3MODE (1 << 2)
#define VGEN3CONFIG (1 << 3)
#define VCAMEN (1 << 6)
#define VCAMSTBY (1 << 7)
#define VCAMMODE (1 << 8)
#define VCAMCONFIG (1 << 9)
#define VVIDEOEN (1 << 12)
#define VIDEOSTBY (1 << 13)
#define VVIDEOMODE (1 << 14)
#define VAUDIOEN (1 << 15)
#define VAUDIOSTBY (1 << 16)
#define VSDEN (1 << 18)
#define VSDSTBY (1 << 19)
#define VSDMODE (1 << 20)
/* Reg Power Control 2*/
#define WDIRESET (1 << 12)
/* SWx Output Volts */
#define SWX_OUT_MASK 0x1F
#define SWX_OUT_1_25 0x1A
#define SWX_OUT_1_30 0X1C
/* Buck Switchers (SW1,2,3,4) Output Voltage */
/*
* NOTE: These values are for SWxHI = 0,
* SWxHI = 1 adds 0.5V to the desired voltage
*/
#define SWx_0_600V 0
#define SWx_0_625V 1
#define SWx_0_650V 2
#define SWx_0_675V 3
#define SWx_0_700V 4
#define SWx_0_725V 5
#define SWx_0_750V 6
#define SWx_0_775V 7
#define SWx_0_800V 8
#define SWx_0_825V 9
#define SWx_0_850V 10
#define SWx_0_875V 11
#define SWx_0_900V 12
#define SWx_0_925V 13
#define SWx_0_950V 14
#define SWx_0_975V 15
#define SWx_1_000V 16
#define SWx_1_025V 17
#define SWx_1_050V 18
#define SWx_1_075V 19
#define SWx_1_100V 20
#define SWx_1_125V 21
#define SWx_1_150V 22
#define SWx_1_175V 23
#define SWx_1_200V 24
#define SWx_1_225V 25
#define SWx_1_250V 26
#define SWx_1_275V 27
#define SWx_1_300V 28
#define SWx_1_325V 29
#define SWx_1_350V 30
#define SWx_1_375V 31
#define SWx_VOLT_MASK 0x1F
#endif
|
1001-study-uboot
|
include/mc13892.h
|
C
|
gpl3
| 5,534
|
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _HUSH_H_
#define _HUSH_H_
#define FLAG_EXIT_FROM_LOOP 1
#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */
#define FLAG_REPARSING (1 << 2) /* >=2nd pass */
extern int u_boot_hush_start(void);
extern int parse_string_outer(const char *, int);
extern int parse_file_outer(void);
int set_local_var(const char *s, int flg_export);
void unset_local_var(const char *name);
char *get_local_var(const char *s);
#if defined(CONFIG_HUSH_INIT_VAR)
extern int hush_init_var (void);
#endif
#endif
|
1001-study-uboot
|
include/hush.h
|
C
|
gpl3
| 1,414
|
/*
* config_cmd_defaults.h - sane defaults for everyone
*
* Copyright (c) 2010-2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _CONFIG_CMD_DEFAULTS_H_
#define _CONFIG_CMD_DEFAULTS_H_
#define CONFIG_CMD_BOOTM 1
#define CONFIG_CMD_CRC32 1
#define CONFIG_CMD_EXPORTENV 1
#define CONFIG_CMD_GO 1
#define CONFIG_CMD_IMPORTENV 1
#endif
|
1001-study-uboot
|
include/config_cmd_defaults.h
|
C
|
gpl3
| 366
|
/*
* (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __VERSION_H__
#define __VERSION_H__
#include <timestamp.h>
#ifndef DO_DEPS_ONLY
#include "generated/version_autogenerated.h"
#endif
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
#endif
#define U_BOOT_VERSION_STRING U_BOOT_VERSION " (" U_BOOT_DATE " - " \
U_BOOT_TIME ")" CONFIG_IDENT_STRING
#ifndef __ASSEMBLY__
extern const char version_string[];
#endif /* __ASSEMBLY__ */
#endif /* __VERSION_H__ */
|
1001-study-uboot
|
include/version.h
|
C
|
gpl3
| 1,315
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
* Keith Outwater, keith_outwater@mvis.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _VIRTEX2_H_
#define _VIRTEX2_H_
#include <xilinx.h>
extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
extern int Virtex2_info(Xilinx_desc *desc);
/*
* Slave SelectMap Implementation function table.
*/
typedef struct {
Xilinx_pre_fn pre;
Xilinx_pgm_fn pgm;
Xilinx_init_fn init;
Xilinx_err_fn err;
Xilinx_done_fn done;
Xilinx_clk_fn clk;
Xilinx_cs_fn cs;
Xilinx_wr_fn wr;
Xilinx_rdata_fn rdata;
Xilinx_wdata_fn wdata;
Xilinx_busy_fn busy;
Xilinx_abort_fn abort;
Xilinx_post_fn post;
} Xilinx_Virtex2_Slave_SelectMap_fns;
/* Slave Serial Implementation function table */
typedef struct {
Xilinx_pgm_fn pgm;
Xilinx_clk_fn clk;
Xilinx_rdata_fn rdata;
Xilinx_wdata_fn wdata;
} Xilinx_Virtex2_Slave_Serial_fns;
/* Device Image Sizes (in bytes)
*********************************************************************/
#define XILINX_XC2V40_SIZE (338208 / 8)
#define XILINX_XC2V80_SIZE (597408 / 8)
#define XILINX_XC2V250_SIZE (1591584 / 8)
#define XILINX_XC2V500_SIZE (2557857 / 8)
#define XILINX_XC2V1000_SIZE (3749408 / 8)
#define XILINX_XC2V1500_SIZE (5166240 / 8)
#define XILINX_XC2V2000_SIZE (6808352 / 8)
#define XILINX_XC2V3000_SIZE (9589408 / 8)
#define XILINX_XC2V4000_SIZE (14220192 / 8)
#define XILINX_XC2V6000_SIZE (19752096 / 8)
#define XILINX_XC2V8000_SIZE (26185120 / 8)
#define XILINX_XC2V10000_SIZE (33519264 / 8)
/* Descriptor Macros
*********************************************************************/
#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
#endif /* _VIRTEX2_H_ */
|
1001-study-uboot
|
include/virtex2.h
|
C
|
gpl3
| 3,976
|
/*
* Fake include for LzmaTools.h
*
* Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __LZMATOOLS_H__FAKE__
#define __LZMATOOLS_H__FAKE__
#include "../../lib/lzma/LzmaTools.h"
#endif
|
1001-study-uboot
|
include/lzma/LzmaTools.h
|
C
|
gpl3
| 1,058
|
/*
* Fake include for LzmaDec.h
*
* Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __LZMADEC_H__FAKE__
#define __LZMADEC_H__FAKE__
#include "../../lib/lzma/LzmaDec.h"
#endif
|
1001-study-uboot
|
include/lzma/LzmaDec.h
|
C
|
gpl3
| 1,050
|
/*
* Fake include for Types.h
*
* Copyright (C) 2007-2009 Industrie Dial Face S.p.A.
* Luigi 'Comio' Mantellini (luigi.mantellini@idf-hit.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __TYPES_H__FAKE__
#define __TYPES_H__FAKE__
/*
*This avoids the collition with zlib.h Byte definition
*/
#define Byte LZByte
#include "../../lib/lzma/Types.h"
#endif
|
1001-study-uboot
|
include/lzma/LzmaTypes.h
|
C
|
gpl3
| 1,126
|
/***********************************************************************
*
* Copyright (C) 2004 by FS Forth-Systeme GmbH.
* All rights reserved.
*
* $Id: ns9750_bbus.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
* @Author: Markus Pietrek
* @Descr: Definitions for BBus usage
* @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 10
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*
***********************************************************************/
#ifndef FS_NS9750_BBUS_H
#define FS_NS9750_BBUS_H
#define NS9750_BBUS_MODULE_BASE (0x90600000)
#define get_bbus_reg_addr(c) \
((volatile unsigned int *)(NS9750_BBUS_MODULE_BASE+(unsigned int) (c)))
/* We have support for 50 GPIO pins */
#define get_gpio_cfg_reg_addr(pin) \
get_bbus_reg_addr( NS9750_BBUS_GPIO_CFG_BASE + (((pin) >> 3) * 4) )
/* To Read/Modify/Write a pin configuration register, use it like
set_gpio_cfg_reg_val( 12, NS9750_GPIO_CFG_FUNC_GPIO|NS9750_GPIO_CFG_OUTPUT );
They should be wrapped by cli()/sti() */
#define set_gpio_cfg_reg_val(pin,cfg) \
*get_gpio_cfg_reg_addr(pin)=(*get_gpio_cfg_reg_addr((pin)) & \
~NS9750_GPIO_CFG_MASK((pin))) |\
NS9750_GPIO_CFG_VAL((pin),(cfg));
#define NS9750_GPIO_CFG_MASK(pin) (NS9750_GPIO_CFG_VAL(pin, \
NS9750_GPIO_CFG_MA))
#define NS9750_GPIO_CFG_VAL(pin,cfg) ((cfg) << (((pin) % 8) * 4))
#define NS9750_GPIO_CFG_MA (0x0F)
#define NS9750_GPIO_CFG_INPUT (0x00)
#define NS9750_GPIO_CFG_OUTPUT (0x08)
#define NS9750_GPIO_CFG_FUNC_GPIO (0x03)
#define NS9750_GPIO_CFG_FUNC_2 (0x02)
#define NS9750_GPIO_CFG_FUNC_1 (0x01)
#define NS9750_GPIO_CFG_FUNC_0 (0x00)
/* the register addresses */
#define NS9750_BBUS_MASTER_RESET (0x00)
#define NS9750_BBUS_GPIO_CFG_BASE (0x10)
#define NS9750_BBUS_GPIO_CTRL_BASE (0x30)
#define NS9750_BBUS_GPIO_STAT_BASE (0x40)
#define NS9750_BBUS_MONITOR (0x50)
#define NS9750_BBUS_DMA_INT_STAT (0x60)
#define NS9750_BBUS_DMA_INT_ENABLE (0x64)
#define NS9750_BBUS_USB_CFG (0x70)
#define NS9750_BBUS_ENDIAN_CFG (0x80)
#define NS9750_BBUS_ARM_WAKE_UP (0x90)
/* register bit fields */
#define NS9750_BBUS_MASTER_RESET_UTIL (0x00000100)
#define NS9750_BBUS_MASTER_RESET_I2C (0x00000080)
#define NS9750_BBUS_MASTER_RESET_1284 (0x00000040)
#define NS9750_BBUS_MASTER_RESET_SER4 (0x00000020)
#define NS9750_BBUS_MASTER_RESET_SER3 (0x00000010)
#define NS9750_BBUS_MASTER_RESET_SER2 (0x00000008)
#define NS9750_BBUS_MASTER_RESET_SER1 (0x00000004)
#define NS9750_BBUS_MASTER_RESET_USB (0x00000002)
#define NS9750_BBUS_MASTER_RESET_DMA (0x00000001)
/* BS9750_BBUS_DMA_INT_BINT* are valid for *DMA_INT_STAT and *DMA_INT_ENABLE */
#define NS9750_BBUS_DMA_INT_BINT16 (0x00010000)
#define NS9750_BBUS_DMA_INT_BINT15 (0x00008000)
#define NS9750_BBUS_DMA_INT_BINT14 (0x00004000)
#define NS9750_BBUS_DMA_INT_BINT13 (0x00002000)
#define NS9750_BBUS_DMA_INT_BINT12 (0x00001000)
#define NS9750_BBUS_DMA_INT_BINT11 (0x00000800)
#define NS9750_BBUS_DMA_INT_BINT10 (0x00000400)
#define NS9750_BBUS_DMA_INT_BINT9 (0x00000200)
#define NS9750_BBUS_DMA_INT_BINT8 (0x00000100)
#define NS9750_BBUS_DMA_INT_BINT7 (0x00000080)
#define NS9750_BBUS_DMA_INT_BINT6 (0x00000040)
#define NS9750_BBUS_DMA_INT_BINT5 (0x00000020)
#define NS9750_BBUS_DMA_INT_BINT4 (0x00000010)
#define NS9750_BBUS_DMA_INT_BINT3 (0x00000008)
#define NS9750_BBUS_DMA_INT_BINT2 (0x00000004)
#define NS9750_BBUS_DMA_INT_BINT1 (0x00000002)
#define NS9750_BBUS_DMA_INT_BINT0 (0x00000001)
#define NS9750_BBUS_USB_CFG_OUTEN (0x00000008)
#define NS9750_BBUS_USB_CFG_SPEED (0x00000004)
#define NS9750_BBUS_USB_CFG_CFG_MA (0x00000003)
#define NS9750_BBUS_USB_CFG_CFG_HOST_SOFT (0x00000003)
#define NS9750_BBUS_USB_CFG_CFG_DEVICE (0x00000002)
#define NS9750_BBUS_USB_CFG_CFG_HOST (0x00000001)
#define NS9750_BBUS_USB_CFG_CFG_DIS (0x00000000)
#define NS9750_BBUS_ENDIAN_CFG_AHBM (0x00001000)
#define NS9750_BBUS_ENDIAN_CFG_I2C (0x00000080)
#define NS9750_BBUS_ENDIAN_CFG_IEEE1284 (0x00000040)
#define NS9750_BBUS_ENDIAN_CFG_SER4 (0x00000020)
#define NS9750_BBUS_ENDIAN_CFG_SER3 (0x00000010)
#define NS9750_BBUS_ENDIAN_CFG_SER2 (0x00000008)
#define NS9750_BBUS_ENDIAN_CFG_SER1 (0x00000004)
#define NS9750_BBUS_ENDIAN_CFG_USB (0x00000002)
#define NS9750_BBUS_ENDIAN_CFG_DMA (0x00000001)
#endif /* FS_NS9750_BBUS_H */
|
1001-study-uboot
|
include/ns9750_bbus.h
|
C
|
gpl3
| 4,925
|
/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Date & Time support for the MK48T59 RTC
*/
#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
#define RTC_PORT_ADDR0 CONFIG_SYS_ISA_IO + 0x70
#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1
#define RTC_PORT_DATA CONFIG_SYS_ISA_IO + 0x76
/* RTC Offsets */
#define RTC_SECONDS 0x1FF9
#define RTC_MINUTES 0x1FFA
#define RTC_HOURS 0x1FFB
#define RTC_DAY_OF_WEEK 0x1FFC
#define RTC_DAY_OF_MONTH 0x1FFD
#define RTC_MONTH 0x1FFE
#define RTC_YEAR 0x1FFF
#define RTC_CONTROLA 0x1FF8
#define RTC_CA_WRITE 0x80
#define RTC_CA_READ 0x40
#define RTC_CA_CALIB_SIGN 0x20
#define RTC_CA_CALIB_MASK 0x1f
#define RTC_CONTROLB 0x1FF9
#define RTC_CB_STOP 0x80
#define RTC_WATCHDOG 0x1FF7
#define RTC_WDS 0x80
#define RTC_WD_RB_16TH 0x0
#define RTC_WD_RB_4TH 0x1
#define RTC_WD_RB_1 0x2
#define RTC_WD_RB_4 0x3
void rtc_set_watchdog(short multi, short res);
void *nvram_read(void *dest, const short src, size_t count);
void nvram_write(short dest, const void *src, size_t count);
#endif
|
1001-study-uboot
|
include/mk48t59.h
|
C
|
gpl3
| 2,071
|
/*
** MPC823 Video Controller
** =======================
** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
** AIRVENT SAM s.p.a - RIMINI(ITALY)
**
*/
#ifndef _VIDEO_H_
#define _VIDEO_H_
/* Video functions */
int video_init (void *videobase);
void video_putc (const char c);
void video_puts (const char *s);
void video_printf (const char *fmt, ...);
#endif
|
1001-study-uboot
|
include/video.h
|
C
|
gpl3
| 358
|
/*
* (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
*
* base on universe.h by
*
* (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _tsi148_h
#define _tsi148_h
#ifndef PCI_DEVICE_ID_TUNDRA_TSI148
#define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148
#endif
typedef struct _TSI148 TSI148;
typedef struct _OUTBOUND OUTBOUND;
typedef struct _INBOUND INBOUND;
typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
struct _OUTBOUND {
unsigned int otsau; /* 0x000 Outbound start upper */
unsigned int otsal; /* 0x004 Outbouud start lower */
unsigned int oteau; /* 0x008 Outbound end upper */
unsigned int oteal; /* 0x00c Outbound end lower */
unsigned int otofu; /* 0x010 Outbound translation upper */
unsigned int otofl; /* 0x014 Outbound translation lower */
unsigned int otbs; /* 0x018 Outbound translation 2eSST */
unsigned int otat; /* 0x01c Outbound translation attr */
};
struct _INBOUND {
unsigned int itsau; /* 0x000 inbound start upper */
unsigned int itsal; /* 0x004 inbouud start lower */
unsigned int iteau; /* 0x008 inbound end upper */
unsigned int iteal; /* 0x00c inbound end lower */
unsigned int itofu; /* 0x010 inbound translation upper */
unsigned int itofl; /* 0x014 inbound translation lower */
unsigned int itat; /* 0x018 inbound translation attr */
unsigned int spare; /* 0x01c not used */
};
struct _TSI148 {
unsigned int pci_id; /* 0x000 */
unsigned int pci_csr; /* 0x004 */
unsigned int pci_class; /* 0x008 */
unsigned int pci_misc0; /* 0x00c */
unsigned int pci_mbarl; /* 0x010 */
unsigned int pci_mbarh; /* 0x014 */
unsigned int spare0[(0x03c-0x018)/4]; /* 0x018 */
unsigned int pci_misc1; /* 0x03c */
unsigned int pci_pcixcap; /* 0x040 */
unsigned int pci_pcixstat; /* 0x044 */
unsigned int spare1[(0x100-0x048)/4]; /* 0x048 */
OUTBOUND outbound[8]; /* 0x100 */
unsigned int viack[8]; /* 0x204 */
unsigned int rmwau; /* 0x220 */
unsigned int rmwal; /* 0x224 */
unsigned int rmwen; /* 0x228 */
unsigned int rmwc; /* 0x22c */
unsigned int rmws; /* 0x230 */
unsigned int vmctrl; /* 0x234 */
unsigned int vctrl; /* 0x238 */
unsigned int vstat; /* 0x23c */
unsigned int pcsr; /* 0x240 */
unsigned int spare2[3]; /* 0x244 - 0x24c */
unsigned int vmefl; /* 0x250 */
unsigned int spare3[3]; /* 0x254 - 0x25c */
unsigned int veau; /* 0x260 */
unsigned int veal; /* 0x264 */
unsigned int veat; /* 0x268 */
unsigned int spare4[1]; /* 0x26c */
unsigned int edpau; /* 0x270 */
unsigned int edpal; /* 0x274 */
unsigned int edpxa; /* 0x278 */
unsigned int edpxs; /* 0x27c */
unsigned int edpat; /* 0x280 */
unsigned int spare5[31]; /* 0x284 - 0x2fc */
INBOUND inbound[8]; /* 0x100 */
unsigned int gbau; /* 0x400 */
unsigned int gbal; /* 0x404 */
unsigned int gcsrat; /* 0x408 */
unsigned int cbau; /* 0x40c */
unsigned int cbal; /* 0x410 */
unsigned int crgat; /* 0x414 */
unsigned int crou; /* 0x418 */
unsigned int crol; /* 0x41c */
unsigned int crat; /* 0x420 */
unsigned int lmbau; /* 0x424 */
unsigned int lmbal; /* 0x428 */
unsigned int lmat; /* 0x42c */
unsigned int r64bcu; /* 0x430 */
unsigned int r64bcl; /* 0x434 */
unsigned int bpgtr; /* 0x438 */
unsigned int bpctr; /* 0x43c */
unsigned int vicr; /* 0x440 */
unsigned int spare6[1]; /* 0x444 */
unsigned int inten; /* 0x448 */
unsigned int inteo; /* 0x44c */
unsigned int ints; /* 0x450 */
unsigned int intc; /* 0x454 */
unsigned int intm1; /* 0x458 */
unsigned int intm2; /* 0x45c */
unsigned int spare7[40]; /* 0x460 - 0x4fc */
unsigned int dctl0; /* 0x500 */
unsigned int dsta0; /* 0x504 */
unsigned int dcsau0; /* 0x508 */
unsigned int dcsal0; /* 0x50c */
unsigned int dcdau0; /* 0x510 */
unsigned int dcdal0; /* 0x514 */
unsigned int dclau0; /* 0x518 */
unsigned int dclal0; /* 0x51c */
unsigned int dsau0; /* 0x520 */
unsigned int dsal0; /* 0x524 */
unsigned int ddau0; /* 0x528 */
unsigned int ddal0; /* 0x52c */
unsigned int dsat0; /* 0x530 */
unsigned int ddat0; /* 0x534 */
unsigned int dnlau0; /* 0x538 */
unsigned int dnlal0; /* 0x53c */
unsigned int dcnt0; /* 0x540 */
unsigned int ddbs0; /* 0x544 */
unsigned int r20[14]; /* 0x548 - 0x57c */
unsigned int dctl1; /* 0x580 */
unsigned int dsta1; /* 0x584 */
unsigned int dcsau1; /* 0x588 */
unsigned int dcsal1; /* 0x58c */
unsigned int dcdau1; /* 0x590 */
unsigned int dcdal1; /* 0x594 */
unsigned int dclau1; /* 0x598 */
unsigned int dclal1; /* 0x59c */
unsigned int dsau1; /* 0x5a0 */
unsigned int dsal1; /* 0x5a4 */
unsigned int ddau1; /* 0x5a8 */
unsigned int ddal1; /* 0x5ac */
unsigned int dsat1; /* 0x5b0 */
unsigned int ddat1; /* 0x5b4 */
unsigned int dnlau1; /* 0x5b8 */
unsigned int dnlal1; /* 0x5bc */
unsigned int dcnt1; /* 0x5c0 */
unsigned int ddbs1; /* 0x5c4 */
unsigned int r21[14]; /* 0x5c8 - 0x5fc */
unsigned int devi_veni_2; /* 0x600 */
unsigned int gctrl_ga_revid; /* 0x604 */
unsigned int semaphore0_1_2_3; /* 0x608 */
unsigned int semaphore4_5_6_7; /* 0x60c */
unsigned int mbox0; /* 0x610 */
unsigned int mbox1; /* 0x614 */
unsigned int mbox2; /* 0x618 */
unsigned int mbox3; /* 0x61c */
unsigned int r22[629]; /* 0x620 - 0xff0 */
unsigned int csrbcr; /* 0xff4 */
unsigned int csrbsr; /* 0xff8 */
unsigned int cbar; /* 0xffc */
};
#define IRQ_VOWN 0x0001
#define IRQ_VIRQ1 0x0002
#define IRQ_VIRQ2 0x0004
#define IRQ_VIRQ3 0x0008
#define IRQ_VIRQ4 0x0010
#define IRQ_VIRQ5 0x0020
#define IRQ_VIRQ6 0x0040
#define IRQ_VIRQ7 0x0080
#define IRQ_DMA 0x0100
#define IRQ_LERR 0x0200
#define IRQ_VERR 0x0400
#define IRQ_res 0x0800
#define IRQ_IACK 0x1000
#define IRQ_SWINT 0x2000
#define IRQ_SYSFAIL 0x4000
#define IRQ_ACFAIL 0x8000
struct _TDMA_CMD_PACKET {
unsigned int dctl; /* DMA Control */
unsigned int dtbc; /* Transfer Byte Count */
unsigned int dlv; /* PCI Address */
unsigned int res1; /* Reserved */
unsigned int dva; /* Vme Address */
unsigned int res2; /* Reserved */
unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
unsigned int res3; /* Reserved */
};
#define VME_AM_A16 0x01
#define VME_AM_A24 0x02
#define VME_AM_A32 0x03
#define VME_AM_Axx 0x03
#define VME_AM_USR 0x04
#define VME_AM_SUP 0x08
#define VME_AM_DATA 0x10
#define VME_AM_PROG 0x20
#define VME_AM_Mxx (VME_AM_DATA | VME_AM_PROG)
#define VME_FLAG_D8 0x01
#define VME_FLAG_D16 0x02
#define VME_FLAG_D32 0x03
#define VME_FLAG_Dxx 0x03
#endif
|
1001-study-uboot
|
include/tsi148.h
|
C
|
gpl3
| 10,323
|
#ifndef _LINUX_LMB_H
#define _LINUX_LMB_H
#ifdef __KERNEL__
#include <asm/types.h>
/*
* Logical memory blocks.
*
* Copyright (C) 2001 Peter Bergner, IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#define MAX_LMB_REGIONS 8
struct lmb_property {
phys_addr_t base;
phys_size_t size;
};
struct lmb_region {
unsigned long cnt;
phys_size_t size;
struct lmb_property region[MAX_LMB_REGIONS+1];
};
struct lmb {
struct lmb_region memory;
struct lmb_region reserved;
};
extern struct lmb lmb;
extern void lmb_init(struct lmb *lmb);
extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
phys_addr_t max_addr);
extern phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
phys_addr_t max_addr);
extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern void lmb_dump_all(struct lmb *lmb);
static inline phys_size_t
lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
{
return type->region[region_nr].size;
}
void board_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve(struct lmb *lmb);
#endif /* __KERNEL__ */
#endif /* _LINUX_LMB_H */
|
1001-study-uboot
|
include/lmb.h
|
C
|
gpl3
| 1,669
|
/*
* (C) Copyright 2000, 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mpc8260.h
*
* MPC8255 / MPC8260 specific definitions
*/
#ifndef __MPC8260_H__
#define __MPC8260_H__
#ifdef CONFIG_MPC8255
#define CPU_ID_STR "MPC8255"
#endif
#ifndef CPU_ID_STR
#if defined(CONFIG_MPC8272_FAMILY)
#ifdef CONFIG_MPC8247
#define CPU_ID_STR "MPC8247"
#elif defined CONFIG_MPC8248
#define CPU_ID_STR "MPC8248"
#elif defined CONFIG_MPC8271
#define CPU_ID_STR "MPC8271"
#else
#define CPU_ID_STR "MPC8272"
#endif
#else
#define CPU_ID_STR "MPC8260"
#endif
#endif /* !CPU_ID_STR */
/*-----------------------------------------------------------------------
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* BCR - Bus Configuration Register 4-25
*/
#define BCR_EBM 0x80000000 /* External Bus Mode */
#define BCR_APD_MSK 0x70000000 /* Address Phase Delay Mask */
#define BCR_L2C 0x08000000 /* Secondary Cache Controller */
#define BCR_L2D_MSK 0x07000000 /* L2 Cache Hit Delay Mask */
#define BCR_PLDP 0x00800000 /* Pipeline Maximum Depth */
#define BCR_EAV 0x00400000 /* Enable Address Visibility */
#define BCR_ETM 0x00080000 /* Compatibility Mode Enable */
#define BCR_LETM 0x00040000 /* LocalBus Compatibility Mode Enable*/
#define BCR_EPAR 0x00020000 /* Even Parity */
#define BCR_LEPAR 0x00010000 /* Local Bus Even Parity */
#define BCR_NPQM0 0x00008000 /* Non PowerQUICC-II Master 0 */
#define BCR_NPQM1 0x00004000 /* Non PowerQUICC-II Master 1 */
#define BCR_NPQM2 0x00002000 /* Non PowerQUICC-II Master 2 */
#define BCR_EXDD 0x00000400 /* External Master Delay Disable*/
#define BCR_ISPS 0x00000010 /* Internal Space Port Size */
/*-----------------------------------------------------------------------
* PPC_ACR - 60x Bus Arbiter Configuration Register 4-28
*/
#define PPC_ACR_DBGD 0x20 /* Data Bus Grant Delay */
#define PPC_ACR_EARB 0x10 /* External Arbitration */
#define PPC_ACR_PRKM_MSK 0x0f /* Parking Master */
#define PPC_ACR_PRKM_CPMH 0x00 /* CPM high request level */
#define PPC_ACR_PRKM_CPMM 0x01 /* CPM middle request level */
#define PPC_ACR_PRKM_CPML 0x02 /* CPM low request level */
#define PPC_ACR_PRKM_CORE 0x06 /* Internal Core */
#define PPC_ACR_PRKM_EXT1 0x07 /* External Master 1 */
#define PPC_ACR_PRKM_EXT2 0x08 /* External Master 2 */
#define PPC_ACR_PRKM_EXT3 0x09 /* External Master 3 */
/*-----------------------------------------------------------------------
* PPC_ALRH/PPC_ALRL - 60x Bus Arbitration-Level Registers 4-28
*/
#define PPC_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */
#define PPC_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */
#define PPC_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */
#define PPC_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */
#define PPC_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */
#define PPC_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */
#define PPC_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */
#define PPC_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */
#define PPC_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */
#define PPC_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */
#define PPC_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */
#define PPC_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */
#define PPC_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */
#define PPC_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */
#define PPC_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */
#define PPC_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */
/*-----------------------------------------------------------------------
* LCL_ACR - Local Bus Arbiter Configuration Register 4-29
*/
#define LCL_ACR_DBGD 0x20 /* Data Bus Grant Delay */
#define LCL_ACR_PRKM_MSK 0x0f /* Parking Master */
#define LCL_ACR_PRKM_CPMH 0x00 /* CPM high request level */
#define LCL_ACR_PRKM_CPMM 0x01 /* CPM middle request level */
#define LCL_ACR_PRKM_CPML 0x02 /* CPM low request level */
#define LCL_ACR_PRKM_HOST 0x03 /* Host Bridge */
/*-----------------------------------------------------------------------
* LCL_ALRH/LCL_ALRL - Local Bus Arbitration Level Registers 4-30
*/
#define LCL_ALRH_PF0_MSK 0xf0000000 /* Priority Field 0 Mask */
#define LCL_ALRH_PF1_MSK 0x0f000000 /* Priority Field 1 Mask */
#define LCL_ALRH_PF2_MSK 0x00f00000 /* Priority Field 2 Mask */
#define LCL_ALRH_PF3_MSK 0x000f0000 /* Priority Field 3 Mask */
#define LCL_ALRH_PF4_MSK 0x0000f000 /* Priority Field 4 Mask */
#define LCL_ALRH_PF5_MSK 0x00000f00 /* Priority Field 5 Mask */
#define LCL_ALRH_PF6_MSK 0x000000f0 /* Priority Field 6 Mask */
#define LCL_ALRH_PF7_MSK 0x0000000f /* Priority Field 7 Mask */
#define LCL_ALRL_PF8_MSK 0xf0000000 /* Priority Field 8 Mask */
#define LCL_ALRL_PF9_MSK 0x0f000000 /* Priority Field 9 Mask */
#define LCL_ALRL_PF10_MSK 0x00f00000 /* Priority Field 10 Mask */
#define LCL_ALRL_PF11_MSK 0x000f0000 /* Priority Field 11 Mask */
#define LCL_ALRL_PF12_MSK 0x0000f000 /* Priority Field 12 Mask */
#define LCL_ALRL_PF13_MSK 0x00000f00 /* Priority Field 13 Mask */
#define LCL_ALRL_PF14_MSK 0x000000f0 /* Priority Field 14 Mask */
#define LCL_ALRL_PF15_MSK 0x0000000f /* Priority Field 15 Mask */
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration Register 4-31
*/
#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
#define SIUMCR_CDIS 0x10000000 /* Core Disable */
#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
#define SIUMCR_DPPC01 0x04000000 /* - " - */
#define SIUMCR_DPPC10 0x08000000 /* - " - */
#define SIUMCR_DPPC11 0x0c000000 /* - " - */
#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
#define SIUMCR_L2CPC01 0x01000000 /* - " - */
#define SIUMCR_L2CPC10 0x02000000 /* - " - */
#define SIUMCR_L2CPC11 0x03000000 /* - " - */
#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
#define SIUMCR_LBPC01 0x00400000 /* - " - */
#define SIUMCR_LBPC10 0x00800000 /* - " - */
#define SIUMCR_LBPC11 0x00c00000 /* - " - */
#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
#define SIUMCR_APPC01 0x00100000 /* - " - */
#define SIUMCR_APPC10 0x00200000 /* - " - */
#define SIUMCR_APPC11 0x00300000 /* - " - */
#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
#define SIUMCR_CS10PC01 0x00040000 /* - " - */
#define SIUMCR_CS10PC10 0x00080000 /* - " - */
#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
#define SIUMCR_BCTLC01 0x00010000 /* - " - */
#define SIUMCR_BCTLC10 0x00020000 /* - " - */
#define SIUMCR_BCTLC11 0x00030000 /* - " - */
#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
#define SIUMCR_MMR01 0x00004000 /* - " - */
#define SIUMCR_MMR10 0x00008000 /* - " - */
#define SIUMCR_MMR11 0x0000c000 /* - " - */
#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
#define SIUMCR_ABE 0x00000400 /* Address output buffer impedance*/
/*-----------------------------------------------------------------------
* IMMR - Internal Memory Map Register 4-34
*/
#define IMMR_ISB_MSK 0xfffe0000 /* Internal Space base */
#define IMMR_PARTNUM_MSK 0x0000ff00 /* Part number */
#define IMMR_MASKNUM_MSK 0x000000ff /* Mask number */
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control Register 4-35
*/
#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count*/
#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
#define SYPCR_PBME 0x00000080 /* 60x Bus Monitor Enable */
#define SYPCR_LBME 0x00000040 /* Local Bus Monitor Enable */
#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select*/
#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
/*-----------------------------------------------------------------------
* TMCNTSC - Time Counter Status and Control Register 4-40
*/
#define TMCNTSC_SEC 0x0080 /* Once Per Second Interrupt */
#define TMCNTSC_ALR 0x0040 /* Alarm Interrupt */
#define TMCNTSC_SIE 0x0008 /* Second Interrupt Enable */
#define TMCNTSC_ALE 0x0004 /* Alarm Interrupt Enable */
#define TMCNTSC_TCF 0x0002 /* Time Counter Frequency */
#define TMCNTSC_TCE 0x0001 /* Time Counter Enable */
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control Register 4-42
*/
#if 0 /* already defined in asm/immap_8260.h */
#define PISCR_PS 0x0080 /* Periodic Interrupt Status */
#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
#define PISCR_PTF 0x0002 /* Periodic Timer Frequency */
#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
#endif
/*-----------------------------------------------------------------------
* RSR - Reset Status Register 5-4
*/
#define RSR_JTRS 0x00000020 /* JTAG Reset Status */
#define RSR_CSRS 0x00000010 /* Check Stop Reset Status */
#define RSR_SWRS 0x00000008 /* Software Watchdog Reset Status*/
#define RSR_BMRS 0x00000004 /* Bus Monitor Reset Status */
#define RSR_ESRS 0x00000002 /* External Soft Reset Status */
#define RSR_EHRS 0x00000001 /* External Hard Reset Status */
#define RSR_ALLBITS (RSR_JTRS|RSR_CSRS|RSR_SWRS|RSR_BMRS|RSR_ESRS|RSR_EHRS)
/*-----------------------------------------------------------------------
* RMR - Reset Mode Register 5-5
*/
#define RMR_CSRE 0x00000001 /* Checkstop Reset Enable */
/*-----------------------------------------------------------------------
* Hard Reset Configuration Word 5-8
*/
#define HRCW_EARB 0x80000000 /* External Arbitration */
#define HRCW_EXMC 0x40000000 /* External Memory Controller */
#define HRCW_CDIS 0x20000000 /* Core Disable */
#define HRCW_EBM 0x10000000 /* External Bus Mode */
#define HRCW_BPS00 0x00000000 /* Boot Port Size */
#define HRCW_BPS01 0x04000000 /* - " - */
#define HRCW_BPS10 0x08000000 /* - " - */
#define HRCW_BPS11 0x0c000000 /* - " - */
#define HRCW_CIP 0x02000000 /* Core Initial Prefix */
#define HRCW_ISPS 0x01000000 /* Internal Space Port Size */
#define HRCW_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
#define HRCW_L2CPC01 0x00400000 /* - " - */
#define HRCW_L2CPC10 0x00800000 /* - " - */
#define HRCW_L2CPC11 0x00c00000 /* - " - */
#define HRCW_DPPC00 0x00000000 /* Data Parity Pin Configuration*/
#define HRCW_DPPC01 0x00100000 /* - " - */
#define HRCW_DPPC10 0x00200000 /* - " - */
#define HRCW_DPPC11 0x00300000 /* - " - */
#define HRCW_reserved1 0x00080000 /* reserved */
#define HRCW_ISB000 0x00000000 /* Initial Internal Space Base */
#define HRCW_ISB001 0x00010000 /* - " - */
#define HRCW_ISB010 0x00020000 /* - " - */
#define HRCW_ISB011 0x00030000 /* - " - */
#define HRCW_ISB100 0x00040000 /* - " - */
#define HRCW_ISB101 0x00050000 /* - " - */
#define HRCW_ISB110 0x00060000 /* - " - */
#define HRCW_ISB111 0x00070000 /* - " - */
#define HRCW_BMS 0x00008000 /* Boot Memory Space */
#define HRCW_BBD 0x00004000 /* Bus Busy Disable */
#define HRCW_MMR00 0x00000000 /* Mask Masters Requests */
#define HRCW_MMR01 0x00001000 /* - " - */
#define HRCW_MMR10 0x00002000 /* - " - */
#define HRCW_MMR11 0x00003000 /* - " - */
#define HRCW_LBPC00 0x00000000 /* Local Bus Pin Configuration */
#define HRCW_LBPC01 0x00000400 /* - " - */
#define HRCW_LBPC10 0x00000800 /* - " - */
#define HRCW_LBPC11 0x00000c00 /* - " - */
#define HRCW_APPC00 0x00000000 /* Address Parity Pin Configuration*/
#define HRCW_APPC01 0x00000100 /* - " - */
#define HRCW_APPC10 0x00000200 /* - " - */
#define HRCW_APPC11 0x00000300 /* - " - */
#define HRCW_CS10PC00 0x00000000 /* CS10 Pin Configuration */
#define HRCW_CS10PC01 0x00000040 /* - " - */
#define HRCW_CS10PC10 0x00000080 /* - " - */
#define HRCW_CS10PC11 0x000000c0 /* - " - */
#define HRCW_MODCK_H0000 0x00000000 /* High-order bits of MODCK Bus */
#define HRCW_MODCK_H0001 0x00000001 /* - " - */
#define HRCW_MODCK_H0010 0x00000002 /* - " - */
#define HRCW_MODCK_H0011 0x00000003 /* - " - */
#define HRCW_MODCK_H0100 0x00000004 /* - " - */
#define HRCW_MODCK_H0101 0x00000005 /* - " - */
#define HRCW_MODCK_H0110 0x00000006 /* - " - */
#define HRCW_MODCK_H0111 0x00000007 /* - " - */
#define HRCW_MODCK_H1000 0x00000008 /* - " - */
#define HRCW_MODCK_H1001 0x00000009 /* - " - */
#define HRCW_MODCK_H1010 0x0000000a /* - " - */
#define HRCW_MODCK_H1011 0x0000000b /* - " - */
#define HRCW_MODCK_H1100 0x0000000c /* - " - */
#define HRCW_MODCK_H1101 0x0000000d /* - " - */
#define HRCW_MODCK_H1110 0x0000000e /* - " - */
#define HRCW_MODCK_H1111 0x0000000f /* - " - */
/*-----------------------------------------------------------------------
* SCCR - System Clock Control Register 9-8
*/
#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
#define SCCR_PCIDF_SHIFT 3
#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */
#define SCCR_DFBRG_SHIFT 0
#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/
#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 128 */
/*-----------------------------------------------------------------------
* SCMR - System Clock Mode Register 9-9
*/
#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */
#define SCMR_CORECNF_SHIFT 24
#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */
#define SCMR_BUSDF_SHIFT 20
#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */
#define SCMR_CPMDF_SHIFT 16
#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */
#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/
#define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */
#define SCMR_PLLMF_SHIFT 0
/*-----------------------------------------------------------------------
* MxMR - Machine A/B/C Mode Registers 10-13
*/
#define MxMR_BSEL 0x80000000 /* Bus Select */
#define MxMR_RFEN 0x40000000 /* Refresh Enable */
#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
#define MxMR_OP_WARR 0x10000000 /* Write to Array */
#define MxMR_OP_RARR 0x20000000 /* Read from Array */
#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
#define MxMR_AMx_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
#define MxMR_AMx_TYPE_1 0x01000000 /* Addess Multiplexing Type 1 */
#define MxMR_AMx_TYPE_2 0x02000000 /* Addess Multiplexing Type 2 */
#define MxMR_AMx_TYPE_3 0x03000000 /* Addess Multiplexing Type 3 */
#define MxMR_AMx_TYPE_4 0x04000000 /* Addess Multiplexing Type 4 */
#define MxMR_AMx_TYPE_5 0x05000000 /* Addess Multiplexing Type 5 */
#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
#define MxMR_G0CLx_A12 0x00000000 /* General Line 0 : A12 */
#define MxMR_G0CLx_A11 0x00080000 /* General Line 0 : A11 */
#define MxMR_G0CLx_A10 0x00100000 /* General Line 0 : A10 */
#define MxMR_G0CLx_A9 0x00180000 /* General Line 0 : A9 */
#define MxMR_G0CLx_A8 0x00200000 /* General Line 0 : A8 */
#define MxMR_G0CLx_A7 0x00280000 /* General Line 0 : A7 */
#define MxMR_G0CLx_A6 0x00300000 /* General Line 0 : A6 */
#define MxMR_G0CLx_A5 0x00380000 /* General Line 0 : A5 */
#define MxMR_RLFx_1X 0x00004000 /* Read Loop is executed 1 time */
#define MxMR_RLFx_2X 0x00008000 /* Read Loop is executed 2 times*/
#define MxMR_RLFx_3X 0x0000c000 /* Read Loop is executed 3 times*/
#define MxMR_RLFx_4X 0x00010000 /* Read Loop is executed 4 times*/
#define MxMR_RLFx_5X 0x00014000 /* Read Loop is executed 5 times*/
#define MxMR_RLFx_6X 0x00018000 /* Read Loop is executed 6 times*/
#define MxMR_RLFx_7X 0x0001c000 /* Read Loop is executed 7 times*/
#define MxMR_RLFx_8X 0x00020000 /* Read Loop is executed 8 times*/
#define MxMR_RLFx_9X 0x00024000 /* Read Loop is executed 9 times*/
#define MxMR_RLFx_10X 0x00028000 /* Read Loop is executed 10 times*/
#define MxMR_RLFx_11X 0x0002c000 /* Read Loop is executed 11 times*/
#define MxMR_RLFx_12X 0x00030000 /* Read Loop is executed 12 times*/
#define MxMR_RLFx_13X 0x00034000 /* Read Loop is executed 13 times*/
#define MxMR_RLFx_14X 0x00038000 /* Read Loop is executed 14 times*/
#define MxMR_RLFx_15X 0x0003c000 /* Read Loop is executed 15 times*/
#define MxMR_RLFx_16X 0x00000000 /* Read Loop is executed 16 times*/
#define MxMR_WLFx_1X 0x00000400 /* Write Loop is executed 1 time*/
#define MxMR_WLFx_2X 0x00000800 /* Write Loop is executed 2 times*/
#define MxMR_WLFx_3X 0x00000c00 /* Write Loop is executed 3 times*/
#define MxMR_WLFx_4X 0x00001000 /* Write Loop is executed 4 times*/
#define MxMR_WLFx_5X 0x00001400 /* Write Loop is executed 5 times*/
#define MxMR_WLFx_6X 0x00001800 /* Write Loop is executed 6 times*/
#define MxMR_WLFx_7X 0x00001c00 /* Write Loop is executed 7 times*/
#define MxMR_WLFx_8X 0x00002000 /* Write Loop is executed 8 times*/
#define MxMR_WLFx_9X 0x00002400 /* Write Loop is executed 9 times*/
#define MxMR_WLFx_10X 0x00002800 /* Write Loop is executed 10 times*/
#define MxMR_WLFx_11X 0x00002c00 /* Write Loop is executed 11 times*/
#define MxMR_WLFx_12X 0x00003000 /* Write Loop is executed 12 times*/
#define MxMR_WLFx_13X 0x00003400 /* Write Loop is executed 13 times*/
#define MxMR_WLFx_14X 0x00003800 /* Write Loop is executed 14 times*/
#define MxMR_WLFx_15X 0x00003c00 /* Write Loop is executed 15 times*/
#define MxMR_WLFx_16X 0x00000000 /* Write Loop is executed 16 times*/
#define MxMR_TLFx_1X 0x00000040 /* Timer Loop is executed 1 time*/
#define MxMR_TLFx_2X 0x00000080 /* Timer Loop is executed 2 times*/
#define MxMR_TLFx_3X 0x000000c0 /* Timer Loop is executed 3 times*/
#define MxMR_TLFx_4X 0x00000100 /* Timer Loop is executed 4 times*/
#define MxMR_TLFx_5X 0x00000140 /* Timer Loop is executed 5 times*/
#define MxMR_TLFx_6X 0x00000180 /* Timer Loop is executed 6 times*/
#define MxMR_TLFx_7X 0x000001c0 /* Timer Loop is executed 7 times*/
#define MxMR_TLFx_8X 0x00000200 /* Timer Loop is executed 8 times*/
#define MxMR_TLFx_9X 0x00000240 /* Timer Loop is executed 9 times*/
#define MxMR_TLFx_10X 0x00000280 /* Timer Loop is executed 10 times*/
#define MxMR_TLFx_11X 0x000002c0 /* Timer Loop is executed 11 times*/
#define MxMR_TLFx_12X 0x00000300 /* Timer Loop is executed 12 times*/
#define MxMR_TLFx_13X 0x00000340 /* Timer Loop is executed 13 times*/
#define MxMR_TLFx_14X 0x00000380 /* Timer Loop is executed 14 times*/
#define MxMR_TLFx_15X 0x000003c0 /* Timer Loop is executed 15 times*/
#define MxMR_TLFx_16X 0x00000000 /* Timer Loop is executed 16 times*/
/*-----------------------------------------------------------------------
* BRx - Memory Controller: Base Register 10-14
*/
#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
#define BRx_PS_MSK 0x00001800 /* Port Size Mask */
#define BRx_DECC_MSK 0x00000600 /* Data Error Correct+Check Mask*/
#define BRx_WP 0x00000100 /* Write Protect */
#define BRx_MS_MSK 0x000000e0 /* Machine Select Mask */
#define BRx_EMEMC 0x00000010 /* External MEMC Enable */
#define BRx_ATOM_MSK 0x0000000c /* Atomic Operation Mask */
#define BRx_DR 0x00000002 /* Data Pipelining */
#define BRx_V 0x00000001 /* Bank Valid */
#define BRx_PS_64 0x00000000 /* 64 bit port size (60x bus only)*/
#define BRx_PS_8 0x00000800 /* 8 bit port size */
#define BRx_PS_16 0x00001000 /* 16 bit port size */
#define BRx_PS_32 0x00001800 /* 32 bit port size */
#define BRx_DECC_NONE 0x00000000 /* Data Errors Checking Disabled*/
#define BRx_DECC_NORMAL 0x00000200 /* Normal Parity Checking */
#define BRx_DECC_RMWPC 0x00000400 /* Read-Modify-Write Parity Checking*/
#define BRx_DECC_ECC 0x00000600 /* ECC Correction and Checking */
#define BRx_MS_GPCM_P 0x00000000 /* G.P.C.M. 60x Bus Machine Select*/
#define BRx_MS_GPCM_L 0x00000020 /* G.P.C.M. Local Bus Machine Select*/
#define BRx_MS_SDRAM_P 0x00000040 /* SDRAM 60x Bus Machine Select */
#define BRx_MS_SDRAM_L 0x00000060 /* SDRAM Local Bus Machine Select*/
#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
#define BRx_ATOM_RAWA 0x00000004 /* Read-After-Write-Atomic */
#define BRx_ATOM_WARA 0x00000008 /* Write-After-Read-Atomic */
/*-----------------------------------------------------------------------
* ORx - Memory Controller: Option Register - SDRAM Mode 10-16
*/
#define ORxS_SDAM_MSK 0xfff00000 /* SDRAM Address Mask Mask */
#define ORxS_LSDAM_MSK 0x000f8000 /* Lower SDRAM Address Mask Mask*/
#define ORxS_BPD_MSK 0x00006000 /* Banks Per Device Mask */
#define ORxS_ROWST_MSK 0x00001e00 /* Row Start Address Bit Mask */
#define ORxS_NUMR_MSK 0x000001c0 /* Number of Row Addr Lines Mask*/
#define ORxS_PMSEL 0x00000020 /* Page Mode Select */
#define ORxS_IBID 0x00000010 /* Internal Bank Interleaving Disable*/
#define ORxS_BPD_2 0x00000000 /* 2 Banks Per Device */
#define ORxS_BPD_4 0x00002000 /* 4 Banks Per Device */
#define ORxS_BPD_8 0x00004000 /* 8 Banks Per Device */
/* ROWST values for xSDMR[PBI] = 0 */
#define ORxS_ROWST_PBI0_A7 0x00000400 /* Row Start Address Bit is A7 */
#define ORxS_ROWST_PBI0_A8 0x00000800 /* Row Start Address Bit is A8 */
#define ORxS_ROWST_PBI0_A9 0x00000c00 /* Row Start Address Bit is A9 */
#define ORxS_ROWST_PBI0_A10 0x00001000 /* Row Start Address Bit is A10 */
#define ORxS_ROWST_PBI0_A11 0x00001400 /* Row Start Address Bit is A11 */
#define ORxS_ROWST_PBI0_A12 0x00001800 /* Row Start Address Bit is A12 */
#define ORxS_ROWST_PBI0_A13 0x00001c00 /* Row Start Address Bit is A13 */
/* ROWST values for xSDMR[PBI] = 1 */
#define ORxS_ROWST_PBI1_A0 0x00000000 /* Row Start Address Bit is A0 */
#define ORxS_ROWST_PBI1_A1 0x00000200 /* Row Start Address Bit is A1 */
#define ORxS_ROWST_PBI1_A2 0x00000400 /* Row Start Address Bit is A2 */
#define ORxS_ROWST_PBI1_A3 0x00000600 /* Row Start Address Bit is A3 */
#define ORxS_ROWST_PBI1_A4 0x00000800 /* Row Start Address Bit is A4 */
#define ORxS_ROWST_PBI1_A5 0x00000a00 /* Row Start Address Bit is A5 */
#define ORxS_ROWST_PBI1_A6 0x00000c00 /* Row Start Address Bit is A6 */
#define ORxS_ROWST_PBI1_A7 0x00000e00 /* Row Start Address Bit is A7 */
#define ORxS_ROWST_PBI1_A8 0x00001000 /* Row Start Address Bit is A8 */
#define ORxS_ROWST_PBI1_A9 0x00001200 /* Row Start Address Bit is A9 */
#define ORxS_ROWST_PBI1_A10 0x00001400 /* Row Start Address Bit is A10 */
#define ORxS_ROWST_PBI1_A11 0x00001600 /* Row Start Address Bit is A11 */
#define ORxS_ROWST_PBI1_A12 0x00001800 /* Row Start Address Bit is A12 */
#define ORxS_NUMR_9 0x00000000 /* 9 Row Address Lines */
#define ORxS_NUMR_10 0x00000040 /* 10 Row Address Lines */
#define ORxS_NUMR_11 0x00000080 /* 11 Row Address Lines */
#define ORxS_NUMR_12 0x000000c0 /* 12 Row Address Lines */
#define ORxS_NUMR_13 0x00000100 /* 13 Row Address Lines */
#define ORxS_NUMR_14 0x00000140 /* 14 Row Address Lines */
#define ORxS_NUMR_15 0x00000180 /* 15 Row Address Lines */
#define ORxS_NUMR_16 0x000001c0 /* 16 Row Address Lines */
/* helper to determine the AM for a given size (SDRAM mode) */
#define ORxS_SIZE_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
/*-----------------------------------------------------------------------
* ORx - Memory Controller: Option Register - GPCM Mode 10-18
*/
#define ORxG_AM_MSK 0xffff8000 /* Address Mask Mask */
#define ORxG_BCTLD 0x00001000 /* Data Buffer Control Disable */
#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
#define ORxG_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask*/
#define ORxG_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */
#define ORxG_SETA 0x00000008 /* External Access Termination */
#define ORxG_TRLX 0x00000004 /* Timing Relaxed */
#define ORxG_EHTR 0x00000002 /* Extended Hold Time on Read */
#define ORxG_ACS_DIV1 0x00000000 /* CS is output at the same time*/
#define ORxG_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later*/
#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
#define ORxG_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
#define ORxG_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
#define ORxG_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
#define ORxG_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
#define ORxG_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
#define ORxG_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
#define ORxG_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
#define ORxG_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
#define ORxG_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
#define ORxG_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
#define ORxG_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
#define ORxG_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
#define ORxG_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
#define ORxG_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
/*-----------------------------------------------------------------------
* ORx - Memory Controller: Option Register - UPM Mode 10-20
*/
#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
#define ORxU_BCTLD 0x00001000 /* Data Buffer Control Disable */
#define ORxU_BI 0x00000100 /* Burst Inhibit */
#define ORxU_EHTR_MSK 0x00000006 /* Extended Hold Time on Read Mask*/
#define ORxU_EHTR_NORM 0x00000000 /* Normal Timing */
#define ORxU_EHTR_1IDLE 0x00000002 /* One Idle Clock Cycle Inserted*/
#define ORxU_EHTR_4IDLE 0x00000004 /* Four Idle Clock Cycles Inserted*/
#define ORxU_EHTR_8IDLE 0x00000006 /* Eight Idle Clock Cycles Inserted*/
/* helpers to convert values into an OR address mask (GPCM mode) */
#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
/*-----------------------------------------------------------------------
* PSDMR - 60x SDRAM Mode Register 10-21
*/
#define PSDMR_PBI 0x80000000 /* Page-based Interleaving */
#define PSDMR_RFEN 0x40000000 /* Refresh Enable */
#define PSDMR_OP_MSK 0x38000000 /* SDRAM Operation Mask */
#define PSDMR_SDAM_MSK 0x07000000 /* SDRAM Address Multiplex Mask */
#define PSDMR_BSMA_MSK 0x00e00000 /* Bank Select Muxd Addr Line Mask*/
#define PSDMR_SDA10_MSK 0x001c0000 /* A10 Control Mask */
#define PSDMR_RFRC_MSK 0x00038000 /* Refresh Recovery Mask */
#define PSDMR_PRETOACT_MSK 0x00007000 /* Precharge to Activate Intvl Mask*/
#define PSDMR_ACTTORW_MSK 0x00000e00 /* Activate to Read/Write Intvl Mask*/
#define PSDMR_BL 0x00000100 /* Burst Length */
#define PSDMR_LDOTOPRE_MSK 0x000000c0 /* Last Data Out to Precharge Mask*/
#define PSDMR_WRC_MSK 0x00000030 /* Write Recovery Time Mask */
#define PSDMR_EAMUX 0x00000008 /* External Address Multiplexing*/
#define PSDMR_BUFCMD 0x00000004 /* SDRAM ctl lines asrtd for 2 cycles*/
#define PSDMR_CL_MSK 0x00000003 /* CAS Latency Mask */
#define PSDMR_OP_NORM 0x00000000 /* Normal Operation */
#define PSDMR_OP_CBRR 0x08000000 /* CBR Refresh */
#define PSDMR_OP_SELFR 0x10000000 /* Self Refresh */
#define PSDMR_OP_MRW 0x18000000 /* Mode Register Write */
#define PSDMR_OP_PREB 0x20000000 /* Precharge Bank */
#define PSDMR_OP_PREA 0x28000000 /* Precharge All Banks */
#define PSDMR_OP_ACTB 0x30000000 /* Activate Bank */
#define PSDMR_OP_RW 0x38000000 /* Read/Write */
#define PSDMR_SDAM_A13_IS_A5 0x00000000 /* SDRAM Address Multiplex A13 is A5 */
#define PSDMR_SDAM_A14_IS_A5 0x01000000 /* SDRAM Address Multiplex A14 is A5 */
#define PSDMR_SDAM_A15_IS_A5 0x02000000 /* SDRAM Address Multiplex A15 is A5 */
#define PSDMR_SDAM_A16_IS_A5 0x03000000 /* SDRAM Address Multiplex A16 is A5 */
#define PSDMR_SDAM_A17_IS_A5 0x04000000 /* SDRAM Address Multiplex A17 is A5 */
#define PSDMR_SDAM_A18_IS_A5 0x05000000 /* SDRAM Address Multiplex A18 is A5 */
#define PSDMR_BSMA_A12_A14 0x00000000 /* A12 - A14 */
#define PSDMR_BSMA_A13_A15 0x00200000 /* A13 - A15 */
#define PSDMR_BSMA_A14_A16 0x00400000 /* A14 - A16 */
#define PSDMR_BSMA_A15_A17 0x00600000 /* A15 - A17 */
#define PSDMR_BSMA_A16_A18 0x00800000 /* A16 - A18 */
#define PSDMR_BSMA_A17_A19 0x00a00000 /* A17 - A19 */
#define PSDMR_BSMA_A18_A20 0x00c00000 /* A18 - A20 */
#define PSDMR_BSMA_A19_A21 0x00e00000 /* A19 - A21 */
/* SDA10 values for xSDMR[PBI] = 0 */
#define PSDMR_SDA10_PBI0_A12 0x00000000 /* "A10" Control is A12 */
#define PSDMR_SDA10_PBI0_A11 0x00040000 /* "A10" Control is A11 */
#define PSDMR_SDA10_PBI0_A10 0x00080000 /* "A10" Control is A10 */
#define PSDMR_SDA10_PBI0_A9 0x000c0000 /* "A10" Control is A9 */
#define PSDMR_SDA10_PBI0_A8 0x00100000 /* "A10" Control is A8 */
#define PSDMR_SDA10_PBI0_A7 0x00140000 /* "A10" Control is A7 */
#define PSDMR_SDA10_PBI0_A6 0x00180000 /* "A10" Control is A6 */
#define PSDMR_SDA10_PBI0_A5 0x001c0000 /* "A10" Control is A5 */
/* SDA10 values for xSDMR[PBI] = 1 */
#define PSDMR_SDA10_PBI1_A10 0x00000000 /* "A10" Control is A10 */
#define PSDMR_SDA10_PBI1_A9 0x00040000 /* "A10" Control is A9 */
#define PSDMR_SDA10_PBI1_A8 0x00080000 /* "A10" Control is A8 */
#define PSDMR_SDA10_PBI1_A7 0x000c0000 /* "A10" Control is A7 */
#define PSDMR_SDA10_PBI1_A6 0x00100000 /* "A10" Control is A6 */
#define PSDMR_SDA10_PBI1_A5 0x00140000 /* "A10" Control is A5 */
#define PSDMR_SDA10_PBI1_A4 0x00180000 /* "A10" Control is A4 */
#define PSDMR_SDA10_PBI1_A3 0x001c0000 /* "A10" Control is A3 */
#define PSDMR_RFRC_3_CLK 0x00008000 /* 3 Clocks */
#define PSDMR_RFRC_4_CLK 0x00010000 /* 4 Clocks */
#define PSDMR_RFRC_5_CLK 0x00018000 /* 5 Clocks */
#define PSDMR_RFRC_6_CLK 0x00020000 /* 6 Clocks */
#define PSDMR_RFRC_7_CLK 0x00028000 /* 7 Clocks */
#define PSDMR_RFRC_8_CLK 0x00030000 /* 8 Clocks */
#define PSDMR_RFRC_16_CLK 0x00038000 /* 16 Clocks */
#define PSDMR_PRETOACT_8W 0x00000000 /* 8 Clock-cycle Wait States */
#define PSDMR_PRETOACT_1W 0x00001000 /* 1 Clock-cycle Wait States */
#define PSDMR_PRETOACT_2W 0x00002000 /* 2 Clock-cycle Wait States */
#define PSDMR_PRETOACT_3W 0x00003000 /* 3 Clock-cycle Wait States */
#define PSDMR_PRETOACT_4W 0x00004000 /* 4 Clock-cycle Wait States */
#define PSDMR_PRETOACT_5W 0x00005000 /* 5 Clock-cycle Wait States */
#define PSDMR_PRETOACT_6W 0x00006000 /* 6 Clock-cycle Wait States */
#define PSDMR_PRETOACT_7W 0x00007000 /* 7 Clock-cycle Wait States */
#define PSDMR_ACTTORW_8W 0x00000000 /* 8 Clock-cycle Wait States */
#define PSDMR_ACTTORW_1W 0x00000200 /* 1 Clock-cycle Wait States */
#define PSDMR_ACTTORW_2W 0x00000400 /* 2 Clock-cycle Wait States */
#define PSDMR_ACTTORW_3W 0x00000600 /* 3 Clock-cycle Wait States */
#define PSDMR_ACTTORW_4W 0x00000800 /* 4 Clock-cycle Wait States */
#define PSDMR_ACTTORW_5W 0x00000a00 /* 5 Clock-cycle Wait States */
#define PSDMR_ACTTORW_6W 0x00000c00 /* 6 Clock-cycle Wait States */
#define PSDMR_ACTTORW_7W 0x00000e00 /* 7 Clock-cycle Wait States */
#define PSDMR_LDOTOPRE_0C 0x00000000 /* 0 Clock Cycles */
#define PSDMR_LDOTOPRE_1C 0x00000040 /* 1 Clock Cycles */
#define PSDMR_LDOTOPRE_2C 0x00000080 /* 2 Clock Cycles */
#define PSDMR_WRC_4C 0x00000000 /* 4 Clock Cycles */
#define PSDMR_WRC_1C 0x00000010 /* 1 Clock Cycles */
#define PSDMR_WRC_2C 0x00000020 /* 2 Clock Cycles */
#define PSDMR_WRC_3C 0x00000030 /* 3 Clock Cycles */
#define PSDMR_CL_1 0x00000001 /* CAS Latency = 1 */
#define PSDMR_CL_2 0x00000002 /* CAS Latency = 2 */
#define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */
/*-----------------------------------------------------------------------
* LSDMR - Local Bus SDRAM Mode Register 10-24
*/
/*
* No definitions here - the LSDMR has the same fields as the PSDMR.
*/
/*-----------------------------------------------------------------------
* MPTPR - Memory Refresh Timer Prescaler Register 10-32
* See User's Manual Errata for the changed definition (matches the
* 8xx now). The wrong prescaler definition causes excessive refreshes
* (typically "divide by 2" when "divide by 32" is intended) which will
* cause unnecessary memory subsystem slowdown.
*/
#define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */
#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */
#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */
#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */
#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */
#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */
#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */
/*-----------------------------------------------------------------------
* TGCR1/TGCR2 - Timer Global Configuration Registers 17-4
*/
#define TGCR1_CAS2 0x80 /* Cascade Timer 1 and 2 */
#define TGCR1_STP2 0x20 /* Stop timer 2 */
#define TGCR1_RST2 0x10 /* Reset timer 2 */
#define TGCR1_GM1 0x08 /* Gate Mode for Pin 1 */
#define TGCR1_STP1 0x02 /* Stop timer 1 */
#define TGCR1_RST1 0x01 /* Reset timer 1 */
#define TGCR2_CAS4 0x80 /* Cascade Timer 3 and 4 */
#define TGCR2_STP4 0x20 /* Stop timer 4 */
#define TGCR2_RST4 0x10 /* Reset timer 4 */
#define TGCR2_GM2 0x08 /* Gate Mode for Pin 2 */
#define TGCR2_STP3 0x02 /* Stop timer 3 */
#define TGCR2_RST3 0x01 /* Reset timer 3 */
/*-----------------------------------------------------------------------
* TMR1-TMR4 - Timer Mode Registers 17-6
*/
#define TMRx_PS_MSK 0xff00 /* Prescaler Value */
#define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/
#define TMRx_OM 0x0020 /* Output Mode */
#define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/
#define TMRx_FRR 0x0008 /* Free Run/Restart */
#define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
#define TMRx_GE 0x0001 /* Gate Enable */
#define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/
#define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
#define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */
#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
#define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/
#define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/
#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */
/*-----------------------------------------------------------------------
* CMXFCR - CMX FCC Clock Route Register 15-12
*/
#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
/*-----------------------------------------------------------------------
* CMXSCR - CMX SCC Clock Route Register 15-14
*/
#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
/*-----------------------------------------------------------------------
* CMXSMR - CMX SMC Clock Route Register 15-17
*/
#define CMXSMR_SMC1 0x80 /* SMC1 Connection */
#define CMXSMR_SMC1CS_MSK 0x30 /* SMC1 Clock Source */
#define CMXSMR_SMC2 0x08 /* SMC2 Connection */
#define CMXSMR_SMC2CS_MSK 0x03 /* SMC2 Clock Source */
#define CMXSMR_SMC1CS_BRG1 0x00 /* SMC1 Tx and Rx Clocks are BRG1 */
#define CMXSMR_SMC1CS_BRG7 0x10 /* SMC1 Tx and Rx Clocks are BRG7 */
#define CMXSMR_SMC1CS_CLK7 0x20 /* SMC1 Tx and Rx Clocks are CLK7 */
#define CMXSMR_SMC1CS_CLK9 0x30 /* SMC1 Tx and Rx Clocks are CLK9 */
#define CMXSMR_SMC2CS_BRG2 0x00 /* SMC2 Tx and Rx Clocks are BRG2 */
#define CMXSMR_SMC2CS_BRG8 0x01 /* SMC2 Tx and Rx Clocks are BRG8 */
#define CMXSMR_SMC2CS_CLK19 0x02 /* SMC2 Tx and Rx Clocks are CLK19 */
#define CMXSMR_SMC2CS_CLK20 0x03 /* SMC2 Tx and Rx Clocks are CLK20 */
/*-----------------------------------------------------------------------
* miscellaneous
*/
#define UPMA 1
#define UPMB 2
#define UPMC 3
#if !defined(__ASSEMBLY__) && defined(CONFIG_WATCHDOG)
extern __inline__ void
reset_8260_watchdog(volatile immap_t *immr)
{
immr->im_siu_conf.sc_swsr = 0x556c;
immr->im_siu_conf.sc_swsr = 0xaa39;
}
#endif /* !__ASSEMBLY && CONFIG_WATCHDOG */
#endif /* __MPC8260_H__ */
|
1001-study-uboot
|
include/mpc8260.h
|
C
|
gpl3
| 48,610
|
/*
* Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu>
*
* SJA1000 register layout for basic CAN mode
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SJA1000_H_
#define _SJA1000_H_
/*
* SJA1000 register layout in basic can mode
*/
struct sja1000_basic_s {
u8 cr;
u8 cmr;
u8 sr;
u8 ir;
u8 ac;
u8 am;
u8 btr0;
u8 btr1;
u8 oc;
u8 txb[10];
u8 rxb[10];
u8 unused;
u8 cdr;
};
/* control register */
#define CR_RR 0x01
/* output control register */
#define OC_MODE0 0x01
#define OC_MODE1 0x02
#define OC_POL0 0x04
#define OC_TN0 0x08
#define OC_TP0 0x10
#define OC_POL1 0x20
#define OC_TN1 0x40
#define OC_TP1 0x80
#endif
|
1001-study-uboot
|
include/sja1000.h
|
C
|
gpl3
| 1,410
|
/*
* FILE SA-1100.h
*
* Version 1.2
* Author Copyright (c) Marc A. Viredaz, 1998
* DEC Western Research Laboratory, Palo Alto, CA
* Date January 1998 (April 1997)
* System StrongARM SA-1100
* Language C or ARM Assembly
* Purpose Definition of constants related to the StrongARM
* SA-1100 microprocessor (Advanced RISC Machine (ARM)
* architecture version 4). This file is based on the
* StrongARM SA-1100 data sheet version 2.2.
*
* Language-specific definitions are selected by the
* macro "LANGUAGE", which should be defined as either
* "C" (default) or "Assembly".
*/
#ifndef LANGUAGE
# ifdef __ASSEMBLY__
# define LANGUAGE Assembly
# else
# define LANGUAGE C
# endif
#endif
#ifndef io_p2v
#define io_p2v(PhAdd) (PhAdd)
#endif
#include <asm/arch-sa1100/bitfield.h>
#define C 0
#define Assembly 1
#if LANGUAGE == C
typedef unsigned short Word16 ;
typedef unsigned int Word32 ;
typedef Word32 Word ;
typedef Word Quad [4] ;
typedef void *Address ;
typedef void (*ExcpHndlr) (void) ;
#endif /* LANGUAGE == C */
/*
* Memory
*/
#define MemBnkSp 0x08000000 /* Memory Bank Space [byte] */
#define StMemBnkSp MemBnkSp /* Static Memory Bank Space [byte] */
#define StMemBnk0Sp StMemBnkSp /* Static Memory Bank 0 Space */
/* [byte] */
#define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */
/* [byte] */
#define StMemBnk2Sp StMemBnkSp /* Static Memory Bank 2 Space */
/* [byte] */
#define StMemBnk3Sp StMemBnkSp /* Static Memory Bank 3 Space */
/* [byte] */
#define DRAMBnkSp MemBnkSp /* DRAM Bank Space [byte] */
#define DRAMBnk0Sp DRAMBnkSp /* DRAM Bank 0 Space [byte] */
#define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */
#define DRAMBnk2Sp DRAMBnkSp /* DRAM Bank 2 Space [byte] */
#define DRAMBnk3Sp DRAMBnkSp /* DRAM Bank 3 Space [byte] */
#define ZeroMemSp MemBnkSp /* Zero Memory bank Space [byte] */
#define _StMemBnk(Nb) /* Static Memory Bank [0..3] */ \
(0x00000000 + (Nb)*StMemBnkSp)
#define _StMemBnk0 _StMemBnk (0) /* Static Memory Bank 0 */
#define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */
#define _StMemBnk2 _StMemBnk (2) /* Static Memory Bank 2 */
#define _StMemBnk3 _StMemBnk (3) /* Static Memory Bank 3 */
#if LANGUAGE == C
typedef Quad StMemBnkType [StMemBnkSp/sizeof (Quad)] ;
#define StMemBnk /* Static Memory Bank [0..3] */ \
((StMemBnkType *) io_p2v (_StMemBnk (0)))
#define StMemBnk0 (StMemBnk [0]) /* Static Memory Bank 0 */
#define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */
#define StMemBnk2 (StMemBnk [2]) /* Static Memory Bank 2 */
#define StMemBnk3 (StMemBnk [3]) /* Static Memory Bank 3 */
#endif /* LANGUAGE == C */
#define _DRAMBnk(Nb) /* DRAM Bank [0..3] */ \
(0xC0000000 + (Nb)*DRAMBnkSp)
#define _DRAMBnk0 _DRAMBnk (0) /* DRAM Bank 0 */
#define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */
#define _DRAMBnk2 _DRAMBnk (2) /* DRAM Bank 2 */
#define _DRAMBnk3 _DRAMBnk (3) /* DRAM Bank 3 */
#if LANGUAGE == C
typedef Quad DRAMBnkType [DRAMBnkSp/sizeof (Quad)] ;
#define DRAMBnk /* DRAM Bank [0..3] */ \
((DRAMBnkType *) io_p2v (_DRAMBnk (0)))
#define DRAMBnk0 (DRAMBnk [0]) /* DRAM Bank 0 */
#define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */
#define DRAMBnk2 (DRAMBnk [2]) /* DRAM Bank 2 */
#define DRAMBnk3 (DRAMBnk [3]) /* DRAM Bank 3 */
#endif /* LANGUAGE == C */
#define _ZeroMem 0xE0000000 /* Zero Memory bank */
#if LANGUAGE == C
typedef Quad ZeroMemType [ZeroMemSp/sizeof (Quad)] ;
#define ZeroMem /* Zero Memory bank */ \
(*((ZeroMemType *) io_p2v (_ZeroMem)))
#endif /* LANGUAGE == C */
/*
* Personal Computer Memory Card International Association (PCMCIA) sockets
*/
#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
(0x20000000 + (Nb)*PCMCIASp)
#define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
(_PCMCIA (Nb) + 2*PCMCIAPrtSp)
#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
(_PCMCIA (Nb) + 3*PCMCIAPrtSp)
#define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
#define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
#define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
#define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
#define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
#define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
#define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
#define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
#if LANGUAGE == C
typedef Quad PCMCIAPrtType [PCMCIAPrtSp/sizeof (Quad)] ;
typedef PCMCIAPrtType PCMCIAType [PCMCIASp/PCMCIAPrtSp] ;
#define PCMCIA0 /* PCMCIA 0 */ \
(*((PCMCIAType *) io_p2v (_PCMCIA0)))
#define PCMCIA0IO /* PCMCIA 0 I/O */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA0IO)))
#define PCMCIA0Attr /* PCMCIA 0 Attribute */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Attr)))
#define PCMCIA0Mem /* PCMCIA 0 Memory */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA0Mem)))
#define PCMCIA1 /* PCMCIA 1 */ \
(*((PCMCIAType *) io_p2v (_PCMCIA1)))
#define PCMCIA1IO /* PCMCIA 1 I/O */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA1IO)))
#define PCMCIA1Attr /* PCMCIA 1 Attribute */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Attr)))
#define PCMCIA1Mem /* PCMCIA 1 Memory */ \
(*((PCMCIAPrtType *) io_p2v (_PCMCIA1Mem)))
#endif /* LANGUAGE == C */
/*
* Universal Serial Bus (USB) Device Controller (UDC) control registers
*
* Registers
* Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Control Register (read/write).
* Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Address Register (read/write).
* Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Output Maximum Packet size register
* (read/write).
* Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Input Maximum Packet size register
* (read/write).
* Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Control/Status register end-point 0
* (read/write).
* Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Control/Status register end-point 1
* (output, read/write).
* Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Control/Status register end-point 2
* (input, read/write).
* Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Data register end-point 0
* (read/write).
* Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Write Count register end-point 0
* (read).
* Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Data Register (read/write).
* Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
* Controller (UDC) Status Register (read/write).
*/
#define _Ser0UDCCR 0x80000000 /* Ser. port 0 UDC Control Reg. */
#define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */
#define _Ser0UDCOMP 0x80000008 /* Ser. port 0 UDC Output Maximum */
/* Packet size reg. */
#define _Ser0UDCIMP 0x8000000C /* Ser. port 0 UDC Input Maximum */
/* Packet size reg. */
#define _Ser0UDCCS0 0x80000010 /* Ser. port 0 UDC Control/Status */
/* reg. end-point 0 */
#define _Ser0UDCCS1 0x80000014 /* Ser. port 0 UDC Control/Status */
/* reg. end-point 1 (output) */
#define _Ser0UDCCS2 0x80000018 /* Ser. port 0 UDC Control/Status */
/* reg. end-point 2 (input) */
#define _Ser0UDCD0 0x8000001C /* Ser. port 0 UDC Data reg. */
/* end-point 0 */
#define _Ser0UDCWC 0x80000020 /* Ser. port 0 UDC Write Count */
/* reg. end-point 0 */
#define _Ser0UDCDR 0x80000028 /* Ser. port 0 UDC Data Reg. */
#define _Ser0UDCSR 0x80000030 /* Ser. port 0 UDC Status Reg. */
#if LANGUAGE == C
#define Ser0UDCCR /* Ser. port 0 UDC Control Reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCCR)))
#define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCAR)))
#define Ser0UDCOMP /* Ser. port 0 UDC Output Maximum */ \
/* Packet size reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCOMP)))
#define Ser0UDCIMP /* Ser. port 0 UDC Input Maximum */ \
/* Packet size reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCIMP)))
#define Ser0UDCCS0 /* Ser. port 0 UDC Control/Status */ \
/* reg. end-point 0 */ \
(*((volatile Word *) io_p2v (_Ser0UDCCS0)))
#define Ser0UDCCS1 /* Ser. port 0 UDC Control/Status */ \
/* reg. end-point 1 (output) */ \
(*((volatile Word *) io_p2v (_Ser0UDCCS1)))
#define Ser0UDCCS2 /* Ser. port 0 UDC Control/Status */ \
/* reg. end-point 2 (input) */ \
(*((volatile Word *) io_p2v (_Ser0UDCCS2)))
#define Ser0UDCD0 /* Ser. port 0 UDC Data reg. */ \
/* end-point 0 */ \
(*((volatile Word *) io_p2v (_Ser0UDCD0)))
#define Ser0UDCWC /* Ser. port 0 UDC Write Count */ \
/* reg. end-point 0 */ \
(*((volatile Word *) io_p2v (_Ser0UDCWC)))
#define Ser0UDCDR /* Ser. port 0 UDC Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCDR)))
#define Ser0UDCSR /* Ser. port 0 UDC Status Reg. */ \
(*((volatile Word *) io_p2v (_Ser0UDCSR)))
#endif /* LANGUAGE == C */
#define UDCCR_UDD 0x00000001 /* UDC Disable */
#define UDCCR_UDA 0x00000002 /* UDC Active (read) */
#define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
#define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
/* (disable) */
#define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
/* (disable) */
#define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
/* (disable) */
#define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
/* (disable) */
#define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */
#define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
#define UDCAR_ADD Fld (7, 0) /* function ADDress */
#define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
/* [byte] */
#define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
/* [1..256 byte] */ \
(((Size) - 1) << FShft (UDCOMP_OUTMAXP))
#define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
/* [byte] */
#define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
/* [1..256 byte] */ \
(((Size) - 1) << FShft (UDCIMP_INMAXP))
#define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
#define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
#define UDCCS0_SST 0x00000004 /* Sent STall */
#define UDCCS0_FST 0x00000008 /* Force STall */
#define UDCCS0_DE 0x00000010 /* Data End */
#define UDCCS0_SE 0x00000020 /* Setup End (read) */
#define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
/* (write) */
#define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
#define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
/* Service request (read) */
#define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
#define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
#define UDCCS1_SST 0x00000008 /* Sent STall */
#define UDCCS1_FST 0x00000010 /* Force STall */
#define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
#define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
/* Service request (read) */
#define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
#define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
#define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
#define UDCCS2_SST 0x00000010 /* Sent STall */
#define UDCCS2_FST 0x00000020 /* Force STall */
#define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
#define UDCWC_WC Fld (4, 0) /* Write Count */
#define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
#define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
#define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
#define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
#define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
#define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
#define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
/*
* Universal Asynchronous Receiver/Transmitter (UART) control registers
*
* Registers
* Ser1UTCR0 Serial port 1 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 0
* (read/write).
* Ser1UTCR1 Serial port 1 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 1
* (read/write).
* Ser1UTCR2 Serial port 1 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 2
* (read/write).
* Ser1UTCR3 Serial port 1 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 3
* (read/write).
* Ser1UTDR Serial port 1 Universal Asynchronous
* Receiver/Transmitter (UART) Data Register
* (read/write).
* Ser1UTSR0 Serial port 1 Universal Asynchronous
* Receiver/Transmitter (UART) Status Register 0
* (read/write).
* Ser1UTSR1 Serial port 1 Universal Asynchronous
* Receiver/Transmitter (UART) Status Register 1 (read).
*
* Ser2UTCR0 Serial port 2 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 0
* (read/write).
* Ser2UTCR1 Serial port 2 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 1
* (read/write).
* Ser2UTCR2 Serial port 2 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 2
* (read/write).
* Ser2UTCR3 Serial port 2 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 3
* (read/write).
* Ser2UTCR4 Serial port 2 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 4
* (read/write).
* Ser2UTDR Serial port 2 Universal Asynchronous
* Receiver/Transmitter (UART) Data Register
* (read/write).
* Ser2UTSR0 Serial port 2 Universal Asynchronous
* Receiver/Transmitter (UART) Status Register 0
* (read/write).
* Ser2UTSR1 Serial port 2 Universal Asynchronous
* Receiver/Transmitter (UART) Status Register 1 (read).
*
* Ser3UTCR0 Serial port 3 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 0
* (read/write).
* Ser3UTCR1 Serial port 3 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 1
* (read/write).
* Ser3UTCR2 Serial port 3 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 2
* (read/write).
* Ser3UTCR3 Serial port 3 Universal Asynchronous
* Receiver/Transmitter (UART) Control Register 3
* (read/write).
* Ser3UTDR Serial port 3 Universal Asynchronous
* Receiver/Transmitter (UART) Data Register
* (read/write).
* Ser3UTSR0 Serial port 3 Universal Asynchronous
* Receiver/Transmitter (UART) Status Register 0
* (read/write).
* Ser3UTSR1 Serial port 3 Universal Asynchronous
* Receiver/Transmitter (UART) Status Register 1 (read).
*
* Clocks
* fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
* or 3.5795 MHz).
* fua, Tua Frequency, period of the UART communication.
*/
#define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \
(0x80010000 + ((Nb) - 1)*0x00020000)
#define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \
(0x80010004 + ((Nb) - 1)*0x00020000)
#define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \
(0x80010008 + ((Nb) - 1)*0x00020000)
#define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \
(0x8001000C + ((Nb) - 1)*0x00020000)
#define _UTCR4(Nb) /* UART Control Reg. 4 [2] */ \
(0x80010010 + ((Nb) - 1)*0x00020000)
#define _UTDR(Nb) /* UART Data Reg. [1..3] */ \
(0x80010014 + ((Nb) - 1)*0x00020000)
#define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \
(0x8001001C + ((Nb) - 1)*0x00020000)
#define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \
(0x80010020 + ((Nb) - 1)*0x00020000)
#define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
#define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
#define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
#define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
#define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
#define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
#define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
#define _Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
#define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
#define _Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
#define _Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
#define _Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
#define _Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
#define _Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
#define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
#define _Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
#define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
#define _Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
#define _Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
#define _Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
#define _Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
#define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
#if LANGUAGE == C
#define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser1UTCR0)))
#define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser1UTCR1)))
#define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser1UTCR2)))
#define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_Ser1UTCR3)))
#define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser1UTDR)))
#define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser1UTSR0)))
#define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser1UTSR1)))
#define Ser2UTCR0 /* Ser. port 2 UART Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR0)))
#define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR1)))
#define Ser2UTCR2 /* Ser. port 2 UART Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR2)))
#define Ser2UTCR3 /* Ser. port 2 UART Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR3)))
#define Ser2UTCR4 /* Ser. port 2 UART Control Reg. 4 */ \
(*((volatile Word *) io_p2v (_Ser2UTCR4)))
#define Ser2UTDR /* Ser. port 2 UART Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser2UTDR)))
#define Ser2UTSR0 /* Ser. port 2 UART Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser2UTSR0)))
#define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser2UTSR1)))
#define Ser3UTCR0 /* Ser. port 3 UART Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser3UTCR0)))
#define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser3UTCR1)))
#define Ser3UTCR2 /* Ser. port 3 UART Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser3UTCR2)))
#define Ser3UTCR3 /* Ser. port 3 UART Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_Ser3UTCR3)))
#define Ser3UTDR /* Ser. port 3 UART Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser3UTDR)))
#define Ser3UTSR0 /* Ser. port 3 UART Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser3UTSR0)))
#define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser3UTSR1)))
#elif LANGUAGE == Assembly
#define Ser1UTCR0 ( io_p2v (_Ser1UTCR0))
#define Ser1UTCR1 ( io_p2v (_Ser1UTCR1))
#define Ser1UTCR2 ( io_p2v (_Ser1UTCR2))
#define Ser1UTCR3 ( io_p2v (_Ser1UTCR3))
#define Ser1UTDR ( io_p2v (_Ser1UTDR))
#define Ser1UTSR0 ( io_p2v (_Ser1UTSR0))
#define Ser1UTSR1 ( io_p2v (_Ser1UTSR1))
#define Ser2UTCR0 ( io_p2v (_Ser2UTCR0))
#define Ser2UTCR1 ( io_p2v (_Ser2UTCR1))
#define Ser2UTCR2 ( io_p2v (_Ser2UTCR2))
#define Ser2UTCR3 ( io_p2v (_Ser2UTCR3))
#define Ser2UTCR4 ( io_p2v (_Ser2UTCR4))
#define Ser2UTDR ( io_p2v (_Ser2UTDR))
#define Ser2UTSR0 ( io_p2v (_Ser2UTSR0))
#define Ser2UTSR1 ( io_p2v (_Ser2UTSR1))
#define Ser3UTCR0 ( io_p2v (_Ser3UTCR0))
#define Ser3UTCR1 ( io_p2v (_Ser3UTCR1))
#define Ser3UTCR2 ( io_p2v (_Ser3UTCR2))
#define Ser3UTCR3 ( io_p2v (_Ser3UTCR3))
#define Ser3UTDR ( io_p2v (_Ser3UTDR))
#define Ser3UTSR0 ( io_p2v (_Ser3UTSR0))
#define Ser3UTSR1 ( io_p2v (_Ser3UTSR1))
#endif /* LANGUAGE == C */
#define UTCR0_PE 0x00000001 /* Parity Enable */
#define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
#define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
#define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
#define UTCR0_SBS 0x00000004 /* Stop Bit Select */
#define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
#define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
#define UTCR0_DSS 0x00000008 /* Data Size Select */
#define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
#define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
#define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
/* (ser. port 1: GPIO [18], */
/* ser. port 3: GPIO [20]) */
#define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
#define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
#define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
#define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
#define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
#define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
#define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
(UTCR0_1StpBit + UTCR0_8BitData)
#define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
#define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
/* fua = fxtl/(16*(BRD[11:0] + 1)) */
/* Tua = 16*(BRD [11:0] + 1)*Txtl */
#define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
(((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
FShft (UTCR1_BRD))
#define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
(((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
FShft (UTCR2_BRD))
/* fua = fxtl/(16*Floor (Div/16)) */
/* Tua = 16*Floor (Div/16)*Txtl */
#define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
(((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
FShft (UTCR1_BRD))
#define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
(((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
FShft (UTCR2_BRD))
/* fua = fxtl/(16*Ceil (Div/16)) */
/* Tua = 16*Ceil (Div/16)*Txtl */
#define UTCR3_RXE 0x00000001 /* Receive Enable */
#define UTCR3_TXE 0x00000002 /* Transmit Enable */
#define UTCR3_BRK 0x00000004 /* BReaK mode */
#define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
/* more Interrupt Enable */
#define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
/* Interrupt Enable */
#define UTCR3_LBM 0x00000020 /* Look-Back Mode */
#define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
/* TIE, LBM can be set or cleared) */ \
(UTCR3_RXE + UTCR3_TXE)
#define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
/* (HP-SIR) modulation Enable */
#define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
#define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
#define UTCR4_LPM 0x00000002 /* Low-Power Mode */
#define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
#define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
#define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
#if 0 /* Hidden receive FIFO bits */
#define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
#define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
#define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
#endif /* 0 */
#define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
/* Service request (read) */
#define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
/* more Service request (read) */
#define UTSR0_RID 0x00000004 /* Receiver IDle */
#define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
#define UTSR0_REB 0x00000010 /* Receive End of Break */
#define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
#define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
#define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
#define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
#define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
#define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
#define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
/*
* Synchronous Data Link Controller (SDLC) control registers
*
* Registers
* Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
* Control Register 0 (read/write).
* Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
* Control Register 1 (read/write).
* Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
* Control Register 2 (read/write).
* Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
* Control Register 3 (read/write).
* Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
* Control Register 4 (read/write).
* Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
* Data Register (read/write).
* Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
* Status Register 0 (read/write).
* Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
* Status Register 1 (read/write).
*
* Clocks
* fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
* or 3.5795 MHz).
* fsd, Tsd Frequency, period of the SDLC communication.
*/
#define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */
#define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */
#define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */
#define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */
#define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */
#define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */
#define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */
#define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */
#if LANGUAGE == C
#define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR0)))
#define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR1)))
#define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR2)))
#define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR3)))
#define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \
(*((volatile Word *) io_p2v (_Ser1SDCR4)))
#define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser1SDDR)))
#define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser1SDSR0)))
#define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser1SDSR1)))
#endif /* LANGUAGE == C */
#define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
#define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
#define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
#define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
#define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
#define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
#define SDCR0_LBM 0x00000004 /* Look-Back Mode */
#define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
#define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
#define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
#define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
#define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
/* (GPIO [16]) */
#define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
#define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
#define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
#define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
#define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
#define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
#define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
#define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
#define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
/* (GPIO [17]) */
#define SDCR1_TXE 0x00000002 /* Transmit Enable */
#define SDCR1_RXE 0x00000004 /* Receive Enable */
#define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
/* more Interrupt Enable */
#define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
/* Interrupt Enable */
#define SDCR1_AME 0x00000020 /* Address Match Enable */
#define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
#define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
#define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
#define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
#define SDCR2_AMV Fld (8, 0) /* Address Match Value */
#define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
#define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
/* fsd = fxtl/(16*(BRD[11:0] + 1)) */
/* Tsd = 16*(BRD[11:0] + 1)*Txtl */
#define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
(((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
FShft (SDCR3_BRD))
#define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
(((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
FShft (SDCR4_BRD))
/* fsd = fxtl/(16*Floor (Div/16)) */
/* Tsd = 16*Floor (Div/16)*Txtl */
#define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
(((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
FShft (SDCR3_BRD))
#define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
(((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
FShft (SDCR4_BRD))
/* fsd = fxtl/(16*Ceil (Div/16)) */
/* Tsd = 16*Ceil (Div/16)*Txtl */
#define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
#if 0 /* Hidden receive FIFO bits */
#define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
#define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
#define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
#endif /* 0 */
#define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
#define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
#define SDSR0_RAB 0x00000004 /* Receive ABort */
#define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
/* Service request (read) */
#define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
/* more Service request (read) */
#define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
#define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
#define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
#define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
#define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
#define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
#define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
#define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
/*
* High-Speed Serial to Parallel controller (HSSP) control registers
*
* Registers
* Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
* controller (HSSP) Control Register 0 (read/write).
* Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
* controller (HSSP) Control Register 1 (read/write).
* Ser2HSDR Serial port 2 High-Speed Serial to Parallel
* controller (HSSP) Data Register (read/write).
* Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
* controller (HSSP) Status Register 0 (read/write).
* Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
* controller (HSSP) Status Register 1 (read).
* Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
* controller (HSSP) Control Register 2 (read/write).
* [The HSCR2 register is only implemented in
* versions 2.0 (rev. = 8) and higher of the StrongARM
* SA-1100.]
*/
#define _Ser2HSCR0 0x80040060 /* Ser. port 2 HSSP Control Reg. 0 */
#define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */
#define _Ser2HSDR 0x8004006C /* Ser. port 2 HSSP Data Reg. */
#define _Ser2HSSR0 0x80040074 /* Ser. port 2 HSSP Status Reg. 0 */
#define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */
#define _Ser2HSCR2 0x90060028 /* Ser. port 2 HSSP Control Reg. 2 */
#if LANGUAGE == C
#define Ser2HSCR0 /* Ser. port 2 HSSP Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser2HSCR0)))
#define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser2HSCR1)))
#define Ser2HSDR /* Ser. port 2 HSSP Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser2HSDR)))
#define Ser2HSSR0 /* Ser. port 2 HSSP Status Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser2HSSR0)))
#define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser2HSSR1)))
#define Ser2HSCR2 /* Ser. port 2 HSSP Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_Ser2HSCR2)))
#endif /* LANGUAGE == C */
#define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
#define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
#define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
#define HSCR0_LBM 0x00000002 /* Look-Back Mode */
#define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
#define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
#define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
#define HSCR0_TXE 0x00000008 /* Transmit Enable */
#define HSCR0_RXE 0x00000010 /* Receive Enable */
#define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
/* more Interrupt Enable */
#define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
/* Interrupt Enable */
#define HSCR0_AME 0x00000080 /* Address Match Enable */
#define HSCR1_AMV Fld (8, 0) /* Address Match Value */
#define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
#if 0 /* Hidden receive FIFO bits */
#define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
#define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
#define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
#endif /* 0 */
#define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
#define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
#define HSSR0_RAB 0x00000004 /* Receive ABort */
#define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
/* Service request (read) */
#define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
/* more Service request (read) */
#define HSSR0_FRE 0x00000020 /* receive FRaming Error */
#define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
#define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
#define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
#define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
#define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
#define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
#define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
#define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
#define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
/* (inverted) */
#define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
/* (non-inverted) */
#define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
#define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
/* (inverted) */
#define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
/* (non-inverted) */
/*
* Multi-media Communications Port (MCP) control registers
*
* Registers
* Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
* Control Register 0 (read/write).
* Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
* Data Register 0 (audio, read/write).
* Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
* Data Register 1 (telecom, read/write).
* Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
* Data Register 2 (CODEC registers, read/write).
* Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
* Status Register (read/write).
* Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
* Control Register 1 (read/write).
* [The MCCR1 register is only implemented in
* versions 2.0 (rev. = 8) and higher of the StrongARM
* SA-1100.]
*
* Clocks
* fmc, Tmc Frequency, period of the MCP communication (10 MHz,
* 12 MHz, or GPIO [21]).
* faud, Taud Frequency, period of the audio sampling.
* ftcm, Ttcm Frequency, period of the telecom sampling.
*/
#define _Ser4MCCR0 0x80060000 /* Ser. port 4 MCP Control Reg. 0 */
#define _Ser4MCDR0 0x80060008 /* Ser. port 4 MCP Data Reg. 0 */
/* (audio) */
#define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */
/* (telecom) */
#define _Ser4MCDR2 0x80060010 /* Ser. port 4 MCP Data Reg. 2 */
/* (CODEC reg.) */
#define _Ser4MCSR 0x80060018 /* Ser. port 4 MCP Status Reg. */
#define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */
#if LANGUAGE == C
#define Ser4MCCR0 /* Ser. port 4 MCP Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser4MCCR0)))
#define Ser4MCDR0 /* Ser. port 4 MCP Data Reg. 0 */ \
/* (audio) */ \
(*((volatile Word *) io_p2v (_Ser4MCDR0)))
#define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \
/* (telecom) */ \
(*((volatile Word *) io_p2v (_Ser4MCDR1)))
#define Ser4MCDR2 /* Ser. port 4 MCP Data Reg. 2 */ \
/* (CODEC reg.) */ \
(*((volatile Word *) io_p2v (_Ser4MCDR2)))
#define Ser4MCSR /* Ser. port 4 MCP Status Reg. */ \
(*((volatile Word *) io_p2v (_Ser4MCSR)))
#define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser4MCCR1)))
#endif /* LANGUAGE == C */
#define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
/* [6..127] */
/* faud = fmc/(32*ASD) */
/* Taud = 32*ASD*Tmc */
#define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
/* [192..4064] */ \
((Div)/32 << FShft (MCCR0_ASD))
/* faud = fmc/(32*Floor (Div/32)) */
/* Taud = 32*Floor (Div/32)*Tmc */
#define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
(((Div) + 31)/32 << FShft (MCCR0_ASD))
/* faud = fmc/(32*Ceil (Div/32)) */
/* Taud = 32*Ceil (Div/32)*Tmc */
#define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
/* Divisor/32 [16..127] */
/* ftcm = fmc/(32*TSD) */
/* Ttcm = 32*TSD*Tmc */
#define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
/* [512..4064] */ \
((Div)/32 << FShft (MCCR0_TSD))
/* ftcm = fmc/(32*Floor (Div/32)) */
/* Ttcm = 32*Floor (Div/32)*Tmc */
#define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
(((Div) + 31)/32 << FShft (MCCR0_TSD))
/* ftcm = fmc/(32*Ceil (Div/32)) */
/* Ttcm = 32*Ceil (Div/32)*Tmc */
#define MCCR0_MCE 0x00010000 /* MCP Enable */
#define MCCR0_ECS 0x00020000 /* External Clock Select */
#define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
#define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
#define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
/* sampling/storing Mode */
#define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
#define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
#define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
/* or less interrupt Enable */
#define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
/* or more interrupt Enable */
#define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
/* or less interrupt Enable */
#define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
/* more interrupt Enable */
#define MCCR0_LBM 0x00800000 /* Look-Back Mode */
#define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
#define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
(((Div) - 1) << FShft (MCCR0_ECP))
#define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
/* FIFOs */
#define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
/* FIFOs */
/* receive/transmit CODEC reg. */
/* FIFOs: */
#define MCDR2_DATA Fld (16, 0) /* reg. DATA */
#define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
#define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
#define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
#define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
#define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
/* or less Service request (read) */
#define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
/* more Service request (read) */
#define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
/* or less Service request (read) */
#define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
/* or more Service request (read) */
#define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
#define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
#define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
#define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
#define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
/* (read) */
#define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
/* (read) */
#define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
/* (read) */
#define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
/* (read) */
#define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
/* (read) */
#define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
/* (read) */
#define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
#define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
#define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
#define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
/* (11.981 MHz) */
#define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
/* (9.585 MHz) */
/*
* Synchronous Serial Port (SSP) control registers
*
* Registers
* Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
* Register 0 (read/write).
* Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
* Register 1 (read/write).
* [Bits SPO and SP are only implemented in versions 2.0
* (rev. = 8) and higher of the StrongARM SA-1100.]
* Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
* Register (read/write).
* Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
* Register (read/write).
*
* Clocks
* fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
* or 3.5795 MHz).
* fss, Tss Frequency, period of the SSP communication.
*/
#define _Ser4SSCR0 0x80070060 /* Ser. port 4 SSP Control Reg. 0 */
#define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */
#define _Ser4SSDR 0x8007006C /* Ser. port 4 SSP Data Reg. */
#define _Ser4SSSR 0x80070074 /* Ser. port 4 SSP Status Reg. */
#if LANGUAGE == C
#define Ser4SSCR0 /* Ser. port 4 SSP Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_Ser4SSCR0)))
#define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_Ser4SSCR1)))
#define Ser4SSDR /* Ser. port 4 SSP Data Reg. */ \
(*((volatile Word *) io_p2v (_Ser4SSDR)))
#define Ser4SSSR /* Ser. port 4 SSP Status Reg. */ \
(*((volatile Word *) io_p2v (_Ser4SSSR)))
#endif /* LANGUAGE == C */
#define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
#define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
(((Size) - 1) << FShft (SSCR0_DSS))
#define SSCR0_FRF Fld (2, 4) /* FRame Format */
#define SSCR0_Motorola /* Motorola Serial Peripheral */ \
/* Interface (SPI) format */ \
(0 << FShft (SSCR0_FRF))
#define SSCR0_TI /* Texas Instruments Synchronous */ \
/* Serial format */ \
(1 << FShft (SSCR0_FRF))
#define SSCR0_National /* National Microwire format */ \
(2 << FShft (SSCR0_FRF))
#define SSCR0_SSE 0x00000080 /* SSP Enable */
#define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
/* fss = fxtl/(2*(SCR + 1)) */
/* Tss = 2*(SCR + 1)*Txtl */
#define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
(((Div) - 2)/2 << FShft (SSCR0_SCR))
/* fss = fxtl/(2*Floor (Div/2)) */
/* Tss = 2*Floor (Div/2)*Txtl */
#define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
(((Div) - 1)/2 << FShft (SSCR0_SCR))
/* fss = fxtl/(2*Ceil (Div/2)) */
/* Tss = 2*Ceil (Div/2)*Txtl */
#define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
/* Interrupt Enable */
#define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
/* Interrupt Enable */
#define SSCR1_LBM 0x00000004 /* Look-Back Mode */
#define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
#define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
#define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
#define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
#define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
/* after frame (SFRM, 1st edge) */
#define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
/* after frame (SFRM, 1st edge) */
#define SSCR1_ECS 0x00000020 /* External Clock Select */
#define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
#define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
#define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
#define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
#define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
#define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
#define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
/* Service request (read) */
#define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
/* Service request (read) */
#define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
/*
* Operating System (OS) timer control registers
*
* Registers
* OSMR0 Operating System (OS) timer Match Register 0
* (read/write).
* OSMR1 Operating System (OS) timer Match Register 1
* (read/write).
* OSMR2 Operating System (OS) timer Match Register 2
* (read/write).
* OSMR3 Operating System (OS) timer Match Register 3
* (read/write).
* OSCR Operating System (OS) timer Counter Register
* (read/write).
* OSSR Operating System (OS) timer Status Register
* (read/write).
* OWER Operating System (OS) timer Watch-dog Enable Register
* (read/write).
* OIER Operating System (OS) timer Interrupt Enable Register
* (read/write).
*/
#define _OSMR(Nb) /* OS timer Match Reg. [0..3] */ \
(0x90000000 + (Nb)*4)
#define _OSMR0 _OSMR (0) /* OS timer Match Reg. 0 */
#define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */
#define _OSMR2 _OSMR (2) /* OS timer Match Reg. 2 */
#define _OSMR3 _OSMR (3) /* OS timer Match Reg. 3 */
#define _OSCR 0x90000010 /* OS timer Counter Reg. */
#define _OSSR 0x90000014 /* OS timer Status Reg. */
#define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */
#define _OIER 0x9000001C /* OS timer Interrupt Enable Reg. */
#if LANGUAGE == C
#define OSMR /* OS timer Match Reg. [0..3] */ \
((volatile Word *) io_p2v (_OSMR (0)))
#define OSMR0 (OSMR [0]) /* OS timer Match Reg. 0 */
#define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */
#define OSMR2 (OSMR [2]) /* OS timer Match Reg. 2 */
#define OSMR3 (OSMR [3]) /* OS timer Match Reg. 3 */
#define OSCR /* OS timer Counter Reg. */ \
(*((volatile Word *) io_p2v (_OSCR)))
#define OSSR /* OS timer Status Reg. */ \
(*((volatile Word *) io_p2v (_OSSR)))
#define OWER /* OS timer Watch-dog Enable Reg. */ \
(*((volatile Word *) io_p2v (_OWER)))
#define OIER /* OS timer Interrupt Enable Reg. */ \
(*((volatile Word *) io_p2v (_OIER)))
#endif /* LANGUAGE == C */
#define OSSR_M(Nb) /* Match detected [0..3] */ \
(0x00000001 << (Nb))
#define OSSR_M0 OSSR_M (0) /* Match detected 0 */
#define OSSR_M1 OSSR_M (1) /* Match detected 1 */
#define OSSR_M2 OSSR_M (2) /* Match detected 2 */
#define OSSR_M3 OSSR_M (3) /* Match detected 3 */
#define OWER_WME 0x00000001 /* Watch-dog Match Enable */
/* (set only) */
#define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
(0x00000001 << (Nb))
#define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
#define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
#define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
#define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
/*
* Real-Time Clock (RTC) control registers
*
* Registers
* RTAR Real-Time Clock (RTC) Alarm Register (read/write).
* RCNR Real-Time Clock (RTC) CouNt Register (read/write).
* RTTR Real-Time Clock (RTC) Trim Register (read/write).
* RTSR Real-Time Clock (RTC) Status Register (read/write).
*
* Clocks
* frtx, Trtx Frequency, period of the real-time clock crystal
* (32.768 kHz nominal).
* frtc, Trtc Frequency, period of the real-time clock counter
* (1 Hz nominal).
*/
#define _RTAR 0x90010000 /* RTC Alarm Reg. */
#define _RCNR 0x90010004 /* RTC CouNt Reg. */
#define _RTTR 0x90010008 /* RTC Trim Reg. */
#define _RTSR 0x90010010 /* RTC Status Reg. */
#if LANGUAGE == C
#define RTAR /* RTC Alarm Reg. */ \
(*((volatile Word *) io_p2v (_RTAR)))
#define RCNR /* RTC CouNt Reg. */ \
(*((volatile Word *) io_p2v (_RCNR)))
#define RTTR /* RTC Trim Reg. */ \
(*((volatile Word *) io_p2v (_RTTR)))
#define RTSR /* RTC Status Reg. */ \
(*((volatile Word *) io_p2v (_RTSR)))
#endif /* LANGUAGE == C */
#define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
#define RTTR_D Fld (10, 16) /* trim Delete count */
/* frtc = (1023*(C + 1) - D)*frtx/ */
/* (1023*(C + 1)^2) */
/* Trtc = (1023*(C + 1)^2)*Trtx/ */
/* (1023*(C + 1) - D) */
#define RTSR_AL 0x00000001 /* ALarm detected */
#define RTSR_HZ 0x00000002 /* 1 Hz clock detected */
#define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */
#define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */
/*
* Power Manager (PM) control registers
*
* Registers
* PMCR Power Manager (PM) Control Register (read/write).
* PSSR Power Manager (PM) Sleep Status Register (read/write).
* PSPR Power Manager (PM) Scratch-Pad Register (read/write).
* PWER Power Manager (PM) Wake-up Enable Register
* (read/write).
* PCFR Power Manager (PM) general ConFiguration Register
* (read/write).
* PPCR Power Manager (PM) Phase-Locked Loop (PLL)
* Configuration Register (read/write).
* PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
* Sleep state Register (read/write, see GPIO pins).
* POSR Power Manager (PM) Oscillator Status Register (read).
*
* Clocks
* fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
* or 3.5795 MHz).
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
*/
#define _PMCR 0x90020000 /* PM Control Reg. */
#define _PSSR 0x90020004 /* PM Sleep Status Reg. */
#define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */
#define _PWER 0x9002000C /* PM Wake-up Enable Reg. */
#define _PCFR 0x90020010 /* PM general ConFiguration Reg. */
#define _PPCR 0x90020014 /* PM PLL Configuration Reg. */
#define _PGSR 0x90020018 /* PM GPIO Sleep state Reg. */
#define _POSR 0x9002001C /* PM Oscillator Status Reg. */
#if LANGUAGE == C
#define PMCR /* PM Control Reg. */ \
(*((volatile Word *) io_p2v (_PMCR)))
#define PSSR /* PM Sleep Status Reg. */ \
(*((volatile Word *) io_p2v (_PSSR)))
#define PSPR /* PM Scratch-Pad Reg. */ \
(*((volatile Word *) io_p2v (_PSPR)))
#define PWER /* PM Wake-up Enable Reg. */ \
(*((volatile Word *) io_p2v (_PWER)))
#define PCFR /* PM general ConFiguration Reg. */ \
(*((volatile Word *) io_p2v (_PCFR)))
#define PPCR /* PM PLL Configuration Reg. */ \
(*((volatile Word *) io_p2v (_PPCR)))
#define PGSR /* PM GPIO Sleep state Reg. */ \
(*((volatile Word *) io_p2v (_PGSR)))
#define POSR /* PM Oscillator Status Reg. */ \
(*((volatile Word *) io_p2v (_POSR)))
#elif LANGUAGE == Assembly
#define PMCR (io_p2v (_PMCR))
#define PSSR (io_p2v (_PSSR))
#define PSPR (io_p2v (_PSPR))
#define PWER (io_p2v (_PWER))
#define PCFR (io_p2v (_PCFR))
#define PPCR (io_p2v (_PPCR))
#define PGSR (io_p2v (_PGSR))
#define POSR (io_p2v (_POSR))
#endif /* LANGUAGE == C */
#define PMCR_SF 0x00000001 /* Sleep Force (set only) */
#define PSSR_SS 0x00000001 /* Software Sleep */
#define PSSR_BFS 0x00000002 /* Battery Fault Status */
/* (BATT_FAULT) */
#define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
#define PSSR_DH 0x00000008 /* DRAM control Hold */
#define PSSR_PH 0x00000010 /* Peripheral control Hold */
#define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
#define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
#define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
#define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
#define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
#define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
#define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
#define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
#define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
#define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
#define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
#define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
#define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
#define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
#define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
#define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
#define PCFR_FP 0x00000002 /* Float PCMCIA pins */
#define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
#define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
#define PCFR_FS 0x00000004 /* Float Static memory pins */
#define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
#define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
#define PCFR_FO 0x00000008 /* Force RTC oscillator */
/* (32.768 kHz) enable On */
#define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
#define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
(0x00 << FShft (PPCR_CCF))
#define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
(0x01 << FShft (PPCR_CCF))
#define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
(0x02 << FShft (PPCR_CCF))
#define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
(0x03 << FShft (PPCR_CCF))
#define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
(0x04 << FShft (PPCR_CCF))
#define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
(0x05 << FShft (PPCR_CCF))
#define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
(0x06 << FShft (PPCR_CCF))
#define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
(0x07 << FShft (PPCR_CCF))
#define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
(0x08 << FShft (PPCR_CCF))
#define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
(0x09 << FShft (PPCR_CCF))
#define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
(0x0A << FShft (PPCR_CCF))
#define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
(0x0B << FShft (PPCR_CCF))
#define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
(0x0C << FShft (PPCR_CCF))
#define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
(0x0D << FShft (PPCR_CCF))
#define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
(0x0E << FShft (PPCR_CCF))
#define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
(0x0F << FShft (PPCR_CCF))
/* 3.6864 MHz crystal (fxtl): */
#define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
#define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
#define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
#define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
#define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
#define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
#define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
#define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
#define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
#define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
#define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
#define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
#define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
#define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
#define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
#define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
/* 3.5795 MHz crystal (fxtl): */
#define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
#define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
#define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
#define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
#define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
#define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
#define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
#define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
#define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
#define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
#define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
#define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
#define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
#define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
#define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
#define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
#define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
/*
* Reset Controller (RC) control registers
*
* Registers
* RSRR Reset Controller (RC) Software Reset Register
* (read/write).
* RCSR Reset Controller (RC) Status Register (read/write).
*/
#define _RSRR 0x90030000 /* RC Software Reset Reg. */
#define _RCSR 0x90030004 /* RC Status Reg. */
#if LANGUAGE == C
#define RSRR /* RC Software Reset Reg. */ \
(*((volatile Word *) io_p2v (_RSRR)))
#define RCSR /* RC Status Reg. */ \
(*((volatile Word *) io_p2v (_RCSR)))
#endif /* LANGUAGE == C */
#define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
#define RCSR_HWR 0x00000001 /* HardWare Reset */
#define RCSR_SWR 0x00000002 /* SoftWare Reset */
#define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
#define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
/*
* Test unit control registers
*
* Registers
* TUCR Test Unit Control Register (read/write).
*/
#define _TUCR 0x90030008 /* Test Unit Control Reg. */
#if LANGUAGE == C
#define TUCR /* Test Unit Control Reg. */ \
(*((volatile Word *) io_p2v (_TUCR)))
#endif /* LANGUAGE == C */
#define TUCR_TIC 0x00000040 /* TIC mode */
#define TUCR_TTST 0x00000080 /* Trim TeST mode */
#define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
/* Check */
#define TUCR_PMD 0x00000200 /* Power Management Disable */
#define TUCR_MR 0x00000400 /* Memory Request mode */
#define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
#define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
/* grant (MBGNT) on GPIO [22:21] */
#define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
#define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
#define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
#define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
#define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
#define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
#define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
(0 << FShft (TUCR_TSEL))
#define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
(1 << FShft (TUCR_TSEL))
#define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
(2 << FShft (TUCR_TSEL))
#define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
(3 << FShft (TUCR_TSEL))
#define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
/* Clocks on GPIO [26:27] */ \
(4 << FShft (TUCR_TSEL))
#define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
/* (Alternative) */ \
(5 << FShft (TUCR_TSEL))
#define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
(6 << FShft (TUCR_TSEL))
#define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
(7 << FShft (TUCR_TSEL))
/*
* General-Purpose Input/Output (GPIO) control registers
*
* Registers
* GPLR General-Purpose Input/Output (GPIO) Pin Level
* Register (read).
* GPDR General-Purpose Input/Output (GPIO) Pin Direction
* Register (read/write).
* GPSR General-Purpose Input/Output (GPIO) Pin output Set
* Register (write).
* GPCR General-Purpose Input/Output (GPIO) Pin output Clear
* Register (write).
* GRER General-Purpose Input/Output (GPIO) Rising-Edge
* detect Register (read/write).
* GFER General-Purpose Input/Output (GPIO) Falling-Edge
* detect Register (read/write).
* GEDR General-Purpose Input/Output (GPIO) Edge Detect
* status Register (read/write).
* GAFR General-Purpose Input/Output (GPIO) Alternate
* Function Register (read/write).
*
* Clock
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
*/
#define _GPLR 0x90040000 /* GPIO Pin Level Reg. */
#define _GPDR 0x90040004 /* GPIO Pin Direction Reg. */
#define _GPSR 0x90040008 /* GPIO Pin output Set Reg. */
#define _GPCR 0x9004000C /* GPIO Pin output Clear Reg. */
#define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */
#define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */
#define _GEDR 0x90040018 /* GPIO Edge Detect status Reg. */
#define _GAFR 0x9004001C /* GPIO Alternate Function Reg. */
#if LANGUAGE == C
#define GPLR /* GPIO Pin Level Reg. */ \
(*((volatile Word *) io_p2v (_GPLR)))
#define GPDR /* GPIO Pin Direction Reg. */ \
(*((volatile Word *) io_p2v (_GPDR)))
#define GPSR /* GPIO Pin output Set Reg. */ \
(*((volatile Word *) io_p2v (_GPSR)))
#define GPCR /* GPIO Pin output Clear Reg. */ \
(*((volatile Word *) io_p2v (_GPCR)))
#define GRER /* GPIO Rising-Edge detect Reg. */ \
(*((volatile Word *) io_p2v (_GRER)))
#define GFER /* GPIO Falling-Edge detect Reg. */ \
(*((volatile Word *) io_p2v (_GFER)))
#define GEDR /* GPIO Edge Detect status Reg. */ \
(*((volatile Word *) io_p2v (_GEDR)))
#define GAFR /* GPIO Alternate Function Reg. */ \
(*((volatile Word *) io_p2v (_GAFR)))
#elif LANGUAGE == Assembly
#define GPLR (io_p2v (_GPLR))
#define GPDR (io_p2v (_GPDR))
#define GPSR (io_p2v (_GPSR))
#define GPCR (io_p2v (_GPCR))
#define GRER (io_p2v (_GRER))
#define GFER (io_p2v (_GFER))
#define GEDR (io_p2v (_GEDR))
#define GAFR (io_p2v (_GAFR))
#endif /* LANGUAGE == C */
#define GPIO_MIN (0)
#define GPIO_MAX (27)
#define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
(0x00000001 << (Nb))
#define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
#define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
#define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
#define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
#define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
#define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
#define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
#define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
#define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
#define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
#define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
#define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
#define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
#define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
#define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
#define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
#define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
#define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
#define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
#define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
#define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
#define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
#define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
#define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
#define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
#define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
#define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
#define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
#define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
GPIO_GPIO ((Nb) - 6)
#define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
#define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
#define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
#define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
#define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
#define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
#define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
#define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
/* ser. port 4: */
#define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
#define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
#define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
#define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
/* ser. port 1: */
#define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
#define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
#define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
#define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
#define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
/* ser. port 4: */
#define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
/* ser. port 3: */
#define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
/* ser. port 4: */
#define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
/* test controller: */
#define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
#define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
#define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
#define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
#define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
#define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
#define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
#define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
#define GPDR_In 0 /* Input */
#define GPDR_Out 1 /* Output */
/*
* Interrupt Controller (IC) control registers
*
* Registers
* ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
* Pending register (read).
* ICMR Interrupt Controller (IC) Mask Register (read/write).
* ICLR Interrupt Controller (IC) Level Register (read/write).
* ICCR Interrupt Controller (IC) Control Register
* (read/write).
* [The ICCR register is only implemented in versions 2.0
* (rev. = 8) and higher of the StrongARM SA-1100.]
* ICFP Interrupt Controller (IC) Fast Interrupt reQuest
* (FIQ) Pending register (read).
* ICPR Interrupt Controller (IC) Pending Register (read).
* [The ICPR register is active low (inverted) in
* versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
* StrongARM SA-1100, it is active high (non-inverted) in
* versions 2.0 (rev. = 8) and higher.]
*/
#define _ICIP 0x90050000 /* IC IRQ Pending reg. */
#define _ICMR 0x90050004 /* IC Mask Reg. */
#define _ICLR 0x90050008 /* IC Level Reg. */
#define _ICCR 0x9005000C /* IC Control Reg. */
#define _ICFP 0x90050010 /* IC FIQ Pending reg. */
#define _ICPR 0x90050020 /* IC Pending Reg. */
#if LANGUAGE == C
#define ICIP /* IC IRQ Pending reg. */ \
(*((volatile Word *) io_p2v (_ICIP)))
#define ICMR /* IC Mask Reg. */ \
(*((volatile Word *) io_p2v (_ICMR)))
#define ICLR /* IC Level Reg. */ \
(*((volatile Word *) io_p2v (_ICLR)))
#define ICCR /* IC Control Reg. */ \
(*((volatile Word *) io_p2v (_ICCR)))
#define ICFP /* IC FIQ Pending reg. */ \
(*((volatile Word *) io_p2v (_ICFP)))
#define ICPR /* IC Pending Reg. */ \
(*((volatile Word *) io_p2v (_ICPR)))
#endif /* LANGUAGE == C */
#define IC_GPIO(Nb) /* GPIO [0..10] */ \
(0x00000001 << (Nb))
#define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
#define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
#define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
#define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
#define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
#define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
#define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
#define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
#define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
#define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
#define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
#define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
#define IC_LCD 0x00001000 /* LCD controller */
#define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
#define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
#define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
#define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
#define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
#define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
#define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
#define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
(0x00100000 << (Nb))
#define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
#define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
#define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
#define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
#define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
#define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
#define IC_OST(Nb) /* OS Timer match [0..3] */ \
(0x04000000 << (Nb))
#define IC_OST0 IC_OST (0) /* OS Timer match 0 */
#define IC_OST1 IC_OST (1) /* OS Timer match 1 */
#define IC_OST2 IC_OST (2) /* OS Timer match 2 */
#define IC_OST3 IC_OST (3) /* OS Timer match 3 */
#define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
#define IC_RTCAlrm 0x80000000 /* RTC Alarm */
#define ICLR_IRQ 0 /* Interrupt ReQuest */
#define ICLR_FIQ 1 /* Fast Interrupt reQuest */
#define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
/* Mask */
#define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
/* (ICMR ignored) */
#define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
/* enable (ICMR used) */
/*
* Peripheral Pin Controller (PPC) control registers
*
* Registers
* PPDR Peripheral Pin Controller (PPC) Pin Direction
* Register (read/write).
* PPSR Peripheral Pin Controller (PPC) Pin State Register
* (read/write).
* PPAR Peripheral Pin Controller (PPC) Pin Assignment
* Register (read/write).
* PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
* Direction Register (read/write).
* PPFR Peripheral Pin Controller (PPC) Pin Flag Register
* (read).
*/
#define _PPDR 0x90060000 /* PPC Pin Direction Reg. */
#define _PPSR 0x90060004 /* PPC Pin State Reg. */
#define _PPAR 0x90060008 /* PPC Pin Assignment Reg. */
#define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */
/* Reg. */
#define _PPFR 0x90060010 /* PPC Pin Flag Reg. */
#if LANGUAGE == C
#define PPDR /* PPC Pin Direction Reg. */ \
(*((volatile Word *) io_p2v (_PPDR)))
#define PPSR /* PPC Pin State Reg. */ \
(*((volatile Word *) io_p2v (_PPSR)))
#define PPAR /* PPC Pin Assignment Reg. */ \
(*((volatile Word *) io_p2v (_PPAR)))
#define PSDR /* PPC Sleep-mode pin Direction */ \
/* Reg. */ \
(*((volatile Word *) io_p2v (_PSDR)))
#define PPFR /* PPC Pin Flag Reg. */ \
(*((volatile Word *) io_p2v (_PPFR)))
#endif /* LANGUAGE == C */
#define PPC_LDD(Nb) /* LCD Data [0..7] */ \
(0x00000001 << (Nb))
#define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
#define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
#define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
#define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
#define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
#define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
#define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
#define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
#define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
#define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
#define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
#define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
/* ser. port 1: */
#define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
#define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
/* ser. port 2: */
#define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
#define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
/* ser. port 3: */
#define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
#define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
/* ser. port 4: */
#define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
#define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
#define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
#define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
#define PPDR_In 0 /* Input */
#define PPDR_Out 1 /* Output */
/* ser. port 1: */
#define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
#define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
#define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
/* ser. port 4: */
#define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
#define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
/* & SFRM_C */
#define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
#define PSDR_OutL 0 /* Output Low in sleep mode */
#define PSDR_Flt 1 /* Floating (input) in sleep mode */
#define PPFR_LCD 0x00000001 /* LCD controller */
#define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
#define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
#define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
#define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
#define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
#define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
#define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
#define PPFR_PerEn 0 /* Peripheral Enabled */
#define PPFR_PPCEn 1 /* PPC Enabled */
/*
* Dynamic Random-Access Memory (DRAM) control registers
*
* Registers
* MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
* CoNFiGuration register (read/write).
* MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
* Column Address Strobe (CAS) shift register 0
* (read/write).
* MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
* Column Address Strobe (CAS) shift register 1
* (read/write).
* MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
* Column Address Strobe (CAS) shift register 2
* (read/write).
*
* Clocks
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
* fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
* fcas, Tcas Frequency, period of the DRAM CAS shift registers.
*/
/* Memory system: */
#define _MDCNFG 0xA0000000 /* DRAM CoNFiGuration reg. */
#define _MDCAS(Nb) /* DRAM CAS shift reg. [0..3] */ \
(0xA0000004 + (Nb)*4)
#define _MDCAS0 _MDCAS (0) /* DRAM CAS shift reg. 0 */
#define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */
#define _MDCAS2 _MDCAS (2) /* DRAM CAS shift reg. 2 */
#if LANGUAGE == C
/* Memory system: */
#define MDCNFG /* DRAM CoNFiGuration reg. */ \
(*((volatile Word *) io_p2v (_MDCNFG)))
#define MDCAS /* DRAM CAS shift reg. [0..3] */ \
((volatile Word *) io_p2v (_MDCAS (0)))
#define MDCAS0 (MDCAS [0]) /* DRAM CAS shift reg. 0 */
#define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */
#define MDCAS2 (MDCAS [2]) /* DRAM CAS shift reg. 2 */
#elif LANGUAGE == Assembly
#define MDCNFG (io_p2v(_MDCNFG))
#endif /* LANGUAGE == C */
/* SA1100 MDCNFG values */
#define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
(0x00000001 << (Nb))
#define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
#define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
#define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
#define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
#define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
#define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
(((Add) - 9) << FShft (MDCNFG_DRAC))
#define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
/* (fcas = fcpu/2) */
#define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
#define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
(((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
#define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
(((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
#define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
#define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
(((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
#define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
(((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
#define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
#define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
((Tcpu) << FShft (MDCNFG_TDL))
#define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
/* [Tmem] */
#define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
/* [0..262136 Tcpu] */ \
((Tcpu)/8 << FShft (MDCNFG_DRI))
/* SA1110 MDCNFG values */
#define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
#define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
#define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
#define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
#define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
/* bank 0/1 */
#define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
#define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
#define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
/* deassertion 0/1 */
#define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
#define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
#define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
#define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
#define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
#define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
/* bank 0/1 */
#define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
#define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
#define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
/* deassertion 0/1 */
#define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
/*
* Static memory control registers
*
* Registers
* MSC0 Memory system: Static memory Control register 0
* (read/write).
* MSC1 Memory system: Static memory Control register 1
* (read/write).
*
* Clocks
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
* fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
*/
/* Memory system: */
#define _MSC(Nb) /* Static memory Control reg. */ \
/* [0..1] */ \
(0xA0000010 + (Nb)*4)
#define _MSC0 _MSC (0) /* Static memory Control reg. 0 */
#define _MSC1 _MSC (1) /* Static memory Control reg. 1 */
#define _MSC2 0xA000002C /* Static memory Control reg. 2, not contiguous */
#if LANGUAGE == C
/* Memory system: */
#define MSC /* Static memory Control reg. */ \
/* [0..1] */ \
((volatile Word *) io_p2v (_MSC (0)))
#define MSC0 (MSC [0]) /* Static memory Control reg. 0 */
#define MSC1 (MSC [1]) /* Static memory Control reg. 1 */
#define MSC2 (*(volatile Word *) io_p2v (_MSC2)) /* Static memory Control reg. 2 */
#elif LANGUAGE == Assembly
#define MSC0 io_p2v(0xa0000010)
#define MSC1 io_p2v(0xa0000014)
#define MSC2 io_p2v(0xa000002c)
#endif /* LANGUAGE == C */
#define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
Fld (16, ((Nb) Modulo 2)*16)
#define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
#define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
#define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
#define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
#define MSC_RT Fld (2, 0) /* ROM/static memory Type */
#define MSC_NonBrst /* Non-Burst static memory */ \
(0 << FShft (MSC_RT))
#define MSC_SRAM /* 32-bit byte-writable SRAM */ \
(1 << FShft (MSC_RT))
#define MSC_Brst4 /* Burst-of-4 static memory */ \
(2 << FShft (MSC_RT))
#define MSC_Brst8 /* Burst-of-8 static memory */ \
(3 << FShft (MSC_RT))
#define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
#define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
#define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
#define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
/* First access - 1(.5) [Tmem] */
#define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
/* static memory) [3..65 Tcpu] */ \
((((Tcpu) - 3)/2) << FShft (MSC_RDF))
#define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MSC_RDF))
#define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
/* static memory) [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MSC_RDF))
#define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MSC_RDF))
#define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
/* Next access - 1 [Tmem] */
#define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
/* static memory) [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MSC_RDN))
#define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MSC_RDN))
#define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
/* static memory) [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MSC_RDN))
#define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MSC_RDN))
#define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
/* time/2 [Tmem] */
#define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
(((Tcpu)/4) << FShft (MSC_RRR))
#define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
((((Tcpu) + 3)/4) << FShft (MSC_RRR))
/*
* Personal Computer Memory Card International Association (PCMCIA) control
* register
*
* Register
* MECR Memory system: Expansion memory bus (PCMCIA)
* Configuration Register (read/write).
*
* Clocks
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
* fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
* fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK).
*/
/* Memory system: */
#define _MECR 0xA0000018 /* Expansion memory bus (PCMCIA) */
/* Configuration Reg. */
#if LANGUAGE == C
/* Memory system: */
#define MECR /* Expansion memory bus (PCMCIA) */ \
/* Configuration Reg. */ \
(*((volatile Word *) io_p2v (_MECR)))
#endif /* LANGUAGE == C */
#define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
Fld (15, (Nb)*16)
#define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
#define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
#define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
#define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
#define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
#define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
/* [Tmem] */
#define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MECR_BSA))
#define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MECR_BSA))
#define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
#define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
((((Tcpu) - 2)/2) << FShft (MECR_BSM))
#define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
((((Tcpu) - 1)/2) << FShft (MECR_BSM))
/*
* On SA1110 only
*/
#define _MDREFR 0xA000001C
#if LANGUAGE == C
/* Memory system: */
#define MDREFR \
(*((volatile Word *) io_p2v (_MDREFR)))
#elif LANGUAGE == Assembly
#define MDREFR (io_p2v(_MDREFR))
#endif /* LANGUAGE == C */
#define MDREFR_TRASR Fld (4, 0)
#define MDREFR_DRI Fld (12, 4)
#define MDREFR_E0PIN (1 << 16)
#define MDREFR_K0RUN (1 << 17)
#define MDREFR_K0DB2 (1 << 18)
#define MDREFR_E1PIN (1 << 20)
#define MDREFR_K1RUN (1 << 21)
#define MDREFR_K1DB2 (1 << 22)
#define MDREFR_K2RUN (1 << 25)
#define MDREFR_K2DB2 (1 << 26)
#define MDREFR_EAPD (1 << 28)
#define MDREFR_KAPD (1 << 29)
#define MDREFR_SLFRSH (1 << 31)
/*
* Direct Memory Access (DMA) control registers
*
* Registers
* DDAR0 Direct Memory Access (DMA) Device Address Register
* channel 0 (read/write).
* DCSR0 Direct Memory Access (DMA) Control and Status
* Register channel 0 (read/write).
* DBSA0 Direct Memory Access (DMA) Buffer Start address
* register A channel 0 (read/write).
* DBTA0 Direct Memory Access (DMA) Buffer Transfer count
* register A channel 0 (read/write).
* DBSB0 Direct Memory Access (DMA) Buffer Start address
* register B channel 0 (read/write).
* DBTB0 Direct Memory Access (DMA) Buffer Transfer count
* register B channel 0 (read/write).
*
* DDAR1 Direct Memory Access (DMA) Device Address Register
* channel 1 (read/write).
* DCSR1 Direct Memory Access (DMA) Control and Status
* Register channel 1 (read/write).
* DBSA1 Direct Memory Access (DMA) Buffer Start address
* register A channel 1 (read/write).
* DBTA1 Direct Memory Access (DMA) Buffer Transfer count
* register A channel 1 (read/write).
* DBSB1 Direct Memory Access (DMA) Buffer Start address
* register B channel 1 (read/write).
* DBTB1 Direct Memory Access (DMA) Buffer Transfer count
* register B channel 1 (read/write).
*
* DDAR2 Direct Memory Access (DMA) Device Address Register
* channel 2 (read/write).
* DCSR2 Direct Memory Access (DMA) Control and Status
* Register channel 2 (read/write).
* DBSA2 Direct Memory Access (DMA) Buffer Start address
* register A channel 2 (read/write).
* DBTA2 Direct Memory Access (DMA) Buffer Transfer count
* register A channel 2 (read/write).
* DBSB2 Direct Memory Access (DMA) Buffer Start address
* register B channel 2 (read/write).
* DBTB2 Direct Memory Access (DMA) Buffer Transfer count
* register B channel 2 (read/write).
*
* DDAR3 Direct Memory Access (DMA) Device Address Register
* channel 3 (read/write).
* DCSR3 Direct Memory Access (DMA) Control and Status
* Register channel 3 (read/write).
* DBSA3 Direct Memory Access (DMA) Buffer Start address
* register A channel 3 (read/write).
* DBTA3 Direct Memory Access (DMA) Buffer Transfer count
* register A channel 3 (read/write).
* DBSB3 Direct Memory Access (DMA) Buffer Start address
* register B channel 3 (read/write).
* DBTB3 Direct Memory Access (DMA) Buffer Transfer count
* register B channel 3 (read/write).
*
* DDAR4 Direct Memory Access (DMA) Device Address Register
* channel 4 (read/write).
* DCSR4 Direct Memory Access (DMA) Control and Status
* Register channel 4 (read/write).
* DBSA4 Direct Memory Access (DMA) Buffer Start address
* register A channel 4 (read/write).
* DBTA4 Direct Memory Access (DMA) Buffer Transfer count
* register A channel 4 (read/write).
* DBSB4 Direct Memory Access (DMA) Buffer Start address
* register B channel 4 (read/write).
* DBTB4 Direct Memory Access (DMA) Buffer Transfer count
* register B channel 4 (read/write).
*
* DDAR5 Direct Memory Access (DMA) Device Address Register
* channel 5 (read/write).
* DCSR5 Direct Memory Access (DMA) Control and Status
* Register channel 5 (read/write).
* DBSA5 Direct Memory Access (DMA) Buffer Start address
* register A channel 5 (read/write).
* DBTA5 Direct Memory Access (DMA) Buffer Transfer count
* register A channel 5 (read/write).
* DBSB5 Direct Memory Access (DMA) Buffer Start address
* register B channel 5 (read/write).
* DBTB5 Direct Memory Access (DMA) Buffer Transfer count
* register B channel 5 (read/write).
*/
#define DMASp 0x00000020 /* DMA control reg. Space [byte] */
#define _DDAR(Nb) /* DMA Device Address Reg. */ \
/* channel [0..5] */ \
(0xB0000000 + (Nb)*DMASp)
#define _SetDCSR(Nb) /* Set DMA Control & Status Reg. */ \
/* channel [0..5] (write) */ \
(0xB0000004 + (Nb)*DMASp)
#define _ClrDCSR(Nb) /* Clear DMA Control & Status Reg. */ \
/* channel [0..5] (write) */ \
(0xB0000008 + (Nb)*DMASp)
#define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \
/* channel [0..5] (read) */ \
(0xB000000C + (Nb)*DMASp)
#define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \
/* channel [0..5] */ \
(0xB0000010 + (Nb)*DMASp)
#define _DBTA(Nb) /* DMA Buffer Transfer count */ \
/* reg. A channel [0..5] */ \
(0xB0000014 + (Nb)*DMASp)
#define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \
/* channel [0..5] */ \
(0xB0000018 + (Nb)*DMASp)
#define _DBTB(Nb) /* DMA Buffer Transfer count */ \
/* reg. B channel [0..5] */ \
(0xB000001C + (Nb)*DMASp)
#define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */
/* channel 0 */
#define _SetDCSR0 _SetDCSR (0) /* Set DMA Control & Status Reg. */
/* channel 0 (write) */
#define _ClrDCSR0 _ClrDCSR (0) /* Clear DMA Control & Status Reg. */
/* channel 0 (write) */
#define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */
/* channel 0 (read) */
#define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */
/* channel 0 */
#define _DBTA0 _DBTA (0) /* DMA Buffer Transfer count */
/* reg. A channel 0 */
#define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */
/* channel 0 */
#define _DBTB0 _DBTB (0) /* DMA Buffer Transfer count */
/* reg. B channel 0 */
#define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */
/* channel 1 */
#define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */
/* channel 1 (write) */
#define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */
/* channel 1 (write) */
#define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */
/* channel 1 (read) */
#define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */
/* channel 1 */
#define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */
/* reg. A channel 1 */
#define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */
/* channel 1 */
#define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */
/* reg. B channel 1 */
#define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */
/* channel 2 */
#define _SetDCSR2 _SetDCSR (2) /* Set DMA Control & Status Reg. */
/* channel 2 (write) */
#define _ClrDCSR2 _ClrDCSR (2) /* Clear DMA Control & Status Reg. */
/* channel 2 (write) */
#define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */
/* channel 2 (read) */
#define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */
/* channel 2 */
#define _DBTA2 _DBTA (2) /* DMA Buffer Transfer count */
/* reg. A channel 2 */
#define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */
/* channel 2 */
#define _DBTB2 _DBTB (2) /* DMA Buffer Transfer count */
/* reg. B channel 2 */
#define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */
/* channel 3 */
#define _SetDCSR3 _SetDCSR (3) /* Set DMA Control & Status Reg. */
/* channel 3 (write) */
#define _ClrDCSR3 _ClrDCSR (3) /* Clear DMA Control & Status Reg. */
/* channel 3 (write) */
#define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */
/* channel 3 (read) */
#define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */
/* channel 3 */
#define _DBTA3 _DBTA (3) /* DMA Buffer Transfer count */
/* reg. A channel 3 */
#define _DBSB3 _DBSB (3) /* DMA Buffer Start address reg. B */
/* channel 3 */
#define _DBTB3 _DBTB (3) /* DMA Buffer Transfer count */
/* reg. B channel 3 */
#define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */
/* channel 4 */
#define _SetDCSR4 _SetDCSR (4) /* Set DMA Control & Status Reg. */
/* channel 4 (write) */
#define _ClrDCSR4 _ClrDCSR (4) /* Clear DMA Control & Status Reg. */
/* channel 4 (write) */
#define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */
/* channel 4 (read) */
#define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */
/* channel 4 */
#define _DBTA4 _DBTA (4) /* DMA Buffer Transfer count */
/* reg. A channel 4 */
#define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */
/* channel 4 */
#define _DBTB4 _DBTB (4) /* DMA Buffer Transfer count */
/* reg. B channel 4 */
#define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */
/* channel 5 */
#define _SetDCSR5 _SetDCSR (5) /* Set DMA Control & Status Reg. */
/* channel 5 (write) */
#define _ClrDCSR5 _ClrDCSR (5) /* Clear DMA Control & Status Reg. */
/* channel 5 (write) */
#define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */
/* channel 5 (read) */
#define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */
/* channel 5 */
#define _DBTA5 _DBTA (5) /* DMA Buffer Transfer count */
/* reg. A channel 5 */
#define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */
/* channel 5 */
#define _DBTB5 _DBTB (5) /* DMA Buffer Transfer count */
/* reg. B channel 5 */
#if LANGUAGE == C
#define DDAR0 /* DMA Device Address Reg. */ \
/* channel 0 */ \
(*((volatile Word *) io_p2v (_DDAR0)))
#define SetDCSR0 /* Set DMA Control & Status Reg. */ \
/* channel 0 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR0)))
#define ClrDCSR0 /* Clear DMA Control & Status Reg. */ \
/* channel 0 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR0)))
#define RdDCSR0 /* Read DMA Control & Status Reg. */ \
/* channel 0 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR0)))
#define DBSA0 /* DMA Buffer Start address reg. A */ \
/* channel 0 */ \
(*((volatile Address *) io_p2v (_DBSA0)))
#define DBTA0 /* DMA Buffer Transfer count */ \
/* reg. A channel 0 */ \
(*((volatile Word *) io_p2v (_DBTA0)))
#define DBSB0 /* DMA Buffer Start address reg. B */ \
/* channel 0 */ \
(*((volatile Address *) io_p2v (_DBSB0)))
#define DBTB0 /* DMA Buffer Transfer count */ \
/* reg. B channel 0 */ \
(*((volatile Word *) io_p2v (_DBTB0)))
#define DDAR1 /* DMA Device Address Reg. */ \
/* channel 1 */ \
(*((volatile Word *) io_p2v (_DDAR1)))
#define SetDCSR1 /* Set DMA Control & Status Reg. */ \
/* channel 1 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR1)))
#define ClrDCSR1 /* Clear DMA Control & Status Reg. */ \
/* channel 1 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR1)))
#define RdDCSR1 /* Read DMA Control & Status Reg. */ \
/* channel 1 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR1)))
#define DBSA1 /* DMA Buffer Start address reg. A */ \
/* channel 1 */ \
(*((volatile Address *) io_p2v (_DBSA1)))
#define DBTA1 /* DMA Buffer Transfer count */ \
/* reg. A channel 1 */ \
(*((volatile Word *) io_p2v (_DBTA1)))
#define DBSB1 /* DMA Buffer Start address reg. B */ \
/* channel 1 */ \
(*((volatile Address *) io_p2v (_DBSB1)))
#define DBTB1 /* DMA Buffer Transfer count */ \
/* reg. B channel 1 */ \
(*((volatile Word *) io_p2v (_DBTB1)))
#define DDAR2 /* DMA Device Address Reg. */ \
/* channel 2 */ \
(*((volatile Word *) io_p2v (_DDAR2)))
#define SetDCSR2 /* Set DMA Control & Status Reg. */ \
/* channel 2 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR2)))
#define ClrDCSR2 /* Clear DMA Control & Status Reg. */ \
/* channel 2 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR2)))
#define RdDCSR2 /* Read DMA Control & Status Reg. */ \
/* channel 2 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR2)))
#define DBSA2 /* DMA Buffer Start address reg. A */ \
/* channel 2 */ \
(*((volatile Address *) io_p2v (_DBSA2)))
#define DBTA2 /* DMA Buffer Transfer count */ \
/* reg. A channel 2 */ \
(*((volatile Word *) io_p2v (_DBTA2)))
#define DBSB2 /* DMA Buffer Start address reg. B */ \
/* channel 2 */ \
(*((volatile Address *) io_p2v (_DBSB2)))
#define DBTB2 /* DMA Buffer Transfer count */ \
/* reg. B channel 2 */ \
(*((volatile Word *) io_p2v (_DBTB2)))
#define DDAR3 /* DMA Device Address Reg. */ \
/* channel 3 */ \
(*((volatile Word *) io_p2v (_DDAR3)))
#define SetDCSR3 /* Set DMA Control & Status Reg. */ \
/* channel 3 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR3)))
#define ClrDCSR3 /* Clear DMA Control & Status Reg. */ \
/* channel 3 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR3)))
#define RdDCSR3 /* Read DMA Control & Status Reg. */ \
/* channel 3 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR3)))
#define DBSA3 /* DMA Buffer Start address reg. A */ \
/* channel 3 */ \
(*((volatile Address *) io_p2v (_DBSA3)))
#define DBTA3 /* DMA Buffer Transfer count */ \
/* reg. A channel 3 */ \
(*((volatile Word *) io_p2v (_DBTA3)))
#define DBSB3 /* DMA Buffer Start address reg. B */ \
/* channel 3 */ \
(*((volatile Address *) io_p2v (_DBSB3)))
#define DBTB3 /* DMA Buffer Transfer count */ \
/* reg. B channel 3 */ \
(*((volatile Word *) io_p2v (_DBTB3)))
#define DDAR4 /* DMA Device Address Reg. */ \
/* channel 4 */ \
(*((volatile Word *) io_p2v (_DDAR4)))
#define SetDCSR4 /* Set DMA Control & Status Reg. */ \
/* channel 4 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR4)))
#define ClrDCSR4 /* Clear DMA Control & Status Reg. */ \
/* channel 4 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR4)))
#define RdDCSR4 /* Read DMA Control & Status Reg. */ \
/* channel 4 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR4)))
#define DBSA4 /* DMA Buffer Start address reg. A */ \
/* channel 4 */ \
(*((volatile Address *) io_p2v (_DBSA4)))
#define DBTA4 /* DMA Buffer Transfer count */ \
/* reg. A channel 4 */ \
(*((volatile Word *) io_p2v (_DBTA4)))
#define DBSB4 /* DMA Buffer Start address reg. B */ \
/* channel 4 */ \
(*((volatile Address *) io_p2v (_DBSB4)))
#define DBTB4 /* DMA Buffer Transfer count */ \
/* reg. B channel 4 */ \
(*((volatile Word *) io_p2v (_DBTB4)))
#define DDAR5 /* DMA Device Address Reg. */ \
/* channel 5 */ \
(*((volatile Word *) io_p2v (_DDAR5)))
#define SetDCSR5 /* Set DMA Control & Status Reg. */ \
/* channel 5 (write) */ \
(*((volatile Word *) io_p2v (_SetDCSR5)))
#define ClrDCSR5 /* Clear DMA Control & Status Reg. */ \
/* channel 5 (write) */ \
(*((volatile Word *) io_p2v (_ClrDCSR5)))
#define RdDCSR5 /* Read DMA Control & Status Reg. */ \
/* channel 5 (read) */ \
(*((volatile Word *) io_p2v (_RdDCSR5)))
#define DBSA5 /* DMA Buffer Start address reg. A */ \
/* channel 5 */ \
(*((volatile Address *) io_p2v (_DBSA5)))
#define DBTA5 /* DMA Buffer Transfer count */ \
/* reg. A channel 5 */ \
(*((volatile Word *) io_p2v (_DBTA5)))
#define DBSB5 /* DMA Buffer Start address reg. B */ \
/* channel 5 */ \
(*((volatile Address *) io_p2v (_DBSB5)))
#define DBTB5 /* DMA Buffer Transfer count */ \
/* reg. B channel 5 */ \
(*((volatile Word *) io_p2v (_DBTB5)))
#endif /* LANGUAGE == C */
#define DDAR_RW 0x00000001 /* device data Read/Write */
#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
/* (memory -> device) */
#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
/* (device -> memory) */
#define DDAR_E 0x00000002 /* big/little Endian device */
#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
#define DDAR_BS 0x00000004 /* device Burst Size */
#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
#define DDAR_DW 0x00000008 /* device Data Width */
#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
#define DDAR_DS Fld (4, 4) /* Device Select */
#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
(0x0 << FShft (DDAR_DS))
#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
(0x1 << FShft (DDAR_DS))
#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
(0x2 << FShft (DDAR_DS))
#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
(0x3 << FShft (DDAR_DS))
#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
(0x4 << FShft (DDAR_DS))
#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
(0x5 << FShft (DDAR_DS))
#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
(0x6 << FShft (DDAR_DS))
#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
(0x7 << FShft (DDAR_DS))
#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
(0x8 << FShft (DDAR_DS))
#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
(0x9 << FShft (DDAR_DS))
#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
/* (audio) */ \
(0xA << FShft (DDAR_DS))
#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
/* (audio) */ \
(0xB << FShft (DDAR_DS))
#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
/* (telecom) */ \
(0xC << FShft (DDAR_DS))
#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
/* (telecom) */ \
(0xD << FShft (DDAR_DS))
#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
(0xE << FShft (DDAR_DS))
#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
(0xF << FShft (DDAR_DS))
#define DDAR_DA Fld (24, 8) /* Device Address */
#define DDAR_DevAdd(Add) /* Device Address */ \
(((Add) & 0xF0000000) | \
(((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
DDAR_Ser0UDCTr + DDAR_DevAdd (_Ser0UDCDR))
#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
DDAR_Ser0UDCRc + DDAR_DevAdd (_Ser0UDCDR))
#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser1UARTTr + DDAR_DevAdd (_Ser1UTDR))
#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser1UARTRc + DDAR_DevAdd (_Ser1UTDR))
#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser1SDLCTr + DDAR_DevAdd (_Ser1SDDR))
#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser1SDLCRc + DDAR_DevAdd (_Ser1SDDR))
#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2UTDR))
#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2UTDR))
#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
(DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
DDAR_Ser2ICPTr + DDAR_DevAdd (_Ser2HSDR))
#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
(DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
DDAR_Ser2ICPRc + DDAR_DevAdd (_Ser2HSDR))
#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser3UARTTr + DDAR_DevAdd (_Ser3UTDR))
#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
DDAR_Ser3UARTRc + DDAR_DevAdd (_Ser3UTDR))
#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4MCP0Tr + DDAR_DevAdd (_Ser4MCDR0))
#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4MCP0Rc + DDAR_DevAdd (_Ser4MCDR0))
#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
/* (telecom) */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4MCP1Tr + DDAR_DevAdd (_Ser4MCDR1))
#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
/* (telecom) */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4MCP1Rc + DDAR_DevAdd (_Ser4MCDR1))
#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
(DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4SSPTr + DDAR_DevAdd (_Ser4SSDR))
#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
(DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
DDAR_Ser4SSPRc + DDAR_DevAdd (_Ser4SSDR))
#define DCSR_RUN 0x00000001 /* DMA RUNing */
#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
#define DCSR_ERROR 0x00000004 /* DMA ERROR */
#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
#define DBT_TC Fld (13, 0) /* Transfer Count */
#define DBTA_TCA DBT_TC /* Transfer Count buffer A */
#define DBTB_TCB DBT_TC /* Transfer Count buffer B */
/*
* Liquid Crystal Display (LCD) control registers
*
* Registers
* LCCR0 Liquid Crystal Display (LCD) Control Register 0
* (read/write).
* [Bits LDM, BAM, and ERM are only implemented in
* versions 2.0 (rev. = 8) and higher of the StrongARM
* SA-1100.]
* LCSR Liquid Crystal Display (LCD) Status Register
* (read/write).
* [Bit LDD can be only read in versions 1.0 (rev. = 1)
* and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
* read and written (cleared) in versions 2.0 (rev. = 8)
* and higher.]
* DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
* (DMA) Base Address Register channel 1 (read/write).
* DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
* (DMA) Current Address Register channel 1 (read).
* DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
* (DMA) Base Address Register channel 2 (read/write).
* DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
* (DMA) Current Address Register channel 2 (read).
* LCCR1 Liquid Crystal Display (LCD) Control Register 1
* (read/write).
* [The LCCR1 register can be only written in
* versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
* StrongARM SA-1100, it can be written and read in
* versions 2.0 (rev. = 8) and higher.]
* LCCR2 Liquid Crystal Display (LCD) Control Register 2
* (read/write).
* [The LCCR1 register can be only written in
* versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
* StrongARM SA-1100, it can be written and read in
* versions 2.0 (rev. = 8) and higher.]
* LCCR3 Liquid Crystal Display (LCD) Control Register 3
* (read/write).
* [The LCCR1 register can be only written in
* versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
* StrongARM SA-1100, it can be written and read in
* versions 2.0 (rev. = 8) and higher. Bit PCP is only
* implemented in versions 2.0 (rev. = 8) and higher of
* the StrongARM SA-1100.]
*
* Clocks
* fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
* fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
* fpix, Tpix Frequency, period of the pixel clock.
* fln, Tln Frequency, period of the line clock.
* fac, Tac Frequency, period of the AC bias clock.
*/
#define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
#define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
/* [byte] */ \
(16*LCD_PEntrySp)
#define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
/* [byte] */ \
(256*LCD_PEntrySp)
#define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
/* dummy-Palette Space [byte] */ \
(16*LCD_PEntrySp)
#define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
#define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
#define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
#define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
#define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
#define LCD_4Bit /* LCD 4-Bit pixel mode */ \
(0 << FShft (LCD_PBS))
#define LCD_8Bit /* LCD 8-Bit pixel mode */ \
(1 << FShft (LCD_PBS))
#define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
(2 << FShft (LCD_PBS))
#define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
#define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
#define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
#define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
#define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
#define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
#define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
#define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
#define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
#define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
#define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
#define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
#define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
#define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
#define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
/* (Alternative) */
#define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */
#define _LCSR 0xB0100004 /* LCD Status Reg. */
#define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */
/* channel 1 */
#define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */
/* channel 1 */
#define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */
/* channel 2 */
#define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */
/* channel 2 */
#define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */
#define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */
#define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */
#if LANGUAGE == C
#define LCCR0 /* LCD Control Reg. 0 */ \
(*((volatile Word *) io_p2v (_LCCR0)))
#define LCSR /* LCD Status Reg. */ \
(*((volatile Word *) io_p2v (_LCSR)))
#define DBAR1 /* LCD DMA Base Address Reg. */ \
/* channel 1 */ \
(*((volatile Address *) io_p2v (_DBAR1)))
#define DCAR1 /* LCD DMA Current Address Reg. */ \
/* channel 1 */ \
(*((volatile Address *) io_p2v (_DCAR1)))
#define DBAR2 /* LCD DMA Base Address Reg. */ \
/* channel 2 */ \
(*((volatile Address *) io_p2v (_DBAR2)))
#define DCAR2 /* LCD DMA Current Address Reg. */ \
/* channel 2 */ \
(*((volatile Address *) io_p2v (_DCAR2)))
#define LCCR1 /* LCD Control Reg. 1 */ \
(*((volatile Word *) io_p2v (_LCCR1)))
#define LCCR2 /* LCD Control Reg. 2 */ \
(*((volatile Word *) io_p2v (_LCCR2)))
#define LCCR3 /* LCD Control Reg. 3 */ \
(*((volatile Word *) io_p2v (_LCCR3)))
#endif /* LANGUAGE == C */
#define LCCR0_LEN 0x00000001 /* LCD ENable */
#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
#define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
/* Select */
#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
#define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
/* interrupt Mask (disable) */
#define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
/* interrupt Mask (disable) */
#define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
/* IUU, OOL, OUL, OOU, and OUU) */
/* interrupt Mask (disable) */
#define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
#define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
#define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
#define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
#define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
/* display mode) */
#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
/* display */
#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
/* display */
#define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
/* [Tmem] */
#define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
/* [0..510 Tcpu] */ \
((Tcpu)/2 << FShft (LCCR0_PDD))
#define LCSR_LDD 0x00000001 /* LCD Disable Done */
#define LCSR_BAU 0x00000002 /* Base Address Update (read) */
#define LCSR_BER 0x00000004 /* Bus ERror */
#define LCSR_ABC 0x00000008 /* AC Bias clock Count */
#define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
/* panel */
#define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
/* panel */
#define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
/* panel */
#define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
/* panel */
#define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
/* panel */
#define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
/* panel */
#define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
/* panel */
#define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
/* panel */
#define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
#define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
(((Pixel) - 16)/16 << FShft (LCCR1_PPL))
#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
/* pulse Width - 2 [Tpix] (L_LCLK) */
#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
/* pulse Width [2..65 Tpix] */ \
(((Tpix) - 2) << FShft (LCCR1_HSW))
#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
/* count - 1 [Tpix] */
#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
/* [1..256 Tpix] */ \
(((Tpix) - 1) << FShft (LCCR1_ELW))
#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
/* Wait count - 1 [Tpix] */
#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
/* [1..256 Tpix] */ \
(((Tpix) - 1) << FShft (LCCR1_BLW))
#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
(((Line) - 1) << FShft (LCCR2_LPP))
#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
/* Width - 1 [Tln] (L_FCLK) */
#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
/* Width [1..64 Tln] */ \
(((Tln) - 1) << FShft (LCCR2_VSW))
#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
/* count [Tln] */
#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
/* [0..255 Tln] */ \
((Tln) << FShft (LCCR2_EFW))
#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
/* Wait count [Tln] */
#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
/* [0..255 Tln] */ \
((Tln) << FShft (LCCR2_BFW))
#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
/* [1..255] (L_PCLK) */
/* fpix = fcpu/(2*(PCD + 2)) */
/* Tpix = 2*(PCD + 2)*Tcpu */
#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
(((Div) - 4)/2 << FShft (LCCR3_PCD))
/* fpix = fcpu/(2*Floor (Div/2)) */
/* Tpix = 2*Floor (Div/2)*Tcpu */
#define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
(((Div) - 3)/2 << FShft (LCCR3_PCD))
/* fpix = fcpu/(2*Ceil (Div/2)) */
/* Tpix = 2*Ceil (Div/2)*Tcpu */
#define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
/* [Tln] (L_BIAS) */
#define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
(((Div) - 2)/2 << FShft (LCCR3_ACB))
/* fac = fln/(2*Floor (Div/2)) */
/* Tac = 2*Floor (Div/2)*Tln */
#define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
(((Div) - 1)/2 << FShft (LCCR3_ACB))
/* fac = fln/(2*Ceil (Div/2)) */
/* Tac = 2*Ceil (Div/2)*Tln */
#define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
/* Interrupt */
#define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
/* Off */ \
(0 << FShft (LCCR3_API))
#define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
/* [1..15] */ \
((Trans) << FShft (LCCR3_API))
#define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
/* Polarity (L_FCLK) */
#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
/* active High */
#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
/* active Low */
#define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
/* pulse Polarity (L_LCLK) */
#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
/* pulse active High */
#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
/* pulse active Low */
#define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
#define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
/* active display mode) */
#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
#undef C
#undef Assembly
|
1001-study-uboot
|
include/SA-1100.h
|
C
|
gpl3
| 125,404
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FM_ETH_H__
#define __FM_ETH_H__
#include <common.h>
#include <asm/types.h>
#include <asm/fsl_enet.h>
enum fm_port {
FM1_DTSEC1,
FM1_DTSEC2,
FM1_DTSEC3,
FM1_DTSEC4,
FM1_DTSEC5,
FM1_10GEC1,
FM2_DTSEC1,
FM2_DTSEC2,
FM2_DTSEC3,
FM2_DTSEC4,
FM2_10GEC1,
NUM_FM_PORTS,
};
enum fm_eth_type {
FM_ETH_1G_E,
FM_ETH_10G_E,
};
#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
/* Fman ethernet info struct */
#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
.fm = idx, \
.phy_regs = (void *)pregs, \
.enet_if = PHY_INTERFACE_MODE_NONE, \
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
{ \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_1G_E, \
.port = FM##idx##_DTSEC##n, \
.rx_port_id = RX_PORT_1G_BASE + n - 1, \
.tx_port_id = TX_PORT_1G_BASE + n - 1, \
.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, mac_1g[n-1]),\
}
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
.index = idx, \
.num = n - 1, \
.type = FM_ETH_10G_E, \
.port = FM##idx##_10GEC##n, \
.rx_port_id = RX_PORT_10G_BASE + n - 1, \
.tx_port_id = TX_PORT_10G_BASE + n - 1, \
.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, mac_10g[n-1]),\
}
struct fm_eth_info {
u8 enabled;
u8 fm;
u8 num;
u8 phy_addr;
int index;
u16 rx_port_id;
u16 tx_port_id;
enum fm_port port;
enum fm_eth_type type;
void *phy_regs;
phy_interface_t enet_if;
u32 compat_offset;
struct mii_dev *bus;
};
struct tgec_mdio_info {
struct tgec_mdio_controller *regs;
char *name;
};
int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
int fm_standard_init(bd_t *bis);
void fman_enet_init(void);
void fdt_fixup_fman_ethernet(void *fdt);
phy_interface_t fm_info_get_enet_if(enum fm_port port);
void fm_info_set_phy_address(enum fm_port port, int address);
void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
void fm_disable_port(enum fm_port port);
#endif
|
1001-study-uboot
|
include/fm_eth.h
|
C
|
gpl3
| 3,095
|
/*
* tsec.h
*
* Driver for the Motorola Triple Speed Ethernet Controller
*
* This software may be used and distributed according to the
* terms of the GNU Public License, Version 2, incorporated
* herein by reference.
*
* Copyright 2004, 2007, 2009, 2011 Freescale Semiconductor, Inc.
* (C) Copyright 2003, Motorola, Inc.
* maintained by Xianghua Xiao (x.xiao@motorola.com)
* author Andy Fleming
*
*/
#ifndef __TSEC_H
#define __TSEC_H
#include <net.h>
#include <config.h>
#include <phy.h>
#include <asm/fsl_enet.h>
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
#define DEFAULT_MII_NAME "FSL_MDIO"
#define STD_TSEC_INFO(num) \
{ \
.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
+ (num - 1) * TSEC_MDIO_OFFSET), \
.devname = CONFIG_TSEC##num##_NAME, \
.phyaddr = TSEC##num##_PHY_ADDR, \
.flags = TSEC##num##_FLAGS, \
.mii_devname = DEFAULT_MII_NAME \
}
#define SET_STD_TSEC_INFO(x, num) \
{ \
x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
x.miiregs_sgmii = (struct tsec_mii_mng *)(CONFIG_SYS_MDIO_BASE_ADDR \
+ (num - 1) * TSEC_MDIO_OFFSET); \
x.devname = CONFIG_TSEC##num##_NAME; \
x.phyaddr = TSEC##num##_PHY_ADDR; \
x.flags = TSEC##num##_FLAGS;\
x.mii_devname = DEFAULT_MII_NAME;\
}
#define MAC_ADDR_LEN 6
/* #define TSEC_TIMEOUT 1000000 */
#define TSEC_TIMEOUT 1000
#define TOUT_LOOP 1000000
/* TBI register addresses */
#define TBI_CR 0x00
#define TBI_SR 0x01
#define TBI_ANA 0x04
#define TBI_ANLPBPA 0x05
#define TBI_ANEX 0x06
#define TBI_TBICON 0x11
/* TBI MDIO register bit fields*/
#define TBICON_CLK_SELECT 0x0020
#define TBIANA_ASYMMETRIC_PAUSE 0x0100
#define TBIANA_SYMMETRIC_PAUSE 0x0080
#define TBIANA_HALF_DUPLEX 0x0040
#define TBIANA_FULL_DUPLEX 0x0020
#define TBICR_PHY_RESET 0x8000
#define TBICR_ANEG_ENABLE 0x1000
#define TBICR_RESTART_ANEG 0x0200
#define TBICR_FULL_DUPLEX 0x0100
#define TBICR_SPEED1_SET 0x0040
/* MAC register bits */
#define MACCFG1_SOFT_RESET 0x80000000
#define MACCFG1_RESET_RX_MC 0x00080000
#define MACCFG1_RESET_TX_MC 0x00040000
#define MACCFG1_RESET_RX_FUN 0x00020000
#define MACCFG1_RESET_TX_FUN 0x00010000
#define MACCFG1_LOOPBACK 0x00000100
#define MACCFG1_RX_FLOW 0x00000020
#define MACCFG1_TX_FLOW 0x00000010
#define MACCFG1_SYNCD_RX_EN 0x00000008
#define MACCFG1_RX_EN 0x00000004
#define MACCFG1_SYNCD_TX_EN 0x00000002
#define MACCFG1_TX_EN 0x00000001
#define MACCFG2_INIT_SETTINGS 0x00007205
#define MACCFG2_FULL_DUPLEX 0x00000001
#define MACCFG2_IF 0x00000300
#define MACCFG2_GMII 0x00000200
#define MACCFG2_MII 0x00000100
#define ECNTRL_INIT_SETTINGS 0x00001000
#define ECNTRL_TBI_MODE 0x00000020
#define ECNTRL_REDUCED_MODE 0x00000010
#define ECNTRL_R100 0x00000008
#define ECNTRL_REDUCED_MII_MODE 0x00000004
#define ECNTRL_SGMII_MODE 0x00000002
#ifndef CONFIG_SYS_TBIPA_VALUE
#define CONFIG_SYS_TBIPA_VALUE 0x1f
#endif
#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
#define MINFLR_INIT_SETTINGS 0x00000040
#define DMACTRL_INIT_SETTINGS 0x000000c3
#define DMACTRL_GRS 0x00000010
#define DMACTRL_GTS 0x00000008
#define TSTAT_CLEAR_THALT 0x80000000
#define RSTAT_CLEAR_RHALT 0x00800000
#define IEVENT_INIT_CLEAR 0xffffffff
#define IEVENT_BABR 0x80000000
#define IEVENT_RXC 0x40000000
#define IEVENT_BSY 0x20000000
#define IEVENT_EBERR 0x10000000
#define IEVENT_MSRO 0x04000000
#define IEVENT_GTSC 0x02000000
#define IEVENT_BABT 0x01000000
#define IEVENT_TXC 0x00800000
#define IEVENT_TXE 0x00400000
#define IEVENT_TXB 0x00200000
#define IEVENT_TXF 0x00100000
#define IEVENT_IE 0x00080000
#define IEVENT_LC 0x00040000
#define IEVENT_CRL 0x00020000
#define IEVENT_XFUN 0x00010000
#define IEVENT_RXB0 0x00008000
#define IEVENT_GRSC 0x00000100
#define IEVENT_RXF0 0x00000080
#define IMASK_INIT_CLEAR 0x00000000
#define IMASK_TXEEN 0x00400000
#define IMASK_TXBEN 0x00200000
#define IMASK_TXFEN 0x00100000
#define IMASK_RXFEN0 0x00000080
/* Default Attribute fields */
#define ATTR_INIT_SETTINGS 0x000000c0
#define ATTRELI_INIT_SETTINGS 0x00000000
/* TxBD status field bits */
#define TXBD_READY 0x8000
#define TXBD_PADCRC 0x4000
#define TXBD_WRAP 0x2000
#define TXBD_INTERRUPT 0x1000
#define TXBD_LAST 0x0800
#define TXBD_CRC 0x0400
#define TXBD_DEF 0x0200
#define TXBD_HUGEFRAME 0x0080
#define TXBD_LATECOLLISION 0x0080
#define TXBD_RETRYLIMIT 0x0040
#define TXBD_RETRYCOUNTMASK 0x003c
#define TXBD_UNDERRUN 0x0002
#define TXBD_STATS 0x03ff
/* RxBD status field bits */
#define RXBD_EMPTY 0x8000
#define RXBD_RO1 0x4000
#define RXBD_WRAP 0x2000
#define RXBD_INTERRUPT 0x1000
#define RXBD_LAST 0x0800
#define RXBD_FIRST 0x0400
#define RXBD_MISS 0x0100
#define RXBD_BROADCAST 0x0080
#define RXBD_MULTICAST 0x0040
#define RXBD_LARGE 0x0020
#define RXBD_NONOCTET 0x0010
#define RXBD_SHORT 0x0008
#define RXBD_CRCERR 0x0004
#define RXBD_OVERRUN 0x0002
#define RXBD_TRUNCATED 0x0001
#define RXBD_STATS 0x003f
typedef struct txbd8
{
ushort status; /* Status Fields */
ushort length; /* Buffer length */
uint bufPtr; /* Buffer Pointer */
} txbd8_t;
typedef struct rxbd8
{
ushort status; /* Status Fields */
ushort length; /* Buffer Length */
uint bufPtr; /* Buffer Pointer */
} rxbd8_t;
typedef struct rmon_mib
{
/* Transmit and Receive Counters */
uint tr64; /* Transmit and Receive 64-byte Frame Counter */
uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
/* Receive Counters */
uint rbyt; /* Receive Byte Counter */
uint rpkt; /* Receive Packet Counter */
uint rfcs; /* Receive FCS Error Counter */
uint rmca; /* Receive Multicast Packet (Counter) */
uint rbca; /* Receive Broadcast Packet */
uint rxcf; /* Receive Control Frame Packet */
uint rxpf; /* Receive Pause Frame Packet */
uint rxuo; /* Receive Unknown OP Code */
uint raln; /* Receive Alignment Error */
uint rflr; /* Receive Frame Length Error */
uint rcde; /* Receive Code Error */
uint rcse; /* Receive Carrier Sense Error */
uint rund; /* Receive Undersize Packet */
uint rovr; /* Receive Oversize Packet */
uint rfrg; /* Receive Fragments */
uint rjbr; /* Receive Jabber */
uint rdrp; /* Receive Drop */
/* Transmit Counters */
uint tbyt; /* Transmit Byte Counter */
uint tpkt; /* Transmit Packet */
uint tmca; /* Transmit Multicast Packet */
uint tbca; /* Transmit Broadcast Packet */
uint txpf; /* Transmit Pause Control Frame */
uint tdfr; /* Transmit Deferral Packet */
uint tedf; /* Transmit Excessive Deferral Packet */
uint tscl; /* Transmit Single Collision Packet */
/* (0x2_n700) */
uint tmcl; /* Transmit Multiple Collision Packet */
uint tlcl; /* Transmit Late Collision Packet */
uint txcl; /* Transmit Excessive Collision Packet */
uint tncl; /* Transmit Total Collision */
uint res2;
uint tdrp; /* Transmit Drop Frame */
uint tjbr; /* Transmit Jabber Frame */
uint tfcs; /* Transmit FCS Error */
uint txcf; /* Transmit Control Frame */
uint tovr; /* Transmit Oversize Frame */
uint tund; /* Transmit Undersize Frame */
uint tfrg; /* Transmit Fragments Frame */
/* General Registers */
uint car1; /* Carry Register One */
uint car2; /* Carry Register Two */
uint cam1; /* Carry Register One Mask */
uint cam2; /* Carry Register Two Mask */
} rmon_mib_t;
typedef struct tsec_hash_regs
{
uint iaddr0; /* Individual Address Register 0 */
uint iaddr1; /* Individual Address Register 1 */
uint iaddr2; /* Individual Address Register 2 */
uint iaddr3; /* Individual Address Register 3 */
uint iaddr4; /* Individual Address Register 4 */
uint iaddr5; /* Individual Address Register 5 */
uint iaddr6; /* Individual Address Register 6 */
uint iaddr7; /* Individual Address Register 7 */
uint res1[24];
uint gaddr0; /* Group Address Register 0 */
uint gaddr1; /* Group Address Register 1 */
uint gaddr2; /* Group Address Register 2 */
uint gaddr3; /* Group Address Register 3 */
uint gaddr4; /* Group Address Register 4 */
uint gaddr5; /* Group Address Register 5 */
uint gaddr6; /* Group Address Register 6 */
uint gaddr7; /* Group Address Register 7 */
uint res2[24];
} tsec_hash_t;
typedef struct tsec
{
/* General Control and Status Registers (0x2_n000) */
uint res000[4];
uint ievent; /* Interrupt Event */
uint imask; /* Interrupt Mask */
uint edis; /* Error Disabled */
uint res01c;
uint ecntrl; /* Ethernet Control */
uint minflr; /* Minimum Frame Length */
uint ptv; /* Pause Time Value */
uint dmactrl; /* DMA Control */
uint tbipa; /* TBI PHY Address */
uint res034[3];
uint res040[48];
/* Transmit Control and Status Registers (0x2_n100) */
uint tctrl; /* Transmit Control */
uint tstat; /* Transmit Status */
uint res108;
uint tbdlen; /* Tx BD Data Length */
uint res110[5];
uint ctbptr; /* Current TxBD Pointer */
uint res128[23];
uint tbptr; /* TxBD Pointer */
uint res188[30];
/* (0x2_n200) */
uint res200;
uint tbase; /* TxBD Base Address */
uint res208[42];
uint ostbd; /* Out of Sequence TxBD */
uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
uint res2b8[18];
/* Receive Control and Status Registers (0x2_n300) */
uint rctrl; /* Receive Control */
uint rstat; /* Receive Status */
uint res308;
uint rbdlen; /* RxBD Data Length */
uint res310[4];
uint res320;
uint crbptr; /* Current Receive Buffer Pointer */
uint res328[6];
uint mrblr; /* Maximum Receive Buffer Length */
uint res344[16];
uint rbptr; /* RxBD Pointer */
uint res388[30];
/* (0x2_n400) */
uint res400;
uint rbase; /* RxBD Base Address */
uint res408[62];
/* MAC Registers (0x2_n500) */
uint maccfg1; /* MAC Configuration #1 */
uint maccfg2; /* MAC Configuration #2 */
uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
uint hafdup; /* Half-duplex */
uint maxfrm; /* Maximum Frame */
uint res514;
uint res518;
uint res51c;
uint resmdio[6];
uint res538;
uint ifstat; /* Interface Status */
uint macstnaddr1; /* Station Address, part 1 */
uint macstnaddr2; /* Station Address, part 2 */
uint res548[46];
/* (0x2_n600) */
uint res600[32];
/* RMON MIB Registers (0x2_n680-0x2_n73c) */
rmon_mib_t rmon;
uint res740[48];
/* Hash Function Registers (0x2_n800) */
tsec_hash_t hash;
uint res900[128];
/* Pattern Registers (0x2_nb00) */
uint resb00[62];
uint attr; /* Default Attribute Register */
uint attreli; /* Default Attribute Extract Length and Index */
/* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
uint resc00[256];
} tsec_t;
#define TSEC_GIGABIT (1 << 0)
/* These flags currently only have meaning if we're using the eTSEC */
#define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */
#define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */
struct tsec_private {
tsec_t *regs;
struct tsec_mii_mng *phyregs_sgmii;
struct phy_device *phydev;
phy_interface_t interface;
struct mii_dev *bus;
uint phyaddr;
char mii_devname[16];
u32 flags;
};
struct tsec_info_struct {
tsec_t *regs;
struct tsec_mii_mng *miiregs_sgmii;
char *devname;
char *mii_devname;
phy_interface_t interface;
unsigned int phyaddr;
u32 flags;
};
int tsec_standard_init(bd_t *bis);
int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num);
#endif /* __TSEC_H */
|
1001-study-uboot
|
include/tsec.h
|
C
|
gpl3
| 11,801
|
/* Memory.h - Memory mappings and remapping functions declarations */
/* Copyright - Galileo technology. */
#ifndef __INCmemoryh
#define __INCmemoryh
/* includes */
#include "core.h"
/* defines */
#define DONT_MODIFY 0xffffffff
#define PARITY_SUPPORT 0x40000000
#define _8BIT 0x00000000
#define _16BIT 0x00100000
#define _32BIT 0x00200000
#define _64BIT 0x00300000
/* typedefs */
typedef struct deviceParam
{ /* boundary values */
unsigned int turnOff; /* 0x0 - 0xf */
unsigned int acc2First; /* 0x0 - 0x1f */
unsigned int acc2Next; /* 0x0 - 0x1f */
unsigned int ale2Wr; /* 0x0 - 0xf */
unsigned int wrLow; /* 0x0 - 0xf */
unsigned int wrHigh; /* 0x0 - 0xf */
unsigned int deviceWidth; /* in Bytes */
} DEVICE_PARAM;
typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
MEM_REGION3,MEM_REGION4,MEM_REGION5, \
MEM_REGION6,MEM_REGION7} \
MEMORY_PROTECT_REGION;
typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
MEMORY_ACCESS;
typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
MEMORY_ACCESS_WRITE;
typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
MEMORY_CACHE_PROTECT;
typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
MEMORY_SNOOP_TYPE;
typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
MEMORY_SNOOP_REGION;
/* functions */
unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
unsigned int memoryGetDeviceBaseAddress(DEVICE device);
unsigned int memoryGetBankSize(MEMORY_BANK bank);
unsigned int memoryGetDeviceSize(DEVICE device);
unsigned int memoryGetDeviceWidth(DEVICE device);
/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
/* Change the Internal Register Base Address to a new given Address. */
bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
/* returns internal Register Space Base Address. */
unsigned int memoryGetInternalRegistersSpace(void);
/* Configurate the protection feature to a given space. */
bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
MEMORY_ACCESS memoryAccess,
MEMORY_ACCESS_WRITE memoryWrite,
MEMORY_CACHE_PROTECT cacheProtection,
unsigned int baseAddress,
unsigned int regionLength);
/* Configurate the snoop feature to a given space. */
bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
MEMORY_SNOOP_TYPE snoopType,
unsigned int baseAddress,
unsigned int regionLength);
bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
#endif /* __INCmemoryh */
|
1001-study-uboot
|
include/galileo/memory.h
|
C
|
gpl3
| 3,406
|
/* PCI.h - PCI functions header file */
/* Copyright - Galileo technology. */
#ifndef __INCpcih
#define __INCpcih
/* includes */
#include "core.h"
#include "memory.h"
/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
#define PCI_MAX_DEVICES 22
/* Macros */
#define SELF 32
/* Defines for the access regions. */
#define PREFETCH_ENABLE BIT12
#define PREFETCH_DISABLE NO_BIT
#define DELAYED_READ_ENABLE BIT13
/* #define CACHING_ENABLE BIT14 */
/* aggressive prefetch: PCI slave prefetch two burst in advance*/
#define AGGRESSIVE_PREFETCH BIT16
/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
#define READ_LINE_AGGRESSIVE_PREFETCH BIT17
/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
#define READ_MULTI_AGGRESSIVE_PREFETCH BIT18
#define MAX_BURST_4 NO_BIT
#define MAX_BURST_8 BIT20 /* Bits[21:20] = 01 */
#define MAX_BURST_16 BIT21 /* Bits[21:20] = 10 */
#define PCI_BYTE_SWAP NO_BIT /* Bits[25:24] = 00 */
#define PCI_NO_SWAP BIT24 /* Bits[25:24] = 01 */
#define PCI_BYTE_AND_WORD_SWAP BIT25 /* Bits[25:24] = 10 */
#define PCI_WORD_SWAP (BIT24 | BIT25) /* Bits[25:24] = 11 */
#define PCI_ACCESS_PROTECT BIT28
#define PCI_WRITE_PROTECT BIT29
/* typedefs */
typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
REGION6,REGION7} PCI_ACCESS_REGIONS;
typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
PCI_SNOOP_TYPE;
typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
PCI_SNOOP_REGION;
typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
PCI_REGION2,PCI_REGION3,
PCI_IO}
PCI_REGION;
/* read/write configuration registers on local PCI bus. */
void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum, unsigned int data);
unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
unsigned int pciDevNum);
/* read/write configuration registers on another PCI bus. */
void pciOverBridgeWriteConfigReg(PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum,unsigned int data);
unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
unsigned int regOffset,
unsigned int pciDevNum,
unsigned int busNum);
/* Master`s memory space */
bool pciMapSpace(PCI_HOST host, PCI_REGION region,
unsigned int remapBase,
unsigned int deviceBase,
unsigned int deviceLength);
unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
/* Slave`s memory space */
void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
/* PCI region options */
bool pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
unsigned int features, unsigned int baseAddress,
unsigned int regionLength);
void pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
/* PCI arbiter */
bool pciArbiterEnable(PCI_HOST host);
bool pciArbiterDisable(PCI_HOST host);
bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
PCI_AGENT_PARK externalAgent0,
PCI_AGENT_PARK externalAgent1,
PCI_AGENT_PARK externalAgent2,
PCI_AGENT_PARK externalAgent3,
PCI_AGENT_PARK externalAgent4,
PCI_AGENT_PARK externalAgent5);
bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
PCI_SNOOP_TYPE snoopType,
unsigned int baseAddress,
unsigned int regionLength);
#endif /* __INCpcih */
|
1001-study-uboot
|
include/galileo/pci.h
|
C
|
gpl3
| 4,131
|
/* gt64260R.h - GT64260 Internal registers definition file */
/* Copyright - Galileo technology. */
#ifndef __INCgt64260rh
#define __INCgt64260rh
#ifndef GT64260
#define GT64260
#endif
/* CPU MASTER CONTROL REGISTER */
#define CPU_CONFIGURATION 0x0
#define CPU_MASTER_CONTROL 0x160
/****************************************/
/* Processor Address Space */
/****************************************/
/* Sdram's BAR'S */
#define SCS_0_LOW_DECODE_ADDRESS 0x008
#define SCS_0_HIGH_DECODE_ADDRESS 0x010
#define SCS_1_LOW_DECODE_ADDRESS 0x208
#define SCS_1_HIGH_DECODE_ADDRESS 0x210
#define SCS_2_LOW_DECODE_ADDRESS 0x018
#define SCS_2_HIGH_DECODE_ADDRESS 0x020
#define SCS_3_LOW_DECODE_ADDRESS 0x218
#define SCS_3_HIGH_DECODE_ADDRESS 0x220
/* Devices BAR'S */
#define CS_0_LOW_DECODE_ADDRESS 0x028
#define CS_0_HIGH_DECODE_ADDRESS 0x030
#define CS_1_LOW_DECODE_ADDRESS 0x228
#define CS_1_HIGH_DECODE_ADDRESS 0x230
#define CS_2_LOW_DECODE_ADDRESS 0x248
#define CS_2_HIGH_DECODE_ADDRESS 0x250
#define CS_3_LOW_DECODE_ADDRESS 0x038
#define CS_3_HIGH_DECODE_ADDRESS 0x040
#define BOOTCS_LOW_DECODE_ADDRESS 0x238
#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
#define INTERNAL_SPACE_DECODE 0x068
#define CPU_0_LOW_DECODE_ADDRESS 0x290
#define CPU_0_HIGH_DECODE_ADDRESS 0x298
#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
#define PCI_0I_O_ADDRESS_REMAP 0x0f0
#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
#define PCI_1I_O_ADDRESS_REMAP 0x108
#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
/****************************************/
/* CPU Sync Barrier */
/****************************************/
#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
/****************************************/
/* CPU Access Protect */
/****************************************/
#define CPU_LOW_PROTECT_ADDRESS_0 0x180
#define CPU_HIGH_PROTECT_ADDRESS_0 0x188
#define CPU_LOW_PROTECT_ADDRESS_1 0x190
#define CPU_HIGH_PROTECT_ADDRESS_1 0x198
#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0
#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8
#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0
#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8
#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0
#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8
#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0
#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8
#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0
#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8
#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0
#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8
/****************************************/
/* Snoop Control */
/****************************************/
#define SNOOP_BASE_ADDRESS_0 0x380
#define SNOOP_TOP_ADDRESS_0 0x388
#define SNOOP_BASE_ADDRESS_1 0x390
#define SNOOP_TOP_ADDRESS_1 0x398
#define SNOOP_BASE_ADDRESS_2 0x3a0
#define SNOOP_TOP_ADDRESS_2 0x3a8
#define SNOOP_BASE_ADDRESS_3 0x3b0
#define SNOOP_TOP_ADDRESS_3 0x3b8
/****************************************/
/* CPU Error Report */
/****************************************/
#define CPU_ERROR_ADDRESS_LOW 0x070
#define CPU_ERROR_ADDRESS_HIGH 0x078
#define CPU_ERROR_DATA_LOW 0x128
#define CPU_ERROR_DATA_HIGH 0x130
#define CPU_ERROR_PARITY 0x138
#define CPU_ERROR_CAUSE 0x140
#define CPU_ERROR_MASK 0x148
/****************************************/
/* Pslave Debug */
/****************************************/
#define X_0_ADDRESS 0x360
#define X_0_COMMAND_ID 0x368
#define X_1_ADDRESS 0x370
#define X_1_COMMAND_ID 0x378
#define WRITE_DATA_LOW 0x3c0
#define WRITE_DATA_HIGH 0x3c8
#define WRITE_BYTE_ENABLE 0x3e0
#define READ_DATA_LOW 0x3d0
#define READ_DATA_HIGH 0x3d8
#define READ_ID 0x3e8
/****************************************/
/* SDRAM and Device Address Space */
/****************************************/
/****************************************/
/* SDRAM Configuration */
/****************************************/
#define SDRAM_CONFIGURATION 0x448
#define SDRAM_OPERATION_MODE 0x474
#define SDRAM_ADDRESS_DECODE 0x47c
#define SDRAM_UMA_CONTROL 0x4a4
#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8
#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac
#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0
#define SDRAM_TIMING 0x4b4
/****************************************/
/* SDRAM Parameters */
/****************************************/
#define SDRAM_BANK0PARAMETERS 0x44C
#define SDRAM_BANK1PARAMETERS 0x450
#define SDRAM_BANK2PARAMETERS 0x454
#define SDRAM_BANK3PARAMETERS 0x458
/****************************************/
/* SDRAM Error Report */
/****************************************/
#define SDRAM_ERROR_DATA_LOW 0x484
#define SDRAM_ERROR_DATA_HIGH 0x480
#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
#define SDRAM_RECEIVED_ECC 0x488
#define SDRAM_CALCULATED_ECC 0x48c
#define SDRAM_ECC_CONTROL 0x494
#define SDRAM_ECC_ERROR_COUNTER 0x498
/****************************************/
/* SDunit Debug (for internal use) */
/****************************************/
#define X0_ADDRESS 0x500
#define X0_COMMAND_AND_ID 0x504
#define X0_WRITE_DATA_LOW 0x508
#define X0_WRITE_DATA_HIGH 0x50c
#define X0_WRITE_BYTE_ENABLE 0x518
#define X0_READ_DATA_LOW 0x510
#define X0_READ_DATA_HIGH 0x514
#define X0_READ_ID 0x51c
#define X1_ADDRESS 0x520
#define X1_COMMAND_AND_ID 0x524
#define X1_WRITE_DATA_LOW 0x528
#define X1_WRITE_DATA_HIGH 0x52c
#define X1_WRITE_BYTE_ENABLE 0x538
#define X1_READ_DATA_LOW 0x530
#define X1_READ_DATA_HIGH 0x534
#define X1_READ_ID 0x53c
#define X0_SNOOP_ADDRESS 0x540
#define X0_SNOOP_COMMAND 0x544
#define X1_SNOOP_ADDRESS 0x548
#define X1_SNOOP_COMMAND 0x54c
/****************************************/
/* Device Parameters */
/****************************************/
#define DEVICE_BANK0PARAMETERS 0x45c
#define DEVICE_BANK1PARAMETERS 0x460
#define DEVICE_BANK2PARAMETERS 0x464
#define DEVICE_BANK3PARAMETERS 0x468
#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
#define DEVICE_CONTROL 0x4c0
#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
/****************************************/
/* Device Interrupt */
/****************************************/
#define DEVICE_INTERRUPT_CAUSE 0x4d0
#define DEVICE_INTERRUPT_MASK 0x4d4
#define DEVICE_ERROR_ADDRESS 0x4d8
/****************************************/
/* DMA Record */
/****************************************/
#define CHANNEL0_DMA_BYTE_COUNT 0x800
#define CHANNEL1_DMA_BYTE_COUNT 0x804
#define CHANNEL2_DMA_BYTE_COUNT 0x808
#define CHANNEL3_DMA_BYTE_COUNT 0x80C
#define CHANNEL4_DMA_BYTE_COUNT 0x900
#define CHANNEL5_DMA_BYTE_COUNT 0x904
#define CHANNEL6_DMA_BYTE_COUNT 0x908
#define CHANNEL7_DMA_BYTE_COUNT 0x90C
#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
#define CHANNEL0NEXT_RECORD_POINTER 0x830
#define CHANNEL1NEXT_RECORD_POINTER 0x834
#define CHANNEL2NEXT_RECORD_POINTER 0x838
#define CHANNEL3NEXT_RECORD_POINTER 0x83C
#define CHANNEL4NEXT_RECORD_POINTER 0x930
#define CHANNEL5NEXT_RECORD_POINTER 0x934
#define CHANNEL6NEXT_RECORD_POINTER 0x938
#define CHANNEL7NEXT_RECORD_POINTER 0x93C
#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
/****************************************/
/* DMA Channel Control */
/****************************************/
#define CHANNEL0CONTROL 0x840
#define CHANNEL0CONTROL_HIGH 0x880
#define CHANNEL1CONTROL 0x844
#define CHANNEL1CONTROL_HIGH 0x884
#define CHANNEL2CONTROL 0x848
#define CHANNEL2CONTROL_HIGH 0x888
#define CHANNEL3CONTROL 0x84C
#define CHANNEL3CONTROL_HIGH 0x88C
#define CHANNEL4CONTROL 0x940
#define CHANNEL4CONTROL_HIGH 0x980
#define CHANNEL5CONTROL 0x944
#define CHANNEL5CONTROL_HIGH 0x984
#define CHANNEL6CONTROL 0x948
#define CHANNEL6CONTROL_HIGH 0x988
#define CHANNEL7CONTROL 0x94C
#define CHANNEL7CONTROL_HIGH 0x98C
/****************************************/
/* DMA Arbiter */
/****************************************/
#define ARBITER_CONTROL_0_3 0x860
#define ARBITER_CONTROL_4_7 0x960
/****************************************/
/* DMA Interrupt */
/****************************************/
#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
#define CHANELS0_3_INTERRUPT_MASK 0x8c4
#define CHANELS0_3_ERROR_ADDRESS 0x8c8
#define CHANELS0_3_ERROR_SELECT 0x8cc
#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
#define CHANELS4_7_INTERRUPT_MASK 0x9c4
#define CHANELS4_7_ERROR_ADDRESS 0x9c8
#define CHANELS4_7_ERROR_SELECT 0x9cc
/****************************************/
/* DMA Debug (for internal use) */
/****************************************/
#define DMA_X0_ADDRESS 0x8e0
#define DMA_X0_COMMAND_AND_ID 0x8e4
#define DMA_X0_WRITE_DATA_LOW 0x8e8
#define DMA_X0_WRITE_DATA_HIGH 0x8ec
#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
#define DMA_X0_READ_DATA_LOW 0x8f0
#define DMA_X0_READ_DATA_HIGH 0x8f4
#define DMA_X0_READ_ID 0x8fc
#define DMA_X1_ADDRESS 0x9e0
#define DMA_X1_COMMAND_AND_ID 0x9e4
#define DMA_X1_WRITE_DATA_LOW 0x9e8
#define DMA_X1_WRITE_DATA_HIGH 0x9ec
#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
#define DMA_X1_READ_DATA_LOW 0x9f0
#define DMA_X1_READ_DATA_HIGH 0x9f4
#define DMA_X1_READ_ID 0x9fc
/****************************************/
/* Timer_Counter */
/****************************************/
#define TIMER_COUNTER0 0x850
#define TIMER_COUNTER1 0x854
#define TIMER_COUNTER2 0x858
#define TIMER_COUNTER3 0x85C
#define TIMER_COUNTER_0_3_CONTROL 0x864
#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
#define TIMER_COUNTER4 0x950
#define TIMER_COUNTER5 0x954
#define TIMER_COUNTER6 0x958
#define TIMER_COUNTER7 0x95C
#define TIMER_COUNTER_4_7_CONTROL 0x964
#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
/****************************************/
/* PCI Slave Address Decoding */
/****************************************/
#define PCI_0SCS_0_BANK_SIZE 0xc08
#define PCI_1SCS_0_BANK_SIZE 0xc88
#define PCI_0SCS_1_BANK_SIZE 0xd08
#define PCI_1SCS_1_BANK_SIZE 0xd88
#define PCI_0SCS_2_BANK_SIZE 0xc0c
#define PCI_1SCS_2_BANK_SIZE 0xc8c
#define PCI_0SCS_3_BANK_SIZE 0xd0c
#define PCI_1SCS_3_BANK_SIZE 0xd8c
#define PCI_0CS_0_BANK_SIZE 0xc10
#define PCI_1CS_0_BANK_SIZE 0xc90
#define PCI_0CS_1_BANK_SIZE 0xd10
#define PCI_1CS_1_BANK_SIZE 0xd90
#define PCI_0CS_2_BANK_SIZE 0xd18
#define PCI_1CS_2_BANK_SIZE 0xd98
#define PCI_0CS_3_BANK_SIZE 0xc14
#define PCI_1CS_3_BANK_SIZE 0xc94
#define PCI_0CS_BOOT_BANK_SIZE 0xd14
#define PCI_1CS_BOOT_BANK_SIZE 0xd94
#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
#define PCI_0P2P_I_O_BAR_SIZE 0xd24
#define PCI_1P2P_I_O_BAR_SIZE 0xda4
#define PCI_0CPU_BAR_SIZE 0xd28
#define PCI_1CPU_BAR_SIZE 0xda8
#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
#define PCI_1DAC_CPU_BAR_SIZE 0xeac
#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
/****************************************/
/* PCI Control */
/****************************************/
#define PCI_0COMMAND 0xc00
#define PCI_1COMMAND 0xc80
#define PCI_0MODE 0xd00
#define PCI_1MODE 0xd80
#define PCI_0TIMEOUT_RETRY 0xc04
#define PCI_1TIMEOUT_RETRY 0xc84
#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
#define MSI_0TRIGGER_TIMER 0xc38
#define MSI_1TRIGGER_TIMER 0xcb8
#define PCI_0ARBITER_CONTROL 0x1d00
#define PCI_1ARBITER_CONTROL 0x1d80
/* changing untill here */
#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
#define PCI_0P2P_CONFIGURATION 0x1d14
#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10
#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20
#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30
#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40
#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50
#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60
#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70
#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
#define PCI_1P2P_CONFIGURATION 0x1d94
#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90
#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0
#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0
#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0
#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0
#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0
#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0
#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
/****************************************/
/* PCI Snoop Control */
/****************************************/
#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
/****************************************/
/* PCI Configuration Address */
/****************************************/
#define PCI_0CONFIGURATION_ADDRESS 0xcf8
#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
#define PCI_1CONFIGURATION_ADDRESS 0xc78
#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
/****************************************/
/* PCI Error Report */
/****************************************/
#define PCI_0SERR_MASK 0xc28
#define PCI_0ERROR_ADDRESS_LOW 0x1d40
#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
#define PCI_0ERROR_DATA_LOW 0x1d48
#define PCI_0ERROR_DATA_HIGH 0x1d4c
#define PCI_0ERROR_COMMAND 0x1d50
#define PCI_0ERROR_CAUSE 0x1d58
#define PCI_0ERROR_MASK 0x1d5c
#define PCI_1SERR_MASK 0xca8
#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
#define PCI_1ERROR_DATA_LOW 0x1dc8
#define PCI_1ERROR_DATA_HIGH 0x1dcc
#define PCI_1ERROR_COMMAND 0x1dd0
#define PCI_1ERROR_CAUSE 0x1dd8
#define PCI_1ERROR_MASK 0x1ddc
/****************************************/
/* Lslave Debug (for internal use) */
/****************************************/
#define L_SLAVE_X0_ADDRESS 0x1d20
#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
#define L_SLAVE_X1_ADDRESS 0x1d28
#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
#define L_SLAVE_WRITE_DATA_LOW 0x1d30
#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
#define L_SLAVE_READ_DATA_LOW 0x1d38
#define L_SLAVE_READ_DATA_HIGH 0x1d3c
#define L_SLAVE_READ_ID 0x1d64
/****************************************/
/* PCI Configuration Function 0 */
/****************************************/
#define PCI_DEVICE_AND_VENDOR_ID 0x000
#define PCI_STATUS_AND_COMMAND 0x004
#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
#define PCI_SCS_0_BASE_ADDRESS 0x010
#define PCI_SCS_1_BASE_ADDRESS 0x014
#define PCI_SCS_2_BASE_ADDRESS 0x018
#define PCI_SCS_3_BASE_ADDRESS 0x01C
#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
#define PCI_CAPABILTY_LIST_POINTER 0x034
#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
#define PCI_VPD_ADDRESS 0x048
#define PCI_VPD_DATA 0x04c
#define PCI_MSI_MESSAGE_CONTROL 0x050
#define PCI_MSI_MESSAGE_ADDRESS 0x054
#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
#define PCI_MSI_MESSAGE_DATA 0x05c
#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
/****************************************/
/* PCI Configuration Function 1 */
/****************************************/
#define PCI_CS_0_BASE_ADDRESS 0x110
#define PCI_CS_1_BASE_ADDRESS 0x114
#define PCI_CS_2_BASE_ADDRESS 0x118
#define PCI_CS_3_BASE_ADDRESS 0x11c
#define PCI_BOOTCS_BASE_ADDRESS 0x120
/****************************************/
/* PCI Configuration Function 2 */
/****************************************/
#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
#define PCI_P2P_MEM1_BASE_ADDRESS 0x214
#define PCI_P2P_I_O_BASE_ADDRESS 0x218
#define PCI_CPU_BASE_ADDRESS 0x21c
/****************************************/
/* PCI Configuration Function 4 */
/****************************************/
#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
/****************************************/
/* PCI Configuration Function 5 */
/****************************************/
#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
/****************************************/
/* PCI Configuration Function 6 */
/****************************************/
#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
/****************************************/
/* PCI Configuration Function 7 */
/****************************************/
#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
/****************************************/
/* Interrupts */
/****************************************/
#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
#define CPU_SELECT_CAUSE_REGISTER 0xc70
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
#define PCI_0SELECT_CAUSE 0xc74
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
#define PCI_1SELECT_CAUSE 0xcf4
#define CPU_INT_0_MASK 0xe60
#define CPU_INT_1_MASK 0xe64
#define CPU_INT_2_MASK 0xe68
#define CPU_INT_3_MASK 0xe6c
/****************************************/
/* I20 Support registers */
/****************************************/
#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C
/****************************************/
/* Communication Unit Registers */
/****************************************/
#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200
#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0
#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4
#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
#define SERIAL_INIT_LAST_DATA 0xf324
#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
#define COMM_UNIT_ARBITER_CONTROL 0xf300
#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
#define COMM_UNIT_INTERRUPT_MASK 0xf314
#define COMM_UNIT_ERROR_ADDRESS 0xf314
/****************************************/
/* Cunit Debug (for internal use) */
/****************************************/
#define CUNIT_ADDRESS 0xf340
#define CUNIT_COMMAND_AND_ID 0xf344
#define CUNIT_WRITE_DATA_LOW 0xf348
#define CUNIT_WRITE_DATA_HIGH 0xf34c
#define CUNIT_WRITE_BYTE_ENABLE 0xf358
#define CUNIT_READ_DATA_LOW 0xf350
#define CUNIT_READ_DATA_HIGH 0xf354
#define CUNIT_READ_ID 0xf35c
/****************************************/
/* Fast Ethernet Unit Registers */
/****************************************/
/* Ethernet */
#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
#define ETHERNET_SMI_REGISTER 0x2010
/* Ethernet 0 */
#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
#define ETHERNET0_MIB_COUNTER_BASE 0x2500
/* Ethernet 1 */
#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
#define ETHERNET1_MIB_COUNTER_BASE 0x2900
/* Ethernet 2 */
#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
/****************************************/
/* SDMA Registers */
/****************************************/
#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
#define CHANNEL0_COMMAND_REGISTER 0x4008
#define CHANNEL0_RX_CMD_STATUS 0x4800
#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
#define CHANNEL0_RX_BUFFER_POINTER 0x4808
#define CHANNEL0_RX_NEXT_POINTER 0x480c
#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
#define CHANNEL0_TX_CMD_STATUS 0x4C00
#define CHANNEL0_TX_PACKET_SIZE 0x4C04
#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
#define CHANNEL1_CONFIGURATION_REGISTER 0x5000
#define CHANNEL1_COMMAND_REGISTER 0x5008
#define CHANNEL1_RX_CMD_STATUS 0x5800
#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804
#define CHANNEL1_RX_BUFFER_POINTER 0x5808
#define CHANNEL1_RX_NEXT_POINTER 0x580c
#define CHANNEL1_TX_CMD_STATUS 0x5C00
#define CHANNEL1_TX_PACKET_SIZE 0x5C04
#define CHANNEL1_TX_BUFFER_POINTER 0x5C08
#define CHANNEL1_TX_NEXT_POINTER 0x5C0c
#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810
#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10
#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14
#define CHANNEL2_CONFIGURATION_REGISTER 0x6000
#define CHANNEL2_COMMAND_REGISTER 0x6008
#define CHANNEL2_RX_CMD_STATUS 0x6800
#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804
#define CHANNEL2_RX_BUFFER_POINTER 0x6808
#define CHANNEL2_RX_NEXT_POINTER 0x680c
#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
#define CHANNEL2_TX_CMD_STATUS 0x6C00
#define CHANNEL2_TX_PACKET_SIZE 0x6C04
#define CHANNEL2_TX_BUFFER_POINTER 0x6C08
#define CHANNEL2_TX_NEXT_POINTER 0x6C0c
#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
/* SDMA Interrupt */
#define SDMA_CAUSE 0xb820
#define SDMA_MASK 0xb8a0
/****************************************/
/* Baude Rate Generators Registers */
/****************************************/
/* BRG 0 */
#define BRG0_CONFIGURATION_REGISTER 0xb200
#define BRG0_BAUDE_TUNING_REGISTER 0xb204
/* BRG 1 */
#define BRG1_CONFIGURATION_REGISTER 0xb208
#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
/* BRG 2 */
#define BRG2_CONFIGURATION_REGISTER 0xb210
#define BRG2_BAUDE_TUNING_REGISTER 0xb214
/* BRG Interrupts */
#define BRG_CAUSE_REGISTER 0xb834
#define BRG_MASK_REGISTER 0xb8b4
/* MISC */
#define MAIN_ROUTING_REGISTER 0xb400
#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
#define WATCHDOG_VALUE_REGISTER 0xb414
/****************************************/
/* Flex TDM Registers */
/****************************************/
/* FTDM Port */
#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
/* FTDM Interrupts */
#define FTDM_CAUSE_REGISTER 0xb830
#define FTDM_MASK_REGISTER 0xb8b0
/****************************************/
/* GPP Interface Registers */
/****************************************/
#define GPP_IO_CONTROL 0xf100
#define GPP_LEVEL_CONTROL 0xf110
#define GPP_VALUE 0xf104
#define GPP_INTERRUPT_CAUSE 0xf108
#define GPP_INTERRUPT_MASK 0xf10c
#define MPP_CONTROL0 0xf000
#define MPP_CONTROL1 0xf004
#define MPP_CONTROL2 0xf008
#define MPP_CONTROL3 0xf00c
#define DEBUG_PORT_MULTIPLEX 0xf014
#define SERIAL_PORT_MULTIPLEX 0xf010
/****************************************/
/* I2C Registers */
/****************************************/
#define I2C_SLAVE_ADDRESS 0xc000
#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
#define I2C_DATA 0xc004
#define I2C_CONTROL 0xc008
#define I2C_STATUS_BAUDE_RATE 0xc00C
#define I2C_SOFT_RESET 0xc01c
/****************************************/
/* MPSC Registers */
/****************************************/
/* MPSC0 */
#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
#define CHANNEL0_REGISTER1 0x800c
#define CHANNEL0_REGISTER2 0x8010
#define CHANNEL0_REGISTER3 0x8014
#define CHANNEL0_REGISTER4 0x8018
#define CHANNEL0_REGISTER5 0x801c
#define CHANNEL0_REGISTER6 0x8020
#define CHANNEL0_REGISTER7 0x8024
#define CHANNEL0_REGISTER8 0x8028
#define CHANNEL0_REGISTER9 0x802c
#define CHANNEL0_REGISTER10 0x8030
#define CHANNEL0_REGISTER11 0x8034
/* MPSC1 */
#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840
#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844
#define MPSC1_PROTOCOL_CONFIGURATION 0x8848
#define CHANNEL1_REGISTER1 0x884c
#define CHANNEL1_REGISTER2 0x8850
#define CHANNEL1_REGISTER3 0x8854
#define CHANNEL1_REGISTER4 0x8858
#define CHANNEL1_REGISTER5 0x885c
#define CHANNEL1_REGISTER6 0x8860
#define CHANNEL1_REGISTER7 0x8864
#define CHANNEL1_REGISTER8 0x8868
#define CHANNEL1_REGISTER9 0x886c
#define CHANNEL1_REGISTER10 0x8870
#define CHANNEL1_REGISTER11 0x8874
/* MPSC2 */
#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040
#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044
#define MPSC2_PROTOCOL_CONFIGURATION 0x9048
#define CHANNEL2_REGISTER1 0x904c
#define CHANNEL2_REGISTER2 0x9050
#define CHANNEL2_REGISTER3 0x9054
#define CHANNEL2_REGISTER4 0x9058
#define CHANNEL2_REGISTER5 0x905c
#define CHANNEL2_REGISTER6 0x9060
#define CHANNEL2_REGISTER7 0x9064
#define CHANNEL2_REGISTER8 0x9068
#define CHANNEL2_REGISTER9 0x906c
#define CHANNEL2_REGISTER10 0x9070
#define CHANNEL2_REGISTER11 0x9074
/* MPSCs Interrupts */
#define MPSC0_CAUSE 0xb824
#define MPSC0_MASK 0xb8a4
#define MPSC1_CAUSE 0xb828
#define MPSC1_MASK 0xb8a8
#define MPSC2_CAUSE 0xb82c
#define MPSC2_MASK 0xb8ac
#endif /* __INCgt64260rh */
|
1001-study-uboot
|
include/galileo/gt64260R.h
|
C
|
gpl3
| 45,683
|
/* Core.h - Basic core logic functions and definitions */
/* Copyright Galileo Technology. */
/*
DESCRIPTION
This header file contains simple read/write macros for addressing
the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
space). The macros take care of Big/Little endian conversions.
*/
#ifndef __INCcoreh
#define __INCcoreh
/* includes */
#include "gt64260R.h"
extern unsigned int INTERNAL_REG_BASE_ADDR;
/*
* GT-6426x variants
*/
#define GT_64260 0 /* includes both 64260A and 64260B */
#define GT_64261 1
#if (CONFIG_SYS_GT_6426x == GT_64260)
#ifdef CONFIG_ETHER_PORT_MII
#define GAL_ETH_DEVS 2
#else
#define GAL_ETH_DEVS 3
#endif
#elif (CONFIG_SYS_GT_6426x == GT_64261)
#define GAL_ETH_DEVS 2
#else
#define GAL_ETH_DEVS 3 /* default to a 64260 */
#endif
/****************************************/
/* GENERAL Definitions */
/****************************************/
#define NO_BIT 0x00000000
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define _1K 0x00000400
#define _2K 0x00000800
#define _4K 0x00001000
#define _8K 0x00002000
#define _16K 0x00004000
#define _32K 0x00008000
#define _64K 0x00010000
#define _128K 0x00020000
#define _256K 0x00040000
#define _512K 0x00080000
#define _1M 0x00100000
#define _2M 0x00200000
#define _3M 0x00300000
#define _4M 0x00400000
#define _5M 0x00500000
#define _6M 0x00600000
#define _7M 0x00700000
#define _8M 0x00800000
#define _9M 0x00900000
#define _10M 0x00a00000
#define _11M 0x00b00000
#define _12M 0x00c00000
#define _13M 0x00d00000
#define _14M 0x00e00000
#define _15M 0x00f00000
#define _16M 0x01000000
#define _32M 0x02000000
#define _64M 0x04000000
#define _128M 0x08000000
#define _256M 0x10000000
#define _512M 0x20000000
#define _1G 0x40000000
#define _2G 0x80000000
#ifndef BOOL_WAS_DEFINED
#define BOOL_WAS_DEFINED
typedef enum _bool{false,true} bool;
#endif
/* Little to Big endian conversion macros */
#ifdef LE /* Little Endian */
#define SHORT_SWAP(X) (X)
#define WORD_SWAP(X) (X)
#define LONG_SWAP(X) ((l64)(X))
#else /* Big Endian */
#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
#define WORD_SWAP(X) (((X)&0xff)<<24)+ \
(((X)&0xff00)<<8)+ \
(((X)&0xff0000)>>8)+ \
(((X)&0xff000000)>>24)
#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
(((X)&0xff00ULL)<<40)+ \
(((X)&0xff0000ULL)<<24)+ \
(((X)&0xff000000ULL)<<8)+ \
(((X)&0xff00000000ULL)>>8)+ \
(((X)&0xff0000000000ULL)>>24)+ \
(((X)&0xff000000000000ULL)>>40)+ \
(((X)&0xff00000000000000ULL)>>56))
#endif
#ifndef NULL
#define NULL 0
#endif
/* Those two definitions were defined to be compatible with MIPS */
#define NONE_CACHEABLE 0x00000000
#define CACHEABLE 0x00000000
/* 750 cache line */
#define CACHE_LINE_SIZE 32
#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
/* Read/Write to/from GT`s internal registers */
#define GT_REG_READ(offset, pData) \
*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \
INTERNAL_REG_BASE_ADDR | (offset))) ) ; \
*pData = WORD_SWAP(*pData)
#define GTREGREAD(offset) \
(WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \
INTERNAL_REG_BASE_ADDR | (offset))) ))
#define GT_REG_WRITE(offset, data) \
*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \
WORD_SWAP(data)
/* Write 32/16/8 bit */
#define WRITE_CHAR(address, data) \
*((unsigned char *)(address)) = data
#define WRITE_SHORT(address, data) \
*((unsigned short *)(address)) = data
#define WRITE_WORD(address, data) \
*((unsigned int *)(address)) = data
/* Read 32/16/8 bits - returns data in variable. */
#define READ_CHAR(address, pData) \
*pData = *((volatile unsigned char *)(address))
#define READ_SHORT(address, pData) \
*pData = *((volatile unsigned short *)(address))
#define READ_WORD(address, pData) \
*pData = *((volatile unsigned int *)(address))
/* Read 32/16/8 bit - returns data direct. */
#define READCHAR(address) \
*((volatile unsigned char *)((address) | NONE_CACHEABLE))
#define READSHORT(address) \
*((volatile unsigned short *)((address) | NONE_CACHEABLE))
#define READWORD(address) \
*((volatile unsigned int *)((address) | NONE_CACHEABLE))
/* Those two Macros were defined to be compatible with MIPS */
#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff)
#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE)
/* SET_REG_BITS(regOffset,bits) -
gets register offset and bits: a 32bit value. It set to logic '1' in the
internal register the bits which given as an input example:
SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'1' in register 0x840 while the other bits stays as is. */
#define SET_REG_BITS(regOffset,bits) \
*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
regOffset) |= (unsigned int)WORD_SWAP(bits)
/* RESET_REG_BITS(regOffset,bits) -
gets register offset and bits: a 32bit value. It set to logic '0' in the
internal register the bits which given as an input example:
RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'0' in register 0x840 while the other bits stays as is. */
#define RESET_REG_BITS(regOffset,bits) \
*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \
| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
#endif /* __INCcoreh */
|
1001-study-uboot
|
include/galileo/core.h
|
C
|
gpl3
| 7,557
|
/*
* (C) Copyright 2006
* Bryan O'Donoghue, deckard@codehermit.ie, CodeHermit
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
/* ACM Control Requests */
#define ACM_SEND_ENCAPSULATED_COMMAND 0x00
#define ACM_GET_ENCAPSULATED_RESPONSE 0x01
#define ACM_SET_COMM_FEATURE 0x02
#define ACM_GET_COMM_FEATRUE 0x03
#define ACM_CLEAR_COMM_FEATURE 0x04
#define ACM_SET_LINE_ENCODING 0x20
#define ACM_GET_LINE_ENCODING 0x21
#define ACM_SET_CONTROL_LINE_STATE 0x22
#define ACM_SEND_BREAK 0x23
/* ACM Notification Codes */
#define ACM_NETWORK_CONNECTION 0x00
#define ACM_RESPONSE_AVAILABLE 0x01
#define ACM_SERIAL_STATE 0x20
/* Format of response expected by a ACM_GET_LINE_ENCODING request */
struct rs232_emu{
unsigned long dter;
unsigned char stop_bits;
unsigned char parity;
unsigned char data_bits;
}__attribute__((packed));
|
1001-study-uboot
|
include/usb_cdc_acm.h
|
C
|
gpl3
| 1,499
|
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Most of the following information was derived from the document
* "Information Technology - AT Attachment-3 Interface (ATA-3)"
* which can be found at:
* http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip
* ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP
* ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip
*/
#ifndef _ATA_H
#define _ATA_H
#include <libata.h>
/* Register addressing depends on the hardware design; for instance,
* 8-bit (register) and 16-bit (data) accesses might use different
* address spaces. This is implemented by the following definitions.
*/
#ifndef CONFIG_SYS_ATA_STRIDE
#define CONFIG_SYS_ATA_STRIDE 1
#endif
#define ATA_IO_DATA(x) (CONFIG_SYS_ATA_DATA_OFFSET+((x) * CONFIG_SYS_ATA_STRIDE))
#define ATA_IO_REG(x) (CONFIG_SYS_ATA_REG_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
#define ATA_IO_ALT(x) (CONFIG_SYS_ATA_ALT_OFFSET +((x) * CONFIG_SYS_ATA_STRIDE))
/*
* I/O Register Descriptions
*/
#define ATA_DATA_REG ATA_IO_DATA(0)
#define ATA_ERROR_REG ATA_IO_REG(1)
#define ATA_SECT_CNT ATA_IO_REG(2)
#define ATA_SECT_NUM ATA_IO_REG(3)
#define ATA_CYL_LOW ATA_IO_REG(4)
#define ATA_CYL_HIGH ATA_IO_REG(5)
#define ATA_DEV_HD ATA_IO_REG(6)
#define ATA_COMMAND ATA_IO_REG(7)
#define ATA_DATA_EVEN ATA_IO_REG(8)
#define ATA_DATA_ODD ATA_IO_REG(9)
#define ATA_STATUS ATA_COMMAND
#define ATA_DEV_CTL ATA_IO_ALT(6)
#define ATA_LBA_LOW ATA_SECT_NUM
#define ATA_LBA_MID ATA_CYL_LOW
#define ATA_LBA_HIGH ATA_CYL_HIGH
#define ATA_LBA_SEL ATA_DEV_CTL
/*
* Status register bits
*/
#define ATA_STAT_BUSY 0x80 /* Device Busy */
#define ATA_STAT_READY 0x40 /* Device Ready */
#define ATA_STAT_FAULT 0x20 /* Device Fault */
#define ATA_STAT_SEEK 0x10 /* Device Seek Complete */
#define ATA_STAT_DRQ 0x08 /* Data Request (ready) */
#define ATA_STAT_CORR 0x04 /* Corrected Data Error */
#define ATA_STAT_INDEX 0x02 /* Vendor specific */
#define ATA_STAT_ERR 0x01 /* Error */
/*
* Device / Head Register Bits
*/
#define ATA_DEVICE(x) ((x & 1)<<4)
#define ATA_LBA 0xE0
/*
* ATA Commands (only mandatory commands listed here)
*/
#define ATA_CMD_READ 0x20 /* Read Sectors (with retries) */
#define ATA_CMD_READN 0x21 /* Read Sectors ( no retries) */
#define ATA_CMD_WRITE 0x30 /* Write Sectores (with retries)*/
#define ATA_CMD_WRITEN 0x31 /* Write Sectors ( no retries)*/
#define ATA_CMD_VRFY 0x40 /* Read Verify (with retries) */
#define ATA_CMD_VRFYN 0x41 /* Read verify ( no retries) */
#define ATA_CMD_SEEK 0x70 /* Seek */
#define ATA_CMD_DIAG 0x90 /* Execute Device Diagnostic */
#define ATA_CMD_INIT 0x91 /* Initialize Device Parameters */
#define ATA_CMD_RD_MULT 0xC4 /* Read Multiple */
#define ATA_CMD_WR_MULT 0xC5 /* Write Multiple */
#define ATA_CMD_SETMULT 0xC6 /* Set Multiple Mode */
#define ATA_CMD_RD_DMA 0xC8 /* Read DMA (with retries) */
#define ATA_CMD_RD_DMAN 0xC9 /* Read DMS ( no retries) */
#define ATA_CMD_WR_DMA 0xCA /* Write DMA (with retries) */
#define ATA_CMD_WR_DMAN 0xCB /* Write DMA ( no retires) */
#define ATA_CMD_IDENT 0xEC /* Identify Device */
#define ATA_CMD_SETF 0xEF /* Set Features */
#define ATA_CMD_CHK_PWR 0xE5 /* Check Power Mode */
#define ATA_CMD_READ_EXT 0x24 /* Read Sectors (with retries) with 48bit addressing */
#define ATA_CMD_WRITE_EXT 0x34 /* Write Sectores (with retries) with 48bit addressing */
#define ATA_CMD_VRFY_EXT 0x42 /* Read Verify (with retries) with 48bit addressing */
/*
* ATAPI Commands
*/
#define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */
#define ATAPI_CMD_PACKET 0xA0 /* Packed Command */
#define ATAPI_CMD_INQUIRY 0x12
#define ATAPI_CMD_REQ_SENSE 0x03
#define ATAPI_CMD_READ_CAP 0x25
#define ATAPI_CMD_START_STOP 0x1B
#define ATAPI_CMD_READ_12 0xA8
#define ATA_GET_ERR() inb(ATA_STATUS)
#define ATA_GET_STAT() inb(ATA_STATUS)
#define ATA_OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good))
#define ATA_BAD_R_STAT (ATA_STAT_BUSY | ATA_STAT_ERR)
#define ATA_BAD_W_STAT (ATA_BAD_R_STAT | ATA_STAT_FAULT)
#define ATA_BAD_STAT (ATA_BAD_R_STAT | ATA_STAT_DRQ)
#define ATA_DRIVE_READY (ATA_READY_STAT | ATA_STAT_SEEK)
#define ATA_DATA_READY (ATA_STAT_DRQ)
#define ATA_BLOCKSIZE 512 /* bytes */
#define ATA_BLOCKSHIFT 9 /* 2 ^ ATA_BLOCKSIZESHIFT = 512 */
#define ATA_SECTORWORDS (512 / sizeof(unsigned long))
#ifndef ATA_RESET_TIME
#define ATA_RESET_TIME 60 /* spec allows up to 31 seconds */
#endif
/* ------------------------------------------------------------------------- */
/*
* structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec
*/
typedef struct hd_driveid {
unsigned short config; /* lots of obsolete bit flags */
unsigned short cyls; /* "physical" cyls */
unsigned short reserved2; /* reserved (word 2) */
unsigned short heads; /* "physical" heads */
unsigned short track_bytes; /* unformatted bytes per track */
unsigned short sector_bytes; /* unformatted bytes per sector */
unsigned short sectors; /* "physical" sectors per track */
unsigned short vendor0; /* vendor unique */
unsigned short vendor1; /* vendor unique */
unsigned short vendor2; /* vendor unique */
unsigned char serial_no[20]; /* 0 = not_specified */
unsigned short buf_type;
unsigned short buf_size; /* 512 byte increments; 0 = not_specified */
unsigned short ecc_bytes; /* for r/w long cmds; 0 = not_specified */
unsigned char fw_rev[8]; /* 0 = not_specified */
unsigned char model[40]; /* 0 = not_specified */
unsigned char max_multsect; /* 0=not_implemented */
unsigned char vendor3; /* vendor unique */
unsigned short dword_io; /* 0=not_implemented; 1=implemented */
unsigned char vendor4; /* vendor unique */
unsigned char capability; /* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/
unsigned short reserved50; /* reserved (word 50) */
unsigned char vendor5; /* vendor unique */
unsigned char tPIO; /* 0=slow, 1=medium, 2=fast */
unsigned char vendor6; /* vendor unique */
unsigned char tDMA; /* 0=slow, 1=medium, 2=fast */
unsigned short field_valid; /* bits 0:cur_ok 1:eide_ok */
unsigned short cur_cyls; /* logical cylinders */
unsigned short cur_heads; /* logical heads */
unsigned short cur_sectors; /* logical sectors per track */
unsigned short cur_capacity0; /* logical total sectors on drive */
unsigned short cur_capacity1; /* (2 words, misaligned int) */
unsigned char multsect; /* current multiple sector count */
unsigned char multsect_valid; /* when (bit0==1) multsect is ok */
unsigned int lba_capacity; /* total number of sectors */
unsigned short dma_1word; /* single-word dma info */
unsigned short dma_mword; /* multiple-word dma info */
unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */
unsigned short eide_dma_min; /* min mword dma cycle time (ns) */
unsigned short eide_dma_time; /* recommended mword dma cycle time (ns) */
unsigned short eide_pio; /* min cycle time (ns), no IORDY */
unsigned short eide_pio_iordy; /* min cycle time (ns), with IORDY */
unsigned short words69_70[2]; /* reserved words 69-70 */
unsigned short words71_74[4]; /* reserved words 71-74 */
unsigned short queue_depth; /* */
unsigned short words76_79[4]; /* reserved words 76-79 */
unsigned short major_rev_num; /* */
unsigned short minor_rev_num; /* */
unsigned short command_set_1; /* bits 0:Smart 1:Security 2:Removable 3:PM */
unsigned short command_set_2; /* bits 14:Smart Enabled 13:0 zero 10:lba48 support*/
unsigned short cfsse; /* command set-feature supported extensions */
unsigned short cfs_enable_1; /* command set-feature enabled */
unsigned short cfs_enable_2; /* command set-feature enabled */
unsigned short csf_default; /* command set-feature default */
unsigned short dma_ultra; /* */
unsigned short word89; /* reserved (word 89) */
unsigned short word90; /* reserved (word 90) */
unsigned short CurAPMvalues; /* current APM values */
unsigned short word92; /* reserved (word 92) */
unsigned short hw_config; /* hardware config */
unsigned short words94_99[6];/* reserved words 94-99 */
/*unsigned long long lba48_capacity; /--* 4 16bit values containing lba 48 total number of sectors */
unsigned short lba48_capacity[4]; /* 4 16bit values containing lba 48 total number of sectors */
unsigned short words104_125[22];/* reserved words 104-125 */
unsigned short last_lun; /* reserved (word 126) */
unsigned short word127; /* reserved (word 127) */
unsigned short dlf; /* device lock function
* 15:9 reserved
* 8 security level 1:max 0:high
* 7:6 reserved
* 5 enhanced erase
* 4 expire
* 3 frozen
* 2 locked
* 1 en/disabled
* 0 capability
*/
unsigned short csfo; /* current set features options
* 15:4 reserved
* 3 auto reassign
* 2 reverting
* 1 read-look-ahead
* 0 write cache
*/
unsigned short words130_155[26];/* reserved vendor words 130-155 */
unsigned short word156;
unsigned short words157_159[3];/* reserved vendor words 157-159 */
unsigned short words160_162[3];/* reserved words 160-162 */
unsigned short cf_advanced_caps;
unsigned short words164_255[92];/* reserved words 164-255 */
} hd_driveid_t;
/*
* PIO Mode Configuration
*
* See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21
*/
typedef struct {
unsigned int t_setup; /* Setup Time in [ns] or clocks */
unsigned int t_length; /* Length Time in [ns] or clocks */
unsigned int t_hold; /* Hold Time in [ns] or clocks */
}
pio_config_t;
#define IDE_MAX_PIO_MODE 4 /* max suppurted PIO mode */
/* ------------------------------------------------------------------------- */
#endif /* _ATA_H */
|
1001-study-uboot
|
include/ata.h
|
C
|
gpl3
| 10,498
|
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix at windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git
*
* Copyright (C) 2007-2009 Texas Instruments, Inc.
*/
#ifndef TWL4030_H
#define TWL4030_H
#include <common.h>
#include <i2c.h>
/* I2C chip addresses */
/* USB */
#define TWL4030_CHIP_USB 0x48
/* AUD */
#define TWL4030_CHIP_AUDIO_VOICE 0x49
#define TWL4030_CHIP_GPIO 0x49
#define TWL4030_CHIP_INTBR 0x49
#define TWL4030_CHIP_PIH 0x49
#define TWL4030_CHIP_TEST 0x49
/* AUX */
#define TWL4030_CHIP_KEYPAD 0x4a
#define TWL4030_CHIP_MADC 0x4a
#define TWL4030_CHIP_INTERRUPTS 0x4a
#define TWL4030_CHIP_LED 0x4a
#define TWL4030_CHIP_MAIN_CHARGE 0x4a
#define TWL4030_CHIP_PRECHARGE 0x4a
#define TWL4030_CHIP_PWM0 0x4a
#define TWL4030_CHIP_PWM1 0x4a
#define TWL4030_CHIP_PWMA 0x4a
#define TWL4030_CHIP_PWMB 0x4a
/* POWER */
#define TWL4030_CHIP_BACKUP 0x4b
#define TWL4030_CHIP_INT 0x4b
#define TWL4030_CHIP_PM_MASTER 0x4b
#define TWL4030_CHIP_PM_RECEIVER 0x4b
#define TWL4030_CHIP_RTC 0x4b
#define TWL4030_CHIP_SECURED_REG 0x4b
/* Register base addresses */
/* USB */
#define TWL4030_BASEADD_USB 0x0000
/* AUD */
#define TWL4030_BASEADD_AUDIO_VOICE 0x0000
#define TWL4030_BASEADD_GPIO 0x0098
#define TWL4030_BASEADD_INTBR 0x0085
#define TWL4030_BASEADD_PIH 0x0080
#define TWL4030_BASEADD_TEST 0x004C
/* AUX */
#define TWL4030_BASEADD_INTERRUPTS 0x00B9
#define TWL4030_BASEADD_LED 0x00EE
#define TWL4030_BASEADD_MADC 0x0000
#define TWL4030_BASEADD_MAIN_CHARGE 0x0074
#define TWL4030_BASEADD_PRECHARGE 0x00AA
#define TWL4030_BASEADD_PWM0 0x00F8
#define TWL4030_BASEADD_PWM1 0x00FB
#define TWL4030_BASEADD_PWMA 0x00EF
#define TWL4030_BASEADD_PWMB 0x00F1
#define TWL4030_BASEADD_KEYPAD 0x00D2
/* POWER */
#define TWL4030_BASEADD_BACKUP 0x0014
#define TWL4030_BASEADD_INT 0x002E
#define TWL4030_BASEADD_PM_MASTER 0x0036
#define TWL4030_BASEADD_PM_RECIEVER 0x005B
#define TWL4030_BASEADD_RTC 0x001C
#define TWL4030_BASEADD_SECURED_REG 0x0000
/*
* Power Management Master
*/
#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x36
#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x37
#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x38
#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x39
#define TWL4030_PM_MASTER_STS_BOOT 0x3A
#define TWL4030_PM_MASTER_CFG_BOOT 0x3B
#define TWL4030_PM_MASTER_SHUNDAN 0x3C
#define TWL4030_PM_MASTER_BOOT_BCI 0x3D
#define TWL4030_PM_MASTER_CFG_PWRANA1 0x3E
#define TWL4030_PM_MASTER_CFG_PWRANA2 0x3F
#define TWL4030_PM_MASTER_BGAP_TRIM 0x40
#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x41
#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x42
#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x43
#define TWL4030_PM_MASTER_PROTECT_KEY 0x44
#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x45
#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x46
#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x47
#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x48
#define TWL4030_PM_MASTER_STS_P123_STATE 0x49
#define TWL4030_PM_MASTER_PB_CFG 0x4A
#define TWL4030_PM_MASTER_PB_WORD_MSB 0x4B
#define TWL4030_PM_MASTER_PB_WORD_LSB 0x4C
#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x52
#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x53
#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x54
#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x55
#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x56
#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x57
#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x58
#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x59
#define TWL4030_PM_MASTER_MEMORY_DATA 0x5A
#define TWL4030_PM_MASTER_SC_CONFIG 0x5B
#define TWL4030_PM_MASTER_SC_DETECT1 0x5C
#define TWL4030_PM_MASTER_SC_DETECT2 0x5D
#define TWL4030_PM_MASTER_WATCHDOG_CFG 0x5E
#define TWL4030_PM_MASTER_IT_CHECK_CFG 0x5F
#define TWL4030_PM_MASTER_VIBRATOR_CFG 0x60
#define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG 0x61
#define TWL4030_PM_MASTER_VDD1_TRIM1 0x62
#define TWL4030_PM_MASTER_VDD1_TRIM2 0x63
#define TWL4030_PM_MASTER_VDD2_TRIM1 0x64
#define TWL4030_PM_MASTER_VDD2_TRIM2 0x65
#define TWL4030_PM_MASTER_VIO_TRIM1 0x66
#define TWL4030_PM_MASTER_VIO_TRIM2 0x67
#define TWL4030_PM_MASTER_MISC_CFG 0x68
#define TWL4030_PM_MASTER_LS_TST_A 0x69
#define TWL4030_PM_MASTER_LS_TST_B 0x6A
#define TWL4030_PM_MASTER_LS_TST_C 0x6B
#define TWL4030_PM_MASTER_LS_TST_D 0x6C
#define TWL4030_PM_MASTER_BB_CFG 0x6D
#define TWL4030_PM_MASTER_MISC_TST 0x6E
#define TWL4030_PM_MASTER_TRIM1 0x6F
/* P[1-3]_SW_EVENTS */
#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6)
#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5)
#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4)
#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3)
#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2)
#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
/* Power Managment Receiver */
#define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B
#define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C
#define TWL4030_PM_RECEIVER_SC_DETECT2 0x5D
#define TWL4030_PM_RECEIVER_WATCHDOG_CFG 0x5E
#define TWL4030_PM_RECEIVER_IT_CHECK_CFG 0x5F
#define TWL4030_PM_RECEIVER_VIBRATOR_CFG 0x5F
#define TWL4030_PM_RECEIVER_DC_TO_DC_CFG 0x61
#define TWL4030_PM_RECEIVER_VDD1_TRIM1 0x62
#define TWL4030_PM_RECEIVER_VDD1_TRIM2 0x63
#define TWL4030_PM_RECEIVER_VDD2_TRIM1 0x64
#define TWL4030_PM_RECEIVER_VDD2_TRIM2 0x65
#define TWL4030_PM_RECEIVER_VIO_TRIM1 0x66
#define TWL4030_PM_RECEIVER_VIO_TRIM2 0x67
#define TWL4030_PM_RECEIVER_MISC_CFG 0x68
#define TWL4030_PM_RECEIVER_LS_TST_A 0x69
#define TWL4030_PM_RECEIVER_LS_TST_B 0x6A
#define TWL4030_PM_RECEIVER_LS_TST_C 0x6B
#define TWL4030_PM_RECEIVER_LS_TST_D 0x6C
#define TWL4030_PM_RECEIVER_BB_CFG 0x6D
#define TWL4030_PM_RECEIVER_MISC_TST 0x6E
#define TWL4030_PM_RECEIVER_TRIM1 0x6F
#define TWL4030_PM_RECEIVER_TRIM2 0x70
#define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT 0x71
#define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP 0x72
#define TWL4030_PM_RECEIVER_VAUX1_TYPE 0x73
#define TWL4030_PM_RECEIVER_VAUX1_REMAP 0x74
#define TWL4030_PM_RECEIVER_VAUX1_DEDICATED 0x75
#define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP 0x76
#define TWL4030_PM_RECEIVER_VAUX2_TYPE 0x77
#define TWL4030_PM_RECEIVER_VAUX2_REMAP 0x78
#define TWL4030_PM_RECEIVER_VAUX2_DEDICATED 0x79
#define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP 0x7A
#define TWL4030_PM_RECEIVER_VAUX3_TYPE 0x7B
#define TWL4030_PM_RECEIVER_VAUX3_REMAP 0x7C
#define TWL4030_PM_RECEIVER_VAUX3_DEDICATED 0x7D
#define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP 0x7E
#define TWL4030_PM_RECEIVER_VAUX4_TYPE 0x7F
#define TWL4030_PM_RECEIVER_VAUX4_REMAP 0x80
#define TWL4030_PM_RECEIVER_VAUX4_DEDICATED 0x81
#define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP 0x82
#define TWL4030_PM_RECEIVER_VMMC1_TYPE 0x83
#define TWL4030_PM_RECEIVER_VMMC1_REMAP 0x84
#define TWL4030_PM_RECEIVER_VMMC1_DEDICATED 0x85
#define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP 0x86
#define TWL4030_PM_RECEIVER_VMMC2_TYPE 0x87
#define TWL4030_PM_RECEIVER_VMMC2_REMAP 0x88
#define TWL4030_PM_RECEIVER_VMMC2_DEDICATED 0x89
#define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP 0x8A
#define TWL4030_PM_RECEIVER_VPLL1_TYPE 0x8B
#define TWL4030_PM_RECEIVER_VPLL1_REMAP 0x8C
#define TWL4030_PM_RECEIVER_VPLL1_DEDICATED 0x8D
#define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP 0x8E
#define TWL4030_PM_RECEIVER_VPLL2_TYPE 0x8F
#define TWL4030_PM_RECEIVER_VPLL2_REMAP 0x90
#define TWL4030_PM_RECEIVER_VPLL2_DEDICATED 0x91
#define TWL4030_PM_RECEIVER_VSIM_DEV_GRP 0x92
#define TWL4030_PM_RECEIVER_VSIM_TYPE 0x93
#define TWL4030_PM_RECEIVER_VSIM_REMAP 0x94
#define TWL4030_PM_RECEIVER_VSIM_DEDICATED 0x95
#define TWL4030_PM_RECEIVER_VDAC_DEV_GRP 0x96
#define TWL4030_PM_RECEIVER_VDAC_TYPE 0x97
#define TWL4030_PM_RECEIVER_VDAC_REMAP 0x98
#define TWL4030_PM_RECEIVER_VDAC_DEDICATED 0x99
#define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP 0x9A
#define TWL4030_PM_RECEIVER_VINTANA1_TYP 0x9B
#define TWL4030_PM_RECEIVER_VINTANA1_REMAP 0x9C
#define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED 0x9D
#define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP 0x9E
#define TWL4030_PM_RECEIVER_VINTANA2_TYPE 0x9F
#define TWL4030_PM_RECEIVER_VINTANA2_REMAP 0xA0
#define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED 0xA1
#define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP 0xA2
#define TWL4030_PM_RECEIVER_VINTDIG_TYPE 0xA3
#define TWL4030_PM_RECEIVER_VINTDIG_REMAP 0xA4
#define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED 0xA5
#define TWL4030_PM_RECEIVER_VIO_DEV_GRP 0xA6
#define TWL4030_PM_RECEIVER_VIO_TYPE 0xA7
#define TWL4030_PM_RECEIVER_VIO_REMAP 0xA8
#define TWL4030_PM_RECEIVER_VIO_CFG 0xA9
#define TWL4030_PM_RECEIVER_VIO_MISC_CFG 0xAA
#define TWL4030_PM_RECEIVER_VIO_TEST1 0xAB
#define TWL4030_PM_RECEIVER_VIO_TEST2 0xAC
#define TWL4030_PM_RECEIVER_VIO_OSC 0xAD
#define TWL4030_PM_RECEIVER_VIO_RESERVED 0xAE
#define TWL4030_PM_RECEIVER_VIO_VSEL 0xAF
#define TWL4030_PM_RECEIVER_VDD1_DEV_GRP 0xB0
#define TWL4030_PM_RECEIVER_VDD1_TYPE 0xB1
#define TWL4030_PM_RECEIVER_VDD1_REMAP 0xB2
#define TWL4030_PM_RECEIVER_VDD1_CFG 0xB3
#define TWL4030_PM_RECEIVER_VDD1_MISC_CFG 0xB4
#define TWL4030_PM_RECEIVER_VDD1_TEST1 0xB5
#define TWL4030_PM_RECEIVER_VDD1_TEST2 0xB6
#define TWL4030_PM_RECEIVER_VDD1_OSC 0xB7
#define TWL4030_PM_RECEIVER_VDD1_RESERVED 0xB8
#define TWL4030_PM_RECEIVER_VDD1_VSEL 0xB9
#define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG 0xBA
#define TWL4030_PM_RECEIVER_VDD1_VFLOOR 0xBB
#define TWL4030_PM_RECEIVER_VDD1_VROOF 0xBC
#define TWL4030_PM_RECEIVER_VDD1_STEP 0xBD
#define TWL4030_PM_RECEIVER_VDD2_DEV_GRP 0xBE
#define TWL4030_PM_RECEIVER_VDD2_TYPE 0xBF
#define TWL4030_PM_RECEIVER_VDD2_REMAP 0xC0
#define TWL4030_PM_RECEIVER_VDD2_CFG 0xC1
#define TWL4030_PM_RECEIVER_VDD2_MISC_CFG 0xC2
#define TWL4030_PM_RECEIVER_VDD2_TEST1 0xC3
#define TWL4030_PM_RECEIVER_VDD2_TEST2 0xC4
#define TWL4030_PM_RECEIVER_VDD2_OSC 0xC5
#define TWL4030_PM_RECEIVER_VDD2_RESERVED 0xC6
#define TWL4030_PM_RECEIVER_VDD2_VSEL 0xC7
#define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG 0xC8
#define TWL4030_PM_RECEIVER_VDD2_VFLOOR 0xC9
#define TWL4030_PM_RECEIVER_VDD2_VROOF 0xCA
#define TWL4030_PM_RECEIVER_VDD2_STEP 0xCB
#define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP 0xCC
#define TWL4030_PM_RECEIVER_VUSB1V5_TYPE 0xCD
#define TWL4030_PM_RECEIVER_VUSB1V5_REMAP 0xCE
#define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP 0xCF
#define TWL4030_PM_RECEIVER_VUSB1V8_TYPE 0xD0
#define TWL4030_PM_RECEIVER_VUSB1V8_REMAP 0xD1
#define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP 0xD2
#define TWL4030_PM_RECEIVER_VUSB3V1_TYPE 0xD3
#define TWL4030_PM_RECEIVER_VUSB3V1_REMAP 0xD4
#define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP 0xD5
#define TWL4030_PM_RECEIVER_VUSBCP_TYPE 0xD6
#define TWL4030_PM_RECEIVER_VUSBCP_REMAP 0xD7
#define TWL4030_PM_RECEIVER_VUSB_DEDICATED1 0xD8
#define TWL4030_PM_RECEIVER_VUSB_DEDICATED2 0xD9
#define TWL4030_PM_RECEIVER_REGEN_DEV_GRP 0xDA
#define TWL4030_PM_RECEIVER_REGEN_TYPE 0xDB
#define TWL4030_PM_RECEIVER_REGEN_REMAP 0xDC
#define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP 0xDD
#define TWL4030_PM_RECEIVER_NRESPWRON_TYPE 0xDE
#define TWL4030_PM_RECEIVER_NRESPWRON_REMAP 0xDF
#define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP 0xE0
#define TWL4030_PM_RECEIVER_CLKEN_TYPE 0xE1
#define TWL4030_PM_RECEIVER_CLKEN_REMAP 0xE2
#define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP 0xE3
#define TWL4030_PM_RECEIVER_SYSEN_TYPE 0xE4
#define TWL4030_PM_RECEIVER_SYSEN_REMAP 0xE5
#define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP 0xE6
#define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE 0xE7
#define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP 0xE8
#define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP 0xE9
#define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE 0xEA
#define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP 0xEB
#define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP 0xEC
#define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE 0xED
#define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP 0xEE
#define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP 0xEF
#define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0
#define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1
/* Voltage Selection in PM Receiver Module */
#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05
#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03
#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05
#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03
/* Device Selection in PM Receiver Module */
#define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20
#define TWL4030_PM_RECEIVER_DEV_GRP_ALL 0xE0
/* LED */
#define TWL4030_LED_LEDEN 0xEE
#define TWL4030_LED_LEDEN_LEDAON (1 << 0)
#define TWL4030_LED_LEDEN_LEDBON (1 << 1)
#define TWL4030_LED_LEDEN_LEDAPWM (1 << 4)
#define TWL4030_LED_LEDEN_LEDBPWM (1 << 5)
/* Keypad */
#define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2
#define TWL4030_KEYPAD_KEY_DEB_REG 0xD3
#define TWL4030_KEYPAD_LONG_KEY_REG1 0xD4
#define TWL4030_KEYPAD_LK_PTV_REG 0xD5
#define TWL4030_KEYPAD_TIME_OUT_REG1 0xD6
#define TWL4030_KEYPAD_TIME_OUT_REG2 0xD7
#define TWL4030_KEYPAD_KBC_REG 0xD8
#define TWL4030_KEYPAD_KBR_REG 0xD9
#define TWL4030_KEYPAD_KEYP_SMS 0xDA
#define TWL4030_KEYPAD_FULL_CODE_7_0 0xDB
#define TWL4030_KEYPAD_FULL_CODE_15_8 0xDC
#define TWL4030_KEYPAD_FULL_CODE_23_16 0xDD
#define TWL4030_KEYPAD_FULL_CODE_31_24 0xDE
#define TWL4030_KEYPAD_FULL_CODE_39_32 0xDF
#define TWL4030_KEYPAD_FULL_CODE_47_40 0xE0
#define TWL4030_KEYPAD_FULL_CODE_55_48 0xE1
#define TWL4030_KEYPAD_FULL_CODE_63_56 0xE2
#define TWL4030_KEYPAD_KEYP_ISR1 0xE3
#define TWL4030_KEYPAD_KEYP_IMR1 0xE4
#define TWL4030_KEYPAD_KEYP_ISR2 0xE5
#define TWL4030_KEYPAD_KEYP_IMR2 0xE6
#define TWL4030_KEYPAD_KEYP_SIR 0xE7
#define TWL4030_KEYPAD_KEYP_EDR 0xE8
#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0xE9
#define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6)
#define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5)
#define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4)
#define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3)
#define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2)
#define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1)
#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0)
/* USB */
#define TWL4030_USB_VENDOR_ID_LO 0x00
#define TWL4030_USB_VENDOR_ID_HI 0x01
#define TWL4030_USB_PRODUCT_ID_LO 0x02
#define TWL4030_USB_PRODUCT_ID_HI 0x03
#define TWL4030_USB_FUNC_CTRL 0x04
#define TWL4030_USB_FUNC_CTRL_SET 0x05
#define TWL4030_USB_FUNC_CTRL_CLR 0x06
#define TWL4030_USB_IFC_CTRL 0x07
#define TWL4030_USB_IFC_CTRL_SET 0x08
#define TWL4030_USB_IFC_CTRL_CLR 0x09
#define TWL4030_USB_OTG_CTRL 0x0A
#define TWL4030_USB_OTG_CTRL_SET 0x0B
#define TWL4030_USB_OTG_CTRL_CLR 0x0C
#define TWL4030_USB_USB_INT_EN_RISE 0x0D
#define TWL4030_USB_USB_INT_EN_RISE_SET 0x0E
#define TWL4030_USB_USB_INT_EN_RISE_CLR 0x0F
#define TWL4030_USB_USB_INT_EN_FALL 0x10
#define TWL4030_USB_USB_INT_EN_FALL_SET 0x11
#define TWL4030_USB_USB_INT_EN_FALL_CLR 0x12
#define TWL4030_USB_USB_INT_STS 0x13
#define TWL4030_USB_USB_INT_LATCH 0x14
#define TWL4030_USB_DEBUG 0x15
#define TWL4030_USB_SCRATCH_REG 0x16
#define TWL4030_USB_SCRATCH_REG_SET 0x17
#define TWL4030_USB_SCRATCH_REG_CLR 0x18
#define TWL4030_USB_CARKIT_CTRL 0x19
#define TWL4030_USB_CARKIT_CTRL_SET 0x1A
#define TWL4030_USB_CARKIT_CTRL_CLR 0x1B
#define TWL4030_USB_CARKIT_INT_DELAY 0x1C
#define TWL4030_USB_CARKIT_INT_EN 0x1D
#define TWL4030_USB_CARKIT_INT_EN_SET 0x1E
#define TWL4030_USB_CARKIT_INT_EN_CLR 0x1F
#define TWL4030_USB_CARKIT_INT_STS 0x20
#define TWL4030_USB_CARKIT_INT_LATCH 0x21
#define TWL4030_USB_CARKIT_PLS_CTRL 0x22
#define TWL4030_USB_CARKIT_PLS_CTRL_SET 0x23
#define TWL4030_USB_CARKIT_PLS_CTRL_CLR 0x24
#define TWL4030_USB_TRANS_POS_WIDTH 0x25
#define TWL4030_USB_TRANS_NEG_WIDTH 0x26
#define TWL4030_USB_RCV_PLTY_RECOVERY 0x27
#define TWL4030_USB_MCPC_CTRL 0x30
#define TWL4030_USB_MCPC_CTRL_SET 0x31
#define TWL4030_USB_MCPC_CTRL_CLR 0x32
#define TWL4030_USB_MCPC_IO_CTRL 0x33
#define TWL4030_USB_MCPC_IO_CTRL_SET 0x34
#define TWL4030_USB_MCPC_IO_CTRL_CLR 0x35
#define TWL4030_USB_MCPC_CTRL2 0x36
#define TWL4030_USB_MCPC_CTRL2_SET 0x37
#define TWL4030_USB_MCPC_CTRL2_CLR 0x38
#define TWL4030_USB_OTHER_FUNC_CTRL 0x80
#define TWL4030_USB_OTHER_FUNC_CTRL_SET 0x81
#define TWL4030_USB_OTHER_FUNC_CTRL_CLR 0x82
#define TWL4030_USB_OTHER_IFC_CTRL 0x83
#define TWL4030_USB_OTHER_IFC_CTRL_SET 0x84
#define TWL4030_USB_OTHER_IFC_CTRL_CLR 0x85
#define TWL4030_USB_OTHER_INT_EN_RISE_SET 0x87
#define TWL4030_USB_OTHER_INT_EN_RISE_CLR 0x88
#define TWL4030_USB_OTHER_INT_EN_FALL 0x89
#define TWL4030_USB_OTHER_INT_EN_FALL_SET 0x8A
#define TWL4030_USB_OTHER_INT_EN_FALL_CLR 0x8B
#define TWL4030_USB_OTHER_INT_STS 0x8C
#define TWL4030_USB_OTHER_INT_LATCH 0x8D
#define TWL4030_USB_ID_STATUS 0x96
#define TWL4030_USB_CARKIT_SM_1_INT_EN 0x97
#define TWL4030_USB_CARKIT_SM_1_INT_EN_SET 0x98
#define TWL4030_USB_CARKIT_SM_1_INT_EN_CLR 0x99
#define TWL4030_USB_CARKIT_SM_1_INT_STS 0x9A
#define TWL4030_USB_CARKIT_SM_1_INT_LATCH 0x9B
#define TWL4030_USB_CARKIT_SM_2_INT_EN 0x9C
#define TWL4030_USB_CARKIT_SM_2_INT_EN_SET 0x9D
#define TWL4030_USB_CARKIT_SM_2_INT_EN_CLR 0x9E
#define TWL4030_USB_CARKIT_SM_2_INT_STS 0x9F
#define TWL4030_USB_CARKIT_SM_2_INT_LATCH 0xA0
#define TWL4030_USB_CARKIT_SM_CTRL 0xA1
#define TWL4030_USB_CARKIT_SM_CTRL_SET 0xA2
#define TWL4030_USB_CARKIT_SM_CTRL_CLR 0xA3
#define TWL4030_USB_CARKIT_SM_CMD 0xA4
#define TWL4030_USB_CARKIT_SM_CMD_SET 0xA5
#define TWL4030_USB_CARKIT_SM_CMD_CLR 0xA6
#define TWL4030_USB_CARKIT_SM_CMD_STS 0xA7
#define TWL4030_USB_CARKIT_SM_STATUS 0xA8
#define TWL4030_USB_CARKIT_SM_ERR_STATUS 0xAA
#define TWL4030_USB_CARKIT_SM_CTRL_STATE 0xAB
#define TWL4030_USB_POWER_CTRL 0xAC
#define TWL4030_USB_POWER_CTRL_SET 0xAD
#define TWL4030_USB_POWER_CTRL_CLR 0xAE
#define TWL4030_USB_OTHER_IFC_CTRL2 0xAF
#define TWL4030_USB_OTHER_IFC_CTRL2_SET 0xB0
#define TWL4030_USB_OTHER_IFC_CTRL2_CLR 0xB1
#define TWL4030_USB_REG_CTRL_EN 0xB2
#define TWL4030_USB_REG_CTRL_EN_SET 0xB3
#define TWL4030_USB_REG_CTRL_EN_CLR 0xB4
#define TWL4030_USB_REG_CTRL_ERROR 0xB5
#define TWL4030_USB_OTHER_FUNC_CTRL2 0xB8
#define TWL4030_USB_OTHER_FUNC_CTRL2_SET 0xB9
#define TWL4030_USB_OTHER_FUNC_CTRL2_CLR 0xBA
#define TWL4030_USB_CARKIT_ANA_CTRL 0xBB
#define TWL4030_USB_CARKIT_ANA_CTRL_SET 0xBC
#define TWL4030_USB_CARKIT_ANA_CTRL_CLR 0xBD
#define TWL4030_USB_VBUS_DEBOUNCE 0xC0
#define TWL4030_USB_ID_DEBOUNCE 0xC1
#define TWL4030_USB_TPH_DP_CON_MIN 0xC2
#define TWL4030_USB_TPH_DP_CON_MAX 0xC3
#define TWL4030_USB_TCR_DP_CON_MIN 0xC4
#define TWL4030_USB_TCR_DP_CON_MAX 0xC5
#define TWL4030_USB_TPH_DP_PD_SHORT 0xC6
#define TWL4030_USB_TPH_CMD_DLY 0xC7
#define TWL4030_USB_TPH_DET_RST 0xC8
#define TWL4030_USB_TPH_AUD_BIAS 0xC9
#define TWL4030_USB_TCR_UART_DET_MIN 0xCA
#define TWL4030_USB_TCR_UART_DET_MAX 0xCB
#define TWL4030_USB_TPH_ID_INT_PW 0xCD
#define TWL4030_USB_TACC_ID_INT_WAIT 0xCE
#define TWL4030_USB_TACC_ID_INT_PW 0xCF
#define TWL4030_USB_TPH_CMD_WAIT 0xD0
#define TWL4030_USB_TPH_ACK_WAIT 0xD1
#define TWL4030_USB_TPH_DP_DISC_DET 0xD2
#define TWL4030_USB_VBAT_TIMER 0xD3
#define TWL4030_USB_CARKIT_4W_DEBUG 0xE0
#define TWL4030_USB_CARKIT_5W_DEBUG 0xE1
#define TWL4030_USB_PHY_PWR_CTRL 0xFD
#define TWL4030_USB_PHY_CLK_CTRL 0xFE
#define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF
/*
* Convience functions to read and write from TWL4030
*
* chip_no is the i2c address, it must be one of the chip addresses
* defined at the top of this file with the prefix TWL4030_CHIP_
* examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD
*
* val is the data either written to or read from the twl4030
*
* reg is the register to act on, it must be one of the defines
* above and with the format TWL4030_<chip suffix>_<register name>
* examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
* TWL4030_LED_LEDEN.
*/
static inline int twl4030_i2c_write_u8(u8 chip_no, u8 val, u8 reg)
{
return i2c_write(chip_no, reg, 1, &val, 1);
}
static inline int twl4030_i2c_read_u8(u8 chip_no, u8 *val, u8 reg)
{
return i2c_read(chip_no, reg, 1, val, 1);
}
/*
* Power
*/
/* For hardware resetting */
void twl4030_power_reset_init(void);
/* For setting device group and voltage */
void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
u8 dev_grp, u8 dev_grp_sel);
/* For initializing power device */
void twl4030_power_init(void);
/* For initializing mmc power */
void twl4030_power_mmc_init(void);
/*
* LED
*/
void twl4030_led_init(unsigned char ledon_mask);
/*
* USB
*/
int twl4030_usb_ulpi_init(void);
#endif /* TWL4030_H */
|
1001-study-uboot
|
include/twl4030.h
|
C
|
gpl3
| 21,492
|
/*
* Keep all the ugly #ifdef for system stuff here
*/
#ifndef __COMPILER_H__
#define __COMPILER_H__
#include <stddef.h>
#ifdef USE_HOSTCC
#if defined(__BEOS__) || \
defined(__NetBSD__) || \
defined(__FreeBSD__) || \
defined(__sun__) || \
defined(__APPLE__)
# include <inttypes.h>
#elif defined(__linux__) || defined(__WIN32__) || defined(__MINGW32__)
# include <stdint.h>
#endif
#include <errno.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#if !defined(__WIN32__) && !defined(__MINGW32__)
# include <sys/mman.h>
#endif
/* Not all systems (like Windows) has this define, and yes
* we do replace/emulate mmap() on those systems ...
*/
#ifndef MAP_FAILED
# define MAP_FAILED ((void *)-1)
#endif
#include <fcntl.h>
#ifndef O_BINARY /* should be define'd on __WIN32__ */
#define O_BINARY 0
#endif
#ifdef __linux__
# include <endian.h>
# include <byteswap.h>
#elif defined(__MACH__) || defined(__FreeBSD__)
# include <machine/endian.h>
typedef unsigned long ulong;
#endif
typedef uint8_t __u8;
typedef uint16_t __u16;
typedef uint32_t __u32;
typedef unsigned int uint;
#define uswap_16(x) \
((((x) & 0xff00) >> 8) | \
(((x) & 0x00ff) << 8))
#define uswap_32(x) \
((((x) & 0xff000000) >> 24) | \
(((x) & 0x00ff0000) >> 8) | \
(((x) & 0x0000ff00) << 8) | \
(((x) & 0x000000ff) << 24))
#define _uswap_64(x, sfx) \
((((x) & 0xff00000000000000##sfx) >> 56) | \
(((x) & 0x00ff000000000000##sfx) >> 40) | \
(((x) & 0x0000ff0000000000##sfx) >> 24) | \
(((x) & 0x000000ff00000000##sfx) >> 8) | \
(((x) & 0x00000000ff000000##sfx) << 8) | \
(((x) & 0x0000000000ff0000##sfx) << 24) | \
(((x) & 0x000000000000ff00##sfx) << 40) | \
(((x) & 0x00000000000000ff##sfx) << 56))
#if defined(__GNUC__)
# define uswap_64(x) _uswap_64(x, ull)
#else
# define uswap_64(x) _uswap_64(x, )
#endif
#if __BYTE_ORDER == __LITTLE_ENDIAN
# define cpu_to_le16(x) (x)
# define cpu_to_le32(x) (x)
# define cpu_to_le64(x) (x)
# define le16_to_cpu(x) (x)
# define le32_to_cpu(x) (x)
# define le64_to_cpu(x) (x)
# define cpu_to_be16(x) uswap_16(x)
# define cpu_to_be32(x) uswap_32(x)
# define cpu_to_be64(x) uswap_64(x)
# define be16_to_cpu(x) uswap_16(x)
# define be32_to_cpu(x) uswap_32(x)
# define be64_to_cpu(x) uswap_64(x)
#else
# define cpu_to_le16(x) uswap_16(x)
# define cpu_to_le32(x) uswap_32(x)
# define cpu_to_le64(x) uswap_64(x)
# define le16_to_cpu(x) uswap_16(x)
# define le32_to_cpu(x) uswap_32(x)
# define le64_to_cpu(x) uswap_64(x)
# define cpu_to_be16(x) (x)
# define cpu_to_be32(x) (x)
# define cpu_to_be64(x) (x)
# define be16_to_cpu(x) (x)
# define be32_to_cpu(x) (x)
# define be64_to_cpu(x) (x)
#endif
#else /* !USE_HOSTCC */
#include <linux/string.h>
#include <linux/types.h>
#include <asm/byteorder.h>
#if __SIZEOF_LONG__ == 8
# define __WORDSIZE 64
#elif __SIZEOF_LONG__ == 4
# define __WORDSIZE 32
#else
/*
* Assume 32-bit for now - only newer toolchains support this feature and
* this is only required for sandbox support at present.
*/
#define __WORDSIZE 32
#endif
/* Type for `void *' pointers. */
typedef unsigned long int uintptr_t;
#endif /* USE_HOSTCC */
/* compiler options */
#define uninitialized_var(x) x = x
#define likely(x) __builtin_expect(!!(x), 1)
#define unlikely(x) __builtin_expect(!!(x), 0)
#endif
|
1001-study-uboot
|
include/compiler.h
|
C
|
gpl3
| 3,341
|
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* The purpose of this code is to signal the operational status of a
* target which usually boots over the network; while running in
* PCBoot, a status LED is blinking. As soon as a valid BOOTP reply
* message has been received, the LED is turned off. The Linux
* kernel, once it is running, will start blinking the LED again,
* with another frequency.
*/
#ifndef _STATUS_LED_H_
#define _STATUS_LED_H_
#ifdef CONFIG_STATUS_LED
#define STATUS_LED_OFF 0
#define STATUS_LED_BLINKING 1
#define STATUS_LED_ON 2
void status_led_tick (unsigned long timestamp);
void status_led_set (int led, int state);
/***** TQM8xxL ********************************************************/
#if defined(CONFIG_TQM8xxL)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** MVS v1 **********************************************************/
#elif (defined(CONFIG_MVS) && CONFIG_MVS < 2)
# define STATUS_LED_PAR im_ioport.iop_pdpar
# define STATUS_LED_DIR im_ioport.iop_pddir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pddat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** ETX_094 ********************************************************/
#elif defined(CONFIG_ETX094)
# define STATUS_LED_PAR im_ioport.iop_pdpar
# define STATUS_LED_DIR im_ioport.iop_pddir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pddat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** GEN860T *********************************************************/
#elif defined(CONFIG_GEN860T)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x0800 /* Red LED 0 is on PA.4 */
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
# define STATUS_LED_STATE STATUS_LED_OFF
# define STATUS_LED_BIT1 0x0400 /* Grn LED 1 is on PA.5 */
# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 8)
# define STATUS_LED_STATE1 STATUS_LED_BLINKING
# define STATUS_LED_BIT2 0x0080 /* Red LED 2 is on PA.8 */
# define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 4)
# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_BIT3 0x0040 /* Grn LED 3 is on PA.9 */
# define STATUS_LED_PERIOD3 (CONFIG_SYS_HZ / 4)
# define STATUS_LED_STATE3 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 1 /* Boot status on LED 1 */
/***** IVMS8 **********************************************************/
#elif defined(CONFIG_IVMS8)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ)
# define STATUS_LED_STATE STATUS_LED_OFF
# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
/* IDE LED usable for other purposes, too */
# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ)
# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_ILOCK_SWITCH 0x00800000 /* ILOCK switch in IRQ4 */
# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */
# define STATUS_LED_YELLOW 0
# define STATUS_LED_GREEN 1
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
/***** IVML24 *********************************************************/
#elif defined(CONFIG_IVML24)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000010 /* LED 0 is on PB.27 */
# define STATUS_LED_PERIOD (1 * CONFIG_SYS_HZ)
# define STATUS_LED_STATE STATUS_LED_OFF
# define STATUS_LED_BIT1 0x00000020 /* LED 1 is on PB.26 */
# define STATUS_LED_PERIOD1 (1 * CONFIG_SYS_HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
/* IDE LED usable for other purposes, too */
# define STATUS_LED_BIT2 0x00000008 /* LED 2 is on PB.28 */
# define STATUS_LED_PERIOD2 (1 * CONFIG_SYS_HZ)
# define STATUS_LED_STATE2 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_ILOCK_SWITCH 0x00004000 /* ILOCK is on PB.17 */
# define STATUS_ILOCK_PERIOD (CONFIG_SYS_HZ / 10) /* about every 100 ms */
# define STATUS_LED_YELLOW 0
# define STATUS_LED_GREEN 1
# define STATUS_LED_BOOT 2 /* IDE LED used for boot status */
/***** LANTEC *********************************************************/
#elif defined(CONFIG_LANTEC)
# define STATUS_LED_PAR im_ioport.iop_pdpar
# define STATUS_LED_DIR im_ioport.iop_pddir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pddat
# if CONFIG_LATEC < 2
# define STATUS_LED_BIT 0x1000
# else
# define STATUS_LED_BIT 0x0800
# endif
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** ICU862 ********************************************************/
#elif defined(CONFIG_ICU862)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x4000 /* LED 0 is on PA.1 */
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x1000 /* LED 1 is on PA.3 */
# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** Someone else defines these *************************************/
#elif defined(STATUS_LED_PAR)
/*
* ADVICE: Define in your board configuration file rather than
* filling this file up with lots of custom board stuff.
*/
/***** NetVia ********************************************************/
#elif defined(CONFIG_NETVIA)
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define STATUS_LED_PAR im_ioport.iop_pdpar
#define STATUS_LED_DIR im_ioport.iop_pddir
#undef STATUS_LED_ODR
#define STATUS_LED_DAT im_ioport.iop_pddat
# define STATUS_LED_BIT 0x0080 /* PD.8 */
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x0040 /* PD.9 */
# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE1 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#endif
/***** CMI ********************************************************/
#elif defined(CONFIG_CMI)
# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr
# define STATUS_LED_DAT im_mios.mios_mpiosm32dr
# define STATUS_LED_BIT 0x2000 /* Select one of the 16 possible*/
/* MIOS outputs */
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Blinking periode is 500 ms */
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** KUP4K, KUP4X ****************************************************/
#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
# define STATUS_LED_PAR im_ioport.iop_papar
# define STATUS_LED_DIR im_ioport.iop_padir
# define STATUS_LED_ODR im_ioport.iop_paodr
# define STATUS_LED_DAT im_ioport.iop_padat
# define STATUS_LED_BIT 0x00000300 /* green + red PA[8]=yellow, PA[7]=red, PA[6]=green */
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#elif defined(CONFIG_SVM_SC8xx)
# define STATUS_LED_PAR im_cpm.cp_pbpar
# define STATUS_LED_DIR im_cpm.cp_pbdir
# define STATUS_LED_ODR im_cpm.cp_pbodr
# define STATUS_LED_DAT im_cpm.cp_pbdat
# define STATUS_LED_BIT 0x00000001
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** RBC823 ********************************************************/
#elif defined(CONFIG_RBC823)
# define STATUS_LED_PAR im_ioport.iop_pcpar
# define STATUS_LED_DIR im_ioport.iop_pcdir
# undef STATUS_LED_ODR
# define STATUS_LED_DAT im_ioport.iop_pcdat
# define STATUS_LED_BIT 0x0002 /* LED 0 is on PC.14 */
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x0004 /* LED 1 is on PC.13 */
# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
# define STATUS_LED_STATE1 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
/***** NetPhone ********************************************************/
#elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
/* XXX empty just to avoid the error */
/***** STx XTc ********************************************************/
#elif defined(CONFIG_STXXTC)
/* XXX empty just to avoid the error */
/************************************************************************/
#elif defined(CONFIG_NIOS2)
/* XXX empty just to avoid the error */
/************************************************************************/
#elif defined(CONFIG_V38B)
# define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#elif defined(CONFIG_MOTIONPRO)
#define STATUS_LED_BIT ((vu_long *) MPC5XXX_GPT6_ENABLE)
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 10)
#define STATUS_LED_STATE STATUS_LED_BLINKING
#define STATUS_LED_BIT1 ((vu_long *) MPC5XXX_GPT7_ENABLE)
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 10)
#define STATUS_LED_STATE1 STATUS_LED_OFF
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#elif defined(CONFIG_BOARD_SPECIFIC_LED)
/* led_id_t is unsigned long mask */
typedef unsigned long led_id_t;
extern void __led_toggle (led_id_t mask);
extern void __led_init (led_id_t mask, int state);
extern void __led_set (led_id_t mask, int state);
#else
# error Status LED configuration missing
#endif
/************************************************************************/
#ifndef CONFIG_BOARD_SPECIFIC_LED
# include <asm/status_led.h>
#endif
/*
* Coloured LEDs API
*/
#ifndef __ASSEMBLY__
extern void coloured_LED_init (void);
extern void red_led_on(void);
extern void red_led_off(void);
extern void green_led_on(void);
extern void green_led_off(void);
extern void yellow_led_on(void);
extern void yellow_led_off(void);
extern void blue_led_on(void);
extern void blue_led_off(void);
#else
.extern LED_init
.extern red_led_on
.extern red_led_off
.extern yellow_led_on
.extern yellow_led_off
.extern green_led_on
.extern green_led_off
.extern blue_led_on
.extern blue_led_off
#endif
#endif /* CONFIG_STATUS_LED */
#endif /* _STATUS_LED_H_ */
|
1001-study-uboot
|
include/status_led.h
|
C
|
gpl3
| 13,261
|
/*
* drivers/usb/gadget/s3c_udc.h
* Samsung S3C on-chip full/high speed USB device controllers
* Copyright (C) 2005 for Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __S3C_USB_GADGET
#define __S3C_USB_GADGET
#include <asm/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/list.h>
#include <usb/lin_gadget_compat.h>
#define PHY0_SLEEP (1 << 5)
/*-------------------------------------------------------------------------*/
/* DMA bounce buffer size, 16K is enough even for mass storage */
#define DMA_BUFFER_SIZE (4096*4)
#define EP0_FIFO_SIZE 64
#define EP_FIFO_SIZE 512
#define EP_FIFO_SIZE2 1024
/* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */
#define S3C_MAX_ENDPOINTS 4
#define S3C_MAX_HW_ENDPOINTS 16
#define WAIT_FOR_SETUP 0
#define DATA_STATE_XMIT 1
#define DATA_STATE_NEED_ZLP 2
#define WAIT_FOR_OUT_STATUS 3
#define DATA_STATE_RECV 4
#define WAIT_FOR_COMPLETE 5
#define WAIT_FOR_OUT_COMPLETE 6
#define WAIT_FOR_IN_COMPLETE 7
#define WAIT_FOR_NULL_COMPLETE 8
#define TEST_J_SEL 0x1
#define TEST_K_SEL 0x2
#define TEST_SE0_NAK_SEL 0x3
#define TEST_PACKET_SEL 0x4
#define TEST_FORCE_ENABLE_SEL 0x5
/* ************************************************************************* */
/* IO
*/
enum ep_type {
ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
};
struct s3c_ep {
struct usb_ep ep;
struct s3c_udc *dev;
const struct usb_endpoint_descriptor *desc;
struct list_head queue;
unsigned long pio_irqs;
int len;
void *dma_buf;
u8 stopped;
u8 bEndpointAddress;
u8 bmAttributes;
enum ep_type ep_type;
int fifo_num;
};
struct s3c_request {
struct usb_request req;
struct list_head queue;
};
struct s3c_udc {
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
struct s3c_plat_otg_data *pdata;
void *dma_buf[S3C_MAX_ENDPOINTS+1];
dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1];
int ep0state;
struct s3c_ep ep[S3C_MAX_ENDPOINTS];
unsigned char usb_address;
unsigned req_pending:1, req_std:1, req_config:1;
};
extern struct s3c_udc *the_controller;
#define ep_is_in(EP) (((EP)->bEndpointAddress&USB_DIR_IN) == USB_DIR_IN)
#define ep_index(EP) ((EP)->bEndpointAddress&0xF)
#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
/*-------------------------------------------------------------------------*/
/* #define DEBUG_UDC */
#ifdef DEBUG_UDC
#define DBG(stuff...) printf("udc: " stuff)
#else
#define DBG(stuff...) do {} while (0)
#endif
#ifdef DEBUG_S3C_UDC_SETUP
#define DEBUG_SETUP(fmt, args...) printk(fmt, ##args)
#else
#define DEBUG_SETUP(fmt, args...) do {} while (0)
#endif
#ifdef DEBUG_S3C_UDC_EP0
#define DEBUG_EP0(fmt, args...) printk(fmt, ##args)
#else
#define DEBUG_EP0(fmt, args...) do {} while (0)
#endif
#ifdef DEBUG_S3C_UDC_ISR
#define DEBUG_ISR 1
#else
#define DEBUG_ISR 0
#endif
#ifdef DEBUG_S3C_UDC_OUT_EP
#define DEBUG_OUT_EP(fmt, args...) printk(fmt, ##args)
#else
#define DEBUG_OUT_EP(fmt, args...) do {} while (0)
#endif
#ifdef DEBUG_S3C_UDC_IN_EP
#define DEBUG_IN_EP 1
#else
#define DEBUG_IN_EP 0
#endif
#if defined(DEBUG_S3C_UDC_SETUP) || defined(DEBUG_S3C_UDC_EP0) || \
defined(DEBUG_S3C_UDC_ISR) || defined(DEBUG_S3C_UDC_OUT_EP) || \
defined(DEBUG_S3C_UDC_IN_EP) || defined(DEBUG_S3C_UDC)
#define DEBUG
#endif
#define ERR(stuff...) printf("ERR udc: " stuff)
#define WARN(stuff...) printf("WARNING udc: " stuff)
#define INFO(stuff...) printf("INFO udc: " stuff)
extern void otg_phy_init(struct s3c_udc *dev);
extern void otg_phy_off(struct s3c_udc *dev);
extern void s3c_udc_ep_set_stall(struct s3c_ep *ep);
extern int s3c_udc_probe(struct s3c_plat_otg_data *pdata);
struct s3c_plat_otg_data {
int (*phy_control)(int on);
unsigned int regs_phy;
unsigned int regs_otg;
unsigned int usb_phy_ctrl;
unsigned int usb_flags;
};
#endif
|
1001-study-uboot
|
include/usb/s3c_udc.h
|
C
|
gpl3
| 4,525
|
/*
* Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
* Copyright (c) 2005 MontaVista Software
* Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _EHCI_FSL_H
#define _EHCI_FSL_H
#include <asm/processor.h>
/* Global offsets */
#define FSL_SKIP_PCI 0x100
/* offsets for the non-ehci registers in the FSL SOC USB controller */
#define FSL_SOC_USB_ULPIVP 0x170
#define FSL_SOC_USB_PORTSC1 0x184
#define PORT_PTS_MSK (3 << 30)
#define PORT_PTS_UTMI (0 << 30)
#define PORT_PTS_ULPI (2 << 30)
#define PORT_PTS_SERIAL (3 << 30)
#define PORT_PTS_PTW (1 << 28)
#define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */
#define PORT_PTS_PHCD (1 << 23)
#define PORT_PP (1 << 12)
#define PORT_PR (1 << 8)
/* USBMODE Register bits */
#define CM_IDLE (0 << 0)
#define CM_RESERVED (1 << 0)
#define CM_DEVICE (2 << 0)
#define CM_HOST (3 << 0)
#define ES_BE (1 << 2) /* Big Endian Select, default is LE */
#define USBMODE_RESERVED_2 (0 << 2)
#define SLOM (1 << 3)
#define SDIS (1 << 4)
/* CONTROL Register bits */
#define ULPI_INT_EN (1 << 0)
#define WU_INT_EN (1 << 1)
#define USB_EN (1 << 2)
#define LSF_EN (1 << 3)
#define KEEP_OTG_ON (1 << 4)
#define OTG_PORT (1 << 5)
#define REFSEL_12MHZ (0 << 6)
#define REFSEL_16MHZ (1 << 6)
#define REFSEL_48MHZ (2 << 6)
#define PLL_RESET (1 << 8)
#define UTMI_PHY_EN (1 << 9)
#define PHY_CLK_SEL_UTMI (0 << 10)
#define PHY_CLK_SEL_ULPI (1 << 10)
#define CLKIN_SEL_USB_CLK (0 << 11)
#define CLKIN_SEL_USB_CLK2 (1 << 11)
#define CLKIN_SEL_SYS_CLK (2 << 11)
#define CLKIN_SEL_SYS_CLK2 (3 << 11)
#define RESERVED_18 (0 << 13)
#define RESERVED_17 (0 << 14)
#define RESERVED_16 (0 << 15)
#define WU_INT (1 << 16)
#define PHY_CLK_VALID (1 << 17)
#define FSL_SOC_USB_PORTSC2 0x188
/* OTG Status Control Register bits */
#define FSL_SOC_USB_OTGSC 0x1a4
#define CTRL_VBUS_DISCHARGE (0x1<<0)
#define CTRL_VBUS_CHARGE (0x1<<1)
#define CTRL_OTG_TERMINATION (0x1<<3)
#define CTRL_DATA_PULSING (0x1<<4)
#define CTRL_ID_PULL_EN (0x1<<5)
#define HA_DATA_PULSE (0x1<<6)
#define HA_BA (0x1<<7)
#define STS_USB_ID (0x1<<8)
#define STS_A_VBUS_VALID (0x1<<9)
#define STS_A_SESSION_VALID (0x1<<10)
#define STS_B_SESSION_VALID (0x1<<11)
#define STS_B_SESSION_END (0x1<<12)
#define STS_1MS_TOGGLE (0x1<<13)
#define STS_DATA_PULSING (0x1<<14)
#define INTSTS_USB_ID (0x1<<16)
#define INTSTS_A_VBUS_VALID (0x1<<17)
#define INTSTS_A_SESSION_VALID (0x1<<18)
#define INTSTS_B_SESSION_VALID (0x1<<19)
#define INTSTS_B_SESSION_END (0x1<<20)
#define INTSTS_1MS (0x1<<21)
#define INTSTS_DATA_PULSING (0x1<<22)
#define INTR_USB_ID_EN (0x1<<24)
#define INTR_A_VBUS_VALID_EN (0x1<<25)
#define INTR_A_SESSION_VALID_EN (0x1<<26)
#define INTR_B_SESSION_VALID_EN (0x1<<27)
#define INTR_B_SESSION_END_EN (0x1<<28)
#define INTR_1MS_TIMER_EN (0x1<<29)
#define INTR_DATA_PULSING_EN (0x1<<30)
#define INTSTS_MASK (0x00ff0000)
/* USBCMD Bits of interest */
#define EHCI_FSL_USBCMD_RST (1 << 1)
#define EHCI_FSL_USBCMD_RS (1 << 0)
#define INTERRUPT_ENABLE_BITS_MASK \
(INTR_USB_ID_EN | \
INTR_1MS_TIMER_EN | \
INTR_A_VBUS_VALID_EN | \
INTR_A_SESSION_VALID_EN | \
INTR_B_SESSION_VALID_EN | \
INTR_B_SESSION_END_EN | \
INTR_DATA_PULSING_EN)
#define INTERRUPT_STATUS_BITS_MASK \
(INTSTS_USB_ID | \
INTR_1MS_TIMER_EN | \
INTSTS_A_VBUS_VALID | \
INTSTS_A_SESSION_VALID | \
INTSTS_B_SESSION_VALID | \
INTSTS_B_SESSION_END | \
INTSTS_DATA_PULSING)
#define FSL_SOC_USB_USBMODE 0x1a8
#define USBGENCTRL 0x200 /* NOTE: big endian */
#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */
#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/
#define GC_PPP (1 << 3) /* Port Power Polarity */
#define GC_PFP (1 << 2) /* Power Fault Polarity */
#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */
#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */
#define ISIPHYCTRL 0x204 /* NOTE: big endian */
#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */
#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */
#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */
#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */
#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */
#define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
#define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
#define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
#define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
#define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
#define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
#define SNOOP_SIZE_2GB 0x1e
/* System Clock Control Register */
#define MPC83XX_SCCR_USB_MASK 0x00f00000
#define MPC83XX_SCCR_USB_DRCM_11 0x00300000
#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
#if defined(CONFIG_MPC83xx)
#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
#elif defined(CONFIG_MPC85xx)
#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
#elif defined(CONFIG_MPC512X)
#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
#endif
/*
* USB Registers
*/
struct usb_ehci {
u32 id; /* 0x000 - Identification register */
u32 hwgeneral; /* 0x004 - General hardware parameters */
u32 hwhost; /* 0x008 - Host hardware parameters */
u32 hwdevice; /* 0x00C - Device hardware parameters */
u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */
u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */
u8 res1[0x68];
u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */
u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */
u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */
u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
u32 sbuscfg; /* 0x090 - System Bus Interface Control */
u8 res2[0x6C];
u8 caplength; /* 0x100 - Capability Register Length */
u8 res3[0x1];
u16 hciversion; /* 0x102 - Host Interface Version */
u32 hcsparams; /* 0x104 - Host Structural Parameters */
u32 hccparams; /* 0x108 - Host Capability Parameters */
u8 res4[0x14];
u32 dciversion; /* 0x120 - Device Interface Version */
u32 dciparams; /* 0x124 - Device Controller Params */
u8 res5[0x18];
u32 usbcmd; /* 0x140 - USB Command */
u32 usbsts; /* 0x144 - USB Status */
u32 usbintr; /* 0x148 - USB Interrupt Enable */
u32 frindex; /* 0x14C - USB Frame Index */
u8 res6[0x4];
u32 perlistbase; /* 0x154 - Periodic List Base
- USB Device Address */
u32 ep_list_addr; /* 0x158 - Next Asynchronous List
- End Point Address */
u8 res7[0x4];
u32 burstsize; /* 0x160 - Programmable Burst Size */
#define FSL_EHCI_TXPBURST(X) ((X) << 8)
#define FSL_EHCI_RXPBURST(X) (X)
u32 txfilltuning; /* 0x164 - Host TT Transmit
pre-buffer packet tuning */
u8 res8[0x8];
u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
u8 res9[0xc];
u32 config_flag; /* 0x180 - Configured Flag Register */
u32 portsc; /* 0x184 - Port status/control */
u8 res10[0x1C];
u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
u32 usbmode; /* 0x1a8 - USB Device Mode */
u32 epsetupstat; /* 0x1ac - End Point Setup Status */
u32 epprime; /* 0x1b0 - End Point Init Status */
u32 epflush; /* 0x1b4 - End Point De-initlialize */
u32 epstatus; /* 0x1b8 - End Point Status */
u32 epcomplete; /* 0x1bc - End Point Complete */
u32 epctrl0; /* 0x1c0 - End Point Control 0 */
u32 epctrl1; /* 0x1c4 - End Point Control 1 */
u32 epctrl2; /* 0x1c8 - End Point Control 2 */
u32 epctrl3; /* 0x1cc - End Point Control 3 */
u32 epctrl4; /* 0x1d0 - End Point Control 4 */
u32 epctrl5; /* 0x1d4 - End Point Control 5 */
u8 res11[0x28];
u32 usbgenctrl; /* 0x200 - USB General Control */
u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
u8 res12[0x1F8];
u32 snoop1; /* 0x400 - Snoop 1 */
u32 snoop2; /* 0x404 - Snoop 2 */
u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
u32 prictrl; /* 0x40c - Priority Control */
u32 sictrl; /* 0x410 - System Interface Control */
u8 res13[0xEC];
u32 control; /* 0x500 - Control */
u8 res14[0xafc];
};
/*
* For MXC SOCs
*/
#define MXC_EHCI_POWER_PINS_ENABLED (1 << 5)
#define MXC_EHCI_TTL_ENABLED (1 << 6)
#define MXC_EHCI_INTERNAL_PHY (1 << 7)
/* Board-specific initialization */
int board_ehci_hcd_init(int port);
/* CPU-specific abstracted-out IOMUX init */
#ifdef CONFIG_MX51
void setup_iomux_usb_h1(void);
void setup_iomux_usb_h2(void);
#endif
#endif /* _EHCI_FSL_H */
|
1001-study-uboot
|
include/usb/ehci-fsl.h
|
C
|
gpl3
| 9,157
|
/*
* Copyright (c) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* This is a Linux kernel compatibility layer for USB Gadget
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __LIN_COMPAT_H__
#define __LIN_COMPAT_H__
/* common */
#define spin_lock_init(...)
#define spin_lock(...)
#define spin_lock_irqsave(lock, flags) do { debug("%lu\n", flags); } while (0)
#define spin_unlock(...)
#define spin_unlock_irqrestore(lock, flags) do {flags = 0; } while (0)
#define disable_irq(...)
#define enable_irq(...)
#define mutex_init(...)
#define mutex_lock(...)
#define mutex_unlock(...)
#define WARN_ON(x) if (x) {printf("WARNING in %s line %d\n" \
, __FILE__, __LINE__); }
#define KERN_WARNING
#define KERN_ERR
#define KERN_NOTICE
#define KERN_DEBUG
#define GFP_KERNEL 0
#define IRQ_HANDLED 1
#define ENOTSUPP 524 /* Operation is not supported */
#define kmalloc(size, type) memalign(CONFIG_SYS_CACHELINE_SIZE, size)
#define kfree(addr) free(addr)
#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
#define __iomem
#define min_t min
#define dma_cache_maint(addr, size, mode) cache_flush()
void cache_flush(void);
#endif /* __LIN_COMPAT_H__ */
|
1001-study-uboot
|
include/usb/lin_gadget_compat.h
|
C
|
gpl3
| 1,886
|
/*
* Generic ULPI interface.
*
* Copyright (C) 2011 Jana Rapava <fermata7@gmail.com>
* Copyright (C) 2011 CompuLab, Ltd. <www.compulab.co.il>
*
* Authors: Jana Rapava <fermata7@gmail.com>
* Igor Grinberg <grinberg@compulab.co.il>
*
* Register offsets taken from:
* linux/include/linux/usb/ulpi.h
*
* Original Copyrights follow:
* Copyright (C) 2010 Nokia Corporation
*
* This software is distributed under the terms of the GNU General
* Public License ("GPL") as published by the Free Software Foundation,
* version 2 of that License.
*/
#ifndef __USB_ULPI_H__
#define __USB_ULPI_H__
#define ULPI_ERROR (1 << 8) /* overflow from any register value */
#ifndef CONFIG_USB_ULPI_TIMEOUT
#define CONFIG_USB_ULPI_TIMEOUT 1000 /* timeout in us */
#endif
/*
* Initialize the ULPI transciever and check the interface integrity.
* @ulpi_viewport - the address of the ULPI viewport register.
*
* returns 0 on success, ULPI_ERROR on failure.
*/
int ulpi_init(u32 ulpi_viewport);
/*
* Select transceiver speed.
* @speed - ULPI_FC_HIGH_SPEED, ULPI_FC_FULL_SPEED (default),
* ULPI_FC_LOW_SPEED, ULPI_FC_FS4LS
* returns 0 on success, ULPI_ERROR on failure.
*/
int ulpi_select_transceiver(u32 ulpi_viewport, unsigned speed);
/*
* Enable/disable VBUS.
* @ext_power - external VBUS supply is used (default is false)
* @ext_indicator - external VBUS over-current indicator is used
*
* returns 0 on success, ULPI_ERROR on failure.
*/
int ulpi_enable_vbus(u32 ulpi_viewport, int on, int ext_power, int ext_ind);
/*
* Enable/disable pull-down resistors on D+ and D- USB lines.
*
* returns 0 on success, ULPI_ERROR on failure.
*/
int ulpi_set_pd(u32 ulpi_viewport, int enable);
/*
* Select OpMode.
* @opmode - ULPI_FC_OPMODE_NORMAL (default), ULPI_FC_OPMODE_NONDRIVING,
* ULPI_FC_OPMODE_DISABLE_NRZI, ULPI_FC_OPMODE_NOSYNC_NOEOP
*
* returns 0 on success, ULPI_ERROR on failure.
*/
int ulpi_opmode_sel(u32 ulpi_viewport, unsigned opmode);
/*
* Switch to Serial Mode.
* @smode - ULPI_IFACE_6_PIN_SERIAL_MODE or ULPI_IFACE_3_PIN_SERIAL_MODE
*
* returns 0 on success, ULPI_ERROR on failure.
*
* Notes:
* Switches immediately to Serial Mode.
* To return from Serial Mode, STP line needs to be asserted.
*/
int ulpi_serial_mode_enable(u32 ulpi_viewport, unsigned smode);
/*
* Put PHY into low power mode.
*
* returns 0 on success, ULPI_ERROR on failure.
*
* Notes:
* STP line must be driven low to keep the PHY in suspend.
* To resume the PHY, STP line needs to be asserted.
*/
int ulpi_suspend(u32 ulpi_viewport);
/*
* Reset the transceiver. ULPI interface and registers are not affected.
*
* returns 0 on success, ULPI_ERROR on failure.
*/
int ulpi_reset(u32 ulpi_viewport);
/* ULPI access methods below must be implemented for each ULPI viewport. */
/*
* Write to the ULPI PHY register via the viewport.
* @reg - the ULPI register (one of the fields in struct ulpi_regs).
* @value - the value - only 8 lower bits are used, others ignored.
*
* returns 0 on success, ULPI_ERROR on failure.
*/
int ulpi_write(u32 ulpi_viewport, u8 *reg, u32 value);
/*
* Read the ULPI PHY register content via the viewport.
* @reg - the ULPI register (one of the fields in struct ulpi_regs).
*
* returns register content on success, ULPI_ERROR on failure.
*/
u32 ulpi_read(u32 ulpi_viewport, u8 *reg);
/*
* Wait for the reset to complete.
* The Link must not attempt to access the PHY until the reset has
* completed and DIR line is de-asserted.
*/
int ulpi_reset_wait(u32 ulpi_viewport);
/* Access Extended Register Set (indicator) */
#define ACCESS_EXT_REGS_OFFSET 0x2f /* read-write */
/* Vendor-specific */
#define VENDOR_SPEC_OFFSET 0x30
/*
* Extended Register Set
*
* Addresses 0x00-0x3F map directly to Immediate Register Set.
* Addresses 0x40-0x7F are reserved.
* Addresses 0x80-0xff are vendor-specific.
*/
#define EXT_VENDOR_SPEC_OFFSET 0x80
/* ULPI registers, bits and offsets definitions */
struct ulpi_regs {
/* Vendor ID and Product ID: 0x00 - 0x03 Read-only */
u8 vendor_id_low;
u8 vendor_id_high;
u8 product_id_low;
u8 product_id_high;
/* Function Control: 0x04 - 0x06 Read */
u8 function_ctrl; /* 0x04 Write */
u8 function_ctrl_set; /* 0x05 Set */
u8 function_ctrl_clear; /* 0x06 Clear */
/* Interface Control: 0x07 - 0x09 Read */
u8 iface_ctrl; /* 0x07 Write */
u8 iface_ctrl_set; /* 0x08 Set */
u8 iface_ctrl_clear; /* 0x09 Clear */
/* OTG Control: 0x0A - 0x0C Read */
u8 otg_ctrl; /* 0x0A Write */
u8 otg_ctrl_set; /* 0x0B Set */
u8 otg_ctrl_clear; /* 0x0C Clear */
/* USB Interrupt Enable Rising: 0x0D - 0x0F Read */
u8 usb_ie_rising; /* 0x0D Write */
u8 usb_ie_rising_set; /* 0x0E Set */
u8 usb_ie_rising_clear; /* 0x0F Clear */
/* USB Interrupt Enable Falling: 0x10 - 0x12 Read */
u8 usb_ie_falling; /* 0x10 Write */
u8 usb_ie_falling_set; /* 0x11 Set */
u8 usb_ie_falling_clear; /* 0x12 Clear */
/* USB Interrupt Status: 0x13 Read-only */
u8 usb_int_status;
/* USB Interrupt Latch: 0x14 Read-only with auto-clear */
u8 usb_int_latch;
/* Debug: 0x15 Read-only */
u8 debug;
/* Scratch Register: 0x16 - 0x18 Read */
u8 scratch; /* 0x16 Write */
u8 scratch_set; /* 0x17 Set */
u8 scratch_clear; /* 0x18 Clear */
/*
* Optional Carkit registers:
* Carkit Control: 0x19 - 0x1B Read
*/
u8 carkit_ctrl; /* 0x19 Write */
u8 carkit_ctrl_set; /* 0x1A Set */
u8 carkit_ctrl_clear; /* 0x1B Clear */
/* Carkit Interrupt Delay: 0x1C Read, Write */
u8 carkit_int_delay;
/* Carkit Interrupt Enable: 0x1D - 0x1F Read */
u8 carkit_ie; /* 0x1D Write */
u8 carkit_ie_set; /* 0x1E Set */
u8 carkit_ie_clear; /* 0x1F Clear */
/* Carkit Interrupt Status: 0x20 Read-only */
u8 carkit_int_status;
/* Carkit Interrupt Latch: 0x21 Read-only with auto-clear */
u8 carkit_int_latch;
/* Carkit Pulse Control: 0x22 - 0x24 Read */
u8 carkit_pulse_ctrl; /* 0x22 Write */
u8 carkit_pulse_ctrl_set; /* 0x23 Set */
u8 carkit_pulse_ctrl_clear; /* 0x24 Clear */
/*
* Other optional registers:
* Transmit Positive Width: 0x25 Read, Write
*/
u8 transmit_pos_width;
/* Transmit Negative Width: 0x26 Read, Write */
u8 transmit_neg_width;
/* Receive Polarity Recovery: 0x27 Read, Write */
u8 recv_pol_recovery;
/*
* Addresses 0x28 - 0x2E are reserved, so we use offsets
* for immediate registers with higher addresses
*/
};
/*
* Register Bits
*/
/* Function Control */
#define ULPI_FC_XCVRSEL_MASK (3 << 0)
#define ULPI_FC_HIGH_SPEED (0 << 0)
#define ULPI_FC_FULL_SPEED (1 << 0)
#define ULPI_FC_LOW_SPEED (2 << 0)
#define ULPI_FC_FS4LS (3 << 0)
#define ULPI_FC_TERMSELECT (1 << 2)
#define ULPI_FC_OPMODE_MASK (3 << 3)
#define ULPI_FC_OPMODE_NORMAL (0 << 3)
#define ULPI_FC_OPMODE_NONDRIVING (1 << 3)
#define ULPI_FC_OPMODE_DISABLE_NRZI (2 << 3)
#define ULPI_FC_OPMODE_NOSYNC_NOEOP (3 << 3)
#define ULPI_FC_RESET (1 << 5)
#define ULPI_FC_SUSPENDM (1 << 6)
/* Interface Control */
#define ULPI_IFACE_6_PIN_SERIAL_MODE (1 << 0)
#define ULPI_IFACE_3_PIN_SERIAL_MODE (1 << 1)
#define ULPI_IFACE_CARKITMODE (1 << 2)
#define ULPI_IFACE_CLOCKSUSPENDM (1 << 3)
#define ULPI_IFACE_AUTORESUME (1 << 4)
#define ULPI_IFACE_EXTVBUS_COMPLEMENT (1 << 5)
#define ULPI_IFACE_PASSTHRU (1 << 6)
#define ULPI_IFACE_PROTECT_IFC_DISABLE (1 << 7)
/* OTG Control */
#define ULPI_OTG_ID_PULLUP (1 << 0)
#define ULPI_OTG_DP_PULLDOWN (1 << 1)
#define ULPI_OTG_DM_PULLDOWN (1 << 2)
#define ULPI_OTG_DISCHRGVBUS (1 << 3)
#define ULPI_OTG_CHRGVBUS (1 << 4)
#define ULPI_OTG_DRVVBUS (1 << 5)
#define ULPI_OTG_DRVVBUS_EXT (1 << 6)
#define ULPI_OTG_EXTVBUSIND (1 << 7)
/*
* USB Interrupt Enable Rising,
* USB Interrupt Enable Falling,
* USB Interrupt Status and
* USB Interrupt Latch
*/
#define ULPI_INT_HOST_DISCONNECT (1 << 0)
#define ULPI_INT_VBUS_VALID (1 << 1)
#define ULPI_INT_SESS_VALID (1 << 2)
#define ULPI_INT_SESS_END (1 << 3)
#define ULPI_INT_IDGRD (1 << 4)
/* Debug */
#define ULPI_DEBUG_LINESTATE0 (1 << 0)
#define ULPI_DEBUG_LINESTATE1 (1 << 1)
/* Carkit Control */
#define ULPI_CARKIT_CTRL_CARKITPWR (1 << 0)
#define ULPI_CARKIT_CTRL_IDGNDDRV (1 << 1)
#define ULPI_CARKIT_CTRL_TXDEN (1 << 2)
#define ULPI_CARKIT_CTRL_RXDEN (1 << 3)
#define ULPI_CARKIT_CTRL_SPKLEFTEN (1 << 4)
#define ULPI_CARKIT_CTRL_SPKRIGHTEN (1 << 5)
#define ULPI_CARKIT_CTRL_MICEN (1 << 6)
/* Carkit Interrupt Enable */
#define ULPI_CARKIT_INT_EN_IDFLOAT_RISE (1 << 0)
#define ULPI_CARKIT_INT_EN_IDFLOAT_FALL (1 << 1)
#define ULPI_CARKIT_INT_EN_CARINTDET (1 << 2)
#define ULPI_CARKIT_INT_EN_DP_RISE (1 << 3)
#define ULPI_CARKIT_INT_EN_DP_FALL (1 << 4)
/* Carkit Interrupt Status and Latch */
#define ULPI_CARKIT_INT_IDFLOAT (1 << 0)
#define ULPI_CARKIT_INT_CARINTDET (1 << 1)
#define ULPI_CARKIT_INT_DP (1 << 2)
/* Carkit Pulse Control*/
#define ULPI_CARKIT_PLS_CTRL_TXPLSEN (1 << 0)
#define ULPI_CARKIT_PLS_CTRL_RXPLSEN (1 << 1)
#define ULPI_CARKIT_PLS_CTRL_SPKRLEFT_BIASEN (1 << 2)
#define ULPI_CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN (1 << 3)
#endif /* __USB_ULPI_H__ */
|
1001-study-uboot
|
include/usb/ulpi.h
|
C
|
gpl3
| 9,052
|
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MUSB_UDC_H__
#define __MUSB_UDC_H__
#include <usbdevice.h>
/* UDC level routines */
void udc_irq(void);
void udc_set_nak(int ep_num);
void udc_unset_nak(int ep_num);
int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
void udc_setup_ep(struct usb_device_instance *device, unsigned int id,
struct usb_endpoint_instance *endpoint);
void udc_connect(void);
void udc_disconnect(void);
void udc_enable(struct usb_device_instance *device);
void udc_disable(void);
void udc_startup_events(struct usb_device_instance *device);
int udc_init(void);
/* usbtty */
#ifdef CONFIG_USB_TTY
#define EP0_MAX_PACKET_SIZE 64 /* MUSB_EP0_FIFOSIZE */
#define UDC_INT_ENDPOINT 1
#define UDC_INT_PACKET_SIZE 64
#define UDC_OUT_ENDPOINT 2
#define UDC_OUT_PACKET_SIZE 64
#define UDC_IN_ENDPOINT 3
#define UDC_IN_PACKET_SIZE 64
#define UDC_BULK_PACKET_SIZE 64
#endif /* CONFIG_USB_TTY */
#endif /* __MUSB_UDC_H__ */
|
1001-study-uboot
|
include/usb/musb_udc.h
|
C
|
gpl3
| 1,727
|
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MV_UDC_H__
#define __MV_UDC_H__
#include <asm/byteorder.h>
#include <asm/errno.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
/* Endpoint 0 states */
#define EP0_IDLE 0
#define EP0_IN_DATA 1
#define EP0_OUT_DATA 2
#define EP0_XFER_COMPLETE 3
/* Endpoint parameters */
#define MAX_ENDPOINTS 4
#define EP_MAX_PACKET_SIZE 0x200
#define EP0_MAX_PACKET_SIZE 64
#define UDC_OUT_ENDPOINT 0x02
#define UDC_OUT_PACKET_SIZE EP_MAX_PACKET_SIZE
#define UDC_IN_ENDPOINT 0x01
#define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE
#define UDC_INT_ENDPOINT 0x05
#define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE
#define UDC_BULK_PACKET_SIZE EP_MAX_PACKET_SIZE
#define NUM_ENDPOINTS 6
#define REQ_COUNT 12
struct mv_ep {
struct usb_ep ep;
struct usb_request req;
struct list_head queue;
const struct usb_endpoint_descriptor *desc;
};
struct mv_udc {
u32 pad0[80];
#define MICRO_8FRAME 0x8
#define USBCMD_ITC(x) (((x > 0xff) ? 0xff : x) << 16)
#define USBCMD_FS2 (1 << 15)
#define USBCMD_RST (1 << 1)
#define USBCMD_RUN (1)
u32 usbcmd; /* 0x140 */
#define STS_SLI (1 << 8)
#define STS_URI (1 << 6)
#define STS_PCI (1 << 2)
#define STS_UEI (1 << 1)
#define STS_UI (1 << 0)
u32 usbsts; /* 0x144 */
u32 pad1[3];
u32 devaddr; /* 0x154 */
u32 epinitaddr; /* 0x158 */
u32 pad2[10];
#define PTS_ENABLE 2
#define PTS(x) ((x & 0x3) << 30)
#define PFSC (1 << 24)
u32 portsc; /* 0x184 */
u32 pad3[8];
#define USBMODE_DEVICE 2
u32 usbmode; /* 0x1a8 */
u32 epstat; /* 0x1ac */
#define EPT_TX(x) (1 << ((x & 0xffff) + 16))
#define EPT_RX(x) (1 << (x & 0xffff))
u32 epprime; /* 0x1b0 */
u32 epflush; /* 0x1b4 */
u32 pad4;
u32 epcomp; /* 0x1bc */
#define CTRL_TXE (1 << 23)
#define CTRL_TXR (1 << 22)
#define CTRL_RXE (1 << 7)
#define CTRL_RXR (1 << 6)
#define CTRL_TXT_BULK (2 << 18)
#define CTRL_RXT_BULK (2 << 2)
u32 epctrl[16]; /* 0x1c0 */
};
struct mv_drv {
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
struct mv_udc *udc;
};
struct ept_queue_head {
unsigned config;
unsigned current; /* read-only */
unsigned next;
unsigned info;
unsigned page0;
unsigned page1;
unsigned page2;
unsigned page3;
unsigned page4;
unsigned reserved_0;
unsigned char setup_data[8];
unsigned reserved_1;
unsigned reserved_2;
unsigned reserved_3;
unsigned reserved_4;
};
#define CONFIG_MAX_PKT(n) ((n) << 16)
#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
#define CONFIG_IOS (1 << 15) /* IRQ on setup */
struct ept_queue_item {
unsigned next;
unsigned info;
unsigned page0;
unsigned page1;
unsigned page2;
unsigned page3;
unsigned page4;
unsigned reserved;
};
#define TERMINATE 1
#define INFO_BYTES(n) ((n) << 16)
#define INFO_IOC (1 << 15)
#define INFO_ACTIVE (1 << 7)
#define INFO_HALTED (1 << 6)
#define INFO_BUFFER_ERROR (1 << 5)
#define INFO_TX_ERROR (1 << 3)
extern int usb_lowlevel_init(void);
#endif /* __MV_UDC_H__ */
|
1001-study-uboot
|
include/usb/mv_udc.h
|
C
|
gpl3
| 3,901
|
/*
* (C) Copyright 2003
* Gerry Hamel, geh@ti.com, Texas Instruments
*
* Based on
* linux/drivers/usb/device/bi/omap.h
* Register definitions for TI OMAP1510 USB bus interface driver
*
* Author: MontaVista Software, Inc.
* source@mvista.com
*
* 2003 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __USBDCORE_OMAP1510_H__
#define __USBDCORE_OMAP1510_H__
/*
* 13.2 MPU Register Map
*/
/* Table 13-1. USB Function Module Registers (endpoint) */
#define UDC_BASE 0xFFFB4000
#define UDC_OFFSET(offset) (UDC_BASE + (offset))
#define UDC_REV UDC_OFFSET(0x0) /* Revision */
#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */
#define UDC_DATA UDC_OFFSET(0x08) /* Data */
#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */
#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */
#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */
#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */
#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */
#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */
#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */
#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */
#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */
#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */
#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */
#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */
/* IRQ_EN register fields */
#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */
#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */
#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */
#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */
#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */
/* IRQ_SRC register fields */
#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */
#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */
#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */
#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */
#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */
#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */
#define UDC_DS_Chg (1 << 3) /* Device state changed */
#define UDC_Setup (1 << 2) /* Setup transaction */
#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */
#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */
/* DEVSTAT register fields, 14.2.9 */
#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */
#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */
#define UDC_SUS (1 << 4) /* Suspended state */
#define UDC_CFG (1 << 3) /* Configured state */
#define UDC_ADD (1 << 2) /* Addressed state */
#define UDC_DEF (1 << 1) /* Default state */
#define UDC_ATT (1 << 0) /* Attached state */
/* SYSCON1 register fields */
#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */
#define UDC_Nak_En (1 << 4) /* NAK enable */
#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */
#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */
#define UDC_Pullup_En (1 << 0) /* External pullup enabled */
/* SYSCON2 register fields */
#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */
#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */
#define UDC_Dev_Cfg (1 << 3) /* Device configured */
#define UDC_Clr_Cfg (1 << 2) /* Clear configured */
/*
* Select and enable endpoints
*/
/* Table 13-1. USB Function Module Registers (endpoint configuration) */
#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */
#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */
#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */
#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4)
#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */
#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4)
/* EP_NUM register fields */
#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */
#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */
#define UDC_EP_Dir (1 << 4) /* Endpoint direction */
/* CTRL register fields */
#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */
#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */
#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */
#define UDC_Clr_EP (1 << 1) /* Clear endpoint */
#define UDC_Reset_EP (1 << 0) /* Reset endpoint */
/* STAT_FLG register fields */
#define UDC_Miss_In (1 << 14)
#define UDC_Data_Flush (1 << 13)
#define UDC_ISO_Err (1 << 12)
#define UDC_ISO_FIFO_Empty (1 << 9)
#define UDC_ISO_FIFO_Full (1 << 8)
#define UDC_EP_Halted (1 << 6)
#define UDC_STALL (1 << 5)
#define UDC_NAK (1 << 4)
#define UDC_ACK (1 << 3)
#define UDC_FIFO_En (1 << 2)
#define UDC_Non_ISO_FIFO_Empty (1 << 1)
#define UDC_Non_ISO_FIFO_Full (1 << 0)
/* EPn_RX register fields */
#define UDC_EPn_RX_Valid (1 << 15) /* valid */
#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */
#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */
/* EPn_TX register fields */
#define UDC_EPn_TX_Valid (1 << 15) /* valid */
#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */
#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */
#define EP0_PACKETSIZE 0x40
/* physical to logical endpoint mapping
* Physical endpoints are an index into device->bus->endpoint_array.
* Logical endpoints are endpoints 0 to 15 IN and OUT as defined in
* the USB specification.
*
* physical ep logical ep direction endpoint_address
* 0 0 IN and OUT 0x00
* 1 to 15 1 to 15 OUT 0x01 to 0x0f
* 16 to 30 1 to 15 IN 0x81 to 0x8f
*/
#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */
#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17)
/* Other registers (may be) related to USB */
#define CLOCK_CTRL (0xFFFE0830)
#define APLL_CTRL (0xFFFE084C)
#define DPLL_CTRL (0xFFFE083C)
#define SOFT_REQ (0xFFFE0834)
#define STATUS_REQ (0xFFFE0840)
/* FUNC_MUX_CTRL_0 bits related to USB */
#define UDC_VBUS_CTRL (1 << 19)
#define UDC_VBUS_MODE (1 << 18)
/* OMAP Endpoint parameters */
#define EP0_MAX_PACKET_SIZE 64
#define UDC_OUT_ENDPOINT 2
#define UDC_OUT_PACKET_SIZE 64
#define UDC_IN_ENDPOINT 1
#define UDC_IN_PACKET_SIZE 64
#define UDC_INT_ENDPOINT 5
#define UDC_INT_PACKET_SIZE 16
#define UDC_BULK_PACKET_SIZE 16
void udc_irq (void);
/* Flow control */
void udc_set_nak(int epid);
void udc_unset_nak (int epid);
/* Higher level functions for abstracting away from specific device */
int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
int udc_init (void);
void udc_enable(struct usb_device_instance *device);
void udc_disable(void);
void udc_connect(void);
void udc_disconnect(void);
void udc_startup_events(struct usb_device_instance *device);
void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint);
#endif
|
1001-study-uboot
|
include/usb/omap1510_udc.h
|
C
|
gpl3
| 7,699
|
/*
* PXA27x register declarations and HCD data structures
*
* Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
* Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __PXA270X_UDC_H__
#define __PXA270X_UDC_H__
#include <asm/byteorder.h>
/* Endpoint 0 states */
#define EP0_IDLE 0
#define EP0_IN_DATA 1
#define EP0_OUT_DATA 2
#define EP0_XFER_COMPLETE 3
/* Endpoint parameters */
#define MAX_ENDPOINTS 4
#define EP_MAX_PACKET_SIZE 64
#define EP0_MAX_PACKET_SIZE 16
#define UDC_OUT_ENDPOINT 0x02
#define UDC_OUT_PACKET_SIZE EP_MAX_PACKET_SIZE
#define UDC_IN_ENDPOINT 0x01
#define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE
#define UDC_INT_ENDPOINT 0x05
#define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE
#define UDC_BULK_PACKET_SIZE EP_MAX_PACKET_SIZE
void udc_irq(void);
/* Flow control */
void udc_set_nak(int epid);
void udc_unset_nak(int epid);
/* Higher level functions for abstracting away from specific device */
int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
int udc_init(void);
void udc_enable(struct usb_device_instance *device);
void udc_disable(void);
void udc_connect(void);
void udc_disconnect(void);
void udc_startup_events(struct usb_device_instance *device);
void udc_setup_ep(struct usb_device_instance *device,
unsigned int ep, struct usb_endpoint_instance *endpoint);
#endif
|
1001-study-uboot
|
include/usb/pxa27x_udc.h
|
C
|
gpl3
| 2,105
|
/*
* Copyright (C) 2006 Bryan O'Donoghue, CodeHermit
* bodonoghue@codehermit.ie
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the
* Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
#include <commproc.h>
/* Mode Register */
#define USMOD_EN 0x01
#define USMOD_HOST 0x02
#define USMOD_TEST 0x04
#define USMOD_SFTE 0x08
#define USMOD_RESUME 0x40
#define USMOD_LSS 0x80
/* Endpoint Registers */
#define USEP_RHS_NORM 0x00
#define USEP_RHS_IGNORE 0x01
#define USEP_RHS_NAK 0x02
#define USEP_RHS_STALL 0x03
#define USEP_THS_NORM 0x00
#define USEP_THS_IGNORE 0x04
#define USEP_THS_NAK 0x08
#define USEP_THS_STALL 0x0C
#define USEP_RTE 0x10
#define USEP_MF 0x20
#define USEP_TM_CONTROL 0x00
#define USEP_TM_INT 0x100
#define USEP_TM_BULK 0x200
#define USEP_TM_ISO 0x300
/* Command Register */
#define USCOM_EP0 0x00
#define USCOM_EP1 0x01
#define USCOM_EP2 0x02
#define USCOM_EP3 0x03
#define USCOM_FLUSH 0x40
#define USCOM_STR 0x80
/* Event Register */
#define USB_E_RXB 0x0001
#define USB_E_TXB 0x0002
#define USB_E_BSY 0x0004
#define USB_E_SOF 0x0008
#define USB_E_TXE1 0x0010
#define USB_E_TXE2 0x0020
#define USB_E_TXE3 0x0040
#define USB_E_TXE4 0x0080
#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4)
#define USB_E_IDLE 0x0100
#define USB_E_RESET 0x0200
/* Mask Register */
#define USBS_IDLE 0x01
/* RX Buffer Descriptor */
#define RX_BD_OV 0x02
#define RX_BD_CR 0x04
#define RX_BD_AB 0x08
#define RX_BD_NO 0x10
#define RX_BD_PID_DATA0 0x00
#define RX_BD_PID_DATA1 0x40
#define RX_BD_PID_SETUP 0x80
#define RX_BD_F 0x400
#define RX_BD_L 0x800
#define RX_BD_I 0x1000
#define RX_BD_W 0x2000
#define RX_BD_E 0x8000
/* Useful masks */
#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP)
#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL)
#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK)
#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF)
/* TX Buffer Descriptor */
#define TX_BD_UN 0x02
#define TX_BD_TO 0x04
#define TX_BD_NO_PID 0x00
#define TX_BD_PID_DATA0 0x80
#define TX_BD_PID_DATA1 0xC0
#define TX_BD_CNF 0x200
#define TX_BD_TC 0x400
#define TX_BD_L 0x800
#define TX_BD_I 0x1000
#define TX_BD_W 0x2000
#define TX_BD_R 0x8000
/* Implementation specific defines */
#define EP_MIN_PACKET_SIZE 0x08
#define MAX_ENDPOINTS 0x04
#define FIFO_SIZE 0x10
#define EP_MAX_PKT FIFO_SIZE
#define TX_RING_SIZE 0x04
#define RX_RING_SIZE 0x06
#define USB_MAX_PKT 0x40
#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80
#define TOGGLE_RX_PID(x) x^= 0x40
#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */
#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */
#define PROFF_USB 0x00000000
#define CPM_USB_BASE 0x00000A00
/* UDC device defines */
#define EP0_MAX_PACKET_SIZE EP_MAX_PKT
#define UDC_OUT_ENDPOINT 0x02
#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE
#define UDC_IN_ENDPOINT 0x03
#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE
#define UDC_INT_ENDPOINT 0x01
#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE
#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE
struct mpc8xx_ep {
struct urb * urb;
unsigned char pid;
unsigned char sc;
volatile cbd_t * prx;
};
typedef struct mpc8xx_usb{
char usmod; /* Mode Register */
char usaddr; /* Slave Address Register */
char uscom; /* Command Register */
char res1; /* Reserved */
ushort usep[4];
ulong res2; /* Reserved */
ushort usber; /* Event Register */
ushort res3; /* Reserved */
ushort usbmr; /* Mask Register */
char res4; /* Reserved */
char usbs; /* Status Register */
char res5[8]; /* Reserved */
}usb_t;
typedef struct mpc8xx_parameter_ram{
ushort ep0ptr; /* Endpoint Pointer Register 0 */
ushort ep1ptr; /* Endpoint Pointer Register 1 */
ushort ep2ptr; /* Endpoint Pointer Register 2 */
ushort ep3ptr; /* Endpoint Pointer Register 3 */
uint rstate; /* Receive state */
uint rptr; /* Receive internal data pointer */
ushort frame_n; /* Frame number */
ushort rbcnt; /* Receive byte count */
uint rtemp; /* Receive temp cp use only */
uint rxusb; /* Rx Data Temp */
ushort rxuptr; /* Rx microcode return address temp */
}usb_pram_t;
typedef struct endpoint_parameter_block_pointer{
ushort rbase; /* RxBD base address */
ushort tbase; /* TxBD base address */
char rfcr; /* Rx Function code */
char tfcr; /* Tx Function code */
ushort mrblr; /* Maximum Receive Buffer Length */
ushort rbptr; /* RxBD pointer Next Buffer Descriptor */
ushort tbptr; /* TxBD pointer Next Buffer Descriptor */
ulong tstate; /* Transmit internal state */
ulong tptr; /* Transmit internal data pointer */
ushort tcrc; /* Transmit temp CRC */
ushort tbcnt; /* Transmit internal bye count */
ulong ttemp; /* Tx temp */
ushort txuptr; /* Tx microcode return address */
ushort res1; /* Reserved */
}usb_epb_t;
typedef enum mpc8xx_udc_state{
STATE_NOT_READY,
STATE_ERROR,
STATE_READY,
}mpc8xx_udc_state_t;
/* Declarations */
int udc_init(void);
void udc_irq(void);
int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
struct usb_endpoint_instance *endpoint);
void udc_connect(void);
void udc_disconnect(void);
void udc_enable(struct usb_device_instance *device);
void udc_disable(void);
void udc_startup_events(struct usb_device_instance *device);
/* Flow control */
void udc_set_nak(int epid);
void udc_unset_nak (int epid);
|
1001-study-uboot
|
include/usb/mpc8xx_udc.h
|
C
|
gpl3
| 5,992
|
/*
* (C) Copyright 2009
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SPR_UDC_H
#define __SPR_UDC_H
/*
* Defines for USBD
*
* The udc_ahb controller has three AHB slaves:
*
* 1. THe UDC registers
* 2. The plug detect
* 3. The RX/TX FIFO
*/
#define MAX_ENDPOINTS 16
struct udc_endp_regs {
u32 endp_cntl;
u32 endp_status;
u32 endp_bsorfn;
u32 endp_maxpacksize;
u32 reserved_1;
u32 endp_desc_point;
u32 reserved_2;
u32 write_done;
};
/* Endpoint Control Register definitions */
#define ENDP_CNTL_STALL 0x00000001
#define ENDP_CNTL_FLUSH 0x00000002
#define ENDP_CNTL_SNOOP 0x00000004
#define ENDP_CNTL_POLL 0x00000008
#define ENDP_CNTL_CONTROL 0x00000000
#define ENDP_CNTL_ISO 0x00000010
#define ENDP_CNTL_BULK 0x00000020
#define ENDP_CNTL_INT 0x00000030
#define ENDP_CNTL_NAK 0x00000040
#define ENDP_CNTL_SNAK 0x00000080
#define ENDP_CNTL_CNAK 0x00000100
#define ENDP_CNTL_RRDY 0x00000200
/* Endpoint Satus Register definitions */
#define ENDP_STATUS_PIDMSK 0x0000000f
#define ENDP_STATUS_OUTMSK 0x00000030
#define ENDP_STATUS_OUT_NONE 0x00000000
#define ENDP_STATUS_OUT_DATA 0x00000010
#define ENDP_STATUS_OUT_SETUP 0x00000020
#define ENDP_STATUS_IN 0x00000040
#define ENDP_STATUS_BUFFNAV 0x00000080
#define ENDP_STATUS_FATERR 0x00000100
#define ENDP_STATUS_HOSTBUSERR 0x00000200
#define ENDP_STATUS_TDC 0x00000400
#define ENDP_STATUS_RXPKTMSK 0x003ff800
struct udc_regs {
struct udc_endp_regs in_regs[MAX_ENDPOINTS];
struct udc_endp_regs out_regs[MAX_ENDPOINTS];
u32 dev_conf;
u32 dev_cntl;
u32 dev_stat;
u32 dev_int;
u32 dev_int_mask;
u32 endp_int;
u32 endp_int_mask;
u32 reserved_3[0x39];
u32 reserved_4; /* offset 0x500 */
u32 udc_endp_reg[MAX_ENDPOINTS];
};
/* Device Configuration Register definitions */
#define DEV_CONF_HS_SPEED 0x00000000
#define DEV_CONF_LS_SPEED 0x00000002
#define DEV_CONF_FS_SPEED 0x00000003
#define DEV_CONF_REMWAKEUP 0x00000004
#define DEV_CONF_SELFPOW 0x00000008
#define DEV_CONF_SYNCFRAME 0x00000010
#define DEV_CONF_PHYINT_8 0x00000020
#define DEV_CONF_PHYINT_16 0x00000000
#define DEV_CONF_UTMI_BIDIR 0x00000040
#define DEV_CONF_STATUS_STALL 0x00000080
/* Device Control Register definitions */
#define DEV_CNTL_RESUME 0x00000001
#define DEV_CNTL_TFFLUSH 0x00000002
#define DEV_CNTL_RXDMAEN 0x00000004
#define DEV_CNTL_TXDMAEN 0x00000008
#define DEV_CNTL_DESCRUPD 0x00000010
#define DEV_CNTL_BIGEND 0x00000020
#define DEV_CNTL_BUFFILL 0x00000040
#define DEV_CNTL_TSHLDEN 0x00000080
#define DEV_CNTL_BURSTEN 0x00000100
#define DEV_CNTL_DMAMODE 0x00000200
#define DEV_CNTL_SOFTDISCONNECT 0x00000400
#define DEV_CNTL_SCALEDOWN 0x00000800
#define DEV_CNTL_BURSTLENU 0x00010000
#define DEV_CNTL_BURSTLENMSK 0x00ff0000
#define DEV_CNTL_TSHLDLENU 0x01000000
#define DEV_CNTL_TSHLDLENMSK 0xff000000
/* Device Status Register definitions */
#define DEV_STAT_CFG 0x0000000f
#define DEV_STAT_INTF 0x000000f0
#define DEV_STAT_ALT 0x00000f00
#define DEV_STAT_SUSP 0x00001000
#define DEV_STAT_ENUM 0x00006000
#define DEV_STAT_ENUM_SPEED_HS 0x00000000
#define DEV_STAT_ENUM_SPEED_FS 0x00002000
#define DEV_STAT_ENUM_SPEED_LS 0x00004000
#define DEV_STAT_RXFIFO_EMPTY 0x00008000
#define DEV_STAT_PHY_ERR 0x00010000
#define DEV_STAT_TS 0xf0000000
/* Device Interrupt Register definitions */
#define DEV_INT_MSK 0x0000007f
#define DEV_INT_SETCFG 0x00000001
#define DEV_INT_SETINTF 0x00000002
#define DEV_INT_INACTIVE 0x00000004
#define DEV_INT_USBRESET 0x00000008
#define DEV_INT_SUSPUSB 0x00000010
#define DEV_INT_SOF 0x00000020
#define DEV_INT_ENUM 0x00000040
/* Endpoint Interrupt Register definitions */
#define ENDP0_INT_CTRLIN 0x00000001
#define ENDP1_INT_BULKIN 0x00000002
#define ENDP_INT_NONISOIN_MSK 0x0000AAAA
#define ENDP2_INT_BULKIN 0x00000004
#define ENDP0_INT_CTRLOUT 0x00010000
#define ENDP1_INT_BULKOUT 0x00020000
#define ENDP2_INT_BULKOUT 0x00040000
#define ENDP_INT_NONISOOUT_MSK 0x55540000
/* Endpoint Register definitions */
#define ENDP_EPDIR_OUT 0x00000000
#define ENDP_EPDIR_IN 0x00000010
#define ENDP_EPTYPE_CNTL 0x0
#define ENDP_EPTYPE_ISO 0x1
#define ENDP_EPTYPE_BULK 0x2
#define ENDP_EPTYPE_INT 0x3
/*
* Defines for Plug Detect
*/
struct plug_regs {
u32 plug_state;
u32 plug_pending;
};
/* Plug State Register definitions */
#define PLUG_STATUS_EN 0x1
#define PLUG_STATUS_ATTACHED 0x2
#define PLUG_STATUS_PHY_RESET 0x4
#define PLUG_STATUS_PHY_MODE 0x8
/*
* Defines for UDC FIFO (Slave Mode)
*/
struct udcfifo_regs {
u32 *fifo_p;
};
/*
* USBTTY definitions
*/
#define EP0_MAX_PACKET_SIZE 64
#define UDC_INT_ENDPOINT 1
#define UDC_INT_PACKET_SIZE 64
#define UDC_OUT_ENDPOINT 2
#define UDC_BULK_PACKET_SIZE 64
#define UDC_IN_ENDPOINT 3
#define UDC_OUT_PACKET_SIZE 64
#define UDC_IN_PACKET_SIZE 64
/*
* UDC endpoint definitions
*/
#define UDC_EP0 0
#define UDC_EP1 1
#define UDC_EP2 2
#define UDC_EP3 3
/*
* Function declarations
*/
void udc_irq(void);
void udc_set_nak(int epid);
void udc_unset_nak(int epid);
int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
int udc_init(void);
void udc_enable(struct usb_device_instance *device);
void udc_disable(void);
void udc_connect(void);
void udc_disconnect(void);
void udc_startup_events(struct usb_device_instance *device);
void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
struct usb_endpoint_instance *endpoint);
#endif /* __SPR_UDC_H */
|
1001-study-uboot
|
include/usb/spr_udc.h
|
C
|
gpl3
| 6,382
|
/*
*==========================================================================
*
* xyzModem.h
*
* RedBoot stream handler for xyzModem protocol
*
*==========================================================================
*####ECOSGPLCOPYRIGHTBEGIN####
* -------------------------------------------
* This file is part of eCos, the Embedded Configurable Operating System.
* Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
* Copyright (C) 2002 Gary Thomas
*
* eCos is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 or (at your option) any later version.
*
* eCos is distributed in the hope that it will be useful, but WITHOUT ANY
* WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with eCos; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*
* As a special exception, if other files instantiate templates or use macros
* or inline functions from this file, or you compile this file and link it
* with other works to produce a work based on this file, this file does not
* by itself cause the resulting work to be covered by the GNU General Public
* License. However the source code for this file must still be made available
* in accordance with section (3) of the GNU General Public License.
*
* This exception does not invalidate any other reasons why a work based on
* this file might be covered by the GNU General Public License.
*
* Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
* at http: *sources.redhat.com/ecos/ecos-license/
* -------------------------------------------
*####ECOSGPLCOPYRIGHTEND####
*==========================================================================
*#####DESCRIPTIONBEGIN####
*
* Author(s): gthomas
* Contributors: gthomas
* Date: 2000-07-14
* Purpose:
* Description:
*
* This code is part of RedBoot (tm).
*
*####DESCRIPTIONEND####
*
*==========================================================================
*/
#ifndef _XYZMODEM_H_
#define _XYZMODEM_H_
#define xyzModem_xmodem 1
#define xyzModem_ymodem 2
/* Don't define this until the protocol support is in place */
/*#define xyzModem_zmodem 3 */
#define xyzModem_access -1
#define xyzModem_noZmodem -2
#define xyzModem_timeout -3
#define xyzModem_eof -4
#define xyzModem_cancel -5
#define xyzModem_frame -6
#define xyzModem_cksum -7
#define xyzModem_sequence -8
#define xyzModem_close 1
#define xyzModem_abort 2
#ifdef REDBOOT
extern getc_io_funcs_t xyzModem_io;
#else
#define CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT
#define CYGACC_CALL_IF_SET_CONSOLE_COMM(x)
#define diag_vprintf vprintf
#define diag_printf printf
#define diag_vsprintf vsprintf
#define CYGACC_CALL_IF_DELAY_US(x) udelay(x)
typedef struct {
char *filename;
int mode;
int chan;
#ifdef CYGPKG_REDBOOT_NETWORKING
struct sockaddr_in *server;
#endif
} connection_info_t;
#ifndef BOOL_WAS_DEFINED
#define BOOL_WAS_DEFINED
typedef unsigned int bool;
#endif
#define false 0
#define true 1
#endif
int xyzModem_stream_open(connection_info_t *info, int *err);
void xyzModem_stream_close(int *err);
void xyzModem_stream_terminate(bool method, int (*getc)(void));
int xyzModem_stream_read(char *buf, int size, int *err);
char *xyzModem_error(int err);
#endif /* _XYZMODEM_H_ */
|
1001-study-uboot
|
include/xyzModem.h
|
C
|
gpl3
| 3,669
|
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* WARNING! This file is automatically generated - DO NOT EDIT!
*/
#define KERNELBASE -1073741824
#define STATE 0
#define NEXT_TASK 64
#define COUNTER 52
#define PROCESSOR 916
#define SIGPENDING 8
#define TSS 576
#define MM 880
#define TASK_STRUCT_SIZE 928
#define KSP 0
#define PG_TABLES 4
#define PGD 8
#define LAST_SYSCALL 20
#define PT_REGS 12
#define PF_TRACESYS 32
#define TASK_FLAGS 4
#define TSS_FPR0 24
#define TSS_FPSCR 284
#define TSS_SMP_FORK_RET 288
#define TASK_UNION_SIZE 8192
#define STACK_FRAME_OVERHEAD 16
#define INT_FRAME_SIZE 192
#define GPR0 16
#define GPR1 20
#define GPR2 24
#define GPR3 28
#define GPR4 32
#define GPR5 36
#define GPR6 40
#define GPR7 44
#define GPR8 48
#define GPR9 52
#define GPR10 56
#define GPR11 60
#define GPR12 64
#define GPR13 68
#define GPR14 72
#define GPR15 76
#define GPR16 80
#define GPR17 84
#define GPR18 88
#define GPR19 92
#define GPR20 96
#define GPR21 100
#define GPR22 104
#define GPR23 108
#define GPR24 112
#define GPR25 116
#define GPR26 120
#define GPR27 124
#define GPR28 128
#define GPR29 132
#define GPR30 136
#define GPR31 140
#define _NIP 144
#define _MSR 148
#define _CTR 156
#define _LINK 160
#define _CCR 168
#define _XER 164
#define _DAR 180
#define _DSISR 184
#define ORIG_GPR3 152
#define RESULT 188
#define TRAP 176
|
1001-study-uboot
|
include/ppc_defs.h
|
C
|
gpl3
| 2,179
|
/*
** video easylogo
** ==============
** (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
** AIRVENT SAM s.p.a - RIMINI(ITALY)
**
** This utility is still under construction!
*/
#ifndef _EASYLOGO_H_
#define _EASYLOGO_H_
#if 0
#define ENABLE_ASCII_BANNERS
#endif
typedef struct {
unsigned char *data;
int width;
int height;
int bpp;
int pixel_size;
int size;
} fastimage_t ;
#endif /* _EASYLOGO_H_ */
|
1001-study-uboot
|
include/video_easylogo.h
|
C
|
gpl3
| 412
|
/*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _FLASH_H_
#define _FLASH_H_
#ifndef CONFIG_SYS_NO_FLASH
/*-----------------------------------------------------------------------
* FLASH Info: contains chip specific data, per FLASH bank
*/
typedef struct {
ulong size; /* total bank size in bytes */
ushort sector_count; /* number of erase units */
ulong flash_id; /* combined device & manufacturer code */
ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* virtual sector start address */
uchar protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status */
#ifdef CONFIG_SYS_FLASH_CFI
uchar portwidth; /* the width of the port */
uchar chipwidth; /* the width of the chip */
ushort buffer_size; /* # of bytes in write buffer */
ulong erase_blk_tout; /* maximum block erase timeout */
ulong write_tout; /* maximum write timeout */
ulong buffer_write_tout; /* maximum buffer write timeout */
ushort vendor; /* the primary vendor id */
ushort cmd_reset; /* vendor specific reset command */
ushort interface; /* used for x8/x16 adjustments */
ushort legacy_unlock; /* support Intel legacy (un)locking */
ushort manufacturer_id; /* manufacturer id */
ushort device_id; /* device id */
ushort device_id2; /* extended device id */
ushort ext_addr; /* extended query table address */
ushort cfi_version; /* cfi version */
ushort cfi_offset; /* offset for cfi query */
ulong addr_unlock1; /* unlock address 1 for AMD flash roms */
ulong addr_unlock2; /* unlock address 2 for AMD flash roms */
const char *name; /* human-readable name */
#endif
} flash_info_t;
extern flash_info_t flash_info[]; /* info for FLASH chips */
typedef unsigned long flash_sect_t;
/*
* Values for the width of the port
*/
#define FLASH_CFI_8BIT 0x01
#define FLASH_CFI_16BIT 0x02
#define FLASH_CFI_32BIT 0x04
#define FLASH_CFI_64BIT 0x08
/*
* Values for the width of the chip
*/
#define FLASH_CFI_BY8 0x01
#define FLASH_CFI_BY16 0x02
#define FLASH_CFI_BY32 0x04
#define FLASH_CFI_BY64 0x08
/* convert between bit value and numeric value */
#define CFI_FLASH_SHIFT_WIDTH 3
/*
* Values for the flash device interface
*/
#define FLASH_CFI_X8 0x00
#define FLASH_CFI_X16 0x01
#define FLASH_CFI_X8X16 0x02
#define FLASH_CFI_X16X32 0x05
/* convert between bit value and numeric value */
#define CFI_FLASH_SHIFT_WIDTH 3
/* Prototypes */
extern unsigned long flash_init (void);
extern void flash_protect_default(void);
extern void flash_print_info (flash_info_t *);
extern int flash_erase (flash_info_t *, int, int);
extern int flash_sect_erase (ulong addr_first, ulong addr_last);
extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
extern int flash_sect_roundb (ulong *addr);
extern unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect);
extern void flash_set_verbose(uint);
/* common/flash.c */
extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
extern int flash_write (char *, ulong, ulong);
extern flash_info_t *addr2info (ulong);
extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
/* drivers/mtd/cfi_mtd.c */
#ifdef CONFIG_FLASH_CFI_MTD
extern int cfi_mtd_init(void);
#endif
/* board/?/flash.c */
#if defined(CONFIG_SYS_FLASH_PROTECTION)
extern int flash_real_protect(flash_info_t *info, long sector, int prot);
extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len);
extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
#endif /* CONFIG_SYS_FLASH_PROTECTION */
#ifdef CONFIG_FLASH_CFI_LEGACY
extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info);
extern int jedec_flash_match(flash_info_t *info, ulong base);
#define CFI_CMDSET_AMD_LEGACY 0xFFF0
#endif
#if defined(CONFIG_SYS_FLASH_CFI)
extern flash_info_t *flash_get_info(ulong base);
#endif
/*-----------------------------------------------------------------------
* return codes from flash_write():
*/
#define ERR_OK 0
#define ERR_TIMOUT 1
#define ERR_NOT_ERASED 2
#define ERR_PROTECTED 4
#define ERR_INVAL 8
#define ERR_ALIGN 16
#define ERR_UNKNOWN_FLASH_VENDOR 32
#define ERR_UNKNOWN_FLASH_TYPE 64
#define ERR_PROG_ERROR 128
/*-----------------------------------------------------------------------
* Protection Flags for flash_protect():
*/
#define FLAG_PROTECT_SET 0x01
#define FLAG_PROTECT_CLEAR 0x02
#define FLAG_PROTECT_INVALID 0x03
/*-----------------------------------------------------------------------
* Set Environment according to label:
*/
#define FLAG_SETENV 0x80
/*-----------------------------------------------------------------------
* Device IDs
*/
/* Manufacturers inside bank 0 have ids like 0x00xx00xx */
#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */
#define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */
#define ATM_MANUFACT 0x001F001F /* ATMEL */
#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
#define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */
#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */
#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */
#define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/
#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */
#define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */
#define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */
/* Manufacturers inside bank 1 have ids like 0x01xx01xx */
#define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */
/* Manufacturers inside bank 2 have ids like 0x02xx02xx */
/* Micron Technologies (INTEL compat.) */
#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
#define AMD_ID_LV040B 0x4F /* 29LV040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
#define AMD_ID_F033C 0xA3 /* 29LV033C ID */
/* 32 Mbit, 4Mbits x 8, */
/* 64 64K x 8 uniform sectors */
#define AMD_ID_F065D 0x93 /* 29LV065D ID */
/* 64 Mbit, 8Mbits x 8, */
/* 126 64K x 8 uniform sectors */
#define ATM_ID_LV040 0x13 /* 29LV040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
#define AMD_ID_F040B 0xA4 /* 29F040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
#define STM_ID_M29W040B 0xE3 /* M29W040B ID */
/* 4 Mbit, 512K x 8, */
/* 8 64K x 8 uniform sectors */
#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */
/* 8 Mbit, 512K x 16, */
/* 8 64K x 16 uniform sectors */
#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */
#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */
#define AMD_ID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */
#define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */
#define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */
#define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */
#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
#define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */
#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
#define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */
#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
#define MX_ID_LV320B 0x22A822A8 /* 29LV320B by Macronix, AMD compatible */
#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */
#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */
#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */
#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */
#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
#define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */
#define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */
#define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */
#define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */
#define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */
#define AMD_ID_LV640MT_2 0x22102210 /* 2nd ID word for AM29LV640MT at 0x38 */
#define AMD_ID_LV640MT_3 0x22012201 /* 3rd ID word for AM29LV640MT at 0x3c */
#define AMD_ID_LV640MB_2 0x22102210 /* 2nd ID word for AM29LV640MB at 0x38 */
#define AMD_ID_LV640MB_3 0x22002200 /* 3rd ID word for AM29LV640MB at 0x3c */
#define AMD_ID_LV128U_2 0x22122212 /* 2nd ID word for AM29LV128M at 0x38 */
#define AMD_ID_LV128U_3 0x22002200 /* 3rd ID word for AM29LV128M at 0x3c */
#define AMD_ID_LV256U_2 0x22122212 /* 2nd ID word for AM29LV256M at 0x38 */
#define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */
#define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */
#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */
#define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */
#define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */
#define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */
#define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */
#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */
#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
#define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */
#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
#define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */
#define ATM_ID_BV6416 0x000000D6 /* 49BV6416 ID */
#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
#define FUJI_ID_29LV650UE 0x22d722d7 /* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
#define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */
#define SST_ID_xF1601 0x234B234B /* 39xF1601 ID (16M = 1M x 16 ) */
#define SST_ID_xF1602 0x234A234A /* 39xF1602 ID (16M = 1M x 16 ) */
#define SST_ID_xF3201 0x235B235B /* 39xF3201 ID (32M = 2M x 16 ) */
#define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */
#define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */
#define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */
#define SST_ID_xF020 0xBFD6BFD6 /* 39xF020 ID (256KB = 2Mbit x 8) */
#define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */
#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */
/* 8 64K x 8 uniform sectors */
#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
#define STM_ID_29W320ET 0x22562256 /* M29W320ET ID (32 M, top boot sector) */
#define STM_ID_29W320EB 0x22572257 /* M29W320EB ID (32 M, bottom boot sect)*/
#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
#define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */
#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
#define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */
#define INTEL_ID_28F800B3B 0x88938893 /* 8M = 512K x 16 bottom boot sector */
#define INTEL_ID_28F160B3T 0x88908890 /* 16M = 1M x 16 top boot sector */
#define INTEL_ID_28F160B3B 0x88918891 /* 16M = 1M x 16 bottom boot sector */
#define INTEL_ID_28F320B3T 0x88968896 /* 32M = 2M x 16 top boot sector */
#define INTEL_ID_28F320B3B 0x88978897 /* 32M = 2M x 16 bottom boot sector */
#define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */
#define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */
#define INTEL_ID_28F160F3B 0x88F488F4 /* 16M = 1M x 16 bottom boot sector */
#define INTEL_ID_28F800C3T 0x88C088C0 /* 8M = 512K x 16 top boot sector */
#define INTEL_ID_28F800C3B 0x88C188C1 /* 8M = 512K x 16 bottom boot sector */
#define INTEL_ID_28F160C3T 0x88C288C2 /* 16M = 1M x 16 top boot sector */
#define INTEL_ID_28F160C3B 0x88C388C3 /* 16M = 1M x 16 bottom boot sector */
#define INTEL_ID_28F320C3T 0x88C488C4 /* 32M = 2M x 16 top boot sector */
#define INTEL_ID_28F320C3B 0x88C588C5 /* 32M = 2M x 16 bottom boot sector */
#define INTEL_ID_28F640C3T 0x88CC88CC /* 64M = 4M x 16 top boot sector */
#define INTEL_ID_28F640C3B 0x88CD88CD /* 64M = 4M x 16 bottom boot sector */
#define INTEL_ID_28F128J3 0x89188918 /* 16M = 8M x 16 x 128 */
#define INTEL_ID_28F320J5 0x00140014 /* 32M = 128K x 32 */
#define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */
#define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */
#define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */
#define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */
#define INTEL_ID_28F256J3A 0x001D001D /* 256M = 128K x 256 */
#define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */
#define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */
#define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */
#define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */
#define INTEL_ID_28F64P30T 0x88178817 /* 64M = 32K x 255 + 32k x 4 */
#define INTEL_ID_28F64P30B 0x881A881A /* 64M = 32K x 255 + 32k x 4 */
#define INTEL_ID_28F128P30T 0x88188818 /* 128M = 64K x 255 + 32k x 4 */
#define INTEL_ID_28F128P30B 0x881B881B /* 128M = 64K x 255 + 32k x 4 */
#define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */
#define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */
#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */
#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */
/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
#define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */
#define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */
#define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */
/* LH28F008SCR-L85 1Mx8, 16 64k blocks */
#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */
#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */
#define PHILIPS_LPC2292 0x0401FF13 /* LPC2292 internal FLASH */
/*-----------------------------------------------------------------------
* Internal FLASH identification codes
*
* Be careful when adding new type! Odd numbers are "bottom boot sector" types!
*/
#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */
/* Bright Micro BM29F040 */
/* Fujitsu MBM29F040A */
/* STM M29W040B */
/* SGS Thomson M29F040B */
/* 8 64K x 8 uniform sectors */
#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */
#define FLASH_AM400B 0x0003
#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */
#define FLASH_AM800B 0x0005
#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */
#define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */
#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */
#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
#define FLASH_AM160B 0x0007
#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */
#define FLASH_AM320B 0x0009
#define FLASH_AM080 0x000A /* AMD Am29F080B */
/* 16 64K x 8 uniform sectors */
#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */
#define FLASH_AMDL322B 0x0011
#define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */
#define FLASH_AMDL323B 0x0013
#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
#define FLASH_AMDL324B 0x0015
#define FLASH_AMDLV033C 0x0018
#define FLASH_AMDLV065D 0x001A
#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
#define FLASH_AMD016 0x0018 /* AMD AM29F016D */
#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/
#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */
#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */
#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
#define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
#define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */
#define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */
#define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */
#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */
#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/
#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/
#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
#define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */
#define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */
#define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */
#define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */
#define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */
#define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */
#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */
#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */
#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */
#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */
#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */
#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */
#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */
#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */
#define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */
#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */
#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */
#define FLASH_AM065D 0x0093
#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */
#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */
#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */
#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */
#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */
#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */
#define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */
#define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */
#define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */
#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */
#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */
#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
#define FLASH_AMDL163B 0x00B3
#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */
#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */
#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */
#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */
#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */
#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */
#define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */
#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */
#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
/* manufacturer offsets
*/
#define FLASH_MAN_AMD 0x00000000 /* AMD */
#define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */
#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */
#define FLASH_MAN_MX 0x00030000 /* MXIC */
#define FLASH_MAN_STM 0x00040000
#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */
#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */
#define FLASH_MAN_SST 0x00100000
#define FLASH_MAN_INTEL 0x00300000
#define FLASH_MAN_MT 0x00400000
#define FLASH_MAN_SHARP 0x00500000
#define FLASH_MAN_ATM 0x00600000
#define FLASH_MAN_CFI 0x01000000
#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
#define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */
/* with AMD, Fujitsu and SST */
/* (JEDEC standard commands ?) */
#define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */
/*-----------------------------------------------------------------------
* Timeout constants:
*
* We can't find any specifications for maximum chip erase times,
* so these values are guestimates.
*/
#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */
#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */
#endif /* !CONFIG_SYS_NO_FLASH */
#endif /* _FLASH_H_ */
|
1001-study-uboot
|
include/flash.h
|
C
|
gpl3
| 24,658
|
/*
* Copyright (C) 2008 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __FIS_H__
#define __FIS_H__
/*
* Register - Host to Device FIS
*/
typedef struct sata_fis_h2d {
u8 fis_type;
u8 pm_port_c;
u8 command;
u8 features;
u8 lba_low;
u8 lba_mid;
u8 lba_high;
u8 device;
u8 lba_low_exp;
u8 lba_mid_exp;
u8 lba_high_exp;
u8 features_exp;
u8 sector_count;
u8 sector_count_exp;
u8 res1;
u8 control;
u8 res2[4];
} __attribute__ ((packed)) sata_fis_h2d_t;
/*
* Register - Host to Device FIS for read/write FPDMA queued
*/
typedef struct sata_fis_h2d_ncq {
u8 fis_type;
u8 pm_port_c;
u8 command;
u8 sector_count_low;
u8 lba_low;
u8 lba_mid;
u8 lba_high;
u8 device;
u8 lba_low_exp;
u8 lba_mid_exp;
u8 lba_high_exp;
u8 sector_count_high;
u8 tag;
u8 res1;
u8 res2;
u8 control;
u8 res3[4];
} __attribute__ ((packed)) sata_fis_h2d_ncq_t;
/*
* Register - Device to Host FIS
*/
typedef struct sata_fis_d2h {
u8 fis_type;
u8 pm_port_i;
u8 status;
u8 error;
u8 lba_low;
u8 lba_mid;
u8 lba_high;
u8 device;
u8 lba_low_exp;
u8 lba_mid_exp;
u8 lba_high_exp;
u8 res1;
u8 sector_count;
u8 sector_count_exp;
u8 res2[2];
u8 res3[4];
} __attribute__ ((packed)) sata_fis_d2h_t;
/*
* DMA Setup - Device to Host or Host to Device FIS
*/
typedef struct sata_fis_dma_setup {
u8 fis_type;
u8 pm_port_dir_int_act;
u8 res1;
u8 res2;
u32 dma_buffer_id_low;
u32 dma_buffer_id_high;
u32 res3;
u32 dma_buffer_offset;
u32 dma_transfer_count;
u32 res4;
} __attribute__ ((packed)) sata_fis_dma_setup_t;
/*
* PIO Setup - Device to Host FIS
*/
typedef struct sata_fis_pio_setup {
u8 fis_type;
u8 pm_port_dir_int;
u8 status;
u8 error;
u8 lba_low;
u8 lba_mid;
u8 lba_high;
u8 res1;
u8 lba_low_exp;
u8 lba_mid_exp;
u8 lba_high_exp;
u8 res2;
u8 sector_count;
u8 sector_count_exp;
u8 res3;
u8 e_status;
u16 transfer_count;
u16 res4;
} __attribute__ ((packed)) sata_fis_pio_setup_t;
/*
* Data - Host to Device or Device to Host FIS
*/
typedef struct sata_fis_data {
u8 fis_type;
u8 pm_port;
u8 res1;
u8 res2;
u32 data[2048];
} __attribute__ ((packed)) sata_fis_data_t;
/* fis_type - SATA FIS type
*/
enum sata_fis_type {
SATA_FIS_TYPE_REGISTER_H2D = 0x27,
SATA_FIS_TYPE_REGISTER_D2H = 0x34,
SATA_FIS_TYPE_DMA_ACT_D2H = 0x39,
SATA_FIS_TYPE_DMA_SETUP_BI = 0x41,
SATA_FIS_TYPE_DATA_BI = 0x46,
SATA_FIS_TYPE_BIST_ACT_BI = 0x58,
SATA_FIS_TYPE_PIO_SETUP_D2H = 0x5F,
SATA_FIS_TYPE_SET_DEVICE_BITS_D2H = 0xA1,
};
#endif /* __FIS_H__ */
|
1001-study-uboot
|
include/fis.h
|
C
|
gpl3
| 3,238
|
/*
* (C) Copyright 2002-2007
* Detlev Zundel, dzu@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _LOGBUFF_H
#define _LOGBUFF_H
#ifdef CONFIG_LOGBUFFER
#define LOGBUFF_MAGIC 0xc0de4ced /* Forced by code, eh! */
#define LOGBUFF_LEN (16384) /* Must be 16k right now */
#define LOGBUFF_MASK (LOGBUFF_LEN-1)
#define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */
#define LOGBUFF_RESERVE (LOGBUFF_LEN+LOGBUFF_OVERHEAD)
/* The mapping used here has to be the same as in setup_ext_logbuff ()
in linux/kernel/printk */
typedef struct {
union {
struct {
unsigned long tag;
unsigned long start;
unsigned long con;
unsigned long end;
unsigned long chars;
} v2;
struct {
unsigned long dummy;
unsigned long tag;
unsigned long start;
unsigned long size;
unsigned long chars;
} v1;
};
unsigned char buf[0];
} logbuff_t;
int drv_logbuff_init (void);
void logbuff_init_ptrs (void);
void logbuff_log(char *msg);
void logbuff_reset (void);
unsigned long logbuffer_base (void);
#endif /* CONFIG_LOGBUFFER */
#endif /* _LOGBUFF_H */
|
1001-study-uboot
|
include/logbuff.h
|
C
|
gpl3
| 1,850
|
/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MPC106_PCI_H
#define _MPC106_PCI_H
/*
* Defines for the MPC106 PCI Config address and data registers followed by
* defines for the standard PCI device configuration header.
*/
#define PCIDEVID_MPC106 0x0
/*
* MPC106 Registers
*/
#define MPC106_REG 0x80000000
#ifdef CONFIG_SYS_ADDRESS_MAP_A
#define MPC106_REG_ADDR 0x80000cf8
#define MPC106_REG_DATA 0x80000cfc
#define MPC106_ISA_IO_PHYS 0x80000000
#define MPC106_ISA_IO_BUS 0x00000000
#define MPC106_ISA_IO_SIZE 0x00800000
#define MPC106_PCI_IO_PHYS 0x81000000
#define MPC106_PCI_IO_BUS 0x01000000
#define MPC106_PCI_IO_SIZE 0x3e800000
#define MPC106_PCI_MEM_PHYS 0xc0000000
#define MPC106_PCI_MEM_BUS 0x00000000
#define MPC106_PCI_MEM_SIZE 0x3f000000
#define MPC106_PCI_MEMORY_PHYS 0x00000000
#define MPC106_PCI_MEMORY_BUS 0x80000000
#define MPC106_PCI_MEMORY_SIZE 0x80000000
#else
#define MPC106_REG_ADDR 0xfec00cf8
#define MPC106_REG_DATA 0xfee00cfc
#define MPC106_ISA_MEM_PHYS 0xfd000000
#define MPC106_ISA_MEM_BUS 0x00000000
#define MPC106_ISA_MEM_SIZE 0x01000000
#define MPC106_ISA_IO_PHYS 0xfe000000
#define MPC106_ISA_IO_BUS 0x00000000
#define MPC106_ISA_IO_SIZE 0x00800000
#define MPC106_PCI_IO_PHYS 0xfe800000
#define MPC106_PCI_IO_BUS 0x00800000
#define MPC106_PCI_IO_SIZE 0x00400000
#define MPC106_PCI_MEM_PHYS 0x80000000
#define MPC106_PCI_MEM_BUS 0x80000000
#define MPC106_PCI_MEM_SIZE 0x7d000000
#define MPC106_PCI_MEMORY_PHYS 0x00000000
#define MPC106_PCI_MEMORY_BUS 0x00000000
#define MPC106_PCI_MEMORY_SIZE 0x40000000
#endif
#define CMD_SERR 0x0100
#define PCI_CMD_MASTER 0x0004
#define PCI_CMD_MEMEN 0x0002
#define PCI_CMD_IOEN 0x0001
#define PCI_STAT_NO_RSV_BITS 0xffff
#define PCI_BUSNUM 0x40
#define PCI_SUBBUSNUM 0x41
#define PCI_DISCOUNT 0x42
#define PCI_PICR1 0xA8
#define PICR1_CF_CBA(value) ((value & 0xff) << 24)
#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22)
#define PICR1_PROC_TYPE_603 0x40000
#define PICR1_PROC_TYPE_604 0x60000
#define PICR1_MCP_EN 0x800
#define PICR1_CF_DPARK 0x200
#define PICR1_CF_LOOP_SNOOP 0x10
#define PICR1_CF_L2_COPY_BACK 0x2
#define PICR1_CF_L2_CACHE_MASK 0x3
#define PICR1_CF_APARK 0x8
#define PICR1_ADDRESS_MAP 0x10000
#define PICR1_XIO_MODE 0x80000
#define PICR1_CF_CACHE_1G 0x200000
#define PCI_PICR2 0xAC
#define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18)
#define PICR2_CF_FLUSH_L2 0x10000000
#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9)
#define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2)
#define PICR2_CF_INV_MODE 0x00001000
#define PICR2_CF_MOD_HIGH 0x00020000
#define PICR2_CF_HIT_HIGH 0x00010000
#define PICR2_L2_SIZE_256K 0x00000000
#define PICR2_L2_SIZE_512K 0x00000010
#define PICR2_L2_SIZE_1MB 0x00000020
#define PICR2_L2_EN 0x40000000
#define PICR2_L2_UPDATE_EN 0x80000000
#define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000
#define PICR2_CF_FAST_CASTOUT 0x00000080
#define PICR2_CF_WDATA 0x00000001
#define PICR2_CF_DATA_RAM_PBURST 0x00400000
/*
* Memory controller
*/
#define MPC106_MCCR1 0xF0
#define MCCR1_TYPE_EDO 0x00020000
#define MCCR1_BK0_9BITS 0x0
#define MCCR1_BK0_10BITS 0x1
#define MCCR1_BK0_11BITS 0x2
#define MCCR1_BK0_12BITS 0x3
#define MCCR1_BK1_9BITS 0x0
#define MCCR1_BK1_10BITS 0x4
#define MCCR1_BK1_11BITS 0x8
#define MCCR1_BK1_12BITS 0xC
#define MCCR1_BK2_9BITS 0x00
#define MCCR1_BK2_10BITS 0x10
#define MCCR1_BK2_11BITS 0x20
#define MCCR1_BK2_12BITS 0x30
#define MCCR1_BK3_9BITS 0x00
#define MCCR1_BK3_10BITS 0x40
#define MCCR1_BK3_11BITS 0x80
#define MCCR1_BK3_12BITS 0xC0
#define MCCR1_MEMGO 0x00080000
#define MPC106_MCCR2 0xF4
#define MPC106_MCCR3 0xF8
#define MPC106_MCCR4 0xFC
#define MPC106_MSAR1 0x80
#define MPC106_EMSAR1 0x88
#define MPC106_EMSAR2 0x8C
#define MPC106_MEAR1 0x90
#define MPC106_EMEAR1 0x98
#define MPC106_EMEAR2 0x9C
#define MPC106_MBER 0xA0
#define MBER_BANK0 0x1
#define MBER_BANK1 0x2
#define MBER_BANK2 0x4
#define MBER_BANK3 0x8
#endif
|
1001-study-uboot
|
include/mpc106.h
|
C
|
gpl3
| 4,918
|
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __NIOS2_H__
#define __NIOS2_H__
/*------------------------------------------------------------------------
* Control registers -- use with wrctl() & rdctl()
*----------------------------------------------------------------------*/
#define CTL_STATUS 0 /* Processor status reg */
#define CTL_ESTATUS 1 /* Exception status reg */
#define CTL_BSTATUS 2 /* Break status reg */
#define CTL_IENABLE 3 /* Interrut enable reg */
#define CTL_IPENDING 4 /* Interrut pending reg */
/*------------------------------------------------------------------------
* Access to control regs
*----------------------------------------------------------------------*/
#define _str_(x) #x
#define rdctl(reg)\
({unsigned int val;\
asm volatile( "rdctl %0, ctl" _str_(reg)\
: "=r" (val) ); val;})
#define wrctl(reg,val)\
asm volatile( "wrctl ctl" _str_(reg) ",%0"\
: : "r" (val))
/*------------------------------------------------------------------------
* Control reg bit masks
*----------------------------------------------------------------------*/
#define STATUS_IE (1<<0) /* Interrupt enable */
#define STATUS_U (1<<1) /* User-mode */
/*------------------------------------------------------------------------
* Bit-31 Cache bypass -- only valid for data access. When data cache
* is not implemented, bit 31 is ignored for compatibility.
*----------------------------------------------------------------------*/
#define CACHE_BYPASS(a) ((a) | 0x80000000)
#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000)
#endif /* __NIOS2_H__ */
|
1001-study-uboot
|
include/nios2.h
|
C
|
gpl3
| 2,452
|
/*
* Broadcom BCM5221 Ethernet PHY
*
* (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
* Anders Larsen <alarsen@rea.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define BCM5221_BMCR 0 /* Basic Mode Control Register */
#define BCM5221_BMSR 1 /* Basic Mode Status Register */
#define BCM5221_PHYID1 2 /* PHY Identifier Register 1 */
#define BCM5221_PHYID2 3 /* PHY Identifier Register 2 */
#define BCM5221_ANAR 4 /* Auto-negotiation Advertisement Register */
#define BCM5221_ANLPAR 5 /* Auto-negotiation Link Partner Ability Register */
#define BCM5221_ANER 6 /* Auto-negotiation Expansion Register */
#define BCM5221_ACSR 24 /* Auxiliary Control/Status Register */
#define BCM5221_INTR 26 /* Interrupt Register */
/* --Bit definitions: BCM5221_BMCR */
#define BCM5221_RESET (1 << 15) /* 1= Software Reset; 0=Normal Operation */
#define BCM5221_LOOPBACK (1 << 14) /* 1=loopback Enabled; 0=Normal Operation */
#define BCM5221_SPEED_SELECT (1 << 13) /* 1=100Mbps; 0=10Mbps */
#define BCM5221_AUTONEG (1 << 12)
#define BCM5221_POWER_DOWN (1 << 11)
#define BCM5221_ISOLATE (1 << 10)
#define BCM5221_RESTART_AUTONEG (1 << 9)
#define BCM5221_DUPLEX_MODE (1 << 8)
#define BCM5221_COLLISION_TEST (1 << 7)
/*--Bit definitions: BCM5221_BMSR */
#define BCM5221_100BASE_T4 (1 << 15)
#define BCM5221_100BASE_TX_FD (1 << 14)
#define BCM5221_100BASE_TX_HD (1 << 13)
#define BCM5221_10BASE_T_FD (1 << 12)
#define BCM5221_10BASE_T_HD (1 << 11)
#define BCM5221_MF_PREAMB_SUPPR (1 << 6)
#define BCM5221_AUTONEG_COMP (1 << 5)
#define BCM5221_REMOTE_FAULT (1 << 4)
#define BCM5221_AUTONEG_ABILITY (1 << 3)
#define BCM5221_LINK_STATUS (1 << 2)
#define BCM5221_JABBER_DETECT (1 << 1)
#define BCM5221_EXTEND_CAPAB (1 << 0)
/*--definitions: BCM5221_PHYID1 */
#define BCM5221_PHYID1_OUI 0x1018
#define BCM5221_LSB_MASK 0x3F
/*--Bit definitions: BCM5221_ANAR, BCM5221_ANLPAR */
#define BCM5221_NP (1 << 15)
#define BCM5221_ACK (1 << 14)
#define BCM5221_RF (1 << 13)
#define BCM5221_FCS (1 << 10)
#define BCM5221_T4 (1 << 9)
#define BCM5221_TX_FDX (1 << 8)
#define BCM5221_TX_HDX (1 << 7)
#define BCM5221_10_FDX (1 << 6)
#define BCM5221_10_HDX (1 << 5)
#define BCM5221_AN_IEEE_802_3 0x0001
/*--Bit definitions: BCM5221_ANER */
#define BCM5221_PDF (1 << 4)
#define BCM5221_LP_NP_ABLE (1 << 3)
#define BCM5221_NP_ABLE (1 << 2)
#define BCM5221_PAGE_RX (1 << 1)
#define BCM5221_LP_AN_ABLE (1 << 0)
/*--Bit definitions: BCM5221_ACSR */
#define BCM5221_100 (1 << 1)
#define BCM5221_FDX (1 << 0)
/*--Bit definitions: BCM5221_INTR */
#define BCM5221_FDX_LED (1 << 15)
#define BCM5221_INTR_ENABLE (1 << 14)
#define BCM5221_FDX_MASK (1 << 11)
#define BCM5221_SPD_MASK (1 << 10)
#define BCM5221_LINK_MASK (1 << 9)
#define BCM5221_INTR_MASK (1 << 8)
#define BCM5221_FDX_CHG (1 << 3)
#define BCM5221_SPD_CHG (1 << 2)
#define BCM5221_LINK_CHG (1 << 1)
#define BCM5221_INTR_STATUS (1 << 0)
/****************** function prototypes **********************/
unsigned int bcm5221_IsPhyConnected(AT91PS_EMAC p_mac);
unsigned char bcm5221_GetLinkSpeed(AT91PS_EMAC p_mac);
unsigned char bcm5221_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
unsigned char bcm5221_InitPhy(AT91PS_EMAC p_mac);
|
1001-study-uboot
|
include/bcm5221.h
|
C
|
gpl3
| 3,947
|
/*
* (C) Copyright 2007-2008 Semihalf
*
* Written by: Rafal Jaworowski <raj@semihalf.com>
*
* This file is dual licensed; you can use it under the terms of
* either the GPL, or the BSD license, at your option.
*
* I. GPL:
*
* This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Alternatively,
*
* II. BSD license:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _API_PUBLIC_H_
#define _API_PUBLIC_H_
#define API_EINVAL 1 /* invalid argument(s) */
#define API_ENODEV 2 /* no device */
#define API_ENOMEM 3 /* no memory */
#define API_EBUSY 4 /* busy, occupied etc. */
#define API_EIO 5 /* I/O error */
#define API_ESYSC 6 /* syscall error */
typedef int (*scp_t)(int, int *, ...);
#define API_SIG_VERSION 1
#define API_SIG_MAGIC "UBootAPI"
#define API_SIG_MAGLEN 8
struct api_signature {
char magic[API_SIG_MAGLEN]; /* magic string */
uint16_t version; /* API version */
uint32_t checksum; /* checksum of this sig struct */
scp_t syscall; /* entry point to the API */
};
enum {
API_RSVD = 0,
API_GETC,
API_PUTC,
API_TSTC,
API_PUTS,
API_RESET,
API_GET_SYS_INFO,
API_UDELAY,
API_GET_TIMER,
API_DEV_ENUM,
API_DEV_OPEN,
API_DEV_CLOSE,
API_DEV_READ,
API_DEV_WRITE,
API_ENV_ENUM,
API_ENV_GET,
API_ENV_SET,
API_DISPLAY_GET_INFO,
API_DISPLAY_DRAW_BITMAP,
API_DISPLAY_CLEAR,
API_MAXCALL
};
#define MR_ATTR_FLASH 0x0001
#define MR_ATTR_DRAM 0x0002
#define MR_ATTR_SRAM 0x0003
struct mem_region {
unsigned long start;
unsigned long size;
int flags;
};
struct sys_info {
unsigned long clk_bus;
unsigned long clk_cpu;
unsigned long bar;
struct mem_region *mr;
int mr_no; /* number of memory regions */
};
#undef CONFIG_SYS_64BIT_LBA
#ifdef CONFIG_SYS_64BIT_LBA
typedef u_int64_t lbasize_t;
#else
typedef unsigned long lbasize_t;
#endif
typedef unsigned long lbastart_t;
#define DEV_TYP_NONE 0x0000
#define DEV_TYP_NET 0x0001
#define DEV_TYP_STOR 0x0002
#define DT_STOR_IDE 0x0010
#define DT_STOR_SCSI 0x0020
#define DT_STOR_USB 0x0040
#define DT_STOR_MMC 0x0080
#define DT_STOR_SATA 0x0100
#define DEV_STA_CLOSED 0x0000 /* invalid, closed */
#define DEV_STA_OPEN 0x0001 /* open i.e. active */
struct device_info {
int type;
void *cookie;
union {
struct {
lbasize_t block_count; /* no of blocks */
unsigned long block_size; /* size of one block */
} storage;
struct {
unsigned char hwaddr[6];
} net;
} info;
#define di_stor info.storage
#define di_net info.net
int state;
};
#define DISPLAY_TYPE_LCD 0x0001
#define DISPLAY_TYPE_VIDEO 0x0002
struct display_info {
int type;
/* screen size in pixels */
int pixel_width;
int pixel_height;
/* screen size in rows and columns of text */
int screen_rows;
int screen_cols;
};
#endif /* _API_PUBLIC_H_ */
|
1001-study-uboot
|
include/api_public.h
|
C
|
gpl3
| 4,659
|
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef MCD_TSK_INIT_H
#define MCD_TSK_INIT_H 1
/*
* Do not edit!
*/
/* Task 0 */
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr,
int xferSize, short xferSizeIncr, int *cSave,
volatile TaskTableEntry * taskTable, int channel);
/* Task 1 */
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr,
short destIncr, int dmaSize, short xferSizeIncr,
int flags, int *currBD, int *cSave,
volatile TaskTableEntry * taskTable, int channel);
/* Task 2 */
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr,
int xferSize, short xferSizeIncr, int *cSave,
volatile TaskTableEntry * taskTable, int channel);
/* Task 3 */
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr,
short destIncr, int dmaSize, short xferSizeIncr,
int flags, int *currBD, int *cSave,
volatile TaskTableEntry * taskTable, int channel);
/* Task 4 */
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr,
volatile TaskTableEntry * taskTable, int channel);
/* Task 5 */
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr,
volatile TaskTableEntry * taskTable, int channel);
#endif /* MCD_TSK_INIT_H */
|
1001-study-uboot
|
include/MCD_tasksInit.h
|
C
|
gpl3
| 2,111
|
/*
* MPC823 and PXA LCD Controller
*
* Modeled after video interface by Paolo Scaffardi
*
*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _LCD_H_
#define _LCD_H_
extern char lcd_is_enabled;
extern int lcd_line_length;
extern int lcd_color_fg;
extern int lcd_color_bg;
/*
* Frame buffer memory information
*/
extern void *lcd_base; /* Start of framebuffer memory */
extern void *lcd_console_address; /* Start of console buffer */
extern short console_col;
extern short console_row;
extern struct vidinfo panel_info;
extern void lcd_ctrl_init (void *lcdbase);
extern void lcd_enable (void);
/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
extern void lcd_setcolreg (ushort regno,
ushort red, ushort green, ushort blue);
extern void lcd_initcolregs (void);
/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
#if defined CONFIG_MPC823
/*
* LCD controller stucture for MPC823 CPU
*/
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
ushort vl_width; /* Width of display area in millimeters */
ushort vl_height; /* Height of display area in millimeters */
/* LCD configuration register */
u_char vl_clkp; /* Clock polarity */
u_char vl_oep; /* Output Enable polarity */
u_char vl_hsp; /* Horizontal Sync polarity */
u_char vl_vsp; /* Vertical Sync polarity */
u_char vl_dp; /* Data polarity */
u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
u_char vl_clor; /* Color, 0 = mono, 1 = color */
u_char vl_tft; /* 0 = passive, 1 = TFT */
/* Horizontal control register. Timing from data sheet */
ushort vl_wbl; /* Wait between lines */
/* Vertical control register */
u_char vl_vpw; /* Vertical sync pulse width */
u_char vl_lcdac; /* LCD AC timing */
u_char vl_wbf; /* Wait between frames */
} vidinfo_t;
#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
defined CONFIG_CPU_MONAHANS
/*
* PXA LCD DMA descriptor
*/
struct pxafb_dma_descriptor {
u_long fdadr; /* Frame descriptor address register */
u_long fsadr; /* Frame source address register */
u_long fidr; /* Frame ID register */
u_long ldcmd; /* Command register */
};
/*
* PXA LCD info
*/
struct pxafb_info {
/* Misc registers */
u_long reg_lccr3;
u_long reg_lccr2;
u_long reg_lccr1;
u_long reg_lccr0;
u_long fdadr0;
u_long fdadr1;
/* DMA descriptors */
struct pxafb_dma_descriptor * dmadesc_fblow;
struct pxafb_dma_descriptor * dmadesc_fbhigh;
struct pxafb_dma_descriptor * dmadesc_palette;
u_long screen; /* physical address of frame buffer */
u_long palette; /* physical address of palette memory */
u_int palette_size;
};
/*
* LCD controller stucture for PXA CPU
*/
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
ushort vl_width; /* Width of display area in millimeters */
ushort vl_height; /* Height of display area in millimeters */
/* LCD configuration register */
u_char vl_clkp; /* Clock polarity */
u_char vl_oep; /* Output Enable polarity */
u_char vl_hsp; /* Horizontal Sync polarity */
u_char vl_vsp; /* Vertical Sync polarity */
u_char vl_dp; /* Data polarity */
u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
u_char vl_clor; /* Color, 0 = mono, 1 = color */
u_char vl_tft; /* 0 = passive, 1 = TFT */
/* Horizontal control register. Timing from data sheet */
ushort vl_hpw; /* Horz sync pulse width */
u_char vl_blw; /* Wait before of line */
u_char vl_elw; /* Wait end of line */
/* Vertical control register. */
u_char vl_vpw; /* Vertical sync pulse width */
u_char vl_bfw; /* Wait before of frame */
u_char vl_efw; /* Wait end of frame */
/* PXA LCD controller params */
struct pxafb_info pxa;
} vidinfo_t;
#elif defined(CONFIG_ATMEL_LCD)
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 640) */
ushort vl_row; /* Number of rows (i.e. 480) */
u_long vl_clk; /* pixel clock in ps */
/* LCD configuration register */
u_long vl_sync; /* Horizontal / vertical sync */
u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
u_long vl_tft; /* 0 = passive, 1 = TFT */
u_long vl_cont_pol_low; /* contrast polarity is low */
/* Horizontal control register. */
u_long vl_hsync_len; /* Length of horizontal sync */
u_long vl_left_margin; /* Time from sync to picture */
u_long vl_right_margin; /* Time from picture to sync */
/* Vertical control register. */
u_long vl_vsync_len; /* Length of vertical sync */
u_long vl_upper_margin; /* Time from sync to picture */
u_long vl_lower_margin; /* Time from picture to sync */
u_long mmio; /* Memory mapped registers */
} vidinfo_t;
#else
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 160) */
ushort vl_row; /* Number of rows (i.e. 100) */
u_char vl_bpix; /* Bits per pixel, 0 = 1 */
ushort *cmap; /* Pointer to the colormap */
void *priv; /* Pointer to driver-specific data */
} vidinfo_t;
#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
extern vidinfo_t panel_info;
/* Video functions */
#if defined(CONFIG_RBC823)
void lcd_disable (void);
#endif
/* int lcd_init (void *lcdbase); */
void lcd_putc (const char c);
void lcd_puts (const char *s);
void lcd_printf (const char *fmt, ...);
void lcd_clear(void);
int lcd_display_bitmap(ulong bmp_image, int x, int y);
/* Allow boards to customize the information displayed */
void lcd_show_board_info(void);
/************************************************************************/
/* ** BITMAP DISPLAY SUPPORT */
/************************************************************************/
#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
# include <bmp_layout.h>
# include <asm/byteorder.h>
#endif
/*
* Information about displays we are using. This is for configuring
* the LCD controller and memory allocation. Someone has to know what
* is connected, as we can't autodetect anything.
*/
#define CONFIG_SYS_HIGH 0 /* Pins are active high */
#define CONFIG_SYS_LOW 1 /* Pins are active low */
#define LCD_MONOCHROME 0
#define LCD_COLOR2 1
#define LCD_COLOR4 2
#define LCD_COLOR8 3
#define LCD_COLOR16 4
/*----------------------------------------------------------------------*/
#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
# define LCD_INFO_X 0
# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
#elif defined(CONFIG_LCD_LOGO)
# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH)
# define LCD_INFO_Y (VIDEO_FONT_HEIGHT)
#else
# define LCD_INFO_X (VIDEO_FONT_WIDTH)
# define LCD_INFO_Y (VIDEO_FONT_HEIGHT)
#endif
/* Default to 8bpp if bit depth not specified */
#ifndef LCD_BPP
# define LCD_BPP LCD_COLOR8
#endif
#ifndef LCD_DF
# define LCD_DF 1
#endif
/* Calculate nr. of bits per pixel and nr. of colors */
#define NBITS(bit_code) (1 << (bit_code))
#define NCOLORS(bit_code) (1 << NBITS(bit_code))
/************************************************************************/
/* ** CONSOLE CONSTANTS */
/************************************************************************/
#if LCD_BPP == LCD_MONOCHROME
/*
* Simple black/white definitions
*/
# define CONSOLE_COLOR_BLACK 0
# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */
#elif LCD_BPP == LCD_COLOR8
/*
* 8bpp color definitions
*/
# define CONSOLE_COLOR_BLACK 0
# define CONSOLE_COLOR_RED 1
# define CONSOLE_COLOR_GREEN 2
# define CONSOLE_COLOR_YELLOW 3
# define CONSOLE_COLOR_BLUE 4
# define CONSOLE_COLOR_MAGENTA 5
# define CONSOLE_COLOR_CYAN 6
# define CONSOLE_COLOR_GREY 14
# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
#else
/*
* 16bpp color definitions
*/
# define CONSOLE_COLOR_BLACK 0x0000
# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
#endif /* color definitions */
/************************************************************************/
#ifndef PAGE_SIZE
# define PAGE_SIZE 4096
#endif
/************************************************************************/
/* ** CONSOLE DEFINITIONS & FUNCTIONS */
/************************************************************************/
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
# define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \
/ VIDEO_FONT_HEIGHT)
#else
# define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT)
#endif
#define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH)
#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length)
#define CONSOLE_ROW_FIRST (lcd_console_address)
#define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE)
#define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \
- CONSOLE_ROW_SIZE)
#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS)
#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE)
#if LCD_BPP == LCD_MONOCHROME
# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \
(c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
# define COLOR_MASK(c) (c)
#else
# error Unsupported LCD BPP.
#endif
/************************************************************************/
#endif /* _LCD_H_ */
|
1001-study-uboot
|
include/lcd.h
|
C
|
gpl3
| 10,431
|
/* Collection of constants used to access Nomadik registers */
#ifndef __NOMADIK_H__
#define __NOMADIK_H__
/* Base addresses of our peripherals */
#define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */
#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */
#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */
#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */
#define NOMADIK_1NAND_BASE 0x30000000
#define NOMADIK_GPIO0_BASE 0x101E4000
#define NOMADIK_GPIO1_BASE 0x101E5000
#define NOMADIK_GPIO2_BASE 0x101E6000
#define NOMADIK_GPIO3_BASE 0x101E7000
#define NOMADIK_CPLD_BASE 0x36000000
#define NOMADIK_UART0_BASE 0x101FD000
#define NOMADIK_UART1_BASE 0x101FB000
#define NOMADIK_UART2_BASE 0x101F2000
#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */
#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */
#define NOMADIK_RTC_BASE 0x101E8000
#define NOMADIK_ETH0_BASE 0x36800300
#define NOMADIK_CPLD_UART_BASE 0x36480000
/* Chip select registers ("Flexible Static Memory Controller") */
#define REG_FSMC_BCR0 (NOMADIK_FSMC_BASE + 0x00)
#define REG_FSMC_BTR0 (NOMADIK_FSMC_BASE + 0x04)
#define REG_FSMC_BCR1 (NOMADIK_FSMC_BASE + 0x08)
#define REG_FSMC_BTR1 (NOMADIK_FSMC_BASE + 0x0c)
#define REG_FSMC_PCR0 (NOMADIK_FSMC_BASE + 0x40)
#define REG_FSMC_PMEM0 (NOMADIK_FSMC_BASE + 0x48)
#define REG_FSMC_PATT0 (NOMADIK_FSMC_BASE + 0x4c)
#define REG_FSMC_ECCR0 (NOMADIK_FSMC_BASE + 0x54)
#endif /* __NOMADIK_H__ */
|
1001-study-uboot
|
include/nomadik.h
|
C
|
gpl3
| 1,520
|
/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* lh7a40x SoC series common interface
*/
#ifndef __LH7A40X_H__
#define __LH7A40X_H__
/* (SMC) Static Memory Controller (usersguide 4.2.1) */
typedef struct {
volatile u32 attib;
volatile u32 com;
volatile u32 io;
volatile u32 rsvd1;
} /*__attribute__((__packed__))*/ lh7a40x_pccard_t;
typedef struct {
volatile u32 bcr[8];
lh7a40x_pccard_t pccard[2];
volatile u32 pcmciacon;
} /*__attribute__((__packed__))*/ lh7a40x_smc_t;
#define LH7A40X_SMC_BASE (0x80002000)
#define LH7A40X_SMC_PTR ((lh7a40x_smc_t*) LH7A40X_SMC_BASE)
/* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */
typedef struct {
volatile u32 rsvd1;
volatile u32 gblcnfg;
volatile u32 rfshtmr;
volatile u32 bootstat;
volatile u32 sdcsc[4];
} /*__attribute__((__packed__))*/ lh7a40x_sdmc_t;
#define LH7A40X_SDMC_BASE (0x80002400)
#define LH7A40X_SDMC_PTR ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE)
/* (CSC) Clock and State Controller (userguide 6.2.1) */
typedef struct {
volatile u32 pwrsr;
volatile u32 pwrcnt;
volatile u32 halt;
volatile u32 stby;
volatile u32 bleoi;
volatile u32 mceoi;
volatile u32 teoi;
volatile u32 stfclr;
volatile u32 clkset;
volatile u32 scrreg[2];
volatile u32 rsvd1;
volatile u32 usbreset;
} /*__attribute__((__packed__))*/ lh7a40x_csc_t;
#define LH7A40X_STPWR_BASE (0x80000400)
#define LH7A40X_CSC_PTR ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE)
#define CLKSET_SMCROM (0x01000000)
#define CLKSET_PS (0x000C0000)
#define CLKSET_PS_0 (0x00000000)
#define CLKSET_PS_1 (0x00040000)
#define CLKSET_PS_2 (0x00080000)
#define CLKSET_PS_3 (0x000C0000)
#define CLKSET_PCLKDIV (0x00030000)
#define CLKSET_PCLKDIV_2 (0x00000000)
#define CLKSET_PCLKDIV_4 (0x00010000)
#define CLKSET_PCLKDIV_8 (0x00020000)
#define CLKSET_MAINDIV2 (0x0000f800)
#define CLKSET_MAINDIV1 (0x00000780)
#define CLKSET_PREDIV (0x0000007C)
#define CLKSET_HCLKDIV (0x00000003)
/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
typedef struct {
volatile u32 maxcnt;
volatile u32 base;
volatile u32 current;
volatile u32 rsvd1;
} lh7a40x_dmabuf_t;
typedef struct {
volatile u32 control;
volatile u32 interrupt;
volatile u32 rsvd1;
volatile u32 status;
volatile u32 rsvd2;
volatile u32 remain;
volatile u32 rsvd3;
volatile u32 rsvd4;
lh7a40x_dmabuf_t buf[2];
} /*__attribute__((__packed__))*/ lh7a40x_dmachan_t;
/* (WDT) Watchdog Timer (userguide 11.2.1) */
typedef struct {
volatile u32 ctl;
volatile u32 rst;
volatile u32 status;
volatile u32 count[4];
} /*__attribute__((__packed__))*/ lh7a40x_wdt_t;
#define LH7A40X_WDT_BASE (0x80001400)
#define LH7A40X_WDT_PTR ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE)
/* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */
typedef struct {
volatile u32 rtcdr;
volatile u32 rtclr;
volatile u32 rtcmr;
volatile u32 unk1;
volatile u32 rtcstat_eoi;
volatile u32 rtccr;
volatile u32 rsvd1[58];
} /*__attribute__((__packed__))*/ lh7a40x_rtc_t;
#define LH7A40X_RTC_BASE (0x80000D00)
#define LH7A40X_RTC_PTR ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE)
/* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */
typedef struct {
volatile u32 load;
volatile u32 value;
volatile u32 control;
volatile u32 tceoi;
} /*__attribute__((__packed__))*/ lh7a40x_timer_t;
typedef struct {
lh7a40x_timer_t timer1;
volatile u32 rsvd1[4];
lh7a40x_timer_t timer2;
volatile u32 unk1[4];
volatile u32 bzcon;
volatile u32 unk2[15];
lh7a40x_timer_t timer3;
/*volatile u32 rsvd2;*/
} /*__attribute__((__packed__))*/ lh7a40x_timers_t;
#define LH7A40X_TIMERS_BASE (0x80000C00)
#define LH7A40X_TIMERS_PTR ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE)
#define TIMER_EN (0x00000080)
#define TIMER_PER (0x00000040)
#define TIMER_FREE (0x00000000)
#define TIMER_CLK508K (0x00000008)
#define TIMER_CLK2K (0x00000000)
/* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */
typedef struct {
volatile u32 cr0;
volatile u32 cr1;
volatile u32 irr_roeoi;
volatile u32 dr;
volatile u32 cpr;
volatile u32 sr;
/*volatile u32 rsvd1[58];*/
} /*__attribute__((__packed__))*/ lh7a40x_ssp_t;
#define LH7A40X_SSP_BASE (0x80000B00)
#define LH7A40X_SSP_PTR ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE)
/* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */
typedef struct {
volatile u32 data;
volatile u32 fcon;
volatile u32 brcon;
volatile u32 con;
volatile u32 status;
volatile u32 rawisr;
volatile u32 inten;
volatile u32 isr;
volatile u32 rsvd1[56];
} /*__attribute__((__packed__))*/ lh7a40x_uart_t;
#define LH7A40X_UART_BASE (0x80000600)
#define LH7A40X_UART_PTR(n) \
((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t))))
#define UART_BE (0x00000800) /* the rx error bits */
#define UART_OE (0x00000400)
#define UART_PE (0x00000200)
#define UART_FE (0x00000100)
#define UART_WLEN (0x00000060) /* fcon bits */
#define UART_WLEN_8 (0x00000060)
#define UART_WLEN_7 (0x00000040)
#define UART_WLEN_6 (0x00000020)
#define UART_WLEN_5 (0x00000000)
#define UART_FEN (0x00000010)
#define UART_STP2 (0x00000008)
#define UART_STP2_2 (0x00000008)
#define UART_STP2_1 (0x00000000)
#define UART_EPS (0x00000004)
#define UART_EPS_EVEN (0x00000004)
#define UART_EPS_ODD (0x00000000)
#define UART_PEN (0x00000002)
#define UART_BRK (0x00000001)
#define UART_BAUDDIV (0x0000ffff) /* brcon bits */
#define UART_SIRBD (0x00000080) /* con bits */
#define UART_LBE (0x00000040)
#define UART_MXP (0x00000020)
#define UART_TXP (0x00000010)
#define UART_RXP (0x00000008)
#define UART_SIRLP (0x00000004)
#define UART_SIRD (0x00000002)
#define UART_EN (0x00000001)
#define UART_TXFE (0x00000080) /* status bits */
#define UART_RXFF (0x00000040)
#define UART_TXFF (0x00000020)
#define UART_RXFE (0x00000010)
#define UART_BUSY (0x00000008)
#define UART_DCD (0x00000004)
#define UART_DSR (0x00000002)
#define UART_CTS (0x00000001)
#define UART_MSEOI (0xfffffff0) /* rawisr interrupt bits */
#define UART_RTI (0x00000008) /* generic interrupt bits */
#define UART_MI (0x00000004)
#define UART_TI (0x00000002)
#define UART_RI (0x00000001)
/* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */
typedef struct {
volatile u32 pad;
volatile u32 pbd;
volatile u32 pcd;
volatile u32 pdd;
volatile u32 padd;
volatile u32 pbdd;
volatile u32 pcdd;
volatile u32 pddd;
volatile u32 ped;
volatile u32 pedd;
volatile u32 kbdctl;
volatile u32 pinmux;
volatile u32 pfd;
volatile u32 pfdd;
volatile u32 pgd;
volatile u32 pgdd;
volatile u32 phd;
volatile u32 phdd;
volatile u32 rsvd1;
volatile u32 inttype1;
volatile u32 inttype2;
volatile u32 gpiofeoi;
volatile u32 gpiointen;
volatile u32 intstatus;
volatile u32 rawintstatus;
volatile u32 gpiodb;
volatile u32 papd;
volatile u32 pbpd;
volatile u32 pcpd;
volatile u32 pdpd;
volatile u32 pepd;
volatile u32 pfpd;
volatile u32 pgpd;
volatile u32 phpd;
} /*__attribute__((__packed__))*/ lh7a40x_gpioint_t;
#define LH7A40X_GPIOINT_BASE (0x80000E00)
#define LH7A40X_GPIOINT_PTR ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE)
/* Embedded SRAM */
#define CONFIG_SYS_SRAM_BASE (0xB0000000)
#define CONFIG_SYS_SRAM_SIZE (80*1024) /* 80kB */
#endif /* __LH7A40X_H__ */
|
1001-study-uboot
|
include/lh7a40x.h
|
C
|
gpl3
| 8,228
|
#ifndef __SATA_H__
#define __SATA_H__
int init_sata(int dev);
int scan_sata(int dev);
ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer);
ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer);
int sata_initialize(void);
int __sata_initialize(void);
#endif
|
1001-study-uboot
|
include/sata.h
|
C
|
gpl3
| 293
|
/**
* \file sha1.h
* based from http://xyssl.org/code/source/sha1/
* FIPS-180-1 compliant SHA-1 implementation
*
* Copyright (C) 2003-2006 Christophe Devine
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License, version 2.1 as published by the Free Software Foundation.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/*
* The SHA-1 standard was published by NIST in 1993.
*
* http://www.itl.nist.gov/fipspubs/fip180-1.htm
*/
#ifndef _SHA1_H
#define _SHA1_H
#ifdef __cplusplus
extern "C" {
#endif
#define SHA1_SUM_POS -0x20
#define SHA1_SUM_LEN 20
/**
* \brief SHA-1 context structure
*/
typedef struct
{
unsigned long total[2]; /*!< number of bytes processed */
unsigned long state[5]; /*!< intermediate digest state */
unsigned char buffer[64]; /*!< data block being processed */
}
sha1_context;
/**
* \brief SHA-1 context setup
*
* \param ctx SHA-1 context to be initialized
*/
void sha1_starts( sha1_context *ctx );
/**
* \brief SHA-1 process buffer
*
* \param ctx SHA-1 context
* \param input buffer holding the data
* \param ilen length of the input data
*/
void sha1_update( sha1_context *ctx, unsigned char *input, int ilen );
/**
* \brief SHA-1 final digest
*
* \param ctx SHA-1 context
* \param output SHA-1 checksum result
*/
void sha1_finish( sha1_context *ctx, unsigned char output[20] );
/**
* \brief Output = SHA-1( input buffer )
*
* \param input buffer holding the data
* \param ilen length of the input data
* \param output SHA-1 checksum result
*/
void sha1_csum( unsigned char *input, int ilen,
unsigned char output[20] );
/**
* \brief Output = SHA-1( input buffer ), with watchdog triggering
*
* \param input buffer holding the data
* \param ilen length of the input data
* \param output SHA-1 checksum result
* \param chunk_sz watchdog triggering period (in bytes of input processed)
*/
void sha1_csum_wd (unsigned char *input, int ilen,
unsigned char output[20], unsigned int chunk_sz);
/**
* \brief Output = SHA-1( file contents )
*
* \param path input file name
* \param output SHA-1 checksum result
* \return 0 if successful, or 1 if fopen failed
*/
int sha1_file( char *path, unsigned char output[20] );
/**
* \brief Output = HMAC-SHA-1( input buffer, hmac key )
*
* \param key HMAC secret key
* \param keylen length of the HMAC key
* \param input buffer holding the data
* \param ilen length of the input data
* \param output HMAC-SHA-1 result
*/
void sha1_hmac( unsigned char *key, int keylen,
unsigned char *input, int ilen,
unsigned char output[20] );
/**
* \brief Checkup routine
*
* \return 0 if successful, or 1 if the test failed
*/
int sha1_self_test( void );
#ifdef __cplusplus
}
#endif
#endif /* sha1.h */
|
1001-study-uboot
|
include/sha1.h
|
C
|
gpl3
| 3,363
|
/*
* (C) Copyright 2001
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Digital Thermometers and Thermostats.
*/
#ifndef _DTT_H_
#define _DTT_H_
#if defined(CONFIG_DTT_ADM1021) || \
defined(CONFIG_DTT_ADT7460) || \
defined(CONFIG_DTT_DS1621) || \
defined(CONFIG_DTT_DS1775) || \
defined(CONFIG_DTT_LM63) || \
defined(CONFIG_DTT_LM73) || \
defined(CONFIG_DTT_LM75) || \
defined(CONFIG_DTT_LM81)
#define CONFIG_DTT /* We have a DTT */
#ifndef CONFIG_DTT_ADM1021
#define DTT_COMMERCIAL_MAX_TEMP 70 /* 0 - +70 C */
#define DTT_INDUSTRIAL_MAX_TEMP 85 /* -40 - +85 C */
#define DTT_AUTOMOTIVE_MAX_TEMP 105 /* -40 - +105 C */
#ifndef CONFIG_SYS_DTT_MAX_TEMP
#define CONFIG_SYS_DTT_MAX_TEMP DTT_COMMERCIAL_MAX_TEMP
#endif
#ifndef CONFIG_SYS_DTT_HYSTERESIS
#define CONFIG_SYS_DTT_HYSTERESIS 5 /* 5 C */
#endif
#endif /* CONFIG_DTT_ADM1021 */
extern void dtt_init(void);
extern int dtt_init_one(int);
extern int dtt_read(int sensor, int reg);
extern int dtt_write(int sensor, int reg, int val);
extern int dtt_get_temp(int sensor);
#endif
#endif /* _DTT_H_ */
|
1001-study-uboot
|
include/dtt.h
|
C
|
gpl3
| 1,910
|
/*
* (C) Copyright 2009
* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _TWS_H_
#define _TWS_H_
/*
* Read/Write interface:
* buffer: Where to read/write the data
* len: How many bits to read/write
*
* Returns: 0 on success, not 0 on failure
*/
int tws_read(uchar *buffer, int len);
int tws_write(uchar *buffer, int len);
#endif /* _TWS_H_ */
|
1001-study-uboot
|
include/tws.h
|
C
|
gpl3
| 1,183
|
/*
* Ethernet: An implementation of the Ethernet Device Driver suite for the
* uClinux 2.0.38 operating system. This Driver has been developed
* for AT75C220 board.
*
* NOTE: The driver is implemented for one MAC
*
* Version: @(#)at91rm9200_net.h 1.0.0 01/10/2001
*
* Authors: Lineo Inc <www.lineo.com>
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef AT91RM9200_ETHERNET
#define AT91RM9200_ETHERNET
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#define FALSE 0
#define TRUE 1
#define ETHERNET_ADDRESS_SIZE 6
typedef unsigned char UCHAR;
/* Interface to drive the physical layer */
typedef struct _AT91S_PhyOps
{
unsigned char (*Init)(AT91S_EMAC *pmac);
unsigned int (*IsPhyConnected)(AT91S_EMAC *pmac);
unsigned char (*GetLinkSpeed)(AT91S_EMAC *pmac);
unsigned char (*AutoNegotiate)(AT91S_EMAC *pmac, int *);
} AT91S_PhyOps,*AT91PS_PhyOps;
#define EMAC_DESC_DONE 0x00000001 /* ownership bit */
#define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */
/****************** function prototypes **********************/
/* MII functions */
void at91rm9200_EmacEnableMDIO(AT91PS_EMAC p_mac);
void at91rm9200_EmacDisableMDIO(AT91PS_EMAC p_mac);
UCHAR at91rm9200_EmacReadPhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pInput);
UCHAR at91rm9200_EmacWritePhy(AT91PS_EMAC p_mac, unsigned char RegisterAddress, unsigned short *pOutput);
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops);
#endif /* AT91RM9200_ETHERNET */
|
1001-study-uboot
|
include/at91rm9200_net.h
|
C
|
gpl3
| 1,727
|
/*
* Copyright (c) 2011 The Chromium OS Authors.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _INCLUDE_TPM_H_
#define _INCLUDE_TPM_H_
#include <common.h>
/*
* tis_init()
*
* Initialize the TPM device. Returns 0 on success or -1 on
* failure (in case device probing did not succeed).
*/
int tis_init(void);
/*
* tis_open()
*
* Requests access to locality 0 for the caller. After all commands have been
* completed the caller is supposed to call tis_close().
*
* Returns 0 on success, -1 on failure.
*/
int tis_open(void);
/*
* tis_close()
*
* terminate the currect session with the TPM by releasing the locked
* locality. Returns 0 on success of -1 on failure (in case lock
* removal did not succeed).
*/
int tis_close(void);
/*
* tis_sendrecv()
*
* Send the requested data to the TPM and then try to get its response
*
* @sendbuf - buffer of the data to send
* @send_size size of the data to send
* @recvbuf - memory to save the response to
* @recv_len - pointer to the size of the response buffer
*
* Returns 0 on success (and places the number of response bytes at recv_len)
* or -1 on failure.
*/
int tis_sendrecv(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf,
size_t *recv_len);
#endif /* _INCLUDE_TPM_H_ */
|
1001-study-uboot
|
include/tpm.h
|
C
|
gpl3
| 2,028
|
/*
* This file is a modified version of bzlib.h from the bzip2-1.0.2
* distribution which can be found at http://sources.redhat.com/bzip2/
*/
/*-------------------------------------------------------------*/
/*--- Public header file for the library. ---*/
/*--- bzlib.h ---*/
/*-------------------------------------------------------------*/
/*--
This file is a part of bzip2 and/or libbzip2, a program and
library for lossless, block-sorting data compression.
Copyright (C) 1996-2002 Julian R Seward. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. The origin of this software must not be misrepresented; you must
not claim that you wrote the original software. If you use this
software in a product, an acknowledgment in the product
documentation would be appreciated but is not required.
3. Altered source versions must be plainly marked as such, and must
not be misrepresented as being the original software.
4. The name of the author may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Julian Seward, Cambridge, UK.
jseward@acm.org
bzip2/libbzip2 version 1.0 of 21 March 2000
This program is based on (at least) the work of:
Mike Burrows
David Wheeler
Peter Fenwick
Alistair Moffat
Radford Neal
Ian H. Witten
Robert Sedgewick
Jon L. Bentley
For more information on these sources, see the manual.
--*/
#ifndef _BZLIB_H
#define _BZLIB_H
/* Configure for U-Boot environment */
#define BZ_NO_STDIO
#define BZ_NO_COMPRESS
/* End of configuration for U-Boot environment */
#ifdef __cplusplus
extern "C" {
#endif
#define BZ_RUN 0
#define BZ_FLUSH 1
#define BZ_FINISH 2
#define BZ_OK 0
#define BZ_RUN_OK 1
#define BZ_FLUSH_OK 2
#define BZ_FINISH_OK 3
#define BZ_STREAM_END 4
#define BZ_SEQUENCE_ERROR (-1)
#define BZ_PARAM_ERROR (-2)
#define BZ_MEM_ERROR (-3)
#define BZ_DATA_ERROR (-4)
#define BZ_DATA_ERROR_MAGIC (-5)
#define BZ_IO_ERROR (-6)
#define BZ_UNEXPECTED_EOF (-7)
#define BZ_OUTBUFF_FULL (-8)
#define BZ_CONFIG_ERROR (-9)
typedef
struct {
char *next_in;
unsigned int avail_in;
unsigned int total_in_lo32;
unsigned int total_in_hi32;
char *next_out;
unsigned int avail_out;
unsigned int total_out_lo32;
unsigned int total_out_hi32;
void *state;
void *(*bzalloc)(void *,int,int);
void (*bzfree)(void *,void *);
void *opaque;
}
bz_stream;
#ifndef BZ_IMPORT
#define BZ_EXPORT
#endif
#ifdef _WIN32
# include <windows.h>
# ifdef small
/* windows.h define small to char */
# undef small
# endif
# ifdef BZ_EXPORT
# define BZ_API(func) WINAPI func
# define BZ_EXTERN extern
# else
/* import windows dll dynamically */
# define BZ_API(func) (WINAPI * func)
# define BZ_EXTERN
# endif
#else
# define BZ_API(func) func
# define BZ_EXTERN extern
#endif
/*-- Core (low-level) library functions --*/
BZ_EXTERN int BZ_API(BZ2_bzCompressInit) (
bz_stream* strm,
int blockSize100k,
int verbosity,
int workFactor
);
BZ_EXTERN int BZ_API(BZ2_bzCompress) (
bz_stream* strm,
int action
);
BZ_EXTERN int BZ_API(BZ2_bzCompressEnd) (
bz_stream* strm
);
BZ_EXTERN int BZ_API(BZ2_bzDecompressInit) (
bz_stream *strm,
int verbosity,
int small
);
BZ_EXTERN int BZ_API(BZ2_bzDecompress) (
bz_stream* strm
);
BZ_EXTERN int BZ_API(BZ2_bzDecompressEnd) (
bz_stream *strm
);
/*-- High(er) level library functions --*/
#ifndef BZ_NO_STDIO
#define BZ_MAX_UNUSED 5000
/* Need a definitition for FILE */
#include <stdio.h>
typedef void BZFILE;
BZ_EXTERN BZFILE* BZ_API(BZ2_bzReadOpen) (
int* bzerror,
FILE* f,
int verbosity,
int small,
void* unused,
int nUnused
);
BZ_EXTERN void BZ_API(BZ2_bzReadClose) (
int* bzerror,
BZFILE* b
);
BZ_EXTERN void BZ_API(BZ2_bzReadGetUnused) (
int* bzerror,
BZFILE* b,
void** unused,
int* nUnused
);
BZ_EXTERN int BZ_API(BZ2_bzRead) (
int* bzerror,
BZFILE* b,
void* buf,
int len
);
BZ_EXTERN BZFILE* BZ_API(BZ2_bzWriteOpen) (
int* bzerror,
FILE* f,
int blockSize100k,
int verbosity,
int workFactor
);
BZ_EXTERN void BZ_API(BZ2_bzWrite) (
int* bzerror,
BZFILE* b,
void* buf,
int len
);
BZ_EXTERN void BZ_API(BZ2_bzWriteClose) (
int* bzerror,
BZFILE* b,
int abandon,
unsigned int* nbytes_in,
unsigned int* nbytes_out
);
BZ_EXTERN void BZ_API(BZ2_bzWriteClose64) (
int* bzerror,
BZFILE* b,
int abandon,
unsigned int* nbytes_in_lo32,
unsigned int* nbytes_in_hi32,
unsigned int* nbytes_out_lo32,
unsigned int* nbytes_out_hi32
);
#endif
/*-- Utility functions --*/
BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffCompress) (
char* dest,
unsigned int* destLen,
char* source,
unsigned int sourceLen,
int blockSize100k,
int verbosity,
int workFactor
);
BZ_EXTERN int BZ_API(BZ2_bzBuffToBuffDecompress) (
char* dest,
unsigned int* destLen,
char* source,
unsigned int sourceLen,
int small,
int verbosity
);
/*--
Code contributed by Yoshioka Tsuneo
(QWF00133@niftyserve.or.jp/tsuneo-y@is.aist-nara.ac.jp),
to support better zlib compatibility.
This code is not _officially_ part of libbzip2 (yet);
I haven't tested it, documented it, or considered the
threading-safeness of it.
If this code breaks, please contact both Yoshioka and me.
--*/
BZ_EXTERN const char * BZ_API(BZ2_bzlibVersion) (
void
);
#ifndef BZ_NO_STDIO
BZ_EXTERN BZFILE * BZ_API(BZ2_bzopen) (
const char *path,
const char *mode
);
BZ_EXTERN BZFILE * BZ_API(BZ2_bzdopen) (
int fd,
const char *mode
);
BZ_EXTERN int BZ_API(BZ2_bzread) (
BZFILE* b,
void* buf,
int len
);
BZ_EXTERN int BZ_API(BZ2_bzwrite) (
BZFILE* b,
void* buf,
int len
);
BZ_EXTERN int BZ_API(BZ2_bzflush) (
BZFILE* b
);
BZ_EXTERN void BZ_API(BZ2_bzclose) (
BZFILE* b
);
BZ_EXTERN const char * BZ_API(BZ2_bzerror) (
BZFILE *b,
int *errnum
);
#endif
#ifdef __cplusplus
}
#endif
#endif
/*-------------------------------------------------------------*/
/*--- end bzlib.h ---*/
/*-------------------------------------------------------------*/
|
1001-study-uboot
|
include/bzlib.h
|
C
|
gpl3
| 8,005
|
#ifndef _AT45_H_
#define _AT45_H_
#ifdef CONFIG_DATAFLASH_MMC_SELECT
extern void AT91F_SelectMMC(void);
extern void AT91F_SelectSPI(void);
extern int AT91F_GetMuxStatus(void);
#endif
extern void AT91F_SpiInit(void);
extern void AT91F_SpiEnable(int cs);
extern unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc );
extern AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
AT91PS_DataFlash pDataFlash,
unsigned char OpCode,
unsigned int CmdSize,
unsigned int DataflashAddress);
extern AT91S_DataFlashStatus AT91F_DataFlashGetStatus (
AT91PS_DataflashDesc pDesc);
extern AT91S_DataFlashStatus AT91F_DataFlashWaitReady (
AT91PS_DataflashDesc pDataFlashDesc,
unsigned int timeout);
extern AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
AT91PS_DataFlash pDataFlash,
int src,
unsigned char *dataBuffer,
int sizeToRead );
extern AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int SizeToWrite);
extern AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int page);
extern AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned char *dataBuffer,
unsigned int bufferAddress,
int SizeToWrite );
extern AT91S_DataFlashStatus AT91F_PageErase(
AT91PS_DataFlash pDataFlash,
unsigned int page);
extern AT91S_DataFlashStatus AT91F_BlockErase(
AT91PS_DataFlash pDataFlash,
unsigned int block);
extern AT91S_DataFlashStatus AT91F_WriteBufferToMain (
AT91PS_DataFlash pDataFlash,
unsigned char BufferCommand,
unsigned int dest );
extern AT91S_DataFlashStatus AT91F_PartialPageWrite (
AT91PS_DataFlash pDataFlash,
unsigned char *src,
unsigned int dest,
unsigned int size);
extern AT91S_DataFlashStatus AT91F_DataFlashWrite(
AT91PS_DataFlash pDataFlash,
unsigned char *src,
int dest,
int size );
extern int AT91F_DataFlashRead(
AT91PS_DataFlash pDataFlash,
unsigned long addr,
unsigned long size,
char *buffer);
extern int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc);
#endif
|
1001-study-uboot
|
include/at45.h
|
C
|
gpl3
| 2,140
|
/*
* DP83848 ethernet Physical layer
*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */
#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */
#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */
#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */
#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */
#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */
#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */
#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */
#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */
#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */
/*--Bit definitions: DP83848_CTL_REG */
#define DP83848_RESET (1 << 15) /* 1= S/W Reset */
#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */
#define DP83848_SPEED_SELECT (1 << 13)
#define DP83848_AUTONEG (1 << 12)
#define DP83848_POWER_DOWN (1 << 11)
#define DP83848_ISOLATE (1 << 10)
#define DP83848_RESTART_AUTONEG (1 << 9)
#define DP83848_DUPLEX_MODE (1 << 8)
#define DP83848_COLLISION_TEST (1 << 7)
/*--Bit definitions: DP83848_STAT_REG */
#define DP83848_100BASE_T4 (1 << 15)
#define DP83848_100BASE_TX_FD (1 << 14)
#define DP83848_100BASE_TX_HD (1 << 13)
#define DP83848_10BASE_T_FD (1 << 12)
#define DP83848_10BASE_T_HD (1 << 11)
#define DP83848_MF_PREAMB_SUPPR (1 << 6)
#define DP83848_AUTONEG_COMP (1 << 5)
#define DP83848_RMT_FAULT (1 << 4)
#define DP83848_AUTONEG_ABILITY (1 << 3)
#define DP83848_LINK_STATUS (1 << 2)
#define DP83848_JABBER_DETECT (1 << 1)
#define DP83848_EXTEND_CAPAB (1 << 0)
/*--definitions: DP83848_PHYID1 */
#define DP83848_PHYID1_OUI 0x2000
#define DP83848_PHYID2_OUI 0x5c90
/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
#define DP83848_NP (1 << 15)
#define DP83848_ACK (1 << 14)
#define DP83848_RF (1 << 13)
#define DP83848_PAUSE (1 << 10)
#define DP83848_T4 (1 << 9)
#define DP83848_TX_FDX (1 << 8)
#define DP83848_TX_HDX (1 << 7)
#define DP83848_10_FDX (1 << 6)
#define DP83848_10_HDX (1 << 5)
#define DP83848_AN_IEEE_802_3 0x0001
/*--Bit definitions: DP83848_ANER */
#define DP83848_PDF (1 << 4)
#define DP83848_LP_NP_ABLE (1 << 3)
#define DP83848_NP_ABLE (1 << 2)
#define DP83848_PAGE_RX (1 << 1)
#define DP83848_LP_AN_ABLE (1 << 0)
/*--Bit definitions: DP83848_PHY_STAT */
#define DP83848_RX_ERR_LATCH (1 << 13)
#define DP83848_POLARITY_STAT (1 << 12)
#define DP83848_FALSE_CAR_SENSE (1 << 11)
#define DP83848_SIG_DETECT (1 << 10)
#define DP83848_DESCRAM_LOCK (1 << 9)
#define DP83848_PAGE_RCV (1 << 8)
#define DP83848_PHY_RMT_FAULT (1 << 6)
#define DP83848_JABBER (1 << 5)
#define DP83848_AUTONEG_COMPLETE (1 << 4)
#define DP83848_LOOPBACK_STAT (1 << 3)
#define DP83848_DUPLEX (1 << 2)
#define DP83848_SPEED (1 << 1)
#define DP83848_LINK (1 << 0)
|
1001-study-uboot
|
include/dp83848.h
|
C
|
gpl3
| 3,187
|
/*
* Copyright 2003 Motorola,Inc.
* Xianghua Xiao(x.xiao@motorola.com)
*/
#ifndef __E500_H__
#define __E500_H__
#ifndef __ASSEMBLY__
typedef struct
{
unsigned long freqProcessor[CONFIG_MAX_CPUS];
unsigned long freqSystemBus;
unsigned long freqDDRBus;
unsigned long freqLocalBus;
unsigned long freqQE;
#ifdef CONFIG_SYS_DPAA_FMAN
unsigned long freqFMan[CONFIG_SYS_NUM_FMAN];
#endif
#ifdef CONFIG_SYS_DPAA_PME
unsigned long freqPME;
#endif
} MPC85xx_SYS_INFO;
#endif /* _ASMLANGUAGE */
#define RESET_VECTOR 0xfffffffc
#endif /* __E500_H__ */
|
1001-study-uboot
|
include/e500.h
|
C
|
gpl3
| 564
|
/*
* (C) Copyright 2008
* Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
*This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _IO_MUX_H
#define _IO_MUX_H
#include <stdio_dev.h>
/*
* Stuff required to support console multiplexing.
*/
/*
* Pointers to devices used for each file type. Defined in console.c
* but storage is allocated in iomux.c.
*/
extern struct stdio_dev **console_devices[MAX_FILES];
/*
* The count of devices assigned to each FILE. Defined in console.c
* and populated in iomux.c.
*/
extern int cd_count[MAX_FILES];
int iomux_doenv(const int, const char *);
void iomux_printdevs(const int);
struct stdio_dev *search_device(int, const char *);
#endif /* _IO_MUX_H */
|
1001-study-uboot
|
include/iomux.h
|
C
|
gpl3
| 1,470
|
/*
* (C) Copyright 2000
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _VIDEO_FONT_
#define _VIDEO_FONT_
#define VIDEO_FONT_CHARS 256
#define VIDEO_FONT_WIDTH 8
#define VIDEO_FONT_HEIGHT 16
#define VIDEO_FONT_SIZE (VIDEO_FONT_CHARS * VIDEO_FONT_HEIGHT)
#endif /* _VIDEO_FONT_ */
|
1001-study-uboot
|
include/video_font.h
|
C
|
gpl3
| 1,114
|
/*
* (C) Copyright 2005-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2010
* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _led_display_h_
#define _led_display_h_
/* Display Commands */
#define DISPLAY_CLEAR 0x1 /* Clear the display */
#define DISPLAY_HOME 0x2 /* Set cursor at home position */
void display_set(int cmd);
int display_putc(char c);
#endif
|
1001-study-uboot
|
include/led-display.h
|
C
|
gpl3
| 1,215
|
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __TIMESTAMP_H__
#define __TIMESTAMP_H__
#ifndef DO_DEPS_ONLY
#include "generated/timestamp_autogenerated.h"
#endif
#endif /* __TIMESTAMP_H__ */
|
1001-study-uboot
|
include/timestamp.h
|
C
|
gpl3
| 1,011
|
#ifndef _FDT_H
#define _FDT_H
#ifndef __ASSEMBLY__
struct fdt_header {
uint32_t magic; /* magic word FDT_MAGIC */
uint32_t totalsize; /* total size of DT block */
uint32_t off_dt_struct; /* offset to structure */
uint32_t off_dt_strings; /* offset to strings */
uint32_t off_mem_rsvmap; /* offset to memory reserve map */
uint32_t version; /* format version */
uint32_t last_comp_version; /* last compatible version */
/* version 2 fields below */
uint32_t boot_cpuid_phys; /* Which physical CPU id we're
booting on */
/* version 3 fields below */
uint32_t size_dt_strings; /* size of the strings block */
/* version 17 fields below */
uint32_t size_dt_struct; /* size of the structure block */
};
struct fdt_reserve_entry {
uint64_t address;
uint64_t size;
};
struct fdt_node_header {
uint32_t tag;
char name[0];
};
struct fdt_property {
uint32_t tag;
uint32_t len;
uint32_t nameoff;
char data[0];
};
#endif /* !__ASSEMBLY */
#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */
#define FDT_TAGSIZE sizeof(uint32_t)
#define FDT_BEGIN_NODE 0x1 /* Start node: full name */
#define FDT_END_NODE 0x2 /* End node */
#define FDT_PROP 0x3 /* Property: name off,
size, content */
#define FDT_NOP 0x4 /* nop */
#define FDT_END 0x9
#define FDT_V1_SIZE (7*sizeof(uint32_t))
#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(uint32_t))
#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(uint32_t))
#define FDT_V16_SIZE FDT_V3_SIZE
#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(uint32_t))
/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
#define FDT_RAMDISK_OVERHEAD 0x80
#endif /* _FDT_H */
|
1001-study-uboot
|
include/fdt.h
|
C
|
gpl3
| 1,650
|
/***********************************************************************
*
* Copyright (C) 2004 by FS Forth-Systeme GmbH.
* All rights reserved.
*
* $Id: ns9750_sys.h,v 1.1 2004/02/16 10:37:20 mpietrek Exp $
* @Author: Markus Pietrek
* @Descr: Definitions for SYS Control Module
* @References: [1] NS9750 Hardware Reference Manual/December 2003 Chap. 4
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
***********************************************************************/
#ifndef FS_NS9750_SYS_H
#define FS_NS9750_SYS_H
#define NS9750_SYS_MODULE_BASE (0xA0900000)
#define get_sys_reg_addr(c) \
((volatile unsigned int *)(NS9750_SYS_MODULE_BASE+(unsigned int) (c)))
/* the register addresses */
#define NS9750_SYS_AHB_GEN (0x0000)
#define NS9750_SYS_BRC_BASE (0x0004)
#define NS9750_SYS_AHB_TIMEOUT (0x0014)
#define NS9750_SYS_AHB_ERROR1 (0x0018)
#define NS9750_SYS_AHB_ERROR2 (0x001C)
#define NS9750_SYS_AHB_MON (0x0020)
#define NS9750_SYS_TIMER_COUNT_BASE (0x0044)
#define NS9750_SYS_TIMER_READ_BASE (0x0084)
#define NS9750_SYS_INT_VEC_ADR_BASE (0x00C4)
#define NS9750_SYS_INT_CFG_BASE (0x0144)
#define NS9750_SYS_ISRADDR (0x0164)
#define NS9750_SYS_INT_STAT_ACTIVE (0x0168)
#define NS9750_SYS_INT_STAT_RAW (0x016C)
#define NS9750_SYS_TIMER_INT_STAT (0x0170)
#define NS9750_SYS_SW_WDOG_CFG (0x0174)
#define NS9750_SYS_SW_WDOG_TIMER (0x0178)
#define NS9750_SYS_CLOCK (0x017C)
#define NS9750_SYS_RESET (0x0180)
#define NS9750_SYS_MISC (0x0184)
#define NS9750_SYS_PLL (0x0188)
#define NS9750_SYS_ACT_INT_STAT (0x018C)
#define NS9750_SYS_TIMER_CTRL_BASE (0x0190)
#define NS9750_SYS_CS_DYN_BASE_BASE (0x01D0)
#define NS9750_SYS_CS_DYN_MASK_BASE (0x01D4)
#define NS9750_SYS_CS_STATIC_BASE_BASE (0x01F0)
#define NS9750_SYS_CS_STATIC_MASK_BASE (0x01F4)
#define NS9750_SYS_GEN_ID (0x0210)
#define NS9750_SYS_EXT_INT_CTRL_BASE (0x0214)
/* the vectored register addresses */
#define NS9750_SYS_TIMER_COUNT(c) (NS9750_SYS_TIMER_COUNT_BASE + (c))
#define NS9750_SYS_TIMER_READ(c) (NS9750_SYS_TIMER_READ_BASE + (c))
#define NS9750_SYS_INT_VEC_ADR(c) (NS9750_SYS_INT_VEC_ADR_BASE + (c))
#define NS9750_SYS_TIMER_CTRL(c) (NS9750_SYS_TIMER_CTRL_BASE + (c))
/* CS_DYN start with 4 */
#define NS9750_SYS_CS_DYN_BASE(c) (NS9750_SYS_CS_DYN_BASE_BASE + ((c)-4)*2)
#define NS9750_SYS_CS_DYN_MASK(c) (NS9750_SYS_CS_DYN_MASK_BASE + ((c)-4)*2)
/* CS_STATIC start with 0 */
#define NS9750_SYS_CS_STATIC_BASE(c) (NS9750_SYS_CS_STATIC_BASE_BASE + (c)*2)
#define NS9750_SYS_CS_STATIC_MASK(c) (NS9750_SYS_CS_STATIC_MASK_BASE + (c)*2)
#define NS9750_SYS_EXT_INT_CTRL(c) (NS9750_SYS_EXT_INT_CTRL + (c))
/* register bit fields */
#define NS9750_SYS_AHB_GEN_EXMAM (0x00000001)
/* need to be n*8bit to BRC channel */
#define NS9750_SYS_BRC_CEB (0x00000080)
#define NS9750_SYS_BRC_BRF_MA (0x00000030)
#define NS9750_SYS_BRC_BRF_100 (0x00000000)
#define NS9750_SYS_BRC_BRF_75 (0x00000010)
#define NS9750_SYS_BRC_BRF_50 (0x00000020)
#define NS9750_SYS_BRC_BRF_25 (0x00000030)
#define NS9750_SYS_AHB_TIMEOUT_BAT_MA (0xFFFF0000)
#define NS9750_SYS_AHB_TIMEOUT_BMT_MA (0x0000FFFF)
#define NS9750_SYS_AHB_ERROR2_ABL (0x00040000)
#define NS9750_SYS_AHB_ERROR2_AER (0x00020000)
#define NS9750_SYS_AHB_ERROR2_ABM (0x00010000)
#define NS9750_SYS_AHB_ERROR2_ABA (0x00008000)
#define NS9750_SYS_AHB_ERROR2_HWRT (0x00004000)
#define NS9750_SYS_AHB_ERROR2_HMID_MA (0x00003C00)
#define NS9750_SYS_AHB_ERROR2_HTPC_MA (0x000003C0)
#define NS9750_SYS_AHB_ERROR2_HSZ_MA (0x00000038)
#define NS9750_SYS_AHB_ERROR2_RR_MA (0x00000007)
#define NS9750_SYS_AHB_MON_EIC (0x00800000)
#define NS9750_SYS_AHB_MON_MBII (0x00400000)
#define NS9750_SYS_AHB_MON_MBL_MA (0x003FFFC0)
#define NS9750_SYS_AHB_MON_MBLDC (0x00000020)
#define NS9750_SYS_AHB_MON_SERDC (0x00000010)
#define NS9750_SYS_AHB_MON_BMTC_MA (0x0000000C)
#define NS9750_SYS_AHB_MON_BMTC_RECORD (0x00000000)
#define NS9750_SYS_AHB_MON_BMTC_GEN_IRQ (0x00000004)
#define NS9750_SYS_AHB_MON_BMTC_GEN_RES (0x00000008)
#define NS9750_SYS_AHB_MON_BATC_MA (0x00000003)
#define NS9750_SYS_AHB_MON_BATC_RECORD (0x00000000)
#define NS9750_SYS_AHB_MON_BATC_GEN_IRQ (0x00000001)
#define NS9750_SYS_AHB_MON_BATC_GEN_RES (0x00000002)
/* need to be n*8bit to Int Level */
#define NS9750_SYS_INT_CFG_IE (0x00000080)
#define NS9750_SYS_INT_CFG_IT (0x00000020)
#define NS9750_SYS_INT_CFG_IAD_MA (0x0000001F)
#define NS9750_SYS_TIMER_INT_STAT_MA (0x0000FFFF)
#define NS9750_SYS_SW_WDOG_CFG_SWWE (0x00000080)
#define NS9750_SYS_SW_WDOG_CFG_SWWI (0x00000020)
#define NS9750_SYS_SW_WDOG_CFG_SWWIC (0x00000010)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_MA (0x00000007)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_2 (0x00000000)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_4 (0x00000001)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_8 (0x00000002)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_16 (0x00000003)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_32 (0x00000004)
#define NS9750_SYS_SW_WDOG_CFG_SWTCS_64 (0x00000005)
#define NS9750_SYS_CLOCK_LPCS_MA (0x00000380)
#define NS9750_SYS_CLOCK_LPCS_1 (0x00000000)
#define NS9750_SYS_CLOCK_LPCS_2 (0x00000080)
#define NS9750_SYS_CLOCK_LPCS_4 (0x00000100)
#define NS9750_SYS_CLOCK_LPCS_8 (0x00000180)
#define NS9750_SYS_CLOCK_LPCS_EXT (0x00000200)
#define NS9750_SYS_CLOCK_BBC (0x00000040)
#define NS9750_SYS_CLOCK_LCC (0x00000020)
#define NS9750_SYS_CLOCK_MCC (0x00000010)
#define NS9750_SYS_CLOCK_PARBC (0x00000008)
#define NS9750_SYS_CLOCK_PC (0x00000004)
#define NS9750_SYS_CLOCK_MACC (0x00000001)
#define NS9750_SYS_RESET_SR (0x80000000)
#define NS9750_SYS_RESET_I2CW (0x00100000)
#define NS9750_SYS_RESET_CSE (0x00080000)
#define NS9750_SYS_RESET_SMWE (0x00040000)
#define NS9750_SYS_RESET_EWE (0x00020000)
#define NS9750_SYS_RESET_PI3WE (0x00010000)
#define NS9750_SYS_RESET_BBT (0x00000040)
#define NS9750_SYS_RESET_LCDC (0x00000020)
#define NS9750_SYS_RESET_MEMC (0x00000010)
#define NS9750_SYS_RESET_PCIAR (0x00000008)
#define NS9750_SYS_RESET_PCIM (0x00000004)
#define NS9750_SYS_RESET_MACM (0x00000001)
#define NS9750_SYS_MISC_REV_MA (0xFF000000)
#define NS9750_SYS_MISC_PCIA (0x00002000)
#define NS9750_SYS_MISC_VDIS (0x00001000)
#define NS9750_SYS_MISC_BMM (0x00000800)
#define NS9750_SYS_MISC_CS1DB (0x00000400)
#define NS9750_SYS_MISC_CS1DW_MA (0x00000300)
#define NS9750_SYS_MISC_MCCM (0x00000080)
#define NS9750_SYS_MISC_PMSS (0x00000040)
#define NS9750_SYS_MISC_CS1P (0x00000020)
#define NS9750_SYS_MISC_ENDM (0x00000008)
#define NS9750_SYS_MISC_MBAR (0x00000004)
#define NS9750_SYS_MISC_IRAM0 (0x00000001)
#define NS9750_SYS_PLL_PLLBS (0x02000000)
#define NS9750_SYS_PLL_PLLFS_MA (0x01800000)
#define NS9750_SYS_PLL_PLLIS_MA (0x00600000)
#define NS9750_SYS_PLL_PLLND_MA (0x001F0000)
#define NS9750_SYS_PLL_PLLSW (0x00008000)
#define NS9750_SYS_PLL_PLLBSSW (0x00000200)
#define NS9750_SYS_PLL_FSEL_MA (0x00000180)
#define NS9750_SYS_PLL_CPCC_MA (0x00000060)
#define NS9750_SYS_PLL_NDSW_MA (0x0000001F)
#define NS9750_SYS_ACT_INT_STAT_MA (0x0000FFFF)
#define NS9750_SYS_TIMER_CTRL_TEN (0x00008000)
#define NS9750_SYS_TIMER_CTRL_INTC (0x00000200)
#define NS9750_SYS_TIMER_CTRL_TLCS_MA (0x000001C0)
#define NS9750_SYS_TIMER_CTRL_TLCS_1 (0x00000000)
#define NS9750_SYS_TIMER_CTRL_TLCS_2 (0x00000040)
#define NS9750_SYS_TIMER_CTRL_TLCS_4 (0x00000080)
#define NS9750_SYS_TIMER_CTRL_TLCS_8 (0x000000C0)
#define NS9750_SYS_TIMER_CTRL_TLCS_16 (0x00000100)
#define NS9750_SYS_TIMER_CTRL_TLCS_32 (0x00000140)
#define NS9750_SYS_TIMER_CTRL_TLCS_64 (0x00000180)
#define NS9750_SYS_TIMER_CTRL_TLCS_EXT (0x000001C0)
#define NS9750_SYS_TIMER_CTRL_TM_MA (0x00000030)
#define NS9750_SYS_TIMER_CTRL_TM_INT (0x00000000)
#define NS9750_SYS_TIMER_CTRL_TM_LOW (0x00000010)
#define NS9750_SYS_TIMER_CTRL_TM_HIGH (0x00000020)
#define NS9750_SYS_TIMER_CTRL_INTS (0x00000008)
#define NS9750_SYS_TIMER_CTRL_UDS (0x00000004)
#define NS9750_SYS_TIMER_CTRL_TSZ (0x00000002)
#define NS9750_SYS_TIMER_CTRL_REN (0x00000001)
#define NS9750_SYS_EXT_INT_CTRL_STS (0x00000008)
#define NS9750_SYS_EXT_INT_CTRL_CLR (0x00000004)
#define NS9750_SYS_EXT_INT_CTRL_PLTY (0x00000002)
#define NS9750_SYS_EXT_INT_CTRL_LVEDG (0x00000001)
#endif /* FS_NS9750_SYS_H */
|
1001-study-uboot
|
include/ns9750_sys.h
|
C
|
gpl3
| 8,795
|
/* $Id$ */
#ifndef TABLES_H
#define TABLES_H
/* This is only included by common/bedbug.c, and depends on the following
* files to already be included
* common.h
* bedbug/bedbug.h
* bedbug/ppc.h
* bedbug/regs.h
*/
struct operand operands[] = {
/*Field Name Bits Shift Hint Position */
/*----- ------ ----- ----- ---- ------------ */
{ O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */
{ O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */
{ O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */
{ O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */
{ O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */
{ O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */
{ O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */
{ O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */
{ O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */
{ O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */
{ O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */
{ O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */
{ O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */
{ O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */
{ O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */
{ O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */
{ O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */
{ O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */
{ O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */
{ O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */
{ O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */
{ O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */
{ O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */
{ O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */
{ O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */
{ O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */
{ O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */
{ O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */
{ O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */
{ O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */
{ O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */
{ O_L, "O_L", 1, 21, 0 }, /* 10 */
{ O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */
{ O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */
{ O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */
};
const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]);
/* A note about the fields array in the opcodes structure:
The operands are listed in the order they appear in the output.
This table is arranged in numeric order of the opcode. Note that some
opcodes have defined bits in odd places so not all forms of a command
will be in the same place. This is done so that a binary search can be
done to find the opcodes. Note that table D.2 in the MPC860 User's
Manual "Instructions Sorted by Opcode" does not account for these
bit locations */
struct opcode opcodes[] = {
{ D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0},
0, "twi", 0 },
{ D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "mulli", 0 },
{ D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "subfic", 0 },
{ D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0},
0, "cmpli", 0 },
{ D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0},
0, "cmpi", 0 },
{ D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "addic", 0 },
{ D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "addic.", 0 },
{ D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "addi", H_RA0_IS_0 },
{ D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0},
0, "addis", H_RA0_IS_0|H_IMM_HIGH },
{ B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
handle_bc, "bc", H_RELATIVE },
{ B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
0, "bcl", H_RELATIVE },
{ B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
0, "bca", 0 },
{ B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0},
0, "bcla", 0 },
{ SC_OPCODE(17), SC_MASK, {0},
0, "sc", 0 },
{ I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0},
0, "b", H_RELATIVE },
{ I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0},
0, "bl", H_RELATIVE },
{ I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0},
0, "ba", 0 },
{ I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0},
0, "bla", 0 },
{ XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS},
0, "mcrf", 0 },
{ XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
0, "bclr", 0 },
{ XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
0, "bclrl", 0 },
{ XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crnor", 0 },
{ XL_OPCODE(19,50,0), XL_MASK, {0},
0, "rfi", 0 },
{ XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crandc", 0 },
{ XL_OPCODE(19,150,0), XL_MASK, {0},
0, "isync", 0 },
{ XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crxor", 0 },
{ XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crnand", 0 },
{ XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crand", 0 },
{ XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "creqv", 0 },
{ XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "crorc", 0 },
{ XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0},
0, "cror", 0 },
{ XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0},
0, "bcctr", 0 },
{ XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0},
0, "bcctrl", 0 },
{ M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
0, "rlwimi", 0 },
{ M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
0, "rlwimi.", 0 },
{ M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
0, "rlwinm", 0 },
{ M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0},
0, "rlwinm.", 0 },
{ M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
0, "rlwnm", 0 },
{ M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0},
0, "rlwnm.", 0 },
{ D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "ori", 0 },
{ D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "oris", H_IMM_HIGH },
{ D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "xori", 0 },
{ D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "xoris", H_IMM_HIGH },
{ D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "andi.", 0 },
{ D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0},
0, "andis.", H_IMM_HIGH },
{ X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
0, "cmp", 0 },
{ X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0},
0, "tw", 0 },
{ XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfc", 0 },
{ XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfc.", 0 },
{ XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addc", 0 },
{ XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addc.", 0 },
{ XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
0, "mulhwu", 0 },
{ XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
0, "mulhwu.", 0 },
{ X_OPCODE(31,19,0), X_MASK, {O_rD, 0},
0, "mfcr", 0 },
{ X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lwarx", H_RA0_IS_0 },
{ X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lwzx", H_RA0_IS_0 },
{ X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "slw", 0 },
{ X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "slw.", 0 },
{ X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 },
0, "cntlzw", 0 },
{ X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "cntlzw.", 0 },
{ X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "and", 0 },
{ X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "and.", 0 },
{ X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0},
0, "cmpl", 0 },
{ XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subf", 0 },
{ XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subf.", 0 },
{ X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbst", H_RA0_IS_0 },
{ X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lwzux", 0 },
{ X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "andc", 0 },
{ X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "andc.", 0 },
{ XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
0, "mulhw", 0 },
{ XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0},
0, "mulhw.", 0 },
{ X_OPCODE(31,83,0), X_MASK, {O_rD, 0},
0, "mfmsr", 0 },
{ X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbf", H_RA0_IS_0 },
{ X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lbzx", H_RA0_IS_0 },
{ XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "neg", 0 },
{ XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "neg.", 0 },
{ X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lbzux", 0 },
{ X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "nor", 0 },
{ X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "nor.", 0 },
{ XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfe", 0 },
{ XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfe.", 0 },
{ XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "adde", 0 },
{ XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "adde.", 0 },
{ XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0},
0, "mtcrf", 0 },
{ X_OPCODE(31,146,0), X_MASK, {O_rS, 0},
0, "mtmsr", 0 },
{ X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stwcx.", 0 },
{ X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stwx", 0 },
{ X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stwux", 0 },
{ XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfze", 0 },
{ XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfze.", 0 },
{ XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addze", 0 },
{ XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addze.", 0 },
{ X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0},
0, "mtsr", 0 },
{ X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stbx", H_RA0_IS_0 },
{ XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfme", 0 },
{ XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfme.", 0 },
{ XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addme", 0 },
{ XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addme.", 0 },
{ XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "mullw", 0 },
{ XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "mullw.", 0 },
{ X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0},
0, "mtsrin", 0 },
{ X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbtst", H_RA0_IS_0 },
{ X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stbux", 0 },
{ XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "add", 0 },
{ XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "add.", 0 },
{ X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbt", H_RA0_IS_0 },
{ X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhzx", H_RA0_IS_0 },
{ X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "eqv", 0 },
{ X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "eqv.", 0 },
{ X_OPCODE(31,306,0), X_MASK, {O_rB, 0},
0, "tlbie", 0 },
{ X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "eciwx", H_RA0_IS_0 },
{ X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhzux", 0 },
{ X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "xor", 0 },
{ X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "xor.", 0 },
{ XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0},
0, "mfspr", 0 },
{ X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhax", H_RA0_IS_0 },
{ X_OPCODE(31,370,0), X_MASK, {0},
0, "tlbia", 0 },
{ XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0},
0, "mftb", 0 },
{ X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhaux", 0 },
{ X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "sthx", H_RA0_IS_0 },
{ X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "orc", 0 },
{ X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "orc.", 0 },
{ X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "ecowx", H_RA0_IS_0 },
{ X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "sthux", 0 },
{ X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "or", 0 },
{ X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "or.", 0 },
{ XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwu", 0 },
{ XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwu.", 0 },
{ XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0},
0, "mtspr", 0 },
{ X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbi", H_RA0_IS_0 },
{ X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "nand", 0 },
{ X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0},
0, "nand.", 0 },
{ XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divw", 0 },
{ XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divw.", 0 },
{ X_OPCODE(31,512,0), X_MASK, {O_crfD, 0},
0, "mcrxr", 0 },
{ XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfco", 0 },
{ XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfco.", 0 },
{ XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addco", 0 },
{ XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addco.", 0 },
{ X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lswx", H_RA0_IS_0 },
{ X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lwbrx", H_RA0_IS_0 },
{ X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "srw", 0 },
{ X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "srw.", 0 },
{ XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfo", 0 },
{ XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfo.", 0 },
{ X_OPCODE(31,566,0), X_MASK, {0},
0, "tlbsync", 0 },
{ X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0},
0, "mfsr", 0 },
{ X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0},
0, "lswi", H_RA0_IS_0 },
{ X_OPCODE(31,598,0), X_MASK, {0},
0, "sync", 0 },
{ XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "nego", 0 },
{ XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "nego.", 0 },
{ XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfeo", 0 },
{ XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "subfeo.", 0 },
{ XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addeo", 0 },
{ XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addeo.", 0 },
{ X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0},
0, "mfsrin", 0 },
{ X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stswx", H_RA0_IS_0 },
{ X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "stwbrx", H_RA0_IS_0 },
{ XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfzeo", 0 },
{ XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfzeo.", 0 },
{ XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addzeo", 0 },
{ XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addzeo.", 0 },
{ X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0},
0, "stswi", H_RA0_IS_0 },
{ XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfmeo", 0 },
{ XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "subfmeo.", 0 },
{ XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addmeo", 0 },
{ XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0},
0, "addmeo.", 0 },
{ XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "mullwo", 0 },
{ XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "mullwo.", 0 },
{ XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addo", 0 },
{ XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "addo.", 0 },
{ X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0},
0, "lhbrx", H_RA0_IS_0 },
{ X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "sraw", 0 },
{ X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0},
0, "sraw.", 0 },
{ X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
0, "srawi", 0 },
{ X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0},
0, "srawi.", 0 },
{ X_OPCODE(31,854,0), X_MASK, {0},
0, "eieio", 0 },
{ X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0},
0, "sthbrx", H_RA0_IS_0 },
{ X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "extsh", 0 },
{ X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "extsh.", 0 },
{ X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "extsb", 0 },
{ X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0},
0, "extsb.", 0 },
{ XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwuo", 0 },
{ XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwuo.", 0 },
{ X_OPCODE(31,978,0), X_MASK, {O_rB, 0},
0, "tlbld", 0 },
{ X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0},
0, "icbi", H_RA0_IS_0 },
{ XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwo", 0 },
{ XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0},
0, "divwo.", 0 },
{ X_OPCODE(31,1010,0), X_MASK, {O_rB, 0},
0, "tlbli", 0 },
{ X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0},
0, "dcbz", H_RA0_IS_0 },
{ D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lwz", H_RA0_IS_0 },
{ D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lwzu", 0 },
{ D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lbz", H_RA0_IS_0 },
{ D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lbzu", 0 },
{ D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stw", H_RA0_IS_0 },
{ D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stwu", 0 },
{ D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stb", H_RA0_IS_0 },
{ D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stbu", 0 },
{ D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lhz", H_RA0_IS_0 },
{ D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lhzu", 0 },
{ D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lha", H_RA0_IS_0 },
{ D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lhau", 0 },
{ D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0},
0, "sth", H_RA0_IS_0 },
{ D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0},
0, "sthu", 0 },
{ D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0},
0, "lmw", H_RA0_IS_0 },
{ D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0},
0, "stmw", H_RA0_IS_0 },
};
const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]);
struct spr_info spr_map[] = {
{ SPR_XER, "XER" },
{ SPR_LR, "LR" },
{ SPR_CTR, "CTR" },
{ SPR_DSISR, "DSISR" },
{ SPR_DAR, "DAR" },
{ SPR_DEC, "DEC" },
{ SPR_SRR0, "SRR0" },
{ SPR_SRR1, "SRR1" },
{ SPR_EIE, "EIE" },
{ SPR_EID, "EID" },
{ SPR_CMPA, "CMPA" },
{ SPR_CMPB, "CMPB" },
{ SPR_CMPC, "CMPC" },
{ SPR_CMPD, "CMPD" },
{ SPR_ICR, "ICR" },
{ SPR_DER, "DER" },
{ SPR_COUNTA, "COUNTA" },
{ SPR_COUNTB, "COUNTB" },
{ SPR_CMPE, "CMPE" },
{ SPR_CMPF, "CMPF" },
{ SPR_CMPG, "CMPG" },
{ SPR_CMPH, "CMPH" },
{ SPR_LCTRL1, "LCTRL1" },
{ SPR_LCTRL2, "LCTRL2" },
{ SPR_ICTRL, "ICTRL" },
{ SPR_BAR, "BAR" },
{ SPR_USPRG0, "USPRG0" },
{ SPR_SPRG4_RO, "SPRG4_RO" },
{ SPR_SPRG5_RO, "SPRG5_RO" },
{ SPR_SPRG6_RO, "SPRG6_RO" },
{ SPR_SPRG7_RO, "SPRG7_RO" },
{ SPR_SPRG0, "SPRG0" },
{ SPR_SPRG1, "SPRG1" },
{ SPR_SPRG2, "SPRG2" },
{ SPR_SPRG3, "SPRG3" },
{ SPR_SPRG4, "SPRG4" },
{ SPR_SPRG5, "SPRG5" },
{ SPR_SPRG6, "SPRG6" },
{ SPR_SPRG7, "SPRG7" },
{ SPR_EAR, "EAR" },
{ SPR_TBL, "TBL" },
{ SPR_TBU, "TBU" },
{ SPR_IC_CST, "IC_CST" },
{ SPR_IC_ADR, "IC_ADR" },
{ SPR_IC_DAT, "IC_DAT" },
{ SPR_DC_CST, "DC_CST" },
{ SPR_DC_ADR, "DC_ADR" },
{ SPR_DC_DAT, "DC_DAT" },
{ SPR_DPDR, "DPDR" },
{ SPR_IMMR, "IMMR" },
{ SPR_MI_CTR, "MI_CTR" },
{ SPR_MI_AP, "MI_AP" },
{ SPR_MI_EPN, "MI_EPN" },
{ SPR_MI_TWC, "MI_TWC" },
{ SPR_MI_RPN, "MI_RPN" },
{ SPR_MD_CTR, "MD_CTR" },
{ SPR_M_CASID, "M_CASID" },
{ SPR_MD_AP, "MD_AP" },
{ SPR_MD_EPN, "MD_EPN" },
{ SPR_M_TWB, "M_TWB" },
{ SPR_MD_TWC, "MD_TWC" },
{ SPR_MD_RPN, "MD_RPN" },
{ SPR_M_TW, "M_TW" },
{ SPR_MI_DBCAM, "MI_DBCAM" },
{ SPR_MI_DBRAM0, "MI_DBRAM0" },
{ SPR_MI_DBRAM1, "MI_DBRAM1" },
{ SPR_MD_DBCAM, "MD_DBCAM" },
{ SPR_MD_DBRAM0, "MD_DBRAM0" },
{ SPR_MD_DBRAM1, "MD_DBRAM1" },
{ SPR_ZPR, "ZPR" },
{ SPR_PID, "PID" },
{ SPR_CCR0, "CCR0" },
{ SPR_IAC3, "IAC3" },
{ SPR_IAC4, "IAC4" },
{ SPR_DVC1, "DVC1" },
{ SPR_DVC2, "DVC2" },
{ SPR_SGR, "SGR" },
{ SPR_DCWR, "DCWR" },
{ SPR_SLER, "SLER" },
{ SPR_SU0R, "SU0R" },
{ SPR_DBCR1, "DBCR1" },
{ SPR_ICDBDR, "ICDBDR" },
{ SPR_ESR, "ESR" },
{ SPR_DEAR, "DEAR" },
{ SPR_EVPR, "EVPR" },
{ SPR_TSR, "TSR" },
{ SPR_TCR, "TCR" },
{ SPR_PIT, "PIT" },
{ SPR_SRR2, "SRR2" },
{ SPR_SRR3, "SRR3" },
{ SPR_DBSR, "DBSR" },
{ SPR_DBCR0, "DBCR0" },
{ SPR_IAC1, "IAC1" },
{ SPR_IAC2, "IAC2" },
{ SPR_DAC1, "DAC1" },
{ SPR_DAC2, "DAC2" },
{ SPR_DCCR, "DCCR" },
{ SPR_ICCR, "ICCR" },
};
const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]);
#endif
/*
* Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
* All rights reserved.
*
* Redistribution and use in source and binary forms are freely
* permitted provided that the above copyright notice and this
* paragraph and the following disclaimer are duplicated in all
* such forms.
*
* This software is provided "AS IS" and without any express or
* implied warranties, including, without limitation, the implied
* warranties of merchantability and fitness for a particular
* purpose.
*/
|
1001-study-uboot
|
include/bedbug/tables.h
|
C
|
gpl3
| 25,799
|
/* $Id$ */
#ifndef _BEDBUG_H
#define _BEDBUG_H
#ifndef NULL
#define NULL 0
#endif
#define _USE_PROTOTYPES
#ifndef isblank
#define isblank(c) isspace((int)(c))
#endif
#ifndef __P
#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus))
#define __P(protos) protos /* full-blown ANSI C */
#else
#define __P(protos) () /* traditional C preprocessor */
#endif
#endif
#endif /* _BEDBUG_H */
/*
* Copyright (c) 2001 William L. Pitts
* All rights reserved.
*
* Redistribution and use in source and binary forms are freely
* permitted provided that the above copyright notice and this
* paragraph and the following disclaimer are duplicated in all
* such forms.
*
* This software is provided "AS IS" and without any express or
* implied warranties, including, without limitation, the implied
* warranties of merchantability and fitness for a particular
* purpose.
*/
|
1001-study-uboot
|
include/bedbug/bedbug.h
|
C
|
gpl3
| 900
|
#ifndef _TYPE_BEDBUG_H
#define _TYPE_BEDBUG_H
/* Supporting routines */
int bedbug_puts (const char *);
void bedbug_init (void);
void bedbug860_init (void);
void do_bedbug_breakpoint (struct pt_regs *);
void bedbug_main_loop (unsigned long, struct pt_regs *);
typedef struct {
int hw_debug_enabled;
int stopped;
int current_bp;
struct pt_regs *regs;
void (*do_break) (cmd_tbl_t *, int, int, char * const []);
void (*break_isr) (struct pt_regs *);
int (*find_empty) (void);
int (*set) (int, unsigned long);
int (*clear) (int);
} CPU_DEBUG_CTX;
#endif /* _TYPE_BEDBUG_H */
|
1001-study-uboot
|
include/bedbug/type.h
|
C
|
gpl3
| 587
|
/* $Id$ */
#ifndef _PPC_H
#define _PPC_H
/*======================================================================
*
* OPERANDS
*
*======================================================================*/
enum OP_FIELD {
O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
O_cr2 };
struct operand {
enum OP_FIELD field; /* The operand identifier from the
enum above */
char * name; /* Symbolic name of this operand */
unsigned int bits; /* The number of bits used by this
operand */
unsigned int shift; /* How far to the right the operand
should be shifted so that it is
aligned at the beginning of the
word */
unsigned int hint; /* A bitwise-inclusive-OR of the
values shown below. These are used
tell the disassembler how to print
this operand */
};
/* Values for operand hint */
#define OH_SILENT 0x01 /* dont print this operand */
#define OH_ADDR 0x02 /* this operand is an address */
#define OH_REG 0x04 /* this operand is a register */
#define OH_SPR 0x08 /* this operand is an SPR */
#define OH_TBR 0x10 /* this operand is a TBR */
#define OH_OFFSET 0x20 /* this operand is an offset */
#define OH_LITERAL 0x40 /* a literal string */
/*======================================================================
*
* OPCODES
*
*======================================================================*/
/* From the MPCxxx instruction set documentation, all instructions are
* 32 bits long and word aligned. Bits 0-5 always specify the primary
* opcode. Many instructions also have an extended opcode.
*/
#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
* instruction forms
*/
/*-------------------------------------------------
* I-Form Instructions:
* bX
*-------------------------------------------------
* OPCD | LI |AA|LK
*-------------------------------------------------*/
#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
#define I_MASK I_OPCODE(0x3f,0x1,0x1)
/*-------------------------------------------------
* B-Form Instructions:
* bcX
*-------------------------------------------------
* OPCD | BO | BI | BD |AA|LK
*-------------------------------------------------*/
#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
#define B_MASK B_OPCODE(0x3f,0x1,0x1)
/*-------------------------------------------------
* SC-Form Instructions:
* sc
*-------------------------------------------------
* OPCD | 00000 | 00000 | 00000000000000 |1|0
*-------------------------------------------------*/
#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
#define SC_MASK SC_OPCODE(0x3f)
/*-------------------------------------------------
* D-Form Instructions:
* addi addic addic. addis andi. andis. cmpi cmpli
* lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
* ori oris stb stbu sth sthu stmw stw stwu subfic
* twi xori xoris
*-------------------------------------------------
* OPCD | D | A | d
* OPCD | D | A | SIMM
* OPCD | S | A | d
* OPCD | S | A | UIMM
* OPCD |crfD|0|L| A | SIMM
* OPCD |crfD|0|L| A | UIMM
* OPCD | TO | A | SIMM
*-------------------------------------------------*/
#define D_OPCODE(i) MAKE_OPCODE(i)
#define D_MASK MAKE_OPCODE(0x3f)
/*-------------------------------------------------
* DS-Form Instructions:
* (none supported by MPC860)
*-------------------------------------------------
* OPCD | D | A | ds |XO
* OPCD | S | A | ds |XO
*-------------------------------------------------*/
#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
#define DS_MASK DS_OPCODE(0x3f,0x1)
/*---------------------------------------------------
* X-Form Instructions:
* andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
* dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
* icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
* lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
* mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
* orX orcX slwX srawX srawiX srwX stbux stbx
* sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
* stwx sync tlbie tlbld tlbli tlbsync tw xorX
*---------------------------------------------------
* OPCD | D | A | B | XO |0
* OPCD | D | A | NB | XO |0
* OPCD | D | 00000 | B | XO |0
* OPCD | D | 00000 | 00000 | XO |0
* OPCD | D |0| SR | 00000 | XO |0
* OPCD | S | A | B | XO |Rc
* OPCD | S | A | B | XO |1
* OPCD | S | A | B | XO |0
* OPCD | S | A | NB | XO |0
* OPCD | S | A | 00000 | XO |Rc
* OPCD | S | 00000 | B | XO |0
* OPCD | S | 00000 | 00000 | XO |0
* OPCD | S |0| SR | 00000 | XO |0
* OPCD | S | A | SH | XO |Rc
* OPCD |crfD|0|L| A | SH | XO |0
* OPCD |crfD |00| A | B | XO |0
* OPCD |crfD |00|crfS |00| 00000 | XO |0
* OPCD |crfD |00| 00000 | 00000 | XO |0
* OPCD |crfD |00| 00000 | IMM |0| XO |Rc
* OPCD | TO | A | B | XO |0
* OPCD | D | 00000 | B | XO |Rc
* OPCD | D | 00000 | 00000 | XO |Rc
* OPCD | crbD | 00000 | 00000 | XO |Rc
* OPCD | 00000 | A | B | XO |0
* OPCD | 00000 | 00000 | B | XO |0
* OPCD | 00000 | 00000 | 00000 | XO |0
*---------------------------------------------------*/
#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
((rc) & 0x1))
#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
/*---------------------------------------------------
* XL-Form Instructions:
* bcctrX bclrX crand crandc creqv crnand crnor cror
* croc crxorisync mcrf rfi
*---------------------------------------------------
* OPCD | BO | BI | 00000 | XO |LK
* OPCD | crbD | crbA | crbB | XO |0
* OPCD |crfD |00|crfS |00| 00000 | XO |0
* OPCD | 00000 | 00000 | 00000 | XO |0
*---------------------------------------------------*/
#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
((lk) & 0x1))
#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
/*---------------------------------------------------
* XFX-Form Instructions:
* mfspr mftb mtcrf mtspr
*---------------------------------------------------
* OPCD | D | spr | XO |0
* OPCD | D |0| CRM |0| XO |0
* OPCD | S | spr | XO |0
* OPCD | D | tbr | XO |0
*---------------------------------------------------*/
#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
((rc) & 0x1))
#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
/*---------------------------------------------------
* XFL-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD |0| FM |0| B | XO |0
*---------------------------------------------------*/
#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
((rc) & 0x1))
#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
/*---------------------------------------------------
* XS-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD | S | A | sh | XO |sh|LK
*---------------------------------------------------*/
#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
((rc) & 0x1))
#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
/*---------------------------------------------------
* XO-Form Instructions:
* addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
* mulhwuX mullwX negX subfX subfcX subfeX subfmeX
* subfzeX
*---------------------------------------------------
* OPCD | D | A | B |OE| XO |Rc
* OPCD | D | A | B |0 | XO |Rc
* OPCD | D | A | 00000 |OE| XO |Rc
*---------------------------------------------------*/
#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
(((xo) & 0x1ff) << 1) | ((rc) & 0x1))
#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
/*---------------------------------------------------
* A-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD | D | A | B |00000| XO |Rc
* OPCD | D | A | B | C | XO |Rc
* OPCD | D | A | 00000 | C | XO |Rc
* OPCD | D | 00000 | B |00000| XO |Rc
*---------------------------------------------------*/
#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
((rc) & 0x1))
#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
/*---------------------------------------------------
* M-Form Instructions:
* rlwimiX rlwinmX rlwnmX
*---------------------------------------------------
* OPCD | S | A | SH | MB | ME |Rc
* OPCD | S | A | B | MB | ME |Rc
*---------------------------------------------------*/
#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
#define M_MASK M_OPCODE(0x3f,0x1)
/*---------------------------------------------------
* MD-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD | S | A | sh | mb | XO |sh|Rc
* OPCD | S | A | sh | me | XO |sh|Rc
*---------------------------------------------------*/
#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
((rc) & 0x1))
#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
/*---------------------------------------------------
* MDS-Form Instructions:
* (none supported by MPC860)
*---------------------------------------------------
* OPCD | S | A | B | mb | XO |Rc
* OPCD | S | A | B | me | XO |Rc
*---------------------------------------------------*/
#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
((rc) & 0x1))
#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
#ifndef FALSE
#define FALSE 0
#define TRUE (!FALSE)
#endif
#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
#define MAX_OPERANDS 8
struct ppc_ctx;
struct opcode {
unsigned long opcode; /* The complete opcode as produced by
one of the XXX_OPCODE macros above */
unsigned long mask; /* The mask to use on an instruction
before comparing with the opcode
field to see if it matches */
enum OP_FIELD fields[MAX_OPERANDS];
/* An array defining the operands for
this opcode. The values of the
array are the operand identifiers */
int (*hfunc)(struct ppc_ctx *);
/* Address of a function to handle the given
mnemonic */
char * name; /* The symbolic name of this opcode */
unsigned int hint; /* A bitwise-inclusive-OR of the
values shown below. These are used
tell the disassembler how to print
some operands for this opcode */
};
/* values for opcode hints */
#define H_RELATIVE 0x1 /* The address operand is relative */
#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */
#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */
struct ppc_ctx {
struct opcode * op;
unsigned long instr;
unsigned int flags;
int datalen;
char data[ 256 ];
char radix_fmt[ 8 ];
unsigned char * virtual;
};
/*======================================================================
*
* FUNCTIONS
*
*======================================================================*/
/* Values for flags as passed to various ppc routines */
#define F_RADOCTAL 0x1 /* output radix = unsigned octal */
#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */
#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */
#define F_RADHEX 0x8 /* output radix = unsigned hex */
#define F_SIMPLE 0x10 /* use simplified mnemonics */
#define F_SYMBOL 0x20 /* use symbol lookups for addresses */
#define F_INSTR 0x40 /* output the raw instruction */
#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory
rather than from the HMI */
#define F_LINENO 0x100 /* show line number info if available */
#define F_VALIDONLY 0x200 /* cache: valid entries only */
/* Values for assembler error codes */
#define E_ASM_BAD_OPCODE 1
#define E_ASM_NUM_OPERANDS 2
#define E_ASM_BAD_REGISTER 3
#define E_ASM_BAD_SPR 4
#define E_ASM_BAD_TBR 5
extern int disppc __P((unsigned char *,unsigned char *,int,
int (*)(const char *), unsigned long));
extern int print_source_line __P((char *,char *,int,
int (*pfunc)(const char *)));
extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
extern int handle_bc __P((struct ppc_ctx *));
extern unsigned long asmppc __P((unsigned long,char*,int*));
extern char *asm_error_str __P((int));
/*======================================================================
*
* GLOBAL VARIABLES
*
*======================================================================*/
extern struct operand operands[];
extern const unsigned int n_operands;
extern struct opcode opcodes[];
extern const unsigned int n_opcodes;
#endif /* _PPC_H */
/*
* Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
* All rights reserved.
*
* Redistribution and use in source and binary forms are freely
* permitted provided that the above copyright notice and this
* paragraph and the following disclaimer are duplicated in all
* such forms.
*
* This software is provided "AS IS" and without any express or
* implied warranties, including, without limitation, the implied
* warranties of merchantability and fitness for a particular
* purpose.
*/
|
1001-study-uboot
|
include/bedbug/ppc.h
|
C
|
gpl3
| 14,642
|
/* $Id$ */
#ifndef _REGS_H
#define _REGS_H
/* Special Purpose Registers */
#define SPR_CR -1
#define SPR_MSR -2
#define SPR_XER 1
#define SPR_LR 8
#define SPR_CTR 9
#define SPR_DSISR 18
#define SPR_DAR 19
#define SPR_DEC 22
#define SPR_SRR0 26
#define SPR_SRR1 27
#define SPR_EIE 80
#define SPR_EID 81
#define SPR_CMPA 144
#define SPR_CMPB 145
#define SPR_CMPC 146
#define SPR_CMPD 147
#define SPR_ICR 148
#define SPR_DER 149
#define SPR_COUNTA 150
#define SPR_COUNTB 151
#define SPR_CMPE 152
#define SPR_CMPF 153
#define SPR_CMPG 154
#define SPR_CMPH 155
#define SPR_LCTRL1 156
#define SPR_LCTRL2 157
#define SPR_ICTRL 158
#define SPR_BAR 159
#define SPR_USPRG0 256
#define SPR_SPRG4_RO 260
#define SPR_SPRG5_RO 261
#define SPR_SPRG6_RO 262
#define SPR_SPRG7_RO 263
#define SPR_SPRG0 272
#define SPR_SPRG1 273
#define SPR_SPRG2 274
#define SPR_SPRG3 275
#define SPR_SPRG4 276
#define SPR_SPRG5 277
#define SPR_SPRG6 278
#define SPR_SPRG7 279
#define SPR_EAR 282 /* MPC603e core */
#define SPR_TBL 284
#define SPR_TBU 285
#define SPR_PVR 287
#define SPR_IC_CST 560
#define SPR_IC_ADR 561
#define SPR_IC_DAT 562
#define SPR_DC_CST 568
#define SPR_DC_ADR 569
#define SPR_DC_DAT 570
#define SPR_DPDR 630
#define SPR_IMMR 638
#define SPR_MI_CTR 784
#define SPR_MI_AP 786
#define SPR_MI_EPN 787
#define SPR_MI_TWC 789
#define SPR_MI_RPN 790
#define SPR_MD_CTR 792
#define SPR_M_CASID 793
#define SPR_MD_AP 794
#define SPR_MD_EPN 795
#define SPR_M_TWB 796
#define SPR_MD_TWC 797
#define SPR_MD_RPN 798
#define SPR_M_TW 799
#define SPR_MI_DBCAM 816
#define SPR_MI_DBRAM0 817
#define SPR_MI_DBRAM1 818
#define SPR_MD_DBCAM 824
#define SPR_MD_DBRAM0 825
#define SPR_MD_DBRAM1 826
#define SPR_ZPR 944
#define SPR_PID 945
#define SPR_CCR0 947
#define SPR_IAC3 948
#define SPR_IAC4 949
#define SPR_DVC1 950
#define SPR_DVC2 951
#define SPR_SGR 953
#define SPR_DCWR 954
#define SPR_SLER 955
#define SPR_SU0R 956
#define SPR_DBCR1 957
#define SPR_ICDBDR 979
#define SPR_ESR 980
#define SPR_DEAR 981
#define SPR_EVPR 982
#define SPR_TSR 984
#define SPR_TCR 986
#define SPR_PIT 987
#define SPR_SRR2 990
#define SPR_SRR3 991
#define SPR_DBSR 1008
#define SPR_DBCR0 1010
#define SPR_IABR 1010 /* MPC603e core */
#define SPR_IAC1 1012
#define SPR_IAC2 1013
#define SPR_DAC1 1014
#define SPR_DAC2 1015
#define SPR_DCCR 1018
#define SPR_ICCR 1019
/* Bits for the DBCR0 register */
#define DBCR0_EDM 0x80000000
#define DBCR0_IDM 0x40000000
#define DBCR0_RST 0x30000000
#define DBCR0_IC 0x08000000
#define DBCR0_BT 0x04000000
#define DBCR0_EDE 0x02000000
#define DBCR0_TDE 0x01000000
#define DBCR0_IA1 0x00800000
#define DBCR0_IA2 0x00400000
#define DBCR0_IA12 0x00200000
#define DBCR0_IA12X 0x00100000
#define DBCR0_IA3 0x00080000
#define DBCR0_IA4 0x00040000
#define DBCR0_IA34 0x00020000
#define DBCR0_IA34X 0x00010000
#define DBCR0_IA12T 0x00008000
#define DBCR0_IA34T 0x00004000
#define DBCR0_FT 0x00000001
/* Bits for the DBCR1 register */
#define DBCR1_D1R 0x80000000
#define DBCR1_D2R 0x40000000
#define DBCR1_D1W 0x20000000
#define DBCR1_D2W 0x10000000
#define DBCR1_D1S 0x0C000000
#define DBCR1_D2S 0x03000000
#define DBCR1_DA12 0x00800000
#define DBCR1_DA12X 0x00400000
#define DBCR1_DV1M 0x000C0000
#define DBCR1_DV2M 0x00030000
#define DBCR1_DV1BE 0x0000F000
#define DBCR1_DV2BE 0x00000F00
/*
* DBSR bits which have conflicting definitions on true Book E versus PPC40x
*/
#ifdef CONFIG_BOOKE
#define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */
#define DBSR_IA2 0x00400000 /* Instr Address Compare 2 Event */
#define DBSR_IA3 0x00200000 /* Instr Address Compare 3 Event */
#define DBSR_IA4 0x00100000 /* Instr Address Compare 4 Event */
#endif
#ifndef CONFIG_440
#define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */
#define DBSR_IA2 0x02000000 /* Instr Address Compare 2 Event */
#define DBSR_IA3 0x00080000 /* Instr Address Compare 3 Event */
#define DBSR_IA4 0x00040000 /* Instr Address Compare 4 Event */
#endif
struct spr_info {
int spr_val;
char spr_name[ 10 ];
};
extern struct spr_info spr_map[];
extern const unsigned int n_sprs;
#define SET_REGISTER( str, val ) \
({ unsigned long __value = (val); \
asm volatile( str : : "r" (__value)); \
__value; })
#define GET_REGISTER( str ) \
({ unsigned long __value; \
asm volatile( str : "=r" (__value) : ); \
__value; })
#define GET_CR() GET_REGISTER( "mfcr %0" )
#define SET_CR(val) SET_REGISTER( "mtcr %0", val )
#define GET_MSR() GET_REGISTER( "mfmsr %0" )
#define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
#define GET_XER() GET_REGISTER( "mfspr %0,1" )
#define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
#define GET_LR() GET_REGISTER( "mfspr %0,8" )
#define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
#define GET_CTR() GET_REGISTER( "mfspr %0,9" )
#define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
#define GET_DSISR() GET_REGISTER( "mfspr %0,18" )
#define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val )
#define GET_DAR() GET_REGISTER( "mfspr %0,19" )
#define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
#define GET_DEC() GET_REGISTER( "mfspr %0,22" )
#define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
#define GET_SRR0() GET_REGISTER( "mfspr %0,26" )
#define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val )
#define GET_SRR1() GET_REGISTER( "mfspr %0,27" )
#define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
#define GET_EIE() GET_REGISTER( "mfspr %0,80" )
#define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
#define GET_EID() GET_REGISTER( "mfspr %0,81" )
#define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val )
#define GET_CMPA() GET_REGISTER( "mfspr %0,144" )
#define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val )
#define GET_CMPB() GET_REGISTER( "mfspr %0,145" )
#define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val )
#define GET_CMPC() GET_REGISTER( "mfspr %0,146" )
#define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val )
#define GET_CMPD() GET_REGISTER( "mfspr %0,147" )
#define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val )
#define GET_ICR() GET_REGISTER( "mfspr %0,148" )
#define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val )
#define GET_DER() GET_REGISTER( "mfspr %0,149" )
#define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val )
#define GET_COUNTA() GET_REGISTER( "mfspr %0,150" )
#define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val )
#define GET_COUNTB() GET_REGISTER( "mfspr %0,151" )
#define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val )
#define GET_CMPE() GET_REGISTER( "mfspr %0,152" )
#define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val )
#define GET_CMPF() GET_REGISTER( "mfspr %0,153" )
#define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val )
#define GET_CMPG() GET_REGISTER( "mfspr %0,154" )
#define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val )
#define GET_CMPH() GET_REGISTER( "mfspr %0,155" )
#define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val )
#define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" )
#define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val )
#define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" )
#define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val )
#define GET_ICTRL() GET_REGISTER( "mfspr %0,158" )
#define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val )
#define GET_BAR() GET_REGISTER( "mfspr %0,159" )
#define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val )
#define GET_USPRG0() GET_REGISTER( "mfspr %0,256" )
#define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val )
#define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" )
#define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val )
#define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" )
#define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val )
#define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" )
#define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val )
#define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" )
#define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val )
#define GET_SPRG0() GET_REGISTER( "mfspr %0,272" )
#define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val )
#define GET_SPRG1() GET_REGISTER( "mfspr %0,273" )
#define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val )
#define GET_SPRG2() GET_REGISTER( "mfspr %0,274" )
#define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val )
#define GET_SPRG3() GET_REGISTER( "mfspr %0,275" )
#define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val )
#define GET_SPRG4() GET_REGISTER( "mfspr %0,276" )
#define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val )
#define GET_SPRG5() GET_REGISTER( "mfspr %0,277" )
#define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val )
#define GET_SPRG6() GET_REGISTER( "mfspr %0,278" )
#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val )
#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" )
#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val )
#define GET_EAR() GET_REGISTER( "mfspr %0,282" )
#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val )
#define GET_TBL() GET_REGISTER( "mfspr %0,284" )
#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val )
#define GET_TBU() GET_REGISTER( "mfspr %0,285" )
#define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val )
#define GET_PVR() GET_REGISTER( "mfspr %0,287" )
#define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val )
#define GET_IC_CST() GET_REGISTER( "mfspr %0,560" )
#define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val )
#define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" )
#define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val )
#define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" )
#define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val )
#define GET_DC_CST() GET_REGISTER( "mfspr %0,568" )
#define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val )
#define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" )
#define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val )
#define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" )
#define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val )
#define GET_DPDR() GET_REGISTER( "mfspr %0,630" )
#define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val )
#define GET_IMMR() GET_REGISTER( "mfspr %0,638" )
#define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val )
#define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" )
#define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val )
#define GET_MI_AP() GET_REGISTER( "mfspr %0,786" )
#define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val )
#define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" )
#define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val )
#define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" )
#define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val )
#define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" )
#define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val )
#define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" )
#define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val )
#define GET_M_CASID() GET_REGISTER( "mfspr %0,793" )
#define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val )
#define GET_MD_AP() GET_REGISTER( "mfspr %0,794" )
#define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val )
#define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" )
#define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val )
#define GET_M_TWB() GET_REGISTER( "mfspr %0,796" )
#define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val )
#define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" )
#define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val )
#define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" )
#define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val )
#define GET_M_TW() GET_REGISTER( "mfspr %0,799" )
#define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val )
#define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" )
#define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val )
#define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" )
#define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val )
#define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" )
#define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val )
#define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" )
#define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val )
#define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" )
#define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val )
#define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" )
#define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val )
#define GET_ZPR() GET_REGISTER( "mfspr %0,944" )
#define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val )
#define GET_PID() GET_REGISTER( "mfspr %0,945" )
#define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val )
#define GET_CCR0() GET_REGISTER( "mfspr %0,947" )
#define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val )
#define GET_IAC3() GET_REGISTER( "mfspr %0,948" )
#define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val )
#define GET_IAC4() GET_REGISTER( "mfspr %0,949" )
#define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val )
#define GET_DVC1() GET_REGISTER( "mfspr %0,950" )
#define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val )
#define GET_DVC2() GET_REGISTER( "mfspr %0,951" )
#define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val )
#define GET_SGR() GET_REGISTER( "mfspr %0,953" )
#define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val )
#define GET_DCWR() GET_REGISTER( "mfspr %0,954" )
#define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val )
#define GET_SLER() GET_REGISTER( "mfspr %0,955" )
#define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val )
#define GET_SU0R() GET_REGISTER( "mfspr %0,956" )
#define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val )
#define GET_DBCR1() GET_REGISTER( "mfspr %0,957" )
#define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val )
#define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" )
#define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val )
#define GET_ESR() GET_REGISTER( "mfspr %0,980" )
#define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val )
#define GET_DEAR() GET_REGISTER( "mfspr %0,981" )
#define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val )
#define GET_EVPR() GET_REGISTER( "mfspr %0,982" )
#define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val )
#define GET_TSR() GET_REGISTER( "mfspr %0,984" )
#define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val )
#define GET_TCR() GET_REGISTER( "mfspr %0,986" )
#define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val )
#define GET_PIT() GET_REGISTER( "mfspr %0,987" )
#define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val )
#define GET_SRR2() GET_REGISTER( "mfspr %0,990" )
#define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val )
#define GET_SRR3() GET_REGISTER( "mfspr %0,991" )
#define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val )
#define GET_DBSR() GET_REGISTER( "mfspr %0,1008" )
#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val )
#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" )
#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val )
#define GET_IABR() GET_REGISTER( "mfspr %0,1010" )
#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val )
#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" )
#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val )
#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" )
#define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val )
#define GET_DAC1() GET_REGISTER( "mfspr %0,1014" )
#define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val )
#define GET_DAC2() GET_REGISTER( "mfspr %0,1015" )
#define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val )
#define GET_DCCR() GET_REGISTER( "mfspr %0,1018" )
#define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val )
#define GET_ICCR() GET_REGISTER( "mfspr %0,1019" )
#define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val )
#endif /* _REGS_H */
/*
* Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
* All rights reserved.
*
* Redistribution and use in source and binary forms are freely
* permitted provided that the above copyright notice and this
* paragraph and the following disclaimer are duplicated in all
* such forms.
*
* This software is provided "AS IS" and without any express or
* implied warranties, including, without limitation, the implied
* warranties of merchantability and fitness for a particular
* purpose.
*/
|
1001-study-uboot
|
include/bedbug/regs.h
|
C
|
gpl3
| 17,450
|
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*--------------------------------------------------------------------------
*
* Motorola S-Record Format:
*
* Motorola S-Records are an industry-standard format for
* transmitting binary files to target systems and PROM
* programmers. LSI Logic have extended this standard to include
* an S4-record containing an address and a symbol.
*
* The extended S-record standard is as follows:
*
* S<type><length><address><data....><checksum>
* S4<length><address><name>,<checksum>
*
* Where:
*
* type
* is the record type. Where:
*
* 0 starting record (optional)
* 1 data record with 16-bit address
* 2 data record with 24-bit address
* 3 data record with 32-bit address
* 4 symbol record (LSI extension)
* 5 number of data records in preceeding block
* 6 unused
* 7 ending record for S3 records
* 8 ending record for S2 records
* 9 ending record for S1 records
*
* length
* is two hex characters. This defines the length of the
* record in bytes (not characters). It includes the address
* field, the data field, and the checksum field.
*
* address
* is 4, 6, or 8 characters. Corresponding to a 16-, 24-, or
* 32-bit address. The address field for S4 records is
* always 32 bits.
*
* data
*
* Are the data bytes. Each pair of hex characters represent
* one byte in memory.
*
* name
* Is the symbol name. The symbol is terminated by a ','.
*
* checksum
* Is the one's complement of the 8-bit checksum.
*
* Example
*
* S0030000FC
* .
* .
* S325000004403C0880018D08DD900000000011000026000000003C0880012508DC50C50000B401
* S32500000460C50100B8C50200BCC50300C0C50400C4C50500C8C50600CCC50700D0C50800D4FA
* S32500000480C50900D8C50A00DCC50B00E0C50C00E4C50D00E8C50E00ECC50F00F0C51000F49A
* S325000004A0C51100F8C51200FCC5130100C5140104C5150108C516010CC5170110C518011434
* .
* .
* S70500000000FA
*
* The S0 record starts the file. The S3 records contain the
* data. The S7 record contains the entry address and terminates
* the download.
*
*--------------------------------------------------------------------------
*/
#define SREC_START 0 /* Start Record (module name) */
#define SREC_DATA2 1 /* Data Record with 2 byte address */
#define SREC_DATA3 2 /* Data Record with 3 byte address */
#define SREC_DATA4 3 /* Data Record with 4 byte address */
#define SREC_COUNT 5 /* Count Record (previously transmitted) */
#define SREC_END4 7 /* End Record with 4 byte start address */
#define SREC_END3 8 /* End Record with 3 byte start address */
#define SREC_END2 9 /* End Record with 2 byte start address */
#define SREC_EMPTY 10 /* Empty Record without any data */
#define SREC_REC_OK SREC_EMPTY /* last code without error condition */
#define SREC_E_BADTYPE -1 /* no valid S-Record */
#define SREC_E_NOSREC -2 /* line format differs from s-record */
#define SREC_E_BADCHKS -3 /* checksum error in an s-record line */
#define SREC_MAXRECLEN (512 + 4) /* max ASCII record length */
#define SREC_MAXBINLEN 255 /* resulting binary length */
int srec_decode (char *input, int *count, ulong *addr, char *data);
|
1001-study-uboot
|
include/s_record.h
|
C
|
gpl3
| 4,118
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _SPARTAN2_H_
#define _SPARTAN2_H_
#include <xilinx.h>
extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size);
extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
extern int Spartan2_info(Xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
Xilinx_pre_fn pre;
Xilinx_pgm_fn pgm;
Xilinx_init_fn init;
Xilinx_err_fn err;
Xilinx_done_fn done;
Xilinx_clk_fn clk;
Xilinx_cs_fn cs;
Xilinx_wr_fn wr;
Xilinx_rdata_fn rdata;
Xilinx_wdata_fn wdata;
Xilinx_busy_fn busy;
Xilinx_abort_fn abort;
Xilinx_post_fn post;
} Xilinx_Spartan2_Slave_Parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
Xilinx_pre_fn pre;
Xilinx_pgm_fn pgm;
Xilinx_clk_fn clk;
Xilinx_init_fn init;
Xilinx_done_fn done;
Xilinx_wr_fn wr;
Xilinx_post_fn post;
} Xilinx_Spartan2_Slave_Serial_fns;
/* Device Image Sizes
*********************************************************************/
/* Spartan-II (2.5V) */
#define XILINX_XC2S15_SIZE 197728/8
#define XILINX_XC2S30_SIZE 336800/8
#define XILINX_XC2S50_SIZE 559232/8
#define XILINX_XC2S100_SIZE 781248/8
#define XILINX_XC2S150_SIZE 1040128/8
#define XILINX_XC2S200_SIZE 1335872/8
/* Spartan-IIE (1.8V) */
#define XILINX_XC2S50E_SIZE 630048/8
#define XILINX_XC2S100E_SIZE 863840/8
#define XILINX_XC2S150E_SIZE 1134496/8
#define XILINX_XC2S200E_SIZE 1442016/8
#define XILINX_XC2S300E_SIZE 1875648/8
/* Descriptor Macros
*********************************************************************/
/* Spartan-II devices */
#define XILINX_XC2S15_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie }
#define XILINX_XC2S30_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie }
#define XILINX_XC2S50_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie }
#define XILINX_XC2S100_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie }
#define XILINX_XC2S150_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie }
#define XILINX_XC2S200_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie }
#define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie }
#define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie }
#define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie }
#define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie }
#define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie }
#endif /* _SPARTAN2_H_ */
|
1001-study-uboot
|
include/spartan2.h
|
C
|
gpl3
| 3,844
|
/*
* Copyright 2007 Freescale Semiconductor, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License Version 2. This file is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef _CONFIG_CMD_DEFAULT_H
#define _CONFIG_CMD_DEFAULT_H
/*
* Alphabetical list of all commands that are configured by default.
* This is essentially all commands minus those that are considered
* "non-standard" for some reason (memory hogs, requires special
* hardware, not fully tested, etc.).
*/
#define CONFIG_CMD_BDI /* bdinfo */
#define CONFIG_CMD_BOOTD /* bootd */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_ECHO /* echo arguments */
#define CONFIG_CMD_EDITENV /* editenv */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_IMI /* iminfo */
#define CONFIG_CMD_ITEST /* Integer (and string) test */
#ifndef CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_IMLS /* List all found images */
#endif
#define CONFIG_CMD_LOADB /* loadb */
#define CONFIG_CMD_LOADS /* loads */
#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_RUN /* run command in env variable */
#define CONFIG_CMD_SAVEENV /* saveenv */
#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
#define CONFIG_CMD_SOURCE /* "source" command support */
#define CONFIG_CMD_XIMG /* Load part of Multi Image */
#endif /* _CONFIG_CMD_DEFAULT_H */
|
1001-study-uboot
|
include/config_cmd_default.h
|
C
|
gpl3
| 1,673
|
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* mpc8xx.h
*
* MPC8xx specific definitions
*/
#ifndef __MPCXX_H__
#define __MPCXX_H__
/*-----------------------------------------------------------------------
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control Register 11-9
*/
#define SYPCR_SWTC 0xFFFF0000 /* Software Watchdog Timer Count */
#define SYPCR_BMT 0x0000FF00 /* Bus Monitor Timing */
#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration Register 11-6
*/
#define SIUMCR_EARB 0x80000000 /* External Arbitration */
#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
#define SIUMCR_DBGC01 0x00200000 /* - " - */
#define SIUMCR_DBGC10 0x00400000 /* - " - */
#define SIUMCR_DBGC11 0x00600000 /* - " - */
#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
#define SIUMCR_DBPC01 0x00080000 /* - " - */
#define SIUMCR_DBPC10 0x00100000 /* - " - */
#define SIUMCR_DBPC11 0x00180000 /* - " - */
#define SIUMCR_FRC 0x00020000 /* FRZ pin Configuration */
#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
#define SIUMCR_PNCS 0x00008000 /* Parity Non-mem Crtl reg */
#define SIUMCR_OPAR 0x00004000 /* Odd Parity */
#define SIUMCR_DPC 0x00002000 /* Data Parity pins Config. */
#define SIUMCR_MPRE 0x00001000 /* Multi CPU Reserva. Enable */
#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
#define SIUMCR_MLRC01 0x00000400 /* - " - */
#define SIUMCR_MLRC10 0x00000800 /* - " - */
#define SIUMCR_MLRC11 0x00000C00 /* - " - */
#define SIUMCR_AEME 0x00000200 /* Asynchro External Master */
#define SIUMCR_SEME 0x00000100 /* Synchro External Master */
#define SIUMCR_BSC 0x00000080 /* Byte Select Configuration */
#define SIUMCR_GB5E 0x00000040 /* GPL_B(5) Enable */
#define SIUMCR_B2DD 0x00000020 /* Bank 2 Double Drive */
#define SIUMCR_B3DD 0x00000010 /* Bank 3 Double Drive */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control Register 11-26
*/
#define TBSCR_TBIRQ7 0x8000 /* Time Base Interrupt Request 7 */
#define TBSCR_TBIRQ6 0x4000 /* Time Base Interrupt Request 6 */
#define TBSCR_TBIRQ5 0x2000 /* Time Base Interrupt Request 5 */
#define TBSCR_TBIRQ4 0x1000 /* Time Base Interrupt Request 4 */
#define TBSCR_TBIRQ3 0x0800 /* Time Base Interrupt Request 3 */
#define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */
#define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */
#define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */
#if 0 /* already in asm/8xx_immap.h */
#define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */
#define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */
#define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */
#define TBSCR_REFBE 0x0004 /* Second Interrupt Enable B */
#define TBSCR_TBF 0x0002 /* Time Base Freeze */
#define TBSCR_TBE 0x0001 /* Time Base Enable */
#endif
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control Register 11-31
*/
#undef PISCR_PIRQ /* TBD */
#define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */
#if 0 /* already in asm/8xx_immap.h */
#define PISCR_PS 0x0080 /* Periodic interrupt Status */
#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
#endif
/*-----------------------------------------------------------------------
* RSR - Reset Status Register 5-4
*/
#define RSR_JTRS 0x01000000 /* JTAG Reset Status */
#define RSR_DBSRS 0x02000000 /* Debug Port Soft Reset Status */
#define RSR_DBHRS 0x04000000 /* Debug Port Hard Reset Status */
#define RSR_CSRS 0x08000000 /* Check Stop Reset Status */
#define RSR_SWRS 0x10000000 /* Software Watchdog Reset Status*/
#define RSR_LLRS 0x20000000 /* Loss-of-Lock Reset Status */
#define RSR_ESRS 0x40000000 /* External Soft Reset Status */
#define RSR_EHRS 0x80000000 /* External Hard Reset Status */
#define RSR_ALLBITS (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS)
/*-----------------------------------------------------------------------
* Newer chips (MPC866 family and MPC87x/88x family) have different
* clock distribution system. Their IMMR lower half is >= 0x0800
*/
#define MPC8xx_NEW_CLK 0x0800
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*/
/* Newer chips (MPC866/87x/88x et al) defines */
#define PLPRCR_MFN_MSK 0xF8000000 /* Multiplication factor numerator bits */
#define PLPRCR_MFN_SHIFT 27 /* Multiplication factor numerator shift*/
#define PLPRCR_MFD_MSK 0x07C00000 /* Multiplication factor denominator bits */
#define PLPRCR_MFD_SHIFT 22 /* Multiplication factor denominator shift*/
#define PLPRCR_S_MSK 0x00300000 /* Multiplication factor integer bits */
#define PLPRCR_S_SHIFT 20 /* Multiplication factor integer shift */
#define PLPRCR_MFI_MSK 0x000F0000 /* Multiplication factor integer bits */
#define PLPRCR_MFI_SHIFT 16 /* Multiplication factor integer shift */
#define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */
#define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */
#define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */
/* Multiplication factor + PDF bits */
#define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \
PLPRCR_MFD_MSK | \
PLPRCR_S_MSK | \
PLPRCR_MFI_MSK | \
PLPRCR_PDF_MSK)
/* Older chips (MPC860/862 et al) defines */
#define PLPRCR_MF_MSK 0xFFF00000 /* Multiplication factor bits */
#define PLPRCR_MF_SHIFT 20 /* Multiplication factor shift value */
#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
#define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */
#define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */
#define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */
#define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */
#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */
#define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */
/* Common defines */
#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
#define PLPRCR_CSRC 0x00000400 /* Clock Source */
#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
#define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */
#define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*/
#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
#define SCCR_COM10 0x40000000 /* reserved */
#define SCCR_COM11 0x60000000 /* CLKOUT output buffer disabled */
#define SCCR_TBS 0x02000000 /* Time Base Source */
#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
#define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */
#define SCCR_CRQEN 0x00400000 /* CPM Request Enable */
#define SCCR_PRQEN 0x00200000 /* Power Management Request Enable */
#define SCCR_EBDF00 0x00000000 /* CLKOUT is GCLK2 / 1 (normal op.) */
#define SCCR_EBDF01 0x00020000 /* CLKOUT is GCLK2 / 2 */
#define SCCR_EBDF10 0x00040000 /* reserved */
#define SCCR_EBDF11 0x00060000 /* reserved */
#define SCCR_DFSYNC00 0x00000000 /* SyncCLK division by 1 (normal op.) */
#define SCCR_DFSYNC01 0x00002000 /* SyncCLK division by 4 */
#define SCCR_DFSYNC10 0x00004000 /* SyncCLK division by 16 */
#define SCCR_DFSYNC11 0x00006000 /* SyncCLK division by 64 */
#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 1 (normal op.) */
#define SCCR_DFBRG01 0x00000800 /* BRGCLK division by 4 */
#define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */
#define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */
#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
#define SCCR_DFNL001 0x00000100 /* Division by 4 */
#define SCCR_DFNL010 0x00000200 /* Division by 8 */
#define SCCR_DFNL011 0x00000300 /* Division by 16 */
#define SCCR_DFNL100 0x00000400 /* Division by 32 */
#define SCCR_DFNL101 0x00000500 /* Division by 64 */
#define SCCR_DFNL110 0x00000600 /* Division by 128 */
#define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */
#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */
#define SCCR_DFNH111 0x000000E0 /* reserved */
#define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFLCD001 0x00000004 /* Division by 2 */
#define SCCR_DFLCD010 0x00000008 /* Division by 4 */
#define SCCR_DFLCD011 0x0000000C /* Division by 8 */
#define SCCR_DFLCD100 0x00000010 /* Division by 16 */
#define SCCR_DFLCD101 0x00000014 /* Division by 32 */
#define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */
#define SCCR_DFLCD111 0x0000001C /* reserved */
#define SCCR_DFALCD00 0x00000000 /* Division by 1 (default = minimum) */
#define SCCR_DFALCD01 0x00000001 /* Division by 3 */
#define SCCR_DFALCD10 0x00000002 /* Division by 5 */
#define SCCR_DFALCD11 0x00000003 /* Division by 7 (maximum) */
/*-----------------------------------------------------------------------
* BR - Memory Controler: Base Register 16-9
*/
#define BR_BA_MSK 0xFFFF8000 /* Base Address Mask */
#define BR_AT_MSK 0x00007000 /* Address Type Mask */
#define BR_PS_MSK 0x00000C00 /* Port Size Mask */
#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_PS_16 0x00000800 /* 16 bit port size */
#define BR_PS_8 0x00000400 /* 8 bit port size */
#define BR_PARE 0x00000200 /* Parity Enable */
#define BR_WP 0x00000100 /* Write Protect */
#define BR_MS_MSK 0x000000C0 /* Machine Select Mask */
#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
#define BR_MS_UPMB 0x000000C0 /* U.P.M.B Machine Select */
#define BR_V 0x00000001 /* Bank Valid */
/*-----------------------------------------------------------------------
* OR - Memory Controler: Option Register 16-11
*/
#define OR_AM_MSK 0xFFFF8000 /* Address Mask Mask */
#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
/* Address Multiplex */
#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
#define OR_BI 0x00000100 /* Burst inhibit */
#define OR_SCY_MSK 0x000000F0 /* Cycle Lenght in Clocks */
#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
#define OR_SCY_10_CLK 0x000000A0 /* 10 clock cycles wait states */
#define OR_SCY_11_CLK 0x000000B0 /* 11 clock cycles wait states */
#define OR_SCY_12_CLK 0x000000C0 /* 12 clock cycles wait states */
#define OR_SCY_13_CLK 0x000000D0 /* 13 clock cycles wait states */
#define OR_SCY_14_CLK 0x000000E0 /* 14 clock cycles wait states */
#define OR_SCY_15_CLK 0x000000F0 /* 15 clock cycles wait states */
#define OR_SETA 0x00000008 /* External Transfer Acknowledge */
#define OR_TRLX 0x00000004 /* Timing Relaxed */
#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
/*-----------------------------------------------------------------------
* MPTPR - Memory Periodic Timer Prescaler Register 16-17
*/
#define MPTPR_PTP_MSK 0xFF00 /* Periodic Timers Prescaler Mask */
#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */
#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */
#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */
#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */
#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */
#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */
/*-----------------------------------------------------------------------
* MCR - Memory Command Register
*/
#define MCR_OP_WRITE 0x00000000 /* WRITE command */
#define MCR_OP_READ 0x40000000 /* READ command */
#define MCR_OP_RUN 0x80000000 /* RUN command */
#define MCR_UPM_A 0x00000000 /* Select UPM A */
#define MCR_UPM_B 0x00800000 /* Select UPM B */
#define MCR_MB_CS0 0x00000000 /* Use Chip Select /CS0 */
#define MCR_MB_CS1 0x00002000 /* Use Chip Select /CS1 */
#define MCR_MB_CS2 0x00004000 /* Use Chip Select /CS2 */
#define MCR_MB_CS3 0x00006000 /* Use Chip Select /CS3 */
#define MCR_MB_CS4 0x00008000 /* Use Chip Select /CS4 */
#define MCR_MB_CS5 0x0000A000 /* Use Chip Select /CS5 */
#define MCR_MB_CS6 0x0000C000 /* Use Chip Select /CS6 */
#define MCR_MB_CS7 0x0000E000 /* Use Chip Select /CS7 */
#define MCR_MLCF(n) (((n)&0xF)<<8) /* Memory Command Loop Count Field */
#define MCR_MAD(addr) ((addr)&0x3F) /* Memory Array Index */
/*-----------------------------------------------------------------------
* Machine A Mode Register 16-13
*/
#define MAMR_PTA_MSK 0xFF000000 /* Periodic Timer A period mask */
#define MAMR_PTA_SHIFT 0x00000018 /* Periodic Timer A period shift */
#define MAMR_PTAE 0x00800000 /* Periodic Timer A Enable */
#define MAMR_AMA_MSK 0x00700000 /* Addess Multiplexing size A */
#define MAMR_AMA_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
#define MAMR_AMA_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
#define MAMR_AMA_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
#define MAMR_AMA_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
#define MAMR_AMA_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
#define MAMR_AMA_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
#define MAMR_DSA_MSK 0x00060000 /* Disable Timer period mask */
#define MAMR_DSA_1_CYCL 0x00000000 /* 1 cycle Disable Period */
#define MAMR_DSA_2_CYCL 0x00020000 /* 2 cycle Disable Period */
#define MAMR_DSA_3_CYCL 0x00040000 /* 3 cycle Disable Period */
#define MAMR_DSA_4_CYCL 0x00060000 /* 4 cycle Disable Period */
#define MAMR_G0CLA_MSK 0x0000E000 /* General Line 0 Control A */
#define MAMR_G0CLA_A12 0x00000000 /* General Line 0 : A12 */
#define MAMR_G0CLA_A11 0x00002000 /* General Line 0 : A11 */
#define MAMR_G0CLA_A10 0x00004000 /* General Line 0 : A10 */
#define MAMR_G0CLA_A9 0x00006000 /* General Line 0 : A9 */
#define MAMR_G0CLA_A8 0x00008000 /* General Line 0 : A8 */
#define MAMR_G0CLA_A7 0x0000A000 /* General Line 0 : A7 */
#define MAMR_G0CLA_A6 0x0000C000 /* General Line 0 : A6 */
#define MAMR_G0CLA_A5 0x0000E000 /* General Line 0 : A5 */
#define MAMR_GPL_A4DIS 0x00001000 /* GPL_A4 ouput line Disable */
#define MAMR_RLFA_MSK 0x00000F00 /* Read Loop Field A mask */
#define MAMR_RLFA_1X 0x00000100 /* The Read Loop is executed 1 time */
#define MAMR_RLFA_2X 0x00000200 /* The Read Loop is executed 2 times */
#define MAMR_RLFA_3X 0x00000300 /* The Read Loop is executed 3 times */
#define MAMR_RLFA_4X 0x00000400 /* The Read Loop is executed 4 times */
#define MAMR_RLFA_5X 0x00000500 /* The Read Loop is executed 5 times */
#define MAMR_RLFA_6X 0x00000600 /* The Read Loop is executed 6 times */
#define MAMR_RLFA_7X 0x00000700 /* The Read Loop is executed 7 times */
#define MAMR_RLFA_8X 0x00000800 /* The Read Loop is executed 8 times */
#define MAMR_RLFA_9X 0x00000900 /* The Read Loop is executed 9 times */
#define MAMR_RLFA_10X 0x00000A00 /* The Read Loop is executed 10 times */
#define MAMR_RLFA_11X 0x00000B00 /* The Read Loop is executed 11 times */
#define MAMR_RLFA_12X 0x00000C00 /* The Read Loop is executed 12 times */
#define MAMR_RLFA_13X 0x00000D00 /* The Read Loop is executed 13 times */
#define MAMR_RLFA_14X 0x00000E00 /* The Read Loop is executed 14 times */
#define MAMR_RLFA_15X 0x00000F00 /* The Read Loop is executed 15 times */
#define MAMR_RLFA_16X 0x00000000 /* The Read Loop is executed 16 times */
#define MAMR_WLFA_MSK 0x000000F0 /* Write Loop Field A mask */
#define MAMR_WLFA_1X 0x00000010 /* The Write Loop is executed 1 time */
#define MAMR_WLFA_2X 0x00000020 /* The Write Loop is executed 2 times */
#define MAMR_WLFA_3X 0x00000030 /* The Write Loop is executed 3 times */
#define MAMR_WLFA_4X 0x00000040 /* The Write Loop is executed 4 times */
#define MAMR_WLFA_5X 0x00000050 /* The Write Loop is executed 5 times */
#define MAMR_WLFA_6X 0x00000060 /* The Write Loop is executed 6 times */
#define MAMR_WLFA_7X 0x00000070 /* The Write Loop is executed 7 times */
#define MAMR_WLFA_8X 0x00000080 /* The Write Loop is executed 8 times */
#define MAMR_WLFA_9X 0x00000090 /* The Write Loop is executed 9 times */
#define MAMR_WLFA_10X 0x000000A0 /* The Write Loop is executed 10 times */
#define MAMR_WLFA_11X 0x000000B0 /* The Write Loop is executed 11 times */
#define MAMR_WLFA_12X 0x000000C0 /* The Write Loop is executed 12 times */
#define MAMR_WLFA_13X 0x000000D0 /* The Write Loop is executed 13 times */
#define MAMR_WLFA_14X 0x000000E0 /* The Write Loop is executed 14 times */
#define MAMR_WLFA_15X 0x000000F0 /* The Write Loop is executed 15 times */
#define MAMR_WLFA_16X 0x00000000 /* The Write Loop is executed 16 times */
#define MAMR_TLFA_MSK 0x0000000F /* Timer Loop Field A mask */
#define MAMR_TLFA_1X 0x00000001 /* The Timer Loop is executed 1 time */
#define MAMR_TLFA_2X 0x00000002 /* The Timer Loop is executed 2 times */
#define MAMR_TLFA_3X 0x00000003 /* The Timer Loop is executed 3 times */
#define MAMR_TLFA_4X 0x00000004 /* The Timer Loop is executed 4 times */
#define MAMR_TLFA_5X 0x00000005 /* The Timer Loop is executed 5 times */
#define MAMR_TLFA_6X 0x00000006 /* The Timer Loop is executed 6 times */
#define MAMR_TLFA_7X 0x00000007 /* The Timer Loop is executed 7 times */
#define MAMR_TLFA_8X 0x00000008 /* The Timer Loop is executed 8 times */
#define MAMR_TLFA_9X 0x00000009 /* The Timer Loop is executed 9 times */
#define MAMR_TLFA_10X 0x0000000A /* The Timer Loop is executed 10 times */
#define MAMR_TLFA_11X 0x0000000B /* The Timer Loop is executed 11 times */
#define MAMR_TLFA_12X 0x0000000C /* The Timer Loop is executed 12 times */
#define MAMR_TLFA_13X 0x0000000D /* The Timer Loop is executed 13 times */
#define MAMR_TLFA_14X 0x0000000E /* The Timer Loop is executed 14 times */
#define MAMR_TLFA_15X 0x0000000F /* The Timer Loop is executed 15 times */
#define MAMR_TLFA_16X 0x00000000 /* The Timer Loop is executed 16 times */
/*-----------------------------------------------------------------------
* Machine B Mode Register 16-13
*/
#define MBMR_PTB_MSK 0xFF000000 /* Periodic Timer B period mask */
#define MBMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */
#define MBMR_PTBE 0x00800000 /* Periodic Timer B Enable */
#define MBMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */
#define MBMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
#define MBMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
#define MBMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
#define MBMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
#define MBMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
#define MBMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
#define MBMR_DSB_MSK 0x00060000 /* Disable Timer period mask */
#define MBMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */
#define MBMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */
#define MBMR_DSB_3_CYCL 0x00040000 /* 3 cycle Disable Period */
#define MBMR_DSB_4_CYCL 0x00060000 /* 4 cycle Disable Period */
#define MBMR_G0CLB_MSK 0x0000E000 /* General Line 0 Control B */
#define MBMR_G0CLB_A12 0x00000000 /* General Line 0 : A12 */
#define MBMR_G0CLB_A11 0x00002000 /* General Line 0 : A11 */
#define MBMR_G0CLB_A10 0x00004000 /* General Line 0 : A10 */
#define MBMR_G0CLB_A9 0x00006000 /* General Line 0 : A9 */
#define MBMR_G0CLB_A8 0x00008000 /* General Line 0 : A8 */
#define MBMR_G0CLB_A7 0x0000A000 /* General Line 0 : A7 */
#define MBMR_G0CLB_A6 0x0000C000 /* General Line 0 : A6 */
#define MBMR_G0CLB_A5 0x0000E000 /* General Line 0 : A5 */
#define MBMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */
#define MBMR_RLFB_MSK 0x00000F00 /* Read Loop Field B mask */
#define MBMR_RLFB_1X 0x00000100 /* The Read Loop is executed 1 time */
#define MBMR_RLFB_2X 0x00000200 /* The Read Loop is executed 2 times */
#define MBMR_RLFB_3X 0x00000300 /* The Read Loop is executed 3 times */
#define MBMR_RLFB_4X 0x00000400 /* The Read Loop is executed 4 times */
#define MBMR_RLFB_5X 0x00000500 /* The Read Loop is executed 5 times */
#define MBMR_RLFB_6X 0x00000600 /* The Read Loop is executed 6 times */
#define MBMR_RLFB_7X 0x00000700 /* The Read Loop is executed 7 times */
#define MBMR_RLFB_8X 0x00000800 /* The Read Loop is executed 8 times */
#define MBMR_RLFB_9X 0x00000900 /* The Read Loop is executed 9 times */
#define MBMR_RLFB_10X 0x00000A00 /* The Read Loop is executed 10 times */
#define MBMR_RLFB_11X 0x00000B00 /* The Read Loop is executed 11 times */
#define MBMR_RLFB_12X 0x00000C00 /* The Read Loop is executed 12 times */
#define MBMR_RLFB_13X 0x00000D00 /* The Read Loop is executed 13 times */
#define MBMR_RLFB_14X 0x00000E00 /* The Read Loop is executed 14 times */
#define MBMR_RLFB_15X 0x00000f00 /* The Read Loop is executed 15 times */
#define MBMR_RLFB_16X 0x00000000 /* The Read Loop is executed 16 times */
#define MBMR_WLFB_MSK 0x000000F0 /* Write Loop Field B mask */
#define MBMR_WLFB_1X 0x00000010 /* The Write Loop is executed 1 time */
#define MBMR_WLFB_2X 0x00000020 /* The Write Loop is executed 2 times */
#define MBMR_WLFB_3X 0x00000030 /* The Write Loop is executed 3 times */
#define MBMR_WLFB_4X 0x00000040 /* The Write Loop is executed 4 times */
#define MBMR_WLFB_5X 0x00000050 /* The Write Loop is executed 5 times */
#define MBMR_WLFB_6X 0x00000060 /* The Write Loop is executed 6 times */
#define MBMR_WLFB_7X 0x00000070 /* The Write Loop is executed 7 times */
#define MBMR_WLFB_8X 0x00000080 /* The Write Loop is executed 8 times */
#define MBMR_WLFB_9X 0x00000090 /* The Write Loop is executed 9 times */
#define MBMR_WLFB_10X 0x000000A0 /* The Write Loop is executed 10 times */
#define MBMR_WLFB_11X 0x000000B0 /* The Write Loop is executed 11 times */
#define MBMR_WLFB_12X 0x000000C0 /* The Write Loop is executed 12 times */
#define MBMR_WLFB_13X 0x000000D0 /* The Write Loop is executed 13 times */
#define MBMR_WLFB_14X 0x000000E0 /* The Write Loop is executed 14 times */
#define MBMR_WLFB_15X 0x000000F0 /* The Write Loop is executed 15 times */
#define MBMR_WLFB_16X 0x00000000 /* The Write Loop is executed 16 times */
#define MBMR_TLFB_MSK 0x0000000F /* Timer Loop Field B mask */
#define MBMR_TLFB_1X 0x00000001 /* The Timer Loop is executed 1 time */
#define MBMR_TLFB_2X 0x00000002 /* The Timer Loop is executed 2 times */
#define MBMR_TLFB_3X 0x00000003 /* The Timer Loop is executed 3 times */
#define MBMR_TLFB_4X 0x00000004 /* The Timer Loop is executed 4 times */
#define MBMR_TLFB_5X 0x00000005 /* The Timer Loop is executed 5 times */
#define MBMR_TLFB_6X 0x00000006 /* The Timer Loop is executed 6 times */
#define MBMR_TLFB_7X 0x00000007 /* The Timer Loop is executed 7 times */
#define MBMR_TLFB_8X 0x00000008 /* The Timer Loop is executed 8 times */
#define MBMR_TLFB_9X 0x00000009 /* The Timer Loop is executed 9 times */
#define MBMR_TLFB_10X 0x0000000A /* The Timer Loop is executed 10 times */
#define MBMR_TLFB_11X 0x0000000B /* The Timer Loop is executed 11 times */
#define MBMR_TLFB_12X 0x0000000C /* The Timer Loop is executed 12 times */
#define MBMR_TLFB_13X 0x0000000D /* The Timer Loop is executed 13 times */
#define MBMR_TLFB_14X 0x0000000E /* The Timer Loop is executed 14 times */
#define MBMR_TLFB_15X 0x0000000F /* The Timer Loop is executed 15 times */
#define MBMR_TLFB_16X 0x00000000 /* The Timer Loop is executed 16 times */
/*-----------------------------------------------------------------------
* Timer Global Configuration Register 18-8
*/
#define TGCR_CAS4 0x8000 /* Cascade Timer 3 and 4 */
#define TGCR_FRZ4 0x4000 /* Freeze timer 4 */
#define TGCR_STP4 0x2000 /* Stop timer 4 */
#define TGCR_RST4 0x1000 /* Reset timer 4 */
#define TGCR_GM2 0x0800 /* Gate Mode for Pin 2 */
#define TGCR_FRZ3 0x0400 /* Freeze timer 3 */
#define TGCR_STP3 0x0200 /* Stop timer 3 */
#define TGCR_RST3 0x0100 /* Reset timer 3 */
#define TGCR_CAS2 0x0080 /* Cascade Timer 1 and 2 */
#define TGCR_FRZ2 0x0040 /* Freeze timer 2 */
#define TGCR_STP2 0x0020 /* Stop timer 2 */
#define TGCR_RST2 0x0010 /* Reset timer 2 */
#define TGCR_GM1 0x0008 /* Gate Mode for Pin 1 */
#define TGCR_FRZ1 0x0004 /* Freeze timer 1 */
#define TGCR_STP1 0x0002 /* Stop timer 1 */
#define TGCR_RST1 0x0001 /* Reset timer 1 */
/*-----------------------------------------------------------------------
* Timer Mode Register 18-9
*/
#define TMR_PS_MSK 0xFF00 /* Prescaler Value */
#define TMR_PS_SHIFT 8 /* Prescaler position */
#define TMR_CE_MSK 0x00C0 /* Capture Edge and Enable Interrupt */
#define TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */
#define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
#define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
#define TMR_CE_ANY 0x00C0 /* Capture on any TINx edge */
#define TMR_OM 0x0020 /* Output Mode */
#define TMR_ORI 0x0010 /* Output Reference Interrupt Enable */
#define TMR_FRR 0x0008 /* Free Run/Restart */
#define TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
#define TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
#define TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */
#define TMR_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16 */
#define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */
#define TMR_GE 0x0001 /* Gate Enable */
/*-----------------------------------------------------------------------
* I2C Controller Registers
*/
#define I2MOD_REVD 0x20 /* Reverese Data */
#define I2MOD_GCD 0x10 /* General Call Disable */
#define I2MOD_FLT 0x08 /* Clock Filter */
#define I2MOD_PDIV32 0x00 /* Pre-Divider 32 */
#define I2MOD_PDIV16 0x02 /* Pre-Divider 16 */
#define I2MOD_PDIV8 0x04 /* Pre-Divider 8 */
#define I2MOD_PDIV4 0x06 /* Pre-Divider 4 */
#define I2MOD_EN 0x01 /* Enable */
#define I2CER_TXE 0x10 /* Tx Error */
#define I2CER_BSY 0x04 /* Busy Condition */
#define I2CER_TXB 0x02 /* Tx Buffer Transmitted */
#define I2CER_RXB 0x01 /* Rx Buffer Received */
#define I2CER_ALL (I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB)
#define I2COM_STR 0x80 /* Start Transmit */
#define I2COM_MASTER 0x01 /* Master mode */
/*-----------------------------------------------------------------------
* SPI Controller Registers 31-10
*/
#define SPI_EMASK 0x37 /* Event Mask */
#define SPI_MME 0x20 /* Multi-Master Error */
#define SPI_TXE 0x10 /* Transmit Error */
#define SPI_BSY 0x04 /* Busy */
#define SPI_TXB 0x02 /* Tx Buffer Empty */
#define SPI_RXB 0x01 /* RX Buffer full/closed */
#define SPI_STR 0x80 /* SPCOM: Start transmit */
/*-----------------------------------------------------------------------
* PCMCIA Interface General Control Register 17-12
*/
#define PCMCIA_GCRX_CXRESET 0x00000040
#define PCMCIA_GCRX_CXOE 0x00000080
#define PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
#define PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
#define PCMCIA_VS_MASK(slot) (0xC0000000 >> (slot << 4))
#define PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
#define PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
#define PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
#define PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
#define PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
#define PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
#define PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
#define PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
#define PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
#define PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
#define PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
#define PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
/*-----------------------------------------------------------------------
* PCMCIA Option Register Definitions
*
* Bank Sizes:
*/
#define PCMCIA_BSIZE_1 0x00000000 /* Bank size: 1 Bytes */
#define PCMCIA_BSIZE_2 0x08000000 /* Bank size: 2 Bytes */
#define PCMCIA_BSIZE_4 0x18000000 /* Bank size: 4 Bytes */
#define PCMCIA_BSIZE_8 0x10000000 /* Bank size: 8 Bytes */
#define PCMCIA_BSIZE_16 0x30000000 /* Bank size: 16 Bytes */
#define PCMCIA_BSIZE_32 0x38000000 /* Bank size: 32 Bytes */
#define PCMCIA_BSIZE_64 0x28000000 /* Bank size: 64 Bytes */
#define PCMCIA_BSIZE_128 0x20000000 /* Bank size: 128 Bytes */
#define PCMCIA_BSIZE_256 0x60000000 /* Bank size: 256 Bytes */
#define PCMCIA_BSIZE_512 0x68000000 /* Bank size: 512 Bytes */
#define PCMCIA_BSIZE_1K 0x78000000 /* Bank size: 1 kB */
#define PCMCIA_BSIZE_2K 0x70000000 /* Bank size: 2 kB */
#define PCMCIA_BSIZE_4K 0x50000000 /* Bank size: 4 kB */
#define PCMCIA_BSIZE_8K 0x58000000 /* Bank size: 8 kB */
#define PCMCIA_BSIZE_16K 0x48000000 /* Bank size: 16 kB */
#define PCMCIA_BSIZE_32K 0x40000000 /* Bank size: 32 kB */
#define PCMCIA_BSIZE_64K 0xC0000000 /* Bank size: 64 kB */
#define PCMCIA_BSIZE_128K 0xC8000000 /* Bank size: 128 kB */
#define PCMCIA_BSIZE_256K 0xD8000000 /* Bank size: 256 kB */
#define PCMCIA_BSIZE_512K 0xD0000000 /* Bank size: 512 kB */
#define PCMCIA_BSIZE_1M 0xF0000000 /* Bank size: 1 MB */
#define PCMCIA_BSIZE_2M 0xF8000000 /* Bank size: 2 MB */
#define PCMCIA_BSIZE_4M 0xE8000000 /* Bank size: 4 MB */
#define PCMCIA_BSIZE_8M 0xE0000000 /* Bank size: 8 MB */
#define PCMCIA_BSIZE_16M 0xA0000000 /* Bank size: 16 MB */
#define PCMCIA_BSIZE_32M 0xA8000000 /* Bank size: 32 MB */
#define PCMCIA_BSIZE_64M 0xB8000000 /* Bank size: 64 MB */
/* PCMCIA Timing */
#define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */
#define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */
#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */
/* PCMCIA Port Sizes */
#define PCMCIA_PPS_8 0x00000000 /* 8 bit port size */
#define PCMCIA_PPS_16 0x00000040 /* 16 bit port size */
/* PCMCIA Region Select */
#define PCMCIA_PRS_MEM 0x00000000 /* Common Memory Space */
#define PCMCIA_PRS_ATTR 0x00000010 /* Attribute Space */
#define PCMCIA_PRS_IO 0x00000018 /* I/O Space */
#define PCMCIA_PRS_DMA 0x00000020 /* DMA, normal transfer */
#define PCMCIA_PRS_DMA_LAST 0x00000028 /* DMA, last transactn */
#define PCMCIA_PRS_CEx 0x00000030 /* A[22:23] ==> CE1,CE2 */
#define PCMCIA_PSLOT_A 0x00000000 /* Slot A */
#define PCMCIA_PSLOT_B 0x00000004 /* Slot B */
#define PCMCIA_WPROT 0x00000002 /* Write Protect */
#define PCMCIA_PV 0x00000001 /* Valid Bit */
#define UPMA 0x00000000
#define UPMB 0x00800000
#endif /* __MPCXX_H__ */
|
1001-study-uboot
|
include/mpc8xx.h
|
C
|
gpl3
| 33,967
|
/*
* Copyright 2010-2011 Calxeda, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __MENU_H__
#define __MENU_H__
struct menu;
struct menu *menu_create(char *title, int timeout, int prompt,
void (*item_data_print)(void *));
int menu_default_set(struct menu *m, char *item_key);
int menu_get_choice(struct menu *m, void **choice);
int menu_item_add(struct menu *m, char *item_key, void *item_data);
int menu_destroy(struct menu *m);
#endif /* __MENU_H__ */
|
1001-study-uboot
|
include/menu.h
|
C
|
gpl3
| 1,076
|
/*
* File: include/pca9564.h
* Author:
*
* Created: 2009-06-23
* Description: PCA9564 i2c bridge driver
*
* Modified:
* Copyright 2009 CJSC "NII STT", http://www.niistt.ru/
*
* Bugs:
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PCA9564_H
#define _PCA9564_H
/* Clock speeds for the bus */
#define PCA_CON_330kHz 0x00
#define PCA_CON_288kHz 0x01
#define PCA_CON_217kHz 0x02
#define PCA_CON_146kHz 0x03
#define PCA_CON_88kHz 0x04
#define PCA_CON_59kHz 0x05
#define PCA_CON_44kHz 0x06
#define PCA_CON_36kHz 0x07
#define PCA_CON_AA 0x80 /* Assert Acknowledge */
#define PCA_CON_ENSIO 0x40 /* Enable */
#define PCA_CON_STA 0x20 /* Start */
#define PCA_CON_STO 0x10 /* Stop */
#define PCA_CON_SI 0x08 /* Serial Interrupt */
#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */
#endif
|
1001-study-uboot
|
include/pca9564.h
|
C
|
gpl3
| 1,620
|
/*
* Copyright (c) 1995, 1996, 2001, 2002
* Erik Theisen. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This is the ELF ABI header file
* formerly known as "elf_abi.h".
*/
#ifndef _ELF_H
#define _ELF_H
#include "compiler.h"
/*
* This version doesn't work for 64-bit ABIs - Erik.
*/
/*
* These typedefs need to be handled better.
*/
typedef uint32_t Elf32_Addr; /* Unsigned program address */
typedef uint32_t Elf32_Off; /* Unsigned file offset */
typedef int32_t Elf32_Sword; /* Signed large integer */
typedef uint32_t Elf32_Word; /* Unsigned large integer */
typedef uint16_t Elf32_Half; /* Unsigned medium integer */
/* e_ident[] identification indexes */
#define EI_MAG0 0 /* file ID */
#define EI_MAG1 1 /* file ID */
#define EI_MAG2 2 /* file ID */
#define EI_MAG3 3 /* file ID */
#define EI_CLASS 4 /* file class */
#define EI_DATA 5 /* data encoding */
#define EI_VERSION 6 /* ELF header version */
#define EI_OSABI 7 /* OS/ABI specific ELF extensions */
#define EI_ABIVERSION 8 /* ABI target version */
#define EI_PAD 9 /* start of pad bytes */
#define EI_NIDENT 16 /* Size of e_ident[] */
/* e_ident[] magic number */
#define ELFMAG0 0x7f /* e_ident[EI_MAG0] */
#define ELFMAG1 'E' /* e_ident[EI_MAG1] */
#define ELFMAG2 'L' /* e_ident[EI_MAG2] */
#define ELFMAG3 'F' /* e_ident[EI_MAG3] */
#define ELFMAG "\177ELF" /* magic */
#define SELFMAG 4 /* size of magic */
/* e_ident[] file class */
#define ELFCLASSNONE 0 /* invalid */
#define ELFCLASS32 1 /* 32-bit objs */
#define ELFCLASS64 2 /* 64-bit objs */
#define ELFCLASSNUM 3 /* number of classes */
/* e_ident[] data encoding */
#define ELFDATANONE 0 /* invalid */
#define ELFDATA2LSB 1 /* Little-Endian */
#define ELFDATA2MSB 2 /* Big-Endian */
#define ELFDATANUM 3 /* number of data encode defines */
/* e_ident[] OS/ABI specific ELF extensions */
#define ELFOSABI_NONE 0 /* No extension specified */
#define ELFOSABI_HPUX 1 /* Hewlett-Packard HP-UX */
#define ELFOSABI_NETBSD 2 /* NetBSD */
#define ELFOSABI_LINUX 3 /* Linux */
#define ELFOSABI_SOLARIS 6 /* Sun Solaris */
#define ELFOSABI_AIX 7 /* AIX */
#define ELFOSABI_IRIX 8 /* IRIX */
#define ELFOSABI_FREEBSD 9 /* FreeBSD */
#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX */
#define ELFOSABI_MODESTO 11 /* Novell Modesto */
#define ELFOSABI_OPENBSD 12 /* OpenBSD */
/* 64-255 Architecture-specific value range */
/* e_ident[] ABI Version */
#define ELFABIVERSION 0
/* e_ident */
#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \
(ehdr).e_ident[EI_MAG1] == ELFMAG1 && \
(ehdr).e_ident[EI_MAG2] == ELFMAG2 && \
(ehdr).e_ident[EI_MAG3] == ELFMAG3)
/* ELF Header */
typedef struct elfhdr{
unsigned char e_ident[EI_NIDENT]; /* ELF Identification */
Elf32_Half e_type; /* object file type */
Elf32_Half e_machine; /* machine */
Elf32_Word e_version; /* object file version */
Elf32_Addr e_entry; /* virtual entry point */
Elf32_Off e_phoff; /* program header table offset */
Elf32_Off e_shoff; /* section header table offset */
Elf32_Word e_flags; /* processor-specific flags */
Elf32_Half e_ehsize; /* ELF header size */
Elf32_Half e_phentsize; /* program header entry size */
Elf32_Half e_phnum; /* number of program header entries */
Elf32_Half e_shentsize; /* section header entry size */
Elf32_Half e_shnum; /* number of section header entries */
Elf32_Half e_shstrndx; /* section header table's "section
header string table" entry offset */
} Elf32_Ehdr;
/* e_type */
#define ET_NONE 0 /* No file type */
#define ET_REL 1 /* relocatable file */
#define ET_EXEC 2 /* executable file */
#define ET_DYN 3 /* shared object file */
#define ET_CORE 4 /* core file */
#define ET_NUM 5 /* number of types */
#define ET_LOOS 0xfe00 /* reserved range for operating */
#define ET_HIOS 0xfeff /* system specific e_type */
#define ET_LOPROC 0xff00 /* reserved range for processor */
#define ET_HIPROC 0xffff /* specific e_type */
/* e_machine */
#define EM_NONE 0 /* No Machine */
#define EM_M32 1 /* AT&T WE 32100 */
#define EM_SPARC 2 /* SPARC */
#define EM_386 3 /* Intel 80386 */
#define EM_68K 4 /* Motorola 68000 */
#define EM_88K 5 /* Motorola 88000 */
#if 0
#define EM_486 6 /* RESERVED - was Intel 80486 */
#endif
#define EM_860 7 /* Intel 80860 */
#define EM_MIPS 8 /* MIPS R3000 Big-Endian only */
#define EM_S370 9 /* IBM System/370 Processor */
#define EM_MIPS_RS4_BE 10 /* MIPS R4000 Big-Endian */
#if 0
#define EM_SPARC64 11 /* RESERVED - was SPARC v9
64-bit unoffical */
#endif
/* RESERVED 11-14 for future use */
#define EM_PARISC 15 /* HPPA */
/* RESERVED 16 for future use */
#define EM_VPP500 17 /* Fujitsu VPP500 */
#define EM_SPARC32PLUS 18 /* Enhanced instruction set SPARC */
#define EM_960 19 /* Intel 80960 */
#define EM_PPC 20 /* PowerPC */
#define EM_PPC64 21 /* 64-bit PowerPC */
#define EM_S390 22 /* IBM System/390 Processor */
/* RESERVED 23-35 for future use */
#define EM_V800 36 /* NEC V800 */
#define EM_FR20 37 /* Fujitsu FR20 */
#define EM_RH32 38 /* TRW RH-32 */
#define EM_RCE 39 /* Motorola RCE */
#define EM_ARM 40 /* Advanced Risc Machines ARM */
#define EM_ALPHA 41 /* Digital Alpha */
#define EM_SH 42 /* Hitachi SH */
#define EM_SPARCV9 43 /* SPARC Version 9 */
#define EM_TRICORE 44 /* Siemens TriCore embedded processor */
#define EM_ARC 45 /* Argonaut RISC Core */
#define EM_H8_300 46 /* Hitachi H8/300 */
#define EM_H8_300H 47 /* Hitachi H8/300H */
#define EM_H8S 48 /* Hitachi H8S */
#define EM_H8_500 49 /* Hitachi H8/500 */
#define EM_IA_64 50 /* Intel Merced */
#define EM_MIPS_X 51 /* Stanford MIPS-X */
#define EM_COLDFIRE 52 /* Motorola Coldfire */
#define EM_68HC12 53 /* Motorola M68HC12 */
#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/
#define EM_PCP 55 /* Siemens PCP */
#define EM_NCPU 56 /* Sony nCPU embeeded RISC */
#define EM_NDR1 57 /* Denso NDR1 microprocessor */
#define EM_STARCORE 58 /* Motorola Start*Core processor */
#define EM_ME16 59 /* Toyota ME16 processor */
#define EM_ST100 60 /* STMicroelectronic ST100 processor */
#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/
#define EM_X86_64 62 /* AMD x86-64 */
#define EM_PDSP 63 /* Sony DSP Processor */
/* RESERVED 64,65 for future use */
#define EM_FX66 66 /* Siemens FX66 microcontroller */
#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */
#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */
#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */
#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */
#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */
#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */
#define EM_SVX 73 /* Silicon Graphics SVx */
#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */
#define EM_VAX 75 /* Digital VAX */
#define EM_CHRIS 76 /* Axis Communications embedded proc. */
#define EM_JAVELIN 77 /* Infineon Technologies emb. proc. */
#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */
#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */
#define EM_MMIX 80 /* Donald Knuth's edu 64-bit proc. */
#define EM_HUANY 81 /* Harvard University mach-indep objs */
#define EM_PRISM 82 /* SiTera Prism */
#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */
#define EM_FR30 84 /* Fujitsu FR30 */
#define EM_D10V 85 /* Mitsubishi DV10V */
#define EM_D30V 86 /* Mitsubishi DV30V */
#define EM_V850 87 /* NEC v850 */
#define EM_M32R 88 /* Mitsubishi M32R */
#define EM_MN10300 89 /* Matsushita MN10200 */
#define EM_MN10200 90 /* Matsushita MN10200 */
#define EM_PJ 91 /* picoJava */
#define EM_NUM 92 /* number of machine types */
/* Version */
#define EV_NONE 0 /* Invalid */
#define EV_CURRENT 1 /* Current */
#define EV_NUM 2 /* number of versions */
/* Section Header */
typedef struct {
Elf32_Word sh_name; /* name - index into section header
string table section */
Elf32_Word sh_type; /* type */
Elf32_Word sh_flags; /* flags */
Elf32_Addr sh_addr; /* address */
Elf32_Off sh_offset; /* file offset */
Elf32_Word sh_size; /* section size */
Elf32_Word sh_link; /* section header table index link */
Elf32_Word sh_info; /* extra information */
Elf32_Word sh_addralign; /* address alignment */
Elf32_Word sh_entsize; /* section entry size */
} Elf32_Shdr;
/* Special Section Indexes */
#define SHN_UNDEF 0 /* undefined */
#define SHN_LORESERVE 0xff00 /* lower bounds of reserved indexes */
#define SHN_LOPROC 0xff00 /* reserved range for processor */
#define SHN_HIPROC 0xff1f /* specific section indexes */
#define SHN_LOOS 0xff20 /* reserved range for operating */
#define SHN_HIOS 0xff3f /* specific semantics */
#define SHN_ABS 0xfff1 /* absolute value */
#define SHN_COMMON 0xfff2 /* common symbol */
#define SHN_XINDEX 0xffff /* Index is an extra table */
#define SHN_HIRESERVE 0xffff /* upper bounds of reserved indexes */
/* sh_type */
#define SHT_NULL 0 /* inactive */
#define SHT_PROGBITS 1 /* program defined information */
#define SHT_SYMTAB 2 /* symbol table section */
#define SHT_STRTAB 3 /* string table section */
#define SHT_RELA 4 /* relocation section with addends*/
#define SHT_HASH 5 /* symbol hash table section */
#define SHT_DYNAMIC 6 /* dynamic section */
#define SHT_NOTE 7 /* note section */
#define SHT_NOBITS 8 /* no space section */
#define SHT_REL 9 /* relation section without addends */
#define SHT_SHLIB 10 /* reserved - purpose unknown */
#define SHT_DYNSYM 11 /* dynamic symbol table section */
#define SHT_INIT_ARRAY 14 /* Array of constructors */
#define SHT_FINI_ARRAY 15 /* Array of destructors */
#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */
#define SHT_GROUP 17 /* Section group */
#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */
#define SHT_NUM 19 /* number of section types */
#define SHT_LOOS 0x60000000 /* Start OS-specific */
#define SHT_HIOS 0x6fffffff /* End OS-specific */
#define SHT_LOPROC 0x70000000 /* reserved range for processor */
#define SHT_HIPROC 0x7fffffff /* specific section header types */
#define SHT_LOUSER 0x80000000 /* reserved range for application */
#define SHT_HIUSER 0xffffffff /* specific indexes */
/* Section names */
#define ELF_BSS ".bss" /* uninitialized data */
#define ELF_COMMENT ".comment" /* version control information */
#define ELF_DATA ".data" /* initialized data */
#define ELF_DATA1 ".data1" /* initialized data */
#define ELF_DEBUG ".debug" /* debug */
#define ELF_DYNAMIC ".dynamic" /* dynamic linking information */
#define ELF_DYNSTR ".dynstr" /* dynamic string table */
#define ELF_DYNSYM ".dynsym" /* dynamic symbol table */
#define ELF_FINI ".fini" /* termination code */
#define ELF_FINI_ARRAY ".fini_array" /* Array of destructors */
#define ELF_GOT ".got" /* global offset table */
#define ELF_HASH ".hash" /* symbol hash table */
#define ELF_INIT ".init" /* initialization code */
#define ELF_INIT_ARRAY ".init_array" /* Array of constuctors */
#define ELF_INTERP ".interp" /* Pathname of program interpreter */
#define ELF_LINE ".line" /* Symbolic line numnber information */
#define ELF_NOTE ".note" /* Contains note section */
#define ELF_PLT ".plt" /* Procedure linkage table */
#define ELF_PREINIT_ARRAY ".preinit_array" /* Array of pre-constructors */
#define ELF_REL_DATA ".rel.data" /* relocation data */
#define ELF_REL_FINI ".rel.fini" /* relocation termination code */
#define ELF_REL_INIT ".rel.init" /* relocation initialization code */
#define ELF_REL_DYN ".rel.dyn" /* relocaltion dynamic link info */
#define ELF_REL_RODATA ".rel.rodata" /* relocation read-only data */
#define ELF_REL_TEXT ".rel.text" /* relocation code */
#define ELF_RODATA ".rodata" /* read-only data */
#define ELF_RODATA1 ".rodata1" /* read-only data */
#define ELF_SHSTRTAB ".shstrtab" /* section header string table */
#define ELF_STRTAB ".strtab" /* string table */
#define ELF_SYMTAB ".symtab" /* symbol table */
#define ELF_SYMTAB_SHNDX ".symtab_shndx"/* symbol table section index */
#define ELF_TBSS ".tbss" /* thread local uninit data */
#define ELF_TDATA ".tdata" /* thread local init data */
#define ELF_TDATA1 ".tdata1" /* thread local init data */
#define ELF_TEXT ".text" /* code */
/* Section Attribute Flags - sh_flags */
#define SHF_WRITE 0x1 /* Writable */
#define SHF_ALLOC 0x2 /* occupies memory */
#define SHF_EXECINSTR 0x4 /* executable */
#define SHF_MERGE 0x10 /* Might be merged */
#define SHF_STRINGS 0x20 /* Contains NULL terminated strings */
#define SHF_INFO_LINK 0x40 /* sh_info contains SHT index */
#define SHF_LINK_ORDER 0x80 /* Preserve order after combining*/
#define SHF_OS_NONCONFORMING 0x100 /* Non-standard OS specific handling */
#define SHF_GROUP 0x200 /* Member of section group */
#define SHF_TLS 0x400 /* Thread local storage */
#define SHF_MASKOS 0x0ff00000 /* OS specific */
#define SHF_MASKPROC 0xf0000000 /* reserved bits for processor */
/* specific section attributes */
/* Section Group Flags */
#define GRP_COMDAT 0x1 /* COMDAT group */
#define GRP_MASKOS 0x0ff00000 /* Mask OS specific flags */
#define GRP_MASKPROC 0xf0000000 /* Mask processor specific flags */
/* Symbol Table Entry */
typedef struct elf32_sym {
Elf32_Word st_name; /* name - index into string table */
Elf32_Addr st_value; /* symbol value */
Elf32_Word st_size; /* symbol size */
unsigned char st_info; /* type and binding */
unsigned char st_other; /* 0 - no defined meaning */
Elf32_Half st_shndx; /* section header index */
} Elf32_Sym;
/* Symbol table index */
#define STN_UNDEF 0 /* undefined */
/* Extract symbol info - st_info */
#define ELF32_ST_BIND(x) ((x) >> 4)
#define ELF32_ST_TYPE(x) (((unsigned int) x) & 0xf)
#define ELF32_ST_INFO(b,t) (((b) << 4) + ((t) & 0xf))
#define ELF32_ST_VISIBILITY(x) ((x) & 0x3)
/* Symbol Binding - ELF32_ST_BIND - st_info */
#define STB_LOCAL 0 /* Local symbol */
#define STB_GLOBAL 1 /* Global symbol */
#define STB_WEAK 2 /* like global - lower precedence */
#define STB_NUM 3 /* number of symbol bindings */
#define STB_LOOS 10 /* reserved range for operating */
#define STB_HIOS 12 /* system specific symbol bindings */
#define STB_LOPROC 13 /* reserved range for processor */
#define STB_HIPROC 15 /* specific symbol bindings */
/* Symbol type - ELF32_ST_TYPE - st_info */
#define STT_NOTYPE 0 /* not specified */
#define STT_OBJECT 1 /* data object */
#define STT_FUNC 2 /* function */
#define STT_SECTION 3 /* section */
#define STT_FILE 4 /* file */
#define STT_NUM 5 /* number of symbol types */
#define STT_TLS 6 /* Thread local storage symbol */
#define STT_LOOS 10 /* reserved range for operating */
#define STT_HIOS 12 /* system specific symbol types */
#define STT_LOPROC 13 /* reserved range for processor */
#define STT_HIPROC 15 /* specific symbol types */
/* Symbol visibility - ELF32_ST_VISIBILITY - st_other */
#define STV_DEFAULT 0 /* Normal visibility rules */
#define STV_INTERNAL 1 /* Processor specific hidden class */
#define STV_HIDDEN 2 /* Symbol unavailable in other mods */
#define STV_PROTECTED 3 /* Not preemptible, not exported */
/* Relocation entry with implicit addend */
typedef struct
{
Elf32_Addr r_offset; /* offset of relocation */
Elf32_Word r_info; /* symbol table index and type */
} Elf32_Rel;
/* Relocation entry with explicit addend */
typedef struct
{
Elf32_Addr r_offset; /* offset of relocation */
Elf32_Word r_info; /* symbol table index and type */
Elf32_Sword r_addend;
} Elf32_Rela;
/* Extract relocation info - r_info */
#define ELF32_R_SYM(i) ((i) >> 8)
#define ELF32_R_TYPE(i) ((unsigned char) (i))
#define ELF32_R_INFO(s,t) (((s) << 8) + (unsigned char)(t))
/* Program Header */
typedef struct {
Elf32_Word p_type; /* segment type */
Elf32_Off p_offset; /* segment offset */
Elf32_Addr p_vaddr; /* virtual address of segment */
Elf32_Addr p_paddr; /* physical address - ignored? */
Elf32_Word p_filesz; /* number of bytes in file for seg. */
Elf32_Word p_memsz; /* number of bytes in mem. for seg. */
Elf32_Word p_flags; /* flags */
Elf32_Word p_align; /* memory alignment */
} Elf32_Phdr;
/* Segment types - p_type */
#define PT_NULL 0 /* unused */
#define PT_LOAD 1 /* loadable segment */
#define PT_DYNAMIC 2 /* dynamic linking section */
#define PT_INTERP 3 /* the RTLD */
#define PT_NOTE 4 /* auxiliary information */
#define PT_SHLIB 5 /* reserved - purpose undefined */
#define PT_PHDR 6 /* program header */
#define PT_TLS 7 /* Thread local storage template */
#define PT_NUM 8 /* Number of segment types */
#define PT_LOOS 0x60000000 /* reserved range for operating */
#define PT_HIOS 0x6fffffff /* system specific segment types */
#define PT_LOPROC 0x70000000 /* reserved range for processor */
#define PT_HIPROC 0x7fffffff /* specific segment types */
/* Segment flags - p_flags */
#define PF_X 0x1 /* Executable */
#define PF_W 0x2 /* Writable */
#define PF_R 0x4 /* Readable */
#define PF_MASKOS 0x0ff00000 /* OS specific segment flags */
#define PF_MASKPROC 0xf0000000 /* reserved bits for processor */
/* specific segment flags */
/* Dynamic structure */
typedef struct
{
Elf32_Sword d_tag; /* controls meaning of d_val */
union
{
Elf32_Word d_val; /* Multiple meanings - see d_tag */
Elf32_Addr d_ptr; /* program virtual address */
} d_un;
} Elf32_Dyn;
extern Elf32_Dyn _DYNAMIC[];
/* Dynamic Array Tags - d_tag */
#define DT_NULL 0 /* marks end of _DYNAMIC array */
#define DT_NEEDED 1 /* string table offset of needed lib */
#define DT_PLTRELSZ 2 /* size of relocation entries in PLT */
#define DT_PLTGOT 3 /* address PLT/GOT */
#define DT_HASH 4 /* address of symbol hash table */
#define DT_STRTAB 5 /* address of string table */
#define DT_SYMTAB 6 /* address of symbol table */
#define DT_RELA 7 /* address of relocation table */
#define DT_RELASZ 8 /* size of relocation table */
#define DT_RELAENT 9 /* size of relocation entry */
#define DT_STRSZ 10 /* size of string table */
#define DT_SYMENT 11 /* size of symbol table entry */
#define DT_INIT 12 /* address of initialization func. */
#define DT_FINI 13 /* address of termination function */
#define DT_SONAME 14 /* string table offset of shared obj */
#define DT_RPATH 15 /* string table offset of library
search path */
#define DT_SYMBOLIC 16 /* start sym search in shared obj. */
#define DT_REL 17 /* address of rel. tbl. w addends */
#define DT_RELSZ 18 /* size of DT_REL relocation table */
#define DT_RELENT 19 /* size of DT_REL relocation entry */
#define DT_PLTREL 20 /* PLT referenced relocation entry */
#define DT_DEBUG 21 /* bugger */
#define DT_TEXTREL 22 /* Allow rel. mod. to unwritable seg */
#define DT_JMPREL 23 /* add. of PLT's relocation entries */
#define DT_BIND_NOW 24 /* Process relocations of object */
#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */
#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */
#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */
#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */
#define DT_RUNPATH 29 /* Library search path */
#define DT_FLAGS 30 /* Flags for the object being loaded */
#define DT_ENCODING 32 /* Start of encoded range */
#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/
#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */
#define DT_NUM 34 /* Number used. */
#define DT_LOOS 0x60000000 /* reserved range for OS */
#define DT_HIOS 0x6fffffff /* specific dynamic array tags */
#define DT_LOPROC 0x70000000 /* reserved range for processor */
#define DT_HIPROC 0x7fffffff /* specific dynamic array tags */
/* Dynamic Tag Flags - d_un.d_val */
#define DF_ORIGIN 0x01 /* Object may use DF_ORIGIN */
#define DF_SYMBOLIC 0x02 /* Symbol resolutions starts here */
#define DF_TEXTREL 0x04 /* Object contains text relocations */
#define DF_BIND_NOW 0x08 /* No lazy binding for this object */
#define DF_STATIC_TLS 0x10 /* Static thread local storage */
/* Standard ELF hashing function */
unsigned long elf_hash(const unsigned char *name);
#define ELF_TARG_VER 1 /* The ver for which this code is intended */
/*
* XXX - PowerPC defines really don't belong in here,
* but we'll put them in for simplicity.
*/
/* Values for Elf32/64_Ehdr.e_flags. */
#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */
/* Cygnus local bits below */
#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/
#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib
flag */
/* PowerPC relocations defined by the ABIs */
#define R_PPC_NONE 0
#define R_PPC_ADDR32 1 /* 32bit absolute address */
#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
#define R_PPC_ADDR16 3 /* 16bit absolute address */
#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
#define R_PPC_ADDR14_BRTAKEN 8
#define R_PPC_ADDR14_BRNTAKEN 9
#define R_PPC_REL24 10 /* PC relative 26 bit */
#define R_PPC_REL14 11 /* PC relative 16 bit */
#define R_PPC_REL14_BRTAKEN 12
#define R_PPC_REL14_BRNTAKEN 13
#define R_PPC_GOT16 14
#define R_PPC_GOT16_LO 15
#define R_PPC_GOT16_HI 16
#define R_PPC_GOT16_HA 17
#define R_PPC_PLTREL24 18
#define R_PPC_COPY 19
#define R_PPC_GLOB_DAT 20
#define R_PPC_JMP_SLOT 21
#define R_PPC_RELATIVE 22
#define R_PPC_LOCAL24PC 23
#define R_PPC_UADDR32 24
#define R_PPC_UADDR16 25
#define R_PPC_REL32 26
#define R_PPC_PLT32 27
#define R_PPC_PLTREL32 28
#define R_PPC_PLT16_LO 29
#define R_PPC_PLT16_HI 30
#define R_PPC_PLT16_HA 31
#define R_PPC_SDAREL16 32
#define R_PPC_SECTOFF 33
#define R_PPC_SECTOFF_LO 34
#define R_PPC_SECTOFF_HI 35
#define R_PPC_SECTOFF_HA 36
/* Keep this the last entry. */
#define R_PPC_NUM 37
/* The remaining relocs are from the Embedded ELF ABI, and are not
in the SVR4 ELF ABI. */
#define R_PPC_EMB_NADDR32 101
#define R_PPC_EMB_NADDR16 102
#define R_PPC_EMB_NADDR16_LO 103
#define R_PPC_EMB_NADDR16_HI 104
#define R_PPC_EMB_NADDR16_HA 105
#define R_PPC_EMB_SDAI16 106
#define R_PPC_EMB_SDA2I16 107
#define R_PPC_EMB_SDA2REL 108
#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */
#define R_PPC_EMB_MRKREF 110
#define R_PPC_EMB_RELSEC16 111
#define R_PPC_EMB_RELST_LO 112
#define R_PPC_EMB_RELST_HI 113
#define R_PPC_EMB_RELST_HA 114
#define R_PPC_EMB_BIT_FLD 115
#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */
/* Diab tool relocations. */
#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */
#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */
#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */
#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */
#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */
#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */
/* This is a phony reloc to handle any old fashioned TOC16 references
that may still be in object files. */
#define R_PPC_TOC16 255
#endif /* _ELF_H */
|
1001-study-uboot
|
include/elf.h
|
C
|
gpl3
| 25,356
|
/*
* (C) Copyright 2009 mGine co.
* unsik Kim <donari75@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef MG_DISK_H_
#define MG_DISK_H_
#include <asm/types.h>
/* private driver data */
struct mg_drv_data {
/* base address of mflash */
u32 base;
/* Initialize hard reset, write protect, deep power down pins.
* Set these pins to GPIO and output high
*/
void (*mg_ctrl_pin_init) (void);
/* Set hard reset pin for given level
* level : logical level of hard reset pin (0 or 1)
*/
void (*mg_hdrst_pin) (u8 level);
};
struct mg_drv_data* mg_get_drv_data (void);
unsigned int mg_disk_init (void);
unsigned int mg_disk_read (u32 addr, u8 *buff, u32 len);
unsigned int mg_disk_write(u32 addr, u8 *buff, u32 len);
unsigned int mg_disk_write_sects(void *buff, u32 sect_num, u32 sect_cnt);
unsigned int mg_disk_read_sects(void *buff, u32 sect_num, u32 sect_cnt);
#endif /*MG_DISK_H_*/
|
1001-study-uboot
|
include/mg_disk.h
|
C
|
gpl3
| 1,664
|
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __USB_ETHER_H__
#define __USB_ETHER_H__
#include <net.h>
/*
* IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble
* and FCS/CRC (frame check sequence).
*/
#define ETH_ALEN 6 /* Octets in one ethernet addr */
#define ETH_HLEN 14 /* Total octets in header. */
#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */
#define ETH_DATA_LEN 1500 /* Max. octets in payload */
#define ETH_FRAME_LEN PKTSIZE_ALIGN /* Max. octets in frame sans FCS */
#define ETH_FCS_LEN 4 /* Octets in the FCS */
struct ueth_data {
/* eth info */
struct eth_device eth_dev; /* used with eth_register */
int phy_id; /* mii phy id */
/* usb info */
struct usb_device *pusb_dev; /* this usb_device */
unsigned char ifnum; /* interface number */
unsigned char ep_in; /* in endpoint */
unsigned char ep_out; /* out ....... */
unsigned char ep_int; /* interrupt . */
unsigned char subclass; /* as in overview */
unsigned char protocol; /* .............. */
unsigned char irqinterval; /* Intervall for IRQ Pipe */
/* private fields for each driver can go here if needed */
#ifdef CONFIG_USB_ETHER_SMSC95XX
size_t rx_urb_size; /* maximum USB URB size */
u32 mac_cr; /* MAC control register value */
int have_hwaddr; /* 1 if we have a hardware MAC address */
#endif
};
/*
* Function definitions for each USB ethernet driver go here, bracketed by
* #ifdef CONFIG_USB_ETHER_xxx...#endif
*/
#ifdef CONFIG_USB_ETHER_ASIX
void asix_eth_before_probe(void);
int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss);
int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth);
#endif
#ifdef CONFIG_USB_ETHER_SMSC95XX
void smsc95xx_eth_before_probe(void);
int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss);
int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth);
#endif
#endif /* __USB_ETHER_H__ */
|
1001-study-uboot
|
include/usb_ether.h
|
C
|
gpl3
| 2,851
|
/*
* Copyright (c) International Business Machines Corp., 2006
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
* the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* Author: Artem Bityutskiy (Битюцкий Артём)
*/
#ifndef __UBI_USER_H__
#define __UBI_USER_H__
/*
* UBI device creation (the same as MTD device attachment)
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* MTD devices may be attached using %UBI_IOCATT ioctl command of the UBI
* control device. The caller has to properly fill and pass
* &struct ubi_attach_req object - UBI will attach the MTD device specified in
* the request and return the newly created UBI device number as the ioctl
* return value.
*
* UBI device deletion (the same as MTD device detachment)
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* An UBI device maybe deleted with %UBI_IOCDET ioctl command of the UBI
* control device.
*
* UBI volume creation
* ~~~~~~~~~~~~~~~~~~~
*
* UBI volumes are created via the %UBI_IOCMKVOL IOCTL command of UBI character
* device. A &struct ubi_mkvol_req object has to be properly filled and a
* pointer to it has to be passed to the IOCTL.
*
* UBI volume deletion
* ~~~~~~~~~~~~~~~~~~~
*
* To delete a volume, the %UBI_IOCRMVOL IOCTL command of the UBI character
* device should be used. A pointer to the 32-bit volume ID hast to be passed
* to the IOCTL.
*
* UBI volume re-size
* ~~~~~~~~~~~~~~~~~~
*
* To re-size a volume, the %UBI_IOCRSVOL IOCTL command of the UBI character
* device should be used. A &struct ubi_rsvol_req object has to be properly
* filled and a pointer to it has to be passed to the IOCTL.
*
* UBI volume update
* ~~~~~~~~~~~~~~~~~
*
* Volume update should be done via the %UBI_IOCVOLUP IOCTL command of the
* corresponding UBI volume character device. A pointer to a 64-bit update
* size should be passed to the IOCTL. After this, UBI expects user to write
* this number of bytes to the volume character device. The update is finished
* when the claimed number of bytes is passed. So, the volume update sequence
* is something like:
*
* fd = open("/dev/my_volume");
* ioctl(fd, UBI_IOCVOLUP, &image_size);
* write(fd, buf, image_size);
* close(fd);
*
* Atomic eraseblock change
* ~~~~~~~~~~~~~~~~~~~~~~~~
*
* Atomic eraseblock change operation is done via the %UBI_IOCEBCH IOCTL
* command of the corresponding UBI volume character device. A pointer to
* &struct ubi_leb_change_req has to be passed to the IOCTL. Then the user is
* expected to write the requested amount of bytes. This is similar to the
* "volume update" IOCTL.
*/
/*
* When a new UBI volume or UBI device is created, users may either specify the
* volume/device number they want to create or to let UBI automatically assign
* the number using these constants.
*/
#define UBI_VOL_NUM_AUTO (-1)
#define UBI_DEV_NUM_AUTO (-1)
/* Maximum volume name length */
#define UBI_MAX_VOLUME_NAME 127
/* IOCTL commands of UBI character devices */
#define UBI_IOC_MAGIC 'o'
/* Create an UBI volume */
#define UBI_IOCMKVOL _IOW(UBI_IOC_MAGIC, 0, struct ubi_mkvol_req)
/* Remove an UBI volume */
#define UBI_IOCRMVOL _IOW(UBI_IOC_MAGIC, 1, int32_t)
/* Re-size an UBI volume */
#define UBI_IOCRSVOL _IOW(UBI_IOC_MAGIC, 2, struct ubi_rsvol_req)
/* IOCTL commands of the UBI control character device */
#define UBI_CTRL_IOC_MAGIC 'o'
/* Attach an MTD device */
#define UBI_IOCATT _IOW(UBI_CTRL_IOC_MAGIC, 64, struct ubi_attach_req)
/* Detach an MTD device */
#define UBI_IOCDET _IOW(UBI_CTRL_IOC_MAGIC, 65, int32_t)
/* IOCTL commands of UBI volume character devices */
#define UBI_VOL_IOC_MAGIC 'O'
/* Start UBI volume update */
#define UBI_IOCVOLUP _IOW(UBI_VOL_IOC_MAGIC, 0, int64_t)
/* An eraseblock erasure command, used for debugging, disabled by default */
#define UBI_IOCEBER _IOW(UBI_VOL_IOC_MAGIC, 1, int32_t)
/* An atomic eraseblock change command */
#define UBI_IOCEBCH _IOW(UBI_VOL_IOC_MAGIC, 2, int32_t)
/* Maximum MTD device name length supported by UBI */
#define MAX_UBI_MTD_NAME_LEN 127
/*
* UBI data type hint constants.
*
* UBI_LONGTERM: long-term data
* UBI_SHORTTERM: short-term data
* UBI_UNKNOWN: data persistence is unknown
*
* These constants are used when data is written to UBI volumes in order to
* help the UBI wear-leveling unit to find more appropriate physical
* eraseblocks.
*/
enum {
UBI_LONGTERM = 1,
UBI_SHORTTERM = 2,
UBI_UNKNOWN = 3,
};
/*
* UBI volume type constants.
*
* @UBI_DYNAMIC_VOLUME: dynamic volume
* @UBI_STATIC_VOLUME: static volume
*/
enum {
UBI_DYNAMIC_VOLUME = 3,
UBI_STATIC_VOLUME = 4,
};
/**
* struct ubi_attach_req - attach MTD device request.
* @ubi_num: UBI device number to create
* @mtd_num: MTD device number to attach
* @vid_hdr_offset: VID header offset (use defaults if %0)
* @padding: reserved for future, not used, has to be zeroed
*
* This data structure is used to specify MTD device UBI has to attach and the
* parameters it has to use. The number which should be assigned to the new UBI
* device is passed in @ubi_num. UBI may automatically assign the number if
* @UBI_DEV_NUM_AUTO is passed. In this case, the device number is returned in
* @ubi_num.
*
* Most applications should pass %0 in @vid_hdr_offset to make UBI use default
* offset of the VID header within physical eraseblocks. The default offset is
* the next min. I/O unit after the EC header. For example, it will be offset
* 512 in case of a 512 bytes page NAND flash with no sub-page support. Or
* it will be 512 in case of a 2KiB page NAND flash with 4 512-byte sub-pages.
*
* But in rare cases, if this optimizes things, the VID header may be placed to
* a different offset. For example, the boot-loader might do things faster if the
* VID header sits at the end of the first 2KiB NAND page with 4 sub-pages. As
* the boot-loader would not normally need to read EC headers (unless it needs
* UBI in RW mode), it might be faster to calculate ECC. This is weird example,
* but it real-life example. So, in this example, @vid_hdr_offer would be
* 2KiB-64 bytes = 1984. Note, that this position is not even 512-bytes
* aligned, which is OK, as UBI is clever enough to realize this is 4th sub-page
* of the first page and add needed padding.
*/
struct ubi_attach_req {
int32_t ubi_num;
int32_t mtd_num;
int32_t vid_hdr_offset;
uint8_t padding[12];
};
/**
* struct ubi_mkvol_req - volume description data structure used in
* volume creation requests.
* @vol_id: volume number
* @alignment: volume alignment
* @bytes: volume size in bytes
* @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
* @padding1: reserved for future, not used, has to be zeroed
* @name_len: volume name length
* @padding2: reserved for future, not used, has to be zeroed
* @name: volume name
*
* This structure is used by user-space programs when creating new volumes. The
* @used_bytes field is only necessary when creating static volumes.
*
* The @alignment field specifies the required alignment of the volume logical
* eraseblock. This means, that the size of logical eraseblocks will be aligned
* to this number, i.e.,
* (UBI device logical eraseblock size) mod (@alignment) = 0.
*
* To put it differently, the logical eraseblock of this volume may be slightly
* shortened in order to make it properly aligned. The alignment has to be
* multiple of the flash minimal input/output unit, or %1 to utilize the entire
* available space of logical eraseblocks.
*
* The @alignment field may be useful, for example, when one wants to maintain
* a block device on top of an UBI volume. In this case, it is desirable to fit
* an integer number of blocks in logical eraseblocks of this UBI volume. With
* alignment it is possible to update this volume using plane UBI volume image
* BLOBs, without caring about how to properly align them.
*/
struct ubi_mkvol_req {
int32_t vol_id;
int32_t alignment;
int64_t bytes;
int8_t vol_type;
int8_t padding1;
int16_t name_len;
int8_t padding2[4];
char name[UBI_MAX_VOLUME_NAME + 1];
} __attribute__ ((packed));
/**
* struct ubi_rsvol_req - a data structure used in volume re-size requests.
* @vol_id: ID of the volume to re-size
* @bytes: new size of the volume in bytes
*
* Re-sizing is possible for both dynamic and static volumes. But while dynamic
* volumes may be re-sized arbitrarily, static volumes cannot be made to be
* smaller then the number of bytes they bear. To arbitrarily shrink a static
* volume, it must be wiped out first (by means of volume update operation with
* zero number of bytes).
*/
struct ubi_rsvol_req {
int64_t bytes;
int32_t vol_id;
} __attribute__ ((packed));
/**
* struct ubi_leb_change_req - a data structure used in atomic logical
* eraseblock change requests.
* @lnum: logical eraseblock number to change
* @bytes: how many bytes will be written to the logical eraseblock
* @dtype: data type (%UBI_LONGTERM, %UBI_SHORTTERM, %UBI_UNKNOWN)
* @padding: reserved for future, not used, has to be zeroed
*/
struct ubi_leb_change_req {
int32_t lnum;
int32_t bytes;
uint8_t dtype;
uint8_t padding[7];
} __attribute__ ((packed));
#endif /* __UBI_USER_H__ */
|
1001-study-uboot
|
include/mtd/ubi-user.h
|
C
|
gpl3
| 9,896
|
/*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __CFI_FLASH_H__
#define __CFI_FLASH_H__
#define FLASH_CMD_CFI 0x98
#define FLASH_CMD_READ_ID 0x90
#define FLASH_CMD_RESET 0xff
#define FLASH_CMD_BLOCK_ERASE 0x20
#define FLASH_CMD_ERASE_CONFIRM 0xD0
#define FLASH_CMD_WRITE 0x40
#define FLASH_CMD_PROTECT 0x60
#define FLASH_CMD_SETUP 0x60
#define FLASH_CMD_SET_CR_CONFIRM 0x03
#define FLASH_CMD_PROTECT_SET 0x01
#define FLASH_CMD_PROTECT_CLEAR 0xD0
#define FLASH_CMD_CLEAR_STATUS 0x50
#define FLASH_CMD_READ_STATUS 0x70
#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9
#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
#define FLASH_STATUS_DONE 0x80
#define FLASH_STATUS_ESS 0x40
#define FLASH_STATUS_ECLBS 0x20
#define FLASH_STATUS_PSLBS 0x10
#define FLASH_STATUS_VPENS 0x08
#define FLASH_STATUS_PSS 0x04
#define FLASH_STATUS_DPS 0x02
#define FLASH_STATUS_R 0x01
#define FLASH_STATUS_PROTECT 0x01
#define AMD_CMD_RESET 0xF0
#define AMD_CMD_WRITE 0xA0
#define AMD_CMD_ERASE_START 0x80
#define AMD_CMD_ERASE_SECTOR 0x30
#define AMD_CMD_UNLOCK_START 0xAA
#define AMD_CMD_UNLOCK_ACK 0x55
#define AMD_CMD_WRITE_TO_BUFFER 0x25
#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
#define AMD_STATUS_TOGGLE 0x40
#define AMD_STATUS_ERROR 0x20
#define ATM_CMD_UNLOCK_SECT 0x70
#define ATM_CMD_SOFTLOCK_START 0x80
#define ATM_CMD_LOCK_SECT 0x40
#define FLASH_CONTINUATION_CODE 0x7F
#define FLASH_OFFSET_MANUFACTURER_ID 0x00
#define FLASH_OFFSET_DEVICE_ID 0x01
#define FLASH_OFFSET_DEVICE_ID2 0x0E
#define FLASH_OFFSET_DEVICE_ID3 0x0F
#define FLASH_OFFSET_CFI 0x55
#define FLASH_OFFSET_CFI_ALT 0x555
#define FLASH_OFFSET_CFI_RESP 0x10
#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
/* extended query table primary address */
#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
#define FLASH_OFFSET_WTOUT 0x1F
#define FLASH_OFFSET_WBTOUT 0x20
#define FLASH_OFFSET_ETOUT 0x21
#define FLASH_OFFSET_CETOUT 0x22
#define FLASH_OFFSET_WMAX_TOUT 0x23
#define FLASH_OFFSET_WBMAX_TOUT 0x24
#define FLASH_OFFSET_EMAX_TOUT 0x25
#define FLASH_OFFSET_CEMAX_TOUT 0x26
#define FLASH_OFFSET_SIZE 0x27
#define FLASH_OFFSET_INTERFACE 0x28
#define FLASH_OFFSET_BUFFER_SIZE 0x2A
#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
#define FLASH_OFFSET_ERASE_REGIONS 0x2D
#define FLASH_OFFSET_PROTECT 0x02
#define FLASH_OFFSET_USER_PROTECTION 0x85
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
#define CFI_CMDSET_NONE 0
#define CFI_CMDSET_INTEL_EXTENDED 1
#define CFI_CMDSET_AMD_STANDARD 2
#define CFI_CMDSET_INTEL_STANDARD 3
#define CFI_CMDSET_AMD_EXTENDED 4
#define CFI_CMDSET_MITSU_STANDARD 256
#define CFI_CMDSET_MITSU_EXTENDED 257
#define CFI_CMDSET_SST 258
#define CFI_CMDSET_INTEL_PROG_REGIONS 512
#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
# undef FLASH_CMD_RESET
# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
#endif
#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
typedef union {
unsigned char c;
unsigned short w;
unsigned long l;
unsigned long long ll;
} cfiword_t;
/* CFI standard query structure */
struct cfi_qry {
u8 qry[3];
u16 p_id;
u16 p_adr;
u16 a_id;
u16 a_adr;
u8 vcc_min;
u8 vcc_max;
u8 vpp_min;
u8 vpp_max;
u8 word_write_timeout_typ;
u8 buf_write_timeout_typ;
u8 block_erase_timeout_typ;
u8 chip_erase_timeout_typ;
u8 word_write_timeout_max;
u8 buf_write_timeout_max;
u8 block_erase_timeout_max;
u8 chip_erase_timeout_max;
u8 dev_size;
u16 interface_desc;
u16 max_buf_write_size;
u8 num_erase_regions;
u32 erase_region_info[NUM_ERASE_REGIONS];
} __attribute__((packed));
struct cfi_pri_hdr {
u8 pri[3];
u8 major_version;
u8 minor_version;
} __attribute__((packed));
#ifndef CONFIG_SYS_FLASH_BANKS_LIST
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif
/*
* CFI_MAX_FLASH_BANKS only used for flash_info struct declaration.
*
* Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined
*/
#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
#define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks)
#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT
/* board code can update this variable before CFI detection */
extern int cfi_flash_num_flash_banks;
#else
#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS
#endif
void flash_write_cmd(flash_info_t * info, flash_sect_t sect,
uint offset, u32 cmd);
#endif /* __CFI_FLASH_H__ */
|
1001-study-uboot
|
include/mtd/cfi_flash.h
|
C
|
gpl3
| 5,268
|
/*
* Copyright 2011, Marvell Semiconductor Inc.
* Lei Wen <leiwen@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Back ported to the 8xx platform (from the 8260 platform) by
* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
*/
#ifndef __SDHCI_HW_H
#define __SDHCI_HW_H
#include <asm/io.h>
#include <mmc.h>
/*
* Controller registers
*/
#define SDHCI_DMA_ADDRESS 0x00
#define SDHCI_BLOCK_SIZE 0x04
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
#define SDHCI_BLOCK_COUNT 0x06
#define SDHCI_ARGUMENT 0x08
#define SDHCI_TRANSFER_MODE 0x0C
#define SDHCI_TRNS_DMA 0x01
#define SDHCI_TRNS_BLK_CNT_EN 0x02
#define SDHCI_TRNS_ACMD12 0x04
#define SDHCI_TRNS_READ 0x10
#define SDHCI_TRNS_MULTI 0x20
#define SDHCI_COMMAND 0x0E
#define SDHCI_CMD_RESP_MASK 0x03
#define SDHCI_CMD_CRC 0x08
#define SDHCI_CMD_INDEX 0x10
#define SDHCI_CMD_DATA 0x20
#define SDHCI_CMD_ABORTCMD 0xC0
#define SDHCI_CMD_RESP_NONE 0x00
#define SDHCI_CMD_RESP_LONG 0x01
#define SDHCI_CMD_RESP_SHORT 0x02
#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
#define SDHCI_RESPONSE 0x10
#define SDHCI_BUFFER 0x20
#define SDHCI_PRESENT_STATE 0x24
#define SDHCI_CMD_INHIBIT 0x00000001
#define SDHCI_DATA_INHIBIT 0x00000002
#define SDHCI_DOING_WRITE 0x00000100
#define SDHCI_DOING_READ 0x00000200
#define SDHCI_SPACE_AVAILABLE 0x00000400
#define SDHCI_DATA_AVAILABLE 0x00000800
#define SDHCI_CARD_PRESENT 0x00010000
#define SDHCI_WRITE_PROTECT 0x00080000
#define SDHCI_HOST_CONTROL 0x28
#define SDHCI_CTRL_LED 0x01
#define SDHCI_CTRL_4BITBUS 0x02
#define SDHCI_CTRL_HISPD 0x04
#define SDHCI_CTRL_DMA_MASK 0x18
#define SDHCI_CTRL_SDMA 0x00
#define SDHCI_CTRL_ADMA1 0x08
#define SDHCI_CTRL_ADMA32 0x10
#define SDHCI_CTRL_ADMA64 0x18
#define SDHCI_CTRL_8BITBUS 0x20
#define SDHCI_POWER_CONTROL 0x29
#define SDHCI_POWER_ON 0x01
#define SDHCI_POWER_180 0x0A
#define SDHCI_POWER_300 0x0C
#define SDHCI_POWER_330 0x0E
#define SDHCI_BLOCK_GAP_CONTROL 0x2A
#define SDHCI_WAKE_UP_CONTROL 0x2B
#define SDHCI_WAKE_ON_INT 0x01
#define SDHCI_WAKE_ON_INSERT 0x02
#define SDHCI_WAKE_ON_REMOVE 0x04
#define SDHCI_CLOCK_CONTROL 0x2C
#define SDHCI_DIVIDER_SHIFT 8
#define SDHCI_DIVIDER_HI_SHIFT 6
#define SDHCI_DIV_MASK 0xFF
#define SDHCI_DIV_MASK_LEN 8
#define SDHCI_DIV_HI_MASK 0x300
#define SDHCI_CLOCK_CARD_EN 0x0004
#define SDHCI_CLOCK_INT_STABLE 0x0002
#define SDHCI_CLOCK_INT_EN 0x0001
#define SDHCI_TIMEOUT_CONTROL 0x2E
#define SDHCI_SOFTWARE_RESET 0x2F
#define SDHCI_RESET_ALL 0x01
#define SDHCI_RESET_CMD 0x02
#define SDHCI_RESET_DATA 0x04
#define SDHCI_INT_STATUS 0x30
#define SDHCI_INT_ENABLE 0x34
#define SDHCI_SIGNAL_ENABLE 0x38
#define SDHCI_INT_RESPONSE 0x00000001
#define SDHCI_INT_DATA_END 0x00000002
#define SDHCI_INT_DMA_END 0x00000008
#define SDHCI_INT_SPACE_AVAIL 0x00000010
#define SDHCI_INT_DATA_AVAIL 0x00000020
#define SDHCI_INT_CARD_INSERT 0x00000040
#define SDHCI_INT_CARD_REMOVE 0x00000080
#define SDHCI_INT_CARD_INT 0x00000100
#define SDHCI_INT_ERROR 0x00008000
#define SDHCI_INT_TIMEOUT 0x00010000
#define SDHCI_INT_CRC 0x00020000
#define SDHCI_INT_END_BIT 0x00040000
#define SDHCI_INT_INDEX 0x00080000
#define SDHCI_INT_DATA_TIMEOUT 0x00100000
#define SDHCI_INT_DATA_CRC 0x00200000
#define SDHCI_INT_DATA_END_BIT 0x00400000
#define SDHCI_INT_BUS_POWER 0x00800000
#define SDHCI_INT_ACMD12ERR 0x01000000
#define SDHCI_INT_ADMA_ERROR 0x02000000
#define SDHCI_INT_NORMAL_MASK 0x00007FFF
#define SDHCI_INT_ERROR_MASK 0xFFFF8000
#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
#define SDHCI_ACMD12_ERR 0x3C
/* 3E-3F reserved */
#define SDHCI_CAPABILITIES 0x40
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
#define SDHCI_TIMEOUT_CLK_SHIFT 0
#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
#define SDHCI_CLOCK_BASE_MASK 0x00003F00
#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
#define SDHCI_CLOCK_BASE_SHIFT 8
#define SDHCI_MAX_BLOCK_MASK 0x00030000
#define SDHCI_MAX_BLOCK_SHIFT 16
#define SDHCI_CAN_DO_8BIT 0x00040000
#define SDHCI_CAN_DO_ADMA2 0x00080000
#define SDHCI_CAN_DO_ADMA1 0x00100000
#define SDHCI_CAN_DO_HISPD 0x00200000
#define SDHCI_CAN_DO_SDMA 0x00400000
#define SDHCI_CAN_VDD_330 0x01000000
#define SDHCI_CAN_VDD_300 0x02000000
#define SDHCI_CAN_VDD_180 0x04000000
#define SDHCI_CAN_64BIT 0x10000000
#define SDHCI_CAPABILITIES_1 0x44
#define SDHCI_MAX_CURRENT 0x48
/* 4C-4F reserved for more max current */
#define SDHCI_SET_ACMD12_ERROR 0x50
#define SDHCI_SET_INT_ERROR 0x52
#define SDHCI_ADMA_ERROR 0x54
/* 55-57 reserved */
#define SDHCI_ADMA_ADDRESS 0x58
/* 60-FB reserved */
#define SDHCI_SLOT_INT_STATUS 0xFC
#define SDHCI_HOST_VERSION 0xFE
#define SDHCI_VENDOR_VER_MASK 0xFF00
#define SDHCI_VENDOR_VER_SHIFT 8
#define SDHCI_SPEC_VER_MASK 0x00FF
#define SDHCI_SPEC_VER_SHIFT 0
#define SDHCI_SPEC_100 0
#define SDHCI_SPEC_200 1
#define SDHCI_SPEC_300 2
/*
* End of controller registers.
*/
#define SDHCI_MAX_DIV_SPEC_200 256
#define SDHCI_MAX_DIV_SPEC_300 2046
/*
* quirks
*/
#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
#define SDHCI_QUIRK_REG32_RW (1 << 1)
/* to make gcc happy */
struct sdhci_host;
/*
* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
*/
#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
struct sdhci_ops {
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
u32 (*read_l)(struct sdhci_host *host, int reg);
u16 (*read_w)(struct sdhci_host *host, int reg);
u8 (*read_b)(struct sdhci_host *host, int reg);
void (*write_l)(struct sdhci_host *host, u32 val, int reg);
void (*write_w)(struct sdhci_host *host, u16 val, int reg);
void (*write_b)(struct sdhci_host *host, u8 val, int reg);
#endif
};
struct sdhci_host {
char *name;
void *ioaddr;
unsigned int quirks;
unsigned int version;
unsigned int clock;
struct mmc *mmc;
const struct sdhci_ops *ops;
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
if (unlikely(host->ops->write_l))
host->ops->write_l(host, val, reg);
else
writel(val, host->ioaddr + reg);
}
static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
if (unlikely(host->ops->write_w))
host->ops->write_w(host, val, reg);
else
writew(val, host->ioaddr + reg);
}
static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
if (unlikely(host->ops->write_b))
host->ops->write_b(host, val, reg);
else
writeb(val, host->ioaddr + reg);
}
static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
if (unlikely(host->ops->read_l))
return host->ops->read_l(host, reg);
else
return readl(host->ioaddr + reg);
}
static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
if (unlikely(host->ops->read_w))
return host->ops->read_w(host, reg);
else
return readw(host->ioaddr + reg);
}
static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
if (unlikely(host->ops->read_b))
return host->ops->read_b(host, reg);
else
return readb(host->ioaddr + reg);
}
#else
static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
writel(val, host->ioaddr + reg);
}
static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
writew(val, host->ioaddr + reg);
}
static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
writeb(val, host->ioaddr + reg);
}
static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
return readl(host->ioaddr + reg);
}
static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
return readw(host->ioaddr + reg);
}
static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
return readb(host->ioaddr + reg);
}
#endif
int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
#endif /* __SDHCI_HW_H */
|
1001-study-uboot
|
include/sdhci.h
|
C
|
gpl3
| 9,093
|
/* Interface for accessing Gaisler AMBA Plug&Play Bus.
* The AHB bus can be interfaced with a simpler bus -
* the APB bus, also freely available in GRLIB at
* www.gaisler.com.
*
* (C) Copyright 2007
* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __AMBAPP_H__
#define __AMBAPP_H__
/* Default location of Plug&Play info
* normally 0xfffff000 for AHB masters
* and 0xfffff800 for AHB slaves.
* Normally no need to change this.
*/
#define LEON3_IO_AREA 0xfff00000
#define LEON3_CONF_AREA 0xff000
#define LEON3_AHB_SLAVE_CONF_AREA (1 << 11)
/* Max devices this software will support */
#define LEON3_AHB_MASTERS 16
#define LEON3_AHB_SLAVES 16
/*#define LEON3_APB_MASTERS 1*/ /* Number of APB buses that has Plug&Play */
#define LEON3_APB_SLAVES 16 /* Total number of APB slaves per APB bus */
/* Vendor codes */
#define VENDOR_GAISLER 1
#define VENDOR_PENDER 2
#define VENDOR_ESA 4
#define VENDOR_ASTRIUM 6
#define VENDOR_OPENCHIP 7
#define VENDOR_OPENCORES 8
#define VENDOR_CONTRIB 9
#define VENDOR_EONIC 11
#define VENDOR_RADIONOR 15
#define VENDOR_GLEICHMANN 16
#define VENDOR_MENTA 17
#define VENDOR_SUN 19
#define VENDOR_EMBEDDIT 234
#define VENDOR_CAL 202
/* Gaisler Research device id's */
#define GAISLER_LEON3 0x003
#define GAISLER_LEON3DSU 0x004
#define GAISLER_ETHAHB 0x005
#define GAISLER_APBMST 0x006
#define GAISLER_AHBUART 0x007
#define GAISLER_SRCTRL 0x008
#define GAISLER_SDCTRL 0x009
#define GAISLER_APBUART 0x00C
#define GAISLER_IRQMP 0x00D
#define GAISLER_AHBRAM 0x00E
#define GAISLER_GPTIMER 0x011
#define GAISLER_PCITRG 0x012
#define GAISLER_PCISBRG 0x013
#define GAISLER_PCIFBRG 0x014
#define GAISLER_PCITRACE 0x015
#define GAISLER_PCIDMA 0x016
#define GAISLER_AHBTRACE 0x017
#define GAISLER_ETHDSU 0x018
#define GAISLER_PIOPORT 0x01A
#define GAISLER_AHBJTAG 0x01c
#define GAISLER_SPW 0x01f
#define GAISLER_ATACTRL 0x024
#define GAISLER_VGA 0x061
#define GAISLER_KBD 0X060
#define GAISLER_ETHMAC 0x01D
#define GAISLER_DDRSPA 0x025
#define GAISLER_EHCI 0x026
#define GAISLER_UHCI 0x027
#define GAISLER_SPW2 0x029
#define GAISLER_DDR2SPA 0x02E
#define GAISLER_AHBSTAT 0x052
#define GAISLER_FTMCTRL 0x054
#define GAISLER_L2TIME 0xffd /* internal device: leon2 timer */
#define GAISLER_L2C 0xffe /* internal device: leon2compat */
#define GAISLER_PLUGPLAY 0xfff /* internal device: plug & play configarea */
/* European Space Agency device id's */
#define ESA_LEON2 0x2
#define ESA_MCTRL 0xF
/* Opencores device id's */
#define OPENCORES_PCIBR 0x4
#define OPENCORES_ETHMAC 0x5
/* Vendor codes */
/*
*
* Macros for manipulating Configuration registers
*
*/
#define amba_vendor(x) (((x) >> 24) & 0xff)
#define amba_device(x) (((x) >> 12) & 0xfff)
#define amba_membar_start(mbar) \
(((mbar) & 0xfff00000) & (((mbar) & 0xfff0) << 16))
#define amba_iobar_start(base, iobar) \
((base) | ((((iobar) & 0xfff00000)>>12) & (((iobar) & 0xfff0)<<4)) )
#define amba_irq(conf) ((conf) & 0xf)
#define amba_ver(conf) (((conf)>>5) & 0x1f)
#define amba_membar_type(mbar) ((mbar) & 0xf)
#define amba_membar_mask(mbar) (((mbar)>>4) & 0xfff)
#define AMBA_TYPE_APBIO 0x1
#define AMBA_TYPE_MEM 0x2
#define AMBA_TYPE_AHBIO 0x3
#define AMBA_TYPE_AHBIO_ADDR(addr) (LEON3_IO_AREA | ((addr) >> 12))
#ifndef __ASSEMBLER__
#ifdef CONFIG_CMD_AMBAPP
/* AMBA Plug&Play relocation & initialization */
int ambapp_init_reloc(void);
/* AMBA Plug&Play Name of Vendors and devices */
/* Return name of device */
char *ambapp_device_id2str(int vendor, int id);
/* Return name of vendor */
char *ambapp_vendor_id2str(int vendor);
#endif
/*
* Types and structure used for AMBA Plug & Play bus scanning
*/
/* AMBA Plug&Play AHB information layout */
typedef struct {
unsigned int conf;
unsigned int userdef[3];
unsigned int bars[4];
} ahbctrl_pp_dev;
/* Prototypes for scanning AMBA Plug&Play bus for AMBA
* i) AHB Masters
* ii) AHB Slaves
* iii) APB Slaves (APB MST is a AHB Slave)
*/
typedef struct {
unsigned char irq;
unsigned char ver;
unsigned int address;
} ambapp_apbdev;
typedef struct {
unsigned char irq;
unsigned char ver;
unsigned int userdef[3];
unsigned int address[4];
} ambapp_ahbdev;
/* AMBA Plug&Play AHB Masters & Slaves information locations
* Max devices is 64 supported by HW, however often only 8
* are used.
*/
typedef struct {
ahbctrl_pp_dev masters[64];
ahbctrl_pp_dev slaves[64];
} ahbctrl_info;
/* AMBA Plug&Play AHB information layout */
typedef struct {
unsigned int conf;
unsigned int bar;
} apbctrl_pp_dev;
/* All functions return the number of found devices
* 0 = no devices found
*/
/****************************** APB SLAVES ******************************/
int ambapp_apb_count(unsigned int vendor, unsigned int driver);
int ambapp_apb_first(unsigned int vendor,
unsigned int driver, ambapp_apbdev * dev);
int ambapp_apb_next(unsigned int vendor,
unsigned int driver, ambapp_apbdev * dev, int index);
int ambapp_apbs_first(unsigned int vendor,
unsigned int driver, ambapp_apbdev * dev, int max_cnt);
/****************************** AHB MASTERS ******************************/
int ambapp_ahbmst_count(unsigned int vendor, unsigned int driver);
int ambapp_ahbmst_first(unsigned int vendor,
unsigned int driver, ambapp_ahbdev * dev);
int ambapp_ahbmst_next(unsigned int vendor,
unsigned int driver, ambapp_ahbdev * dev, int index);
int ambapp_ahbmsts_first(unsigned int vendor,
unsigned int driver, ambapp_ahbdev * dev, int max_cnt);
/****************************** AHB SLAVES ******************************/
int ambapp_ahbslv_count(unsigned int vendor, unsigned int driver);
int ambapp_ahbslv_first(unsigned int vendor,
unsigned int driver, ambapp_ahbdev * dev);
int ambapp_ahbslv_next(unsigned int vendor,
unsigned int driver, ambapp_ahbdev * dev, int index);
int ambapp_ahbslvs_first(unsigned int vendor,
unsigned int driver, ambapp_ahbdev * dev, int max_cnt);
/*************************** AHB/APB only regs functions *************************
* During start up, no memory is available we can use the simplified functions
* to get to the memory controller.
*
* Functions uses no stack/memory, only registers.
*/
unsigned int ambapp_apb_next_nomem(register unsigned int vendor, /* Plug&Play Vendor ID */
register unsigned int driver, /* Plug&Play Device ID */
register int index);
ahbctrl_pp_dev *ambapp_ahb_next_nomem(register unsigned int vendor, /* Plug&Play Vendor ID */
register unsigned int driver, /* Plug&Play Device ID */
register unsigned int opts, /* scan for AHB 1=slave, 0=masters */
register int index);
unsigned int ambapp_ahb_get_info(ahbctrl_pp_dev * ahb, int info);
/*************************** AMBA Plug&Play device register MAPS *****************/
/*
* The following defines the bits in the LEON UART Status Registers.
*/
#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
/*
* The following defines the bits in the LEON UART Ctrl Registers.
*/
#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */
#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */
#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */
#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */
#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */
#define LEON_REG_UART_CTRL_DBG (1<<11) /* Debug Bit used by GRMON */
#define LEON3_GPTIMER_EN 1
#define LEON3_GPTIMER_RL 2
#define LEON3_GPTIMER_LD 4
#define LEON3_GPTIMER_IRQEN 8
/*
* The following defines the bits in the LEON PS/2 Status Registers.
*/
#define LEON_REG_PS2_STATUS_DR 0x00000001 /* Data Ready */
#define LEON_REG_PS2_STATUS_PE 0x00000002 /* Parity error */
#define LEON_REG_PS2_STATUS_FE 0x00000004 /* Framing error */
#define LEON_REG_PS2_STATUS_KI 0x00000008 /* Keyboard inhibit */
/*
* The following defines the bits in the LEON PS/2 Ctrl Registers.
*/
#define LEON_REG_PS2_CTRL_RE 0x00000001 /* Receiver enable */
#define LEON_REG_PS2_CTRL_TE 0x00000002 /* Transmitter enable */
#define LEON_REG_PS2_CTRL_RI 0x00000004 /* Keyboard receive interrupt */
#define LEON_REG_PS2_CTRL_TI 0x00000008 /* Keyboard transmit interrupt */
typedef struct {
volatile unsigned int ilevel;
volatile unsigned int ipend;
volatile unsigned int iforce;
volatile unsigned int iclear;
volatile unsigned int mstatus;
volatile unsigned int notused[11];
volatile unsigned int cpu_mask[16];
volatile unsigned int cpu_force[16];
} ambapp_dev_irqmp;
typedef struct {
volatile unsigned int data;
volatile unsigned int status;
volatile unsigned int ctrl;
volatile unsigned int scaler;
} ambapp_dev_apbuart;
typedef struct {
volatile unsigned int val;
volatile unsigned int rld;
volatile unsigned int ctrl;
volatile unsigned int unused;
} ambapp_dev_gptimer_element;
#define LEON3_GPTIMER_CTRL_EN 0x1 /* Timer enable */
#define LEON3_GPTIMER_CTRL_RS 0x2 /* Timer reStart */
#define LEON3_GPTIMER_CTRL_LD 0x4 /* Timer reLoad */
#define LEON3_GPTIMER_CTRL_IE 0x8 /* interrupt enable */
#define LEON3_GPTIMER_CTRL_IP 0x10 /* interrupt flag/pending */
#define LEON3_GPTIMER_CTRL_CH 0x20 /* Chain with previous timer */
typedef struct {
volatile unsigned int scalar;
volatile unsigned int scalar_reload;
volatile unsigned int config;
volatile unsigned int unused;
volatile ambapp_dev_gptimer_element e[8];
} ambapp_dev_gptimer;
typedef struct {
volatile unsigned int iodata;
volatile unsigned int ioout;
volatile unsigned int iodir;
volatile unsigned int irqmask;
volatile unsigned int irqpol;
volatile unsigned int irqedge;
} ambapp_dev_ioport;
typedef struct {
volatile unsigned int write;
volatile unsigned int dummy;
volatile unsigned int txcolor;
volatile unsigned int bgcolor;
} ambapp_dev_textvga;
typedef struct {
volatile unsigned int data;
volatile unsigned int status;
volatile unsigned int ctrl;
} ambapp_dev_apbps2;
typedef struct {
unsigned int mcfg1, mcfg2, mcfg3;
} ambapp_dev_mctrl;
typedef struct {
unsigned int sdcfg;
} ambapp_dev_sdctrl;
typedef struct {
unsigned int cfg1;
unsigned int cfg2;
unsigned int cfg3;
} ambapp_dev_ddr2spa;
typedef struct {
unsigned int ctrl;
unsigned int cfg;
} ambapp_dev_ddrspa;
#endif
#endif
|
1001-study-uboot
|
include/ambapp.h
|
C
|
gpl3
| 11,956
|
#ifndef _MPC8260_IRQ_H
#define _MPC8260_IRQ_H
/****************************************************************************/
/* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC */
/* source. There was no copyright information in the file. */
/*
* this is the # irq's for all ppc arch's (pmac/chrp/prep)
* so it is the max of them all
*
* [let's just worry about 8260 for now - mjj]
*/
#define NR_IRQS 64
/* The 8260 has an internal interrupt controller with a maximum of
* 64 IRQs. We will use NR_IRQs from above since it is large enough.
* Don't be confused by the 8260 documentation where they list an
* "interrupt number" and "interrupt vector". We are only interested
* in the interrupt vector. There are "reserved" holes where the
* vector number increases, but the interrupt number in the table does not.
* (Document errata updates have fixed this...make sure you have up to
* date processor documentation -- Dan).
*/
#define NR_SIU_INTS 64
/* There are many more than these, we will add them as we need them.
*/
#define SIU_INT_SMC1 ((uint)0x04)
#define SIU_INT_SMC2 ((uint)0x05)
#define SIU_INT_IRQ1 ((uint)0x13)
#define SIU_INT_IRQ2 ((uint)0x14)
#define SIU_INT_IRQ3 ((uint)0x15)
#define SIU_INT_IRQ4 ((uint)0x16)
#define SIU_INT_IRQ5 ((uint)0x17)
#define SIU_INT_IRQ6 ((uint)0x18)
#define SIU_INT_IRQ7 ((uint)0x19)
#define SIU_INT_FCC1 ((uint)0x20)
#define SIU_INT_FCC2 ((uint)0x21)
#define SIU_INT_FCC3 ((uint)0x22)
#define SIU_INT_SCC1 ((uint)0x28)
#define SIU_INT_SCC2 ((uint)0x29)
#define SIU_INT_SCC3 ((uint)0x2a)
#define SIU_INT_SCC4 ((uint)0x2b)
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
#endif /* _MPC8260_IRQ_H */
|
1001-study-uboot
|
include/mpc8260_irq.h
|
C
|
gpl3
| 1,704
|
/*
* (C) Copyright 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* Based on Linux IPU driver for MX51 (ipu.h):
*
* (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __IPU_PIXFMT_H__
#define __IPU_PIXFMT_H__
#include <linux/list.h>
#include <linux/fb.h>
/* IPU Pixel format definitions */
#define fourcc(a, b, c, d)\
(((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
/*
* Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
* the same used by V4L2 API.
*/
#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0')
#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1')
#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6')
#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8')
#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */
#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */
#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*< 32 BGR-8-8-8-8 */
#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*< 32 RGB-8-8-8-8 */
#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*< 32 RGB-8-8-8-8 */
#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*< 32 ABGR-8-8-8-8 */
/* YUV Interleaved Formats */
#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*< 16 YUV 4:2:2 */
#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*< 16 YUV 4:2:2 */
#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*< 12 YUV 4:1:1 */
#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*< 24 YUV 4:4:4 */
/* two planes -- one Y, one Cb + Cr interleaved */
#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*< 8 Greyscale */
#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*< 9 YVU 4:1:0 */
#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*< 9 YUV 4:1:0 */
#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*< 12 YVU 4:2:0 */
#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*< 12 YUV 4:2:0 */
#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*< 12 YUV 4:2:0 */
#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*< 16 YVU 4:2:2 */
#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*< 16 YUV 4:2:2 */
int mx51_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
#endif
|
1001-study-uboot
|
include/ipu_pixfmt.h
|
C
|
gpl3
| 3,667
|
/*
* (C) Copyright 2001
* Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* 74xx_7xx.h
*
* 74xx/7xx specific definitions
*/
#ifndef __MPC74XX_H__
#define __MPC74XX_H__
/*----------------------------------------------------------------
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*----------------------------------------------------------------
* l2cr values
*/
#define l2cr 1017
#define L2CR_L2E 0x80000000 /* bit 0 - enable */
#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
#define L2CR_TS 0x00040000 /* bit 13 - test support on */
#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
#ifndef __ASSEMBLY__
/* cpu ids we detect */
typedef enum __cpu_t {
CPU_740, CPU_750,
CPU_740P, CPU_750P,
CPU_745, CPU_755,
CPU_750CX, CPU_750FX, CPU_750GX,
CPU_7400,
CPU_7410,
CPU_7447A, CPU_7448,
CPU_7450, CPU_7455, CPU_7457,
CPU_UNKNOWN} cpu_t;
extern cpu_t get_cpu_type(void);
#define l1icache_enable icache_enable
void l2cache_enable(void);
void l1dcache_enable(void);
static __inline__ unsigned long get_msr (void)
{
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr;
}
static __inline__ void set_msr (unsigned long msr)
{
asm volatile("mtmsr %0" : : "r" (msr));
}
static __inline__ unsigned long get_hid0 (void)
{
unsigned long hid0;
asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
return hid0;
}
static __inline__ unsigned long get_hid1 (void)
{
unsigned long hid1;
asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
return hid1;
}
static __inline__ void set_hid0 (unsigned long hid0)
{
asm volatile("mtspr 1008, %0" : : "r" (hid0));
}
static __inline__ void set_hid1 (unsigned long hid1)
{
asm volatile("mtspr 1009, %0" : : "r" (hid1));
}
#endif /* __ASSEMBLY__ */
#endif /* __MPC74XX_H__ */
|
1001-study-uboot
|
include/74xx_7xx.h
|
C
|
gpl3
| 4,111
|