code
stringlengths 1
2.01M
| repo_name
stringlengths 3
62
| path
stringlengths 1
267
| language
stringclasses 231
values | license
stringclasses 13
values | size
int64 1
2.01M
|
|---|---|---|---|---|---|
#ifndef __SERIAL_H__
#define __SERIAL_H__
#include <post.h>
#define NAMESIZE 16
struct serial_device {
char name[NAMESIZE];
int (*init) (void);
int (*uninit) (void);
void (*setbrg) (void);
int (*getc) (void);
int (*tstc) (void);
void (*putc) (const char c);
void (*puts) (const char *s);
#if CONFIG_POST & CONFIG_SYS_POST_UART
void (*loop) (int);
#endif
struct serial_device *next;
};
extern struct serial_device serial_smc_device;
extern struct serial_device serial_scc_device;
extern struct serial_device *default_serial_console(void);
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
defined(CONFIG_405EX) || defined(CONFIG_440) || \
defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
defined(CONFIG_TEGRA2)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
#if defined(CONFIG_SYS_NS16550_SERIAL)
extern struct serial_device eserial1_device;
extern struct serial_device eserial2_device;
extern struct serial_device eserial3_device;
extern struct serial_device eserial4_device;
#endif /* CONFIG_SYS_NS16550_SERIAL */
#endif
#if defined(CONFIG_MPC512X)
extern struct serial_device serial1_device;
extern struct serial_device serial3_device;
extern struct serial_device serial4_device;
extern struct serial_device serial6_device;
#endif
#if defined(CONFIG_XILINX_UARTLITE)
extern struct serial_device uartlite_serial0_device;
extern struct serial_device uartlite_serial1_device;
extern struct serial_device uartlite_serial2_device;
extern struct serial_device uartlite_serial3_device;
#endif
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
extern struct serial_device s3c24xx_serial0_device;
extern struct serial_device s3c24xx_serial1_device;
extern struct serial_device s3c24xx_serial2_device;
#endif
#if defined(CONFIG_S5P)
extern struct serial_device s5p_serial0_device;
extern struct serial_device s5p_serial1_device;
extern struct serial_device s5p_serial2_device;
extern struct serial_device s5p_serial3_device;
#endif
#if defined(CONFIG_OMAP3_ZOOM2)
extern struct serial_device zoom2_serial_device0;
extern struct serial_device zoom2_serial_device1;
extern struct serial_device zoom2_serial_device2;
extern struct serial_device zoom2_serial_device3;
#endif
extern struct serial_device serial_ffuart_device;
extern struct serial_device serial_btuart_device;
extern struct serial_device serial_stuart_device;
#if defined(CONFIG_SYS_BFIN_UART)
extern void serial_register_bfin_uart(void);
extern struct serial_device bfin_serial0_device;
extern struct serial_device bfin_serial1_device;
extern struct serial_device bfin_serial2_device;
extern struct serial_device bfin_serial3_device;
#endif
extern void serial_register(struct serial_device *);
extern void serial_initialize(void);
extern void serial_stdio_init(void);
extern int serial_assign(const char *name);
extern void serial_reinit_all(void);
/* For usbtty */
#ifdef CONFIG_USB_TTY
extern int usbtty_getc(void);
extern void usbtty_putc(const char c);
extern void usbtty_puts(const char *str);
extern int usbtty_tstc(void);
#else
/* stubs */
#define usbtty_getc() 0
#define usbtty_putc(a)
#define usbtty_puts(a)
#define usbtty_tstc() 0
#endif /* CONFIG_USB_TTY */
#if defined(CONFIG_MPC512X) && defined(CONFIG_SERIAL_MULTI)
extern struct stdio_dev *open_port(int num, int baudrate);
extern int close_port(int num);
extern int write_port(struct stdio_dev *port, char *buf);
extern int read_port(struct stdio_dev *port, char *buf, int size);
#endif
#endif
|
1001-study-uboot
|
include/serial.h
|
C
|
gpl3
| 3,680
|
/*
* (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _VIDEO_AD7179_H_
#define _VIDEO_AD7179_H_
/*
* The video encoder data are board specific now!
*/
#if defined(CONFIG_RRVISION)
#include "../board/RRvision/video_ad7179.h"
#else
#error "Please provide a board-specific video_ad7179.h"
#endif
#endif /* _VIDEO_AD7179_H_ */
|
1001-study-uboot
|
include/video_ad7179.h
|
C
|
gpl3
| 1,140
|
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Note: Part of this code has been derived from linux
*
*/
#ifndef _USB_DEFS_H_
#define _USB_DEFS_H_
/* USB constants */
/* Device and/or Interface Class codes */
#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_DATA 10
#define USB_CLASS_VENDOR_SPEC 0xff
/* some HID sub classes */
#define USB_SUB_HID_NONE 0
#define USB_SUB_HID_BOOT 1
/* some UID Protocols */
#define USB_PROT_HID_NONE 0
#define USB_PROT_HID_KEYBOARD 1
#define USB_PROT_HID_MOUSE 2
/* Sub STORAGE Classes */
#define US_SC_RBC 1 /* Typically, flash devices */
#define US_SC_8020 2 /* CD-ROM */
#define US_SC_QIC 3 /* QIC-157 Tapes */
#define US_SC_UFI 4 /* Floppy */
#define US_SC_8070 5 /* Removable media */
#define US_SC_SCSI 6 /* Transparent */
#define US_SC_MIN US_SC_RBC
#define US_SC_MAX US_SC_SCSI
/* STORAGE Protocols */
#define US_PR_CB 1 /* Control/Bulk w/o interrupt */
#define US_PR_CBI 0 /* Control/Bulk/Interrupt */
#define US_PR_BULK 0x50 /* bulk only */
/* USB types */
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
/* USB recipients */
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
/* USB directions */
#define USB_DIR_OUT 0
#define USB_DIR_IN 0x80
/* USB device speeds */
#define USB_SPEED_FULL 0x0 /* 12Mbps */
#define USB_SPEED_LOW 0x1 /* 1.5Mbps */
#define USB_SPEED_HIGH 0x2 /* 480Mbps */
#define USB_SPEED_RESERVED 0x3
/* Descriptor types */
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_HID (USB_TYPE_CLASS | 0x01)
#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02)
#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
#define USB_DT_HUB (USB_TYPE_CLASS | 0x09)
/* Descriptor sizes per descriptor type */
#define USB_DT_DEVICE_SIZE 18
#define USB_DT_CONFIG_SIZE 9
#define USB_DT_INTERFACE_SIZE 9
#define USB_DT_ENDPOINT_SIZE 7
#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */
#define USB_DT_HUB_NONVAR_SIZE 7
#define USB_DT_HID_SIZE 9
/* Endpoints */
#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
#define USB_ENDPOINT_DIR_MASK 0x80
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
/* USB Packet IDs (PIDs) */
#define USB_PID_UNDEF_0 0xf0
#define USB_PID_OUT 0xe1
#define USB_PID_ACK 0xd2
#define USB_PID_DATA0 0xc3
#define USB_PID_UNDEF_4 0xb4
#define USB_PID_SOF 0xa5
#define USB_PID_UNDEF_6 0x96
#define USB_PID_UNDEF_7 0x87
#define USB_PID_UNDEF_8 0x78
#define USB_PID_IN 0x69
#define USB_PID_NAK 0x5a
#define USB_PID_DATA1 0x4b
#define USB_PID_PREAMBLE 0x3c
#define USB_PID_SETUP 0x2d
#define USB_PID_STALL 0x1e
#define USB_PID_UNDEF_F 0x0f
/* Standard requests */
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
/* HID requests */
#define USB_REQ_GET_REPORT 0x01
#define USB_REQ_GET_IDLE 0x02
#define USB_REQ_GET_PROTOCOL 0x03
#define USB_REQ_SET_REPORT 0x09
#define USB_REQ_SET_IDLE 0x0A
#define USB_REQ_SET_PROTOCOL 0x0B
/* "pipe" definitions */
#define PIPE_ISOCHRONOUS 0
#define PIPE_INTERRUPT 1
#define PIPE_CONTROL 2
#define PIPE_BULK 3
#define PIPE_DEVEP_MASK 0x0007ff00
#define USB_ISOCHRONOUS 0
#define USB_INTERRUPT 1
#define USB_CONTROL 2
#define USB_BULK 3
/* USB-status codes: */
#define USB_ST_ACTIVE 0x1 /* TD is active */
#define USB_ST_STALLED 0x2 /* TD is stalled */
#define USB_ST_BUF_ERR 0x4 /* buffer error */
#define USB_ST_BABBLE_DET 0x8 /* Babble detected */
#define USB_ST_NAK_REC 0x10 /* NAK Received*/
#define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */
#define USB_ST_BIT_ERR 0x40 /* Bitstuff error */
#define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */
/*************************************************************************
* Hub defines
*/
/*
* Hub request types
*/
#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
/*
* Hub Class feature numbers
*/
#define C_HUB_LOCAL_POWER 0
#define C_HUB_OVER_CURRENT 1
/*
* Port feature numbers
*/
#define USB_PORT_FEAT_CONNECTION 0
#define USB_PORT_FEAT_ENABLE 1
#define USB_PORT_FEAT_SUSPEND 2
#define USB_PORT_FEAT_OVER_CURRENT 3
#define USB_PORT_FEAT_RESET 4
#define USB_PORT_FEAT_POWER 8
#define USB_PORT_FEAT_LOWSPEED 9
#define USB_PORT_FEAT_HIGHSPEED 10
#define USB_PORT_FEAT_C_CONNECTION 16
#define USB_PORT_FEAT_C_ENABLE 17
#define USB_PORT_FEAT_C_SUSPEND 18
#define USB_PORT_FEAT_C_OVER_CURRENT 19
#define USB_PORT_FEAT_C_RESET 20
/* wPortStatus bits */
#define USB_PORT_STAT_CONNECTION 0x0001
#define USB_PORT_STAT_ENABLE 0x0002
#define USB_PORT_STAT_SUSPEND 0x0004
#define USB_PORT_STAT_OVERCURRENT 0x0008
#define USB_PORT_STAT_RESET 0x0010
#define USB_PORT_STAT_POWER 0x0100
#define USB_PORT_STAT_LOW_SPEED 0x0200
#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */
#define USB_PORT_STAT_SPEED \
(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
/* wPortChange bits */
#define USB_PORT_STAT_C_CONNECTION 0x0001
#define USB_PORT_STAT_C_ENABLE 0x0002
#define USB_PORT_STAT_C_SUSPEND 0x0004
#define USB_PORT_STAT_C_OVERCURRENT 0x0008
#define USB_PORT_STAT_C_RESET 0x0010
/* wHubCharacteristics (masks) */
#define HUB_CHAR_LPSM 0x0003
#define HUB_CHAR_COMPOUND 0x0004
#define HUB_CHAR_OCPM 0x0018
/*
*Hub Status & Hub Change bit masks
*/
#define HUB_STATUS_LOCAL_POWER 0x0001
#define HUB_STATUS_OVERCURRENT 0x0002
#define HUB_CHANGE_LOCAL_POWER 0x0001
#define HUB_CHANGE_OVERCURRENT 0x0002
#endif /*_USB_DEFS_H_ */
|
1001-study-uboot
|
include/usb_defs.h
|
C
|
gpl3
| 8,088
|
/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _SCSI_H
#define _SCSI_H
typedef struct SCSI_cmd_block{
unsigned char cmd[16]; /* command */
unsigned char sense_buf[64]; /* for request sense */
unsigned char status; /* SCSI Status */
unsigned char target; /* Target ID */
unsigned char lun; /* Target LUN */
unsigned char cmdlen; /* command len */
unsigned long datalen; /* Total data length */
unsigned char * pdata; /* pointer to data */
unsigned char msgout[12]; /* Messge out buffer (NOT USED) */
unsigned char msgin[12]; /* Message in buffer */
unsigned char sensecmdlen; /* Sense command len */
unsigned long sensedatalen; /* Sense data len */
unsigned char sensecmd[6]; /* Sense command */
unsigned long contr_stat; /* Controller Status */
unsigned long trans_bytes; /* tranfered bytes */
unsigned int priv;
}ccb;
/*-----------------------------------------------------------
**
** SCSI constants.
**
**-----------------------------------------------------------
*/
/*
** Messages
*/
#define M_COMPLETE (0x00)
#define M_EXTENDED (0x01)
#define M_SAVE_DP (0x02)
#define M_RESTORE_DP (0x03)
#define M_DISCONNECT (0x04)
#define M_ID_ERROR (0x05)
#define M_ABORT (0x06)
#define M_REJECT (0x07)
#define M_NOOP (0x08)
#define M_PARITY (0x09)
#define M_LCOMPLETE (0x0a)
#define M_FCOMPLETE (0x0b)
#define M_RESET (0x0c)
#define M_ABORT_TAG (0x0d)
#define M_CLEAR_QUEUE (0x0e)
#define M_INIT_REC (0x0f)
#define M_REL_REC (0x10)
#define M_TERMINATE (0x11)
#define M_SIMPLE_TAG (0x20)
#define M_HEAD_TAG (0x21)
#define M_ORDERED_TAG (0x22)
#define M_IGN_RESIDUE (0x23)
#define M_IDENTIFY (0x80)
#define M_X_MODIFY_DP (0x00)
#define M_X_SYNC_REQ (0x01)
#define M_X_WIDE_REQ (0x03)
#define M_X_PPR_REQ (0x04)
/*
** Status
*/
#define S_GOOD (0x00)
#define S_CHECK_COND (0x02)
#define S_COND_MET (0x04)
#define S_BUSY (0x08)
#define S_INT (0x10)
#define S_INT_COND_MET (0x14)
#define S_CONFLICT (0x18)
#define S_TERMINATED (0x20)
#define S_QUEUE_FULL (0x28)
#define S_ILLEGAL (0xff)
#define S_SENSE (0x80)
/*
* Sense_keys
*/
#define SENSE_NO_SENSE 0x0
#define SENSE_RECOVERED_ERROR 0x1
#define SENSE_NOT_READY 0x2
#define SENSE_MEDIUM_ERROR 0x3
#define SENSE_HARDWARE_ERROR 0x4
#define SENSE_ILLEGAL_REQUEST 0x5
#define SENSE_UNIT_ATTENTION 0x6
#define SENSE_DATA_PROTECT 0x7
#define SENSE_BLANK_CHECK 0x8
#define SENSE_VENDOR_SPECIFIC 0x9
#define SENSE_COPY_ABORTED 0xA
#define SENSE_ABORTED_COMMAND 0xB
#define SENSE_VOLUME_OVERFLOW 0xD
#define SENSE_MISCOMPARE 0xE
#define SCSI_CHANGE_DEF 0x40 /* Change Definition (Optional) */
#define SCSI_COMPARE 0x39 /* Compare (O) */
#define SCSI_COPY 0x18 /* Copy (O) */
#define SCSI_COP_VERIFY 0x3A /* Copy and Verify (O) */
#define SCSI_INQUIRY 0x12 /* Inquiry (MANDATORY) */
#define SCSI_LOG_SELECT 0x4C /* Log Select (O) */
#define SCSI_LOG_SENSE 0x4D /* Log Sense (O) */
#define SCSI_MODE_SEL6 0x15 /* Mode Select 6-byte (Device Specific) */
#define SCSI_MODE_SEL10 0x55 /* Mode Select 10-byte (Device Specific) */
#define SCSI_MODE_SEN6 0x1A /* Mode Sense 6-byte (Device Specific) */
#define SCSI_MODE_SEN10 0x5A /* Mode Sense 10-byte (Device Specific) */
#define SCSI_READ_BUFF 0x3C /* Read Buffer (O) */
#define SCSI_REQ_SENSE 0x03 /* Request Sense (MANDATORY) */
#define SCSI_SEND_DIAG 0x1D /* Send Diagnostic (O) */
#define SCSI_TST_U_RDY 0x00 /* Test Unit Ready (MANDATORY) */
#define SCSI_WRITE_BUFF 0x3B /* Write Buffer (O) */
/***************************************************************************
* %%% Commands Unique to Direct Access Devices %%%
***************************************************************************/
#define SCSI_COMPARE 0x39 /* Compare (O) */
#define SCSI_FORMAT 0x04 /* Format Unit (MANDATORY) */
#define SCSI_LCK_UN_CAC 0x36 /* Lock Unlock Cache (O) */
#define SCSI_PREFETCH 0x34 /* Prefetch (O) */
#define SCSI_MED_REMOVL 0x1E /* Prevent/Allow medium Removal (O) */
#define SCSI_READ6 0x08 /* Read 6-byte (MANDATORY) */
#define SCSI_READ10 0x28 /* Read 10-byte (MANDATORY) */
#define SCSI_RD_CAPAC 0x25 /* Read Capacity (MANDATORY) */
#define SCSI_RD_DEFECT 0x37 /* Read Defect Data (O) */
#define SCSI_READ_LONG 0x3E /* Read Long (O) */
#define SCSI_REASS_BLK 0x07 /* Reassign Blocks (O) */
#define SCSI_RCV_DIAG 0x1C /* Receive Diagnostic Results (O) */
#define SCSI_RELEASE 0x17 /* Release Unit (MANDATORY) */
#define SCSI_REZERO 0x01 /* Rezero Unit (O) */
#define SCSI_SRCH_DAT_E 0x31 /* Search Data Equal (O) */
#define SCSI_SRCH_DAT_H 0x30 /* Search Data High (O) */
#define SCSI_SRCH_DAT_L 0x32 /* Search Data Low (O) */
#define SCSI_SEEK6 0x0B /* Seek 6-Byte (O) */
#define SCSI_SEEK10 0x2B /* Seek 10-Byte (O) */
#define SCSI_SEND_DIAG 0x1D /* Send Diagnostics (MANDATORY) */
#define SCSI_SET_LIMIT 0x33 /* Set Limits (O) */
#define SCSI_START_STP 0x1B /* Start/Stop Unit (O) */
#define SCSI_SYNC_CACHE 0x35 /* Synchronize Cache (O) */
#define SCSI_VERIFY 0x2F /* Verify (O) */
#define SCSI_WRITE6 0x0A /* Write 6-Byte (MANDATORY) */
#define SCSI_WRITE10 0x2A /* Write 10-Byte (MANDATORY) */
#define SCSI_WRT_VERIFY 0x2E /* Write and Verify (O) */
#define SCSI_WRITE_LONG 0x3F /* Write Long (O) */
#define SCSI_WRITE_SAME 0x41 /* Write Same (O) */
/****************************************************************************
* decleration of functions which have to reside in the LowLevel Part Driver
*/
void scsi_print_error(ccb *pccb);
int scsi_exec(ccb *pccb);
void scsi_bus_reset(void);
void scsi_low_level_init(int busdevfunc);
/***************************************************************************
* functions residing inside cmd_scsi.c
*/
void scsi_init(void);
void scsi_scan(int mode);
#define SCSI_IDENTIFY 0xC0 /* not used */
/* Hardware errors */
#define SCSI_SEL_TIME_OUT 0x00000101 /* Selection time out */
#define SCSI_HNS_TIME_OUT 0x00000102 /* Handshake */
#define SCSI_MA_TIME_OUT 0x00000103 /* Phase error */
#define SCSI_UNEXP_DIS 0x00000104 /* unexpected disconnect */
#define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif /* _SCSI_H */
|
1001-study-uboot
|
include/scsi.h
|
C
|
gpl3
| 7,147
|
/*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FSL_PMIC_H__
#define __FSL_PMIC_H__
/*
* The registers of different PMIC has the same meaning
* but the bit positions of the fields can differ or
* some fields has a meaning only on some devices.
* You have to check with the internal SPI bitmap
* (see Freescale Documentation) to set the registers
* for the device you are using
*/
enum {
REG_INT_STATUS0 = 0,
REG_INT_MASK0,
REG_INT_SENSE0,
REG_INT_STATUS1,
REG_INT_MASK1,
REG_INT_SENSE1,
REG_PU_MODE_S,
REG_IDENTIFICATION,
REG_UNUSED0,
REG_ACC0,
REG_ACC1, /*10 */
REG_UNUSED1,
REG_UNUSED2,
REG_POWER_CTL0,
REG_POWER_CTL1,
REG_POWER_CTL2,
REG_REGEN_ASSIGN,
REG_UNUSED3,
REG_MEM_A,
REG_MEM_B,
REG_RTC_TIME, /*20 */
REG_RTC_ALARM,
REG_RTC_DAY,
REG_RTC_DAY_ALARM,
REG_SW_0,
REG_SW_1,
REG_SW_2,
REG_SW_3,
REG_SW_4,
REG_SW_5,
REG_SETTING_0, /*30 */
REG_SETTING_1,
REG_MODE_0,
REG_MODE_1,
REG_POWER_MISC,
REG_UNUSED4,
REG_UNUSED5,
REG_UNUSED6,
REG_UNUSED7,
REG_UNUSED8,
REG_UNUSED9, /*40 */
REG_UNUSED10,
REG_UNUSED11,
REG_ADC0,
REG_ADC1,
REG_ADC2,
REG_ADC3,
REG_ADC4,
REG_CHARGE,
REG_USB0,
REG_USB1, /*50 */
REG_LED_CTL0,
REG_LED_CTL1,
REG_LED_CTL2,
REG_LED_CTL3,
REG_UNUSED12,
REG_UNUSED13,
REG_TRIM0,
REG_TRIM1,
REG_TEST0,
REG_TEST1, /*60 */
REG_TEST2,
REG_TEST3,
REG_TEST4,
PMIC_NUM_OF_REGS,
};
/* REG_POWER_MISC */
#define GPO1EN (1 << 6)
#define GPO1STBY (1 << 7)
#define GPO2EN (1 << 8)
#define GPO2STBY (1 << 9)
#define GPO3EN (1 << 10)
#define GPO3STBY (1 << 11)
#define GPO4EN (1 << 12)
#define GPO4STBY (1 << 13)
#define PWGT1SPIEN (1 << 15)
#define PWGT2SPIEN (1 << 16)
#define PWUP (1 << 21)
/* Power Control 0 */
#define COINCHEN (1 << 23)
#define BATTDETEN (1 << 19)
/* Interrupt status 1 */
#define RTCRSTI (1 << 7)
#endif
|
1001-study-uboot
|
include/fsl_pmic.h
|
C
|
gpl3
| 2,723
|
/*
* Copyright 2008,2010 Freescale Semiconductor, Inc
* Andy Fleming
*
* Based (loosely) on the Linux code
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MMC_H_
#define _MMC_H_
#include <linux/list.h>
#define SD_VERSION_SD 0x20000
#define SD_VERSION_2 (SD_VERSION_SD | 0x20)
#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10)
#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a)
#define MMC_VERSION_MMC 0x10000
#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12)
#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14)
#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22)
#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
#define MMC_MODE_HS 0x001
#define MMC_MODE_HS_52MHz 0x010
#define MMC_MODE_4BIT 0x100
#define MMC_MODE_8BIT 0x200
#define MMC_MODE_SPI 0x400
#define MMC_MODE_HC 0x800
#define SD_DATA_4BIT 0x00040000
#define IS_SD(x) (x->version & SD_VERSION_SD)
#define MMC_DATA_READ 1
#define MMC_DATA_WRITE 2
#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
#define UNUSABLE_ERR -17 /* Unusable Card */
#define COMM_ERR -18 /* Communications Error */
#define TIMEOUT -19
#define MMC_CMD_GO_IDLE_STATE 0
#define MMC_CMD_SEND_OP_COND 1
#define MMC_CMD_ALL_SEND_CID 2
#define MMC_CMD_SET_RELATIVE_ADDR 3
#define MMC_CMD_SET_DSR 4
#define MMC_CMD_SWITCH 6
#define MMC_CMD_SELECT_CARD 7
#define MMC_CMD_SEND_EXT_CSD 8
#define MMC_CMD_SEND_CSD 9
#define MMC_CMD_SEND_CID 10
#define MMC_CMD_STOP_TRANSMISSION 12
#define MMC_CMD_SEND_STATUS 13
#define MMC_CMD_SET_BLOCKLEN 16
#define MMC_CMD_READ_SINGLE_BLOCK 17
#define MMC_CMD_READ_MULTIPLE_BLOCK 18
#define MMC_CMD_WRITE_SINGLE_BLOCK 24
#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
#define MMC_CMD_ERASE_GROUP_START 35
#define MMC_CMD_ERASE_GROUP_END 36
#define MMC_CMD_ERASE 38
#define MMC_CMD_APP_CMD 55
#define MMC_CMD_SPI_READ_OCR 58
#define MMC_CMD_SPI_CRC_ON_OFF 59
#define SD_CMD_SEND_RELATIVE_ADDR 3
#define SD_CMD_SWITCH_FUNC 6
#define SD_CMD_SEND_IF_COND 8
#define SD_CMD_APP_SET_BUS_WIDTH 6
#define SD_CMD_ERASE_WR_BLK_START 32
#define SD_CMD_ERASE_WR_BLK_END 33
#define SD_CMD_APP_SEND_OP_COND 41
#define SD_CMD_APP_SEND_SCR 51
/* SCR definitions in different words */
#define SD_HIGHSPEED_BUSY 0x00020000
#define SD_HIGHSPEED_SUPPORTED 0x00020000
#define MMC_HS_TIMING 0x00000100
#define MMC_HS_52MHZ 0x2
#define OCR_BUSY 0x80000000
#define OCR_HCS 0x40000000
#define OCR_VOLTAGE_MASK 0x007FFF80
#define OCR_ACCESS_MODE 0x60000000
#define SECURE_ERASE 0x80000000
#define MMC_STATUS_MASK (~0x0206BF7F)
#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
#define MMC_STATUS_CURR_STATE (0xf << 9)
#define MMC_STATUS_ERROR (1 << 19)
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
addressed by index which are
1 in value field */
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
addressed by index, which are
1 in value field */
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
#define SD_SWITCH_CHECK 0
#define SD_SWITCH_SWITCH 1
/*
* EXT_CSD fields
*/
#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
#define EXT_CSD_PART_CONF 179 /* R/W */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_CARD_TYPE 196 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
/*
* EXT_CSD field definitions
*/
#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
#define EXT_CSD_CMD_SET_SECURE (1 << 1)
#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
#define R1_ILLEGAL_COMMAND (1 << 22)
#define R1_APP_CMD (1 << 5)
#define MMC_RSP_PRESENT (1 << 0)
#define MMC_RSP_136 (1 << 1) /* 136 bit response */
#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
#define MMC_RSP_NONE (0)
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
MMC_RSP_BUSY)
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
#define MMCPART_NOAVAILABLE (0xff)
#define PART_ACCESS_MASK (0x7)
#define PART_SUPPORT (0x1)
struct mmc_cid {
unsigned long psn;
unsigned short oid;
unsigned char mid;
unsigned char prv;
unsigned char mdt;
char pnm[7];
};
/*
* WARNING!
*
* This structure is used by atmel_mci.c only.
* It works for the AVR32 architecture but NOT
* for ARM/AT91 architectures.
* Its use is highly depreciated.
* After the atmel_mci.c driver for AVR32 has
* been replaced this structure will be removed.
*/
struct mmc_csd
{
u8 csd_structure:2,
spec_vers:4,
rsvd1:2;
u8 taac;
u8 nsac;
u8 tran_speed;
u16 ccc:12,
read_bl_len:4;
u64 read_bl_partial:1,
write_blk_misalign:1,
read_blk_misalign:1,
dsr_imp:1,
rsvd2:2,
c_size:12,
vdd_r_curr_min:3,
vdd_r_curr_max:3,
vdd_w_curr_min:3,
vdd_w_curr_max:3,
c_size_mult:3,
sector_size:5,
erase_grp_size:5,
wp_grp_size:5,
wp_grp_enable:1,
default_ecc:2,
r2w_factor:3,
write_bl_len:4,
write_bl_partial:1,
rsvd3:5;
u8 file_format_grp:1,
copy:1,
perm_write_protect:1,
tmp_write_protect:1,
file_format:2,
ecc:2;
u8 crc:7;
u8 one:1;
};
struct mmc_cmd {
ushort cmdidx;
uint resp_type;
uint cmdarg;
uint response[4];
uint flags;
};
struct mmc_data {
union {
char *dest;
const char *src; /* src buffers don't get written to */
};
uint flags;
uint blocks;
uint blocksize;
};
struct mmc {
struct list_head link;
char name[32];
void *priv;
uint voltages;
uint version;
uint has_init;
uint f_min;
uint f_max;
int high_capacity;
uint bus_width;
uint clock;
uint card_caps;
uint host_caps;
uint ocr;
uint scr[2];
uint csd[4];
uint cid[4];
ushort rca;
char part_config;
char part_num;
uint tran_speed;
uint read_bl_len;
uint write_bl_len;
uint erase_grp_size;
u64 capacity;
block_dev_desc_t block_dev;
int (*send_cmd)(struct mmc *mmc,
struct mmc_cmd *cmd, struct mmc_data *data);
void (*set_ios)(struct mmc *mmc);
int (*init)(struct mmc *mmc);
uint b_max;
};
int mmc_register(struct mmc *mmc);
int mmc_initialize(bd_t *bis);
int mmc_init(struct mmc *mmc);
int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
void mmc_set_clock(struct mmc *mmc, uint clock);
struct mmc *find_mmc_device(int dev_num);
int mmc_set_dev(int dev_num);
void print_mmc_devices(char separator);
int get_mmc_num(void);
int board_mmc_getcd(u8 *cd, struct mmc *mmc);
int mmc_switch_part(int dev_num, unsigned int part_num);
#ifdef CONFIG_GENERIC_MMC
int atmel_mci_init(void *regs);
#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
#else
int mmc_legacy_init(int verbose);
#endif
#endif /* _MMC_H_ */
|
1001-study-uboot
|
include/mmc.h
|
C
|
gpl3
| 9,407
|
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef __MVMFP_H
#define __MVMFP_H
/*
* Header file for MultiFunctionPin (MFP) Configururation framework
*
* Processors Supported:
* 1. Marvell ARMADA100 Processors
*
* processor to be supported should be added here
*/
/*
* MFP configuration is represented by a 32-bit unsigned integer
*/
#define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \
/* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \
/* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \
/* bit 12 - Unused */ \
/* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \
/* bit 09 - Pull State flag */ (((_pF) & 0x1) << 9) | \
/* bit 08 - Drv-strength flag */ (((_dF) & 0x1) << 8) | \
/* bit 07 - Edge-det flag */ (((_eF) & 0x1) << 7) | \
/* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \
/* bits 03..00 - Alt-fun flag */ (((_aF) & 0x1) << 3) | \
/* bits Alternate-fun select */ ((_afn) & 0x7))
/*
* to facilitate the definition, the following macros are provided
*
* offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
#define MFP_OFFSET_MASK MFP(0xffff, 0,0, 0,0, 0,0, 0,0)
#define MFP_REG(x) MFP(x, 0,0, 0,0, 0,0, 0,0)
#define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16)
#define MFP_AF_FLAG MFP(0x0000, 0,0, 0,0, 0,0, 0,1)
#define MFP_DRIVE_FLAG MFP(0x0000, 0,0, 0,1, 0,0, 0,0)
#define MFP_EDGE_FLAG MFP(0x0000, 0,0, 0,0, 0,1, 0,0)
#define MFP_PULL_FLAG MFP(0x0000, 0,1, 0,0, 0,0, 0,0)
#define MFP_AF0 MFP(0x0000, 0,0, 0,0, 0,0, 0,1)
#define MFP_AF1 MFP(0x0000, 0,0, 0,0, 0,0, 1,1)
#define MFP_AF2 MFP(0x0000, 0,0, 0,0, 0,0, 2,1)
#define MFP_AF3 MFP(0x0000, 0,0, 0,0, 0,0, 3,1)
#define MFP_AF4 MFP(0x0000, 0,0, 0,0, 0,0, 4,1)
#define MFP_AF5 MFP(0x0000, 0,0, 0,0, 0,0, 5,1)
#define MFP_AF6 MFP(0x0000, 0,0, 0,0, 0,0, 6,1)
#define MFP_AF7 MFP(0x0000, 0,0, 0,0, 0,0, 7,1)
#define MFP_AF_MASK MFP(0x0000, 0,0, 0,0, 0,0, 7,0)
#define MFP_LPM_EDGE_NONE MFP(0x0000, 0,0, 0,0, 0,1, 0,0)
#define MFP_LPM_EDGE_RISE MFP(0x0000, 0,0, 0,0, 1,1, 0,0)
#define MFP_LPM_EDGE_FALL MFP(0x0000, 0,0, 0,0, 2,1, 0,0)
#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0,0, 0,0, 3,1, 0,0)
#define MFP_LPM_EDGE_MASK MFP(0x0000, 0,0, 0,0, 3,0, 0,0)
#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0,0, 0,1, 0,0, 0,0)
#define MFP_DRIVE_SLOW MFP(0x0000, 0,0, 1,1, 0,0, 0,0)
#define MFP_DRIVE_MEDIUM MFP(0x0000, 0,0, 2,1, 0,0, 0,0)
#define MFP_DRIVE_FAST MFP(0x0000, 0,0, 3,1, 0,0, 0,0)
#define MFP_DRIVE_MASK MFP(0x0000, 0,0, 3,0, 0,0, 0,0)
#define MFP_PULL_NONE MFP(0x0000, 0,1, 0,0, 0,0, 0,0)
#define MFP_PULL_LOW MFP(0x0000, 1,1, 0,0, 0,0, 0,0)
#define MFP_PULL_HIGH MFP(0x0000, 2,1, 0,0, 0,0, 0,0)
#define MFP_PULL_BOTH MFP(0x0000, 3,1, 0,0, 0,0, 0,0)
#define MFP_PULL_FLOAT MFP(0x0000, 4,1, 0,0, 0,0, 0,0)
#define MFP_PULL_MASK MFP(0x0000, 7,0, 0,0, 0,0, 0,0)
#define MFP_EOC 0xffffffff /* indicates end-of-conf */
/* Functions */
void mfp_config(u32 *mfp_cfgs);
#endif /* __MVMFP_H */
|
1001-study-uboot
|
include/mvmfp.h
|
C
|
gpl3
| 4,273
|
/*
* Copyright 2000-2002 by Hans Reiser, licensing governed by reiserfs/README
*
* GRUB -- GRand Unified Bootloader
* Copyright (C) 2000, 2001 Free Software Foundation, Inc.
*
* (C) Copyright 2003 Sysgo Real-Time Solutions, AG <www.elinos.com>
* Pavel Bartusek <pba@sysgo.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* An implementation for the ReiserFS filesystem ported from GRUB.
* Some parts of this code (mainly the structures and defines) are
* from the original reiser fs code, as found in the linux kernel.
*/
#define SECTOR_SIZE 0x200
#define SECTOR_BITS 9
/* Error codes */
typedef enum
{
ERR_NONE = 0,
ERR_BAD_FILENAME,
ERR_BAD_FILETYPE,
ERR_BAD_GZIP_DATA,
ERR_BAD_GZIP_HEADER,
ERR_BAD_PART_TABLE,
ERR_BAD_VERSION,
ERR_BELOW_1MB,
ERR_BOOT_COMMAND,
ERR_BOOT_FAILURE,
ERR_BOOT_FEATURES,
ERR_DEV_FORMAT,
ERR_DEV_VALUES,
ERR_EXEC_FORMAT,
ERR_FILELENGTH,
ERR_FILE_NOT_FOUND,
ERR_FSYS_CORRUPT,
ERR_FSYS_MOUNT,
ERR_GEOM,
ERR_NEED_LX_KERNEL,
ERR_NEED_MB_KERNEL,
ERR_NO_DISK,
ERR_NO_PART,
ERR_NUMBER_PARSING,
ERR_OUTSIDE_PART,
ERR_READ,
ERR_SYMLINK_LOOP,
ERR_UNRECOGNIZED,
ERR_WONT_FIT,
ERR_WRITE,
ERR_BAD_ARGUMENT,
ERR_UNALIGNED,
ERR_PRIVILEGED,
ERR_DEV_NEED_INIT,
ERR_NO_DISK_SPACE,
ERR_NUMBER_OVERFLOW,
MAX_ERR_NUM
} reiserfs_error_t;
extern int reiserfs_set_blk_dev(block_dev_desc_t *rbdd, int part);
extern int reiserfs_ls (char *dirname);
extern int reiserfs_open (char *filename);
extern int reiserfs_read (char *buf, unsigned len);
extern int reiserfs_mount (unsigned part_length);
|
1001-study-uboot
|
include/reiserfs.h
|
C
|
gpl3
| 2,268
|
/*
* MPC8xx Communication Processor Module.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* This file contains structures and information for the communication
* processor channels. Some CPM control and status is available
* throught the MPC8xx internal memory map. See immap.h for details.
* This file only contains what I need for the moment, not the total
* CPM capabilities. I (or someone else) will add definitions as they
* are needed. -- Dan
*
* On the MBX board, EPPC-Bug loads CPM microcode into the first 512
* bytes of the DP RAM and relocates the I2C parameter area to the
* IDMA1 space. The remaining DP RAM is available for buffer descriptors
* or other use.
*/
#ifndef __CPM_8XX__
#define __CPM_8XX__
#include <linux/config.h>
#include <asm/8xx_immap.h>
/* CPM Command register.
*/
#define CPM_CR_RST ((ushort)0x8000)
#define CPM_CR_OPCODE ((ushort)0x0f00)
#define CPM_CR_CHAN ((ushort)0x00f0)
#define CPM_CR_FLG ((ushort)0x0001)
/* Some commands (there are more...later)
*/
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
/* Channel numbers.
*/
#define CPM_CR_CH_SCC1 ((ushort)0x0000)
#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
#define CPM_CR_CH_SCC2 ((ushort)0x0004)
#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
#define CPM_CR_CH_SCC3 ((ushort)0x0008)
#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
#define CPM_CR_CH_SCC4 ((ushort)0x000c)
#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
/*
* DPRAM defines and allocation functions
*/
/* The dual ported RAM is multi-functional. Some areas can be (and are
* being) used for microcode. There is an area that can only be used
* as data ram for buffer descriptors, which is all we use right now.
* Currently the first 512 and last 256 bytes are used for microcode.
*/
#ifdef CONFIG_SYS_ALLOC_DPRAM
#define CPM_DATAONLY_BASE ((uint)0x0800)
#define CPM_DATAONLY_SIZE ((uint)0x0700)
#define CPM_DP_NOSPACE ((uint)0x7fffffff)
#else
#define CPM_SERIAL_BASE 0x0800
#define CPM_I2C_BASE 0x0820
#define CPM_SPI_BASE 0x0840
#define CPM_FEC_BASE 0x0860
#define CPM_SERIAL2_BASE 0x08E0
#define CPM_SCC_BASE 0x0900
#define CPM_POST_BASE 0x0980
#define CPM_WLKBD_BASE 0x0a00
#endif
#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
#define CPM_POST_WORD_ADDR 0x07FC
#else
#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
#endif
#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
#else
#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
#endif
#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
/* Export the base address of the communication processor registers
* and dual port ram.
*/
extern cpm8xx_t *cpmp; /* Pointer to comm processor */
/* Buffer descriptors used by many of the CPM protocols.
*/
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
/* Parameter RAM offsets.
*/
#define PROFF_SCC1 ((uint)0x0000)
#define PROFF_IIC ((uint)0x0080)
#define PROFF_SCC2 ((uint)0x0100)
#define PROFF_SPI ((uint)0x0180)
#define PROFF_SCC3 ((uint)0x0200)
#define PROFF_SMC1 ((uint)0x0280)
#define PROFF_SCC4 ((uint)0x0300)
#define PROFF_SMC2 ((uint)0x0380)
/* Define enough so I can at least use the serial port as a UART.
* The MBX uses SMC1 as the host serial port.
*/
typedef struct smc_uart {
ushort smc_rbase; /* Rx Buffer descriptor base address */
ushort smc_tbase; /* Tx Buffer descriptor base address */
u_char smc_rfcr; /* Rx function code */
u_char smc_tfcr; /* Tx function code */
ushort smc_mrblr; /* Max receive buffer length */
uint smc_rstate; /* Internal */
uint smc_idp; /* Internal */
ushort smc_rbptr; /* Internal */
ushort smc_ibc; /* Internal */
uint smc_rxtmp; /* Internal */
uint smc_tstate; /* Internal */
uint smc_tdp; /* Internal */
ushort smc_tbptr; /* Internal */
ushort smc_tbc; /* Internal */
uint smc_txtmp; /* Internal */
ushort smc_maxidl; /* Maximum idle characters */
ushort smc_tmpidl; /* Temporary idle counter */
ushort smc_brklen; /* Last received break length */
ushort smc_brkec; /* rcv'd break condition counter */
ushort smc_brkcr; /* xmt break count register */
ushort smc_rmask; /* Temporary bit mask */
u_char res1[8];
ushort smc_rpbase; /* Relocation pointer */
} smc_uart_t;
/* Function code bits.
*/
#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
/* SMC uart mode register.
*/
#define SMCMR_REN ((ushort)0x0001)
#define SMCMR_TEN ((ushort)0x0002)
#define SMCMR_DM ((ushort)0x000c)
#define SMCMR_SM_GCI ((ushort)0x0000)
#define SMCMR_SM_UART ((ushort)0x0020)
#define SMCMR_SM_TRANS ((ushort)0x0030)
#define SMCMR_SM_MASK ((ushort)0x0030)
#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
#define SMCMR_REVD SMCMR_PM_EVEN
#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
#define SMCMR_BS SMCMR_PEN
#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
/* SMC2 as Centronics parallel printer. It is half duplex, in that
* it can only receive or transmit. The parameter ram values for
* each direction are either unique or properly overlap, so we can
* include them in one structure.
*/
typedef struct smc_centronics {
ushort scent_rbase;
ushort scent_tbase;
u_char scent_cfcr;
u_char scent_smask;
ushort scent_mrblr;
uint scent_rstate;
uint scent_r_ptr;
ushort scent_rbptr;
ushort scent_r_cnt;
uint scent_rtemp;
uint scent_tstate;
uint scent_t_ptr;
ushort scent_tbptr;
ushort scent_t_cnt;
uint scent_ttemp;
ushort scent_max_sl;
ushort scent_sl_cnt;
ushort scent_character1;
ushort scent_character2;
ushort scent_character3;
ushort scent_character4;
ushort scent_character5;
ushort scent_character6;
ushort scent_character7;
ushort scent_character8;
ushort scent_rccm;
ushort scent_rccr;
} smc_cent_t;
/* Centronics Status Mask Register.
*/
#define SMC_CENT_F ((u_char)0x08)
#define SMC_CENT_PE ((u_char)0x04)
#define SMC_CENT_S ((u_char)0x02)
/* SMC Event and Mask register.
*/
#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
#define SMCM_BSY ((unsigned char)0x04)
#define SMCM_TX ((unsigned char)0x02)
#define SMCM_RX ((unsigned char)0x01)
/* Baud rate generators.
*/
#define CPM_BRG_RST ((uint)0x00020000)
#define CPM_BRG_EN ((uint)0x00010000)
#define CPM_BRG_EXTC_INT ((uint)0x00000000)
#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
#define CPM_BRG_ATB ((uint)0x00002000)
#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
#define CPM_BRG_DIV16 ((uint)0x00000001)
/* SI Clock Route Register
*/
#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
/* SCCs.
*/
#define SCC_GSMRH_IRP ((uint)0x00040000)
#define SCC_GSMRH_GDE ((uint)0x00010000)
#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
#define SCC_GSMRH_REVD ((uint)0x00002000)
#define SCC_GSMRH_TRX ((uint)0x00001000)
#define SCC_GSMRH_TTX ((uint)0x00000800)
#define SCC_GSMRH_CDP ((uint)0x00000400)
#define SCC_GSMRH_CTSP ((uint)0x00000200)
#define SCC_GSMRH_CDS ((uint)0x00000100)
#define SCC_GSMRH_CTSS ((uint)0x00000080)
#define SCC_GSMRH_TFL ((uint)0x00000040)
#define SCC_GSMRH_RFW ((uint)0x00000020)
#define SCC_GSMRH_TXSY ((uint)0x00000010)
#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
#define SCC_GSMRH_RTSM ((uint)0x00000002)
#define SCC_GSMRH_RSYN ((uint)0x00000001)
#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
#define SCC_GSMRL_TCI ((uint)0x10000000)
#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
#define SCC_GSMRL_RINV ((uint)0x02000000)
#define SCC_GSMRL_TINV ((uint)0x01000000)
#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
#define SCC_GSMRL_TEND ((uint)0x00040000)
#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
#define SCC_GSMRL_ENR ((uint)0x00000020)
#define SCC_GSMRL_ENT ((uint)0x00000010)
#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
#define SCC_TODR_TOD ((ushort)0x8000)
/* SCC Event and Mask register.
*/
#define SCCM_TXE ((unsigned char)0x10)
#define SCCM_BSY ((unsigned char)0x04)
#define SCCM_TX ((unsigned char)0x02)
#define SCCM_RX ((unsigned char)0x01)
typedef struct scc_param {
ushort scc_rbase; /* Rx Buffer descriptor base address */
ushort scc_tbase; /* Tx Buffer descriptor base address */
u_char scc_rfcr; /* Rx function code */
u_char scc_tfcr; /* Tx function code */
ushort scc_mrblr; /* Max receive buffer length */
uint scc_rstate; /* Internal */
uint scc_idp; /* Internal */
ushort scc_rbptr; /* Internal */
ushort scc_ibc; /* Internal */
uint scc_rxtmp; /* Internal */
uint scc_tstate; /* Internal */
uint scc_tdp; /* Internal */
ushort scc_tbptr; /* Internal */
ushort scc_tbc; /* Internal */
uint scc_txtmp; /* Internal */
uint scc_rcrc; /* Internal */
uint scc_tcrc; /* Internal */
} sccp_t;
/* Function code bits.
*/
#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
/* CPM Ethernet through SCCx.
*/
typedef struct scc_enet {
sccp_t sen_genscc;
uint sen_cpres; /* Preset CRC */
uint sen_cmask; /* Constant mask for CRC */
uint sen_crcec; /* CRC Error counter */
uint sen_alec; /* alignment error counter */
uint sen_disfc; /* discard frame counter */
ushort sen_pads; /* Tx short frame pad character */
ushort sen_retlim; /* Retry limit threshold */
ushort sen_retcnt; /* Retry limit counter */
ushort sen_maxflr; /* maximum frame length register */
ushort sen_minflr; /* minimum frame length register */
ushort sen_maxd1; /* maximum DMA1 length */
ushort sen_maxd2; /* maximum DMA2 length */
ushort sen_maxd; /* Rx max DMA */
ushort sen_dmacnt; /* Rx DMA counter */
ushort sen_maxb; /* Max BD byte count */
ushort sen_gaddr1; /* Group address filter */
ushort sen_gaddr2;
ushort sen_gaddr3;
ushort sen_gaddr4;
uint sen_tbuf0data0; /* Save area 0 - current frame */
uint sen_tbuf0data1; /* Save area 1 - current frame */
uint sen_tbuf0rba; /* Internal */
uint sen_tbuf0crc; /* Internal */
ushort sen_tbuf0bcnt; /* Internal */
ushort sen_paddrh; /* physical address (MSB) */
ushort sen_paddrm;
ushort sen_paddrl; /* physical address (LSB) */
ushort sen_pper; /* persistence */
ushort sen_rfbdptr; /* Rx first BD pointer */
ushort sen_tfbdptr; /* Tx first BD pointer */
ushort sen_tlbdptr; /* Tx last BD pointer */
uint sen_tbuf1data0; /* Save area 0 - current frame */
uint sen_tbuf1data1; /* Save area 1 - current frame */
uint sen_tbuf1rba; /* Internal */
uint sen_tbuf1crc; /* Internal */
ushort sen_tbuf1bcnt; /* Internal */
ushort sen_txlen; /* Tx Frame length counter */
ushort sen_iaddr1; /* Individual address filter */
ushort sen_iaddr2;
ushort sen_iaddr3;
ushort sen_iaddr4;
ushort sen_boffcnt; /* Backoff counter */
/* NOTE: Some versions of the manual have the following items
* incorrectly documented. Below is the proper order.
*/
ushort sen_taddrh; /* temp address (MSB) */
ushort sen_taddrm;
ushort sen_taddrl; /* temp address (LSB) */
} scc_enet_t;
/**********************************************************************
*
* Board specific configuration settings.
*
* Please note that we use the presence of a #define SCC_ENET and/or
* #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
**********************************************************************/
/*** ADS *************************************************************/
#if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
/* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
*/
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define SCC_ENET 0
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0100)
#define PA_ENET_RCLK ((ushort)0x0200)
#define PB_ENET_TENA ((uint)0x00001000)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000002c)
/* 68160 PHY control */
#define PC_ENET_ETHLOOP ((ushort)0x0800)
#define PC_ENET_TPFLDL ((ushort)0x0400)
#define PC_ENET_TPSQEL ((ushort)0x0200)
#endif /* MPC860ADS */
/*** AMX860 **********************************************/
#if defined(CONFIG_AMX860)
/* This ENET stuff is for the AMX860 with ethernet on SCC1.
*/
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define SCC_ENET 0
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0400)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PB_ENET_TENA ((uint)0x00001000)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000003e)
/* 68160 PHY control */
#define PB_ENET_ETHLOOP ((uint)0x00020000)
#define PB_ENET_TPFLDL ((uint)0x00010000)
#define PB_ENET_TPSQEL ((uint)0x00008000)
#define PD_ENET_ETH_EN ((ushort)0x0004)
#endif /* CONFIG_AMX860 */
/*** BSEIP **********************************************************/
#ifdef CONFIG_BSEIP
/* This ENET stuff is for the MPC823 with ethernet on SCC2.
* This is unique to the BSE ip-Engine board.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0100)
#define PA_ENET_RCLK ((ushort)0x0200)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
/* BSE uses port B and C bits for PHY control also.
*/
#define PB_BSE_POWERUP ((uint)0x00000004)
#define PB_BSE_FDXDIS ((uint)0x00008000)
#define PC_BSE_LOOPBACK ((ushort)0x0800)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002c00)
#endif /* CONFIG_BSEIP */
/*** BSEIP **********************************************************/
#ifdef CONFIG_FLAGADM
/* Enet configuration for the FLAGADM */
/* Enet on SCC2 */
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0100)
#define PA_ENET_RCLK ((ushort)0x0400)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00003400)
#endif /* CONFIG_FLAGADM */
/*** C2MON **********************************************************/
#ifdef CONFIG_C2MON
# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */
# error "Ethernet on SCC not supported on C2MON Board!"
# else /* Use FEC for Fast Ethernet */
#undef SCC_ENET
#define FEC_ENET
#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
# endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_C2MON */
/*********************************************************************/
/*** ELPT860 *********************************************************/
#ifdef CONFIG_ELPT860
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
# define PROFF_ENET PROFF_SCC1
# define CPM_CR_ENET CPM_CR_CH_SCC1
# define SCC_ENET 0
# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */
# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
# define SICR_ENET_MASK ((uint)0x000000FF)
# define SICR_ENET_CLKRT ((uint)0x00000025)
#endif /* CONFIG_ELPT860 */
/*** ESTEEM 192E **************************************************/
#ifdef CONFIG_ESTEEM192E
/* ESTEEM192E
* This ENET stuff is for the MPC850 with ethernet on SCC2. This
* is very similar to the RPX-Lite configuration.
* Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00003d00)
#define PB_ENET_LOOPBACK ((uint)0x00004000)
#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
#endif
/*** FADS823 ********************************************************/
#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
/* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
*/
#ifdef CONFIG_SCC2_ENET
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define CPMVEC_ENET CPMVEC_SCC2
#endif
#ifdef CONFIG_SCC1_ENET
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define SCC_ENET 0
#define CPMVEC_ENET CPMVEC_SCC1
#endif
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0400)
#define PA_ENET_RCLK ((ushort)0x0200)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002e00)
#endif /* CONFIG_FADS823FADS */
/*** FADS850SAR ********************************************************/
#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of
* this may be unique to the FADS850SAR configuration.
* Note TENA is on Port B.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */
#endif /* CONFIG_FADS850SAR */
/*** FADS860T********************************************************/
#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x)
/*
* This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1.
*/
#ifdef CONFIG_SCC1_ENET
#define SCC_ENET 0
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0100)
#define PA_ENET_RCLK ((ushort)0x0200)
#define PB_ENET_TENA ((uint)0x00001000)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000002c)
#endif /* CONFIG_SCC1_ETHERNET */
/*
* This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS
* with ethernet on FEC.
*/
#ifdef CONFIG_FEC_ENET
#define FEC_ENET /* Use FEC for Ethernet */
#endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_FADS && CONFIG_MPC86x */
/*** FPS850L, FPS860L ************************************************/
#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
#endif /* CONFIG_FPS850L, CONFIG_FPS860L */
/*** GEN860T **********************************************************/
#if defined(CONFIG_GEN860T)
#undef SCC_ENET
#define FEC_ENET
#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */
#endif /* CONFIG_GEN860T */
/*** GENIETV ********************************************************/
#if defined(CONFIG_GENIETV)
/* Ethernet is only on SCC2 */
#define CONFIG_SCC2_ENET
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define CPMVEC_ENET CPMVEC_SCC2
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002e00)
#endif /* CONFIG_GENIETV */
/*** HERMES-PRO ******************************************************/
/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
#ifdef CONFIG_HERMES
#define FEC_ENET /* use FEC for EThernet */
#undef SCC_ENET
#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
#endif /* CONFIG_HERMES */
/*** IAD210 **********************************************************/
/* The IAD210 uses the FEC on a MPC860P for Ethernet */
#if defined(CONFIG_IAD210)
# define FEC_ENET /* use FEC for Ethernet */
# undef SCC_ENET
# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */
# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */
# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */
# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */
# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */
# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */
# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */
# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */
# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */
# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */
# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */
# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */
# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */
# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */
#endif /* CONFIG_IAD210 */
/*** ICU862 **********************************************************/
#if defined(CONFIG_ICU862)
#ifdef CONFIG_FEC_ENET
#define FEC_ENET /* use FEC for EThernet */
#endif /* CONFIG_FEC_ETHERNET */
#endif /* CONFIG_ICU862 */
/*** IP860 **********************************************************/
#if defined(CONFIG_IP860)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define SCC_ENET 0
#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000002C)
#endif /* CONFIG_IP860 */
/*** IVMS8 **********************************************************/
/* The IVMS8 uses the FEC on a MPC860T for Ethernet */
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
#define FEC_ENET /* use FEC for EThernet */
#undef SCC_ENET
#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
#endif /* CONFIG_IVMS8, CONFIG_IVML24 */
/*** KUP4K, KUP4X ****************************************************/
/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */
#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
#define FEC_ENET /* use FEC for EThernet */
#undef SCC_ENET
#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */
#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */
#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
#endif /* CONFIG_KUP4K */
/*** LANTEC *********************************************************/
#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000FF00)
#define SICR_ENET_CLKRT ((uint)0x00002E00)
#endif /* CONFIG_LANTEC v2 */
/*** LWMON **********************************************************/
#if defined(CONFIG_LWMON)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00003E00)
#endif /* CONFIG_LWMON */
/*** NX823 ***********************************************/
#if defined(CONFIG_NX823)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002f00)
#endif /* CONFIG_NX823 */
/*** MBX ************************************************************/
#ifdef CONFIG_MBX
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use. The TCLK and RCLK seem unique
* to the MBX860 board. Any two of the four available clocks could be
* used, and the MPC860 cookbook manual has an example using different
* clock pins.
*/
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define SCC_ENET 0
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PC_ENET_TENA ((ushort)0x0001)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000003d)
#endif /* CONFIG_MBX */
/*** KM8XX *********************************************************/
/* The KM8XX Service Module uses SCC3 for Ethernet */
#ifdef CONFIG_KM8XX
#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
#define CPM_CR_ENET CPM_CR_CH_SCC3
#define SCC_ENET 2
#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */
#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */
#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */
#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */
#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */
#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */
/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to
* SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
*/
#define SICR_ENET_MASK ((uint)0x00FF0000)
#define SICR_ENET_CLKRT ((uint)0x00250000)
#endif /* CONFIG_KM8XX */
/*** MHPC ********************************************************/
#if defined(CONFIG_MHPC)
/* This ENET stuff is for the MHPC with ethernet on SCC2.
* Note TENA is on Port B.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */
#endif /* CONFIG_MHPC */
/*** NETVIA *******************************************************/
/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
#if ( defined CONFIG_SVM_SC8xx )
# ifndef CONFIG_FEC_ENET
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
/* Bits in parallel I/O port registers that have to be set/cleared
* * * * to configure the pins for SCC2 use.
* * * */
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */
#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
* * * */
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00003700)
# else /* Use FEC for Fast Ethernet */
#undef SCC_ENET
#define FEC_ENET
#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
# endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_SVM_SC8xx */
#if defined(CONFIG_NETVIA)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
#elif CONFIG_NETVIA_VERSION >= 2
# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
#endif
#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002f00)
#endif /* CONFIG_NETVIA */
/*** QS850/QS823 ***************************************************/
#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
#undef FEC_ENET /* Don't use FEC for EThernet */
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */
#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */
#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */
#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */
#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */
#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */
#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */
#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */
#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */
#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */
/* SCC2 TXCLK from CLK2
* SCC2 RXCLK from CLK4
* SCC2 Connected to NMSI */
#define SICR_ENET_MASK ((uint)0x00007F00)
#define SICR_ENET_CLKRT ((uint)0x00003D00)
#endif /* CONFIG_QS850/QS823 */
/*** QS860T ***************************************************/
#ifdef CONFIG_QS860T
#ifdef CONFIG_FEC_ENET
#define FEC_ENET /* use FEC for EThernet */
#endif /* CONFIG_FEC_ETHERNET */
/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define SCC_ENET 0
#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */
#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */
#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */
#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */
#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */
#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */
#define SICR_ENET_MASK ((uint)0x000000ff)
/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
#define SICR_ENET_CLKRT ((uint)0x0000003D)
#endif /* CONFIG_QS860T */
/*** RPXCLASSIC *****************************************************/
#ifdef CONFIG_RPXCLASSIC
#ifdef CONFIG_FEC_ENET
# define FEC_ENET /* use FEC for EThernet */
# undef SCC_ENET
#else /* ! CONFIG_FEC_ENET */
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define SCC_ENET 0
#define PA_ENET_RXD ((ushort)0x0001)
#define PA_ENET_TXD ((ushort)0x0002)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#define PB_ENET_TENA ((uint)0x00001000)
#define PC_ENET_CLSN ((ushort)0x0010)
#define PC_ENET_RENA ((ushort)0x0020)
/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x0000003d)
#endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_RPXCLASSIC */
/*** RPXLITE ********************************************************/
#ifdef CONFIG_RPXLITE
/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of
* this may be unique to the RPX-Lite configuration.
* Note TENA is on Port B.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0200)
#define PA_ENET_RCLK ((ushort)0x0800)
#if defined(CONFIG_RMU)
#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */
#else
#define PB_ENET_TENA ((uint)0x00002000)
#endif
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00003d00)
#endif /* CONFIG_RPXLITE */
/*** SM850 *********************************************************/
/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
#ifdef CONFIG_SM850
#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
#define CPM_CR_ENET CPM_CR_CH_SCC3
#define SCC_ENET 2
#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */
#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */
#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */
#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
*/
#define SICR_ENET_MASK ((uint)0x00FF0000)
#define SICR_ENET_CLKRT ((uint)0x00260000)
#endif /* CONFIG_SM850 */
/*** SPD823TS ******************************************************/
#ifdef CONFIG_SPD823TS
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */
#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002E00)
#endif /* CONFIG_SPD823TS */
/*** SXNI855T ******************************************************/
#if defined(CONFIG_SXNI855T)
#ifdef CONFIG_FEC_ENET
#define FEC_ENET /* use FEC for Ethernet */
#endif /* CONFIG_FEC_ETHERNET */
#endif /* CONFIG_SXNI855T */
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \
defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */
#define SCC_ENET 1
#endif
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
#if defined(CONFIG_R360MPI)
#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */
#endif /* CONFIG_R360MPI */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002600)
# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
#define FEC_ENET
# endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
*/
#define PROFF_ENET PROFF_SCC1
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define SCC_ENET 0
#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */
#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */
#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
*/
#define SICR_ENET_MASK ((uint)0x000000ff)
#define SICR_ENET_CLKRT ((uint)0x00000026)
# endif /* CONFIG_SCC1_ENET */
# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
#define FEC_ENET
#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
# endif /* CONFIG_FEC_ENET */
#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
/*** V37 **********************************************************/
#ifdef CONFIG_V37
/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
* this may be unique to the Marel V37 configuration.
* Note TENA is on Port B.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004)
#define PA_ENET_TXD ((ushort)0x0008)
#define PA_ENET_TCLK ((ushort)0x0400)
#define PA_ENET_RCLK ((ushort)0x0200)
#define PB_ENET_TENA ((uint)0x00002000)
#define PC_ENET_CLSN ((ushort)0x0040)
#define PC_ENET_RENA ((ushort)0x0080)
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002e00)
#endif /* CONFIG_V37 */
/*********************************************************************/
/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* SCC Mode Register (PSMR) as used by Ethernet.
*/
#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
#define BD_ENET_TX_UN ((ushort)0x0002)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
/* SCC as UART
*/
typedef struct scc_uart {
sccp_t scc_genscc;
uint scc_res1; /* Reserved */
uint scc_res2; /* Reserved */
ushort scc_maxidl; /* Maximum idle chars */
ushort scc_idlc; /* temp idle counter */
ushort scc_brkcr; /* Break count register */
ushort scc_parec; /* receive parity error counter */
ushort scc_frmec; /* receive framing error counter */
ushort scc_nosec; /* receive noise counter */
ushort scc_brkec; /* receive break condition counter */
ushort scc_brkln; /* last received break length */
ushort scc_uaddr1; /* UART address character 1 */
ushort scc_uaddr2; /* UART address character 2 */
ushort scc_rtemp; /* Temp storage */
ushort scc_toseq; /* Transmit out of sequence char */
ushort scc_char1; /* control character 1 */
ushort scc_char2; /* control character 2 */
ushort scc_char3; /* control character 3 */
ushort scc_char4; /* control character 4 */
ushort scc_char5; /* control character 5 */
ushort scc_char6; /* control character 6 */
ushort scc_char7; /* control character 7 */
ushort scc_char8; /* control character 8 */
ushort scc_rccm; /* receive control character mask */
ushort scc_rccr; /* receive control character register */
ushort scc_rlbc; /* receive last break character */
} scc_uart_t;
/* SCC Event and Mask registers when it is used as a UART.
*/
#define UART_SCCM_GLR ((ushort)0x1000)
#define UART_SCCM_GLT ((ushort)0x0800)
#define UART_SCCM_AB ((ushort)0x0200)
#define UART_SCCM_IDL ((ushort)0x0100)
#define UART_SCCM_GRA ((ushort)0x0080)
#define UART_SCCM_BRKE ((ushort)0x0040)
#define UART_SCCM_BRKS ((ushort)0x0020)
#define UART_SCCM_CCR ((ushort)0x0008)
#define UART_SCCM_BSY ((ushort)0x0004)
#define UART_SCCM_TX ((ushort)0x0002)
#define UART_SCCM_RX ((ushort)0x0001)
/* The SCC PSMR when used as a UART.
*/
#define SCU_PSMR_FLC ((ushort)0x8000)
#define SCU_PSMR_SL ((ushort)0x4000)
#define SCU_PSMR_CL ((ushort)0x3000)
#define SCU_PSMR_UM ((ushort)0x0c00)
#define SCU_PSMR_FRZ ((ushort)0x0200)
#define SCU_PSMR_RZS ((ushort)0x0100)
#define SCU_PSMR_SYN ((ushort)0x0080)
#define SCU_PSMR_DRT ((ushort)0x0040)
#define SCU_PSMR_PEN ((ushort)0x0010)
#define SCU_PSMR_RPM ((ushort)0x000c)
#define SCU_PSMR_REVP ((ushort)0x0008)
#define SCU_PSMR_TPM ((ushort)0x0003)
#define SCU_PSMR_TEVP ((ushort)0x0003)
/* CPM Transparent mode SCC.
*/
typedef struct scc_trans {
sccp_t st_genscc;
uint st_cpres; /* Preset CRC */
uint st_cmask; /* Constant mask for CRC */
} scc_trans_t;
#define BD_SCC_TX_LAST ((ushort)0x0800)
/* IIC parameter RAM.
*/
typedef struct iic {
ushort iic_rbase; /* Rx Buffer descriptor base address */
ushort iic_tbase; /* Tx Buffer descriptor base address */
u_char iic_rfcr; /* Rx function code */
u_char iic_tfcr; /* Tx function code */
ushort iic_mrblr; /* Max receive buffer length */
uint iic_rstate; /* Internal */
uint iic_rdp; /* Internal */
ushort iic_rbptr; /* Internal */
ushort iic_rbc; /* Internal */
uint iic_rxtmp; /* Internal */
uint iic_tstate; /* Internal */
uint iic_tdp; /* Internal */
ushort iic_tbptr; /* Internal */
ushort iic_tbc; /* Internal */
uint iic_txtmp; /* Internal */
uint iic_res; /* reserved */
ushort iic_rpbase; /* Relocation pointer */
ushort iic_res2; /* reserved */
} iic_t;
/* SPI parameter RAM.
*/
typedef struct spi {
ushort spi_rbase; /* Rx Buffer descriptor base address */
ushort spi_tbase; /* Tx Buffer descriptor base address */
u_char spi_rfcr; /* Rx function code */
u_char spi_tfcr; /* Tx function code */
ushort spi_mrblr; /* Max receive buffer length */
uint spi_rstate; /* Internal */
uint spi_rdp; /* Internal */
ushort spi_rbptr; /* Internal */
ushort spi_rbc; /* Internal */
uint spi_rxtmp; /* Internal */
uint spi_tstate; /* Internal */
uint spi_tdp; /* Internal */
ushort spi_tbptr; /* Internal */
ushort spi_tbc; /* Internal */
uint spi_txtmp; /* Internal */
uint spi_res;
ushort spi_rpbase; /* Relocation pointer */
ushort spi_res2;
} spi_t;
/* SPI Mode register.
*/
#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
#define SPMODE_EN ((ushort)0x0100) /* Enable */
#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
#define SPMODE_PM(x) ((x) &0xF)
/* HDLC parameter RAM.
*/
typedef struct hdlc_pram_s {
/*
* SCC parameter RAM
*/
ushort rbase; /* Rx Buffer descriptor base address */
ushort tbase; /* Tx Buffer descriptor base address */
uchar rfcr; /* Rx function code */
uchar tfcr; /* Tx function code */
ushort mrblr; /* Rx buffer length */
ulong rstate; /* Rx internal state */
ulong rptr; /* Rx internal data pointer */
ushort rbptr; /* rb BD Pointer */
ushort rcount; /* Rx internal byte count */
ulong rtemp; /* Rx temp */
ulong tstate; /* Tx internal state */
ulong tptr; /* Tx internal data pointer */
ushort tbptr; /* Tx BD pointer */
ushort tcount; /* Tx byte count */
ulong ttemp; /* Tx temp */
ulong rcrc; /* temp receive CRC */
ulong tcrc; /* temp transmit CRC */
/*
* HDLC specific parameter RAM
*/
uchar res[4]; /* reserved */
ulong c_mask; /* CRC constant */
ulong c_pres; /* CRC preset */
ushort disfc; /* discarded frame counter */
ushort crcec; /* CRC error counter */
ushort abtsc; /* abort sequence counter */
ushort nmarc; /* nonmatching address rx cnt */
ushort retrc; /* frame retransmission cnt */
ushort mflr; /* maximum frame length reg */
ushort max_cnt; /* maximum length counter */
ushort rfthr; /* received frames threshold */
ushort rfcnt; /* received frames count */
ushort hmask; /* user defined frm addr mask */
ushort haddr1; /* user defined frm address 1 */
ushort haddr2; /* user defined frm address 2 */
ushort haddr3; /* user defined frm address 3 */
ushort haddr4; /* user defined frm address 4 */
ushort tmp; /* temp */
ushort tmp_mb; /* temp */
} hdlc_pram_t;
/* CPM interrupts. There are nearly 32 interrupts generated by CPM
* channels or devices. All of these are presented to the PPC core
* as a single interrupt. The CPM interrupt handler dispatches its
* own handlers, in a similar fashion to the PPC core handler. We
* use the table as defined in the manuals (i.e. no special high
* priority and SCC1 == SCCa, etc...).
*/
#define CPMVEC_NR 32
#define CPMVEC_OFFSET 0x00010000
#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
/* CPM interrupt configuration vector.
*/
#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
#define CICR_IEN ((uint)0x00000080) /* Int. enable */
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
#endif /* __CPM_8XX__ */
|
1001-study-uboot
|
include/commproc.h
|
C
|
gpl3
| 62,472
|
#ifndef __SYSTEMACE_H
#define __SYSTEMACE_H
/*
* Copyright (c) 2004 Picture Elements, Inc.
* Stephen Williams (steve@picturel.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ident "$Id:$"
#ifdef CONFIG_SYSTEMACE
# include <part.h>
block_dev_desc_t * systemace_get_dev(int dev);
#endif /* CONFIG_SYSTEMACE */
#endif /* __SYSTEMACE_H */
|
1001-study-uboot
|
include/systemace.h
|
C
|
gpl3
| 1,087
|
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _ENVIRONMENT_H_
#define _ENVIRONMENT_H_ 1
/**************************************************************************
*
* The "environment" is stored as a list of '\0' terminated
* "name=value" strings. The end of the list is marked by a double
* '\0'. New entries are always added at the end. Deleting an entry
* shifts the remaining entries to the front. Replacing an entry is a
* combination of deleting the old value and adding the new one.
*
* The environment is preceeded by a 32 bit CRC over the data part.
*
**************************************************************************
*/
#if defined(CONFIG_ENV_IS_IN_FLASH)
# ifndef CONFIG_ENV_ADDR
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
# endif
# ifndef CONFIG_ENV_OFFSET
# define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
# endif
# if !defined(CONFIG_ENV_ADDR_REDUND) && defined(CONFIG_ENV_OFFSET_REDUND)
# define CONFIG_ENV_ADDR_REDUND \
(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET_REDUND)
# endif
# if defined(CONFIG_ENV_SECT_SIZE) || defined(CONFIG_ENV_SIZE)
# ifndef CONFIG_ENV_SECT_SIZE
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
# endif
# ifndef CONFIG_ENV_SIZE
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
# endif
# else
# error "Both CONFIG_ENV_SECT_SIZE and CONFIG_ENV_SIZE undefined"
# endif
# if defined(CONFIG_ENV_ADDR_REDUND) && !defined(CONFIG_ENV_SIZE_REDUND)
# define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
# endif
# if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \
(CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <= \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
# define ENV_IS_EMBEDDED 1
# endif
# if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND)
# define CONFIG_SYS_REDUNDAND_ENVIRONMENT 1
# endif
# ifdef CONFIG_ENV_IS_EMBEDDED
# error "do not define CONFIG_ENV_IS_EMBEDDED in your board config"
# error "it is calculated automatically for you"
# endif
#endif /* CONFIG_ENV_IS_IN_FLASH */
#if defined(CONFIG_ENV_IS_IN_NAND)
# if defined(CONFIG_ENV_OFFSET_OOB)
# ifdef CONFIG_ENV_OFFSET_REDUND
# error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB"
# error "is set"
# endif
extern unsigned long nand_env_oob_offset;
# define CONFIG_ENV_OFFSET nand_env_oob_offset
# else
# ifndef CONFIG_ENV_OFFSET
# error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND"
# endif
# ifdef CONFIG_ENV_OFFSET_REDUND
# define CONFIG_SYS_REDUNDAND_ENVIRONMENT
# endif
# endif /* CONFIG_ENV_OFFSET_OOB */
# ifndef CONFIG_ENV_SIZE
# error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND"
# endif
#endif /* CONFIG_ENV_IS_IN_NAND */
#if defined(CONFIG_ENV_IS_IN_MG_DISK)
# ifndef CONFIG_ENV_ADDR
# error "Need to define CONFIG_ENV_ADDR when using CONFIG_ENV_IS_IN_MG_DISK"
# endif
# ifndef CONFIG_ENV_SIZE
# error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_MG_DISK"
# endif
#endif /* CONFIG_ENV_IS_IN_MG_DISK */
/* Embedded env is only supported for some flash types */
#ifdef CONFIG_ENV_IS_EMBEDDED
# if !defined(CONFIG_ENV_IS_IN_FLASH) && \
!defined(CONFIG_ENV_IS_IN_NAND) && \
!defined(CONFIG_ENV_IS_IN_ONENAND) && \
!defined(CONFIG_ENV_IS_IN_SPI_FLASH)
# error "CONFIG_ENV_IS_EMBEDDED not supported for your flash type"
# endif
#endif
/*
* For the flash types where embedded env is supported, but it cannot be
* calculated automatically (i.e. NAND), take the board opt-in.
*/
#if defined(CONFIG_ENV_IS_EMBEDDED) && !defined(ENV_IS_EMBEDDED)
# define ENV_IS_EMBEDDED 1
#endif
/* The build system likes to know if the env is embedded */
#ifdef DO_DEPS_ONLY
# ifdef ENV_IS_EMBEDDED
# ifndef CONFIG_ENV_IS_EMBEDDED
# define CONFIG_ENV_IS_EMBEDDED
# endif
# endif
#endif
#include "compiler.h"
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
# define ENV_HEADER_SIZE (sizeof(uint32_t) + 1)
# define ACTIVE_FLAG 1
# define OBSOLETE_FLAG 0
#else
# define ENV_HEADER_SIZE (sizeof(uint32_t))
#endif
#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
extern char *env_name_spec;
#endif
#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
typedef struct environment_s {
uint32_t crc; /* CRC32 over data bytes */
#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
unsigned char flags; /* active/obsolete flags */
#endif
unsigned char data[ENV_SIZE]; /* Environment data */
} env_t;
#ifdef ENV_IS_EMBEDDED
extern env_t environment;
#endif /* ENV_IS_EMBEDDED */
extern const unsigned char default_environment[];
extern env_t *env_ptr;
extern void env_relocate_spec(void);
extern unsigned char env_get_char_spec(int);
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
extern void env_reloc(void);
#endif
#ifndef DO_DEPS_ONLY
#include <search.h>
extern struct hsearch_data env_htab;
/* Function that returns a character from the environment */
unsigned char env_get_char(int);
/* Function that returns a pointer to a value from the environment */
const unsigned char *env_get_addr(int);
unsigned char env_get_char_memory(int index);
/* Function that updates CRC of the enironment */
void env_crc_update(void);
/* [re]set to the default environment */
void set_default_env(const char *s);
/* Import from binary representation into hash table */
int env_import(const char *buf, int check);
#endif /* DO_DEPS_ONLY */
#endif /* _ENVIRONMENT_H_ */
|
1001-study-uboot
|
include/environment.h
|
C
|
gpl3
| 6,207
|
/*
* include/mpc8220.h
*
* Prototypes, etc. for the Motorola MPC8220
* embedded cpu chips
*
* 2004 (c) Freescale, Inc.
* Author: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MPC8220_H__
#define __MPC8220_H__
/* Processor name */
#if defined(CONFIG_MPC8220)
#define CPU_ID_STR "MPC8220"
#endif
/* Exception offsets (PowerPC standard) */
#define EXC_OFF_SYS_RESET 0x0100
#define _START_OFFSET EXC_OFF_SYS_RESET
/* Internal memory map */
/* MPC8220 Internal Register MMAP */
#define MMAP_MBAR (CONFIG_SYS_MBAR + 0x00000000) /* chip selects */
#define MMAP_MEMCTL (CONFIG_SYS_MBAR + 0x00000100) /* sdram controller */
#define MMAP_XLBARB (CONFIG_SYS_MBAR + 0x00000200) /* xlb arbitration control */
#define MMAP_CDM (CONFIG_SYS_MBAR + 0x00000300) /* clock distribution module */
#define MMAP_VDOPLL (CONFIG_SYS_MBAR + 0x00000400) /* video PLL */
#define MMAP_FB (CONFIG_SYS_MBAR + 0x00000500) /* flex bus controller */
#define MMAP_PCFG (CONFIG_SYS_MBAR + 0x00000600) /* port config */
#define MMAP_ICTL (CONFIG_SYS_MBAR + 0x00000700) /* interrupt controller */
#define MMAP_GPTMR (CONFIG_SYS_MBAR + 0x00000800) /* general purpose timers */
#define MMAP_SLTMR (CONFIG_SYS_MBAR + 0x00000900) /* slice timers */
#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00000A00) /* gpio module */
#define MMAP_XCPCI (CONFIG_SYS_MBAR + 0x00000B00) /* pci controller */
#define MMAP_PCIARB (CONFIG_SYS_MBAR + 0x00000C00) /* pci arbiter */
#define MMAP_EXTDMA1 (CONFIG_SYS_MBAR + 0x00000D00) /* external dma1 */
#define MMAP_EXTDMA2 (CONFIG_SYS_MBAR + 0x00000E00) /* external dma1 */
#define MMAP_USBH (CONFIG_SYS_MBAR + 0x00001000) /* usb host */
#define MMAP_CMTMR (CONFIG_SYS_MBAR + 0x00007f00) /* comm timers */
#define MMAP_DMA (CONFIG_SYS_MBAR + 0x00008000) /* dma */
#define MMAP_USBD (CONFIG_SYS_MBAR + 0x00008200) /* usb device */
#define MMAP_COMMPCI (CONFIG_SYS_MBAR + 0x00008400) /* pci comm Bus regs */
#define MMAP_1284 (CONFIG_SYS_MBAR + 0x00008500) /* 1284 */
#define MMAP_PEV (CONFIG_SYS_MBAR + 0x00008600) /* print engine video */
#define MMAP_PSC1 (CONFIG_SYS_MBAR + 0x00008800) /* psc1 block */
#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00008f00) /* i2c controller */
#define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00009000) /* fast ethernet 1 */
#define MMAP_FEC2 (CONFIG_SYS_MBAR + 0x00009800) /* fast ethernet 2 */
#define MMAP_JBIGRAM (CONFIG_SYS_MBAR + 0x0000a000) /* jbig RAM */
#define MMAP_JBIG (CONFIG_SYS_MBAR + 0x0000c000) /* jbig */
#define MMAP_PDLA (CONFIG_SYS_MBAR + 0x00010000) /* */
#define MMAP_SRAMCFG (CONFIG_SYS_MBAR + 0x0001ff00) /* SRAM config */
#define MMAP_SRAM (CONFIG_SYS_MBAR + 0x00020000) /* SRAM */
#define SRAM_SIZE 0x8000 /* 32 KB */
/* ------------------------------------------------------------------------ */
/*
* Macro for Programmable Serial Channel
*/
/* equates for mode reg. 1 for channel A or B */
#define PSC_MR1_RX_RTS 0x80000000 /* receiver RTS enabled */
#define PSC_MR1_RX_INT 0x40000000 /* receiver intrupt enabled */
#define PSC_MR1_ERR_MODE 0x20000000 /* block error mode */
#define PSC_MR1_PAR_MODE_MULTI 0x18000000 /* multi_drop mode */
#define PSC_MR1_NO_PARITY 0x10000000 /* no parity mode */
#define PSC_MR1_ALWAYS_0 0x08000000 /* force parity mode */
#define PSC_MR1_ALWAYS_1 0x0c000000 /* force parity mode */
#define PSC_MR1_EVEN_PARITY 0x00000000 /* parity mode */
#define PSC_MR1_ODD_PARITY 0x04000000 /* 0 = even, 1 = odd */
#define PSC_MR1_BITS_CHAR_8 0x03000000 /* 8 bits */
#define PSC_MR1_BITS_CHAR_7 0x02000000 /* 7 bits */
#define PSC_MR1_BITS_CHAR_6 0x01000000 /* 6 bits */
#define PSC_MR1_BITS_CHAR_5 0x00000000 /* 5 bits */
/* equates for mode reg. 2 for channel A or B */
#define PSC_MR2_NORMAL_MODE 0x00000000 /* normal channel mode */
#define PSC_MR2_AUTO_MODE 0x40000000 /* automatic channel mode */
#define PSC_MR2_LOOPBACK_LOCL 0x80000000 /* local loopback channel mode */
#define PSC_MR2_LOOPBACK_REMT 0xc0000000 /* remote loopback channel mode */
#define PSC_MR2_TX_RTS 0x20000000 /* transmitter RTS enabled */
#define PSC_MR2_TX_CTS 0x10000000 /* transmitter CTS enabled */
#define PSC_MR2_STOP_BITS_2 0x0f000000 /* 2 stop bits */
#define PSC_MR2_STOP_BITS_1 0x07000000 /* 1 stop bit */
/* equates for status reg. A or B */
#define PSC_SR_BREAK 0x80000000 /* received break */
#define PSC_SR_NEOF PSC_SR_BREAK /* Next byte is EOF - MIR/FIR */
#define PSC_SR_FRAMING 0x40000000 /* framing error */
#define PSC_SR_PHYERR PSC_SR_FRAMING/* Physical Layer error - MIR/FIR */
#define PSC_SR_PARITY 0x20000000 /* parity error */
#define PSC_SR_CRCERR PSC_SR_PARITY /* CRC error */
#define PSC_SR_OVERRUN 0x10000000 /* overrun error */
#define PSC_SR_TXEMT 0x08000000 /* transmitter empty */
#define PSC_SR_TXRDY 0x04000000 /* transmitter ready*/
#define PSC_SR_FFULL 0x02000000 /* fifo full */
#define PSC_SR_RXRDY 0x01000000 /* receiver ready */
#define PSC_SR_DEOF 0x00800000 /* Detect EOF or RX-FIFO contain EOF */
#define PSC_SR_ERR 0x00400000 /* Error Status including FIFO */
/* equates for clock select reg. */
#define PSC_CSRX16EXT_CLK 0x1110 /* x 16 ext_clock */
#define PSC_CSRX1EXT_CLK 0x1111 /* x 1 ext_clock */
/* equates for command reg. A or B */
#define PSC_CR_NO_COMMAND 0x00000000 /* no command */
#define PSC_CR_RST_MR_PTR_CMD 0x10000000 /* reset mr pointer command */
#define PSC_CR_RST_RX_CMD 0x20000000 /* reset receiver command */
#define PSC_CR_RST_TX_CMD 0x30000000 /* reset transmitter command */
#define PSC_CR_RST_ERR_STS_CMD 0x40000000 /* reset error status cmnd */
#define PSC_CR_RST_BRK_INT_CMD 0x50000000 /* reset break int. command */
#define PSC_CR_STR_BREAK_CMD 0x60000000 /* start break command */
#define PSC_CR_STP_BREAK_CMD 0x70000000 /* stop break command */
#define PSC_CR_RX_ENABLE 0x01000000 /* receiver enabled */
#define PSC_CR_RX_DISABLE 0x02000000 /* receiver disabled */
#define PSC_CR_TX_ENABLE 0x04000000 /* transmitter enabled */
#define PSC_CR_TX_DISABLE 0x08000000 /* transmitter disabled */
/* equates for input port change reg. */
#define PSC_IPCR_SYNC 0x80000000 /* Sync Detect */
#define PSC_IPCR_D_CTS 0x10000000 /* Delta CTS */
#define PSC_IPCR_CTS 0x01000000 /* CTS - current state of PSC_CTS */
/* equates for auxiliary control reg. (timer and counter clock selects) */
#define PSC_ACR_BRG 0x80000000 /* for 68681 compatibility
baud rate gen select
0 = set 1; 1 = set 2
equates are set 2 ONLY */
#define PSC_ACR_TMR_EXT_CLK_16 0x70000000 /* xtnl clock divided by 16 */
#define PSC_ACR_TMR_EXT_CLK 0x60000000 /* external clock */
#define PSC_ACR_TMR_IP2_16 0x50000000 /* ip2 divided by 16 */
#define PSC_ACR_TMR_IP2 0x40000000 /* ip2 */
#define PSC_ACR_CTR_EXT_CLK_16 0x30000000 /* xtnl clock divided by 16 */
#define PSC_ACR_CTR_TXCB 0x20000000 /* channel B xmitr clock */
#define PSC_ACR_CTR_TXCA 0x10000000 /* channel A xmitr clock */
#define PSC_ACR_CTR_IP2 0x00000000 /* ip2 */
#define PSC_ACR_IEC0 0x01000000 /* interrupt enable ctrl for D_CTS */
/* equates for int. status reg. */
#define PSC_ISR_IPC 0x80000000 /* input port change*/
#define PSC_ISR_BREAK 0x04000000 /* delta break */
#define PSC_ISR_RX_RDY 0x02000000 /* receiver rdy /fifo full */
#define PSC_ISR_TX_RDY 0x01000000 /* transmitter ready */
#define PSC_ISR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
#define PSC_ISR_ERR 0x00400000 /* Error Status including FIFO */
/* equates for int. mask reg. */
#define PSC_IMR_CLEAR 0xff000000 /* Clear the imr */
#define PSC_IMR_IPC 0x80000000 /* input port change*/
#define PSC_IMR_BREAK 0x04000000 /* delta break */
#define PSC_IMR_RX_RDY 0x02000000 /* rcvr ready / fifo full */
#define PSC_IMR_TX_RDY 0x01000000 /* transmitter ready */
#define PSC_IMR_DEOF 0x00800000 /* Detect EOF / RX-FIFO contains EOF */
#define PSC_IMR_ERR 0x00400000 /* Error Status including FIFO */
/* equates for input port reg. */
#define PSC_IP_LPWRB 0x80000000 /* Low power mode in Ac97 */
#define PSC_IP_TGL 0x40000000 /* test usage */
#define PSC_IP_CTS 0x01000000 /* CTS */
/* equates for output port bit set reg. */
#define PSC_OPSET_RTS 0x01000000 /* Assert PSC_RTS output */
/* equates for output port bit reset reg. */
#define PSC_OPRESET_RTS 0x01000000 /* Assert PSC_RTS output */
/* equates for rx FIFO number of data reg. */
#define PSC_RFNUM(x) ((x&0xff)<<24)/* receive count */
/* equates for tx FIFO number of data reg. */
#define PSC_TFNUM(x) ((x&0xff)<<24)/* receive count */
/* equates for rx FIFO status reg */
#define PSC_RFSTAT_TAG(x) ((x&3)<<28) /* tag */
#define PSC_RFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
#define PSC_RFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
#define PSC_RFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
#define PSC_RFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
#define PSC_RFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
#define PSC_RFSTAT_ERR 0x00400000 /* Fifo err */
#define PSC_RFSTAT_UF 0x00200000 /* Underflow */
#define PSC_RFSTAT_OF 0x00100000 /* overflow */
#define PSC_RFSTAT_FR 0x00080000 /* frame ready */
#define PSC_RFSTAT_FULL 0x00040000 /* full */
#define PSC_RFSTAT_ALARM 0x00020000 /* alarm */
#define PSC_RFSTAT_EMPTY 0x00010000 /* empty */
/* equates for tx FIFO status reg */
#define PSC_TFSTAT_TAG(x) ((x&3)<<28) /* tag */
#define PSC_TFSTAT_FRAME0 0x08 /* Frame Indicator 0 */
#define PSC_TFSTAT_FRAME1 0x04 /* Frame Indicator 1 */
#define PSC_TFSTAT_FRAME2 0x02 /* Frame Indicator 2 */
#define PSC_TFSTAT_FRAME3 0x01 /* Frame Indicator 3 */
#define PSC_TFSTAT_FRAME(x) ((x&0x0f)<<24)/* Frame indicator */
#define PSC_TFSTAT_ERR 0x00400000 /* Fifo err */
#define PSC_TFSTAT_UF 0x00200000 /* Underflow */
#define PSC_TFSTAT_OF 0x00100000 /* overflow */
#define PSC_TFSTAT_FR 0x00080000 /* frame ready */
#define PSC_TFSTAT_FULL 0x00040000 /* full */
#define PSC_TFSTAT_ALARM 0x00020000 /* alarm */
#define PSC_TFSTAT_EMPTY 0x00010000 /* empty */
/* equates for rx FIFO control reg. */
#define PSC_RFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
#define PSC_RFCNTL_FRAME 0x08000000 /* Frame mode enable */
#define PSC_RFCNTL_GR(x) ((x&7)<<24) /* Granularity */
/* equates for tx FIFO control reg. */
#define PSC_TFCNTL_WTAG(x) ((x&3)<<29) /* Write tag */
#define PSC_TFCNTL_FRAME 0x08000000 /* Frame mode enable */
#define PSC_TFCNTL_GR(x) ((x&7)<<24) /* Granularity */
/* equates for rx FIFO alarm reg */
#define PSC_RFALARM(x) (x&0x1ff) /* Alarm */
/* equates for tx FIFO alarm reg */
#define PSC_TFALARM(x) (x&0x1ff) /* Alarm */
/* equates for rx FIFO read pointer */
#define PSC_RFRPTR(x) (x&0x1ff) /* read pointer */
/* equates for tx FIFO read pointer */
#define PSC_TFRPTR(x) (x&0x1ff) /* read pointer */
/* equates for rx FIFO write pointer */
#define PSC_RFWPTR(x) (x&0x1ff) /* write pointer */
/* equates for rx FIFO write pointer */
#define PSC_TFWPTR(x) (x&0x1ff) /* write pointer */
/* equates for rx FIFO last read frame pointer reg */
#define PSC_RFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
/* equates for tx FIFO last read frame pointer reg */
#define PSC_TFLRFPTR(x) (x&0x1ff) /* last read frame pointer */
/* equates for rx FIFO last write frame pointer reg */
#define PSC_RFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
/* equates for tx FIFO last write frame pointer reg */
#define PSC_TFLWFPTR(x) (x&0x1ff) /* last write frame pointer */
/* PCI configuration (only for PLL determination)*/
#define PCI_REG_PCIGSCR (MMAP_XCPCI + 0x60) /* Global status/control register */
#define PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK 0x07000000
#define PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT 24
#define PCI_REG_PCICAR (MMAP_XCPCI + 0xF8) /* Configuration Address Register */
/* ------------------------------------------------------------------------ */
/*
* Macro for General Purpose Timer
*/
/* Enable and Mode Select */
#define GPT_OCT(x) (x & 0x3)<<4/* Output Compare Type */
#define GPT_ICT(x) (x & 0x3) /* Input Capture Type */
#define GPT_CTRL_WDEN 0x80 /* Watchdog Enable */
#define GPT_CTRL_CE 0x10 /* Counter Enable */
#define GPT_CTRL_STPCNT 0x04 /* Stop continous */
#define GPT_CTRL_ODRAIN 0x02 /* Open Drain */
#define GPT_CTRL_INTEN 0x01 /* Interrupt Enable */
#define GPT_MODE_GPIO(x) (x & 0x3)<<4/* Gpio Mode Type */
#define GPT_TMS_ICT 0x01 /* Input Capture Enable */
#define GPT_TMS_OCT 0x02 /* Output Capture Enable */
#define GPT_TMS_PWM 0x03 /* PWM Capture Enable */
#define GPT_TMS_SGPIO 0x04 /* PWM Capture Enable */
#define GPT_PWM_WIDTH(x) (x & 0xffff)
/* Status */
#define GPT_STA_CAPTURE(x) (x & 0xffff)/* Read of internal counter */
#define GPT_OVFPIN_OVF(x) (x & 0x70) /* Internal counter roll over */
#define GPT_OVFPIN_PIN 0x01 /* Input pin - Timer 0 and 1 */
#define GPT_INT_TEXP 0x08 /* Timer Expired in Internal Timer mode */
#define GPT_INT_PWMP 0x04 /* PWM end of period occurred */
#define GPT_INT_COMP 0x02 /* OC reference event occurred */
#define GPT_INT_CAPT 0x01 /* IC reference event occurred */
/* ------------------------------------------------------------------------ */
/*
* Port configuration
*/
#define CONFIG_SYS_FEC1_PORT0_CONFIG 0x00000000
#define CONFIG_SYS_FEC1_PORT1_CONFIG 0x00000000
#define CONFIG_SYS_1284_PORT0_CONFIG 0x00000000
#define CONFIG_SYS_1284_PORT1_CONFIG 0x00000000
#define CONFIG_SYS_FEC2_PORT2_CONFIG 0x00000000
#define CONFIG_SYS_PEV_PORT2_CONFIG 0x00000000
#define CONFIG_SYS_GP0_PORT0_CONFIG 0x00000000
#define CONFIG_SYS_GP1_PORT2_CONFIG 0xaaaaaac0
#define CONFIG_SYS_PSC_PORT3_CONFIG 0x00020000
#define CONFIG_SYS_CS1_PORT3_CONFIG 0x00000000
#define CONFIG_SYS_CS2_PORT3_CONFIG 0x10000000
#define CONFIG_SYS_CS3_PORT3_CONFIG 0x40000000
#define CONFIG_SYS_CS4_PORT3_CONFIG 0x00000400
#define CONFIG_SYS_CS5_PORT3_CONFIG 0x00000200
#define CONFIG_SYS_PCI_PORT3_CONFIG 0x01400180
#define CONFIG_SYS_I2C_PORT3_CONFIG 0x00000000
#define CONFIG_SYS_GP2_PORT3_CONFIG 0x000200a0
/* ------------------------------------------------------------------------ */
/*
* DRAM configuration
*/
/* Field definitions for the control register */
#define CTL_MODE_ENABLE_SHIFT 31
#define CTL_CKE_SHIFT 30
#define CTL_DDR_SHIFT 29
#define CTL_REFRESH_SHIFT 28
#define CTL_ADDRMUX_SHIFT 24
#define CTL_PRECHARGE_SHIFT 23
#define CTL_DRIVE_RULE_SHIFT 22
#define CTL_REFRESH_INTERVAL_SHIFT 16
#define CTL_DQSOEN_SHIFT 8
#define CTL_BUFFERED_SHIFT 4
#define CTL_REFRESH_CMD_SHIFT 2
#define CTL_PRECHARGE_CMD_SHIFT 1
#define CTL_MODE_ENABLE (1<<CTL_MODE_ENABLE_SHIFT)
#define CTL_CKE_HIGH (1<<CTL_CKE_SHIFT)
#define CTL_DDR_MODE (1<<CTL_DDR_SHIFT)
#define CTL_REFRESH_ENABLE (1<<CTL_REFRESH_SHIFT)
#define CTL_ADDRMUX(value) ((value)<<CTL_ADDRMUX_SHIFT)
#define CTL_A8PRECHARGE (1<<CTL_PRECHARGE_SHIFT)
#define CTL_REFRESH_INTERVAL(value) ((value)<<CTL_REFRESH_INTERVAL_SHIFT)
#define CTL_DQSOEN(value) ((value)<<CTL_DQSOEN_SHIFT)
#define CTL_BUFFERED (1<<CTL_BUFFERED_SHIFT)
#define CTL_REFRESH_CMD (1<<CTL_REFRESH_CMD_SHIFT)
#define CTL_PRECHARGE_CMD (1<<CTL_PRECHARGE_CMD_SHIFT)
/* Field definitions for config register 1 */
#define CFG1_SRD2RWP_SHIFT 28
#define CFG1_SWT2RWP_SHIFT 24
#define CFG1_RLATENCY_SHIFT 20
#define CFG1_ACT2WR_SHIFT 16
#define CFG1_PRE2ACT_SHIFT 12
#define CFG1_REF2ACT_SHIFT 8
#define CFG1_WLATENCY_SHIFT 4
#define CFG1_SRD2RWP(value) ((value)<<CFG1_SRD2RWP_SHIFT)
#define CFG1_SWT2RWP(value) ((value)<<CFG1_SWT2RWP_SHIFT)
#define CFG1_RLATENCY(value) ((value)<<CFG1_RLATENCY_SHIFT)
#define CFG1_ACT2WR(value) ((value)<<CFG1_ACT2WR_SHIFT)
#define CFG1_PRE2ACT(value) ((value)<<CFG1_PRE2ACT_SHIFT)
#define CFG1_REF2ACT(value) ((value)<<CFG1_REF2ACT_SHIFT)
#define CFG1_WLATENCY(value) ((value)<<CFG1_WLATENCY_SHIFT)
/* Field definitions for config register 2 */
#define CFG2_BRD2RP_SHIFT 28
#define CFG2_BWT2RWP_SHIFT 24
#define CFG2_BRD2WT_SHIFT 20
#define CFG2_BURSTLEN_SHIFT 16
#define CFG2_BRD2RP(value) ((value)<<CFG2_BRD2RP_SHIFT)
#define CFG2_BWT2RWP(value) ((value)<<CFG2_BWT2RWP_SHIFT)
#define CFG2_BRD2WT(value) ((value)<<CFG2_BRD2WT_SHIFT)
#define CFG2_BURSTLEN(value) ((value)<<CFG2_BURSTLEN_SHIFT)
/* Field definitions for the mode/extended mode register - mode
* register access
*/
#define MODE_REG_SHIFT 30
#define MODE_OPMODE_SHIFT 25
#define MODE_CL_SHIFT 22
#define MODE_BT_SHIFT 21
#define MODE_BURSTLEN_SHIFT 18
#define MODE_CMD_SHIFT 16
#define MODE_MODE 0
#define MODE_OPMODE(value) ((value)<<MODE_OPMODE_SHIFT)
#define MODE_CL(value) ((value)<<MODE_CL_SHIFT)
#define MODE_BT_INTERLEAVED (1<<MODE_BT_SHIFT)
#define MODE_BT_SEQUENTIAL (0<<MODE_BT_SHIFT)
#define MODE_BURSTLEN(value) ((value)<<MODE_BURSTLEN_SHIFT)
#define MODE_CMD (1<<MODE_CMD_SHIFT)
#define MODE_BURSTLEN_8 3
#define MODE_BURSTLEN_4 2
#define MODE_BURSTLEN_2 1
#define MODE_CL_2 2
#define MODE_CL_2p5 6
#define MODE_OPMODE_NORMAL 0
#define MODE_OPMODE_RESETDLL 2
/* Field definitions for the mode/extended mode register - extended
* mode register access
*/
#define MODE_X_DLL_SHIFT 18 /* DLL enable/disable */
#define MODE_X_DS_SHIFT 19 /* Drive strength normal/reduced */
#define MODE_X_QFC_SHIFT 20 /* QFC function (whatever that is) */
#define MODE_X_OPMODE_SHIFT 21
#define MODE_EXTENDED (1<<MODE_REG_SHIFT)
#define MODE_X_DLL_ENABLE 0
#define MODE_X_DLL_DISABLE (1<<MODE_X_DLL_SHIFT)
#define MODE_X_DS_NORMAL 0
#define MODE_X_DS_REDUCED (1<<MODE_X_DS_SHIFT)
#define MODE_X_QFC_DISABLED 0
#define MODE_X_OPMODE(value) ((value)<<MODE_X_OPMODE_SHIFT)
#ifndef __ASSEMBLY__
/*
* DMA control/status registers.
*/
struct mpc8220_dma {
u32 taskBar; /* DMA + 0x00 */
u32 currentPointer; /* DMA + 0x04 */
u32 endPointer; /* DMA + 0x08 */
u32 variablePointer;/* DMA + 0x0c */
u8 IntVect1; /* DMA + 0x10 */
u8 IntVect2; /* DMA + 0x11 */
u16 PtdCntrl; /* DMA + 0x12 */
u32 IntPend; /* DMA + 0x14 */
u32 IntMask; /* DMA + 0x18 */
u16 tcr_0; /* DMA + 0x1c */
u16 tcr_1; /* DMA + 0x1e */
u16 tcr_2; /* DMA + 0x20 */
u16 tcr_3; /* DMA + 0x22 */
u16 tcr_4; /* DMA + 0x24 */
u16 tcr_5; /* DMA + 0x26 */
u16 tcr_6; /* DMA + 0x28 */
u16 tcr_7; /* DMA + 0x2a */
u16 tcr_8; /* DMA + 0x2c */
u16 tcr_9; /* DMA + 0x2e */
u16 tcr_a; /* DMA + 0x30 */
u16 tcr_b; /* DMA + 0x32 */
u16 tcr_c; /* DMA + 0x34 */
u16 tcr_d; /* DMA + 0x36 */
u16 tcr_e; /* DMA + 0x38 */
u16 tcr_f; /* DMA + 0x3a */
u8 IPR0; /* DMA + 0x3c */
u8 IPR1; /* DMA + 0x3d */
u8 IPR2; /* DMA + 0x3e */
u8 IPR3; /* DMA + 0x3f */
u8 IPR4; /* DMA + 0x40 */
u8 IPR5; /* DMA + 0x41 */
u8 IPR6; /* DMA + 0x42 */
u8 IPR7; /* DMA + 0x43 */
u8 IPR8; /* DMA + 0x44 */
u8 IPR9; /* DMA + 0x45 */
u8 IPR10; /* DMA + 0x46 */
u8 IPR11; /* DMA + 0x47 */
u8 IPR12; /* DMA + 0x48 */
u8 IPR13; /* DMA + 0x49 */
u8 IPR14; /* DMA + 0x4a */
u8 IPR15; /* DMA + 0x4b */
u8 IPR16; /* DMA + 0x4c */
u8 IPR17; /* DMA + 0x4d */
u8 IPR18; /* DMA + 0x4e */
u8 IPR19; /* DMA + 0x4f */
u8 IPR20; /* DMA + 0x50 */
u8 IPR21; /* DMA + 0x51 */
u8 IPR22; /* DMA + 0x52 */
u8 IPR23; /* DMA + 0x53 */
u8 IPR24; /* DMA + 0x54 */
u8 IPR25; /* DMA + 0x55 */
u8 IPR26; /* DMA + 0x56 */
u8 IPR27; /* DMA + 0x57 */
u8 IPR28; /* DMA + 0x58 */
u8 IPR29; /* DMA + 0x59 */
u8 IPR30; /* DMA + 0x5a */
u8 IPR31; /* DMA + 0x5b */
u32 res1; /* DMA + 0x5c */
u32 res2; /* DMA + 0x60 */
u32 res3; /* DMA + 0x64 */
u32 MDEDebug; /* DMA + 0x68 */
u32 ADSDebug; /* DMA + 0x6c */
u32 Value1; /* DMA + 0x70 */
u32 Value2; /* DMA + 0x74 */
u32 Control; /* DMA + 0x78 */
u32 Status; /* DMA + 0x7c */
u32 EU00; /* DMA + 0x80 */
u32 EU01; /* DMA + 0x84 */
u32 EU02; /* DMA + 0x88 */
u32 EU03; /* DMA + 0x8c */
u32 EU04; /* DMA + 0x90 */
u32 EU05; /* DMA + 0x94 */
u32 EU06; /* DMA + 0x98 */
u32 EU07; /* DMA + 0x9c */
u32 EU10; /* DMA + 0xa0 */
u32 EU11; /* DMA + 0xa4 */
u32 EU12; /* DMA + 0xa8 */
u32 EU13; /* DMA + 0xac */
u32 EU14; /* DMA + 0xb0 */
u32 EU15; /* DMA + 0xb4 */
u32 EU16; /* DMA + 0xb8 */
u32 EU17; /* DMA + 0xbc */
u32 EU20; /* DMA + 0xc0 */
u32 EU21; /* DMA + 0xc4 */
u32 EU22; /* DMA + 0xc8 */
u32 EU23; /* DMA + 0xcc */
u32 EU24; /* DMA + 0xd0 */
u32 EU25; /* DMA + 0xd4 */
u32 EU26; /* DMA + 0xd8 */
u32 EU27; /* DMA + 0xdc */
u32 EU30; /* DMA + 0xe0 */
u32 EU31; /* DMA + 0xe4 */
u32 EU32; /* DMA + 0xe8 */
u32 EU33; /* DMA + 0xec */
u32 EU34; /* DMA + 0xf0 */
u32 EU35; /* DMA + 0xf4 */
u32 EU36; /* DMA + 0xf8 */
u32 EU37; /* DMA + 0xfc */
};
/*
* PCI Header Registers
*/
typedef struct mpc8220_xcpci {
u32 dev_ven_id; /* 0xb00 - device/vendor ID */
u32 stat_cmd_reg; /* 0xb04 - status command register */
u32 class_code_rev_id; /* 0xb08 - class code / revision ID */
u32 bist_htyp_lat_cshl; /* 0xb0c - BIST/HeaderType/Latency/cache line */
u32 base0; /* 0xb10 - base address 0 */
u32 base1; /* 0xb14 - base address 1 */
u32 reserved1[4]; /* 0xb18->0xd27 - base address 2 - 5 */
u32 cis; /* 0xb28 - cardBus CIS pointer */
u32 sub_sys_ven_id; /* 0xb2c - sub system ID/ subsystem vendor ID */
u32 reserved2; /* 0xb30 - expansion ROM base address */
u32 reserved3; /* 0xb00 - reserved */
u32 reserved4; /* 0xb00 - reserved */
u32 mlat_mgnt_ipl; /* 0xb3c - MaxLat/MinGnt/ int pin/int line */
u32 reserved5[8];
/* MPC8220 specific - not accessible in PCI header space externally */
u32 glb_stat_ctl; /* 0xb60 - Global Status Control */
u32 target_bar0; /* 0xb64 - Target Base Address 0 */
u32 target_bar1; /* 0xb68 - Target Base Address 1 */
u32 target_ctrl; /* 0xb6c - Target Control */
u32 init_win0; /* 0xb70 - Initiator Window 0 Base/Translation */
u32 init_win1; /* 0xb74 - Initiator Window 1 Base/Translation */
u32 init_win2; /* 0xb78 - Initiator Window 2 Base/Translation */
u32 reserved6; /* 0xb7c - reserved */
u32 init_win_cfg; /* 0xb80 */
u32 init_ctrl; /* 0xb84 */
u32 init_stat; /* 0xb88 */
u32 reserved7[27];
u32 cfg_adr; /* 0xbf8 */
u32 reserved8;
} mpc8220_xcpci_t;
/* PCI->XLB space translation (MPC8220 target), reg0 can address max 256MB,
reg1 - 1GB */
#define PCI_BASE_ADDR_REG0 0x40000000
#define PCI_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE)
#define PCI_TARGET_BASE_ADDR_REG0 (CONFIG_SYS_MBAR)
#define PCI_TARGET_BASE_ADDR_REG1 (CONFIG_SYS_SDRAM_BASE)
#define PCI_TARGET_BASE_ADDR_EN 1<<0
/* PCI Global Status/Control Register (PCIGSCR) */
#define PCI_GLB_STAT_CTRL_PE_SHIFT 29
#define PCI_GLB_STAT_CTRL_SE_SHIFT 28
#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_SHIFT 24
#define PCI_GLB_STAT_CTRL_XLB_TO_PCI_CLK_MASK 0x7
#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_SHIFT 16
#define PCI_GLB_STAT_CTRL_IPG_TO_PCI_CLK_MASK 0x7
#define PCI_GLB_STAT_CTRL_PEE_SHIFT 13
#define PCI_GLB_STAT_CTRL_SEE_SHIFT 12
#define PCI_GLB_STAT_CTRL_PR_SHIFT 0
#define PCI_GLB_STAT_CTRL_PE (1<<PCI_GLB_STAT_CTRL_PE_SHIFT)
#define PCI_GLB_STAT_CTRL_SE (1<<PCI_GLB_STAT_CTRL_SE_SHIFT)
#define PCI_GLB_STAT_CTRL_PEE (1<<PCI_GLB_STAT_CTRL_PEE_SHIFT)
#define PCI_GLB_STAT_CTRL_SEE (1<<PCI_GLB_STAT_CTRL_SEE_SHIFT)
#define PCI_GLB_STAT_CTRL_PR (1<<PCI_GLB_STAT_CTRL_PR_SHIFT)
/* PCI Target Control Register (PCITCR) */
#define PCI_TARGET_CTRL_LD_SHIFT 24
#define PCI_TARGET_CTRL_P_SHIFT 16
#define PCI_TARGET_CTRL_LD (1<<PCI_TARGET_CTRL_LD_SHIFT)
#define PCI_TARGET_CTRL_P (1<<PCI_TARGET_CTRL_P_SHIFT)
/* PCI Initiator Window Configuration Register (PCIIWCR) */
#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT 27
#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_SHIFT 25
#define PCI_INIT_WIN_CFG_WIN0_CTRL_PRC_MASK 0x3
#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT 24
#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT 19
#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_SHIFT 17
#define PCI_INIT_WIN_CFG_WIN1_CTRL_PRC_MASK 0x3
#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT 16
#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT 11
#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_SHIFT 9
#define PCI_INIT_WIN_CFG_WIN2_CTRL_PRC_MASK 0x3
#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT 8
#define PCI_INIT_WIN_CFG_WIN_MEM_READ 0x0
#define PCI_INIT_WIN_CFG_WIN_MEM_READ_LINE 0x1
#define PCI_INIT_WIN_CFG_WIN_MEM_READ_MULTIPLE 0x2
#define PCI_INIT_WIN_CFG_WIN0_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_IO_SHIFT)
#define PCI_INIT_WIN_CFG_WIN0_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN0_CTRL_EN_SHIFT)
#define PCI_INIT_WIN_CFG_WIN1_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_IO_SHIFT)
#define PCI_INIT_WIN_CFG_WIN1_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN1_CTRL_EN_SHIFT)
#define PCI_INIT_WIN_CFG_WIN2_CTRL_IO (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_IO_SHIFT)
#define PCI_INIT_WIN_CFG_WIN2_CTRL_EN (1<<PCI_INIT_WIN_CFG_WIN2_CTRL_EN_SHIFT)
/* PCI Initiator Control Register (PCIICR) */
#define PCI_INIT_CTRL_REE_SHIFT 26
#define PCI_INIT_CTRL_IAE_SHIFT 25
#define PCI_INIT_CTRL_TAE_SHIFT 24
#define PCI_INIT_CTRL_MAX_RETRIES_SHIFT 0
#define PCI_INIT_CTRL_MAX_RETRIES_MASK 0xff
#define PCI_INIT_CTRL_REE (1<<PCI_INIT_CTRL_REE_SHIFT)
#define PCI_INIT_CTRL_IAE (1<<PCI_INIT_CTRL_IAE_SHIFT)
#define PCI_INIT_CTRL_TAE (1<<PCI_INIT_CTRL_TAE_SHIFT)
/* PCI Status/Command Register (PCISCR) - PCI Dword 1 */
#define PCI_STAT_CMD_PE_SHIFT 31
#define PCI_STAT_CMD_SE_SHIFT 30
#define PCI_STAT_CMD_MA_SHIFT 29
#define PCI_STAT_CMD_TR_SHIFT 28
#define PCI_STAT_CMD_TS_SHIFT 27
#define PCI_STAT_CMD_DT_SHIFT 25
#define PCI_STAT_CMD_DT_MASK 0x3
#define PCI_STAT_CMD_DP_SHIFT 24
#define PCI_STAT_CMD_FC_SHIFT 23
#define PCI_STAT_CMD_R_SHIFT 22
#define PCI_STAT_CMD_66M_SHIFT 21
#define PCI_STAT_CMD_C_SHIFT 20
#define PCI_STAT_CMD_F_SHIFT 9
#define PCI_STAT_CMD_S_SHIFT 8
#define PCI_STAT_CMD_ST_SHIFT 7
#define PCI_STAT_CMD_PER_SHIFT 6
#define PCI_STAT_CMD_V_SHIFT 5
#define PCI_STAT_CMD_MW_SHIFT 4
#define PCI_STAT_CMD_SP_SHIFT 3
#define PCI_STAT_CMD_B_SHIFT 2
#define PCI_STAT_CMD_M_SHIFT 1
#define PCI_STAT_CMD_IO_SHIFT 0
#define PCI_STAT_CMD_PE (1<<PCI_STAT_CMD_PE_SHIFT)
#define PCI_STAT_CMD_SE (1<<PCI_STAT_CMD_SE_SHIFT)
#define PCI_STAT_CMD_MA (1<<PCI_STAT_CMD_MA_SHIFT)
#define PCI_STAT_CMD_TR (1<<PCI_STAT_CMD_TR_SHIFT)
#define PCI_STAT_CMD_TS (1<<PCI_STAT_CMD_TS_SHIFT)
#define PCI_STAT_CMD_DP (1<<PCI_STAT_CMD_DP_SHIFT)
#define PCI_STAT_CMD_FC (1<<PCI_STAT_CMD_FC_SHIFT)
#define PCI_STAT_CMD_R (1<<PCI_STAT_CMD_R_SHIFT)
#define PCI_STAT_CMD_66M (1<<PCI_STAT_CMD_66M_SHIFT)
#define PCI_STAT_CMD_C (1<<PCI_STAT_CMD_C_SHIFT)
#define PCI_STAT_CMD_F (1<<PCI_STAT_CMD_F_SHIFT)
#define PCI_STAT_CMD_S (1<<PCI_STAT_CMD_S_SHIFT)
#define PCI_STAT_CMD_ST (1<<PCI_STAT_CMD_ST_SHIFT)
#define PCI_STAT_CMD_PER (1<<PCI_STAT_CMD_PER_SHIFT)
#define PCI_STAT_CMD_V (1<<PCI_STAT_CMD_V_SHIFT)
#define PCI_STAT_CMD_MW (1<<PCI_STAT_CMD_MW_SHIFT)
#define PCI_STAT_CMD_SP (1<<PCI_STAT_CMD_SP_SHIFT)
#define PCI_STAT_CMD_B (1<<PCI_STAT_CMD_B_SHIFT)
#define PCI_STAT_CMD_M (1<<PCI_STAT_CMD_M_SHIFT)
#define PCI_STAT_CMD_IO (1<<PCI_STAT_CMD_IO_SHIFT)
/* PCI Configuration 1 Register (PCICR1) - PCI Dword 3 */
#define PCI_CFG1_HT_SHIFT 16
#define PCI_CFG1_HT_MASK 0xff
#define PCI_CFG1_LT_SHIFT 8
#define PCI_CFG1_LT_MASK 0xff
#define PCI_CFG1_CLS_SHIFT 0
#define PCI_CFG1_CLS_MASK 0xf
/* function prototypes */
void loadtask(int basetask, int tasks);
u32 dramSetup(void);
#if defined(CONFIG_PSC_CONSOLE)
int psc_serial_init (void);
void psc_serial_putc(const char c);
void psc_serial_puts (const char *s);
int psc_serial_getc(void);
int psc_serial_tstc(void);
void psc_serial_setbrg(void);
#endif
#if defined (CONFIG_EXTUART_CONSOLE)
int ext_serial_init (void);
void ext_serial_putc(const char c);
void ext_serial_puts (const char *s);
int ext_serial_getc(void);
int ext_serial_tstc(void);
void ext_serial_setbrg(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __MPC8220_H__ */
|
1001-study-uboot
|
include/mpc8220.h
|
C
|
gpl3
| 29,539
|
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __PCA953X_H_
#define __PCA953X_H_
#define PCA953X_IN 0x00
#define PCA953X_OUT 0x01
#define PCA953X_POL 0x02
#define PCA953X_CONF 0x03
#define PCA953X_OUT_LOW 0
#define PCA953X_OUT_HIGH 1
#define PCA953X_POL_NORMAL 0
#define PCA953X_POL_INVERT 1
#define PCA953X_DIR_OUT 0
#define PCA953X_DIR_IN 1
int pca953x_set_val(u8 chip, uint mask, uint data);
int pca953x_set_pol(u8 chip, uint mask, uint data);
int pca953x_set_dir(u8 chip, uint mask, uint data);
int pca953x_get_val(u8 chip);
#endif /* __PCA953X_H_ */
|
1001-study-uboot
|
include/pca953x.h
|
C
|
gpl3
| 1,241
|
#ifndef _SHA256_H
#define _SHA256_H
#define SHA256_SUM_LEN 32
typedef struct {
uint32_t total[2];
uint32_t state[8];
uint8_t buffer[64];
} sha256_context;
void sha256_starts(sha256_context * ctx);
void sha256_update(sha256_context * ctx, uint8_t * input, uint32_t length);
void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]);
#endif /* _SHA256_H */
|
1001-study-uboot
|
include/sha256.h
|
C
|
gpl3
| 377
|
/*
* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Andreas Heppel <aheppel@sysgo.de>
*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* aloong with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _PCI_H
#define _PCI_H
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CLASS_CODE 0x0b /* Device class code */
#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_HEADER_TYPE_NORMAL 0
#define PCI_HEADER_TYPE_BRIDGE 1
#define PCI_HEADER_TYPE_CARDBUS 2
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
/* bit 1 is reserved if address_space = 1 */
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
#define PCI_ROM_ADDRESS_ENABLE 0x01
#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
/* 0x35-0x3b are reserved */
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1d
#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
#define PCI_IO_RANGE_TYPE_16 0x00
#define PCI_IO_RANGE_TYPE_32 0x01
#define PCI_IO_RANGE_MASK ~0x0f
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
#define PCI_MEMORY_RANGE_MASK ~0x0f
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_RANGE_TYPE_MASK 0x0f
#define PCI_PREF_RANGE_TYPE_32 0x00
#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_RANGE_MASK ~0x0f
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16 0x32
/* 0x34 same as for htype 0 */
/* 0x35-0x3b is reserved */
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL 0x3e
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
/* From 440ep */
#define PCI_ERREN 0x48 /* Error Enable */
#define PCI_ERRSTS 0x49 /* Error Status */
#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
#define PCI_CAPID 0x58 /* Capability Identifier */
#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
#define PCI_PMC 0x5A /* Power Management Capabilities */
#define PCI_PMCSR 0x5C /* Power Management Control Status */
#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
/* Header type 2 (CardBus bridges) */
#define PCI_CB_CAPABILITY_LIST 0x14
/* 0x15 reserved */
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0 0x1c
#define PCI_CB_MEMORY_LIMIT_0 0x20
#define PCI_CB_MEMORY_BASE_1 0x24
#define PCI_CB_MEMORY_LIMIT_1 0x28
#define PCI_CB_IO_BASE_0 0x2c
#define PCI_CB_IO_BASE_0_HI 0x2e
#define PCI_CB_IO_LIMIT_0 0x30
#define PCI_CB_IO_LIMIT_0_HI 0x32
#define PCI_CB_IO_BASE_1 0x34
#define PCI_CB_IO_BASE_1_HI 0x36
#define PCI_CB_IO_LIMIT_1 0x38
#define PCI_CB_IO_LIMIT_1_HI 0x3a
#define PCI_CB_IO_RANGE_MASK ~0x03
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_CB_BRIDGE_CONTROL 0x3e
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
#define PCI_CB_BRIDGE_CTL_SERR 0x02
#define PCI_CB_BRIDGE_CTL_ISA 0x04
#define PCI_CB_BRIDGE_CTL_VGA 0x08
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
#define PCI_CB_SUBSYSTEM_ID 0x42
#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
/* 0x48-0x7f reserved */
/* Capability lists */
#define PCI_CAP_LIST_ID 0 /* Capability ID */
#define PCI_CAP_ID_PM 0x01 /* Power Management */
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
#define PCI_CAP_SIZEOF 4
/* Power Management Registers */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
#define PCI_PM_CTRL 4 /* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
#define PCI_PM_DATA_REGISTER 7 /* (??) */
#define PCI_PM_SIZEOF 8
/* AGP registers */
#define PCI_AGP_VERSION 2 /* BCD version number */
#define PCI_AGP_RFU 3 /* Rest of capability flags */
#define PCI_AGP_STATUS 4 /* Status register */
#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
#define PCI_AGP_COMMAND 8 /* Control register */
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
#define PCI_AGP_SIZEOF 12
/* PCI-X registers */
#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
/* Slot Identification */
#define PCI_SID_ESR 2 /* Expansion Slot Register */
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
/* Message Signalled Interrupts registers */
#define PCI_MSI_FLAGS 2 /* Various flags */
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
#define PCI_MSI_RFU 3 /* Rest of capability flags */
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
#define PCI_MAX_PCI_DEVICES 32
#define PCI_MAX_PCI_FUNCTIONS 8
#define PCI_DCR 0x54 /* PCIe Device Control Register */
#define PCI_DSR 0x56 /* PCIe Device Status Register */
#define PCI_LSR 0x5e /* PCIe Link Status Register */
#define PCI_LCR 0x5c /* PCIe Link Control Register */
#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
#define PCI_LTSSM_L0 0x16 /* L0 state */
/* Include the ID list */
#include <pci_ids.h>
#ifdef CONFIG_SYS_PCI_64BIT
typedef u64 pci_addr_t;
typedef u64 pci_size_t;
#else
typedef u32 pci_addr_t;
typedef u32 pci_size_t;
#endif
struct pci_region {
pci_addr_t bus_start; /* Start on the bus */
phys_addr_t phys_start; /* Start in physical address space */
pci_size_t size; /* Size */
unsigned long flags; /* Resource flags */
pci_addr_t bus_lower;
};
#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
#define PCI_REGION_IO 0x00000001 /* PCI IO space */
#define PCI_REGION_TYPE 0x00000001
#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
#define PCI_REGION_RO 0x00000200 /* Read-only memory */
extern __inline__ void pci_set_region(struct pci_region *reg,
pci_addr_t bus_start,
phys_addr_t phys_start,
pci_size_t size,
unsigned long flags) {
reg->bus_start = bus_start;
reg->phys_start = phys_start;
reg->size = size;
reg->flags = flags;
}
typedef int pci_dev_t;
#define PCI_BUS(d) (((d) >> 16) & 0xff)
#define PCI_DEV(d) (((d) >> 11) & 0x1f)
#define PCI_FUNC(d) (((d) >> 8) & 0x7)
#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
#define PCI_ANY_ID (~0)
struct pci_device_id {
unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
};
struct pci_controller;
struct pci_config_table {
unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
unsigned int class; /* Class ID, or PCI_ANY_ID */
unsigned int bus; /* Bus number, or PCI_ANY_ID */
unsigned int dev; /* Device number, or PCI_ANY_ID */
unsigned int func; /* Function number, or PCI_ANY_ID */
void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
unsigned long priv[3];
};
extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
struct pci_config_table *);
#define MAX_PCI_REGIONS 7
#define INDIRECT_TYPE_NO_PCIE_LINK 1
/*
* Structure of a PCI controller (host bridge)
*/
struct pci_controller {
struct pci_controller *next;
int first_busno;
int last_busno;
volatile unsigned int *cfg_addr;
volatile unsigned char *cfg_data;
int indirect_type;
struct pci_region regions[MAX_PCI_REGIONS];
int region_count;
struct pci_config_table *config_table;
void (*fixup_irq)(struct pci_controller *, pci_dev_t);
/* Low-level architecture-dependent routines */
int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
/* Used by auto config */
struct pci_region *pci_mem, *pci_io, *pci_prefetch;
/* Used by ppc405 autoconfig*/
struct pci_region *pci_fb;
int current_busno;
void *priv_data;
};
extern __inline__ void pci_set_ops(struct pci_controller *hose,
int (*read_byte)(struct pci_controller*,
pci_dev_t, int where, u8 *),
int (*read_word)(struct pci_controller*,
pci_dev_t, int where, u16 *),
int (*read_dword)(struct pci_controller*,
pci_dev_t, int where, u32 *),
int (*write_byte)(struct pci_controller*,
pci_dev_t, int where, u8),
int (*write_word)(struct pci_controller*,
pci_dev_t, int where, u16),
int (*write_dword)(struct pci_controller*,
pci_dev_t, int where, u32)) {
hose->read_byte = read_byte;
hose->read_word = read_word;
hose->read_dword = read_dword;
hose->write_byte = write_byte;
hose->write_word = write_word;
hose->write_dword = write_dword;
}
extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
pci_addr_t addr, unsigned long flags);
extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
phys_addr_t addr, unsigned long flags);
#define pci_phys_to_bus(dev, addr, flags) \
pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
#define pci_bus_to_phys(dev, addr, flags) \
pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
#define pci_virt_to_bus(dev, addr, flags) \
pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
(virt_to_phys(addr)), (flags))
#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
(addr), (flags)), \
(len), (map_flags))
#define pci_phys_to_mem(dev, addr) \
pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
#define pci_mem_to_phys(dev, addr) \
pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
#define pci_virt_to_mem(dev, addr) \
pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
#define pci_mem_to_virt(dev, addr, len, map_flags) \
pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
#define pci_virt_to_io(dev, addr) \
pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
#define pci_io_to_virt(dev, addr, len, map_flags) \
pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
extern int pci_hose_read_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word(struct pci_controller *hose,
pci_dev_t dev, int where, u16 *val);
extern int pci_hose_read_config_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u32 *val);
extern int pci_hose_write_config_byte(struct pci_controller *hose,
pci_dev_t dev, int where, u8 val);
extern int pci_hose_write_config_word(struct pci_controller *hose,
pci_dev_t dev, int where, u16 val);
extern int pci_hose_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u32 val);
extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u16 *val);
extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u8 val);
extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u16 val);
extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
extern void pci_register_hose(struct pci_controller* hose);
extern struct pci_controller* pci_bus_to_hose(int bus);
extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
extern int pci_hose_scan(struct pci_controller *hose);
extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
extern void pciauto_region_init(struct pci_region* res);
extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
extern void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
struct pci_region *prefetch,
struct pci_region *io);
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
int wanted_prog_if, int index);
extern int pci_hose_config_device(struct pci_controller *hose,
pci_dev_t dev,
unsigned long io,
pci_addr_t mem,
unsigned long command);
const char * pci_class_str(u8 class);
int pci_last_busno(void);
#ifdef CONFIG_MPC824X
extern void pci_mpc824x_init (struct pci_controller *hose);
#endif
#ifdef CONFIG_MPC85xx
extern void pci_mpc85xx_init (struct pci_controller *hose);
#endif
#endif /* _PCI_H */
|
1001-study-uboot
|
include/pci.h
|
C
|
gpl3
| 23,371
|
/*
* Copyright Rob Taylor, Flying Pig Systems Ltd. 2000.
* Copyright (C) 2001, James Dougherty, jfd@cs.stanford.edu
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MPC824X_H__
#define __MPC824X_H__
#include <config.h>
/* CPU Types */
#define CPU_TYPE_601 0x01 /* PPC 601 CPU */
#define CPU_TYPE_602 0x02 /* PPC 602 CPU */
#define CPU_TYPE_603 0x03 /* PPC 603 CPU */
#define CPU_TYPE_603E 0x06 /* PPC 603e CPU */
#define CPU_TYPE_603P 0x07 /* PPC 603p CPU */
#define CPU_TYPE_604 0x04 /* PPC 604 CPU */
#define CPU_TYPE_604E 0x09 /* PPC 604e CPU */
#define CPU_TYPE_604R 0x0a /* PPC 604r CPU */
#define CPU_TYPE_750 0x08 /* PPC 750 CPU */
#define CPU_TYPE_8240 0x81 /* PPC 8240 CPU */
#define CPU_TYPE_8245 0x8081 /* PPC 8245/8241 CPU */
#define _CACHE_ALIGN_SIZE 32 /* cache line size */
/* spr976 - DMISS data tlb miss address register
* spr977 - DCMP data tlb miss compare register
* spr978 - HASH1 PTEG1 address register
* spr980 - HASH2 PTEG2 address register
* IMISS - instruction tlb miss address register
* ICMP - instruction TLB mis compare register
* RPA - real page address register
* HID0 - hardware implemntation register
* HID2 - instruction address breakpoint register
*/
/* Kahlua/MPC8240 defines */
#define VEN_DEV_ID 0x00021057 /* Vendor and Dev. ID for MPC106 */
#define KAHLUA_ID 0x00031057 /* Vendor & Dev Id for Kahlua's PCI */
#define KAHLUA2_ID 0x00061057 /* 8245 is aka Kahlua-2 */
#define BMC_BASE 0x80000000 /* Kahlua ID in PCI Memory space */
#define CHRP_REG_ADDR 0xfec00000 /* MPC107 Config, Map B */
#define CHRP_REG_DATA 0xfee00000 /* MPC107 Config, Map B */
#define CHRP_ISA_MEM_PHYS 0xfd000000
#define CHRP_ISA_MEM_BUS 0x00000000
#define CHRP_ISA_MEM_SIZE 0x01000000
#define CHRP_ISA_IO_PHYS 0xfe000000
#define CHRP_ISA_IO_BUS 0x00000000
#define CHRP_ISA_IO_SIZE 0x00800000
#define CHRP_PCI_IO_PHYS 0xfe800000
#define CHRP_PCI_IO_BUS 0x00800000
#define CHRP_PCI_IO_SIZE 0x00400000
#define CHRP_PCI_MEM_PHYS 0x80000000
#define CHRP_PCI_MEM_BUS 0x80000000
#define CHRP_PCI_MEM_SIZE 0x7d000000
#define CHRP_PCI_MEMORY_PHYS 0x00000000
#define CHRP_PCI_MEMORY_BUS 0x00000000
#define CHRP_PCI_MEMORY_SIZE 0x40000000
#define PREP_REG_ADDR 0x80000cf8 /* MPC107 Config, Map A */
#define PREP_REG_DATA 0x80000cfc /* MPC107 Config, Map A */
#define PREP_ISA_IO_PHYS 0x80000000
#define PREP_ISA_IO_BUS 0x00000000
#define PREP_ISA_IO_SIZE 0x00800000
#define PREP_PCI_IO_PHYS 0x81000000
#define PREP_PCI_IO_BUS 0x01000000
#define PREP_PCI_IO_SIZE 0x3e800000
#define PREP_PCI_MEM_PHYS 0xc0000000
#define PREP_PCI_MEM_BUS 0x00000000
#define PREP_PCI_MEM_SIZE 0x3f000000
#define PREP_PCI_MEMORY_PHYS 0x00000000
#define PREP_PCI_MEMORY_BUS 0x80000000
#define PREP_PCI_MEMORY_SIZE 0x80000000
#define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */
#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */
#define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */
#define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */
#define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */
#define MEM_CONT2_ADR 0x800000f4 /* MPC107 Memory control config. 2 */
#define MEM_CONT3_ADR 0x800000f8 /* MPC107 Memory control config. 3 */
#define MEM_CONT4_ADR 0x800000fc /* MPC107 Memory control config. 4 */
#define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */
#define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */
#define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */
#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/
#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/
#define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */
#define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */
#define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */
#define XMEM_END2_ADR 0x8000009c /* MPC107 Extended mem. end addrs-lo*/
#define OUT_DRV_CONT 0x80000073 /* MPC107 Output Driver Control reg */
#define MEM_EN_ADR 0x800000a0 /* Memory bank enable */
#define PAGE_MODE 0x800000a3 /* MPC107 Page Mode Counter/Timer */
/*-----------------------------------------------------------------------
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_RESERVED0 0x0000 /* Reserved */
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
#define EXC_OFF_MACH_CHCK 0x0200 /* Machine Check */
#define EXC_OFF_DATA_STOR 0x0300 /* Data Storage */
#define EXC_OFF_INS_STOR 0x0400 /* Instruction Storage */
#define EXC_OFF_EXTERNAL 0x0500 /* External */
#define EXC_OFF_ALIGN 0x0600 /* Alignment */
#define EXC_OFF_PROGRAM 0x0700 /* Program */
#define EXC_OFF_FPUNAVAIL 0x0800 /* Floating-point Unavailable */
#define EXC_OFF_DECR 0x0900 /* Decrementer */
#define EXC_OFF_RESERVED1 0x0A00 /* Reserved */
#define EXC_OFF_RESERVED2 0x0B00 /* Reserved */
#define EXC_OFF_SYS_CALL 0x0C00 /* System Call */
#define EXC_OFF_TRACE 0x0D00 /* Trace */
#define EXC_OFF_FPUNASSIST 0x0E00 /* Floating-point Assist */
/* 0x0E10 - 0x0FFF are marked reserved in The PowerPC Architecture book */
/* these found in DINK code - may not apply to 8240*/
#define EXC_OFF_PMI 0x0F00 /* Performance Monitoring Interrupt */
#define EXC_OFF_VMXUI 0x0F20 /* VMX (AltiVec) Unavailable Interrupt */
/* 0x1000 - 0x2FFF are implementation specific */
/* these found in DINK code - may not apply to 8240 */
#define EXC_OFF_ITME 0x1000 /* Instruction Translation Miss Exception */
#define EXC_OFF_DLTME 0x1100 /* Data Load Translation Miss Exception */
#define EXC_OFF_DSTME 0x1200 /* Data Store Translation Miss Exception */
#define EXC_OFF_IABE 0x1300 /* Instruction Addr Breakpoint Exception */
#define EXC_OFF_SMIE 0x1400 /* System Management Interrupt Exception */
#define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/
#define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */
#define _START_OFFSET EXC_OFF_SYS_RESET
#define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */
#define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */
#define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */
#define MAP_A_CONFIG_DATA_LOW 0x0CFC /* Lower half of CONFIG_DAT for Map A */
#define MAP_B_CONFIG_ADDR_HIGH 0xfec0 /* Upper half of CONFIG_ADDR for Map B */
#define MAP_B_CONFIG_ADDR_LOW 0x0000 /* Lower half of CONFIG_ADDR for Map B */
#define MAP_B_CONFIG_DATA_HIGH 0xfee0 /* Upper half of CONFIG_DAT for Map B */
#define MAP_B_CONFIG_DATA_LOW 0x0000 /* Lower half of CONFIG_DAT for Map B */
#if defined(CONFIG_SYS_ADDR_MAP_A)
#define CONFIG_ADDR_HIGH MAP_A_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */
#define CONFIG_ADDR_LOW MAP_A_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
#define CONFIG_DATA_HIGH MAP_A_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */
#define CONFIG_DATA_LOW MAP_A_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
#else /* Assume Map B, default */
#define CONFIG_ADDR_HIGH MAP_B_CONFIG_ADDR_HIGH /* Upper half of CONFIG_ADDR */
#define CONFIG_ADDR_LOW MAP_B_CONFIG_ADDR_LOW /* Lower half of CONFIG_ADDR */
#define CONFIG_DATA_HIGH MAP_B_CONFIG_DATA_HIGH /* Upper half of CONFIG_DAT */
#define CONFIG_DATA_LOW MAP_B_CONFIG_DATA_LOW /* Lower half of CONFIG_DAT */
#endif
#define CONFIG_ADDR (CONFIG_ADDR_HIGH << 16 | CONFIG_ADDR_LOW)
#define CONFIG_DATA (CONFIG_DATA_HIGH << 16 | CONFIG_DATA_LOW)
/* Macros to write to config registers. addr should be a constant in all cases */
#define CONFIG_WRITE_BYTE( addr, data ) \
__asm__ __volatile__( \
" stwbrx %1, 0, %0\n \
sync\n \
stb %3, %4(%2)\n \
sync " \
: /* no output */ \
: "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
"b" (CONFIG_DATA), "r" (data), \
"n" ((addr) & 3));
#define CONFIG_WRITE_HALFWORD( addr, data ) \
__asm__ __volatile__( \
" stwbrx %1, 0, %0\n \
sync\n \
sthbrx %3, %4, %2\n \
sync " \
: /* no output */ \
: "r" (CONFIG_ADDR), "r" ((addr) & ~3), \
"r" (CONFIG_DATA), "r" (data), \
"b" ((addr) & 3));
/* this assumes it's writeing on word boundaries*/
#define CONFIG_WRITE_WORD( addr, data ) \
__asm__ __volatile__( \
" stwbrx %1, 0, %0\n \
sync\n \
stwbrx %3, 0, %2\n \
sync " \
: /* no output */ \
: "r" (CONFIG_ADDR), "r" (addr), \
"r" (CONFIG_DATA), "r" (data));
/* Configuration register reads*/
#define CONFIG_READ_BYTE( addr, reg ) \
__asm__ ( \
" stwbrx %1, 0, %2\n \
sync\n \
lbz %0, %4(%3)\n \
sync " \
: "=r" (reg) \
: "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
"b" (CONFIG_DATA), "n" ((addr) & 3));
#define CONFIG_READ_HALFWORD( addr, reg ) \
__asm__ ( \
" stwbrx %1, 0, %2\n \
sync\n \
lhbrx %0, %4, %3\n \
sync " \
: "=r" (reg) \
: "r" ((addr) & ~3), "r" (CONFIG_ADDR), \
"r" (CONFIG_DATA), \
"b" ((addr) & 3));
/* this assumes it's reading on word boundaries*/
#define CONFIG_READ_WORD( addr, reg ) \
__asm__ ( \
" stwbrx %1, 0, %2\n \
sync\n \
lwbrx %0, 0, %3\n \
sync " \
: "=r" (reg) \
: "r" (addr), "r" (CONFIG_ADDR),\
"r" (CONFIG_DATA));
/*
* configuration register 'addresses'.
* These are described in chaper 5 of the 8240 users manual.
* Where the register has an abreviation in the manual, this has
* been usaed here, otherwise a name in keeping with the norm has
* been invented.
* Note that some of these registers aren't documented in the manual.
*/
#define PCICR 0x80000004 /* PCI Command Register */
#define PCISR 0x80000006 /* PCI Status Register */
#define REVID 0x80000008 /* CPU revision id */
#define PIR 0x80000009 /* PCI Programming Interface Register */
#define PBCCR 0x8000000b /* PCI Base Class Code Register */
#define PCLSR 0x8000000c /* Processor Cache Line Size Register */
#define PLTR 0x8000000d /* PCI Latancy Timer Register */
#define PHTR 0x8000000e /* PCI Header Type Register */
#define BISTCTRL 0x8000000f /* BIST Control */
#define LMBAR 0x80000010 /* Local Base Address Register */
#define PCSRBAR 0x80000014 /* PCSR Base Address Register */
#define ILR 0x8000003c /* PCI Interrupt Line Register */
#define IPR 0x8000003d /* Interrupt Pin Register */
#define MINGNT 0x8000003e /* MIN GNI */
#define MAXLAT 0x8000003f /* MAX LAT */
#define PCIACR 0x80000046 /* PCI Arbiter Control Register */
#define PMCR1 0x80000070 /* Power management config. 1 */
#define PMCR2 0x80000072 /* Power management config. 2 */
#define ODCR 0x80000073 /* Output Driver Control Register */
#define CLKDCR 0x80000074 /* CLK Driver Control Register */
#if defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */
#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */
#endif
#define EUMBBAR 0x80000078 /* Embedded Utilities Memory Block Base Address Register */
#define EUMBBAR_VAL 0x80500000 /* PCI Relocation offset for EUMB region */
#define EUMBSIZE 0x00100000 /* Size of EUMB region */
#define MSAR1 0x80000080 /* Memory Starting Address Register 1 */
#define MSAR2 0x80000084 /* Memory Starting Address Register 2 */
#define EMSAR1 0x80000088 /* Extended Memory Starting Address Register 1*/
#define EMSAR2 0x8000008c /* Extended Memory Starting Address Register 2*/
#define MEAR1 0x80000090 /* Memory Ending Address Register 1 */
#define MEAR2 0x80000094 /* Memory Ending Address Register 2 */
#define EMEAR1 0x80000098 /* Extended Memory Ending Address Register 1 */
#define EMEAR2 0x8000009c /* Extended Memory Ending Address Register 2 */
#define MBER 0x800000a0 /* Memory bank Enable Register*/
#define MPMR 0x800000a3 /* Memory Page Mode Register (stores PGMAX) */
#define PICR1 0x800000a8 /* Processor Interface Configuration Register 1 */
#define PICR2 0x800000ac /* Processor Interface Configuration Register 2 */
#define ECCSBECR 0x800000b8 /* ECC Single-Bit Error Counter Register */
#define ECCSBETR 0x800000b8 /* ECC Single-Bit Error Trigger Register */
#define ERRENR1 0x800000c0 /* Error Enableing Register 1 */
#define ERRENR2 0x800000c4 /* Error Enableing Register 2 */
#define ERRDR1 0x800000c1 /* Error Detection Register 1 */
#define IPBESR 0x800000c3 /* Internal Processor Error Status Register */
#define ERRDR2 0x800000c5 /* Error Detection Register 2 */
#define PBESR 0x800000c7 /* PCI Bus Error Status Register */
#define PBEAR 0x800000c8 /* Processor/PCI Bus Error Status Register */
#define AMBOR 0x800000e0 /* Address Map B Options Register */
#define PCMBCR 0x800000e1 /* PCI/Memory Buffer Configuration */
#define MCCR1 0x800000f0 /* Memory Control Configuration Register 1 */
#define MCCR2 0x800000f4 /* Memory Control Configuration Register 2 */
#define MCCR3 0x800000f8 /* Memory Control Configuration Register 3 */
#define MCCR4 0x800000fc /* Memory Control Configuration Register 4 */
/* some values for some of the above */
#define PICR1_CF_APARK 0x00000008
#define PICR1_LE_MODE 0x00000020
#define PICR1_ST_GATH_EN 0x00000040
#if defined(CONFIG_MPC8240)
#define PICR1_EN_PCS 0x00000080 /* according to dink code, sets the 8240 to handle pci config space */
#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define PICR1_NO_BUSW_CK 0x00000080 /* no bus width check for flash writes */
#define PICR1_DEC 0x00000100 /* Time Base enable on 8245/8241 */
#define ERCR1 0x800000d0 /* Extended ROM Configuration Register 1 */
#define ERCR2 0x800000d4 /* Extended ROM Configuration Register 2 */
#define ERCR3 0x800000d8 /* Extended ROM Configuration Register 3 */
#define ERCR4 0x800000dc /* Extended ROM Configuration Register 4 */
#define MIOCR1 0x80000076 /* Miscellaneous I/O Control Register 1 */
#define MIOCR1_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */
#define MIOCR1_SHIFT 2
#define MIOCR2 0x80000077 /* Miscellaneous I/O Control Register 2 */
#define MIOCR2_ADR_X 0x80000074 /* Miscellaneous I/O Control Register 1 */
#define MIOCR2_SHIFT 3
#define ODCR_ADR_X 0x80000070 /* Output Driver Control register */
#define ODCR_SHIFT 3
#define PMCR2_ADR 0x80000072 /* Power Mgmnt Cfg 2 register */
#define PMCR2_ADR_X 0x80000070
#define PMCR2_SHIFT 3
#define PMCR1_ADR 0x80000070 /* Power Mgmnt Cfg 1 reister */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
#define PICR1_CF_DPARK 0x00000200
#define PICR1_MCP_EN 0x00000800
#define PICR1_FLASH_WR_EN 0x00001000
#ifdef CONFIG_MPC8240
#define PICR1_ADDRESS_MAP 0x00010000
#define PIRC1_MSK 0xff000000
#endif
#define PICR1_PROC_TYPE_MSK 0x00060000
#define PICR1_PROC_TYPE_603E 0x00040000
#define PICR1_RCS0 0x00100000
#define PICR2_CF_SNOOP_WS_MASK 0x000c0000
#define PICR2_CF_SNOOP_WS_0WS 0x00000000
#define PICR2_CF_SNOOP_WS_1WS 0x00040000
#define PICR2_CF_SNOOP_WS_2WS 0x00080000
#define PICR2_CF_SNOOP_WS_3WS 0x000c0000
#define PICR2_CF_APHASE_WS_MASK 0x0000000c
#define PICR2_CF_APHASE_WS_0WS 0x00000000
#define PICR2_CF_APHASE_WS_1WS 0x00000004
#define PICR2_CF_APHASE_WS_2WS 0x00000008
#define PICR2_CF_APHASE_WS_3WS 0x0000000c
#define MCCR1_ROMNAL_SHIFT 28
#define MCCR1_ROMNAL_MSK 0xf0000000
#define MCCR1_ROMFAL_SHIFT 23
#define MCCR1_ROMFAL_MSK 0x0f800000
#define MCCR1_DBUS_SIZE0 0x00400000
#define MCCR1_BURST 0x00100000
#define MCCR1_MEMGO 0x00080000
#define MCCR1_SREN 0x00040000
#if defined(CONFIG_MPC8240)
#define MCCR1_RAM_TYPE 0x00020000
#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define MCCR1_SDRAM_EN 0x00020000
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
#define MCCR1_PCKEN 0x00010000
#define MCCR1_BANK1ROW_SHIFT 2
#define MCCR1_BANK2ROW_SHIFT 4
#define MCCR1_BANK3ROW_SHIFT 6
#define MCCR1_BANK4ROW_SHIFT 8
#define MCCR1_BANK5ROW_SHIFT 10
#define MCCR1_BANK6ROW_SHIFT 12
#define MCCR1_BANK7ROW_SHIFT 14
#define MCCR2_TS_WAIT_TIMER_MSK 0xe0000000
#define MCCR2_TS_WAIT_TIMER_SHIFT 29
#define MCCR2_ASRISE_MSK 0x1e000000
#define MCCR2_ASRISE_SHIFT 25
#define MCCR2_ASFALL_MSK 0x01e00000
#define MCCR2_ASFALL_SHIFT 21
#define MCCR2_INLINE_PAR_NOT_ECC 0x00100000
#define MCCR2_WRITE_PARITY_CHK 0x00080000
#define MCCR2_INLFRD_PARECC_CHK_EN 0x00040000
#ifdef CONFIG_MPC8240
#define MCCR2_ECC_EN 0x00020000
#define MCCR2_EDO 0x00010000
#endif
#define MCCR2_REFINT_MSK 0x0000fffc
#define MCCR2_REFINT_SHIFT 2
#define MCCR2_RSV_PG 0x00000002
#define MCCR2_PMW_PAR 0x00000001
#define MCCR3_BSTOPRE2TO5_MSK 0xf0000000 /*BSTOPRE[2-5]*/
#define MCCR3_BSTOPRE2TO5_SHIFT 28
#define MCCR3_REFREC_MSK 0x0f000000
#define MCCR3_REFREC_SHIFT 24
#ifdef CONFIG_MPC8240
#define MCCR3_RDLAT_MSK 0x00f00000
#define MCCR3_RDLAT_SHIFT 20
#define MCCR3_CPX 0x00010000
#define MCCR3_RAS6P_MSK 0x00078000
#define MCCR3_RAS6P_SHIFT 15
#define MCCR3_CAS5_MSK 0x00007000
#define MCCR3_CAS5_SHIFT 12
#define MCCR3_CP4_MSK 0x00000e00
#define MCCR3_CP4_SHIFT 9
#define MCCR3_CAS3_MSK 0x000001c0
#define MCCR3_CAS3_SHIFT 6
#define MCCR3_RCD2_MSK 0x00000038
#define MCCR3_RCD2_SHIFT 3
#define MCCR3_RP1_MSK 0x00000007
#define MCCR3_RP1_SHIFT 0
#endif
#define MCCR4_PRETOACT_MSK 0xf0000000
#define MCCR4_PRETOACT_SHIFT 28
#define MCCR4_ACTTOPRE_MSK 0x0f000000
#define MCCR4_ACTTOPRE_SHIFT 24
#define MCCR4_WMODE 0x00800000
#define MCCR4_INLINE 0x00400000
#if defined(CONFIG_MPC8240)
#define MCCR4_BIT21 0x00200000 /* this include cos DINK code sets it- unknown function*/
#elif defined(CONFIG_MPC8245) || defined(CONFIG_MPC8241)
#define MCCR4_EXTROM 0x00200000 /* enables Extended ROM space */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
#define MCCR4_REGISTERED 0x00100000
#define MCCR4_BSTOPRE0TO1_MSK 0x000c0000 /*BSTOPRE[0-1]*/
#define MCCR4_BSTOPRE0TO1_SHIFT 18
#define MCCR4_REGDIMM 0x00008000
#define MCCR4_SDMODE_MSK 0x00007f00
#define MCCR4_SDMODE_SHIFT 8
#define MCCR4_ACTTORW_MSK 0x000000f0
#define MCCR4_ACTTORW_SHIFT 4
#define MCCR4_BSTOPRE6TO9_MSK 0x0000000f /*BSTOPRE[6-9]*/
#define MCCR4_BSTOPRE6TO9_SHIFT 0
#define MCCR4_DBUS_SIZE2_SHIFT 17
#define MICR_ADDR_MASK 0x0ff00000
#define MICR_ADDR_SHIFT 20
#define MICR_EADDR_MASK 0x30000000
#define MICR_EADDR_SHIFT 28
/*eumb and epic config*/
#define EPIC_FPR 0x00041000
#define EPIC_GCR 0x00041020
#define EPIC_EICR 0x00041030
#define EPIC_EVI 0x00041080
#define EPIC_PI 0x00041090
#define EPIC_SVR 0x000410E0
#define EPIC_TFRR 0x000410F0
/*
* Note the information for these is rather mangled in the 8240 manual.
* These are guesses.
*/
#define EPIC_GTCCR0 0x00041100
#define EPIC_GTCCR1 0x00041140
#define EPIC_GTCCR2 0x00041180
#define EPIC_GTCCR3 0x000411C0
#define EPIC_GTBCR0 0x00041110
#define EPIC_GTBCR1 0x00041150
#define EPIC_GTBCR2 0x00041190
#define EPIC_GTBCR3 0x000411D0
#define EPIC_GTVPR0 0x00041120
#define EPIC_GTVPR1 0x00041160
#define EPIC_GTVPR2 0x000411a0
#define EPIC_GTVPR3 0x000411e0
#define EPIC_GTDR0 0x00041130
#define EPIC_GTDR1 0x00041170
#define EPIC_GTDR2 0x000411b0
#define EPIC_GTDR3 0x000411f0
#define EPIC_IVPR0 0x00050200
#define EPIC_IVPR1 0x00050220
#define EPIC_IVPR2 0x00050240
#define EPIC_IVPR3 0x00050260
#define EPIC_IVPR4 0x00050280
#define EPIC_SVPR0 0x00050200
#define EPIC_SVPR1 0x00050220
#define EPIC_SVPR2 0x00050240
#define EPIC_SVPR3 0x00050260
#define EPIC_SVPR4 0x00050280
#define EPIC_SVPR5 0x000502A0
#define EPIC_SVPR6 0x000502C0
#define EPIC_SVPR7 0x000502E0
#define EPIC_SVPR8 0x00050300
#define EPIC_SVPR9 0x00050320
#define EPIC_SVPRa 0x00050340
#define EPIC_SVPRb 0x00050360
#define EPIC_SVPRc 0x00050380
#define EPIC_SVPRd 0x000503A0
#define EPIC_SVPRe 0x000503C0
#define EPIC_SVPRf 0x000503E0
/* MPC8240 Byte Swap/PCI Support Macros */
#define BYTE_SWAP_16_BIT(x) ( (((x) & 0x00ff) << 8) | ( (x) >> 8) )
#define LONGSWAP(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
(((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) )
#define PCISWAP(x) LONGSWAP(x)
#ifndef __ASSEMBLY__
/*
* MPC107 Support
*
*/
unsigned int mpc824x_mpc107_getreg(unsigned int regNum);
void mpc824x_mpc107_setreg(unsigned int regNum, unsigned int regVal);
void mpc824x_mpc107_write8(unsigned int address, unsigned char data);
void mpc824x_mpc107_write16(unsigned int address, unsigned short data);
void mpc824x_mpc107_write32(unsigned int address, unsigned int data);
unsigned char mpc824x_mpc107_read8(unsigned int address);
unsigned short mpc824x_mpc107_read16(unsigned int address);
unsigned int mpc824x_mpc107_read32(unsigned int address);
unsigned int mpc824x_eummbar_read(unsigned int regNum);
void mpc824x_eummbar_write(unsigned int regNum, unsigned int regVal);
#ifdef CONFIG_PCI
struct pci_controller;
void pci_cpm824x_init(struct pci_controller* hose);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __MPC824X_H__ */
|
1001-study-uboot
|
include/mpc824x.h
|
C
|
gpl3
| 21,757
|
/*
* (C) Copyright 2003
* Gerry Hamel, geh@ti.com, Texas Instruments
*
* Based on
* linux/drivers/usbd/usb-function.h - USB Function
*
* Copyright (c) 2000, 2001, 2002 Lineo
* Copyright (c) 2001 Hewlett Packard
*
* By:
* Stuart Lynne <sl@lineo.com>,
* Tom Rushworth <tbr@lineo.com>,
* Bruce Balden <balden@lineo.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
/* USB Descriptors - Create a complete description of all of the
* function driver capabilities. These map directly to the USB descriptors.
*
* This heirarchy is created by the functions drivers and is passed to the
* usb-device driver when the function driver is registered.
*
* device
* configuration
* interface
* alternate
* class
* class
* alternate
* endpoint
* endpoint
* interface
* alternate
* endpoint
* endpoint
* configuration
* interface
* alternate
* endpoint
* endpoint
*
*
* The configuration structures refer to the USB Configurations that will be
* made available to a USB HOST during the enumeration process.
*
* The USB HOST will select a configuration and optionally an interface with
* the usb set configuration and set interface commands.
*
* The selected interface (or the default interface if not specifically
* selected) will define the list of endpoints that will be used.
*
* The configuration and interfaces are stored in an array that is indexed
* by the specified configuratin or interface number minus one.
*
* A configuration number of zero is used to specify a return to the unconfigured
* state.
*
*/
#ifndef __USBDESCRIPTORS_H__
#define __USBDESCRIPTORS_H__
#include <asm/types.h>
/*
* communications class types
*
* c.f. CDC USB Class Definitions for Communications Devices
* c.f. WMCD USB CDC Subclass Specification for Wireless Mobile Communications Devices
*
*/
#define CLASS_BCD_VERSION 0x0110
/* c.f. CDC 4.1 Table 14 */
#define COMMUNICATIONS_DEVICE_CLASS 0x02
/* c.f. CDC 4.2 Table 15 */
#define COMMUNICATIONS_INTERFACE_CLASS_CONTROL 0x02
#define COMMUNICATIONS_INTERFACE_CLASS_DATA 0x0A
#define COMMUNICATIONS_INTERFACE_CLASS_VENDOR 0x0FF
/* c.f. CDC 4.3 Table 16 */
#define COMMUNICATIONS_NO_SUBCLASS 0x00
#define COMMUNICATIONS_DLCM_SUBCLASS 0x01
#define COMMUNICATIONS_ACM_SUBCLASS 0x02
#define COMMUNICATIONS_TCM_SUBCLASS 0x03
#define COMMUNICATIONS_MCCM_SUBCLASS 0x04
#define COMMUNICATIONS_CCM_SUBCLASS 0x05
#define COMMUNICATIONS_ENCM_SUBCLASS 0x06
#define COMMUNICATIONS_ANCM_SUBCLASS 0x07
/* c.f. WMCD 5.1 */
#define COMMUNICATIONS_WHCM_SUBCLASS 0x08
#define COMMUNICATIONS_DMM_SUBCLASS 0x09
#define COMMUNICATIONS_MDLM_SUBCLASS 0x0a
#define COMMUNICATIONS_OBEX_SUBCLASS 0x0b
/* c.f. CDC 4.4 Table 17 */
#define COMMUNICATIONS_NO_PROTOCOL 0x00
#define COMMUNICATIONS_V25TER_PROTOCOL 0x01 /*Common AT Hayes compatible*/
/* c.f. CDC 4.5 Table 18 */
#define DATA_INTERFACE_CLASS 0x0a
/* c.f. CDC 4.6 No Table */
#define DATA_INTERFACE_SUBCLASS_NONE 0x00 /* No subclass pertinent */
/* c.f. CDC 4.7 Table 19 */
#define DATA_INTERFACE_PROTOCOL_NONE 0x00 /* No class protcol required */
/* c.f. CDC 5.2.3 Table 24 */
#define CS_INTERFACE 0x24
#define CS_ENDPOINT 0x25
/*
* bDescriptorSubtypes
*
* c.f. CDC 5.2.3 Table 25
* c.f. WMCD 5.3 Table 5.3
*/
#define USB_ST_HEADER 0x00
#define USB_ST_CMF 0x01
#define USB_ST_ACMF 0x02
#define USB_ST_DLMF 0x03
#define USB_ST_TRF 0x04
#define USB_ST_TCLF 0x05
#define USB_ST_UF 0x06
#define USB_ST_CSF 0x07
#define USB_ST_TOMF 0x08
#define USB_ST_USBTF 0x09
#define USB_ST_NCT 0x0a
#define USB_ST_PUF 0x0b
#define USB_ST_EUF 0x0c
#define USB_ST_MCMF 0x0d
#define USB_ST_CCMF 0x0e
#define USB_ST_ENF 0x0f
#define USB_ST_ATMNF 0x10
#define USB_ST_WHCM 0x11
#define USB_ST_MDLM 0x12
#define USB_ST_MDLMD 0x13
#define USB_ST_DMM 0x14
#define USB_ST_OBEX 0x15
#define USB_ST_CS 0x16
#define USB_ST_CSD 0x17
#define USB_ST_TCM 0x18
/* endpoint modifiers
* static struct usb_endpoint_description function_default_A_1[] = {
*
* {this_endpoint: 0, attributes: CONTROL, max_size: 8, polling_interval: 0 },
* {this_endpoint: 1, attributes: BULK, max_size: 64, polling_interval: 0, direction: IN},
* {this_endpoint: 2, attributes: BULK, max_size: 64, polling_interval: 0, direction: OUT},
* {this_endpoint: 3, attributes: INTERRUPT, max_size: 8, polling_interval: 0},
*
*
*/
#define OUT 0x00
#define IN 0x80
#define CONTROL 0x00
#define ISOCHRONOUS 0x01
#define BULK 0x02
#define INTERRUPT 0x03
/* configuration modifiers
*/
#define BMATTRIBUTE_RESERVED 0x80
#define BMATTRIBUTE_SELF_POWERED 0x40
/*
* standard usb descriptor structures
*/
struct usb_endpoint_descriptor {
u8 bLength;
u8 bDescriptorType; /* 0x5 */
u8 bEndpointAddress;
u8 bmAttributes;
u16 wMaxPacketSize;
u8 bInterval;
} __attribute__ ((packed));
struct usb_interface_descriptor {
u8 bLength;
u8 bDescriptorType; /* 0x04 */
u8 bInterfaceNumber;
u8 bAlternateSetting;
u8 bNumEndpoints;
u8 bInterfaceClass;
u8 bInterfaceSubClass;
u8 bInterfaceProtocol;
u8 iInterface;
} __attribute__ ((packed));
struct usb_configuration_descriptor {
u8 bLength;
u8 bDescriptorType; /* 0x2 */
u16 wTotalLength;
u8 bNumInterfaces;
u8 bConfigurationValue;
u8 iConfiguration;
u8 bmAttributes;
u8 bMaxPower;
} __attribute__ ((packed));
struct usb_device_descriptor {
u8 bLength;
u8 bDescriptorType; /* 0x01 */
u16 bcdUSB;
u8 bDeviceClass;
u8 bDeviceSubClass;
u8 bDeviceProtocol;
u8 bMaxPacketSize0;
u16 idVendor;
u16 idProduct;
u16 bcdDevice;
u8 iManufacturer;
u8 iProduct;
u8 iSerialNumber;
u8 bNumConfigurations;
} __attribute__ ((packed));
struct usb_string_descriptor {
u8 bLength;
u8 bDescriptorType; /* 0x03 */
u16 wData[0];
} __attribute__ ((packed));
struct usb_generic_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubtype;
} __attribute__ ((packed));
/*
* communications class descriptor structures
*
* c.f. CDC 5.2 Table 25c
*/
struct usb_class_function_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype;
} __attribute__ ((packed));
struct usb_class_function_descriptor_generic {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype;
u8 bmCapabilities;
} __attribute__ ((packed));
struct usb_class_header_function_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x00 */
u16 bcdCDC;
} __attribute__ ((packed));
struct usb_class_call_management_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x01 */
u8 bmCapabilities;
u8 bDataInterface;
} __attribute__ ((packed));
struct usb_class_abstract_control_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x02 */
u8 bmCapabilities;
} __attribute__ ((packed));
struct usb_class_direct_line_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x03 */
} __attribute__ ((packed));
struct usb_class_telephone_ringer_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x04 */
u8 bRingerVolSeps;
u8 bNumRingerPatterns;
} __attribute__ ((packed));
struct usb_class_telephone_call_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x05 */
u8 bmCapabilities;
} __attribute__ ((packed));
struct usb_class_union_function_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x06 */
u8 bMasterInterface;
/* u8 bSlaveInterface0[0]; */
u8 bSlaveInterface0;
} __attribute__ ((packed));
struct usb_class_country_selection_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x07 */
u8 iCountryCodeRelDate;
u16 wCountryCode0[0];
} __attribute__ ((packed));
struct usb_class_telephone_operational_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x08 */
u8 bmCapabilities;
} __attribute__ ((packed));
struct usb_class_usb_terminal_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x09 */
u8 bEntityId;
u8 bInterfaceNo;
u8 bOutInterfaceNo;
u8 bmOptions;
u8 bChild0[0];
} __attribute__ ((packed));
struct usb_class_network_channel_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x0a */
u8 bEntityId;
u8 iName;
u8 bChannelIndex;
u8 bPhysicalInterface;
} __attribute__ ((packed));
struct usb_class_protocol_unit_function_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x0b */
u8 bEntityId;
u8 bProtocol;
u8 bChild0[0];
} __attribute__ ((packed));
struct usb_class_extension_unit_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x0c */
u8 bEntityId;
u8 bExtensionCode;
u8 iName;
u8 bChild0[0];
} __attribute__ ((packed));
struct usb_class_multi_channel_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x0d */
u8 bmCapabilities;
} __attribute__ ((packed));
struct usb_class_capi_control_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x0e */
u8 bmCapabilities;
} __attribute__ ((packed));
struct usb_class_ethernet_networking_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x0f */
u8 iMACAddress;
u32 bmEthernetStatistics;
u16 wMaxSegmentSize;
u16 wNumberMCFilters;
u8 bNumberPowerFilters;
} __attribute__ ((packed));
struct usb_class_atm_networking_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x10 */
u8 iEndSystermIdentifier;
u8 bmDataCapabilities;
u8 bmATMDeviceStatistics;
u16 wType2MaxSegmentSize;
u16 wType3MaxSegmentSize;
u16 wMaxVC;
} __attribute__ ((packed));
struct usb_class_mdlm_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x12 */
u16 bcdVersion;
u8 bGUID[16];
} __attribute__ ((packed));
struct usb_class_mdlmd_descriptor {
u8 bFunctionLength;
u8 bDescriptorType;
u8 bDescriptorSubtype; /* 0x13 */
u8 bGuidDescriptorType;
u8 bDetailData[0];
} __attribute__ ((packed));
/*
* HID class descriptor structures
*
* c.f. HID 6.2.1
*/
struct usb_class_hid_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 bcdCDC;
u8 bCountryCode;
u8 bNumDescriptors; /* 0x01 */
u8 bDescriptorType0;
u16 wDescriptorLength0;
/* optional descriptors are not supported. */
} __attribute__((packed));
struct usb_class_report_descriptor {
u8 bLength; /* dummy */
u8 bDescriptorType;
u16 wLength;
u8 bData[0];
} __attribute__((packed));
/*
* descriptor union structures
*/
struct usb_descriptor {
union {
struct usb_generic_descriptor generic;
struct usb_endpoint_descriptor endpoint;
struct usb_interface_descriptor interface;
struct usb_configuration_descriptor configuration;
struct usb_device_descriptor device;
struct usb_string_descriptor string;
} descriptor;
} __attribute__ ((packed));
struct usb_class_descriptor {
union {
struct usb_class_function_descriptor function;
struct usb_class_function_descriptor_generic generic;
struct usb_class_header_function_descriptor header_function;
struct usb_class_call_management_descriptor call_management;
struct usb_class_abstract_control_descriptor abstract_control;
struct usb_class_direct_line_descriptor direct_line;
struct usb_class_telephone_ringer_descriptor telephone_ringer;
struct usb_class_telephone_operational_descriptor telephone_operational;
struct usb_class_telephone_call_descriptor telephone_call;
struct usb_class_union_function_descriptor union_function;
struct usb_class_country_selection_descriptor country_selection;
struct usb_class_usb_terminal_descriptor usb_terminal;
struct usb_class_network_channel_descriptor network_channel;
struct usb_class_extension_unit_descriptor extension_unit;
struct usb_class_multi_channel_descriptor multi_channel;
struct usb_class_capi_control_descriptor capi_control;
struct usb_class_ethernet_networking_descriptor ethernet_networking;
struct usb_class_atm_networking_descriptor atm_networking;
struct usb_class_mdlm_descriptor mobile_direct;
struct usb_class_mdlmd_descriptor mobile_direct_detail;
struct usb_class_hid_descriptor hid;
} descriptor;
} __attribute__ ((packed));
#ifdef DEBUG
static inline void print_device_descriptor(struct usb_device_descriptor *d)
{
serial_printf("usb device descriptor \n");
serial_printf("\tbLength %2.2x\n", d->bLength);
serial_printf("\tbDescriptorType %2.2x\n", d->bDescriptorType);
serial_printf("\tbcdUSB %4.4x\n", d->bcdUSB);
serial_printf("\tbDeviceClass %2.2x\n", d->bDeviceClass);
serial_printf("\tbDeviceSubClass %2.2x\n", d->bDeviceSubClass);
serial_printf("\tbDeviceProtocol %2.2x\n", d->bDeviceProtocol);
serial_printf("\tbMaxPacketSize0 %2.2x\n", d->bMaxPacketSize0);
serial_printf("\tidVendor %4.4x\n", d->idVendor);
serial_printf("\tidProduct %4.4x\n", d->idProduct);
serial_printf("\tbcdDevice %4.4x\n", d->bcdDevice);
serial_printf("\tiManufacturer %2.2x\n", d->iManufacturer);
serial_printf("\tiProduct %2.2x\n", d->iProduct);
serial_printf("\tiSerialNumber %2.2x\n", d->iSerialNumber);
serial_printf("\tbNumConfigurations %2.2x\n", d->bNumConfigurations);
}
#else
/* stubs */
#define print_device_descriptor(d)
#endif /* DEBUG */
#endif
|
1001-study-uboot
|
include/usbdescriptors.h
|
C
|
gpl3
| 14,103
|
/*
* (C) Copyright 2002
* Stäubli Faverges - <www.staubli.com>
* Pierre AUBERT p.aubert@staubli.com
*
* (C) Copyright 2005
* Martin Krause TQ-Systems GmbH martin.krause@tqs.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Basic video support for SMI SM501 "Voyager" graphic controller
*/
#ifndef _SM501_H_
#define _SM501_H_
#define PCI_VENDOR_SM 0x126f
#define PCI_DEVICE_SM501 0x0501
typedef struct {
unsigned int Index;
unsigned int Value;
} SMI_REGS;
/* Board specific functions */
unsigned int board_video_init (void);
void board_validate_screen (unsigned int base);
const SMI_REGS *board_get_regs (void);
int board_get_width (void);
int board_get_height (void);
unsigned int board_video_get_fb (void);
#endif /* _SM501_H_ */
|
1001-study-uboot
|
include/sm501.h
|
C
|
gpl3
| 1,556
|
/*
* Declarations for System V style searching functions.
* Copyright (C) 1995-1999, 2000 Free Software Foundation, Inc.
* This file is part of the GNU C Library.
*
* The GNU C Library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* The GNU C Library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with the GNU C Library; if not, write to the Free
* Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA.
*/
/*
* Based on code from uClibc-0.9.30.3
* Extensions for use within U-Boot
* Copyright (C) 2010 Wolfgang Denk <wd@denx.de>
*/
#ifndef _SEARCH_H
#define _SEARCH_H 1
#include <stddef.h>
#define __set_errno(val) do { errno = val; } while (0)
/* Action which shall be performed in the call the hsearch. */
typedef enum {
FIND,
ENTER
} ACTION;
typedef struct entry {
const char *key;
char *data;
} ENTRY;
/* Opaque type for internal use. */
struct _ENTRY;
/*
* Family of hash table handling functions. The functions also
* have reentrant counterparts ending with _r. The non-reentrant
* functions all work on a signle internal hashing table.
*/
/* Data type for reentrant functions. */
struct hsearch_data {
struct _ENTRY *table;
unsigned int size;
unsigned int filled;
};
/* Create a new hashing table which will at most contain NEL elements. */
extern int hcreate_r(size_t __nel, struct hsearch_data *__htab);
/* Destroy current internal hashing table. */
extern void hdestroy_r(struct hsearch_data *__htab);
/*
* Search for entry matching ITEM.key in internal hash table. If
* ACTION is `FIND' return found entry or signal error by returning
* NULL. If ACTION is `ENTER' replace existing data (if any) with
* ITEM.data.
* */
extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval,
struct hsearch_data *__htab);
/*
* Search for an entry matching `MATCH'. Otherwise, Same semantics
* as hsearch_r().
*/
extern int hmatch_r(const char *__match, int __last_idx, ENTRY ** __retval,
struct hsearch_data *__htab);
/*
* Search for an entry whose key or data contains `MATCH'. Otherwise,
* Same semantics as hsearch_r().
*/
extern int hstrstr_r(const char *__match, int __last_idx, ENTRY ** __retval,
struct hsearch_data *__htab);
/* Search and delete entry matching ITEM.key in internal hash table. */
extern int hdelete_r(const char *__key, struct hsearch_data *__htab);
extern ssize_t hexport_r(struct hsearch_data *__htab,
const char __sep, char **__resp, size_t __size,
int argc, char * const argv[]);
extern int himport_r(struct hsearch_data *__htab,
const char *__env, size_t __size, const char __sep,
int __flag);
/* Flags for himport_r() */
#define H_NOCLEAR 1 /* do not clear hash table before importing */
#endif /* search.h */
|
1001-study-uboot
|
include/search.h
|
C
|
gpl3
| 3,271
|
/*
A version of malloc/free/realloc written by Doug Lea and released to the
public domain. Send questions/comments/complaints/performance data
to dl@cs.oswego.edu
* VERSION 2.6.6 Sun Mar 5 19:10:03 2000 Doug Lea (dl at gee)
Note: There may be an updated version of this malloc obtainable at
ftp://g.oswego.edu/pub/misc/malloc.c
Check before installing!
* Why use this malloc?
This is not the fastest, most space-conserving, most portable, or
most tunable malloc ever written. However it is among the fastest
while also being among the most space-conserving, portable and tunable.
Consistent balance across these factors results in a good general-purpose
allocator. For a high-level description, see
http://g.oswego.edu/dl/html/malloc.html
* Synopsis of public routines
(Much fuller descriptions are contained in the program documentation below.)
malloc(size_t n);
Return a pointer to a newly allocated chunk of at least n bytes, or null
if no space is available.
free(Void_t* p);
Release the chunk of memory pointed to by p, or no effect if p is null.
realloc(Void_t* p, size_t n);
Return a pointer to a chunk of size n that contains the same data
as does chunk p up to the minimum of (n, p's size) bytes, or null
if no space is available. The returned pointer may or may not be
the same as p. If p is null, equivalent to malloc. Unless the
#define REALLOC_ZERO_BYTES_FREES below is set, realloc with a
size argument of zero (re)allocates a minimum-sized chunk.
memalign(size_t alignment, size_t n);
Return a pointer to a newly allocated chunk of n bytes, aligned
in accord with the alignment argument, which must be a power of
two.
valloc(size_t n);
Equivalent to memalign(pagesize, n), where pagesize is the page
size of the system (or as near to this as can be figured out from
all the includes/defines below.)
pvalloc(size_t n);
Equivalent to valloc(minimum-page-that-holds(n)), that is,
round up n to nearest pagesize.
calloc(size_t unit, size_t quantity);
Returns a pointer to quantity * unit bytes, with all locations
set to zero.
cfree(Void_t* p);
Equivalent to free(p).
malloc_trim(size_t pad);
Release all but pad bytes of freed top-most memory back
to the system. Return 1 if successful, else 0.
malloc_usable_size(Void_t* p);
Report the number usable allocated bytes associated with allocated
chunk p. This may or may not report more bytes than were requested,
due to alignment and minimum size constraints.
malloc_stats();
Prints brief summary statistics on stderr.
mallinfo()
Returns (by copy) a struct containing various summary statistics.
mallopt(int parameter_number, int parameter_value)
Changes one of the tunable parameters described below. Returns
1 if successful in changing the parameter, else 0.
* Vital statistics:
Alignment: 8-byte
8 byte alignment is currently hardwired into the design. This
seems to suffice for all current machines and C compilers.
Assumed pointer representation: 4 or 8 bytes
Code for 8-byte pointers is untested by me but has worked
reliably by Wolfram Gloger, who contributed most of the
changes supporting this.
Assumed size_t representation: 4 or 8 bytes
Note that size_t is allowed to be 4 bytes even if pointers are 8.
Minimum overhead per allocated chunk: 4 or 8 bytes
Each malloced chunk has a hidden overhead of 4 bytes holding size
and status information.
Minimum allocated size: 4-byte ptrs: 16 bytes (including 4 overhead)
8-byte ptrs: 24/32 bytes (including, 4/8 overhead)
When a chunk is freed, 12 (for 4byte ptrs) or 20 (for 8 byte
ptrs but 4 byte size) or 24 (for 8/8) additional bytes are
needed; 4 (8) for a trailing size field
and 8 (16) bytes for free list pointers. Thus, the minimum
allocatable size is 16/24/32 bytes.
Even a request for zero bytes (i.e., malloc(0)) returns a
pointer to something of the minimum allocatable size.
Maximum allocated size: 4-byte size_t: 2^31 - 8 bytes
8-byte size_t: 2^63 - 16 bytes
It is assumed that (possibly signed) size_t bit values suffice to
represent chunk sizes. `Possibly signed' is due to the fact
that `size_t' may be defined on a system as either a signed or
an unsigned type. To be conservative, values that would appear
as negative numbers are avoided.
Requests for sizes with a negative sign bit when the request
size is treaded as a long will return null.
Maximum overhead wastage per allocated chunk: normally 15 bytes
Alignnment demands, plus the minimum allocatable size restriction
make the normal worst-case wastage 15 bytes (i.e., up to 15
more bytes will be allocated than were requested in malloc), with
two exceptions:
1. Because requests for zero bytes allocate non-zero space,
the worst case wastage for a request of zero bytes is 24 bytes.
2. For requests >= mmap_threshold that are serviced via
mmap(), the worst case wastage is 8 bytes plus the remainder
from a system page (the minimal mmap unit); typically 4096 bytes.
* Limitations
Here are some features that are NOT currently supported
* No user-definable hooks for callbacks and the like.
* No automated mechanism for fully checking that all accesses
to malloced memory stay within their bounds.
* No support for compaction.
* Synopsis of compile-time options:
People have reported using previous versions of this malloc on all
versions of Unix, sometimes by tweaking some of the defines
below. It has been tested most extensively on Solaris and
Linux. It is also reported to work on WIN32 platforms.
People have also reported adapting this malloc for use in
stand-alone embedded systems.
The implementation is in straight, hand-tuned ANSI C. Among other
consequences, it uses a lot of macros. Because of this, to be at
all usable, this code should be compiled using an optimizing compiler
(for example gcc -O2) that can simplify expressions and control
paths.
__STD_C (default: derived from C compiler defines)
Nonzero if using ANSI-standard C compiler, a C++ compiler, or
a C compiler sufficiently close to ANSI to get away with it.
DEBUG (default: NOT defined)
Define to enable debugging. Adds fairly extensive assertion-based
checking to help track down memory errors, but noticeably slows down
execution.
REALLOC_ZERO_BYTES_FREES (default: NOT defined)
Define this if you think that realloc(p, 0) should be equivalent
to free(p). Otherwise, since malloc returns a unique pointer for
malloc(0), so does realloc(p, 0).
HAVE_MEMCPY (default: defined)
Define if you are not otherwise using ANSI STD C, but still
have memcpy and memset in your C library and want to use them.
Otherwise, simple internal versions are supplied.
USE_MEMCPY (default: 1 if HAVE_MEMCPY is defined, 0 otherwise)
Define as 1 if you want the C library versions of memset and
memcpy called in realloc and calloc (otherwise macro versions are used).
At least on some platforms, the simple macro versions usually
outperform libc versions.
HAVE_MMAP (default: defined as 1)
Define to non-zero to optionally make malloc() use mmap() to
allocate very large blocks.
HAVE_MREMAP (default: defined as 0 unless Linux libc set)
Define to non-zero to optionally make realloc() use mremap() to
reallocate very large blocks.
malloc_getpagesize (default: derived from system #includes)
Either a constant or routine call returning the system page size.
HAVE_USR_INCLUDE_MALLOC_H (default: NOT defined)
Optionally define if you are on a system with a /usr/include/malloc.h
that declares struct mallinfo. It is not at all necessary to
define this even if you do, but will ensure consistency.
INTERNAL_SIZE_T (default: size_t)
Define to a 32-bit type (probably `unsigned int') if you are on a
64-bit machine, yet do not want or need to allow malloc requests of
greater than 2^31 to be handled. This saves space, especially for
very small chunks.
INTERNAL_LINUX_C_LIB (default: NOT defined)
Defined only when compiled as part of Linux libc.
Also note that there is some odd internal name-mangling via defines
(for example, internally, `malloc' is named `mALLOc') needed
when compiling in this case. These look funny but don't otherwise
affect anything.
WIN32 (default: undefined)
Define this on MS win (95, nt) platforms to compile in sbrk emulation.
LACKS_UNISTD_H (default: undefined if not WIN32)
Define this if your system does not have a <unistd.h>.
LACKS_SYS_PARAM_H (default: undefined if not WIN32)
Define this if your system does not have a <sys/param.h>.
MORECORE (default: sbrk)
The name of the routine to call to obtain more memory from the system.
MORECORE_FAILURE (default: -1)
The value returned upon failure of MORECORE.
MORECORE_CLEARS (default 1)
True (1) if the routine mapped to MORECORE zeroes out memory (which
holds for sbrk).
DEFAULT_TRIM_THRESHOLD
DEFAULT_TOP_PAD
DEFAULT_MMAP_THRESHOLD
DEFAULT_MMAP_MAX
Default values of tunable parameters (described in detail below)
controlling interaction with host system routines (sbrk, mmap, etc).
These values may also be changed dynamically via mallopt(). The
preset defaults are those that give best performance for typical
programs/systems.
USE_DL_PREFIX (default: undefined)
Prefix all public routines with the string 'dl'. Useful to
quickly avoid procedure declaration conflicts and linker symbol
conflicts with existing memory allocation routines.
*/
#ifndef __MALLOC_H__
#define __MALLOC_H__
/* Preliminaries */
#ifndef __STD_C
#ifdef __STDC__
#define __STD_C 1
#else
#if __cplusplus
#define __STD_C 1
#else
#define __STD_C 0
#endif /*__cplusplus*/
#endif /*__STDC__*/
#endif /*__STD_C*/
#ifndef Void_t
#if (__STD_C || defined(WIN32))
#define Void_t void
#else
#define Void_t char
#endif
#endif /*Void_t*/
#if __STD_C
#include <linux/stddef.h> /* for size_t */
#else
#include <sys/types.h>
#endif /* __STD_C */
#ifdef __cplusplus
extern "C" {
#endif
#if 0 /* not for U-Boot */
#include <stdio.h> /* needed for malloc_stats */
#endif
/*
Compile-time options
*/
/*
Debugging:
Because freed chunks may be overwritten with link fields, this
malloc will often die when freed memory is overwritten by user
programs. This can be very effective (albeit in an annoying way)
in helping track down dangling pointers.
If you compile with -DDEBUG, a number of assertion checks are
enabled that will catch more memory errors. You probably won't be
able to make much sense of the actual assertion errors, but they
should help you locate incorrectly overwritten memory. The
checking is fairly extensive, and will slow down execution
noticeably. Calling malloc_stats or mallinfo with DEBUG set will
attempt to check every non-mmapped allocated and free chunk in the
course of computing the summmaries. (By nature, mmapped regions
cannot be checked very much automatically.)
Setting DEBUG may also be helpful if you are trying to modify
this code. The assertions in the check routines spell out in more
detail the assumptions and invariants underlying the algorithms.
*/
/*
INTERNAL_SIZE_T is the word-size used for internal bookkeeping
of chunk sizes. On a 64-bit machine, you can reduce malloc
overhead by defining INTERNAL_SIZE_T to be a 32 bit `unsigned int'
at the expense of not being able to handle requests greater than
2^31. This limitation is hardly ever a concern; you are encouraged
to set this. However, the default version is the same as size_t.
*/
#ifndef INTERNAL_SIZE_T
#define INTERNAL_SIZE_T size_t
#endif
/*
REALLOC_ZERO_BYTES_FREES should be set if a call to
realloc with zero bytes should be the same as a call to free.
Some people think it should. Otherwise, since this malloc
returns a unique pointer for malloc(0), so does realloc(p, 0).
*/
/* #define REALLOC_ZERO_BYTES_FREES */
/*
WIN32 causes an emulation of sbrk to be compiled in
mmap-based options are not currently supported in WIN32.
*/
/* #define WIN32 */
#ifdef WIN32
#define MORECORE wsbrk
#define HAVE_MMAP 0
#define LACKS_UNISTD_H
#define LACKS_SYS_PARAM_H
/*
Include 'windows.h' to get the necessary declarations for the
Microsoft Visual C++ data structures and routines used in the 'sbrk'
emulation.
Define WIN32_LEAN_AND_MEAN so that only the essential Microsoft
Visual C++ header files are included.
*/
#define WIN32_LEAN_AND_MEAN
#include <windows.h>
#endif
/*
HAVE_MEMCPY should be defined if you are not otherwise using
ANSI STD C, but still have memcpy and memset in your C library
and want to use them in calloc and realloc. Otherwise simple
macro versions are defined here.
USE_MEMCPY should be defined as 1 if you actually want to
have memset and memcpy called. People report that the macro
versions are often enough faster than libc versions on many
systems that it is better to use them.
*/
#define HAVE_MEMCPY
#ifndef USE_MEMCPY
#ifdef HAVE_MEMCPY
#define USE_MEMCPY 1
#else
#define USE_MEMCPY 0
#endif
#endif
#if (__STD_C || defined(HAVE_MEMCPY))
#if __STD_C
void* memset(void*, int, size_t);
void* memcpy(void*, const void*, size_t);
#else
#ifdef WIN32
/* On Win32 platforms, 'memset()' and 'memcpy()' are already declared in */
/* 'windows.h' */
#else
Void_t* memset();
Void_t* memcpy();
#endif
#endif
#endif
#if USE_MEMCPY
/* The following macros are only invoked with (2n+1)-multiples of
INTERNAL_SIZE_T units, with a positive integer n. This is exploited
for fast inline execution when n is small. */
#define MALLOC_ZERO(charp, nbytes) \
do { \
INTERNAL_SIZE_T mzsz = (nbytes); \
if(mzsz <= 9*sizeof(mzsz)) { \
INTERNAL_SIZE_T* mz = (INTERNAL_SIZE_T*) (charp); \
if(mzsz >= 5*sizeof(mzsz)) { *mz++ = 0; \
*mz++ = 0; \
if(mzsz >= 7*sizeof(mzsz)) { *mz++ = 0; \
*mz++ = 0; \
if(mzsz >= 9*sizeof(mzsz)) { *mz++ = 0; \
*mz++ = 0; }}} \
*mz++ = 0; \
*mz++ = 0; \
*mz = 0; \
} else memset((charp), 0, mzsz); \
} while(0)
#define MALLOC_COPY(dest,src,nbytes) \
do { \
INTERNAL_SIZE_T mcsz = (nbytes); \
if(mcsz <= 9*sizeof(mcsz)) { \
INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) (src); \
INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) (dest); \
if(mcsz >= 5*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \
*mcdst++ = *mcsrc++; \
if(mcsz >= 7*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \
*mcdst++ = *mcsrc++; \
if(mcsz >= 9*sizeof(mcsz)) { *mcdst++ = *mcsrc++; \
*mcdst++ = *mcsrc++; }}} \
*mcdst++ = *mcsrc++; \
*mcdst++ = *mcsrc++; \
*mcdst = *mcsrc ; \
} else memcpy(dest, src, mcsz); \
} while(0)
#else /* !USE_MEMCPY */
/* Use Duff's device for good zeroing/copying performance. */
#define MALLOC_ZERO(charp, nbytes) \
do { \
INTERNAL_SIZE_T* mzp = (INTERNAL_SIZE_T*)(charp); \
long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \
if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \
switch (mctmp) { \
case 0: for(;;) { *mzp++ = 0; \
case 7: *mzp++ = 0; \
case 6: *mzp++ = 0; \
case 5: *mzp++ = 0; \
case 4: *mzp++ = 0; \
case 3: *mzp++ = 0; \
case 2: *mzp++ = 0; \
case 1: *mzp++ = 0; if(mcn <= 0) break; mcn--; } \
} \
} while(0)
#define MALLOC_COPY(dest,src,nbytes) \
do { \
INTERNAL_SIZE_T* mcsrc = (INTERNAL_SIZE_T*) src; \
INTERNAL_SIZE_T* mcdst = (INTERNAL_SIZE_T*) dest; \
long mctmp = (nbytes)/sizeof(INTERNAL_SIZE_T), mcn; \
if (mctmp < 8) mcn = 0; else { mcn = (mctmp-1)/8; mctmp %= 8; } \
switch (mctmp) { \
case 0: for(;;) { *mcdst++ = *mcsrc++; \
case 7: *mcdst++ = *mcsrc++; \
case 6: *mcdst++ = *mcsrc++; \
case 5: *mcdst++ = *mcsrc++; \
case 4: *mcdst++ = *mcsrc++; \
case 3: *mcdst++ = *mcsrc++; \
case 2: *mcdst++ = *mcsrc++; \
case 1: *mcdst++ = *mcsrc++; if(mcn <= 0) break; mcn--; } \
} \
} while(0)
#endif
/*
Define HAVE_MMAP to optionally make malloc() use mmap() to
allocate very large blocks. These will be returned to the
operating system immediately after a free().
*/
/***
#ifndef HAVE_MMAP
#define HAVE_MMAP 1
#endif
***/
#undef HAVE_MMAP /* Not available for U-Boot */
/*
Define HAVE_MREMAP to make realloc() use mremap() to re-allocate
large blocks. This is currently only possible on Linux with
kernel versions newer than 1.3.77.
*/
/***
#ifndef HAVE_MREMAP
#ifdef INTERNAL_LINUX_C_LIB
#define HAVE_MREMAP 1
#else
#define HAVE_MREMAP 0
#endif
#endif
***/
#undef HAVE_MREMAP /* Not available for U-Boot */
#if HAVE_MMAP
#include <unistd.h>
#include <fcntl.h>
#include <sys/mman.h>
#if !defined(MAP_ANONYMOUS) && defined(MAP_ANON)
#define MAP_ANONYMOUS MAP_ANON
#endif
#endif /* HAVE_MMAP */
/*
Access to system page size. To the extent possible, this malloc
manages memory from the system in page-size units.
The following mechanics for getpagesize were adapted from
bsd/gnu getpagesize.h
*/
#define LACKS_UNISTD_H /* Shortcut for U-Boot */
#define malloc_getpagesize 4096
#ifndef LACKS_UNISTD_H
# include <unistd.h>
#endif
#ifndef malloc_getpagesize
# ifdef _SC_PAGESIZE /* some SVR4 systems omit an underscore */
# ifndef _SC_PAGE_SIZE
# define _SC_PAGE_SIZE _SC_PAGESIZE
# endif
# endif
# ifdef _SC_PAGE_SIZE
# define malloc_getpagesize sysconf(_SC_PAGE_SIZE)
# else
# if defined(BSD) || defined(DGUX) || defined(HAVE_GETPAGESIZE)
extern size_t getpagesize();
# define malloc_getpagesize getpagesize()
# else
# ifdef WIN32
# define malloc_getpagesize (4096) /* TBD: Use 'GetSystemInfo' instead */
# else
# ifndef LACKS_SYS_PARAM_H
# include <sys/param.h>
# endif
# ifdef EXEC_PAGESIZE
# define malloc_getpagesize EXEC_PAGESIZE
# else
# ifdef NBPG
# ifndef CLSIZE
# define malloc_getpagesize NBPG
# else
# define malloc_getpagesize (NBPG * CLSIZE)
# endif
# else
# ifdef NBPC
# define malloc_getpagesize NBPC
# else
# ifdef PAGESIZE
# define malloc_getpagesize PAGESIZE
# else
# define malloc_getpagesize (4096) /* just guess */
# endif
# endif
# endif
# endif
# endif
# endif
# endif
#endif
/*
This version of malloc supports the standard SVID/XPG mallinfo
routine that returns a struct containing the same kind of
information you can get from malloc_stats. It should work on
any SVID/XPG compliant system that has a /usr/include/malloc.h
defining struct mallinfo. (If you'd like to install such a thing
yourself, cut out the preliminary declarations as described above
and below and save them in a malloc.h file. But there's no
compelling reason to bother to do this.)
The main declaration needed is the mallinfo struct that is returned
(by-copy) by mallinfo(). The SVID/XPG malloinfo struct contains a
bunch of fields, most of which are not even meaningful in this
version of malloc. Some of these fields are are instead filled by
mallinfo() with other numbers that might possibly be of interest.
HAVE_USR_INCLUDE_MALLOC_H should be set if you have a
/usr/include/malloc.h file that includes a declaration of struct
mallinfo. If so, it is included; else an SVID2/XPG2 compliant
version is declared below. These must be precisely the same for
mallinfo() to work.
*/
/* #define HAVE_USR_INCLUDE_MALLOC_H */
#if HAVE_USR_INCLUDE_MALLOC_H
#include "/usr/include/malloc.h"
#else
/* SVID2/XPG mallinfo structure */
struct mallinfo {
int arena; /* total space allocated from system */
int ordblks; /* number of non-inuse chunks */
int smblks; /* unused -- always zero */
int hblks; /* number of mmapped regions */
int hblkhd; /* total space in mmapped regions */
int usmblks; /* unused -- always zero */
int fsmblks; /* unused -- always zero */
int uordblks; /* total allocated space */
int fordblks; /* total non-inuse space */
int keepcost; /* top-most, releasable (via malloc_trim) space */
};
/* SVID2/XPG mallopt options */
#define M_MXFAST 1 /* UNUSED in this malloc */
#define M_NLBLKS 2 /* UNUSED in this malloc */
#define M_GRAIN 3 /* UNUSED in this malloc */
#define M_KEEP 4 /* UNUSED in this malloc */
#endif
/* mallopt options that actually do something */
#define M_TRIM_THRESHOLD -1
#define M_TOP_PAD -2
#define M_MMAP_THRESHOLD -3
#define M_MMAP_MAX -4
#ifndef DEFAULT_TRIM_THRESHOLD
#define DEFAULT_TRIM_THRESHOLD (128 * 1024)
#endif
/*
M_TRIM_THRESHOLD is the maximum amount of unused top-most memory
to keep before releasing via malloc_trim in free().
Automatic trimming is mainly useful in long-lived programs.
Because trimming via sbrk can be slow on some systems, and can
sometimes be wasteful (in cases where programs immediately
afterward allocate more large chunks) the value should be high
enough so that your overall system performance would improve by
releasing.
The trim threshold and the mmap control parameters (see below)
can be traded off with one another. Trimming and mmapping are
two different ways of releasing unused memory back to the
system. Between these two, it is often possible to keep
system-level demands of a long-lived program down to a bare
minimum. For example, in one test suite of sessions measuring
the XF86 X server on Linux, using a trim threshold of 128K and a
mmap threshold of 192K led to near-minimal long term resource
consumption.
If you are using this malloc in a long-lived program, it should
pay to experiment with these values. As a rough guide, you
might set to a value close to the average size of a process
(program) running on your system. Releasing this much memory
would allow such a process to run in memory. Generally, it's
worth it to tune for trimming rather tham memory mapping when a
program undergoes phases where several large chunks are
allocated and released in ways that can reuse each other's
storage, perhaps mixed with phases where there are no such
chunks at all. And in well-behaved long-lived programs,
controlling release of large blocks via trimming versus mapping
is usually faster.
However, in most programs, these parameters serve mainly as
protection against the system-level effects of carrying around
massive amounts of unneeded memory. Since frequent calls to
sbrk, mmap, and munmap otherwise degrade performance, the default
parameters are set to relatively high values that serve only as
safeguards.
The default trim value is high enough to cause trimming only in
fairly extreme (by current memory consumption standards) cases.
It must be greater than page size to have any useful effect. To
disable trimming completely, you can set to (unsigned long)(-1);
*/
#ifndef DEFAULT_TOP_PAD
#define DEFAULT_TOP_PAD (0)
#endif
/*
M_TOP_PAD is the amount of extra `padding' space to allocate or
retain whenever sbrk is called. It is used in two ways internally:
* When sbrk is called to extend the top of the arena to satisfy
a new malloc request, this much padding is added to the sbrk
request.
* When malloc_trim is called automatically from free(),
it is used as the `pad' argument.
In both cases, the actual amount of padding is rounded
so that the end of the arena is always a system page boundary.
The main reason for using padding is to avoid calling sbrk so
often. Having even a small pad greatly reduces the likelihood
that nearly every malloc request during program start-up (or
after trimming) will invoke sbrk, which needlessly wastes
time.
Automatic rounding-up to page-size units is normally sufficient
to avoid measurable overhead, so the default is 0. However, in
systems where sbrk is relatively slow, it can pay to increase
this value, at the expense of carrying around more memory than
the program needs.
*/
#ifndef DEFAULT_MMAP_THRESHOLD
#define DEFAULT_MMAP_THRESHOLD (128 * 1024)
#endif
/*
M_MMAP_THRESHOLD is the request size threshold for using mmap()
to service a request. Requests of at least this size that cannot
be allocated using already-existing space will be serviced via mmap.
(If enough normal freed space already exists it is used instead.)
Using mmap segregates relatively large chunks of memory so that
they can be individually obtained and released from the host
system. A request serviced through mmap is never reused by any
other request (at least not directly; the system may just so
happen to remap successive requests to the same locations).
Segregating space in this way has the benefit that mmapped space
can ALWAYS be individually released back to the system, which
helps keep the system level memory demands of a long-lived
program low. Mapped memory can never become `locked' between
other chunks, as can happen with normally allocated chunks, which
menas that even trimming via malloc_trim would not release them.
However, it has the disadvantages that:
1. The space cannot be reclaimed, consolidated, and then
used to service later requests, as happens with normal chunks.
2. It can lead to more wastage because of mmap page alignment
requirements
3. It causes malloc performance to be more dependent on host
system memory management support routines which may vary in
implementation quality and may impose arbitrary
limitations. Generally, servicing a request via normal
malloc steps is faster than going through a system's mmap.
All together, these considerations should lead you to use mmap
only for relatively large requests.
*/
#ifndef DEFAULT_MMAP_MAX
#if HAVE_MMAP
#define DEFAULT_MMAP_MAX (64)
#else
#define DEFAULT_MMAP_MAX (0)
#endif
#endif
/*
M_MMAP_MAX is the maximum number of requests to simultaneously
service using mmap. This parameter exists because:
1. Some systems have a limited number of internal tables for
use by mmap.
2. In most systems, overreliance on mmap can degrade overall
performance.
3. If a program allocates many large regions, it is probably
better off using normal sbrk-based allocation routines that
can reclaim and reallocate normal heap memory. Using a
small value allows transition into this mode after the
first few allocations.
Setting to 0 disables all use of mmap. If HAVE_MMAP is not set,
the default value is 0, and attempts to set it to non-zero values
in mallopt will fail.
*/
/*
USE_DL_PREFIX will prefix all public routines with the string 'dl'.
Useful to quickly avoid procedure declaration conflicts and linker
symbol conflicts with existing memory allocation routines.
*/
/* #define USE_DL_PREFIX */
/*
Special defines for linux libc
Except when compiled using these special defines for Linux libc
using weak aliases, this malloc is NOT designed to work in
multithreaded applications. No semaphores or other concurrency
control are provided to ensure that multiple malloc or free calls
don't run at the same time, which could be disasterous. A single
semaphore could be used across malloc, realloc, and free (which is
essentially the effect of the linux weak alias approach). It would
be hard to obtain finer granularity.
*/
#ifdef INTERNAL_LINUX_C_LIB
#if __STD_C
Void_t * __default_morecore_init (ptrdiff_t);
Void_t *(*__morecore)(ptrdiff_t) = __default_morecore_init;
#else
Void_t * __default_morecore_init ();
Void_t *(*__morecore)() = __default_morecore_init;
#endif
#define MORECORE (*__morecore)
#define MORECORE_FAILURE 0
#define MORECORE_CLEARS 1
#else /* INTERNAL_LINUX_C_LIB */
#if __STD_C
extern Void_t* sbrk(ptrdiff_t);
#else
extern Void_t* sbrk();
#endif
#ifndef MORECORE
#define MORECORE sbrk
#endif
#ifndef MORECORE_FAILURE
#define MORECORE_FAILURE -1
#endif
#ifndef MORECORE_CLEARS
#define MORECORE_CLEARS 1
#endif
#endif /* INTERNAL_LINUX_C_LIB */
#if defined(INTERNAL_LINUX_C_LIB) && defined(__ELF__)
#define cALLOc __libc_calloc
#define fREe __libc_free
#define mALLOc __libc_malloc
#define mEMALIGn __libc_memalign
#define rEALLOc __libc_realloc
#define vALLOc __libc_valloc
#define pvALLOc __libc_pvalloc
#define mALLINFo __libc_mallinfo
#define mALLOPt __libc_mallopt
#pragma weak calloc = __libc_calloc
#pragma weak free = __libc_free
#pragma weak cfree = __libc_free
#pragma weak malloc = __libc_malloc
#pragma weak memalign = __libc_memalign
#pragma weak realloc = __libc_realloc
#pragma weak valloc = __libc_valloc
#pragma weak pvalloc = __libc_pvalloc
#pragma weak mallinfo = __libc_mallinfo
#pragma weak mallopt = __libc_mallopt
#else
#ifdef USE_DL_PREFIX
#define cALLOc dlcalloc
#define fREe dlfree
#define mALLOc dlmalloc
#define mEMALIGn dlmemalign
#define rEALLOc dlrealloc
#define vALLOc dlvalloc
#define pvALLOc dlpvalloc
#define mALLINFo dlmallinfo
#define mALLOPt dlmallopt
#else /* USE_DL_PREFIX */
#define cALLOc calloc
#define fREe free
#define mALLOc malloc
#define mEMALIGn memalign
#define rEALLOc realloc
#define vALLOc valloc
#define pvALLOc pvalloc
#define mALLINFo mallinfo
#define mALLOPt mallopt
#endif /* USE_DL_PREFIX */
#endif
/* Public routines */
#if __STD_C
Void_t* mALLOc(size_t);
void fREe(Void_t*);
Void_t* rEALLOc(Void_t*, size_t);
Void_t* mEMALIGn(size_t, size_t);
Void_t* vALLOc(size_t);
Void_t* pvALLOc(size_t);
Void_t* cALLOc(size_t, size_t);
void cfree(Void_t*);
int malloc_trim(size_t);
size_t malloc_usable_size(Void_t*);
void malloc_stats(void);
int mALLOPt(int, int);
struct mallinfo mALLINFo(void);
#else
Void_t* mALLOc();
void fREe();
Void_t* rEALLOc();
Void_t* mEMALIGn();
Void_t* vALLOc();
Void_t* pvALLOc();
Void_t* cALLOc();
void cfree();
int malloc_trim();
size_t malloc_usable_size();
void malloc_stats();
int mALLOPt();
struct mallinfo mALLINFo();
#endif
/*
* Begin and End of memory area for malloc(), and current "brk"
*/
extern ulong mem_malloc_start;
extern ulong mem_malloc_end;
extern ulong mem_malloc_brk;
void mem_malloc_init(ulong start, ulong size);
#ifdef __cplusplus
}; /* end of extern "C" */
#endif
#endif /* __MALLOC_H__ */
|
1001-study-uboot
|
include/malloc.h
|
C
|
gpl3
| 33,853
|
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
* Jun-jie Zhang <b18070@freescale.com>
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FSL_PHY_H__
#define __FSL_PHY_H__
#include <net.h>
#include <miiphy.h>
#include <asm/fsl_enet.h>
/* PHY register offsets */
#define PHY_EXT_PAGE_ACCESS 0x1f
/* MII Management Configuration Register */
#define MIIMCFG_RESET_MGMT 0x80000000
#define MIIMCFG_MGMT_CLOCK_SELECT 0x00000007
#define MIIMCFG_INIT_VALUE 0x00000003
/* MII Management Command Register */
#define MIIMCOM_READ_CYCLE 0x00000001
#define MIIMCOM_SCAN_CYCLE 0x00000002
/* MII Management Address Register */
#define MIIMADD_PHY_ADDR_SHIFT 8
/* MII Management Indicator Register */
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
void tsec_local_mdio_write(struct tsec_mii_mng *phyregs, int port_addr,
int dev_addr, int reg, int value);
int tsec_local_mdio_read(struct tsec_mii_mng *phyregs, int port_addr,
int dev_addr, int regnum);
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum);
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
u16 value);
struct fsl_pq_mdio_info {
struct tsec_mii_mng *regs;
char *name;
};
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
#endif /* __FSL_PHY_H__ */
|
1001-study-uboot
|
include/fsl_mdio.h
|
C
|
gpl3
| 2,043
|
/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Logic lh7a400-10 Card Engine CPLD interface
*/
#ifndef __LPD7A400_CPLD_H_
#define __LPD7A400_CPLD_H_
/*
* IO Controller Address and Register Definitions
* - using LH7A400-10 Card Engine IO Controller Specification
* (logic PN: 70000079)
*/
/*------------------------------------------------------------------
* Slow Peripherals (nCS6)
*/
#define LPD7A400_CPLD_CF (0x60200000)
#define LPD7A400_CPLD_ISA (0x60400000)
/*------------------------------------------------------------------
* Fast Peripherals (nCS7)
*
* The CPLD directs access to 0x70000000-0x701fffff to the onboard
* ethernet controller
*/
#define LPD7A400_CPLD_WLAN_BASE (0x70000000)
/* All registers are 8 bit */
#define LPD7A400_CPLD_CECTL_REG (0x70200000)
#define LPD7A400_CPLD_SPIDATA_REG (0x70600000)
#define LPD7A400_CPLD_SPICTL_REG (0x70800000)
#define LPD7A400_CPLD_EEPSPI_REG (0x70a00000)
#define LPD7A400_CPLD_INTMASK_REG (0x70c00000)
#define LPD7A400_CPLD_MODE_REG (0x70e00000)
#define LPD7A400_CPLD_FLASH_REG (0x71000000)
#define LPD7A400_CPLD_PWRMG_REG (0x71200000)
#define LPD7A400_CPLD_REV_REG (0x71400000)
#define LPD7A400_CPLD_EXTGPIO_REG (0x71600000)
#define LPD7A400_CPLD_GPIODATA_REG (0x71800000)
#define LPD7A400_CPLD_GPIODIR_REG (0x71a00000)
#define LPD7A400_CPLD_REGPTR (volatile u8*)
/* Card Engine Control Register (section 3.1.2) */
#define CECTL_SWINT (0x80) /* Software settable interrupt source
(routed to uP PF3)
0 = generate interrupt, 1 = do not */
#define CECTL_OCMSK (0x40) /* USB1 connection interrupt mask
0 = not masked, 1 = masked */
#define CECTL_PDRV (0x20) /* PCC_nDRV output
0 = active, 1 = inactive */
#define CECTL_USB1C (0x10) /* USB1 connection interrupt
0 = active, 1 = inactive */
#define CECTL_USB1P (0x08) /* USB1 Power enable
0 = enabled, 1 = disabled */
#define CECTL_AWKP (0x04) /* Auto-Wakeup enable
0 = enabled, 1 = disabled */
#define CECTL_LCDV (0x02) /* LCD VEE enable
0 = disabled, 1 = enabled */
#define CECTL_WLPE (0x01) /* Wired LAN power enable
0 = enabled, 1 = disabled */
/* SPI Control Register (section 3.1.5) */
#define SPICTL_SPLD (0x20) /* SPI load (R)
0 = data reg. has not been loaded, shift
count has not been reset
1 = data reg. loaded, shift count reset */
#define SPICTL_SPST (0x10) /* SPI start (RW)
0 = don't load data reg. and reset shift count
1 = ready to load data reg and reset shift count */
#define SPICTL_SPDN (0x08) /* SPI done (R)
0 = not done
1 = access done */
#define SPICTL_SPRW (0x04) /* SPI read/write (RW)
0 = SPI write access
1 = SPI read access */
#define SPICTL_STCS (0x02) /* SPI touch chip select (RW)
0 = not selected
1 = selected */
#define SPICTL_SCCS (0x01) /* SPI CODEC chip select (RW) {not used}
0 = not selected
1 = selected */
/* EEPROM SPI Interface Register (section 3.1.6) */
#define EEPSPI_EECS (0x08) /* EEPROM chip select (RW)
0 = not selected
1 = selected */
#define EEPSPI_EECK (0x04) /* EEPROM SPI clock (RW) */
#define EEPSPI_EETX (0x02) /* EEPROM SPI tx data (RW) */
#define EEPSPI_EERX (0x01) /* EEPROM SPI rx data (R) */
/* Interrupt/Mask Register (section 3.1.7) */
#define INTMASK_CMSK (0x80) /* CPLD_nIRQD interrupt mask (RW)
0 = not masked
1 = masked */
#define INTMASK_CIRQ (0x40) /* interrupt signal to CPLD (R)
0 = interrupt active
1 = no interrupt */
#define INTMASK_PIRQ (0x10) /* legacy, no effect */
#define INTMASK_TMSK (0x08) /* Touch chip interrupt mask (RW)
0 = not masked
1 = masked */
#define INTMASK_WMSK (0x04) /* Wired LAN interrupt mask (RW)
0 = not masked
1 = masked */
#define INTMASK_TIRQ (0x02) /* Touch chip interrupt request (R)
0 = interrupt active
1 = no interrupt */
#define INTMASK_WIRQ (0x01) /* Wired LAN interrupt request (R)
0 = interrupt active
1 = no interrupt */
/* Mode Register (section 3.1.8) */
#define MODE_VS1 (0x80) /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R)
0 = active slot VS1 pin is low
1 = active slot VS1 pin is high */
#define MODE_CD2 (0x40) /* PCMCIA Card Detect 2 input (PCC_nCD2) (R)
0 = active slot CD2 is low
1 = active slot CD2 is high */
#define MODE_IOIS16 (0x20) /* PCMCIA IOIS16 input (PCC_nIOIS16) (R)
0 = 16 bit access area
1 = 8 bit access area */
#define MODE_CD1 (0x10) /* PCMCIA Card Detect 1 input (PCC_nCD1) (R)
0 = active slot CD1 is low
1 = active slot CD1 is high */
#define MODE_upMODE3 (0x08) /* Mode Pin 3 (R)
0 = off-board boot device
1 = on-board boot device (flash) */
#define MODE_upMODE2 (0x04) /* Mode Pin 2 (R) (LH7A400 Little Endian only)
0 = big endian
1 = little endian */
#define MODE_upMODE1 (0x02) /* Mode Pin 1 and Mode Pin 2 (R) */
#define MODE_upMODE0 (0x01) /* - bus width at boot */
/* Flash Register (section 3.1.9) */
#define FLASH_FPOP (0x08) /* Flash populated (RW)
0 = populated, 1 = not */
#define FLASH_FST2 (0x04) /* Flash status (R) (RY/BY# pin for upper 16 bit chip
0 = busy, 1 = ready */
#define FLASH_FST1 (0x02) /* Flash status (R) (RY/BY# pin for lower 16 bit chip
0 = busy, 1 = ready */
#define FLASH_FPEN (0x01) /* Flash program enable (RW)
0 = flash write protected
1 = programming enabled */
/* Power Management Register (section 3.1.10)
* - when either of these is low an unmaskable interrupt to cpu
* is generated
*/
#define PWRMG_STBY (0x10) /* state of nSTANDBY signal to CPLD (R)
0 = low, 1 = high */
#define PWRMG_SPND (0x04) /* state of nSUSPEND signal to CPLD (R)
0 = low, 1 = high */
/* Extended GPIO Register (section 3.1.12) */
#define EXTGPIO_STATUS1 (0x04) /* Status 1 output (RW) (uP_STATUS_1)
0 = set pin low, 1 = set pin high */
#define EXTGPIO_STATUS2 (0x02) /* Status 2 output (RW) (uP_STATUS_2)
0 = set pin low, 1 = set pin high */
#define EXTGPIO_GPIO1 (0x01) /* General purpose output (RW) (CPLD_GPIO_1)
0 = set pin low, 1 = set pin high */
/* GPIO Data Register (section 3.1.13) */
#define GPIODATA_GPIO2 (0x01) /* General purpose input/output (RW) (CPLD_GPIO_2)
0 = set low (output) / read low (input)
1 = set high (output) / read high (input) */
/* GPIO Direction Register (section 3.1.14) */
#define GPIODIR_GPDR0 (0x01) /* GPIO2 direction (RW)
0 = output, 1 = input */
#endif /* __LH7A400_H__ */
|
1001-study-uboot
|
include/lpd7a400_cpld.h
|
C
|
gpl3
| 7,354
|
/*
* (C) Copyright 2011 Andes Technology Corp
* Macpaul Lin <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Andes Power Control Unit
*/
#ifndef __ANDES_PCU_H
#define __ANDES_PCU_H
#ifndef __ASSEMBLY__
struct pcs {
unsigned int cr; /* PCSx Configuration (clock scaling) */
unsigned int parm; /* PCSx Parameter*/
unsigned int stat1; /* PCSx Status 1 */
unsigned int stat2; /* PCSx Stusts 2 */
unsigned int pdd; /* PCSx PDD */
};
struct andes_pcu {
unsigned int rev; /* 0x00 - PCU Revision */
unsigned int spinfo; /* 0x04 - Scratch Pad Info */
unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
unsigned int soc_id; /* 0x10 - SoC ID */
unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
unsigned int soc_apb; /* 0x18 - SoC APB configuration */
unsigned int rsvd2; /* 0x1C */
unsigned int dcsrcr0; /* 0x20 - Driving Capability
and Slew Rate Control 0 */
unsigned int dcsrcr1; /* 0x24 - Driving Capability
and Slew Rate Control 1 */
unsigned int dcsrcr2; /* 0x28 - Driving Capability
and Slew Rate Control 2 */
unsigned int rsvd3; /* 0x2C */
unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */
unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */
unsigned int dmaes; /* 0x38 - DMA Engine Selection */
unsigned int rsvd4; /* 0x3C */
unsigned int oscc; /* 0x40 - OSC Control */
unsigned int pwmcd; /* 0x44 - PWM Clock divider */
unsigned int socmisc; /* 0x48 - SoC Misc. */
unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */
unsigned int bsmcr; /* 0x80 - BSM Controrl */
unsigned int bsmst; /* 0x84 - BSM Status */
unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/
unsigned int west; /* 0x8C - Wakeup Event Status */
unsigned int rsttiming; /* 0x90 - Reset Timing */
unsigned int intr_st; /* 0x94 - PCU Interrupt Status */
unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */
struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */
unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */
struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */
unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */
struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */
unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */
struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */
unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */
struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */
unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */
struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */
unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */
struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */
unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */
struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */
unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */
struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */
unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */
unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager
Scratch Pad Memory 0 */
};
#endif /* __ASSEMBLY__ */
/*
* PCU Revision Register (ro)
*/
#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff)
#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff)
/*
* Scratch Pad Info Register (ro)
*/
#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff)
#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf)
/*
* SoC ID Register (ro)
*/
#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf)
#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff)
#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff)
/*
* SoC AHB Configuration Register (ro)
*/
#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0)
#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1)
#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2)
#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3)
#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4)
#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5)
#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6)
#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7)
#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8)
#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9)
#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12)
#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13)
#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14)
#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15)
#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16)
#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17)
#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18)
#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19)
#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20)
#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27)
#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28)
#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29)
#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30)
#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31)
/*
* SoC APB Configuration Register (ro)
*/
#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1)
#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2)
#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3)
#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5)
#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6)
#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8)
#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16)
#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17)
#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18)
#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19)
#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20)
#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22)
#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23)
/*
* Driving Capability and Slew Rate Control Register 0 (rw)
*/
#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0)
#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8)
#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12)
#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16)
#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20)
/*
* Driving Capability and Slew Rate Control Register 1 (rw)
*/
#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0)
/*
* Driving Capability and Slew Rate Control Register 2 (rw)
*/
#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0)
#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4)
#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8)
#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12)
#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16)
#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20)
#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24)
#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28)
/*
* Multi-function Port Setting Register 0 (rw)
*/
#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0)
#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1)
#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2)
#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3)
#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4)
#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28)
#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31)
/*
* Multi-function Port Setting Register 1 (rw)
*/
#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0)
#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1)
#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2)
#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3)
#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4)
#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5)
#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6)
#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7)
#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8)
#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9)
#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10)
#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27)
#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28)
#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29)
#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30)
#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31)
/*
* DMA Engine Selection Register (rw)
*/
#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2)
#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3)
#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4)
#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5)
#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6)
#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7)
#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8)
#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9)
/*
* OSC Control Register (rw)
*/
#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0)
#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1)
#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2)
#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4)
#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6)
#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8)
/*
* PWM Clock Divider Register (rw)
*/
#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0)
/*
* SoC Misc. Register (rw)
*/
#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0)
#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1)
#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2)
#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3)
#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4)
#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6)
#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8)
#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9)
#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10)
#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11)
#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12)
#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13)
#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14)
#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15)
#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16)
#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17)
#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18)
#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19)
#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20)
#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21)
#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22)
#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23)
#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24)
#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25)
#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26)
#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27)
#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28)
#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29)
#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30)
#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31)
/*
* BSM Control Register (rw)
*/
#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0)
#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4)
#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24)
#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28)
#define ANDES_PCU_BSMCR_IE(x) ((x) << 31)
/*
* BSM Status Register
*/
#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0)
#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4)
#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24)
#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28)
/*
* Wakeup Event Sensitivity Register (rw)
*/
#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0)
/*
* Wakeup Event Status Register (ro)
*/
#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0)
/*
* Reset Timing Register
*/
#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0)
#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8)
#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16)
#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24)
/*
* PCU Interrupt Status Register
*/
#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0)
#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1)
#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2)
#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3)
#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4)
#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5)
#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6)
#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7)
#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8)
#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9)
/*
* PCSx Configuration Register
*/
#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0)
#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16)
#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20)
#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */
/*
* PCSx Parameter Register (rw)
*/
#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0)
#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24)
#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28)
#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31)
/*
* PCSx Status Register 1
*/
#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0)
#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28)
/*
* PCSx Status Register 2
*/
#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0)
#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24)
/*
* PCSx PDD Register
* This is reserved for PCS(1-7)
*/
#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0)
#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8)
#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16)
#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24)
#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0)
#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6)
#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12)
#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18)
#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24)
#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27)
#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28)
#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30)
#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31)
#endif /* __ANDES_PCU_H */
|
1001-study-uboot
|
include/andestech/andes_pcu.h
|
C
|
gpl3
| 13,854
|
/*
* (C) Copyright 2002
* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef _SPARTAN3_H_
#define _SPARTAN3_H_
#include <xilinx.h>
extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size);
extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
extern int Spartan3_info(Xilinx_desc *desc);
/* Slave Parallel Implementation function table */
typedef struct {
Xilinx_pre_fn pre;
Xilinx_pgm_fn pgm;
Xilinx_init_fn init;
Xilinx_err_fn err;
Xilinx_done_fn done;
Xilinx_clk_fn clk;
Xilinx_cs_fn cs;
Xilinx_wr_fn wr;
Xilinx_rdata_fn rdata;
Xilinx_wdata_fn wdata;
Xilinx_busy_fn busy;
Xilinx_abort_fn abort;
Xilinx_post_fn post;
} Xilinx_Spartan3_Slave_Parallel_fns;
/* Slave Serial Implementation function table */
typedef struct {
Xilinx_pre_fn pre;
Xilinx_pgm_fn pgm;
Xilinx_clk_fn clk;
Xilinx_init_fn init;
Xilinx_done_fn done;
Xilinx_wr_fn wr;
Xilinx_post_fn post;
Xilinx_bwr_fn bwr; /* block write function */
Xilinx_abort_fn abort;
} Xilinx_Spartan3_Slave_Serial_fns;
/* Device Image Sizes
*********************************************************************/
/* Spartan-III (1.2V) */
#define XILINX_XC3S50_SIZE 439264/8
#define XILINX_XC3S200_SIZE 1047616/8
#define XILINX_XC3S400_SIZE 1699136/8
#define XILINX_XC3S1000_SIZE 3223488/8
#define XILINX_XC3S1500_SIZE 5214784/8
#define XILINX_XC3S2000_SIZE 7673024/8
#define XILINX_XC3S4000_SIZE 11316864/8
#define XILINX_XC3S5000_SIZE 13271936/8
/* Spartan-3E (v3.4) */
#define XILINX_XC3S100E_SIZE 581344/8
#define XILINX_XC3S250E_SIZE 1353728/8
#define XILINX_XC3S500E_SIZE 2270208/8
#define XILINX_XC3S1200E_SIZE 3841184/8
#define XILINX_XC3S1600E_SIZE 5969696/8
/* Descriptor Macros
*********************************************************************/
/* Spartan-III devices */
#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
/* Spartan-3E devices */
#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
#endif /* _SPARTAN3_H_ */
|
1001-study-uboot
|
include/spartan3.h
|
C
|
gpl3
| 4,281
|
/*
* Copyright (C) 2011 Samsung Electronics
* Lukasz Majewski <l.majewski@samsung.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MAX8998_PMIC_H_
#define __MAX8998_PMIC_H_
/* MAX 8998 registers */
enum {
MAX8998_REG_IRQ1,
MAX8998_REG_IRQ2,
MAX8998_REG_IRQ3,
MAX8998_REG_IRQ4,
MAX8998_REG_IRQM1,
MAX8998_REG_IRQM2,
MAX8998_REG_IRQM3,
MAX8998_REG_IRQM4,
MAX8998_REG_STATUS1,
MAX8998_REG_STATUS2,
MAX8998_REG_STATUSM1,
MAX8998_REG_STATUSM2,
MAX8998_REG_CHGR1,
MAX8998_REG_CHGR2,
MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
MAX8998_REG_ONOFF1,
MAX8998_REG_ONOFF2,
MAX8998_REG_ONOFF3,
MAX8998_REG_ONOFF4,
MAX8998_REG_BUCK1_VOLTAGE1,
MAX8998_REG_BUCK1_VOLTAGE2,
MAX8998_REG_BUCK1_VOLTAGE3,
MAX8998_REG_BUCK1_VOLTAGE4,
MAX8998_REG_BUCK2_VOLTAGE1,
MAX8998_REG_BUCK2_VOLTAGE2,
MAX8998_REG_BUCK3,
MAX8998_REG_BUCK4,
MAX8998_REG_LDO2_LDO3,
MAX8998_REG_LDO4,
MAX8998_REG_LDO5,
MAX8998_REG_LDO6,
MAX8998_REG_LDO7,
MAX8998_REG_LDO8_LDO9,
MAX8998_REG_LDO10_LDO11,
MAX8998_REG_LDO12,
MAX8998_REG_LDO13,
MAX8998_REG_LDO14,
MAX8998_REG_LDO15,
MAX8998_REG_LDO16,
MAX8998_REG_LDO17,
MAX8998_REG_BKCHR,
MAX8998_REG_LBCNFG1,
MAX8998_REG_LBCNFG2,
PMIC_NUM_OF_REGS,
};
#define MAX8998_LDO3 (1 << 2)
#define MAX8998_LDO8 (1 << 5)
#define MAX8998_SAFEOUT1 (1 << 4)
#define MAX8998_I2C_ADDR (0xCC >> 1)
enum { LDO_OFF, LDO_ON };
#endif /* __MAX8998_PMIC_H_ */
|
1001-study-uboot
|
include/max8998_pmic.h
|
C
|
gpl3
| 2,225
|
/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _DS1722_H_
#define _DS1722_H_
#define DS1722_RESOLUTION_8BIT 0x0
#define DS1722_RESOLUTION_9BIT 0x1
#define DS1722_RESOLUTION_10BIT 0x2
#define DS1722_RESOLUTION_11BIT 0x3
#define DS1722_RESOLUTION_12BIT 0x4
int ds1722_probe(int dev);
#endif /* _DS1722_H_ */
|
1001-study-uboot
|
include/ds1722.h
|
C
|
gpl3
| 1,070
|
/*
* (C) Copyright 1997-2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* smiLynxEM.h
* Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
*
*
* modification history
* --------------------
* 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
*/
#ifndef _VIDEO_FB_H_
#define _VIDEO_FB_H_
#define CONSOLE_BG_COL 0x00
#define CONSOLE_FG_COL 0xa0
/*
* Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
*/
#define GDF__8BIT_INDEX 0
#define GDF_15BIT_555RGB 1
#define GDF_16BIT_565RGB 2
#define GDF_32BIT_X888RGB 3
#define GDF_24BIT_888RGB 4
#define GDF__8BIT_332RGB 5
/******************************************************************************/
/* Export Graphic Driver Control */
/******************************************************************************/
typedef struct {
unsigned int isaBase;
unsigned int pciBase;
unsigned int dprBase;
unsigned int vprBase;
unsigned int cprBase;
unsigned int frameAdrs;
unsigned int memSize;
unsigned int mode;
unsigned int gdfIndex;
unsigned int gdfBytesPP;
unsigned int fg;
unsigned int bg;
unsigned int plnSizeX;
unsigned int plnSizeY;
unsigned int winSizeX;
unsigned int winSizeY;
char modeIdent[80];
} GraphicDevice;
/******************************************************************************/
/* Export Graphic Functions */
/******************************************************************************/
void *video_hw_init (void); /* returns GraphicDevice struct or NULL */
#ifdef VIDEO_HW_BITBLT
void video_hw_bitblt (
unsigned int bpp, /* bytes per pixel */
unsigned int src_x, /* source pos x */
unsigned int src_y, /* source pos y */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y /* frame height */
);
#endif
#ifdef VIDEO_HW_RECTFILL
void video_hw_rectfill (
unsigned int bpp, /* bytes per pixel */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y, /* frame height */
unsigned int color /* fill color */
);
#endif
void video_set_lut (
unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
);
#ifdef CONFIG_VIDEO_HW_CURSOR
void video_set_hw_cursor(int x, int y); /* x y in pixel */
void video_init_hw_cursor(int font_width, int font_height);
#endif
#endif /*_VIDEO_FB_H_ */
|
1001-study-uboot
|
include/video_fb.h
|
C
|
gpl3
| 3,742
|
/*
* (C) Copyright 2003
* Gerry Hamel, geh@ti.com, Texas Instruments
*
* Based on linux/drivers/usbd/usbd.h
*
* Copyright (c) 2000, 2001, 2002 Lineo
* Copyright (c) 2001 Hewlett Packard
*
* By:
* Stuart Lynne <sl@lineo.com>,
* Tom Rushworth <tbr@lineo.com>,
* Bruce Balden <balden@lineo.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __USBDCORE_H__
#define __USBDCORE_H__
#include <common.h>
#include "usbdescriptors.h"
#define MAX_URBS_QUEUED 5
#if 1
#define usberr(fmt,args...) serial_printf("ERROR: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
#else
#define usberr(fmt,args...) do{}while(0)
#endif
#if 0
#define usbdbg(fmt,args...) serial_printf("debug: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
#else
#define usbdbg(fmt,args...) do{}while(0)
#endif
#if 0
#define usbinfo(fmt,args...) serial_printf("info: %s(), %d: "fmt"\n",__FUNCTION__,__LINE__,##args)
#else
#define usbinfo(fmt,args...) do{}while(0)
#endif
#ifndef le16_to_cpu
#define le16_to_cpu(x) (x)
#endif
#ifndef inb
#define inb(p) (*(volatile u8*)(p))
#endif
#ifndef outb
#define outb(val,p) (*(volatile u8*)(p) = (val))
#endif
#ifndef inw
#define inw(p) (*(volatile u16*)(p))
#endif
#ifndef outw
#define outw(val,p) (*(volatile u16*)(p) = (val))
#endif
#ifndef inl
#define inl(p) (*(volatile u32*)(p))
#endif
#ifndef outl
#define outl(val,p) (*(volatile u32*)(p) = (val))
#endif
#ifndef insw
#define insw(p,to,len) mmio_insw(p,to,len)
#endif
#ifndef outsw
#define outsw(p,from,len) mmio_outsw(p,from,len)
#endif
#ifndef insb
#define insb(p,to,len) mmio_insb(p,to,len)
#endif
#ifndef mmio_insw
#define mmio_insw(r,b,l) ({ int __i ; \
u16 *__b2; \
__b2 = (u16 *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = inw(r); \
}; \
})
#endif
#ifndef mmio_outsw
#define mmio_outsw(r,b,l) ({ int __i; \
u16 *__b2; \
__b2 = (u16 *) b; \
for (__i = 0; __i < l; __i++) { \
outw( *(__b2 + __i), r); \
} \
})
#endif
#ifndef mmio_insb
#define mmio_insb(r,b,l) ({ int __i ; \
u8 *__b2; \
__b2 = (u8 *) b; \
for (__i = 0; __i < l; __i++) { \
*(__b2 + __i) = inb(r); \
}; \
})
#endif
/*
* Structure member address manipulation macros.
* These are used by client code (code using the urb_link routines), since
* the urb_link structure is embedded in the client data structures.
*
* Note: a macro offsetof equivalent to member_offset is defined in stddef.h
* but this is kept here for the sake of portability.
*
* p2surround returns a pointer to the surrounding structure given
* type of the surrounding structure, the name memb of the structure
* member pointed at by ptr. For example, if you have:
*
* struct foo {
* int x;
* float y;
* char z;
* } thingy;
*
* char *cp = &thingy.z;
*
* then
*
* &thingy == p2surround(struct foo, z, cp)
*
* Clear?
*/
#define _cv_(ptr) ((char*)(void*)(ptr))
#define member_offset(type,memb) (_cv_(&(((type*)0)->memb))-(char*)0)
#define p2surround(type,memb,ptr) ((type*)(void*)(_cv_(ptr)-member_offset(type,memb)))
struct urb;
struct usb_endpoint_instance;
struct usb_interface_instance;
struct usb_configuration_instance;
struct usb_device_instance;
struct usb_bus_instance;
/*
* Device and/or Interface Class codes
*/
#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PHYSICAL 5
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_DATA 10
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
/*
* USB types
*/
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
/*
* USB recipients
*/
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
/*
* USB directions
*/
#define USB_DIR_OUT 0
#define USB_DIR_IN 0x80
/*
* Descriptor types
*/
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_HID (USB_TYPE_CLASS | 0x01)
#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02)
#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
#define USB_DT_HUB (USB_TYPE_CLASS | 0x09)
/*
* Descriptor sizes per descriptor type
*/
#define USB_DT_DEVICE_SIZE 18
#define USB_DT_CONFIG_SIZE 9
#define USB_DT_INTERFACE_SIZE 9
#define USB_DT_ENDPOINT_SIZE 7
#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */
#define USB_DT_HUB_NONVAR_SIZE 7
#define USB_DT_HID_SIZE 9
/*
* Endpoints
*/
#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
#define USB_ENDPOINT_DIR_MASK 0x80
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
/*
* USB Packet IDs (PIDs)
*/
#define USB_PID_UNDEF_0 0xf0
#define USB_PID_OUT 0xe1
#define USB_PID_ACK 0xd2
#define USB_PID_DATA0 0xc3
#define USB_PID_PING 0xb4 /* USB 2.0 */
#define USB_PID_SOF 0xa5
#define USB_PID_NYET 0x96 /* USB 2.0 */
#define USB_PID_DATA2 0x87 /* USB 2.0 */
#define USB_PID_SPLIT 0x78 /* USB 2.0 */
#define USB_PID_IN 0x69
#define USB_PID_NAK 0x5a
#define USB_PID_DATA1 0x4b
#define USB_PID_PREAMBLE 0x3c /* Token mode */
#define USB_PID_ERR 0x3c /* USB 2.0: handshake mode */
#define USB_PID_SETUP 0x2d
#define USB_PID_STALL 0x1e
#define USB_PID_MDATA 0x0f /* USB 2.0 */
/*
* Standard requests
*/
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
#define USBD_DEVICE_REQUESTS(x) (((unsigned int)x <= USB_REQ_SYNCH_FRAME) ? usbd_device_requests[x] : "UNKNOWN")
/*
* HID requests
*/
#define USB_REQ_GET_REPORT 0x01
#define USB_REQ_GET_IDLE 0x02
#define USB_REQ_GET_PROTOCOL 0x03
#define USB_REQ_SET_REPORT 0x09
#define USB_REQ_SET_IDLE 0x0A
#define USB_REQ_SET_PROTOCOL 0x0B
/*
* USB Spec Release number
*/
#define USB_BCD_VERSION 0x0110
/*
* Device Requests (c.f Table 9-2)
*/
#define USB_REQ_DIRECTION_MASK 0x80
#define USB_REQ_TYPE_MASK 0x60
#define USB_REQ_RECIPIENT_MASK 0x1f
#define USB_REQ_DEVICE2HOST 0x80
#define USB_REQ_HOST2DEVICE 0x00
#define USB_REQ_TYPE_STANDARD 0x00
#define USB_REQ_TYPE_CLASS 0x20
#define USB_REQ_TYPE_VENDOR 0x40
#define USB_REQ_RECIPIENT_DEVICE 0x00
#define USB_REQ_RECIPIENT_INTERFACE 0x01
#define USB_REQ_RECIPIENT_ENDPOINT 0x02
#define USB_REQ_RECIPIENT_OTHER 0x03
/*
* get status bits
*/
#define USB_STATUS_SELFPOWERED 0x01
#define USB_STATUS_REMOTEWAKEUP 0x02
#define USB_STATUS_HALT 0x01
/*
* descriptor types
*/
#define USB_DESCRIPTOR_TYPE_DEVICE 0x01
#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02
#define USB_DESCRIPTOR_TYPE_STRING 0x03
#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04
#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05
#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06
#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION 0x07
#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08
#define USB_DESCRIPTOR_TYPE_HID 0x21
#define USB_DESCRIPTOR_TYPE_REPORT 0x22
#define USBD_DEVICE_DESCRIPTORS(x) (((unsigned int)x <= USB_DESCRIPTOR_TYPE_INTERFACE_POWER) ? \
usbd_device_descriptors[x] : "UNKNOWN")
/*
* standard feature selectors
*/
#define USB_ENDPOINT_HALT 0x00
#define USB_DEVICE_REMOTE_WAKEUP 0x01
#define USB_TEST_MODE 0x02
/* USB Requests
*
*/
struct usb_device_request {
u8 bmRequestType;
u8 bRequest;
u16 wValue;
u16 wIndex;
u16 wLength;
} __attribute__ ((packed));
/* USB Status
*
*/
typedef enum urb_send_status {
SEND_IN_PROGRESS,
SEND_FINISHED_OK,
SEND_FINISHED_ERROR,
RECV_READY,
RECV_OK,
RECV_ERROR
} urb_send_status_t;
/*
* Device State (c.f USB Spec 2.0 Figure 9-1)
*
* What state the usb device is in.
*
* Note the state does not change if the device is suspended, we simply set a
* flag to show that it is suspended.
*
*/
typedef enum usb_device_state {
STATE_INIT, /* just initialized */
STATE_CREATED, /* just created */
STATE_ATTACHED, /* we are attached */
STATE_POWERED, /* we have seen power indication (electrical bus signal) */
STATE_DEFAULT, /* we been reset */
STATE_ADDRESSED, /* we have been addressed (in default configuration) */
STATE_CONFIGURED, /* we have seen a set configuration device command */
STATE_UNKNOWN, /* destroyed */
} usb_device_state_t;
#define USBD_DEVICE_STATE(x) (((unsigned int)x <= STATE_UNKNOWN) ? usbd_device_states[x] : "UNKNOWN")
/*
* Device status
*
* Overall state
*/
typedef enum usb_device_status {
USBD_OPENING, /* we are currently opening */
USBD_OK, /* ok to use */
USBD_SUSPENDED, /* we are currently suspended */
USBD_CLOSING, /* we are currently closing */
} usb_device_status_t;
#define USBD_DEVICE_STATUS(x) (((unsigned int)x <= USBD_CLOSING) ? usbd_device_status[x] : "UNKNOWN")
/*
* Device Events
*
* These are defined in the USB Spec (c.f USB Spec 2.0 Figure 9-1).
*
* There are additional events defined to handle some extra actions we need
* to have handled.
*
*/
typedef enum usb_device_event {
DEVICE_UNKNOWN, /* bi - unknown event */
DEVICE_INIT, /* bi - initialize */
DEVICE_CREATE, /* bi - */
DEVICE_HUB_CONFIGURED, /* bi - bus has been plugged int */
DEVICE_RESET, /* bi - hub has powered our port */
DEVICE_ADDRESS_ASSIGNED, /* ep0 - set address setup received */
DEVICE_CONFIGURED, /* ep0 - set configure setup received */
DEVICE_SET_INTERFACE, /* ep0 - set interface setup received */
DEVICE_SET_FEATURE, /* ep0 - set feature setup received */
DEVICE_CLEAR_FEATURE, /* ep0 - clear feature setup received */
DEVICE_DE_CONFIGURED, /* ep0 - set configure setup received for ?? */
DEVICE_BUS_INACTIVE, /* bi - bus in inactive (no SOF packets) */
DEVICE_BUS_ACTIVITY, /* bi - bus is active again */
DEVICE_POWER_INTERRUPTION, /* bi - hub has depowered our port */
DEVICE_HUB_RESET, /* bi - bus has been unplugged */
DEVICE_DESTROY, /* bi - device instance should be destroyed */
DEVICE_HOTPLUG, /* bi - a hotplug event has occured */
DEVICE_FUNCTION_PRIVATE, /* function - private */
} usb_device_event_t;
typedef struct urb_link {
struct urb_link *next;
struct urb_link *prev;
} urb_link;
/* USB Data structure - for passing data around.
*
* This is used for both sending and receiving data.
*
* The callback function is used to let the function driver know when
* transmitted data has been sent.
*
* The callback function is set by the alloc_recv function when an urb is
* allocated for receiving data for an endpoint and used to call the
* function driver to inform it that data has arrived.
*/
#define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer static data */
struct urb {
struct usb_endpoint_instance *endpoint;
struct usb_device_instance *device;
struct usb_device_request device_request; /* contents of received SETUP packet */
struct urb_link link; /* embedded struct for circular doubly linked list of urbs */
u8* buffer;
unsigned int buffer_length;
unsigned int actual_length;
urb_send_status_t status;
int data;
u16 buffer_data[URB_BUF_SIZE]; /* data received (OUT) or being sent (IN) */
};
/* Endpoint configuration
*
* Per endpoint configuration data. Used to track which function driver owns
* an endpoint.
*
*/
struct usb_endpoint_instance {
int endpoint_address; /* logical endpoint address */
/* control */
int status; /* halted */
int state; /* available for use by bus interface driver */
/* receive side */
struct urb_link rcv; /* received urbs */
struct urb_link rdy; /* empty urbs ready to receive */
struct urb *rcv_urb; /* active urb */
int rcv_attributes; /* copy of bmAttributes from endpoint descriptor */
int rcv_packetSize; /* maximum packet size from endpoint descriptor */
int rcv_transferSize; /* maximum transfer size from function driver */
int rcv_queue;
/* transmit side */
struct urb_link tx; /* urbs ready to transmit */
struct urb_link done; /* transmitted urbs */
struct urb *tx_urb; /* active urb */
int tx_attributes; /* copy of bmAttributes from endpoint descriptor */
int tx_packetSize; /* maximum packet size from endpoint descriptor */
int tx_transferSize; /* maximum transfer size from function driver */
int tx_queue;
int sent; /* data already sent */
int last; /* data sent in last packet XXX do we need this */
};
struct usb_alternate_instance {
struct usb_interface_descriptor *interface_descriptor;
int endpoints;
int *endpoint_transfersize_array;
struct usb_endpoint_descriptor **endpoints_descriptor_array;
};
struct usb_interface_instance {
int alternates;
struct usb_alternate_instance *alternates_instance_array;
};
struct usb_configuration_instance {
int interfaces;
struct usb_configuration_descriptor *configuration_descriptor;
struct usb_interface_instance *interface_instance_array;
};
/* USB Device Instance
*
* For each physical bus interface we create a logical device structure. This
* tracks all of the required state to track the USB HOST's view of the device.
*
* Keep track of the device configuration for a real physical bus interface,
* this includes the bus interface, multiple function drivers, the current
* configuration and the current state.
*
* This will show:
* the specific bus interface driver
* the default endpoint 0 driver
* the configured function driver
* device state
* device status
* endpoint list
*/
struct usb_device_instance {
/* generic */
char *name;
struct usb_device_descriptor *device_descriptor; /* per device descriptor */
void (*event) (struct usb_device_instance *device, usb_device_event_t event, int data);
/* Do cdc device specific control requests */
int (*cdc_recv_setup)(struct usb_device_request *request, struct urb *urb);
/* bus interface */
struct usb_bus_instance *bus; /* which bus interface driver */
/* configuration descriptors */
int configurations;
struct usb_configuration_instance *configuration_instance_array;
/* device state */
usb_device_state_t device_state; /* current USB Device state */
usb_device_state_t device_previous_state; /* current USB Device state */
u8 address; /* current address (zero is default) */
u8 configuration; /* current show configuration (zero is default) */
u8 interface; /* current interface (zero is default) */
u8 alternate; /* alternate flag */
usb_device_status_t status; /* device status */
int urbs_queued; /* number of submitted urbs */
/* Shouldn't need to make this atomic, all we need is a change indicator */
unsigned long usbd_rxtx_timestamp;
unsigned long usbd_last_rxtx_timestamp;
};
/* Bus Interface configuration structure
*
* This is allocated for each configured instance of a bus interface driver.
*
* The privdata pointer may be used by the bus interface driver to store private
* per instance state information.
*/
struct usb_bus_instance {
struct usb_device_instance *device;
struct usb_endpoint_instance *endpoint_array; /* array of available configured endpoints */
int max_endpoints; /* maximimum number of rx enpoints */
unsigned char maxpacketsize;
unsigned int serial_number;
char *serial_number_str;
void *privdata; /* private data for the bus interface */
};
extern char *usbd_device_events[];
extern char *usbd_device_states[];
extern char *usbd_device_status[];
extern char *usbd_device_requests[];
extern char *usbd_device_descriptors[];
void urb_link_init (urb_link * ul);
void urb_detach (struct urb *urb);
urb_link *first_urb_link (urb_link * hd);
struct urb *first_urb (urb_link * hd);
struct urb *first_urb_detached (urb_link * hd);
void urb_append (urb_link * hd, struct urb *urb);
struct urb *usbd_alloc_urb (struct usb_device_instance *device, struct usb_endpoint_instance *endpoint);
void usbd_dealloc_urb (struct urb *urb);
/*
* usbd_device_event is used by bus interface drivers to tell the higher layers that
* certain events have taken place.
*/
void usbd_device_event_irq (struct usb_device_instance *conf, usb_device_event_t, int);
void usbd_device_event (struct usb_device_instance *conf, usb_device_event_t, int);
/* descriptors
*
* Various ways of finding descriptors based on the current device and any
* possible configuration / interface / endpoint for it.
*/
struct usb_configuration_descriptor *usbd_device_configuration_descriptor (struct usb_device_instance *, int, int);
struct usb_function_instance *usbd_device_function_instance (struct usb_device_instance *, unsigned int);
struct usb_interface_instance *usbd_device_interface_instance (struct usb_device_instance *, int, int, int);
struct usb_alternate_instance *usbd_device_alternate_instance (struct usb_device_instance *, int, int, int, int);
struct usb_interface_descriptor *usbd_device_interface_descriptor (struct usb_device_instance *, int, int, int, int);
struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor_index (struct usb_device_instance *, int, int, int, int, int);
struct usb_class_descriptor *usbd_device_class_descriptor_index (struct usb_device_instance *, int, int, int, int, int);
struct usb_class_report_descriptor *usbd_device_class_report_descriptor_index( struct usb_device_instance *, int , int , int , int , int );
struct usb_endpoint_descriptor *usbd_device_endpoint_descriptor (struct usb_device_instance *, int, int, int, int, int);
int usbd_device_endpoint_transfersize (struct usb_device_instance *, int, int, int, int, int);
struct usb_string_descriptor *usbd_get_string (u8);
struct usb_device_descriptor *usbd_device_device_descriptor (struct usb_device_instance *, int);
int usbd_endpoint_halted (struct usb_device_instance *device, int endpoint);
void usbd_rcv_complete(struct usb_endpoint_instance *endpoint, int len, int urb_bad);
void usbd_tx_complete (struct usb_endpoint_instance *endpoint);
/* These are macros used in debugging */
#ifdef DEBUG
static inline void print_urb(struct urb *u)
{
serial_printf("urb %p\n", (u));
serial_printf("\tendpoint %p\n", u->endpoint);
serial_printf("\tdevice %p\n", u->device);
serial_printf("\tbuffer %p\n", u->buffer);
serial_printf("\tbuffer_length %d\n", u->buffer_length);
serial_printf("\tactual_length %d\n", u->actual_length);
serial_printf("\tstatus %d\n", u->status);
serial_printf("\tdata %d\n", u->data);
}
static inline void print_usb_device_request(struct usb_device_request *r)
{
serial_printf("usb request\n");
serial_printf("\tbmRequestType 0x%2.2x\n", r->bmRequestType);
if ((r->bmRequestType & USB_REQ_DIRECTION_MASK) == 0)
serial_printf("\t\tDirection : To device\n");
else
serial_printf("\t\tDirection : To host\n");
if ((r->bmRequestType & USB_TYPE_STANDARD) == USB_TYPE_STANDARD)
serial_printf("\t\tType : Standard\n");
if ((r->bmRequestType & USB_TYPE_CLASS) == USB_TYPE_CLASS)
serial_printf("\t\tType : Standard\n");
if ((r->bmRequestType & USB_TYPE_VENDOR) == USB_TYPE_VENDOR)
serial_printf("\t\tType : Standard\n");
if ((r->bmRequestType & USB_TYPE_RESERVED) == USB_TYPE_RESERVED)
serial_printf("\t\tType : Standard\n");
if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
USB_REQ_RECIPIENT_DEVICE)
serial_printf("\t\tRecipient : Device\n");
if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
USB_REQ_RECIPIENT_INTERFACE)
serial_printf("\t\tRecipient : Interface\n");
if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
USB_REQ_RECIPIENT_ENDPOINT)
serial_printf("\t\tRecipient : Endpoint\n");
if ((r->bmRequestType & USB_REQ_RECIPIENT_MASK) ==
USB_REQ_RECIPIENT_OTHER)
serial_printf("\t\tRecipient : Other\n");
serial_printf("\tbRequest 0x%2.2x\n", r->bRequest);
if (r->bRequest == USB_REQ_GET_STATUS)
serial_printf("\t\tGET_STATUS\n");
else if (r->bRequest == USB_REQ_SET_ADDRESS)
serial_printf("\t\tSET_ADDRESS\n");
else if (r->bRequest == USB_REQ_SET_FEATURE)
serial_printf("\t\tSET_FEATURE\n");
else if (r->bRequest == USB_REQ_GET_DESCRIPTOR)
serial_printf("\t\tGET_DESCRIPTOR\n");
else if (r->bRequest == USB_REQ_SET_CONFIGURATION)
serial_printf("\t\tSET_CONFIGURATION\n");
else if (r->bRequest == USB_REQ_SET_INTERFACE)
serial_printf("\t\tUSB_REQ_SET_INTERFACE\n");
else
serial_printf("\tUNKNOWN %d\n", r->bRequest);
serial_printf("\twValue 0x%4.4x\n", r->wValue);
if (r->bRequest == USB_REQ_GET_DESCRIPTOR) {
switch (r->wValue >> 8) {
case USB_DESCRIPTOR_TYPE_DEVICE:
serial_printf("\tDEVICE\n");
break;
case USB_DESCRIPTOR_TYPE_CONFIGURATION:
serial_printf("\tCONFIGURATION\n");
break;
case USB_DESCRIPTOR_TYPE_STRING:
serial_printf("\tSTRING\n");
break;
case USB_DESCRIPTOR_TYPE_INTERFACE:
serial_printf("\tINTERFACE\n");
break;
case USB_DESCRIPTOR_TYPE_ENDPOINT:
serial_printf("\tENDPOINT\n");
break;
case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER:
serial_printf("\tDEVICE_QUALIFIER\n");
break;
case USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION:
serial_printf("\tOTHER_SPEED_CONFIGURATION\n");
break;
case USB_DESCRIPTOR_TYPE_INTERFACE_POWER:
serial_printf("\tINTERFACE_POWER\n");
break;
case USB_DESCRIPTOR_TYPE_HID:
serial_printf("\tHID\n");
break;
case USB_DESCRIPTOR_TYPE_REPORT:
serial_printf("\tREPORT\n");
break;
default:
serial_printf("\tUNKNOWN TYPE\n");
break;
}
}
serial_printf("\twIndex 0x%4.4x\n", r->wIndex);
serial_printf("\twLength 0x%4.4x\n", r->wLength);
}
#else
/* stubs */
#define print_urb(u)
#define print_usb_device_request(r)
#endif /* DEBUG */
#endif
|
1001-study-uboot
|
include/usbdevice.h
|
C
|
gpl3
| 22,865
|
/*
* (C) Copyright 2000
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _VIDEO_AD7176_H_
#define _VIDEO_AD7176_H_
#define VIDEO_ENCODER_NAME "Analog Devices AD7176"
#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */
#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
#undef VIDEO_MODE_RGB
#define VIDEO_MODE_BPP 16
#ifdef VIDEO_MODE_PAL
#define VIDEO_ACTIVE_COLS 720
#define VIDEO_ACTIVE_ROWS 576
#define VIDEO_VISIBLE_COLS 640
#define VIDEO_VISIBLE_ROWS 480
#endif
#ifdef VIDEO_MODE_NTSC
#define VIDEO_ACTIVE_COLS 720
#define VIDEO_ACTIVE_ROWS 525
#define VIDEO_VISIBLE_COLS 640
#define VIDEO_VISIBLE_ROWS 400
#endif
static unsigned char video_encoder_data[] = {
#ifdef VIDEO_MODE_NTSC
0x04, /* Mode Register 0 */
#ifdef VIDEO_DEBUG_COLORBARS
0x82,
#else
0x02, /* Mode Register 1 */
#endif /* VIDEO_DEBUG_COLORBARS */
0x16, /* Subcarrier Freq 0 */
0x7c, /* Subcarrier Freq 1 */
0xf0, /* Subcarrier Freq 2 */
0x21, /* Subcarrier Freq 3 */
0x00, /* Subcarrier phase */
0x02, /* Timing Register 0 */
0x00, /* Extended Captioning 0 */
0x00, /* Extended Captioning 1 */
0x00, /* Closed Captioning 0 */
0x00, /* Closed Captioning 1 */
0x00, /* Timing Register 1 */
0x08, /* Mode Register 2 */
0x00, /* Pedestal Register 0 */
0x00, /* Pedestal Register 1 */
0x00, /* Pedestal Register 2 */
0x00, /* Pedestal Register 3 */
0x00 /* Mode Register 3 */
#endif /* VIDEO_MODE_NTSC */
#ifdef VIDEO_MODE_PAL
0x05, /* Mode Register 0 */
#ifdef VIDEO_DEBUG_COLORBARS
0x82,
#else
0x02, /* Mode Register 1 (2) */
#endif /* VIDEO_DEBUG_COLORBARS */
0xcb, /* Subcarrier Freq 0 */
0x8a, /* Subcarrier Freq 1 */
0x09, /* Subcarrier Freq 2 */
0x2a, /* Subcarrier Freq 3 */
0x00, /* Subcarrier phase */
0x0a, /* Timing Register 0 (a) */
0x00, /* Extended Captioning 0 */
0x00, /* Extended Captioning 1 */
0x00, /* Closed Captioning 0 */
0x00, /* Closed Captioning 1 */
0x00, /* Timing Register 1 */
0x08, /* Mode Register 2 (8) */
0x00, /* Pedestal Register 0 */
0x00, /* Pedestal Register 1 */
0x00, /* Pedestal Register 2 */
0x00, /* Pedestal Register 3 */
0x00 /* Mode Register 3 */
#endif /* VIDEO_MODE_PAL */
} ;
#endif /* _VIDEO_AD7176_H_ */
|
1001-study-uboot
|
include/video_ad7176.h
|
C
|
gpl3
| 3,264
|
/*
* LiMon Monitor (LiMon) - Network.
*
* Copyright 1994 - 2000 Neil Russell.
* (See License)
*
*
* History
* 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
*/
#ifndef __NET_H__
#define __NET_H__
#if defined(CONFIG_8xx)
#include <commproc.h>
#endif /* CONFIG_8xx */
#include <asm/byteorder.h> /* for nton* / ntoh* stuff */
/*
* The number of receive packet buffers, and the required packet buffer
* alignment in memory.
*
*/
#ifdef CONFIG_SYS_RX_ETH_BUFFER
# define PKTBUFSRX CONFIG_SYS_RX_ETH_BUFFER
#else
# define PKTBUFSRX 4
#endif
#define PKTALIGN 32
/* IPv4 addresses are always 32 bits in size */
typedef u32 IPaddr_t;
/**
* An incoming packet handler.
* @param pkt pointer to the application packet
* @param dport destination UDP port
* @param sip source IP address
* @param sport source UDP port
* @param len packet length
*/
typedef void rxhand_f(uchar *pkt, unsigned dport,
IPaddr_t sip, unsigned sport,
unsigned len);
/**
* An incoming ICMP packet handler.
* @param type ICMP type
* @param code ICMP code
* @param dport destination UDP port
* @param sip source IP address
* @param sport source UDP port
* @param pkt pointer to the ICMP packet data
* @param len packet length
*/
typedef void rxhand_icmp_f(unsigned type, unsigned code, unsigned dport,
IPaddr_t sip, unsigned sport, uchar *pkt, unsigned len);
/*
* A timeout handler. Called after time interval has expired.
*/
typedef void thand_f(void);
#define NAMESIZE 16
enum eth_state_t {
ETH_STATE_INIT,
ETH_STATE_PASSIVE,
ETH_STATE_ACTIVE
};
struct eth_device {
char name[NAMESIZE];
unsigned char enetaddr[6];
int iobase;
int state;
int (*init) (struct eth_device*, bd_t*);
int (*send) (struct eth_device*, volatile void* packet, int length);
int (*recv) (struct eth_device*);
void (*halt) (struct eth_device*);
#ifdef CONFIG_MCAST_TFTP
int (*mcast) (struct eth_device*, u32 ip, u8 set);
#endif
int (*write_hwaddr) (struct eth_device*);
struct eth_device *next;
void *priv;
};
extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */
extern int eth_register(struct eth_device* dev);/* Register network device */
extern void eth_try_another(int first_restart); /* Change the device */
extern void eth_set_current(void); /* set nterface to ethcur var */
extern struct eth_device *eth_get_dev(void); /* get the current device MAC */
extern struct eth_device *eth_get_dev_by_name(const char *devname);
extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */
extern int eth_get_dev_index (void); /* get the device index */
extern void eth_parse_enetaddr(const char *addr, uchar *enetaddr);
extern int eth_getenv_enetaddr(char *name, uchar *enetaddr);
extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr);
/*
* Get the hardware address for an ethernet interface .
* Args:
* base_name - base name for device (normally "eth")
* index - device index number (0 for first)
* enetaddr - returns 6 byte hardware address
* Returns:
* Return true if the address is valid.
*/
extern int eth_getenv_enetaddr_by_index(const char *base_name, int index,
uchar *enetaddr);
extern int usb_eth_initialize(bd_t *bi);
extern int eth_init(bd_t *bis); /* Initialize the device */
extern int eth_send(volatile void *packet, int length); /* Send a packet */
#ifdef CONFIG_API
extern int eth_receive(volatile void *packet, int length); /* Receive a packet*/
#endif
extern int eth_rx(void); /* Check for received packets */
extern void eth_halt(void); /* stop SCC */
extern char *eth_get_name(void); /* get name of current device */
/*
* Set the hardware address for an ethernet interface based on 'eth%daddr'
* environment variable (or just 'ethaddr' if eth_number is 0).
* Args:
* base_name - base name for device (normally "eth")
* eth_number - value of %d (0 for first device of this type)
* Returns:
* 0 is success, non-zero is error status from driver.
*/
int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
int eth_number);
#ifdef CONFIG_MCAST_TFTP
int eth_mcast_join( IPaddr_t mcast_addr, u8 join);
u32 ether_crc (size_t len, unsigned char const *p);
#endif
/**********************************************************************/
/*
* Protocol headers.
*/
/*
* Ethernet header
*/
typedef struct {
uchar et_dest[6]; /* Destination node */
uchar et_src[6]; /* Source node */
ushort et_protlen; /* Protocol or length */
uchar et_dsap; /* 802 DSAP */
uchar et_ssap; /* 802 SSAP */
uchar et_ctl; /* 802 control */
uchar et_snap1; /* SNAP */
uchar et_snap2;
uchar et_snap3;
ushort et_prot; /* 802 protocol */
} Ethernet_t;
#define ETHER_HDR_SIZE 14 /* Ethernet header size */
#define E802_HDR_SIZE 22 /* 802 ethernet header size */
/*
* Ethernet header
*/
typedef struct {
uchar vet_dest[6]; /* Destination node */
uchar vet_src[6]; /* Source node */
ushort vet_vlan_type; /* PROT_VLAN */
ushort vet_tag; /* TAG of VLAN */
ushort vet_type; /* protocol type */
} VLAN_Ethernet_t;
#define VLAN_ETHER_HDR_SIZE 18 /* VLAN Ethernet header size */
#define PROT_IP 0x0800 /* IP protocol */
#define PROT_ARP 0x0806 /* IP ARP protocol */
#define PROT_RARP 0x8035 /* IP ARP protocol */
#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */
#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */
#define IPPROTO_UDP 17 /* User Datagram Protocol */
/*
* Internet Protocol (IP) header.
*/
typedef struct {
uchar ip_hl_v; /* header length and version */
uchar ip_tos; /* type of service */
ushort ip_len; /* total length */
ushort ip_id; /* identification */
ushort ip_off; /* fragment offset field */
uchar ip_ttl; /* time to live */
uchar ip_p; /* protocol */
ushort ip_sum; /* checksum */
IPaddr_t ip_src; /* Source IP address */
IPaddr_t ip_dst; /* Destination IP address */
ushort udp_src; /* UDP source port */
ushort udp_dst; /* UDP destination port */
ushort udp_len; /* Length of UDP packet */
ushort udp_xsum; /* Checksum */
} IP_t;
#define IP_OFFS 0x1fff /* ip offset *= 8 */
#define IP_FLAGS 0xe000 /* first 3 bits */
#define IP_FLAGS_RES 0x8000 /* reserved */
#define IP_FLAGS_DFRAG 0x4000 /* don't fragments */
#define IP_FLAGS_MFRAG 0x2000 /* more fragments */
#define IP_HDR_SIZE_NO_UDP (sizeof (IP_t) - 8)
#define IP_HDR_SIZE (sizeof (IP_t))
/*
* Address Resolution Protocol (ARP) header.
*/
typedef struct
{
ushort ar_hrd; /* Format of hardware address */
# define ARP_ETHER 1 /* Ethernet hardware address */
ushort ar_pro; /* Format of protocol address */
uchar ar_hln; /* Length of hardware address */
uchar ar_pln; /* Length of protocol address */
ushort ar_op; /* Operation */
# define ARPOP_REQUEST 1 /* Request to resolve address */
# define ARPOP_REPLY 2 /* Response to previous request */
# define RARPOP_REQUEST 3 /* Request to resolve address */
# define RARPOP_REPLY 4 /* Response to previous request */
/*
* The remaining fields are variable in size, according to
* the sizes above, and are defined as appropriate for
* specific hardware/protocol combinations.
*/
uchar ar_data[0];
#if 0
uchar ar_sha[]; /* Sender hardware address */
uchar ar_spa[]; /* Sender protocol address */
uchar ar_tha[]; /* Target hardware address */
uchar ar_tpa[]; /* Target protocol address */
#endif /* 0 */
} ARP_t;
#define ARP_HDR_SIZE (8+20) /* Size assuming ethernet */
/*
* ICMP stuff (just enough to handle (host) redirect messages)
*/
#define ICMP_ECHO_REPLY 0 /* Echo reply */
#define ICMP_NOT_REACH 3 /* Detination unreachable */
#define ICMP_REDIRECT 5 /* Redirect (change route) */
#define ICMP_ECHO_REQUEST 8 /* Echo request */
/* Codes for REDIRECT. */
#define ICMP_REDIR_NET 0 /* Redirect Net */
#define ICMP_REDIR_HOST 1 /* Redirect Host */
/* Codes for NOT_REACH */
#define ICMP_NOT_REACH_PORT 3 /* Port unreachable */
typedef struct icmphdr {
uchar type;
uchar code;
ushort checksum;
union {
struct {
ushort id;
ushort sequence;
} echo;
ulong gateway;
struct {
ushort __unused;
ushort mtu;
} frag;
uchar data[0];
} un;
} ICMP_t;
/*
* Maximum packet size; used to allocate packet storage.
* TFTP packets can be 524 bytes + IP header + ethernet header.
* Lets be conservative, and go for 38 * 16. (Must also be
* a multiple of 32 bytes).
*/
/*
* AS.HARNOIS : Better to set PKTSIZE to maximum size because
* traffic type is not always controlled
* maximum packet size = 1518
* maximum packet size and multiple of 32 bytes = 1536
*/
#define PKTSIZE 1518
#define PKTSIZE_ALIGN 1536
/*#define PKTSIZE 608*/
/*
* Maximum receive ring size; that is, the number of packets
* we can buffer before overflow happens. Basically, this just
* needs to be enough to prevent a packet being discarded while
* we are processing the previous one.
*/
#define RINGSZ 4
#define RINGSZ_LOG2 2
/**********************************************************************/
/*
* Globals.
*
* Note:
*
* All variables of type IPaddr_t are stored in NETWORK byte order
* (big endian).
*/
/* net.c */
/** BOOTP EXTENTIONS **/
extern IPaddr_t NetOurGatewayIP; /* Our gateway IP addresse */
extern IPaddr_t NetOurSubnetMask; /* Our subnet mask (0 = unknown)*/
extern IPaddr_t NetOurDNSIP; /* Our Domain Name Server (0 = unknown)*/
#if defined(CONFIG_BOOTP_DNS2)
extern IPaddr_t NetOurDNS2IP; /* Our 2nd Domain Name Server (0 = unknown)*/
#endif
extern char NetOurNISDomain[32]; /* Our NIS domain */
extern char NetOurHostName[32]; /* Our hostname */
extern char NetOurRootPath[64]; /* Our root path */
extern ushort NetBootFileSize; /* Our boot file size in blocks */
/** END OF BOOTP EXTENTIONS **/
extern ulong NetBootFileXferSize; /* size of bootfile in bytes */
extern uchar NetOurEther[6]; /* Our ethernet address */
extern uchar NetServerEther[6]; /* Boot server enet address */
extern IPaddr_t NetOurIP; /* Our IP addr (0 = unknown) */
extern IPaddr_t NetServerIP; /* Server IP addr (0 = unknown) */
extern volatile uchar * NetTxPacket; /* THE transmit packet */
extern volatile uchar * NetRxPackets[PKTBUFSRX];/* Receive packets */
extern volatile uchar * NetRxPacket; /* Current receive packet */
extern int NetRxPacketLen; /* Current rx packet length */
extern unsigned NetIPID; /* IP ID (counting) */
extern uchar NetBcastAddr[6]; /* Ethernet boardcast address */
extern uchar NetEtherNullAddr[6];
#define VLAN_NONE 4095 /* untagged */
#define VLAN_IDMASK 0x0fff /* mask of valid vlan id */
extern ushort NetOurVLAN; /* Our VLAN */
extern ushort NetOurNativeVLAN; /* Our Native VLAN */
extern uchar NetCDPAddr[6]; /* Ethernet CDP address */
extern ushort CDPNativeVLAN; /* CDP returned native VLAN */
extern ushort CDPApplianceVLAN; /* CDP returned appliance VLAN */
extern int NetState; /* Network loop state */
#define NETLOOP_CONTINUE 1
#define NETLOOP_RESTART 2
#define NETLOOP_SUCCESS 3
#define NETLOOP_FAIL 4
extern int NetRestartWrap; /* Tried all network devices */
enum proto_t {
BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
TFTPSRV, TFTPPUT
};
/* from net/net.c */
extern char BootFile[128]; /* Boot File name */
#if defined(CONFIG_CMD_DNS)
extern char *NetDNSResolve; /* The host to resolve */
extern char *NetDNSenvvar; /* the env var to put the ip into */
#endif
#if defined(CONFIG_CMD_PING)
extern IPaddr_t NetPingIP; /* the ip address to ping */
#endif
#if defined(CONFIG_CMD_CDP)
/* when CDP completes these hold the return values */
extern ushort CDPNativeVLAN;
extern ushort CDPApplianceVLAN;
#endif
#if defined(CONFIG_CMD_SNTP)
extern IPaddr_t NetNtpServerIP; /* the ip address to NTP */
extern int NetTimeOffset; /* offset time from UTC */
#endif
/* Initialize the network adapter */
extern int NetLoop(enum proto_t);
/* Shutdown adapters and cleanup */
extern void NetStop(void);
/* Load failed. Start again. */
extern void NetStartAgain(void);
/* Get size of the ethernet header when we send */
extern int NetEthHdrSize(void);
/* Set ethernet header; returns the size of the header */
extern int NetSetEther(volatile uchar *, uchar *, uint);
/* Set IP header */
extern void NetSetIP(volatile uchar *, IPaddr_t, int, int, int);
/* Checksum */
extern int NetCksumOk(uchar *, int); /* Return true if cksum OK */
extern uint NetCksum(uchar *, int); /* Calculate the checksum */
/* Set callbacks */
extern void NetSetHandler(rxhand_f *); /* Set RX packet handler */
extern void net_set_icmp_handler(rxhand_icmp_f *f); /* Set ICMP RX handler */
extern void NetSetTimeout(ulong, thand_f *);/* Set timeout handler */
/* Transmit "NetTxPacket" */
extern void NetSendPacket(volatile uchar *, int);
/* Transmit UDP packet, performing ARP request if needed */
extern int NetSendUDPPacket(uchar *ether, IPaddr_t dest, int dport, int sport, int len);
/* Processes a received packet */
extern void NetReceive(volatile uchar *, int);
/*
* Check if autoload is enabled. If so, use either NFS or TFTP to download
* the boot file.
*/
void net_auto_load(void);
/*
* The following functions are a bit ugly, but necessary to deal with
* alignment restrictions on ARM.
*
* We're using inline functions, which had the smallest memory
* footprint in our tests.
*/
/* return IP *in network byteorder* */
static inline IPaddr_t NetReadIP(volatile void *from)
{
IPaddr_t ip;
memcpy((void*)&ip, (void*)from, sizeof(ip));
return ip;
}
/* return ulong *in network byteorder* */
static inline ulong NetReadLong(ulong *from)
{
ulong l;
memcpy((void*)&l, (void*)from, sizeof(l));
return l;
}
/* write IP *in network byteorder* */
static inline void NetWriteIP(void *to, IPaddr_t ip)
{
memcpy(to, (void*)&ip, sizeof(ip));
}
/* copy IP */
static inline void NetCopyIP(volatile void *to, void *from)
{
memcpy((void*)to, from, sizeof(IPaddr_t));
}
/* copy ulong */
static inline void NetCopyLong(ulong *to, ulong *from)
{
memcpy((void*)to, (void*)from, sizeof(ulong));
}
/**
* is_zero_ether_addr - Determine if give Ethernet address is all zeros.
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Return true if the address is all zeroes.
*/
static inline int is_zero_ether_addr(const u8 *addr)
{
return !(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5]);
}
/**
* is_multicast_ether_addr - Determine if the Ethernet address is a multicast.
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Return true if the address is a multicast address.
* By definition the broadcast address is also a multicast address.
*/
static inline int is_multicast_ether_addr(const u8 *addr)
{
return (0x01 & addr[0]);
}
/*
* is_broadcast_ether_addr - Determine if the Ethernet address is broadcast
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Return true if the address is the broadcast address.
*/
static inline int is_broadcast_ether_addr(const u8 *addr)
{
return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) == 0xff;
}
/*
* is_valid_ether_addr - Determine if the given Ethernet address is valid
* @addr: Pointer to a six-byte array containing the Ethernet address
*
* Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not
* a multicast address, and is not FF:FF:FF:FF:FF:FF.
*
* Return true if the address is valid.
*/
static inline int is_valid_ether_addr(const u8 *addr)
{
/* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to
* explicitly check for it here. */
return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr);
}
/* Convert an IP address to a string */
extern void ip_to_string (IPaddr_t x, char *s);
/* Convert a string to ip address */
extern IPaddr_t string_to_ip(const char *s);
/* Convert a VLAN id to a string */
extern void VLAN_to_string (ushort x, char *s);
/* Convert a string to a vlan id */
extern ushort string_to_VLAN(const char *s);
/* read a VLAN id from an environment variable */
extern ushort getenv_VLAN(char *);
/* copy a filename (allow for "..." notation, limit length) */
extern void copy_filename (char *dst, const char *src, int size);
/* get a random source port */
extern unsigned int random_port(void);
/**********************************************************************/
#endif /* __NET_H__ */
|
1001-study-uboot
|
include/net.h
|
C
|
gpl3
| 16,508
|
/*
* Copyright 2006 Freescale Semiconductor.
* Jeffrey Brown
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
*/
#ifndef __MPC86xx_H__
#define __MPC86xx_H__
#include <asm/fsl_lbc.h>
#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*
* platform register addresses
*/
#define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4)
#define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000)
#define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008)
/*
* l2cr values. Look in config_<BOARD>.h for the actual setup
*/
#define l2cr 1017
#define L2CR_L2E 0x80000000 /* bit 0 - enable */
#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */
#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */
#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
#define HID0_XBSEN 0x00000100
#define HID0_HIGH_BAT_EN 0x00800000
#define HID0_XAEN 0x00020000
#ifndef __ASSEMBLY__
typedef struct {
unsigned long freqProcessor;
unsigned long freqSystemBus;
unsigned long freqLocalBus;
} MPC86xx_SYS_INFO;
#define l1icache_enable icache_enable
void l2cache_enable(void);
void l1dcache_enable(void);
static __inline__ unsigned long get_hid0 (void)
{
unsigned long hid0;
asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
return hid0;
}
static __inline__ unsigned long get_hid1 (void)
{
unsigned long hid1;
asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
return hid1;
}
static __inline__ void set_hid0 (unsigned long hid0)
{
asm volatile("mtspr 1008, %0" : : "r" (hid0));
}
static __inline__ void set_hid1 (unsigned long hid1)
{
asm volatile("mtspr 1009, %0" : : "r" (hid1));
}
static __inline__ unsigned long get_l2cr (void)
{
unsigned long l2cr_val;
asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
return l2cr_val;
}
void setup_ddr_bat(phys_addr_t dram_size);
extern void setup_bats(void);
#endif /* _ASMLANGUAGE */
#endif /* __MPC86xx_H__ */
|
1001-study-uboot
|
include/mpc86xx.h
|
C
|
gpl3
| 2,251
|
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
/* I2C chip addresses */
#define TWL6030_CHIP_PM 0x48
#define TWL6030_CHIP_USB 0x49
#define TWL6030_CHIP_ADC 0x49
#define TWL6030_CHIP_CHARGER 0x49
#define TWL6030_CHIP_PWM 0x49
/* Slave Address 0x48 */
#define VMMC_CFG_STATE 0x9A
#define VMMC_CFG_VOLTATE 0x9B
#define VUSB_CFG_STATE 0xA2
#define MISC1 0xE4
#define VAC_MEAS (1 << 2)
#define VBAT_MEAS (1 << 1)
#define BB_MEAS (1 << 0)
#define MISC2 0xE5
/* Slave Address 0x49 */
/* Battery CHARGER REGISTERS */
#define CONTROLLER_INT_MASK 0xE0
#define CONTROLLER_CTRL1 0xE1
#define CONTROLLER_WDG 0xE2
#define CONTROLLER_STAT1 0xE3
#define CHARGERUSB_INT_STATUS 0xE4
#define CHARGERUSB_INT_MASK 0xE5
#define CHARGERUSB_STATUS_INT1 0xE6
#define CHARGERUSB_STATUS_INT2 0xE7
#define CHARGERUSB_CTRL1 0xE8
#define CHARGERUSB_CTRL2 0xE9
#define CHARGERUSB_CTRL3 0xEA
#define CHARGERUSB_STAT1 0xEB
#define CHARGERUSB_VOREG 0xEC
#define CHARGERUSB_VICHRG 0xED
#define CHARGERUSB_CINLIMIT 0xEE
#define CHARGERUSB_CTRLLIMIT1 0xEF
/* CHARGERUSB_VICHRG */
#define CHARGERUSB_VICHRG_500 0x4
#define CHARGERUSB_VICHRG_1500 0xE
/* CHARGERUSB_CINLIMIT */
#define CHARGERUSB_CIN_LIMIT_100 0x1
#define CHARGERUSB_CIN_LIMIT_300 0x5
#define CHARGERUSB_CIN_LIMIT_500 0x9
#define CHARGERUSB_CIN_LIMIT_NONE 0xF
/* CONTROLLER_INT_MASK */
#define MVAC_FAULT (1 << 6)
#define MAC_EOC (1 << 5)
#define MBAT_REMOVED (1 << 4)
#define MFAULT_WDG (1 << 3)
#define MBAT_TEMP (1 << 2)
#define MVBUS_DET (1 << 1)
#define MVAC_DET (1 << 0)
/* CHARGERUSB_INT_MASK */
#define MASK_MCURRENT_TERM (1 << 3)
#define MASK_MCHARGERUSB_STAT (1 << 2)
#define MASK_MCHARGERUSB_THMREG (1 << 1)
#define MASK_MCHARGERUSB_FAULT (1 << 0)
/* CHARGERUSB_VOREG */
#define CHARGERUSB_VOREG_3P52 0x01
#define CHARGERUSB_VOREG_4P0 0x19
#define CHARGERUSB_VOREG_4P2 0x23
#define CHARGERUSB_VOREG_4P76 0x3F
/* CHARGERUSB_CTRL1 */
#define SUSPEND_BOOT (1 << 7)
#define OPA_MODE (1 << 6)
#define HZ_MODE (1 << 5)
#define TERM (1 << 4)
/* CHARGERUSB_CTRL2 */
#define CHARGERUSB_CTRL2_VITERM_50 (0 << 5)
#define CHARGERUSB_CTRL2_VITERM_100 (1 << 5)
#define CHARGERUSB_CTRL2_VITERM_150 (2 << 5)
#define CHARGERUSB_CTRL2_VITERM_400 (7 << 5)
/* CONTROLLER_CTRL1 */
#define CONTROLLER_CTRL1_EN_CHARGER (1 << 4)
#define CONTROLLER_CTRL1_SEL_CHARGER (1 << 3)
/* CONTROLLER_STAT1 */
#define CHRG_EXTCHRG_STATZ (1 << 7)
#define CHRG_DET_N (1 << 5)
#define VAC_DET (1 << 3)
#define VBUS_DET (1 << 2)
#define FG_REG_10 0xCA
#define FG_REG_11 0xCB
#define TOGGLE1 0x90
#define FGS (1 << 5)
#define FGR (1 << 4)
#define GPADCS (1 << 1)
#define GPADCR (1 << 0)
#define CTRL_P2 0x34
#define CTRL_P2_SP2 (1 << 2)
#define CTRL_P2_EOCP2 (1 << 1)
#define CTRL_P2_BUSY (1 << 0)
#define GPCH0_LSB 0x57
#define GPCH0_MSB 0x58
void twl6030_init_battery_charging(void);
void twl6030_usb_device_settings(void);
void twl6030_start_usb_charging(void);
void twl6030_stop_usb_charging(void);
int twl6030_get_battery_voltage(void);
int twl6030_get_battery_current(void);
void twl6030_power_mmc_init(void);
|
1001-study-uboot
|
include/twl6030.h
|
C
|
gpl3
| 3,922
|
/*
* Copyright 2007, 2011 Freescale Semiconductor, Inc.
* Authors: York Sun <yorksun@freescale.com>
* Timur Tabi <timur@freescale.com>
*
* FSL DIU Framebuffer driver
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix);
/* Prototypes for external board-specific functions */
int platform_diu_init(unsigned int xres, unsigned int yres, const char *port);
void diu_set_pixel_clock(unsigned int pixclock);
|
1001-study-uboot
|
include/fsl_diu_fb.h
|
C
|
gpl3
| 1,235
|
/* Permission is hereby granted to copy, modify and redistribute this code
* in terms of the GNU Library General Public License, Version 2 or later,
* at your option.
*/
/* inline functions to translate to/from binary and binary-coded decimal
* (frequently found in RTC chips).
*/
#ifndef _BCD_H
#define _BCD_H
#include <linux/types.h>
static inline unsigned int bcd2bin(u8 val)
{
return ((val) & 0x0f) + ((val) >> 4) * 10;
}
static inline u8 bin2bcd (unsigned int val)
{
return (((val / 10) << 4) | (val % 10));
}
#endif /* _BCD_H */
|
1001-study-uboot
|
include/bcd.h
|
C
|
gpl3
| 548
|
/*
* i82365.h 1.21 2001/08/24 12:15:33
*
* The contents of this file are subject to the Mozilla Public License
* Version 1.1 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License
* at http://www.mozilla.org/MPL/
*
* Software distributed under the License is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
* the License for the specific language governing rights and
* limitations under the License.
*
* The initial developer of the original code is David A. Hinds
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
*
* Alternatively, the contents of this file may be used under the
* terms of the GNU General Public License version 2 (the "GPL"), in
* which case the provisions of the GPL are applicable instead of the
* above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use
* your version of this file under the MPL, indicate your decision by
* deleting the provisions above and replace them with the notice and
* other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file
* under either the MPL or the GPL.
*/
#ifndef _LINUX_I82365_H
#define _LINUX_I82365_H
/* register definitions for the Intel 82365SL PCMCIA controller */
/* Offsets for PCIC registers */
#define I365_IDENT 0x00 /* Identification and revision */
#define I365_STATUS 0x01 /* Interface status */
#define I365_POWER 0x02 /* Power and RESETDRV control */
#define I365_INTCTL 0x03 /* Interrupt and general control */
#define I365_CSC 0x04 /* Card status change */
#define I365_CSCINT 0x05 /* Card status change interrupt control */
#define I365_ADDRWIN 0x06 /* Address window enable */
#define I365_IOCTL 0x07 /* I/O control */
#define I365_GENCTL 0x16 /* Card detect and general control */
#define I365_GBLCTL 0x1E /* Global control register */
/* Offsets for I/O and memory window registers */
#define I365_IO(map) (0x08+((map)<<2))
#define I365_MEM(map) (0x10+((map)<<3))
#define I365_W_START 0
#define I365_W_STOP 2
#define I365_W_OFF 4
/* Flags for I365_STATUS */
#define I365_CS_BVD1 0x01
#define I365_CS_STSCHG 0x01
#define I365_CS_BVD2 0x02
#define I365_CS_SPKR 0x02
#define I365_CS_DETECT 0x0C
#define I365_CS_WRPROT 0x10
#define I365_CS_READY 0x20 /* Inverted */
#define I365_CS_POWERON 0x40
#define I365_CS_GPI 0x80
/* Flags for I365_POWER */
#define I365_PWR_OFF 0x00 /* Turn off the socket */
#define I365_PWR_OUT 0x80 /* Output enable */
#define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */
#define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */
#define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */
/* There are different layouts for B-step and DF-step chips: the B
step has independent Vpp1/Vpp2 control, and the DF step has only
Vpp1 control, plus 3V control */
#define I365_VCC_5V 0x10 /* Vcc = 5.0v */
#define I365_VCC_3V 0x18 /* Vcc = 3.3v */
#define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */
#define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */
#define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */
#define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */
#define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */
#define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */
/* Flags for I365_INTCTL */
#define I365_RING_ENA 0x80
#define I365_PC_RESET 0x40
#define I365_PC_IOCARD 0x20
#define I365_INTR_ENA 0x10
#define I365_IRQ_MASK 0x0F
/* Flags for I365_CSC and I365_CSCINT*/
#define I365_CSC_BVD1 0x01
#define I365_CSC_STSCHG 0x01
#define I365_CSC_BVD2 0x02
#define I365_CSC_READY 0x04
#define I365_CSC_DETECT 0x08
#define I365_CSC_ANY 0x0F
#define I365_CSC_GPI 0x10
/* Flags for I365_ADDRWIN */
#define I365_ADDR_MEMCS16 0x20
#define I365_ENA_IO(map) (0x40 << (map))
#define I365_ENA_MEM(map) (0x01 << (map))
/* Flags for I365_IOCTL */
#define I365_IOCTL_MASK(map) (0x0F << (map<<2))
#define I365_IOCTL_WAIT(map) (0x08 << (map<<2))
#define I365_IOCTL_0WS(map) (0x04 << (map<<2))
#define I365_IOCTL_IOCS16(map) (0x02 << (map<<2))
#define I365_IOCTL_16BIT(map) (0x01 << (map<<2))
/* Flags for I365_GENCTL */
#define I365_CTL_16DELAY 0x01
#define I365_CTL_RESET 0x02
#define I365_CTL_GPI_ENA 0x04
#define I365_CTL_GPI_CTL 0x08
#define I365_CTL_RESUME 0x10
#define I365_CTL_SW_IRQ 0x20
/* Flags for I365_GBLCTL */
#define I365_GBL_PWRDOWN 0x01
#define I365_GBL_CSC_LEV 0x02
#define I365_GBL_WRBACK 0x04
#define I365_GBL_IRQ_0_LEV 0x08
#define I365_GBL_IRQ_1_LEV 0x10
/* Flags for memory window registers */
#define I365_MEM_16BIT 0x8000 /* In memory start high byte */
#define I365_MEM_0WS 0x4000
#define I365_MEM_WS1 0x8000 /* In memory stop high byte */
#define I365_MEM_WS0 0x4000
#define I365_MEM_WRPROT 0x8000 /* In offset high byte */
#define I365_MEM_REG 0x4000
#define I365_REG(slot, reg) (((slot) << 6) | (reg))
/* Default ISA interrupt mask */
#define I365_ISA_IRQ_MASK 0xdeb8 /* irq's 3-5,7,9-12,14,15 */
/* Device ID's for PCI-to-PCMCIA bridges */
#ifndef PCI_VENDOR_ID_INTEL
#define PCI_VENDOR_ID_INTEL 0x8086
#endif
#ifndef PCI_DEVICE_ID_INTEL_82092AA_0
#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
#endif
#ifndef PCI_VENDOR_ID_OMEGA
#define PCI_VENDOR_ID_OMEGA 0x119b
#endif
#ifndef PCI_DEVICE_ID_OMEGA_82C092G
#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221
#endif
#endif /* _LINUX_I82365_H */
|
1001-study-uboot
|
include/pcmcia/i82365.h
|
C
|
gpl3
| 5,480
|
/*
* yenta.h 1.20 2001/08/24 12:15:34
*
* The contents of this file are subject to the Mozilla Public License
* Version 1.1 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License
* at http://www.mozilla.org/MPL/
*
* Software distributed under the License is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
* the License for the specific language governing rights and
* limitations under the License.
*
* The initial developer of the original code is David A. Hinds
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
*
* Alternatively, the contents of this file may be used under the
* terms of the GNU General Public License version 2 (the "GPL"), in
* which case the provisions of the GPL are applicable instead of the
* above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use
* your version of this file under the MPL, indicate your decision by
* deleting the provisions above and replace them with the notice and
* other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file
* under either the MPL or the GPL.
*/
#ifndef _LINUX_YENTA_H
#define _LINUX_YENTA_H
/* PCI Configuration Registers */
#define PCI_STATUS_CAPLIST 0x10
#define PCI_CB_CAPABILITY_POINTER 0x14 /* 8 bit */
#define PCI_CAPABILITY_ID 0x00 /* 8 bit */
#define PCI_CAPABILITY_PM 0x01
#define PCI_NEXT_CAPABILITY 0x01 /* 8 bit */
#define PCI_PM_CAPABILITIES 0x02 /* 16 bit */
#define PCI_PMCAP_PME_D3COLD 0x8000
#define PCI_PMCAP_PME_D3HOT 0x4000
#define PCI_PMCAP_PME_D2 0x2000
#define PCI_PMCAP_PME_D1 0x1000
#define PCI_PMCAP_PME_D0 0x0800
#define PCI_PMCAP_D2_CAP 0x0400
#define PCI_PMCAP_D1_CAP 0x0200
#define PCI_PMCAP_DYN_DATA 0x0100
#define PCI_PMCAP_DSI 0x0020
#define PCI_PMCAP_AUX_PWR 0x0010
#define PCI_PMCAP_PMECLK 0x0008
#define PCI_PMCAP_VERSION_MASK 0x0007
#define PCI_PM_CONTROL_STATUS 0x04 /* 16 bit */
#define PCI_PMCS_PME_STATUS 0x8000
#define PCI_PMCS_DATASCALE_MASK 0x6000
#define PCI_PMCS_DATASCALE_SHIFT 13
#define PCI_PMCS_DATASEL_MASK 0x1e00
#define PCI_PMCS_DATASEL_SHIFT 9
#define PCI_PMCS_PME_ENABLE 0x0100
#define PCI_PMCS_PWR_STATE_MASK 0x0003
#define PCI_PMCS_PWR_STATE_D0 0x0000
#define PCI_PMCS_PWR_STATE_D1 0x0001
#define PCI_PMCS_PWR_STATE_D2 0x0002
#define PCI_PMCS_PWR_STATE_D3 0x0003
#define PCI_PM_BRIDGE_EXT 0x06 /* 8 bit */
#define PCI_PM_DATA 0x07 /* 8 bit */
#define CB_PRIMARY_BUS 0x18 /* 8 bit */
#define CB_CARDBUS_BUS 0x19 /* 8 bit */
#define CB_SUBORD_BUS 0x1a /* 8 bit */
#define CB_LATENCY_TIMER 0x1b /* 8 bit */
#define CB_MEM_BASE(m) (0x1c + 8*(m))
#define CB_MEM_LIMIT(m) (0x20 + 8*(m))
#define CB_IO_BASE(m) (0x2c + 8*(m))
#define CB_IO_LIMIT(m) (0x30 + 8*(m))
#define CB_BRIDGE_CONTROL 0x3e /* 16 bit */
#define CB_BCR_PARITY_ENA 0x0001
#define CB_BCR_SERR_ENA 0x0002
#define CB_BCR_ISA_ENA 0x0004
#define CB_BCR_VGA_ENA 0x0008
#define CB_BCR_MABORT 0x0020
#define CB_BCR_CB_RESET 0x0040
#define CB_BCR_ISA_IRQ 0x0080
#define CB_BCR_PREFETCH(m) (0x0100 << (m))
#define CB_BCR_WRITE_POST 0x0400
#define CB_LEGACY_MODE_BASE 0x44
/* Memory mapped registers */
#define CB_SOCKET_EVENT 0x0000
#define CB_SE_CSTSCHG 0x00000001
#define CB_SE_CCD 0x00000006
#define CB_SE_CCD1 0x00000002
#define CB_SE_CCD2 0x00000004
#define CB_SE_PWRCYCLE 0x00000008
#define CB_SOCKET_MASK 0x0004
#define CB_SM_CSTSCHG 0x00000001
#define CB_SM_CCD 0x00000006
#define CB_SM_PWRCYCLE 0x00000008
#define CB_SOCKET_STATE 0x0008
#define CB_SS_CSTSCHG 0x00000001
#define CB_SS_CCD 0x00000006
#define CB_SS_CCD1 0x00000002
#define CB_SS_CCD2 0x00000004
#define CB_SS_PWRCYCLE 0x00000008
#define CB_SS_16BIT 0x00000010
#define CB_SS_32BIT 0x00000020
#define CB_SS_CINT 0x00000040
#define CB_SS_BADCARD 0x00000080
#define CB_SS_DATALOST 0x00000100
#define CB_SS_BADVCC 0x00000200
#define CB_SS_5VCARD 0x00000400
#define CB_SS_3VCARD 0x00000800
#define CB_SS_XVCARD 0x00001000
#define CB_SS_YVCARD 0x00002000
#define CB_SS_VSENSE 0x00003c86
#define CB_SS_5VSOCKET 0x10000000
#define CB_SS_3VSOCKET 0x20000000
#define CB_SS_XVSOCKET 0x40000000
#define CB_SS_YVSOCKET 0x80000000
#define CB_SOCKET_FORCE 0x000c
#define CB_SF_CVSTEST 0x00004000
#define CB_SOCKET_CONTROL 0x0010
#define CB_SC_VPP_MASK 0x00000007
#define CB_SC_VPP_OFF 0x00000000
#define CB_SC_VPP_12V 0x00000001
#define CB_SC_VPP_5V 0x00000002
#define CB_SC_VPP_3V 0x00000003
#define CB_SC_VPP_XV 0x00000004
#define CB_SC_VPP_YV 0x00000005
#define CB_SC_VCC_MASK 0x00000070
#define CB_SC_VCC_OFF 0x00000000
#define CB_SC_VCC_5V 0x00000020
#define CB_SC_VCC_3V 0x00000030
#define CB_SC_VCC_XV 0x00000040
#define CB_SC_VCC_YV 0x00000050
#define CB_SC_CCLK_STOP 0x00000080
#define CB_SOCKET_POWER 0x0020
#define CB_SP_CLK_CTRL 0x00000001
#define CB_SP_CLK_CTRL_ENA 0x00010000
#define CB_SP_CLK_MODE 0x01000000
#define CB_SP_ACCESS 0x02000000
/* Address bits 31..24 for memory windows for 16-bit cards,
accessable only by memory mapping the 16-bit register set */
#define CB_MEM_PAGE(map) (0x40 + (map))
#endif /* _LINUX_YENTA_H */
|
1001-study-uboot
|
include/pcmcia/yenta.h
|
C
|
gpl3
| 5,524
|
/*
* ss.h 1.31 2001/08/24 12:16:13
*
* The contents of this file are subject to the Mozilla Public License
* Version 1.1 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License
* at http://www.mozilla.org/MPL/
*
* Software distributed under the License is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
* the License for the specific language governing rights and
* limitations under the License.
*
* The initial developer of the original code is David A. Hinds
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
*
* Alternatively, the contents of this file may be used under the
* terms of the GNU General Public License version 2 (the "GPL"), in
* which case the provisions of the GPL are applicable instead of the
* above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use
* your version of this file under the MPL, indicate your decision by
* deleting the provisions above and replace them with the notice and
* other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file
* under either the MPL or the GPL.
*/
#ifndef _LINUX_SS_H
#define _LINUX_SS_H
/* For RegisterCallback */
typedef struct ss_callback_t {
void (*handler)(void *info, u_int events);
void *info;
} ss_callback_t;
/* Definitions for card status flags for GetStatus */
#define SS_WRPROT 0x0001
#define SS_CARDLOCK 0x0002
#define SS_EJECTION 0x0004
#define SS_INSERTION 0x0008
#define SS_BATDEAD 0x0010
#define SS_BATWARN 0x0020
#define SS_READY 0x0040
#define SS_DETECT 0x0080
#define SS_POWERON 0x0100
#define SS_GPI 0x0200
#define SS_STSCHG 0x0400
#define SS_CARDBUS 0x0800
#define SS_3VCARD 0x1000
#define SS_XVCARD 0x2000
#define SS_PENDING 0x4000
/* for InquireSocket */
typedef struct socket_cap_t {
u_int features;
u_int irq_mask;
u_int map_size;
u_char pci_irq;
u_char cardbus;
struct pci_bus *cb_bus;
struct bus_operations *bus;
} socket_cap_t;
/* InquireSocket capabilities */
#define SS_CAP_PAGE_REGS 0x0001
#define SS_CAP_VIRTUAL_BUS 0x0002
#define SS_CAP_MEM_ALIGN 0x0004
#define SS_CAP_STATIC_MAP 0x0008
#define SS_CAP_PCCARD 0x4000
#define SS_CAP_CARDBUS 0x8000
/* for GetSocket, SetSocket */
typedef struct socket_state_t {
u_int flags;
u_int csc_mask;
u_char Vcc, Vpp;
u_char io_irq;
} socket_state_t;
/* Socket configuration flags */
#define SS_PWR_AUTO 0x0010
#define SS_IOCARD 0x0020
#define SS_RESET 0x0040
#define SS_DMA_MODE 0x0080
#define SS_SPKR_ENA 0x0100
#define SS_OUTPUT_ENA 0x0200
#define SS_ZVCARD 0x0400
/* Flags for I/O port and memory windows */
#define MAP_ACTIVE 0x01
#define MAP_16BIT 0x02
#define MAP_AUTOSZ 0x04
#define MAP_0WS 0x08
#define MAP_WRPROT 0x10
#define MAP_ATTRIB 0x20
#define MAP_USE_WAIT 0x40
#define MAP_PREFETCH 0x80
/* Use this just for bridge windows */
#define MAP_IOSPACE 0x20
typedef struct pccard_io_map {
u_char map;
u_char flags;
u_short speed;
u_short start, stop;
} pccard_io_map;
typedef struct pccard_mem_map {
u_char map;
u_char flags;
u_short speed;
u_long sys_start, sys_stop;
u_int card_start;
} pccard_mem_map;
typedef struct cb_bridge_map {
u_char map;
u_char flags;
u_int start, stop;
} cb_bridge_map;
enum ss_service {
SS_RegisterCallback, SS_InquireSocket,
SS_GetStatus, SS_GetSocket, SS_SetSocket,
SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap,
SS_GetBridge, SS_SetBridge, SS_ProcSetup
};
#endif /* _LINUX_SS_H */
|
1001-study-uboot
|
include/pcmcia/ss.h
|
C
|
gpl3
| 3,769
|
/*
* ti113x.h 1.31 2002/05/12 18:19:47
*
* The contents of this file are subject to the Mozilla Public License
* Version 1.1 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License
* at http://www.mozilla.org/MPL/
*
* Software distributed under the License is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
* the License for the specific language governing rights and
* limitations under the License.
*
* The initial developer of the original code is David A. Hinds
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
*
* Alternatively, the contents of this file may be used under the
* terms of the GNU General Public License version 2 (the "GPL"), in
* which case the provisions of the GPL are applicable instead of the
* above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use
* your version of this file under the MPL, indicate your decision by
* deleting the provisions above and replace them with the notice and
* other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file
* under either the MPL or the GPL.
*/
#ifndef _LINUX_TI113X_H
#define _LINUX_TI113X_H
#ifndef PCI_VENDOR_ID_TI
#define PCI_VENDOR_ID_TI 0x104c
#endif
#ifndef PCI_DEVICE_ID_TI_1130
#define PCI_DEVICE_ID_TI_1130 0xac12
#endif
#ifndef PCI_DEVICE_ID_TI_1031
#define PCI_DEVICE_ID_TI_1031 0xac13
#endif
#ifndef PCI_DEVICE_ID_TI_1131
#define PCI_DEVICE_ID_TI_1131 0xac15
#endif
#ifndef PCI_DEVICE_ID_TI_1210
#define PCI_DEVICE_ID_TI_1210 0xac1a
#endif
#ifndef PCI_DEVICE_ID_TI_1211
#define PCI_DEVICE_ID_TI_1211 0xac1e
#endif
#ifndef PCI_DEVICE_ID_TI_1220
#define PCI_DEVICE_ID_TI_1220 0xac17
#endif
#ifndef PCI_DEVICE_ID_TI_1221
#define PCI_DEVICE_ID_TI_1221 0xac19
#endif
#ifndef PCI_DEVICE_ID_TI_1250A
#define PCI_DEVICE_ID_TI_1250A 0xac16
#endif
#ifndef PCI_DEVICE_ID_TI_1225
#define PCI_DEVICE_ID_TI_1225 0xac1c
#endif
#ifndef PCI_DEVICE_ID_TI_1251A
#define PCI_DEVICE_ID_TI_1251A 0xac1d
#endif
#ifndef PCI_DEVICE_ID_TI_1251B
#define PCI_DEVICE_ID_TI_1251B 0xac1f
#endif
#ifndef PCI_DEVICE_ID_TI_1410
#define PCI_DEVICE_ID_TI_1410 0xac50
#endif
#ifndef PCI_DEVICE_ID_TI_1420
#define PCI_DEVICE_ID_TI_1420 0xac51
#endif
#ifndef PCI_DEVICE_ID_TI_1450
#define PCI_DEVICE_ID_TI_1450 0xac1b
#endif
#ifndef PCI_DEVICE_ID_TI_1451
#define PCI_DEVICE_ID_TI_1451 0xac52
#endif
#ifndef PCI_DEVICE_ID_TI_1510
#define PCI_DEVICE_ID_TI_1510 0xac56
#endif
#ifndef PCI_DEVICE_ID_TI_4410
#define PCI_DEVICE_ID_TI_4410 0xac41
#endif
#ifndef PCI_DEVICE_ID_TI_4450
#define PCI_DEVICE_ID_TI_4450 0xac40
#endif
#ifndef PCI_DEVICE_ID_TI_4451
#define PCI_DEVICE_ID_TI_4451 0xac42
#endif
/* Register definitions for TI 113X PCI-to-CardBus bridges */
/* System Control Register */
#define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */
#define TI113X_SCR_SMIROUTE 0x04000000
#define TI113X_SCR_SMISTATUS 0x02000000
#define TI113X_SCR_SMIENB 0x01000000
#define TI113X_SCR_VCCPROT 0x00200000
#define TI113X_SCR_REDUCEZV 0x00100000
#define TI113X_SCR_CDREQEN 0x00080000
#define TI113X_SCR_CDMACHAN 0x00070000
#define TI113X_SCR_SOCACTIVE 0x00002000
#define TI113X_SCR_PWRSTREAM 0x00000800
#define TI113X_SCR_DELAYUP 0x00000400
#define TI113X_SCR_DELAYDOWN 0x00000200
#define TI113X_SCR_INTERROGATE 0x00000100
#define TI113X_SCR_CLKRUN_SEL 0x00000080
#define TI113X_SCR_PWRSAVINGS 0x00000040
#define TI113X_SCR_SUBSYSRW 0x00000020
#define TI113X_SCR_CB_DPAR 0x00000010
#define TI113X_SCR_CDMA_EN 0x00000008
#define TI113X_SCR_ASYNC_IRQ 0x00000004
#define TI113X_SCR_KEEPCLK 0x00000002
#define TI113X_SCR_CLKRUN_ENA 0x00000001
#define TI122X_SCR_SER_STEP 0xc0000000
#define TI122X_SCR_INTRTIE 0x20000000
#define TI122X_SCR_P2CCLK 0x08000000
#define TI122X_SCR_CBRSVD 0x00400000
#define TI122X_SCR_MRBURSTDN 0x00008000
#define TI122X_SCR_MRBURSTUP 0x00004000
#define TI122X_SCR_RIMUX 0x00000001
/* Multimedia Control Register */
#define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */
#define TI1250_MMC_ZVOUTEN 0x80
#define TI1250_MMC_PORTSEL 0x40
#define TI1250_MMC_ZVEN1 0x02
#define TI1250_MMC_ZVEN0 0x01
#define TI1250_GENERAL_STATUS 0x85 /* 8 bit */
#define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */
#define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */
#define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */
#define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */
#define TI12XX_IRQMUX 0x8c /* 32 bit */
/* Retry Status Register */
#define TI113X_RETRY_STATUS 0x90 /* 8 bit */
#define TI113X_RSR_PCIRETRY 0x80
#define TI113X_RSR_CBRETRY 0x40
#define TI113X_RSR_TEXP_CBB 0x20
#define TI113X_RSR_MEXP_CBB 0x10
#define TI113X_RSR_TEXP_CBA 0x08
#define TI113X_RSR_MEXP_CBA 0x04
#define TI113X_RSR_TEXP_PCI 0x02
#define TI113X_RSR_MEXP_PCI 0x01
/* Card Control Register */
#define TI113X_CARD_CONTROL 0x91 /* 8 bit */
#define TI113X_CCR_RIENB 0x80
#define TI113X_CCR_ZVENABLE 0x40
#define TI113X_CCR_PCI_IRQ_ENA 0x20
#define TI113X_CCR_PCI_IREQ 0x10
#define TI113X_CCR_PCI_CSC 0x08
#define TI113X_CCR_SPKROUTEN 0x02
#define TI113X_CCR_IFG 0x01
#define TI1220_CCR_PORT_SEL 0x20
#define TI122X_CCR_AUD2MUX 0x04
/* Device Control Register */
#define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */
#define TI113X_DCR_5V_FORCE 0x40
#define TI113X_DCR_3V_FORCE 0x20
#define TI113X_DCR_IMODE_MASK 0x06
#define TI113X_DCR_IMODE_ISA 0x02
#define TI113X_DCR_IMODE_SERIAL 0x04
#define TI12XX_DCR_IMODE_PCI_ONLY 0x00
#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
/* Buffer Control Register */
#define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */
#define TI113X_BCR_CB_READ_DEPTH 0x08
#define TI113X_BCR_CB_WRITE_DEPTH 0x04
#define TI113X_BCR_PCI_READ_DEPTH 0x02
#define TI113X_BCR_PCI_WRITE_DEPTH 0x01
/* Diagnostic Register */
#define TI1250_DIAGNOSTIC 0x93 /* 8 bit */
#define TI1250_DIAG_TRUE_VALUE 0x80
#define TI1250_DIAG_PCI_IREQ 0x40
#define TI1250_DIAG_PCI_CSC 0x20
#define TI1250_DIAG_ASYNC_CSC 0x01
/* DMA Registers */
#define TI113X_DMA_0 0x94 /* 32 bit */
#define TI113X_DMA_1 0x98 /* 32 bit */
/* ExCA IO offset registers */
#define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
/* Data structure for tracking vendor-specific state */
typedef struct ti113x_state_t {
u32 sysctl; /* TI113X_SYSTEM_CONTROL */
u8 cardctl; /* TI113X_CARD_CONTROL */
u8 devctl; /* TI113X_DEVICE_CONTROL */
u8 diag; /* TI1250_DIAGNOSTIC */
u32 irqmux; /* TI12XX_IRQMUX */
} ti113x_state_t;
#define TI_PCIC_ID \
IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \
IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \
IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \
IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451
#define TI_PCIC_INFO \
{ "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
{ "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
{ "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
{ "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
{ "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
{ "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
{ "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
{ "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
{ "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
{ "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
{ "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
{ "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
{ "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
{ "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
{ "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
{ "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
{ "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
{ "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
{ "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) }
#endif /* _LINUX_TI113X_H */
|
1001-study-uboot
|
include/pcmcia/ti113x.h
|
C
|
gpl3
| 8,059
|
/*
* cirrus.h 1.4 1999/10/25 20:03:34
*
* The contents of this file are subject to the Mozilla Public License
* Version 1.1 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License
* at http://www.mozilla.org/MPL/
*
* Software distributed under the License is distributed on an "AS IS"
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
* the License for the specific language governing rights and
* limitations under the License.
*
* The initial developer of the original code is David A. Hinds
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
*
* Alternatively, the contents of this file may be used under the
* terms of the GNU General Public License version 2 (the "GPL"), in which
* case the provisions of the GPL are applicable instead of the
* above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use
* your version of this file under the MPL, indicate your decision by
* deleting the provisions above and replace them with the notice and
* other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file
* under either the MPL or the GPL.
*/
#ifndef _LINUX_CIRRUS_H
#define _LINUX_CIRRUS_H
#ifndef PCI_VENDOR_ID_CIRRUS
#define PCI_VENDOR_ID_CIRRUS 0x1013
#endif
#ifndef PCI_DEVICE_ID_CIRRUS_6729
#define PCI_DEVICE_ID_CIRRUS_6729 0x1100
#endif
#ifndef PCI_DEVICE_ID_CIRRUS_6832
#define PCI_DEVICE_ID_CIRRUS_6832 0x1110
#endif
#define PD67_MISC_CTL_1 0x16 /* Misc control 1 */
#define PD67_FIFO_CTL 0x17 /* FIFO control */
#define PD67_MISC_CTL_2 0x1E /* Misc control 2 */
#define PD67_CHIP_INFO 0x1f /* Chip information */
#define PD67_ATA_CTL 0x026 /* 6730: ATA control */
#define PD67_EXT_INDEX 0x2e /* Extension index */
#define PD67_EXT_DATA 0x2f /* Extension data */
/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
#define PD67_DATA_MASK0 0x01 /* Data mask 0 */
#define PD67_DATA_MASK1 0x02 /* Data mask 1 */
#define PD67_DMA_CTL 0x03 /* DMA control */
/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
#define PD67_EXT_CTL_1 0x03 /* Extension control 1 */
#define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */
#define PD67_EXTERN_DATA 0x0a
#define PD67_MISC_CTL_3 0x25
#define PD67_SMB_PWR_CTL 0x26
/* I/O window address offset */
#define PD67_IO_OFF(w) (0x36+((w)<<1))
/* Timing register sets */
#define PD67_TIME_SETUP(n) (0x3a + 3*(n))
#define PD67_TIME_CMD(n) (0x3b + 3*(n))
#define PD67_TIME_RECOV(n) (0x3c + 3*(n))
/* Flags for PD67_MISC_CTL_1 */
#define PD67_MC1_5V_DET 0x01 /* 5v detect */
#define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */
#define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */
#define PD67_MC1_PULSE_MGMT 0x04
#define PD67_MC1_PULSE_IRQ 0x08
#define PD67_MC1_SPKR_ENA 0x10
#define PD67_MC1_INPACK_ENA 0x80
/* Flags for PD67_FIFO_CTL */
#define PD67_FIFO_EMPTY 0x80
/* Flags for PD67_MISC_CTL_2 */
#define PD67_MC2_FREQ_BYPASS 0x01
#define PD67_MC2_DYNAMIC_MODE 0x02
#define PD67_MC2_SUSPEND 0x04
#define PD67_MC2_5V_CORE 0x08
#define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */
#define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */
#define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */
#define PD67_MC2_DMA_MODE 0x40
#define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */
/* Flags for PD67_CHIP_INFO */
#define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */
#define PD67_INFO_CHIP_ID 0xc0
#define PD67_INFO_REV 0x1c
/* Fields in PD67_TIME_* registers */
#define PD67_TIME_SCALE 0xc0
#define PD67_TIME_SCALE_1 0x00
#define PD67_TIME_SCALE_16 0x40
#define PD67_TIME_SCALE_256 0x80
#define PD67_TIME_SCALE_4096 0xc0
#define PD67_TIME_MULT 0x3f
/* Fields in PD67_DMA_CTL */
#define PD67_DMA_MODE 0xc0
#define PD67_DMA_OFF 0x00
#define PD67_DMA_DREQ_INPACK 0x40
#define PD67_DMA_DREQ_WP 0x80
#define PD67_DMA_DREQ_BVD2 0xc0
#define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */
/* Fields in PD67_EXT_CTL_1 */
#define PD67_EC1_VCC_PWR_LOCK 0x01
#define PD67_EC1_AUTO_PWR_CLEAR 0x02
#define PD67_EC1_LED_ENA 0x04
#define PD67_EC1_INV_CARD_IRQ 0x08
#define PD67_EC1_INV_MGMT_IRQ 0x10
#define PD67_EC1_PULLUP_CTL 0x20
/* Fields in PD67_MISC_CTL_3 */
#define PD67_MC3_IRQ_MASK 0x03
#define PD67_MC3_IRQ_PCPCI 0x00
#define PD67_MC3_IRQ_EXTERN 0x01
#define PD67_MC3_IRQ_PCIWAY 0x02
#define PD67_MC3_IRQ_PCI 0x03
#define PD67_MC3_PWR_MASK 0x0c
#define PD67_MC3_PWR_SERIAL 0x00
#define PD67_MC3_PWR_TI2202 0x08
#define PD67_MC3_PWR_SMB 0x0c
/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
#define PD68_EXT_CTL_2 0x0b
#define PD68_PCI_SPACE 0x22
#define PD68_PCCARD_SPACE 0x23
#define PD68_WINDOW_TYPE 0x24
#define PD68_EXT_CSC 0x2e
#define PD68_MISC_CTL_4 0x2f
#define PD68_MISC_CTL_5 0x30
#define PD68_MISC_CTL_6 0x31
/* Extra flags in PD67_MISC_CTL_3 */
#define PD68_MC3_HW_SUSP 0x10
#define PD68_MC3_MM_EXPAND 0x40
#define PD68_MC3_MM_ARM 0x80
/* Bridge Control Register */
#define PD6832_BCR_MGMT_IRQ_ENA 0x0800
/* Socket Number Register */
#define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */
typedef struct cirrus_state_t {
u_char misc1, misc2;
u_char timer[6];
} cirrus_state_t;
/* Cirrus options */
static int has_dma = -1;
static int has_led = -1;
static int has_ring = -1;
static int dynamic_mode = 0;
static int freq_bypass = -1;
#ifdef CONFIG_CPC45
static int setup_time = 2;
static int cmd_time = 6;
static int recov_time = 1;
#else
static int setup_time = -1;
static int cmd_time = -1;
static int recov_time = -1;
#endif
#endif /* _LINUX_CIRRUS_H */
|
1001-study-uboot
|
include/pcmcia/cirrus.h
|
C
|
gpl3
| 5,842
|
/*
* Copyright (C) 2009
* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _S6E63D6_H_
#define _S6E63D6_H_
struct s6e63d6 {
unsigned int bus;
unsigned int cs;
unsigned int id;
struct spi_slave *slave;
};
extern int s6e63d6_init(struct s6e63d6 *data);
extern int s6e63d6_index(struct s6e63d6 *data, u8 idx);
extern int s6e63d6_param(struct s6e63d6 *data, u16 param);
#endif
|
1001-study-uboot
|
include/s6e63d6.h
|
C
|
gpl3
| 1,203
|
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*************************************************************************
* Altera Nios-II EPCS Controller Core interfaces
************************************************************************/
#ifndef __NIOS2_EPCS_H__
#define __NIOS2_EPCS_H__
typedef struct epcs_devinfo_t {
const char *name; /* Device name */
unsigned char id; /* Device silicon id */
unsigned char size; /* Total size log2(bytes)*/
unsigned char num_sects; /* Number of sectors */
unsigned char sz_sect; /* Sector size log2(bytes) */
unsigned char sz_page; /* Page size log2(bytes) */
unsigned char prot_mask; /* Protection mask */
}epcs_devinfo_t;
/* Resets the epcs controller -- to prevent (potential) soft-reset
* problems when booting from the epcs controller
*/
extern int epcs_reset (void);
/* Returns the devinfo struct if EPCS device is found;
* NULL otherwise.
*/
extern epcs_devinfo_t *epcs_dev_find (void);
/* Returns the number of bytes used by config data.
* Negative on error.
*/
extern int epcs_cfgsz (void);
/* Erase sectors 'start' to 'end' - return zero on success
*/
extern int epcs_erase (unsigned start, unsigned end);
/* Read 'cnt' bytes from device offset 'off' into buf at 'addr'
* Zero return on success
*/
extern int epcs_read (ulong addr, ulong off, ulong cnt);
/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'.
* Zero return on success
*/
extern int epcs_write (ulong addr, ulong off, ulong cnt);
/* Verify 'cnt' bytes at device offset 'off' comparing with buf
* at 'addr'. On failure, write first invalid offset to *err.
* Zero return on success
*/
extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err);
#endif /* __NIOS2_EPCS_H__ */
|
1001-study-uboot
|
include/nios2-epcs.h
|
C
|
gpl3
| 2,605
|
/*
* You do not need to use #ifdef around functions that may not exist
* in the final configuration (such as i2c).
*/
EXPORT_FUNC(get_version)
EXPORT_FUNC(getc)
EXPORT_FUNC(tstc)
EXPORT_FUNC(putc)
EXPORT_FUNC(puts)
EXPORT_FUNC(printf)
EXPORT_FUNC(install_hdlr)
EXPORT_FUNC(free_hdlr)
EXPORT_FUNC(malloc)
EXPORT_FUNC(free)
EXPORT_FUNC(udelay)
EXPORT_FUNC(get_timer)
EXPORT_FUNC(vprintf)
EXPORT_FUNC(do_reset)
EXPORT_FUNC(getenv)
EXPORT_FUNC(setenv)
EXPORT_FUNC(simple_strtoul)
EXPORT_FUNC(strict_strtoul)
EXPORT_FUNC(simple_strtol)
EXPORT_FUNC(strcmp)
EXPORT_FUNC(i2c_write)
EXPORT_FUNC(i2c_read)
EXPORT_FUNC(spi_init)
EXPORT_FUNC(spi_setup_slave)
EXPORT_FUNC(spi_free_slave)
EXPORT_FUNC(spi_claim_bus)
EXPORT_FUNC(spi_release_bus)
EXPORT_FUNC(spi_xfer)
|
1001-study-uboot
|
include/_exports.h
|
C
|
gpl3
| 756
|
/*
* Header file for OneNAND support for U-Boot
*
* Adaptation from kernel to U-Boot
*
* Copyright (C) 2005-2007 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __UBOOT_ONENAND_H
#define __UBOOT_ONENAND_H
#include <linux/types.h>
/* Forward declarations */
struct mtd_info;
struct mtd_oob_ops;
struct erase_info;
struct onenand_chip;
extern struct mtd_info onenand_mtd;
extern struct onenand_chip onenand_chip;
/* board */
extern void onenand_board_init(struct mtd_info *);
/* Functions */
extern void onenand_init(void);
extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t * retlen, u_char * buf);
extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops);
extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len,
size_t * retlen, const u_char * buf);
extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr);
extern char *onenand_print_device_info(int device, int version);
extern unsigned onenand_block(struct onenand_chip *this, loff_t addr);
extern loff_t onenand_addr(struct onenand_chip *this, int block);
extern int flexonenand_region(struct mtd_info *mtd, loff_t addr);
extern int flexonenand_set_boundary(struct mtd_info *mtd, int die,
int boundary, int lock);
/* S3C64xx */
extern void s3c64xx_onenand_init(struct mtd_info *);
extern void s3c64xx_set_width_regs(struct onenand_chip *);
/* SPL */
void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst);
#endif /* __UBOOT_ONENAND_H */
|
1001-study-uboot
|
include/onenand_uboot.h
|
C
|
gpl3
| 1,749
|
/*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* lh7a404 SoC interface
*/
#ifndef __LH7A404_H__
#define __LH7A404_H__
#include "lh7a40x.h"
/* Interrupt Controller (userguide 8.2.1) */
typedef struct {
volatile u32 irqstatus;
volatile u32 fiqstatus;
volatile u32 rawintr;
volatile u32 intsel;
volatile u32 inten;
volatile u32 intenclr;
volatile u32 softint;
volatile u32 softintclr;
volatile u32 protect;
volatile u32 unused1;
volatile u32 unused2;
volatile u32 vectaddr;
volatile u32 nvaddr;
volatile u32 unused3[32];
volatile u32 vad[16];
volatile u32 unused4[44];
volatile u32 vectcntl[16];
volatile u32 unused5[44];
volatile u32 itcr;
volatile u32 itip1;
volatile u32 itip2;
volatile u32 itop1;
volatile u32 itop2;
volatile u32 unused6[333];
volatile u32 periphid[4];
volatile u32 pcellid[4];
} /*__attribute__((__packed__))*/ lh7a404_vic_t;
#define LH7A404_VIC_BASE (0x80008000)
#define LH7A400_VIC_PTR(x) ((lh7a404_vic_t*)(LH7A400_VIC_BASE + (x*0x2000)))
typedef struct {
lh7a40x_dmachan_t m2p0_tx;
lh7a40x_dmachan_t m2p1_rx;
lh7a40x_dmachan_t m2p2_tx;
lh7a40x_dmachan_t m2p3_rx;
lh7a40x_dmachan_t m2m0;
lh7a40x_dmachan_t m2m1;
lh7a40x_dmachan_t unused1;
lh7a40x_dmachan_t unused2;
lh7a40x_dmachan_t m2p5_rx;
lh7a40x_dmachan_t m2p4_tx;
lh7a40x_dmachan_t m2p7_rx;
lh7a40x_dmachan_t m2p6_tx;
lh7a40x_dmachan_t m2p9_rx;
lh7a40x_dmachan_t m2p8_tx;
volatile u32 chanarb;
volatile u32 glblint;
} /*__attribute__((__packed__))*/ lh7a400_dma_t;
#endif /* __LH7A404_H__ */
|
1001-study-uboot
|
include/lh7a404.h
|
C
|
gpl3
| 2,330
|
/*
* include/linux/pc_keyb.h
*
* PC Keyboard And Keyboard Controller
*
* (c) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
*/
/*
* Configuration Switches
*/
#undef KBD_REPORT_ERR /* Report keyboard errors */
#define KBD_REPORT_UNKN /* Report unknown scan codes */
#define KBD_REPORT_TIMEOUTS /* Report keyboard timeouts */
#undef KBD_IS_FOCUS_9000 /* We have the brain-damaged FOCUS-9000 keyboard */
#undef INITIALIZE_MOUSE /* Define if your PS/2 mouse needs initialization. */
#define KBD_INIT_TIMEOUT 1000 /* Timeout in ms for initializing the keyboard */
#define KBC_TIMEOUT 250 /* Timeout in ms for sending to keyboard controller */
#define KBD_TIMEOUT 1000 /* Timeout in ms for keyboard command acknowledge */
/*
* Internal variables of the driver
*/
extern unsigned char pckbd_read_mask;
extern unsigned char aux_device_present;
/*
* Keyboard Controller Registers on normal PCs.
*/
#define KBD_STATUS_REG 0x64 /* Status register (R) */
#define KBD_CNTL_REG 0x64 /* Controller command register (W) */
#define KBD_DATA_REG 0x60 /* Keyboard data register (R/W) */
/*
* Keyboard Controller Commands
*/
#define KBD_CCMD_READ_MODE 0x20 /* Read mode bits */
#define KBD_CCMD_WRITE_MODE 0x60 /* Write mode bits */
#define KBD_CCMD_GET_VERSION 0xA1 /* Get controller version */
#define KBD_CCMD_MOUSE_DISABLE 0xA7 /* Disable mouse interface */
#define KBD_CCMD_MOUSE_ENABLE 0xA8 /* Enable mouse interface */
#define KBD_CCMD_TEST_MOUSE 0xA9 /* Mouse interface test */
#define KBD_CCMD_SELF_TEST 0xAA /* Controller self test */
#define KBD_CCMD_KBD_TEST 0xAB /* Keyboard interface test */
#define KBD_CCMD_KBD_DISABLE 0xAD /* Keyboard interface disable */
#define KBD_CCMD_KBD_ENABLE 0xAE /* Keyboard interface enable */
#define KBD_CCMD_WRITE_AUX_OBUF 0xD3 /* Write to output buffer as if
initiated by the auxiliary device */
#define KBD_CCMD_WRITE_MOUSE 0xD4 /* Write the following byte to the mouse */
/*
* Keyboard Commands
*/
#define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
#define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
#define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
#define KBD_CMD_DISABLE 0xF5 /* Disable scanning */
#define KBD_CMD_RESET 0xFF /* Reset */
/*
* Keyboard Replies
*/
#define KBD_REPLY_POR 0xAA /* Power on reset */
#define KBD_REPLY_ACK 0xFA /* Command ACK */
#define KBD_REPLY_RESEND 0xFE /* Command NACK, send the cmd again */
/*
* Status Register Bits
*/
#define KBD_STAT_OBF 0x01 /* Keyboard output buffer full */
#define KBD_STAT_IBF 0x02 /* Keyboard input buffer full */
#define KBD_STAT_SELFTEST 0x04 /* Self test successful */
#define KBD_STAT_CMD 0x08 /* Last write was a command write (0=data) */
#define KBD_STAT_UNLOCKED 0x10 /* Zero if keyboard locked */
#define KBD_STAT_MOUSE_OBF 0x20 /* Mouse output buffer full */
#define KBD_STAT_GTO 0x40 /* General receive/xmit timeout */
#define KBD_STAT_PERR 0x80 /* Parity error */
#define AUX_STAT_OBF (KBD_STAT_OBF | KBD_STAT_MOUSE_OBF)
/*
* Controller Mode Register Bits
*/
#define KBD_MODE_KBD_INT 0x01 /* Keyboard data generate IRQ1 */
#define KBD_MODE_MOUSE_INT 0x02 /* Mouse data generate IRQ12 */
#define KBD_MODE_SYS 0x04 /* The system flag (?) */
#define KBD_MODE_NO_KEYLOCK 0x08 /* The keylock doesn't affect the keyboard if set */
#define KBD_MODE_DISABLE_KBD 0x10 /* Disable keyboard interface */
#define KBD_MODE_DISABLE_MOUSE 0x20 /* Disable mouse interface */
#define KBD_MODE_KCC 0x40 /* Scan code conversion to PC format */
#define KBD_MODE_RFU 0x80
/*
* Mouse Commands
*/
#define AUX_SET_RES 0xE8 /* Set resolution */
#define AUX_SET_SCALE11 0xE6 /* Set 1:1 scaling */
#define AUX_SET_SCALE21 0xE7 /* Set 2:1 scaling */
#define AUX_GET_SCALE 0xE9 /* Get scaling factor */
#define AUX_SET_STREAM 0xEA /* Set stream mode */
#define AUX_SET_SAMPLE 0xF3 /* Set sample rate */
#define AUX_ENABLE_DEV 0xF4 /* Enable aux device */
#define AUX_DISABLE_DEV 0xF5 /* Disable aux device */
#define AUX_RESET 0xFF /* Reset aux device */
#define AUX_ACK 0xFA /* Command byte ACK. */
#define AUX_BUF_SIZE 2048 /* This might be better divisible by
three to make overruns stay in sync
but then the read function would need
a lock etc - ick */
#if 0
struct aux_queue {
unsigned long head;
unsigned long tail;
wait_queue_head_t proc_list;
struct fasync_struct *fasync;
unsigned char buf[AUX_BUF_SIZE];
};
#endif
|
1001-study-uboot
|
include/pc_keyb.h
|
C
|
gpl3
| 4,422
|
/*
* Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* Based on original Kirkwood support which is
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_EDMINIV2_H
#define _CONFIG_EDMINIV2_H
/*
* Version number information
*/
#define CONFIG_IDENT_STRING " EDMiniV2"
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_MARVELL 1
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#define CONFIG_FEROCEON 1 /* CPU Core subversion */
#define CONFIG_ORION5X 1 /* SOC Family Name */
#define CONFIG_88F5182 1 /* SOC Name */
#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
#include <asm/arch/orion5x.h>
/*
* CLKs configurations
*/
#define CONFIG_SYS_HZ 1000
/*
* Board-specific values for Orion5x MPP low level init:
* - MPPs 12 to 15 are SATA LEDs (mode 5)
* - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
* MPP16 to MPP19, mode 0 for others
*/
#define ORION5X_MPP0_7 0x00000003
#define ORION5X_MPP8_15 0x55550000
#define ORION5X_MPP16_23 0x00005555
/*
* Board-specific values for Orion5x GPIO low level init:
* - GPIO3 is input (RTC interrupt)
* - GPIO16 is Power LED control (0 = on, 1 = off)
* - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
* - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
* - Last GPIO is 26, further bits are supposed to be 0.
* Enable mask has ones for INPUT, 0 for OUTPUT.
* Default is LED ON.
*/
#define ORION5X_GPIO_OUT_ENABLE 0x03fcffff
#define ORION5X_GPIO_OUT_VALUE 0x03fcffff
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
/*
* Serial Port configuration
* The following definitions let you select what serial you want to use
* for your console driver.
*/
#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
/*
* FLASH configuration
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE 0xfff80000
#define CONFIG_SYS_FLASH_SECTSZ \
{16384, 8192, 8192, 32768, \
65536, 65536, 65536, 65536, 65536, 65536, 65536}
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
/*
* Commands configuration - using default command set for now
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_IDE
#define CONFIG_CMD_I2C
/*
* Network
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE /* Enable Marvell GbE Driver */
#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
#define CONFIG_PHY_BASE_ADR 0x8
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif
/*
* IDE
*/
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_IDE_PREINIT
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
/* ED Mini V has an IDE-compatible SATA connector for port 1 */
#define CONFIG_MVSATA_IDE
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE 4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* A single bus, a single device */
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
/* end of IDE defines */
#endif /* CMD_IDE */
/*
* I2C related stuff
*/
#ifdef CONFIG_CMD_I2C
#define CONFIG_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
#endif
/*
* Environment variables configurations
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
/*
* Other required minimal configurations
*/
#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_STACKSIZE 0x00100000
#define CONFIG_SYS_LOAD_ADDR 0x00800000
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x007fffff
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
#define CONFIG_SYS_MAXARGS 16
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* _CONFIG_EDMINIV2_H */
|
1001-study-uboot
|
include/configs/edminiv2.h
|
C
|
gpl3
| 7,131
|
/*
* Configuation settings for the esd TASREG board.
*
* (C) Copyright 2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5249EVB_H
#define _M5249EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5249 /* define processor type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
/*
* BOOTP options
*/
#undef CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_BOOTP_BOOTPATH
#undef CONFIG_BOOTP_GATEWAY
#undef CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_NET
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_HZ 1000
/*
* Clock configuration: enable only one of the following options
*/
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CONFIG_SYS_MBAR2 0x80000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
#endif
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN 0x20000
#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CONFIG_SYS_FLASH_CHECKSUM
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/* CS0 - AMD Flash, address 0xffc00000 */
#define CONFIG_SYS_CS0_BASE 0xffe00000
#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
#define CONFIG_SYS_CS1_BASE 0xe0000000
#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* M5249 */
|
1001-study-uboot
|
include/configs/M5249EVB.h
|
C
|
gpl3
| 7,618
|
/*
* U-boot - Configuration file for Bluetechnix TCM-BF518 board
*/
#ifndef __CONFIG_TCM_BF518_H__
#define __CONFIG_TCM_BF518_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf518-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 16
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/*
* Memory Settings
*/
/* This board has a 32meg MT48H16M16 */
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
#define CONFIG_EBIU_SDRRC_VAL 0x3f8
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
/*
* Network Settings
*/
#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE 1
#endif
#define CONFIG_HOSTNAME tcm-bf518
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 19
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x8000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/tcm-bf518.h
|
C
|
gpl3
| 3,139
|
/*
* (C) Copyright 2000
* Murray Jensen, CSIRO-MST
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _CONFIG_COGENT_COMMON_H
#define _CONFIG_COGENT_COMMON_H
/*
* Cogent Motherboard Capabilities
*/
#define CMA_MB_CAP_SERPAR 0x0001 /* has dual serial+parallel (16C552) */
#define CMA_MB_CAP_LCD 0x0002 /* has LCD display (HD44780) */
#define CMA_MB_CAP_FLASH 0x0004 /* has flash (E28F800B or AM29F800BB) */
#define CMA_MB_CAP_RTC 0x0008 /* has RTC+NVRAM (MK48T02) */
#define CMA_MB_CAP_ETHER 0x0010 /* has Ethernet (MB86964) */
#define CMA_MB_CAP_SLOT1 0x0020 /* has CMABus slot 1 */
#define CMA_MB_CAP_SLOT2 0x0040 /* has CMABus slot 2 */
#define CMA_MB_CAP_SLOT3 0x0080 /* has CMABus slot 3 */
#define CMA_MB_CAP_KBM 0x0100 /* has PS/2 keyboard+mouse (HT6542B) */
#define CMA_MB_CAP_SER2 0x0200 /* has 2nd dual serial (16C2552) */
#define CMA_MB_CAP_PCI 0x0400 /* has pci bridge (V360EPC) */
#define CMA_MB_CAP_PCI_EXT 0x0800 /* can access extended pci space */
#define CMA_MB_CAP_PCI_ETHER 0x1000 /* has 10/100 ether on PCI (GD82559) */
#define CMA_MB_CAP_PCI_VIDEO 0x2000 /* has video int'face on PCI (B69000) */
#define CMA_MB_CAP_PCI_CARDBUS 0x4000 /* has Cardbus Ctlr on PCI (PD6832) */
/*
* Cogent option sanity checking
*/
#if defined(CONFIG_MPC821) || defined(CONFIG_MPC823) || \
defined(CONFIG_MPC850) || defined(CONFIG_MPC860)
/*
* check a PowerPC 8xx cpu module has been selected
*/
# if defined(CONFIG_CMA286_21)
# define COGENT_CPU_MODULE "CMA286-21"
# elif defined(CONFIG_CMA286_60_OLD)
# define COGENT_CPU_MODULE "CMA286-60 (old)"
# elif defined(CONFIG_CMA286_60)
# define COGENT_CPU_MODULE "CMA286-60"
# elif defined(CONFIG_CMA286_60P)
# define COGENT_CPU_MODULE "CMA286-60P"
# elif defined(CONFIG_CMA287_21)
# define COGENT_CPU_MODULE "CMA287-21"
# elif defined(CONFIG_CMA287_50)
# define COGENT_CPU_MODULE "CMA287-50"
# else
# error Cogent CPU Module must be a PowerPC MPC8xx module
# endif
#elif defined(CONFIG_MPC8260)
/*
* check a PowerPC 8260 cpu module has been selected
*/
# if defined(CONFIG_CMA282)
# define COGENT_CPU_MODULE "CMA282"
# else
# error Cogent CPU Module must be a PowerPC MPC8260 module
# endif
#else
# error CPU type must be PowerPC 8xx or 8260
#endif
/*
* check a motherboard has been selected
* define the motherboard capabilities while we're at it
*/
#if defined(CONFIG_CMA101)
# define COGENT_MOTHERBOARD "CMA101"
# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
CMA_MB_CAP_RTC | CMA_MB_CAP_ETHER | \
CMA_MB_CAP_SLOT1 | CMA_MB_CAP_SLOT2 | \
CMA_MB_CAP_SLOT3)
# define CMA_MB_NSLOTS 3
#elif defined(CONFIG_CMA102)
# define COGENT_MOTHERBOARD "CMA102"
# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
CMA_MB_CAP_RTC | CMA_MB_CAP_SLOT1 | \
CMA_MB_CAP_SLOT2 | CMA_MB_CAP_SLOT3)
# define CMA_MB_NSLOTS 3
#elif defined(CONFIG_CMA110)
# define COGENT_MOTHERBOARD "CMA110"
# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
CMA_MB_CAP_KBM | CMA_MB_CAP_PCI)
# define CMA_MB_NSLOTS 0
#elif defined(CONFIG_CMA111)
# define COGENT_MOTHERBOARD "CMA111"
# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
CMA_MB_CAP_PCI | CMA_MB_CAP_PCI_EXT | \
CMA_MB_CAP_PCI_ETHER)
# define CMA_MB_NSLOTS 1
#elif defined(CONFIG_CMA120)
# define COGENT_MOTHERBOARD "CMA120"
# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
CMA_MB_CAP_SLOT1 | CMA_MB_CAP_KBM | \
CMA_MB_CAP_SER2 | CMA_MB_CAP_PCI | \
CMA_MB_CAP_PCI_EXT | CMA_MB_CAP_PCI_ETHER | \
CMA_MB_CAP_PCI_VIDEO | CMA_MB_CAP_PCI_CARDBUS)
# define CMA_MB_NSLOTS 1
#elif defined(CONFIG_CMA150)
# define COGENT_MOTHERBOARD "CMA150"
# define CMA_MB_CAPS (CMA_MB_CAP_SERPAR | CMA_MB_CAP_LCD | \
CMA_MB_CAP_FLASH | CMA_MB_CAP_RTC | \
CMA_MB_CAP_KBM)
# define CMA_MB_NSLOTS 0
#else
# error Cogent Motherboard either unsupported or undefined
#endif
/*
* check a flash i/o module has been selected if no flash on m/b
*/
#if defined(CONFIG_CMA302)
# define COGENT_FLASH_MODULE "CMA302"
#elif (CMA_MB_CAPS & CMA_MB_CAP_FLASH) == 0
# error Cogent Flash I/O module (e.g. CMA302) is required with this Motherboard
#endif
/*
* some further sanity checks
*/
#if (CMA_MB_CAPS & CMA_MB_CAP_PCI) && (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
#error Cogent Sanity Check: Both Slot2 and PCI are defined
#endif
#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
#error Extended PCI capability defined without PCI capability
#endif
#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_ETHER) && !(CMA_MB_CAPS & CMA_MB_CAP_PCI)
#error Motherboard ethernet capability defined without PCI capability
#endif
#if (CMA_MB_CAPS & CMA_MB_CAP_SER2) && !(CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
#error 2nd dual serial capability defined without serial/parallel capability
#endif
#include "../board/cogent/mb.h"
#endif /* _CONFIG_COGENT_COMMON_H */
|
1001-study-uboot
|
include/configs/cogent_common.h
|
C
|
gpl3
| 5,832
|
/*
* Configuation settings for the Freescale MCF5329 FireEngine board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5235EVB_H
#define _M5235EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF523x /* define processor family */
#define CONFIG_M5235 /* define processor type */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_BOOTFILE "u-boot.bin"
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M5235EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off ffe00000 ffe3ffff;" \
"era ffe00000 ffe3ffff;" \
"cp.b ${loadaddr} ffe00000 ${filesize};"\
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_KGDB)
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 75000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
#define CONFIG_SYS_MBAR 0x40000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
#ifdef NORFLASH_PS32BIT
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
#else
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#endif
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#ifdef NORFLASH_PS32BIT
# define CONFIG_ENV_OFFSET (0x8000)
# define CONFIG_ENV_SIZE 0x4000
# define CONFIG_ENV_SECT_SIZE 0x4000
#else
# define CONFIG_ENV_OFFSET (0x4000)
# define CONFIG_ENV_SIZE 0x2000
# define CONFIG_ENV_SECT_SIZE 0x2000
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - Available
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
* CS6 - Available
* CS7 - Available
*/
#ifdef NORFLASH_PS32BIT
# define CONFIG_SYS_CS0_BASE 0xFFC00000
# define CONFIG_SYS_CS0_MASK 0x003f0001
# define CONFIG_SYS_CS0_CTRL 0x00001D00
#else
# define CONFIG_SYS_CS0_BASE 0xFFE00000
# define CONFIG_SYS_CS0_MASK 0x001f0001
# define CONFIG_SYS_CS0_CTRL 0x00001D80
#endif
#endif /* _M5329EVB_H */
|
1001-study-uboot
|
include/configs/M5235EVB.h
|
C
|
gpl3
| 8,884
|
/*
* U-boot - Configuration file for BF518F EZBrd board
*/
#ifndef __CONFIG_BF518F_EZBRD_H__
#define __CONFIG_BF518F_EZBRD_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf518-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 16
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
/* This board has a 64meg MT48H32M16 */
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x0096
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
/*
* Network Settings
*/
#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_BFIN_MAC_PINS \
{ \
P_MII0_ETxD0, \
P_MII0_ETxD1, \
P_MII0_ETxD2, \
P_MII0_ETxD3, \
P_MII0_ETxEN, \
P_MII0_TxCLK, \
P_MII0_PHYINT, \
P_MII0_COL, \
P_MII0_ERxD0, \
P_MII0_ERxD1, \
P_MII0_ERxD2, \
P_MII0_ERxD3, \
P_MII0_ERxDV, \
P_MII0_ERxCLK, \
P_MII0_CRS, \
P_MII0_MDC, \
P_MII0_MDIO, \
0 }
#define CONFIG_NETCONSOLE 1
#endif
#define CONFIG_HOSTNAME bf518f-ezbrd
#define CONFIG_PHY_ADDR 3
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_STMICRO
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#endif
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* SDH Settings
*/
#if !defined(__ADSPBF512__)
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_BFIN_SDH
#endif
/*
* Misc Settings
*/
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf518f-ezbrd.h
|
C
|
gpl3
| 3,888
|
/*
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
*
* Based on sheevaplug.h originally written by
* Prafulla Wadaskar <prafulla@marvell.com>
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_DOCKSTAR_H
#define _CONFIG_DOCKSTAR_H
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nSeagate FreeAgent DockStar"
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_DOCKSTAR /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
#undef CONFIG_SYS_PROMPT /* previously defined in mv-common.h */
#define CONFIG_SYS_PROMPT "DockStar> " /* Command Prompt */
/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
#define CONFIG_ENV_ADDR 0x60000
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND \
"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
"ubi part root; " \
"ubifsmount root; " \
"ubifsload 0x800000 ${kernel}; " \
"ubifsload 0x1100000 ${initrd}; " \
"bootm 0x800000 0x1100000"
#define CONFIG_MTDPARTS "mtdparts=orion_nand:1m(uboot),-(root)\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
"mtdparts="CONFIG_MTDPARTS \
"kernel=/boot/uImage\0" \
"initrd=/boot/uInitrd\0" \
"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#endif /* CONFIG_CMD_NET */
/*
* File system
*/
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
#endif /* _CONFIG_DOCKSTAR_H */
|
1001-study-uboot
|
include/configs/dockstar.h
|
C
|
gpl3
| 3,603
|
/*
* U-boot - Configuration file for BlackStamp board
* Configuration by Ben Matthews for UR LLE using bf533-stamp.h
* as a template
* See http://blackfin.uclinux.org/gf/project/blackstamp/
*/
#ifndef __CONFIG_BLACKSTAMP_H__
#define __CONFIG_BLACKSTAMP_H__
#include <asm/config-pre.h>
/*
* Debugging: Set these options if you're having problems
*/
/*
* #define CONFIG_DEBUG_EARLY_SERIAL
* #define DEBUG
* #define CONFIG_DEBUG_DUMP
* #define CONFIG_DEBUG_DUMP_SYMS
*/
#define CONFIG_PANIC_HANG 0
/* CPU Options
* Be sure to set the Silicon Revision Correctly
*/
#define CONFIG_BFIN_CPU bf532-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
* Board settings
*/
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20300300
/* FLASH/ETHERNET uses the same address range
* Depending on what you have the CPLD doing
* this probably isn't needed
*/
#define SHARED_RESOURCES 1
/* Is I2C bit-banged? */
#undef CONFIG_SOFT_I2
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 16
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 3
/*
* Network settings
*/
#ifdef CONFIG_SMC91111
#define CONFIG_IPADDR 192.168.0.15
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_SERVERIP 192.168.0.2
#define CONFIG_HOSTNAME blackstamp
#define CONFIG_ROOTPATH "/checkout/uClinux-dist/romfs"
#define CONFIG_SYS_AUTOLOAD "no"
/* To remove hardcoding and enable MAC storage in EEPROM */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
#endif
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x40000
/*
* SDRAM settings & memory map
*/
#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (384 << 10)
/*
* Command settings
*/
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_ENV_OVERWRITE 1
#include <config_cmd_default.h>
#ifdef CONFIG_SMC91111
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
#else
# undef CONFIG_CMD_NET
#endif
#ifdef CONFIG_SOFT_I2C
# define CONFIG_CMD_I2C
#endif
#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CPLBINFO
#define CONFIG_CMD_DATE
#define CONFIG_CMD_SF
#define CONFIG_CMD_ELF
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTCOMMAND "run ramboot"
#define CONFIG_BOOTARGS \
"root=/dev/mtdblock0 rw " \
"clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
"earlyprintk=" \
"serial," \
"uart" MK_STR(CONFIG_UART_CONSOLE) "," \
MK_STR(CONFIG_BAUDRATE) " " \
"console=ttyBF0," MK_STR(CONFIG_BAUDRATE)
#if defined(CONFIG_CMD_NET)
# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
# define UBOOT_ENV_FILE "u-boot.bin"
# else
# define UBOOT_ENV_FILE "u-boot.ldr"
# endif
# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
# ifdef CONFIG_SPI
# define UBOOT_ENV_UPDATE \
"eeprom write $(loadaddr) 0x0 $(filesize)"
# else
# define UBOOT_ENV_UPDATE \
"sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 0x40000;" \
"sf write $(loadaddr) 0 $(filesize)"
# endif
# else
# define UBOOT_ENV_UPDATE \
"protect off 0x20000000 0x2003FFFF;" \
"erase 0x20000000 0x2003FFFF;" \
"cp.b $(loadaddr) 0x20000000 $(filesize)"
# endif
# define NETWORK_ENV_SETTINGS \
"ubootfile=" UBOOT_ENV_FILE "\0" \
"update=" \
"tftp $(loadaddr) $(ubootfile);" \
UBOOT_ENV_UPDATE \
"\0" \
"addip=set bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
"$(hostname):eth0:off" \
"\0" \
"ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
"ramboot=" \
"tftp $(loadaddr) uImage;" \
"run ramargs;" \
"run addip;" \
"bootm" \
"\0" \
"nfsargs=set bootargs " \
"root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
"\0" \
"nfsboot=" \
"tftp $(loadaddr) vmImage;" \
"run nfsargs;" \
"run addip;" \
"bootm" \
"\0"
#else
# define NETWORK_ENV_SETTINGS
#endif
/*
* Console settings
*/
#define CONFIG_BAUDRATE 57600
#define CONFIG_LOADS_ECHO 1
#define CONFIG_UART_CONSOLE 0
/*
* I2C settings
* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
* Located on the expansion connector on pins 86/85
* Note these pins are arbitrarily chosen because we aren't using
* them yet. You can (and probably should) change these values!
*/
#ifdef CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF9
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF8
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0xFE
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_RTC_BFIN 1
/*
* Serial Flash Infomation
*/
#define CONFIG_BFIN_SPI
/* For the M25P64 SCK Should be Kept < 15Mhz */
#define CONFIG_ENV_SPI_MAX_HZ 15000000
#define CONFIG_SF_DEFAULT_SPEED 15000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* FLASH organization and environment definitions
*/
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
#define CONFIG_EBIU_SDRRC_VAL 0x268
#define CONFIG_EBIU_SDGCTL_VAL 0x911109
/* Even though Rev C boards have Parallel Flash
* We aren't supporting it. Newer versions of the
* hardware don't support Parallel Flash at all.
*/
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_JFFS2
#undef CONFIG_CMD_FLASH
#endif
|
1001-study-uboot
|
include/configs/blackstamp.h
|
C
|
gpl3
| 6,234
|
/*
* (C) Copyright 2003-2004
* MPC Data Limited (http://www.mpc-data.co.uk)
* Dave Peverley <dpeverley at mpc-data.co.uk>
*
* Configuation settings for the TI OMAP Perseus 2 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP730 1 /* which is in a 730 */
#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
/*
* Input clock of PLL
* The OMAP730 Perseus 2 has 13MHz input clock
*/
#define CONFIG_SYS_CLK_FREQ 13000000
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04000300
#define CONFIG_LAN91C96_EXT_PHY
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (1)
#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
* on perseus */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#include <configs/omap730.h>
#include <configs/h2_p2_dbg_board.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
#define CONFIG_LOADADDR 0x10000000
#define CONFIG_ETHADDR
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.0.23
#define CONFIG_SERVERIP 192.150.0.100
#define CONFIG_BOOTFILE "uImage" /* File to load */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
* the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
* local divisor.
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#if defined(CONFIG_CS0_BOOT)
#define PHYS_FLASH_1 0x0C000000
#elif defined(CONFIG_CS3_BOOT)
#define PHYS_FLASH_1 0x00000000
#else
#error Unknown Boot Chip-Select number
#endif
#define PHYS_SRAM 0x20000000
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
/* addr of environment */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
#endif /* ! __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap730p2.h
|
C
|
gpl3
| 6,389
|
/*
* (C) Copyright 2010
* ISEE 2007 SL, <www.iseebcn.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_IGEP0030 1 /* working with IGEP0030 */
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#define CONFIG_OF_LIBFDT 1
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/* select serial console configuration */
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR */
#define CONFIG_OMAP3_NUMONYX_DDR 1
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#define CONFIG_TWL4030_USB 1
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID 0x0451
#define CONFIG_USBD_PRODUCTID 0x5678
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME "IGEP"
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_ONENAND /* ONENAND support */
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* nfs */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* TWL4030
*/
#define CONFIG_TWL4030_POWER 1
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
"console=ttyS2,115200n8\0" \
"mpurate=500\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"nandrootfstype=jffs2\0" \
"mmcargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapfb.debug=y " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"nandargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapfb.debug=y " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from onenand ...; " \
"run nandargs; " \
"onenand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "U-Boot # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
/* works on */
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
/*
* Physical Memory Map
*
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*
* FLASH and environment organization
*/
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/igep0030.h
|
C
|
gpl3
| 7,630
|
/*
* U-boot - Configuration file for BF537 PNAV board
*/
#ifndef __CONFIG_BF537_PNAV_H__
#define __CONFIG_BF537_PNAV_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 24576000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x3b7
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_RMII
#endif
#define CONFIG_HOSTNAME bf537-pnav
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#else
#define ENV_IS_EMBEDDED
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x20004000
#define CONFIG_ENV_OFFSET 0x4000
#endif
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x2000
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* an error during compilation remove an object here to get
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
/*
* NAND Settings
*/
#define CONFIG_NAND_PLAT
#define CONFIG_SYS_NAND_BASE 0x20100000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
SSYNC(); \
} while (0)
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF12
/*
* I2C settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
/* JFFS Partition offset set */
#define CONFIG_SYS_JFFS2_FIRST_BANK 0
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs"
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf537-pnav.h
|
C
|
gpl3
| 4,291
|
/*
* Configuation settings for the Motorola MC5275EVB board.
*
* By Arthur Shipkowski <art@videon-central.com>
* Copyright (C) 2005 Videon Central, Inc.
*
* Based off of M5272C3 board code by Josef Baumgartner
* <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5275EVB_H
#define _M5275EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5275 /* define processor type */
#define CONFIG_M5275EVB /* define board type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
#else
#define CONFIG_ENV_ADDR 0xffe04000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
#endif
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Available command configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#define CONFIG_MII 1
#define CONFIG_MII_INIT 1
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_RX_ETH_BUFFER 8
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_SYS_FEC0_PINMUX 0
#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
#define CONFIG_SYS_FEC1_PINMUX 0
#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
#define MCFFEC_TOUT_LOOP 50000
#define CONFIG_HAS_ETH1
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#ifndef CONFIG_SYS_DISCOVER_PHY
#define FECDUPLEX FULL
#define FECSPEED _100BASET
#else
#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#endif
#endif
#endif
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if (CONFIG_CMD_KGDB)
# define CONFIG_SYS_CBSIZE 1024
#else
# define CONFIG_SYS_CBSIZE 256
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x800000
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTCOMMAND "bootm ffe40000"
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_RETRY_COUNT 5
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${uboot}\0" \
"upd=run load; run prog\0" \
"prog=prot off ffe00000 ffe3ffff;" \
"era ffe00000 ffe3ffff;" \
"cp.b ${loadaddr} ffe00000 ${filesize};"\
"save\0" \
""
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 150000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x40000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE 0x20000
#else
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_MONITOR_LEN 0x20000
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_SIZE 0x200000
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CONFIG_SYS_CS0_BASE 0xffe00000
#define CONFIG_SYS_CS0_CTRL 0x00001980
#define CONFIG_SYS_CS0_MASK 0x001F0001
#define CONFIG_SYS_CS1_BASE 0x30000000
#define CONFIG_SYS_CS1_CTRL 0x00001900
#define CONFIG_SYS_CS1_MASK 0x00070001
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_FECI2C 0x0FA0
#endif /* _M5275EVB_H */
|
1001-study-uboot
|
include/configs/M5275EVB.h
|
C
|
gpl3
| 7,718
|
/*
* Toradex Colibri PXA270 configuration file
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_PXA_COMMON_H__
#define __CONFIG_PXA_COMMON_H__
#define CONFIG_DISPLAY_CPUINFO
/*
* KGDB
*/
#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE 230400
#define CONFIG_KGDB_SER_INDEX 2
#endif
/*
* MMC Card Configuration
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_PXA_MMC_GENERIC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#endif
/*
* OHCI USB
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4c000000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "pxa-ohci"
#define CONFIG_USB_STORAGE
#endif
#endif /* __CONFIG_PXA_COMMON_H__ */
|
1001-study-uboot
|
include/configs/pxa-common.h
|
C
|
gpl3
| 1,622
|
/*
* (C) Copyright 2004
* Greg Ungerer <greg.ungerer@opengear.com>.
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
/*
* select serial console configuration
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_KS8695_SERIAL
#define CONFIG_SERIAL1
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_SAVEENV
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200"
#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/cm4008.h
|
C
|
gpl3
| 4,356
|
/*
* U-boot - Configuration file for BF536 brettl2 board
*/
#ifndef __CONFIG_BCT_BRETTL2_H__
#define __CONFIG_BCT_BRETTL2_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf536-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 16384000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 24
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 3
#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
/*
* SDRAM Settings
*/
#define CONFIG_EBIU_SDRRC_VAL 0x07f6
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC 1
#define CONFIG_NETCONSOLE 1
#define CONFIG_HOSTNAME brettl2
#define CONFIG_IPADDR 192.168.233.224
#define CONFIG_GATEWAYIP 192.168.233.1
#define CONFIG_SERVERIP 192.168.233.53
#define CONFIG_ROOTPATH "/romfs/brettl2"
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
#endif
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 135
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* an error during compilation remove an object here to get
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* Misc Settings
*/
#define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x800000
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BAUDRATE 115200
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
/* disable unnecessary features */
#undef CONFIG_BOOTM_RTEMS
#undef CONFIG_BZIP2
#undef CONFIG_KALLSYMS
#endif
|
1001-study-uboot
|
include/configs/bct-brettl2.h
|
C
|
gpl3
| 3,784
|
/*
* (C) Copyright 2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_KEYMILE_POWERPC_H
#define __CONFIG_KEYMILE_POWERPC_H
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_CMD_DTT
#define CONFIG_JFFS2_CMDLINE
/* EEprom support 24C08, 24C16, 24C64 */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
/******************************************************************************
* (PRAM usage)
* ... -------------------------------------------------------
* ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
* ... |<------------------- pram -------------------------->|
* ... -------------------------------------------------------
* @END_OF_RAM:
* @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
* @CONFIG_KM_PHRAM: address for /var
* @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
* @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
*/
/* size of rootfs in RAM */
#define CONFIG_KM_ROOTFSSIZE 0x0
/* pseudo-non volatile RAM [hex] */
#define CONFIG_KM_PNVRAM 0x80000
/* physical RAM MTD size [hex] */
#define CONFIG_KM_PHRAM 0x100000
/* resereved pram area at the end of memroy [hex] */
#define CONFIG_KM_RESERVED_PRAM 0x0
/* enable protected RAM */
#define CONFIG_PRAM 0
#define CONFIG_KM_CRAMFS_ADDR 0x800000
#define CONFIG_KM_KERNEL_ADDR 0x400000 /* 3968Kbytes */
#define CONFIG_KM_FDT_ADDR 0x7E0000 /* 128Kbytes */
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
#define CONFIG_KM_DEF_ENV_CPU \
"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
"cramfsloadfdt=" \
"cramfsload ${fdt_addr_r} " \
"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
"fdt_addr_r=" xstr(CONFIG_KM_FDT_ADDR) "\0" \
"u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"update=" \
"protect off " xstr(BOOTFLASH_START) " +${filesize} && "\
"erase " xstr(BOOTFLASH_START) " +${filesize} && " \
"cp.b ${load_addr_r} " xstr(BOOTFLASH_START) \
" ${filesize} && " \
"protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \
""
#endif /* __CONFIG_KEYMILE_POWERPC_H */
|
1001-study-uboot
|
include/configs/km/km-powerpc.h
|
C
|
gpl3
| 3,354
|
/*
* (C) Copyright 2007-2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __KM82XX_COMMON
#define __KM82XX_COMMON
/*
* Select serial console configuration
*
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
* for SCC).
*/
#define CONFIG_CONS_ON_SMC /* Console is on SMC */
#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
#undef CONFIG_CONS_NONE /* It's not on external UART */
#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
#define CONFIG_SYS_SMC_RXBUFLEN 128
#define CONFIG_SYS_MAXIDLE 10
/*
* Select ethernet configuration
*
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
* then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
* SCC, 1-3 for FCC)
*
* If CONFIG_ETHER_NONE is defined, then either the ethernet routines
* must be defined elsewhere (as for the console), or CONFIG_CMD_NET
* must be unset.
*/
#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
#undef CONFIG_ETHER_NONE /* No external Ethernet */
#define CONFIG_ETHER_INDEX 4
#define CONFIG_HAS_ETH0
#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
#define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
#ifndef CONFIG_8260_CLKIN
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
#endif
#define BOOTFLASH_START 0xFE000000
#define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
#define MTDPARTS_DEFAULT "mtdparts=" \
"app:" \
"768k(u-boot)," \
"128k(env)," \
"128k(envred)," \
"3072k(free)," \
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
/*
* Default environment settings
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_BOARD_EXTRA_ENV \
CONFIG_KM_DEF_ENV \
"EEprom_ivm=pca9544a:70:4 \0" \
"unlock=yes\0" \
"newenv=" \
"prot off 0xFE0C0000 +0x40000 && " \
"era 0xFE0C0000 +0x40000\0" \
"arch=ppc_82xx\0" \
""
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_MONITOR_LEN (768 << 10)
#define CONFIG_ENV_IS_IN_FLASH
#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */
/* enable I2C and select the hardware/software driver */
#undef CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
/*
* Software (bit-bang) I2C driver configuration
*/
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
#define I2C_SDA(bit) do { \
if (bit) \
iop->pdat |= 0x00010000; \
else \
iop->pdat &= ~0x00010000; \
} while (0)
#define I2C_SCL(bit) do { \
if (bit) \
iop->pdat |= 0x00020000; \
else \
iop->pdat &= ~0x00020000; \
} while (0)
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#ifndef __ASSEMBLY__
void set_sda(int state);
void set_scl(int state);
int get_sda(void);
int get_scl(void);
#endif
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_IMMR 0xF0000000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* Hard reset configuration word */
#define CONFIG_SYS_HRCW_MASTER 0x0604b211
/* No slaves */
#define CONFIG_SYS_HRCW_SLAVE1 0
#define CONFIG_SYS_HRCW_SLAVE2 0
#define CONFIG_SYS_HRCW_SLAVE3 0
#define CONFIG_SYS_HRCW_SLAVE4 0
#define CONFIG_SYS_HRCW_SLAVE5 0
#define CONFIG_SYS_HRCW_SLAVE6 0
#define CONFIG_SYS_HRCW_SLAVE7 0
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#define CONFIG_SYS_HID0_INIT 0
#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
#define CONFIG_SYS_HID2 0
#define CONFIG_SYS_SIUMCR 0x4020c200
#define CONFIG_SYS_SYPCR 0xFFFFFF83
#define CONFIG_SYS_BCR 0x10000000
#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
/*
*-----------------------------------------------------------------------
* RMR - Reset Mode Register 5-5
*-----------------------------------------------------------------------
* turn on Checkstop Reset Enable
*/
#define CONFIG_SYS_RMR 0
/*
*-----------------------------------------------------------------------
* TMCNTSC - Time Counter Status and Control 4-40
*-----------------------------------------------------------------------
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
* and enable Time Counter
*/
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
/*
*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 4-42
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
* Periodic timer
*/
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
/*
*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_RCCR 0
/*
* Init Memory Controller:
*
* Bank Bus Machine PortSz Device
* ---- --- ------- ------ ------
* 0 60x GPCM 8 bit FLASH
* 1 60x SDRAM 32 bit SDRAM
* 3 60x GPCM 8 bit GPIO/PIGGY
* 5 60x GPCM 16 bit CFG-Flash
*
*/
/* Bank 0 - FLASH
*/
#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
BRx_PS_8 |\
BRx_MS_GPCM_P |\
BRx_V)
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
ORxG_CSNT |\
ORxG_ACS_DIV2 |\
ORxG_SCY_5_CLK |\
ORxG_TRLX)
#define CONFIG_SYS_MPTPR 0x1800
/*
*-----------------------------------------------------------------------------
* Address for Mode Register Set (MRS) command
*-----------------------------------------------------------------------------
*/
#define CONFIG_SYS_MRS_OFFS 0x00000110
#define CONFIG_SYS_PSRT 0x0e
#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
BRx_PS_64 |\
BRx_MS_SDRAM_P |\
BRx_V)
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
/*
* UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
*/
#define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
ORxG_CSNT | ORxG_ACS_DIV2 |\
ORxG_SCY_3_CLK | ORxG_TRLX)
/*
* BFTICU board FPGA on CS4 initialization values
*/
#define CONFIG_SYS_FPGA_BASE 0x40000000
#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
ORxG_CSNT | ORxG_ACS_DIV2 |\
ORxG_SCY_3_CLK | ORxG_TRLX)
/*
* CFG-Flash on CS5 initialization values
*/
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
#define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
CONFIG_SYS_FLASH_SIZE_2) |\
ORxG_CSNT | ORxG_ACS_DIV2 |\
ORxG_SCY_5_CLK | ORxG_TRLX)
#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
/* pass open firmware flat tree */
#define CONFIG_FIT 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
#endif /* __KM82XX_COMMON */
|
1001-study-uboot
|
include/configs/km/km82xx-common.h
|
C
|
gpl3
| 9,819
|
/*
* (C) Copyright 2008-2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_KEYMILE_H
#define __CONFIG_KEYMILE_H
/* Do boardspecific init for all boards */
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT
#define CONFIG_BOOTCOUNT_LIMIT
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DEFAULTENV_VARS
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_SETEXPR
#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_HUSH_INIT_VAR
#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */
#define CONFIG_SYS_HZ 1000 /* decr. freq: 1 ms ticks */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 1
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MUX
/* Support the IVM EEprom */
#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
#define CONFIG_SYS_FLASH_PROTECTION
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
/* UBI Support for all Keymile boards */
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_CONCAT
#define CONFIG_CMD_CRAMFS
#define CONFIG_CRAMFS_CMDLINE
#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS
#define CONFIG_KM_DEF_ENV_BOOTPARAMS \
"actual_bank=0\0"
#endif
#ifndef CONFIG_KM_DEF_NETDEV
#define CONFIG_KM_DEF_NETDEV \
"netdev=eth0\0"
#endif
#ifndef CONFIG_KM_UBI_PARTITION_NAME
#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
#endif
#ifndef CONFIG_KM_UBI_LINUX_MTD_NAME
#define CONFIG_KM_UBI_LINUX_MTD_NAME "ubi0"
#endif
#define xstr(s) str(s)
#define str(s) #s
/*
* boottargets
* - set 'subbootcmds'
* - set 'bootcmd' and 'altbootcmd'
* available targets:
* - 'release': for a standalone system kernel/rootfs from flash
*/
#define CONFIG_KM_DEF_ENV_BOOTTARGETS \
"subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel " \
"flashargs add_default addpanic boot\0" \
"develop=" \
"tftp 200000 scripts/develop-${arch}.txt && " \
"env import -t 200000 ${filesize} && " \
"run setup_debug_env\0" \
"ramfs=" \
"tftp 200000 scripts/ramfs-${arch}.txt && " \
"env import -t 200000 ${filesize} && " \
"run setup_debug_env\0" \
""
/*
* bootargs
* - modify 'bootargs'
*
* - 'add_default': default bootargs common for all arm/ppc boards
* - 'addpanic': add kernel panic options
* - 'flashargs': defaults arguments for flash base boot
*
*/
#define CONFIG_KM_DEF_ENV_BOOTARGS \
"add_default=" \
"setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off3" \
" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \
" mem=${kernelmem} init=${init}" \
" phram.phram=phvar,${varaddr}," xstr(CONFIG_KM_PHRAM) \
" ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \
CONFIG_KM_DEF_BOOT_ARGS_CPU \
"\0" \
"addpanic=" \
"setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0" \
"flashargs=" \
"setenv bootargs " \
"root=mtdblock:rootfs${boot_bank} " \
"rootfstype=squashfs ro\0" \
""
/*
* flash_boot
* - commands for booting from flash
*
* - 'cramfsloadkernel': copy kernel from a cramfs to ram
* - 'ubiattach': attach ubi partition
* - 'ubicopy': copy ubi volume to ram
* - volume names: bootfs0, bootfs1, bootfs2, ...
*
* processor specific settings
* - 'cramfsloadfdt': copy fdt from a cramfs to ram
*/
#define CONFIG_KM_DEF_ENV_FLASH_BOOT \
"cramfsaddr=" xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \
"cramfsloadkernel=cramfsload ${load_addr_r} uImage\0" \
"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME "\0" \
"ubicopy=ubi read "xstr(CONFIG_KM_CRAMFS_ADDR) \
" bootfs${boot_bank}\0" \
""
/*
* constants
* - KM specific constants and commands
*
* - 'default': setup default environment
*/
#define CONFIG_KM_DEF_ENV_CONSTANTS \
"backup_bank=0\0" \
"release=run newenv; reset\0" \
"pnvramsize=" xstr(CONFIG_KM_PNVRAM) "\0" \
"testbootcmd=setenv boot_bank ${test_bank}; " \
"run ${subbootcmds}; reset\0" \
""
#ifndef CONFIG_KM_DEF_ENV
#define CONFIG_KM_DEF_ENV \
CONFIG_KM_DEF_ENV_BOOTPARAMS \
CONFIG_KM_DEF_NETDEV \
CONFIG_KM_DEF_ENV_CPU \
CONFIG_KM_DEF_ENV_BOOTTARGETS \
CONFIG_KM_DEF_ENV_BOOTARGS \
CONFIG_KM_DEF_ENV_FLASH_BOOT \
CONFIG_KM_DEF_ENV_CONSTANTS \
"altbootcmd=run bootcmd\0" \
"bootcmd=km_checkbidhwk && " \
" setenv bootcmd \'setenv boot_bank ${actual_bank}; " \
"run ${subbootcmds}; reset\' && " \
"setenv altbootcmd \'setenv boot_bank ${backup_bank}; " \
"run ${subbootcmds}; reset\' && " \
"saveenv && saveenv && boot\0" \
"bootlimit=2\0" \
"init=/sbin/init-overlay.sh\0" \
"load_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
"load=tftpboot ${load_addr_r} ${u-boot}\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"stderr=serial\0" \
"stdin=serial\0" \
"stdout=serial\0" \
""
#endif /* CONFIG_KM_DEF_ENV */
#define CONFIG_VERSION_VARIABLE /* include version env variable */
#endif /* __CONFIG_KEYMILE_H */
|
1001-study-uboot
|
include/configs/km/keymile-common.h
|
C
|
gpl3
| 7,396
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2010-2011
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/*
* for linking errors see
* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
*/
#ifndef _CONFIG_KM_ARM_H
#define _CONFIG_KM_ARM_H
/* We got removed from Linux mach-types.h */
#define MACH_TYPE_KM_KIRKWOOD 2255
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_MARVELL
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#define CONFIG_CMD_NAND
#define CONFIG_CMD_SF
#define CONFIG_SOFT_I2C /* I2C bit-banged */
#include "asm/arch/config.h"
#define CONFIG_SYS_TEXT_BASE 0x07d00000 /* code address before reloc */
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
/* pseudo-non volatile RAM [hex] */
#define CONFIG_KM_PNVRAM 0x80000
/* physical RAM MTD size [hex] */
#define CONFIG_KM_PHRAM 0x17F000
#define CONFIG_KM_CRAMFS_ADDR 0x2400000
#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
"bootcountaddr=${bootcountaddr} ${mtdparts}" \
" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
#define CONFIG_KM_DEF_ENV_CPU \
"boot=bootm ${load_addr_r} - -\0" \
"cramfsloadfdt=true\0" \
"u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
CONFIG_KM_DEF_ENV_UPDATE \
""
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_MISC_INIT_R
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
/*
* Serial Port configuration
* The following definitions let you select what serial you want to use
* for your console driver.
*/
#define CONFIG_CONS_INDEX 1 /* Console on UART0 */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_INITRD_TAG /* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
/*
* Commands configuration
*/
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NFS
/*
* Without NOR FLASH we need this
*/
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
/*
* NAND Flash configuration
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define BOOTFLASH_START 0x0
/* Kirkwood has two serial IF */
#if (CONFIG_CONS_INDEX == 2)
#define CONFIG_KM_CONSOLE_TTY "ttyS1"
#else
#define CONFIG_KM_CONSOLE_TTY "ttyS0"
#endif
/*
* Other required minimal configurations
*/
#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
/*
* Ethernet Driver configuration
*/
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
/*
* UBI related stuff
*/
#define CONFIG_SYS_USE_UBI
/*
* I2C related stuff
*/
#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
#if defined(CONFIG_SOFT_I2C)
#ifndef __ASSEMBLY__
#include <asm/arch-kirkwood/gpio.h>
extern void __set_direction(unsigned pin, int high);
void set_sda(int state);
void set_scl(int state);
int get_sda(void);
int get_scl(void);
#define KM_KIRKWOOD_SDA_PIN 8
#define KM_KIRKWOOD_SCL_PIN 9
#define KM_KIRKWOOD_ENV_WP 38
#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0)
#define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1)
#define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0)
#define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit)
#define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit)
#endif
#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
#define I2C_SOFT_DECLARATIONS
#endif
/* EEprom support 24C128, 24C256 valid for environment eeprom */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/*
* Environment variables configurations
*/
#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_EEPROM_WREN
#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
#define CONFIG_I2C_ENV_EEPROM_BUS KM_ENV_BUS "\0"
/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define FLASH_GPIO_PIN 0x00010000
#define MTDIDS_DEFAULT "nand0=orion_nand"
/* test-only: partitioning needs some tuning, this is just for tests */
#define MTDPARTS_DEFAULT "mtdparts=" \
"orion_nand:" \
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
#define CONFIG_KM_DEF_ENV_UPDATE \
"update=" \
"spi on;sf probe 0;sf erase 0 50000;" \
"sf write ${load_addr_r} 0 ${filesize};" \
"spi off\0"
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
"eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
" ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0" \
"arch=arm\0" \
"EEprom_ivm=" KM_IVM_BUS "\0" \
""
#if defined(CONFIG_SYS_NO_FLASH)
#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
#undef CONFIG_FLASH_CFI_MTD
#undef CONFIG_JFFS2_CMDLINE
#endif
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* Do early setups now in board_init_f() */
#define CONFIG_BOARD_EARLY_INIT_F
/*
* resereved pram area at the end of memroy [hex]
* 8Mbytes for switch + 4Kbytes for bootcount
*/
#define CONFIG_KM_RESERVED_PRAM 0x801000
/* address for the bootcount (taken from end of RAM) */
#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM)
/* enable POST tests */
#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS)
#define CONFIG_POST_SKIP_ENV_FLAGS
#define CONFIG_POST_EXTERNAL_WORD_FUNCS
#define CONFIG_CMD_DIAG
#endif /* _CONFIG_KM_ARM_H */
|
1001-study-uboot
|
include/configs/km/km_arm.h
|
C
|
gpl3
| 8,731
|
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* Copyright (C) 2007 Logic Product Development, Inc.
* Peter Barada <peterb@logicpd.com>
*
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* (C) Copyright 2010
* Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
*
* (C) Copyright 2010-2011
* Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __CONFIG_KM8321_COMMON_H
#define __CONFIG_KM8321_COMMON_H
/*
* High Level Configuration Options
*/
#define CONFIG_QE /* Has QE */
#define CONFIG_MPC832x /* MPC832x CPU specific */
#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */
#define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
/* include common defines/options for all 83xx Keymile boards */
#include "km83xx-common.h"
#define CONFIG_MISC_INIT_R
/*
* System IO Config
*/
#define CONFIG_SYS_SICRL SICRL_IRQ_CKS
/*
* Hardware Reset Configuration Word
*/
#define CONFIG_SYS_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
HRCWL_DDR_TO_SCB_CLK_2X1 | \
HRCWL_CSB_TO_CLKIN_2X1 | \
HRCWL_CORE_TO_CSB_2_5X1 | \
HRCWL_CE_PLL_VCO_DIV_2 | \
HRCWL_CE_TO_PLL_1X3)
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_AGENT | \
HRCWH_PCI_ARBITER_DISABLE | \
HRCWH_CORE_ENABLE | \
HRCWH_FROM_0X00000100 | \
HRCWH_BOOTSEQ_DISABLE | \
HRCWH_SW_WATCHDOG_DISABLE | \
HRCWH_ROM_LOC_LOCAL_16BIT | \
HRCWH_BIG_ENDIAN | \
HRCWH_LALE_NORMAL)
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
SDRAM_CFG_32_BE | \
SDRAM_CFG_SREN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ODT_WR_CFG | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_MODE 0x47860252
#define CONFIG_SYS_DDR_MODE2 0x8080c000
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
(0 << TIMING_CFG0_WWT_SHIFT) | \
(0 << TIMING_CFG0_RRT_SHIFT) | \
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
(2 << TIMING_CFG1_WRREC_SHIFT) | \
(6 << TIMING_CFG1_REFREC_SHIFT) | \
(2 << TIMING_CFG1_ACTTORW_SHIFT) | \
(6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
(2 << TIMING_CFG1_PRETOACT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
(5 << TIMING_CFG2_CPO_SHIFT))
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/*
* Local Bus Configuration & Clock Setup
*/
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
* MMU Setup
*/
#define CONFIG_SYS_IBAT7L (0)
#define CONFIG_SYS_IBAT7U (0)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif /* __CONFIG_KM8321_COMMON_H */
|
1001-study-uboot
|
include/configs/km/km8321-common.h
|
C
|
gpl3
| 4,068
|
/*
* (C) Copyright 2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __CONFIG_KM83XX_H
#define __CONFIG_KM83XX_H
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#include "km-powerpc.h"
#define MTDIDS_DEFAULT "nor0=boot"
#define MTDPARTS_DEFAULT "mtdparts=" \
"boot:" \
"768k(u-boot)," \
"128k(env)," \
"128k(envred)," \
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
#define CONFIG_MISC_INIT_R
/*
* System Clock Setup
*/
#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_83XX_DDR_USES_CS0
/*
* Manually set up DDR parameters
*/
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE 0xF0000000
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
/* Reserve 768 kB for Mon */
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* Init Local Bus Memory Controller:
*
* Bank Bus Machine PortSz Size Device
* ---- --- ------- ------ ----- ------
* 0 Local GPCM 16 bit 256MB FLASH
* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
*
*/
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
BR_PS_16 | /* 16 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
/*
* PRIO1/PIGGY on the local bus CS1
*/
/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB)
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
BR_PS_8 | /* 8 bit port size */ \
BR_MS_GPCM | /* MSEL = GPCM */ \
BR_V)
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "UEC0"
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif
/*
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else /* CFG_SYS_RAMBOOT */
#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif /* CFG_SYS_RAMBOOT */
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_FSL_I2C
#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x3000
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
#endif
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/*
* Internal Definitions
*/
#define BOOTFLASH_START 0xF0000000
#define CONFIG_KM_CONSOLE_TTY "ttyS0"
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif
#ifndef CONFIG_KM_DEF_ARCH
#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
CONFIG_KM_DEF_ARCH \
"dtt_bus=pca9547:70:a\0" \
"EEprom_ivm=pca9547:70:9\0" \
"newenv=" \
"prot off 0xF00C0000 +0x40000 && " \
"era 0xF00C0000 +0x40000\0" \
"unlock=yes\0" \
""
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#endif
#endif /* __CONFIG_KM83XX_H */
|
1001-study-uboot
|
include/configs/km/km83xx-common.h
|
C
|
gpl3
| 9,635
|
/*
* Configuation settings for the Freescale MCF53017EVB.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M53017EVB_H
#define _M53017EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF5301x /* define processor family */
#define CONFIG_M53015 /* define processor type */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#undef CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_SYS_UNIFY_CACHE
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_TX_ETH_BUFFER 8
# define CONFIG_SYS_FEC_BUF_USE_SRAM
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_HAS_ETH1
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define CONFIG_SYS_FEC1_PINMUX 0
# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
# define MCFFEC_TOUT_LOOP 50000
# define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2"
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_CNT (0x8000)
#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M53017
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 3ffff;" \
"era 0 3ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
#define CONFIG_SYS_LOAD_ADDR 0x40010000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
#define CONFIG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x43711630
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
# define CONFIG_FLASH_SPANSION_S29WS_N 1
# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CONFIG_ENV_OFFSET 0x8000
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x8000
#define CONFIG_ENV_IS_IN_FLASH 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash
* CS1 - Ext SRAM
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0
#define CONFIG_SYS_CS0_MASK 0x00FF0001
#define CONFIG_SYS_CS0_CTRL 0x00001FA0
#define CONFIG_SYS_CS1_BASE 0xC0000000
#define CONFIG_SYS_CS1_MASK 0x00070001
#define CONFIG_SYS_CS1_CTRL 0x00001FA0
#endif /* _M53017EVB_H */
|
1001-study-uboot
|
include/configs/M53017EVB.h
|
C
|
gpl3
| 8,415
|
/*
* Configuation settings for the Freescale M5271EVB
*
* Based on MC5272C3 and r5200 board configs
* (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5271EVB_H
#define _M5271EVB_H
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5271 /* define processor type */
#define CONFIG_M5271EVB /* define board type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET 0x4000
#else
#define CONFIG_ENV_ADDR 0xffe04000
#endif
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00000300
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
#define CONFIG_BOOTFILE "u-boot.bin"
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_RETRY_COUNT 5
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M5271EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"uboot=u-boot.bin\0" \
"load=tftp $loadaddr $uboot\0" \
"upd=run load; run prog\0" \
"prog=prot off ffe00000 ffe3ffff;" \
"era ffe00000 ffe3ffff;" \
"cp.b $loadaddr ffe00000 $filesize;" \
"save\0" \
""
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_HZ 1000000
/* Clock configuration
* The external oscillator is a 25.000 MHz
* CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
* bus_clk = (cpu_clk/2) (fixed ratio)
*
* If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
* match the new clock speed. Max cpu_clk is 150 MHz.
*/
#define CONFIG_SYS_CLK 100000000
#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE 0x20000
#else
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_MONITOR_LEN 0x40000
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_SIZE 0x200000
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/* Chip Select 0 : Boot Flash */
#define CONFIG_SYS_CS0_BASE 0xFFE00000
#define CONFIG_SYS_CS0_MASK 0x001F0001
#define CONFIG_SYS_CS0_CTRL 0x00001980
/* Chip Select 1 : External SRAM */
#define CONFIG_SYS_CS1_BASE 0x30000000
#define CONFIG_SYS_CS1_MASK 0x00070001
#define CONFIG_SYS_CS1_CTRL 0x00001900
#endif /* _M5271EVB_H */
|
1001-study-uboot
|
include/configs/M5271EVB.h
|
C
|
gpl3
| 8,053
|
/*
* U-boot - Configuration file for BF561 EZKIT board
*/
#ifndef __CONFIG_BF561_EZKIT_H__
#define __CONFIG_BF561_EZKIT_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf561-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 30000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 6
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x306
#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
#define CONFIG_EBIU_AMGCTL_VAL 0x3F
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x2C010300
#define CONFIG_SMC_USE_32_BIT 1
#define CONFIG_HOSTNAME bf561-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 135
/* The BF561-EZKIT uses a top boot flash */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET (0x800000 - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE 0x2000
/*
* I2C Settings
*/
#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
/*
* Misc Settings
*/
#define CONFIG_UART_CONSOLE 0
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf561-ezkit.h
|
C
|
gpl3
| 2,694
|
/*
* (C) Copyright 2003
* Texas Instruments.
* Kshitij Gupta <kshitij@ti.com>
* Configuation settings for the TI OMAP Innovator board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP1610 1 /* which is in a 1610 */
#define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_INNOVATOR
/* input clock of PLL */
/* the OMAP1610 Innovator has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
/*
*/
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04000300
#define CONFIG_LAN91C96_EXT_PHY
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \
root=/dev/nfs rw nfsroot=157.87.82.48:\
/home/a0875451/mwd/myfs/target ip=dhcp"
#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */
#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
#define CONFIG_BOOTFILE "uImage" /* file to load */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
* DPLL1. This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */
#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */
#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */
#ifndef __ASSEMBLY__
extern unsigned long omap_flash_base; /* set in flash__init */
#endif
#define CONFIG_SYS_FLASH_BASE omap_flash_base
#elif defined(CONFIG_CS0_BOOT)
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0
#else
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1
#endif
#define PHYS_SRAM 0x20000000
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
/* addr of environment */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap1610inn.h
|
C
|
gpl3
| 6,409
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* P4080 DS board configuration file
*/
#define CONFIG_P4080DS
#define CONFIG_PHYS_64BIT
#define CONFIG_PPC_P4080
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_MMC
#define CONFIG_PCIE3
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
|
1001-study-uboot
|
include/configs/P4080DS.h
|
C
|
gpl3
| 1,168
|
/*
* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* BOARD/CPU
*/
#include "../board/altera/nios2-generic/custom_fpga.h" /* fpga parameters */
#define CONFIG_BOARD_NAME "nios2-generic" /* custom board name */
#define CONFIG_BOARD_EARLY_INIT_F /* enable early board-spec. init */
#define CONFIG_SYS_NIOS_SYSID_BASE CONFIG_SYS_SYSID_BASE
/*
* SERIAL
*/
#define CONFIG_ALTERA_UART
#if defined(CONFIG_ALTERA_JTAG_UART)
# define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_JTAG_UART_BASE
#else
# define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_UART_BASE
#endif
#define CONFIG_ALTERA_JTAG_UART_BYPASS
#define CONFIG_SYS_NIOS_FIXEDBAUD
#define CONFIG_BAUDRATE CONFIG_SYS_UART_BAUD
#define CONFIG_SYS_BAUDRATE_TABLE {CONFIG_BAUDRATE}
#define CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress console info */
/*
* TIMER
*/
#define CONFIG_SYS_LOW_RES_TIMER
#define CONFIG_SYS_NIOS_TMRBASE CONFIG_SYS_TIMER_BASE
#define CONFIG_SYS_NIOS_TMRIRQ CONFIG_SYS_TIMER_IRQ
#define CONFIG_SYS_HZ 1000 /* Always 1000 */
#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
#define CONFIG_SYS_NIOS_TMRCNT \
(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_TIMER_FREQ / 1000) - 1)
/*
* STATUS LED
*/
#define CONFIG_ALTERA_PIO
#define CONFIG_SYS_ALTERA_PIO_NUM 1
#define CONFIG_SYS_ALTERA_PIO_GPIO_NUM LED_PIO_WIDTH
#define CONFIG_STATUS_LED /* Enable status driver */
#define CONFIG_GPIO_LED /* Enable GPIO LED driver */
#define CONFIG_GPIO /* Enable GPIO driver */
#define STATUS_LED_BIT 0 /* Bit-0 on GPIO */
#define STATUS_LED_STATE 1 /* Blinking */
#define STATUS_LED_PERIOD (500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BOOTD
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_ITEST
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
#ifdef CONFIG_CMD_NET
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
#endif
/*
* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
* CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
* reset address, no? This will keep the environment in user region
* of flash. NOTE: the monitor length must be multiple of sector size
* (which is common practice).
*/
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */
#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
#define CONFIG_ENV_ADDR ((CONFIG_SYS_RESET_ADDR + \
CONFIG_SYS_MONITOR_LEN) | \
CONFIG_SYS_FLASH_BASE)
/*
* MEMORY ORGANIZATION
* -Monitor at top of sdram.
* -The heap is placed below the monitor
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*/
#define CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_SDRAM_SIZE - \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x20000)
#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - \
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
/*
* MISC
*/
#define CONFIG_SYS_LONGHELP /* Provide extended help */
#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
#define CONFIG_SYS_MAXARGS 16 /* Max command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + \
16) /* Print buf size */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - 0x20000)
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/nios2-generic.h
|
C
|
gpl3
| 5,024
|
/*
* Configuation settings for the esd TASREG board.
*
* (C) Copyright 2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _TASREG_H
#define _TASREG_H
#ifndef __ASSEMBLY__
#include <asm/m5249.h>
#endif
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5249 /* define processor type */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_NET
#define CONFIG_BOOTDELAY 3
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_HZ 1000
/*
* Clock configuration: enable only one of the following options
*/
#if 0 /* this setting will run the cpu at 11MHz */
#define CONFIG_SYS_PLL_BYPASS 1 /* bypass PLL for test purpose */
#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
#define CONFIG_SYS_CLK 11289600 /* PLL bypass */
#endif
#if 0 /* this setting will run the cpu at 70MHz */
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
#define CONFIG_SYS_CLK 72185018 /* The next lower speed */
#endif
#if 1 /* this setting will run the cpu at 140MHz */
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
#endif
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CONFIG_SYS_MBAR2 0x80000000
/*-----------------------------------------------------------------------
* I2C
*/
#define CONFIG_SOFT_I2C
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
/* 32 byte page write mode using*/
/* last 5 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#if defined (CONFIG_SOFT_I2C)
#if 0 /* push-pull */
#define SDA 0x00800000
#define SCL 0x00000008
#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;}
#define I2C_READ ((IN1&SDA)?1:0)
#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;}
#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;}
#define I2C_DELAY {udelay(5);}
#define I2C_ACTIVE {DIR1|=SDA;}
#define I2C_TRISTATE {DIR1&=~SDA;}
#else /* open-collector */
#define SDA 0x00800000
#define SCL 0x00000008
#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
#define I2C_READ ((IN1&SDA)?1:0)
#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;}
#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;}
#define I2C_DELAY {udelay(5);}
#define I2C_ACTIVE {DIR1|=SDA;}
#define I2C_TRISTATE {DIR1&=~SDA;}
#endif
#endif
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#if 0 /* test-only */
#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
#endif
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN 0x20000
#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
/* CS0 - AMD Flash, address 0xffc00000 */
#define CONFIG_SYS_CS0_BASE 0xffc00000
#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
/* CS1 - FPGA, address 0xe0000000 */
#define CONFIG_SYS_CS1_BASE 0xe0000000
#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
/*-----------------------------------------------------------------------
* FPGA stuff
*/
#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
#define CONFIG_SYS_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */
#define CONFIG_SYS_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */
#define CONFIG_SYS_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */
#define CONFIG_SYS_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */
#endif /* _TASREG_H */
|
1001-study-uboot
|
include/configs/TASREG.h
|
C
|
gpl3
| 12,156
|
/*
* U-boot - Configuration file for CM-BF537U board
*/
#ifndef __CONFIG_CM_BF537U_H__
#define __CONFIG_CM_BF537U_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 30000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 18
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/* Core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
#define CONFIG_EBIU_SDRRC_VAL 0x3f8
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0x20308000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_NETCONSOLE 1
#endif
#define CONFIG_HOSTNAME cm-bf537u
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 35
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE 0x8000
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* an error during compilation remove an object here to get
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* SPI_MMC Settings
*/
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/cm-bf537u.h
|
C
|
gpl3
| 3,851
|
/*
* (C) Copyright 2004
* Texas Instruments.
* Kshitij Gupta <kshitij@ti.com>
* Configuration settings for the TI OMAP 1610 H2 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP1610 1 /* which is in a 1610 */
#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_H2
/* input clock of PLL */
/* the OMAP1610 H2 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04000300
#define CONFIG_LAN91C96_EXT_PHY
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp"
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
* DPLL1. This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */
#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */
#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */
#ifndef __ASSEMBLY__
extern unsigned long omap_flash_base; /* set in flash__init */
#endif
#define CONFIG_SYS_FLASH_BASE omap_flash_base
#elif defined(CONFIG_CS0_BOOT)
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0
#else
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1
#endif
#define PHYS_SRAM 0x20000000
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
/* addr of environment */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap1610h2.h
|
C
|
gpl3
| 6,153
|
/*
* U-boot - Configuration file for TCM-BF537 board
*/
#ifndef __CONFIG_TCM_BF537_H__
#define __CONFIG_TCM_BF537_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 21
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
#define CONFIG_EBIU_SDRRC_VAL 0x3f8
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0x20308000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_NETCONSOLE 1
#endif
#define CONFIG_HOSTNAME tcm-bf537
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 67
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x8000
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_SECT_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* an error during compilation remove an object here to get
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* SPI_MMC Settings
*/
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/tcm-bf537.h
|
C
|
gpl3
| 3,883
|
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*CPU*/
#define CONFIG_440 1
#define CONFIG_XILINX_PPC440_GENERIC 1
#include "../board/xilinx/ppc440-generic/xparameters.h"
/*Mem Map*/
#define CONFIG_SYS_SDRAM_SIZE_MB 256
/*Env*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0x340000
#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
/*Misc*/
#define CONFIG_SYS_PROMPT "board:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 259
#define MTDIDS_DEFAULT "nor0=ml507-flash"
#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/xilinx-ppc440-generic.h
|
C
|
gpl3
| 1,675
|
/*
* U-boot - Configuration file for BF533 STAMP board
*/
#ifndef __CONFIG_BF533_STAMP_H__
#define __CONFIG_BF533_STAMP_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 11059200
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 45
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 11
#define CONFIG_MEM_SIZE 128
#define CONFIG_EBIU_SDRRC_VAL 0x268
#define CONFIG_EBIU_SDGCTL_VAL 0x911109
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20300300
#define SMC91111_EEPROM_INIT() \
do { \
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
bfin_write_FIO_FLAG_C(PF1); \
bfin_write_FIO_FLAG_S(PF0); \
SSYNC(); \
} while (0)
#define CONFIG_HOSTNAME bf533-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 67
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* an error during compilation remove an object here to get
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
/*
* I2C Settings
*/
#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
/*
* Compact Flash / IDE / ATA Settings
*/
/* Enabled below option for CF support */
/* #define CONFIG_STAMP_CF */
#if defined(CONFIG_STAMP_CF)
#define CONFIG_MISC_INIT_R
#define CONFIG_DOS_PARTITION 1
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 2
#undef CONFIG_EBIU_AMBCTL1_VAL
#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
#endif
/*
* Misc Settings
*/
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
/* FLASH/ETHERNET uses the same async bank */
#define SHARED_RESOURCES 1
/* define to enable boot progress via leds */
/* #define CONFIG_SHOW_BOOT_PROGRESS */
/* define to enable run status via led */
/* #define CONFIG_STATUS_LED */
#ifdef CONFIG_STATUS_LED
#define CONFIG_GPIO_LED
#define CONFIG_BOARD_SPECIFIC_LED
/* use LED0 to indicate booting/alive */
#define STATUS_LED_BOOT 0
#define STATUS_LED_BIT GPIO_PF2
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
/* use LED1 to indicate crash */
#define STATUS_LED_CRASH 1
#define STATUS_LED_BIT1 GPIO_PF3
#define STATUS_LED_STATE1 STATUS_LED_ON
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
/* #define STATUS_LED_BIT2 GPIO_PF4 */
#endif
/* define to enable splash screen support */
/* #define CONFIG_VIDEO */
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf533-stamp.h
|
C
|
gpl3
| 5,503
|
/*
* (C) Copyright 2012
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
* Gary Jennejohn <garyj@denx.de>
* David Mueller <d.mueller@elsoft.ch>
*
* Modified for the friendly-arm mini2440 by
* wang_xi@anyka.com
* (C) Copyright 2012
*
* Configuation settings for the friendly-arm mini2440 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T /* This is an ARM920T Core */
#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2440 /* specifically a SAMSUNG S3C2440 SoC */
#define CONFIG_MINI2440
//wx: if nand boot img size is larger than 4K, need open this to reload
#define CONFIG_NAND_BOOT //CONFIG_NAND_SPL
#ifdef CONFIG_NAND_BOOT
//#define CONFIG_SKIP_LOWLEVEL_INIT
/*wx: 0x33000000->0x34000000 (48M:16M)*/
#define CONFIG_SYS_TEXT_BASE 0x33000000
#else
/*wx:if run on ram, must open it*/
#define CONFIG_SKIP_LOWLEVEL_INIT
/*wx: 0x33400000->0x34000000 (52M:12M)*/
#define CONFIG_SYS_TEXT_BASE 0x33400000
#endif
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
/* input clock of PLL (the mini2440 has 12MHz input clock) */
#define CONFIG_SYS_CLK_FREQ 12000000
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
/*'wx: if defined this macro, uboot will auto create the memery info tag, if not
* MUST describle in CONFIG_BOOTARGS "mem=xx"(e.g. mem=64M)
*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*
* Hardware drivers
*/
#if 1
/*mini2440 use DM9000EP which conected with nGCS4(0x20000000)*/
#define CONFIG_DRIVER_DM9000
#define CONFIG_DM9000_NO_SROM
#define CONFIG_DM9000_BASE 0x20000300
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
//#define CONFIG_DM9000_DEBUG
#else
#define CONFIG_CS8900 /* we have a CS8900 on-board */
#define CONFIG_CS8900_BASE 0x19000300
#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
#endif
/*
* select serial console configuration
*/
#define CONFIG_S3C24X0_SERIAL
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on mini2440 */
/************************************************************
* USB support (currently only works with D-cache off)
************************************************************/
#define CONFIG_USB_OHCI
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
/************************************************************
* RTC
************************************************************/
#define CONFIG_RTC_S3C24X0
#define CONFIG_BAUDRATE 115200
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB
#define CONFIG_CMD_NET
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
/* autoboot */
#define CONFIG_BOOTDELAY 9
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_RESET_TO_RETRY
#define CONFIG_ZERO_BOOTDELAY_CHECK
//-----------------------------------------------------------------------------
#define CONFIG_BOOTARGS_CRAMFS \
"root=/dev/mtdblock2 rw "\
"rootfstype=cramfs "\
"console=ttySAC0,115200 "\
"noinitrd "\
"mem=64M "\
"init=/linuxrc"
//-----------------------------------------------------------------------------
// nand flash boot, rootfs at mtd2, refer to kernel partition.
#define CONFIG_BOOTARGS_YAFFS \
"root=/dev/mtdblock2 rw "\
"rootfstype=yaffs "\
"noinitrd "\
"console=ttySAC0,115200 "\
"init=/linuxrc"
//------------- ramfs use init instead of linuxrc -----------------------------
#define CONFIG_BOOTARGS_RAMFS_P_IMG \
"root=ramfs "\
"devfs=mount "\
"console=ttySAC0,115200"
//-----------------------------------------------------------------------------
#define CONFIG_BOOTARGS_RAMDISK_IMG \
"initrd=0x31000000,0x400000 "\
"mem=64M "\
"root=/dev/ram rw "\
"console=ttySAC0,115200 "\
"init=/linuxrc"
//-----------------------------------------------------------------------------
#define CONFIG_BOOTARGS CONFIG_BOOTARGS_RAMFS_P_IMG
//-----------------------------------------------------------------------------
#define SET_CRAMFS_BOOTARGS_COMMAND \
"setenv bootargs " CONFIG_BOOTARGS_CRAMFS
#define SET_YAFFSFS_BOOTARGS_COMMAND \
"setenv bootargs " CONFIG_BOOTARGS_YAFFS
#define SET_RAMFS_P_BOOTARGS_COMMAND \
"setenv bootargs " CONFIG_BOOTARGS_RAMFS_P_IMG
#define SET_RAMDISK_BOOTARGS_COMMAND \
"setenv bootargs " CONFIG_BOOTARGS_RAMDISK_IMG
//==============================================================================E
//wx: the Head 3 bytes MUST is a valid Value,or else the MAC will set Failed.
#define CONFIG_ETHADDR 12:34:56:85:09:09
#define CONFIG_NETMASK 255.255.255.0
//wx: because my wireless LAN has used 192.168.0.X net, and I seted wired LAN on 192.168.9.X net
#define CONFIG_IPADDR 192.168.9.1
#define CONFIG_SERVERIP 192.168.9.2
#define CONFIG_GATEWAYIP 192.168.9.2
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "[WangXi@MINI2440]#" //wx:comment:boot command line prefix string
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* may be activated as soon as s3c24x0 has print_cpuinfo support */
/*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */
#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x30008000
#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* support additional compression methods */
#define CONFIG_BZIP2
#define CONFIG_LZO
#define CONFIG_LZMA
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
//wx:Sdram HY57V561620FTP/K4S561632N is conected with nGCS6(0x30000000),and maped to its first bank.
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #0 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* wx:32M X 2=64M */
//wx:Norfalsh SST39VF1601/S29AL016 is conected with NGCS0(0x00000000)
//this will be a member of cfi_flash_bank_addr
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* NorFLASH and environment organization
*/
/* wx:comment: bleow is the configure of NorFlash S29AL016(Supplier:Spansion)
* a.Common Flash Interface(CFI) is an open specification,May be implemently
* by vendor:Inter,AMD,Sharp,Fujitsu.
* b.Legacy Component:JEDEC Stardard, not CFI.
* c.Spansion is a supplier which established by AMD and Fujistu, This NorFlash
* is CFI compliant and compatility JEDEC Standard.
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER//wx: enable compile cfi_flash.o
//#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS {0xffff}
#define CONFIG_SYS_FLASH_LEGACY_1024Kx16 //(1M x 16bit = 2M byte)
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }/*wx:comment this will be a member list,_as the return of_cfi_flash_bank_addr*/
/* If use SST39VF1601, operator mode is block and sector, when use sector mode,
* and 1 sector=2K word = 4K byte, so the sector is (2M / 4K) = 512
* If use S29AL016, has 35 sectors (spec:P20),and 64Kbytes per sector.
*/
#define CONFIG_SYS_MAX_FLASH_SECT (35) //wx:replace:(19)
#if defined (CONFIG_NAND_BOOT)
#define CONFIG_ENV_IS_IN_NAND //CONFIG_ENV_IS_IN_FLASH//
#else
#define CONFIG_ENV_IS_IN_FLASH
#endif
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/*
* Size of malloc() pool
* BZIP2 / LZO / LZMA need a lot of RAM
*/
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_LEN (448 * 1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/*
* NAND configuration
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_S3C2440
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1 //wx: all nand chips count
/*wx:s3c2400 NandFlash controler register base address,for r/w K9F2G08U0B*/
#define CONFIG_SYS_NAND_BASE 0x4E000000
#define CONFIG_S3C2440_NAND_HWECC
#define CONFIG_SYS_NAND_ECCSIZE 2048
#define CONFIG_SYS_NAND_ECCBYTES 4
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#endif
/*
* File system
*/
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
//wx: write nand as yaffs
#define CONFIG_CMD_NAND_YAFFS
#define CONFIG_YAFFS2
#define CONFIG_RBTREE
#define BT_XMK_STR(x) #x
#define BT_MK_STR(x) BT_XMK_STR(x)
#define IMG_UBOOT_PATH "u-boot.bin"
#define IMG_KERNEL_PATH "uImage"
#define IMG_ROOTFS_PATH "rootfs.img"
/**
* NAND Partion Will Create as bellow layout when burn img to nand
* 0 - 4M : boot (here we only use 0-1M, 1M-4M unused)[burn as raw]
* 4M - 8M : kernel(here we only use 4-7M, 7M-8M unused)[burn as raw]
* 8M - ? : fs [burn as fs]
*
*!NOTE:
* [burn as raw] is for u-boot read as raw mode when load the kernel image(u-boot
* not support read nand as yaffs mode[default code])
* [burn as fs] is for kernel mount nand as fs mode when kernel init.(MUST make
* image to fs, and read as fs mode for load image)
* So FrinedlyArm-linux-kernnel nand partition as bellow:
* (refer to the linux-kernel: mach-mini2440.c friendly_arm_default_nand_part[] line282)
*
static struct mtd_partition friendly_arm_default_nand_part[] = {
[0] = {
.name = "uboot+params",
.size = SZ_4M,
.offset = 0,
},
[1] = {
.name = "kernel",
.offset = SZ_4M,
.size = SZ_4M,
},
[2] = {
.name = "rootfs",
.offset = SZ_8M,
.size = 1024 * 1024 * 1024, //
},
[3] = {
.name = "whole_nand",
.offset = 0x00000000,
.size = 1024 * 1024 * 1024, //
}
};
*/
//wx: enable the nand defalut partition manage
#define MTDIDS_DEFAULT "nand0=nandflash0"
//wx: define the defalut nand partion configure,
/** wx: !NOTE:
* MUST make sure the offset of root partition same as the target system(linux-kernel defined)
* Here Skip (params) partition, and need not care about the offset because it be
* included in bootloader partition.
*/
#define MTDPARTS_DEFAULT "mtdparts=nandflash0:4M@0(uboot+params)," \
"4M(kernel_uImage)," \
"-(rootfs)"
//mtdblock0 [0M-1M]/[0M-4M]
#define IMG_UBOOT_OFFSET 0
#define IMG_UBOOT_SIZE 0x100000
//between uboot and kernel
#define IMG_PARAM_OFFSET 0x200000
#define IMG_PARAM_SIZE 0x20000
//mtdblock1 [4M-7M]/[4M-8M]
#define IMG_KERNEL_OFFSET 0x400000
#define IMG_KERNEL_SIZE 0x400000
//mtdblock2 [8M-?]
#define IMG_ROOTFS_OFFSET 0x800000
#if defined(CONFIG_ENV_IS_IN_FLASH)
#define CONFIG_ENV_SIZE (0x10000) // 64*1024
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000 - CONFIG_ENV_SIZE)//wx:norflash: 2M:0
#elif defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_ENV_SIZE (IMG_PARAM_SIZE) // 128*1024, wx: MUST mutiply with Block Size(128K), orelse env will write failed
#define CONFIG_ENV_OFFSET (IMG_PARAM_OFFSET)
#else
#error save environments?
#endif
#define BT_STR_ENV_OFFSET BT_MK_STR(CONFIG_ENV_OFFSET)
#define BT_STR_ENV_SIZE BT_MK_STR(CONFIG_ENV_SIZE)
//==============================================================================
#define BOOT_FROM_NAND_COMMAND \
"nand read " BT_MK_STR(CONFIG_SYS_LOAD_ADDR) " " BT_MK_STR(IMG_KERNEL_OFFSET) " " BT_MK_STR(IMG_KERNEL_SIZE)\
";bootm" " " BT_MK_STR(CONFIG_SYS_LOAD_ADDR)
#define BOOT_FROM_TFTP_COMMAND \
"tftp " BT_MK_STR(CONFIG_SYS_LOAD_ADDR) " " IMG_KERNEL_PATH\
";bootm" " " BT_MK_STR(CONFIG_SYS_LOAD_ADDR)
#define BOOT_FROM_RAMDISK_COMMAND \
"tftp " BT_MK_STR(CONFIG_SYS_LOAD_ADDR) " " IMG_KERNEL_PATH\
";tftp " "0x31000000 " IMG_ROOTFS_PATH\
";bootm" " " BT_MK_STR(CONFIG_SYS_LOAD_ADDR)
//-----------------------------------------------------------------------------
// boot default
#define CONFIG_BOOTCOMMAND BOOT_FROM_TFTP_COMMAND
//==============================================================================
//==============================================================================
//wx: usage: run 'cmdname' on console input line.
#define INSTALL_UBOOT_COMMAND \
"tftp " BT_MK_STR(CONFIG_SYS_LOAD_ADDR) " " IMG_UBOOT_PATH\
";nand erase " BT_MK_STR(IMG_UBOOT_OFFSET) " $filesize"\
";nand write $fileaddr" " " BT_MK_STR(IMG_UBOOT_OFFSET) " $filesize"
#define INSTALL_KERNEL_COMMAND \
"tftp " BT_MK_STR(CONFIG_SYS_LOAD_ADDR) " " IMG_KERNEL_PATH\
";nand erase " BT_MK_STR(IMG_KERNEL_OFFSET) " $filesize"\
";nand write $fileaddr" " " BT_MK_STR(IMG_KERNEL_OFFSET) " $filesize"
#define INSTALL_ROOTFS_COMMAND \
"tftp " BT_MK_STR(CONFIG_SYS_LOAD_ADDR) " "IMG_ROOTFS_PATH\
";nand erase " BT_MK_STR(IMG_ROOTFS_OFFSET) " $filesize"\
";nand write.yaffs $fileaddr " BT_MK_STR(IMG_ROOTFS_OFFSET) " $filesize"
//-----------------------------------------------------------------------------
#define ERASE_PARAM_COMMAND \
"nand erase " BT_MK_STR(IMG_PARAM_OFFSET) " "BT_MK_STR(IMG_PARAM_SIZE)
//-----------------------------------------------------------------------------
/* additions for new relocation code, must be added to all boards */
//wx:comment physical ram start address.(mini2440 sdram use nGCS6)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
// wx:comment: start.s jump to c function use bleow stack address(must init before call c function)
// the GENERATED_GBL_DATA_SIZA(global_data) is create by kbulid tools as in asm-offsets.c
//---------------------------------
//| (4K)=0x30001000
//| +sizeof(struct global_data) = gd
//| =INIT_SP_ADDR | // up is stack, down is system global data
//| +SP_SIZE ?(dymatic size, decide by gd size)
//|--------------------------------
//| boot code
//|------- (nGCS6)=0x30000000
//---------------------------------
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/mini2440.h
|
C
|
gpl3
| 16,390
|
/*
* U-boot - Configuration file for BF538F EZ-Kit Lite board
*/
#ifndef __CONFIG_BF538F_EZKIT_H__
#define __CONFIG_BF538F_EZKIT_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf538-0.4
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 21
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL (0x03F6)
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)
#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | AMBEN_ALL | AMCKEN)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20310300
#define CONFIG_HOSTNAME bf538f-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* an error during compilation remove an object here to get
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* Misc Settings
*/
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf538f-ezkit.h
|
C
|
gpl3
| 3,764
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2010-2011
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com.
* Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* for linking errors see
* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
#ifndef _CONFIG_PORTL2_H
#define _CONFIG_PORTL2_H
/* include common defines/options for all arm based Keymile boards */
#include "km/km_arm.h"
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nKeymile Port-L2"
#define CONFIG_HOSTNAME portl2
#define CONFIG_PORTL2
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
/*
* Note: This is only valid for HW > P1A if you got an outdated P1A
* use KM_ENV_BUS "pca9544a:70:a"
*/
#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
/*
* portl2 has a fixed link to the XMPP backplane
* with 100MB full duplex and autoneg off, for this
* reason we have to change the default settings
*/
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
MVGBE_SET_GMII_SPEED_TO_10_100 |\
MVGBE_SET_MII_SPEED_TO_100)
/*
* portl2 does use the PCIe Port0
*/
#define CONFIG_KIRKWOOD_PCIE_INIT
#endif /* _CONFIG_PORTL2_H */
|
1001-study-uboot
|
include/configs/portl2.h
|
C
|
gpl3
| 2,696
|
/*
* (C) Copyright 2006-2008
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
* Nishanth Menon <nm@ti.com>
*
* Configuration settings for the TI OMAP3430 Zoom MDK board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#define CONFIG_OF_LIBFDT 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#define CONFIG_TWL4030_USB 1
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID 0x0451
#define CONFIG_USBD_PRODUCTID 0x5678
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME "Zoom1"
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* TWL4030
*/
#define CONFIG_TWL4030_POWER 1
#define CONFIG_TWL4030_LED 1
/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET 0x680000
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
/* partition */
/* Environment information */
#define CONFIG_BOOTDELAY 10
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
"console=ttyS2,115200n8\0" \
"mmcdev=0\0" \
"videomode=1024x768@60,vxres=1024,vyres=768\0" \
"videospec=omapfb:vram:2M,vram:4M\0" \
"mmcargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"nandargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mtdblock4 rw " \
"rootfstype=jffs2\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
/* works on */
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_NAND 1
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
#define CONFIG_SYS_CACHELINE_SIZE 64
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap3_zoom1.h
|
C
|
gpl3
| 9,125
|
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Define this to make U-Boot skip low level initialization when loaded
* by initial bootloader. Not required by NAND U-Boot version but IS
* required for a NOR version used to burn the real NOR U-Boot into
* NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
* so it is NOT possible to build a U-Boot with both NAND and NOR routines.
* NOR U-Boot is loaded directly from Flash so it must perform all the
* low level initialization itself. NAND version is loaded by an initial
* bootloader (UBL in TI-ese) that performs such an initialization so it's
* skipped in NAND version. The third DaVinci boot mode loads a bootloader
* via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
* performing low level init prior to loading. All that means we can NOT use
* NAND version to put U-Boot into NOR because it doesn't have NOR support and
* we can NOT use NOR version because it performs low level initialization
* effectively destroying itself in DDR memory. That's why a separate NOR
* version with this define is needed. It is loaded via UART, then one uses
* it to somehow download a proper NOR version built WITHOUT this define to
* RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
* NOR support into the initial bootloader so it won't be needed but DaVinci
* static RAM might be too small for this (I have something like 2Kbytes left
* as of now, without NOR support) so this might've not happened...
*
#define CONFIG_NOR_UART_BOOT
*/
/*=======*/
/* Board */
/*=======*/
#define DV_EVM
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NAND
#define CONFIG_DISPLAY_CPUINFO
/*===================*/
/* SoC Configuration */
/*===================*/
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM644X
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
/*====================================================*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/*=============*/
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x10000000 /* DDR size 256MB */
#define DDR_8BANKS /* 8-bank DDR2 (256MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*===================*/
/* I2C Configuration */
/*===================*/
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/*=====================*/
/* Flash & Environment */
/*=====================*/
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#ifdef CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT \
"nand0=davinci_nand.0"
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)"
#else
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#else
#undef CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ 0x10000 /* 64KB sect size AMD Flash */
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*3)
#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_MUSB_HCD
#define CONFIG_USB_DAVINCI
/*===================*/
/* Linux Information */
/*===================*/
#define LINUX_BOOT_PARAM_ADDR 0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "mem=120M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2050000"
/*=================*/
/* U-Boot commands */
/*=================*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#ifdef CONFIG_SYS_USE_NAND
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#elif defined(CONFIG_SYS_USE_NOR)
#define CONFIG_CMD_JFFS2
#else
#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
#endif
/*==========================*/
/* USB MSC support (if any) */
/*==========================*/
#ifdef CONFIG_USB_DAVINCI
#define CONFIG_CMD_USB
#ifdef CONFIG_MUSB_HCD
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_STORAGE
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif
#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#endif
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/davinci_dvevm.h
|
C
|
gpl3
| 9,574
|
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _M5253EVBE_H
#define _M5253EVBE_H
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5253 /* define processor type */
#define CONFIG_M5253EVBE /* define board type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
#define CONFIG_BOOTDELAY 5
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
#else
#define CONFIG_ENV_ADDR 0xffe04000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
#endif
/*
* BOOTP options
*/
#undef CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_BOOTP_BOOTPATH
#undef CONFIG_BOOTP_GATEWAY
#undef CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_NET
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
/* ATA */
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_IDE_RESET 1
#define CONFIG_IDE_PREINIT 1
#define CONFIG_ATAPI
#undef CONFIG_LBA48
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 2
#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
#define CONFIG_SYS_ATA_IDE0_OFFSET 0
#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_HZ 1000
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
# define CONFIG_SYS_PLLCR 0x1243E054
# define CONFIG_SYS_CLK 140000000
#else
# define CONFIG_SYS_PLLCR 0x135a4140
# define CONFIG_SYS_CLK 70000000
#endif
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE 0x20000
#else
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_MONITOR_LEN 0x40000
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_SIZE 0x200000
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(2) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
/* Port configuration */
#define CONFIG_SYS_FECI2C 0xF0
#define CONFIG_SYS_CS0_BASE 0xFFE00000
#define CONFIG_SYS_CS0_MASK 0x001F0021
#define CONFIG_SYS_CS0_CTRL 0x00001D80
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* _M5253EVB_H */
|
1001-study-uboot
|
include/configs/M5253EVBE.h
|
C
|
gpl3
| 7,063
|
/*
* U-boot - Configuration file for BF548 STAMP board
*/
#ifndef __CONFIG_BF548_EZKIT_H__
#define __CONFIG_BF548_EZKIT_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf548-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 21
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
/* Default EZ-Kit bank mapping:
* Async Bank 0 - 32MB Burst Flash
* Async Bank 1 - Ethernet
* Async Bank 2 - Nothing
* Async Bank 3 - Nothing
*/
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0x24000000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME bf548-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_SIZE 0x20000
#else
/* The BF548-EZKIT uses a top boot flash */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE 0x8000
#endif
/*
* NAND Settings
*/
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
# define CONFIG_BFIN_NFC_BOOTROM_ECC
#endif
#define CONFIG_DRIVER_NAND_BFIN
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* SATA
*/
#if !defined(__ADSPBF544__)
#define CONFIG_LIBATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
#define CONFIG_PATA_BFIN
#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800
#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
#endif
/*
* SDH Settings
*/
#if !defined(__ADSPBF544__)
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_BFIN_SDH
#endif
/*
* USB Settings
*/
#if !defined(__ADSPBF544__)
#define CONFIG_USB
#define CONFIG_MUSB_HCD
#define CONFIG_USB_BLACKFIN
#define CONFIG_USB_STORAGE
#define CONFIG_MUSB_TIMEOUT 100000
#endif
/*
* Misc Settings
*/
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
#ifndef __ADSPBF542__
/* Don't waste time transferring a logo over the UART */
# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
# define CONFIG_VIDEO
# endif
# define CONFIG_DEB_DMA_URGENT
#endif
/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
#define CONFIG_POST_BSPEC1_GPIO_LEDS \
GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
#define CONFIG_POST_BSPEC2_GPIO_NAMES \
13, 12, 11, 10,
#define CONFIG_SYS_POST_FLASH_START 10
#define CONFIG_SYS_POST_FLASH_END 127
#endif
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf548-ezkit.h
|
C
|
gpl3
| 5,157
|
/*
* U-boot - Configuration file for SSV DNP5370 board
*/
#ifndef __CONFIG_DNP5370_H__
#define __CONFIG_DNP5370_H__
/* this must come first */
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
#define CONFIG_CLKIN_HZ 25000000
#define CONFIG_CLKIN_HALF 0
#define CONFIG_PLL_BYPASS 0
#define CONFIG_VCO_MULT 24
#define CONFIG_CCLK_DIV 1
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
#define CONFIG_EBIU_SDRRC_VAL 0x03a0
#define CONFIG_EBIU_SDBCTL_VAL 0x0013
#define CONFIG_EBIU_SDGCTL_VAL 0x8091998d
#define CONFIG_EBIU_AMGCTL_VAL 0xF7
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#ifndef __ADSPBF534__
#define CONFIG_ROOTPATH "/romfs"
#define CONFIG_BFIN_MAC 1
#define CONFIG_PHY_ADDR 0
#define CONFIG_RMII 1
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#endif
/*
* Flash Settings
*
* Only 3 MB of the 4 MB NOR flash are addressable.
* But limiting the flash size does not seem to work.
* It seems the CFI detection has precedence.
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* (M29W320EB) */
/* 512k reserved for u-boot */
#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x20004000
#define CONFIG_ENV_SIZE 0x00002000
#define CONFIG_ENV_SECT_SIZE 0x00002000 /* Total Size of Environment Sector */
#define CONFIG_ENV_OFFSET 0x00004000 /* (CONFIG_ENV_ADDR - CONFIG_FLASH_BASE) */
#define ENV_IS_EMBEDDED
#define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
/*
* Misc Settings
*/
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_STRINGS
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_SYS_LONGHELP
/* This disables the hardware watchdog (not inside the bfin) */
#define CONFIG_DNP5370_EXT_WD_DISABLE 1
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTCOMMAND "bootm 0x20030000"
#define CONFIG_BOOTARGS "console=ttyBF0,115200 root=/dev/mtdblock3 rootfstype=ext2"
/* Convenience commands to update Linux in NOR flash */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fetchme=tftpboot 0x01000000 uImage;" \
"iminfo\0" \
"flashme=protect off 0x20030000 0x2003ffff;" \
"erase 0x20030000 0x202effff;" \
"cp.b 0x01000000 0x20030000 0x2c0000\0" \
"runme=bootm 0x01000000\0"
/* this sets up the default list of enabled commands */
#include <config_cmd_default.h>
#ifndef CONFIG_BFIN_MAC
# undef CONFIG_CMD_NET
# undef CONFIG_CMD_NFS
#endif
#endif
|
1001-study-uboot
|
include/configs/dnp5370.h
|
C
|
gpl3
| 3,306
|
/*
* (C) Copyright 2010
* ISEE 2007 SL, <www.iseebcn.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#define CONFIG_OF_LIBFDT 1
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/* select serial console configuration */
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR */
#define CONFIG_OMAP3_NUMONYX_DDR 1
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#define CONFIG_TWL4030_USB 1
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID 0x0451
#define CONFIG_USBD_PRODUCTID 0x5678
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME "IGEP"
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_ONENAND /* ONENAND support */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
#define CONFIG_MTD_DEVICE
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* TWL4030
*/
#define CONFIG_TWL4030_POWER 1
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
"console=ttyS2,115200n8\0" \
"mpurate=500\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"nandrootfstype=jffs2\0" \
"mmcargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapfb.debug=y " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"nandargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapfb.debug=y " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from onenand ...; " \
"run nandargs; " \
"onenand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "U-Boot # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
/* works on */
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
/*
* Physical Memory Map
*
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*
* FLASH and environment organization
*/
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* SMSC911x Ethernet
*/
#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/igep0020.h
|
C
|
gpl3
| 7,866
|
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
#include "tegra2-common.h"
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (Harmony) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Harmony"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA2_ENABLE_UARTD
/* UARTD: keyboard satellite board UART, default */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#ifdef CONFIG_TEGRA2_ENABLE_UARTA
/* UARTA: debug board UART */
#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/harmony.h
|
C
|
gpl3
| 1,868
|
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/hardware.h>
#define CONFIG_AT91_LEGACY
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91SAM9M10G45EK
#define CONFIG_AT91FAMILY
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
/* serial console */
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
/*
* This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files.
*/
#define ATMEL_ID_UHP ATMEL_ID_UHPHS
/*
* Specify the clock enable bit in the PMC_SCER register.
*/
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
/* LCD */
#define CONFIG_LCD
#define LCD_BPP LCD_COLOR8
#define CONFIG_LCD_LOGO
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_ATMEL_LCD
#define CONFIG_ATMEL_LCD_RGB565
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* board specific(not enough SRAM) */
#define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
/* LED */
#define CONFIG_AT91_LED
#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */
#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */
#define CONFIG_BOOTDELAY 3
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NAND
#define CONFIG_CMD_USB
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
/* No NOR flash */
#define CONFIG_SYS_NO_FLASH
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_MAX_CHIPS 1
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
#endif
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R
/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_HCI
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
/* bootstrap + u-boot + env in nandflash */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_BOOTCOMMAND "nand read 0x70000000 0x100000 0x200000;" \
"bootm 0x70000000"
#define CONFIG_BOOTARGS \
"console=ttyS0,115200 earlyprintk " \
"root=/dev/mtdblock5 " \
"mtdparts=atmel_nand:128k(bootstrap)ro," \
"256k(uboot)ro,128k(env1)ro,128k(env2)ro," \
"2M@1M(linux),-(root) " \
"rw rootfstype=jffs2"
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif
#endif
|
1001-study-uboot
|
include/configs/at91sam9m10g45ek.h
|
C
|
gpl3
| 5,878
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Siddarth Gore <gores@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_GURUPLUG_H
#define _CONFIG_GURUPLUG_H
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nMarvell-GuruPlug"
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_GURUPLUG /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_IDE
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
#define CONFIG_ENV_ADDR 0x60000
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
"${x_bootcmd_ethernet}; setenv ethact egiga1; " \
"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"bootm 0x6400000;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"x_bootcmd_ethernet=ping 192.168.2.1\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \
"x_bootargs=console=ttyS0,115200\0" \
"x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
#endif /* CONFIG_CMD_NET */
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
#define CONFIG_SYS_ALT_MEMTEST
#endif /* _CONFIG_GURUPLUG_H */
|
1001-study-uboot
|
include/configs/guruplug.h
|
C
|
gpl3
| 3,223
|
/*
* (C) Copyright 2009
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MANROLAND_COMMON_H
#define __MANROLAND_COMMON_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_BOARD_EARLY_INIT_R
/* Partitions */
#define CONFIG_DOS_PARTITION
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DISPLAY
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_DTT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NFS
#define CONFIG_CMD_MII
#define CONFIG_CMD_SNTP
/*
* 8-symbol LED display (can be accessed with 'display' command)
*/
#define CONFIG_PDSP188x
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
/*
* Autobooting
*/
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS
#define xstr(s) str(s)
#define str(s) #s
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addwdt=setenv bootargs ${bootargs} wdt=off\0" \
"logval=4\0" \
"addlog=setenv bootargs ${bootargs} loglevel=${logval}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"kernel_addr=ff810000\0" \
"fdt_addr="xstr(CONFIG_SYS_FLASH_BASE)"\0" \
"flash_nfs=run nfsargs addip addcon addwdt addlog;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"kernel_addr_r=300000\0" \
"fdt_addr_r=200000\0" \
"fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
xstr(CONFIG_HOSTNAME) ".dtb\0" \
"kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
"load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \
"load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \
"addcon=setenv bootargs ${bootargs} console=ttyPSC0,${baudrate}\0"\
"net_nfs=run load_fdt load_kernel; " \
"run nfsargs addip addcon addwdt addlog;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \
"u-boot_addr_r=200000\0" \
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
"update=protect off " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize};" \
"erase " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize};" \
"cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_TEXT_BASE) \
" ${filesize};" \
"protect on " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize}\0" \
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_MISC_INIT_R 1
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
/* Enable an alternate, more extensive memory test */
#define CONFIG_SYS_ALT_MEMTEST
/*
* Enable loopw command.
*/
#define CONFIG_LOOPW
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#endif /* __MANROLAND_COMMON_H */
|
1001-study-uboot
|
include/configs/manroland/common.h
|
C
|
gpl3
| 4,495
|
/*
* (C) Copyright 2009
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MANROLAND_MPC52XX__COMMON_H
#define __MANROLAND_MPC52XX__COMMON_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/*
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\
230400 }
#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
# define CONFIG_SYS_LOWBOOT 1
#endif
/*
* IPB Bus clocking configuration.
*/
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR 0x51
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
/*
* Flash configuration
*/
#define CONFIG_SYS_FLASH_BASE 0xFF800000
#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
/*
* Environment settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
/*
* Memory map
*/
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */
#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */
/* Settings for XLB = 132 MHz */
#define SDRAM_DDR 1
#define SDRAM_MODE 0x018D0000
#define SDRAM_EMODE 0x40090000
#define SDRAM_CONTROL 0x714f0f00
#define SDRAM_CONFIG1 0x73722930
#define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000
/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
#else
#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
#endif
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
# define CONFIG_SYS_RAMBOOT 1
#endif
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
/*
* Ethernet configuration
*/
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR 0x00
#define CONFIG_MII 1
/*use Hardware WDT */
#define CONFIG_HW_WATCHDOG
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
#endif
/*
* Various low-level settings
*/
#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL HID0_ICE
#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
/* 8Mbit SRAM @0x80100000 */
#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
#define CONFIG_SYS_CS_BURST 0x00000000
#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CONFIG_IDE_PREINIT 1
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE 4
#define CONFIG_ATAPI 1
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
#define CONFIG_OF_IDE_FIXUP
#endif /* __MANROLAND_MPC52XX__COMMON_H */
|
1001-study-uboot
|
include/configs/manroland/mpc5200-common.h
|
C
|
gpl3
| 6,611
|
/*
*
* BRIEF MODULE DESCRIPTION
* OMAP hardware map
*
* Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
* Author: RidgeRun, Inc.
* Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/sizes.h>
/*
There are 2 sets of general I/O -->
1. GPIO (shared between ARM & DSP, configured by ARM)
2. MPUIO which can be used only by the ARM.
Base address FFFB:5000 is where the ARM accesses the MPUIO control registers
(see 7.2.2 of the TRM for MPUIO reg definitions).
Base address E101:5000 is reserved for ARM access of the same MPUIO control
regs, but via the DSP I/O map. This address is unavailable on 1510.
Base address FFFC:E000 is where the ARM accesses the GPIO config registers
directly via its own peripheral bus.
Base address E101:E000 is where the ARM can access the same GPIO config
registers, but the access takes place through the ARM port interface (called
API or MPUI) via the DSP's peripheral bus (DSP I/O space).
Therefore, the ARM should setup the GPIO regs thru the FFFC:E000 addresses
instead of the E101:E000 addresses. The DSP has only read access of the pin
control register, so this may explain the inability to write to E101:E018.
Try accessing pin control reg at FFFC:E018.
*/
#define OMAP1510_GPIO_BASE 0xfffce000
#define OMAP1510_GPIO_START OMAP1510_GPIO_BASE
#define OMAP1510_GPIO_SIZE SZ_4K
#define OMAP1510_MCBSP1_BASE 0xE1011000
#define OMAP1510_MCBSP1_SIZE SZ_4K
#define OMAP1510_MCBSP1_START 0xE1011000
#define OMAP1510_MCBSP2_BASE 0xFFFB1000
#define OMAP1510_MCBSP3_BASE 0xE1017000
#define OMAP1510_MCBSP3_SIZE SZ_4K
#define OMAP1510_MCBSP3_START 0xE1017000
/*
* Where's the flush address (for flushing D and I cache?)
*/
#define FLUSH_BASE 0xdf000000
#define FLUSH_BASE_PHYS 0x00000000
#ifndef __ASSEMBLER__
#define PCIO_BASE 0
/*
* RAM definitions
*/
#define MAPTOPHYS(a) ((unsigned long)(a) - PAGE_OFFSET)
#define KERNTOPHYS(a) ((unsigned long)(&a))
#define KERNEL_BASE (0x10008000)
#endif
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) ((x))
/* ----------------------------------------------------------------------------
* OMAP1510 system registers
* ----------------------------------------------------------------------------
*/
#define OMAP1510_UART1_BASE 0xfffb0000 /* "BLUETOOTH-UART" */
#define OMAP1510_UART2_BASE 0xfffb0800 /* "MODEM-UART" */
#define OMAP1510_RTC_BASE 0xfffb4800 /* RTC */
#define OMAP1510_UART3_BASE 0xfffb9800 /* Shared MPU/DSP UART */
#define OMAP1510_COM_MCBSP2_BASE 0xffff1000 /* Com McBSP2 */
#define OMAP1510_AUDIO_MCBSP_BASE 0xffff1800 /* Audio McBSP2 */
#define OMAP1510_ARMIO_BASE 0xfffb5000 /* keyboard/gpio */
/*
* OMAP1510 UART3 Registers
*/
#define OMAP_MPU_UART3_BASE 0xFFFB9800 /* UART3 through MPU bus */
/* UART3 Registers Maping through MPU bus */
#define UART3_RHR (OMAP_MPU_UART3_BASE + 0)
#define UART3_THR (OMAP_MPU_UART3_BASE + 0)
#define UART3_DLL (OMAP_MPU_UART3_BASE + 0)
#define UART3_IER (OMAP_MPU_UART3_BASE + 4)
#define UART3_DLH (OMAP_MPU_UART3_BASE + 4)
#define UART3_IIR (OMAP_MPU_UART3_BASE + 8)
#define UART3_FCR (OMAP_MPU_UART3_BASE + 8)
#define UART3_EFR (OMAP_MPU_UART3_BASE + 8)
#define UART3_LCR (OMAP_MPU_UART3_BASE + 0x0C)
#define UART3_MCR (OMAP_MPU_UART3_BASE + 0x10)
#define UART3_XON1_ADDR1 (OMAP_MPU_UART3_BASE + 0x10)
#define UART3_XON2_ADDR2 (OMAP_MPU_UART3_BASE + 0x14)
#define UART3_LSR (OMAP_MPU_UART3_BASE + 0x14)
#define UART3_TCR (OMAP_MPU_UART3_BASE + 0x18)
#define UART3_MSR (OMAP_MPU_UART3_BASE + 0x18)
#define UART3_XOFF1 (OMAP_MPU_UART3_BASE + 0x18)
#define UART3_XOFF2 (OMAP_MPU_UART3_BASE + 0x1C)
#define UART3_SPR (OMAP_MPU_UART3_BASE + 0x1C)
#define UART3_TLR (OMAP_MPU_UART3_BASE + 0x1C)
#define UART3_MDR1 (OMAP_MPU_UART3_BASE + 0x20)
#define UART3_MDR2 (OMAP_MPU_UART3_BASE + 0x24)
#define UART3_SFLSR (OMAP_MPU_UART3_BASE + 0x28)
#define UART3_TXFLL (OMAP_MPU_UART3_BASE + 0x28)
#define UART3_RESUME (OMAP_MPU_UART3_BASE + 0x2C)
#define UART3_TXFLH (OMAP_MPU_UART3_BASE + 0x2C)
#define UART3_SFREGL (OMAP_MPU_UART3_BASE + 0x30)
#define UART3_RXFLL (OMAP_MPU_UART3_BASE + 0x30)
#define UART3_SFREGH (OMAP_MPU_UART3_BASE + 0x34)
#define UART3_RXFLH (OMAP_MPU_UART3_BASE + 0x34)
#define UART3_BLR (OMAP_MPU_UART3_BASE + 0x38)
#define UART3_ACREG (OMAP_MPU_UART3_BASE + 0x3C)
#define UART3_DIV16 (OMAP_MPU_UART3_BASE + 0x3C)
#define UART3_SCR (OMAP_MPU_UART3_BASE + 0x40)
#define UART3_SSR (OMAP_MPU_UART3_BASE + 0x44)
#define UART3_EBLR (OMAP_MPU_UART3_BASE + 0x48)
#define UART3_OSC_12M_SEL (OMAP_MPU_UART3_BASE + 0x4C)
#define UART3_MVR (OMAP_MPU_UART3_BASE + 0x50)
/*
* Configuration Registers
*/
#define FUNC_MUX_CTRL_0 0xfffe1000
#define FUNC_MUX_CTRL_1 0xfffe1004
#define FUNC_MUX_CTRL_2 0xfffe1008
#define COMP_MODE_CTRL_0 0xfffe100c
#define FUNC_MUX_CTRL_3 0xfffe1010
#define FUNC_MUX_CTRL_4 0xfffe1014
#define FUNC_MUX_CTRL_5 0xfffe1018
#define FUNC_MUX_CTRL_6 0xfffe101C
#define FUNC_MUX_CTRL_7 0xfffe1020
#define FUNC_MUX_CTRL_8 0xfffe1024
#define FUNC_MUX_CTRL_9 0xfffe1028
#define FUNC_MUX_CTRL_A 0xfffe102C
#define FUNC_MUX_CTRL_B 0xfffe1030
#define FUNC_MUX_CTRL_C 0xfffe1034
#define FUNC_MUX_CTRL_D 0xfffe1038
#define PULL_DWN_CTRL_0 0xfffe1040
#define PULL_DWN_CTRL_1 0xfffe1044
#define PULL_DWN_CTRL_2 0xfffe1048
#define PULL_DWN_CTRL_3 0xfffe104c
#define GATE_INH_CTRL_0 0xfffe1050
#define VOLTAGE_CTRL_0 0xfffe1060
#define TEST_DBG_CTRL_0 0xfffe1070
#define MOD_CONF_CTRL_0 0xfffe1080
#ifdef CONFIG_OMAP1610 /* 1610 Configuration Register */
#define USB_OTG_CTRL 0xFFFB040C
#define USB_TRANSCEIVER_CTRL 0xFFFE1064
#define PULL_DWN_CTRL_4 0xFFFE10AC
#define PU_PD_SEL_0 0xFFFE10B4
#define PU_PD_SEL_1 0xFFFE10B8
#define PU_PD_SEL_2 0xFFFE10BC
#define PU_PD_SEL_3 0xFFFE10C0
#define PU_PD_SEL_4 0xFFFE10C4
#endif
/*
* Traffic Controller Memory Interface Registers
*/
#define TCMIF_BASE 0xfffecc00
#define IMIF_PRIO (TCMIF_BASE + 0x00)
#define EMIFS_PRIO_REG (TCMIF_BASE + 0x04)
#define EMIFF_PRIO_REG (TCMIF_BASE + 0x08)
#define EMIFS_CONFIG_REG (TCMIF_BASE + 0x0c)
#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
#define EMIFF_MRS (TCMIF_BASE + 0x24)
#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
#define TC_ENDIANISM (TCMIF_BASE + 0x34)
#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
/*
* LCD Panel
*/
#define TI925_LCD_BASE 0xFFFEC000
#define TI925_LCD_CONTROL (TI925_LCD_BASE)
#define TI925_LCD_TIMING0 (TI925_LCD_BASE+0x4)
#define TI925_LCD_TIMING1 (TI925_LCD_BASE+0x8)
#define TI925_LCD_TIMING2 (TI925_LCD_BASE+0xc)
#define TI925_LCD_STATUS (TI925_LCD_BASE+0x10)
#define TI925_LCD_SUBPANEL (TI925_LCD_BASE+0x14)
#define OMAP_LCD_CONTROL TI925_LCD_CONTROL
/* I2C Registers */
#define I2C_BASE 0xfffb3800
#define I2C_REV (I2C_BASE + 0x00)
#define I2C_IE (I2C_BASE + 0x04)
#define I2C_STAT (I2C_BASE + 0x08)
#define I2C_IV (I2C_BASE + 0x0c)
#define I2C_BUF (I2C_BASE + 0x14)
#define I2C_CNT (I2C_BASE + 0x18)
#define I2C_DATA (I2C_BASE + 0x1c)
#define I2C_CON (I2C_BASE + 0x24)
#define I2C_OA (I2C_BASE + 0x28)
#define I2C_SA (I2C_BASE + 0x2c)
#define I2C_PSC (I2C_BASE + 0x30)
#define I2C_SCLL (I2C_BASE + 0x34)
#define I2C_SCLH (I2C_BASE + 0x38)
#define I2C_SYSTEST (I2C_BASE + 0x3c)
/* I2C masks */
/* I2C Interrupt Enable Register (I2C_IE): */
#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
/* I2C Status Register (I2C_STAT): */
#define I2C_STAT_SBD (1 << 15) /* Single byte data */
#define I2C_STAT_BB (1 << 12) /* Bus busy */
#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
#define I2C_STAT_AAS (1 << 9) /* Address as slave */
#define I2C_STAT_AD0 (1 << 8) /* Address zero */
#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
/* I2C Interrupt Vector Register (I2C_IV): */
/* I2C Interrupt Code Register (I2C_INTCODE): */
#define I2C_INTCODE_MASK 7
#define I2C_INTCODE_NONE 0
#define I2C_INTCODE_AL 1 /* Arbitration lost */
#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
#define I2C_INTCODE_ARDY 3 /* Register access ready */
#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
/* I2C Buffer Configuration Register (I2C_BUF): */
#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */
#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */
/* I2C Configuration Register (I2C_CON): */
#define I2C_CON_EN (1 << 15) /* I2C module enable */
#define I2C_CON_BE (1 << 14) /* Big endian mode */
#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
#define I2C_CON_MST (1 << 10) /* Master/slave mode */
#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
#define I2C_CON_XA (1 << 8) /* Expand address */
#define I2C_CON_RM (1 << 2) /* Repeat mode (master mode only) */
#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
/* I2C System Test Register (I2C_SYSTEST): */
#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */
#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */
#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */
#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */
#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */
/*
* MMC/SD Host Controller Registers
*/
#define OMAP_MMC_CMD 0xFFFB7800 /* MMC Command */
#define OMAP_MMC_ARGL 0xFFFB7804 /* MMC argument low */
#define OMAP_MMC_ARGH 0xFFFB7808 /* MMC argument high */
#define OMAP_MMC_CON 0xFFFB780C /* MMC system configuration */
#define OMAP_MMC_STAT 0xFFFB7810 /* MMC status */
#define OMAP_MMC_IE 0xFFFB7814 /* MMC system interrupt enable */
#define OMAP_MMC_CTO 0xFFFB7818 /* MMC command time-out */
#define OMAP_MMC_DTO 0xFFFB781C /* MMC data time-out */
#define OMAP_MMC_DATA 0xFFFB7820 /* MMC TX/RX FIFO data */
#define OMAP_MMC_BLEN 0xFFFB7824 /* MMC block length */
#define OMAP_MMC_NBLK 0xFFFB7828 /* MMC number of blocks */
#define OMAP_MMC_BUF 0xFFFB782C /* MMC buffer configuration */
#define OMAP_MMC_SPI 0xFFFB7830 /* MMC serial port interface */
#define OMAP_MMC_SDIO 0xFFFB7834 /* MMC SDIO mode configuration */
#define OMAP_MMC_SYST 0xFFFB7838 /* MMC system test */
#define OMAP_MMC_REV 0xFFFB783C /* MMC module version */
#define OMAP_MMC_RSP0 0xFFFB7840 /* MMC command response 0 */
#define OMAP_MMC_RSP1 0xFFFB7844 /* MMC command response 1 */
#define OMAP_MMC_RSP2 0xFFFB7848 /* MMC command response 2 */
#define OMAP_MMC_RSP3 0xFFFB784C /* MMC command response 3 */
#define OMAP_MMC_RSP4 0xFFFB7850 /* MMC command response 4 */
#define OMAP_MMC_RSP5 0xFFFB7854 /* MMC command response 5 */
#define OMAP_MMC_RSP6 0xFFFB7858 /* MMC command response 6 */
#define OMAP_MMC_RSP7 0xFFFB785C /* MMC command response 4 */
/* MMC masks */
#define OMAP_MMC_END_OF_CMD (1 << 0) /* End of command phase */
#define OMAP_MMC_CARD_BUSY (1 << 2) /* Card enter busy state */
#define OMAP_MMC_BLOCK_RS (1 << 3) /* Block received/sent */
#define OMAP_MMC_EOF_BUSY (1 << 4) /* Card exit busy state */
#define OMAP_MMC_DATA_TIMEOUT (1 << 5) /* Data response time-out */
#define OMAP_MMC_DATA_CRC (1 << 6) /* Date CRC error */
#define OMAP_MMC_CMD_TIMEOUT (1 << 7) /* Command response time-out */
#define OMAP_MMC_CMD_CRC (1 << 8) /* Command CRC error */
#define OMAP_MMC_A_FULL (1 << 10) /* Buffer almost full */
#define OMAP_MMC_A_EMPTY (1 << 11) /* Buffer almost empty */
#define OMAP_MMC_OCR_BUSY (1 << 12) /* OCR busy */
#define OMAP_MMC_CARD_IRQ (1 << 13) /* Card IRQ received */
#define OMAP_MMC_CARD_ERR (1 << 14) /* Card status error in response */
/* 2.9.2 MPUI Interface Registers FFFE:C900 */
#define MPUI_CTRL_REG (volatile __u32 *)(0xfffec900)
#define MPUI_DEBUG_ADDR (volatile __u32 *)(0xfffec904)
#define MPUI_DEBUG_DATA (volatile __u32 *)(0xfffec908)
#define MPUI_DEBUG_FLAG (volatile __u16 *)(0xfffec90c)
#define MPUI_STATUS_REG (volatile __u16 *)(0xfffec910)
#define MPUI_DSP_STATUS_REG (volatile __u16 *)(0xfffec914)
#define MPUI_DSP_BOOT_CONFIG (volatile __u16 *)(0xfffec918)
#define MPUI_DSP_API_CONFIG (volatile __u16 *)(0xfffec91c)
/* 2.9.6 Traffic Controller Memory Interface Registers: */
#define OMAP_IMIF_PRIO_REG 0xfffecc00
#define OMAP_EMIFS_PRIO_REG 0xfffecc04
#define OMAP_EMIFF_PRIO_REG 0xfffecc08
#define OMAP_EMIFS_CONFIG_REG 0xfffecc0c
#define OMAP_EMIFS_CS0_CONFIG 0xfffecc10
#define OMAP_EMIFS_CS1_CONFIG 0xfffecc14
#define OMAP_EMIFS_CS2_CONFIG 0xfffecc18
#define OMAP_EMIFS_CS3_CONFIG 0xfffecc1c
#define OMAP_EMIFF_SDRAM_CONFIG 0xfffecc20
#define OMAP_EMIFF_MRS 0xfffecc24
#define OMAP_TIMEOUT1 0xfffecc28
#define OMAP_TIMEOUT2 0xfffecc2c
#define OMAP_TIMEOUT3 0xfffecc30
#define OMAP_ENDIANISM 0xfffecc34
/* 2.9.10 EMIF Slow Interface Configuration Register (EMIFS_CONFIG_REG): */
#define OMAP_EMIFS_CONFIG_FR (1 << 4)
#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
#define OMAP_EMIFS_CONFIG_BM (1 << 1)
#define OMAP_EMIFS_CONFIG_WP (1 << 0)
/*
* Memory chunk set aside for the Framebuffer in SRAM
*/
#define SRAM_FRAMEBUFFER_MEMORY OMAP1510_SRAM_BASE
/*
* DMA
*/
#define OMAP1510_DMA_BASE 0xFFFED800
#define OMAP_DMA_BASE OMAP1510_DMA_BASE
/* Global Register selection */
#define NO_GLOBAL_DMA_ACCESS 0
/* Channel select field
* NOTE: all other channels are linear, chan0 is 0, chan1 is 1, etc...
*/
#define LCD_CHANNEL 0xc
/* Register Select Field (LCD) */
#define DMA_LCD_CTRL 0
#define DMA_LCD_TOP_F1_L 1
#define DMA_LCD_TOP_F1_U 2
#define DMA_LCD_BOT_F1_L 3
#define DMA_LCD_BOT_F1_U 4
#define LCD_FRAME_MODE (1<<0)
#define LCD_FRAME_IT_IE (1<<1)
#define LCD_BUS_ERROR_IT_IE (1<<2)
#define LCD_FRAME_1_IT_COND (1<<3)
#define LCD_FRAME_2_IT_COND (1<<4)
#define LCD_BUS_ERROR_IT_COND (1<<5)
#define LCD_SOURCE_IMIF (1<<6)
/*
* Real-Time Clock
*/
#define RTC_SECONDS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x00)
#define RTC_MINUTES (volatile __u8 *)(OMAP1510_RTC_BASE + 0x04)
#define RTC_HOURS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x08)
#define RTC_DAYS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x0C)
#define RTC_MONTHS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x10)
#define RTC_YEARS (volatile __u8 *)(OMAP1510_RTC_BASE + 0x14)
#define RTC_CTRL (volatile __u8 *)(OMAP1510_RTC_BASE + 0x40)
/* ---------------------------------------------------------------------------
* OMAP1510 Interrupt Handlers
* ---------------------------------------------------------------------------
*
*/
#define OMAP_IH1_BASE 0xfffecb00
#define OMAP_IH2_BASE 0xfffe0000
#define OMAP1510_ITR 0x0
#define OMAP1510_MASK 0x4
#define INTERRUPT_HANDLER_BASE OMAP_IH1_BASE
#define INTERRUPT_INPUT_REGISTER OMAP1510_ITR
#define INTERRUPT_MASK_REGISTER OMAP1510_MASK
/* ---------------------------------------------------------------------------
* OMAP1510 TIMERS
* ---------------------------------------------------------------------------
*
*/
#define OMAP1510_32kHz_TIMER_BASE 0xfffb9000
/* 32k Timer Registers */
#define TIMER32k_CR 0x08
#define TIMER32k_TVR 0x00
#define TIMER32k_TCR 0x04
/* 32k Timer Control Register definition */
#define TIMER32k_TSS (1<<0)
#define TIMER32k_TRB (1<<1)
#define TIMER32k_INT (1<<2)
#define TIMER32k_ARL (1<<3)
/* MPU Timer base addresses */
#define OMAP1510_MPUTIMER_BASE 0xfffec500
#define OMAP1510_MPUTIMER_OFF 0x00000100
#define OMAP1510_TIMER1_BASE 0xfffec500
#define OMAP1510_TIMER2_BASE 0xfffec600
#define OMAP1510_TIMER3_BASE 0xfffec700
/* MPU Timer Registers */
#define CNTL_TIMER 0
#define LOAD_TIM 4
#define READ_TIM 8
/* CNTL_TIMER register bits */
#define MPUTIM_FREE (1<<6)
#define MPUTIM_CLOCK_ENABLE (1<<5)
#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT)
#define MPUTIM_PTV_BIT 2
#define MPUTIM_AR (1<<1)
#define MPUTIM_ST (1<<0)
/* ---------------------------------------------------------------------------
* OMAP1510 GPIO (SHARED)
* ---------------------------------------------------------------------------
*
*/
#define GPIO_DATA_INPUT_REG (OMAP1510_GPIO_BASE + 0x0)
#define GPIO_DATA_OUTPUT_REG (OMAP1510_GPIO_BASE + 0x4)
#define GPIO_DIR_CONTROL_REG (OMAP1510_GPIO_BASE + 0x8)
#define GPIO_INT_CONTROL_REG (OMAP1510_GPIO_BASE + 0xc)
#define GPIO_INT_MASK_REG (OMAP1510_GPIO_BASE + 0x10)
#define GPIO_INT_STATUS_REG (OMAP1510_GPIO_BASE + 0x14)
#define GPIO_PIN_CONTROL_REG (OMAP1510_GPIO_BASE + 0x18)
/* ---------------------------
* OMAP1510 MPUIO (ARM only)
*----------------------------
*/
#define OMAP1510_MPUIO_BASE 0xFFFB5000
#define MPUIO_DATA_INPUT_REG (OMAP1510_MPUIO_BASE + 0x0)
#define MPUIO_DATA_OUTPUT_REG (OMAP1510_MPUIO_BASE + 0x4)
#define MPUIO_DIR_CONTROL_REG (OMAP1510_MPUIO_BASE + 0x8)
/* ---------------------------------------------------------------------------
* OMAP1510 TIPB (only)
* ---------------------------------------------------------------------------
*
*/
#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
#define MPU_PUBLIC_TIPB_CNTL_REG (TIPB_PUBLIC_CNTL_BASE + 0x8)
#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
#define MPU_PRIVATE_TIPB_CNTL_REG (TIPB_PRIVATE_CNTL_BASE + 0x8)
/*
* ---------------------------------------------------------------------------
* OMAP1510 Camera Interface
* ---------------------------------------------------------------------------
*/
#define CAMERA_BASE (IO_BASE + 0x6800)
#define CAM_CTRLCLOCK_REG (CAMERA_BASE + 0x00)
#define CAM_IT_STATUS_REG (CAMERA_BASE + 0x04)
#define CAM_MODE_REG (CAMERA_BASE + 0x08)
#define CAM_STATUS_REG (CAMERA_BASE + 0x0C)
#define CAM_CAMDATA_REG (CAMERA_BASE + 0x10)
#define CAM_GPIO_REG (CAMERA_BASE + 0x14)
#define CAM_PEAK_CTR_REG (CAMERA_BASE + 0x18)
#if 0
#ifndef __ASSEMBLY__
typedef struct {
__u32 ctrlclock;
__u32 it_status;
__u32 mode;
__u32 status;
__u32 camdata;
__u32 gpio;
__u32 peak_counter;
} camera_regs_t;
#endif
#endif
/* CTRLCLOCK bit shifts */
#define FOSCMOD_BIT 0
#define FOSCMOD_MASK (0x7 << FOSCMOD_BIT)
#define FOSCMOD_12MHz 0x0
#define FOSCMOD_6MHz 0x2
#define FOSCMOD_9_6MHz 0x4
#define FOSCMOD_24MHz 0x5
#define FOSCMOD_8MHz 0x6
#define POLCLK (1<<3)
#define CAMEXCLK_EN (1<<4)
#define MCLK_EN (1<<5)
#define DPLL_EN (1<<6)
#define LCLK_EN (1<<7)
/* IT_STATUS bit shifts */
#define V_UP (1<<0)
#define V_DOWN (1<<1)
#define H_UP (1<<2)
#define H_DOWN (1<<3)
#define FIFO_FULL (1<<4)
#define DATA_XFER (1<<5)
/* MODE bit shifts */
#define CAMOSC (1<<0)
#define IMGSIZE_BIT 1
#define IMGSIZE_MASK (0x3 << IMGSIZE_BIT)
#define IMGSIZE_CIF (0x0 << IMGSIZE_BIT) /* 352x288 */
#define IMGSIZE_QCIF (0x1 << IMGSIZE_BIT) /* 176x144 */
#define IMGSIZE_VGA (0x2 << IMGSIZE_BIT) /* 640x480 */
#define IMGSIZE_QVGA (0x3 << IMGSIZE_BIT) /* 320x240 */
#define ORDERCAMD (1<<3)
#define EN_V_UP (1<<4)
#define EN_V_DOWN (1<<5)
#define EN_H_UP (1<<6)
#define EN_H_DOWN (1<<7)
#define EN_DMA (1<<8)
#define THRESHOLD (1<<9)
#define THRESHOLD_BIT 9
#define THRESHOLD_MASK (0x7f<<9)
#define EN_NIRQ (1<<16)
#define EN_FIFO_FULL (1<<17)
#define RAZ_FIFO (1<<18)
/* STATUS bit shifts */
#define VSTATUS (1<<0)
#define HSTATUS (1<<1)
/* GPIO bit shifts */
#define CAM_RST (1<<0)
/*********************
* Watchdog timer.
*********************/
#define WDTIM_BASE 0xfffec800
#define WDTIM_CONTROL (WDTIM_BASE+0x00)
#define WDTIM_LOAD (WDTIM_BASE+0x04)
#define WDTIM_READ (WDTIM_BASE+0x04)
#define WDTIM_MODE (WDTIM_BASE+0x08)
/* Values to write to mode register to disable the watchdog function. */
#define DISABLE_SEQ1 0xF5
#define DISABLE_SEQ2 0xA0
/* WDTIM_CONTROL bit definitions. */
#define WDTIM_CONTROL_ST BIT7
/* ---------------------------------------------------------------------------
* Differentiating processor versions for those who care.
* ---------------------------------------------------------------------------
*
*/
#define OMAP1509 0
#define OMAP1510 1
#define OMAP1510_ID_CODE_REG 0xfffed404
#ifndef __ASSEMBLY__
int cpu_type(void);
#endif
/*
* EVM Implementation Specifics.
*
* *** NOTE ***
* Any definitions in these files should be prefixed by an identifier -
* eg. OMAP1510P1_FLASH0_BASE .
*
*/
#ifdef CONFIG_OMAP_INNOVATOR
#include "innovator.h"
#endif
#ifdef CONFIG_OMAP_1510P1
#include "omap1510p1.h"
#endif
/*****************************************************************************/
#define CLKGEN_RESET_BASE (0xfffece00)
#define ARM_CKCTL (volatile __u16 *)(CLKGEN_RESET_BASE + 0x0)
#define ARM_IDLECT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x4)
#define ARM_IDLECT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x8)
#define ARM_EWUPCT (volatile __u16 *)(CLKGEN_RESET_BASE + 0xC)
#define ARM_RSTCT1 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x10)
#define ARM_RSTCT2 (volatile __u16 *)(CLKGEN_RESET_BASE + 0x14)
#define ARM_SYSST (volatile __u16 *)(CLKGEN_RESET_BASE + 0x18)
#define CK_CLKIN 12 /* MHz */
#define CK_RATEF 1
#define CK_IDLEF 2
#define CK_ENABLEF 4
#define CK_SELECTF 8
#ifndef __ASSEMBLER__
#define CK_DPLL1 ((volatile __u16 *)0xfffecf00)
#else
#define CK_DPLL1 (0xfffecf00)
#endif
#define SETARM_IDLE_SHIFT
/* ARM_CKCTL bit shifts */
#define PERDIV 0
#define LCDDIV 2
#define ARMDIV 4
#define DSPDIV 6
#define TCDIV 8
#define DSPMMUDIV 10
#define ARM_TIMXO 12
#define EN_DSPCK 13
#define ARM_INTHCK_SEL 14 /* REVISIT -- where is this used? */
#define ARM_CKCTL_RSRVD_BIT15 (1 << 15)
#define ARM_CKCTL_ARM_INTHCK_SEL (1 << 14)
#define ARM_CKCTL_EN_DSPCK (1 << 13)
#define ARM_CKCTL_ARM_TIMXO (1 << 12)
#define ARM_CKCTL_DSPMMU_DIV1 (1 << 11)
#define ARM_CKCTL_DSPMMU_DIV2 (1 << 10)
#define ARM_CKCTL_TCDIV1 (1 << 9)
#define ARM_CKCTL_TCDIV2 (1 << 8)
#define ARM_CKCTL_DSPDIV1 (1 << 7)
#define ARM_CKCTL_DSPDIV0 (1 << 6)
#define ARM_CKCTL_ARMDIV1 (1 << 5)
#define ARM_CKCTL_ARMDIV0 (1 << 4)
#define ARM_CKCTL_LCDDIV1 (1 << 3)
#define ARM_CKCTL_LCDDIV0 (1 << 2)
#define ARM_CKCTL_PERDIV1 (1 << 1)
#define ARM_CKCTL_PERDIV0 (1 << 0)
/* ARM_IDLECT1 bit shifts */
#define IDLWDT_ARM 0
#define IDLXORP_ARM 1
#define IDLPER_ARM 2
#define IDLLCD_ARM 3
#define IDLLB_ARM 4
#define IDLHSAB_ARM 5
#define IDLIF_ARM 6
#define IDLDPLL_ARM 7
#define IDLAPI_ARM 8
#define IDLTIM_ARM 9
#define SETARM_IDLE 11
/* ARM_IDLECT2 bit shifts */
#define EN_WDTCK 0
#define EN_XORPCK 1
#define EN_PERCK 2
#define EN_LCDCK 3
#define EN_LBCK 4
#define EN_HSABCK 5
#define EN_APICK 6
#define EN_TIMCK 7
#define DMACK_REQ 8
#define EN_GPIOCK 9
#define EN_LBFREECK 10
#define ARM_RSTCT1_SW_RST (1 << 3)
#define ARM_RSTCT1_DSP_RST (1 << 2)
#define ARM_RSTCT1_DSP_EN (1 << 1)
#define ARM_RSTCT1_ARM_RST (1 << 0)
/* ARM_RSTCT2 bit shifts */
#define EN_PER 0
#define ARM_SYSST_RSRVD_BIT15 (1 << 15)
#define ARM_SYSST_RSRVD_BIT14 (1 << 14)
#define ARM_SYSST_CLOCK_SELECT2 (1 << 13)
#define ARM_SYSST_CLOCK_SELECT1 (1 << 12)
#define ARM_SYSST_CLOCK_SELECT0 (1 << 11)
#define ARM_SYSST_RSRVD_BIT10 (1 << 10)
#define ARM_SYSST_RSRVD_BIT9 (1 << 9)
#define ARM_SYSST_RSRVD_BIT8 (1 << 8)
#define ARM_SYSST_RSRVD_BIT7 (1 << 7)
#define ARM_SYSST_IDLE_DSP (1 << 6)
#define ARM_SYSST_POR (1 << 5)
#define ARM_SYSST_EXT_RST (1 << 4)
#define ARM_SYSST_ARM_MCRST (1 << 3)
#define ARM_SYSST_ARM_WDRST (1 << 2)
#define ARM_SYSST_GLOB_SWRST (1 << 1)
#define ARM_SYSST_DSP_WDRST (1 << 0)
/* Table 15-23. DPLL Control Registers: */
#define DPLL_CTL_REG (volatile __u16 *)(0xfffecf00)
/* Table 15-24. Control Register (CTL_REG): */
#define DPLL_CTL_REG_IOB (1 << 13)
#define DPLL_CTL_REG_PLL_MULT Fld(5,0)
/*****************************************************************************/
/* OMAP INTERRUPT REGISTERS */
#define IRQ_ITR 0x00
#define IRQ_MIR 0x04
#define IRQ_SIR_IRQ 0x10
#define IRQ_SIR_FIQ 0x14
#define IRQ_CONTROL_REG 0x18
#define IRQ_ISR 0x9c
#define IRQ_ILR0 0x1c
#define REG_IHL1_MIR (OMAP_IH1_BASE+IRQ_MIR)
#define REG_IHL2_MIR (OMAP_IH2_BASE+IRQ_MIR)
/* INTERRUPT LEVEL REGISTER BITS */
#define ILR_PRIORITY_MASK (0x3c)
#define ILR_PRIORITY_SHIFT (2)
#define ILR_LEVEL_TRIGGER (1<<1)
#define ILR_FIQ (1<<0)
#define IRQ_LEVEL_INT 1
#define IRQ_EDGE_INT 0
/* Macros to access registers */
#define outb(v,p) *(volatile u8 *) (p) = v
#define outw(v,p) *(volatile u16 *) (p) = v
#define outl(v,p) *(volatile u32 *) (p) = v
#define inb(p) *(volatile u8 *) (p)
#define inw(p) *(volatile u16 *) (p)
#define inl(p) *(volatile u32 *) (p)
|
1001-study-uboot
|
include/configs/omap1510.h
|
C
|
gpl3
| 26,698
|
/*
* Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* P3041 DS board configuration file
*
*/
#define CONFIG_P3041DS
#define CONFIG_PHYS_64BIT
#define CONFIG_PPC_P3041
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
|
1001-study-uboot
|
include/configs/P3041DS.h
|
C
|
gpl3
| 1,250
|
/*
* U-boot - Configuration file for IBF-DSP561 board
*/
#ifndef __CONFIG_IBF_DSP561__H__
#define __CONFIG_IBF_DSP561__H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf561-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 24
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x377
#define CONFIG_EBIU_SDGCTL_VAL 0x91998d
#define CONFIG_EBIU_SDBCTL_VAL 0x15
#define CONFIG_EBIU_AMGCTL_VAL 0x3F
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_DRIVER_AX88180 1
#define AX88180_BASE 0x2c000000
#define CONFIG_HOSTNAME ibf-dsp561
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI_AMD_RESET
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max number of sectors on one chip */
/* The BF561-EZKIT uses a top boot flash */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* an error during compilation remove an object here to get
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
/*
* I2C Settings
*/
#define CONFIG_SOFT_I2C 1
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
/*
* Misc Settings
*/
#define CONFIG_UART_CONSOLE 0
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/ibf-dsp561.h
|
C
|
gpl3
| 3,407
|
/*
* (C) Copyright 2005
* Greg Ungerer <greg.ungerer@opengear.com>.
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_KS8695 1 /* it is a KS8695 CPU */
#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
/*
* select serial console configuration
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_KS8695_SERIAL
#define CONFIG_SERIAL1
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_SAVEENV
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200"
#define CONFIG_BOOTCOMMAND "gofsk 0x02200000"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */
#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/cm41xx.h
|
C
|
gpl3
| 4,356
|
/*
* U-boot - Configuration file for CM-BF537E board
*/
#ifndef __CONFIG_CM_BF537E_H__
#define __CONFIG_CM_BF537E_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 21
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
#define CONFIG_EBIU_SDRRC_VAL 0x3f8
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0x20308000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_NETCONSOLE 1
#endif
#define CONFIG_HOSTNAME cm-bf537e
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 35
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE 0x8000
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* an error during compilation remove an object here to get
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* SPI_MMC Settings
*/
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 3c0000;" \
"bootm 0x1000000\0"
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/cm-bf537e.h
|
C
|
gpl3
| 3,897
|
/*
* (C) Copyright 2004
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Kshitij Gupta <kshitij@ti.com>
*
* Configuration settings for the 242x TI H4 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP2420 1 /* which is in a 2420 */
#define CONFIG_OMAP2420H4 1 /* and on a H4 board */
/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */
/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */
#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
/* Clock config to target*/
#define PRCM_CONFIG_II 1
/* #define PRCM_CONFIG_III 1 */
#include <asm/arch/omap2420.h> /* get chip and board defs */
/* On H4, NOR and NAND flash are mutual exclusive.
Define this if you want to use NAND
*/
/*#define CONFIG_SYS_NAND_BOOT */
#ifdef CONFIG_APTIX
#define V_SCLK 1500000
#else
#define V_SCLK 12000000
#endif
/* input clock of PLL */
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define CONFIG_SYS_CLK_FREQ V_SCLK
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K)
/*
* Hardware drivers
*/
/*
* SMC91c96 Etherent
*/
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300)
#define CONFIG_LAN91C96_EXT_PHY
/*
* NS16550 Configuration
*/
#ifdef CONFIG_APTIX
#define V_NS16550_CLK (6000000) /* 6MHz in current MaxSet */
#else
#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
#endif
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* UART1 on H4 */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_DRIVER_OMAP24XX_I2C
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#ifdef CONFIG_SYS_NAND_BOOT
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NAND
#define CONFIG_CMD_JFFS2
#else
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_SOURCE
#endif
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTDELAY 3
#ifdef NFS_BOOT_DEFAULTS
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
#else
#define CONFIG_BOOTARGS "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
#endif
#define CONFIG_NETMASK 255.255.254.0
#define CONFIG_IPADDR 128.247.77.90
#define CONFIG_SERVERIP 128.247.77.158
#define CONFIG_BOOTFILE "uImage"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_APTIX
# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # "
#else
# define CONFIG_SYS_PROMPT "OMAP242x H4 # "
#endif
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#ifdef CONFIG_APTIX
#define V_PTV 3
#else
#define V_PTV 7 /* use with 12MHz/128 */
#endif
#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE SZ_128K /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
#define PHYS_FLASH_SECT_SIZE SZ_128K
#define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */
#define PHYS_FLASH_SIZE_1 SZ_32M
#define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
#define PHYS_FLASH_SIZE_2 SZ_32M
#define PHYS_SRAM 0x4020F800
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
#ifdef CONFIG_SYS_NAND_BOOT
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */
#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
#endif
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_SYS_JFFS2_MEM_NAND
/*
* JFFS2 partitions
*/
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV "nor1"
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "nor1=omap2420-1"
#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)"
*/
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap2420h4.h
|
C
|
gpl3
| 9,177
|
/*
* (C) Copyright 2009
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPEAR_COMMON_H
#define _SPEAR_COMMON_H
/*
* Common configurations used for both spear3xx as well as spear6xx
*/
/* USBD driver configuration */
#define CONFIG_SPEARUDC
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
#define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
/* I2C driver configuration */
#define CONFIG_HARD_I2C
#define CONFIG_SPEAR_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x02
#define CONFIG_I2C_CHIPADDRESS 0x50
/* Timer, HZ specific defines */
#define CONFIG_SYS_HZ (1000)
#define CONFIG_SYS_HZ_CLOCK (8300000)
/* Flash configuration */
#if defined(CONFIG_FLASH_PNOR)
#define CONFIG_SPEAR_EMI 1
#else
#define CONFIG_SPEARSMI 1
#endif
#if defined(CONFIG_SPEARSMI)
#define CONFIG_SYS_MAX_FLASH_BANKS 2
#define CONFIG_SYS_FLASH_BASE (0xF8000000)
#define CONFIG_SYS_CS1_FLASH_BASE (0xF9000000)
#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000)
#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_CS1_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_FLASH_EMPTY_INFO 1
#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
#endif
/*
* Serial Configuration (PL011)
* CONFIG_PL01x_PORTS is defined in specific files
*/
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
57600, 115200 }
#define CONFIG_SYS_LOADS_BAUD_CHANGE
/* NAND FLASH Configuration */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_NAND_SPEAR 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
/*
* Command support defines
*/
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NAND
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES
/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
* Default Environment Varible definitions
*/
#if defined(CONFIG_SPEAR_USBTTY)
#define CONFIG_BOOTDELAY -1
#else
#define CONFIG_BOOTDELAY 1
#endif
#define CONFIG_ENV_OVERWRITE
/*
* U-Boot Environment placing definitions.
*/
#if defined(CONFIG_ENV_IS_IN_FLASH)
#ifdef CONFIG_SPEARSMI
/*
* Environment is in serial NOR flash
*/
#define CONFIG_SYS_MONITOR_LEN 0x00040000
#define CONFIG_ENV_SECT_SIZE 0x00010000
#define CONFIG_FSMTDBLK "/dev/mtdblock8 "
#define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
#elif defined(CONFIG_SPEAR_EMI)
/*
* Environment is in parallel NOR flash
*/
#define CONFIG_SYS_MONITOR_LEN 0x00060000
#define CONFIG_ENV_SECT_SIZE 0x00020000
#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \
"0x4C0000; bootm 0x1600000"
#endif
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#elif defined(CONFIG_ENV_IS_IN_NAND)
/*
* Environment is in NAND
*/
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_RANGE 0x10000
#define CONFIG_FSMTDBLK "/dev/mtdblock12 "
#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
"0x80000 0x4C0000; " \
"bootm 0x1600000"
#endif
#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \
"console=ttyS0 init=/bin/sh"
#define CONFIG_BOOTARGS "console=ttyS0 mem=128M " \
"root="CONFIG_FSMTDBLK \
"rootfstype=jffs2"
#define CONFIG_ENV_SIZE 0x02000
/* Miscellaneous configurable options */
#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_MISC_INIT_R 1
#define CONFIG_ZERO_BOOTDELAY_CHECK 1
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_STOP_STR " "
#define CONFIG_AUTOBOOT_PROMPT \
"Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
#define CONFIG_SYS_MEMTEST_START 0x00800000
#define CONFIG_SYS_MEMTEST_END 0x04000000
#define CONFIG_SYS_MALLOC_LEN (1024*1024)
#define CONFIG_IDENT_STRING "-SPEAr"
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "u-boot> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x00800000
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
#define CONFIG_SYS_64BIT_VSPRINTF 1
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
/* Stack sizes */
#define CONFIG_STACKSIZE (128*1024)
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024)
#define CONFIG_STACKSIZE_FIQ (4*1024)
#endif
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
#define PHYS_SDRAM_1_MAXSIZE 0x40000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#endif
|
1001-study-uboot
|
include/configs/spear-common.h
|
C
|
gpl3
| 6,280
|
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_MVS 1 /* ...on a MVsensor module */
#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */
#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 115200 /* console baudrate */
#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
#define CONFIG_PREBOOT "echo;" \
"echo To mount root over NFS use \"run bootnet\";" \
"echo To mount root from FLASH use \"run bootflash\";" \
"echo"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#define CONFIG_WATCHDOG /* watchdog disabled/enabled */
#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_VENDOREX
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
* Command line configuration.
*/
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_IMI
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_RUN
/*
* Miscellaneous configurable options
*/
#undef CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CONFIG_SYS_IMMR 0xFFF00000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0x40000000
#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_ENV_IS_IN_FLASH 1
/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */
#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*
*/
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
/*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#define CONFIG_SYS_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
/*-----------------------------------------------------------------------
* PCMCIA stuff
*-----------------------------------------------------------------------
*
*/
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
/*-----------------------------------------------------------------------
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */
#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */
#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
/*#define CONFIG_SYS_DER 0x2002000F*/
#define CONFIG_SYS_DER 0
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
#undef FLASH_BASE1_PRELIM
/* used to re-map FLASH both when starting from SRAM or FLASH:
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/*
* FLASH timing:
*/
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_2_CLK | OR_EHTR | OR_BI)
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
/*
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
OR_SCY_5_CLK | OR_EHTR)
*/
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#ifdef CONFIG_MVS_16BIT_FLASH
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
#else
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
#endif
#undef CONFIG_SYS_OR1_REMAP
#undef CONFIG_SYS_OR1_PRELIM
#undef CONFIG_SYS_BR1_PRELIM
/*
* BR2/3 and OR2/3 (SDRAM)
*
*/
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
#undef SDRAM_BASE3_PRELIM
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
#undef CONFIG_SYS_OR3_PRELIM
#undef CONFIG_SYS_BR3_PRELIM
/*
* Memory Periodic Timer Prescaler
*
* The Divider for PTA (refresh timer) configuration is based on an
* example SDRAM configuration (64 MBit, one bank). The adjustment to
* the number of chip selects (NCS) and the actually needed refresh
* rate is done by setting MPTPR.
*
* PTA is calculated from
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
*
* gclk CPU clock (not bus clock!)
* Trefresh Refresh cycle * 4 (four word bursts used)
*
* 4096 Rows from SDRAM example configuration
* 1000 factor s -> ms
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
* --------------------------------------------
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
*
* 50 MHz => 50.000.000 / Divider = 98
* 66 Mhz => 66.000.000 / Divider = 129
* 80 Mhz => 80.000.000 / Divider = 156
*/
#define CONFIG_SYS_MAMR_PTA 98
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/MVS1.h
|
C
|
gpl3
| 14,782
|