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stringlengths 1
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/*
* U-boot - Configuration file for bf525-ucr2 board
* The board includes ADSP-BF525 rev. 0.2,
* 32-bit SDRAM (SAMSUNG K4S561632H-UC75),
* USB 2.0 High Speed OTG USB WIFI,
* SPI flash (cFeon EN25Q128 16 MB),
* Support PPI and ITU-R656,
* See http://www.ucrobotics.com/?q=cn/ucr2
*/
#ifndef __CONFIG_BF525_UCR2_H__
#define __CONFIG_BF525_UCR2_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf525-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 24000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
/*
* SDRAM reference page
* http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
*/
#define CONFIG_EBIU_SDRRC_VAL 0x3f8
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
#define CONFIG_SYS_MALLOC_LEN (320 * 1024)
/* We don't have a parallel flash chip */
#define CONFIG_SYS_NO_FLASH
/* support for serial flash */
#define CONFIG_BFIN_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_HZ 30000000
#define CONFIG_SPI_FLASH_EON
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_OVERWRITE 1
/*
* Misc Settings
*/
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
#define CONFIG_BOOTCOMMAND "run sfboot"
#define CONFIG_BOOTDELAY 5
#define CONFIG_EXTRA_ENV_SETTINGS \
"sfboot=sf probe 1;" \
"sf read 0x1000000 0x20000 0x300000;" \
"bootm 0x1000000\0"
/* this sets up the default list of enabled commands */
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_IMLS
#endif
|
1001-study-uboot
|
include/configs/bf525-ucr2.h
|
C
|
gpl3
| 3,002
|
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
*
* Copyright (C) 2009
* Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
*
* Configuation settings for the Calao TNY-A9260 and TNY-A9G20 boards
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* SoC must be defined first, before hardware.h is included.
* In this case SoC is defined in boards.cfg.
*/
#include <asm/hardware.h>
#if defined(CONFIG_TNY_A9260_NANDFLASH) || defined(CONFIG_TNY_A9G20_NANDFLASH)
#define CONFIG_ENV_IS_IN_NAND
#else
#define CONFIG_ENV_IS_IN_EEPROM
#endif
/* Define actual evaluation board type from used processor type */
#ifdef CONFIG_AT91SAM9G20
# define CONFIG_TNY_A9G20
# define MACH_TYPE_TNY_A9G20 2059
# define CONFIG_MACH_TYPE MACH_TYPE_TNY_A9G20
#else
# define CONFIG_TNY_A9260
# define MACH_TYPE_TNY_A9260 2058
# define CONFIG_MACH_TYPE MACH_TYPE_TNY_A9260
#endif
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
/*
* Hardware drivers
*/
#define CONFIG_ATMEL_LEGACY
#define CONFIG_AT91_GPIO
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_BOOTDELAY 3
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_USB
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
# define CONFIG_SYS_INIT_SP_ADDR \
(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
/* SPI EEPROM */
#define CONFIG_SPI
#define CONFIG_CMD_SPI
#define CONFIG_ATMEL_SPI
#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
#define CONFIG_CMD_EEPROM
#define CONFIG_SPI_M95XXX
#define CONFIG_SYS_EEPROM_SIZE 0x10000
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
/* NAND flash */
#define CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
/* Env in EEPROM, bootstrap + u-boot in NAND*/
#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET 0x20
#define CONFIG_ENV_SIZE 0x1000
#endif
/* Env, bootstrap and u-boot in NAND */
#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
#endif
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock1 " \
"mtdparts=atmel_nand:16M(kernel)ro," \
"120M(rootfs),-(other) " \
"rw rootfstype=jffs2"
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif
#endif
|
1001-study-uboot
|
include/configs/tny_a9260.h
|
C
|
gpl3
| 5,087
|
/*
* (C) Copyright 2008
*
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com
*
* Georg Schardt <schardt@team-ctech.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Configuration file for the Virtex4FX12 Minimodul by Avnet/Memec,
* see http://www.em.avnet.com
*/
#ifndef __CONFIG_FX12_H
#define __CONFIG_FX12_H
#include "../board/avnet/fx12mm/xparameters.h"
/* cmd config */
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#undef CONFIG_CMD_NET
/* sdram */
#define CONFIG_SYS_SDRAM_SIZE_MB 64
/* environment */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_SYS_ENV_OFFSET 0xA0000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
#define CONFIG_ENV_OVERWRITE 1
/*Misc*/
#define CONFIG_SYS_PROMPT "FX12MM:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and running;"
/*Flash*/
#define CONFIG_SYS_FLASH_SIZE (4*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 71
#define MTDIDS_DEFAULT "nor0=fx12mm-flash"
#define MTDPARTS_DEFAULT "mtdparts=fx12mm-flash:-(user)"
#include "configs/xilinx-ppc405.h"
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/fx12mm.h
|
C
|
gpl3
| 2,142
|
/*
* MATRIX VISION GmbH mvBlueLYNX-X
*
* Derived from omap3_beagle.h:
* (C) Copyright 2006-2008
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
*
* Configuration settings for the TI OMAP3530 Beagle board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#define CONFIG_SERIAL_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#define CONFIG_TWL4030_USB 1
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
#define CONFIG_USBD_VENDORID 0x164c
#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
/* no FLASH available */
#define CONFIG_SYS_NO_FLASH
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_FPGA
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0
#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#define CONFIG_I2C_MULTI_BUS 1
/*
* TWL4030
*/
#define CONFIG_TWL4030_POWER 1
/* Environment information */
#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
"console=ttyO2,115200n8\0" \
"mpurate=600\0" \
"vram=12M\0" \
"dvimode=1024x768-24@60\0" \
"defaultdisplay=dvi\0" \
"fpgafilename=mvbluelynx_x.rbf\0" \
"loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
"fpga load 0 ${loadaddr} ${filesize}; " \
"fi;\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapfb.debug=y " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype} " \
"${cmdline_suffix}\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t $loadaddr $filesize\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"mmcbootcmd= " \
"echo Trying mmc${mmcdev}; " \
"mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
"echo SD/MMC found on device ${mmcdev};" \
"if run loadbootenv; then " \
"echo Loading boot environment from mmc${mmcdev}; " \
"run importbootenv; " \
"fi;" \
"run loadfpga; " \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"if run loaduimage; then " \
"run mmcboot; " \
"fi;" \
"fi\0"
#define CONFIG_BOOTCOMMAND \
"setenv mmcdev 1;" \
"run mmcbootcmd || " \
"setenv mmcdev 0;" \
"run mmcbootcmd"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "mvblx # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
/* default load address */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
#define CONFIG_ENV_IS_NOWHERE 1
/*----------------------------------------------------------------------------
* Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
*----------------------------------------------------------------------------
*/
#if defined(CONFIG_CMD_NET)
#define CONFIG_NET_MULTI
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
#define CONFIG_FPGA_COUNT 1
#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_CYCLON2
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_EEPROM_BUS_NUM 2
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_OMAP3_SPI
#define CONFIG_SYS_CACHELINE_SIZE 64
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap3_mvblx.h
|
C
|
gpl3
| 9,398
|
/*
* Copyright (C) 2011 Texas Instruments Incorporated
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Spectrum Digital TMS320DM6467T EVM board */
#define DAVINCI_DM6467EVM
#define DAVINCI_DM6467TEVM
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SKIP_LOWLEVEL_INIT
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
/* Clock rates detection */
#ifndef __ASSEMBLY__
extern unsigned int davinci_arm_clk_get(void);
#endif
#define CFG_REFCLK_FREQ 33000000
/* Arm Clock frequency */
#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get()
/* Timer Input clock freq */
#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM646X
/* EEPROM definitions for EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */
/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
#define CONFIG_REVISION_TAG
/* Serial Driver info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 4
#define CONFIG_SYS_NS16550_COM1 0x01c20000
#define CONFIG_SYS_NS16550_CLK 24000000
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* I2C Configuration */
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 10
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_EMAC_MDIO_PHY_NUM 1
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_CMD_NET
/* Flash & Environment */
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_ENV_OFFSET 0
#else
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */
#endif
/* U-Boot general configuration */
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DM6467 EVM > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm"
#define CONFIG_BOOTARGS \
"mem=120M console=ttyS0,115200n8 " \
"root=/dev/hda1 rw noinitrd ip=dhcp"
/* U-Boot commands */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#ifdef CONFIG_SYS_USE_NAND
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/davinci_dm6467Tevm.h
|
C
|
gpl3
| 5,185
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2010-2011
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/* for linking errors see
* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
#ifndef _CONFIG_MGCOGE3UN_H
#define _CONFIG_MGCOGE3UN_H
/* include common defines/options for all arm based Keymile boards */
#include "km/km_arm.h"
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nKeymile MGCOGE3UN"
#define CONFIG_HOSTNAME mgcoge3un
#define CONFIG_MGCOGE3UN
#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/
#define KM_ENV_BUS "pca9547:70:d" /* I2C2 (Mux-Port 5)*/
/* we use a new RAM type on mgcoge3un board */
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
/*
* mgcoge3un has a fixed link to the marvell switch
* with 100MB full duplex and autoneg off, for this
* reason we have to change the default settings
*/
#define PORT_SERIAL_CONTROL_VALUE ( \
MVGBE_FORCE_LINK_PASS | \
MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
MVGBE_ADV_NO_FLOW_CTRL | \
MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
MVGBE_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
MVGBE_DO_NOT_FORCE_LINK_FAIL | \
MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
MVGBE_DTE_ADV_0 | \
MVGBE_MIIPHY_MAC_MODE | \
MVGBE_AUTO_NEG_NO_CHANGE | \
MVGBE_MAX_RX_PACKET_1552BYTE | \
MVGBE_CLR_EXT_LOOPBACK | \
MVGBE_SET_FULL_DUPLEX_MODE | \
MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
MVGBE_SET_GMII_SPEED_TO_10_100 |\
MVGBE_SET_MII_SPEED_TO_100)
#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
/*
* PCIe port not used on mgcoge3un
*/
#undef CONFIG_KIRKWOOD_PCIE_INIT
#endif /* _CONFIG_MGCOGE3UN_H */
|
1001-study-uboot
|
include/configs/mgcoge3un.h
|
C
|
gpl3
| 2,737
|
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*=======*/
/* Board */
/*=======*/
#define SCHMOOGIE
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
#define CONFIG_DISPLAY_CPUINFO
#define MACH_TYPE_SCHMOOGIE 1255
#define CONFIG_MACH_TYPE MACH_TYPE_SCHMOOGIE
/*===================*/
/* SoC Configuration */
/*===================*/
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM644X
/*=============*/
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*===================*/
/* I2C Configuration */
/*===================*/
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_OVERWRITE_ETHADDR_ONCE
/*=====================*/
/* Flash & Environment */
/*=====================*/
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
/*=====================*/
/* Board related stuff */
/*=====================*/
#define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */
#define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */
#define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */
#define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/*===================*/
/* Linux Information */
/*===================*/
#define LINUX_BOOT_PARAM_ADDR 0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot"
/*=================*/
/* U-Boot commands */
/*=================*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND
#undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/davinci_schmoogie.h
|
C
|
gpl3
| 6,171
|
/*
* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* include common defines/options for all imx27lite related boards */
#include "imx27lite-common.h"
/*
* SoC Configuration
*/
#define CONFIG_IMX27LITE
#define CONFIG_HOSTNAME imx27
#define CONFIG_BOARDNAME "LogicPD imx27lite\n"
/*
* Flash & Environment
*/
#define CONFIG_SYS_FLASH_SECT_SZ 0x2000 /* 8KB sect size Intel Flash */
#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x20000)
#define PHYS_FLASH_SIZE 0x200000
#define CONFIG_ENV_SECT_SIZE 0x10000 /* Env sector Size */
/*
* SD/MMC
*/
#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
/*
* MTD partitions
*/
#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
#define MTDPARTS_DEFAULT \
"mtdparts=" \
"physmap-flash.0:" \
"256k(U-Boot)," \
"1664k(user)," \
"64k(env1)," \
"64k(env2);" \
"mxc_nand.0:" \
"128k(IPL-SPL)," \
"4m(kernel)," \
"22m(rootfs)," \
"-(userfs)"
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/imx27lite.h
|
C
|
gpl3
| 1,729
|
/*
*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
*
* (C) Copyright 2008
* Georg Schardt <schardt@team-ctech.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* cpu parameter */
#define CONFIG_405 1
#define CONFIG_4xx 1
#define CONFIG_XILINX_405 1
#include <configs/xilinx-ppc.h>
#endif
|
1001-study-uboot
|
include/configs/xilinx-ppc405.h
|
C
|
gpl3
| 1,202
|
/*
* U-boot - Configuration file for BF527 AD7160-EVAL board
*/
#ifndef __CONFIG_BF527_AD7160_EVAL_H__
#define __CONFIG_BF527_AD7160_EVAL_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf527-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 24000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 25
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x03F6
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
/*
* NAND Settings
* (can't be used same time as ethernet)
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
# define CONFIG_BFIN_NFC
# define CONFIG_BFIN_NFC_BOOTROM_ECC
#endif
#ifdef CONFIG_BFIN_NFC
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
#define CONFIG_DRIVER_NAND_BFIN
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#endif
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SIZE 0x20000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* SPI_MMC Settings
*/
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
/*
* Misc Settings
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE 0
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf527-ad7160-eval.h
|
C
|
gpl3
| 3,678
|
/*
* Configuation settings for the Freescale MCF5373 FireEngine board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5373EVB_H
#define _M5373EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5373 /* define processor type */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#ifdef NANDFLASH_SIZE
# define CONFIG_CMD_NAND
#endif
#define CONFIG_SYS_UNIFY_CACHE
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
#define CONFIG_MCFRTC
#undef RTC_DEBUG
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M5373EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 3ffff;" \
"era 0 3ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x40010000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
#define CONFIG_SYS_MBAR 0xFC000000
#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x53722730
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#ifdef NANDFLASH_SIZE
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
# define CONFIG_JFFS2_NAND 1
# define CONFIG_JFFS2_DEV "nand0"
# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - CompactFlash and registers
* CS2 - NAND Flash 16, 32, or 64MB
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0
#define CONFIG_SYS_CS0_MASK 0x007f0001
#define CONFIG_SYS_CS0_CTRL 0x00001fa0
#define CONFIG_SYS_CS1_BASE 0x10000000
#define CONFIG_SYS_CS1_MASK 0x001f0001
#define CONFIG_SYS_CS1_CTRL 0x002A3780
#ifdef NANDFLASH_SIZE
#define CONFIG_SYS_CS2_BASE 0x20000000
#define CONFIG_SYS_CS2_MASK ((NANDFLASH_SIZE << 20) | 1)
#define CONFIG_SYS_CS2_CTRL 0x00001f60
#endif
#endif /* _M5373EVB_H */
|
1001-study-uboot
|
include/configs/M5373EVB.h
|
C
|
gpl3
| 8,867
|
/*
* Configuation settings for the Motorola MC5272C3 board.
*
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5272C3_H
#define _M5272C3_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5272 /* define processor type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
#else
#define CONFIG_ENV_ADDR 0xffe04000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
#endif
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_MISC
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#define CONFIG_BOOTDELAY 5
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* CONFIG_MCFFEC */
#define CONFIG_HOSTNAME M5272C3
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off ffe00000 ffe3ffff;" \
"era ffe00000 ffe3ffff;" \
"cp.b ${loadaddr} ffe00000 ${filesize};"\
"save\0" \
""
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x20000
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 66000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CONFIG_SYS_SCR 0x0003
#define CONFIG_SYS_SPR 0xffff
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE 0x20000
#else
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_MONITOR_LEN 0x20000
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/*
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
#define CONFIG_SYS_BR1_PRELIM 0
#define CONFIG_SYS_OR1_PRELIM 0
#define CONFIG_SYS_BR2_PRELIM 0x30000001
#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
#define CONFIG_SYS_BR3_PRELIM 0
#define CONFIG_SYS_OR3_PRELIM 0
#define CONFIG_SYS_BR4_PRELIM 0
#define CONFIG_SYS_OR4_PRELIM 0
#define CONFIG_SYS_BR5_PRELIM 0
#define CONFIG_SYS_OR5_PRELIM 0
#define CONFIG_SYS_BR6_PRELIM 0
#define CONFIG_SYS_OR6_PRELIM 0
#define CONFIG_SYS_BR7_PRELIM 0x00000701
#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_PACNT 0x00000000
#define CONFIG_SYS_PADDR 0x0000
#define CONFIG_SYS_PADAT 0x0000
#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
#define CONFIG_SYS_PBDDR 0x0000
#define CONFIG_SYS_PBDAT 0x0000
#define CONFIG_SYS_PDCNT 0x00000000
#endif /* _M5272C3_H */
|
1001-study-uboot
|
include/configs/M5272C3.h
|
C
|
gpl3
| 8,260
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_RD6281A_H
#define _CONFIG_RD6281A_H
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nMarvell-RD6281A"
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_RD6281A /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_IDE
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
#define CONFIG_ENV_ADDR 0x40000
#define CONFIG_ENV_OFFSET 0x40000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"${x_bootcmd_usb}; bootm 0x6400000;"
#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
"3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
#define CONFIG_PHY_BASE_ADR 0x0A
#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */
#endif /* CONFIG_CMD_NET */
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_RD6281A_H */
|
1001-study-uboot
|
include/configs/rd6281a.h
|
C
|
gpl3
| 3,484
|
/*
* (C) Copyright 2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */
#define CONFIG_OMAP_SX1 1 /* a SX1 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* the SX1 has 12MHz input clock */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SX1 */
/*
* USB device configuration
*/
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_USBD_VENDORID 0x1234
#define CONFIG_USBD_PRODUCTID 0x5678
#define CONFIG_USBD_MANUFACTURER "Siemens"
#define CONFIG_USBD_PRODUCT_NAME "SX1"
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_DRIVER_OMAP1510_I2C
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_NET
#include <configs/omap1510.h>
#define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw"
#ifdef CONFIG_STDOUT_USBTTY
#define CONFIG_PREBOOT "setenv stdout usbtty;setenv stdin usbtty"
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "SX1# " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
* This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
* V1
* PHYS_FLASH_SIZE_1 (16 << 10) 16 MB
* PHYS_FLASH_SIZE_2 (8 << 10) 8 MB
* V2 only 1 flash
* PHYS_FLASH_SIZE_1 (32 << 10) 32 MB
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */
#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, PHYS_FLASH_2 }
/*-----------------------------------------------------------------------
* FLASH driver setup
*/
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Total Size of Environment Sector */
#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_SIZE_REDUND 0x20000
#define CONFIG_ENV_OFFSET_REDUND 0x40000
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/SX1.h
|
C
|
gpl3
| 6,713
|
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
#include "tegra2-common.h"
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (Ventana) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Ventana"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA2_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/ventana.h
|
C
|
gpl3
| 1,690
|
/*
* Copyright (C) 2009 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Configuation settings for the SAMSUNG Universal (s5pc100) board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5P 1 /* which is in a S5P Family */
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#define CONFIG_MACH_GONI 1 /* working with Goni */
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* input clock of PLL: has 24MHz input clock at S5PC110 */
#define CONFIG_SYS_CLK_FREQ_C110 24000000
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
/*
* Size of malloc() pool
* 1MB = 0x100000, 0x100000 = 1024 * 1024
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/*
* select serial console configuration
*/
#define CONFIG_SERIAL2 1 /* use SERIAL2 */
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 115200
/* MMC */
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_S5P_MMC 1
/* PWM */
#define CONFIG_PWM 1
/* It should define before config_cmd_default.h */
#define CONFIG_SYS_NO_FLASH 1
/* Command definition */
#include <config_cmd_default.h>
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_XIMG
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_ONENAND
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */
#define MTDIDS_DEFAULT "onenand0=samsung-onenand"
#define MTDPARTS_DEFAULT "mtdparts=samsung-onenand:1m(bootloader)"\
",256k(params)"\
",2816k(config)"\
",8m(csa)"\
",7m(kernel)"\
",1m(log)"\
",12m(modem)"\
",60m(qboot)"\
",-(UBI)\0"
#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
#define CONFIG_BOOTCOMMAND "run ubifsboot"
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \
" ${console} ${meminfo}"
#define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}"
#define CONFIG_BOOTARGS "root=/dev/mtdblock8 ubi.mtd=8 ubi.mtd=3 ubi.mtd=6" \
" rootfstype=cramfs " CONFIG_COMMON_BOOT
#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \
" onenand write 0x32008000 0x0 0x100000\0"
#define CONFIG_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=3 ubi.mtd=6"
#define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc"
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_UPDATEB \
"updatek=" \
"onenand erase 0xc00000 0x600000;" \
"onenand write 0x31008000 0xc00000 0x600000\0" \
"updateu=" \
"onenand erase 0x01560000 0x1eaa0000;" \
"onenand write 0x32000000 0x1260000 0x8C0000\0" \
"bootk=" \
"onenand read 0x30007FC0 0xc00000 0x600000;" \
"bootm 0x30007FC0\0" \
"flashboot=" \
"set bootargs root=/dev/mtdblock${bootblock} " \
"rootfstype=${rootfstype}" CONFIG_UBI_MTD " ${opts} " \
"${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \
"ubifsboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; run bootk\0" \
"tftpboot=" \
"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
CONFIG_UBIFS_OPTION CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; tftp 0x30007FC0 uImage; " \
"bootm 0x30007FC0\0" \
"ramboot=" \
"set bootargs " CONFIG_RAMDISK_BOOT \
" initrd=0x33000000,8M ramdisk=8192\0" \
"mmcboot=" \
"set bootargs root=${mmcblk} rootfstype=${rootfstype}" \
CONFIG_UBI_MTD " ${opts} ${lcdinfo} " \
CONFIG_COMMON_BOOT "; run bootk\0" \
"boottrace=setenv opts initcall_debug; run bootcmd\0" \
"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
"verify=n\0" \
"rootfstype=cramfs\0" \
"console=" CONFIG_DEFAULT_CONSOLE \
"mtdparts=" MTDPARTS_DEFAULT \
"meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \
"mmcblk=/dev/mmcblk1p1\0" \
"bootblock=9\0" \
"ubiblock=8\0" \
"ubi=enabled\0" \
"opts=always_resume=1"
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "Goni # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000)
#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* Stack sizes */
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
/* Goni has 3 banks of DRAM, but swap the bank */
#define CONFIG_NR_DRAM_BANKS 3
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */
#define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */
#define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */
#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */
#define PHYS_SDRAM_3 0x50000000 /* mDDR DMC2 Bank #2 */
#define PHYS_SDRAM_3_SIZE (128 << 20) /* 128 MB in Bank #2 */
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
/* FLASH and environment organization */
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB, 0x40000 */
#define CONFIG_ENV_ADDR (1 << 20) /* 1 MB, 0x100000 */
#define CONFIG_USE_ONENAND_BOARD_INIT
#define CONFIG_SAMSUNG_ONENAND 1
#define CONFIG_SYS_ONENAND_BASE 0xB0000000
#define CONFIG_DOS_PARTITION 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_MAX8998
#include <asm/arch/gpio.h>
/*
* I2C Settings
*/
#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3)
#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0)
#define CONFIG_SOFT_I2C 1
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS 7
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/s5p_goni.h
|
C
|
gpl3
| 7,696
|
/*
* U-boot - Configuration file for BF537 STAMP board
*/
#ifndef __CONFIG_BF537_STAMP_H__
#define __CONFIG_BF537_STAMP_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x306
#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
/*
* Network Settings
*/
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE 1
#endif
#define CONFIG_HOSTNAME bf537-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
#define CONFIG_SYS_MAX_FLASH_SECT 71
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
* the sector before the environment sector. If it throws
* an error during compilation remove an object here to get
* it linked after the configuration sector.
*/
# define LDS_BOARD_TEXT \
arch/blackfin/lib/libblackfin.o (.text*); \
arch/blackfin/cpu/libblackfin.o (.text*); \
. = DEFINED(env_offset) ? env_offset : .; \
common/env_embedded.o (.text*);
#endif
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* SPI_MMC Settings
*/
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI
/*
* NAND Settings
*/
/* #define CONFIG_NAND_PLAT */
#define CONFIG_SYS_NAND_BASE 0x20212000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
SSYNC(); \
} while (0)
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
/*
* CF-CARD IDE-HDD Support
*/
/*
* Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
* Strange address mapping Blackfin A13 connects to CF_A0
*/
/* #define CONFIG_BFIN_TRUE_IDE */
/*
* Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
* This should be the preferred mode
*/
/* #define CONFIG_BFIN_CF_IDE */
/*
* Add IDE Disk Drive (HDD) support
* See example interface here:
* http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
*/
/* #define CONFIG_BFIN_HDD_IDE */
#if defined(CONFIG_BFIN_CF_IDE) || \
defined(CONFIG_BFIN_HDD_IDE) || \
defined(CONFIG_BFIN_TRUE_IDE)
# define CONFIG_BFIN_IDE 1
# define CONFIG_CMD_IDE
#endif
#if defined(CONFIG_BFIN_IDE)
#define CONFIG_DOS_PARTITION 1
/*
* IDE/ATA stuff
*/
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#undef CONFIG_IDE_RESET /* no reset for ide supported */
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
#undef CONFIG_EBIU_AMBCTL1_VAL
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
#define CONFIG_CF_ATASEL_DIS 0x20311800
#define CONFIG_CF_ATASEL_ENA 0x20311802
#if defined(CONFIG_BFIN_TRUE_IDE)
/*
* Note that these settings aren't for the most part used in include/ata.h
* when all of the ATA registers are setup
*/
#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */
#elif defined(CONFIG_BFIN_CF_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
#elif defined(CONFIG_BFIN_HDD_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
#undef CONFIG_SCLK_DIV
#define CONFIG_SCLK_DIV 8
#endif
#endif
/*
* Misc Settings
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
#define CONFIG_SYS_POST_HOTKEYS_GPIO GPIO_PF5
#define CONFIG_POST_BSPEC1_GPIO_LEDS \
GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
#define CONFIG_POST_BSPEC2_GPIO_NAMES \
10, 11, 12, 13,
#define CONFIG_SYS_POST_FLASH_START 11
#define CONFIG_SYS_POST_FLASH_END 71
#endif
/* These are for board tests */
#if 0
#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT \
"autoboot in %d seconds: press space to stop\n", bootdelay
#define CONFIG_AUTOBOOT_STOP_STR " "
#endif
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf537-stamp.h
|
C
|
gpl3
| 7,637
|
/*
* U-boot - Configuration file for BF527 SDP board
*/
#ifndef __CONFIG_BF527_SDP_H__
#define __CONFIG_BF527_SDP_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf527-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 24000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 25
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
#define CONFIG_PLL_LOCKCNT_VAL 0x0200
#define CONFIG_PLL_CTL_VAL 0x2a00
#define CONFIG_VR_CTL_VAL 0x7090
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
#define CONFIG_EBIU_SDRRC_VAL 0x00FE
#define CONFIG_EBIU_SDGCTL_VAL 0x8011998d
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ALL
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* Misc Settings
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_UART_CONSOLE 0
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf527-sdp.h
|
C
|
gpl3
| 3,051
|
/*
* Configuation settings for the Freescale MCF5329 FireEngine board.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5329EVB_H
#define _M5329EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5329 /* define processor type */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#ifdef CONFIG_NANDFLASH_SIZE
# define CONFIG_CMD_NAND
#endif
#define CONFIG_SYS_UNIFY_CACHE
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
#define CONFIG_MCFRTC
#undef RTC_DEBUG
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M5329EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 3ffff;" \
"era 0 3ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x40010000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 80000000
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
#define CONFIG_SYS_MBAR 0xFC000000
#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x53722730
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#ifdef CONFIG_NANDFLASH_SIZE
# define CONFIG_SYS_MAX_NAND_DEVICE 1
# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
# define CONFIG_SYS_NAND_SIZE 1
# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
# define NAND_ALLOW_ERASE_ALL 1
# define CONFIG_JFFS2_NAND 1
# define CONFIG_JFFS2_DEV "nand0"
# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
# define CONFIG_JFFS2_PART_OFFSET 0x00000000
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - CompactFlash and registers
* CS2 - NAND Flash 16, 32, or 64MB
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0
#define CONFIG_SYS_CS0_MASK 0x007f0001
#define CONFIG_SYS_CS0_CTRL 0x00001fa0
#define CONFIG_SYS_CS1_BASE 0x10000000
#define CONFIG_SYS_CS1_MASK 0x001f0001
#define CONFIG_SYS_CS1_CTRL 0x002A3780
#ifdef CONFIG_NANDFLASH_SIZE
#define CONFIG_SYS_CS2_BASE 0x20000000
#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1)
#define CONFIG_SYS_CS2_CTRL 0x00001f60
#endif
#endif /* _M5329EVB_H */
|
1001-study-uboot
|
include/configs/M5329EVB.h
|
C
|
gpl3
| 8,890
|
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*CPU*/
#define CONFIG_440 1
#define CONFIG_XILINX_ML507 1
#include "../board/avnet/v5fx30teval/xparameters.h"
/*Mem Map*/
#define CONFIG_SYS_SDRAM_SIZE_MB 64
/*Env*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0x1A0000
#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
/*Misc*/
#define CONFIG_SYS_PROMPT "v5fx30t:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CONFIG_SYS_FLASH_SIZE (16*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 131
#define MTDIDS_DEFAULT "nor0=v5fx30t-flash"
#define MTDPARTS_DEFAULT "mtdparts=v5fx30t-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/v5fx30teval.h
|
C
|
gpl3
| 1,666
|
/*
* U-boot - Configuration file for BF506F EZ-Kit board
*/
#ifndef __CONFIG_BF506F_EZKIT_H__
#define __CONFIG_BF506F_EZKIT_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf506-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 16
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
#define CONFIG_MEM_SIZE 0
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
#define CONFIG_SYS_MONITOR_BASE (L1_DATA_A_SRAM_END)
#define CONFIG_SYS_MONITOR_LEN (4 * 1024)
#define CONFIG_SYS_MALLOC_LEN (4 * 1024)
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
#define CONFIG_CMD_FLASH
#define CONFIG_MONITOR_IS_IN_RAM
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x400
#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
/*
* Misc Settings
*/
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ICACHE_OFF
#define CONFIG_DCACHE_OFF
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BAUDRATE 115200
#define CONFIG_CMD_MEMORY
#undef CONFIG_GZIP
#undef CONFIG_ZLIB
#undef CONFIG_CMD_BOOTM
#undef CONFIG_BOOTM_RTEMS
#undef CONFIG_BOOTM_LINUX
#endif
|
1001-study-uboot
|
include/configs/bf506f-ezkit.h
|
C
|
gpl3
| 2,485
|
/*
* (C) Copyright 2003
* Texas Instruments.
* Kshitij Gupta <kshitij@ti.com>
* Configuation settings for the TI OMAP Innovator board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */
#define CONFIG_OSK_OMAP5912 1 /* a OSK Board */
#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
/* input clock of PLL */
/* the OMAP5912 OSK has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
/*
*/
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x04800300
#define CONFIG_LAN91C96_EXT_PHY
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
on helen */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \
root=/dev/nfs rw nfsroot=157.87.82.48:\
/home/mwd/myfs/target ip=dhcp"
#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */
#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */
#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */
#define CONFIG_BOOTFILE "uImage" /* file to load */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
* DPLL1. This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
#define PHYS_SRAM 0x20000000
/*-----------------------------------------------------------------------
* FLASH driver setup
*/
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_ENV_IS_IN_FLASH 1
/* addr of environment */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap5912osk.h
|
C
|
gpl3
| 6,853
|
/*
* U-boot - Configuration file for IP04 board (having BF532 processor)
*
* Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
*
* Copyright (c) 2005-2010 Analog Devices Inc.
*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __CONFIG_IP04_H__
#define __CONFIG_IP04_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf532-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 10000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 40
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 3
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x408
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_HOSTNAME IP04
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_NO_SROM
#define CONFIG_DM9000_BASE 0x20100000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
/*
* Flash Settings
*/
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_SYS_NO_FLASH /* we have only NAND */
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_PREBOOT "echo starting from spi flash"
#define CONFIG_ENV_OFFSET 0x30000
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
/*
* NAND Settings
*/
#define CONFIG_NAND_PLAT
#define CONFIG_SYS_NAND_BASE 0x20000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
SSYNC(); \
} while (0)
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R /* needed for MAC address */
#define CONFIG_UART_CONSOLE 0
#undef CONFIG_SHOW_BOOT_PROGRESS
/* Enable this if bootretry required; currently it's disabled */
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_BOOTCOMMAND "run nandboot"
#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/ip04.h
|
C
|
gpl3
| 3,732
|
/*
* U-boot - Configuration file for BF561 Acvilon System On Module
* For more information please go to http://www.niistt.ru/
*/
#ifndef __CONFIG_BF561_ACVILON_H__
#define __CONFIG_BF561_ACVILON_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf561-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 12000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 50
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 128
#define CONFIG_EBIU_SDRRC_VAL 0x300
#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189
#define CONFIG_EBIU_AMGCTL_VAL 0x4e
#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* RTC Settings
*/
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
#define CONFIG_SYS_I2C_DTT_ADDR 0x49
/*#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3*/
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DTT
#if defined(CONFIG_CMD_NET)
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_32_BIT
/* #define CONFIG_SMC911X_16_BIT */
#define CONFIG_SMC911X_BASE 0x28000000
#endif /* (CONFIG_CMD_NET) */
#define CONFIG_HOSTNAME bf561-acvilon
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_SYS_NO_FLASH
/*
* I2C Settings
*/
#define CONFIG_HARD_I2C
/* Use 300kHz speed by default */
#define CONFIG_SYS_I2C_SPEED 0x00
#define CONFIG_PCA9564_I2C
#define CONFIG_PCA9564_BASE 0x2c000000
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_SPI_FLASH
/* #define CONFIG_CMD_SAVEENV */
#define CONFIG_ENV_SECT_SIZE (1056 * 8)
#define CONFIG_ENV_OFFSET ((16 + 256) * 1056)
#define CONFIG_ENV_SIZE (8 * 1056)
/*
* NAND Settings
* We're using NAND_PLAT driver to make things simplier
*/
#define CONFIG_NAND_PLAT
#define CONFIG_CMD_NAND
#define CONFIG_SYS_NAND_BASE 0x24000000
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
#define BFIN_NAND_WRITE(addr, cmd) \
do { \
bfin_write8(addr, cmd); \
SSYNC(); \
} while (0)
#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
/*
* Misc Settings
*/
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BAUDRATE 57600
#define CONFIG_SYS_PROMPT "Acvilon> "
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif /* __CONFIG_BF561_ACVILON_H__ */
|
1001-study-uboot
|
include/configs/bf561-acvilon.h
|
C
|
gpl3
| 4,229
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_MV88F6281GTW_GE_H
#define _CONFIG_MV88F6281GTW_GE_H
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nMarvell-MV88F6281GTW_GE"
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_MV88F6281GTW_GE /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
#define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#define CONFIG_CMD_USB
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/* Unwanted stuffs from mv-common.h */
#undef CONFIG_CMD_EXT2
#undef CONFIG_CMD_JFFS2
#undef CONFIG_CMD_FAT
#undef CONFIG_CMD_UBI
#undef CONFIG_CMD_UBIFS
#undef CONFIG_RBTREE
/*
* Environment variables configurations
*/
#ifdef CONFIG_SPI_FLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
#define CONFIG_ENV_SIZE 0x1000 /* 4k */
#define CONFIG_ENV_ADDR 0x30000
#define CONFIG_ENV_OFFSET 0x30000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"${x_bootcmd_usb}; bootm 0x6400000;"
#define CONFIG_MTDPARTS "spi0.0:512k(uboot)," \
"512k@512k(psm),2m@1m(kernel),13m@3m(rootfs)\0"
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
"x_bootcmd_kernel=cp.b 0xE8100000 0x6400000 0x200000\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=/dev/mtdblock3 ro rootfstype=squashfs\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_MV88E61XX_SWITCH /* Enable mv88e61xx switch driver */
#endif /* CONFIG_CMD_NET */
#endif /* _CONFIG_MV88F6281GTW_GE_H */
|
1001-study-uboot
|
include/configs/mv88f6281gtw_ge.h
|
C
|
gpl3
| 3,184
|
/*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* Hayden Fraser (Hayden.Fraser@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _M5253DEMO_H
#define _M5253DEMO_H
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5253 /* define processor type */
#define CONFIG_M5253DEMO /* define board type */
#define CONFIG_MCFTMR
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
#define CONFIG_BOOTDELAY 5
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#ifdef CONFIG_MONITOR_IS_IN_RAM
# define CONFIG_ENV_OFFSET 0x4000
# define CONFIG_ENV_SECT_SIZE 0x1000
# define CONFIG_ENV_IS_IN_FLASH 1
#else
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
# define CONFIG_ENV_SECT_SIZE 0x1000
# define CONFIG_ENV_IS_IN_FLASH 1
#endif
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_PING
#ifdef CONFIG_CMD_IDE
/* ATA */
# define CONFIG_DOS_PARTITION
# define CONFIG_MAC_PARTITION
# define CONFIG_IDE_RESET 1
# define CONFIG_IDE_PREINIT 1
# define CONFIG_ATAPI
# undef CONFIG_LBA48
# define CONFIG_SYS_IDE_MAXBUS 1
# define CONFIG_SYS_IDE_MAXDEVICE 2
# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
# define CONFIG_SYS_ATA_IDE0_OFFSET 0
# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
#endif
#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300)
# define DM9000_IO CONFIG_DM9000_BASE
# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
# undef CONFIG_DM9000_DEBUG
# define CONFIG_DM9000_BYTE_SWAPPED
# define CONFIG_OVERWRITE_ETHADDR_ONCE
# define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0xff800000 0xff82ffff;" \
"era 0xff800000 0xff82ffff;" \
"cp.b ${loadaddr} 0xff800000 ${filesize};" \
"save\0" \
""
#endif
#define CONFIG_HOSTNAME M5253DEMO
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00000280
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET (0)
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_HZ 1000
#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
# define CONFIG_SYS_PLLCR 0x1243E054
# define CONFIG_SYS_CLK 140000000
#else
# define CONFIG_SYS_PLLCR 0x135a4140
# define CONFIG_SYS_CLK 70000000
#endif
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#ifdef CONFIG_MONITOR_IS_IN_RAM
# define CONFIG_SYS_MONITOR_BASE 0x20000
#else
# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_MONITOR_LEN 0x40000
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
#define FLASH_SST6401B 0x200
#define SST_ID_xF6401B 0x236D236D
#undef CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
/*
* Unable to use CFI driver, due to incompatible sector erase command by SST.
* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
* 0x30 is block erase in SST
*/
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_SIZE 0x800000
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_FLASH_CFI_LEGACY
#else
# define CONFIG_SYS_SST_SECT 2048
# define CONFIG_SYS_SST_SECTSZ 0x1000
# define CONFIG_SYS_FLASH_WRITE_TOUT 500
#endif
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
CF_ADDRMASK(8) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
CF_CACR_DBWE)
/* Port configuration */
#define CONFIG_SYS_FECI2C 0xF0
#define CONFIG_SYS_CS0_BASE 0xFF800000
#define CONFIG_SYS_CS0_MASK 0x007F0021
#define CONFIG_SYS_CS0_CTRL 0x00001D80
#define CONFIG_SYS_CS1_BASE 0xE0000000
#define CONFIG_SYS_CS1_MASK 0x00000001
#define CONFIG_SYS_CS1_CTRL 0x00003DD8
/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
#endif /* _M5253DEMO_H */
|
1001-study-uboot
|
include/configs/M5253DEMO.h
|
C
|
gpl3
| 8,672
|
/*
* Copyright (C) 2006 CodeHermit.
* Bryan O'Donoghue <bodonoghue@codehermit.ie>
*
* Provides support for USB console on the Analogue & Micro Adder87x
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ADDERUSB__
#define __ADDERUSB__
/* Include the board port */
#include "Adder.h"
#define CONFIG_USB_DEVICE /* Include UDC driver */
#define CONFIG_USB_TTY /* Bind the TTY driver to UDC */
#define CONFIG_SYS_USB_EXTC_CLK 0x02 /* Oscillator on EXTC_CLK 2 */
#define CONFIG_SYS_USB_BRG_CLK 0x04 /* or use Baud rate generator 0x04 */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Console is in env */
/* If you have a USB-IF assigned VendorID then you may wish to define
* your own vendor specific values either in BoardName.h or directly in
* usbd_vendor_info.h
*/
/*
#define CONFIG_USBD_MANUFACTURER "CodeHermit.ie"
#define CONFIG_USBD_PRODUCT_NAME "Das U-Boot"
#define CONFIG_USBD_VENDORID 0xFFFF
#define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF
#define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE
*/
#endif /* __ADDERUSB_H__ */
|
1001-study-uboot
|
include/configs/AdderUSB.h
|
C
|
gpl3
| 1,790
|
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* P3060 QDS board configuration file
*/
#define CONFIG_P3060QDS
#define CONFIG_PHYS_64BIT
#define CONFIG_PPC_P3060
#define CONFIG_FSL_QIXIS
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SPI_FLASH_EON
#define CONFIG_SPI_FLASH_SST
#include "corenet_ds.h"
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
/* There is a PCA9547 8-channel I2C-bus multiplexer on P3060QDS board */
#define CONFIG_I2C_MUX
#define CONFIG_I2C_MULTI_BUS
|
1001-study-uboot
|
include/configs/P3060QDS.h
|
C
|
gpl3
| 1,492
|
/*
* (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
*
* (C) Copyright 2004
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Kshitij Gupta <kshitij@ti.com>
*
* Configuration settings for the Freescale i.MX31 PDK board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
#define CONFIG_MX31 /* in a mx31 */
#define CONFIG_MX31_HCLK_FREQ 26000000
#define CONFIG_MX31_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
/*
* Hardware drivers
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_HW_WATCHDOG
#define CONFIG_MXC_GPIO
#define CONFIG_HARD_SPI
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
/* PMIC Controller */
#define CONFIG_PMIC
#define CONFIG_PMIC_SPI
#define CONFIG_PMIC_FSL
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 2
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
#define CONFIG_RTC_MC13XXX
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/***********************************************************
* Command definition
***********************************************************/
#include <config_cmd_default.h>
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SPI
#define CONFIG_CMD_DATE
#define CONFIG_CMD_NAND
/*
* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
* that CFG_NO_FLASH is undefined).
*/
#undef CONFIG_CMD_IMLS
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOOTDELAY 3
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
"bootcmd=run bootcmd_net\0" \
"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
"tftpboot 0x81000000 uImage-mx31; bootm\0" \
"prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \
"nand erase 0x0 0x40000; " \
"nand write 0x81000000 0x0 0x40000\0"
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE 0xB6000000
#define CONFIG_SMC911X_32_BIT
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "MX31PDK U-Boot > "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT)+16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x10000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_GBL_DATA_OFFSET)
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* No NOR flash present */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_OFFSET_REDUND 0x60000
#define CONFIG_ENV_SIZE (128 * 1024)
/*
* NAND driver
*/
#define CONFIG_NAND_MXC
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
/* NAND configuration for the NAND_SPL */
/* Start copying real U-boot from the second page */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
/* Load U-Boot to this address */
#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* Configuration of lowlevel_init.S (clocks and SDRAM) */
#define CCM_CCMR_SETUP 0x074B0BF5
#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
PDR0_MCU_PODF(0))
#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
PLL_MFN(12))
#define ESDMISC_MDDR_SETUP 0x00000004
#define ESDMISC_MDDR_RESET_DL 0x0000000c
#define ESDCFG0_MDDR_SETUP 0x006ac73a
#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
ESDCTL_DSIZ(2) | ESDCTL_BL(1))
#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
#define ESDCTL_RW ESDCTL_SETTINGS
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/mx31pdk.h
|
C
|
gpl3
| 7,207
|
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_GEN_H
#define __CONFIG_GEN_H
/*CPU*/
#define CONFIG_4xx 1
#define CONFIG_440 1
#define CONFIG_XILINX_440 1
#include <configs/xilinx-ppc.h>
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/xilinx-ppc440.h
|
C
|
gpl3
| 1,012
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_SHEEVAPLUG_H
#define _CONFIG_SHEEVAPLUG_H
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nMarvell-Sheevaplug"
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_SHEEVAPLUG /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
#define CONFIG_ENV_ADDR 0x60000
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"${x_bootcmd_usb}; bootm 0x6400000;"
#define CONFIG_MTDPARTS "orion_nand:512k(uboot)," \
"3m@1m(kernel),1m@4m(psm),13m@5m(rootfs) rw\0"
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 mtdparts="CONFIG_MTDPARTS \
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#endif /* CONFIG_CMD_NET */
/*
* File system
*/
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
#endif /* _CONFIG_SHEEVAPLUG_H */
|
1001-study-uboot
|
include/configs/sheevaplug.h
|
C
|
gpl3
| 3,335
|
/*
* Configuation settings for the Freescale MCF5475 board.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5475EVB_H
#define _M5475EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF547x_8x /* define processor family */
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB
#define CONFIG_SLTTMR
#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_HAS_ETH1
# define CONFIG_SYS_DMA_USE_INTSRAM 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 32
# define CONFIG_SYS_TX_ETH_BUFFER 48
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define CONFIG_SYS_FEC1_PINMUX 0
# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif
#ifdef CONFIG_CMD_USB
# define CONFIG_USB_OHCI_NEW
# define CONFIG_USB_STORAGE
# ifndef CONFIG_CMD_PCI
# define CONFIG_CMD_PCI
# endif
# define CONFIG_PCI_OHCI
# define CONFIG_DOS_PARTITION
# undef CONFIG_SYS_USB_OHCI_BOARD_INIT
# undef CONFIG_SYS_USB_OHCI_CPU_INIT
# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#endif
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00008F00
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCI_IO_BUS 0x71000000
#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
#endif
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* FEC_ENET */
#define CONFIG_HOSTNAME M547xEVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off bank 1;" \
"era ff800000 ff83ffff;" \
"cp.b ${loadaddr} ff800000 ${filesize};"\
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
#define CONFIG_SYS_INTSRAMSZ 0x8000
/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_CFG1 0x73711630
#define CONFIG_SYS_SDRAM_CFG2 0x46770000
#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
#ifdef CONFIG_SYS_DRAMSZ1
# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
#else
# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
#endif
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#ifdef CONFIG_SYS_NOR1SZ
# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#else
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
#endif
#endif
/* Configuration for environment
* Environment is not embedded in u-boot but at offset 0x40000 on the flash.
* First time runing may have env crc error warning if there is
* no correct environment on the flash.
*/
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_IN_FLASH 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
CF_CACR_IEC | CF_CACR_ICINVA)
#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
CF_CACR_DEC | CF_CACR_DDCM_P | \
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - NOR Flash
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0xFF800000
#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS0_CTRL 0x00101980
#ifdef CONFIG_SYS_NOR1SZ
#define CONFIG_SYS_CS1_BASE 0xE0000000
#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS1_CTRL 0x00101D80
#endif
#endif /* _M5475EVB_H */
|
1001-study-uboot
|
include/configs/M5475EVB.h
|
C
|
gpl3
| 10,847
|
/*
* Configuration settings for the iDMR board
*
* Based on MC5272C3, r5200 and M5271EVB board configs
* (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _IDMR_H
#define _IDMR_H
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_MCF52x2 /* define processor family */
#define CONFIG_M5271 /* define processor type */
#define CONFIG_IDMR /* define board type */
#undef CONFIG_WATCHDOG /* disable watchdog */
/*
* Default environment settings
*/
#define CONFIG_BOOTCOMMAND "run net_nfs"
#define CONFIG_BOOTDELAY 5
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 19200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_ETHADDR 00:06:3b:01:41:55
#define CONFIG_ETHPRIME
#define CONFIG_IPADDR 192.168.30.1
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_ROOTPATH ""
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_HOSTNAME idmr
#define CONFIG_BOOTFILE "/tftpboot/idmr/uImage"
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root " \
"filesystem over NFS; echo"
#define CONFIG_MCFTMR
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
"$(netmask):$(hostname):$(netdev):off panic=1\0" \
"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip;bootm $(kernel_addr) " \
"$(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"ethact=FEC\0 " \
"update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \
"cp.b 200000 ff800000 $(filesize);" \
"prot on ff800000 ff81ffff\0" \
"load=tftp 200000 $(u-boot)\0" \
"u-boot=/tftpboot/idmr/u-boot.bin\0" \
""
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NET
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*
* Configuration for environment, which occupies third sector in flash.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_ADDR 0xff820000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH
#else /* CONFIG_MONITOR_IS_IN_RAM */
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH
#endif /* !CONFIG_MONITOR_IS_IN_RAM */
#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x00100000
#define CONFIG_SYS_MEMTEST_START 0x400
#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_HZ (50000000 / 64)
#define CONFIG_SYS_CLK 100000000
#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
/*
* Ethernet
*/
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
/*
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE 0xff800000
#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE 0x20000
#else /* !CONFIG_MONITOR_IS_IN_RAM */
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#endif /* CONFIG_MONITOR_IS_IN_RAM */
#define CONFIG_SYS_MONITOR_LEN 0x20000
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/* FLASH organization */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
#define CONFIG_SYS_FLASH_SIZE 0x800000
/*
* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
*/
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/* Port configuration */
#define CONFIG_SYS_FECI2C 0xF0
/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=idmr-0"
#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \
"64k(env)," \
"640k(kernel)," \
"2m(rootfs)," \
"-(user)";
#if defined(CONFIG_CMD_MII)
#error "MII commands don't work on iDMR board and should not be enabled."
#endif
#endif /* _IDMR_H */
|
1001-study-uboot
|
include/configs/idmr.h
|
C
|
gpl3
| 8,075
|
/*
* U-boot - Configuration file for CM-BF533 board
*/
#ifndef __CONFIG_CM_BF533_H__
#define __CONFIG_CM_BF533_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 22
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 8192) - (7 + 2))
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20200300
#define CONFIG_HOSTNAME cm-bf533
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 16
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x10000
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/cm-bf533.h
|
C
|
gpl3
| 2,864
|
/*
* (C) Copyright 2003
* Texas Instruments.
* Kshitij Gupta <kshitij@ti.com>
* Configuation settings for the TI OMAP Innovator board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */
#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
/*
#define CONFIG_DRIVER_SMC9196
#define CONFIG_SMC9196_BASE 0x08000300
#define CONFIG_SMC9196_EXT_PHY
*/
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE 0x08000300
#define CONFIG_LAN91C96_EXT_PHY
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */
#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#include <configs/omap1510.h>
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp"
#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
* This time is further subdivided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define PHYS_SRAM 0x20000000
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE }
/*-----------------------------------------------------------------------
* FLASH driver setup
*/
#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap1510inn.h
|
C
|
gpl3
| 6,725
|
/*
* U-boot - Configuration file for cm-bf548 board
*/
#ifndef __CONFIG_CM_BF548_H__
#define __CONFIG_CM_BF548_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf548-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 21
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
/* Default bank mapping:
* Async Bank 0 - 32MB Burst Flash
* Async Bank 1 - Ethernet
* Async Bank 2 - Nothing
* Async Bank 3 - Nothing
*/
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0x24000000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME cm-bf548
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x20008000
#define CONFIG_ENV_OFFSET 0x8000
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
#ifndef __ADSPBF542__
/* Don't waste time transferring a logo over the UART */
# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
# define CONFIG_VIDEO
# endif
# define CONFIG_DEB_DMA_URGENT
#endif
/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
#endif
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/cm-bf548.h
|
C
|
gpl3
| 3,507
|
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* P5020 DS board configuration file
*
*/
#define CONFIG_P5020DS
#define CONFIG_PHYS_64BIT
#define CONFIG_PPC_P5020
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_SYS_DPAA_RMAN
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h"
|
1001-study-uboot
|
include/configs/P5020DS.h
|
C
|
gpl3
| 1,285
|
/*
* Configuration settings for quick boot from MMC on OMAP3 EVM.
*
* Copyright (C) 2006-2010 Texas Instruments Incorporated - http://www.ti.com/
*
* Author :
* Sanjeev Premi <premi@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __OMAP3_EVM_QUICK_MMC_H
#define __OMAP3_EVM_QUICK_MMC_H
#include <asm/arch/cpu.h>
#include <asm/arch/omap3.h>
/* ----------------------------------------------------------------------------
* Supported U-boot commands
* ----------------------------------------------------------------------------
*/
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
/*
* Board revision is detected by probing the Ethernet chip.
*
* When revision is statically configured via CONFIG_STATIC_BOARD_REV,
* this option can be removed. Generated binary is leaner by ~16Kbytes.
*/
#define CONFIG_CMD_NET
/* ----------------------------------------------------------------------------
* Supported U-boot features
* ----------------------------------------------------------------------------
*/
#define CONFIG_SILENT_CONSOLE
#define CONFIG_ENV_IS_NOWHERE
/* ----------------------------------------------------------------------------
* Supported hardware
* ----------------------------------------------------------------------------
*/
/* MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/* -----------------------------------------------------------------------------
* Include common board configuration
* -----------------------------------------------------------------------------
*/
#include "omap3_evm_common.h"
/* -----------------------------------------------------------------------------
* Default environment
* -----------------------------------------------------------------------------
*/
#define CONFIG_BOOTDELAY 0
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=no\0" \
"silent=1"
#define CONFIG_BOOTCOMMAND \
"mmc rescan 0; " \
"fatload mmc 0 0x82000000 uImage; " \
"bootm 0x82000000;"
/*
* Update the bootargs as necessary e.g. size of memory, partition and fstype
*/
#define CONFIG_BOOTARGS \
"quiet " \
"console=ttyO0,115200n8 " \
"mem=128M " \
"noinitrd " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait"
/*
* SPL
*/
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#endif /* __OMAP3_EVM_QUICK_MMC_H */
|
1001-study-uboot
|
include/configs/omap3_evm_quick_mmc.h
|
C
|
gpl3
| 3,102
|
/*
* U-boot - Configuration file for CSP Minotaur board
*
* Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
* Minotaur config, brushed up for official uClinux dist.
* Parallel flash support disabled, SPI flash boot command
* added ('run flashboot').
*
* Flash image map:
*
* 0x00000000 u-boot bootstrap
* 0x00010000 environment
* 0x00020000 u-boot code
* 0x00030000 uImage.initramfs
*
*/
#ifndef __CONFIG_BF537_MINOTAUR_H__
#define __CONFIG_BF537_MINOTAUR_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
#define CONFIG_MEM_SIZE 32
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_EBIU_SDRRC_VAL 0x306
#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (128 << 10)
/*
* Network Settings
*/
#ifndef __ADSPBF534__
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE 1
#endif
#ifdef CONFIG_BFIN_MAC
#define CONFIG_IPADDR 192.168.0.15
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_SERVERIP 192.168.0.2
#define CONFIG_HOSTNAME bf537-minotaur
#endif
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH "/romfs"
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
/*
* Flash Settings
*/
/* We don't have a parallel flash chip there */
#define CONFIG_SYS_NO_FLASH
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
* I2C settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
/*
* Misc Settings
*/
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_MISC_INIT_R
#define CONFIG_BAUDRATE 57600
#define CONFIG_UART_CONSOLE 0
#define CONFIG_PANIC_HANG 1
#define CONFIG_RTC_BFIN 1
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_LOADS_ECHO 1
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
# define CONFIG_BOOTDELAY -1
#else
# define CONFIG_BOOTDELAY 5
#endif
#include <config_cmd_default.h>
#ifdef CONFIG_BFIN_MAC
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
#else
# undef CONFIG_CMD_NET
# undef CONFIG_CMD_NFS
#endif
#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_SF
#define CONFIG_BOOTCOMMAND "run ramboot"
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
#define CONFIG_SYS_PROMPT "minotaur> "
#define BOOT_ENV_SETTINGS \
"update=tftpboot $(loadaddr) u-boot.ldr;" \
"sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 0x30000;" \
"sf write $(loadaddr) 0 $(filesize)" \
"flashboot=sf read 0x1000000 0x30000 0x320000;" \
"bootm 0x1000000\0"
#ifdef CONFIG_BFIN_MAC
# define NETWORK_ENV_SETTINGS \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):eth0:off\0" \
"ramboot=tftpboot $(loadaddr) linux;" \
"run ramargs;run addip;bootelf\0" \
"nfsboot=tftpboot $(loadaddr) linux;" \
"run nfsargs;run addip;bootelf\0"
#else
# define NETWORK_ENV_SETTINGS
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
NETWORK_ENV_SETTINGS \
"ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
BOOT_ENV_SETTINGS
#endif
|
1001-study-uboot
|
include/configs/bf537-minotaur.h
|
C
|
gpl3
| 4,897
|
/*
* Copyright (C) 2009
* Albin Tonnerre, Free Electrons <albin.tonnerre@free-electrons.com>
*
* Configuation settings for the Calao SBC35-A9G20 board
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* SoC type is defined in boards.cfg */
#include <asm/hardware.h>
#include <asm/sizes.h>
#if defined(CONFIG_SYS_USE_NANDFLASH)
#define CONFIG_ENV_IS_IN_NAND
#else
#define CONFIG_ENV_IS_IN_EEPROM
#endif
#define MACH_TYPE_SBC35_A9G20 1848
#define CONFIG_MACH_TYPE MACH_TYPE_SBC35_A9G20
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_ARCH_CPU_INIT
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT
/* GPIO */
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
#define CONFIG_AT91_GPIO
/* Serial */
#define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
#define CONFIG_USART_ID ATMEL_ID_SYS
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CONFIG_BOOTDELAY 3
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_SOURCE
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_USB
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
/* SPI EEPROM */
#define CONFIG_SPI
#define CONFIG_CMD_SPI
#define CONFIG_ATMEL_SPI
#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
#define CONFIG_CMD_EEPROM
#define CONFIG_SPI_M95XXX
#define CONFIG_SYS_EEPROM_SIZE 0x10000
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
/* SPI RTC */
#define CONFIG_CMD_DATE
#define CONFIG_RTC_M41T94
#define CONFIG_M41T94_SPI_BUS 0
#define CONFIG_M41T94_SPI_CS 0
/* NAND flash */
#define CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH 1
/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_RESET_PHY_R
#define CONFIG_MACB_SEARCH_PHY
/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_FAT
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END 0x23e00000
/* Env in EEPROM, bootstrap + u-boot in NAND*/
#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_OFFSET 0x20
#define CONFIG_ENV_SIZE 0x1000
#endif
/* Env, bootstrap and u-boot in NAND */
#ifdef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x60000
#define CONFIG_ENV_OFFSET_REDUND 0x80000
#define CONFIG_ENV_SIZE 0x20000
#endif
#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000"
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
"root=/dev/mtdblock1 " \
"mtdparts=atmel_nand:16M(kernel)ro," \
"120M(rootfs),-(other) " \
"rw rootfstype=jffs2"
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif
#endif
|
1001-study-uboot
|
include/configs/sbc35_a9g20.h
|
C
|
gpl3
| 5,394
|
/*
* (C) Copyright 2010,2011
* NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
#include "tegra2-common.h"
/* High-level configuration options */
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
#define V_PROMPT "Tegra2 (SeaBoard) # "
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Seaboard"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA2_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
#define CONFIG_BOARD_EARLY_INIT_F
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA2_MMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/seaboard.h
|
C
|
gpl3
| 1,693
|
/*
* Copyright (C) 2009 David Brownell
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Spectrum Digital TMS320DM355 EVM board */
#define DAVINCI_DM355EVM
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM355
/* Memory Info */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
/* Serial Driver info: UART0 for console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0x01c20000
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Ethernet: external DM9000 */
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x04014000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
/* I2C */
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
/* socket has two chipselects, nCE0 gated by address BIT(14) */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
#define CONFIG_DAVINCI_MMC_SD1
#define CONFIG_MMC_MBLOCK
/* USB: OTG connector */
/* NYET -- #define CONFIG_USB_DAVINCI */
/* U-Boot command configuration */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MMC
#endif
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#endif
#ifdef CONFIG_USB_DAVINCI
#define CONFIG_MUSB_HCD
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#else
#undef CONFIG_MUSB_HCD
#undef CONFIG_CMD_USB
#undef CONFIG_USB_STORAGE
#endif
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DM355 EVM # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x3C0000
#undef CONFIG_ENV_IS_IN_FLASH
#endif
#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_CMD_ENV
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
#define CONFIG_ENV_IS_IN_MMC
#undef CONFIG_ENV_IS_IN_FLASH
#endif
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTCOMMAND \
"dhcp;bootm"
#define CONFIG_BOOTARGS \
"console=ttyS0,115200n8 " \
"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
#define CONFIG_TIMESTAMP
#define CONFIG_NET_RETRY_COUNT 10
/* U-Boot memory configuration */
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
/* NAND configuration ... socketed with two chipselects. It normally comes
* with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
* 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
* pretty much demands the 4-bit ECC support.) You can of course swap in
* other parts, including small page ones.
*
* This presents a single read-only partition for all bootloader stuff.
* UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
* some extra space to help cope with bad blocks in that data. Linux
* shouldn't care about its detailed layout, and will probably want to use
* UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to
* override this default partitioning using MTDPARTS and cmdlinepart.
*/
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
#ifdef CONFIG_SYS_NAND_LARGEPAGE
/* Use same layout for 128K/256K blocks; allow some bad blocks */
#define PART_BOOT "2m(bootloader)ro,"
#else
/* Assume 16K erase blocks; allow a few bad ones. */
#define PART_BOOT "512k(bootloader)ro,"
#endif
#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
#define PART_REST "-(filesystem)"
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/davinci_dm355evm.h
|
C
|
gpl3
| 6,926
|
/*
* Copyright (C) 2010 Heiko Schocher <hs@denx.de>
*
* based on:
* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* include common defines/options for all imx27lite related boards */
#include "imx27lite-common.h"
/*
* SoC Configuration
*/
#define CONFIG_MAGNESIUM
#define CONFIG_HOSTNAME magnesium
#define CONFIG_BOARDNAME "Projectiondesign magnesium\n"
/*
* Flash & Environment
*/
#define CONFIG_SYS_FLASH_SECT_SZ 0x8000 /* 64KB sect size */
#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - 0x40000)
#define PHYS_FLASH_SIZE 0x800000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* Env sector Size */
/*
* NAND
*/
#define CONFIG_SYS_NAND_LARGEPAGE
/*
* SD/MMC
*/
#define CONFIG_MXC_MCI_REGS_BASE 0x10013000
/*
* MTD partitions
*/
#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=mxc_nand.0"
#define MTDPARTS_DEFAULT \
"mtdparts=" \
"physmap-flash.0:" \
"256k(U-Boot)," \
"7680k(user)," \
"128k(env1)," \
"128k(env2);" \
"mxc_nand.0:" \
"128k(IPL-SPL)," \
"4m(kernel)," \
"22m(rootfs)," \
"-(userfs)"
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/magnesium.h
|
C
|
gpl3
| 1,850
|
/*
* Configuation settings for the Freescale MCF5208EVBe.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _M5208EVBE_H
#define _M5208EVBE_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF520x /* define processor family */
#define CONFIG_M5208 /* define processor type */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#undef CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 8
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_HAS_ETH1
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x58000
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif /* CONFIG_MCFFEC */
#define CONFIG_HOSTNAME M5208EVBe
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off 0 3ffff;" \
"era 0 3ffff;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
#define CONFIG_SYS_LOAD_ADDR 0x40010000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
#define CONFIG_SYS_PLL_ODR 0x36
#define CONFIG_SYS_PLL_FDR 0x7D
#define CONFIG_SYS_MBAR 0xFC000000
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/* Definitions for initial stack pointer and data area (in DPRAM) */
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1 0x43711630
#define CONFIG_SYS_SDRAM_CFG2 0x56670000
#define CONFIG_SYS_SDRAM_CTRL 0xE1002000
#define CONFIG_SYS_SDRAM_EMOD 0x80010000
#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
/* FLASH organization */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
/*
* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CONFIG_ENV_OFFSET 0x2000
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_IN_FLASH 1
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
CF_CACR_DISD | CF_CACR_INVI | \
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/* Chipselect bank definitions */
/*
* CS0 - NOR Flash
* CS1 - Available
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0
#define CONFIG_SYS_CS0_MASK 0x007F0001
#define CONFIG_SYS_CS0_CTRL 0x00001FA0
#endif /* _M5208EVBE_H */
|
1001-study-uboot
|
include/configs/M5208EVBE.h
|
C
|
gpl3
| 7,576
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Prafulla Wadaskar <prafulla@marvell.com>
*
* (C) Copyright 2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2011
* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.de
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/*
* for linking errors see
* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
*/
#ifndef _CONFIG_KM_KIRKWOOD_H
#define _CONFIG_KM_KIRKWOOD_H
/* include common defines/options for all arm based Keymile boards */
#include "km/km_arm.h"
/*
* Version number information
*/
#ifdef CONFIG_KM_DISABLE_PCI
#define CONFIG_IDENT_STRING "\nKeymile Kirkwood"
#undef CONFIG_KIRKWOOD_PCIE_INIT
#else
#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI"
#endif
#define CONFIG_HOSTNAME km_kirkwood
#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
#define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/
/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */
#define KM_XLX_PROGRAM_B_PIN 39
#endif /* _CONFIG_KM_KIRKWOOD */
|
1001-study-uboot
|
include/configs/km_kirkwood.h
|
C
|
gpl3
| 1,857
|
/*
* Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CONFIG_LACIE_KW_H
#define _CONFIG_LACIE_KW_H
/*
* Machine number definition
*/
#if defined(CONFIG_INETSPACE_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2
#define CONFIG_IDENT_STRING " IS v2"
#elif defined(CONFIG_NETSPACE_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2
#define CONFIG_IDENT_STRING " NS v2"
#elif defined(CONFIG_NETSPACE_MAX_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2
#define CONFIG_IDENT_STRING " NS Max v2"
#elif defined(CONFIG_NET2BIG_V2)
#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2
#define CONFIG_IDENT_STRING " 2Big v2"
#else
#error "Unknown board"
#endif
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
#define CONFIG_KIRKWOOD /* SOC Family Name */
#define CONFIG_KW88F6281 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_ENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_USB
/*
* Core clock definition
*/
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
/*
* SDRAM configuration
*/
#if defined(CONFIG_NET2BIG_V2)
#define CONFIG_NR_DRAM_BANKS 2
#else
#define CONFIG_NR_DRAM_BANKS 1
#endif
#ifdef CONFIG_INETSPACE_V2
/* Different SDRAM configuration and size for Internet Space v2 */
#define CONFIG_SYS_KWD_CONFIG ($(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-is2.cfg)
#endif
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/* Remove or override few declarations from mv-common.h */
#undef CONFIG_RBTREE
#undef CONFIG_ENV_SPI_MAX_HZ
#undef CONFIG_SYS_IDE_MAXBUS
#undef CONFIG_SYS_IDE_MAXDEVICE
#undef CONFIG_SYS_PROMPT
#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
#if defined(CONFIG_NET2BIG_V2)
#define CONFIG_SYS_PROMPT "2big2> "
#else
#define CONFIG_SYS_PROMPT "ns2> "
#endif
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MISC_INIT_R /* Call misc_init_r() to initialize MAC address */
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_NETCONSOLE
#endif
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_NET2BIG_V2)
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif
#endif /* CONFIG_MVSATA_IDE */
/*
* Enable GPI0 support
*/
#define CONFIG_KIRKWOOD_GPIO
/*
* Enable I2C support
*/
#ifdef CONFIG_CMD_I2C
/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */
#endif /* CONFIG_CMD_I2C */
/*
* File systems support
*/
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
/*
* Use the HUSH parser
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Console configuration
*/
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
* Enable device tree support
*/
#define CONFIG_OF_LIBFDT
/*
* Environment variables configurations
*/
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */
#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
#define CONFIG_ENV_ADDR 0x70000
#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTARGS "console=ttyS0,115200"
#define CONFIG_BOOTCOMMAND \
"dhcp && run netconsole; " \
"if run usbload || run diskload; then bootm; fi"
#define CONFIG_EXTRA_ENV_SETTINGS \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"bootfile=uImage\0" \
"loadaddr=0x800000\0" \
"autoload=no\0" \
"netconsole=" \
"set stdin $stdin,nc; " \
"set stdout $stdout,nc; " \
"set stderr $stderr,nc;\0" \
"diskload=ide reset && " \
"ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \
"usbload=usb start && " \
"fatload usb 0:1 $loadaddr /boot/$bootfile\0"
#endif /* _CONFIG_LACIE_KW_H */
|
1001-study-uboot
|
include/configs/lacie_kw.h
|
C
|
gpl3
| 5,058
|
/*
* (C) Copyright 2001
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_ORSG 1 /* ...on a ORSG board */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND "go fff00100"
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ELF
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD 691200
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */
#undef CONFIG_PCI_PNP /* no pci plug-and-play */
/* resource configuration */
#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
* NVRAM organization
*/
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
#else /* Use EEPROM for environment variables */
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
/* total size of a CAT24WC08 is 1024 bytes */
#endif
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC08) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 1 (Flash Bank 1) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
/* Memory Bank 2 (PLD - FPGA-boot) initialization */
#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 3 (PLD - OSL) initialization */
#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
/* Memory Bank 4 (Spartan2 1) initialization */
#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
/* Memory Bank 5 (Spartan2 2) initialization */
#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
/* Memory Bank 6 (Virtex 1) initialization */
#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
/* Memory Bank 7 (Virtex 2) initialization */
#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/ORSG.h
|
C
|
gpl3
| 11,957
|
/*
* (C) Copyright 2011
* Jason Cooper <u-boot@lakedaemon.net>
*
* Based on work by:
* Marvell Semiconductor <www.marvell.com>
* Written-by: Siddarth Gore <gores@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_DREAMPLUG_H
#define _CONFIG_DREAMPLUG_H
/*
* FIXME: This belongs in mach-types.h. However, we only pull mach-types
* from Linus' kernel.org tree. This hasn't been updated primarily due to
* the recent arch/arm reshuffling. So, in the meantime, we'll place it
* here.
*/
#include <asm/mach-types.h>
#ifdef MACH_TYPE_DREAMPLUG
#error "MACH_TYPE_DREAMPLUG has been defined properly, please remove this."
#else
#define MACH_TYPE_DREAMPLUG 3550
#endif
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nMarvell-DreamPlug"
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FAT
#define CONFIG_CMD_SF
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_IDE
#define CONFIG_CMD_DATE
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/*
* Environment variables configurations
*/
#ifdef CONFIG_SPI_FLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH 1
#define CONFIG_HARD_SPI 1
#define CONFIG_KIRKWOOD_SPI 1
#define CONFIG_SPI_FLASH_MACRONIX 1
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50 MHz */
#endif
/*
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x1000 /* 4k */
#define CONFIG_ENV_ADDR 0x100000
#define CONFIG_ENV_OFFSET 0x100000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
"${x_bootcmd_ethernet}; setenv ethact egiga1; " \
"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"bootm 0x6400000;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"x_bootcmd_ethernet=ping 192.168.2.1\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \
"x_bootargs=console=ttyS0,115200\0" \
"x_bootargs_root=root=/dev/sda2 rootdelay=10\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
#endif /* CONFIG_CMD_NET */
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
/*
* RTC driver configuration
*/
#ifdef CONFIG_CMD_DATE
#define CONFIG_RTC_MV
#endif /* CONFIG_CMD_DATE */
#define CONFIG_SYS_ALT_MEMTEST
/*
* display enhanced info about the cpu at boot.
*/
#define CONFIG_DISPLAY_CPUINFO
#endif /* _CONFIG_DREAMPLUG_H */
|
1001-study-uboot
|
include/configs/dreamplug.h
|
C
|
gpl3
| 4,178
|
/*
* U-boot - Configuration file for BF526 EZBrd board
*/
#ifndef __CONFIG_BF526_EZBRD_H__
#define __CONFIG_BF526_EZBRD_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf526-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 16
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
/* This board has a 64meg MT48H32M16 */
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x0267
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_2 | PASR_ALL | TRAS_6 | TRP_4 | TRCD_2 | TWR_2 | PSS)
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
/*
* NAND Settings
* (can't be used same time as ethernet)
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
# define CONFIG_BFIN_NFC
# define CONFIG_BFIN_NFC_BOOTROM_ECC
#endif
#ifdef CONFIG_BFIN_NFC
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
#define CONFIG_DRIVER_NAND_BFIN
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_CMD_NAND
#endif
/*
* Network Settings
*/
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
!defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_RMII
#define CONFIG_NETCONSOLE 1
#endif
#define CONFIG_HOSTNAME bf526-ezbrd
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 71
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#endif
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* USB Settings
*/
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
#define CONFIG_USB
#define CONFIG_MUSB_HCD
#define CONFIG_USB_BLACKFIN
#define CONFIG_USB_STORAGE
#define CONFIG_MUSB_TIMEOUT 100000
#endif
/*
* Misc Settings
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
/* define to enable run status via led */
/* #define CONFIG_STATUS_LED */
#ifdef CONFIG_STATUS_LED
#define CONFIG_GPIO_LED
#define CONFIG_BOARD_SPECIFIC_LED
/* use LED0 to indicate booting/alive */
#define STATUS_LED_BOOT 0
#define STATUS_LED_BIT GPIO_PF8
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
/* use LED1 to indicate crash */
#define STATUS_LED_CRASH 1
#define STATUS_LED_BIT1 GPIO_PG11
#define STATUS_LED_STATE1 STATUS_LED_ON
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
/* #define STATUS_LED_BIT2 GPIO_PG12 */
#endif
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf526-ezbrd.h
|
C
|
gpl3
| 4,658
|
/*
* (C) Copyright 2010
* Texas Instruments Incorporated.
* Steve Sakoman <steve@sakoman.com>
*
* Configuration settings for the TI OMAP4 Panda board.
* See omap4_common.h for OMAP4 common part
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_PANDA_H
#define __CONFIG_PANDA_H
/*
* High Level Configuration Options
*/
#define CONFIG_PANDA 1 /* working with Panda */
#include <configs/omap4_common.h>
/* GPIO */
#define CONFIG_CMD_GPIO
/* ENV related config options */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_PROMPT "Panda # "
#endif /* __CONFIG_PANDA_H */
|
1001-study-uboot
|
include/configs/omap4_panda.h
|
C
|
gpl3
| 1,349
|
/*
* (C) Copyright 2006-2009
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
* Nishanth Menon <nm@ti.com>
* Tom Rix <Tom.Rix@windriver.com>
*
* Configuration settings for the TI OMAP3430 Zoom II board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#define CONFIG_OF_LIBFDT 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
* Zoom2 uses the TL16CP754C on the debug board
*/
#define CONFIG_SERIAL_MULTI 1
/*
* 0 - 1 : first USB with respect to the left edge of the debug board
* 2 - 3 : second USB with respect to the left edge of the debug board
*/
#define ZOOM2_DEFAULT_SERIAL_DEVICE (&zoom2_serial_device0)
#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_REG_SIZE (-2)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {115200}
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* Status LED */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED 1
#define STATUS_LED_BLUE 0
#define STATUS_LED_RED 1
/* Blue */
#define STATUS_LED_BIT STATUS_LED_BLUE
#define STATUS_LED_STATE STATUS_LED_ON
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
/* Red */
#define STATUS_LED_BIT1 STATUS_LED_RED
#define STATUS_LED_STATE1 STATUS_LED_OFF
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
/* Optional value */
#define STATUS_LED_BOOT STATUS_LED_BIT
/* GPIO banks */
#ifdef CONFIG_STATUS_LED
#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */
#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */
#endif
#define CONFIG_OMAP3_GPIO_3 /* board revision */
#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */
/* USB */
#define CONFIG_MUSB_UDC 1
#define CONFIG_USB_OMAP3 1
#define CONFIG_TWL4030_USB 1
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID 0x0451
#define CONFIG_USBD_PRODUCTID 0x5678
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME "Zoom2"
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* TWL4030
*/
#define CONFIG_TWL4030_POWER 1
#define CONFIG_TWL4030_LED 1
/*
* Board NAND Info.
*/
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment information */
#define CONFIG_BOOTDELAY 10
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # "
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE 512
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
/* Memtest from start of memory to 31MB */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)
/* The default load address is the start of memory */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
/* everything, incl board info, in Hz */
#undef CONFIG_SYS_CLKS_IN_HZ
/*
* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using these settings
*/
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_ENV_IS_IN_NAND 1
#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
#define CONFIG_SYS_CACHELINE_SIZE 64
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap3_zoom2.h
|
C
|
gpl3
| 8,051
|
/*
* (C) Copyright 2010 DENX Software Engineering
* Anatolij Gustschin <agust@denx.de>
*
* Common configuration options for MPC5121 based boards
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MPC5121_COMMON_H
#define __MPC5121_COMMON_H
/* Use SRAM for initial stack */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM base */
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE /* Size of area */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END 0x00400000
/*
* Serial console
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_CMDLINE_EDITING 1 /* command line history */
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
#endif /* __MPC5121_COMMON_H */
|
1001-study-uboot
|
include/configs/mpc5121-common.h
|
C
|
gpl3
| 1,769
|
/*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*CPU*/
#define CONFIG_440 1
#define CONFIG_XILINX_ML507 1
#include "../board/xilinx/ml507/xparameters.h"
/*Mem Map*/
#define CONFIG_SYS_SDRAM_SIZE_MB 256
/*Env*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_OFFSET 0x340000
#define CONFIG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CONFIG_ENV_OFFSET)
/*Misc*/
#define CONFIG_SYS_PROMPT "ml507:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 259
#define MTDIDS_DEFAULT "nor0=ml507-flash"
#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)"
/*Generic Configs*/
#include <configs/xilinx-ppc440.h>
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/ml507.h
|
C
|
gpl3
| 1,653
|
/*
* (C) Copyright 2006-2009
* Texas Instruments Incorporated.
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
* Nishanth Menon <nm@ti.com>
*
* Configuration settings for the 3430 TI SDP3430 board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* TODO: REMOVE THE FOLLOWING
* Retained the following till size.h is removed in u-boot
*/
#include <asm/sizes.h>
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/*
* NOTE: these #defines presume standard SDP jumper settings.
* In particular:
* - 26 MHz clock (not 19.2 or 38.4 MHz)
* - Boot from 128MB NOR, not NAND or OneNAND
*
* At this writing, OMAP3 U-Boot support doesn't permit concurrent
* support for all the flash types the board supports.
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#define CONFIG_OF_LIBFDT 1
/*
* Size of malloc() pool
* Total Size Environment - 256k
* Malloc - add 256k
*/
#define CONFIG_ENV_SIZE (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
/*--------------------------------------------------------------------------*/
/*
* Hardware drivers
*/
/*
* TWL4030
*/
#define CONFIG_TWL4030_POWER 1
/*
* serial port - NS16550 compatible
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
* swapped with UART2 via jumpering. Downsides of using J8: it doesn't
* support UART boot (that's only for UART3); it prevents sharing a Linux
* kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
*
* UART boot uses UART3 on J9, and the SDP user's guide says to use
* that for console. Downsides of using J9: you can't use IRDA too;
* since UART3 isn't in the CORE power domain, it may be a bit less
* usable in certain PM-sensitive debug scenarios.
*/
#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
#ifdef CONSOLE_J9
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3 /* UART3 */
#else
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
#define CONFIG_SERIAL1 1 /* UART1 */
#endif
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
/*
* I2C for power management setup
*/
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/* DDR - I use Infineon DDR */
#define CONFIG_OMAP3_INFINEON_DDR 1
/* OMITTED: single 1 Gbit MT29F1G NAND flash */
/*
* NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
*/
#define CONFIG_SYS_FLASH_BASE 0x10000000
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_CFI_WIDTH 2
#define PHYS_FLASH_SIZE (128 << 20)
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10)
#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
/*--------------------------------------------------------------------------*/
/* commands to include */
#include <config_cmd_default.h>
/* Enabled commands */
#define CONFIG_CMD_DHCP /* DHCP Support */
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NET
/* Disabled commands */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMLS /* List all found images */
/*--------------------------------------------------------------------------*/
/*
* MMC boot support
*/
#if defined(CONFIG_CMD_MMC)
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
#endif
/*----------------------------------------------------------------------------
* SMSC9115 Ethernet from SMSC9118 family
*----------------------------------------------------------------------------
*/
#if defined(CONFIG_CMD_NET)
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE DEBUG_BASE
#define CONFIG_LAN91C96_EXT_PHY
#define CONFIG_BOOTP_SEND_HOSTNAME
/*
* BOOTP fields
*/
#define CONFIG_BOOTP_SUBNETMASK 0x00000001
#define CONFIG_BOOTP_GATEWAY 0x00000002
#define CONFIG_BOOTP_HOSTNAME 0x00000004
#define CONFIG_BOOTP_BOOTPATH 0x00000010
#endif /* (CONFIG_CMD_NET) */
/*
* Environment setup
*
* Default boot order: mmc bootscript, MMC uImage, NOR image.
* Network booting environment must be configured at site.
*/
/* allow overwriting serial config and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyS0,115200n8\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"norargs=setenv bootargs console=${console} " \
"root=/dev/mtdblock3 rw " \
"rootfstype=jffs2\0" \
"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from MMC/SD ...; " \
"autoscr ${loadaddr}\0" \
"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
"mmcboot=echo Booting from MMC/SD ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"norboot=echo Booting from NOR ...; " \
"run norargs; " \
"bootm 0x80000\0" \
#define CONFIG_BOOTCOMMAND \
"if mmcinit; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run norboot; " \
"fi; " \
"fi; " \
"else run norboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*--------------------------------------------------------------------------*/
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "OMAP34XX SDP # "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
* a basic sanity check ONLY
* IF you would like to increase coverage, increase the end address
* or run the test with custom options
*/
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20))
/* Default load address */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
/*--------------------------------------------------------------------------*/
/*
* 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
* 32KHz clk, or from external sig. This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* SDRAM Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*--------------------------------------------------------------------------*/
/*
* NOR FLASH usage ... default nCS0:
* - one 256KB sector for U-Boot
* - one 256KB sector for its parameters (not all used)
* - eight sectors (2 MB) for kernel
* - rest for JFFS2
*/
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
/*
* NAND FLASH usage ... default nCS1:
* - four 128KB sectors for X-Loader
* - four 128KB sectors for U-Boot
* - two 128KB sector for its parameters
* - 32 sectors (4 MB) for kernel
* - rest for filesystem
*/
/*
* OneNAND FLASH usage ... default nCS2:
* - four 128KB sectors for X-Loader
* - two 128KB sectors for U-Boot
* - one 128KB sector for its parameters
* - sixteen sectors (2 MB) for kernel
* - rest for filesystem
*/
#define CONFIG_SYS_CACHELINE_SIZE 64
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap3_sdp3430.h
|
C
|
gpl3
| 10,871
|
/*
* U-boot - Configuration file for BF537 STAMP board
*/
#ifndef __CONFIG_BF527_EZKIT_H__
#define __CONFIG_BF527_EZKIT_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf527-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 21
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 10
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL 0x03F6
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
/*
* NAND Settings
* (can't be used same time as ethernet)
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
# define CONFIG_BFIN_NFC
# define CONFIG_BFIN_NFC_BOOTROM_ECC
#endif
#ifdef CONFIG_BFIN_NFC
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
#define CONFIG_DRIVER_NAND_BFIN
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#endif
/*
* Network Settings
*/
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
!defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_RMII
#define CONFIG_NETCONSOLE 1
#endif
#define CONFIG_HOSTNAME bf527-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 259
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* Env Storage Settings
*/
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SIZE 0x20000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET 0x4000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x2000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* USB Settings
*/
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
#define CONFIG_USB
#define CONFIG_MUSB_HCD
#define CONFIG_USB_BLACKFIN
#define CONFIG_USB_STORAGE
#define CONFIG_MUSB_TIMEOUT 100000
#endif
/*
* Video Settings
*/
#ifdef CONFIG_BF527_EZKIT_REV_2_1
# define CONFIG_LQ035Q1_SPI_BUS 0
# define CONFIG_LQ035Q1_SPI_CS 7
#endif
/*
* Misc Settings
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 1
/* Don't waste time transferring a logo over the UART */
#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
# define CONFIG_VIDEO
#endif
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf527-ezkit.h
|
C
|
gpl3
| 4,482
|
/*
*
* BRIEF MODULE DESCRIPTION
* TI H2 and P2 Debug Board hardware map
*
* Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
* Author: MPC-Data Limited
* Dave Peverley
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
#define __INCLUDED_H2_P2_DBH_BOARD_H
#include <asm/sizes.h>
/*
* The Debug board is designed to function with the P2 Sample, H2
* Sample and 1610 Innovator boards. The main difference AFAICT is
* the chip selects used with each system ;
*
* P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
* H2 Sample : CS1a is used to select the CPLD registers.
*
*/
/***************************************************************************
* CPLD Registers
**************************************************************************/
#define H2DBG_CPLD_REVISION 0x04000010
#define H2DBG_BOARD_REVISION 0x04000012
#define H2DBG_GPIO_REGISTER 0x04000014
#define H2DBG_LED_CONTROL 0x04000016
#define H2DBG_MISC_INPUT 0x04000018
#define H2DBG_LAN_STATUS 0x0400001A
#define H2DBG_LAN_RESET 0x0400001C
#define H2DBG_ETH_REG_BASE 0x04000300
/***************************************************************************
* Ethernet Control Registers
* These are for the LAN91C96 on the debug board
**************************************************************************/
/* Bank 0 in IO space */
#define ETH_TCR (H2DBG_ETH_REG_BASE + 0x00) /* Transmit Control Register */
#define ETH_EPH_STATUS (H2DBG_ETH_REG_BASE + 0x02) /* EPH Status Register */
#define ETH_RCR (H2DBG_ETH_REG_BASE + 0x04) /* Receive Control Register */
#define ETH_COUNTER (H2DBG_ETH_REG_BASE + 0x06) /* Counter Register */
#define ETH_MIR (H2DBG_ETH_REG_BASE + 0x08) /* Memory Information Register */
#define ETH_MCR (H2DBG_ETH_REG_BASE + 0x0A) /* Memory Configuration Register */
/* Bank 1 in IO space */
#define ETH_CONFIG (H2DBG_ETH_REG_BASE + 0x00) /* Configuration Register */
#define ETH_BASE (H2DBG_ETH_REG_BASE + 0x02) /* Base Address Register */
#define ETH_IA0 (H2DBG_ETH_REG_BASE + 0x04) /* Individual Address Register - 0 */
#define ETH_IA1 (H2DBG_ETH_REG_BASE + 0x05) /* Individual Address Register - 1 */
#define ETH_IA2 (H2DBG_ETH_REG_BASE + 0x06) /* Individual Address Register - 2 */
#define ETH_IA3 (H2DBG_ETH_REG_BASE + 0x07) /* Individual Address Register - 3 */
#define ETH_IA4 (H2DBG_ETH_REG_BASE + 0x08) /* Individual Address Register - 4 */
#define ETH_IA5 (H2DBG_ETH_REG_BASE + 0x09) /* Individual Address Register - 5 */
#define ETH_GEN_PURPOSE (H2DBG_ETH_REG_BASE + 0x0A) /* General Address Registers */
#define ETH_CONTROL (H2DBG_ETH_REG_BASE + 0x0B) /* Control Register */
/* Bank 2 in IO space */
#define ETH_MMU (H2DBG_ETH_REG_BASE + 0x00) /* MMU Command Register */
#define ETH_AUTO_TX_START (H2DBG_ETH_REG_BASE + 0x01) /* Auto Tx Start Register */
#define ETH_PNR (H2DBG_ETH_REG_BASE + 0x02) /* Packet Number Register */
#define ETH_ARR (H2DBG_ETH_REG_BASE + 0x03) /* Allocation Result Register */
#define ETH_FIFO (H2DBG_ETH_REG_BASE + 0x04) /* FIFO Ports Register */
#define ETH_POINTER (H2DBG_ETH_REG_BASE + 0x06) /* Pointer Register */
#define ETH_DATA_HIGH (H2DBG_ETH_REG_BASE + 0x08) /* Data High Register */
#define ETH_DATA_LOW (H2DBG_ETH_REG_BASE + 0x0A) /* Data Low Register */
#define ETH_INT_STATS (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Status Register - RO */
#define ETH_INT_ACK (H2DBG_ETH_REG_BASE + 0x0C) /* Interrupt Acknowledge Register -WO */
#define ETH_INT_MASK (H2DBG_ETH_REG_BASE + 0x0D) /* Interrupt Mask Register */
#ifndef __ASSEMBLY__
/*
* A couple of utility inlines to aid debugging using the LED's on the
* debug board.
*/
static inline void set_led_state(int state)
{
static unsigned long hw_led_state = 0;
volatile unsigned short *led_address = (volatile unsigned short *)0x04000016;
hw_led_state = ((unsigned long)state);
*((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
}
static inline void spin_up_leds(void)
{
volatile int i, j, k;
for (k = 0; k < 2; k++) {
for (i = 0; i < 16; i++) {
for (j = 0; j < 5000; j++) {
set_led_state(1 << i);
}
}
for (i = 15; i >= 0; i--) {
for (j = 0; j < 5000; j++) {
set_led_state(1 << i);
}
}
}
}
#endif /* ! __ASSEMBLY__ */
#endif /* ! __INCLUDED_H2_P2_DBH_BOARD_H */
|
1001-study-uboot
|
include/configs/h2_p2_dbg_board.h
|
C
|
gpl3
| 5,866
|
/*
* (C) Copyright 2003-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2006
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
* (C) Copyright 2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_CHARON_H
#define __CONFIG_CHARON_H
#define CONFIG_CHARON
#define CONFIG_HOSTNAME charon
#define CONFIG_SYS_GPS_PORT_CONFIG 0x81550414
/* include common defines/options for TQM52xx boards */
#include "TQM5200.h"
/* defines special on charon board */
#undef CONFIG_RTC_MPC5200
#undef CONFIG_CMD_DATE
#undef CUSTOM_ENV_SETTINGS
#define CUSTOM_ENV_SETTINGS \
"bootfile=/tftpboot/charon/uImage\0" \
"fdt_file=/tftpboot/charon/charon.dtb\0" \
"u-boot=/tftpboot/charon/u-boot.bin\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"
/* additional features on charon board */
#define CONFIG_RESET_PHY_R
/*
* I2C configuration
*/
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_TFP410_ADDR 0x38
#define CONFIG_SYS_TFP410_BUS 0
/*
* FPGA configuration
*/
#define CONFIG_SYS_CS3_START 0xE8000000
#define CONFIG_SYS_CS3_SIZE 0x80000 /* 512 KByte */
/*
* CS3 Config Register Init:
* CS3 Enabled
* AddrBus: 8bits
* DataBus: 4bytes
* Multiplexed: Yes
* MuxBank: 00
*/
#define CONFIG_SYS_CS3_CFG 0x00009310
#endif /* __CONFIG_CHARON_H */
|
1001-study-uboot
|
include/configs/charon.h
|
C
|
gpl3
| 2,185
|
/*
* U-Boot - Common settings for Analog Devices boards
*/
#ifndef __CONFIG_BFIN_ADI_COMMON_H__
#define __CONFIG_BFIN_ADI_COMMON_H__
/*
* Command Settings
*/
#ifndef _CONFIG_CMD_DEFAULT_H
# include <config_cmd_default.h>
# if ADI_CMDS_NETWORK
# define CONFIG_CMD_DHCP
# define CONFIG_BOOTP_SUBNETMASK
# define CONFIG_BOOTP_GATEWAY
# define CONFIG_BOOTP_DNS
# define CONFIG_BOOTP_NTPSERVER
# define CONFIG_BOOTP_RANDOM_DELAY
# define CONFIG_KEEP_SERVERADDR
# define CONFIG_CMD_DNS
# define CONFIG_CMD_PING
# ifdef CONFIG_BFIN_MAC
# define CONFIG_CMD_MII
# endif
# else
# undef CONFIG_CMD_BOOTD
# undef CONFIG_CMD_NET
# undef CONFIG_CMD_NFS
# endif
# ifdef CONFIG_LIBATA
# define CONFIG_CMD_FAT
# define CONFIG_CMD_SATA
# define CONFIG_DOS_PARTITION
# endif
# ifdef CONFIG_MMC
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
# define CONFIG_CMD_MMC
# define CONFIG_DOS_PARTITION
# endif
# ifdef CONFIG_MMC_SPI
# define CONFIG_CMD_MMC_SPI
# endif
# ifdef CONFIG_USB
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
# define CONFIG_CMD_USB
# define CONFIG_CMD_USB_STORAGE
# define CONFIG_DOS_PARTITION
# endif
# if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN)
# define CONFIG_CMD_NAND
# define CONFIG_CMD_NAND_LOCK_UNLOCK
# endif
# ifdef CONFIG_POST
# define CONFIG_CMD_DIAG
# endif
# ifdef CONFIG_RTC_BFIN
# define CONFIG_CMD_DATE
# if ADI_CMDS_NETWORK
# define CONFIG_CMD_SNTP
# endif
# endif
# ifdef CONFIG_SPI
# define CONFIG_CMD_EEPROM
# endif
# if defined(CONFIG_BFIN_SPI) || defined(CONFIG_SOFT_SPI)
# define CONFIG_CMD_SPI
# endif
# ifdef CONFIG_SPI_FLASH
# define CONFIG_CMD_SF
# endif
# if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
# define CONFIG_CMD_I2C
# define CONFIG_SOFT_I2C_READ_REPEATED_START
# endif
# ifdef CONFIG_SYS_NO_FLASH
# undef CONFIG_CMD_FLASH
# undef CONFIG_CMD_IMLS
# else
# define CONFIG_CMD_JFFS2
# endif
# ifdef CONFIG_CMD_JFFS2
# define CONFIG_JFFS2_SUMMARY
# endif
# define CONFIG_CMD_BOOTLDR
# define CONFIG_CMD_CACHE
# define CONFIG_CMD_CPLBINFO
# define CONFIG_CMD_ELF
# define CONFIG_CMD_GPIO
# define CONFIG_CMD_KGDB
# define CONFIG_CMD_LDRINFO
# define CONFIG_CMD_REGINFO
# define CONFIG_CMD_STRINGS
# if defined(__ADSPBF51x__) || defined(__ADSPBF52x__) || defined(__ADSPBF54x__)
# define CONFIG_CMD_OTP
# define CONFIG_CMD_SPIBOOTLDR
# endif
#endif
/*
* Console Settings
*/
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE 1
#define CONFIG_LOADS_ECHO 1
#define CONFIG_JTAG_CONSOLE
#define CONFIG_SILENT_CONSOLE
#ifndef CONFIG_BAUDRATE
# define CONFIG_BAUDRATE 57600
#endif
#ifndef CONFIG_DEBUG_EARLY_SERIAL
# define CONFIG_SERIAL_MULTI
# define CONFIG_SYS_BFIN_UART
#endif
/*
* Debug Settings
*/
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_DEBUG_DUMP 1
#define CONFIG_KALLSYMS 1
#define CONFIG_PANIC_HANG 1
/*
* Env Settings
*/
#ifndef CONFIG_BOOTDELAY
# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
# define CONFIG_BOOTDELAY -1
# else
# define CONFIG_BOOTDELAY 5
# endif
#endif
#ifndef CONFIG_BOOTCOMMAND
# define CONFIG_BOOTCOMMAND "run ramboot"
#endif
#ifdef CONFIG_VIDEO
# define CONFIG_BOOTARGS_VIDEO "console=tty0 "
#else
# define CONFIG_BOOTARGS_VIDEO ""
#endif
#ifndef CONFIG_BOOTARGS_ROOT
# define CONFIG_BOOTARGS_ROOT "/dev/mtdblock0 rw"
#endif
#ifndef FLASHBOOT_ENV_SETTINGS
# define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20100000\0"
#endif
#define CONFIG_BOOTARGS \
"root=" CONFIG_BOOTARGS_ROOT " " \
"clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
"earlyprintk=" \
"serial," \
"uart" MK_STR(CONFIG_UART_CONSOLE) "," \
MK_STR(CONFIG_BAUDRATE) " " \
CONFIG_BOOTARGS_VIDEO \
"console=ttyBF" MK_STR(CONFIG_UART_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
#if defined(CONFIG_CMD_NAND)
# define NAND_ENV_SETTINGS \
"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
"nandboot=" \
"nand read $(loadaddr) 0x20000 0x100000;" \
"run nandargs;" \
"bootm" \
"\0"
#else
# define NAND_ENV_SETTINGS
#endif
#if defined(CONFIG_CMD_NET)
# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
# define UBOOT_ENV_FILE "u-boot.bin"
# else
# define UBOOT_ENV_FILE "u-boot.ldr"
# endif
# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
# ifdef CONFIG_SPI
# define UBOOT_ENV_UPDATE \
"eeprom write $(loadaddr) 0x0 $(filesize)"
# else
# ifndef CONFIG_BFIN_SPI_IMG_SIZE
# define CONFIG_BFIN_SPI_IMG_SIZE 0x40000
# endif
# define UBOOT_ENV_UPDATE \
"sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 " MK_STR(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
"sf write $(loadaddr) 0 $(filesize)"
# endif
# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
# define UBOOT_ENV_UPDATE \
"nand unlock 0 0x40000;" \
"nand erase 0 0x40000;" \
"nand write $(loadaddr) 0 0x40000"
# else
# define UBOOT_ENV_UPDATE \
"protect off 0x20000000 +$(filesize);" \
"erase 0x20000000 +$(filesize);" \
"cp.b $(loadaddr) 0x20000000 $(filesize)"
# endif
# ifdef CONFIG_NETCONSOLE
# define NETCONSOLE_ENV \
"nc=" \
"set ncip ${serverip};" \
"set stdin nc;" \
"set stdout nc;" \
"set stderr nc" \
"\0"
# else
# define NETCONSOLE_ENV
# endif
# define NETWORK_ENV_SETTINGS \
NETCONSOLE_ENV \
\
"ubootfile=" UBOOT_ENV_FILE "\0" \
"update=" \
"tftp $(loadaddr) $(ubootfile);" \
UBOOT_ENV_UPDATE \
"\0" \
"addip=set bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):" \
"$(hostname):eth0:off" \
"\0" \
\
"ramfile=uImage\0" \
"ramargs=set bootargs " CONFIG_BOOTARGS "\0" \
"ramboot=" \
"tftp $(loadaddr) $(ramfile);" \
"run ramargs;" \
"run addip;" \
"bootm" \
"\0" \
\
"nfsfile=vmImage\0" \
"nfsargs=set bootargs " \
"root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3" \
"\0" \
"nfsboot=" \
"tftp $(loadaddr) $(nfsfile);" \
"run nfsargs;" \
"run addip;" \
"bootm" \
"\0"
#else
# define NETWORK_ENV_SETTINGS
#endif
#ifndef BOARD_ENV_SETTINGS
# define BOARD_ENV_SETTINGS
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
NAND_ENV_SETTINGS \
NETWORK_ENV_SETTINGS \
FLASHBOOT_ENV_SETTINGS \
BOARD_ENV_SETTINGS
/*
* Network Settings
*/
#ifdef CONFIG_CMD_NET
# define CONFIG_NETMASK 255.255.255.0
# ifndef CONFIG_IPADDR
# define CONFIG_IPADDR 192.168.0.15
# define CONFIG_GATEWAYIP 192.168.0.1
# define CONFIG_SERVERIP 192.168.0.2
# endif
# ifndef CONFIG_ROOTPATH
# define CONFIG_ROOTPATH "/romfs"
# endif
# ifdef CONFIG_CMD_DHCP
# ifndef CONFIG_SYS_AUTOLOAD
# define CONFIG_SYS_AUTOLOAD "no"
# endif
# endif
# define CONFIG_IP_DEFRAG
# define CONFIG_NET_RETRY_COUNT 20
#endif
/*
* Flash Settings
*/
#define CONFIG_FLASH_SHOW_PROGRESS 45
/*
* SPI Settings
*/
#ifdef CONFIG_SPI_FLASH_ALL
# define CONFIG_SPI_FLASH_ATMEL
# define CONFIG_SPI_FLASH_EON
# define CONFIG_SPI_FLASH_MACRONIX
# define CONFIG_SPI_FLASH_SPANSION
# define CONFIG_SPI_FLASH_SST
# define CONFIG_SPI_FLASH_STMICRO
# define CONFIG_SPI_FLASH_WINBOND
#endif
/*
* I2C Settings
*/
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
# ifndef CONFIG_SYS_I2C_SPEED
# define CONFIG_SYS_I2C_SPEED 50000
# endif
# ifndef CONFIG_SYS_I2C_SLAVE
# define CONFIG_SYS_I2C_SLAVE 0
# endif
#endif
/*
* Misc Settings
*/
#ifndef CONFIG_BOARD_SIZE_LIMIT
# define CONFIG_BOARD_SIZE_LIMIT $$(( 256 * 1024 ))
#endif
#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
#define CONFIG_LZMA
#define CONFIG_MONITOR_IS_IN_RAM
#endif
|
1001-study-uboot
|
include/configs/bfin_adi_common.h
|
C
|
gpl3
| 7,394
|
/*
* (C) Copyright 2005-2008
* Samsung Electronics,
* Kyungmin Park <kyungmin.park@samsung.com>
*
* Configuration settings for the 2420 Samsung Apollon board.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP2420 1 /* which is in a 2420 */
#define CONFIG_OMAP2420_APOLLON 1
#define CONFIG_APOLLON 1
#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */
#define CONFIG_ONENAND_U_BOOT y
/* Clock config to target*/
#define PRCM_CONFIG_I 1
/* #define PRCM_CONFIG_II 1 */
/* Boot method */
/* uncomment if you use NOR boot */
/* #define CONFIG_SYS_NOR_BOOT 1 */
/* uncomment if you use NOR on CS3 */
/* #define CONFIG_SYS_USE_NOR 1 */
#ifdef CONFIG_SYS_NOR_BOOT
#undef CONFIG_SYS_USE_NOR
#define CONFIG_SYS_USE_NOR 1
#endif
/* uncommnet if you want to use UBI */
#define CONFIG_SYS_USE_UBI
#include <asm/arch/omap2420.h> /* get chip and board defs */
#define V_SCLK 12000000
/* input clock of PLL */
/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
#define CONFIG_SYS_CLK_FREQ V_SCLK
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
#define CONFIG_ENV_SIZE_FLEX SZ_256K
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M)
/*
* Hardware drivers
*/
/*
* SMC91c96 Etherent
*/
#define CONFIG_LAN91C96
#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300)
#define CONFIG_LAN91C96_EXT_PHY
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* UART1 on H4 */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_ONENAND
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#endif
#undef CONFIG_CMD_SOURCE
#ifndef CONFIG_SYS_USE_NOR
# undef CONFIG_CMD_FLASH
# undef CONFIG_CMD_IMLS
#endif
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTDELAY 1
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.116.25
#define CONFIG_SERVERIP 192.168.116.1
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_ETHADDR 00:0E:99:00:24:20
#ifdef CONFIG_APOLLON_PLUS
#define CONFIG_SYS_MEM "mem=64M"
#else
#define CONFIG_SYS_MEM "mem=128"
#endif
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_SYS_UBI "ubi.mtd=4"
#else
#define CONFIG_SYS_UBI ""
#endif
#define CONFIG_BOOTARGS "root=/dev/nfs rw " CONFIG_SYS_MEM \
" console=ttyS0,115200n8" \
" ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:" \
"apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2 " \
CONFIG_SYS_UBI
#define CONFIG_EXTRA_ENV_SETTINGS \
"Image=tftp 0x80008000 Image; go 0x80008000\0" \
"zImage=tftp 0x80180000 zImage; go 0x80180000\0" \
"uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \
"uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \
"xloader=tftp 0x80180000 x-load.bin; " \
" cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \
"syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \
"syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \
"norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \
"oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0" \
"onesyncboot=run syncmode oneboot\0" \
"updateb=tftp 0x80180000 u-boot-onenand.bin; " \
" onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \
"ubi=setenv bootargs ${bootargs} ubi.mtd=4 ${mtdparts}; run uImage\0" \
"bootcmd=run uboot\0"
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "Apollon # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
/* default load address */
#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0)
/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
* or by 32KHz clk, or from external sig. This rate is divided by a local
* divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2
#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */
#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE SZ_128K /* regular stack */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
#define PHYS_SDRAM_1_SIZE SZ_128M
#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#ifdef CONFIG_SYS_USE_NOR
/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
# define CONFIG_SYS_FLASH_BASE 0x18000000
# define CONFIG_SYS_MAX_FLASH_BANKS 1
# define CONFIG_SYS_MAX_FLASH_SECT 1024
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* Flash memory is CFI compliant */
# define CONFIG_SYS_FLASH_CFI 1
# define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
/* Use buffered writes (~10x faster) */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 */
/* Use h/w sector protection*/
# define CONFIG_SYS_FLASH_PROTECTION 1
#else /* !CONFIG_SYS_USE_NOR */
# define CONFIG_SYS_NO_FLASH 1
#endif /* CONFIG_SYS_USE_NOR */
/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
#define CONFIG_SYS_ONENAND_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN SZ_256K /* U-Boot image size */
#define CONFIG_ENV_IS_IN_ONENAND 1
#define CONFIG_ENV_ADDR 0x00020000
#define CONFIG_ENV_ADDR_FLEX 0x00040000
#ifdef CONFIG_SYS_USE_UBI
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT "onenand0=onenand"
#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(bootloader)," \
"128k(params)," \
"2m(kernel)," \
"16m(rootfs)," \
"32m(fs)," \
"-(ubifs)"
#endif
#define PHYS_SRAM 0x4020F800
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/apollon.h
|
C
|
gpl3
| 8,258
|
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Spectrum Digital TMS320DM6467 EVM board */
#define DAVINCI_DM6467EVM
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SKIP_LOWLEVEL_INIT
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
/* Clock rates detection */
#ifndef __ASSEMBLY__
extern unsigned int davinci_arm_clk_get(void);
#endif
#define CFG_REFCLK_FREQ 27000000
/* Arm Clock frequency */
#define CONFIG_SYS_CLK_FREQ davinci_arm_clk_get()
/* Timer Input clock freq */
#define CONFIG_SYS_HZ_CLOCK (CONFIG_SYS_CLK_FREQ/2)
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM646X
/* EEPROM definitions for EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */
/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
#define CONFIG_REVISION_TAG
/* Serial Driver info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 4
#define CONFIG_SYS_NS16550_COM1 0x01c20000
#define CONFIG_SYS_NS16550_CLK 24000000
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* I2C Configuration */
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 10
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_CMD_NET
/* Flash & Environment */
#define CONFIG_SYS_NO_FLASH
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, }
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_ENV_OFFSET 0
#else
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */
#endif
/* U-Boot general configuration */
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DM6467 EVM > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm"
#define CONFIG_BOOTARGS \
"mem=120M console=ttyS0,115200n8 " \
"root=/dev/hda1 rw noinitrd ip=dhcp"
/* U-Boot commands */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#ifdef CONFIG_SYS_USE_NAND
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/davinci_dm6467evm.h
|
C
|
gpl3
| 5,122
|
/*
* (C) Copyright 2009
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#if defined(CONFIG_spear300)
#define CONFIG_SPEAR3XX 1
#define CONFIG_SPEAR300 1
#elif defined(CONFIG_spear310)
#define CONFIG_SPEAR3XX 1
#define CONFIG_SPEAR310 1
#elif defined(CONFIG_spear320)
#define CONFIG_SPEAR3XX 1
#define CONFIG_SPEAR320 1
#endif
#include <configs/spear-common.h>
/* Serial Configuration (PL011) */
#define CONFIG_SYS_SERIAL0 0xD0000000
#if defined(CONFIG_SPEAR300)
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
#elif defined(CONFIG_SPEAR310)
#if (CONFIG_CONS_INDEX)
#undef CONFIG_PL011_CLOCK
#define CONFIG_PL011_CLOCK (83 * 1000 * 1000)
#endif
#define CONFIG_SYS_SERIAL1 0xB2000000
#define CONFIG_SYS_SERIAL2 0xB2080000
#define CONFIG_SYS_SERIAL3 0xB2100000
#define CONFIG_SYS_SERIAL4 0xB2180000
#define CONFIG_SYS_SERIAL5 0xB2200000
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1, \
(void *)CONFIG_SYS_SERIAL2, \
(void *)CONFIG_SYS_SERIAL3, \
(void *)CONFIG_SYS_SERIAL4, \
(void *)CONFIG_SYS_SERIAL5 }
#elif defined(CONFIG_SPEAR320)
#if (CONFIG_CONS_INDEX)
#undef CONFIG_PL011_CLOCK
#define CONFIG_PL011_CLOCK (83 * 1000 * 1000)
#endif
#define CONFIG_SYS_SERIAL1 0xA3000000
#define CONFIG_SYS_SERIAL2 0xA4000000
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1, \
(void *)CONFIG_SYS_SERIAL2 }
#endif
#if defined(CONFIG_SPEAR_EMI)
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#if defined(CONFIG_SPEAR310)
#define CONFIG_SYS_FLASH_BASE 0x50000000
#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000
#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000
#define CONFIG_SYS_CS3_FLASH_BASE 0x80000000
#define CONFIG_SYS_CS4_FLASH_BASE 0x90000000
#define CONFIG_SYS_CS5_FLASH_BASE 0xA0000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_CS1_FLASH_BASE, \
CONFIG_SYS_CS2_FLASH_BASE, \
CONFIG_SYS_CS3_FLASH_BASE, \
CONFIG_SYS_CS4_FLASH_BASE, \
CONFIG_SYS_CS5_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 6
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_FLASH_BASE 0x44000000
#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000
#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000
#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_CS1_FLASH_BASE, \
CONFIG_SYS_CS2_FLASH_BASE, \
CONFIG_SYS_CS3_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 4
#endif
#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8)
#define CONFIG_SYS_FLASH_QUIET_TEST 1
#endif
#if defined(CONFIG_SPEAR300)
#define CONFIG_SYS_NAND_BASE (0x80000000)
#elif defined(CONFIG_SPEAR310)
#define CONFIG_SYS_NAND_BASE (0x40000000)
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_NAND_BASE (0x50000000)
#endif
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/spear3xx.h
|
C
|
gpl3
| 3,846
|
/*
* U-boot - Configuration file for CSP Minotaur board
*
* Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
* Minotaur config, brushed up for official uClinux dist.
* Parallel flash support disabled, SPI flash boot command
* added ('run flashboot').
*
* Flash image map:
*
* 0x00000000 u-boot bootstrap
* 0x00010000 environment
* 0x00020000 u-boot code
* 0x00030000 uImage.initramfs
*
*/
#ifndef __CONFIG_BF537_SRV1_H__
#define __CONFIG_BF537_SRV1_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf537-0.2
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 22118400
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
#define CONFIG_MEM_SIZE 32
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_EBIU_SDRRC_VAL 0x2ac
#define CONFIG_EBIU_SDGCTL_VAL 0x91110d
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (384 << 10)
/*
* Network Settings
*/
#ifndef __ADSPBF534__
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE 1
#endif
#ifdef CONFIG_BFIN_MAC
#define CONFIG_IPADDR 192.168.0.15
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_SERVERIP 192.168.0.2
#define CONFIG_HOSTNAME bf537-srv1
#endif
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_ROOTPATH "/romfs"
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */
/*
* Flash Settings
*/
/* We don't have a parallel flash chip there */
#define CONFIG_SYS_NO_FLASH
/*
* SPI Settings
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ 30000000
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x10000
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
* I2C settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 50000
#define CONFIG_SYS_I2C_SLAVE 0
/*
* Misc Settings
*/
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_MISC_INIT_R
#define CONFIG_BAUDRATE 115200
#define CONFIG_UART_CONSOLE 0
#define CONFIG_PANIC_HANG 1
#define CONFIG_RTC_BFIN 1
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_LOADS_ECHO 1
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
# define CONFIG_BOOTDELAY -1
#else
# define CONFIG_BOOTDELAY 5
#endif
#include <config_cmd_default.h>
#ifdef CONFIG_BFIN_MAC
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_PING
#else
# undef CONFIG_CMD_NET
# undef CONFIG_CMD_NFS
#endif
#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_SF
#define CONFIG_BOOTCOMMAND "run flashboot"
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
#define CONFIG_SYS_PROMPT "srv1> "
#define BOOT_ENV_SETTINGS \
"update=tftpboot $(loadaddr) u-boot.ldr;" \
"sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 0x30000;" \
"sf write $(loadaddr) 0 $(filesize)" \
"flashboot=sf read 0x1000000 0x30000 0x320000;" \
"bootm 0x1000000\0"
#ifdef CONFIG_BFIN_MAC
# define NETWORK_ENV_SETTINGS \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
":$(hostname):eth0:off\0" \
"ramboot=tftpboot $(loadaddr) linux;" \
"run ramargs;run addip;bootelf\0" \
"nfsboot=tftpboot $(loadaddr) linux;" \
"run nfsargs;run addip;bootelf\0"
#else
# define NETWORK_ENV_SETTINGS
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
NETWORK_ENV_SETTINGS \
"ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
BOOT_ENV_SETTINGS
#endif
|
1001-study-uboot
|
include/configs/bf537-srv1.h
|
C
|
gpl3
| 4,884
|
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_DRAM_SIZE (128 << 20)
/* Number of bits in a C 'long' on this architecture */
#define CONFIG_SANDBOX_BITS_PER_LONG 64
/*
* Size of malloc() pool, although we don't actually use this yet.
*/
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
#define CONFIG_SYS_PROMPT "=>" /* Command Prompt */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP /* #undef to save memory */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16
/* turn on command-line edit/c/auto */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
#define CONFIG_AUTO_COMPLETE
#define CONFIG_ENV_SIZE 8192
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_HZ 1000
/* Memory things - we don't really want a memory test */
#define CONFIG_SYS_LOAD_ADDR 0x10000000
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000)
#define CONFIG_PHYS_64BIT
/* Size of our emulated memory */
#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
#define CONFIG_SANDBOX_SERIAL
#define CONFIG_SYS_NO_FLASH
/* include default commands */
#include <config_cmd_default.h>
/* We don't have networking support yet */
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#define CONFIG_BOOTARGS ""
#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0"
#endif
|
1001-study-uboot
|
include/configs/sandbox.h
|
C
|
gpl3
| 2,559
|
/*
* Configuation settings for the Freescale MCF5485 FireEngine board.
*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef _M5485EVB_H
#define _M5485EVB_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MCF547x_8x /* define processor family */
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#define CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB
#define CONFIG_SLTTMR
#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
# define CONFIG_MII 1
# define CONFIG_MII_INIT 1
# define CONFIG_HAS_ETH1
# define CONFIG_SYS_DMA_USE_INTSRAM 1
# define CONFIG_SYS_DISCOVER_PHY
# define CONFIG_SYS_RX_ETH_BUFFER 32
# define CONFIG_SYS_TX_ETH_BUFFER 48
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FEC0_PINMUX 0
# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define CONFIG_SYS_FEC1_PINMUX 0
# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
# else
# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
# define CONFIG_IPADDR 192.162.1.2
# define CONFIG_NETMASK 255.255.255.0
# define CONFIG_SERVERIP 192.162.1.1
# define CONFIG_GATEWAYIP 192.162.1.1
# define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif
#ifdef CONFIG_CMD_USB
# define CONFIG_USB_STORAGE
# define CONFIG_DOS_PARTITION
# define CONFIG_USB_OHCI_NEW
# ifndef CONFIG_CMD_PCI
# define CONFIG_CMD_PCI
# endif
/*# define CONFIG_PCI_OHCI*/
# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000
# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#endif
/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C /* I2C with hw support */
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x00008F00
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCI_IO_BUS 0x71000000
#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
#endif
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM
#define CONFIG_HOSTNAME M548xEVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
"prog=prot off bank 1;" \
"era ff800000 ff83ffff;" \
"cp.b ${loadaddr} ff800000 ${filesize};"\
"save\0" \
""
#define CONFIG_PRAM 512 /* 512 KB */
#define CONFIG_SYS_PROMPT "-> "
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#ifdef CONFIG_CMD_KGDB
# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
#define CONFIG_SYS_MBAR 0xF0000000
#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
#define CONFIG_SYS_INTSRAMSZ 0x8000
/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL 0x21
#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_CFG1 0x73711630
#define CONFIG_SYS_SDRAM_CFG2 0x46770000
#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
#define CONFIG_SYS_SDRAM_EMOD 0x40010000
#define CONFIG_SYS_SDRAM_MODE 0x018D0000
#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
#ifdef CONFIG_SYS_DRAMSZ1
# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
#else
# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
#endif
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization ??
*/
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#ifdef CONFIG_SYS_NOR1SZ
# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#else
# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
#endif
#endif
/* Configuration for environment
* Environment is not embedded in u-boot. First time runing may have env
* crc error warning if there is no correct environment on the flash.
*/
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_IS_IN_FLASH 1
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \
CF_CACR_IEC | CF_CACR_ICINVA)
#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
CF_CACR_DEC | CF_CACR_DDCM_P | \
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
/*-----------------------------------------------------------------------
* Chipselect bank definitions
*/
/*
* CS0 - NOR Flash 1, 2, 4, or 8MB
* CS1 - NOR Flash
* CS2 - Available
* CS3 - Available
* CS4 - Available
* CS5 - Available
*/
#define CONFIG_SYS_CS0_BASE 0xFF800000
#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS0_CTRL 0x00101980
#ifdef CONFIG_SYS_NOR1SZ
#define CONFIG_SYS_CS1_BASE 0xE0000000
#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS1_CTRL 0x00101D80
#endif
#endif /* _M5485EVB_H */
|
1001-study-uboot
|
include/configs/M5485EVB.h
|
C
|
gpl3
| 10,479
|
/*
*
* BRIEF MODULE DESCRIPTION
* OMAP730 hardware map
*
* Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
* Author: MPC-Data Limited
* Dave Peverley
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __INCLUDED_OMAP730_H
#define __INCLUDED_OMAP730_H
#include <asm/sizes.h>
/***************************************************************************
* OMAP730 Configuration Registers
**************************************************************************/
#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000))
#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000))
#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002))
#define DSP_CONF ((unsigned int)(0xFFFE1004))
#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008))
#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008))
#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C))
#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010))
#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010))
#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012))
#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014))
#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014))
#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016))
#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018))
#define SPECCTL ((unsigned int)(0xFFFE101C))
#define SPARE1 ((unsigned int)(0xFFFE1020))
#define SPARE2 ((unsigned int)(0xFFFE1024))
#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028))
#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030))
#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060))
#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070))
#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074))
#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078))
#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C))
#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080))
#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084))
#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088))
#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C))
#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090))
#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094))
#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098))
#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C))
#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0))
#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4))
#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4))
#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8))
#define BIST_CONTROL ((unsigned int)(0xFFFE10C0))
#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4))
#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8))
#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0))
#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4))
#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8))
#define DEBUG1 ((unsigned int)(0xFFFE10E0))
#define DEBUG2 ((unsigned int)(0xFFFE10E4))
#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8))
/***************************************************************************
* OMAP730 EMIFS Registers (TRM 2.5.7)
**************************************************************************/
#define TCMIF_BASE 0xFFFECC00
#define EMIFS_LRUREG (TCMIF_BASE + 0x04)
#define EMIFS_CONFIG (TCMIF_BASE + 0x0C)
#define FLASH_CFG_0 (TCMIF_BASE + 0x10)
#define FLASH_CFG_1 (TCMIF_BASE + 0x14)
#define FLASH_CFG_2 (TCMIF_BASE + 0x18)
#define FLASH_CFG_3 (TCMIF_BASE + 0x1C)
#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40)
#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28)
#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C)
#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30)
#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44)
#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48)
#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C)
#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50)
#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54)
#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58)
#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C)
/***************************************************************************
* OMAP730 Interrupt handlers
**************************************************************************/
#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */
#define OMAP_IH2_BASE 0xfffe0000
/***************************************************************************
* OMAP730 Timers
*
* There are three general purpose OS timers in the 730 that can be
* configured in autoreload or one-shot modes.
**************************************************************************/
#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000
/* 32k Timer Registers */
#define TIMER32k_CR 0x08
#define TIMER32k_TVR 0x00
#define TIMER32k_TCR 0x04
/* 32k Timer Control Register definition */
#define TIMER32k_TSS (1<<0)
#define TIMER32k_TRB (1<<1)
#define TIMER32k_INT (1<<2)
#define TIMER32k_ARL (1<<3)
/* MPU Timer base addresses */
#define OMAP730_MPUTIMER_BASE 0xfffec500
#define OMAP730_MPUTIMER_OFF 0x00000100
#define OMAP730_TIMER1_BASE 0xFFFEC500
#define OMAP730_TIMER2_BASE 0xFFFEC600
#define OMAP730_TIMER3_BASE 0xFFFEC700
/* MPU Timer Register offsets */
#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */
#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */
#define READ_TIM 0x08 /* MPU_READ_TIMER */
/* MPU_CNTL_TIMER register bits */
#define MPUTIM_FREE (1<<6)
#define MPUTIM_CLOCK_ENABLE (1<<5)
#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT)
#define MPUTIM_PTV_BIT 2
#define MPUTIM_AR (1<<1)
#define MPUTIM_ST (1<<0)
/***************************************************************************
* OMAP730 GPIO
*
* The GPIO control is split over 6 register bases in the OMAP730 to allow
* access to all the (6 x 32) GPIO pins!
**************************************************************************/
#define OMAP730_GPIO_BASE_1 0xFFFBC000
#define OMAP730_GPIO_BASE_2 0xFFFBC800
#define OMAP730_GPIO_BASE_3 0xFFFBD000
#define OMAP730_GPIO_BASE_4 0xFFFBD800
#define OMAP730_GPIO_BASE_5 0xFFFBE000
#define OMAP730_GPIO_BASE_6 0xFFFBE800
#define GPIO_DATA_INPUT 0x00
#define GPIO_DATA_OUTPUT 0x04
#define GPIO_DIRECTION_CONTROL 0x08
#define GPIO_INTERRUPT_CONTROL 0x0C
#define GPIO_INTERRUPT_MASK 0x10
#define GPIO_INTERRUPT_STATUS 0x14
#define GPIO_DATA_INPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
#define GPIO_DATA_OUTPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
#define GPIO_DIRECTION_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
#define GPIO_INTERRUPT_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
#define GPIO_INTERRUPT_MASK_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
#define GPIO_INTERRUPT_STATUS_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
#define GPIO_DATA_INPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
#define GPIO_DATA_OUTPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
#define GPIO_DIRECTION_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
#define GPIO_INTERRUPT_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
#define GPIO_INTERRUPT_MASK_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
#define GPIO_INTERRUPT_STATUS_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
#define GPIO_DATA_INPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
#define GPIO_DATA_OUTPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
#define GPIO_DIRECTION_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
#define GPIO_INTERRUPT_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
#define GPIO_INTERRUPT_MASK_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
#define GPIO_INTERRUPT_STATUS_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
#define GPIO_DATA_INPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
#define GPIO_DATA_OUTPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
#define GPIO_DIRECTION_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
#define GPIO_INTERRUPT_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
#define GPIO_INTERRUPT_MASK_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
#define GPIO_INTERRUPT_STATUS_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
#define GPIO_DATA_INPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
#define GPIO_DATA_OUTPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
#define GPIO_DIRECTION_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
#define GPIO_INTERRUPT_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
#define GPIO_INTERRUPT_MASK_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
#define GPIO_INTERRUPT_STATUS_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
#define GPIO_DATA_INPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
#define GPIO_DATA_OUTPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
#define GPIO_DIRECTION_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
#define GPIO_INTERRUPT_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
#define GPIO_INTERRUPT_MASK_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
#define GPIO_INTERRUPT_STATUS_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
/***************************************************************************
* OMAP730 Watchdog timers
**************************************************************************/
#define WDTIM_BASE 0xFFFEC800
#define WDTIM_CONTROL (WDTIM_BASE + 0x00) /* MPU_CNTL_TIMER */
#define WDTIM_LOAD (WDTIM_BASE + 0x04) /* MPU_LOAD_TIMER */
#define WDTIM_READ (WDTIM_BASE + 0x04) /* MPU_READ_TIMER */
#define WDTIM_MODE (WDTIM_BASE + 0x08) /* MPU_TIMER_MODE */
/***************************************************************************
* OMAP730 Interrupt Registers
**************************************************************************/
/* Interrupt Register offsets */
#define IRQ_ITR 0x00
#define IRQ_MIR 0x04
#define IRQ_SIR_IRQ 0x10
#define IRQ_SIR_FIQ 0x14
#define IRQ_CONTROL_REG 0x18
#define IRQ_ILR0 0x1C /* ILRx == ILR0 + (0x4 * x) */
#define IRQ_SIR 0x9C /* a.k.a.IRQ_ISR */
#define IRQ_GMIR 0xA0
#define REG_IHL1_MIR (OMAP_IH1_BASE + IRQ_MIR)
#define REG_IHL2_MIR (OMAP_IH2_BASE + IRQ_MIR)
/***************************************************************************
* OMAP730 Intersystem Communication Register (TRM 4.5)
**************************************************************************/
#define ICR_BASE 0xFFFBB800
#define M_ICR (ICR_BASE + 0x00)
#define G_ICR (ICR_BASE + 0x02)
#define M_CTL (ICR_BASE + 0x04)
#define G_CTL (ICR_BASE + 0x06)
#define PM_BA (ICR_BASE + 0x0A)
#define DM_BA (ICR_BASE + 0x0C)
#define RM_BA (ICR_BASE + 0x0E)
#define SSPI_TAS (ICR_BASE + 0x12)
#endif /* ! __INCLUDED_OMAP730_H */
|
1001-study-uboot
|
include/configs/omap730.h
|
C
|
gpl3
| 14,179
|
/* U-boot for BlackVME. (C) Wojtek Skulski 2010.
* The board includes ADSP-BF561 rev. 0.5,
* 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
* Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
* SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
* FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
* Spartan6-LX150 (memory-mapped; both PPIs also connected).
* See http://www.skutek.com
*/
#ifndef __CONFIG_BLACKVME_H__
#define __CONFIG_BLACKVME_H__
#include <asm/config-pre.h>
/* Debugging: Set these options if you're having problems
* #define CONFIG_DEBUG_EARLY_SERIAL
* #define DEBUG
* #define CONFIG_DEBUG_DUMP
* #define CONFIG_DEBUG_DUMP_SYMS
* CONFIG_PANIC_HANG means that the board will not auto-reboot
*/
#define CONFIG_PANIC_HANG 0
/* CPU Options */
#define CONFIG_BFIN_CPU bf561-0.5
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
/*
* CLOCK SETTINGS CAVEAT
* You CANNOT just change the clock settings, esp. the SCLK.
* The SDRAM timing, SPI baud, and the serial UART baud
* use SCLK frequency to set their own frequencies. Therefore,
* if you change the SCLK_DIV, you may also have to adjust
* SDRAM refresh and other timings.
* --------------------------------------------------------------
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* 25 * 8 / 1 = 200 MHz
* 25 * 16 / 1 = 400 MHz
* 25 * 24 / 1 = 600 MHz
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
* 25 * 8 / 2 = 100 MHz
* 25 * 24 / 6 = 100 MHz
* 25 * 24 / 5 = 120 MHz
* 25 * 16 / 3 = 133 MHz
* 25 MHz because the oscillator also feeds the ether chip.
* CONFIG_CLKIN_HZ is 25 MHz written in Hz
* CLKIN_HALF controls the DF bit in PLL_CTL
* 0 = CLKIN 1 = CLKIN / 2
* PLL_BYPASS controls the BYPASS bit in PLL_CTL
* 0 = do not bypass 1 = bypass PLL
* VCO_MULT = MSEL (multiplier) in PLL_CTL
* Values can range from 0-63 (where 0 means 64)
* CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
* SCLK_DIV = system clock divider, 1 to 15
*/
#define CONFIG_CLKIN_HZ 25000000
#define CONFIG_CLKIN_HALF 0
#define CONFIG_PLL_BYPASS 0
#define CONFIG_VCO_MULT 8
#define CONFIG_CCLK_DIV 1
#define CONFIG_SCLK_DIV 2
/*
* Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
* Used in 32-bit mode. 16-bit mode not supported.
* http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
*/
/*
* Network settings using a dedicated 2nd ether card in PC
* Windows will automatically acquire IP of that card
* Then use the dedicated card IP + 1 for the board
* http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
*/
#define CONFIG_DRIVER_AX88180 1
#define AX88180_BASE 0x2c000000
#define CONFIG_CMD_MII /* enable probing PHY */
#define CONFIG_HOSTNAME blackvme /* Bfin board */
#define CONFIG_IPADDR 169.254.144.145 /* Bfin board */
#define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */
#define CONFIG_SERVERIP 169.254.144.144 /* tftp server */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_ROOTPATH "/export/uClinux-dist/romfs" /*NFS*/
#define CFG_AUTOLOAD "no"
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_ENV_OVERWRITE 1 /* enable changing MAC at runtime */
/* Comment out hardcoded MAC to enable MAC storage in EEPROM */
/* # define CONFIG_ETHADDR ff:ee:dd:cc:bb:aa */
/*
* SDRAM settings & memory map
*/
#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
/*
* SDRAM reference page
* http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
* NOTE: BlackVME populates only SDRAM bank 0
*/
/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */
#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */
/* Async memory global settings. (ASRAM, not SDRAM)
* HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
* CLKOUT enabled, all async banks enabled, core has priority
* bank 0&1 16 bit (FPGA)
* bank 2&3 32 bit (ether and USB chips)
*/
#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */
/* Async mem timing: BF561 HRM page 16-12 and 16-15.
* Default values 0xFFC2 FFC2 are the slowest supported.
* Example settings of CONFIG_EBIU_AMBCTL1_VAL
* 1. EZ-KIT settings: 0xFFC2 7BB0
* 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
* See the following page:
* http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
* 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
* AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz
* One extra clock needed because AX88180 is asynchronous to CPU.
*/
/* bank 1 0 */
#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
/* bank 3 2 */
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
/* memory layout */
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_SYS_MALLOC_LEN (384 << 10)
/*
* Serial SPI Flash
* For the M25P64 SCK should be kept < 15 MHz
*/
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET 0x40000
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x40000
#define CONFIG_ENV_SPI_MAX_HZ 15000000
#define CONFIG_SF_DEFAULT_SPEED 15000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
/*
* Interactive command settings
*/
#define CONFIG_SYS_LONGHELP 1
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_AUTO_COMPLETE 1
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CPLBINFO
#define CONFIG_CMD_SF
#define CONFIG_CMD_ELF
/*
* Default: boot from SPI flash.
* "sfboot" is a composite command defined in extra settings
*/
#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTCOMMAND "run sfboot"
/*
* Console settings
*/
#define CONFIG_BAUDRATE 57600
#define CONFIG_LOADS_ECHO 1
#define CONFIG_UART_CONSOLE 0
/*
* U-Boot environment variables. Use "printenv" to examine.
* http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
*/
#define CONFIG_BOOTARGS \
"root=/dev/mtdblock0 rw " \
"clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
"earlyprintk=serial,uart0," \
MK_STR(CONFIG_BAUDRATE) " " \
"console=ttyBF0," MK_STR(CONFIG_BAUDRATE) " "
/* Convenience env variables & commands.
* Reserve kernstart = 0x20000 = 128 kB for U-Boot.
* Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size).
* U-Boot image is saved at flash offset=0.
* Kernel image is saved at flash offset=$kernstart.
* Instructions. Ksave takes about a minute to complete.
* 1. Update U-Boot: run uget; run usave
* 2. Update kernel: run kget; run ksave
* After updating U-Boot also update the kernel per above instructions
* to make the saved environment consistent with the flash.
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernstart=0x20000\0" \
"kernarea=0x500000\0" \
"uget=tftp u-boot.ldr\0" \
"kget=tftp uImage\0" \
"usave=sf probe 2; " \
"sf erase 0 $(kernstart); " \
"sf write $(fileaddr) 0 $(filesize)\0" \
"ksave=sf probe 2; " \
"saveenv; " \
"echo Now patiently wait for the prompt...; " \
"sf erase $(kernstart) $(kernarea); " \
"sf write $(fileaddr) $(kernstart) $(filesize)\0" \
"sfboot=sf probe 2; " \
"sf read $(loadaddr) $(kernstart) $(filesize); " \
"run addip; bootm\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
"$(netmask):$(hostname):eth0:off\0"
/*
* Soft I2C settings (BF561 does not have hard I2C)
* PF12,13 on SPI connector 0.
*/
#ifdef CONFIG_SOFT_I2C
# define CONFIG_CMD_I2C
# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12
# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13
# define CONFIG_SYS_I2C_SPEED 50000
# define CONFIG_SYS_I2C_SLAVE 0xFE
#endif
/*
* No Parallel Flash on this board
*/
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_JFFS2
#undef CONFIG_CMD_FLASH
#endif
|
1001-study-uboot
|
include/configs/blackvme.h
|
C
|
gpl3
| 7,764
|
/*
* (C) Copyright 2010
* Texas Instruments Incorporated.
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*
* Configuration settings for the TI SDP4430 board.
* See omap4_common.h for OMAP4 common part
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_SDP4430_H
#define __CONFIG_SDP4430_H
/*
* High Level Configuration Options
*/
#define CONFIG_4430SDP 1 /* working with SDP */
#include <configs/omap4_common.h>
/* Battery Charger */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_CMD_BAT 1
#endif
/* ENV related config options */
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_ENV_OFFSET 0xE0000
#define CONFIG_CMD_SAVEENV
#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
#endif /* __CONFIG_SDP4430_H */
|
1001-study-uboot
|
include/configs/omap4_sdp4430.h
|
C
|
gpl3
| 1,557
|
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* Copyright (C) 2008 Lyrtech <www.lyrtech.com>
* Copyright (C) 2008 Philip Balister, OpenSDR <philip@opensdr.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Board */
#define SFFSDR
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_USE_NAND
#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */
#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM644X
/* EEPROM definitions for Atmel 24LC64 EEPROM chip */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* Memory Info */
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/* Serial Driver info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* I2C Configuration */
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_OVERWRITE_ETHADDR_ONCE
/* Flash & Environment */
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
/* I2C switch definitions for PCA9543 chip */
#define CONFIG_SYS_I2C_PCA9543_ADDR 0x70
#define CONFIG_SYS_I2C_PCA9543_ADDR_LEN 0 /* Single register. */
#define CONFIG_SYS_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */
/* U-Boot general configuration */
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds. */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print buffer size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* Default Linux kernel
* load address. */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far,
* may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* Linux Information */
#define LINUX_BOOT_PARAM_ADDR 0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS \
"mem=56M " \
"console=ttyS0,115200n8 " \
"root=/dev/nfs rw noinitrd ip=dhcp " \
"nfsroot=${serverip}:/nfsroot/sffsdr " \
"eth0=${ethaddr}"
#define CONFIG_BOOTCOMMAND \
"nand read 87A00000 100000 300000;" \
"bootelf 87A00000"
/* U-Boot commands */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF /* Needed to load Integrity kernel. */
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/davinci_sffsdr.h
|
C
|
gpl3
| 6,065
|
/*
* U-boot - Configuration file for CM-BF561 board
*/
#ifndef __CONFIG_CM_BF561_H__
#define __CONFIG_CM_BF561_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf561-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 64
#define CONFIG_EBIU_SDRRC_VAL ((((CONFIG_SCLK_HZ / 1000) * 64) / 4096) - (7 + 2))
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | PSS | TWR_2 | TRCD_2 | TRP_2 | TRAS_7 | PASR_ALL | CL_3)
#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO | B3_PEN | B2_PEN | B1_PEN | B0_PEN | AMBEN_ALL | AMCKEN)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_BASE 0x24008000 /* AMS1 */
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME cm-bf561
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:cf */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 67
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_OFFSET 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/cm-bf561.h
|
C
|
gpl3
| 2,994
|
/*
* Configuration settings for the Gumstix Overo board.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP34XX 1 /* which is a 34XX */
#define CONFIG_OMAP3_OVERO 1 /* working with overo */
#define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap3.h>
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#undef CONFIG_USE_IRQ /* no support for IRQs */
#define CONFIG_MISC_INIT_R
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#define CONFIG_OF_LIBFDT 1
/*
* Size of malloc() pool
*/
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 3
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
#define CONFIG_SERIAL3 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
115200}
#define CONFIG_GENERIC_MMC 1
#define CONFIG_MMC 1
#define CONFIG_OMAP_HSMMC 1
#define CONFIG_DOS_PARTITION 1
/* DDR - I use Micron DDR */
#define CONFIG_OMAP3_MICRON_DDR 1
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
#define CONFIG_CMD_I2C /* I2C serial bus support */
#define CONFIG_CMD_MMC /* MMC support */
#define CONFIG_CMD_NAND /* NAND support */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_IMLS /* List all found images */
#undef CONFIG_CMD_NFS /* NFS support */
#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C 1
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_SYS_I2C_BUS 0
#define CONFIG_SYS_I2C_BUS_SELECT 1
#define CONFIG_I2C_MULTI_BUS 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
/*
* TWL4030
*/
#define CONFIG_TWL4030_POWER 1
#define CONFIG_TWL4030_LED 1
/*
* Board NAND Info.
*/
#define CONFIG_SYS_NAND_QUIET_TEST 1
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand */
/* at CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV "nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET 0x680000
#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
/* partition */
/* Environment information */
#define CONFIG_BOOTDELAY 5
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"console=ttyO2,115200n8\0" \
"mpurate=500\0" \
"optargs=\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext3 rootwait\0" \
"nandroot=ubi0:rootfs ubi.mtd=4\0" \
"nandrootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"if mmc rescan ${mmcdev}; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#define CONFIG_AUTO_COMPLETE 1
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_PROMPT "Overo # "
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Configure the PISMO */
#define PISMO1_NAND_SIZE GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_ENV_IS_IN_NAND 1
#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
#if defined(CONFIG_CMD_NET)
/*----------------------------------------------------------------------------
* SMSC9211 Ethernet from SMSC9118 family
*----------------------------------------------------------------------------
*/
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE 0x2C000000
#endif /* (CONFIG_CMD_NET) */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE 64
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/omap3_overo.h
|
C
|
gpl3
| 9,123
|
/*
* Copyright (C) 2004 by FS Forth-Systeme GmbH.
* All rights reserved.
* Markus Pietrek <mpietrek@fsforth.de>
*
* Configuation settings for the NetSilicon NS9750 DevBoard
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
#define CONFIG_NS9750 1 /* in an NetSilicon NS9750 SoC */
#define CONFIG_NS9750DEV 1 /* on an NetSilicon NS9750 DevBoard */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 324403200 /* Don't use PLL. SW11-4 off */
#define CPU_CLK_FREQ (CONFIG_SYS_CLK_FREQ/2)
#define AHB_CLK_FREQ (CONFIG_SYS_CLK_FREQ/4)
#define BBUS_CLK_FREQ (CONFIG_SYS_CLK_FREQ/8)
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/*@TODO #define CONFIG_STATUS_LED*/
#define CONFIG_USE_IRQ
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/*
* Hardware drivers
*/
#define CONFIG_NS9750_UART 1 /* use on-chip UART */
/*
* select serial console configuration
*/
#define CONFIG_CONS_INDEX 1 /* Port B */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 38400
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#define CONFIG_CMD_BDI
#define CONFIG_CMD_CONSOLE
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PING
#define CONFIG_BOOTDELAY 3
/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
#define CONFIG_ETHADDR 00:04:f3:ff:ff:fb /*@TODO unset */
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.42.30
#define CONFIG_SERVERIP 192.168.42.1
/*#define CONFIG_BOOTFILE "elinos-lart" */
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "NS9750DEV # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00780000 /* 7,5 MB in DRAM */ /* @TODO */
#define CONFIG_SYS_LOAD_ADDR 0x00600000 /* default load address */ /* @TODO */
#define CONFIG_SYS_HZ (CPU_CLK_FREQ/64)
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define NS9750_ETH_PHY_ADDRESS (0x0000)
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
/* TODO */
#define CONFIG_NR_DRAM_BANKS 2 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
#define PHYS_SDRAM_2 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_2_SIZE 0x00800000 /* 8 MB */
#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* @TODO*/
#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
#if 0
#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
#endif
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#ifdef CONFIG_AMD_LV800
#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
#endif
#ifdef CONFIG_AMD_LV400
#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
#endif
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
/* @TODO */
/*#define CONFIG_ENV_IS_IN_FLASH 1*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
#ifdef CONFIG_STATUS_LED
extern void __led_init(led_id_t mask, int state);
extern void __led_toggle(led_id_t mask);
extern void __led_set(led_id_t mask, int state);
#endif /* CONFIG_STATUS_LED */
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/ns9750dev.h
|
C
|
gpl3
| 6,076
|
/*
* (C) Copyright 2009
* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_SPEAR600 1
#include <configs/spear-common.h>
/* Serial Configuration (PL011) */
#define CONFIG_SYS_SERIAL0 0xD0000000
#define CONFIG_SYS_SERIAL1 0xD0080000
#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1 }
#define CONFIG_SYS_NAND_BASE (0xD2000000)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/spear6xx.h
|
C
|
gpl3
| 1,330
|
/*
* U-boot - Configuration file for CM-BF527 board
*/
#ifndef __CONFIG_CM_BF527_H__
#define __CONFIG_CM_BF527_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf527-0.0
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 21
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000)
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
#define CONFIG_MEM_SIZE 32
#define CONFIG_EBIU_SDRRC_VAL 0x3f8
#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* NAND Settings
* (can't be used sametime as ethernet)
*/
/* #define CONFIG_BFIN_NFC */
#ifdef CONFIG_BFIN_NFC
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_CMD_NAND
#endif
/*
* Network Settings
*/
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
!defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
#define ADI_CMDS_NETWORK 1
#define CONFIG_BFIN_MAC
#define CONFIG_RMII
#define CONFIG_NETCONSOLE 1
#endif
#define CONFIG_HOSTNAME cm-bf527
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 67
/*
* Env Storage Settings
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR 0x20008000
#define CONFIG_ENV_OFFSET 0x8000
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_SECT_SIZE 0x8000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
/*
* I2C Settings
*/
#define CONFIG_BFIN_TWI_I2C 1
#define CONFIG_HARD_I2C 1
/*
* Misc Settings
*/
#define CONFIG_BAUDRATE 115200
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
#define CONFIG_BOOTCOMMAND "run flashboot"
#define FLASHBOOT_ENV_SETTINGS \
"flashboot=flread 20040000 1000000 300000;" \
"bootm 0x1000000\0"
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/cm-bf527.h
|
C
|
gpl3
| 3,513
|
/*
* U-boot - Configuration file for BF533 EZKIT board
*/
#ifndef __CONFIG_BF533_EZKIT_H__
#define __CONFIG_BF533_EZKIT_H__
#include <asm/config-pre.h>
/*
* Processor Settings
*/
#define CONFIG_BFIN_CPU bf533-0.3
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 27000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 22
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 5
/*
* Memory Settings
*/
#define CONFIG_MEM_SIZE 32
/* Early EZKITs had 32megs, but later have 64megs */
#if (CONFIG_MEM_SIZE == 64)
# define CONFIG_MEM_ADD_WDTH 10
#else
# define CONFIG_MEM_ADD_WDTH 9
#endif
#define CONFIG_EBIU_SDRRC_VAL 0x398
#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/*
* Network Settings
*/
#define ADI_CMDS_NETWORK 1
#define CONFIG_SMC91111 1
#define CONFIG_SMC91111_BASE 0x20310300
#define SMC91111_EEPROM_INIT() \
do { \
bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
bfin_write_FIO_FLAG_C(PF1); \
bfin_write_FIO_FLAG_S(PF0); \
SSYNC(); \
} while (0)
#define CONFIG_HOSTNAME bf533-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
/*
* Flash Settings
*/
#define CONFIG_SYS_FLASH_BASE 0x20000000
#define CONFIG_SYS_MAX_FLASH_BANKS 3
#define CONFIG_SYS_MAX_FLASH_SECT 40
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR 0x20030000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define FLASH_TOT_SECT 40
/*
* I2C Settings
*/
#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
/*
* Misc Settings
*/
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE 0
/*
* Pull in common ADI header for remaining command/environment setup
*/
#include <configs/bfin_adi_common.h>
#endif
|
1001-study-uboot
|
include/configs/bf533-ezkit.h
|
C
|
gpl3
| 2,770
|
/*
*
* (C) Copyright 2008
* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
* This work has been supported by: QTechnology http://qtec.com/
*
* (C) Copyright 2008
* Georg Schardt <schardt@team-ctech.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_GEN_H
#define __CONFIG_GEN_H
#include "../board/xilinx/ppc405-generic/xparameters.h"
/* sdram */
#define CONFIG_SYS_SDRAM_SIZE_MB 256
/* environment */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_SYS_ENV_OFFSET 0x3F0000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_ENV_OFFSET)
#define CONFIG_ENV_OVERWRITE 1
/*Misc*/
#define CONFIG_SYS_PROMPT "xlx-ppc405:/# " /* Monitor Command Prompt */
#define CONFIG_PREBOOT "echo U-Boot is up and runnining;"
/*Flash*/
#define CONFIG_SYS_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR
#define CONFIG_SYS_FLASH_SIZE (32*1024*1024)
#define CONFIG_SYS_MAX_FLASH_SECT 71
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define MTDIDS_DEFAULT "nor0=ppc405-flash"
#define MTDPARTS_DEFAULT "mtdpartsa=ppc405-flash:-(user)"
#include <configs/xilinx-ppc405.h>
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/xilinx-ppc405-generic.h
|
C
|
gpl3
| 1,975
|
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* KARO TX25 board - SoC Configuration
*/
#define CONFIG_MX25
#define CONFIG_MX25_CLK32 32000 /* OSC32K frequency */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */
/* NAND BOOT is the only boot method */
#define CONFIG_NAND_U_BOOT
#ifndef MACH_TYPE_TX25
#define MACH_TYPE_TX25 2177
#endif
#define CONFIG_MACH_TYPE MACH_TYPE_TX25
#ifdef CONFIG_NAND_SPL
/* Start copying real U-boot from the second page */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000
#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000)
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_SPARE_SIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#else
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*
* Memory Info
*/
/* malloc() len */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
/*
* Board has 2 32MB banks of DRAM but there is a bug when using
* both so only the first is configured
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE 0x02000000
#if (CONFIG_NR_DRAM_BANKS == 2)
#define PHYS_SDRAM_2 0x90000000
#define PHYS_SDRAM_2_SIZE 0x02000000
#endif
/* 8MB DRAM test */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1+0x0800000)
#define CONFIG_STACKSIZE (256 * 1024) /* regular stack */
/*
* Serial Info
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_MXC_GPIO
/*
* Flash & Environment
*/
/* No NOR flash present */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
#define CONFIG_ENV_SIZE (128 * 1024) /* 128 kB NAND block size */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
/* NAND */
#define CONFIG_NAND_MXC
#define CONFIG_NAND_MXC_V1_1
#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (0xBB000000)
#define CONFIG_JFFS2_NAND
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_64BIT_VSPRINTF
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
/* Print buffer sz */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
/* U-Boot commands */
#include <config_cmd_default.h>
#define CONFIG_CMD_NAND
#define CONFIG_CMD_CACHE
/*
* Ethernet
*/
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0x1f
#define CONFIG_MII
#define CONFIG_CMD_NET
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTDELAY 5
#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define xstr(s) str(s)
#define str(s) #s
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttymxc0,${baudrate}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
"u-boot=tx25/u-boot.bin\0" \
"kernel_addr_r=" xstr(CONFIG_LOADADDR) "\0" \
"hostname=tx25\0" \
"bootfile=tx25/uImage\0" \
"rootpath=/opt/eldk/arm\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"run nfsargs addip addtty addmtd addmisc;" \
"bootm\0" \
"bootcmd=run net_nfs\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \
"upd=run load update\0" \
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/tx25.h
|
C
|
gpl3
| 5,665
|
/*
* (C) Copyright 2009
* Net Insight <www.netinsight.net>
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
*
* Based on sheevaplug.h:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _CONFIG_OPENRD_H
#define _CONFIG_OPENRD_H
/*
* Version number information
*/
#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate"
#else
# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
# define CONFIG_IDENT_STRING "\nOpenRD-Client"
# else
# ifdef CONFIG_BOARD_IS_OPENRD_BASE
# define CONFIG_IDENT_STRING "\nOpenRD-Base"
# else
# error Unknown OpenRD board specified
# endif
# endif
#endif
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_OPENRD_BASE /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#define CONFIG_SYS_MVFS
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_IDE
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
#define CONFIG_ENV_ADDR 0x60000
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"${x_bootcmd_usb}; bootm 0x6400000;"
#define MTDIDS_DEFAULT "nand0=nand_mtd"
#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\
"0x400000@0x100000(uImage),"\
"0x1fb00000@0x500000(rootfs)"
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
"mtdids="MTDIDS_DEFAULT"\0" \
"mtdparts="MTDPARTS_DEFAULT"\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
# ifdef CONFIG_BOARD_IS_OPENRD_BASE
# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
# else
# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
# endif
# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
# define CONFIG_PHY_BASE_ADR 0x0
# define PHY_NO "88E1121"
# else
# define CONFIG_PHY_BASE_ADR 0x8
# define PHY_NO "88E1116"
# endif
#endif /* CONFIG_CMD_NET */
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
#endif /* _CONFIG_OPENRD_BASE_H */
|
1001-study-uboot
|
include/configs/openrd.h
|
C
|
gpl3
| 4,125
|
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define DAVINCI_DM355LEOPARD
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_DISPLAY_CPUINFO
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM355 /* DM355 based board */
/* Memory Info */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
/* Serial Driver info: UART0 for console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0x01c20000
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* Ethernet: external DM9000 */
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0x04000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 16)
/* I2C */
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x10
/* NAND */
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 1
/* U-Boot command configuration */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#endif
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DM355 LEOPARD # "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x3C0000
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE
#endif
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "dhcp;bootm"
#define CONFIG_BOOTARGS \
"console=ttyS0,115200n8 " \
"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
#define CONFIG_TIMESTAMP
#define CONFIG_NET_RETRY_COUNT 10
/* U-Boot memory configuration */
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
#ifdef CONFIG_SYS_NAND_LARGEPAGE
#define PART_BOOT "2m(bootloader)ro,"
#else
/* Assume 16K erase blocks; allow a few bad ones. */
#define PART_BOOT "512k(bootloader)ro,"
#endif
#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
#define PART_REST "-(filesystem)"
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/davinci_dm355leopard.h
|
C
|
gpl3
| 5,096
|
/*
* Copyright (C) 2009 Texas Instruments Incorporated
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* Spectrum Digital TMS320DM365 EVM board */
#define DAVINCI_DM365EVM
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */
#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* SoC Configuration */
#define CONFIG_ARM926EJS /* arm926ejs CPU */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM365
/* Memory Info */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */
/* Serial Driver info: UART0 for console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 0x01c20000
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/* EEPROM definitions for EEPROM on DM365 EVM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* Network Configuration */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/* I2C */
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_PAGE_2K
#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
/* socket has two chipselects, nCE0 gated by address BIT(14) */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_MAX_CHIPS 2
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DAVINCI_MMC
#define CONFIG_DAVINCI_MMC_SD1
#define CONFIG_MMC_MBLOCK
#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
#define PINMUX4_USBDRVBUS_BITSET 0x2000
/* USB Configuration */
#define CONFIG_USB_DAVINCI
#define CONFIG_MUSB_HCD
#ifdef CONFIG_USB_DAVINCI
#define CONFIG_CMD_USB /* include support for usb */
#define CONFIG_CMD_STORAGE /* include support for usb */
#define CONFIG_CMD_FAT /* include support for FAT/storage*/
#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/
#endif
#ifdef CONFIG_MUSB_HCD /* include support for usb host */
#define CONFIG_CMD_USB /* include support for usb cmd */
#define CONFIG_USB_STORAGE /* MSC class support */
#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
#ifdef CONFIG_USB_KEYBOARD /* HID class support */
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#endif /* CONFIG_USB_KEYBOARD */
#endif /* CONFIG_MUSB_HCD */
#ifdef CONFIG_MUSB_UDC
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
#define CONFIG_USBD_VENDORID 0x0451
#define CONFIG_USBD_PRODUCTID 0x5678
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME "DM365VM"
#endif /* CONFIG_MUSB_UDC */
/* U-Boot command configuration */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#ifdef CONFIG_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MMC
#endif
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_NAND
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
#endif
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* U-Boot general configuration */
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "DM36x EVM # " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_LONGHELP
#ifdef CONFIG_NAND_DAVINCI
#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x3C0000
#undef CONFIG_ENV_IS_IN_FLASH
#endif
#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
#define CONFIG_CMD_ENV
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
#define CONFIG_ENV_IS_IN_MMC
#undef CONFIG_ENV_IS_IN_FLASH
#endif
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND \
"dhcp;bootm"
#define CONFIG_BOOTARGS \
"console=ttyS0,115200n8 " \
"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
#define CONFIG_TIMESTAMP
/* U-Boot memory configuration */
#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */
#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */
/* Linux interfacing */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
/* NAND configuration issocketed with two chipselects just like the DM355 EVM.
* It normally comes with a 2GByte SLC part with 2KB pages
* (and 128KB erase blocks); other
* 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC
* pretty much demands the 4-bit ECC support.) You can of course swap in
* other parts, including small page ones.
*/
#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
#ifdef CONFIG_SYS_NAND_LARGEPAGE
/* Use same layout for 128K/256K blocks; allow some bad blocks */
#define PART_BOOT "2m(bootloader)ro,"
#else
/* Assume 16K erase blocks; allow a few bad ones. */
#define PART_BOOT "512k(bootloader)ro,"
#endif
#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */
#define PART_REST "-(filesystem)"
#define MTDPARTS_DEFAULT \
"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/davinci_dm365evm.h
|
C
|
gpl3
| 7,908
|
/*
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Define this to make U-Boot skip low level initialization when loaded
* by initial bootloader. Not required by NAND U-Boot version but IS
* required for a NOR version used to burn the real NOR U-Boot into
* NOR Flash. NAND and NOR support for DaVinci chips is mutually exclusive
* so it is NOT possible to build a U-Boot with both NAND and NOR routines.
* NOR U-Boot is loaded directly from Flash so it must perform all the
* low level initialization itself. NAND version is loaded by an initial
* bootloader (UBL in TI-ese) that performs such an initialization so it's
* skipped in NAND version. The third DaVinci boot mode loads a bootloader
* via UART0 and that bootloader in turn loads and runs U-Boot (or whatever)
* performing low level init prior to loading. All that means we can NOT use
* NAND version to put U-Boot into NOR because it doesn't have NOR support and
* we can NOT use NOR version because it performs low level initialization
* effectively destroying itself in DDR memory. That's why a separate NOR
* version with this define is needed. It is loaded via UART, then one uses
* it to somehow download a proper NOR version built WITHOUT this define to
* RAM (tftp?) and burn it to NOR Flash. I would be probably able to squeeze
* NOR support into the initial bootloader so it won't be needed but DaVinci
* static RAM might be too small for this (I have something like 2Kbytes left
* as of now, without NOR support) so this might've not happened...
*
#define CONFIG_NOR_UART_BOOT
*/
/*=======*/
/* Board */
/*=======*/
#define SONATA_BOARD
#define CONFIG_SYS_NAND_SMALLPAGE
#define CONFIG_SYS_USE_NOR
#define CONFIG_DISPLAY_CPUINFO
#define MACH_TYPE_SONATA 1254
#define CONFIG_MACH_TYPE MACH_TYPE_SONATA
/*===================*/
/* SoC Configuration */
/*===================*/
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
#define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SOC_DM644X
/*====================================================*/
/* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
/* on Sonata/DV_EVM board. No EEPROM on schmoogie. */
/*====================================================*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/*=============*/
/* Memory Info */
/*=============*/
#define CONFIG_SYS_MALLOC_LEN (0x10000 + 128*1024) /* malloc() len */
#define CONFIG_SYS_MEMTEST_START 0x80000000 /* memtest start address */
#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_STACKSIZE (256*1024) /* regular stack */
#define PHYS_SDRAM_1 0x80000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
#define DDR_4BANKS /* 4-bank DDR2 (128MB) */
/*====================*/
/* Serial Driver info */
/*====================*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size, byteorder */
#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK /* Input clock to NS16550 */
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*===================*/
/* I2C Configuration */
/*===================*/
#define CONFIG_HARD_I2C
#define CONFIG_DRIVER_DAVINCI_I2C
#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/
/* Network & Ethernet Configuration */
/*==================================*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/*=====================*/
/* Flash & Environment */
/*=====================*/
#ifdef CONFIG_SYS_USE_NAND
#define CONFIG_NAND_DAVINCI
#define CONFIG_SYS_NAND_CS 2
#undef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_OVERWRITE /* instead if obsoleted forceenv() */
#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
#define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#define CONFIG_SYS_NAND_BASE 0x02000000
#define CONFIG_SYS_NAND_HW_ECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
#elif defined(CONFIG_SYS_USE_NOR)
#ifdef CONFIG_NOR_UART_BOOT
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */
#else
#undef CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ 0x20000 /* 128KB sect size AMD Flash */
#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ*2)
#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SZ
#define PHYS_FLASH_1 0x02000000 /* CS2 Base address */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 /* Flash Base for U-Boot */
#define PHYS_FLASH_SIZE 0x2000000 /* Flash size 32MB */
#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ /* Env sector Size */
#endif
/*==============================*/
/* U-Boot general configuration */
/*==============================*/
#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */
#define CONFIG_MISC_INIT_R
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
#define CONFIG_SYS_PROMPT "U-Boot > " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buffer sz */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* default Linux kernel load address */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, may be later */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/*===================*/
/* Linux Information */
/*===================*/
#define LINUX_BOOT_PARAM_ADDR 0x80000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp"
#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot; bootm 0x2060000"
/*=================*/
/* U-Boot commands */
/*=================*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_EEPROM
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#ifdef CONFIG_SYS_USE_NAND
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_NAND
#elif defined(CONFIG_SYS_USE_NOR)
#define CONFIG_CMD_JFFS2
#else
#error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!"
#endif
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */
|
1001-study-uboot
|
include/configs/davinci_sonata.h
|
C
|
gpl3
| 8,906
|
/*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _UBOOT_CRC_H
#define _UBOOT_CRC_H
/* lib/crc32.c */
uint32_t crc32 (uint32_t, const unsigned char *, uint);
uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint);
uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint);
#endif /* _UBOOT_CRC_H */
|
1001-study-uboot
|
include/u-boot/crc.h
|
C
|
gpl3
| 1,201
|
/*
* This file was transplanted with slight modifications from Linux sources
* (fs/cifs/md5.h) into U-Boot by Bartlomiej Sieka <tur@semihalf.com>.
*/
#ifndef _MD5_H
#define _MD5_H
#include "compiler.h"
struct MD5Context {
__u32 buf[4];
__u32 bits[2];
unsigned char in[64];
};
/*
* Calculate and store in 'output' the MD5 digest of 'len' bytes at
* 'input'. 'output' must have enough space to hold 16 bytes.
*/
void md5 (unsigned char *input, int len, unsigned char output[16]);
/*
* Calculate and store in 'output' the MD5 digest of 'len' bytes at 'input'.
* 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the
* watchdog every 'chunk_sz' bytes of input processed.
*/
void md5_wd (unsigned char *input, int len, unsigned char output[16],
unsigned int chunk_sz);
#endif /* _MD5_H */
|
1001-study-uboot
|
include/u-boot/md5.h
|
C
|
gpl3
| 824
|
/*
* This file is derived from zlib.h and zconf.h from the zlib-1.2.3
* distribution by Jean-loup Gailly and Mark Adler, with some additions
* by Paul Mackerras to aid in implementing Deflate compression and
* decompression for PPP packets.
*/
/*
* ==FILEVERSION 960122==
*
* This marker is used by the Linux installation script to determine
* whether an up-to-date version of this file is already installed.
*/
/* zlib.h -- interface of the 'zlib' general purpose compression library
version 1.2.3, July 18th, 2005
Copyright (C) 1995-2005 Jean-loup Gailly and Mark Adler
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. If you use this software
in a product, an acknowledgment in the product documentation would be
appreciated but is not required.
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
Jean-loup Gailly Mark Adler
jloup@gzip.org madler@alumni.caltech.edu
The data format used by the zlib library is described by RFCs (Request for
Comments) 1950 to 1952 in the files http://www.ietf.org/rfc/rfc1950.txt
(zlib format), rfc1951.txt (deflate format) and rfc1952.txt (gzip format).
*/
#ifndef ZLIB_H
#define ZLIB_H
#ifdef __cplusplus
extern "C" {
#endif
#define ZLIB_VERSION "1.2.3"
#define ZLIB_VERNUM 0x1230
/* #include "zconf.h" */ /* included directly here */
/* zconf.h -- configuration of the zlib compression library
* Copyright (C) 1995-2005 Jean-loup Gailly.
* For conditions of distribution and use, see copyright notice in zlib.h
*/
/* Begin of new zconf.h */
/*
* If you *really* need a unique prefix for all types and library functions,
* compile with -DZ_PREFIX. The "standard" zlib should be compiled without it.
*/
#ifdef Z_PREFIX
# define deflateInit_ z_deflateInit_
# define deflate z_deflate
# define deflateEnd z_deflateEnd
# define inflateInit_ z_inflateInit_
# define inflate z_inflate
# define inflateEnd z_inflateEnd
# define deflateInit2_ z_deflateInit2_
# define deflateSetDictionary z_deflateSetDictionary
# define deflateCopy z_deflateCopy
# define deflateReset z_deflateReset
# define deflateParams z_deflateParams
# define deflateBound z_deflateBound
# define deflatePrime z_deflatePrime
# define inflateInit2_ z_inflateInit2_
# define inflateSetDictionary z_inflateSetDictionary
# define inflateSync z_inflateSync
# define inflateSyncPoint z_inflateSyncPoint
# define inflateCopy z_inflateCopy
# define inflateReset z_inflateReset
# define inflateBack z_inflateBack
# define inflateBackEnd z_inflateBackEnd
# define compress z_compress
# define compress2 z_compress2
# define compressBound z_compressBound
# define uncompress z_uncompress
# define adler32 z_adler32
# define crc32 z_crc32
# define get_crc_table z_get_crc_table
# define zError z_zError
# define alloc_func z_alloc_func
# define free_func z_free_func
# define in_func z_in_func
# define out_func z_out_func
# define Byte z_Byte
# define uInt z_uInt
# define uLong z_uLong
# define Bytef z_Bytef
# define charf z_charf
# define intf z_intf
# define uIntf z_uIntf
# define uLongf z_uLongf
# define voidpf z_voidpf
# define voidp z_voidp
#endif
#if defined(__MSDOS__) && !defined(MSDOS)
# define MSDOS
#endif
#if (defined(OS_2) || defined(__OS2__)) && !defined(OS2)
# define OS2
#endif
#if defined(_WINDOWS) && !defined(WINDOWS)
# define WINDOWS
#endif
#if defined(_WIN32) || defined(_WIN32_WCE) || defined(__WIN32__)
# ifndef WIN32
# define WIN32
# endif
#endif
#if (defined(MSDOS) || defined(OS2) || defined(WINDOWS)) && !defined(WIN32)
# if !defined(__GNUC__) && !defined(__FLAT__) && !defined(__386__)
# ifndef SYS16BIT
# define SYS16BIT
# endif
# endif
#endif
/*
* Compile with -DMAXSEG_64K if the alloc function cannot allocate more
* than 64k bytes at a time (needed on systems with 16-bit int).
*/
#ifdef SYS16BIT
# define MAXSEG_64K
#endif
#ifdef MSDOS
# define UNALIGNED_OK
#endif
#ifdef __STDC_VERSION__
# ifndef STDC
# define STDC
# endif
# if __STDC_VERSION__ >= 199901L
# ifndef STDC99
# define STDC99
# endif
# endif
#endif
#if !defined(STDC) && (defined(__STDC__) || defined(__cplusplus))
# define STDC
#endif
#if !defined(STDC) && (defined(__GNUC__) || defined(__BORLANDC__))
# define STDC
#endif
#if !defined(STDC) && (defined(MSDOS) || defined(WINDOWS) || defined(WIN32))
# define STDC
#endif
#if !defined(STDC) && (defined(OS2) || defined(__HOS_AIX__))
# define STDC
#endif
#if defined(__OS400__) && !defined(STDC) /* iSeries (formerly AS/400). */
# define STDC
#endif
#ifndef STDC
# ifndef const /* cannot use !defined(STDC) && !defined(const) on Mac */
# define const /* note: need a more gentle solution here */
# endif
#endif
/* Some Mac compilers merge all .h files incorrectly: */
#if defined(__MWERKS__)||defined(applec)||defined(THINK_C)||defined(__SC__)
# define NO_DUMMY_DECL
#endif
/* Maximum value for memLevel in deflateInit2 */
#ifndef MAX_MEM_LEVEL
# ifdef MAXSEG_64K
# define MAX_MEM_LEVEL 8
# else
# define MAX_MEM_LEVEL 9
# endif
#endif
/* Maximum value for windowBits in deflateInit2 and inflateInit2.
* WARNING: reducing MAX_WBITS makes minigzip unable to extract .gz files
* created by gzip. (Files created by minigzip can still be extracted by
* gzip.)
*/
#ifndef MAX_WBITS
# define MAX_WBITS 15 /* 32K LZ77 window */
#endif
/* The memory requirements for deflate are (in bytes):
(1 << (windowBits+2)) + (1 << (memLevel+9))
that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values)
plus a few kilobytes for small objects. For example, if you want to reduce
the default memory requirements from 256K to 128K, compile with
make CFLAGS="-O -DMAX_WBITS=14 -DMAX_MEM_LEVEL=7"
Of course this will generally degrade compression (there's no free lunch).
The memory requirements for inflate are (in bytes) 1 << windowBits
that is, 32K for windowBits=15 (default value) plus a few kilobytes
for small objects.
*/
/* Type declarations */
#ifndef OF /* function prototypes */
# ifdef STDC
# define OF(args) args
# else
# define OF(args) ()
# endif
#endif
/* The following definitions for FAR are needed only for MSDOS mixed
* model programming (small or medium model with some far allocations).
* This was tested only with MSC; for other MSDOS compilers you may have
* to define NO_MEMCPY in zutil.h. If you don't need the mixed model,
* just define FAR to be empty.
*/
#ifdef SYS16BIT
# if defined(M_I86SM) || defined(M_I86MM)
/* MSC small or medium model */
# define SMALL_MEDIUM
# ifdef _MSC_VER
# define FAR _far
# else
# define FAR far
# endif
# endif
# if (defined(__SMALL__) || defined(__MEDIUM__))
/* Turbo C small or medium model */
# define SMALL_MEDIUM
# ifdef __BORLANDC__
# define FAR _far
# else
# define FAR far
# endif
# endif
#endif
#if defined(WINDOWS) || defined(WIN32)
/* If building or using zlib as a DLL, define ZLIB_DLL.
* This is not mandatory, but it offers a little performance increase.
*/
# ifdef ZLIB_DLL
# if defined(WIN32) && (!defined(__BORLANDC__) || (__BORLANDC__ >= 0x500))
# ifdef ZLIB_INTERNAL
# define ZEXTERN extern __declspec(dllexport)
# else
# define ZEXTERN extern __declspec(dllimport)
# endif
# endif
# endif /* ZLIB_DLL */
/* If building or using zlib with the WINAPI/WINAPIV calling convention,
* define ZLIB_WINAPI.
* Caution: the standard ZLIB1.DLL is NOT compiled using ZLIB_WINAPI.
*/
# ifdef ZLIB_WINAPI
# ifdef FAR
# undef FAR
# endif
# include <windows.h>
/* No need for _export, use ZLIB.DEF instead. */
/* For complete Windows compatibility, use WINAPI, not __stdcall. */
# define ZEXPORT WINAPI
# ifdef WIN32
# define ZEXPORTVA WINAPIV
# else
# define ZEXPORTVA FAR CDECL
# endif
# endif
#endif
#if defined (__BEOS__)
# ifdef ZLIB_DLL
# ifdef ZLIB_INTERNAL
# define ZEXPORT __declspec(dllexport)
# define ZEXPORTVA __declspec(dllexport)
# else
# define ZEXPORT __declspec(dllimport)
# define ZEXPORTVA __declspec(dllimport)
# endif
# endif
#endif
#ifndef ZEXTERN
# define ZEXTERN extern
#endif
#ifndef ZEXPORT
# define ZEXPORT
#endif
#ifndef ZEXPORTVA
# define ZEXPORTVA
#endif
#ifndef FAR
# define FAR
#endif
#if !defined(__MACTYPES__)
typedef unsigned char Byte; /* 8 bits */
#endif
typedef unsigned int uInt; /* 16 bits or more */
typedef unsigned long uLong; /* 32 bits or more */
#ifdef SMALL_MEDIUM
/* Borland C/C++ and some old MSC versions ignore FAR inside typedef */
# define Bytef Byte FAR
#else
typedef Byte FAR Bytef;
#endif
typedef char FAR charf;
typedef int FAR intf;
typedef uInt FAR uIntf;
typedef uLong FAR uLongf;
#ifdef STDC
typedef void const *voidpc;
typedef void FAR *voidpf;
typedef void *voidp;
#else
typedef Byte const *voidpc;
typedef Byte FAR *voidpf;
typedef Byte *voidp;
#endif
# ifdef VMS
# include <unixio.h> /* for off_t */
# endif
# define z_off_t off_t
#ifndef SEEK_SET
# define SEEK_SET 0 /* Seek from beginning of file. */
# define SEEK_CUR 1 /* Seek from current position. */
# define SEEK_END 2 /* Set file pointer to EOF plus "offset" */
#endif
#ifndef z_off_t
# define z_off_t long
#endif
#if defined(__OS400__)
# define NO_vsnprintf
#endif
#if defined(__MVS__)
# define NO_vsnprintf
# ifdef FAR
# undef FAR
# endif
#endif
/* MVS linker does not support external names larger than 8 bytes */
#if defined(__MVS__)
# pragma map(deflateInit_,"DEIN")
# pragma map(deflateInit2_,"DEIN2")
# pragma map(deflateEnd,"DEEND")
# pragma map(deflateBound,"DEBND")
# pragma map(inflateInit_,"ININ")
# pragma map(inflateInit2_,"ININ2")
# pragma map(inflateEnd,"INEND")
# pragma map(inflateSync,"INSY")
# pragma map(inflateSetDictionary,"INSEDI")
# pragma map(compressBound,"CMBND")
# pragma map(inflate_table,"INTABL")
# pragma map(inflate_fast,"INFA")
# pragma map(inflate_copyright,"INCOPY")
#endif
/* End of new zconf.h */
/*
The 'zlib' compression library provides in-memory compression and
decompression functions, including integrity checks of the uncompressed
data. This version of the library supports only one compression method
(deflation) but other algorithms will be added later and will have the same
stream interface.
Compression can be done in a single step if the buffers are large
enough (for example if an input file is mmap'ed), or can be done by
repeated calls of the compression function. In the latter case, the
application must provide more input and/or consume the output
(providing more output space) before each call.
The compressed data format used by default by the in-memory functions is
the zlib format, which is a zlib wrapper documented in RFC 1950, wrapped
around a deflate stream, which is itself documented in RFC 1951.
The library also supports reading and writing files in gzip (.gz) format
with an interface similar to that of stdio using the functions that start
with "gz". The gzip format is different from the zlib format. gzip is a
gzip wrapper, documented in RFC 1952, wrapped around a deflate stream.
This library can optionally read and write gzip streams in memory as well.
The zlib format was designed to be compact and fast for use in memory
and on communications channels. The gzip format was designed for single-
file compression on file systems, has a larger header than zlib to maintain
directory information, and uses a different, slower check method than zlib.
The library does not install any signal handler. The decoder checks
the consistency of the compressed data, so the library should never
crash even in case of corrupted input.
*/
typedef voidpf (*alloc_func) OF((voidpf opaque, uInt items, uInt size));
typedef void (*free_func) OF((voidpf opaque, voidpf address, uInt size));
typedef void (*cb_func) OF((Bytef *buf, uInt len));
struct internal_state;
typedef struct z_stream_s {
Bytef *next_in; /* next input byte */
uInt avail_in; /* number of bytes available at next_in */
uLong total_in; /* total nb of input bytes read so far */
Bytef *next_out; /* next output byte should be put there */
uInt avail_out; /* remaining free space at next_out */
uLong total_out; /* total nb of bytes output so far */
char *msg; /* last error message, NULL if no error */
struct internal_state FAR *state; /* not visible by applications */
alloc_func zalloc; /* used to allocate the internal state */
free_func zfree; /* used to free the internal state */
voidpf opaque; /* private data object passed to zalloc and zfree */
int data_type; /* best guess about the data type:
binary or text */
cb_func outcb; /* called regularly just before blocks of output */
uLong adler; /* adler32 value of the uncompressed data */
uLong reserved; /* reserved for future use */
} z_stream;
typedef z_stream FAR *z_streamp;
/*
gzip header information passed to and from zlib routines. See RFC 1952
for more details on the meanings of these fields.
*/
typedef struct gz_header_s {
int text; /* true if compressed data believed to be text */
uLong time; /* modification time */
int xflags; /* extra flags (not used when writing a gzip file) */
int os; /* operating system */
Bytef *extra; /* pointer to extra field or Z_NULL if none */
uInt extra_len; /* extra field length (valid if extra != Z_NULL) */
uInt extra_max; /* space at extra (only when reading header) */
Bytef *name; /* pointer to zero-terminated file name or Z_NULL */
uInt name_max; /* space at name (only when reading header) */
Bytef *comment; /* pointer to zero-terminated comment or Z_NULL */
uInt comm_max; /* space at comment (only when reading header) */
int hcrc; /* true if there was or will be a header crc */
int done; /* true when done reading gzip header (not used
when writing a gzip file) */
} gz_header;
typedef gz_header FAR *gz_headerp;
/* constants */
#define Z_NO_FLUSH 0
#define Z_PARTIAL_FLUSH 1 /* will be removed, use Z_SYNC_FLUSH instead */
#define Z_SYNC_FLUSH 2
#define Z_FULL_FLUSH 3
#define Z_FINISH 4
#define Z_BLOCK 5
/* Allowed flush values; see deflate() and inflate() below for details */
#define Z_OK 0
#define Z_STREAM_END 1
#define Z_NEED_DICT 2
#define Z_ERRNO (-1)
#define Z_STREAM_ERROR (-2)
#define Z_DATA_ERROR (-3)
#define Z_MEM_ERROR (-4)
#define Z_BUF_ERROR (-5)
#define Z_VERSION_ERROR (-6)
/* Return codes for the compression/decompression functions. Negative
* values are errors, positive values are used for special but normal events.
*/
#define Z_NO_COMPRESSION 0
#define Z_BEST_SPEED 1
#define Z_BEST_COMPRESSION 9
#define Z_DEFAULT_COMPRESSION (-1)
/* compression levels */
#define Z_FILTERED 1
#define Z_HUFFMAN_ONLY 2
#define Z_RLE 3
#define Z_FIXED 4
#define Z_DEFAULT_STRATEGY 0
/* compression strategy; see deflateInit2() below for details */
#define Z_BINARY 0
#define Z_TEXT 1
#define Z_ASCII Z_TEXT /* for compatibility with 1.2.2 and earlier */
#define Z_UNKNOWN 2
/* Possible values of the data_type field (though see inflate()) */
#define Z_DEFLATED 8
/* The deflate compression method (the only one supported in this version) */
#define Z_NULL 0 /* for initializing zalloc, zfree, opaque */
/* basic functions */
/* The application can compare zlibVersion and ZLIB_VERSION for consistency.
If the first character differs, the library code actually used is
not compatible with the zlib.h header file used by the application.
This check is automatically made by deflateInit and inflateInit.
*/
ZEXTERN int ZEXPORT inflateInit_ OF((z_streamp strm, const char *version,
int stream_size));
ZEXTERN int ZEXPORT inflate OF((z_streamp strm, int flush));
/*
inflate decompresses as much data as possible, and stops when the input
buffer becomes empty or the output buffer becomes full. It may introduce
some output latency (reading input without producing any output) except when
forced to flush.
The detailed semantics are as follows. inflate performs one or both of the
following actions:
- Decompress more input starting at next_in and update next_in and avail_in
accordingly. If not all input can be processed (because there is not
enough room in the output buffer), next_in is updated and processing
will resume at this point for the next call of inflate().
- Provide more output starting at next_out and update next_out and avail_out
accordingly. inflate() provides as much output as possible, until there
is no more input data or no more space in the output buffer (see below
about the flush parameter).
Before the call of inflate(), the application should ensure that at least
one of the actions is possible, by providing more input and/or consuming
more output, and updating the next_* and avail_* values accordingly.
The application can consume the uncompressed output when it wants, for
example when the output buffer is full (avail_out == 0), or after each
call of inflate(). If inflate returns Z_OK and with zero avail_out, it
must be called again after making room in the output buffer because there
might be more output pending.
The flush parameter of inflate() can be Z_NO_FLUSH, Z_SYNC_FLUSH,
Z_FINISH, or Z_BLOCK. Z_SYNC_FLUSH requests that inflate() flush as much
output as possible to the output buffer. Z_BLOCK requests that inflate() stop
if and when it gets to the next deflate block boundary. When decoding the
zlib or gzip format, this will cause inflate() to return immediately after
the header and before the first block. When doing a raw inflate, inflate()
will go ahead and process the first block, and will return when it gets to
the end of that block, or when it runs out of data.
The Z_BLOCK option assists in appending to or combining deflate streams.
Also to assist in this, on return inflate() will set strm->data_type to the
number of unused bits in the last byte taken from strm->next_in, plus 64
if inflate() is currently decoding the last block in the deflate stream,
plus 128 if inflate() returned immediately after decoding an end-of-block
code or decoding the complete header up to just before the first byte of the
deflate stream. The end-of-block will not be indicated until all of the
uncompressed data from that block has been written to strm->next_out. The
number of unused bits may in general be greater than seven, except when
bit 7 of data_type is set, in which case the number of unused bits will be
less than eight.
inflate() should normally be called until it returns Z_STREAM_END or an
error. However if all decompression is to be performed in a single step
(a single call of inflate), the parameter flush should be set to
Z_FINISH. In this case all pending input is processed and all pending
output is flushed; avail_out must be large enough to hold all the
uncompressed data. (The size of the uncompressed data may have been saved
by the compressor for this purpose.) The next operation on this stream must
be inflateEnd to deallocate the decompression state. The use of Z_FINISH
is never required, but can be used to inform inflate that a faster approach
may be used for the single inflate() call.
In this implementation, inflate() always flushes as much output as
possible to the output buffer, and always uses the faster approach on the
first call. So the only effect of the flush parameter in this implementation
is on the return value of inflate(), as noted below, or when it returns early
because Z_BLOCK is used.
If a preset dictionary is needed after this call (see inflateSetDictionary
below), inflate sets strm->adler to the adler32 checksum of the dictionary
chosen by the compressor and returns Z_NEED_DICT; otherwise it sets
strm->adler to the adler32 checksum of all output produced so far (that is,
total_out bytes) and returns Z_OK, Z_STREAM_END or an error code as described
below. At the end of the stream, inflate() checks that its computed adler32
checksum is equal to that saved by the compressor and returns Z_STREAM_END
only if the checksum is correct.
inflate() will decompress and check either zlib-wrapped or gzip-wrapped
deflate data. The header type is detected automatically. Any information
contained in the gzip header is not retained, so applications that need that
information should instead use raw inflate, see inflateInit2() below, or
inflateBack() and perform their own processing of the gzip header and
trailer.
inflate() returns Z_OK if some progress has been made (more input processed
or more output produced), Z_STREAM_END if the end of the compressed data has
been reached and all uncompressed output has been produced, Z_NEED_DICT if a
preset dictionary is needed at this point, Z_DATA_ERROR if the input data was
corrupted (input stream not conforming to the zlib format or incorrect check
value), Z_STREAM_ERROR if the stream structure was inconsistent (for example
if next_in or next_out was NULL), Z_MEM_ERROR if there was not enough memory,
Z_BUF_ERROR if no progress is possible or if there was not enough room in the
output buffer when Z_FINISH is used. Note that Z_BUF_ERROR is not fatal, and
inflate() can be called again with more input and more output space to
continue decompressing. If Z_DATA_ERROR is returned, the application may then
call inflateSync() to look for a good compression block if a partial recovery
of the data is desired.
*/
ZEXTERN int ZEXPORT inflateEnd OF((z_streamp strm));
/*
All dynamically allocated data structures for this stream are freed.
This function discards any unprocessed input and does not flush any
pending output.
inflateEnd returns Z_OK if success, Z_STREAM_ERROR if the stream state
was inconsistent. In the error case, msg may be set but then points to a
static string (which must not be deallocated).
*/
/* Advanced functions */
ZEXTERN int ZEXPORT inflateReset OF((z_streamp strm));
/* utility functions */
/*
The following utility functions are implemented on top of the
basic stream-oriented functions. To simplify the interface, some
default options are assumed (compression level and memory usage,
standard memory allocation functions). The source code of these
utility functions can easily be modified if you need special options.
*/
ZEXTERN uLong ZEXPORT adler32 OF((uLong adler, const Bytef *buf, uInt len));
/*
Update a running Adler-32 checksum with the bytes buf[0..len-1] and
return the updated checksum. If buf is NULL, this function returns
the required initial value for the checksum.
An Adler-32 checksum is almost as reliable as a CRC32 but can be computed
much faster. Usage example:
uLong adler = adler32(0L, Z_NULL, 0);
while (read_buffer(buffer, length) != EOF) {
adler = adler32(adler, buffer, length);
}
if (adler != original_adler) error();
*/
/*
Combine two Adler-32 checksums into one. For two sequences of bytes, seq1
and seq2 with lengths len1 and len2, Adler-32 checksums were calculated for
each, adler1 and adler2. adler32_combine() returns the Adler-32 checksum of
seq1 and seq2 concatenated, requiring only adler1, adler2, and len2.
*/
ZEXTERN uInt ZEXPORT crc32 OF((uInt crc, const Bytef *buf, uInt len));
/*
Update a running CRC-32 with the bytes buf[0..len-1] and return the
updated CRC-32. If buf is NULL, this function returns the required initial
value for the for the crc. Pre- and post-conditioning (one's complement) is
performed within this function so it shouldn't be done by the application.
Usage example:
uLong crc = crc32(0L, Z_NULL, 0);
while (read_buffer(buffer, length) != EOF) {
crc = crc32(crc, buffer, length);
}
if (crc != original_crc) error();
*/
ZEXTERN int ZEXPORT inflateInit2_ OF((z_streamp strm, int windowBits,
const char *version, int stream_size));
#define inflateInit(strm) \
inflateInit_((strm), ZLIB_VERSION, sizeof(z_stream))
#define inflateInit2(strm, windowBits) \
inflateInit2_((strm), (windowBits), ZLIB_VERSION, sizeof(z_stream))
#if !defined(ZUTIL_H) && !defined(NO_DUMMY_DECL)
struct internal_state {int dummy;}; /* hack for buggy compilers */
#endif
#ifdef __cplusplus
}
#endif
#endif /* ZLIB_H */
|
1001-study-uboot
|
include/u-boot/zlib.h
|
C
|
gpl3
| 25,990
|
/*
* Linker script helper macros
*
* Copyright (c) 2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __U_BOOT_LDS__
#define __U_BOOT_LDS__
/* See if the linker version is at least the specified version */
#define LD_AT_LEAST(major, minor) \
((major > LD_MAJOR) || (major == LD_MAJOR && minor <= LD_MINOR))
/*
* Linker versions prior to 2.16 don't understand the builtin
* functions SORT_BY_ALIGNMENT() and SORT_BY_NAME(), so disable these
*/
#if !LD_AT_LEAST(2, 16)
# define SORT_BY_ALIGNMENT(x) x
# define SORT_BY_NAME(x) x
#endif
#endif
|
1001-study-uboot
|
include/u-boot/u-boot.lds.h
|
C
|
gpl3
| 578
|
/*
* Copyright 2003-2004 Red Hat, Inc. All rights reserved.
* Copyright 2003-2004 Jeff Garzik
* Copyright (C) 2008 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
* port from libata of linux kernel
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __LIBATA_H__
#define __LIBATA_H__
#include <common.h>
enum {
/* various global constants */
ATA_MAX_DEVICES = 2, /* per bus/port */
ATA_MAX_PRD = 256, /* we could make these 256/256 */
ATA_SECT_SIZE = 512,
ATA_MAX_SECTORS_128 = 128,
ATA_MAX_SECTORS = 256,
ATA_MAX_SECTORS_LBA48 = 65535,
ATA_MAX_SECTORS_TAPE = 65535,
ATA_ID_WORDS = 256,
ATA_ID_SERNO = 10,
ATA_ID_FW_REV = 23,
ATA_ID_PROD = 27,
ATA_ID_OLD_PIO_MODES = 51,
ATA_ID_FIELD_VALID = 53,
ATA_ID_LBA_SECTORS = 60,
ATA_ID_MWDMA_MODES = 63,
ATA_ID_PIO_MODES = 64,
ATA_ID_EIDE_DMA_MIN = 65,
ATA_ID_EIDE_PIO = 67,
ATA_ID_EIDE_PIO_IORDY = 68,
ATA_ID_PIO4 = (1 << 1),
ATA_ID_QUEUE_DEPTH = 75,
ATA_ID_SATA_CAP = 76,
ATA_ID_SATA_FEATURES = 78,
ATA_ID_SATA_FEATURES_EN = 79,
ATA_ID_MAJOR_VER = 80,
ATA_ID_MINOR_VER = 81,
ATA_ID_UDMA_MODES = 88,
ATA_ID_LBA48_SECTORS = 100,
ATA_ID_SERNO_LEN = 20,
ATA_ID_FW_REV_LEN = 8,
ATA_ID_PROD_LEN = 40,
ATA_PCI_CTL_OFS = 2,
ATA_PIO0 = (1 << 0),
ATA_PIO1 = ATA_PIO0 | (1 << 1),
ATA_PIO2 = ATA_PIO1 | (1 << 2),
ATA_PIO3 = ATA_PIO2 | (1 << 3),
ATA_PIO4 = ATA_PIO3 | (1 << 4),
ATA_PIO5 = ATA_PIO4 | (1 << 5),
ATA_PIO6 = ATA_PIO5 | (1 << 6),
ATA_SWDMA0 = (1 << 0),
ATA_SWDMA1 = ATA_SWDMA0 | (1 << 1),
ATA_SWDMA2 = ATA_SWDMA1 | (1 << 2),
ATA_SWDMA2_ONLY = (1 << 2),
ATA_MWDMA0 = (1 << 0),
ATA_MWDMA1 = ATA_MWDMA0 | (1 << 1),
ATA_MWDMA2 = ATA_MWDMA1 | (1 << 2),
ATA_MWDMA12_ONLY = (1 << 1) | (1 << 2),
ATA_MWDMA2_ONLY = (1 << 2),
ATA_UDMA0 = (1 << 0),
ATA_UDMA1 = ATA_UDMA0 | (1 << 1),
ATA_UDMA2 = ATA_UDMA1 | (1 << 2),
ATA_UDMA3 = ATA_UDMA2 | (1 << 3),
ATA_UDMA4 = ATA_UDMA3 | (1 << 4),
ATA_UDMA5 = ATA_UDMA4 | (1 << 5),
ATA_UDMA6 = ATA_UDMA5 | (1 << 6),
ATA_UDMA7 = ATA_UDMA6 | (1 << 7),
/* ATA_UDMA7 is just for completeness... doesn't exist (yet?). */
ATA_UDMA_MASK_40C = ATA_UDMA2, /* udma0-2 */
/* DMA-related */
ATA_PRD_SZ = 8,
ATA_PRD_TBL_SZ = (ATA_MAX_PRD * ATA_PRD_SZ),
ATA_PRD_EOT = (1 << 31), /* end-of-table flag */
ATA_DMA_TABLE_OFS = 4,
ATA_DMA_STATUS = 2,
ATA_DMA_CMD = 0,
ATA_DMA_WR = (1 << 3),
ATA_DMA_START = (1 << 0),
ATA_DMA_INTR = (1 << 2),
ATA_DMA_ERR = (1 << 1),
ATA_DMA_ACTIVE = (1 << 0),
/* bits in ATA command block registers */
ATA_HOB = (1 << 7), /* LBA48 selector */
ATA_NIEN = (1 << 1), /* disable-irq flag */
ATA_LBA = (1 << 6), /* LBA28 selector */
ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */
ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */
ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */
ATA_BUSY = (1 << 7), /* BSY status bit */
ATA_DRDY = (1 << 6), /* device ready */
ATA_DF = (1 << 5), /* device fault */
ATA_DRQ = (1 << 3), /* data request i/o */
ATA_ERR = (1 << 0), /* have an error */
ATA_SRST = (1 << 2), /* software reset */
ATA_ICRC = (1 << 7), /* interface CRC error */
ATA_UNC = (1 << 6), /* uncorrectable media error */
ATA_IDNF = (1 << 4), /* ID not found */
ATA_ABORTED = (1 << 2), /* command aborted */
/* ATA command block registers */
ATA_REG_DATA = 0x00,
ATA_REG_ERR = 0x01,
ATA_REG_NSECT = 0x02,
ATA_REG_LBAL = 0x03,
ATA_REG_LBAM = 0x04,
ATA_REG_LBAH = 0x05,
ATA_REG_DEVICE = 0x06,
ATA_REG_STATUS = 0x07,
ATA_REG_FEATURE = ATA_REG_ERR, /* and their aliases */
ATA_REG_CMD = ATA_REG_STATUS,
ATA_REG_BYTEL = ATA_REG_LBAM,
ATA_REG_BYTEH = ATA_REG_LBAH,
ATA_REG_DEVSEL = ATA_REG_DEVICE,
ATA_REG_IRQ = ATA_REG_NSECT,
/* ATA device commands */
ATA_CMD_DEV_RESET = 0x08, /* ATAPI device reset */
ATA_CMD_CHK_POWER = 0xE5, /* check power mode */
ATA_CMD_STANDBY = 0xE2, /* place in standby power mode */
ATA_CMD_IDLE = 0xE3, /* place in idle power mode */
ATA_CMD_EDD = 0x90, /* execute device diagnostic */
ATA_CMD_FLUSH = 0xE7,
ATA_CMD_FLUSH_EXT = 0xEA,
ATA_CMD_ID_ATA = 0xEC,
ATA_CMD_ID_ATAPI = 0xA1,
ATA_CMD_READ = 0xC8,
ATA_CMD_READ_EXT = 0x25,
ATA_CMD_WRITE = 0xCA,
ATA_CMD_WRITE_EXT = 0x35,
ATA_CMD_WRITE_FUA_EXT = 0x3D,
ATA_CMD_FPDMA_READ = 0x60,
ATA_CMD_FPDMA_WRITE = 0x61,
ATA_CMD_PIO_READ = 0x20,
ATA_CMD_PIO_READ_EXT = 0x24,
ATA_CMD_PIO_WRITE = 0x30,
ATA_CMD_PIO_WRITE_EXT = 0x34,
ATA_CMD_READ_MULTI = 0xC4,
ATA_CMD_READ_MULTI_EXT = 0x29,
ATA_CMD_WRITE_MULTI = 0xC5,
ATA_CMD_WRITE_MULTI_EXT = 0x39,
ATA_CMD_WRITE_MULTI_FUA_EXT = 0xCE,
ATA_CMD_SET_FEATURES = 0xEF,
ATA_CMD_SET_MULTI = 0xC6,
ATA_CMD_PACKET = 0xA0,
ATA_CMD_VERIFY = 0x40,
ATA_CMD_VERIFY_EXT = 0x42,
ATA_CMD_STANDBYNOW1 = 0xE0,
ATA_CMD_IDLEIMMEDIATE = 0xE1,
ATA_CMD_SLEEP = 0xE6,
ATA_CMD_INIT_DEV_PARAMS = 0x91,
ATA_CMD_READ_NATIVE_MAX = 0xF8,
ATA_CMD_READ_NATIVE_MAX_EXT = 0x27,
ATA_CMD_SET_MAX = 0xF9,
ATA_CMD_SET_MAX_EXT = 0x37,
ATA_CMD_READ_LOG_EXT = 0x2f,
ATA_CMD_PMP_READ = 0xE4,
ATA_CMD_PMP_WRITE = 0xE8,
ATA_CMD_CONF_OVERLAY = 0xB1,
ATA_CMD_SEC_FREEZE_LOCK = 0xF5,
/* READ_LOG_EXT pages */
ATA_LOG_SATA_NCQ = 0x10,
/* READ/WRITE LONG (obsolete) */
ATA_CMD_READ_LONG = 0x22,
ATA_CMD_READ_LONG_ONCE = 0x23,
ATA_CMD_WRITE_LONG = 0x32,
ATA_CMD_WRITE_LONG_ONCE = 0x33,
/* SETFEATURES stuff */
SETFEATURES_XFER = 0x03,
XFER_UDMA_7 = 0x47,
XFER_UDMA_6 = 0x46,
XFER_UDMA_5 = 0x45,
XFER_UDMA_4 = 0x44,
XFER_UDMA_3 = 0x43,
XFER_UDMA_2 = 0x42,
XFER_UDMA_1 = 0x41,
XFER_UDMA_0 = 0x40,
XFER_MW_DMA_4 = 0x24, /* CFA only */
XFER_MW_DMA_3 = 0x23, /* CFA only */
XFER_MW_DMA_2 = 0x22,
XFER_MW_DMA_1 = 0x21,
XFER_MW_DMA_0 = 0x20,
XFER_SW_DMA_2 = 0x12,
XFER_SW_DMA_1 = 0x11,
XFER_SW_DMA_0 = 0x10,
XFER_PIO_6 = 0x0E, /* CFA only */
XFER_PIO_5 = 0x0D, /* CFA only */
XFER_PIO_4 = 0x0C,
XFER_PIO_3 = 0x0B,
XFER_PIO_2 = 0x0A,
XFER_PIO_1 = 0x09,
XFER_PIO_0 = 0x08,
XFER_PIO_SLOW = 0x00,
SETFEATURES_WC_ON = 0x02, /* Enable write cache */
SETFEATURES_WC_OFF = 0x82, /* Disable write cache */
SETFEATURES_SPINUP = 0x07, /* Spin-up drive */
SETFEATURES_SATA_ENABLE = 0x10, /* Enable use of SATA feature */
SETFEATURES_SATA_DISABLE = 0x90, /* Disable use of SATA feature */
/* SETFEATURE Sector counts for SATA features */
SATA_AN = 0x05, /* Asynchronous Notification */
SATA_DIPM = 0x03, /* Device Initiated Power Management */
/* feature values for SET_MAX */
ATA_SET_MAX_ADDR = 0x00,
ATA_SET_MAX_PASSWD = 0x01,
ATA_SET_MAX_LOCK = 0x02,
ATA_SET_MAX_UNLOCK = 0x03,
ATA_SET_MAX_FREEZE_LOCK = 0x04,
/* feature values for DEVICE CONFIGURATION OVERLAY */
ATA_DCO_RESTORE = 0xC0,
ATA_DCO_FREEZE_LOCK = 0xC1,
ATA_DCO_IDENTIFY = 0xC2,
ATA_DCO_SET = 0xC3,
/* ATAPI stuff */
ATAPI_PKT_DMA = (1 << 0),
ATAPI_DMADIR = (1 << 2), /* ATAPI data dir:
0=to device, 1=to host */
ATAPI_CDB_LEN = 16,
/* PMP stuff */
SATA_PMP_MAX_PORTS = 15,
SATA_PMP_CTRL_PORT = 15,
SATA_PMP_GSCR_DWORDS = 128,
SATA_PMP_GSCR_PROD_ID = 0,
SATA_PMP_GSCR_REV = 1,
SATA_PMP_GSCR_PORT_INFO = 2,
SATA_PMP_GSCR_ERROR = 32,
SATA_PMP_GSCR_ERROR_EN = 33,
SATA_PMP_GSCR_FEAT = 64,
SATA_PMP_GSCR_FEAT_EN = 96,
SATA_PMP_PSCR_STATUS = 0,
SATA_PMP_PSCR_ERROR = 1,
SATA_PMP_PSCR_CONTROL = 2,
SATA_PMP_FEAT_BIST = (1 << 0),
SATA_PMP_FEAT_PMREQ = (1 << 1),
SATA_PMP_FEAT_DYNSSC = (1 << 2),
SATA_PMP_FEAT_NOTIFY = (1 << 3),
/* cable types */
ATA_CBL_NONE = 0,
ATA_CBL_PATA40 = 1,
ATA_CBL_PATA80 = 2,
ATA_CBL_PATA40_SHORT = 3, /* 40 wire cable to high UDMA spec */
ATA_CBL_PATA_UNK = 4, /* don't know, maybe 80c? */
ATA_CBL_PATA_IGN = 5, /* don't know, ignore cable handling */
ATA_CBL_SATA = 6,
/* SATA Status and Control Registers */
SCR_STATUS = 0,
SCR_ERROR = 1,
SCR_CONTROL = 2,
SCR_ACTIVE = 3,
SCR_NOTIFICATION = 4,
/* SError bits */
SERR_DATA_RECOVERED = (1 << 0), /* recovered data error */
SERR_COMM_RECOVERED = (1 << 1), /* recovered comm failure */
SERR_DATA = (1 << 8), /* unrecovered data error */
SERR_PERSISTENT = (1 << 9), /* persistent data/comm error */
SERR_PROTOCOL = (1 << 10), /* protocol violation */
SERR_INTERNAL = (1 << 11), /* host internal error */
SERR_PHYRDY_CHG = (1 << 16), /* PHY RDY changed */
SERR_PHY_INT_ERR = (1 << 17), /* PHY internal error */
SERR_COMM_WAKE = (1 << 18), /* Comm wake */
SERR_10B_8B_ERR = (1 << 19), /* 10b to 8b decode error */
SERR_DISPARITY = (1 << 20), /* Disparity */
SERR_CRC = (1 << 21), /* CRC error */
SERR_HANDSHAKE = (1 << 22), /* Handshake error */
SERR_LINK_SEQ_ERR = (1 << 23), /* Link sequence error */
SERR_TRANS_ST_ERROR = (1 << 24), /* Transport state trans. error */
SERR_UNRECOG_FIS = (1 << 25), /* Unrecognized FIS */
SERR_DEV_XCHG = (1 << 26), /* device exchanged */
/* struct ata_taskfile flags */
ATA_TFLAG_LBA48 = (1 << 0), /* enable 48-bit LBA and "HOB" */
ATA_TFLAG_ISADDR = (1 << 1), /* enable r/w to nsect/lba regs */
ATA_TFLAG_DEVICE = (1 << 2), /* enable r/w to device reg */
ATA_TFLAG_WRITE = (1 << 3), /* data dir: host->dev==1 (write) */
ATA_TFLAG_LBA = (1 << 4), /* enable LBA */
ATA_TFLAG_FUA = (1 << 5), /* enable FUA */
ATA_TFLAG_POLLING = (1 << 6), /* set nIEN to 1 and use polling */
/* protocol flags */
ATA_PROT_FLAG_PIO = (1 << 0), /* is PIO */
ATA_PROT_FLAG_DMA = (1 << 1), /* is DMA */
ATA_PROT_FLAG_DATA = ATA_PROT_FLAG_PIO | ATA_PROT_FLAG_DMA,
ATA_PROT_FLAG_NCQ = (1 << 2), /* is NCQ */
ATA_PROT_FLAG_ATAPI = (1 << 3), /* is ATAPI */
};
enum ata_tf_protocols {
/* ATA taskfile protocols */
ATA_PROT_UNKNOWN, /* unknown/invalid */
ATA_PROT_NODATA, /* no data */
ATA_PROT_PIO, /* PIO data xfer */
ATA_PROT_DMA, /* DMA */
ATA_PROT_NCQ, /* NCQ */
ATAPI_PROT_NODATA, /* packet command, no data */
ATAPI_PROT_PIO, /* packet command, PIO data xfer*/
ATAPI_PROT_DMA, /* packet command with special DMA sauce */
};
enum ata_ioctls {
ATA_IOC_GET_IO32 = 0x309,
ATA_IOC_SET_IO32 = 0x324,
};
enum ata_dev_typed {
ATA_DEV_ATA, /* ATA device */
ATA_DEV_ATAPI, /* ATAPI device */
ATA_DEV_PMP, /* Port Multiplier Port */
ATA_DEV_UNKNOWN, /* unknown */
};
struct ata_taskfile {
unsigned long flags; /* ATA_TFLAG_xxx */
u8 protocol; /* ATA_PROT_xxx */
u8 ctl; /* control reg */
u8 hob_feature; /* additional data */
u8 hob_nsect; /* to support LBA48 */
u8 hob_lbal;
u8 hob_lbam;
u8 hob_lbah;
u8 feature;
u8 nsect;
u8 lbal;
u8 lbam;
u8 lbah;
u8 device;
u8 command; /* IO operation */
};
/*
* protocol tests
*/
static inline unsigned int ata_prot_flags(u8 prot)
{
switch (prot) {
case ATA_PROT_NODATA:
return 0;
case ATA_PROT_PIO:
return ATA_PROT_FLAG_PIO;
case ATA_PROT_DMA:
return ATA_PROT_FLAG_DMA;
case ATA_PROT_NCQ:
return ATA_PROT_FLAG_DMA | ATA_PROT_FLAG_NCQ;
case ATAPI_PROT_NODATA:
return ATA_PROT_FLAG_ATAPI;
case ATAPI_PROT_PIO:
return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_PIO;
case ATAPI_PROT_DMA:
return ATA_PROT_FLAG_ATAPI | ATA_PROT_FLAG_DMA;
}
return 0;
}
static inline int ata_is_atapi(u8 prot)
{
return ata_prot_flags(prot) & ATA_PROT_FLAG_ATAPI;
}
static inline int ata_is_nodata(u8 prot)
{
return !(ata_prot_flags(prot) & ATA_PROT_FLAG_DATA);
}
static inline int ata_is_pio(u8 prot)
{
return ata_prot_flags(prot) & ATA_PROT_FLAG_PIO;
}
static inline int ata_is_dma(u8 prot)
{
return ata_prot_flags(prot) & ATA_PROT_FLAG_DMA;
}
static inline int ata_is_ncq(u8 prot)
{
return ata_prot_flags(prot) & ATA_PROT_FLAG_NCQ;
}
static inline int ata_is_data(u8 prot)
{
return ata_prot_flags(prot) & ATA_PROT_FLAG_DATA;
}
/*
* id tests
*/
#define ata_id_is_ata(id) (((id)[0] & (1 << 15)) == 0)
#define ata_id_has_lba(id) ((id)[49] & (1 << 9))
#define ata_id_has_dma(id) ((id)[49] & (1 << 8))
#define ata_id_has_ncq(id) ((id)[76] & (1 << 8))
#define ata_id_queue_depth(id) (((id)[75] & 0x1f) + 1)
#define ata_id_removeable(id) ((id)[0] & (1 << 7))
#define ata_id_iordy_disable(id) ((id)[49] & (1 << 10))
#define ata_id_has_iordy(id) ((id)[49] & (1 << 11))
#define ata_id_u32(id,n) \
(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
#define ata_id_u64(id,n) \
( ((u64) (id)[(n) + 3] << 48) | \
((u64) (id)[(n) + 2] << 32) | \
((u64) (id)[(n) + 1] << 16) | \
((u64) (id)[(n) + 0]) )
#define ata_id_cdb_intr(id) (((id)[0] & 0x60) == 0x20)
static inline int ata_id_has_fua(const u16 *id)
{
if ((id[84] & 0xC000) != 0x4000)
return 0;
return id[84] & (1 << 6);
}
static inline int ata_id_has_flush(const u16 *id)
{
if ((id[83] & 0xC000) != 0x4000)
return 0;
return id[83] & (1 << 12);
}
static inline int ata_id_has_flush_ext(const u16 *id)
{
if ((id[83] & 0xC000) != 0x4000)
return 0;
return id[83] & (1 << 13);
}
static inline int ata_id_has_lba48(const u16 *id)
{
if ((id[83] & 0xC000) != 0x4000)
return 0;
if (!ata_id_u64(id, 100))
return 0;
return id[83] & (1 << 10);
}
static inline int ata_id_hpa_enabled(const u16 *id)
{
/* Yes children, word 83 valid bits cover word 82 data */
if ((id[83] & 0xC000) != 0x4000)
return 0;
/* And 87 covers 85-87 */
if ((id[87] & 0xC000) != 0x4000)
return 0;
/* Check command sets enabled as well as supported */
if ((id[85] & ( 1 << 10)) == 0)
return 0;
return id[82] & (1 << 10);
}
static inline int ata_id_has_wcache(const u16 *id)
{
/* Yes children, word 83 valid bits cover word 82 data */
if ((id[83] & 0xC000) != 0x4000)
return 0;
return id[82] & (1 << 5);
}
static inline int ata_id_has_pm(const u16 *id)
{
if ((id[83] & 0xC000) != 0x4000)
return 0;
return id[82] & (1 << 3);
}
static inline int ata_id_rahead_enabled(const u16 *id)
{
if ((id[87] & 0xC000) != 0x4000)
return 0;
return id[85] & (1 << 6);
}
static inline int ata_id_wcache_enabled(const u16 *id)
{
if ((id[87] & 0xC000) != 0x4000)
return 0;
return id[85] & (1 << 5);
}
static inline unsigned int ata_id_major_version(const u16 *id)
{
unsigned int mver;
if (id[ATA_ID_MAJOR_VER] == 0xFFFF)
return 0;
for (mver = 14; mver >= 1; mver--)
if (id[ATA_ID_MAJOR_VER] & (1 << mver))
break;
return mver;
}
static inline int ata_id_is_sata(const u16 *id)
{
return ata_id_major_version(id) >= 5 && id[93] == 0;
}
static inline int ata_id_has_tpm(const u16 *id)
{
/* The TPM bits are only valid on ATA8 */
if (ata_id_major_version(id) < 8)
return 0;
if ((id[48] & 0xC000) != 0x4000)
return 0;
return id[48] & (1 << 0);
}
static inline int ata_id_has_dword_io(const u16 *id)
{
/* ATA 8 reuses this flag for "trusted" computing */
if (ata_id_major_version(id) > 7)
return 0;
if (id[48] & (1 << 0))
return 1;
return 0;
}
static inline int ata_id_current_chs_valid(const u16 *id)
{
/* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command
has not been issued to the device then the values of
id[54] to id[56] are vendor specific. */
return (id[53] & 0x01) && /* Current translation valid */
id[54] && /* cylinders in current translation */
id[55] && /* heads in current translation */
id[55] <= 16 &&
id[56]; /* sectors in current translation */
}
static inline int ata_id_is_cfa(const u16 *id)
{
u16 v = id[0];
if (v == 0x848A) /* Standard CF */
return 1;
/* Could be CF hiding as standard ATA */
if (ata_id_major_version(id) >= 3 && id[82] != 0xFFFF &&
(id[82] & ( 1 << 2)))
return 1;
return 0;
}
static inline int ata_drive_40wire(const u16 *dev_id)
{
if (ata_id_is_sata(dev_id))
return 0; /* SATA */
if ((dev_id[93] & 0xE000) == 0x6000)
return 0; /* 80 wire */
return 1;
}
static inline int ata_drive_40wire_relaxed(const u16 *dev_id)
{
if ((dev_id[93] & 0x2000) == 0x2000)
return 0; /* 80 wire */
return 1;
}
static inline int atapi_cdb_len(const u16 *dev_id)
{
u16 tmp = dev_id[0] & 0x3;
switch (tmp) {
case 0: return 12;
case 1: return 16;
default: return -1;
}
}
static inline int atapi_command_packet_set(const u16 *dev_id)
{
return (dev_id[0] >> 8) & 0x1f;
}
static inline int atapi_id_dmadir(const u16 *dev_id)
{
return ata_id_major_version(dev_id) >= 7 && (dev_id[62] & 0x8000);
}
static inline int is_multi_taskfile(struct ata_taskfile *tf)
{
return (tf->command == ATA_CMD_READ_MULTI) ||
(tf->command == ATA_CMD_WRITE_MULTI) ||
(tf->command == ATA_CMD_READ_MULTI_EXT) ||
(tf->command == ATA_CMD_WRITE_MULTI_EXT) ||
(tf->command == ATA_CMD_WRITE_MULTI_FUA_EXT);
}
static inline int ata_ok(u8 status)
{
return ((status & (ATA_BUSY | ATA_DRDY | ATA_DF | ATA_DRQ | ATA_ERR))
== ATA_DRDY);
}
static inline int lba_28_ok(u64 block, u32 n_block)
{
/* check the ending block number */
return ((block + n_block - 1) < ((u64)1 << 28)) && (n_block <= 256);
}
static inline int lba_48_ok(u64 block, u32 n_block)
{
/* check the ending block number */
return ((block + n_block - 1) < ((u64)1 << 48)) && (n_block <= 65536);
}
#define sata_pmp_gscr_vendor(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] & 0xffff)
#define sata_pmp_gscr_devid(gscr) ((gscr)[SATA_PMP_GSCR_PROD_ID] >> 16)
#define sata_pmp_gscr_rev(gscr) (((gscr)[SATA_PMP_GSCR_REV] >> 8) & 0xff)
#define sata_pmp_gscr_ports(gscr) ((gscr)[SATA_PMP_GSCR_PORT_INFO] & 0xf)
u64 ata_id_n_sectors(u16 *id);
u32 ata_dev_classify(u32 sig);
void ata_id_c_string(const u16 *id, unsigned char *s,
unsigned int ofs, unsigned int len);
void ata_dump_id(u16 *id);
void ata_swap_buf_le16(u16 *buf, unsigned int buf_words);
#endif /* __LIBATA_H__ */
|
1001-study-uboot
|
include/libata.h
|
C
|
gpl3
| 18,104
|
/* ---------------------------------------------------------------------------- */
/* ATMEL Microcontroller Software Support - ROUSSET - */
/* ---------------------------------------------------------------------------- */
/* The software is delivered "AS IS" without warranty or condition of any */
/* kind, either express, implied or statutory. This includes without */
/* limitation any warranty or condition with respect to merchantability or */
/* fitness for any particular purpose, or against the infringements of */
/* intellectual property rights of others. */
/* ---------------------------------------------------------------------------- */
/* File Name : at91rm9200_i2c.h */
/* Object : AT91RM9200 / TWI definitions */
/* Generated : AT91 SW Application Group 12/03/2002 (10:48:02) */
/* */
/* ---------------------------------------------------------------------------- */
#ifndef AT91RM9200_TWI_H
#define AT91RM9200_TWI_H
/* ******************************************************************************/
/* SOFTWARE API DEFINITION FOR Two-wire Interface */
/* ******************************************************************************/
#ifndef __ASSEMBLY__
typedef struct _AT91S_TWI {
AT91_REG TWI_CR; /* Control Register */
AT91_REG TWI_MMR; /* Master Mode Register */
AT91_REG TWI_SMR; /* Slave Mode Register */
AT91_REG TWI_IADR; /* Internal Address Register */
AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */
AT91_REG Reserved0[3];
AT91_REG TWI_SR; /* Status Register */
AT91_REG TWI_IER; /* Interrupt Enable Register */
AT91_REG TWI_IDR; /* Interrupt Disable Register */
AT91_REG TWI_IMR; /* Interrupt Mask Register */
AT91_REG TWI_RHR; /* Receive Holding Register */
AT91_REG TWI_THR; /* Transmit Holding Register */
AT91_REG Reserved1[50];
AT91_REG TWI_RPR; /* Receive Pointer Register */
AT91_REG TWI_RCR; /* Receive Counter Register */
AT91_REG TWI_TPR; /* Transmit Pointer Register */
AT91_REG TWI_TCR; /* Transmit Counter Register */
AT91_REG TWI_RNPR; /* Receive Next Pointer Register */
AT91_REG TWI_RNCR; /* Receive Next Counter Register */
AT91_REG TWI_TNPR; /* Transmit Next Pointer Register */
AT91_REG TWI_TNCR; /* Transmit Next Counter Register */
AT91_REG TWI_PTCR; /* PDC Transfer Control Register */
AT91_REG TWI_PTSR; /* PDC Transfer Status Register */
} AT91S_TWI, *AT91PS_TWI;
#endif
/* -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- */
#define AT91C_TWI_START (0x1 << 0) /* (TWI) Send a START Condition */
#define AT91C_TWI_STOP (0x1 << 1) /* (TWI) Send a STOP Condition */
#define AT91C_TWI_MSEN (0x1 << 2) /* (TWI) TWI Master Transfer Enabled */
#define AT91C_TWI_MSDIS (0x1 << 3) /* (TWI) TWI Master Transfer Disabled */
#define AT91C_TWI_SVEN (0x1 << 4) /* (TWI) TWI Slave Transfer Enabled */
#define AT91C_TWI_SVDIS (0x1 << 5) /* (TWI) TWI Slave Transfer Disabled */
#define AT91C_TWI_SWRST (0x1 << 7) /* (TWI) Software Reset */
/* -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- */
#define AT91C_TWI_IADRSZ (0x3 << 8) /* (TWI) Internal Device Address Size */
#define AT91C_TWI_IADRSZ_NO (0x0 << 8) /* (TWI) No internal device address */
#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) /* (TWI) One-byte internal device address */
#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) /* (TWI) Two-byte internal device address */
#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) /* (TWI) Three-byte internal device address */
#define AT91C_TWI_MREAD (0x1 << 12) /* (TWI) Master Read Direction */
#define AT91C_TWI_DADR (0x7F << 6) /* (TWI) Device Address */
/* -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- */
#define AT91C_TWI_SADR (0x7F << 16) /* (TWI) Slave Device Address */
/* -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- */
#define AT91C_TWI_CLDIV (0xFF << 0) /* (TWI) Clock Low Divider */
#define AT91C_TWI_CHDIV (0xFF << 8) /* (TWI) Clock High Divider */
#define AT91C_TWI_CKDIV (0x7 << 16) /* (TWI) Clock Divider */
/* -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- */
#define AT91C_TWI_TXCOMP (0x1 << 0) /* (TWI) Transmission Completed */
#define AT91C_TWI_RXRDY (0x1 << 1) /* (TWI) Receive holding register ReaDY */
#define AT91C_TWI_TXRDY (0x1 << 2) /* (TWI) Transmit holding register ReaDY*/
#define AT91C_TWI_SVREAD (0x1 << 3) /* (TWI) Slave Read */
#define AT91C_TWI_SVACC (0x1 << 4) /* (TWI) Slave Access */
#define AT91C_TWI_GCACC (0x1 << 5) /* (TWI) General Call Access */
#define AT91C_TWI_OVRE (0x1 << 6) /* (TWI) Overrun Error */
#define AT91C_TWI_UNRE (0x1 << 7) /* (TWI) Underrun Error */
#define AT91C_TWI_NACK (0x1 << 8) /* (TWI) Not Acknowledged */
#define AT91C_TWI_ARBLST (0x1 << 9) /* (TWI) Arbitration Lost */
/* -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- */
/* -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register ------- */
/* -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- */
/*
i2c Support for Atmel's AT91RM9200 Two-Wire Interface
(c) Rick Bronson
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef AT91_I2C_H
#define AT91_I2C_H
#define AT91C_TWI_CLOCK 100000
#define AT91C_TWI_SCLOCK (10 * AT91C_MASTER_CLOCK / AT91C_TWI_CLOCK)
#define AT91C_TWI_CKDIV1 (2 << 16) /* TWI clock divider. NOTE: see Errata #22 */
#if (AT91C_TWI_SCLOCK % 10) >= 5
#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 5)
#else
#define AT91C_TWI_CLDIV2 ((AT91C_TWI_SCLOCK / 10) - 6)
#endif
#define AT91C_TWI_CLDIV3 ((AT91C_TWI_CLDIV2 + (4 - AT91C_TWI_CLDIV2 % 4)) >> 2)
#define AT91C_EEPROM_I2C_ADDRESS (0x50 << 16)
#endif /* __ASSEMBLY__ */
#endif /* AT91RM9200_TWI_H */
|
1001-study-uboot
|
include/at91rm9200_i2c.h
|
C
|
gpl3
| 6,514
|
#ifndef __ADDR_MAP_H
#define __ADDR_MAP_H
/*
* Copyright 2008 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/types.h>
extern phys_addr_t addrmap_virt_to_phys(void *vaddr);
extern unsigned long addrmap_phys_to_virt(phys_addr_t paddr);
extern void addrmap_set_entry(unsigned long vaddr, phys_addr_t paddr,
phys_size_t size, int idx);
#endif
|
1001-study-uboot
|
include/addr_map.h
|
C
|
gpl3
| 1,001
|
/*
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SPI_H_
#define _SPI_H_
/* Controller-specific definitions: */
/* SPI mode flags */
#define SPI_CPHA 0x01 /* clock phase */
#define SPI_CPOL 0x02 /* clock polarity */
#define SPI_MODE_0 (0|0) /* (original MicroWire) */
#define SPI_MODE_1 (0|SPI_CPHA)
#define SPI_MODE_2 (SPI_CPOL|0)
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
#define SPI_CS_HIGH 0x04 /* CS active high */
#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
#define SPI_3WIRE 0x10 /* SI/SO signals shared */
#define SPI_LOOP 0x20 /* loopback mode */
/* SPI transfer flags */
#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
/*-----------------------------------------------------------------------
* Representation of a SPI slave, i.e. what we're communicating with.
*
* Drivers are expected to extend this with controller-specific data.
*
* bus: ID of the bus that the slave is attached to.
* cs: ID of the chip select connected to the slave.
*/
struct spi_slave {
unsigned int bus;
unsigned int cs;
};
/*-----------------------------------------------------------------------
* Initialization, must be called once on start up.
*
* TODO: I don't think we really need this.
*/
void spi_init(void);
/*-----------------------------------------------------------------------
* Set up communications parameters for a SPI slave.
*
* This must be called once for each slave. Note that this function
* usually doesn't touch any actual hardware, it only initializes the
* contents of spi_slave so that the hardware can be easily
* initialized later.
*
* bus: Bus ID of the slave chip.
* cs: Chip select ID of the slave chip on the specified bus.
* max_hz: Maximum SCK rate in Hz.
* mode: Clock polarity, clock phase and other parameters.
*
* Returns: A spi_slave reference that can be used in subsequent SPI
* calls, or NULL if one or more of the parameters are not supported.
*/
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode);
/*-----------------------------------------------------------------------
* Free any memory associated with a SPI slave.
*
* slave: The SPI slave
*/
void spi_free_slave(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* Claim the bus and prepare it for communication with a given slave.
*
* This must be called before doing any transfers with a SPI slave. It
* will enable and initialize any SPI hardware as necessary, and make
* sure that the SCK line is in the correct idle state. It is not
* allowed to claim the same bus for several slaves without releasing
* the bus in between.
*
* slave: The SPI slave
*
* Returns: 0 if the bus was claimed successfully, or a negative value
* if it wasn't.
*/
int spi_claim_bus(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* Release the SPI bus
*
* This must be called once for every call to spi_claim_bus() after
* all transfers have finished. It may disable any SPI hardware as
* appropriate.
*
* slave: The SPI slave
*/
void spi_release_bus(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* SPI transfer
*
* This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
* "bitlen" bits in the SPI MISO port. That's just the way SPI works.
*
* The source of the outgoing bits is the "dout" parameter and the
* destination of the input bits is the "din" parameter. Note that "dout"
* and "din" can point to the same memory location, in which case the
* input data overwrites the output data (since both are buffered by
* temporary variables, this is OK).
*
* spi_xfer() interface:
* slave: The SPI slave which will be sending/receiving the data.
* bitlen: How many bits to write and read.
* dout: Pointer to a string of bits to send out. The bits are
* held in a byte array and are sent MSB first.
* din: Pointer to a string of bits that will be filled in.
* flags: A bitwise combination of SPI_XFER_* flags.
*
* Returns: 0 on success, not 0 on failure
*/
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags);
/*-----------------------------------------------------------------------
* Determine if a SPI chipselect is valid.
* This function is provided by the board if the low-level SPI driver
* needs it to determine if a given chipselect is actually valid.
*
* Returns: 1 if bus:cs identifies a valid chip on this board, 0
* otherwise.
*/
int spi_cs_is_valid(unsigned int bus, unsigned int cs);
/*-----------------------------------------------------------------------
* Activate a SPI chipselect.
* This function is provided by the board code when using a driver
* that can't control its chipselects automatically (e.g.
* common/soft_spi.c). When called, it should activate the chip select
* to the device identified by "slave".
*/
void spi_cs_activate(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* Deactivate a SPI chipselect.
* This function is provided by the board code when using a driver
* that can't control its chipselects automatically (e.g.
* common/soft_spi.c). When called, it should deactivate the chip
* select to the device identified by "slave".
*/
void spi_cs_deactivate(struct spi_slave *slave);
/*-----------------------------------------------------------------------
* Set transfer speed.
* This sets a new speed to be applied for next spi_xfer().
* slave: The SPI slave
* hz: The transfer speed
*/
void spi_set_speed(struct spi_slave *slave, uint hz);
/*-----------------------------------------------------------------------
* Write 8 bits, then read 8 bits.
* slave: The SPI slave we're communicating with
* byte: Byte to be written
*
* Returns: The value that was read, or a negative value on error.
*
* TODO: This function probably shouldn't be inlined.
*/
static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
{
unsigned char dout[2];
unsigned char din[2];
int ret;
dout[0] = byte;
dout[1] = 0;
ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
return ret < 0 ? ret : din[1];
}
#endif /* _SPI_H_ */
|
1001-study-uboot
|
include/spi.h
|
C
|
gpl3
| 7,306
|
/*
* U-boot - errno.h Error number defines
*
* Copyright (c) 2005-2007 Analog Devices Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
#ifndef _GENERIC_ERRNO_H
#define _GENERIC_ERRNO_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Argument list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
#define EDEADLOCK EDEADLK
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
#endif
|
1001-study-uboot
|
include/asm-generic/errno.h
|
C
|
gpl3
| 7,058
|
#ifndef _GENERIC_UNALIGNED_H
#define _GENERIC_UNALIGNED_H
#include <asm/byteorder.h>
#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/generic.h>
/*
* Select endianness
*/
#if defined(__LITTLE_ENDIAN)
#define get_unaligned __get_unaligned_le
#define put_unaligned __put_unaligned_le
#elif defined(__BIG_ENDIAN)
#define get_unaligned __get_unaligned_be
#define put_unaligned __put_unaligned_be
#else
#error invalid endian
#endif
#endif
|
1001-study-uboot
|
include/asm-generic/unaligned.h
|
C
|
gpl3
| 501
|
#ifndef _ASM_GENERIC_IOCTL_H
#define _ASM_GENERIC_IOCTL_H
/* ioctl command encoding: 32 bits total, command in lower 16 bits,
* size of the parameter structure in the lower 14 bits of the
* upper 16 bits.
* Encoding the size of the parameter structure in the ioctl request
* is useful for catching programs compiled with old versions
* and to avoid overwriting user space outside the user buffer area.
* The highest 2 bits are reserved for indicating the ``access mode''.
* NOTE: This limits the max parameter size to 16kB -1 !
*/
/*
* The following is for compatibility across the various Linux
* platforms. The generic ioctl numbering scheme doesn't really enforce
* a type field. De facto, however, the top 8 bits of the lower 16
* bits are indeed used as a type field, so we might just as well make
* this explicit here. Please be sure to use the decoding macros
* below from now on.
*/
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
/*
* Let any architecture override either of the following before
* including this file.
*/
#ifndef _IOC_SIZEBITS
# define _IOC_SIZEBITS 14
#endif
#ifndef _IOC_DIRBITS
# define _IOC_DIRBITS 2
#endif
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
/*
* Direction bits, which any architecture can choose to override
* before including this file.
*/
#ifndef _IOC_NONE
# define _IOC_NONE 0U
#endif
#ifndef _IOC_WRITE
# define _IOC_WRITE 1U
#endif
#ifndef _IOC_READ
# define _IOC_READ 2U
#endif
#define _IOC(dir,type,nr,size) \
(((dir) << _IOC_DIRSHIFT) | \
((type) << _IOC_TYPESHIFT) | \
((nr) << _IOC_NRSHIFT) | \
((size) << _IOC_SIZESHIFT))
#ifdef __KERNEL__
/* provoke compile error for invalid uses of size argument */
extern unsigned int __invalid_size_argument_for_IOC;
#define _IOC_TYPECHECK(t) \
((sizeof(t) == sizeof(t[1]) && \
sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
sizeof(t) : __invalid_size_argument_for_IOC)
#else
#define _IOC_TYPECHECK(t) (sizeof(t))
#endif
/* used to create numbers */
#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
/* used to decode ioctl numbers.. */
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
/* ...and for the drivers/sound files... */
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
#endif /* _ASM_GENERIC_IOCTL_H */
|
1001-study-uboot
|
include/asm-generic/ioctl.h
|
C
|
gpl3
| 3,450
|
#ifndef __ASM_GENERIC_SIGNAL_H
#define __ASM_GENERIC_SIGNAL_H
#include <linux/types.h>
#define _NSIG 64
#define _NSIG_BPW BITS_PER_LONG
#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
#define SIGHUP 1
#define SIGINT 2
#define SIGQUIT 3
#define SIGILL 4
#define SIGTRAP 5
#define SIGABRT 6
#define SIGIOT 6
#define SIGBUS 7
#define SIGFPE 8
#define SIGKILL 9
#define SIGUSR1 10
#define SIGSEGV 11
#define SIGUSR2 12
#define SIGPIPE 13
#define SIGALRM 14
#define SIGTERM 15
#define SIGSTKFLT 16
#define SIGCHLD 17
#define SIGCONT 18
#define SIGSTOP 19
#define SIGTSTP 20
#define SIGTTIN 21
#define SIGTTOU 22
#define SIGURG 23
#define SIGXCPU 24
#define SIGXFSZ 25
#define SIGVTALRM 26
#define SIGPROF 27
#define SIGWINCH 28
#define SIGIO 29
#define SIGPOLL SIGIO
/*
#define SIGLOST 29
*/
#define SIGPWR 30
#define SIGSYS 31
#define SIGUNUSED 31
/* These should not be considered constants from userland. */
#define SIGRTMIN 32
#ifndef SIGRTMAX
#define SIGRTMAX _NSIG
#endif
/*
* SA_FLAGS values:
*
* SA_ONSTACK indicates that a registered stack_t will be used.
* SA_RESTART flag to get restarting signals (which were the default long ago)
* SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
* SA_RESETHAND clears the handler when the signal is delivered.
* SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
* SA_NODEFER prevents the current signal from being masked in the handler.
*
* SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
* Unix names RESETHAND and NODEFER respectively.
*/
#define SA_NOCLDSTOP 0x00000001
#define SA_NOCLDWAIT 0x00000002
#define SA_SIGINFO 0x00000004
#define SA_ONSTACK 0x08000000
#define SA_RESTART 0x10000000
#define SA_NODEFER 0x40000000
#define SA_RESETHAND 0x80000000
#define SA_NOMASK SA_NODEFER
#define SA_ONESHOT SA_RESETHAND
/*
* New architectures should not define the obsolete
* SA_RESTORER 0x04000000
*/
/*
* sigaltstack controls
*/
#define SS_ONSTACK 1
#define SS_DISABLE 2
#define MINSIGSTKSZ 2048
#define SIGSTKSZ 8192
#ifndef __ASSEMBLY__
typedef struct {
unsigned long sig[_NSIG_WORDS];
} sigset_t;
/* not actually used, but required for linux/syscalls.h */
#endif /* __ASSEMBLY__ */
#endif /* _ASM_GENERIC_SIGNAL_H */
|
1001-study-uboot
|
include/asm-generic/signal.h
|
C
|
gpl3
| 2,260
|
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Generic GPIO API for U-Boot
*
* GPIOs are numbered from 0 to GPIO_COUNT-1 which value is defined
* by the SOC/architecture.
*
* Each GPIO can be an input or output. If an input then its value can
* be read as 0 or 1. If an output then its value can be set to 0 or 1.
* If you try to write an input then the value is undefined. If you try
* to read an output, barring something very unusual, you will get
* back the value of the output that you previously set.
*
* In some cases the operation may fail, for example if the GPIO number
* is out of range, or the GPIO is not available because its pin is
* being used by another function. In that case, functions may return
* an error value of -1.
*/
/**
* Make a GPIO an input.
*
* @param gp GPIO number
* @return 0 if ok, -1 on error
*/
int gpio_direction_input(int gp);
/**
* Make a GPIO an output, and set its value.
*
* @param gp GPIO number
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_direction_output(int gp, int value);
/**
* Get a GPIO's value. This will work whether the GPIO is an input
* or an output.
*
* @param gp GPIO number
* @return 0 if low, 1 if high, -1 on error
*/
int gpio_get_value(int gp);
/**
* Set an output GPIO's value. The GPIO must already be an output of
* this function may have no effect.
*
* @param gp GPIO number
* @param value GPIO value (0 for low or 1 for high)
* @return 0 if ok, -1 on error
*/
int gpio_set_value(int gp, int value);
|
1001-study-uboot
|
include/asm-generic/gpio.h
|
C
|
gpl3
| 2,366
|
/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _NS87308_H_
#define _NS87308_H_
#include <asm/pci_io.h>
/* Note: I couldn't find a full data sheet for the ns87308, but the ns87307 seems to be pretty
functionally- (and pin-) equivalent to the 87308, but the 308 has better ir support. */
void initialise_ns87308(void);
/*
* The following struct represents the GPIO registers on the NS87308/NS97307
*/
struct GPIO
{
unsigned char dta1; /* 0 data port 1 */
unsigned char dir1; /* 1 direction port 1 */
unsigned char out1; /* 2 output type port 1 */
unsigned char puc1; /* 3 pull-up control port 1 */
unsigned char dta2; /* 4 data port 2 */
unsigned char dir2; /* 5 direction port 2 */
unsigned char out2; /* 6 output type port 2 */
unsigned char puc2; /* 7 pull-up control port 2 */
};
/*
* The following represents the power management registers on the NS87308/NS97307
*/
#define PWM_FER1 0 /* 0 function enable reg. 1 */
#define PWM_FER2 1 /* 1 function enable reg. 2 */
#define PWM_PMC1 2 /* 2 power mgmt. control 1 */
#define PWM_PMC2 3 /* 3 power mgmt. control 2 */
#define PWM_PMC3 4 /* 4 power mgmt. control 3 */
#define PWM_WDTO 5 /* 5 watchdog time-out */
#define PWM_WDCF 6 /* 6 watchdog config. */
#define PWM_WDST 7 /* 7 watchdog status */
/*PNP config registers:
* these depend on the stated of BADDR1 and BADDR0 on startup
* so there's three versions here with the last two digits indicating
* for which configuration their valid
* the 1st of the two digits indicates the state of BADDR1
* the 2st of the two digits indicates the state of BADDR0
*/
#define IO_INDEX_OFFSET_0x 0x0279 /* full PnP isa Mode */
#define IO_INDEX_OFFSET_10 0x015C /* PnP motherboard mode */
#define IO_INDEX_OFFSET_11 0x002E /* PnP motherboard mode */
#define IO_DATA_OFFSET_0x 0x0A79 /* full PnP isa Mode */
#define IO_DATA_OFFSET_10 0x015D /* PnP motherboard mode */
#define IO_DATA_OFFSET_11 0x002F /* PnP motherboard mode */
#if defined(CONFIG_SYS_NS87308_BADDR_0x)
#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_0x)
#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_0x)
#elif defined(CONFIG_SYS_NS87308_BADDR_10)
#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_10)
#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_10)
#elif defined(CONFIG_SYS_NS87308_BADDR_11)
#define IO_INDEX (CONFIG_SYS_ISA_IO + IO_INDEX_OFFSET_11)
#define IO_DATA (CONFIG_SYS_ISA_IO + IO_DATA_OFFSET_11)
#endif
/* PnP register definitions */
#define SET_RD_DATA_PORT 0x00
#define SERIAL_ISOLATION 0x01
#define CONFIG_CONTROL 0x02
#define WAKE_CSN 0x03
#define RES_DATA 0x04
#define STATUS 0x05
#define SET_CSN 0x06
#define LOGICAL_DEVICE 0x07
/*vendor defined values */
#define SID_REG 0x20
#define SUPOERIO_CONF1 0x21
#define SUPOERIO_CONF2 0x22
#define PGCS_INDEX 0x23
#define PGCS_DATA 0x24
/* values above 30 are different for each logical device
but I can't be arsed to enter them all. the ones here
are pretty consistent between all logical devices
feel free to correct the situation if you want.. ;)
*/
#define ACTIVATE 0x30
#define ACTIVATE_OFF 0x00
#define ACTIVATE_ON 0x01
#define BASE_ADDR_HIGH 0x60
#define BASE_ADDR_LOW 0x61
#define LUN_CONFIG_REG 0xF0
#define DBASE_HIGH 0x60 /* SIO KBC data base address, 15:8 */
#define DBASE_LOW 0x61 /* SIO KBC data base address, 7:0 */
#define CBASE_HIGH 0x62 /* SIO KBC command base addr, 15:8 */
#define CBASE_LOW 0x63 /* SIO KBC command base addr, 7:0 */
/* the logical devices*/
#define LDEV_KBC1 0x00 /* 2 devices for keyboard and mouse controller*/
#define LDEV_KBC2 0x01
#define LDEV_MOUSE 0x01
#define LDEV_RTC_APC 0x02 /*Real Time Clock and Advanced Power Control*/
#define LDEV_FDC 0x03 /*floppy disk controller*/
#define LDEV_PARP 0x04 /*Parallel port*/
#define LDEV_UART2 0x05
#define LDEV_UART1 0x06
#define LDEV_GPIO 0x07 /*General Purpose IO and chip select output signals*/
#define LDEV_POWRMAN 0x08 /*Power Managment*/
#define CONFIG_SYS_NS87308_KBC1 (1 << LDEV_KBC1)
#define CONFIG_SYS_NS87308_KBC2 (1 << LDEV_KBC2)
#define CONFIG_SYS_NS87308_MOUSE (1 << LDEV_MOUSE)
#define CONFIG_SYS_NS87308_RTC_APC (1 << LDEV_RTC_APC)
#define CONFIG_SYS_NS87308_FDC (1 << LDEV_FDC)
#define CONFIG_SYS_NS87308_PARP (1 << LDEV_PARP)
#define CONFIG_SYS_NS87308_UART2 (1 << LDEV_UART2)
#define CONFIG_SYS_NS87308_UART1 (1 << LDEV_UART1)
#define CONFIG_SYS_NS87308_GPIO (1 << LDEV_GPIO)
#define CONFIG_SYS_NS87308_POWRMAN (1 << LDEV_POWRMAN)
/*some functions and macro's for doing configuration */
static inline void read_pnp_config(unsigned char index, unsigned char *data)
{
pci_writeb(index,IO_INDEX);
pci_readb(IO_DATA, *data);
}
static inline void write_pnp_config(unsigned char index, unsigned char data)
{
pci_writeb(index,IO_INDEX);
pci_writeb(data, IO_DATA);
}
static inline void pnp_set_device(unsigned char dev)
{
write_pnp_config(LOGICAL_DEVICE, dev);
}
static inline void write_pm_reg(unsigned short base, unsigned char index, unsigned char data)
{
pci_writeb(index, CONFIG_SYS_ISA_IO + base);
eieio();
pci_writeb(data, CONFIG_SYS_ISA_IO + base + 1);
}
/*void write_pnp_config(unsigned char index, unsigned char data);
void pnp_set_device(unsigned char dev);
*/
#define PNP_SET_DEVICE_BASE(dev,base) \
pnp_set_device(dev); \
write_pnp_config(ACTIVATE, ACTIVATE_OFF); \
write_pnp_config(BASE_ADDR_HIGH, ((base) >> 8) & 0xff ); \
write_pnp_config(BASE_ADDR_LOW, (base) &0xff); \
write_pnp_config(ACTIVATE, ACTIVATE_ON);
#define PNP_ACTIVATE_DEVICE(dev) \
pnp_set_device(dev); \
write_pnp_config(ACTIVATE, ACTIVATE_ON);
#define PNP_DEACTIVATE_DEVICE(dev) \
pnp_set_device(dev); \
write_pnp_config(ACTIVATE, ACTIVATE_OFF);
static inline void write_pgcs_config(unsigned char index, unsigned char data)
{
write_pnp_config(PGCS_INDEX, index);
write_pnp_config(PGCS_DATA, data);
}
/* these macrose configure the 3 CS lines
on the sandpoint board these controll NVRAM
CS0 is connected to NVRAMCS
CS1 is connected to NVRAMAS0
CS2 is connected to NVRAMAS1
*/
#define PGCS_CS_ASSERT_ON_WRITE 0x10
#define PGCS_CS_ASSERT_ON_READ 0x20
#define PNP_PGCS_CSLINE_BASE(cs, base) \
write_pgcs_config((cs) << 2, ((base) >> 8) & 0xff ); \
write_pgcs_config(((cs) << 2) + 1, (base) & 0xff );
#define PNP_PGCS_CSLINE_CONF(cs, conf) \
write_pgcs_config(((cs) << 2) + 2, (conf) );
/* The following sections are for 87308 extensions to the standard compoents it emulates */
/* extensions to 16550*/
#define MCR_MDSL_MSK 0xe0 /*mode select mask*/
#define MCR_MDSL_UART 0x00 /*uart, default*/
#define MCR_MDSL_SHRPIR 0x02 /*Sharp IR*/
#define MCR_MDSL_SIR 0x03 /*SIR*/
#define MCR_MDSL_CIR 0x06 /*Consumer IR*/
#define FCR_TXFTH0 0x10 /* these bits control threshod of data level in fifo */
#define FCR_TXFTH1 0x20 /* for interrupt trigger */
/*
* Default NS87308 configuration
*/
#ifndef CONFIG_SYS_NS87308_KBC1_BASE
#define CONFIG_SYS_NS87308_KBC1_BASE 0x0060
#endif
#ifndef CONFIG_SYS_NS87308_RTC_BASE
#define CONFIG_SYS_NS87308_RTC_BASE 0x0070
#endif
#ifndef CONFIG_SYS_NS87308_FDC_BASE
#define CONFIG_SYS_NS87308_FDC_BASE 0x03F0
#endif
#ifndef CONFIG_SYS_NS87308_LPT_BASE
#define CONFIG_SYS_NS87308_LPT_BASE 0x0278
#endif
#ifndef CONFIG_SYS_NS87308_UART1_BASE
#define CONFIG_SYS_NS87308_UART1_BASE 0x03F8
#endif
#ifndef CONFIG_SYS_NS87308_UART2_BASE
#define CONFIG_SYS_NS87308_UART2_BASE 0x02F8
#endif
#endif /*_NS87308_H_*/
|
1001-study-uboot
|
include/ns87308.h
|
C
|
gpl3
| 8,565
|
/*
* (C) Copyright 2011 Andes Technology Corp
* Macpaul Lin <macpaul@andestech.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller
*/
#ifndef __DWCDDR21MCTL_H
#define __DWCDDR21MCTL_H
#ifndef __ASSEMBLY__
struct dwcddr21mctl {
unsigned int ccr; /* Controller Configuration */
unsigned int dcr; /* DRAM Configuration */
unsigned int iocr; /* I/O Configuration */
unsigned int csr; /* Controller Status */
unsigned int drr; /* DRAM refresh */
unsigned int tpr0; /* SDRAM Timing Parameters 0 */
unsigned int tpr1; /* SDRAM Timing Parameters 1 */
unsigned int tpr2; /* SDRAM Timing Parameters 2 */
unsigned int gdllcr; /* Global DLL Control */
unsigned int dllcr[10]; /* DLL Control */
unsigned int rslr[4]; /* Rank System Lantency */
unsigned int rdgr[4]; /* Rank DQS Gating */
unsigned int dqtr[9]; /* DQ Timing */
unsigned int dqstr; /* DQS Timing */
unsigned int dqsbtr; /* DQS_b Timing */
unsigned int odtcr; /* ODT Configuration */
unsigned int dtr[2]; /* Data Training */
unsigned int dtar; /* Data Training Address */
unsigned int rsved[82]; /* Reserved */
unsigned int mr; /* Mode Register */
unsigned int emr; /* Extended Mode Register */
unsigned int emr2; /* Extended Mode Register 2 */
unsigned int emr3; /* Extended Mode Register 3 */
unsigned int hpcr[32]; /* Host Port Configurarion */
unsigned int pqcr[8]; /* Priority Queue Configuration */
unsigned int mmgcr; /* Memory Manager General Config */
};
#endif /* __ASSEMBLY__ */
/*
* Control Configuration Register
*/
#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0)
#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1)
#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2)
#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3)
#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4)
#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13)
#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14)
#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15)
#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17)
#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27)
#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28)
#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29)
#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30)
#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31)
/*
* DRAM Configuration Register
*/
#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0)
#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1)
#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9)
#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10)
#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12)
#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13)
#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25)
#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31)
/*
* I/O Configuration Register
*/
#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8)
#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26)
#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29)
#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30)
#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31)
/*
* Controller Status Register
*/
#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0)
#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18)
#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19)
#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20)
#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21)
#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22)
/*
* DRAM Refresh Register
*/
#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0)
#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8)
#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31)
/*
* SDRAM Timing Parameters Register 0
*/
#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0)
#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2)
#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5)
#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16)
#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25)
#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31)
/*
* SDRAM Timing Parameters Register 1
*/
#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0)
#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2)
#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3)
#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12)
#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14)
#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27)
#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31)
/*
* SDRAM Timing Parameters Register 2
*/
#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0)
#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10)
#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15)
/*
* Global DLL Control Register
*/
#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0)
#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2)
#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5)
#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9)
#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11)
#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12)
#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20)
#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29)
/*
* DLL Control Register 0-9
*/
#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12)
#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14)
#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18)
#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19)
#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31)
/*
* Rank System Lantency Register
*/
#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12)
#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15)
#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18)
#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21)
#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24)
/*
* Rank DQS Gating Register
*/
#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0)
#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2)
#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4)
#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6)
#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8)
#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10)
#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12)
#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14)
#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16)
/*
* DQ Timing Register
*/
#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0)
#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4)
#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8)
#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12)
#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16)
#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20)
#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24)
#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28)
/*
* DQS Timing Register
*/
#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12)
#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15)
#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18)
#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21)
#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24)
/*
* DQS_b (DQSBTR) Timing Register
*/
#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6)
#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12)
#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15)
#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18)
#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21)
#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24)
/*
* ODT Configuration Register
*/
#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0)
#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4)
#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8)
#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12)
#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16)
#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20)
#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24)
#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28)
/*
* Data Training Register
*/
#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */
#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */
#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */
#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */
#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */
#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */
#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */
#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */
/*
* Data Training Address Register
*/
#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0)
#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12)
#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28)
/*
* Mode Register
*/
#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_MR_BT(x) ((x) << 3)
#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4)
#define DWCDDR21MCTL_MR_TM(x) ((x) << 7)
#define DWCDDR21MCTL_MR_DR(x) ((x) << 8)
#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9)
#define DWCDDR21MCTL_MR_PD(x) ((x) << 12)
/*
* Extended Mode register
*/
#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0)
#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1)
#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2)
#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3)
#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6)
#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7)
#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10)
#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11)
#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12)
#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x)
#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x)
#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0))
#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1))
#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0))
#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1))
/*
* Extended Mode register 2
*/
#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0)
#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3)
#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7)
/*
* Extended Mode register 3: [15:0] reserved for JEDEC.
*/
/*
* Host port Configuration register 0-31
*/
#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0)
/*
* Priority Queue Configuration register 0-7
*/
#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0)
#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8)
#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10)
#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12)
#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20)
#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25)
#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28)
/*
* Memory Manager General Configuration register
*/
#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0)
#endif /* __DWCDDR21MCTL_H */
|
1001-study-uboot
|
include/synopsys/dwcddr21mctl.h
|
C
|
gpl3
| 12,701
|
/*
* (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Definitions for Command Processor
*/
#ifndef __COMMAND_H
#define __COMMAND_H
#include <config.h>
#ifndef NULL
#define NULL 0
#endif
/* Default to a width of 8 characters for help message command width */
#ifndef CONFIG_SYS_HELP_CMD_WIDTH
#define CONFIG_SYS_HELP_CMD_WIDTH 8
#endif
#ifndef __ASSEMBLY__
/*
* Monitor Command Table
*/
struct cmd_tbl_s {
char *name; /* Command Name */
int maxargs; /* maximum number of arguments */
int repeatable; /* autorepeat allowed? */
/* Implementation function */
int (*cmd)(struct cmd_tbl_s *, int, int, char * const []);
char *usage; /* Usage message (short) */
#ifdef CONFIG_SYS_LONGHELP
char *help; /* Help message (long) */
#endif
#ifdef CONFIG_AUTO_COMPLETE
/* do auto completion on the arguments */
int (*complete)(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
#endif
};
typedef struct cmd_tbl_s cmd_tbl_t;
extern cmd_tbl_t __u_boot_cmd_start;
extern cmd_tbl_t __u_boot_cmd_end;
#if defined(CONFIG_CMD_RUN)
extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
/* common/command.c */
int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
flag, int argc, char * const argv[]);
cmd_tbl_t *find_cmd(const char *cmd);
cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len);
extern int cmd_usage(const cmd_tbl_t *cmdtp);
#ifdef CONFIG_AUTO_COMPLETE
extern int var_complete(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]);
extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp);
#endif
/*
* Monitor Command
*
* All commands use a common argument format:
*
* void function (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
*/
#if defined(CONFIG_CMD_MEMORY) \
|| defined(CONFIG_CMD_I2C) \
|| defined(CONFIG_CMD_ITEST) \
|| defined(CONFIG_CMD_PCI) \
|| defined(CONFIG_CMD_PORTIO)
#define CMD_DATA_SIZE
extern int cmd_get_data_size(char* arg, int default_size);
#endif
#ifdef CONFIG_CMD_BOOTD
extern int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
#ifdef CONFIG_CMD_BOOTM
extern int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
extern int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd);
#else
static inline int bootm_maybe_autostart(cmd_tbl_t *cmdtp, const char *cmd)
{
return 0;
}
#endif
extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif /* __ASSEMBLY__ */
/*
* Command Flags:
*/
#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */
#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */
#define Struct_Section __attribute__((unused, section(".u_boot_cmd"), \
aligned(4)))
#ifdef CONFIG_AUTO_COMPLETE
# define _CMD_COMPLETE(x) x,
#else
# define _CMD_COMPLETE(x)
#endif
#ifdef CONFIG_SYS_LONGHELP
# define _CMD_HELP(x) x,
#else
# define _CMD_HELP(x)
#endif
#define U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
{#name, maxargs, rep, cmd, usage, _CMD_HELP(help) _CMD_COMPLETE(comp)}
#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \
U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
#define U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
cmd_tbl_t __u_boot_cmd_##name Struct_Section = \
U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp)
#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
#endif
#endif /* __COMMAND_H */
|
1001-study-uboot
|
include/command.h
|
C
|
gpl3
| 4,541
|
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __DS4510_H_
#define __DS4510_H_
/* General defines */
#define DS4510_NUM_IO 0x04
#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1)
#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20
/* EEPROM from 0x00 - 0x39 */
#define DS4510_EEPROM 0x00
#define DS4510_EEPROM_SIZE 0x40
#define DS4510_EEPROM_PAGE_SIZE 0x08
#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1))
/* SEEPROM from 0xf0 - 0xf7 */
#define DS4510_SEEPROM 0xf0
#define DS4510_SEEPROM_SIZE 0x08
/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */
#define DS4510_PULLUP 0xF0
#define DS4510_PULLUP_DIS 0x00
#define DS4510_PULLUP_EN 0x01
#define DS4510_RSTDELAY 0xF1
#define DS4510_RSTDELAY_MASK 0x03
#define DS4510_RSTDELAY_125 0x00
#define DS4510_RSTDELAY_250 0x01
#define DS4510_RSTDELAY_500 0x02
#define DS4510_RSTDELAY_1000 0x03
#define DS4510_IO3 0xF4
#define DS4510_IO2 0xF5
#define DS4510_IO1 0xF6
#define DS4510_IO0 0xF7
/* Status configuration registers from 0xf8 - 0xf9*/
#define DS4510_IO_STATUS 0xF8
#define DS4510_CFG 0xF9
#define DS4510_CFG_READY 0x80
#define DS4510_CFG_TRIP_POINT 0x40
#define DS4510_CFG_RESET 0x20
#define DS4510_CFG_SEE 0x10
#define DS4510_CFG_SWRST 0x08
/* SRAM from 0xfa - 0xff */
#define DS4510_SRAM 0xfa
#define DS4510_SRAM_SIZE 0x06
int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count);
int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count);
int ds4510_see_write(uint8_t chip, uint8_t nv);
int ds4510_rstdelay_write(uint8_t chip, uint8_t delay);
int ds4510_pullup_write(uint8_t chip, uint8_t val);
int ds4510_pullup_read(uint8_t chip);
int ds4510_gpio_write(uint8_t chip, uint8_t val);
int ds4510_gpio_read(uint8_t chip);
int ds4510_gpio_read_val(uint8_t chip);
#endif /* __DS4510_H_ */
|
1001-study-uboot
|
include/ds4510.h
|
C
|
gpl3
| 2,536
|
/*
* (C) Copyright 1997-2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* smiLynxEM.h
* Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
*
*
* modification history
* --------------------
* 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
*/
#ifndef _SMI_LYNX_EM_H_
#define _SMI_LYNX_EM_H_
/*
* SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external
*/
#define VIDEO_MEM_SIZE 0x400000
/*
* Supported video modes for SMI Lynx E/EM/EM+
*/
#define VIDEO_MODES 7
#define DUAL_800_600 0 /* SMI710:VGA1:75Hz (pitch=1600) */
/* VGA2:60/120Hz (pitch=1600) */
/* SMI810:VGA1:75Hz (pitch=1600) */
/* VGA2:75Hz (pitch=1600) */
#define DUAL_1024_768 1 /* VGA1:75Hz VGA2:73Hz (pitch=2048) */
#define SINGLE_800_600 2 /* VGA1:75Hz (pitch=800) */
#define SINGLE_1024_768 3 /* VGA1:75Hz (pitch=1024) */
#define SINGLE_1280_1024 4 /* VGA1:75Hz (pitch=1280) */
#define TV_MODE_CCIR 5 /* VGA1:50Hz (h=720;v=576;pitch=720) */
#define TV_MODE_EIA 6 /* VGA1:60Hz (h=720;v=484;pitch=720) */
/*
* ISA mapped regs
*/
#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */
#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */
#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */
#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */
#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */
#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */
#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */
#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */
#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */
#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */
#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/
/*
* Video processor control
*/
typedef struct {
unsigned int control;
unsigned int colorKey;
unsigned int colorKeyMask;
unsigned int start;
unsigned short offset;
unsigned short width;
unsigned int fifoPrio;
unsigned int fifoERL;
unsigned int YUVtoRGB;
} SmiVideoProc;
/*
* Video window control
*/
typedef struct {
unsigned short top;
unsigned short left;
unsigned short bottom;
unsigned short right;
unsigned int srcStart;
unsigned short width;
unsigned short offset;
unsigned char hStretch;
unsigned char vStretch;
} SmiVideoWin;
/*
* Capture port control
*/
typedef struct {
unsigned int control;
unsigned short topClip;
unsigned short leftClip;
unsigned short srcHeight;
unsigned short srcWidth;
unsigned int srcBufStart1;
unsigned int srcBufStart2;
unsigned short srcOffset;
unsigned short fifoControl;
} SmiCapturePort;
/******************************************************************************/
/* Export Graphic Driver Control */
/******************************************************************************/
typedef struct {
unsigned int isaBase;
unsigned int pciBase;
unsigned int dprBase;
unsigned int vprBase;
unsigned int cprBase;
unsigned int frameAdrs;
unsigned int memSize;
unsigned int mode;
unsigned int gdfIndex;
unsigned int gdfBytesPP;
unsigned int fg;
unsigned int bg;
unsigned int plnSizeX;
unsigned int plnSizeY;
unsigned int winSizeX;
unsigned int winSizeY;
char modeIdent[80];
} GraphicDevice;
extern GraphicDevice smi;
/******************************************************************************/
/* Export Graphic Functions */
/******************************************************************************/
void *video_hw_init (void); /* returns GraphicDevice struct or NULL */
void video_hw_bitblt (
unsigned int bpp, /* bytes per pixel */
unsigned int src_x, /* source pos x */
unsigned int src_y, /* source pos y */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y /* frame height */
);
void video_hw_rectfill (
unsigned int bpp, /* bytes per pixel */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y, /* frame height */
unsigned int color /* fill color */
);
void video_set_lut (
unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
);
#endif /*_SMI_LYNX_EM_H_ */
|
1001-study-uboot
|
include/smiLynxEM.h
|
C
|
gpl3
| 5,946
|
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Andy Fleming <afleming@freescale.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
*/
#ifndef _PHY_H
#define _PHY_H
#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>
#define PHY_MAX_ADDR 32
#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
SUPPORTED_10baseT_Full | \
SUPPORTED_100baseT_Half | \
SUPPORTED_100baseT_Full | \
SUPPORTED_Autoneg | \
SUPPORTED_TP | \
SUPPORTED_MII)
#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
SUPPORTED_1000baseT_Half | \
SUPPORTED_1000baseT_Full)
#define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
SUPPORTED_10000baseT_Full)
#define PHY_ANEG_TIMEOUT 4000
typedef enum {
PHY_INTERFACE_MODE_MII,
PHY_INTERFACE_MODE_GMII,
PHY_INTERFACE_MODE_SGMII,
PHY_INTERFACE_MODE_TBI,
PHY_INTERFACE_MODE_RMII,
PHY_INTERFACE_MODE_RGMII,
PHY_INTERFACE_MODE_RGMII_ID,
PHY_INTERFACE_MODE_RGMII_RXID,
PHY_INTERFACE_MODE_RGMII_TXID,
PHY_INTERFACE_MODE_RTBI,
PHY_INTERFACE_MODE_XGMII,
PHY_INTERFACE_MODE_NONE /* Must be last */
} phy_interface_t;
static const char *phy_interface_strings[] = {
[PHY_INTERFACE_MODE_MII] = "mii",
[PHY_INTERFACE_MODE_GMII] = "gmii",
[PHY_INTERFACE_MODE_SGMII] = "sgmii",
[PHY_INTERFACE_MODE_TBI] = "tbi",
[PHY_INTERFACE_MODE_RMII] = "rmii",
[PHY_INTERFACE_MODE_RGMII] = "rgmii",
[PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
[PHY_INTERFACE_MODE_RTBI] = "rtbi",
[PHY_INTERFACE_MODE_XGMII] = "xgmii",
[PHY_INTERFACE_MODE_NONE] = "",
};
static inline const char *phy_string_for_interface(phy_interface_t i)
{
/* Default to unknown */
if (i > PHY_INTERFACE_MODE_NONE)
i = PHY_INTERFACE_MODE_NONE;
return phy_interface_strings[i];
}
struct phy_device;
#define MDIO_NAME_LEN 32
struct mii_dev {
struct list_head link;
char name[MDIO_NAME_LEN];
void *priv;
int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
u16 val);
int (*reset)(struct mii_dev *bus);
struct phy_device *phymap[PHY_MAX_ADDR];
u32 phy_mask;
};
/* struct phy_driver: a structure which defines PHY behavior
*
* uid will contain a number which represents the PHY. During
* startup, the driver will poll the PHY to find out what its
* UID--as defined by registers 2 and 3--is. The 32-bit result
* gotten from the PHY will be masked to
* discard any bits which may change based on revision numbers
* unimportant to functionality
*
*/
struct phy_driver {
char *name;
unsigned int uid;
unsigned int mask;
unsigned int mmds;
u32 features;
/* Called to do any driver startup necessities */
/* Will be called during phy_connect */
int (*probe)(struct phy_device *phydev);
/* Called to configure the PHY, and modify the controller
* based on the results. Should be called after phy_connect */
int (*config)(struct phy_device *phydev);
/* Called when starting up the controller */
int (*startup)(struct phy_device *phydev);
/* Called when bringing down the controller */
int (*shutdown)(struct phy_device *phydev);
struct list_head list;
};
struct phy_device {
/* Information about the PHY type */
/* And management functions */
struct mii_dev *bus;
struct phy_driver *drv;
void *priv;
struct eth_device *dev;
/* forced speed & duplex (no autoneg)
* partner speed & duplex & pause (autoneg)
*/
int speed;
int duplex;
/* The most recently read link state */
int link;
int port;
phy_interface_t interface;
u32 advertising;
u32 supported;
u32 mmds;
int autoneg;
int addr;
int pause;
int asym_pause;
u32 phy_id;
u32 flags;
};
static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
struct mii_dev *bus = phydev->bus;
return bus->read(bus, phydev->addr, devad, regnum);
}
static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
u16 val)
{
struct mii_dev *bus = phydev->bus;
return bus->write(bus, phydev->addr, devad, regnum, val);
}
#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;
/* For now, XGMII is the only 10G interface */
static inline int is_10g_interface(phy_interface_t interface)
{
return interface == PHY_INTERFACE_MODE_XGMII;
}
#endif
int phy_init(void);
int phy_reset(struct phy_device *phydev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
phy_interface_t interface);
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_davicom_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_teranetics_init(void);
int phy_vitesse_init(void);
/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_TN2020 0x00a19410
#endif
|
1001-study-uboot
|
include/phy.h
|
C
|
gpl3
| 6,297
|
/*
* (C) Copyright 2005
* 2N Telekomunikace, a.s. <www.2n.cz>
* Ladislav Michl <michl@2n.cz>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _NAND_H_
#define _NAND_H_
extern void nand_init(void);
#include <linux/mtd/compat.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
extern int board_nand_init(struct nand_chip *nand);
typedef struct mtd_info nand_info_t;
extern int nand_curr_device;
extern nand_info_t nand_info[];
static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
{
return info->read(info, ofs, *len, (size_t *)len, buf);
}
static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
{
return info->write(info, ofs, *len, (size_t *)len, buf);
}
static inline int nand_block_isbad(nand_info_t *info, loff_t ofs)
{
return info->block_isbad(info, ofs);
}
static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
{
struct erase_info instr;
instr.mtd = info;
instr.addr = off;
instr.len = size;
instr.callback = 0;
return info->erase(info, &instr);
}
/*****************************************************************************
* declarations from nand_util.c
****************************************************************************/
struct nand_write_options {
u_char *buffer; /* memory block containing image to write */
ulong length; /* number of bytes to write */
ulong offset; /* start address in NAND */
int quiet; /* don't display progress messages */
int autoplace; /* if true use auto oob layout */
int forcejffs2; /* force jffs2 oob layout */
int forceyaffs; /* force yaffs oob layout */
int noecc; /* write without ecc */
int writeoob; /* image contains oob data */
int pad; /* pad to page size */
int blockalign; /* 1|2|4 set multiple of eraseblocks
* to align to */
};
typedef struct nand_write_options nand_write_options_t;
typedef struct mtd_oob_ops mtd_oob_ops_t;
struct nand_read_options {
u_char *buffer; /* memory block in which read image is written*/
ulong length; /* number of bytes to read */
ulong offset; /* start address in NAND */
int quiet; /* don't display progress messages */
int readoob; /* put oob data in image */
};
typedef struct nand_read_options nand_read_options_t;
struct nand_erase_options {
loff_t length; /* number of bytes to erase */
loff_t offset; /* first address in NAND to erase */
int quiet; /* don't display progress messages */
int jffs2; /* if true: format for jffs2 usage
* (write appropriate cleanmarker blocks) */
int scrub; /* if true, really clean NAND by erasing
* bad blocks (UNSAFE) */
/* Don't include skipped bad blocks in size to be erased */
int spread;
};
typedef struct nand_erase_options nand_erase_options_t;
int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
u_char *buffer);
#define WITH_YAFFS_OOB (1 << 0) /* whether write with yaffs format. This flag
* is a 'mode' meaning it cannot be mixed with
* other flags */
#define WITH_DROP_FFS (1 << 1) /* drop trailing all-0xff pages */
int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
u_char *buffer, int flags);
int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
#define NAND_LOCK_STATUS_TIGHT 0x01
#define NAND_LOCK_STATUS_LOCK 0x02
#define NAND_LOCK_STATUS_UNLOCK 0x04
int nand_lock( nand_info_t *meminfo, int tight );
int nand_unlock( nand_info_t *meminfo, ulong start, ulong length );
int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
void nand_deselect(void);
#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
void board_nand_select_device(struct nand_chip *nand, int chip);
#endif
__attribute__((noreturn)) void nand_boot(void);
#endif
#ifdef CONFIG_ENV_OFFSET_OOB
#define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored
as block number*/
#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
stored as byte number */
#define ENV_OFFSET_SIZE 8
int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
#endif
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1001-study-uboot
|
include/nand.h
|
C
|
gpl3
| 4,859
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