text stringlengths 14 100k | source stringclasses 1
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<|fim_prefix|>/*
* Copyright (c) 2014-2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Private kernel definitions
*
* This file contains private kernel structures definitions and various
* other definitions for the ARCv2 processor architecture.
*
* This file is a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2014-2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Private kernel definitions
*
* This file contains private kernel structures definitions and various
* other definitions for the ARCv2 processor architecture.
*
* This file is a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_ARCH_ARC_INCLUDE_OFFSETS_SHORT_ARCH_H_
#define ZEPHYR_ARCH_ARC_INCLUDE_OFFSETS_SHORT_ARCH_H_
#include <zephyr/offsets.h>
/* kernel */
/* nothing for now */
/* end - kernel */
/* threads */
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* swap_macros.h - helper macros for context switch */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_
#define ZEPHYR_ARCH_ARC_INCLUDE_SWAP_MACROS_H_
#include <offsets_short.h>
#include <zephyr/toolchain.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>*/
#endif
_ARC_V2_AUX_IRQ_CTRL_BLINK | /* save blink */
_ARC_V2_AUX_IRQ_CTRL_14_REGS /* save r0 -> r13 (caller-saved) */
);
z_arc_cpu_sleep_mode = _ARC_V2_WAKE_IRQ_LEVEL;
#ifdef CONFIG_ARC_NORMAL_FIRMWARE
/* normal mode cannot write irq_ctrl, ignore it */
ARG_UNUSED(aux_irq_ctrl_value);
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ern void __ev_trap(void);
extern void __ev_extension(void);
extern void __ev_div_zero(void);
extern void __ev_dc_error(void);
extern void __ev_maligned(void);
#ifdef __cplusplus
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_ARCH_ARC_INCLUDE_VECTOR_TABLE_H_ */
<|fim_prefix|>/*
* Copyright (c) 201... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* @file
* @brief Basic C++ destructor module for globals for ARM
*/
#include <zephyr/toolchain.h>
EXTERN_C int __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso);
/**
* @brief Register destructor fo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ache-2.0
*/
/**
* @file
* @brief Definitions for boot code
*/
#ifndef _BOOT_H_
#define _BOOT_H_
#ifndef _ASMLANGUAGE
extern void *_vector_table[];
extern void __start(void);
#endif /* _ASMLANGUAGE */
/* Offsets into the boot_params structure */
#define BOOT_PARAM_MPID_OFFSET 0
#define BOOT_PARA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>}
/* Cache not enabled - safe to invalidate (no dirty lines) */
arch_dcache_invd_all();
val |= SCTLR_C_Msk;
barrier_dsync_fence_full();
__set_SCTLR(val);
barrier_isync_fence_full();
}
void arch_dcache_disable(void)
{
uint32_t val;
L1C_CleanInvalidateDCacheAll();
val = __get_SCTLR();
val &= ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2023 Arm Limited
* Copyright (c) 2026 Synaptics Incorporated
* Author: Jisheng Zhang <jszhang@kernel.org>
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* ARM Cortex-A and Cortex-R power management
*/
#include <zephyr/kernel.h>
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
* Copyright (c) 2018 Lexmark International, Inc.
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/exception.h>
#include <kernel_internal.h>
#include <zephyr/arch/common/ex... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-A and Cortex-R interrupt initialization
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/interrupt_controller/gic.h>
/**
*
* @brief Initialize inte... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-A and Cortex-R interrupt management
*
*
* Interrupt management: enabling/disabling and dynamic ISR
* connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Full C support initialization
*
*
* Initialization of full C support: zero the .bss, copy the .da... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>HAIN_WARNING_NONNULL)
#include <string.h>
#define VECTOR_ADDRESS 0
void __weak relocate_vector_table(void)
{
#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
!defined(CONFIG_XIP) && (DT_CHOSEN_SRAM_ADDR != 0)
write_sctlr(read_sctlr() & ~HIVECS);
si... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022, Commonwealth Scientific and Industrial Research
* Organisation (CSIRO) ABN 41 687 119 230.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/sys/util_macro.h>
#include <zephyr/arch/common/semihost.h>
#if !(defined(CONFIG_ISA_ARM) || defined(CONFIG_ISA_THUMB2))
#error Unsupporte... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023, 2024 Arm Limited (or its affiliates).
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel/thread_stack.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/arm/cortex_a_r/lib_helpers.h>
#include <zephyr/drivers/interrupt_controller/gic.h>
#include <ipi.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Lexmark International, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "zephyr/kernel/thread_stack.h"
#include <zephyr/kernel.h>
#include <cortex_a_r/stack.h>
#include <string.h>
#include <kernel_internal.h>
<|fim_suffix|>K_KERNEL_STACK_ARRAY_DEFINE(z_arm_svc_stack, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>|
ACTLR_B1TCMPCEN_Msk);
__set_ACTLR(actlr);
#endif
}
<|fim_prefix|>/*
* Copyright (c) 2020, Antmicro
*
* SPDX-License-Identifier: Apache-2<|fim_middle|>.0
*/
#include <zephyr/kernel.h>
#include <cmsis_core.h>
void z_arm_tcm_disable_ecc(void)
{
#if defined(CONFIG_ARMV7_R)
uint32_t actlr;
actlr =... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2021 Lexmark International, Inc.
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief New thread creation for ARM Cortex-A and Cortex-R
*
* Core thr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>m_reserved)
GTEXT(z_prep_c)
GTEXT(_isr_wrapper)
#else /* _ASMLANGUAGE */
#ifdef __cplusplus
extern "C" {
#endif
extern void *_vector_table[];
#ifdef __cplusplus
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* _VECTOR_TABLE__H_ */
<|fim_prefix|>/*
* Copyright (c) 2018 Marvell
* Copyright (c) 2018 Lex... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>otent (e.g. "addeq r0,
* r0, #1" can't be done twice, because you would add two to r0!)
*
* The fix is to check for this condition (which is very rare) on
* interrupt exit when we are switching, and if we discover we've
* interrupted such an instruction we swap the return address with a
* trampoline... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2020-2022 Qualcomm Innovation Center, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Cache manipulation
*
* This module contains functions for manipulation caches.
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/cach... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <cortex_m/cmse.h>
int arm_cmse_mpu_region_get(uint32_t addr)
{
cmse_address_info_t addr_info = cmse_TT((void *)addr);
if (addr_info.flags.mpu_region_valid) {
return ad... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>turn (uintptr_t)thread->switch_handle;
#else
return thread->callee_saved.psp;
#endif
}
<|fim_prefix|>/*
* Copyright (c) 2020 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#inclu<|fim_middle|>de <zephyr/debug/coredump.h>
#include <zephyr/kernel/thread.h>
#define A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>it_instr(); \
ON_EXIT_IDLE_HOOK; \
} while (false)
#endif
#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
void arch_cpu_idle(void)
{
#if defined(CONFIG_TRACING)
sys_trace_idle(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
/* ASSERT that we have the comparator needed for the implementation */
if (((DWT->CTRL & DWT_CTRL_NUMCOMP_Msk) >> DWT_CTRL_NUMCOMP_Pos) < 1) {
__ASSERT(0, "on board DWT does not support the feature\n");
return -EINV... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)
{
#ifdef CONFIG_PREEMPT_ENABLED
if (_kernel.ready_q.cache != _kernel.cpus->current) {
SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
}
#endif /* CONFIG_PREEMPT_ENABLED */
#ifdef CONFIG_STACK_SENTINEL
z_check_stack_sentinel();
#endif /* CONFIG_STACK_SENTINEL */
}
<|fim_prefix|>/*
* Copyright (c) 2013-2014 W... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2014 Wind River Systems, Inc.
* Copyright (c) 2020 Nordic Semiconductor ASA.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Common fault handler for ARM Cortex-M
*
* Common fault handler for ARM Cortex-M processors.
*/
#include <zephyr/kernel.h>
#include <ke... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> :);
}
#endif
}
<|fim_prefix|>/*
* Copyright (c) 2019,2020 Linaro Limited
* Copyright (c) 2021 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/cortex_m/fpu.h>
/**
* @file @brief Helper functions for s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-M interrupt initialization
*
*/
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
/**
*
* @brief Initialize interrupts
*
* Ensures all interrupts have their priorit... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-M interrupt management
*
*
* Interrupt management: enabling/disabling and dynamic ISR
* connecting/replacing. SW_ISR_TABLE_DYNAMIC has to be enabled for
* connectin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>only the external
* interrupts.
*/
irq_number -= 16;
#if defined(CONFIG_GEN_SW_ISR_TABLE_ARRAY)
const struct _isr_table_entry *entry = &_sw_isr_table[irq_number];
(entry->isr)(entry->arg);
#elif defined(CONFIG_GEN_SW_ISR_TABLE_SWITCH)
struct _isr_table_entry entry;
get_isr_entry(irq_number, &en... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_NODELABEL(pm_s2ram), zephyr_memory_region)
/* Linker section name is given by `zephyr,memory-region` property of
* `zephyr,memory-region` compatible DT node with nodelabel `pm_s2ram`.
*/
__attribute__((section(DT_PROP(DT_NODELABEL(pm_s2ram), zephyr_memory_region))))
#else
__noinit
#endif
_cpu_context_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Full C support initialization
*
*
* Initialization of full C support: zero the .bss, copy the .data if XIP,
* call z_cstart().
*
* Stack is available in this module, but not t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-M System Control Block interface
*
*
* Most of the SCB interface consists of simple bit-flipping methods, and is
* implemente... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t r0 __asm__("r0") = instr;
register void *r1 __asm__("r1") = args;
register int ret __asm__("r0");
__asm__ volatile("bkpt 0xab" : "=r"(ret) : "r"(r0), "r"(r1) : "memory");
return ret;
}
<|fim_prefix|>/*
* Copyright (c) 2022, Commonwealth Scientific and Industrial Research
* Organisation (CSIRO) AB... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright (c) 2021 Lexmark International, Inc.
* Copyright (c) 2023, 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief New thread creation for ARM Cortex-M
*
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-M k_thread_abort() routine
*
* The ARM Cortex-M architecture provid<|fim_suffix|>T_TRACING_OBJ_FUNC_EXIT(k_thread, abort, thread);
}
<|fim_middle|>es its own k_thread_abort(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Nordic Semiconductor ASA
* Copyright (c) 2020 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM Cortex-M Timing functions interface based on DWT
*
*/
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/timing/timing.h... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Definitions for the boot vector table
*
*
* Definitions for the boot vector table.
*
* System exception handler names all have the same format:
*
* __<exception name with underscores>
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation
* Copyright (c) 2024 Schneider Electric
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/llext/elf.h>
#include <zephyr/llext/llext.h>
#include <zephyr/llext/llext_internal.h>
#include <zephyr/llext/loader.h>
#include <zephyr/logging/log.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>allee->v3);
EXCEPTION_DUMP("r7/v4: 0x%08x r8/v5: 0x%08x r9/v6: 0x%08x",
callee->v4, callee->v5, callee->v6);
EXCEPTION_DUMP("r10/v7: 0x%08x r11/v8: 0x%08x psp: 0x%08x",
callee->v7, callee->v8, callee->psp);
}
EXCEPTION_DUMP("EXC_RETURN: 0x%0x", esf->extra_info.exc_return);
#endif /... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
}
return ret;
}
<|fim_prefix|>/*
* Copyright (c) 2023 Marek Vedral <vedrama5@fel.cvut.cz>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <kernel_internal.h>
#include <zephyr/arch/arm/gdbstub.h>
#include <zephyr/debug/gdbstub.h>
/* Position of each register in the p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2015 Intel corporation
* Copyright 2025<|fim_suffix|>RT)
/* ARMv6-M HardFault if you make a SVC call with interrupts locked.
*/
__ASSERT(__get_PRIMASK() == 0U, "irq_offload called with interrupts locked\n");
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE && CONFIG_ASSERT */
k_sched_l... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* ARMv7 MMU support
*
* This implementation supports the Short-descriptor translation
* table format. The standard page size is 4 kB, 1 MB sections
* are only used for mapping the code and data of the Zephyr image.
* Secure mode and PL1 is always assumed. LPAE and PXN extensions
* as well as TEX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* ARMv7 MMU support
*
* Private data declarations
*
* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_ARCH_AARCH32_ARM_MMU_PRIV_H_
#define ZEPHYR_ARCH_AARCH32_ARM_MMU_PRIV_H_
/*
* Comp.:
* ARM Architecture Reference Manual, ARMv7... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited.
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include "arm_core_mpu_dev.h"
#include <zephyr/linker/lin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>/
/* ARM Core MPU Driver API */
/*
* This API has to be implemented by all the MPU drivers that have
* ARM_MPU support.
*/
/**
* @brief configure a set of fixed (static) MPU regions
*
* Internal API function to configure a set of static MPU memory regions,
* within a (background) memory area de... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Linaro Limited.
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/cache.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/barrier.h>
#include "arm_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>AM_REGION_ATTR(REGION_SRAM_SIZE)),
#endif
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/sys/slist.h>
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited.
* Copyright (c) 2018 Nordic Semiconductor ASA.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_MPU_ARM_MPU_V7_INTERNAL_H_
#define ZEPHYR_ARCH_ARM_CORE_AARCH32_MPU_ARM_MPU_V7_INTERNAL_H_
#include <zephyr/sys/math_extras.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited.
* Copyright (c) 2018 Nordic Semiconductor ASA.
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_ARCH_ARM_CORE_AARCH32_MPU_ARM_MPU_V8_INTERNAL_H_
#define ZEPHYR_ARCH_ARM_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)
{
set_region_number(index);
return (get_region_size() & MPU_RASR_ENABLE_Msk) ? 1 : 0;
}
/**
* This internal function returns the access permissions of an MPU region
* specified by its region index.
*
* Note:
* The caller must provide a valid region number.
*/
static inline uint32_t get_regio... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2019 Lexmark International, Inc.
*/
#include <zephyr/sys/math_extras.h>
/**
* Get the number of supported MPU regions.
*/
static inline uint8_t get_num_regions(void)
{
uint32_t type = MPU->TYPE;
type = (type & MPU_TYPE_DREGION_Msk) >> MPU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include "arm_core_mpu_dev.h"
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/math_extras.h>
#include <zephyr/sys/ba... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>echanism for hooking a
* custom run time handler.
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/sys/printk.h>
#include <zephyr/sys/reboot.h>
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
extern void z_SysNmiOnReset(void);
#if !defined(CONFIG_RUNTIME_NM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ts_aarch32.c"
GEN_ABS_SYM_END
<|fim_prefix|>/*
* Copyright (c) 2019 Car<|fim_middle|>lo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <gen_offset.h>
#include "offse<|endoftext|> | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifi<|fim_suffix|>info_t, start);
#endif
/*
* CPU context for S2RAM
*/
#if defined(CONFIG_PM_S2RAM)
GEN_OFFSET_SYM(_cpu_context_t, msp);
GEN_OFF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (C) 2025 Synaptics Incorporated
* Author: Jisheng Zhang <jszhang@kernel.org>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/debug/symtab.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/exception.h>
#include <zephyr/linker/linker-defs.h>
#include <kernel_internal.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <kernel_internal.h>
#include <kernel_tls.h>
#include <zephyr/app_memory/app_memdomain.h>
#include <zephyr/sys/util.h>
#ifdef CONFIG_CPU_CORTEX_M
/*
* Since Cortex-M does not have... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>->nested;
#ifdef CONFIG_SMP
arch_irq_unlock(key);
#endif
return nested != 0U;
}
static ALWAYS_INLINE bool arch_is_in_nested_exception(const struct arch_esf *esf)
{
return (_current_cpu->arch.exc_depth > 1U) ? (true) : (false);
}
/**
* @brief No current implementation where core dump is not supported... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>d z_arm_userspace_enter(k_thread_entry_t user_entry,
void *p1, void *p2, void *p3,
uint32_t stack_end,
uint32_t stack_start,
uint32_t sp_is_priv);
extern void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf);
#endif /* _ASMLANGUAGE */
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>def __cplusplus
}
#endif
#endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_A_R_STACK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2018 Lexmark International, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Stack helpers for Cortex-A and Cortex-R CPUs
*
* Stack helper functions.
*/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020, Antmicro
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Management for Tightly Coupled Memory
*
*/
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_A_R_TCM_H_
#define ZEPHYR_AR<|fim_suffix|> Banks
*
* Notes:
*
* This function shall only be called in Pr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>e The size of the address range
* @param force_npriv Instruct to return the readability of the address range
* for unprivileged access, regardless of whether the current
* mode is privileged or unprivileged.
*
* @return 1 if address range is readable, 0 otherwise... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
<|fim_suffix|>ace based on DWT
*
*/
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_DEBUG_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_DEBUG_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Assess whether a debug monitor event should be treated as an error
*
* This routine checks the status of a ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Nordic Semiconductor ASA
* Copyright (c) 2020 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief DWT utility functions for Cortex-M CPUs
*
*/
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_DWT_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>reFault
* in a PE with the Main Extension instead generate a
* SecureHardFault in a PE without the Main Extension.
*/
#endif /* ARM_SECURE_FIRMWARE && !ARM_SECURE_BUSFAULT_HARDFAULT_NMI */
#if defined(CONFIG_CPU_CORTEX_M_HAS_SYSTICK) && !defined(CONFIG_CORTEX_M_SYSTICK)
/* SoC implements SysTick, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Private kernel definitions (ARM)
*
* This file contains private kernel function definitions a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Stack helpers for Cortex-M CPUs
*
* Stack helper functio<|fim_suffix|>usplus
extern "C" {
#endif
K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_I... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief TrustZone API for use in nonsecure firmware
*
* TrustZone API for Cortex-M CPUs implementing the Security Extension.
* The following API can be used by the nonsecure firmware to interact with the
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>plusplus
extern "C" {
#endif
typedef struct arch_esf _esf_t;
typedef struct __basic_sf _basic_sf_t;
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
typedef struct __fpu_sf _fpu_sf_t;
#endif
#ifdef CONFIG_ARM_MPU
struct z_arm_mpu_partition {
uintptr_t start;
size_t size;
k_mem_partition_attr_t ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>C_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_
#include <kernel_arch_data.h>
#if defined(CONFIG_CPU_CORTEX_M)
#include <cortex_m/kernel_arch_func.h>
#else
#include <cortex_a_r/kernel_arch_func.h>
#endif
#endif /* ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ */
<|fim_prefix|>/*
* Copyright (c)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Definitions for boot code
*/
#ifndef _BOOT_H_
#define _BOOT_H_
#ifndef _ASMLANGUAGE
#include <stdbool.h>
#include <zephyr/toolchain.h>
extern void *_vector_table[];
exter... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Huawei Technologies SASU
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <zephyr/debug/coredump.h>
<|fim_suffix|>
uint64_t x2;
uint64_t x3;
uint64_t x4;
uint64_t x5;
uint64_t x6;
uint64_t x7;
uint64_t x8;
uint64_t x9;
uint64_t x10;
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r_cpu()->id]);
#endif
return;
}
#if defined(CONFIG_USERSPACE) || defined(CONFIG_ARM64_STACK_PROTECTION)
static int insert_region(struct dynamic_region_info *dyn_regions, uint8_t region_num,
uintptr_t start, size_t size, struct arm_mpu_region_attr *attr);
static void arm_core_mpu_background_region_e... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
* Copyright (c) 2026 Synaptics Incorporated
* Author: Jisheng Zhang <jszhang@kernel.org>
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* ARM64 Cortex-A power management
*/
#include <zephyr/kernel.h>
#include <zephyr/tracing/tracing.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>UMP26:
ret = imm_reloc_handler(rel, reloc_type, loc, sym_base_addr);
/* TODO Handle case when address exceeds +/- 128MB */
break;
default:
LOG_ERR("unknown relocation: %llu\n", reloc_type);
return -ENOEXEC;
}
if (overflow_check && ret == -ERANGE) {
LOG_ERR("sym '%s': relocation out of ran... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_info.start + thread->stack_info.size);
return (addr >= start) && (addr < end) && is_address_mapped(addr);
#elif defined(CONFIG_THREAD_LOCAL_STORAGE)
uintptr_t end;
end = thread->tls;
return (addr < end) && is_address_mapped(addr);
#else
ARG_UNUSED(thread);
return is_address_mapped(addr);
#endif
}
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ed_fp_context);
}
_current->arch.saved_fp_context.sve.simd_mode = SIMD_SVE;
} else if (_current->arch.saved_fp_context.sve.simd_mode != SIMD_SVE) {
/* not SVE trap and context is not SVE either */
if ((cpacr & CPACR_EL1_ZEN) != 0) {
/* disable SVE access leaving only FP */
cpacr &= ~CPACR_E... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM64 Cortex-A interrupt initialisation
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/interrupt_controller/gic.h>
/**
* @brief Initialise interrupts
*
* T... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM64 Cortex-A interrupt management
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/tracing/tracing.h>
#include <zephyr/irq.h>
#include <zephyr/t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>LL_IRQ_OFFLOAD),
"r" (x0), "r" (x1));
}
void arch_irq_offload_init(void)
{
}
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Software interrupts utility code - ARM64 implementation
*/
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>o repeat these entries in their own mmu_regions.c.
*
* The banks are mapped as privileged-only (no EL0 access) device memory in the
* default secure state. This is the only sensible configuration: the GIC is
* managed exclusively by the kernel and is never accessed from user mode. It
* supersedes the... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)
#define TCR_TG0_64K (1ULL << 14)
#define TCR_TG0_16K (2ULL << 14)
#define TCR_EPD1_DISABLE (1ULL << 23)
#define TCR_TG1_16K (1ULL << 30)
#define TCR_TG1_4K (2ULL << 30)
#define TCR_TG1_64K (3ULL << 30)
#define TCR_PS_BITS_4GB 0x0ULL
#define TCR_PS_BITS_64GB 0x1ULL
#define TCR_PS_BITS_1TB 0x2ULL
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NULL,
};
<|fim_prefix|>/*
* Copyright 2026 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include <zephyr/arch/arm64/arm_mmu.h>
/*
* Default, empty MMU configuration.
*
* The arch core always maps the Zephyr execution regions, the devicetree
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ARM64 kernel structure member offset definition file
*
* This module is responsible for the generation of the absolute symbols whose
* value represents the member offsets f... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ies the PAC key
* registers. Return address authentication would fail on exit since the keys used to
* sign the return address on entry would no longer match the modified keys on exit.
*
* @param new_thread Pointer to the thread being switched to
* @param old_thread Pointer to the thread being switch... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 BayLibre SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef Z_ARM64_PAGING_H
#define Z_AR<|fim_suffix|>t64_t far);
#endif /* Z_ARM64_PAGING_H */
<|fim_middle|>M64_PAGING_H
bool z_arm64_do_demand_paging(struct arch_esf *esf, uint64_t esr, uin<|endoftext|> | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>pidrro_el0((uintptr_t)&_kernel.cpus[0]);
arch_bss_zero();
arch_data_copy();
#ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
/* After bss clean, _kernel.cpus is in bss section */
z_arm64_safe_exception_stack_init();
#endif
z_arm64_mm_init(true);
z_arm64_interrupt_init();
z_cstart();
CODE_UNREACHABLE;
}
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t implemented", __func__);
ARG_UNUSED(type);
}
#endif
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/reboot.h>
#include <zephyr/drivers/pm_cpu_ops.h>
LOG_MODULE_DECLARE(os, CONFIG_KERNE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel_internal.h>
#include <zephyr/arch/cache.h>
#include <zephyr/sys/barrier.h>
#if defined(CONFIG_GIC_V3)
#include <zephyr/drivers/interrupt_controller/gic.h>
#endif
#include "boot.h"
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>et __asm__ ("x0");
__asm__ volatile ("hlt 0xf000"
: "=r" (ret) : "r" (w0), "r" (x1) : "memory");
return ret;
}
<|fim_prefix|>/*
* Copyright (c) 2022, Commonwealth Scientific and Industrial Research
* Organisation (CSIRO) ABN 41 687 119 230.
<|fim_middle|>*
* SPDX-License-Identifier: Apache-2.0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CONNECT(SGI_FPU_IPI, IRQ_DEFAULT_PRIORITY, flush_fpu_ipi_handler, NULL, 0);
irq_enable(SGI_FPU_IPI);
#endif
return 0;
}
#endif
<|fim_prefix|>/*
* Copyright 2020 NXP
*
* SPDX-License-Identifier: Apache-2.0
*
*/
/**
* @file
* @brief codes required for AArch64 multicore and Zephyr smp support
*/... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief New thread creation for ARM64 Cortex-A
*
* Core thread related primitives for the ARM64 Cortex-A
*/
#include <zephyr/kernel.h>
#include <kernel_internal.h>
#include <zephyr/arch/cpu.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <kernel_internal.h>
#include <kernel_tls.h>
#include <zephyr/app_memory/app_memdomain.h>
#include <zephyr/sys/util.h>
size_t arch_tls_stack_setup(struct k_thread *new_thread, char... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>(const shared_info_t *shared_page)
{
struct xen_add_to_physmap xatp;
xatp.domid = DOMID_SELF;
xatp.idx = 0;
xatp.space = XENMAPSPACE_shared_info;
xatp.gpfn = (((xen_pfn_t) shared_page) >> XEN_PAGE_SHIFT);
return HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp);
}
static int xen_enlighten_init(v... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Exception/interrupt context helpers for Cortex-A CPUs
*
* Exception/interrupt context helpers.
*/
#ifndef ZEPHYR_ARCH_ARM64_IN<|fim_suffix|>nested;
#ifdef CONFIG_SMP
unsi... | fim | zephyrproject-rtos/zephyr | c |
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