text stringlengths 14 100k | source stringclasses 1
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/*
* Copyright 2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT waveshare_dsi2dpi
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/display.h>
#include <zephyr/drivers/mipi_dsi.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Rohit Gujarathi
* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sharp_ls0xx
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ls0xx, CONFIG_DISPLAY_LOG_LEVEL);
#include <string.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Intel Corporation
* Copyright (c) 2021, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This tool uses display controller driver API and requires
* a suitable LED matrix controller driver.
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <string.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> },
{ 1, 0, 0, 1, 0 },
{ 1, 0, 0, 1, 0 },
{ 0, 1, 1, 1, 1 }),
/* 'v' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 0, 0, 1 },
{ 0, 1, 0, 1, 0 },
{ 0, 0, 1, 0, 0 }),
/* 'w' */
MB_IMAGE({ 0, 0, 0, 0, 0 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 0, 0, 1 },
{ 1, 0, 1, 0, 1 },
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Intel Corporation
*
* SPDX-License-Identifier: Apache-<|fim_suffix|>n const struct mb_image mb_font[MB_FONT_COUNT];
<|fim_middle|>2.0
*/
#define MB_FONT_COUNT 95
#define MB_FONT_START ' '
#define MB_FONT_END '~'
exter<|endoftext|> | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
ret = ssd1322_write_command(dev, SSD1322_DISPLAY_ON, NULL, 0);
if (ret < 0) {
return ret;
}
return 0;
}
static int ssd1322_set_pixel_format(const struct device *dev,
const enum display_pixel_format pixel_format)
{
struct ssd1322_data *data = dev->data;
if (pixel_format == PIXEL_FORMAT_... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Andreas Sandberg
* Copyright (c) 2018-2020 PHYTEC Messtechnik GmbH
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_LEVEL CONFIG_DISPLAY_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ssd16xx);
#include <string.h>
#include <zephyr/device.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* ssd16xx_regs.h - Registers definition for SSD16XX compatible controller */
/*
* Copyright (c) 2018 PHYTEC Messtechnik GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SSD16XX_REGS_H__
#define __SSD16XX_REGS_H__
#define SSD16XX_CMD_GDO_CTRL 0x01
#define SSD16XX_CMD_GDV_CTRL 0x03
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Cactus Engineering S.L
* Copyright (c) 2022 Andreas Sandberg
* Copyright (c) 2020 PHYTEC Messtechnik GmbH
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/display... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>uint8_t hres;
uint8_t vres;
} __packed;
BUILD_ASSERT(sizeof(struct uc81xx_tres8) == 2);
struct uc81xx_ptl8 {
uint8_t hrst;
uint8_t hred;
uint8_t vrst;
uint8_t vred;
uint8_t flags;
} __packed;
BUILD_ASSERT(sizeof(struct uc81xx_ptl8) == 5);
struct uc81xx_tres16 {
uint16_t hres;
uint16_t vres;
} ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* SPDX-FileCopyrightText: Copyright (c) 2026 AMD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors */
/*
* Copyright (c) 2026 AMD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <stdio.h>
#include <string.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/driv... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors */
/*
* Copyright (c) 2026 AMD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_DMA_AMD_ACP_HOST_H_
#d<|fim_suffix|>TS
#define ACP_DMA_CHAN_SIZE 0x4
#define ACP_DMA_CHAN_OFFSET(chan) (ACP_DMA_CHAN_SIZE * (ch... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors */
/*
* Copyright (c) 2026 AMD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <stdio.h>
#include <string.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/driv... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>pool = lli_pool_##n,)) \
}; \
\
DEVICE_DT_INST_DEFINE(n, &dma_ameba_init, NULL, &dma_data_##n, &... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> size (msize) defined on bits 12-16.
*
* @param value Packed configuration value (burst size can be 1, 4, 8, 16).
*/
#define AMEBA_DMA_SRC_BST_SIZE_GET(value) ((value >> 12) & 0x1F)
/**
* @brief Destination burst size (msize) defined on bits 17-21.
*
* @param value Packed configuration value (burst... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_write32(0, DMA_CH_CTRL(dev, channel));
sys_write32(FIELD_GET(DMA_INT_STATUS_ABORT_MASK, (channel)), DMA_INT_STATUS(dev));
data->chan[channel].status.busy = false;
k_spin_unlock(&data->lock, key);
return 0;
}
static int dma_atcdmacx00_init(const struct device *dev)
{
struct dma_atcdmacx00_data *co... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT realtek_bee_dma
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/bee_clock_control.h>
#include <zephyr/drivers/dma.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>s_read32(cfg->base_reg + DMA_TOP_CONFIG_OFFSET);
tmp |= DMA_E;
sys_write32(tmp, cfg->base_reg + DMA_TOP_CONFIG_OFFSET);
/* Ensure all channels are disabled and their interrupts masked */
for (int i = 0; i < BFLB_DMA_CH_NB; i++) {
tmp = sys_read32(cfg->base_reg + DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, \
.weight = 0, \
}, \
.chan[6] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[7] = { \
.class = 6, \
.weight = 0, \
}, \
}; \
\
static void dw_dma##inst##_irq_config(void); \
\
static const struct... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT snps_designware_dma_axi
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/cache.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <stdio.h>
#include <string.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/pm/device.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>els_atomic, DW_CHAN_COUNT);
};
/* Device constant configuration parameters */
struct dw_dma_dev_cfg {
uintptr_t base;
void (*irq_config)(void);
};
static ALWAYS_INLINE void dw_write(uintptr_t dma_base, uint32_t reg, uint32_t value)
{
*((volatile uint32_t *)(dma_base + reg)) = value;
}
static ALWAYS_... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023, Meta
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <stdint.h>
#include <stdio.h>
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/util.h>
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022-2026 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_gdma
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dma_esp32_gdma, CONFIG_DMA_LOG_LEVEL);
#include <hal/gdma_hal.h>
#include <hal/gdma_hal_ahb.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ch) = DMA_CHMADDR_RESET_VALUE;
GD32_DMA_INTC(reg) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, ch);
#endif
}
/*
* Utility functions
*/
static inline uint32_t dma_gd32_priority(uint32_t prio)
{
return CHCTL_PRIO(prio);
}
static inline uint32_t dma_gd32_memory_width(uint32_t width)
{
switch (width) {
ca... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
static const struct ifx_cat1_dma_config ifx_cat1_dma_config##n = { \
.num_channels = DT_INST_PROP(n, dma_channels), \
.regs = (DW_Type *)DT_INST_REG_ADDR(n), ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>eon_dmac_resume,
.get_status = infineon_dmac_get_status,
.chan_filter = infineon_dmac_chan_filter,
.chan_release = infineon_dmac_chan_release,
};
#define INFINEON_DMAC_INIT(n) \
static void infineon_dmac_irq_config_##n(void) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief DMA driver for Infineon CAT1 MCU family.
*/
#define DT_DRV_COMPAT infineon_dma
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <adsp_interrupt.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/cache.h>
#define DT_DRV_COMPAT intel_adsp_gpdma
#define GPDMA_CTL_OFFSET 0x0004
#define GPDMA_CTL_FDCGB BIT(0)
#define GPDMA_CTL_DCGD BI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> i++) {
dma_ctx = (struct dma_context *)host_dev[i]->data;
cfg = host_dev[i]->config;
enabled_chs = atomic_get(dma_ctx->atomic);
for (j = 0; enabled_chs && j < dma_ctx->dma_channels; j++) {
if (!(enabled_chs & BIT(j))) {
continue;
}
enabled_chs &= ~(BIT(j));
if (!intel_adsp_hda_is... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_DMA_INTEL_ADSP_HDA_COMMON_H_
#define ZEPHYR_DRIVERS_DMA_INTEL_ADSP_HDA_COMMON_H_
#define INTEL_ADSP_HDA_MAX_CHANNELS DT_PROP(DT_NODELABEL(hda_host_out), dma_channels)
/* Minimum recommended FPI increment ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ig, POST_KERNEL, \
CONFIG_DMA_INIT_PRIORITY, \
&intel_adsp_hda_dma_host_in_api); \
\
static void intel_adsp_hda_dma##inst##_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(i... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_adsp_hda_host_out
#include <zephyr/drivers/dma.h>
#include <adsp_interrupt.h>
#include "dma_intel_adsp_hda.h"
#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_adsp_hda_link_in
#include <zephyr/drivers/dma.h>
#include "dma_intel_adsp_hda.h"
#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
#include <zep<|fim_suffix|>op,
.suspend = intel_adsp_hda_dma_sto... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_adsp_hda_link_out
#include <zephyr/drivers/dma.h>
#include "dma_intel_adsp_hda.h"
#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dma_intel_ad... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_lpss
#include <errno.h>
#include <stdio.h>
#include <string.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/dma.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020 Broadcom
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DMA_IPROC_PAX
#define DMA_IPROC_PAX
/* Broadcom PAX-DMA RM register defines */
#define PAX_DMA_REG_ADDR(_base, _offs) ((_base) + (_offs))
#define PAX_DMA_RING_ADDR_OFFSET(_ring) (0x10000 * (_ring))
/* Per-Ring register... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020 Broadcom
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT brcm_iproc_pax_dma_v1
#include <zephyr/arch/cpu.h>
#include <zephyr/cache.h>
#include <errno.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/linker/sections.h>
#include <soc.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2020 Broadcom
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DMA_IPROC_PAX_V1
#define DMA_IPROC_PAX_V1
#include "dma_iproc_pax.h"
/* Register RM_CONTROL fields */
#define RM_COMM_MSI_INTERRUPT_STATUS_MASK 0x30d0
#define RM_COMM_MSI_INTERRUPT_STATUS_CLEAR 0x30d4
#define RM_COMM_CONTROL_MODE_MA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>else {
LOG_INF("PAX DMA RM HW Init Done\n");
}
return ret;
}
static void rm_cfg_start(struct dma_iproc_pax_data *pd)
{
uint32_t val;
k_mutex_lock(&pd->dma_lock, K_FOREVER);
/* set config done 0, enable toggle mode */
val = sys_read32(RM_COMM_REG(pd, RM_COMM_CONTROL));
val &= ~RM_COMM_CONTROL_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>63:60*/
} __attribute__ ((__packed__));
#endif
<|fim_prefix|>/*
* Copyright 2020 Broadcom
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef DMA_IPROC_PAX_V2
#define DMA_IPROC_PAX_V2
#include "dma_iproc_pax.h"
#define RING_COMPLETION_INTERRUPT_STAT_MASK 0x088
#define RING_COMPLETION_INTERRUPT_STAT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_STATUS_OKAY(MAX32_DMA_INIT)
<|fim_prefix|>/*
* Copyright (c) 2023 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>he specified DMA channel and fills
* the provided dma_status structure with relevant information.
*
* @param dev Pointer to the DMA device structure.
* @param channel DMA channel number to retrieve the status for.
* @param stat Pointer to a dma_status structure to store the status.
*
* @return 0 on... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ev, channel);
if (ch_state != DMA_MCHP_CH_ACTIVE) {
LOG_INF("nothing to suspend as dma channel %u is not busy", channel);
}
key = irq_lock();
/* Select the channel */
DMAC_REG->DMAC_CHID = channel;
/* Read-modify-write CHCTRLB */
chctrlb = DMAC_REG->DMAC_CHCTRLB;
chctrlb &= ~DMAC_CHCTRLB_CMD_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>0;
}
/*
* This function is used by the DMA framework to determine whether a given
* channel is suitable for allocation based on the optional user-provided
* filter parameter.
*
* If no filter parameter is provided (i.e., filter_param is NULL), the
* function returns true, allowing any available cha... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> & BIT(XEC_DMA_CHAN_CTRL_DIS_HWFL_POS)) {
status->dir = MEMORY_TO_MEMORY;
} else if (chan_ctrl & BIT(XEC_DMA_CHAN_CTRL_M2D_POS)) {
status->dir = MEMORY_TO_PERIPHERAL;
} else {
status->dir = PERIPHERAL_TO_MEMORY;
}
status->total_copied = chan_data->total_curr_xfr_len;
return 0;
}
int xec_dma_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>* Enable the peripheral DMA request in the previous TCD
*/
EDMA_TCD_CSR(pre_tcd, EDMA_TCD_TYPE((void *)DEV_BASE(dev))) &=
~DMA_CSR_DREQ(1U);
if (data->transfer_settings.empty_tcds == CONFIG_DMA_TCD_QUEUE_SIZE - 1 ||
hw_id == (uint32_t)tcd) {
/* DMA is running on last transfer. HW has l... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020-2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Common part of DMA drivers for some NXP SoC.
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <soc.h>
#include <zephyr/drivers/dma.h>
#include <fsl_dma.h>
#include <fsl_inputmux.h>
#if defined(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_PXP_V3))
ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatARGB8888;
#else
ps_buffer_cfg.pixelFormat = kPXP_PsPixelFormatRGB888;
#endif
output_buffer_cfg.pixelFormat = kPXP_OutputPixelFormatRGB888;
bytes_per_pixel = 3;
break;
case DMA_MCUX_PXP_FMT_ARGB8888:
ps_buffer_cfg.pixelFormat = kPXP_PsPix... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/policy.h>
#include <zephyr/drivers/dma/dma_mcux_smartdma.h>
#include <soc.h>
#include <fsl_smartdma.h>
#include <fsl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dev, 0, DT_INST_IRQN(0));
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
nios2_msgdma_isr, DEVICE_DT_INST_GET(0), 0);
irq_enable(DT_INST_IRQN(0));
return 0;
}
ALTERA_MSGDMA_CSR_DESCRIPTOR_SLAVE_INSTANCE(MSGDMA_0, MSGDMA_0_CSR,
MSGDMA_0_DESCRIPTOR_SLAVE, msgdma_dev0)
static struct... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
static void dma_npcx_##n##_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), dma_npcx_isr, \
DEVICE_DT_INST... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>truct device *dev) \
{ \
nxp_dma_isr(dev, ch); \
}
/* Per-instance macros, connect each channel IRQ by index. */
#define NXP_DMA_IRQ_CFG_FUNC(inst) \
static void _CONCAT(nxp_dma_irq_config_func, inst)(const struct device *dev) \
{ \
IF_ENABLED(DT_INST_IRQ_HAS_IDX(ins... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>d(data->hal_cfg, chan_id, EDMA_TCD_CH_CSR) &
EDMA_TCD_CH_CSR_DONE_MASK;
if (done) {
stat->free = chan->bsize;
stat->pending_length = 0;
} else {
stat->free = (biter - citer) * (chan->bsize / biter);
stat->pending_length = chan->bsize - stat->free;
}
}
LOG_DBG("free: %d, pending: %d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> function is used in edma_isr() for PRODUCER channels to mark
* that data has been produced (i.e: data has been transferred to the
* destination) (this is done via EDMA_CHAN_PRODUCE_CONSUME_A that's
* called in edma_isr()). For consumer channels, this function is used
* in edma_reload() to mark the fa... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
{ \
.magic = DMA_MAGIC, \
.dma_channels = DT_INST_PROP(n, dma_channels), \
.atomic = dma_nxp_gd... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>static const struct sdma_dev_cfg sdma_cfg_##inst = { \
.base = (SDMAARM_Type *)DT_INST_REG_ADDR(inst), \
.irq_config = dma_nxp_sdma_##inst_irq_config, \
}; \
static void dma_nxp_sdma_##inst_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, pr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/dma.h>
#include <zephyr/logging/log.h>
#include <zephyr/cache.h>
/* used for driver binding */
#define DT_DRV_COMPAT nxp_sof_host_dma
/* macros used to parse DTS properties */
#define IDENTITY_VARGS(V, ...) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_callback;
channel_cfg->user_data = cfg->user_data;
if (cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_INCREMENT ||
cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_NO_CHANGE) {
channel_cfg->src_addr_adj = cfg->head_block->source_addr_adj;
} else {
return -ENOTSUP;
}
if (cfg->head_block-... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EC_VALUE 0x0
#define OP_DMA_MOV 0xbc
#define OP_DMA_LOOP_COUNT1 0x22
#define OP_DMA_LOOP 0x20
#define OP_DMA_LD 0x4
#define OP_DMA_ST 0x8
#define OP_DMA_SEV 0x34
#define OP_DMA_END 0x00
#define OP_DMA_LP_BK_JMP1 0x38
#define OP_DMA_LP_BK_JMP2 0x3c
#define SZ_CMD_DMAMOV 0x6
enum dmamov_type {
/* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>2_t data_size = ch->config.source_data_size;
fsp_err_t err;
/* Validate the DMA channel */
if (!dma_renesas_ra_channel_is_valid(dev, channel)) {
LOG_DBG("DMA channel %d is invalid.", channel);
return -EINVAL;
}
/* Check if the DMA channel is open */
if (ch->fsp_ctrl.open == 0) {
LOG_DBG("DMA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nnel_common_checks(dev, channel);
if (ret) {
return ret;
}
dma_instance_ctrl_t *p_ctrl = (dma_instance_ctrl_t *)data->channels[channel].fsp_ctrl;
#ifdef CONFIG_CPU_CORTEX_A
/* Check whether a transfer is suspended. */
if (0 == p_ctrl->p_reg->CHSTAT_b.SUS) {
LOG_ERR("%d: DMA channel not suspend... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
/* Used to store interrupt and priority for channels */
#define RZ_DMA_CHANNEL_DECLARE(n, inst) \
{ ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>if
irq_unlock(key);
return 0;
}
static int dma_sam0_stop(const struct device *dev, uint32_t channel)
{
unsigned int key = irq_lock();
ARG_UNUSED(dev);
#ifdef DMAC_CHID_ID
DMA_REGS->CHID.reg = channel;
DMA_REGS->CHCTRLA.reg = 0;
#else
DmacChannel * chcfg = &DMA_REGS->Channel[channel];
chcfg->... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 comsuisse AG
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam_xdmac
/** @file
* @brief Atmel SAM MCU family Direct Memory Access (XDMAC) driver.
*/
#include <errno.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/device.h>
#include <zephyr/ini... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>mbr_nda;
/** Microblock Control */
uint32_t mbr_ubc;
/** Source Address */
uint32_t mbr_sa;
/** Destination Address */
uint32_t mbr_da;
/** Configuration Register */
uint32_t mbr_cfg;
};
/** DMA Master transfer linked list view 3 structure */
struct sam_xdmac_linked_list_desc_view3 {
/** Next De... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_sedi_dma
#include <errno.h>
#include <stdio.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <string.h>
#include <zephyr/init.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
config->channels[channel].direction = config_dma->channel_direction;
config->channels[channel].size = config_dma->source_data_size;
return 0;
}
static int dma_sf32lb_reload(const struct device *dev, uint32_t channel, uint32_t src, uint32_t dst,
size_t size)
{
const struct dma_sf32lb_config ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ported by HW");
return -ENOTSUP;
case 0b10: /* no change */
channel_descriptor->SRCEND.U32 = block->source_address;
channel_descriptor->CONFIG.SRCAIMD = 0b11;
break;
default:
LOG_ERR("Unknown source_addr_adj value");
return -EINVAL;
}
switch (block->dest_addr_adj) {
case 0b00: /* increme... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r.linkAddr || config->head_block->next_block) {
return -EINVAL;
}
/* A link is already set by a previous call to the function */
if (sys_test_bit((mem_addr_t)&LDMA->CH[channel].LINK, _LDMA_CH_LINK_LINK_SHIFT)) {
return -EINVAL;
}
ret = dma_silabs_block_to_descriptor(config, chan_conf, block_con... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_gpdma
#include <zephyr/irq.h>
#include <zephyr/sys/mem_blocks.h>
#include <zephyr/spinlock.h>
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/clock_control.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2026 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* This driver was originally based on upper layer of the Wiseconnect HAL (the
* UDMAx_*() functions). This layer does not support Scatter-Gather transfers.
* Implementation of Scatter-Gather has been i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>>= DMA_SMARTBOND_CHANNEL_PRIO_MAX) {
cfg->channel_priority = DMA_SMARTBOND_CHANNEL_PRIO_7;
LOG_WRN("Channel priority exceeded max. Setting to highest valid level");
}
DMA_CTRL_REG_SET_FIELD(DMA_PRIO, dma_ctrl_reg, cfg->channel_priority);
if (((cfg->source_burst_length != cfg->dest_burst_length) |... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
DMA_STM32_DEFINE_IRQ_HANDLER(0, 2);
#if DT_INST_IRQ_HAS_IDX(0, 3)
DMA_STM32_DEFINE_IRQ_HANDLER(0, 3);
DMA_STM32_DEFINE_IRQ_HANDLER(0, 4);
#if DT_INST_IRQ_HAS_IDX(0, 5)
DMA_STM32_DEFINE_IRQ_HANDLER(0, 5);
#if DT_INST_IRQ_HAS_IDX(0, 6)
DMA_STM32_DEFINE_IRQ_HANDLER(0, 6);
#if DT_INST_IRQ_HAS_IDX(0, 7)
DMA_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>bool stm32_dma_is_tc_irq_active(DMA_TypeDef *dma, uint32_t id);
void stm32_dma_dump_stream_irq(DMA_TypeDef *dma, uint32_t id);
void stm32_dma_clear_stream_irq(DMA_TypeDef *dma, uint32_t id);
bool stm32_dma_is_irq_happened(DMA_TypeDef *dma, uint32_t id);
bool stm32_dma_is_unexpected_irq_happened(DMA_TypeD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dma_stm32_clear_tc(dma, id);
bdma_stm32_clear_ht(dma, id);
bdma_stm32_clear_te(dma, id);
}
bool stm32_bdma_is_enabled_channel(BDMA_TypeDef *dma, uint32_t id)
{
if (LL_BDMA_IsEnabledChannel(dma, bdma_stm32_id_to_channel(id)) == 1) {
return true;
}
return false;
}
int stm32_bdma_disable_channel(BDM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>uint32_t id);
bool stm32_bdma_is_tc_irq_active(BDMA_TypeDef *ma, uint32_t id);
void stm32_bdma_dump_channel_irq(BDMA_TypeDef *dma, uint32_t id);
void stm32_bdma_clear_channel_irq(BDMA_TypeDef *dma, uint32_t id);
bool stm32_bdma_is_irq_happened(BDMA_TypeDef *dma, uint32_t id);
void stm32_bdma_enable_chann... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>u bursts per beat is unsupported; falling back to single-beat burst",
beats_in_burst);
return LL_DMA_MBURST_SINGLE;
}
}
uint32_t stm32_dma_get_pburst(struct dma_config *config, bool source_periph)
{
uint32_t per_data_size, per_burst_size;
if (source_periph) {
per_data_size = config->source_dat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>F8)
LL_DMA_ClearFlag_TE8,
#endif /* LL_DMA_IFCR_CTEIF4 */
#endif /* LL_DMA_IFCR_CTEIF6 */
#endif /* LL_DMA_IFCR_CTEIF7 */
#endif /* LL_DMA_IFCR_CTEIF8 */
};
__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
func[id](DMAx);
}
void dma_stm32_clear_gi(DMA_TypeDef *DMAx, uint32_t id)
{
static const dma_stm32_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Linaro Limited.
* Copyright (c) 2019 Song Qiang <songqiang1304521@gmail.com>
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Common part of DMA drivers for stm32U5.
* @note Functions named with stm32_dma_* are SoCs related f... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc23x0_dma
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dma_cc23x0, CONFIG_DMA_LOG_LEVEL);
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/irq.h>
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
status = DMA_STATUS_COMPLETE;
} else {
return;
}
data = &dma_data->ch_data[channel];
DL_DMA_disableChannel(cfg->regs, channel);
data->busy = false;
if (data->dma_callback != NULL) {
data->dma_callback(dev, data->user_data, channel, status);
}
}
static int dma_ti_mspm0_init(const struct d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Paul Wedeck <paulwedeck@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wch_wch_dma
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/clock_control.h>
#include <hal_ch32fun.h>
#def<|fim_suffix|>BUSY;
goto end;
}
if (regs->channels[ch].... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/** @file
*@brief Driver for Xilinx AXI DMA.
*/
/*
* Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ef DMA_XILINX_AXI_DMA_H
#define DMA_XILINX_AXI_DMA_H
#define XILINX_AXI_DMA_NUM_CHANNELS 2
#define XILINX_AXI_DMA_TX_CHANNEL_NUM 0
#define XILINX_AXI_DMA_RX_CHANNEL_NUM 1
#define XILINX_AXI_DMA_LINKED_CHANNEL_NO_CSUM_OFFLOAD 0x0
#define XILINX_AXI_DMA_LINKED_CHANNEL_FULL_CSUM_OFFLOAD 0x1
#define XI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Andriy Gelman
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_dma
#include <soc.h>
#include <stdint.h>
#include <xmc_dma.h>
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 STMicroelectronics
* Copyright (c) 2023 Jeroen van Dooren, Nobleo Technology
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Common part of DMAMUX drivers for stm32.
* @note api functions named dmamux_stm32_
* are calling the dma_stm32 corresponding function
* im... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>if (config->dout_reg != NULL) {
if (pins & BIT(SWDP_SWDIO_PIN)) {
if (value & BIT(SWDP_SWDIO_PIN)) {
gpio_pin_set_dt(&config->dout, 1);
} else {
gpio_pin_set_dt(&config->dout, 0);
}
}
} else {
if (pins & BIT(SWDP_SWDIO_PIN)) {
if (value & BIT(SWDP_SWDIO_PIN)) {
gpio_pin_set_... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Private API for SWDP controller drivers
*/
#ifndef ZEPHYR_DRIVERS_DP_SWDP_COMMON_H
#define ZEPHYR_DRIVERS_DP_SWDP_COMMON_H
#include <stdint.h>
#include <zephyr/drivers/swdp.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> "FAST_BITBANG_HW_SUPPORT not defined by any soc specific driver"
#endif
<|fim_prefix|>/*
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <soc.h>
static ALWAYS_INLINE void pin_delay_asm(uint... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#define CPU_CLOCK 64000000U
#define FAST_BITBANG_HW_SUPPORT 1
static ALWAYS_INLINE void swdp_ll_pin_input(void *const base, uint8_t pin)
{
NRF_GPIO_Type *reg = base;
reg->PIN_CNF[pin] = 0b0000;
}
static A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stm32_ll_gpio.h>
#include "stm32_hsem.h"
#define CPU_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
#define FAST_BITBANG_HW_SUPPORT 1
static ALWAYS_INLINE void swdp_ll_pin_input(void *const base, uint8_t pin)
{
GPIO_Type... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_SIZE, K_MEM_CACHE_NONE);
/* Enable Host Bridge generated SERR event */
ibecc_errcmd_setup(bdf, true);
LOG_INF("IBECC driver initialized"); /* LCOV_EXCL_BR_LINE */
return 0;
}
static struct ibecc_data ibecc_data;
DEVICE_DT_DEFINE(DEVICE_NODE, &edac_ibecc_init,
NULL, &ibecc_data, NULL, POST_KER... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nject_error_trigger,
#endif /* CONFIG_EDAC_NXP_ERROR_INJECT */
/* Get error stats */
.errors_cor_get = errors_cor_get,
/* Notification callback set */
.notify_cb_set = notify_callback_set,
};
static int edac_nxp_init(const struct device *dev)
{
const struct edac_nxp_config *config = dev->config;
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>b != NULL)) {
data->notify_cb(dev, data->notify_data);
}
}
static DEVICE_API(edac, edac_nxp_mecc_api) = {
#if defined(CONFIG_EDAC_ERROR_INJECT)
.inject_set_param1 = edac_nxp_mecc_inject_set_param1,
.inject_get_param1 = edac_nxp_mecc_inject_get_param1,
.inject_set_param2 = edac_nxp_mecc_inject_set_p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Calian Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#includ<|fim_suffix|>ys_inject_set_param1,
.inject_get_param1 = edac_synopsys_inject_get_param1,
.inject_set_param2 = edac_synopsys_inject_set_param2,
.inject_get_param2 = edac_synopsys_inject_get_param2,
.inject_set_er... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_EDAC_IBECC_H_
#define ZEPHYR_DRIVERS_EDAC_IBECC_H_
/* TODO: Add to include/sys/util.h */
#define BITFIELD(val, h, l) (((val) & GENMASK(h, l)) >> l)
#define BITFIELD64(val, h, l) (((val) & GENMASK64(h, l))... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020-2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdlib.h>
#include <zephyr/device.h>
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/edac.h>
static const struct device *const edac_device = DEVICE_DT_GET_OR_NULL(DT_CHOSEN(zephyr_edac));
/... | fim | zephyrproject-rtos/zephyr | c |
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