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<|fim_prefix|>/*
* Copyright (c) 2023 Enphase Energy
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT siemens_ivshmem_eth
#include <zephyr/drivers/virtualization/ivshmem.h>
#include <zephyr/logging/log.h>
#include <zephyr/net/ethernet.h>
#include <ethernet/eth_stats.h>
#include "eth.h"
#include "... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Enphase Energy
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ETH_IVSHMEM_PRIV_H
#define ETH_IVSHMEM_PRIV_H
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <openamp/virtio_ring.h>
struct eth_ivshmem_queue {<|fim_suffix|>hmem_queue_tx_commit_buff(st... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Enphase Energy
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "eth_ivshmem_priv.h"
#include <zephyr/arch/cpu.h>
#include <zephyr/cache.h>
#include <zephyr/kernel.h>
#include <stdatomic.h>
#include <string.h>
/* These defines must match on the peer */
#define ETH_IVSHME... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
return -ENODEV;
}
/* Check SPI communication after reset */
ret = lan865x_check_spi(dev);
if (ret < 0) {
LOG_ERR("SPI communication not working, %d", ret);
return ret;
}
/*
* Configure interrupt service routine for LAN865x IRQ
*/
ret = gpio_pin_configure_dt(&cfg->interrupt, GPIO_INPUT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 DENX Software Engineering GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ETH_LAN865X_PRIV_H__
#define ETH_LAN865X_PRIV_H__
#include <stdint.h>
#include <stdbool.h>
#include <zephyr/kernel.h>
#includ<|fim_suffix|>efine LAN865x_MAC_NCFGR_MAXFS BIT(8)
#define LAN865x_MA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>9250_HMAC_CR_PRMS) == 0) {
return -EALREADY;
}
reg |= LAN9250_HMAC_CR_MCPAS;
reg &= ~LAN9250_HMAC_CR_PRMS;
reg &= ~LAN9250_HMAC_CR_HO;
}
return lan9250_write_mac_reg(dev, LAN9250_HMAC_CR, reg);
}
break;
default:
break;
}
return -ENOTSUP;
}
static const struct ether... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne LAN9250_MAC_CSR_CMD_WRITE 0x00000000
#define LAN9250_MAC_CSR_CMD_READ 0x40000000
#define LAN9250_MAC_CSR_CMD_ADDR 0x000000FF
/* Reset Control Register (RESET_CTL) */
#define LAN9250_RESET_CTL_HMAC_RST 0x00000020
#define LAN9250_RESET_CTL_PHY_RST 0x00000002
#define LAN9250_RESET_CTL_DIGITAL_RS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.tx_length_addr = DT_INST_REG_ADDR_BY_NAME(n, tx_length), \
.tx_ev_pending_addr = DT_INST_REG_ADDR_BY_NAME(n, tx_ev_pending), \
.tx_ev_enable_addr = DT_INST_REG_ADDR_BY_NAME(n, tx_ev_enable), \
.rx_buf_addr = ETH_LITEX_SLOT_RX_ADD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
*
* TAP Ethernet driver for the native_sim board. This is meant for network
* connectivity between the host and Zephyr.
*
* Note this driver is divided in two files. This one, built in the embedded ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t = -errno;
close(fd);
return ret;
}
#endif
return fd;
}
int eth_iface_remove(int fd)
{
return close(fd);
}
static int ssystem(const char *fmt, ...)
__attribute__((__format__(__printf__, 1, 2)));
static int ssystem(const char *fmt, ...)
{
char cmd[255];
va_list ap;
int ret;
va_start(ap, f... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>HYR_DRIVERS_ETHERNET_ETH_NATIVE_TAP_PRIV_H_
#define ZEPHYR_DRIVERS_ETHERNET_ETH_NATIVE_TAP_PRIV_H_
int eth_iface_create(const char *dev_name, const char *if_name, bool tun_only);
int eth_iface_remove(int fd);
int eth_wait_data(int fd);
int eth_promisc_mode(const char *if_name, bool enable);
#endif /* ZE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> m_numaker_gmacdev_packet_rx(dev);
}
if (interrupt & synopGMACDmaRxAbnormal) {
LOG_ERR("Abnormal Rx Interrupt Seen");
/* If Mac is not in powerdown */
if (gmacdev->GMAC_Power_down == 0) {
gmacdev->synopGMACNetStats.rx_over_errors++;
dma_ie &= ~DmaIntRxAbnMask;
/* To handle GBPS with 12 ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 1500
/* NuMaker chip's OUI*/
#define NUMAKER_OUI_B0 0xDA
#define NUMAKER_OUI_B1 0x00
#define NUMAKER_OUI_B2 0x53
#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_NUMAKER_PRIV_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifnde... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* NXP ENET MAC Driver
*
* SPDX-FileCopyrightText: Copyright 2023-2024, 2026 NXP
*
* Inspiration from eth_mcux.c, which was:
* Copyright (c) 2016-2017 ARM Ltd
* Copyright (c) 2016 Linaro Ltd
* Copyright (c) 2018 Intel Corporation
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* NXP ENET QOS Ethernet MAC Driver
*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_enet_qos
#include <zephyr/drivers<|fim_suffix|>name), \
.base = (enet_qos_t *)DT_INST_REG_ADDR(n), \
}; \
\
/* Init the module before any enet ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>esc *tx_desc_ptr = data->tx.descriptors;
volatile union nxp_enet_qos_tx_desc *last_desc_ptr;
struct net_buf *fragment = pkt->frags;
int frags_count = 0, total_bytes = 0, frags_idx = 0;
int ret;
#if defined(CONFIG_PTP_CLOCK_NXP_ENET_QOS)
bool pkt_is_ptp;
#endif
/* Only allow send of the maximum nor... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* NXP ENET QOS Header
*
* Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/sys/util.h>
#include <zephyr/net/ethernet.h>
#include <zephyr/drivers/ethernet/eth_nxp_enet_qos.h>
/* s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t device *dev __unused,
struct net_if *iface __unused)
{
return (ETHERNET_LINK_10BASE
| ETHERNET_LINK_100BASE
#if (FEATURE_GMAC_RGMII_EN == 1U)
| ETHERNET_LINK_1000BASE
#endif
| ETHERNET_HW_TX_CHKSUM_OFFLOAD
| ETHERNET_HW_RX_CHKSUM_OFFLOAD
#if defined(CONFIG_NET_VLAN)
| ETHERNET_HW_VLA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(nxp_s32_eth);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/mbox.h>
#include <zephyr/drivers/pinctrl.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ruct net_if *iface,
enum ethernet_config_type type,
const struct ethernet_config *config);
extern void Netc_Eth_Ip_MSIX_Rx(uint8_t si_idx);
#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_NXP_S32_NETC_PRIV_H_ */
<|fim_prefix|>/*
* Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> idx, n) \
[DT_PROP_BY_IDX(node, prop, idx) - 1] = \
&_CONCAT3(nxp_s32_eth##n##_vsi, DT_PROP_BY_IDX(node, prop, idx), _rx_msg_buf)
#define NETC_SWITCH_PORT_CFG(_, n) \
{ \
.ePort = &nxp_s32_eth##n##_switch_port_egress_cfg, \
.iPort = &nxp_s32_eth##n##_switch_port_ingress_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>esc = nxp_s32_eth##n##_rxring0_desc, \
.Buffer = nxp_s32_eth##n##_rxring0_buf, \
.ringSize = CONFIG_ETH_NXP_S32_RX_RING_LEN, \
.maxRingSize = CONFIG_ETH_NXP_S32_RX_RING_LEN, \
.bufferLen = CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZE, \
.maxBuffLen = CONFIG_ETH_NXP_S32_TX_RING_BUF_SIZ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
return -ENOTSUP;
}
__weak void net_if_carrier_on(struct net_if *iface)
{
ARG_UNUSED(iface);
}
__weak void net_if_carrier_off(struct net_if *iface)
{
ARG_UNUSED(iface);
}
<|fim_prefix|>/**
* @file
* @brief Ethernet Driver raw mode
*
* This file contains a collection of functions called from the... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ed to obtain RX buffer");
goto out;
}
if (net_pkt_write(pkt, rx_buf, len)) {
LOG_ERR("Failed to append RX buffer to context buffer");
net_pkt_unref(pkt);
pkt = NULL;
goto out;
}
out:
if (pkt == NULL) {
eth_stats_update_errors_rx(ctx->iface);
}
return pkt;
}
static void renesas_ra_eth... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
LISTIFY(ETH_RX_QUEUE_NUM(n), ETH_RX_DESC_DECLARE, (), n); \
LISTIFY(ETH_TX_QUEUE_NUM(n), ETH_TX_DESC_DECLARE, (), n); \
static rmac_queue_info_t e... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Renesas RA Ethernet RMAC header file
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_ETH_RENESAS_RA_RMAC_H__
#define ZEPHYR_INCLUDE_DRIVERS_ETH_RENESAS_RA_RMAC_H__
#include <stdint.h>
/**
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>4.reg
#define GMAC_TBFT127 TBFT127.reg
#define GMAC_TBFT255 TBFT255.reg
#define GMAC_TBFT511 TBFT511.reg
#define GMAC_TBFT1023 TBFT1023.reg
#define GMAC_TBFT1518 TBFT1518.reg
#define GMAC_GTBFT1518 GTBFT1518.reg
#define GMAC_TUR TUR.reg
#define GMAC_SCF SCF.reg
#define GMAC_MCF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ST_1(n) \
.rx_frag_list = &rx_frag_list##n##_que[PRIORITY_QUEUE1_RX_DESC_IDX],
#else
#define DEFN_RX_FLAG_LIST_1(n)
#endif
#if (GMAC_PRIORITY_QUEUE_NUM >= 2) && (GMAC_ACTIVE_PRIORITY_QUEUE_NUM >= 2)
#define DEFN_RX_FLAG_LIST_2(n) \
.rx_frag_list = &rx_frag_list##n##_que[PRIORITY_QUEUE2_R... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>eue 5 */
};
/** Receive/transmit buffer descriptor */
struct gmac_desc {
uint32_t w0;
uint32_t w1;
};
/** Ring list of receive/transmit buffer descriptors */
struct gmac_desc_list {
struct gmac_desc *buf;
uint16_t len;
uint16_t head;
uint16_t tail;
};
/** GMAC Queue data */
struct gmac_queue {
s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
ETH_NET_DEVICE_DT_INST_DEFINE(n, &sy1xx_mac_initialize, NULL, &sy1xx_mac_dev_data##n, \
&sy1xx_mac_dev_config_##n, CONFIG_ETH_INIT_PRIORITY, \
&sy1xx_mac_driver_api, NET_ETH_MTU);
DT_INST_FOREACH_STATUS_OKAY(SY1XX_MAC_INIT)
<|fim_prefix|>/*
* Copyright... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>AME);
#include <zephyr/net/ethernet.h>
#include "../net/slip.h"
static struct slip_context slip_context_data;
static enum ethernet_hw_caps eth_capabilities(const struct device *dev __unused,
struct net_if *iface __unused)
{
return ETHERNET_HW_VLAN
#if defined(CONFIG_NET_LLDP)
| ETHE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017-2018 ARM Limited
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT smsc_lan9220
/* SMSC911x/SMSC9220 driver. Partly based on mbedOS driver. */
#define LOG_MODULE_NAME eth_smsc911x
#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* SPDX-License-Identifier: Apache-2.0 */
/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
* Copyright (c) 2018-2019 Linaro Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> reg_val = smsc_read_1(sc, RCR);
if (config->promisc_mode && !(reg_val & RCR_PRMS)) {
smsc_write_1(sc, RCR, reg_val | RCR_PRMS);
} else if (!config->promisc_mode && (reg_val & RCR_PRMS)) {
smsc_write_1(sc, RCR, reg_val & ~RCR_PRMS);
} else {
ret = -EALREADY;
}
SMSC_UNLOCK(sc);
break;
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC91X_PRIV_H_
#define ZEPHYR_DRIVERS_ETHERNET_ETH_SMSC91X_PRIV_H_
#include <zephyr/sys/util.h>
/* All Banks, Offset 0xe: Bank Select Register */
#define BSR ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> obtain the register NP value
* to get how many packets are in the Ethernet.
*/
num_packets = sys_read32(REG_MACNP);
for (int i = 0; i < num_packets; i++) {
if (eth_stellaris_rx(dev) != 0) {
break;
}
}
}
if (isr_val & BIT_MACRIS_TXEMP) {
dev_data->tx_err = false;
k_sem_give(&d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* STELLARIS Ethernet Controller
*
* Copyright (c) 2018 Zilogic Systems
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ETH_STELLARIS_PRIV_H_
#define ETH_STELLARIS_PRIV_H_
#define REG_BASE(dev) \
((const struct eth_stellaris_config *const)(dev)->config)->mac_base
/*
* Register mapping
*/
/* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ig_t mac_conf = {0};
hal_status_t hal_status;
HAL_ETH_MAC_GetConfig(heth, &mac_conf);
mac_conf.link_config.duplex_mode = PHY_LINK_IS_FULL_DUPLEX(state->speed)
? HAL_ETH_MAC_FULL_DUPLEX_MODE
: HAL_ETH_MAC_HALF_DUPLEX_MODE;
mac_conf.link_config.speed = PHY_LINK_IS_SPEED_100M(state->speed)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
* Copyright (c) 2020 Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
* Copyright (c) 2021 Carbon Robotics
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/drivers/pinctr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
* Copyright (c) 2025 STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_STM32_HAL_PRIV_H_
#define ZEPHYR_DRIVERS_ETHERNET_ETH_STM32_HAL_PRIV_H_
#include <zephyr/drivers/clock_control.h>
#include <zeph... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
#else
heth->Instance->PTPSSIR = ss_incr_ns;
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
/* Program timestamp addend register */
eth_dev_data->clk_ratio =
((double)CONFIG_ETH_STM32_HAL_PTP_CLOCK_SRC_HZ) / ((double)ptp_clk_rate);
/*
* clk_ratio is the ratio between the desired PTP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>eed) ? ETH_MODE_FULLDUPLEX : ETH_MODE_HALFDUPLEX;
heth->Init.Speed = PHY_LINK_IS_SPEED_100M(state->speed) ? ETH_SPEED_100M : ETH_SPEED_10M;
hal_ret = HAL_ETH_ConfigMAC(heth, NULL);
if (hal_ret != HAL_OK) {
LOG_ERR("HAL_ETH_ConfigMAC: failed: %d", hal_ret);
}
}
int eth_stm32_hal_start(const struct... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
* Copyright (c) 2020 Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
* Copyright (c) 2021 Carbon Robotics
* Copyright (c) 2025 STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
#include <zephyr/sys... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This is not a real ethenet driver. It is used to instantiate struct
* devices for the "vnd,ethernet" devicetree compatible used in test code.
*/
#include "eth.h"
#include "eth_test_priv.h"
#define DT_DRV_COMPA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|><zephyr/net/ethernet.h>
struct vnd_ethernet_config {
struct net_eth_mac_config mcfg;
};
struct vnd_ethernet_data {
uint8_t mac_addr[NET_ETH_ADDR_LEN];
int mac_addr_load_result;
};
#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_TEST_PRIV_H_ */
<|fim_prefix|>/*<|fim_middle|>
* Copyright (c) 2025 Basalte bv
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/net/ethernet.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/virtio.h>
#include <zephyr/drivers/virtio/virtqueue.h>
#include <zephyr/sys/util.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* W5500 Stand-alone Ethernet Controller with SPI
*
* Copyright (c) 2020 Linumiz
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wiznet_w5500
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eth_w5500, CONFIG_ETHERNET_LOG_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_RD (W5500_S0_REGS + W5500_Sn_TX_RD)
#define W5500_S0_TX_WR (W5500_S0_REGS + W5500_Sn_TX_WR)
#define W5500_S0_RX_RSR (W5500_S0_REGS + W5500_Sn_RX_RSR)
#define W5500_S0_RX_RD (W5500_S0_REGS + W5500_Sn_RX_RD)
#define W5500_S0_IMR (W5500_S0_REGS + W5500_Sn_IMR)
#define W5500_S0_MR_MF 7 /* MAC Filter f... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
rx_buf_len = sys_get_be16(tmp);
if (rx_buf_len == 0) {
return;
}
w6100_spi_read(dev, W6100_S0_RX_RD, tmp, 2);
off = sys_get_be16(tmp);
w6100_readbuf(dev, off, header, 2);
rx_len = sys_get_be16(header) - 2;
pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, rx_len,
NET_AF_UNSPEC, 0, K_MSEC(CON... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ine S0_MR_MF 0x40 /* MAC Filter for W6100 */
#define W6100_S0_CR (W6100_S0_REGS + W6100_Sn_CR)
#define S0_CR_OPEN 0x01 /* OPEN command */
#define S0_CR_CLOSE 0x10 /* CLOSE command */
#define S0_CR_SEND 0x20 /* SEND command */
#define S0_CR_RECV 0x40 /* RECV command */
#define W6100_S0_IR (W6... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>"Unable to configure GPIO pin %u", config->reset.pin);
return err;
}
gpio_pin_set_dt(&config->reset, 1);
k_msleep(10);
gpio_pin_set_dt(&config->reset, 0);
k_msleep(150);
}
err = w6300_soft_reset(dev);
if (err != 0) {
LOG_ERR("Reset failed");
return err;
}
if (w6300_spi_read(dev, W... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>define W6300_Sn_RX_RSR 0x0224
#define W6300_Sn_RX_RD 0x0228
#define W6300_Sn_RX_WR 0x022C
/* Socket mode values. */
#define W6300_Sn_MR_MF BIT(7)
#define W6300_Sn_MR_MACRAW 0x07
/* Socket command values. */
#define W6300_Sn_CR_OPEN 0x01
#define W6300_Sn_CR_CLOSE 0x10
#define W6300_Sn_CR_SEND 0x20
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>eDef *eth = dev_config->regs;
switch (type) {
case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
memcpy(data->mac_addr, config->mac_address.addr, 6);
set_mac_addr(eth, data->mac_addr, data->iface);
return 0;
#if defined(CONFIG_NET_PROMISCUOUS_MODE)
case ETHERNET_CONFIG_TYPE_PROMISC_MODE:
if (config->promi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Xilinx AXI Ethernet Lite driver
*
* Copyright(c) 2025, CISPA Helmholtz Center for Information Security
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eth_axi_eth_lite, CONFIG_ETHERNET_LOG_LEVEL);
#include <zephyr/kernel.h>
#include <zephyr/net/ethe... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
irq_enable(DT_INST_IRQN(inst))
#define XILINX_AXIENET_INIT(inst) \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Xilinx Processor System Gigabit Ethernet controller (GEM) driver
*
* Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG
* SPDX-License-Identifier: Apache-2.0
*
* Known current limitations / TODOs:
* - Only supports 32-bit addresses in buffer descriptors, therefore
* the ZynqMP APU (Cor... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Xilinx Processor System Gigabit Ethernet controller (GEM) driver
*
* Driver private data declarations
*
* Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ZEPHYR_DRIVERS_ETHERNET_ETH_XLNX_GEM_PRIV_H_
#define _ZEPHYR_DRIVERS_ETHERNET_ETH... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* XMC4XXX Ethernet controller
*
* Copyright (c) 2023 SLB
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_ethernet
#include "eth.h"
#include <stdint.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/ptp_cl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eth_intel_igc, CONFIG_ETHERNET_LOG_LEVEL);
#include <errno.h>
#include <soc.h>
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
#include <zephyr/device... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_OFFSET * (n)))
/* Transmit Descriptor Ring Length */
#define INTEL_TDLEN_BASE_ADDR 0x0E008
#define INTEL_TDLEN_OFFSET 0x40
#define INTEL_IGC_TDLEN(n) (INTEL_TDLEN_BASE_ADDR + (INTEL_TDLEN_OFFSET * (n)))
/* Transmit Descriptor Head */
#define INTEL_TDH_BASE_ADDR 0x0E010
#define INTEL_TDH_OFFSET ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>INST_INIT(n, pcie), \
}; \
DEVICE_DT_INST_DEFINE(n, intel_eth_plat_init, NULL, &plat_data_##n, &plat_cfg_##n, \
POST_KERNEL, CONFIG_PCIE_INIT_PRIORI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> */
<|fim_prefix|>/*
* Ethernet Platform Utilities for Intel Devices
*
* This module provides utility functions to interact with the PCIe features
* of Intel Ethernet devices, facilitating the retrieval of device-specific
* PCIe configuration details such as BDF (Bus/Device/Function) and device ID.
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 PHOENIX CONTACT Electronics GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_adin2111, CONFIG_MDIO_LOG_LEVEL);
#define DT_DRV_COMPAT adi_adin2111_mdio
#include <stdint.h>
#include <errno.h>
#include <zephyr/device.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT snps_dwcxgmac_mdio
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_clk_indx;
bool suppress_preamble;
#if DWMAC_MDIO_PINCTRL_ENABLED
const struct pinctrl_dev_config *pincfg;
#endif
};
struct dwmac_mdio_data {
struct k_mutex lock;
uint8_t csr_clk_indx;
};
struct dwmac_mdio_clk_div {
uint16_t divisor;
uint8_t csr_clk_indx;
};
/* IEEE 802.3-compliant MDC range (up ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rn;
}
/* Find the matching entry in the iomux array */
while (pin->gpio_num != GPIO_NUM_MAX) {
if (pin->gpio_num == gpio_num) {
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], pin->func);
return;
}
pin++;
}
}
#endif
static int mdio_esp32_initialize(const struct device *dev)
{
const struct m... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> if (rc < 0) {
LOG_ERR("Couldn't configure MDC pin; (%d)", rc);
return rc;
}
rc = gpio_pin_configure_dt(&dev_cfg->mdio_gpio, GPIO_INPUT);
if (rc < 0) {
LOG_ERR("Couldn't configure MDIO pin; (%d)", rc);
return rc;
}
return 0;
}
static DEVICE_API(mdio, mdio_gpio_driver_api) = {
.read = mdio... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_igc_mdio
#include <zephyr/kernel.h>
#include <zephyr/net/mdio.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/pcie/pcie.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGIST... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_lan865x, CONFIG_MDIO_LOG_LEVEL);
#define DT_DRV_COMPAT microchip_lan865x_mdio
#include <stdint.h>
#include <errno.h>
#include <zephyr/device.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Vogl Electronic GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT litex_liteeth_mdio
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/mdio.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023-2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_enet_mdio
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/net/mdio.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/ethernet/eth_nxp_enet.h>
#include <zephyr/drivers/p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>\
POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \
&nxp_enet_qos_mdio_api); \
DT_INST_FOREACH_STATUS_OKAY(NXP_ENET_QOS_MDIO_INIT)
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_enet_qos_mdio
#include <zephyr/net/mdio.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_netc_emdio
#include <zephyr/kernel.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/logging/log.h>
#include "fsl_ne... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_s32_gmac_mdio
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(nxp_s32_mdio, CONFIG_MDIO_LOG_LEVEL);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/mdio.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2022-2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_s32_netc_emdio
#include <zephyr/kernel.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(nxp_s32_emdio, CONFIG_MDIO_LOG_LEVEL);
#include <Net... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/net/ethernet.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/net/ethernet.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 IP-Logix Inc.
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam_mdio
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/drivers/clock_control/atmel_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_SET_CREATE(sub_mdio_cmds,
SHELL_CMD_ARG(scan, &dsub_device_name,
SHELL_HELP("Scan MDIO bus for devices",
"<device> [<reg_addr>]"),
cmd_mdio_scan, 2, 1),
SHELL_CMD_ARG(read, &dsub_device_name,
SHELL_HELP("Read from MDIO device",
"<device> <phy_addr> <reg_addr>"),
cmd_mdio_read, 4, 0)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 BayLibre, SAS
* Copyright (c) 2024 Analog Devices Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm3... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm32_clo<|fim_suffix|>tm32_data *const dev_data = dev->data;
const... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>onfig *const cfg = dev->config;
int ret;
uint32_t v;
prtad &= 0x1f;
regad &= 0x1f;
v = (SY1XX_MDIO_CTRL_OP_READ << SY1XX_MDIO_CTRL_OP_OFFS) |
(prtad << SY1XX_MDIO_CTRL_PHY_ADDR_OFFS) | (regad << SY1XX_MDIO_CTRL_REG_ADDR_OFFS) |
BIT(SY1XX_MDIO_CTRL_INIT_OFFS);
/* start the reading proced... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
DEVICE_DT_INST_DEFINE(inst, &mdio_wch_init, NULL, &mdio_wch_data_##inst, \
&mdio_wch_config_##inst, POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \
&mdio_wch_api);
DT_INST_FOREACH_STATUS_OKAY(MDIO_WCH_DEVICE)
<|fim_prefix|>/*
* Copyright (c) 2025 James Bennio... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Xilinx AXI Ethernet Lite MDIO
*
* Copyright(c) 2025, CISPA Helmholtz Center for Information Security
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mdio_axi_eth_lite, CONFIG_ETHERNET<|fim_suffix|>i_eth_lite_config *config,
mem_addr_t reg)
{... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Xilinx AXI 1G / 2.5G Ethernet Subsystem
*
* Copyright (c) 2024, CISPA Helmholtz Center for Information Security
* SPDX - License - Identifier : Apache-2.0
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eth_xilinx_axienet_mdio, CONFIG_ETHERNET_LOG_LEVEL);
#include <sys/types.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 SLB
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_mdio
#include <errno.h>
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/drivers/mdio.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(nxp_imx_eth);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/mbox.h>
#include <zephyr/drivers/pinctr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> and MII protocol according to PHY mode */
reg_val = MII_PROT_N(RGMII, 0) | MII_PROT_N(RGMII, 1) | MII_PROT_N(XGMII, 2);
sys_write32(reg_val, base + CFG_LINK_MII_PROT);
sys_write32(CFG_LINK_PCS_PROT_10G_SXGMII, base + CFG_LINK_PCS_PROT_2);
return 0;
}
#elif defined(CONFIG_SOC_MIMX94398)
static void i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
struct k_thread rx_thread;
K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_NXP_IMX_RX_THREAD_STACK_SIZE);
uint8_t *rx_frame;
#ifdef CONFIG_ETH_NXP_IMX_NETC_MSI_GIC
unsigned int tx_intid;
unsigned int rx_intid;
#endif
};
int netc_eth_init_common(const struct device *dev);
int netc_eth_tx(const s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NXP_IMX_TX_RING_LEN; \
bdr_config->txBdrConfig[0].dirtyArray = ð##n##_txdirty_array[0][0]; \
bdr_config->txBdrConfig[0].msixEntryIdx = NETC_TX_MSIX_ENTRY_IDX; \
bdr_config->txBdrConfig[0].enIntr = true; \
} ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> net_pkt_read(pkt, oa_tx, len > tc6->cps ? tc6->cps : len);
if (ret < 0) {
return ret;
}
ret = oa_tc6_chunk_spi_transfer(tc6, NULL, oa_tx, hdr, &ftr);
if (ret < 0) {
return ret;
}
len -= tc6->cps;
}
return 0;
}
int oa_tc6_check_status(struct oa_tc6 *tc6)
{
uint32_t sts;
if (!tc6... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 DENX Software Engineering GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef OA_TC6_CFG_H__
#define OA_TC6_CFG_H__
#include <stdint.h>
#include <stdbool.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/net/net_pkt.h>
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>g->phy_addr, phy_id);
return -EINVAL;
}
LOG_INF("PHY %u ID %X", cfg->phy_addr, phy_id);
/* enter software powerdown */
ret = phy_adin2111_sft_pd(dev, true);
if (ret < 0) {
return ret;
}
/* disable interrupts */
ret = phy_adin2111_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC1,
ADIN2111_P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 PHOENIX CONTACT Electronics GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef PHY_ADIN2111_PRIV_H__
#define PHY_ADIN2111_PRIV_H__
#include <zephyr/device.h>
#inclu<|fim_suffix|> /* PHY_ADIN2111_PRIV_H__ */
<|fim_middle|>de <zephyr/net/phy.h>
/**
* @brief Handles PHY i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* DM8806 Stand-alone Ethernet PHY with RMII
*
* Copyright (c) 2024 Robert Slawinski <robert.slawinski1@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT davicom_dm8806_phy
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eth_dm8806_phy, CONFIG_ETHERNET_LOG_LEVEL);
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Robert Slawinski <robert.slawinski1@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/* The absolute PHY address is 10 bit length. Last 5 bits for oldest
* part of address - see Clause 22 of IEEE 802.3.
*/
#define DM8806_REGAD_WIDTH 0x5u
/* Mask for checksum error. Checksum status i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
BUILD_ASSERT((DT_INST_PROP_LEN(n, default_speeds) == 1) && \
(PHY_INST_GENERATE_DEFAULT_SPEEDS(n) != 0), \
"Exactly one valid default speed must be configured"); \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* Inspiration from phy_mii.c, which is:
* Copyright (c) 2021 IP-Logix Inc.
* Copyright 2022 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT maxlinear_gpy111
#include <errno.h>
#include <zephyr/device.h>
#include <zeph... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>et;
}
/* Select correct reference clock mode depending on interface setup */
ret = phy_mc_ksz8081_read(dev, PHY_MC_KSZ8081_CTRL2_REG, (uint32_t *)&ctrl2);
if (ret) {
return ret;
}
if (config->phy_iface == KSZ8081_RMII) {
ctrl2 |= PHY_MC_KSZ8081_CTRL2_REF_CLK_SEL;
} else {
ctrl2 &= ~PHY_MC_K... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_ksz9131
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/mdio.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
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