text stringlengths 14 100k | source stringclasses 1
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<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
* Copyright (c) 2025 STMicroelectronics
*/
#define DT_DRV_COMPAT microchip_lan8742
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(microchip_lan8742, CONFIG_PHY_LOG_LEVEL);
#include <string.h>
#include <zephyr/drivers/gpio.h><|fim_suffix|>_lan8742_dev_dat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.phy_addr = DT_INST_REG_ADDR(n), \
.mdio = DEVICE_DT_GET(DT_INST_PARENT(n)), \
.plca = &mc_t1s_plca_##n##_config, \
}; ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> k_mutex_lock(&data->mutex, K_FOREVER);
/* Stop monitor during reconfiguration */
if (UTIL_OR(UTIL_NOT(DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)),
(!cfg->interrupt_gpio.port))) {
k_work_cancel_delayable(&data->phy_monitor_work);
}
if ((flags & PHY_FLAG_AUTO_NEGOTIATION_DISABLED) != 0U) {
re... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, \
.mdio = DEVICE_DT_GET(DT_INST_BUS(n)), \
RESET_GPIO(n) \
};
#define PHY_MII_DATA(n) \
static struct phy_mii_dev_data phy_mii_dev_data_##n = { \
.dev = DEVICE_DT_INST_GET(n), \
.cb = NULL, \
.sem = Z_SEM_INITIALIZER(phy_mii_dev_data_##n.sem, 1, 1), \
};
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright The Zephyr Project Contributors
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_PHY_MII_H_
#define ZEPHYR_PHY_MII_H_
#include <zephyr/device.h>
#include <zephyr/net/phy.h>
#include <zephyr/net/mii.h>
#define PHY_INST_GENERATE_DEFAULT_SPEEDS(n) \
((DT_INST_ENUM_HAS_VAL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>D) != 0U) {
ret = phy_mii_set_bmcr_reg_autoneg_disabled(dev, adv_speeds);
if (ret >= 0) {
data->autoneg_in_progress = false;
k_work_reschedule(&data->monitor_work, K_NO_WAIT);
}
} else {
ret = phy_mii_cfg_link_autoneg(dev, adv_speeds, true);
if (ret >= 0) {
LOG_DBG("PHY (%d) Starting M... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
\
static struct nxp_t1s_data nxp_t1s_##n##_data; \
\
DEVICE_DT_INST_DEFINE(n, &phy_nxp_t1s_init, NULL, \
&nxp_t1s_##n##_data, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> Disable plca before doing the configuration */
ret = phy_write_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_CTRL0, 0x0);
if (ret) {
return ret;
}
if (!plca_cfg->enable) {
/* As the PLCA is disabled above, just return */
return 0;
}
val = (plca_cfg->node_count << 8) | plca_cfg->node_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_ETHERNET_PHY_OA_TC14_PLCA_H_
#define ZEPHYR_DRIVERS_ETHERNET_PHY_OA_TC14_PLCA_H_
/**
* @brief Write PHY PLCA configuration
*
* This routine provides a gene... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>turn -EIO;
}
/* Energy Efficient Ethernet configuration */
if (cfg->enable_eee) {
ret = qc_ar8031_mmd_read(dev, MDIO_MMD_PCS, MDIO_PCS_EEE_CAP, ®_value);
if (ret) {
return -EIO;
}
ret = qc_ar8031_mmd_write(dev, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
reg_value & (MDIO_AN_EEE_ADV_1000T | MDIO_AN... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2023-2024 NXP
*
* Inspiration from phy_mii.c, which is:
* Copyright (c) 2021 IP-Logix Inc.
* Copyright 2022 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT realtek_rtl8211f
#include <zephyr/kernel.h>
#include <zephyr/net/phy.h>
#include <zephyr/net/mii.h>
#include <zephyr/d... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2024 Bernhard Kraemer
*
* Inspiration from phy_realtek_rtl8211f.c, which is:
* Copyright 2023-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_dp83825
#include <zephyr/kernel.h>
#include <zephyr/net/phy.h>
#include <zephyr/net/mii.h>
#include <zephyr/drivers/mdio.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>te, sizeof(struct phy_link_state));
if (data->cb) {
data->cb(dev, &data->state, data->cb_data);
}
}
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
if (config->interrupt_gpio.port) {
return;
}
#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
k_work_reschedule(&data->phy_monitor_work,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 NXP
* Copyright 2023 CogniPilot Foundation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_tja1103
#include <errno.h>
#include <stdint.h>
#include <stdbool.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/sys/util.h>
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dev = dev;
data->cb = NULL;
data->state.is_up = false;
data->state.speed = LINK_FULL_100BASE;
ret = phy_tja11xx_reg_write(dev, TJA11XX_EXTENDED_CONTROL, 0x1804);
if (ret < 0) {
return ret;
}
ret = phy_tja11xx_reg_write(dev, MII_BMCR, 0x2100);
if (ret < 0) {
return ret;
}
ret = phy_tja11xx... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>(uint16_t emac_instance, uint16_t phy_reg,
uint16_t phy_value, struct eth_cyclonev_priv *p);
int alt_eth_phy_read_register(uint16_t emac_instance, uint16_t phy_reg,
uint16_t *rdval, struct eth_cyclonev_priv *p);
int alt_eth_phy_write_register_extended(uint16_t emac_instance, uint16_t phy_reg,
uint16... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>etval = phy_write(phy, MII_BMCR, MII_BMCR_RESET);
if (retval < 0) {
return retval;
}
/* Wait up to 0.6s for the reset sequence to finish. According to
* IEEE 802.3, Section 2, Subsection 22.2.4.1.1 a PHY reset may take
* up to 0.5 s.
*/
do {
if (retries-- == 0U) {
return -ETIMEDOUT;
}
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Interay Solutions B.V.
* Copyright (c) 2019 Oane Kingma
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_ETHERNET_PHY_GECKO_H_
#define ZEPHYR_DRIVERS_ETHERNET_PHY_GECKO_H_
#include <zephyr/types.h>
#include <soc.h>
#ifdef __cplusplus
extern "C" {
#endif
st... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> bit [3] as indicated
* by the datasheet
*/
phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr,
PHY_MRVL_COPPER_INT_STATUS_REGISTER, (phy_data & 0x8));
return phy_status;
}
/**
* @brief Marvell Alaska PHY link status polling function
* Link status polling function for the Marvel... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PHY_MRVL_1000BASET_CONTROL_REGISTER 9
#define PHY_MRVL_COPPER_CONTROL_1_REGISTER 16
#define PHY_MRVL_COPPER_STATUS_1_REGISTER 17
#define PHY_MRVL_COPPER_INT_ENABLE_REGISTER 18
#define PHY_MRVL_COPPER_INT_STATUS_REGISTER 19
#define PHY_MRVL_COPPER_PAGE_SWITCH_REGISTER 22
#define PHY_MRVL_GENERAL_CONT... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2026 Maximilian Zimmermann
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "qemu_fwcfg.h"
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/kernel/mm.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/sys... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>api != NULL, "fwcfg api must be present");
__ASSERT(api->dma_kick != NULL, "fwcfg dma_kick callback must be present");
return api->dma_kick(dev, descriptor_addr);
}
int fwcfg_init_common(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_FIRMWARE_QEMU_FWCFG_QEMU_FWCFG_H_ */
<|fim_prefix|>/*
* Copyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
DEVICE_DT_DEFINE(node_id, fwcfg_ioport_init, NULL, &fwcfg_data_ioport_##node_id, \
&fwcfg_cfg_ioport_##node_id, POST_KERNEL, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &fwcfg_ioport_api)
DT_FOREACH_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>G_ADDR(node_id), \
}; \
DEVICE_DT_DEFINE(node_id, fwcfg_mmio_init, NULL, &fwcfg_data_mmio_##node_id, \
&fwcfg_cfg_mmio_##node_id, POST_KERNEL, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>T_REG_SIZE(DT_PHANDLE(DT_DRV_INST(n), shared_memory)), \
.shm = DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(n), shared_memory)), \
}; \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Muhammad Waleed Badar
*
* SPDX-License-Identifier: Apache-2.0
*
* Raspberry Pi VideoCore firmware mailbox property interface.
*
* Tag reference:
* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
*/
/**
* @file
* @brief Raspberry Pi VideoCore fi... | fim | zephyrproject-rtos/zephyr | c |
/*
* System Control and Management Interface (SCMI) Base Protocol
*
* Copyright (c) 2026 EPAM Systems
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/firmware/scmi/base.h>
LOG_MODULE_REGISTER(arm_scmi_proto_base);
DT_SCMI_PROTOCOL_D... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/firmware/scmi/clk.h>
#include <string.h>
#include <zephyr/kernel.h>
/* TODO: if extended attributes are supported this should be moved
* to the header file so that users will have access to it.
*/
#define S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>es)
{
struct scmi_protocol_message_attributes_reply reply_buffer;
struct scmi_message msg, reply;
int ret;
if (!proto || !attributes) {
return -EINVAL;
}
msg.hdr = SCMI_MESSAGE_HDR_MAKE(PROTOCOL_MESSAGE_ATTRIBUTES, SCMI_COMMAND,
proto->id, 0x0);
msg.len = sizeof(message_id);
msg.content = &... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>mi_transport_setup_chan(transport, chan, tx);
if (ret < 0) {
LOG_ERR("failed to setup channel");
return ret;
}
/* protocols might share a channel. In such cases, this
* will stop them from being initialized again.
*/
chan->ready = true;
return 0;
}
static int scmi_core_wait_reply(struct sc... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
#include "mailbox.h"
LOG_MODULE_REGISTER(scmi_mbox);
static void scmi_mbox_cb(const struct device *mbox,
mbox_channel_id_t channel_id,
void *user_data,
struct mbox_msg *data)
{
struct scmi_channel *scm... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_
#define _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_
#include <zephyr/drivers/firmware/scmi/transport.h>
#include <zephyr/drivers/firmware/scmi/util.h>
#include <zephyr/drivers/firmware/sc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
int status, ret;
/* input validation */
if (!proto || !cfg) {
return -EINVAL;
}
if (proto->id != SCMI_PROTOCOL_NXP_CPU_DOMAIN) {
return -EINVAL;
}
msg.hdr = SCMI_MESSAGE_HDR_MAKE(CPU_RESET_VECTOR_SET, SCMI_COMMAND,
proto->id, 0x0);
msg.len = sizeof(*cfg);
msg.content = cfg;
reply.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/firmware/scmi/shmem.h>
#include <zephyr/sys/crc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(arm_scmi_shmem_nxp);
#define SMT_CRC_NONE 0U
#define SMT_CRC_XOR 1U /* Unsupported */
#define SMT_CRC_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>f (proto->id != SCMI_PROTOCOL_PINCTRL) {
return -EINVAL;
}
config_num = SCMI_PINCTRL_ATTRIBUTES_CONFIG_NUM(settings->attributes);
if (config_num == 0U && SCMI_PINCTRL_ATTRIBUTES_FID_VALID(settings->attributes) == 0U) {
return -EINVAL;
}
if ((config_num * 2) > ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/firmware/scmi/power.h>
#include <string.h>
#include <zephyr/kernel.h>
DT_SCMI_PROTOCOL_DEFINE_NODEV(DT_INST(0, arm_scmi_power), NULL,
SCMI_POWER_DOMAIN_PROTOCOL_SUPPORTED_VERSION);
enum scmi_power_domain_m... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ate_set(&cfg);
if (ret < 0) {
LOG_ERR("Failed to request power state 0x%x: %d", cfg.system_state, ret);
}
return ret;
}
void sys_arch_reboot(int type)
{
scmi_reboot_handler(type);
}
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* S<|fim_middle|>PDX-License-Identifier: Apache-2.0
*/
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>reset_state)
{
struct scmi_msg_reset_domain_reset_config cfg;
struct scmi_message msg, reply;
int32_t status, ret;
if (proto->id != SCMI_PROTOCOL_RESET_DOMAIN) {
return -EINVAL;
}
cfg.domain_id = id;
cfg.flags = flags;
cfg.reset_state = reset_state;
msg.hdr = SCMI_MESSAGE_HDR_MAKE(RESET, SCM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> &attributes);
if (ret) {
shell_error(sh,
"failed to query parent %d attributes: %d",
info->parent_id, ret);
return ret;
}
memcpy(info->parent_name, attributes.clock_name, SCMI_CLK_NAME_LEN);
return 0;
}
static int get_clk_id(char *str, uint32_t *clk_id)
{
uint32_t attributes;
c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/shell/shell.h>
/* <|fim_suffix|>;
<|fim_middle|>filled in by each of the protocol modules */
SHELL_SUBCMD_SET_CREATE(scmi_cmds, (scmi));
SHELL_CMD_REGISTER(scmi, &scmi_cmds, "ARM SCMI commands", NULL)<|endoftext|> | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>e, mark channel as busy and proceed */
layout->chan_status &= ~SCMI_SHMEM_CHAN_STATUS_BUSY_BIT;
return 0;
}
uint32_t scmi_shmem_channel_status(const struct device *shmem)
{
struct scmi_shmem_layout *layout;
struct scmi_shmem_data *data;
data = shmem->data;
layout = (struct scmi_shmem_layout *)dat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>cols.
* Unlike mailbox transport, SMC doesn't support per-protocol shmem areas
* or function IDs - all protocols use the same SMC call and shared memory.
*/
/*
* Define the SMC transport with a single base channel shared by all protocols.
* This creates:
* 1) One scmi_smc_channel structure contai... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>o->id != SCMI_PROTOCOL_SYSTEM) {
return -EINVAL;
}
msg.hdr = SCMI_MESSAGE_HDR_MAKE(SYSTEM_POWER_STATE_SET, SCMI_COMMAND,
proto->id, 0x0);
msg.len = sizeof(*cfg);
msg.content = cfg;
reply.hdr = msg.hdr;
reply.len = sizeof(status);
reply.content = &status;
ret = scmi_send_message(proto, &m... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>d_params = params->valid_params;
req.nav_id = params->nav_id;
req.index = params->index;
req.rx_fetch_size = params->rx_fetch_size;
req.rxcq_qnum = params->rxcq_qnum;
req.rx_priority = params->rx_priority;
req.rx_qos = params->rx_qos;
req.rx_orderid = params->rx_orderid;
req.rx_sched_priority = pa... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025, Texas Instruments
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Texas Instruments System Control Interface (TISCI) Protocol
*
*/
#ifndef INCLUDE_ZEPHYR_DRIVERS_TISCI_PROTOCOL_H_
#define INCLUDE_ZEPHYR_DRIVERS_TISCI_PROTOCOL_H_
#include "zephyr/kernel.h... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Ambiq Micro Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_flash_controller
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/logging/log.h>
#include <soc.h>
LOG_MODULE_REGISTER(flash_ambiq, CONFIG_FL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)DT_REG_SIZE(SOC_NV_FLASH_NODE);
return 0;
}
static DEVICE_API(flash, flash_ameba_driver_api) = {
.read = flash_ameba_read,
.write = flash_ameba_write,
.erase = flash_ameba_erase,
.get_parameters = flash_ameba_get_parameters,
.get_size = flash_ameba_get_size,
#ifdef CONFIG_FLASH_PAGE_LAYOUT
.page... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Andes Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT andestech_qspi_nor
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/init.h>
#include <string.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Andes Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Flash opcodes */
#define FLASH_ANDES_CMD_WRSR 0x01 /* Write status register */
#define FLASH_ANDES_CMD_RDSR 0x05 /* Read status register */
#define FLASH_ANDES_CMD_READ 0x03 /* Read data */
#d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 The ChromiumOS Authors.
*
* SPDX-License-Identifier: Apache-2.0
*
* This driver is inspired from the flash_andes_qspi.c flash driver.
*
*/
#define DT_DRV_COMPAT andestech_qspi_nor
#include <andes_csr.h>
#include <errno.h>
#include <string.h>
#include <zephyr/kernel.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space)
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT bflb_flash_controller
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/arch/commo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
nand_param->page_count =
(nand_param->npages_per_block * nand_param->nblocks_per_lun * nand_param->nluns);
/* NAND Memory Controller init */
ret = cdns_nand_init(nand_param);
if (ret != 0) {
LOG_ERR("NAND initialization Failed");
return ret;
}
return 0;
}
#define CDNS_NAND_RESET_SPEC_INIT(in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>+block_count);
#elif CONFIG_CDNS_NAND_PIO_MODE
ret = cdns_nand_pio_erase(params, NF_TDEF_TRD_NUM, NF_TDEF_DEV_NUM, start_block_number,
CNF_CMD_ERASE, ++block_count);
#elif CONFIG_CDNS_NAND_GENERIC_MODE
ret = cdns_nand_gen_erase(params, start_block_number, ++block_count);
#endif
if (ret != 0) {
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ANS_CFG1 (0x404)
#define CNF_CTRLCFG_LONG_POLL (0x408)
#define CNF_CTRLCFG_SHORT_POLL (0x40C)
#define CNF_CTRLCFG_DEV_STAT (0x410)
#define CNF_CTRLCFG_DEV_LAYOUT (0x424)
#define CNF_CTRLCFG_ECC_CFG0 (0x428)
#define CNF_CTRLCFG_ECC_CFG1 (0x42C)
#define CNF_CTRLCFG_MULTIPLANE_CFG (0x4... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT cdns_qspi_nor
#include "flash_cadence_qspi_nor_ll.h"
#include <string.h>
#inclu<|fim_suffix|>h, flash_cad_api) = {
.erase = flash_cad_erase,
.write = flash_cad_write,
.read = flash_cad_read... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>uint8_t *buffer, uint32_t len)
{
int status = 0, i;
uint32_t write_count, write_capacity, *write_data, space, write_fill_level, sram_partition;
if (cad_params == NULL) {
LOG_ERR("Wrong parameter\n");
return -EINVAL;
}
status = cad_qspi_indirect_write_start_bank(cad_params, offset, len);
if (s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef CAD_QSPI_NOR_LL_H
#define CAD_QSPI_NOR_LL_H
#include <zephyr/device.h>
#define CAD_QSPI_MICRON_N25Q_SUPPORT CONFIG_CAD_QSPI_MICRON_N25Q_SUPPORT
#define CAD_INVALID -1
#define CAD_QSPI_ER... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_flash_controller
#define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash)
#define FLASH_WRITE_BLK_SZ DT_PROP(SOC_NV_FLASH_NODE, write_block_size)
#define FLA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t device *dev)
{
struct flash_gd32_data *data = dev->data;
k_sem_init(&data->mutex, 1, 1);
return 0;
}
DEVICE_DT_INST_DEFINE(0, flash_gd32_init, NULL,
&flash_data, NULL, POST_KERNEL,
CONFIG_FLASH_INIT_PRIORITY, &flash_gd32_driver_api);
<|fim_prefix|>/*
* Copyright (c) 2022 BrainCo I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ayout,
size_t *layout_size);
#endif
#endif /* ZEPHYR_DRIVERS_FLASH_FLASH_GD32_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 BrainCo Inc.
*
* SPDX-License-Identifier: Apach<|fim_middle|>e-2.0
*/
#ifndef ZEPHYR_DRIVERS_FLASH_FLASH_GD32_H_
#define ZEPHYR_DRIVERS_FLASH_FLASH_GD32_H_
#include <stdi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 BrainCo Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "flash_gd32.h"
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
#include <gd32_fmc.h>
LOG_MODULE_DECLARE(flash_gd32);
#define GD32_NV_FLASH_V1_NODE DT_INST(0, gd_gd32_nv_flash_v1)
#define GD32_NV_FL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> return ret;
}
size -= GD32_NV_FLASH_V2_BANK0_SIZE;
page_addr += GD32_NV_FLASH_V2_BANK0_SIZE;
}
return 0;
}
#endif /* GD32_NV_FLASH_V2_BANK1_SIZE */
bool flash_gd32_valid_range(off_t offset, uint32_t len, bool write)
{
if ((offset > SOC_NV_FLASH_SIZE) ||
((offset + len) > SOC_NV_FLASH_S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>eturn ret;
}
static int gd32_fmc_v3_sector_erase(uint8_t sector)
{
int ret = 0;
gd32_fmc_v3_unlock();
if (FMC_STAT & FMC_STAT_BUSY) {
return -EBUSY;
}
FMC_CTL |= FMC_CTL_SER;
FMC_CTL &= ~FMC_CTL_SN;
FMC_CTL |= CTL_SN(sector);
FMC_CTL |= FMC_CTL_START;
ret = gd32_fmc_v3_wait_idle();
if (... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2018, Piotr Mienkowski
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_gecko_flash_controller
#define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash)
#include <stddef.h>
#include <string.h>
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <em_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>(dev, sfdp_read));
K_OOPS(K_SYSCALL_MEMORY_WRITE(data, len));
return z_impl_flash_sfdp_read(dev, offset, data, len);
}
#include <zephyr/syscalls/flash_sfdp_read_mrsh.c>
static inline int z_vrfy_flash_read_jedec_id(const struct device *dev,
uint8_t *id)
{
K_OOPS(K_SYSCALL_DRIVER_FLASH(dev, re... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_flash_controller
#define SOC_NV_FLASH_NODE DT_PARENT(DT_INST(0, fixed_partitions))
#define P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>gned to write_block_size */
if (((offset % row_len) != 0) || ((remaining_len % row_len) != 0)) {
return -EINVAL;
}
if ((cfg->max_addr - cfg->base_addr) < offset) {
/* offset does not fit within flash memory range */
return -EINVAL;
}
write_offset = cfg->base_addr + offset;
/* check bounds be... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_qspi_flash
#define SOC_NV_FLASH_NODE DT_PARENT(DT_INST(0, fixed_partitions))
#define PAGE_LEN DT_PROP(SO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_qspi_flash
#if defined(CONFIG_DT_HAS_FIXED_PARTITIONS_ENABLED)
#de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ite_it51xxx_manual_flash_1k
#include <soc.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/drivers/flash/it51xxx_flash_api_ex.h>
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
}
static int flash_it8xxx2_init(const struct device *dev)
{
struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
struct flash_it8xxx2_dev_data *data = dev->data;
/* By default, select internal flash for indirect fast read. */
flash_regs->SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLAS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023-2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT adi_max32_flash_controller
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/init.h>
#include "wrap_max32_flc.h"
struct max32_fl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Piotr Mienkowski
* Copyright (c) 2020 Linaro Limited
* Copyright (c) 2022 Georgij Cernysiov
* Copyright (c) 2025 Analog Devices, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT adi_max32_spixf_nor
#include <errno.h>
#include <zephyr/devicetree.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>(reserved for future use).
*
* @return FLASH_MCHP_SUCCESS (0) on success,
* -EINVAL if alignment requirements are not met,
* or other error codes as appropriate.
*/
static int flash_ex_op_user_row_write(const struct device *dev, const uintptr_t in, void *out)
{
ARG_UNUSED(out);
int ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>s_t st;
if ((off < 0) || ((size_t)off + len > cfg->size)) {
return -EINVAL;
}
if (((uintptr_t)off % cfg->erase_block) != 0 || (len % cfg->erase_block) != 0) {
return -EINVAL;
}
key = k_spin_lock(&data->lock);
barrier_dsync_fence_full();
z_barrier_isync_fence_full();
st = FLASH_Erase(&data... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ash_flexspi_hyperflash_init, \
NULL, \
&flash_flexspi_hyperflash_data_##n, \
&flash_flexspi_hyperflash_config_##n, \
POST_KERNEL, \
CONFIG_FLASH_INIT_PRIORITY, \
&flash_flexspi_hyperflash_api);
DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_HYPERF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>B(1), \
.CSIntervalUnit = \
CS_INTERVAL_UNIT( \
DT_INST_PROP(n, cs_interval_unit)), \
.CSInterval = DT_INST_PROP(n, cs_interval), \
.CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
.CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
.dataValidTime = DT_INST_PROP(n, data_valid_time),... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_flexspi_nand
#include <errno.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/l... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_2,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, addr_width);
flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_2PAD, 0x4,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
}
/* Default to 111 mode if no... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_xspi_nor
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/sys_clock.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PI_NOR_SECTOR_SIZE;
}
}
release(flash);
return ret;
}
static const struct flash_parameters *flash_mspi_atxp032_get_parameters(const struct device *flash)
{
const struct flash_mspi_atxp032_config *cfg = flash->config;
return &cfg->flash_param;
}
#if defined(CONFIG_FLASH_PAGE_LAYOUT)
static void... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>eive,
};
/**
* Set up a new MSPI device emulator
*
* @param emul The MSPI device emulator instance itself
* @param bus The MSPI bus emulator instance
* @return 0 If successful
*/
static int emul_mspi_device_init(const struct emul *emul_flash, const struct device *bus)
{
const struct flash_mspi_emu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r_mode = MSPI_DMA;
data->trans.rx_dummy = 8;
data->trans.cmd_length = 1;
data->trans.addr_length = 3;
data->trans.hold_ce = false;
data->trans.priority = MSPI_XFER_PRIORITY_MEDIUM;
data->trans.packets = &data->packet;
data->trans.num_packet... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>d(WITH_SOFT_RESET)
static int soft_reset_66_99(const struct device *dev)
{
const struct flash_mspi_nor_config *dev_config = dev->config;
int rc;
set_up_xfer(dev, MSPI_TX, dev_config->control_xfer_mode);
rc = perform_xfer(dev, SPI_NOR_CMD_RESET_EN);
if (rc < 0) {
LOG_ERR("CMD_RESET_EN failed: %d", ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>efined(WITH_DPD)
uint32_t t_enter_dpd_us;
uint32_t t_exit_dpd_us;
uint32_t t_dpdd_us;
#endif
#if defined(CONFIG_FLASH_PAGE_LAYOUT)
struct flash_pages_layout layout;
#endif
uint8_t jedec_id[SPI_NOR_MAX_ID_LEN];
struct flash_mspi_nor_quirks *quirks;
const struct jesd216_erase_type *default_erase_type... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>spi_nor_cfg.data_rate == MSPI_DATA_RATE_DUAL) {
opi_enable = BIT(1);
} else {
opi_enable = BIT(0);
}
/* Write enable */
rc = cmd_wren(dev);
if (rc < 0) {
return rc;
}
/* Write config register 2 */
set_up_xfer(dev, MSPI_TX, dev_config->control_xfer_mode);
dev_data->xfer.addr_length = 4;
d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifdef CONFIG_FLASH_MSPI_NOR_USE_SFDP
#define BFP_DW16_SOFT_RESET_66_99 BIT(4)
#define BFP_DW16_4B_ADDR_ENTER_B7 BIT(0)
#define BFP_DW16_4B_ADDR_ENTER_06_B7 BIT(1)
#define BFP_DW16_4B_ADDR_PER_CMD BIT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>n), \
.rd_mode = DT_INST_STRING_TOKEN(n, rd_mode), \
.is_logical_low_dev = NPCX_FLASH_IS_LOGICAL_LOW_DEV(n), \
.spi_dev_sz = NPCX_FLASH_SPI_ALLOCATE_SIZE(n), \
}, \
IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, ( \
.layout = { \
.pages_count = DT_INST_PROP(n, size) / \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_fiu_qspi
#include <zephyr/drivers/clock_control.h>
#if defined(CONFIG_FLASH_NPCX_FIU_USE_DMA)
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/dma/dma_npcx_gd... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>utex_is_locked(const struct device *dev);
/**
* @brief Apply qspi configuration
*
* @param dev Pointer to the device structure for qspi bus controller instance.
* @param cfg Pointer to the configuration for the device on qspi bus.
* @param operation Qspi bus operation for the device.
*/
void qspi_n... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/logging/log.h>
#include <Qspi_Ip.h>
#include "flash_nxp_s32_qspi.h"
LOG_MODULE_REGISTER(flash_nxp_s32_qspi, CONFIG_FLASH_LOG_LEVEL);
static ALWAYS_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>32_QSPI_H_ */
<|fim_prefix|>/*
* Copyright 2023-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_FLASH_NXP_S32_QSPI_H_
#define ZEPHYR_DRIVERS_FLASH_NXP_S32_QSPI_H_
#include "jesd216.h"
#define QSPI_ERASE_VALUE 0xff
#define QSPI_IS_ALIGNED(addr, bits) (((addr) & BIT_MASK(b... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_s32_qspi_hyperflash
#include <zephyr/kernel.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/logging/log.h>
#include <Qspi_Ip.h>
#include "memc_nxp_s32_qspi.h"
#include "flash_nxp_s32_qspi.h"
LOG_MOD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>Q_CE), \
}
#define QSPI_RESET_CFG(n) \
{ \
.resetCmdLut = QSPI_LUT_IDX(QSPI_SEQ_RESET), \
.resetCmdCount = 4U, \
}
/*
* SR information used internally by the HAL to access fields BUSY and WEL
* during read/write/erase and polling status operations.
*/
#define QSPI_STATUS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_s32_xspi_hyperram
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(nxp_s32_xspi_hyperram, CONFIG_FLASH_LOG_LEVEL);
#include <zephyr/kernel.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/sys/util.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>page_info, data)) {
return;
}
off += page_info.size;
page++;
}
}
}
<|fim_prefix|>/*
* Copyright (c) 2017 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <zephyr/drivers/flash.h>
static int flash_get_page_info(const struct device *dev,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>f
#endif
<|fim_prefix|>/*
* Copyright (c) 2017 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_FLASH_FLASH_PRIV_H_
#define ZEPHYR_DRIVERS_FLASH_FLASH_PRIV_H_
#if defined(CONFI<|fim_middle|>G_FLASH_PAGE_LAYOUT)
static inline void flash_page_layout_not_imple... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>i = 0; i < (cnt / 4); i++) {
fifo = spic_reg->DR.WORD;
memcpy((void *)(rx_data + rx_num), (void *)&fifo, 4);
rx_num += 4;
}
if (rx_num < len) {
uint32_t remaining = (len - rx_num < cnt % 4) ? len - rx_num : cnt % 4;
for (i = 0; i < remaining; i++) {
*(uint8_t *)(rx_data + rx_num) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lock (%d)", ret);
return ret;
}
ret = clock_control_get_rate(config->clock_dev,
(clock_control_subsys_t)&config->clock_subsys, &clock_freq);
if (ret) {
LOG_ERR("Failed to get clock frequency (%d)", ret);
return ret;
}
if ((config->protocol == XSPI_SPI_MODE && (config->max_frequency /... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_FLASH_RENESAS_RA_OSPI_B_H_
#define ZEPHYR_DRIVERS_FLASH_RENESAS_RA_OSPI_B_H_
#include <zephyr/drivers/flash.h>
#include <zephyr/dt-bindings/flash_controller/xspi.h>
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
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