text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
<|fim_suffix|>rr = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &cmd, ONE_BYTE, false);
if (err == FSP_SUCCESS) {
cmd = SPI_NOR_CMD_RESET_MEM;
err = R_QSPI_DirectWrite(&qspi_data->qspi_ctrl, &cmd, ONE_BYTE, false);
if (err != FSP_SUCCESS) {
LOG_ERR("Direct write for RESET MEM failed");
err = -EIO;
}
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.write_block_size = DT_INST_PROP(n, write_block_size), \
.erase_value = QSPI_ERASE_VALUE, \
}, \
IF_ENABLED(CONFIG_FLASH_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rza2m_qspi_spibsc
#include <stddef.h>
#include <zephyr/cache.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/mem... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>BLE (0U)
#define SPI_COMMAND_ENABLE (1U)
/* Use for setting of the DMCYC [4:0] bit of "data read dummy cycle register"(DRDMCR) */
#define SPI_DUMMY_2CYC (1U)
#define SPI_DUMMY_3CYC (2U)
#define SPI_DUMMY_4CYC (3U)
#define SPI_DUMMY_5CYC (4U)
#define SPI_DUMMY_6CYC (5U)
#define SPI_DUMMY_7CYC (6U)
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2022 Yonatan Schachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <stdint.h>
#include <stddef.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/logging/log.h>
#include <zep... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nfig;
struct s3axx04_data *dev_data = dev->data;
uint8_t write_op[S3AXX04_RW_LEN] = { S3AXX04_WRITE };
int ret;
if (len == 0) {
return 0;
}
if (offset < 0) {
LOG_ERR("Offset is negative");
return -EINVAL;
}
if (offset > config->layout.pages_count || len > (config->layout.pages_count - off... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Aurelien Jarno
* Copyright (c) 2023 Bjarki Arge Andreasen
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This driver defines a page as the erase_block_size.
* This driver defines a write page as defined by the flash controller
* This driver defines a section as a contiguo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>f NVMCTRL_CTRLA_CMD_WP
NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_WP | NVMCTRL_CTRLA_CMDEX_KEY;
#else
NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_CMD_WP | NVMCTRL_CTRLB_CMDEX_KEY;
#endif
err = flash_sam0_check_status(offset);
if (err != 0) {
return err;
}
if (memcmp(data, FLASH_MEM(offset), len) != 0) {
LO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nfig_init_dt(&data->dma, &config_dma);
block_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
block_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
config_dma.head_block = &block_cfg;
config_dma.block_count = 1U;
config_dma.channel_direction = MEMORY_TO_PERIPHERAL;
config_dma.source_data_size = 1U;
confi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017-2023 Nordic Semiconductor ASA
* Copyright (c) 2018 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>tic int flash_si32_read(const struct device *dev, off_t offset, void *data, size_t size)
{
if (!flash_si32_valid_range(offset, size, false)) {
return -EINVAL;
}
if (!size) {
return 0;
}
memcpy(data, (uint8_t *)CONFIG_FLASH_BASE_ADDRESS + offset, size);
return 0;
}
static int flash_si32_write... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
<|fim_suffix|>struct flash_simulator_config flash_simulator_config_##n = { \
.prog_unit_buf = prog_unit_buf_##n, \
.flash_parameters = &flash_parameters_##n, \
.base_offset = FLASH_SIMULATOR_B... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> uint8_t *mock_flash,
unsigned int size, const char *flash_file_path,
bool flash_rm_at_exit)
{
if (flash_in_ram == true) {
if (mock_flash != NULL) {
free(mock_flash);
}
return;
}
if ((mock_flash != MAP_FAILED) && (mock_flash != NULL)) {
munmap(mock_flash, size);
}
if... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
unsigned int erase_value, bool flash_erase_at_start);
void flash_mock_cleanup_native(bool flash_in_ram, int flash_fd, uint8_t *mock_flash,
unsigned int size, const char *flash_file_path,
bool flash_rm_at_exit);
#ifdef __cplusplus
}
#endif
#endif /* DRIVERS_FLASH_FLASH_SIMULAT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Renesas Electronics Cor<|fim_suffix|>C_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk;
qspic_data_write8(0xff);
qspic_data_write8(0xff);
QSPIC->QSPIC_CTRLBUS_REG = QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk;
}
static __ramfunc void qspic_write_enable(void)
{
uint8_t stat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>g wrong key to
* the key register. Option register will remain disabled until reset.
* Writing wrong key causes a bus fault, so we need to set FAULTMASK to
* disable faults, and clear bus fault pending bit before enabling them
* again.
*/
regs->CR |= FLASH_CR_LOCK;
__set_FAULTMASK(1);
regs->... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited
* Copyright (c) 2017 BayLibre, SAS.
* Copyright (c) 2023 Google Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
#define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_
#include <zephyr/drivers/flash.h>
#include "stm32_hsem.h"
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Google Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/types.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash/stm32_flash_api_extensions.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#ifdef CONFIG_USERSPACE
#include <zephyr/syscall.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 STMicroelectronics
* Copyright (c) 2022 Georgij Cernysiov
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_ospi_nor
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/toolchain.h>
#include <zephyr/arch/common/ffs.h>
#include <zephyr/sys/u... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Piotr Mienkowski
* Copyright (c) 2020 Linaro Limited
* Copyright (c) 2022 Georgij Cernysiov
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_qspi_nor
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/toolchain.h>
#include <zephyr/arch/common/ffs.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* **************************************************************************
* xSPI flash controller driver for stm32 series with xSPI periherals
* This driver is based on the stm32Cube HAL XSPI driver
* with... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>mgr;
};
struct flash_stm32_xspi_data {
/* XSPI handle is modifiable ; so part of data struct */
XSPI_HandleTypeDef hxspi;
struct k_sem sem;
struct k_sem sync;
#if defined(CONFIG_FLASH_PAGE_LAYOUT)
struct flash_pages_layout layout;
#endif
struct jesd216_erase_type erase_types[JESD216_NUM_ERASE_TYPES... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>SE_BANK_1;
page = offset / FLASH_PAGE_SIZE;
} else if (offset < FLASH_SIZE) {
bank = bank_swap ? LL_FLASH_ERASE_BANK_1 : LL_FLASH_ERASE_BANK_2;
page = (offset - FLASH_SIZE / 2) / FLASH_PAGE_SIZE;
} else {
LOG_ERR("Offset %d does not exist", offset);
return -EINVAL;
}
LOG_DBG("Erase page %d o... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 BayLibre, SAS
* Copyright (c) 2019 Linaro Limited
* Copyright (c) 2020 Andreas Sandberg
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(flash_stm32generic, CONFIG_FLASH_LOG_LEVEL);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>endif /* FLASH_SECTOR_TOTAL == 12 */
#endif/* !defined(FLASH_SECTOR_TOTAL) */
void flash_stm32_page_layout(const struct device *dev,
const struct flash_pages_layout **layout,
size_t *layout_size)
{
ARG_UNUSED(dev);
*layout = stm32f2_flash_layout;
*layout_size = ARRAY_SIZE(stm32f2_flas... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>L == 5 */
#endif/* !defined(FLASH_SECTOR_TOTAL) */
void flash_stm32_page_layout(const struct device *dev,
const struct flash_pages_layout **layout,
size_t *layout_size)
{
ARG_UNUSED(dev);
*layout = stm32f4_flash_layout;
*layout_size = ARRAY_SIZE(stm32f4_flash_layout);
}
<|fim_prefix|>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Aurelien Jarno
* Copyright (c) 2018 Yong Jin
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <string.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/init.h>
#include <zephyr/sys/barrier.h>
#include <soc.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rc < 0) {
return rc;
}
regs->OPTR = (regs->OPTR & ~mask) | value;
regs->CR |= FLASH_CR_OPTSTRT;
/* Make sure previous write is completed. */
barrier_dsync_fence_full();
rc = flash_stm32_wait_flash_idle(dev);
if (rc < 0) {
return rc;
}
/* Force the option byte loading */
regs->CR |= FLASH... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>art and end pages.
*
* Other STM32 parts (i.e. F4 series) uses bitmask to select sectors.
*
* To implement Write Protection for L4 one should thus add a new EX_OP like
* FLASH_STM32_EX_OP_SECTOR_WP_RANGED in stm32_flash_api_extensions.h
*/
#endif /* CONFIG_FLASH_STM32_WRITE_PROTECT */
#if defined(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> stm32h7_flash_layout[1].pages_count = 1;
stm32h7_flash_layout[1].pages_size =
BANK2_OFFSET - (SECTOR_PER_BANK * FLASH_SECTOR_SIZE);
/* Bank2 */
stm32h7_flash_layout[2].pages_count = SECTOR_PER_BANK;
stm32h7_flash_layout[2].pages_size = FLASH_SECTOR_SIZE;
}
*layout_size = ARRAY_SIZE(... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Linaro Limited
* Copyright (c) 2017 BayLibre, SAS
* Copyright (c) 2019 Centaur Analytics, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_DOMAIN flash_stm32l4
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_DOMAIN flash_stm32l5
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/cach... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>truct device *dev, uint32_t mask, uint32_t value)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
int rc;
if ((regs->OPTR & mask) == value) {
return 0;
}
if (regs->CR & FLASH_CR_OPTLOCK) {
return -EIO;
}
/* Update the target value in the Option Register */
regs->OPTR = (regs->OPTR & ~mask) |... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32wb0_flash_controller
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/flash.h>
#define DT_DRV_COMPAT st_stm32wba_flash_controller
#include <zephyr/logging/log.h>
LOG_MODULE_REGIST... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_DOMAIN flash_stm32wba
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_DOMAIN);
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/cac... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ash_stm32_block_erase_loop(const struct device *dev,
unsigned int offset,
unsigned int len)
{
int i, rc = 0;
#if defined(CONFIG_BT)
/**
* Notify the CPU2 that some flash erase activity may be executed
* On reception of this command, the CPU2 enables the BLE timing
* protection versus... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <limits.h>
#include <stddef.h>
#include <stdint.h>
#include <string.h>
/* FIXME: use k_off_t instead of off_t */
#include <sys/types.h>
#include <zephyr/drivers/flash.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Peter Bigot Consulting, LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/types.h>
#include <zephyr/kernel.h>
#include "jesd216.h"
#include "spi_nor.h"
static bool extract_instr(uint16_t packed,
struct jesd216_instr *res)
{
bool rv = (res != NULL);
if (rv)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>int entry_044: 4;
/* 0-4-4 mode exit method */
unsigned int exit_044: 6;
/* True if 0-4-4 mode is supported */
bool support_044: 1;
/* 4-4-4 mode enable sequences */
unsigned int enable_444: 5;
/* 4-4-4 mode disable sequences */
unsigned int disable_444: 4;
};
/* Get data from BFP DW15.
*
* @pa... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> prevents the issue from occurring.
*/
(void)qspi_rdsr(dev, 1);
#if NRF_QSPI_HAS_XIPEN
nrf_qspi_xip_set(NRF_QSPI, false);
#endif
}
void z_impl_nrf_qspi_nor_xip_enable(const struct device *dev, bool enable)
{
struct qspi_nor_data *dev_data = dev->data;
qspi_acquire(dev);
if (enable) {
if (dev_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Telink Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT telink_b91_flash_controller
#define FLASH_SIZE DT_REG_SIZE(DT_INST(0, soc_nv_flash))
#define FLASH_ORIGIN DT_REG_ADDR(DT_INST(0, soc_nv_flash))
#include "flash.h"
#include <string.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>xx_cc26xx_cache_restore(vims_mode);
k_sem_give(&priv->mutex);
return rc;
}
static int flash_cc13xx_cc26xx_read(const struct device *dev, off_t offs,
void *data, size_t size)
{
ARG_UNUSED(dev);
if (!size) {
return 0;
}
if ((offs < 0) || (size < 1)) {
return -EINVAL;
}
if ((offs + ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Texas Instruments Incorporated
* Copyright (c) 2024 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <string.h>
#include <driverlib/flash.h>
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <string.h>
#include <zephyr/drivers/flash.h>
#include <errno.h>
#include <zephyr/init.h>
#include <soc.h>
#include "flash_priv.h"
#include "fsl_common.h"
#include "fs... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>*
* @param dev Device struct
* @param offset The address's offset
* @param data The buffer to store or read the value
* @param length The size of the buffer
* @return 0 on success,
* -EIO for erroneous area
*/
static int flash_mcux_read(const struct device *dev, off_t offset,
void *data, si... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017-2024 Nordic Semiconductor ASA
* Copyright (c) 2016 Linaro Limited
* Copyright (c) 2016 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> !__SOC_FLASH_NRF_H__ */
<|fim_prefix|>/*
* Copyright (c) 2020 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SOC_FLASH_NRF_H__
#define __SOC_FLASH_NRF_H__
#include <zephyr/kernel.h>
#include <soc.h>
#define FLASH_OP_DONE (0) /* 0 for compliance with the driver API... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/barrier.h>
#include <ironside/se/versions.h>
#if defined(CONFIG_MRAM_LATENCY)
#include "... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ize = nrfx_mramc_memory_size_get();
return 0;
}
static const struct flash_parameters *nrf_mramc_get_parameters(const struct device *dev)
{
ARG_UNUSED(dev);
static const struct flash_parameters parameters = {
.write_block_size = WRITE_BLOCK_SIZE,
.erase_value = ERASE_VALUE,
.caps = {
.no_expl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>f_rram_erase,
#if defined(CONFIG_FLASH_HAS_DRIVER_FILL)
.fill = nrf_rram_fill,
#endif
.get_size = nrf_rram_get_size,
.get_parameters = nrf_rram_get_parameters,
#if defined(CONFIG_FLASH_PAGE_LAYOUT)
.page_layout = nrf_rram_page_layout,
#endif
};
static int nrf_rram_init(const struct device *dev)
{
AR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> */
if ((len % block_size) != 0) {
return -EINVAL;
}
/* Validate offset be multiples of the write block size */
if ((offset % block_size) != 0) {
return -EINVAL;
}
if (k_sem_take(&dev_data->write_lock, K_FOREVER)) {
return -EACCES;
}
key = irq_lock();
while (blocks) {
if (flash_numake... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>n 0;
}
static int32_t flash_numaker_block_write(uint32_t u32_addr, const uint8_t *pu8_data, int block_size)
{
int32_t retval;
const uint32_t *pu32_data = (const uint32_t *)pu8_data;
SYS_UnlockReg();
if (block_size == 4) {
retval = RMC_Write(u32_addr, *pu32_data);
} else if (block_size == 8) {
r... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <string.h>
#include <soc.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>2)
#if defined(CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING)
#define FLASH_FLAG_BLANK BIT(3)
#define FLASH_FLAG_NOT_BLANK BIT(4)
#endif /* CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING */
#endif /* CONFIG_FLASH_RENESAS_RA_HP_BGO */
struct flash_hp_ra_controller {
struct st_flash_hp_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <sys/types.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash/ra_flash_api_extensions.h>
#include <zephyr/kernel.h>
#ifdef CONFIG_USERSPACE
#include <zephyr/syscall.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025-2026 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <string.h>
#include <soc.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_FLASH_SOC_FLASH_RENESAS_RA_LP_H_
#define ZEPHYR_DRIVERS_FLASH_SOC_FLASH_RENESAS_RA_LP_H_
#include <zephyr/drivers/flash.h>
#include <zephyr/sys/atomic.h>
#include <instances/r_fl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/flash.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> device *dev, off_t offset, size_t len)
{
struct flash_rx_data *flash_data = dev->data;
static struct flash_pages_info page_info_off;
flash_err_t err;
uint32_t block_num;
int ret, key = 0, result = 0;
if (!len) {
return 0;
}
if (!flash_rx_valid_range(flash_data->area_size, offset, len)) {
re... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_SOC_FLASH_RENESAS_RX_H_
#define ZEPHYR_DRIVERS_SOC_FLASH_RENESAS_RX_H_
#include <zephyr/drivers/flash.h>
enum flash_region {
CODE_FLASH,
DATA_FLASH,
};
struct flash_rx_config... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
.pages_size = DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
};
static void flash_mcux_pages_layout(const struct device *dev,
const struct flash_pages_layout **layout,
size_t *layout_size)
{
*layout = &dev_layout;
*layout_size = 1;
}
#endif ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Piotr Mienkowski
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_series2_flash_controller
#define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash)
#include <stddef.h>
#include <string.h>
#include <errno.h>... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Silicon Laboratories Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_siwx91x_flash_controller
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/logging/log.h>
#include "sl_si91x_driver.h"
LOG_MODULE_REGISTER(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Schlumberger
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_flash_controller
#define FLASH_WRITE_BLK_SZ DT_PROP(DT_INST(0, infineon_xmc4xxx_nv_flash), write_block_size)
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> struct device *dev)
{
int err;
uint8_t cmd[1] = {DEV_RESUME};
const struct flash_at25xv021a_config *config = dev->config;
const struct spi_buf tx_bufs = {.buf = cmd, .len = ARRAY_SIZE(cmd)};
const struct spi_buf_set tx = {.buffers = &tx_bufs, .count = 1};
/* If in ultra deep sleep mode, we can sen... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>op(dev, CMD_BLOCK_ERASE,
offset);
offset += cfg->block_size;
size -= cfg->block_size;
} else if (is_erase_possible(cfg->page_size,
offset, size)) {
err = perform_erase_op(dev, CMD_PAGE_ERASE,
offset);
offset += cfg->page_size;
size -= cfg->pa... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>,
.len = sizeof(*from_nand),
},
};
const struct spi_buf_set tx_set = {
.buffers = &spi_buf[0],
.count = 1,
};
const struct spi_buf_set rx_set = {
.buffers = &spi_buf[1],
.count = 1,
};
return spi_nand_transceive(dev, &tx_set, from_nand ? &rx_set : NULL);
}
/* Read feature data from a ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ck;
/** Number of blocks per logical unit (LUN) */
uint32_t blocks_per_lun;
/** Number of logical units (LUNs) */
uint8_t num_lun;
/** Number of address cycles (4-7: Column cycles, 0-3 Row cycles) */
uint8_t address_cycles;
/** Number of bits per cell */
uint8_t bits_per_cell;
/** Bad blocks maxi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Savoir-Faire Linux.
* Copyright (c) 2020 Peter Bigot Consulting, LLC
* Copyright (c) 2023 Intercreate, Inc.
*
* This driver is heavily inspired from the spi_flash_w25qxxdv.c SPI NOR driver.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT jedec_spi_nor
#in... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2018 Savoir-Faire Linux.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SPI_NOR_H__
#define __SPI_NOR_H__
#include <zephyr/sys/util.h>
#define SPI_NOR_MAX_ID_LEN 3
/* Status register bits */
#define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */
#define SPI_NOR_WEL_BIT ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __SPI_NOR_S28HX512T_H__
#define __SPI_NOR_S28HX512T_H__
#define S28HX512T_SPI_NOR_CMD_WR_WRARG 0x71 /* Write Any Register */
#define S28HX512T_SPI_NOR_CMD_RSFDPID 0x5A /* Read SFDP ID */
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024, Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT altr_socfpga_agilex_bridge
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/sip_svc/sip_svc.h>
#include <zephyr/drivers/sip_svc/sip_svc_agilex_smc.h>
#include <zephyr/drivers/fp... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024, Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SUBSYS_FPGA_BRIDGE_INTEL_H_
#define ZEPHYR_SUBSYS_FPGA_BRIDGE_INTEL_H_
#include <zephyr/kernel.h>
/* Mask for FPGA-HPS bridges */
#define BRIDGE_MASK 0x0F
/* Mailbox command header index */
#define MBOX_CMD_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/drivers/fpga.h>
#include "fpga_eos_s3.h"
void eos_s3_fpga_enable_clk(void)
{
CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_ON;
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_FPGA_EOS_S3_H_
#define ZEPHYR_DRIVERS_FPGA_EOS_S3_H_
#include <eoss3_dev.h>
struct PIF_struct {
/* Fabric Configuration Control Register, offset: 0x000 */
__IO uint32_t CFG_CTL;
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Meta
* Copyright (c) 2024 SILA Embedded Solutions GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/fpga.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/crc.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> result = work_item->result;
k_mutex_unlock(&data->lock);
return result;
}
<|fim_prefix|>/*
* Copyright (c) 2022 Meta
* Copyright (c) 2024 SILA Embedded Solutions GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include "fpga_ice40_comm... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.config_delay_us = DT_INST_PROP(inst, config_delay_us), \
.creset_delay_us = DT_INST_PROP(inst, creset_delay_us), \
.leading_clocks = DT_INST_PROP(inst, leading_clocks), \
.trailing_clocks = DT_INST_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Meta
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/fpga.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/sp<|fim_suffix|> if (bus.config.cs.cs_is_gpio) {
uint32_t delay_ns = bus.config.cs.delay * 1000;
bus.confi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_mpfs_mailbox
#include <stdio.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/drivers/fpga.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/sys/printk.h>
#include <zephyr/shell/shell.h>
#include <zephyr/version.h>
#include <stdlib.h>
#include <zephyr/drivers/fpga.h>
static int parse_common_args(const struct shell *sh, char **a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>st struct fpga_slg471x5_config *config = dev->config;
if (!i2c_is_ready_dt(&config->bus)) {
LOG_ERR("I2C bus %s not ready", config->bus.bus->name);
return -ENODEV;
}
return 0;
}
#define SLG471X5_INIT(type, inst) \
static struct fp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Sameer Srivastava <l1zard78@proton.me>
*
* SPDX-License-Identifier: Apache-2.0
*
* Driver for Renesas SLG47910 FPGA configured via SPI.
*/
#define DT_DRV_COMPAT renesas_slg47910
#include <errno.h>
#include <stdbool.h>
#include <string.h>
#include <zephyr/device.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021-2022 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT xlnx_fpga
#include <zephyr/device.h>
#include <zephyr/drivers/fpga.h>
#i<|fim_suffix|>itch (IDCODE & IDCODE_MASK) {
case ZU2_IDCODE:
zu_number = 2;
break;
case ZU3_IDCODE:
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021-2022 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_FPGA_ZYNQMP_H
#define ZEPHYR_DRIVERS_FPGA_ZYNQMP_H
#define PCAP_STATUS (*(volatile uint32_t *) (0xFFCA3010))
#define PCAP_RESET (*(volatile uint32_t *) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Analog Devices Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT adi_adp5360_fuel_gauge
#include <zephyr/device.h>
#include <zephyr/drivers/fuel_gauge.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/mfd/adp5360.h>
#include <zephyr/sys/byteorder.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
CONFIG_FUEL_GAUGE_INIT_PRIORITY, &axp2101_api);
DT_INST_FOREACH_STATUS_OKAY(AXP2101_INIT)
<|fim_prefix|>/*
* Copyright (c) 2025, Felix Moessbauer
*
* SPDX-License-Identifier: Apache-2.0
*
* Note: The functions that query the raw values via i2c are named similar
* to the ones ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023, ithinx GmbH
* Copyright (c) 2023, Tonies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_bq27z746
#include "bq27z746.h"
#include <zephyr/kernel.h>
#include <zephyr/drivers/fuel_gauge.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/byteorder... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023, ithinx GmbH
* Copyright (c) 2023, Tonies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_FUELGAUGE_BQ27Z746_GAUGE_H_
#define ZEPHYR_DRIVERS_FUELGAUGE_BQ27Z746_GAUGE_H_
#include <zephyr/drivers/i2c.h>
/* Registers */
enum bq27z746_regs {
BQ27Z746_MAN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
break;
case BQ27Z746_TEMPHICLEARTHRESHOLD:
*val = 1;
break;
case BQ27Z746_TEMPLOSETTHRESHOLD:
*val = 1;
break;
case BQ27Z746_TEMPLOCLEARTHRESHOLD:
*val = 1;
break;
case BQ27Z746_INTERRUPTSTATUS:
*val = 1;
break;
case BQ27Z746_SOCDELTASETTHRESHOLD:
*val = 1;
break;
default:
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, (uint8_t *)&tmp_val,
BQ40Z50_LEN_HALF_WORD);
val->sbs_mfr_access_word = tmp_val;
break;
case FUEL_GAUGE_ABSOLUTE_STATE_OF_CHARGE_PCT:
ret = bq40z50_i2c_read(dev, BQ40Z50_ABSOLUTESTATEOFCHARGE, (uint8_t *)&tmp_val,
BQ40Z50_LEN_BYTE);
val->absolute_state_of_charge_pct = tmp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_FUELGAUGE_BQ40Z50_GAUGE_H_
#define ZEPHYR_DRIVERS_FUELGAUGE_BQ40Z50_GAUGE_H_
#include <zephyr/drivers/i2c.h>
enum bq40z50_regs {
BQ40Z50_MANUFACTURERACCESS = 0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>l_cfg bq40z50_emul_cfg_##n = { \
.i2c_addr = DT_INST_REG_ADDR(n), \
}; \
EMUL_DT_INST_DEFINE(n, emul_bq40z50_init, NULL, &bq40z50_emul_... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024, Embeint Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT zephyr_fuel_gauge_composite
#include <zephyr/device.h>
#include <zephyr/drivers/fuel_gauge.h>
#include <zephyr/drivers/sensor.h>
#include <zephyr/drivers/sensor/battery.h>
#include <zephyr/pm/device_runtime.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/emul_fuel_gauge.h>
/* Emulator syscalls just need to exist as stubs as these <|fim_suffix|>c inline int z_vrfy_emul_fuel_gauge_is_battery_cutoff(const struc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>YSCALL_DRIVER_FUEL_GAUGE(dev, get_buffer_property));
K_OOPS(K_SYSCALL_MEMORY_WRITE(dst, dst_len));
int ret = z_impl_fuel_gauge_get_buffer_prop(dev, prop, dst, dst_len);
return ret;
}
#include <zephyr/syscalls/fuel_gauge_get_buffer_prop_mrsh.c>
static inline int z_vrfy_fuel_gauge_battery_cutoff(con... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>urst_read_dt(&cfg->i2c, cmd, buffer, sizeof(buffer));
if (ret != 0) {
LOG_ERR("Unable to read register, error %d", ret);
return ret;
}
*val = sys_get_le16(buffer);
return 0;
}
static int hy4245_get_prop(const struct device *dev, fuel_gauge_prop_t prop,
union fuel_gauge_prop_val *val)
{
in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ation macro.
*/
#define DEFINE_LC709203F_EMUL(n) \
static struct lc709203f_emul_data lc709203f_emul_data_##n; \
static const struct lc709203f_emul_cfg lc709203f_emul_cfg_##n = { \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.thermistor_b_value = DT_INST_PROP(inst, thermistor_b_value), \
.thermistor_apt = DT_INST_PROP(inst, apt), \
.thermistor_mode = DT_INST_PROP(inst, thermistor_mode), \
}; ... | fim | zephyrproject-rtos/zephyr | c |
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