text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
<|fim_suffix|>;
dev_hw_info.chip_id_1 = mcu_ctrl_device.ui32ChipID1;
if (length > sizeof(dev_hw_info)) {
length = sizeof(dev_hw_info);
}
dev_hw_info.chip_id_0 = BSWAP_32(dev_hw_info.chip_id_0);
dev_hw_info.chip_id_1 = BSWAP_32(dev_hw_info.chip_id_1);
dev_hw_info.factory_trim_version = BSWAP_32(dev_hw_info.fac... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (reason & SMU_WRSR_SW) {
flags |= RESET_SOFTWARE;
}
*cause = flags;
return 0;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
int ret = 0;
uint32_t reason;
if (!device_is_ready(syscon_dev)) {
return -ENODEV;
}
ret = syscon_write_reg(syscon_dev, SMU_WRSR, ANDES_RESET_STATUS_MASK);
if (ret ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/drivers/otp.h>
#include <zephyr/sys/byteorder.h>
/*
* All BFLB SoCs (BL602, BL702, BL702L, BL616) store a factory-pr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Piotr Dymacz
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <string.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/sys/byteorder.h>
#include <driverlib/sys_ctrl.h>
#include <inc/hw_ccfg.h>
#include <inc/hw_fcfg1.h>
#include <inc/hw_memmap.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Baylibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <driverlib/pmctl.h>
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_PIN
| RESET_SOFTWARE
| RESET_B... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Leandro A. F. Pereira
* Copyright (c) 2020 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc/efuse_reg.h>
#include <soc/reset_reasons.h>
#include "esp_system.h"
#include <soc/rtc.h>
#include <zephyr/drivers/hwinfo.h>
#include <str<|fim_suffix|... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>TF) {
flags |= RESET_WATCHDOG;
}
#endif
#if defined(RCU_RSTSCK_FWDGTRSTF)
if (rsts & RCU_RSTSCK_FWDGTRSTF) {
flags |= RESET_WATCHDOG;
}
#endif
#if defined(RCU_RSTSCK_SWRSTF)
if (rsts & RCU_RSTSCK_SWRSTF) {
flags |= RESET_SOFTWARE;
}
#endif
#if defined(RCU_RSTSCK_BORRSTF)
if (rsts & RCU_RSTSCK_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>MU_RSTCAUSE_EM4WURST) || defined(RMU_RSTCAUSE_EM4RST) */
#if HAS_BROWNOUT
| RESET_BROWNOUT
#endif /* HAS_BROWNOUT */
;
return 0;
}
<|fim_prefix|>/*
* Copyright (c) 2021 Sun Amar
* Copyright (c) 2021 Yonatan Schachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <em_system.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/internal/syscall_handler.h>
#incl<|fim_suffix|>hwinfo_get_supported_reset_cause_mrsh.c>
<|fim_middle|>ude <zephyr/drivers/hwinfo.h>
ssize_t z_vrfy_hwinfo_get_device_id(uint8_t *buffer, size_t length... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>->CFG2);
dev_id.id[1] = sys_cpu_to_be32(OCOTP->CFG1);
#endif
if (length > sizeof(dev_id.id)) {
length = sizeof(dev_id.id);
}
memcpy(buffer, dev_id.id, length);
return length;
}
<|fim_prefix|>/*
* Copyright (c) 2019 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/sys/util.h>
#include <string.h>
#include <zephyr/s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> CONFIG_LITEX_CSR_DATA_WIDTH / 8);
for (int i = 0; i < end; i++) {
#if CONFIG_LITEX_CSR_DATA_WIDTH == 8
buffer[i] = litex_read8(addr);
addr += 4;
#elif CONFIG_LITEX_CSR_DATA_WIDTH == 32
buffer[i] = (uint8_t)(litex_read32(addr) >> (addr % 4 * 8));
addr += 1;
#else
#error Unsupported CSR data wid... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/hwinfo.h>
#include <soc.h>
#include <wrap_max32_sys.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
static struct k_spinlock device_id_lock;
static bool initialized;... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>G1_RCAUSE_EXT)) != 0) {
result |= RESET_PIN | RESET_USER;
}
if ((rcause & BIT(RSTC_G1_RCAUSE_WDT)) != 0) {
result |= RESET_WATCHDOG;
}
if ((rcause & BIT(RSTC_G1_RCAUSE_SYST)) != 0) {
result |= RESET_SOFTWARE;
}
if ((rcause & BIT(RSTC_G1_RCAUSE_BACKUP)) != 0) {
result |= RESET_LOW_POWER_WAKE;... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Adib Taraben
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_cmc
#include <stdint.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/logging/log.h>
#include <f<|fim_suffix|>_GetStickySystemResetStatus(base);
*cause = hwinfo_mcux_cmc_xlate_reset_sour... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>pported = hwinfo_mcux_rcm_xlate_reset_sources(UINT32_MAX);
LOG_DBG("supported = 0x%08x", *supported);
return 0;
}
<|fim_prefix|>/*
* Copyright (c) 2021 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/logging/log.h>
#include <f... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/logging/log.h>
#include <fsl_reset.h>
LOG_MODULE_REGISTER(hwinfo_rstctl, CONFIG_HWINFO_LOG_LEVEL);
/* The reset source bits are defined in the rstctl_reset_sour... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <fsl_sim.h>
#include <zephyr/sys/byteorder.h>
#i<|fim_suffix|>dp++ = sys_cpu_to_be32(SIM->UIDML);
#endif /* defined(FSL_FEATURE_SIM_HAS_UIDM) && FSL_FE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Basalte bv
*
* SPDX-License-Identifier: Apache-2.0
*/
<|fim_suffix|>R
#endif
#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW)
| RESET_SOFTWARE
#endif
);
return 0;
}
<|fim_middle|>#define DT_DRV_COMPAT nxp_imx_src
#include <soc.h>
#in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>clear_reset_cause(void)
{
MCUX_SRC_TYPE *base = (MCUX_SRC_TYPE *)DT_INST_REG_ADDR(0);
uint32_t reason = MCUX_SRC_GET_REASON(base);
MCUX_SRC_CLR_REASON(base, reason);
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = (RESET_WATCHDOG
| RESET_DEBUG
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_id.id, length);
return length;
}
<|fim_prefix|>/*
* Copyright (c) 2021 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpc_uid
#include <zephyr/drivers/hwinfo.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
#define UID_WORD_COUNT (DT_INST_REG_SIZE(0) / sizeof(ui... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Linumiz GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h>
#include <ti/driverlib/d<|fim_suffix|>L_FactoryRegion_getUserIDPart();
info.user_var = DL_FactoryRegion_getUserIDVariant();
if (length > sizeof(info)) {
l... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ulting to POR\n",
cause);
native_hwinfo_reset_cause = RESET_POR;
}
}
NATIVE_TASK(native_hwinfo_add_options, PRE_BOOT_1, 10);
NATIVE_TASK(native_hwinfo_gethostid, PRE_BOOT_2, 10);
NATIVE_TASK(native_hwinfo_get_reset_cause, PRE_BOOT_2, 10);
<|fim_prefix|>/*
* Copyright (c) 2025 Henrik Brix Ande... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
* SPDX-License-Identifier: Apache-2.0
*/
#undef _XOPEN_SOURCE
#define _XOPEN_SOURCE 500
#include <unistd.h>
#include "hwinfo_native_bottom.h"
long native_hwinfo_gethostid_bottom(void)
{
return gethostid();
}
<|endoftext|> | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
* SPDX-License-Identifier: Apache-2.0
<|fim_suffix|>_H
#define DRIVERS_HWINFO_NATIVE_BOTTOM_H
long native_hwinfo_gethostid_bottom(void);
#endif /* DRIVERS_HWINFO_NATIVE_BOTTOM_H */
<|fim_middle|> */
#ifndef DRIVERS_HWINFO_NATIVE_BO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018<|fim_suffix|>SET_REASON_HAS_LLOCKUP
if (reason & NRFX_RESET_REASON_LLOCKUP_MASK) {
flags |= RESET_CPU_LOCKUP;
}
#endif
#if NRFX_RESET_REASON_HAS_LDOG
if (reason & NRFX_RESET_REASON_LDOG_MASK) {
flags |= RESET_WATCHDOG;
}
#endif
#if NRFX_RESET_REASON_HAS_LCTRLAP
if (reason... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/sys/byteorder.h>
#include <string.h>
struct numaker_uid {
uint32_t id[3];
};
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>aker_uid dev_id;
bool was_reg_locked = (SYS->REGLCTL == 0);
bool was_rmc_opened = (RMC->ISPCTL & RMC_ISPCTL_ISPEN_Msk);
if (was_reg_locked) {
SYS_UnlockReg();
}
if (!was_rmc_opened) {
RMC_Open();
}
dev_id.id[0] = sys_cpu_to_be32(RMC_ReadUID(0));
dev_id.id[1] = sys_cpu_to_be32(RMC_ReadUID(1))... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_syslib.h>
ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
uint8_t *uid_addr = (uint8_t *) DT_INST_REG_ADDR(0);
if (buffer == NULL) {
return 0;
}
if (length > DT_INST_REG_SIZE(0)) {
length = DT_INST_REG_SIZE(0);
}
memcpy(buffer, uid_addr, length);
return length;
}
<|f... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t();
size_t len = MIN(length, sizeof(unique_id->unique_id_bytes));
memcpy(buffer, &unique_id->unique_id_bytes[0], len);
return len;
}
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0<|fim_middle|>
*/
#include <soc.h>
#include <zephyr/d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nt n = get_sys_info(words, ARRAY_SIZE(words), SYS_INFO_CHIP_INFO);
/* CHIP_INFO returns 4 words */
__ASSERT(n == ARRAY_SIZE(words), "Failed to get chip info");
/* Use DEVICE_ID + WAFER_ID, like BootROM uses for its USB ID */
sys_put_be(id, &words[2], 2 * sizeof(uint32_t));
#else
uint32_t key;
/*
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/hwinfo.h>
#include <fsl_ocotp.h>
#include <fsl_power.h>
/* Because of the ROM clearing the reset register and using scratch register
* which cannot be cleared, we have to "fake" this to meet the hwinfo api.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>sam_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
<|fim_prefix|>/*
* Copyright (c) 2019 Aurelien Jarno
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h<|fim_middle|>>
#include <zephyr/init.h>
#include <soc.h>
#include <string.h>
static... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
<|fim_suffix|>2(*(const uint32_t *)
DT_INST_REG_ADDR_BY_IDX(0, 1));
dev_id.id[2] = sys_cpu_to_be32(*(const uint32_t *)
DT_INST_REG_ADDR_BY_IDX(0, 2));
dev_id.id[3] = sys_cpu_to_be32(*(const uint32_t *)
DT_INST_REG_ADDR_BY_IDX(0, 3));
if (length > sizeof(dev_id.id)) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam4l_uid
#include <zephyr/device.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/init.h>
#include <|fim_suffix|>de <string.h>
ssize_t z_impl_hwinfo_get_d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RSTC_SR_RSTTYP_USER_RST:
*cause = RESET_USER;
break;
default:
break;
}
return 0;
}
int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
{
*supported = RESET_POR
| RESET_LOW_POWER_WAKE
| RESET_WATCHDOG
| RESET_SOFTWARE
| RESET_USER;
return 0;
}
static int hwin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/sys/printk.h>
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/hwinfo.h>
#include <zephyr/types.h>
#include <zephyr/logging/log.h>
static int cmd_get_device_id(const struct shell *sh, size_t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
}
if (rmu & (EMU_RSTCAUSE_WDOG0 | EMU_RSTCAUSE_WDOG1)) {
flags |= RESET_WATCHDOG;
}
if (rmu & EMU_RSTCAUSE_LOCKUP) {
flags |= RESET_CPU_LOCKUP;
}
if (rmu & EMU_RSTCAUSE_SYSREQ) {
flags |= RESET_SOFTWARE;
}
if (rmu & (EMU_RSTCAUSE_DVDDBOD | EMU_RSTCAUSE_DVDDLEBOD | EMU_RSTCAUSE_DECBOD |
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ET_STAT_REG_CMAC_WDOGRESET_STAT_Msk) {
flags |= RESET_WATCHDOG;
}
if (reason & CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk) {
flags |= RESET_DEBUG;
}
}
*cause = flags;
return ret;
}
int z_impl_hwinfo_clear_reset_cause(void)
{
int ret = 0;
CRG_TOP->RESET_STAT_REG = 0;
return ret;
}
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>);
#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
LL_PWR_ClearFlag_MPU();
#elif defined(CONFIG_SOC_SERIES_STM32MP2X) && defined(PWR_FLAG_SB)
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
#elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX)
LL_PWR_ClearFlag_C1STOP_C1STB();
#elif defined(CO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/hwinfo.h>
ssize_t __weak z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
{
return -ENOSYS;
}
int __weak z_impl_hwinfo_get_device_e<|fim_suffix|>rted)
{
return -ENOSYS;
}
<|fim... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/hwspinlock.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/reset.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(hwspinlock_nxp_sema42, CON... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/hwspinlock.h>
#define DT_DRV_COMPAT vnd_hwspinlock
static void vnd_hwspinlock_lock(const struct device *dev, uint32_t id)
{
}
static void vnd_hwspinlock_unloc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>R_ID,
"Tried to lock hwspinlock already locked by this cluster");
sys_write8(HWSPINLOCK_CLUSTER_ID, lock_addr);
while (sys_read8(lock_addr) != HWSPINLOCK_CLUSTER_ID) {
k_busy_wait(CONFIG_SQN_HWSPINLOCK_RELAX_TIME);
sys_write8(HWSPINLOCK_CLUSTER_ID, lock_addr);
}
}
static void sqn_hwspinlock_un... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>->lock);
return gpio_pin_configure_dt(&config->gpio, GPIO_OUTPUT_INACTIVE);
}
#define DEFINE_GPIO_I2C_SWITCH(inst) \
\
static struct gpio_i2c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>:
return I2C_SPEED_HIGH << I2C_SPEED_SHIFT;
case I2C_BITRATE_ULTRA:
return I2C_SPEED_ULTRA << I2C_SPEED_SHIFT;
}
return 0;
}
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_I2C_I2C_PRIV_H_ */
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
#include <zephyr/pm/device_runtime.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_REQ_ACC_INTEN, &acc_mask);
data->tgt = tcfg;
data->enabled = true;
#if IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME)
data->pm_active = pm_got;
#endif
#ifdef CONFIG_I2C_TARGET_BUFFER_MODE
if (data->tgt->callbacks && data->tgt->callbacks->buf_read_requested) {
uint8_t *ptr = NULL;
uint32_t len = 0;
if ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2026 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Driver for Realtek Ameba I2C interface
*/
#define DT_DRV_COMPAT realtek_ameba_i2c
/* Include <soc.h> before <ameba_soc.h> to avoid redefining unlikely() macro */
#include <soc.h>
#include <ameba_soc.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dev));
/* Clear interrupts status. */
sys_write32(0xFFFFFFFF, I2C_STAT(dev));
dev_cfg->dt_init_fn();
i2c_atciic100_default_control(dev);
#if defined(CONFIG_I2C_TARGET)
i2c_atciic100_configure(dev, I2C_SPEED_SET(I2C_SPEED_STANDARD));
#else
i2c_atciic100_configure(dev, I2C_SPEED_SET(I2C_SPEED_STAND... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Andes Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file I2C driver for AndesTech atciic100 IP
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>e */
if (msgs[i].flags & I2C_MSG_ADDR_10_BITS) {
LOG_ERR("10-bits address is not supported");
k_sem_give(&data->mutex);
return -ENOTSUP;
}
/* config stop bit */
send_stop = msgs[i].flags & I2C_MSG_STOP ? 1 : 0;
i2c_master_send_stop(send_stop);
/* transfer data */
if (msgs[i].flags... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>E);
}
static void bcm2711_i2c_segment_len(struct bcm2711_i2c_data *data, uint32_t *segment_len,
bool *last_segment)
{
*segment_len = 0;
*last_segment = true;
for (uint8_t i = data->cur_msg; i < data->num_msgs; i++) {
*segment_len += data->msgs[i].len;
if (i + 1 < data->num_msgs && i2c_is_... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2020 Broadcom
* Copyright 2024 Meta Platforms
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT brcm_iproc_i2c
#include <errno.h>
#include <stdint.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT realtek_bee_i2c
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/bee_clock_control.h>
#include <zephyr/kernel.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>gs[i].flags & I2C_MSG_RESTART) == 0
&& p + msgs[i].len < &(data->transfer_buffer[I2C_MAX_PACKET_LENGTH]); i++) {
if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
memcpy(p, msgs[i].buf, msgs[i].len);
p += msgs[i].len;
}
data->next_transfer_len += msgs[i].len;
}
if (i >= num_msgs) ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Software driven 'bit-banging' library for I2C
*
* This code implements the I2C single master protocol in software by directly
* manipulating the levels of the SCL and SDA lines of an I2C bus. It supports
* the... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Functions for setting and getting the state of the I2C lines.
*
* These need to be implemented by the user of this library.
*/
struct i2c_bitbang_io {
/* Set the state of the SCL line (zero/non-zero value... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ion */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
if (ret < 0) {
return ret;
}
Power_releaseDependency(PowerCC26XX_PERIPH_I2C0);
break;
default:
return -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static int i2c_cc13xx_cc26xx_init(const struct device *dev)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Baylibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc23x0_i2c
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
#include <zephyr/irq.h>
#de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>raw)
{
uint32_t base = DEV_BASE(dev);
uint32_t bitrate_id;
if (!(dev_config_raw & I2C_MODE_CONTROLLER)) {
return -EINVAL;
}
if (dev_config_raw & I2C_ADDR_10_BITS) {
return -EINVAL;
}
switch (I2C_SPEED_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
bitrate_id = 0U;
break;
case I2C_SPEE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rrupt status, indicating the cause of the interrupt
*/
static void cdns_i2c_master_handle_transmit_interrupt(const struct device *dev, uint32_t isr_status)
{
struct cdns_i2c_data *i2c_bus = dev->data;
uint32_t avail_bytes;
uint32_t bytes_to_send;
/* Handle transmission interrupt (data available or t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Logging of I2C messages
*
* Copyright 2020 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <zephyr/drivers/i2c.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c);
#if defined(CONFIG_I2C_CALLBACK) && defined(CO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* dw_i2c.c - I2C file for Design Ware */
/*
* Copyright (c) 2015 Intel Corporation
* Copyright (c) 2022 Andrei-Edward Popa
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/cpu.h>
#ifdef CONFIG_CPU_CORTEX_M
#include <cmsis_core.h>
#endif
#include <stddef.h>
#include <zephyr/types.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nt32_t rx_pending;
uint16_t hcnt;
uint16_t lcnt;
volatile uint8_t state; /* last direction of transfer */
uint32_t request_bytes;
uint8_t xfr_flags;
bool support_hs_mode;
bool read_in_progress;
#ifdef CONFIG_I2C_DW_LPSS_DMA
uintptr_t phy_addr;
uintptr_t base_addr;
/* For dma transfer */
bool ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* i2c_dw_registers.h - array access for I2C Design Ware registers */
/*
* Copyright (c) 2015 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_DW_REGISTERS_H_
#define ZEPHYR_DRIVERS_I2C_I2C_DW_REGISTERS_H_
#ifdef __cplusplus
extern "C" {
#endif
/* IC_CON ... | fim | zephyrproject-rtos/zephyr | c |
/*
* This driver creates fake I2C buses which can contain emulated devices,
* implemented by a separate emulation driver. The API between this driver and
* its emulators is defined by struct i2c_emul_driver_api.
*
* Copyright 2020 Google LLC
* Copyright (c) 2020 Nordic Semiconductor ASA
*
* SPDX-License-Identif... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
}; \
I2C_DEVICE_DT_INST_DEFINE(inst, &i2c_kb1200_init, NULL, &i2c_kb1200_data_##inst, \
&i2c_kb1200_config_##inst, PRE_KERNEL_1, \
CONFIG_KERNEL_INIT... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Intel Corporation
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_i2c
/* Include esp-idf headers first to avoid redefining BIT() macro */
#include <esp_rom_gpio.h>
#include <soc/gpio_sig_map.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>r;
}
/* Fast-mode risetime maximum value: 300ns */
I2C_RT(cfg->reg) = freq * 300U / 1000U + 1U;
/* CLKC = pclk1 / (bitrate * 25) */
clkc = pclk1 / (I2C_BITRATE_FAST * 25U);
if (clkc == 0U) {
clkc = 1U;
}
/* Default DCTY to 1 */
I2C_CKCFG(cfg->reg) |= I2C_CKCFG_DTCY;
I2C_CKCFG(cfg... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Diego Sueiro
* Copyright (c) 2024 Capgemini
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_gecko_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Vestas Wind Systems A/S
* Copyright (c) 2017 Linaro Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT gpio_i2c
/**
* @file
* @brief Driver for software driven I2C using GPIO lines
*
* This driver implements an I2C interface by driving two GPIO lines u... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>R_I2C));
return z_impl_i2c_target_driver_unregister(dev);
}
#include <zephyr/syscalls/i2c_target_driver_unregister_mrsh.c>
static inline int z_vrfy_i2c_recover_bus(const struct device *dev)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_I2C));
return z_impl_i2c_recover_bus(dev);
}
#include <zephyr/syscalls/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>i2cDirectionReceive;
return result;
}
static void i2c_imx_isr(const struct device *dev)
{
I2C_Type *base = DEV_BASE(dev);
struct i2c_imx_data *data = dev->data;
struct i2c_master_transfer *transfer = &data->transfer;
/* Clear interrupt flag. */
I2C_ClearStatusFlag(base, i2cStatusInterrupt);
/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nfiguration */
*dev_config = config | I2C_MODE_CONTROLLER;
return 0;
}
static int ifx_cat1_i2c_msg_validate(struct i2c_msg *msg, uint8_t num_msgs)
{
for (uint32_t i = 0u; i < num_msgs; i++) {
if ((I2C_MSG_ADDR_10_BITS & msg[i].flags) || (msg[i].buf == NULL)) {
return -EINVAL;
}
}
return 0;
}... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief I2C driver for Infineon CAT1 MCU family.
*/
#define DT_DRV_COMPAT infineon_i2c
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief I2C driver for Infineon XMC MCU family.
*/
#define DT_DRV_COMPAT infineon_xmc4xxx_i2c
#include <zephyr/lo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>repeated interrupts. */
(void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1), GPIO_INT_MODE_DISABLED);
}
#endif
static int i2c_enhance_init(const struct device *dev)
{
struct i2c_enhance_data *data = dev->data;
const struct i2c_enhance_config *config = dev->config;
uint8_t *base = config... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t_enable) && \
(DT_INST_PROP(inst, port_num) > SMB_CHANNEL_C)), \
"Only ports 0~2 support I2C target mode"); \
static const struct i2c_it51xxx_config i2c_it51xxx_cfg_##inst = { ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ite_it8xxx2_i2c
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2019 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT litex_i2c
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_litex, CONFIG_I2C_LOG_LEVEL);
#include "i2c-priv.h"
#include "i2c_bitb... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Vogl Electronic GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT litex_litei2c
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/minmax.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CK:
case LPC11U6X_I2C_MASTER_RX_ADR_NACK:
case LPC11U6X_I2C_MASTER_TX_DAT_NACK:
case LPC11U6X_I2C_MASTER_TX_ARB_LOST:
transfer->status = LPC11U6X_I2C_STATUS_FAIL;
set = LPC11U6X_I2C_CONTROL_STOP;
break;
default:
set = LPC11U6X_I2C_CONTROL_STOP;
break;
}
i2c->con_clr = clear;
i2c->con_se... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020, Seagate Technology LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_
#define ZEPHYR_DRIVERS_I2C_I2C_LPC11U6X_H_
#include <zephyr/drivers/pinctrl.h>
#define PINCTRL_STATE_FAST_PLUS PINCTRL_STATE_PRIV_START
#define LPC11U6X_I2C_CONTROL_AA ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT adi_max32_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
#include <zephyr/irq.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>;
break;
case I2C_SPEED_FAST: /** I2C Fast Speed: 400 kHz */
ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FAST_SPEED);
break;
#if defined(MXC_I2C_FASTPLUS_SPEED)
case I2C_SPEED_FAST_PLUS: /** I2C Fast Plus Speed: 1 MHz */
ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FASTPLUS_SPEED);
break;
#endif
#if... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> -EINVAL;
}
sys_write8(ctrl, cfg->i2c_base_addr + CORE_I2C_CTRL);
return 0;
}
static uint8_t *mss_i2c_set_byte_end(struct mss_i2c_data *data, const struct i2c_msg *msg)
{
uint8_t *byte_curr = msg->buf;
data->byte_end = byte_curr + msg->len;
return byte_curr;
}
static int mss_i2c_transfer(const s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_DATA(dev);
if (data->dma_active) {
const struct i2c_mchp_dev_config *cfg = DEV_CFG(dev);
struct i2c_msg *msg = I2C_CURR_MSG(data);
uint32_t ch =
i2c_is_read_op(msg) ? cfg->dma.rx_dma_channel : cfg->dma.tx_dma_channel;
dma_stop(cfg->dma.dma_dev, ch);
data->dma_active = false;
}
#endif /*CO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ddr;
int ret;
int counter = 0;
if (!config) {
return -EINVAL;
}
if (data->slave_attached) {
return -EBUSY;
}
/* Wait for any outstanding transactions to complete so that
* the bus is free
*/
while (!(MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_NBB)) {
ret = xec_spin_yield(&counter);
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_MICROCHIP_MEC_COMMON_XEC_I2C_REGS_H_
#define ZEPHYR_SOC_MICROCHIP_MEC_COMMON_XEC_I2C_REGS_H_
#include <zephyr/sys/util.h>
#ifdef __cplusplus
extern "C" {
#endif
#define XEC_I2C_SMB0_ID 0
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Intel Corporation
* Copyright (c) 2021 Microchip Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_xec_i2c_v2
#include <soc.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_kinetis_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <fsl_i2c.h>
#include <fsl_clock.h>
#include <zephyr/sys/util.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>n) \
.recover_bus_on_init = DT_INST_PROP(n, recover_bus_on_init),
#define I2C_MCUX_FLEXCOMM_RECOVER_CHECK(n) \
BUILD_ASSERT(!DT_INST_PROP(n, recover_bus_on_init) || \
(DT_INST_NODE_HAS_PROP(n, scl_gpios) && \
DT_INST_NODE_HAS_PROP(n, sda_gpios)), \
"I2C node " DT_NODE_FUL... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2016 Freescale Semiconductor, Inc.
* Copyright 2019-2026, NXP
* Copyright (c) 2022 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpi2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>T_SPEC_INST_GET_OR(n, scl_gpios, {0}),
#define I2C_MCUX_LPI2C_SDA_INIT(n) .sda = GPIO_DT_SPEC_INST_GET_OR(n, sda_gpios, {0}),
#else
#define I2C_MCUX_LPI2C_SCL_INIT(n)
#define I2C_MCUX_LPI2C_SDA_INIT(n)
#endif /* CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY */
#define I2C_MCUX_LPI2C_MODULE_IRQ_CONNECT(n) \
do {... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2018 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT altr_nios2_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/sys/util.h>
#include <altera_common.h>
#include "altera_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>c void i2c_ctrl_isr(const struct device *dev)
{
struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
struct i2c_ctrl_data *const data = dev->data;
uint8_t status = inst->SMBST & NPCX_VALID_SMBST_MASK;
#if defined(CONFIG_I2C_NPCX_DMA_DRIVEN)
uint8_t dma_status = inst->DMA_CTRL;
#endif
#ifdef CONFIG_I2C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ock(const struct device *i2c_dev);
/**
* @brief Configure operation of a npcx i2c controller.
*
* @param i2c_dev Pointer to the device structure for i2c controller instance.
* @param dev_config Bit-packed 32-bit value to the device runtime configuration
* for the I2C controller.
*
* @retval 0 If s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* I2C controller functions for 'DMA' mode */
#include <zephyr/drivers/i2c.h>
#include <soc.h>
#include <zephyr/logging/log.h>
#include "i2c_npcx_controller.h"
LOG_MODULE_REGISTER(i2c_npcx_dma, CONF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_threshold_nack(
dev, msg->len, (msg->flags & I2C_MSG_STOP) != 0);
/* Release bus */
i2c_ctrl_fifo_hold_bus(dev, 0);
return;
}
}
}
}
/* Is the STOP condition issued? */
if (data->msg != NULL && (data->msg->flags & I2C_MSG_STOP) != 0) {
/* Clear rx FIFO threshold and sta... | fim | zephyrproject-rtos/zephyr | c |
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