text stringlengths 14 100k | source stringclasses 1
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<|fim_prefix|>/*
* Copyright (c) 2020 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_i2c_port
/**
* @file
* @brief Nuvoton NPCX smb/i2c port driver
*
* This file contains the driver of SMBus/I2C buses (ports) which provides
* pin-muxing for each ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <nrfx_twi.h>
#include "i2c_nrfx_twi_common.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024, Croxel Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <nrfx_twi.h>
#include "i2c_nrfx_twi_common.h"
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(i2c_nrfx_twi);
int ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>YR_DRIVERS_I2C_I2C_NRFX_TWI_COMMON_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024, Croxel Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWI_COMMON_H_
#define ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWI_COMMON_H_
#include <zephyr/pm/device.h>
#include <nrfx_twi.h>
#ifdef __cplu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2024, Croxel Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c/rtio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/pm/device.h>
#include <zephyr/drivers/pinctrl.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c/i2c_nrfx_twim.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/drive... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>KHZ_FREQ
case I2C_SPEED_FAST_PLUS:
nrf_twim_frequency_set(config->twim->p_twim, NRF_TWIM_FREQ_1000K);
break;
#endif
default:
LOG_ERR("unsupported speed");
return -EINVAL;
}
return 0;
}
int i2c_nrfx_twim_msg_transfer(const struct device *dev, uint8_t flags, uint8_t *buf,
size_t buf_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024, Croxel Inc
* Copyright (c) 2024, Embeint Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWIM_COMMON_H_
#define ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWIM_COMMON_H_
#include <zephyr/device.h>
#include <zephyr/pm/device.h>
#include <nrfx_twim.h>
#if... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2024, Croxel Inc
* Copyright (c) 2024, Embeint Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c/rtio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/logging/log.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_numaker_i2c
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
#include <zephyr/driv... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_GET(dev_config_raw)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(100);
break;
case I2C_SPEED_FAST:
baudrate = KHZ(400);
break;
case I2C_SPEED_FAST_PLUS:
baudrate = MHZ(1);
break;
default:
return -EINVAL;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&cloc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (C) 2024 BeagleBoard.org Foundation
* Copyright (C) 2024 Dhruv Menon <dhruvmenon1104@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_omap_i2c
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rcar_i2c
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/renesas_rc... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Realtek, SIBG-SD7
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_rts5912.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_I2C_I2C_REALTEK_RTS5912_H_
#define ZEPHYR_DRIVERS_I2C_I2C_REALTEK_RTS5912_H_
#include "i2c_dw.h"
#inclu<|fim_suffix|>h"
#endif /* ZEPHYR_DRIVERS_I2C_I2C_REALTEK_RTS5912_H_ */
<... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_ra_iic
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/irq.h>
#include <zephyr/sys/util.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_ra_i2c_sci
#define MDDR_DISABLE 256
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>, irq)] = \
EVENT_SCI_RXI(DT_INST_PROP(index, channel)); \
BSP_ASSIGN_EVENT_TO_CURRENT_CORE(EVENT_SCI_RXI(DT_INST_PROP(index, channel))); \
IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq), ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rx_i2c
#include <zephyr/devicetree.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <errno.h>
#include <r_riic_rx_if.h>
#include <r_riic_rx_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rz_riic
#include <math.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#if defined(CONFIG_I2C_RENESAS_RZ_RIIC)
#include "r_riic_master.h"
#els... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>- GIC_SPI_INT_BASE, \
DT_INST_IRQ_BY_NAME(n, irq_name, priority), isr, DEVICE_DT_INST_GET(n), \
DT_INST_IRQ_BY_NAME(n, irq_name, flags)); \
irq_enable(DT_INST_IRQ_BY_NAME(n, irq_name, irq) - GIC_SPI_INT_BASE);
#define I2C_RZA2M... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c/rtio.h>
#include <zephyr/rtio/rtio.h>
#include <zephyr/sys/mpsc_lockfree.h>
#include <zephyr/sys/__assert.h>
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OP) ? I2C_MSG_STOP : 0) |
((iodev_sqe->sqe.iodev_flags & RTIO_IODEV_I2C_RESTART) ? I2C_MSG_RESTART : 0) |
((iodev_sqe->sqe.iodev_flags & RTIO_IODEV_I2C_10_BITS) ? I2C_MSG_ADDR_10_BITS : 0) |
I2C_MSG_WRITE;
}
static inline void i2c_msg_from_tiny_tx(const struct rtio_iodev_sqe *iodev_sqe, struct i2c_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019, Henrik Brix Andersen <henrik@brixandersen.dk>
*
* Based on the i2c_mcux_lpi2c.c driver, which is:
* Copyright (c) 2016 Freescale Sem<|fim_suffix|>ddressing not supported");
return -ENOTSUP;
}
switch (I2C_SPEED_GET(dev_config)) {
case I2C_SPEED_STANDARD:
baudrate = KHZ(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam0_i2c
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Piotr Mienkowski
* Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam_i2c_twim
/** @file
* @brief I2C bus (TWIM) driver for Atmel SAM4L MCU family.
*
* I2C Master Mode with 7/10 bit... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>d) {
cl_div = ((rate / (speed * 2U)) - 4)
/ (1 << ck_div);
if (cl_div <= 255U) {
div_completed = true;
} else {
ck_div++;
}
}
if (ck_div > CKDIV_MAX) {
LOG_ERR("Failed to configure I2C clock");
return -EIO;
}
/* Set TWI clock duty cycle to 50% */
twi->TWI_CWGR = TWI_CWGR_CL... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2017 Piotr Mienkowski
* Copyright (c) 2023 Gerson Fernando Budke
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam_i2c_twihs
/** @file
* @brief I2C bus (TWIHS) driver for Atmel SAM MCU family.
*
* Only I2C Master Mode with 7 bit addressing is currently supported.
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>STOP must both be set */
twihs_cr_stop = (len == 1U) ? TWIHS_CR_STOP : 0;
/* Start the transfer by sending START condition */
twihs->TWIHS_CR = TWIHS_CR_START | twihs_cr_stop;
/* Enable Receive Ready and Transmission Completed interrupts */
twihs->TWIHS_IER = TWIHS_IER_RXRDY | TWIHS_IER_TXCOMP | TW... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Ltd.
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT arm_versatile_i2c
/**
* @file
* @brief Driver for ARM's SBCon 2-wire serial bus interface
*
* SBCon is a simple de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c), 2023 Basalte bv
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_sc18im704_i2c
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>C_CLK_L 0x07
#define SC18IM704_REG_I2C_CLK_H 0x08
#define SC18IM704_REG_I2C_TIMEOUT 0x09
#define SC18IM704_REG_I2C_STAT 0x0a
#define SC18IM704_I2C_STAT_OK 0xf0
#define SC18IM704_I2C_STAT_NACK_ADDR 0xf1
#define SC18IM704_I2C_STAT_NACK_DATA 0xf2
#define SC18IM704_I2C_STAT_TIMEOUT 0xf8
/**
* @... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT intel_sedi_i2c
#include <stdint.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <sedi_driver_i2c.h>
#include <zephyr/pm/device.h>
#include <zephyr/logging/log.h>
LOG_MODU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025, Qingsong Gou <gouqs@hotmail.com>
* Copyright (c) 2025, Haoran Jiang <halfsweet@halfsweet.cn>
* Copyright (c) 2025, SiFli Technologies(Nanjing) Co., Ltd
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sifli_sf32lb_i2c
#include "i2c-priv.h"
#include <zephyr/ar... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>int num_bytes;
int ret;
if (argc > 3) {
num_bytes = strtol(argv[3], NULL, 16);
if (num_bytes > MAX_I2C_BYTES) {
num_bytes = MAX_I2C_BYTES;
}
} else {
num_bytes = MAX_I2C_BYTES;
}
ret = i2c_read_to_buffer(sh, argv[ARGV_DEV], argv[ARGV_ADDR], NULL, buf, num_bytes);
if (ret == 0) {
shell... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 SiFive Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT sifive_i2c0
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(i2c_sifive);
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <soc.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.concat_buf_size = DT_INST_PROP(idx, zephyr_concat_buf_size), \
}; \
\
static struct i2c_s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_smartbond_i2c
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/pinctrl.h>
#include <DA1469xAB.h>
#include <da1469x_pd.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 BayLibre, SAS
* Copyright (c) 2017 Linaro Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/dma/dma_stm32.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> DT_INST_IRQ_BY_NAME(index, event, priority), \
i2c_stm32_event_isr, \
DEVICE_DT_INST_GET(index), 0); \
irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
\
IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
DT_INST_IRQ_BY_NAME(index, error, p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 BayLibre, SAS
* Copyright (c) 2017 Linaro Ltd
* Copyright (c) 2024 Intel Corporation
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <soc.h>
#include <stm32_ll_i2c.h>
#include <stm32_ll_rcc.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/i2c.h>
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017, I-SENSE group of ICCS
* Copyright (c) 2017 Linaro Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* I2C Driver for: STM32F1, STM32F2, STM32F4 and STM32L1
*
*/
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_control.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <soc.h>
#include <stm32_bitops.h>
#include <stm32_ll_i2c.h>
#include <stm32_ll_rcc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 BayLibre, SAS
* Copyright (c) 2017 Linaro Ltd
*
* SPDX-License-Identifier: Apache-2.0
*
* I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0, STM32L4, STM32WB and
* STM32WL
*
*/
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/drivers/clock_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>c;
uint32_t sclh = i2c_h_min_time / ns_presc;
uint32_t scll = i2c_l_min_time / ns_presc;
uint32_t sdadel = i2c_hold_time_min / ns_presc;
uint32_t scldel = i2c_setup_time_min / ns_presc;
if ((sclh - 1) > 255 || (scll - 1) > 255) {
++presc;
continue;
}
if (sdadel > 15 || (scldel - 1) >... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>gs[0].flags |= I2C_MSG_RESTART;
for (uint8_t n = 0; n < num_msgs; n++) {
/* detect transfer type */
if ((msgs[n].flags & I2C_MSG_READ) == I2C_MSG_READ) {
/* read msg */
ret = sy1xx_i2c_read(dev, &msgs[n], addr);
} else {
/* write msg */
ret = sy1xx_i2c_write(dev, &msgs[n], addr);
}
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#define DT_DRV_COMPAT ti_tca9546a
DT_INST_FOREACH_STATUS_OKAY(TCA9546A_INIT)
/*
* TCA9548A: 8 channels switch
*/
#define TCA9548A_INIT(n) TCA954x_ROOT_DEFINE(9548, n, 8, false)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_tca9548a
DT_INST_FOREACH_STATUS_OKAY(TCA9548A_INIT)
<|fim_prefix|>/*
* Copyrigh... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This is not a real I2C driver. It is used to instantiate struct
* devices for the "vnd,i2c" devicetree compatible used in test code.
*/
#include <zephyr/<|fim_suffix|>T(n) \
I2C_DEVICE_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>LR2_FREQ) | freq_range;
return 0;
}
static int i2c_wch_configure(const struct device *dev, uint32_t dev_config)
{
const struct i2c_wch_config *config = dev->config;
I2C_TypeDef *regs = config->regs;
clock_control_subsys_t clk_sys;
uint32_t clock_rate;
int err;
if (!(dev_config & I2C_MODE_CONTROL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* SPDX-License-Identifier: Apache-2.0 */
/*
* Copyright © 2023 Calian Ltd. All rights reserved.
*
* Driver for the Xilinx AXI IIC Bus Interface.
* This is an FPGA logic core as described by Xilinx document PG090.
*/
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_ADR = 0x11C, /* Target Ten Bit Address */
REG_RX_FIFO_PIRQ = 0x120, /* Receive FIFO Programmable Depth Interrupt */
REG_GPO = 0x124, /* General Purpose Output */
REG_TSUSTA = 0x128, /* Timing Parameter */
REG_TSUSTO = 0x12C, /* Timing Parameter */
REG_THDSTA = 0x130, /* Timing Parameter */... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ANDLE_CACHE
if (!buf_in_nocache((uintptr_t)i2s_data_buf, data->block_size)) {
/* I2S DMA is 32-bit datawidth for each sample, so we need to invalidate 2x
* block_size when we are getting 16 bits sample.
*/
sys_cache_data_invd_range(i2s_data_buf, data->block_size);
}
#endif /* CONFIG_I2S_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>truct device *)dev, mem_block, size);
if (ret != 0) {
k_mem_slab_free(tx_cfg->mem_slab, mem_block);
}
return ret;
}
<|fim_prefix|>/*
* Copyright (c) 2018 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <string.h>
#include <zephyr/drivers/i2s.h>
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_i2s
#include <zephyr/drivers/i2s.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/dma/dma_esp32.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_OOPS(ret);
}
ret = i2s_write((const struct device *)dev, mem_block, size);
if (ret != 0) {
k_mem_slab_free(tx_cfg->mem_slab, mem_block);
}
return ret;
}
#include <zephyr/syscalls/i2s_buf_write_mrsh.c>
static inline int z_vrfy_i2s_trigger(const struct device *dev,
enum i2s_dir dir,
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>VICE_SLAVE, \
.wordSize = CY_TDM_SIZE_16, \
.signExtend = CY_ZERO_EXTEND, \
.format = CY_TDM_LEFT_DELAYED, /* fixed for i2s mode */ ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>);
i2s_copy_to_fifo((uint8_t *)mem_block, mem_block_size,
stream->cfg.word_size, stream->cfg.channels);
i2s_clear_pending_irq(cfg->base);
k_mem_slab_free(stream->cfg.mem_slab, mem_block);
}
static DEVICE_API(i2s, i2s_litex_driver_api) = {
.configure = i2s_litex_configure,
.read = i2s_litex_read... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _I2S_LITEI2S__H
#define _I2S_LITEI2S__H
#include <zephyr/device.h<|fim_suffix|>#include <zephyr/drivers/i2s.h>
#include <zephyr/devicetree.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/ringq.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>g.timeout));
if (err < 0) {
LOG_ERR("TX queue full");
return err;
}
return 0;
}
static DEVICE_API(i2s, i2s_max32_driver_api) = {
.read = i2s_max32_read,
.write = i2s_max32_write,
.configure = i2s_max32_configure,
.trigger = i2s_max32_trigger,
};
static int i2s_max32_init(const struct device ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpc_i2s
#include <string.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/i2s.h>
#include <zephyr/drivers/clock_control.h>
#include <fsl_i2s.h>
#include <fsl_dma.h>
#include <zephyr/logging/... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2021,2023-2025 NXP
* All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief I2S bus (SAI) driver for NXP i.MX RT series.
*/
#define DT_DRV_COMPAT nxp_mcux_i2s
#include <errno.h>
#include <string.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/kernel.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>tream->next_deadline_us = nsi_hws_get_time();
stream->last_error = 0;
}
return 0;
}
stream->fd = fd;
stream->missing_file = false;
stream->next_deadline_us = nsi_hws_get_time();
stream->last_error = 0;
return 0;
}
static int ns_i2s_copy_to_rx(struct ns_i2s_data *data, const struct ns_i2s_b... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>athname, O_WRONLY | O_CREAT | O_TRUNC, 0600);
}
if (fd < 0) {
nsi_print_warning("%s could not be opened (%s)\n", pathname, strerror(errno));
return -nsi_errno_to_mid(errno);
}
return fd;
}
<|fim_prefix|>/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* C<|fim_suffix|>/
<|fim_middle|>opyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_I2S_I2S_NATIVE_SIM_BOTTOM_H_
#define ZEPHYR_DRIVERS_I2S_I2S_NATIVE_SIM_BOTTOM_H_
#ifdef __cplusplus
extern "C" {
#endif
int ns_i2s_open_file_bottom(const char *pathname, int rx);
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t.buffer_size = 1;
} else {
/* Next TX buffer cannot be supplied now.
* Defer it to when the user writes more data.
*/
drv_data->next_tx_buffer_needed = true;
return;
}
}
(void)supply_next_buffers(drv_data, &next);
}
}
static void clock_manager_init(const struct device *d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_i2s
#include <stdlib.h>
#include <zephyr/drivers/i2s.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#inclu... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_ra_i2s_ssie
#include <stdlib.h>
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/i2s.h>
#include <zephyr/driv... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 comsuisse AG
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam_ssc
/** @file
* @brief I2S bus (SSC) driver for Atmel SAM MCU family.
*
* Limitations:
* - TX and RX path share a common bit clock divider and as a result they cannot
* be configure... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CHANNEL_CONFIG[1 - cfg->channel_group].I2S_TER_b.TXCHEN = 0;
}
static void i2s_siwx91x_start_rx(const struct device *dev)
{
const struct i2s_siwx91x_config *cfg = dev->config;
cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_RER_b.RXCHEN = 1;
cfg->reg->CHANNEL_CONFIG[cfg->channel_group].I2S_IMR &= ~F... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_i2s
#include <string.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/i2s.h>
#include <zephyr/drivers/dma/dma_stm32.h>
#include <soc.h>
#include <stm32_ll_rcc.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_I2S_I2S_STM32_H_
#define ZEPHYR_DRIVERS_I2S_I2S_STM32_H_
#ifdef CONFIG_STM32_HAL2
#define STM32_I2S_DATA_FORMAT_16_BIT LL_I2S_DATA_FORMAT_16_BIT
#define STM32_I2S_DATA_FORMAT_24_BIT LL_I2S_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_data->hsai;
struct queue_item item;
int ret;
if (dir == I2S_DIR_TX) {
ret = k_msgq_get(&stream->queue, &item, K_NO_WAIT);
if (ret < 0) {
return -ENOMEM;
}
stream->mem_block = item.buffer;
stream->mem_block_len = item.size;
sys_cache_data_flush_range(stream->mem_block, stream->mem_blo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
<|fim_suffix|>clude <zephyr/drivers/i2s.h>
static int vnd_i2s_configure(const struct device *dev, enum i2s_dir dir,
const struct i2s_config *i2s_cfg)
{
return -ENOTSUP;
}
static const struct i2s_config *vnd_i2s_config_get(const struct device *dev, enum i2s_dir dir)
{
return NULL;
}
static... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_len = sizeof(uint8_t) +
sizeof(struct i3c_ccc_deftgts_active_controller) +
(deftgts->count * sizeof(struct i3c_ccc_deftgts_target));
return i3c_do_ccc(controller, &ccc_payload);
}
int i3c_ccc_do_getstatus(const struct i3c_device_desc *target,
union i3c_ccc_getstatus *status,
enum... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OT_STATUS_MASK;
return status;
}
int i3c_addr_slots_init(const struct device *dev)
{
struct i3c_driver_data *data = (struct i3c_driver_data *)dev->data;
const struct i3c_driver_config *config = (const struct i3c_driver_config *)dev->config;
int i, ret = 0;
struct i3c_device_desc *i3c_dev;
struct i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>VAL;
}
return ret;
}
/**
* @brief Configure I3C hardware.
*
* @param dev Pointer to controller device driver instance.
* @param type Type of configuration parameters being passed
* in @p config.
* @param config Pointer to the configuration parameters.
*
* @retval 0 If successful.
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i3c.h>
#include <string.h>
#include <zephyr/internal/syscall_handler.h>
static inline int z_vrfy_i3c_do_ccc(const struct device *dev,
struct i3c_ccc_payload *payload)
{
K_OOPS(K_SYS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (offset < (i3c_i2c_device_desc_pool.info.block_size *
i3c_i2c_device_desc_pool.info.num_blocks)) &&
((offset % i3c_i2c_device_desc_pool.info.block_size) == 0);
}
<|fim_prefix|>/*
* Copyright (c) 2024 Meta Platforms
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Wind River Systems, Inc.
* Copyright (c) 2016,2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/drivers/i3c.h>
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(i3c, CONFIG_I3C_LOG_LEVEL);
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
DEVICE_DT_INST_DEFINE(id, max32_i3c_init, NULL, &max32_i3c_data_##id, \
&max32_i3c_config_##id, POST_KERNEL, \
CONFIG_I3C_CONTROLLER_INIT_PRIORITY, &max32_i3c_driver_api); \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>to controller device driver instance.
*/
static void mcux_i3c_fifo_rx_drain(const struct device *dev)
{
const struct mcux_i3c_config *config = dev->config;
I3C_Type *base = config->base;
uint8_t buf;
/* Read from FIFO as long as RXPEND is set. */
while (mcux_i3c_status_is_set(base, I3C_MSTATUS_RXPE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Meta Platforms
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdlib.h>
#include <zephyr/drivers/i3c.h>
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(i3c, CONFIG_I3C_LOG_LEVEL);
/* Generate Names */
#define UNKNOWN_NAME_STR(i, _) ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*132*/
#define DT_DRV_COMPAT nuvoton_npcx_i3c
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/drivers/clock_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/i3c.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/logging/log.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation
* Copyright (c) 2024 Meta Platforms
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#include <zephyr/drivers/i3c.h>
#include <zephyr/drivers/i3c/rtio.h>
#include <zephyr/rtio/rtio.h>
#include <zephyr/sys/mpsc_lockfree.h>
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Google LLC
* Copyright (c) 2024 Meta Platforms
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i3c.h>
#include <zephyr/drivers/i3c/rtio.h>
#include <zephyr/rtio/rtio.h>
#include <zephyr/rtio/work.h>
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(i3c_r... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Meta Platforms
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/i3c.h>
#include <zephyr/shell/shell.h>
#include <inttypes.h>
#include <stdlib.h>
#include <string.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 EXALT Technologies.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/i3c.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This is not a real I3C driver. It is used to instantiate struct
* devices for the "vnd,i3c" devicetree compatible used in test code.
*/
#define DT_DRV_COMPAT vnd_i3c
#include <zephyr/drivers/i3c.h>
#include <zephyr/devi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ESS);
sys_write8(START_TRANSFER, cfg->base + I3CM01_STATUS);
irq_enable(cfg->irq_num);
return it51xxx_wait_to_complete(dev);
}
static int it51xxx_i3cm_do_ccc(const struct device *dev, struct i3c_ccc_payload *payload)
{
const struct it51xxx_i3cm_config *cfg = dev->config;
struct it51xxx_i3cm_data *d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 ITE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ite_it51xxx_i3cs
#include <zephyr/logging/log.h>
#include <zephyr/logging/log_instance.h>
LOG_MODULE_REGISTER(i3cs_it51xxx);
#include <zephyr/drivers/i3c.h>
#include <zephyr/drivers/pinctrl.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dev)
{
struct b91_data *b91 = dev->data;
#if defined(CONFIG_IEEE802154_B91_RANDOM_MAC)
sys_rand_get(b91->mac_addr, sizeof(b91->mac_addr));
/*
* Clear bit 0 to ensure it isn't a multicast address and set
* bit 1 to indicate address is locally administered and may
* not be globally unique.
*/
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021 Telink Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_B91_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_B91_H_
/* Timeouts */
#define B91_TX_WAIT_TIME_MS (10)
#define B91_ACK_WAIT_TIME_MS (10)
/* Recei... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* ieee802154_cc1200.c - TI CC1200 driver */
#define DT_DRV_COMPAT ti_cc1200
/*
* Copyright (c) 2017 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_MODULE_NAME ieee802154_cc1200
#define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EFINE_STROBE_INSTRUCTION(safc, CC1200_INS_SAFC)
DEFINE_STROBE_INSTRUCTION(swor, CC1200_INS_SWOR)
DEFINE_STROBE_INSTRUCTION(spwd, CC1200_INS_SPWD)
DEFINE_STROBE_INSTRUCTION(sfrx, CC1200_INS_SFRX)
DEFINE_STROBE_INSTRUCTION(sftx, CC1200_INS_SFTX)
DEFINE_STROBE_INSTRUCTION(sworrst, CC1200_INS_SWORRST)
DEFINE_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* ieee802154_cc1200_regs.h - Registers definition for TI CC1200 */
/*
* Copyright (c) 2017 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_REGS_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_REGS_H_
/* Access types (see Sect... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>,
0x00,
0x00,
0x56,
0xCC,
0xCC,
0x02,
0xEE,
0x10,
0x04,
0x50,
0x00,
0x20,
0x40,
0x0E,
0x28,
0x03,
0x00,
0x33,
0xF7,
0x0F,
0x00,
0x00,
0x6E,
0x1C,
0xAC,
0x14,
0x00,
0x00,
0x00,
0xB5,
0x00,
0x02,
0x00,
0x00,
0x10,
0x00,
0x00,
0x05,
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Brett Witherspoon
* Copyright (c) 2020 Friedt Professional Engineering Services, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_ieee802154
#define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_R... | fim | zephyrproject-rtos/zephyr | c |
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