text stringlengths 14 100k | source stringclasses 1
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<|fim_prefix|>/*
* Copyright (c) 2025-2026 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rz_sci_uart
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/interrupt_controller/intc_rz_icu.h>
#include <zephyr/logging/lo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rz_scif_uart
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include "r_scif_uart.h"
LOG_M... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_rza2m_scif_uart
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/interrupt_controlle... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (!pio_can_add_program(pio, RPI_PICO_PIO_GET_PROGRAM(uart_rx))) {
return -EBUSY;
}
offset = pio_add_program(pio, RPI_PICO_PIO_GET_PROGRAM(uart_rx));
sm_config = pio_get_default_sm_config();
pio_sm_set_consecutive_pindirs(pio, sm, rx_pin, 1, false);
sm_config_set_in_pins(&sm_config, rx_pin);
sm_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Ayush Singh, BeagleBoard.org
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/uart.h>
#include <zephyr/ipc/rpmsg_service.h>
#define DT_DRV_COMPAT rpmsg_uart
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(uart_rpmsg, CONFIG_UART_LOG_LEVEL);
#define RX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#define UART_RTT_INIT(idx, config) \
struct uart_rtt_data uart_rtt##idx##_data; \
\
DEVICE_DT_DEFINE(UART_RTT(idx), uart_rtt_init, NULL, \
&uart_rtt##idx##_data, config, \
PRE_KERNEL_2, CONFIG_SERIAL_INIT_PRIORITY, \
&uart_rtt_driver_api... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>n) \
PINCTRL_DT_INST_DEFINE(n); \
\
static struct rv32m1_lpuart_data rv32m1_lpuart_##n##_data; \
\
static const struct rv32m1_lpuart_config rv32m1_lpuart_##n##_cfg;\
\
DEVICE_DT_INST_DEFINE(n, \
rv32m1_lpuart_init, \
NULL, \
&rv32m1_l... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "uart_rzt2m.h"
#include "zephyr/spinlock.h"
#include "zephyr/sys/printk.h"
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/sys/util.h>
#include <zephyr/irq.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
<|fim_suffix|>
#define CCR1_MASK_PE BIT(8)
#define CCR1_MASK_PM BIT(9)
#define CCR1_MASK_NFEN BIT(28)
#define CCR2_MASK_BGDM BIT(4)
#define CCR2_MASK_ABCS BIT(5)
#define CCR2_MASK_ABCSE BIT(6)
#define CCR2_MASK_BRR GENMASK(15, 8)
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>= uart_sam_irq_rx_disable,
.irq_tx_complete = uart_sam_irq_tx_complete,
.irq_rx_ready = uart_sam_irq_rx_ready,
.irq_err_enable = uart_sam_irq_err_enable,
.irq_err_disable = uart_sam_irq_err_disable,
.irq_is_pending = uart_sam_irq_is_pending,
.irq_callback_set = uart_sam_irq_callback_set,
#endif /* C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Google LLC.
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam0_uart
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/init.h>
#include <zephyr/sys/__assert.h>
#include <soc.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include "sedi_driver_uart.h"
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>evice *dev)
{
const struct uart_sf32lb_config *config = dev->config;
return sys_test_bit(config->base + UART_ISR, USART_ISR_TXE_Pos);
}
static int uart_sf32lb_irq_tx_complete(const struct device *dev)
{
const struct uart_sf32lb_config *config = dev->config;
return sys_test_bit(config->base + UART_I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> SHELL_HELP("Read data from the UART device", "<device> <duration in secs>"),
cmd_uart_read, 3, 0),
SHELL_CMD_ARG(config, &dsub_device_name,
SHELL_HELP("Get the UART device configuration", "<device>"), cmd_uart_config,
2, 0),
SHELL_CMD_ARG(baudrate, &dsub_device_name,
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>callback) {
data->callback(dev, data->cb_data);
}
usart_si32_err_check(dev);
}
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
static DEVICE_API(uart, usart_si32_driver_api) = {
.poll_in = usart_si32_poll_in,
.poll_out = usart_si32_poll_out,
.err_check = usart_si32_err_check,
#ifdef CONFIG_UART_INTERRU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief UART driver for the SiFive Freedom Processor
*/
#define DT_DRV_COMPAT sifive_uart0
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/uart.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CHANNEL(idx, rx) \
EUSART_DMA_CHANNEL(idx, tx) \
}; \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT silabs_usart_uart
#include <errno.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/clock_control_silabs.h>
#include <zephyr/drivers/pinctrl.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (dev == uart_console_dev) {
#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
/* For device configured as console wake time is taken from
* Kconfig same way it is configured for other platforms
*/
rx_wake_timeout = CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT;
#endif
}
/* If DTR pin is configured, use it... | fim | zephyrproject-rtos/zephyr | c |
/* stellarisUartDrv.c - Stellaris UART driver */
#define DT_DRV_COMPAT ti_stellaris_uart
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Driver for Stellaris UART
*
* Driver for Stellaris UART found namely on TI LM3S6965 board. It is similar to
* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 Linaro Limited.
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT st_stm32_uart
/**
* @brief Driver for UART port on STM32 family processor.
* @note LPUART and U(S)ART have th... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>int8_t de_deassert_time;
/* enable de pin inversion */
bool de_invert;
/* enable fifo */
bool fifo_enable;
/* pin muxing */
const struct pinctrl_dev_config *pcfg;
#if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API) || \
defined(CONFIG_PM)
uart_irq_config_func_t irq_config_f... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
* Copyright (c) 2024 sensry.io
*/
#define DT_DRV_COMPAT sensry_sy1xx_uart
#include <zephyr/device.h>
#include <zephyr/drivers/uart.h>
#include <soc.h>
#include <zephyr/sys/printk.h>
#include <udma.h>
#include <pad_ctrl.h>
#include <zephyr/drivers/pinctrl.h>
s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
&virtconsole_config_##inst, POST_KERNEL, \
CONFIG_SERIAL_INIT_PRIORITY, &virtconsole_api);
DT_INST_FOREACH_STATUS_OKAY(VIRTIO_CONSOLE_DEFINE)
<|fim_prefix|>/*
* Copyright (c) 2025 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> if (!size || !(regs->STATR & USART_STATR_RXNE)) {
return 0;
}
rx_data[0] = regs->DATAR;
return 1;
}
static void usart_wch_irq_tx_enable(const struct device *dev)
{
const struct usart_wch_config *config = dev->config;
USART_TypeDef *regs = config->regs;
regs->CTLR1 |= (USART_CTLR1_TXEIE | USART... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* uart_xlnx_ps.c - Xilinx Zynq family serial driver */
/*
* Copyright (c) 2018 Xilinx, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT xlnx_xuartps
/**
* @brief Xilinx Zynq Family Serial Driver
*
* This is the driver for the Xilinx Zynq family cadence serial device.
*
* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
*
* Based on uart_mcux_lpuart.c, which is:
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT xlnx_xps_uartlite_1_00_a
#include <zephyr/device.h>
#include <zephyr/drivers/uart.h>
#include... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_USIC_CH_TXFIFO_EVENT_CONF_STANDARD);
} else {
XMC_USIC_CH_DisableEvent(config->uart, XMC_USIC_CH_EVENT_TRANSMIT_SHIFT);
}
}
static int uart_xmc4xxx_irq_rx_ready(const struct device *dev)
{
const struct uart_xmc4xxx_config *config = dev->config;
if (config->fifo_rx_size > 0) {
return !XMC_USIC_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>n -EINVAL;
}
if (!data->initialized) {
return -ENODEV;
}
cfg_out->baudrate = data->baud_rate;
cfg_out->parity = data->parity;
cfg_out->stop_bits = data->stop_bits;
cfg_out->data_bits = data->data_bits;
cfg_out->flow_ctrl = data->flow_ctrl;
return 0;
}
#endif /* CONFIG_UART_USE_RUNTIME_CONFIG... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2016 Piotr Mienkowski
* Copyright (c) 2018 Justin Watson
* Copyright (c) 2023 Gerson Fernando Budke
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT atmel_sam_usart
/** @file
* @brief USART driver for Atmel SAM MCU family.
*/
#include <errno.h>
#include <zephyr/sys/__assert.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>P(DT_SIP_SMC, zephyr_num_clients) != 0), "num-clients should not be zero");
BUILD_ASSERT((CONFIG_ARM_SIP_SVC_EL3_MAX_ALLOWED_TRANSACTIONS > 0),
"CONFIG_ARM_SIP_SVC_EL3_MAX_ALLOWED_TRANSACTIONS should be greater than 0");
#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
SIP_SVC_CONTROLLER_DEFINE(0, DT_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
*
* Intel I/O Controller Hub (ICH) later renamed to Intel Platform Controller
* Hub (PCH) SMBus driver.
*
* PCH provides SMBus 2.0 - compliant Host Controller.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/types.h>
#include <zephyr/kernel.h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nterrupt] " : "", \
reg & PCH_SMBUS_HSTS_DEV_ERROR ? "[Device Error] " : "",\
reg & PCH_SMBUS_HSTS_BUS_ERROR ? "[Bus Error] " : "", \
reg & PCH_SMBUS_HSTS_FAILED ? "[Failed] " : "", \
reg & PCH_SMBUS_HSTS_SMB_ALERT ? "[SMBALERT] " : "", \
reg & PCH_SMBUS_HSTS_BYTE_DONE ? "[Byte Done] " : "", \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/sys/slist.h>
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/smbus.h>
static inline int z_vrfy_smbus_configure(const struct device *dev,
uint32_t dev_config)
{
K_OOPS(K_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>sage: quick <device> <addr>",
cmd_smbus_quick, 3, 0),
SHELL_CMD_ARG(scan, &dsub_device_name,
"Scan SMBus peripheral devices command\n"
"Usage: scan <device>",
cmd_smbus_scan, 2, 0),
SHELL_CMD_ARG(byte_read, &dsub_device_name,
"SMBus: byte read command\n"
"... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 SILA Embedded Solutions GmbH
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c/stm32.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/smbus.h>
#include <zephyr/logging/log... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporation
* Copyright (c) 2023 SILA Embedded Solutions GmbH
* SPDX-License-Identifier: Apache-2.0
*/
#include "smbus_utils.h"
#include <zephyr/logging/log.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/crc.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>h the computed value.
*/
int smbus_read_check_pec(uint32_t flags, uint16_t addr, const struct i2c_msg *msgs,
uint8_t num_msgs);
#endif /* defined(CONFIG_SMBUS_SOFT_PEC) || defined(__DOXYGEN__) */
#endif /* ZEPHYR_DRIVERS_SMBUS_SMBUS_UTILS_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Intel Corporat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>T)
<|fim_prefix|>/*
* Copyright (c) 2024 Ambiq Micro Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* Some Ambiq Apollox Blue SOC (e.g. Apollo3 Blue) uses internal designed BLEIF module which is
* different from the general IOM module for SPI transceiver. The called HAL API will also be
* independe... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_spi
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_ambiq);
#include <zephyr/drivers/spi.h>
#include "spi_rtio.h"
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/k... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Ambiq <www.ambiq.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ambiq_spid
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_ambiq_spid);
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteor... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Andes Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "spi_andes_atcspi200.h"
#include <zephyr/irq.h>
#define DT_DRV_COMPAT andestech_atcspi200
typedef void (*atcspi200_cfg_func_t)(void);
#ifdef CONFIG_ANDES_SPI_DMA_MODE
#define ANDES_SPI_DMA_E... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Andes Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_atcspi200);
#include "spi_context.h"
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#ifdef CONFIG_ANDES_SPI_DM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Telink Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT telink_b91_spi
/* Redefine 'spi_read' and 'spi_write' functions names from HAL */
#define spi_read hal_spi_read
#define spi_write hal_spi_write
#include "spi.c"
#undef spi_read
#undef ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT renesas_ra8_spi_b
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
#include <zephyr/irq.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
&spi_bee_config_##index, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_bee_driver_api);
DT_INST_FOREACH_STATUS_OKAY(BEE_SPI_INIT)
<|fim_prefix|>/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space)
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT bflb_spi
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control.h>
#include <z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>) || spi_context_rx_buf_on(ctx)) {
uint32_t w = 0;
if (ctx->tx_len) {
switch (data->dfs) {
case 4:
case 3:
w = *(uint32_t *)(ctx->tx_buf);
break;
case 2:
w = *(uint16_t *)(ctx->tx_buf);
break;
case 1:
w = *(uint8_t *)(ctx->tx_buf);
break;
}
}
uint32_t r ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Brett Witherspoon
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_spi
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_cc13xx_cc26xx);
#include <zephyr/drivers/spi.h>
#include "spi_rtio.h"
#inclu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_cc23x0_spi
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_cc23x0, CONFIG_SPI_LOG_LEVEL);
#include <zephyr/device.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/pinctrl.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_CONF_TXCLR | SPI_CONF_RXCLR);
spi_cdns_spi_enable(dev, true);
data->fifo_diff = 0;
dfs = SPI_WORD_SIZE_GET(data->ctx.config->operation) / 8;
spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, dfs);
data->tx_remain_entry =
MAX(spi_context_total_rx_len(&data->ctx), spi_context_total_tx_len(&... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Private API for SPI drivers
*/
#ifndef ZEPHYR_DRIVERS_SPI_SPI_CONTEXT_H_
#define ZEPHYR_DRIVERS_SPI_SPI_CONTEXT_H_
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2015 Intel Corporation.
* Copyright (c) 2023 Synopsys, Inc. All rights reserved.
* Copyright (c) 2023 Meta Platforms
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT snps_designware_spi
/* spi_dw.c - Designware SPI driver implementation */
#define LOG_LEVEL CONF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>H_BIT)
#define DW_SPI_CTRLR0_SCPOL BIT(DW_SPI_CTRLR0_SCPOL_BIT)
#define DW_SPI_CTRLR0_SRL BIT(DW_SPI_CTRLR0_SRL_BIT)
#define DW_SPI_CTRLR0_SLV_OE BIT(DW_SPI_CTRLR0_SLV_OE_BIT)
#define DW_SPI_CTRLR0_TMOD_TX_RX (0)
#define DW_SPI_CTRLR0_TMOD_TX (1 << DW_SPI_CTRLR0_TMOD_SHIFT)
#define DW_SPI_CTRLR0_TMOD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>COMP_VERSION (0x5c)
#define DW_SPI_REG_DR (0x60)
#define DW_SPI_REG_RX_SAMPLE_DLY (0xf0)
#define DW_SPI_MIN_SCKDIV (0x2)
/* Register helpers */
DEFINE_MM_REG_WRITE(ctrlr0, DW_SPI_REG_CTRLR0, 32)
DEFINE_MM_REG_READ(ctrlr0, DW_SPI_REG_CTRLR0, 32)
DEFINE_MM_REG_WRITE(txftlr, DW_SPI_REG_TXFTLR, 32)
DEFIN... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Andes Technology Corporation.
* Copyright (c) 2025 Egis Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "spi_egis_et171.h"
#include <zephyr/irq.h>
#define DT_DRV_COMPAT egis_et171_spi
typedef void (*et171_cfg_func_t)(void);
#ifdef CONFIG_DCACHE
#ifdef CONFIG_CACHE_MA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Andes Technology Corporation.
* Copyright (c) 2025 Egis Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_egis_et171);
#include "spi_context.h"
#include <zephyr/device.h>
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DT_GET(node_id), \
},
#define SPI_EMUL_INIT(n) \
static const struct emul_link_for_bus emuls_##n[] = { \
DT_FOREACH_CHILD_STATUS_OKAY(DT_D... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020-2025 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT espressif_esp32_spi
/* Include esp-idf headers first to avoid redefining BIT() macro */
#include <hal/spi_hal.h>
#include <hal/spi_ll.h>
#include <esp_attr.h>
#include <esp_clk_tree... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_
#define ZEPHYR_DRIVERS_SPI_ESP32_SPIM_H_
#include <zephyr/drivers/pinctrl.h>
#include <hal/spi_hal.h>
#ifdef SOC_GDMA_SUPPORTED
#include <hal/gdma_hal.h>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>turn spi_gd32_dma_enabled(dev) ? 2 : 0;
}
#endif
static int spi_gd32_get_err(const struct spi_gd32_config *cfg)
{
uint32_t stat = SPI_STAT(cfg->reg);
if (stat & SPI_GD32_ERR_MASK) {
LOG_ERR("spi%u error status detected, err = %u",
cfg->reg, stat & (uint32_t)SPI_GD32_ERR_MASK);
return -EIO;
}... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Frontgrade Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT gaisler_spimctrl
#include <zephyr/driver<|fim_suffix|>;
return -ENOTSUP;
}
if (config->operation & SPI_MODE_LOOP) {
LOG_ERR("Loopback not supported");
return -ENOTSUP;
}
ctx->co... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>copy, 0, sizeof(tx_bufs_copy));
}
if (rx_bufs) {
const struct spi_buf_set *rx =
(const struct spi_buf_set *)rx_bufs;
K_OOPS(K_SYSCALL_MEMORY_READ(rx_bufs,
sizeof(struct spi_buf_set)));
memcpy(&rx_bufs_copy, rx, sizeof(rx_bufs_copy));
K_OOPS(K_SYSCALL_VERIFY(rx_bufs_copy.count < 32... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ource.block_num = get_hw_block_num(config->reg_addr);
/* Configure dt provided device signals when available */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
/* Configure slave select (master) */
spi_context_cs_configure_all(&data->ctx);
spi_conte... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT infineon_spi
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(cat1_spi, CONF... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
}; \
\
DEVICE_DT_INST_DEFINE(n, &spi_it51xxx_init, NULL, &spi_it51xxx_data_##n, \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 ITE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ite_it8xxx2_spi
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_it8xxx2, CONFIG_SPI_LOG_LEVEL);
#include <zephyr/irq.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/pinct... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> CONFIG_SPI_RTIO
.iodev_submit = spi_rtio_iodev_default_submit,
#endif
.release = spi_litex_release,
};
#define SPI_INIT(n) \
static struct spi_litex_data spi_litex_data_##n = { \
SP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>d, const uint8_t *tx_buf)
{
switch (len) {
case 4:
*txd = sys_get_be32(tx_buf);
break;
case 3:
*txd = sys_get_be24(tx_buf);
break;
case 2:
*txd = sys_get_be16(tx_buf);
break;
default:
*txd = *tx_buf;
break;
}
}
static inline void litex_spi_rx_put(uint8_t len, uint32_t *rxd, uint8_t ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Vogl Electronic GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT litex_spi_litespi
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_litex_litespi);
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/minma... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2026 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT adi_max32_spi
#include <string.h>
#include <errno.h>
#if CONFIG_SPI_MAX32_DMA
#include <zephyr/drivers/dma.h>
#endif
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/spi.h>
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ile (tx_count != 0 && rx_count != 0) {
if (tx->len != rx->len) {
return false;
}
tx++;
tx_count--;
rx++;
rx_count--;
}
return true;
}
static int spi_sam_transceive(const struct device *dev,
const struct spi_config *config,
const struct spi_buf_set *tx_bufs,
c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
SPI_CONTEXT_INIT_SYNC(mss_spi_data_##n, ctx), \
}; \
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne void mss_qspi_receive_x8(const struct device *dev, uint32_t len)
{
const struct mss_qspi_config *s = dev->config;
struct mss_qspi_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
uint32_t rdata, count;
rdata = mss_qspi_read(s, MSS_QSPI_REG_CONTROL);
rdata &= ~MSS_QSPI_CONTROL_FLAGSX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/spi.h>
#include "spi_rtio.h"
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/clock_control/mchp_clock_control.h>
#ifdef C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2017, 2020-2021, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_dspi
#include <errno.h>
#include <zephyr/drivers/spi.h>
#include "spi_rtio.h"
#include <zephyr/drivers/clock_control.h>
#include <fsl_dspi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024, Basalte bv
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_imx_ecspi
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(spi_mcux_ecspi, CONFIG_SPI_LOG_LEVEL);
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2017, 2019, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpc_spi
#include <errno.h>
#include <zephyr/drivers/spi.h>
#include "spi_rtio.h"
#include <zephyr/drivers/clock_control.h>
#include <fsl_spi.h>
#include <ze... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024, STRIM, ALC
* Copyright 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_flexio_spi
#include <errno.h>
#include <zephyr/drivers/spi.h>
#include "spi_rtio.h"
#include <zephyr/drivers/clock_control.h>
#include <fsl_flexio_spi.h>
#include <zeph... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Bang & Olufsen A/S, Denmark
* Copyright (c) 2026 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT ti_mspm0_spi
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/mspm0_clock_control.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>npcx_spip_data_##n, \
&spi_npcx_spip_cfg_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
&spi_npcx_spip_api);
DT_INST_FOREACH_STATUS_OKAY(NPCX_SPI_INIT)
<|fim_prefix|>/*
* Copyright (c) 2024 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/<|fim_suffix|>0) {
nrfx_gpiote_channel_free(gpiote, ch);
return res;
}
return 0;
}
int spi_nrfx_wake_request(nrfx_gpiote_t *gpiote, uint32_t wake_pin)
{
nrf_gpiote_event_t trigger_event = nrfx_gpiote_in_event_get(gpiote, wake_pin);
uint32_t start_cycles;
uint32_t max_wait_cycles =
DIV_ROUND_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_SPI_NRFX_COMMON_H_
#define ZEPHYR_DRIVERS_SPI_NRFX_COMMON_H_
#include <stdint.h>
#include <nrfx_gpiote.h>
#include <gpiote_nrfx.h>
#include <zephyr/drivers/gpio/gpio_nrf.h>
#define WA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 - 2018, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/spi.h>
#include "spi_rtio.h"
#include <zephyr/pm/device.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <nrfx_spi.h>
#include <zephyr/logging/log.h>
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_spim
#include "spi_nrfx_spim_common.h"
LOG_MODULE_DECLARE(spi_nrfx_spim);
#include "spi_context.h"
struct driver_data {
struct spi_nrfx_common_data common;
struct spi_con... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>IVE);
if (ret) {
return ret;
}
}
return 0;
}
#if SPI_NRFX_HAS_WAKE
static void wake_stop(const struct device *dev)
{
struct spi_nrfx_common_data *dev_data = dev->data;
const struct spi_nrfx_common_config *dev_config = dev->config;
gpio_pin_interrupt_configure_dt(&dev_config->wake_pin, GPIO_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Nordic Semiconductor ASA
*
* SPDX-Licens<|fim_suffix|>ta \
) \
\
static void CONCAT(irq_connect, inst)(void) \
{ \
NRF_DT_INST_IRQ_CONNECT( \
inst, \
nrfx_spim_irq_handler, \
_data \
); ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_spim
#include "spi_nrfx_spim_common.h"
#include "spi_rtio.h"
LOG_MODULE_DECLARE(spi_nrfx_spim);
struct driver_data {
struct spi_nrfx_common_data common;
};
struct driver_c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nordic_nrf_spis
#include <zephyr/drivers/spi.h>
#include "spi_rtio.h"
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/gpio.h>
#include <dmm.h>
#include <soc.h>
#include <n... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
.clk_src = DT_INST_CLOCKS_CELL(inst, clock_source), \
.clk_div = DT_INST_CLOCKS_CELL(inst, clock_divider), \
.clk_dev = DEVICE_DT_GET(DT_PARENT(DT_INST_CLOCKS_CTLR(inst))), \
.pincfg = PINCTRL_DT_INST_D... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t device *dev)
{
struct spi_numaker_usci_data *data = dev->data;
const struct spi_numaker_usci_config *dev_cfg = dev->config;
int err = 0;
struct numaker_scc_subsys scc_subsys;
SYS_UnlockReg();
memset(&scc_subsys, 0x00, sizeof(scc_subsys));
scc_subsys.subsys_id = NUMAKER_SCC_SUBSYS_ID_PCC;
scc_s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>spi, lpspi_driver_api) = {
.transceive = lpspi_transceive_sync,
#ifdef CONFIG_SPI_ASYNC
.transceive_async = lpspi_transceive_async,
#endif
#ifdef CONFIG_SPI_RTIO
.iodev_submit = spi_rtio_iodev_default_submit,
#endif
.release = spi_lpspi_release,
};
static int lpspi_init(const struct device *dev)
{
L... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0, best_div = 0;
uint32_t best_freq = 0;
for (int8_t prescaler = 7U; prescaler >= 0; prescaler--) {
/* if maximum freq (div = 0) won't get better than what we got with
* previous prescaler, then we can fast path exit this loop.
*/
if (lpspi_calc_sck_freq(clock_freq, 0, prescaler) < best_freq... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
LOG_ERR("unknown spi stransfer state:%d", dma_data->state);
ret = -EIO;
goto error;
}
LOG_DBG("DMA %cX Block Complete", debug_char);
return;
error:
LOG_ERR("DMA callback error with channel %d.", channel);
spi_context_complete(ctx, spi_dev, ret);
spi_context_cs_control(ctx, false);
}
static ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rifies spi_cfg validity and set up configuration of hardware for xfer
* Unsets interrupt and watermark options, specific implementation should configure that.
* Sets bits in the TCR ONLY *directly* relating to what is in the spi_config struct.
*/
int lpspi_configure(const struct device *dev, const stru... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>iodev_start(dev);
}
}
static int transceive_rtio(const struct device *dev, const struct spi_config *spi_cfg,
const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs)
{
struct lpspi_data *data = (struct lpspi_data *)dev->data;
struct lpspi_driver_data *drv_data = (struct lpspi_driver... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022-2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_s32_spi
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include "spi_nxp_s32.h"
static bool spi_nxp_s32_last_packet(struct spi_nxp_s32_data *data)
{
struct spi_context *... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2022-2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_SPI_SPI_NXP_S32_H_
#define ZEPHYR_DRIVERS_SPI_SPI_NXP_S32_H_
#include <zephyr/drivers/spi.h>
#include "spi_rtio.h"
#include <zephyr/logging/log.h>
#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
LOG_MODULE_REGISTER(spi_nxp_s32);... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ruct device *dev)
{
int err;
const struct spi_oc_simple_cfg *info = dev->config;
struct spi_oc_simple_data *data = dev->data;
/* Clear chip selects */
sys_write8(0, SPI_OC_SIMPLE_SPSS(info));
err = spi_context_cs_configure_all(&data->ctx);
if (err < 0) {
return err;
}
/* Make sure the contex... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Western Digital Corporation or its affiliates
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "spi_context.h"
#define SPI_OC_SIMPLE_DATA(dev) \
((struct spi_oc_simple_data *) ((dev)->data))
#define SPI_OC_SIMPLE_REG(info, offset) \
((mem_addr_t) (info->base + \
... | fim | zephyrproject-rtos/zephyr | c |
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