text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
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|---|---|---|---|
<|fim_suffix|>_HAS_64BIT_CYCLE_COUNTER
EXPORT_SYMBOL(sys_clock_cycle_get_64);
#endif
<|fim_prefix|>/*
* Copyright (c) 2024 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/llext/symbol.h>
#include <limits.h>
#ifdef <|fim_middle|>CONFIG_TI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>n timer is initialized */
static bool g_init;
static void burtc_isr(const void *arg)
{
ARG_UNUSED(arg);
/* Clear the interrupt */
BURTC_IntClear(BURTC_IF_COMP);
uint32_t curr = BURTC_CounterGet();
/* NOTE: this is the only place where g_last_count is modified,
* so we don't need to do make the ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> = ret;
return ret;
}
__pinned_func
uint32_t sys_clock_cycle_get_32(void)
{
return (uint32_t)hpet_counter_get();
}
__pinned_func
uint64_t sys_clock_cycle_get_64(void)
{
return hpet_counter_get();
}
__pinned_func
void sys_clock_idle_exit(void)
{
uint32_t reg;
reg = hpet_gconf_get();
reg |= GCONF_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Low Power timer driver for Infineon CAT1 MCU family.
*/
#define DT_DRV_COMPAT infineon_lp_timer
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>c const uint16_t LPTIMER_SETMATCH_TIME_US;
static const cy_stc_mcwdt_config_t lptimer_default_cfg = {.c0Match = 0xFFFF,
.c1Match = 0xFFFF,
.c0Mode = CY_MCWDT_MODE_INT,
.c1Mode = CY_MCWDT_MODE_INT,
.c2Mode = CY_MCWDT_MODE_NONE,
.c2ToggleBit = 0,
.c0Cle... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>d)
{
return count();
}
/* Interrupt setup is partially-cpu-local state, so needs to be
* repeated for each core when it starts. Note that this conforms to
* the Zephyr convention of sending timer interrupts to all cpus (for
* the benefit of timeslicing).
*/
static void irq_init(void)
{
int cpu = a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EL)) {
/* Always return for non-tickless kernel system */
return;
}
/* Critical section */
k_spinlock_key_t key = k_spin_lock(&lock);
/* Disable event timer */
ext_timer_disable(EVENT_TIMER);
if (ticks == K_TICKS_FOREVER) {
/*
* If kernel doesn't have a timeout:
* 1.CONFIG_SYSTEM_CLOC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>AX_CNT_SYS_TICK (EVENT_TIMER_MAX_CNT \
/ HW_CNT_PER_SYS_TICK)
/* Timer tick threshold to prevent SoC from entering idle mode.
* Calculated as 150µs converted to timer ticks using the formula:
* ticks = us * timer_clk_src / 1000000
* where (event/free run timers)timer_clk_src is fixed at 32768Hz... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019-2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This driver uses two independent GPTIMER subtimers:
* - subtimer 1 is a free-running up-counter clocked at the system cycle rate
* divided by the shared prescaler, the definitive time base used for bot... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
<|fim_prefix|>/*
* Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT litex_timer0
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>struct device *unused)
{
ARG_UNUSED(unused);
k_spinlock_key_t key;
key = k_spin_lock(&lock);
uint32_t curr_cycle = MXC_TMR_GetCount(regs);
uint32_t delta_cycles = curr_cycle - last_cycle;
uint32_t delta_ticks = (uint32_t)delta_cycles / CYC_PER_TICK;
last_cycle += (uint32_t)delta_ticks * CYC_PER_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_S2RAM */
static int sys_clock_driver_init(void)
{
uint8_t prescaler_lo, prescaler_hi;
mxc_wut_pres_t pres;
mxc_wut_cfg_t wut_cfg;
/* Select 32kHz clock source */
Wrap_MXC_SYS_Select32KClockSource(WUT_CLK_SRC);
/* Calculate prescaler register values */
prescaler_lo = FIELD_GET(GENMASK(2, 0), LOG... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT microchip_sam_pit64b
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <zephyr/l... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NT_MASK;
k_spin_unlock(&lock, key);
return ticks;
}
static void xec_rtos_timer_isr(const void *arg)
{
ARG_UNUSED(arg);
uint32_t cycles;
int32_t ticks;
k_spinlock_key_t key = k_spin_lock(&lock);
sys_write32(BIT(TIMER_GIRQ_BITPOS), TIMER_GIRQ_BASE + GIRQ_SRC_OFS);
/* Restart the timer as earl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_gpt_hw_timer
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <fsl_gpt.h>
#include <zephyr/sys_clock.h>
#include <zephyr/spinlock.h>
#include <zephyr/sys/time_units.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Vestas Wind Systems A/S
* Copyright (c) 2025-2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/devicetree.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/time_units.h>
#include <fsl_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_os_timer
#include <limits.h>
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/drivers/timer/nxp_os_timer.h>
#include <zephyr/irq.h>
#include <zephyr/sys_clo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020, 2021 Antony Pavlov <antonynpavlov@gmail.com>
* Copyright (c) 2021 Remy Luisant <remy@luisant.ca>
*
* Based on riscv_machine_timer.c and xtensa_sys_timer.c
*
* SPDX-License-Identifier: Ap<|fim_suffix|>PS_MACHINE_TIMER_IRQ, 0, timer_isr, NULL, 0);
last_count = get_cp0_count()... | fim | zephyrproject-rtos/zephyr | c |
/* Copyright 2023 The ChromiumOS Authors
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/spinlock.h>
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#if defined(CONFIG_TEST)
const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_NODELABEL(ostimer0));
#endif
#define OSTIMER64_BASE DT_R... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017-2019 Oticon A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* Driver for the native_sim board timer
* It provides the same API required by the kernel as any other timer driver
*/
#include <zephyr/types.h>
#include <zephyr/irq.h>
#include <zephyr/init.h>
#include <zephyr/... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nuvoton_npcx_itim_timer
/**
* @file
* @brief Nuvoton NPCX kernel device driver for "system clock driver" interface
*
* This file contains a kernel device driver implemented b... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#if defined(CONFIG_CLOCK_CONTROL_NRF)
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#endif
#include <zephyr/drivers/p... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2016-2021 Nordic Semiconductor ASA
* Copyright (c) 2018 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/nrf_clock_control.h>
#include <zephyr/drivers/timer/sys... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>rrent_count - last_count;
const uint32_t delta_ticks = delta_count / cyc_per_tick;
last_elapsed = delta_ticks;
k_spin_unlock(&lock, key);
return delta_ticks;
}
uint32_t sys_clock_cycle_get_32(void)
{
return get_count();
}
static int sys_clock_driver_init(void)
{
cyc_per_tick = (uint32_t)((uint64_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 IoT.bzh <julien.massot@iot.bzh>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/ren... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
* Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
*/
#define DT_DRV_COMPAT realtek_rts5912_rtmr
#include <stdint.h>
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <zephyr/s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>R_WAIT(RA_ULPT_INST0_REG->ULPTCR_b.TSTART,
RA_ULPT_INST0_REG->ULPTCR_b.TCSTF);
FSP_HARDWARE_REGISTER_WAIT(RA_ULPT_INST1_REG->ULPTCR_b.TSTART,
RA_ULPT_INST1_REG->ULPTCR_b.TCSTF);
cycle_announced = 0U;
return 0;
}
/* Initialize the system timer driver during pre-kernel stage 2. */
SYS_INI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>R_TICK;
delay += elapsed;
delay = DIV_ROUND_UP(delay, CYCLES_PER_TICK) * CYCLES_PER_TICK;
delay -= elapsed;
uint16_t current = *tick_timer_cfg.cmcnt;
uint16_t new_cmcor = (uint16_t)(current + delay - 1U);
*tick_timer_cfg.cmcor = new_cmcor;
k_spin_unlock(&lock, key);
}
SYS_INIT(sys_clock_driver... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t32_t delta_cycles = sys_clock_cycle_get_32() - data->last_cycle;
uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
data->last_elapsed = delta_ticks;
k_spin_unlock(&data->lock, key);
return delta_ticks;
}
void sys_clock_disable(void)
{
struct rz_os_timer_config *config = (struct rz_os_timer_conf... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dler, NULL, DT_IRQ_BY_NAME(RZA2M_OSTM(0), overflow, flags));
/* Restarting the timer will cause reset of CNT register in free-running mode */
sys_clock_disable();
sys_write32(cyc_per_tick, OSTM_REG_ADDR(OSTM_CMP_OFFSET));
sys_write8(OSTM_CTL_FREERUN, OSTM_REG_ADDR(OSTM_CTL_OFFSET));
sys_write8(OSTM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
* Copyright (c) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <limits.h>
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/sys_clock.h>
#i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
* Copyright (c) 2018-2023 Intel Corporation
* Copyright (c) 2026 Alexios Lyrakis <alexios.lyrakis@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <limits.h>
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2018 Foundries.io Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT openisa_rv32m1_lptmr
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <soc.h>
#include <zephyr/irq.h>
/*
* This is jus... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nt % CYCLES_PER_TICK;
/* Round to the nearest tick boundary. */
timeout = DIV_ROUND_UP(timeout, CYCLES_PER_TICK) * CYCLES_PER_TICK;
if (timeout < TICK_THRESHOLD) {
timeout += CYCLES_PER_TICK;
}
rtc_sync();
RTC0->COMP[0].reg = count + timeout;
#else /* !CONFIG_TICKLESS_KERNEL */
if (ticks == ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>er_timer_data *timer)
{
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return;
}
ticks = (ticks == K_TICKS_FOREVER) ? timer->max_timeout_ticks : ticks;
ticks = CLAMP(ticks, 0, timer->max_timeout_ticks);
k_spinlock_key_t key = k_spin_lock(&timer->lock);
uint32_t curr = sl_sleeptimer_get_tick_count()... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)
{
TIMER2->TIMER2_CTRL_REG &= ~TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk;
}
void timer2_isr(const void *arg)
{
uint32_t val;
int32_t delta;
int32_t dticks;
ARG_UNUSED(arg);
TIMER2->TIMER2_CLEAR_IRQ_REG = 1;
val = timer_val_32();
delta = (int32_t)(val - last_isr_val_rounded);
last_isr_val = val;
dti... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>s to the kernel */
dticks = (missed_lptim_cnt * CONFIG_SYS_CLOCK_TICKS_PER_SEC)
/ lptim_clock_freq;
sys_clock_announce(dticks);
/* We've already performed all needed operations */
timeout_stdby = false;
}
#endif /* CONFIG_STM32_LPTIM_STDBY_TIMER */
}
SYS_INIT(sys_clock_driver_init, PRE_KERN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> while ((current_time - last_cpu_wakeup_time) < 16U);
LL_RADIO_TIMER_SetCPUWakeupTime(WAKEUP, current_time + delay + TIMER_ROUNDING);
LL_RADIO_TIMER_EnableCPUWakeupTimer(WAKEUP);
irq_unlock(key);
}
}
uint32_t sys_clock_elapsed(void)
{
if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
return 0;
}
r... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>SET_BIT 1
#define SY1XX_TIMER_IRQ_ENABLE_BIT 2
#define SY1XX_TIMER_IEM_BIT 3
#define SY1XX_TIMER_CMP_CLR_BIT 4
#define SY1XX_TIMER_ONE_SHOT_BIT 5
#define SY1XX_TIMER_PRESCALER_ENABLE_BIT 6
#define SY1XX_TIMER_CLOCK_SOURCE_BIT 7
#define SY1XX_TIMER_PRESCAL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright <|fim_suffix|> @file
* @brief Initialize system clock driver
*
* Initializing the timer driver is done in this module to reduce code
* duplication.
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
/* Weak-linked noop defaults for ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>n how
* many ticks we scheduled, then treat this as wraparound.
*/
wraparound_occurred = counter_int_pending &&
((uint64_t)counter_pre_lpm_ticks + counter_scheduled_lpm_ticks
>= counter_top);
}
if (wraparound_occurred) {
ticks_elapsed = (counter_top - counter_pre_lpm_ticks) + post_lpm_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (C) 2023 BeagleBoard.org Foundation
* Copyright (C) 2023 S Prashanth
* Copyright (c) 2024 Texas Instruments Incorporated
* Andrew Davis <afd@ti.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/irq... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (10)
#define TI_DM_TIMER_TCLR_TRG_MASK (0x00000c00)
#define TI_DM_TIMER_TCLR_PT_SHIFT (12)
#define TI_DM_TIMER_TCLR_PT_MASK (0x00001000)
#define TI_DM_TIMER_TCLR_CAPT_MODE_SHIFT (13)
#d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (c) 2025 Texas Instruments Incorporated
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/irq.h>
#include <zephyr/sys_clock.h>
#include <zephyr/kernel.h>
#include "ti_rti_timer.h"
#define DT_DRV_COMPAT t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (c) 2025 Texas Instruments Incorporated
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_TIMERS_TI_RTI_TIMER_H_
#define ZEPHYR_DRIVERS_TIMERS_TI_RTI_TIMER_H_
#include <zephyr/devicetree.h>
/*
* Refer to "AM261x Sitara Microcontrollers Technical Reference Manual" (Rev. ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>STK_STRE | STK_STCLK | STK_STIE | STK_STE;
irq_enable(DT_INST_IRQN(0));
return 0;
}
SYS_INIT(ch32v00x_systick_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
<|fim_prefix|>/*
* Copyright (c) 2024 Michael Hope
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT wch_systick
#... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
* Copyright (c) 2018 Xilinx, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT xlnx_ttcps
#include <zephyr/arch/cpu.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <zephyr/sys_clock.h>
#include <soc.h>
#include <zeph... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>e of interval counter */
#define XTTC_MAX_INTERVAL_COUNT 0xFFFFFFFFU
#endif /* ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_ */
<|fim_prefix|>/*
* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
* Copyright (c) 2018 Xilinx, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_D... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Intel Corporation
* Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
#include <zephyr/drivers/timer/system_timer.h>
#include <zephyr/sys_clock.h>
#include <zephyr/irq.h>
#include "xtensa_sys_timer.h"... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>is programmed.
*
* The SoC-specific implementation may:
* - Configure an always-on low-power timer (LPTIM) that continues
* running while the CPU CCOUNT register is halted.
* - Program the LPTIM to wake the system after at most
* @p max_lpm_time_us microseconds.
* - Perform any additional ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>m)
{
struct uaol_intel_adsp_data *dp = dev->data;
k_spinlock_key_t key;
int ret;
key = k_spin_lock(&lock);
if (!dp->is_powered_up) {
ret = -EIO;
LOG_ERR("Device not powered on");
goto out;
}
ret = uaol_intel_adsp_set_stream_state(dev, stream, true);
if (ret) {
LOG_ERR("uaol_intel_adsp_s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_UAOL_UAOL_INTEL_ADSP_H_
#define ZEPHYR_DRIVERS_UAOL_UAOL_INTEL_ADSP_H_
#include <stdint.h>
/* UAOL HD Audio Multiple Links (HDAML) Registers */
#define UAOLCAP_OFFSET 0x00
#define UAOLCTL_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/usb/usb_bc12.h>
#include <zep<|fim_suffix|>c12_set_role(const struct device *dev, enum bc12_role role)
{
K_OOPS(K_SYSCALL_DRIVER_BC12(dev, set_role));
return z_impl_bc12_set_role(dev, role);
}
s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nrfx.h>
#include <assert.h>
#include <zephyr/device.h>
#include <zephyr/drivers/regulator.h>
#include <zephyr/drivers/usb/usb_bc12.h>
#include <nrf_usbhs_wrapper.h>
#include <zephyr/l... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>de a devicetree property indicating
* whether the USB data path is supported.
*/
pi3usb9201_set_mode(dev, PI3USB9201_USB_PATH_ON);
break;
case BC12_TYPE_CDP:
if (IS_ENABLED(CONFIG_USB_BC12_PI3USB9201_CDP_ERRATA)) {
/*
* Switch to SDP after device is plugged in to avoid
* noise (pul... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
/* PI3USB9201 USB BC 1.2 Charger Detector driver definitions */
#ifndef ZEPHYR_INCLUDE_USB_BC12_PI3USB9201_H
#define ZEPHYR_INCLUDE_USB_BC12_PI3USB9201_H
#define PI3USB9201_REG_CTRL_1 0x0
#define PI3USB9201_<|fim_suffix|... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2022 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*
* Emulator for Diodes PI3USB9201 Dual-Role USB Charging-Type Detector.
*/
#include <zephyr/device.h>
#include <zephyr/drivers/emul.h>
#include <zephyr/drivers/gpio/gpio_emul.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c_em... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 Nordic Semiconductor ASA
*
*<|fim_suffix|>
<|fim_middle|> SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/net_buf.h>
#include <zephyr/drivers/usb/usb_buf.h>
static inline uint8_t *usb_pool_data_alloc(struct net_buf *const buf,
size_t *co... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>per_data_##n, &usbhs_wrapper_config_##n, \
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(NRF_USBHS_WRAPPER_DEFINE)
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>text, and must not be blocking.
*/
void nrf_usbhs_wrapper_set_udc_cb(const struct device *dev,
regulator_callback_t cb,
const void *const user_data);
#endif /* ZEPHYR_DRIVERS_USB_COMMON_NORDIC_NRF_USBHS_WRAPPER_H_ */
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright Nordic Semiconductor ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>um];
} else {
return NRF_USBD->HALTED.EPOUT[ep_num];
}
}
return false;
}
void nrf_usbd_common_ep_dtoggle_clear(nrf_usbd_common_ep_t ep)
{
__ASSERT_NO_MSG(!NRF_USBD_COMMON_EP_IS_ISO(ep));
NRF_USBD->DTOGGLE = ep | (USBD_DTOGGLE_VALUE_Nop << USBD_DTOGGLE_VALUE_Pos);
NRF_USBD->DTOGGLE = ep | (U... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2016 - 2023, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* This file is undergoing transition towards native Zephyr nrf USB driver. */
/** @cond INTERNAL_HIDDEN */
#ifndef NRF_USBD_COMMON_H__
#define NRF_USBD_COMMON_H__
#include <nrfx.h>
#ifdef __cplusp... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2016 - 2023, Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* This file is undergoing transition towards native Zephyr nrf USB driver. */
/** @cond INTERNAL_HIDDEN */
#ifndef NRF_USBD_COMMON_ERRATA_H__
#define NRF_USBD_COMMON_ERRATA_H__
#include <nrfx.h>
#ifndef NRF_USB... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>MMIO write at runtime.
*/
#define STM32F4_PHY_CFG(usb_node) \
COND_CODE_1(DT_NODE_HAS_COMPAT(usb_node, st_stm32_otghs), \
(LL_AHB1_GRP1_PERIPH_OTGHSULPI), (0))
#define EMBFS_PHY_CFG(usb_node) \
IF_ENABLED(CONFIG_SOC_SERIES_STM32H7X, \
(STM32H7_PHY_CFG(usb_node))) \
IF_ENABLED(... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ere PHY configuration registers reside */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Configure PHY input frequency selection */
HAL_SYSCFG_SetOTGPHYReferenceClockSelection(cfg->reference);
/* Deassert PHY reset */
HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
/* Configure PHY input mux (if provided)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>STATUS_OKAY(compat, _FOREACH_NODE)
FOR_EACH(_FOREACH_COMPAT, (), STM32_USB_COMPATIBLES)
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* ULPI PHY interface driver
*
* Note use of __maybe_unused because this is included
* unconditionally in t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/* STM32F7 USBPHYC driver */
#define DT_DRV_COMPAT st_stm32_usbphyc /* Unused; defined for grep-ability */
<|fim_suffix|>o be enabled, even
* though we are NOT using the ULPI interface...
*
* We _could_ requir... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/* STM32N6 USBPHYC driver */
#define DT_DRV_COMPAT st_stm32_usbphyc /* Unused; defined for grep-ability */
#include <soc.h>
#include <stm32_bitops.h>
#include <zephyr/device.h>
#include <zephyr/drivers/clock_cont... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_USB_COMMON_STM32_STM32_USB_COMMON_H_
#define ZEPHYR_DRIVERS_USB_COMMON_STM32_STM32_USB_COMMON_H_
#include <zephyr/device.h>
#include <zephyr/sys/util.h>
#include <zephyr/types.h>
/* Compatib... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> Enable USB OTG booster */
LL_PWR_EnableUSBBooster();
while (!LL_PWR_IsActiveFlag_USBBOOSTRDY()) {
/* Wait for USB OTG booster to be ready */
}
#elif defined(PWR_USBSCR_USB33SV) || defined(PWR_SVMCR_USV)
/*
* VDDUSB independent USB supply (PWR clock is on)
* with LL_PWR_EnableVDDUSB function (h... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>SIZ0_PKTCNT_MASK (0x1UL << USB_DWC2_DOEPTSIZ0_PKTCNT_POS)
#define USB_DWC2_DOEPTSIZ0_XFERSIZE_POS 0UL
#define USB_DWC2_DOEPTSIZ0_XFERSIZE_MASK 0x7FUL
USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_supcnt, DOEPTSIZ0_SUPCNT)
USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_pktcnt, DOEPTSIZ0_PKTCNT)
USB_DWC2_GET_FIELD_DEFINE(doe... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief USB DesignWare device controller driver
*
* USB DesignWare device controller driver. The driver implements the low
* level control routines to deal directly... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_USB_DEVICE_USB_DC_DW_STM32_H
#define ZEPHYR_DRIVERS_USB_DEVICE_USB_DC_DW_STM32_H
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/drivers/clock_control/stm32_clock_contro... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> ep_idx);
return -EINVAL;
}
if (ep_idx > EP0) {
udata0.ep_data[ep_idx].mps = cfg->ep_mps;
}
udata0.ep_data[ep_idx].ep_status = EP_CHECK;
LOG_DBG("Check cap(%02x)", cfg->ep_addr);
return 0;
}
int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data *const cfg)
{
uint8_t ep_idx = USB_EP_GET_ID... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (data != NULL) {
for (uint32_t i = 0; i < data_len; i++) {
data[i] = bufp[i];
}
}
LOG_DBG("Read idx %d, req %d, read %d bytes", bd_idx, max_data_len,
data_len);
if (read_bytes) {
*read_bytes = data_len;
}
return 0;
}
int usb_dc_ep_read_continue(uint8_t ep)
{
uint8_t ep_idx = USB_EP_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_IDX(ep_init.endpointAddress);
dev_state.eps[ep_abs_idx].ep_mps = USB_CONTROL_EP_MPS;
status = dev_state.dev_struct.controllerInterface->deviceControl(
dev_state.dev_struct.controllerHandle,
kUSB_DeviceControlEndpointInit, &ep_init);
if (kStatus_USB_Success != status) {
LOG_ERR("Failed to init... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>(!usbip_send_common(ep, ep_ctrl->buf_len)) {
return -EIO;
}
if (usbip_send(ep, ep_ctrl->buf, ep_ctrl->buf_len) !=
ep_ctrl->buf_len) {
return -EIO;
}
LOG_HEXDUMP_DBG(ep_ctrl->buf, ep_ctrl->buf_len, ">");
ep_ctrl->cb(ep, USB_DC_EP_DATA_IN);
ep_ctrl->buf_len = 0;
}
return 0;
}
<... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* For accept4() */
#define _GNU_SOURCE 1
#define __packed __attribute__((__packed__))
#include <stdio.h>
#include <stdarg.h>
#include <stdbool.h>
#include <errno.h>
#include <string.h>
#include <unistd.h>
#includ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
struct op_common {
uint16_t version;
uint16_t code;
uint32_t status;
} __packed;
struct devlist_device {
char path[256];
char busid[32];
uint32_t busnum;
uint32_t devnum;
uint32_t speed;
uint16_t idVendor... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Nordic Semiconductor ASA
* Copyright (c) 2018 Sundar Subramaniyan <sundar.subramaniyan@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file usb_dc_nrfx.c
* @brief Nordic USB device controller driver
*
* The driver implements the interface between the USBD p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> device *dev = numaker_usbd_device_get();
struct numaker_usbd_data *data = dev->data;
LOG_DBG("USB device address=%u (0x%02x)", addr, addr);
numaker_usbd_lock(dev);
/* NOTE: Timing for configuring USB device address into H/W is critical. It must be done
* in-between SET_ADDRESS control transfer a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t implemented");
return 0;
}
int usb_dc_reset(void)
{
LOG_ERR("Not implemented");
return 0;
}
int usb_dc_wakeup_request(void)
{
LOG_DBG("Remote Wakeup");
state.rwu_pending = true;
hw_set_alias(usb_hw)->sie_ctrl = USB_SIE_CTRL_RESUME_BITS;
return 0;
}
/*
* This thread is only used to not run ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>i = 0; i < ARRAY_SIZE(usb_sam0_pcksize_bytes); i++) {
if (usb_sam0_pcksize_bytes[i] == cfg->ep_mps) {
size = i;
break;
}
}
if (size < 0) {
return -EINVAL;
}
if (USB_EP_DIR_IS_IN(cfg->ep_addr)) {
bank = &desc->DeviceDescBank[1];
} else {
bank = &desc->DeviceDescBank[0];
}
buf = (v... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ck();
regs->UECONSET[0] = USBC_UECON0SET_NAKINES;
irq_unlock(key);
}
} else {
LOG_ERR("Invalid STP state %d on OUT phase", epctrl_fsm);
return -EPERM;
}
return 0;
}
int usb_dc_ep_read_ex(uint8_t ep, uint8_t *data, uint32_t max_data_len,
uint32_t *read_bytes, bool wait)
{
uint8_t e... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>store EP0 configuration to previously set mps */
struct usb_dc_ep_cfg_data cfg = {
.ep_addr = 0,
.ep_mps = dev_data.ep_data[0].mps,
.ep_type = USB_DC_EP_CONTROL,
};
usb_dc_ep_configure(&cfg);
usb_dc_ep_enable(0);
}
if (usb_dc_ep_is_enabled(0)) {
/* The device clears some of ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
}
if (txs & USB_USB_TXS1_REG_USB_TX_URUN_Msk) {
LOG_DBG("EP 0x%02x FIFO underrun\n", ep_state->ep_addr);
}
/* Start next or repeated packet. */
start_tx_packet(ep_state);
}
static void handle_tx_ev(void)
{
if (USB->USB_TXEV_REG & BIT(0)) {
handle_epx_tx_ev(usb_dc_get_ep_in_state(1));
}
if (... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>) {
LOG_ERR("HAL_PCD_EP_SetStall failed(0x%02x), %d", ep,
(int)status);
return -EIO;
}
ep_state->ep_stalled = 1U;
return 0;
}
int usb_dc_ep_clear_stall(const uint8_t ep)
{
struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
HAL_StatusTypeDef status;
LOG_DBG("ep 0x%02x"... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 Ambiq Micro Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
#include <string.h>
#include <zephyr/drivers/clock_control/clock_control_ambiq.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/usb/udc.h>
#include <zephyr/drivers/gpio.... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>essing */
atomic_and(&priv->xfer_finished, ~BIT(ep_to_bnum(ep_cfg->addr)));
udc_ep_set_busy(ep_cfg, false);
irq_unlock(lock_key);
return 0;
}
static int udc_bflb_v1_ep_enable(const struct device *dev,
struct udc_ep_config *const ep_cfg)
{
const struct udc_bflb_v1_config *const config = dev->c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ret = -EPERM;
goto ep_set_halt_error;
}
cfg = udc_get_ep_cfg(dev, ep);
if (cfg == NULL) {
ret = -ENODEV;
goto ep_set_halt_error;
}
if (!cfg->stat.enabled) {
ret = -ENODEV;
goto ep_set_halt_error;
}
if (ep_attrib_get_transfer(cfg->attributes) == USB_EP_TYPE_ISO) {
ret = -ENOTSUP;
go... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021-2022 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Private API for USB device controller (UDC) drivers
*/
#ifndef ZEPHYR_INCLUDE_UDC_COMMON_H
#define ZEPHYR_INCLUDE_UDC_COMMON_H
#include <zephyr/drivers/usb/udc.h>
#include <zephy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> uint32_t max_pkts, max_transfer;
/* Maximum number of packets that can fit in TxFIFO */
max_pkts = spcavail / spcperpkt;
/* We can transfer up to max_pkts MPS packets and a short one */
max_transfer = (max_pkts * udc_mps_ep_size(cfg)) +
(spcavail % spcperpkt);
/* If there is enoug... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0<|fim_suffix|>ce *dev);
/* Called at the end of IRQ handling */
int (*irq_clear)(const struct device *dev);
/* Called on driver pre-init */
int (*caps)(const struct device *dev);
/* Called while waiting for bit... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDXFileCopyrightText: Copyright (c) 2023 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_USB_UDC_DWC2_ESP32_USB_OTG_H
#define ZEPHYR_DRIVERS_USB_UDC_DWC2_ESP32_USB_OTG_H
#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
#include <zephyr/drivers... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_USB_UDC_DWC2_INFINEON_USBHS_H
#define ZEPHYR_DRIVERS_USB_UDC_DWC2_INFINEON_USBHS_H
#include ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>wrapper + 0x004);
return 0;
}
static inline int usbhs_pre_hibernation_exit(const struct device *dev)
{
struct usb_dwc2_reg *const base = dwc2_get_base(dev);
NRF_USBHS_Type *wrapper = USBHS_DT_WRAPPER_REG_ADDR(0);
sys_clear_bits((mem_addr_t)&base->pcgcctl, USB_DWC2_PCGCCTL_GATEHCLK);
wrapper->TASK... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t);
usbhs_release_pclk24m();
return 0;
}
static inline int usbhs_disable_vreg(const struct device *dev)
{
const struct device *parent = DEVICE_DT_GET(DT_INST_PARENT(0));
ARG_UNUSED(dev);
return nrf_usbhs_wrapper_vreg_disable(parent);
}
static inline int usbhs_init_caps(const struct device *dev)
{... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>onst base = dwc2_get_base(dev);
mem_addr_t ggpio_reg = (mem_addr_t)&base->ggpio;
sys_set_bits(ggpio_reg, USB_DWC2_GGPIO_STM32_PWRDWN | USB_DWC2_GGPIO_STM32_VBDEN);
return 0;
}
static inline int stm32f4_fsotg_disable_phy(const struct device *dev)
{
struct usb_dwc2_reg *const base = dwc2_get_base(dev... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Synaptics, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_DRIVERS_USB_UDC_DWC2_SYNA_SR100_U<|fim_suffix|> return 0;
}
#define QUIRK_SYNA_SR100_USB_DEFINE(n) \
static const struct syna_sr100_usb_clk syna_sr100_usb_clk_##n = { \
.dev = DEVICE_DT_GET(DT_I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 ITE Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "udc_common.h"
#include <soc.h>
#include <soc_dt.h>
#include <zephyr/pm/policy.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/interrupt_controller/... | fim | zephyrproject-rtos/zephyr | c |
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