text stringlengths 14 100k | source stringclasses 1
value | repo stringclasses 810
values | language stringclasses 13
values |
|---|---|---|---|
<|fim_suffix|> * @param pin TGPIO pin
* @param start_time start_time of first pulse in hw cycles
* @param repeat_interval repeat interval between two pulses in hw cycles
* @param periodic_enable enables periodic mode if 'true' is passed.
*
* @return 0 if successful, negative errno code on failure.
*/
__syscall in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DE, 2,\
priority)
#define ARM_TIMER_HYP_PRIO DT_IRQ_BY_IDX(ARM_TIMER_NODE, 3,\
priority)
#define ARM_TIMER_SECURE_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 0, flags)
#define ARM_TIMER_NON_SECURE_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_NODE, 1, flags)
#define ARM_TIMER_VIRTUAL_FLAGS DT_IRQ_BY_IDX(ARM_TIMER_N... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>SS, 0, CONFIG)
#define IFX_TCPWM_PWM_PWMDeadTime(ADDRESS, DEADTIME) \
Cy_TCPWM_PWM_PWMDeadTime((TCPWM_Type *)ADDRESS, 0, DEADTIME)
#define IFX_TCPWM_PWM_PWMDeadTimeBuff(ADDRESS, DEADTIME) \
Cy_TCPWM_PWM_PWMDeadTimeBu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_TIMER_NRF_GRTC_TIMER_H
#define ZEPHYR_INCLUDE_DRIVERS_TIMER_NRF_GRTC_TIMER_H
#ifdef __cplusplus
extern "C" {
#endif
#include <zephyr/sys_clock.h>
/** @brief GRTC timer compare... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> chan Channel ID between 1 and @kconfig{CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT}.
*
* @param target_time Absolute target time in ticks.
*
* @param handler User function called in the context of the RTC interrupt.
*
* @param user_data Data passed to the handler.
*
* @retval 0 if the compare channel wa... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>* event which the system could ignore and go back to sleep.
*
* @retval true if the PM subsystem should ignore wakeup events and go back
* to sleep.
* false if the timer wakeup event is as expected
*/
bool z_nxp_os_timer_ignore_timer_wakeup(void);
#ifdef __cplusplus
}
#endif
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2015 Wind River Systems, Inc.
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Timer driver API
*
* Declare API implemented by system timer driver and used by kernel components.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_SYSTEM_TI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> time from z_sys_clock_lpm_exit().
*
* @note This is an internal kernel/platform interface. Application code must
* not call it.
*
* @param max_lpm_time_us Maximum time allowed in low-power state, in microseconds.
*/
void z_sys_clock_lpm_enter(uint64_t max_lpm_time_us);
/**
* @brief Report elapsed... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>treated as error.
*/
static inline int uaol_stop(const struct device *dev, int stream)
{
return DEVICE_API_GET(uaol, dev)->stop(dev, stream);
}
/**
* @brief Program an endpoint table entry for UAOL individual stream.
*
* @param dev UAOL device instance.
* @param stream UAOL stream index.
* @param ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> is invoked when the USB host changes the baud rate.
*
* @note This function is available only when
* CONFIG_CDC_ACM_DTE_RATE_CALLBACK_SUPPORT is enabled.
*
* @param dev CDC ACM device structure.
* @param callback Event handler.
*
* @return 0 on success.
*/
__deprecated int cdc_acm_dte_r... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022 The ChromiumOS Authors.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_UART_SERIAL_TEST_H_
#define ZEPHYR_INCLUDE_DRIVERS_UART_SERIAL_TEST_H_
#include <errno.h>
#include <zephyr/device.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>-Identifier: Apache-2.0
*/
#include <zephyr/device.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Update the hardware port settings on a uart bridge
*
* If dev is part bridge_dev, then the dev uart configuration are applied to
* the other device in the uart bridge. This allows propagating ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018-2019 Nordic Semiconductor ASA
* Copyright (c) 2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Internal APIs for UART drivers
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_UART_UART_INTERNAL_H_
#define ZEPHYR_INCLUDE_DRIVERS_UART_UART_INTE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018-2019 Nordic Semiconductor ASA
* Copyright (c) 2015 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup uart_interface
* @brief Main header file for UART driver API.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_UART_H_
#define ZEPHYR_INCLUDE_DR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>** API provided for this device */
const struct uart_emul_device_api *api;
};
/** Definition of the emulator API */
struct uart_emul_device_api {
uart_emul_device_tx_data_ready_t tx_data_ready;
};
/**
* Register an emulated device on the controller
*
* @param dev Device that will use the emulator
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>buf, size_t *off);
/** @brief Register UART application.
*
* This function is used to register new UART application.
*
* @param buf Initial buffer for received data.
* @param len Size of buffer.
* @param cb Callback to be called on data reception.
*/
void uart_pipe_register(uint8_t *buf, size_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Backend APIs for the BC1.2 emulators.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_USB_EMUL_BC12_H_
#define ZEPHYR_INCLUDE_DRIVERS_USB_EMUL_BC12_H_
#include <zephyr/drivers/emul.h>
#include <zephyr/drivers/us... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021-2022 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief New USB device controller (UDC) driver API
*/
#ifndef ZEPHYR_INCLUDE_UDC_H
#define ZEPHYR_INCLUDE_UDC_H
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/drivers/usb/usb_b... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
static inline int uhc_sof_enable(const struct device *dev)
{
const struct uhc_api *api = dev->api;
int ret;
api->lock(dev);
ret = api->sof_enable(dev);
api->unlock(dev);
return ret;
}
/**
* @brief Suspend USB bus
*
* Disable SOF generator and emit UHC_EVT_SUSPENDED event when USB bus
* is su... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Public APIs for the USB BC1.2 battery charging detect drivers.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_USB_USB_BC12_H_
#define ZEPHYR_INCLUDE_DRIVERS_USB_USB_BC12_H_
#include <zephyr/device.h>
#ifdef __... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>IGN USB_PRIV_BUFALIGN
/** Buffer granularity required by the UDC driver */
#define USB_BUF_GRANULARITY USB_PRIV_BUFGRANULARITY
/** Round up to the granularity required by the UDC driver */
#define USB_BUF_ROUND_UP(size) ROUND_UP(size, USB_PRIV_BUFGRANULARITY)
/**
* @brief Define a UDC driver-complian... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* usb_dc.h - USB device controller driver interface */
/*
* Copyright (c) 2016 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief USB device controller APIs
*
* This file contains the USB device controller APIs. All device controller
* drivers should implement t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>dor-specific registers, it may override the TCPCI dump_std_reg
* function tp dump them and should also dump the standard registers using this array.
*
*/
extern const struct tcpci_reg_dump_map tcpci_std_regs[TCPCI_STD_REGS_SIZE];
/** Type-C Port Controller Interface Specification Revision 1.0 */
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022 The Chromium OS Authors
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief USB-C Power Delivery API used for USB-C drivers
*
* The information in this file was taken from the USB PD
* Specification Revision 3.0, Version 2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_USBC_U... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> not supported by the driver
*/
static inline int ppc_is_vbus_sink(const struct device *dev)
{
const struct usbc_ppc_driver_api *api = DEVICE_API_GET(usbc_ppc, dev);
if (api->is_vbus_sink == NULL) {
return -ENOSYS;
}
return api->is_vbus_sink(dev);
}
/**
* @brief Set the state of VBUS sinking
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022 The Chromium OS Authors
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief USB Type-C Cable and Connector API used for USB-C drivers
*
* The information in this file was taken from the USB Type-... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022 The Chromium OS Authors
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief USBC Type-C Port Controller device APIs
*
* This file contains the USB Type-C Port Controller device APIs.
* All Type-C Port Controller device drivers should implement the
* APIs described i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
{
return DEVICE_API_GET(usbc_vbus, dev)->measure(dev, meas);
}
/**
* @brief Controls a pin that discharges VBUS
*
* @param dev Runtime device structure
* @param enable Discharge VBUS when true
*
* @retval 0 on success
* @retval -EIO on failure
* @retval -ENOENT if discharge pin isn't... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>D_ARDUCAM_RESET (VIDEO_CID_PRIVATE_BASE + 1)
/** @brief Trigger the entry (1) or exit (0) of low-power mode */
#define VIDEO_CID_ARDUCAM_LOWPOWER (VIDEO_CID_PRIVATE_BASE + 2)
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_INCLUDE_DRIVERS_CAMERA_ARDUCAM_MEGA_H_ */
<|fim_prefix|>/**
* Copyright (c) 202... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_VIDEO_STM32_DCMIPP_H_
#define ZEPHYR_INCLUDE_VIDEO_STM32_DCMIPP_H_
/* Prototypes of ISP external handler weak functions */
void stm32_dcmipp_isp_vsync_update(DCMIPP_HandleTypeDef *hdcmipp, u... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Linaro Limited.
* Copyright (c) 2024 tinyVision.ai Inc.
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_VIDEO_CONTROLS_H_
#define ZEPHYR_INCLUDE_VIDEO_CONTROLS_H_
/**
* @file
* @ingroup video_controls
* @brief Main header file for vi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> integer is then packed in big endian format over two bytes:
*
* @code{.unparsed}
* 15.....8 7......0
* | RrrrrGgg gggBbbbb | ...
* @endcode
*/
#define VIDEO_PIX_FMT_RGB565X VIDEO_FOURCC('R', 'G', 'B', 'R')
/**
* 5 red bits [15:11], 6 green bits [10:5], 5 blue bits [4:0].
* This 16-bit integer ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Antmicro <www.antmicro.com>
* Copyright (c) 2025 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
*
* VIRTIO common definitions based on the specification.
*
* Based on Virtual I/O Device (VIRTIO) Version 1.3 specification:
* https://docs.oasis-open... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> the virtqueue
* @param bufs_size amount of buffers
* @param device_readable_count amount of bufferes readable by the device, the first
* device_readable_count buffers will be set as device readable
* @param cb callback to be invoked after device returns the buffer chain, can be NULL
* @param cb_opaq... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>specific config or NULL if its not present
*/
static inline void *virtio_get_device_specific_config(const struct device *dev)
{
return DEVICE_API_GET(virtio, dev)->get_device_specific_config(dev);
}
/**
* Returns feature bit offered by virtio device
*
* @param dev virtio device it operates on
* @pa... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>S_VIRTUALIZATION_IVSHMEM_H_ */
<|fim_prefix|>/*
* Copyright (c) 2020 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_VIRTUALIZATION_IVSHMEM_H_
#define ZEPHYR_INCLUDE_DRIVERS_VIRTUALIZATION_IVSHMEM_H_
/**
* @brief Interfaces for Inter-VM Shared Memory (ivs... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018 Roman Tataurov <diytronic@yandex.ru>
* Copyright (c) 2022 Thomas Stranger
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file zephyr/drivers/w1.h
* @ingroup w1_interface
* @brief Main header file for 1-Wire driver API.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_W1_H_
#define Z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Nordic Semiconductor ASA
* Copyright (c) 2015 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup watchdog_interface
* @brief Main header file for watchdog driver API.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_WATCHDOG_H_
#define ZEPHYR_INCLUDE_DR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>leep_status(void);
#endif /* CONFIG_NRF_WIFI_LOW_POWER */
#define QSPI_KEY_LEN_BYTES 16
/*! \brief Enable encryption
*
* \param key Pointer to the 128-bit key
* \return 0 on success, negative errno code on failure.
*/
int qspi_enable_encryption(uint8_t *key);
#endif /* __QSPI_IF_H__ */
<|fim_pref... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RET_RAM,
LMAC_SRC_RAM,
UMAC_ROM,
UMAC_RET_RAM,
UMAC_SRC_RAM,
NUM_MEM_BLOCKS
};
/* Keeping it high to avoid changing it often, but modify this value
* if rpu_7002_memmap is changed.
*/
#define NRF_WIFI_QSPI_SLAVE_MAX_LATENCY 4
extern char blk_name[][15];
extern uint32_t rpu_7002_memmap[][3];
int ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
*
* @addtogroup nrf70_off_raw_tx_api nRF70 Offloaded raw TX API
* @{
*
* @brief File containing API's for the Offloaded raw TX feature.
*/
#ifndef INCLUDE_ZEPHYR_DRIVERS_OFF_RAW_TX_API_H_
#define INCLUDE_ZEP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup wuc_interface
* @brief Main header file for WUC (Wakeup Controller) driver API.
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_WUC_H_
#define ZEPHYR_INCLUDE_DRIVERS_WUC_H_
/**
* @brief Wakeup Controller (WUC) Driver A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ief Q31 vector subtraction.
*
* @par Scaling and Overflow Behavior
* The function uses saturating arithmetic.
* Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.
*
* @param[in] src_a points to the first input vector
* @param[in] src_b points to the se... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>is the offset to be added
* @param[out] dst points to the output vector
* @param[in] block_size number of samples in the vector
*/
DSP_FUNC_SCOPE void zdsp_offset_f16(const float16_t *src, float16_t offset, float16_t *dst,
uint32_t block_size);
/**
* @ingroup math_dsp_basic_negate
* ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (c) 2022 Google LLC
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file zephyr/dsp/dsp.h
*
* @brief Public APIs for Digital Signal Processing (DSP) math.
*/
#ifndef ZEPHYR_INCLUDE_DSP_DSP_H_
#define ZEPHYR_INCLUDE_DSP_DSP_H_
#ifdef CONFIG_DSP_BACKEND_HAS_STATIC
#define DSP_FUNC_SCOP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (c) 2023 Google LLC
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DSP_PRINT_FORMAT_H_
#define ZEPHYR_INCLUDE_DSP_PRINT_FORMAT_H_
#include <inttypes.h>
#include <stdlib.h>
#include <zephyr/dsp/types.h>
/**
* @ingroup math_dsp
* @defgroup math_printing Helper macros for... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (c) 2022 Google LLC
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DSP_TYPES_H_
#define ZEPHYR_INCLUDE_DSP_TYPES_H_
#include <stdint.h>
/**
* @addtogroup math_dsp
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @typedef q7_t
* @brief 8-bit fractional data typ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (C) 2024 OWL Services LLC. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file zephyr/dsp/utils.h
*
* @brief Extra utility functions for DSP
*/
#ifndef INCLUDE_ZEPHYR_DSP_UTILS_H_
#define INCLUDE_ZEPHYR_DSP_UTILS_H_
#include <stdint.h>
#include <zephyr/sys... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>I_ACPI_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ACPI_ACPI_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ACPI_ACPI_H_
<|fim_middle|>#define ACPI_IRQ_DETECT 0xFFFFFFFU
#define ACPI_IRQ_FLAG_DETECT 0xFFFFFFFU
#en... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>efine AD4130_ADC_V_MV_M 29
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_AD4130_ADC_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Analog Devices, Inc.
*
*<|fim_middle|> SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_AD4130_ADC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_AD41... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EFIN1_PLUS 25
#define AD4170_ADC_REFIN1_MINUS 26
#define AD4170_ADC_REFIN2_PLUS 27
#define AD4170_ADC_REFIN2_MINUS 28
#define AD4170_ADC_REFOUT 29
/* AD4170 ADC Operating Mode */
#define AD4170_CONTINUOUS_MODE 0
#define AD4170_SINGLE_MODE 4
#define AD4170_STANDBY_MODE 5
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ine AD7124_ADC_DGND 19
#define AD7124_ADC_AVDD_AVSS_DIV6_PLUS 20
#define AD7124_ADC_AVDD_AVSS_DIV6_MINUS 21
#define AD7124_ADC_IOVDD_DGND_DIV6_PLUS 22
#define AD7124_ADC_IOVDD_DGND_DIV6_MINUS 23
#define AD7124_ADC_ALDO_AVSS_DIV6_PLUS 24
#define AD7124_ADC_ALDO_AVSS_DIV6_MINUS 25
#d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2021 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_A<|fim_suffix|>(1)
/** Acquisition time is expressed in nanoseconds. */
#define ADC_ACQ_TIME_NANOSECONDS (2)
/** Acquisition time is expressed in ADC ticks. */
#define ADC_ACQ_TIME_TICKS ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>00 12
#define ADS1X4S0X_CONFIG_DR_4000 13
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS1X4S0X_ADC_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 SILA Embedded Solutions GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS1X4S0X_ADC_H_
#<|fim_middle|>define ZEPHYR_IN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne DT_ADC_GPIO_PD0 0x09
#define DT_ADC_GPIO_PD1 0x0a
#define DT_ADC_VBAT 0x0f
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_B91_ADC_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Telink Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_B91_ADC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_DIV3 3
#define GD32_RCU_ADCCK_APB2_DIV4 4
#define GD32_RCU_ADCCK_AHB_DIV5 5
#define GD32_RCU_ADCCK_APB2_DIV6 6
#define GD32_RCU_ADCCK_AHB_DIV7 7
#define GD32_RCU_ADCCK_APB2_DIV8 8
#define GD32_RCU_ADCCK_AHB_DIV9 9
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_GD32F3X0_H_ */
<|fim_prefix|>/*
* Copyright ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree binding constants for Infineon AutAnalog SAR ADC.
*
* These consta... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apa<|fim_suffix|>T_BINDINGS_ADC_INFINEON_SAR_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_INFINEON_SAR_H_
/*
* SARMUX H... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* Copyright (c) 2026 Microchip Technology Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file mchp_pic32cm_jh_adc.h
* @brief ADC input selection definitions for PIC32CM_JH devices.
*
*/
#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_ADC_PIC32CM_JH_ADC_H_
#define INCLUDE_ZEPHYR_DT_BINDINGS_ADC_PIC32... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* Copyright (c) 2026 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file mchp_pic32cx_sg_adc.h
* @brief ADC input selection definitions for PIC32CX_SG devices.
*
*/
#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_ADC_PIC32CX_SG_ADC_H_
#define INCLUDE_ZEPHYR_DT_BINDINGS_ADC_PI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> MCHP_ADC_REF_AREFA 0x04 /**< External reference A */
#define MCHP_ADC_REF_AREFB 0x05 /**< External reference B */
#define MCHP_ADC_REF_AREFC 0x06 /**< External reference C (ADC1 only) */
#endif /* INCLUDE_ZEPHYR_DT_BINDINGS_ADC_SAM_D5X_E5X_ADC_H_ */
<|fim_prefix|>/**
* Copyright (c) 2025-2026 Mic... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright 2024 Syslinbit SCOP SAS
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCP356XR_ADC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCP356XR_ADC_H_
#include <zephyr/dt-bindings/adc<|fim_suffix|>R_INPUT_AGND (8)
#define MCP356XR_INPUT_CH7 (7)
#define MCP356... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>YCLE (0x1)
#define MCUX_ADC16_ACQUISITION_TIME_24CYCLE (0x0)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCUX_ADC16_H_ */
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCUX_ADC16_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCUX_ADC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright 2023,2025 NXP
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCUX_LPADC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_MCUX_LPADC_H_
#define MCUX_LPADC_CH0A (0x0)
#define MCUX_LPADC_CH0B (0x20)
#define MCUX_LPADC_CH1A (0x1)
#define MCUX_LPADC_CH1B (0x21)
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2022 Nordic Semiconductor ASA
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_ADC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_ADC_H_
#include <zeph<|fim_suffix|>_INCLUDE_DT_BINDINGS_ADC_NRF_ADC_H_ */
<|fim_middle|>yr/dt-bindings/dt-util.h>
... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Nordic Semiconductor ASA
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_H_
#define NRF_SAADC_AIN0 0
#define NRF_SAADC_AIN1 1
#define NRF_SAADC_AIN2 2
#define NRF_SAADC_AIN3 3
#define NRF_SAADC_... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-License-Identifier: Apache-2.0
* Copyright 2022 NXP
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NXP_GAU_ADC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NXP_GAU_ADC_H_
#include <zephyr/dt-bindings/adc/adc.h>
/* Channel Sources */
#define GAU_ADC_CH0 0
#define GAU_ADC_CH1 1
#define GAU_ADC_CH2 2
#define GAU_A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>define IADC_INPUT_PD15 0xbf
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_ADC_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* This file was generated by the script gen_adc.py in the hal_silabs module.
* Do not manually edit.
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#define SIWX91X_ADC_INPUT_HP26 16
#define SIWX91X_ADC_INPUT_HP28 17
#define SIWX91X_ADC_INPUT_HP30 18
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_SIWX91X_ADC_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#ifndef... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_19 19
#define SMARTBOND_GPADC_TEMP 20
/* Values for DT zephyr,input-positive or input-negative */
#define SMARTBOND_SDADC_P1_09 0
#define SMARTBOND_SDADC_P0_25 1
#define SMARTBOND_SDADC_P0_08 2
#define SMARTBOND_SDADC_P0_09 3
#define SMARTBOND_SDADC_P1_14 4
#define SMARTBOND_SDADC_P1_20 5
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 Embeint Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Main header file for battery-related constants to be used in devicetree.
* @ingroup devicetree-battery
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_BATTERY_BATTERY_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_BATTE... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023-2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ADI_MAX32_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ADI_MAX32_CLOCK_H_
/** Peripheral clock register */
#define ADI_MAX32_CLOCK_BUS0 0
#define ADI_MAX32_CLOCK_BUS1 1
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright Alif Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_BALLETTO_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_BALLETTO_CLOCKS_H_
/**
* @file
* @brief Clock IDs for Alif Balletto SoC family
*
* Defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Alif Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_CLOCKS_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ALIF_CLOCKS_COMMON_H_
/**
* @file
* @brief Common clock definitions for Alif Semiconductor SoC families
*
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RENT_CLK_SYST_PCLK)
/** UART6 clock sourced from system PCLK */
#define ALIF_UART6_SYST_PCLK \
ALIF_CLK_CFG(CLKCTL_PER_SLV, UART_CTRL, 6U, 1U, 1U, 1U, 14U, ALIF_PARENT_CLK_SYST_PCLK)
/** UART7 clock sourced from system PCLK */
#define ALIF_UART7_SYST_PCLK \
ALIF_CLK_CFG(CLKCTL_PER_SLV, UAR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lock mapping to GTIMER peripheral.
*/
#define AMEBA_PWM_PERIPHS AMEBA_REMAP_PERIPH(AMEBA_PWM0_CLK, GTIMER)
/**
* @brief SPI clock peripheral mappings.
*/
#define AMEBA_SPI_PERIPHS \
AMEBA_NUMERICAL_PERIPH(SPI, 0) /* AMEBA_SPI0_CLK */ ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AMEBADPLUS_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AMEBADPLUS_CLOCK_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @file
* @brief Realtek Amebadplus c... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>peripheral mapping.
*/
#define AMEBA_LOGUART_PERIPHS AMEBA_SINGLE_PERIPH(LOGUART) /* AMEBA_LOGUART_CLK */
/**
* @brief DMAC clock peripheral mapping.
*/
#define AMEBA_DMAC_PERIPHS AMEBA_SINGLE_PERIPH(DMAC) /* AMEBA_DMAC_CLK */
/**
* @brief SDH clock peripheral mapping.
*/
#define AMEBA_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AST10X0_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Aspeed Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AST10X0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_AST10X0_H_
#define ASPEED_CLK_GRP_0_OFFSET (0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>GCK 3
#define PMC_TYPE_PROGRAMMABLE 4
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ATMEL_SAM_PMC_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com
*
* SPDX-License-Identifier: Apache-2.0
*/
<|fim_middle|>#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ATMEL_SAM_PMC_H_
#de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space)
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL60X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL60X_CLOCK_H_
#include "bflb_clock_common.h"
/**
* @file
* Performance on BL60x is a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EQ_OC1 (DT_FREQ_M(480))
/** Overclocked PLL example 2, increased voltages (1.25v) must be used */
#define BL61X_TOP_FREQ_OC2 (DT_FREQ_M(640))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL61X_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025-2026 MASSDRIVER EI (massdriver.space)
*
* SPDX-License-... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL70X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL70X_CLOCK_H_
#include "bflb_clock_common.h"
/** Root Clock */
#define BL70X_CLKID_CLK_ROOT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) The Zephyr Project Contributors
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file bflb_bl70xl_clock.h
* @brief Clock IDs for the BL70XL SoC series
*/
#ifnde<|fim_suffix|>k, the standard root frequency of the DLL is 128MHz */
#define BL70XL_CLKID_CLK_DLL BFLB_CLKID_CLK_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright The Zephyr Project Contributors
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL808_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_BFLB_BL808_CLOCK_H_
#include "bflb_clock_common.h"
/**
* @file
* BL808 clock IDs and PLL configuration co... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>BFLB_CLKID_CLK_ROOT 0
/** 32MHz RC Oscillator Clock */
#define BFLB_CLKID_CLK_RC32M 1
/** Crystal as clock */
#define BFLB_CLKID_CLK_CRYSTAL 2
/** Bus Clock */
#define BFLB_CLKID_CLK_BCLK 3
/** F32K Clock */
#define BFLB_CLKID_CLK_F32K 4
/** XTAL32K Clock */
#define BFLB_CLKID_CLK_XTAL32K 5
/** RC32K Cloc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>efine CH32V00X_CLOCK_TIM3 CH32V00X_CLOCK_CONFIG(PB1, 2)
#define CH32V00X_CLOCK_WWDG CH32V00X_CLOCK_CONFIG(PB1, 11)
#define CH32V00X_CLOCK_I2C1 CH32V00X_CLOCK_CONFIG(PB1, 21)
#define CH32V00X_CLOCK_PWR CH32V00X_CLOCK_CONFIG(PB1, 28)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_CH32V00X_CLOCKS_H_ */
<|fim_p... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>H32V20X_V30X_CLOCK_USART2 CH32V20X_V30X_CLOCK_CONFIG(APB1, 17)
#define CH32V20X_V30X_CLOCK_USART3 CH32V20X_V30X_CLOCK_CONFIG(APB1, 18)
#define CH32V20X_V30X_CLOCK_USART4 CH32V20X_V30X_CLOCK_CONFIG(APB1, 19)
#define CH32V20X_V30X_CLOCK_USART5 CH32V20X_V30X_CLOCK_CONFIG(APB1, 20)
#define CH32V20X_V30X_CLOCK... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>2 0x05
#define EM32_CLK_FREQ_IRCHIGH64 0x11
#define EM32_CLK_FREQ_IRCHIGH80 0x12
#define EM32_CLK_FREQ_IRCHIGH96 0x13
#define EM32_CLK_FREQ_IRCHIGH112 0x14
#define EM32_CLK_FREQ_IRCHIGH128 0x15
#define EM32_CLK_FREQ_IRCHIGH96Q 0x16
/* AHB PreScaler */
#define EM32_AHB_CLK_DIV1 0x00
#define EM32_AH... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne ESP32_WIFI_MODULE 10 /**< Wi-Fi module */
#define ESP32_BT_MODULE 11 /**< Bluetooth module */
#define ESP32_WIFI_BT_COMMON_MODULE 12 /**< Wi-Fi/BT common module */
#define ESP32_BT_BASEBAND_MODULE 13 /**< BT baseband module */
#define ESP32_PHY_CALIBRATION_MODULE 14 /**< PH... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_
/* Support<|fim_suffix|>**< I2C0 module */
#define ESP32_TIMG1_MODULE 104 /**< Timer... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>/
#define ESP32_I2C0_MODULE 103 /**< I2C0 module */
#define ESP32_I2S1_MODULE 104 /**< I2S1 module */
#define ESP32_RMT_MODULE 105 /**< RMT module */
#define ESP32_SPI_MODULE 106 /**< SPI1 module */
#define ESP32_SPI2_MODULE 107 /**< SPI2 module */
#define ESP32_TWAI_M... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0 /**< Timer group 0 module */
#define ESP32_TIMG1_MODULE 1 /**< Timer group 1 module */
#define ESP32_UHCI0_MODULE 2 /**< UHCI0 module */
#define ESP32_SYSTIMER_MODULE 3 /**< System timer module */
/* Peripherals clock managed by the modem_clock driver must be... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU_CLK_SRC_PLL 1U
#d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32H2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32H2_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Clock module identifiers for Espressif ESP32-P4
*
* Defines clock source and peripheral module IDs for use in
* devicetree clock bindings.
*/
#ifndef ZEPHYR_INCLUDE_DT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S2_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU_CLK_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32S3_H_
/* Supported CPU clock Sources */
#define ESP32_CPU_CLK_SRC_XTAL 0U
#define ESP32_CPU_CLK_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025, FocalTech Systems CO.,Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_FOCALTECH_FT9001_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_FOCALTECH_FT9001_CLOCKS_H_
/**
* @file
* @brief Clock identifiers for FocalTech FT9001
* @ingr... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_COMMON_H_
/**
* Encode RCU register offset and configuration bit.
*
* - 0..5: bit number
* - 6..14: offset
* - 15: ... | fim | zephyrproject-rtos/zephyr | c |
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