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<|fim_prefix|>/*
* Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32A50X_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E10X_CLO<|fim_suffix|>2_CLOCK_CONFIG(APB1EN, 20U)
#define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
#define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1E... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 BrainCo.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32L23X_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32L23X_CLOCKS_H_
#include "gd32-clocks-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHB1EN_OFFSET ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ONFIG(AHBEN, 1U)
#define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
#define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
#define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
#define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
#define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>filiate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#if defined(CONFIG_SOC_SERIES_PSE84)
#include "ifx_clock_source_pse8xx.h"
#elif defined(CONFIG_SOC_SERIES_PSC3)
#include "ifx_clock_source_psc3xx.h"
#elif defined(CONFIG_SOC_FAMILY_INFINEON_PSOC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>iders */
#define IFX_RSC_ADC 0 /*!< Analog to digital converter */
#define IFX_RSC_ADCMIC 1 /*!< Analog to digital converter with Analog Mic support */
#define IFX_RSC_BLESS 2 /*!< Bluetooth communications block */
#define IFX_RSC_CAN 3 /*!< CAN communication block */
#define IFX_RSC_CLKPAT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> */
#define IFX_CAT1_CLKPATH_IN_ALTLF 0x112
/**< Select the PILO (19) as the output of the DSI mux and path mux. \
* Make sure the PILO clock sources in available on used device. \
*/
#define IFX_CAT1_CLKPATH_IN_PILO 0x113
/**< Select the ILO1 (20) as the output of... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lect the ECO as the output of the path mux */
#define IFX_CAT1_CLKPATH_IN_ECO 2
/* Select the IMO as the output of the path mux */
#define IFX_CAT1_CLKPATH_IN_IMO 3
/* Select the ALTHF0 as the output of the path mux */
#define IFX_CAT1_CLKPATH_IN_ALTHF0 4
/* Select the ALTHF1 as the output of the path ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef IFX_CLOCK_SOURCE_PSOC4XX_H_
#define IFX_CLOCK_SOURCE_PSOC4XX_H_
/*
* Note : use IFX_PATH_PSO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|><|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_
/* IMPORTANT: the indexes used by these ma<|fim_middle|>cros need to
* match the indexes in the PCC dr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_SRC + 107)
#define IMX943_CLK_LPUART6 (IMX943_CCM_NUM_CLK_SRC + 108)
#define IMX943_CLK_LPUART7 (IMX943_CCM_NUM_CLK_SRC + 109)
#define IMX943_CLK_LPUART8 (IMX943_CCM_NUM_CLK_SRC + 110)
#define IMX943_CLK_LPUART9 (IMX943_CCM_NUM_CLK_SRC + 111)
#define IMX943_CLK_SAI2 ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>k */
#define IMX952_CLK_BUSNETCMIX (IMX952_CCM_NUM_CLK_SRC + 56)
/** Ethernet clock */
#define IMX952_CLK_ENET (IMX952_CCM_NUM_CLK_SRC + 57)
/** Ethernet PHY test 200MHz clock */
#define IMX952_CLK_ENETPHYTEST200M (IMX952_CCM_NUM_CLK_SRC + 58)
/** Ethernet PHY test 500MHz clock */
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82)
#define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83)
#define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84)
#define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85)
#define IMX95_CLK_I3C2 (IMX95_CCM_NUM_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2017-2022,2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_
/*
* Define 16 bits clock ID: 0xXXXX
* The highest 8 bits is Peripheral ID
* The lowest 8 bits is Instance ID
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0x400UL
#define IMX_CCM_LPI2C0102_CLK 0x400UL
#define IMX_CCM_LPI2C1_CLK 0x400UL
#define IMX_CCM_LPI2C2_CLK 0x401UL
#define IMX_CCM_LPI2C0304_CLK 0x401UL
#define IMX_CCM_LPI2C3_CLK 0x402UL
#define IMX_CCM_LPI2C4_CLK 0x403UL
#define ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (C) 2021, Intel Corporation
*
*<|fim_suffix|>MMC 3
#define INTEL_SOCFPGA_CLOCK_TIMER 4
#define INTEL_SOCFPGA_CLOCK_QSPI 5
#define INTEL_SOCFPGA_CLOCK_I2C 6
#define INTEL_SOCFPGA_CLOCK_I3C 7
#endif /* ZEPHYR_INCLUD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IT51XXX_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IT51XXX_CLOCK_H_
/* Clock control */
#define IT51XXX_ECPM_CGCTRL2R_OFF 0x02
#define IT51XXX_ECPM_CGCTRL3R_OFF 0x05
#define IT51XXX_ECPM_CGCTRL4R_OFF 0x09
/* Clock PLL frequency */
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_MCG_H_
#define ZEPHYR_INCLUDE_DT_BI<|fim_suffix|>MCG_H_ */
<|fim_middle|>NDINGS_CLOCK_KINETIS_MCG_H_
#define KINETIS_MCG_FIXED_FREQ_CLK 0
#define KINETIS_MCG_OU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_PCC_H_
/* NXP Kinetis Peripheral Clock Controller IP sources */
#define KINETIS_PCC_SRC_NONE_OR_EXT 0 /*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 4U
#define KINETIS_SCG_SIRC_CLK 5U
#define KINETIS_SCG_FIRC_CLK 6U
#define KINETIS_SCG_SPLL_CLK 7U
#define KINETIS_SCG_SOSC_ASYNC_DIV1_CLK 8U
#define KINETIS_SCG_SOSC_ASYNC_DIV2_CLK 9U
#define KINETIS_SCG_SIRC_ASYNC_DIV1_CLK 10U
#define KINETIS_SCG_SIRC_AS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017, 2025-2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SIM_H_
#define KINETIS_SIM_CORESYS_CLK 0
#define KINETIS_SIM_PLATFORM_CLK 1
#define KINETIS_SIM_BUS_CLK 2
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Seagate Technology LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_LPC11U6X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_LPC11U6X_CLOCK<|fim_suffix|>e LPC11U6X_CLOCK_I2C0 0
#define LPC11U6X_CLOCK_I2C1 1
#define LPC11U6X_CLOCK... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OCK_MCHP_MCLKPERIPH_ID_AHB_DIVAS MCHP_CLOCK_DERIVE_ID(9, 0, 12, 0x3f, 11)
#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_APBD MCHP_CLOCK_DERIVE_ID(9, 0, 13, 0x3f, 12)
#define CLOCK_MCHP_MCLKPERIPH_ID_AHB_ICM MCHP_CLOCK_DERIVE_ID(9, 0, 14, 0x3f, 13)
#define CLOCK_MCHP_MCLKPERIPH_ID_APBA_PAC MC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> \
MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3f, 0x3f, 9, 9)
/** @brief GCLK peripheral clock ID for TC2 (PCHCTRL10). */
#define CLOCK_MCHP_GCLKPERIPH_ID_TC2 \
MCHP_CLOCK_DERIVE_ID(SUBSYS_TYPE_GCLKPERIPH, 0x3... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CLKPERIPH_ID_DSU_AHB MCHP_CLOCK_DERIVE_ID(9, 0, 0, 0x3f, 0)
/** @brief MCLK Peripheral ID: DSU (APB). */
#define CLOCK_MCHP_MCLKPERIPH_ID_DSU_APB MCHP_CLOCK_DERIVE_ID(9, 0, 1, 0x3f, 1)
/** @brief MCLK Peripheral ID: FCW (AHB). */
#define CLOCK_MCHP_MCLKPERIPH_ID_FCW_AHB MCHP_CLOCK_DERIVE_ID... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OCK_MCHP_SAM_D5X_E5X_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file mchp_sam_d5x_e5x_clock.h
* @brief List clock subsystem IDs for sam_d5x_e5x family.
*
* Clock subsystem IDs. To be used in devicetree nodes, and a... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCHP_XEC_H_
/* PLL 32KHz clock source VTR rail ON. */
#<|fim_suffix|>ition */
#define MCHP_XEC_SCR_ENCODE(idx, bi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2020-2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_
/* Note- clock identifiers in this file must be unique,
* as the driver uses them in a switch case
*/
#de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MICROCHIP_SAM_PMC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CL<|fim_suffix|>12)
#define PMC_MCK3 (PMC_MAIN + 20)
#define PMC_MCK5 (PMC_MAIN + 21)
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PM0_CLOCK_MFCLK MSPM0_CLOCK(0x2, 0x4)
#define MSPM0_CLOCK_BUSCLK MSPM0_CLOCK(0x3, 0x8)
#define MSPM0_CLOCK_ULPCLK MSPM0_CLOCK(0x4, 0x8)
#define MSPM0_CLOCK_MCLK MSPM0_CLOCK(0x5, 0x8)
#define MSPM0_CLOCK_MFPCLK MSPM0_CLOCK(0x6, 0x0)
#define MSPM0_CLOCK_CANCLK MSPM0_CLOCK(0x7, 0x0)
#define MSPM0_CLOCK... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_
/* clock bus references */
#define NPCM_CLO<|fim_suffix|>2) + 0)
#define NPCM_CLOCK_PWM_B ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 1
#define NPCX_PWDWN_CTL2 2
#define NPCX_PWDWN_CTL3 3
#define NPCX_PWDWN_CTL4 4
#define NPCX_PWDWN_CTL5 5
#define NPCX_PWDWN_CTL6 6
#define NPCX_PWDWN_CTL7 7
#define NPCX_PWDWN_CTL8 8
#define NPCX_PWDWN_CTL9 9
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRF_AUXPLL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRF_AUXPLL_H_
#define NRF_AUXPLL_FREQ_DIV_MIN 0
#define NRF_AUXPLL_FREQ_DIV_AUDIO_44K1 15309
#define<|fim_s... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRFS_AUDIOPLL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NRFS_AUDIOPLL_H_
#define NRFS_AUDIOPLL_FREQ_MIN 10666707
#define NRFS_AUDIOPLL_FREQ_AUDIO_44K1 11289600
#define NRFS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0x40000000
#define NUMAKER_CLK_CLKSEL3_UART3SEL_LIRC 0x50000000
#define NUMAKER_CLK_CLKSEL3_UART2SEL_HXT 0x00000000
#define NUMAKER_CLK_CLKSEL3_UART2SEL_PLL 0x01000000
#define NUMAKER_CLK_CLKSEL3_UART2SEL_LXT 0x02000000
#define NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC 0x03000000
#define NUMAKER_CLK_CLKSEL3_UART... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NUMAKER_I2C0_MODULE 0x20000008
#define NUMAKER_I2C1_MODULE 0x20000009
#define NUMAKER_I2C2_MODULE 0x2000000A
#define NUMAKER_I2C3_MODULE 0x2000000B
#define NUMAKER_QSPI0_MODULE 0x2908000C
#define NUMAKER_SPI0_MODULE 0x2990000D
#define NUMAKER_SPI1_MODULE 0x29B0000E
#define NUMAKER_SPI2_MODULE 0x2DA0000F
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M333X_CLOCK_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M333X_CLOCK_H
#define NUMAKER_CLK_CLKSEL0_HCLKSEL_HXT 0x00000000
#define NUMAKER_CLK_CLKS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M335X_CLOCK_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M335X_CLOCK_H
/**
* @file
* @brief Clock source and divider for Nuvoton M335X
* @ingro... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M46X_CLOCK_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M46X_CLOCK_H
/* Beginning of M460 BSP clk_reg.h copy */
#define NUMAKER_CLK_AHBCLK0_PDMA0CKEN_Pos (1)
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M55M1X_CLOCK_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M55M1X_CLOCK_H
#define NUMAKER_CLK_SCLKSEL_SCLKSEL_HIRC 0x00000000
#define NUMAKER_CLK_S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/**
* @file
* @brief Clock module IDs for nuvoton m48x
* @ingroup clock_control_nuvoton_m48x
*/
/*
* Copyright (c) 2026 Fiona Behrens
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMICRO_M48X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMICRO_M48X_CL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_MC_CGM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_MC_CGM_H_
/* Define a set of macros related to NXP mc_cgm IP configuration parameter */
#define NXP_PLL_MAXIDOCHANGE DT_PROP(DT_NOD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>X_FRO_6M 2 /**< FRO 6 MHz clock (kCLOCK_IpSrcFro6M). */
#define MCXW_CLK_IP_MUX_FRO_192M_DIV \
3 /**< FRO 192 MHz divided clock (frequency depends on range). */
#define MCXW_CLK_IP_MUX_SOSC 4 /**< SOSC: RF oscillator clock (kCLOCK_Ip... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K146_CLOCK_H_
#define NXP_S32_LPO_128K_CLK 1U
#define NXP_S32_SIRC_CLK 2U
#define NXP_S32... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K148_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32K148_CLOCK_H_
#define NXP_S32_LPO_128K_CLK 1U
#define NXP_S32_SIRC_CLK 2U
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>U
#define NXP_S32_LPUART6_CLK 105U
#define NXP_S32_LPUART7_CLK 106U
#define NXP_S32_LPUART8_CLK 107U
#define NXP_S32_LPUART9_CLK 108U
#define NXP_S32_LPUART10_CLK 109U
#define NXP_S32_LPUART11... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32_S32K566_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32_S32K566_CLOCK_H_
#define NXP_S32_FIRC_CLK 0U
#define NXP_S32_FIRCDIV2_CLK ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 149U
#define NXP_S32_NANO_CLK 150U
#define NXP_S32_P0_CLKOUT_SRC_CLK 151U
#define NXP_S32_P0_CTU_PER_CLK 152U
#define NXP_S32_P0_DSPI_MSC_CLK 153U
#define NXP_S32_P0_EMIOS_LCU_CLK 154U
#define NXP_S32... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A7795_H_
#include "renesas_cpg_mssr.h"
/* r8a7795 CPG Core Clocks */
#define R8A7795_CLK_Z 0
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ine R8A779F0_CLK_ZB3D4 35
#define R8A779F0_CLK_SD0H 36
#define R8A779F0_CLK_SD0 37
#define R8A779F0_CLK_RPC 38
#define R8A779F0_CLK_RPCD2 39
#define R8A779F0_CLK_MSO 40
#define R8A779F0_CLK_POST 41
#define R8A779F0_CLK_POST2 42
#define R8A779F0_CLK_SASYNCRT 43
#define R8A779F0_CLK_SASYNCPERD1 44
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Renesas R-Car V4H Clock Pulse Generator source definition for Zephyr.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779G0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CL... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2026 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A78000_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A78000_H_
/**
* @file
* @brief Renesas R-Car Gen5 R8A78000 Clock Pulse Generator source definitions.
*/
/... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Renesas RA Clock Generator Circuit (CGC) definitions for Zephyr.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_CLOCK_H_
/**
* @name Ren... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021-<|fim_suffix|> CPG_MOD 1 /* Module Clock */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H_ */
<|fim_middle|>2022 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H_
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#define RZA2M_MODULE_SSIF0 28UL
#define RZA2M_MODULE_SSIF1 29UL
#define RZA2M_MODULE_SSIF2 30UL
#define RZA2M_MODULE_SSIF3 31UL
#define RZA2M_MODULE_I2C0 32UL
#define RZA2M_MODULE_I2C1 33UL
#define RZA2M_MODULE_I2C2 34UL
#define RZA2M_MODULE_I2C3 35UL
#define RZA2M_MODU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>hernet Clock */
#define RZ_CLOCK_TSUCLK 13UL /* TSU Clock */
#define RZ_CLOCK_ZTCLK 14UL /* JAUTH Clock */
#define RZ_CLOCK_P0CLK 15UL /* APB-BUS Clock */
#define RZ_CLOCK_P1CLK 16UL /* AXI-BUS Clock */
#define RZ_CLOCK_P2CLK 17UL /* P2CLK */
#define RZ_CLOCK_ATCLK 18UL /* ATCLK */
#define RZ_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_
/** RZ clock configuration values */
#define RZ_IP_MASK 0xFF000000UL
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZTN_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZTN_CLOCK_H_
/* RZ clock configuration values */
#define RZ_IP_MASK 0xFF0000UL
#define RZ_IP_SHIFT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZV_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZV_CLOCK_H_
/* RZ/V clock configuration values */
#define RZ_IP_MASK 0xFF000000UL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>TOOHIGH 0xFA6
#define RPI_PICO_CLOCK_COUNT 10
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_COMMON_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Andrei-Edward Popa
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_CLOCK_COMMON_H_
#define ZEPHYR_IN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_ADC 8
#define RPI_PICO_CLKID_CLK_RTC 9
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2040_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Andrei-Edward Popa
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2040_CLOCK_H_
#d<|fim_middle|>ef... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2350_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Andrew Featherstone
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2350_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RPI_PICO_RP2350_CLOCK... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RTL8752H_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RTL8752H_CLOCKS_H_
/**
* @file
* @brief Realtek RTL8752H Clock Controller Devicetree Bindings
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RTL87X2G_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RTL87X2G_CLOCKS_H_
/**
* @file
* @brief Realtek RTL87x2G Clock Controller Devicetree Bindings
*/
/**
* @br... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Realtek Semiconductor, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RTS5817_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RTS5817_CLOCK_H_
#define RTS_FP_CLK_SYS_PLL 0
#define RTS_FP_CLK_BUS 1
#define RTS_FP_CLK_SPI_CACH... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
* Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RTS5912_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RTS5912_CLOCK_H_
/* ===============================... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Renesas RX Clock Generator Circuit (CGC) definitions for Zephyr.
* This header provides macro constants for clock source selections
* and multipliers/dividers for Renesas RX SoC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#ifn<|fim_suffix|>CG_K4_SIRC_CLK 6U
#define SCG_K4_FIRC_CLK 7U
#define SCG_K4_RTCOSC_CLK 8U
#define SCG_K4_FLEXIO_CLK 9U
#define SCG_K4_EDMA_CLK 10U
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SCG_K4_H_ */
<|fim_middle|>def ZEP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>served
*
* @param offset RCC register offset to ENRx register
* @param bit Configuration bit
*/
#define SF32LB_CLOCK_CONFIG(offset, bit) \
((((offset) << SF32LB_CLOCK_OFFSET_POS) & SF32LB_CLOCK_OFFSET_MSK) | \
(((bit) << SF32LB_CLOCK_BIT_POS) & SF32LB_CLOCK_BIT_MSK))
#endif /* _INCLUDE_ZEPHYR_DT_B... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CONFIG(SF32LB52X_RCC_ENR1, 14U)
#define SF32LB52X_CLOCK_GPTIM1 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR1, 15U)
#define SF32LB52X_CLOCK_GPTIM2 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR1, 16U)
#define SF32LB52X_CLOCK_BTIM1 SF32LB_CLOCK_CONFIG(SF32LB52X_RCC_ENR1, 17U)
#define SF32LB52X_CLOCK_BTIM2 SF32LB_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>8
#define CLOCK_BRANCH_SYSTICKCLK 29
#define CLOCK_BRANCH_LESENSEHFCLK 30
#define CLOCK_BRANCH_VDAC0CLK 31
#define CLOCK_BRANCH_VDAC1CLK 32
#define CLOCK_BRANCH_USB0CLK 33
#define CLOCK_BRANCH_FLPLLREFCLK 34
#define CLOCK_BRANCH_PDM0CLK 35
#define CLOCK_BRANCH_INVALID 36
#define... | fim | zephyrproject-rtos/zephyr | c |
/* Copyright (c) 2024 Silicon Laboratories Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX91X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX91X_CLOCK_H_
#define SIWX91X_CLK_ULP_UART 0
#define SIWX91X_CLK_ULP_I2C 1
#define SIWX91X_CLK_ULP_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>YR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* This file was generated by the script gen_clock_control.py in the hal_silabs module.
* Do not manually edit.
*/
#ifndef ZEPHYR_INCLUDE_DT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* This file was generated by the script gen_cloc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9))
#define CLOCK_VDAC0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20))
#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13))
#define CLOCK_WDOG1 (FIELD_PREP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21))
#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4))
#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27))
#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PRE... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* This file was generated by the script gen_clock_control.py in the hal_silabs module.
* Do not manually edit.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG26_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SIL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* This file was generated by the script gen_clock_control.py in the hal_silabs module.
* Do not manually edit.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BIND... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>G_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5))
#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2))
#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2))
#define CLOCK_RFECA0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7))
#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2))
#define CLOCK_RFSENSE (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14))
#define CLOCK_RTCC (FIELD_PREP(CLOCK_REG_MASK, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_
/* clock bus references */
#define STM32_CLOCK_BUS_AHB1 0
#define STM32_CLOCK_BUS_AHB2 1
#define STM3... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_
/** System clock */
#define STM32_SRC_SYSCLK 0x001
/** Fixed clocks */
#define STM32_SRC_LSE 0x002
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>32_SRC_HSI48 (STM32_SRC_HSI + 1)
#define STM32_SRC_HSE (STM32_SRC_HSI48 + 1)
/** Peripheral bus clock */
#define STM32_SRC_PCLK (STM32_SRC_HSE + 1)
#define STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK + 1)
/** @brief RCC_CCIPR register offset */
#define CCIPR_REG 0x54
#define CCIPR2_REG 0x58
/** @brief RCC_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief DT bindings for STM32C5 clock system
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C5_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C5_CLOCK_H_
/** @cond INTERNAL_HIDDEN */
#inc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus gatting clocks */
#define STM32_CLOCK_BUS_AHB1 0x014
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (C) 2024, Joakim Andersson
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CL<|fim_suffix|>LL2CLK + 1)
/** CFGR1 devices */
#undef MCO1_SEL /* Need to redefine generic F1 MCO_SEL for connectivity... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F37X_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F37X_CLOCK_H_
#<|fim_suffix|>undef ADC_PRE_DIV_128
#undef ADC_PRE_DIV_256
/** @brief Device domain clocks se... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_
#include "stm32<|fim_suffix|>V_4 0x12
#define ADC_PRE_DIV_6 0x13
#define ADC_PRE_DIV_8 0x14
#define ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DT_CLOCK_SELECT((val), 23, 22, DCKCFGR2_REG)
#define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 27, DCKCFGR2_REG)
#define SDIO_SEL(val) STM32_DT_CLOCK_SELECT((val), 28, 28, DCKCFGR2_REG)
#define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 31, 30, DCKCFGR2_REG)
/* F4 generic I2S_SEL is not compat... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
#include "stm32f4_clock.h"
/** @brief RCC_DCKCFGR register offset */
#define DCKCFGR_REG 0x8C
/*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>val), 9, 8, BDCR_REG)
/* MCO prescaler : division factor */
#define MCO_PRE_DIV_1 0
#define MCO_PRE_DIV_2 4
#define MCO_PRE_DIV_3 5
#define MCO_PRE_DIV_4 6
#define MCO_PRE_DIV_5 7
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Linaro Limited
*
* S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>T_CLOCK_SELECT((val), 26, 26, DCKCFGR2_REG)
#define CK48M_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 27, DCKCFGR2_REG)
#define SDMMC1_SEL(val) STM32_DT_CLOCK_SELECT((val), 28, 28, DCKCFGR2_REG)
#define SDMMC2_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 29, DCKCFGR2_REG)
#define DSI_SEL(val) STM32_DT_CLOC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#define MCO_SEL_RTCCLK 10
#define MCO_SEL_RTCWAKEUP 11
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_B1X_C1X_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Andreas Schuster <andreas.schuster@schuam.de>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG)
#define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR2_REG)
#define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR2_REG)
/** BDCR devices */
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BDCR_REG)
/* MCO prescaler : division factor ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CLOCK_SELECT((val), 7, 6, CCIPR_REG)
#define USART5_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR_REG)
#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG)
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG)
#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 15... | fim | zephyrproject-rtos/zephyr | c |
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