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/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_
/** @cond INTERNAL_HIDDEN */
#include "stm32_common_clocks.h"
/** Domain clocks */
/* RM0481/0492, Table 47 Ker... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>K_SELECT((val), 5, 4, D1CCIPR_REG)
#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 8, 8, D1CCIPR_REG)
#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, D1CCIPR_REG)
#define CKPER_SEL(val) STM32_DT_CLOCK_SELECT((val), 29, 28, D1CCIPR_REG)
/* Device domain clocks selection helpers (RM0468.pdf... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_
#include "stm32_common_clocks.h"
/** Domain clocks */
/* RM0477 */
/** System clock */
/* d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>2_DT_CLOCK_SELECT((val), 1, 0, CCIPR_REG)
#define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 11, 10, CCIPR_REG)
#define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 13, 12, CCIPR_REG)
#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus gatting clocks */
#define STM32_CLOCK_BUS_AHB1 0x01c
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> Internal Multi Speed oscillator */
#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1)
/** Bus clock */
#define STM32_SRC_PCLK (STM32_SRC_MSI + 1)
#define STM32_SRC_TIMPCLK1 (STM32_SRC_PCLK + 1)
#define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1)
/** PLL clock outputs */
#define STM32_SRC_PLL_P (STM32_SRC_TIM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CLOCK_SELECT((val), 7, 5, CCIPR2_REG)
#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR2_REG)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4PLUS_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CIPR2_REG)
#define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, CCIPR2_REG)
#define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR2_REG)
#define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 21, 20, CCIPR2_REG)
/** BDCR devices */
#define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 9, 8, BD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_
#include "stm32_common_clocks.h"
/** System clock */
/* defined in stm32_common_clocks.h */
/*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (C) 2025 Savoir-faire Linux, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP2_CLOCK_H_
/** @cond INTERNAL_HIDDEN */
#include "stm32_common_clocks.h"
/* Undefine the common cloc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 2, 0, CCIPR4_REG)
#define I2C2_SEL(val) STM32_DT_CLOCK_SELECT((val), 6, 4, CCIPR4_REG)
#define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 10, 8, CCIPR4_REG)
#define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 12, CCIPR4_REG)
#define I3C1_SEL(val) STM32... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CT((val), 21, 20, CCIPR_REG)
#define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 23, 22, CCIPR_REG)
#define TIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 24, 24, CCIPR_REG)
#define TIM15_SEL(val) STM32_DT_CLOCK_SELECT((val), 25, 25, CCIPR_REG)
#define CLK48_SEL(val) STM32_DT_CLOCK_SELECT((val), 27, 26, ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>efine MCO_PRE_DIV_32 5
#define MCO_PRE_DIV_64 6
#define MCO_PRE_DIV_128 7
/* ADC/DAC prescaler division factor */
#define ADCDAC_PRE_DIV_1 0x0
#define ADCDAC_PRE_DIV_2 0x1
#define ADCDAC_PRE_DIV_4 0x8
#define ADCDAC_PRE_DIV_8 0x9
#define ADCDAC_PRE_DIV_16 0xA
#define ADCDAC_PRE_DIV_32 0xB
#define ADCDA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_SEL(val) STM32_DT_CLOCK_SELECT((val), 14, 14, CCIPR2_REG)
#define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 15, 15, CCIPR2_REG)
#define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 16, 16, CCIPR2_REG)
#define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 18, 18, CCIPR2_REG)
#define OCTOSPI_SEL(val) STM3... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_
/** Define system & low-speed clocks */
#include "stm32_common_clocks.h"
/** Other fixed clocks.
* - CLKSLOWM... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_
#include "stm32_common_clocks.h"
/** Bus clocks */
#define STM32_CLOCK_BUS_AHB1 0x048
#define STM32_CLOCK_BUS_AHB... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EL_HCLK5 10
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_
#incl... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>O_SEL_SYSCLKPRE 1
#define MCO_SEL_MSI 2
#define MCO_SEL_HSI16 3
#define MCO_SEL_HSE32 4
#define MCO_SEL_PLL1RCLK 5
#define MCO_SEL_LSI 6
#define MCO_SEL_LSE 8
#define MCO_SEL_PLL1PCLK 13
#define MCO_SEL_PLL1QCLK 14
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_ *... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>2_CORE_CLK_CTRL 0x64
/** Bit locations in GLOBAL_CLK_ENABLE1/2 registers */
/** @brief bit shift for clock gating */
#define CGL_REG 16
/** @brief bit shift for AXI clocks */
#define AXI_ID 8
/** Device domain clock selection */
/** @brief Camera clock */
#define SYNA_IMG_CAM_CLK 0
/** @brief GPIO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree binding constants for Infineon AutAnalog PTCOMP.
*
* These constan... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 ITE Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_COMPARATOR_IT51XXX_VCMP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_COMPARATOR_IT51XXX_VCMP_H_
/**
* @name it51xxx voltage comparator channel references
* @{
*/
#define VCMP_CHA<|fim_s... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> NRF_COMP_AIN_VDDH_DIV5 (NRF_COMP_AIN_VDD_SHIM_OFFSET + 4)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_COMP_H_ */
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2025 Nordic Semiconductor ASA
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_COMP_H_
#define ZEPHYR_INCLUDE_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* This file was generated by the script gen_acmp.py in the hal_silabs module.
* Do not manually edit.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_COMPARATOR_SILABS_ACMP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_COMPA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 M2I Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INC<|fim_suffix|>fine DACX0508_CHANNEL_GAIN_1 0x00
#define DACX0508_CHANNEL_GAIN_2 0x01
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DAC_DACX0508_H_ */
<|fim_middle|>LUDE_DT_BINDINGS_DAC_DACX0508_H_
#define ZE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree binding constants for Infineon AutAnalog CTDAC.
*
* These constant... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*
* This file was generated by the script gen_vdac.py in the hal_silabs module.
* Do not manually edit.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DAC_SILABS_VDAC_H_
#define ZEPHYR_INCLUDE_DT_BI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> * PDC = 0, PC = 0 => DISCONNECTED (0)
* PDC = 0, PC = 1 => GPIO INPUT (1)
* PDC = 1, PC = 0 => GPIO OUTPUT (2)
* PDC = 1, PC = 1 => ESAI (3)
*/
#define ESAI_PIN_DISCONNECTED 0
#define ESAI_PIN_GPIO_INPUT 1
#define ESAI_PIN_GPIO_OUTPUT 2
#define ESAI_PIN_ESAI 3
/* ESAI clock IDs */
#define ESAI_CLOCK... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2023-2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup display_interface
* @brief Devicetree pixel format identifiers for display panels.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DISPLAY_PANEL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DISPLAY_PANEL_H_
/**
* @defgroup display... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ief Source burst length: 4 transfers.
*/
#define AMEBA_DMA_SRC_BURST_FOUR AMEBA_DMA_SRC_BURST_SET(1)
/**
* @brief Source burst length: 8 transfers.
*/
#define AMEBA_DMA_SRC_BURST_EIGHT AMEBA_DMA_SRC_BURST_SET(2)
/**
* @brief Source burst length: 16 transfers.
*/
#define AMEBA_DMA_SRC_BURST_SIXTEEN ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>X 32
#define DMA_PERID_SSC_RX 33
#define DMA_PERID_PIOA_RX 34
#define DMA_PERID_AFEC0_RX 35
#define DMA_PERID_AFEC1_RX 36
#define DMA_PERID_AES_TX 37
#define DMA_PERID_AES_RX 38
#define DMA_PERID_PWM1_TX 39
#define DMA_PERID_TC0_RX 40
#define DMA_PERID_TC1_RX 41... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Paul Wedeck
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_
#define CH32V003_ADC1_DMA 0
#define CH32V003_SPI1_RX_DMA 1
#define CH32V003_SPI1_TX_DMA 2
#define CH32V003_USART1_RX_D... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>D_TRIG_MUX_UART2 0x3
#define DMA_SMARTBOND_TRIG_MUX_I2C 0x4
#define DMA_SMARTBOND_TRIG_MUX_I2C2 0x5
#define DMA_SMARTBOND_TRIG_MUX_USB 0x6
#define DMA_SMARTBOND_TRIG_MUX_UART3 0x7
#define DMA_SMARTBOND_TRIG_MUX_PCM 0x8
#define DMA_SMARTBOND_TRIG_MUX_SRC 0x9
#define DMA_SMARTBOND_TRIG_MUX_GPADC 0xC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>efine GD32_DMA_PRIORITY_VERY_HIGH GD32_DMA_CH_CFG_PRIORITY(3)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_GD32_DMA_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_GD3<|fim_middle|>2... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Andriy Gelman <andriy.gelman@gmail.com>
*
* SPDX-License-Identifier: <|fim_suffix|>BINDINGS_DMA_INFINEON_XMC4XXX_DMA_H_
#define XMC4XXX_DMA_REQUEST_SOURCE_POS 0
#define XMC4XXX_DMA_REQUEST_SOURCE_MASK 0xf
#define XMC4XXX_DMA_LINE_POS 4
#define XMC4XXX_DMA_LINE_MASK 0xf
#defi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32650_DMA_H_
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
#define MAX32_DMA_SLOT_SPI0_RX 0x01U
#define MAX32_DMA_S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32655_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32655_DMA_H_
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
#define MAX32_DMA_SLOT_SPI1_RX 0x01U
#define MAX32_DMA_SLOT_UAR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32657_DMA_H_
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
#defin<|fim_suffix|>_DMA_SLOT_SPI_TX 0x21U
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
#define MAX32_DMA_SLOT_SPI0_RX 0x01U
#define MAX32_DMA_SLOT_S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0x3EU
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_
#define MAX32_DMA... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32666_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32666_DMA_H_
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
#define MAX32_DMA_SLOT_SPI1_RX 0x01U
#define MAX32_DMA_SLOT_SPI2_RX 0x02U
#d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OT_CRC 0x2CU
#define MAX32_DMA_SLOT_UART2_TX 0x2EU
#define MAX32_DMA_SLOT_AES_TX 0x30U
#define MAX32_DMA_SLOT_UART3_TX 0x3CU
#define MAX32_DMA_SLOT_I2S_TX 0x3EU
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32670_DMA_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Analog Devices, Inc.
*
* SPDX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> MAX32_DMA_SLOT_I2C2_TX 0x2AU
#define MAX32_DMA_SLOT_CRC 0x2CU
#define MAX32_DMA_SLOT_UART2_TX 0x2EU
#define MAX32_DMA_SLOT_AES_TX 0x30U
#define MAX32_DMA_SLOT_UART3_TX 0x3CU
#define MAX32_DMA_SLOT_I2S_TX 0x3EU
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32672_DMA_H_ */
<|fim_prefix|>/*
* Copy... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32675_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32675_DMA_H<|fim_suffix|>0x04U
#define MAX32_DMA_SLOT_I2C0_RX 0x07U
#define MAX32_DMA_SLOT_I2C2_RX 0x0AU
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2<|fim_suffix|>DINGS_DMA_MAX32680_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32680_DMA_H_
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
#define MAX32_DMA_SLOT_SPI1_RX 0x01U
#define MAX32_DMA_SLOT_UART0_RX 0x04U
#define MAX32_DMA_SLOT_UART1_RX 0x05U
#define MAX32_DMA_SLOT_I2C0_RX 0x07U... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32690_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32690_DMA_H_
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
#define MAX32_DMA_SLOT_SPI0_RX 0x01U
#define MAX32_DMA_SLOT_SPI1_RX 0x02U... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0<|fim_suffix|>INDINGS_DMA_MAX78000_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78000_DMA_H_
#define MAX78_DMA_SLOT_MEMTOMEM 0x00U
#define MAX78_DMA_SLOT_SPI1_RX 0x01U
#define MAX78_DMA_SLOT_UART0_RX 0x04U
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>X78_DMA_SLOT_CRC 0x2CU
#define MAX78_DMA_SLOT_UART2_TX 0x2EU
#define MAX78_DMA_SLOT_SPI0_TX 0x2FU
#define MAX78_DMA_SLOT_AES_TX 0x30U
#define MAX78_DMA_SLOT_I2S_TX 0x3EU
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78002_DMA_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Analog Device<|fim_middle|... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_RENESAS_RZ_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_RENESAS_RZ_DMA_H_
/* mode: bit 0 (0: Normal, 1: Block) */
/* source data size: bit 1, 2, 3 (0b000 -> 0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_COMMON_H_
#define ZEPH<|fim_suffix|>E_DT_BINDINGS_RPI_PICO_DMA_COMMON_H_ */
<|fim_middle|>YR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_COMMON_H_
/*
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>A_DREQ_TO_SLOT(0x37)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_RP2040_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RPI_PICO_DMA_RP2040_H_
#define ZEPHYR_INCLUDE_DT_BINDING... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ine RPI_PICO_DMA_SLOT_PWM_WRAP6 RPI_PICO_DMA_DREQ_TO_SLOT(0x26)
#define RPI_PICO_DMA_SLOT_PWM_WRAP7 RPI_PICO_DMA_DREQ_TO_SLOT(0x27)
#define RPI_PICO_DMA_SLOT_PWM_WRAP8 RPI_PICO_DMA_DREQ_TO_SLOT(0x28)
#define RPI_PICO_DMA_SLOT_PWM_WRAP9 RPI_PICO_DMA_DREQ_TO_SLOT(0x29)
#define RPI_PICO_DMA_SLOT_PWM_WRAP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)
#define SF32LB_DMA_PL_MEDIUM (1UL << SF32LB_DMA_PL_POS)
#define SF32LB_DMA_PL_HIGH (2UL << SF32LB_DMA_PL_POS)
#define SF32LB_DMA_PL_VERY_HIGH (3UL << SF32LB_DMA_PL_POS)
#endif /* INCLUDE_ZEPHYR_DT_BINDINGS_DMA_SF32LB_DMA_CONFIG_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Core Devices LLC
* SP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>U
#define SF32LB52X_DMA_REQ_I2C3 24U
#define SF32LB52X_DMA_REQ_ATIM1_COM 25U
#define SF32LB52X_DMA_REQ_USART3_TX 26U
#define SF32LB52X_DMA_REQ_USART3_RX 27U
#define SF32LB52X_DMA_REQ_SPI1_TX 28U
#define SF32LB52X_DMA_REQ_SPI1_RX 29U
#define SF32LB52... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyrig<|fim_suffix|>icon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_SILABS_COMMON_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_SILABS_COMMON_DMA_H_
#define DMA_SRC_MASK 0x1F0000
#define DMA_SIG_MASK 0x7
#endif /* ZEPHYR_INCLUDE_DT_BIND... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG21_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_XG21_DMA_H_
#include <zephyr/dt-bindings/dt-util.h>
#include "common-dma.h"
/**
* Definition of Silabs LDMA request signal
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>C_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0))
#define DMA_REQSEL_TIMER3CC1 (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 1))
#define DMA_REQSEL_TIMER3CC2 (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 2))
#define DMA_REQSEL_TIMER3UFOF (FIELD_PREP(DMA_SRC_MASK, 1... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG23_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_XG23_DMA_H_
#include <zephyr/dt-bindings/dt-util.h>
#include "common-dma.h"
/**
* Definition of Silabs LDMA request signal
*/
#define DM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG24_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_XG24_DMA_H_
#include <<|fim_suffix|>)
#define DMA_REQSEL_TIMER1CC2 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ASK, 0))
#define DMA_REQSEL_TIMER3CC1 (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 1))
#define DMA_REQSEL_TIMER3CC2 (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 2))
#define DMA_REQSEL_TIMER3UFOF (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 3))
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG27_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_XG27_DMA_H_
#include <zephyr/dt-bindings/dt-util.h>
#include "common-dma.h"
/**
* Definition of Silabs LDMA request signal
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>QSEL_EUSART0TXFL (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 1))
#define DMA_REQSEL_EUSART1RXFL (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 0))
#define DMA_REQSEL_EUSART1TXFL (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 1))
#define DMA_REQSEL_EUSA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> ZEPHYR_INCLUDE_DT_BINDINGS_XG29_DMA_H_
<|fim_prefix|>/*
* Copyright (c) 2025 Silicon Laboratories Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG29_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_XG29_DMA_H_
#include <zephyr/dt-bindings/dt-util.h>
#include "common-dma... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DMA_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_STM32_DMA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_STM32_DMA_H_
/**
* @name custom DMA flags for channel configuration
* @{
*/
/** DMA cyclic mode ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DT_UTIL_H_
#define ZEPHYR_INCLUD<|fim_suffix|>clude <zephyr/dt-bindings/foo.h> form should be included. The
* <zephyr/dt-bindings/dt-util.h> wraps <zephyr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>GPSM3 3
#define NPCX_VWGPSM4 4
#define NPCX_VWGPSM5 5
#define NPCX_VWGPSM6 6
#define NPCX_VWGPSM7 7
#define NPCX_VWGPSM8 8
#define NPCX_VWGPSM9 9
#define NPCX_VWGPSM10 10
#define NPCX_VWGPSM11 11
#define NPCX_VWGPSM12 12
#define NPCX_VWGPSM13 13
#define NPCX_VWGPSM14 14
#define NPCX_VWGPSM15 15
#endif /*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DSA_TAG_PROTO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_DSA_TAG_PROTO_H_
/* No switch tag protocol supported */
#define <|fim_suffix|>AG_PROTO_H_ */
<|fim_middle|>DSA_TAG_PROTO_NOTAG 0
/* NXP NETC switch t... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023-2024 NXP
*
* SPDX-License-Identifier: Apache-<|fim_suffix|>
#define NXP_ENET_INVALID_MII_MODE 100
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_NXP_ENET_H_ */
<|fim_middle|>2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_NXP_ENET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nk speed values */
#define XLNX_GEM_LINK_SPEED_10MBIT 1
#define XLNX_GEM_LINK_SPEED_100MBIT 2
#define XLNX_GEM_LINK_SPEED_1GBIT 3
/* AMBA AHB burst length */
#define XLNX_GEM_AMBA_AHB_BURST_SINGLE 1
#define XLNX_GEM_AMBA_AHB_BURST_INCR4 4
#define XLNX_GEM_AMBA_AHB_BURST_INCR8 8
#define XLNX_GEM_AMBA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_NPCX_FIU_QSPI_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_NPCX_FIU_QSPI_H_
#include <zephyr/dt-bindings/dt-util.h>
/* Software controlled ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_OSPI_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_OSPI_H_
/**
* @name OSPI definition for the OctoSPI peripherals
* Note that the possible combination ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/<|fim_suffix|>
#define XSPI_DUAL_MODE 2
/* 4 Cmd Lines, 4 Address Lines and 4 Data Lines */
#define XSPI_QUAD_MODE 4
/* 8 Cmd Lines, 8 Address Lines and 8 Data Lines */
#define XS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023-2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ADI_MAX32_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ADI_MAX32_GPIO_H_
/**
* @brief MAX32-specific GPIO Flags
* @defgroup gpio_interface_max32 MAX32-specific GPI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PI_MOSI */
#define SDP_120_SPI_SEL_A_N SDP_120_IO(85) /* SPI_SEL_A_N */
/* SPORT - no driver yet */
#define SDP_120_SPI_SPORT_TSCLK SDP_120_IO(87) /* SPORT_TSCLK */
#define SDP_120_SPI_SPORT_DT0 SDP_120_IO(88) /* SPORT_DT0 */
#define SDP_120_SPI_SPORT_TFS SDP_120_IO(89) /* SPORT_TFS */
#define SD... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>f /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ANDESTECH_ATCGPIO100_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_<|fim_middle|>GPIO_ANDESTECH_ATCGPIO100_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ANDESTECH_ATCGP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ArduCam FFC 40-pin camera connector constants.
* @ingroup arducam-ffc-40pin
*/
#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_ARDUCAM_FFC_40PIN_CONNECTOR_H_
#define INCLUDE_ZEPHYR_DT_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Arduino Uno (R3) header pin constants
* @ingroup arduino-header-r3
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_HEADER_R3_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_HEADER_R3_H_
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ER_A8 32 /**< Analog pin 8 (A8) */
#define ARDUINO_MEGA_HEADER_A9 33 /**< Analog pin 9 (A9) */
#define ARDUINO_MEGA_HEADER_A10 34 /**< Analog pin 10 (A10) */
#define ARDUINO_MEGA_HEADER_A11 35 /**< Analog pin 11 (A11) */
#define ARDUINO_MEGA_HEADER_A12 36 /**< Analog pin 12 (A12) */
#define ARDUINO_MEGA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Arduino MKR header pin constants
* @ingroup arduino-mkr-header
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_MKR_HEADER_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_MKR_HEADER_H_
/*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DUINO_NANO_HEADER_A6 20 /**< Analog pin 6 (A6) */
#define ARDUINO_NANO_HEADER_A7 21 /**< Analog pin 7 (A7) */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_NANO_HEADER_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM_GPIO_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr <|fim_suffix|>IO b... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Vestas Wind Systems A/<|fim_suffix|>ifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM0_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ATMEL_SAM0_GPIO_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr specific extension of the st... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Elektronikutvecklingsbyrån EUB AB
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Pmod GPIO nexus signal index definitions
*
* Defines meant to be used in conjunction with the "digilent,pmod"
* GPIO nexus mapping.
*
* Example usage:
*
* @code{.dts}
* &sp... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 tinyVision.ai Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Arducam DVP 20-pin connector pin constants
* @ingroup dvp-20pin-connector
*/
#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_DVP_20PIN_CONNECTOR_H_
#define INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_DVP_20PIN_CO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 ENE Technology Inc.
<|fim_suffix|>e ENE_GPIO_DRIVING_DEFAULT (0U << ENE_GPIO_DRIVING_POS)
/** Set pin driving current at 16mA */
#define ENE_GPIO_DRIVING_16MA (1U << ENE_GPIO_DRIVING_POS)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ENE_KB106X_GPIO_H_ */
<|fim_middle|... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ENE_KB1200_GPIO_H_
#define ZEPHYR_IN<|fim_suffix|> down to 8 are reserved for SoC specific flags.
*/
/** @cond INTERNAL_HIDDEN */
#define KB1200_GPIO_VOLTAGE_POS 8
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Vestas Wind Systems A/S
* Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_
/**
* @nam<|fim_suff... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>w power mode.
*/
#define GPIO_INT_WAKEUP (1 << 6)
/* Note: Bits 15 downto 8 are reserved for SoC specific flags. */
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_GPIO_H_ */
<|fim_prefix|>/*
* Copyright (c) 2019 Piotr Mienkowski
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>XX_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_INFINEON_XMC4XXX_GPIO_H_
#define XMC4XXX_GPIO_DS_POS 9
#define XMC4XXX_GPIO_DS_MASK 0xf
/* GPIO driver will use XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE if DS is unset */
#define XMC4XXX_GPIO_DS_STRONG_SHARP_EDGE ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ITE_IT8XXX2_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ITE_IT8XXX2_GPIO_H_
/**
* @name GPIO pin voltage flags
*
* The voltage flags are a Zephyr specific extension of the stand... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>lags used in addition to standard Zephyr
* GPIO binding flags.
*/
#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_MICROCHIP_PORT_G1_GPIO_H_
#define INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_MICROCHIP_PORT_G1_GPIO_H_
/**
* @def MCHP_GPIO_DEBOUNCE
* @brief Enable hardware debouncing for a GPIO pin.
*
* Zephyr-specifi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>K (0x3U << SAM_GPIO_DRVSTR_POS)
#define SAM_GPIO_DRVSTR_DEFAULT (0U << SAM_GPIO_DRVSTR_POS)
#define SAM_GPIO_DRVSTR_LOW (1U << SAM_GPIO_DRVSTR_POS)
#define SAM_GPIO_DRVSTR_MED (2U << SAM_GPIO_DRVSTR_POS)
#define SAM_GPIO_DRVSTR_HI (3U << SAM_GPIO_DRVSTR_POS)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_MICROCHIP_XEC_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_MICROCHIP_XEC_GPIO_H_
/**
* @brief Microchip XEC GPIO bank and bit position convenience defines
*
* Mic... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Nordic Sem<|fim_suffix|>1=ON)
*
* @ingroup gpio_interface_ext
* @{
*/
/**
* @name nPM10xx GPIO drive strength flags
* @{
*/
/** @cond INTERNAL_HIDDEN */
/** Drive mode field mask */
#define NPM10XX_GPIO_DRIVE_MSK 0x0100U
/** @endcond */
/** Normal (2mA) drive */
#define NP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0x0200U
/** @endcond */
/** Normal drive */
#define NPM13XX_GPIO_DEBOUNCE_OFF (0U << 9U)
/** High drive */
#define NPM13XX_GPIO_DEBOUNCE_ON (1U << 9U)
/** @} */
/**
* @name nPM13xx GPIO watchdog reset flags
* @brief nPM13xx GPIO watchdog reset flags
* @{
*/
/** @cond INTERNAL_HIDDEN */
/** watch... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>d mask */
#define NPM2100_GPIO_DRIVE_MSK 0x0100U
/** @endcond */
/** Normal drive */
#define NPM2100_GPIO_DRIVE_NORMAL (0U << 8U)
/** High drive */
#define NPM2100_GPIO_DRIVE_HIGH (1U << 8U)
/** @} */
/**
* @name nPM2100 GPIO debounce flags
* @brief nPM2100 GPIO debounce flags
* @{
*/
/** @cond ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> (1U << 9U)
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM6001_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NRF_GPIO_H_
/**
* @brief nRF-specific GPIO Flags
* @defgroup gpio_interface_nrf nRF-specific GPIO Fla... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 SEAL AG
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NUMICRO_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NUMICRO_GPIO_H_
/**
* @brief Enable GPIO pin debounce.
*
* The debounce flag is a Zephyr specific extension of ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NPCX_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NUVOTON_NPCX_GPIO_H_
/**
* @name GPIO pin voltage flags
*
* The voltage flags are a Zephyr specific extension of the st... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>< NXP_IGPIO_PULL_STRENGTH_POS)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_IMX_IGPIO_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Feniex Industries Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_IMX_IGPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_G... | fim | zephyrproject-rtos/zephyr | c |
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