text stringlengths 14 100k | source stringclasses 1
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<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_PINCTRL_H_
#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h>
#include <zephyr/dt-bindings/pinc... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>1XX_GPIO0_PAD_CFG7 0x012c
#define SY1XX_RGMII0_PAD_CFG0 0x0130
#define SY1XX_RGMII0_PAD_CFG1 0x0134
#define SY1XX_RGMII0_PAD_CFG2 0x0138
#define SY1XX_RGMII0_PAD_CFG3 0x013c
#define SY1XX_CAN0_PAD_CFG0 0x0140
#define SY1XX_I2S0_PAD_CFG0 0x0144
#define SY1XX_I2S1_PAD_CFG0 0x0148
#define SY1XX_I2S2_PAD_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>SHIFT) | \
(((mode) & SRXXX_MODE_MASK) << SRXXX_MODE_SHIFT) | \
(((mask) & SRXXX_MASK_MASK) << SRXXX_MASK_SHIFT) | \
(((cfg) & SRXXX_CFG_MASK) << SRXXX_CFG_SHIFT))
/** Macros for pinmux selection */
/** @brief global */
#define SRXXX_GLOBAL_PINMUX(reg, bit, mode, cfg) SRXXX_PINMUX(0, reg, bit, m... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC32XX_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC32XX_PINCTRL_H_
/*
* The whole TI CC32XX pin configuration information is encoded in a 32-bit
* b... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Enphase Energy
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_K3_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_K3_PINCTRL_H_
#define PULLUDEN_SHIFT 16
#define PULLTYPESEL_SHIFT 17
#define RXACTIVE_SHIFT 18
#define <|fim_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Schlumberger
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_XMC4XXX_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_XMC4XXX_PINCTRL_H_
/* Bit Masks */
#define XMC4XXX_PORT_POS 0
#define XMC4XXX_PORT_MASK 0xf
#define ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Bjarki Arge Andreasen
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_ATMEL_SAM_SUPC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_ATMEL_SAM_SUPC_H_
#define SUPC_WAKEUP_SOURCE_FWUP 0
#define SUPC_WAKEUP_SOURCE_SM <|fim_suffix|>RCE_RTC 3
#en... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 16
#define IMX943_PD_NPU 17
#define IMX943_PD_WAKEUP 18
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX943_POWER_H_ */
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX943_POWER_H_
#define ZEPHYR_INCLUDE_DT_BIND... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright 2026 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Power domain definitions for NXP i.MX952 SoC
*
* This file defines power domain IDs for the i.MX952 system-on-chip.
* These definitions are based on MIMX9529 fsl_power.h from MCUXpress... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fine IMX95_PD_A55C2 7
#define IMX95_PD_A55C3 8
#define IMX95_PD_A55C4 9
#define IMX95_PD_A55C5 10
#define IMX95_PD_A55P 11
#define IMX95_PD_DDR 12
#define IMX95_PD_DISPLAY 13
#define IMX95_PD_GPU 14
#define IMX95_PD_HSIO_TOP 15
#define IMX95_PD_HSIO_WAON 16
#define IMX9... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX_SCU_RSRC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX_SCU_RSRC_H_
#define IMX_SC_R_A53 0U
#define IMX_SC_R_A53_0 1U
#define IMX_SC_R_A53_1 ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Setpoint definitions for IMX Set point controller. The SPC uses a series
* of set points to determine the clock speeds and states of cores, as well
* as which peripherals to gate clocks to. Higher values correspond to mo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>RESET_CODE_WATCHDOG 0x10
#define PMU_RESET_ITRC 0x20
#define PMU_RESET_RESETB 0x40
#define PMU_RESET_ALL 0x7F
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_PMU_H_ */
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NXP_RW_P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_RENESAS_PD_R8A78000_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_RENESAS_PD_R8A78000_H_
/**
* @file
* @brief Renesas R-Car Gen5 R8A78000 power domain definitions.
*/
/** @cond... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>t source is fixed/not configurable */
#define STM32_PWR_WKUP_PIN_NOT_MUXED STM32_PWR_WKUP_EVT_SRC_0
#define STM32_PWR_WKUP_EVT_SRC_0 BIT(0)
#define STM32_PWR_WKUP_EVT_SRC_1 BIT(1)
#define STM32_PWR_WKUP_EVT_SRC_2 BIT(2)
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_STM32_PWR_H_ */
<|fi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 CodeWrights GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief I/O cell definitions for STM32H5 devices
*/
#<|fim_suffix|>domain powered by VDD supply */
#define STM32_DT_IOCELL_VDDIO2 (1) /**< I/O domain powered by VDDIO2 supply */
/** @brief Return tru... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
<|fim_suffix|>NCLUDE_DT_BINDINGS_POWER_STM32H7RS_IOCELL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_STM32H7RS_IOCELL_H_
/**
* @name I/O power domains used to configure STM32 iocell device
* @{
*/
#define STM32_DT_IOCELL_VDDIO (0) /**< I/O domain powered by VDD supply */
#define STM32_DT_IOCELL_XS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>efine STM32_DT_IOCELL_VDDIO4 (2) /**< I/O domain powered by VDDIO4 supply */
#define STM32_DT_IOCELL_VDDIO5 (3) /**< I/O domain powered by VDDIO5 supply */
#define STM32_DT_IOCELL_VDD (4) /**< I/O domain powered by VDD supply */
/** @brief Return true if @a domain is valid I/O domain */
#define STM32_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
#define PWM_CHANNEL_7 7
/*
* Provides a type to hold PWM configuration flags.
*
* The upper 8 bits are reserved for SoC specific flags.
* Output open-drain flag [ 8 ]
*/
#define PWM_IT51XXX_OPEN_DRAIN BIT(8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT51XXX_H_ */
<|fim_prefix|>/*
* Copyrigh... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> [ 8 ]
*/
#define PWM_IT8XXX2_OPEN_DRAIN BIT(8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_PWM_H_ */
<|fim_prefix|>/*
* Copyright (c) 2021 ITE Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_PWM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2019 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_H_<|fim_suffix|>re convenient to use another scale.
* @{
*/
/** Specify PWM period in nanoseconds */
#define PWM_NSEC(x... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_TCPWM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyri<|fim_suffix|>_CHANNEL_3 3
#define RA_PWM_CHANNEL_4 4
#define RA_PWM_CHANNEL_5 5
#define RA_PWM_CHANNEL_6 6
#define RA_PWM_CHANNEL_7 7
#define RA_PWM_CHANNEL_8 8
#define RA_PWM_CHANNEL_9 9
#define RA_PWM_CHANNEL_10 10
#define RA_PWM_CHANNEL_11 11
#define RA_PWM_CHANNEL_12 12
#define RA_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RENESAS_RZ_PWM_H_
#define ZEPHYR_INCLUDE_DT<|fim_suffix|>IOCxA 0
#define RZ_PWM_MTIOCxB 1
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RENESAS_RZ_PWM_H_ */
<|fim_middle|>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>WM_RX_MTU_PWM_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_RX_MTU_PWM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_RX_MTU_PWM_H_
/* PWM SOURCE DIVIDER */
#define RX_MTU_PWM_SOURCE_DIV_1 0
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: A<|fim_suffix|>32_PWM_CAPTURE_PSC_POS)
/** PWM input capture prescaler is set to 8 */
#define STM32_PWM_CAPTURE_PSC_8 (3U << STM32_PWM_CAPTURE_PSC_POS)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_STM32_PWM_H_ */
<|fim_mid... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_NXP_S32_QSPI_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_NXP_S32_QSPI_H_
#include <zephyr/dt-bindings/<|fim_suffix|>1)
#define NXP_S32_QSPI_PRIVILEGE BIT(2)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_NXP_S32_Q... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2018, Diego Sueiro
* Copyright 2024 NXP
*
* SPDX-License-Identifie<|fim_suffix|>))
#define RDC_DT_VAL(nodelabel) DT_PROP(DT_NODELABEL(nodelabel), rdc)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RDC_IMX_RDC_H_ */
<|fim_middle|>r: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RDC_IMX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nordic Semiconductor ASA
* Copyright (c) 2026 Analog Devices Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup regulator_adp5360
* @brief Header file for ADP5360 Devicetree helpers.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_ADP5360_H_
#define Z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>INGS_REGULATOR_AXP192_H_
/**
* @defgroup regulator_axp192 AXP192 Devicetree helpers
* @brief X-Powers AXP192 PMIC regulator driver Devicetree helpers
* @ingroup devicetree-regulator
* @{
*/
/**
* @name AXP192 DCDC modes
* @{
*/
/** Automatic mode */
#define AXP192_DCDC_MODE_AUTO 0x00U
/** PWM mo... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> Vsrc */
#define IFX_AUTANALOG_PRB_TAP_8 8 /**< 0.5625 * Vsrc */
#define IFX_AUTANALOG_PRB_TAP_9 9 /**< 0.6250 * Vsrc */
#define IFX_AUTANALOG_PRB_TAP_10 10 /**< 0.6875 * Vsrc */
#define IFX_AUTANALOG_PRB_TAP_11 11 /**< 0.7500 * Vsrc */
#define IFX_AUTANALOG_PRB_TAP_12 12 /**< 0.8125 * Vsrc */
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_REGULATOR_MAX20335_H_
/**
* @defgroup regulator_max20335 MAX20335 Devicetree helpers
* @brief Maxim MAX20335 PMIC regulator driver Devicetree helpers
* @ingroup devicetree-regulator
* @{
*/
/**
* @name MAX20335 regulator modes
* @{
*/
/** LDO mode */
#define MAX20335_LDO_MODE 0
/** Load switch ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ode */
#define MSPM0_VREF_MODE_NORMAL 0
/** Sample and hold mode */
#define MSPM0_VREF_MODE_SHMODE 1
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_MSPM0_VREF_H */
<|fim_prefix|>/*
* Copyright 2026 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup regu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> flags can be combined on the BUCK regulator.
*/
/** @cond INTERNAL_HIDDEN */
#define NPM10XX_REG_GPIO_Msk (BIT_MASK(4) << 4)
/** @endcond */
/** Turn on enable GPIO control of a regulator */
#define NPM10XX_REG_GPIO_EN BIT(4)
/** Turn on power mode switching GPIO control of BUCK */
#define NP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup regulator_npm1100
* @brief Header file for nPM1100 Devicetree helpers.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM1100_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM110... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup regulator_npm13xx
* @brief Header file f<|fim_suffix|>r nPM13xx Devicetree helpers.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM13XX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_REG... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup regulator_npm2100
* @brief Header file for nPM2100 Devicetree helpers.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_R<|fim_suffix|>fgroup regulator_npm2100 nPM2100 Devicetree helpers
* @b... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup regulator_npm600<|fim_suffix|>tor
* @{
*/
/**
* @name nPM6001 regulator modes
* @{
*/
/** Hysteretic mode */
#define NPM6001_MODE_HYS 0
/** PWM mode */
#define NPM6001_MODE_PWM 1... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>@{
*/
/** LDO mode */
#define NRF5X_REG_MODE_LDO 0
/** DC/DC mode */
#define NRF5X_REG_MODE_DCDC 1
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NRF5X_H_*/
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @i... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ndby mode */
#define NXP_VREF_MODE_STANDBY 0
/** Low power mode */
#define NXP_VREF_MODE_LOW_POWER 1
/** High power mode */
#define NXP_VREF_MODE_HIGH_POWER 2
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NXP_VREF_H */
<|fim_prefix|>/*
* Copyright 2023, 2025 NXP
*
* SPDX-License... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup regulator_rpi_pico
* @brief Header file for Raspberry Pi Pico on-chip regulator Devicetree helpers.
*/
#ifnde<|fim_suffix|>ULATOR_RPI_PICO_H_ */
<|fim_middle|>f ZEPH... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>S_DCDC_MODE_BUCK 0
/** Boost mode */
#define SILABS_DCDC_MODE_BOOST 1
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_SILABS_DCDC_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Silicon Laboratories Inc.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup regulator_sila... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>| NRF_PERM_S)
#define NRF_PERM_WXS (NRF_PERM_W | NRF_PERM_X | NRF_PERM_S)
#define NRF_PERM_RWXS (NRF_PERM_R | NRF_PERM_W | NRF_PERM_X | NRF_PERM_S)
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESERVED_MEMORY_NORDIC_OWNED_MEMORY_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor AS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>D_RESET_GRP_1_OFFSET + 0)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Aspeed Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_AST10X0_H_
#define ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025, FocalTech Systems CO.,Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_FOCALTECH_FT9001_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_FOCALTECH_FT9001_RESET_H_
/**
* @defgroup focaltech_reset_macros FocalTech Reset Configuration Ma... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ESET_CONFIG(reg, bit) \
(((GD32_ ## reg ## _OFFSET) << 6U) | (bit))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>/* APB2 peripherals */
#define GD32_RESET_SYSCFG GD32_RESET_CONFIG(APB2RST, 0U)
#define GD32_RESET_CMP GD32_RESET_CONFIG(APB2RST, 1U)
#define GD32_RESET_ADC0 GD32_RESET_CONFIG(APB2RST, 9U)
#define GD32_RESET_ADC1 GD32_RESET_CONFIG(APB2RST, 10U)
#define GD32_RESET_TIMER0 GD32_RES... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E10X_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32E50X_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define G<|fim_suffix|>GD32_RESET_G... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> GD32_RESET_CONFIG(AHBRST, 12U)
#define GD32_RESET_GPIOA GD32_RESET_CONFIG(AHBRST, 17U)
#define GD32_RESET_GPIOB GD32_RESET_CONFIG(AHBRST, 18U)
#define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHBRST, 19U)
#define GD32_RESET_GPIOD GD32_RESET_CONFIG(AHBRST, 20U)
#define GD32_RESET_GPIOF ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F403_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET 0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>APB1 additional peripherals */
#define GD32_RESET_CTC GD32_RESET_CONFIG(ADDAPB1RST, 27U)
#define GD32_RESET_IREF GD32_RESET_CONFIG(ADDAPB1RST, 31U)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32F4XX_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 BrainCo.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32L23X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32L23X_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_AHB1RST_OFFSET 0x28U
#define GD3... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32VF103_H_
#include "gd32-common.h"
/**
* @name Register offsets
* @{
*/
#define GD32_APB2RST_OFFSET ... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (C) 2023, Intel Corporation
*
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_INTEL_SOCFPGA_RESET_H_
/* The Reset line value will be used by the reset controller driver to
* derive the register off... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ID_FIC3 0x1b
#define MSS_RESET_ID_ATHENA 0x1c
#define MSS_RESET_ID_CFM 0x1d
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_MCHP_MSS_RESET_H_ */
<|fim_prefix|>/*
* Copyright (C) 2025 embedded brains GmbH & Co. KG
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDI<|fim_midd... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>1_OFFSET + 26)
#define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27)
#define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28)
#define NPCX_RESET_GDMA1 (NPCX_RESET_SWRST_CTL1_OFFSET + 29)
#define NPCX_RESET_GDMA2 (NPCX_RESET_SWRST_CTL1_OFFSET + 30)
#define NPCX_RESET_PMC (NPCX_R... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H
#define NPCX_RESET_SWRST_CTL1_OFFSET 0
#define NPCX_RESET_SWRST_CTL2_OFFSET 32
#define NPCX... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> + 17)
#define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18)
#define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19)
#define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20)
#define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21)
#define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M031X_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M031X_RESET_H
/**
* @file
* @brief Reset module IDs for Nuvoton M031X
* @ingroup reset... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M2L31X_RESET_H
/* Beginning of M2L31 BSP sys_reg.h reset module copy */
#define LPSCC_I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M333X_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M333X_RESET_H
/* Beginning of M3331 BSP sys_reg.h reset module copy */
#define SYS_IPRST... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_Pos 1
#define SYS_IPRST3_LLSI2RST_Pos 2
#define SYS_IPRST3_LLSI3RST_Pos 3
#define SYS_IPRST3_LLSI4RST_Pos 4
#define SYS_IPRST3_LLSI5RST_Pos 5
#define SYS_IPRST3_LLSI6RST_Pos 6
#define SYS_IPRST3_LLSI7RST_Pos 7
#define SYS_IPRST3_LLSI8RST_Pos ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M46X_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M46X_RESET_H
/* Beginning of M460 BSP sys_reg.h reset module copy */
#define NUMAKER_SYS_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M55M1X_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M55M1X_RESET_H
/* Beginning of M55M1 BSP sys_reg.h reset module copy */
#define SYS_RST... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>define NUMICRO_GPIO_RST (NUMICRO_RST_ID_IPRST1 | NUMICRO_SYS_IPRST1_GPIORST_Pos)
#define NUMICRO_TMR0_RST (NUMICRO_RST_ID_IPRST1 | NUMICRO_SYS_IPRST1_TMR0RST_Pos)
#define NUMICRO_TMR1_RST (NUMICRO_RST_ID_IPRST1 | NUMICRO_SYS_IPRST1_TMR1RST_Pos)
#define NUMICRO_TMR2_RST (NUMICRO_RST_ID_IPRST1 | NUM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>COMMON_H_ */
<|fim_prefix|>/*
* Copyright 2024 NXP
*
* <|fim_middle|>SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NXP_SYSCON_RESET_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NXP_SYSCON_RESET_COMMON_H_
#define NXP_SYSCON_RESET(offset, bit) ((offset << 16) | ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Yonatan Schachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESE<|fim_suffix|>RESETS_RESET_BUSCTRL 1
#define RPI_PICO_RESETS_RESET_DMA 2
#define RPI_PICO_RESETS_RESET_I2C0 3
#define RPI_PICO_RESETS_RESET_I2C1 4
#define ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fine RPI_PICO_RESETS_RESET_TIMER0 23
#define RPI_PICO_RESETS_RESET_TIMER1 24
#define RPI_PICO_RESETS_RESET_TRNG 25
#define RPI_PICO_RESETS_RESET_UART0 26
#define RPI_PICO_RESETS_RESET_UART1 27
#define RPI_PICO_RESETS_RESET_USBCTRL 28
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_R... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>e SYS_FORCE_RST_PUF 16
#define SYS_FORCE_RST_USB2 17
#define SYS_FORCE_RST_CK30M 18
#define SYS_FORCE_RST_CK60M 19
#define SYS_FORCE_RST_CK120M 20
#define SYS_FORCE_RST_USB2_PHY 21
#define SYS_FORCE_RST_SYS 22
#define SYS_FORCE_RST_DPHY 23
#define SYS_FORCE_RST_SSI_S_BUS ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>define SF32LB_RESET_PDM1 (25U)
#define SF32LB_RESET_I2C1 (27U)
#define SF32LB_RESET_I2C2 (28U)
#define SF32LB_RESET_PTC1 (31U)
#define SF32LB_RESET_GPIO1 (32U)
#define SF32LB_RESET_MPI1 (33U)
#define SF32LB_RESET_MPI2 (34U)
#define SF32... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32_RESET_COMMON_H_
/**
* Pack RCC register offset and bit in one 32-bit value.
*
* 5 LSBs are used to keep bit n... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne STM32_RESET_BUS_APB1L 0x2C
#define STM32_RESET_BUS_APB1H 0x30
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32C0_RESET_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
* Copyright (c) Benjamin Björnsson <benjamin.bjornsson@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHY... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>HB2 0x64
#define STM32_RESET_BUS_AHB4 0x6C
#define STM32_RESET_BUS_APB1L 0x74
#define STM32_RESET_BUS_APB1H 0x78
#define STM32_RESET_BUS_APB2 0x7C
#define STM32_RESET_BUS_APB3 0x80
/** @endcond */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32C5_RESET_H_ */
<|fim_prefix|>/*
* Copyright (c) 2026 STMicr... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS<|fim_suffix|>define STM32_RESET_BUS_APB2 0x0C
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F0_RESET_H_ */
<|fim_middle|>_RESET_STM32F0_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>offset */
#define STM32_RESET_BUS_AHB1 0x10
#define STM32_RESET_BUS_AHB2 0x14
#define STM32_RESET_BUS_AHB3 0x18
#define STM32_RESET_BUS_APB1 0x20
#define STM32_RESET_BUS_APB2 0x24
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32F2_4_7_RESET_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
*
* SP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>T_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Go<|fim_middle|>ogle Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G0_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G0_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
*
* SPDX-License-Ide<|fim_suffix|>4_L4_5_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32G4_L4_5_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x28
#define STM32_RESET_BUS_AHB2 0x2C
#define STM32_RESET_B... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>/
#define STM32_RESET_BUS_AHB1 0x60
#define STM32_RESET_BUS_AHB2 0x64
#define STM32_RESET_BUS_AHB4 0x6C
#define STM32_RESET_BUS_APB1L 0x74
#define STM32_RESET_BUS_APB1H 0x78
#define STM32_RESET_BUS_APB2 0x7C
#define STM32_RESET_BUS_APB3 0x80
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H5_RESET_H... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_APB2 0x98
#define STM32_RESET_BUS_APB3 0x8C
#define STM32_RESET_BUS_APB4 0x9C
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7_RESET_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RE<|fim_middle|>SET_STM32H7_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#define STM32_RESET_BUS_APB1H 0x94
#define STM32_RESET_BUS_APB2 0x98
#define STM32_RESET_BUS_APB4 0x9C
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32H7RS_RESET_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
*
* SPDX-License-Identifier: Apache-2.0
<|fim_suffix|>B1 0x20
#define STM32_RESET_BUS_APB1 0x28
#define STM32_RESET_BUS_APB2 0x24
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L0_RESET_H_ */
<|fim_middle|> */
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L0_RESET_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L1_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L1_RES<|fim_suffix|>ET_BUS_APB2 0x14
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32L1_RESET_H_ */
<|fim_middle|>ET_H... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP13_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP13_RESET_H_
/**
* Pack RCC register offset and bit in one 32-bit value.
*
* bits[4..0] stores the reset controller bi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* <|fim_suffix|>ET_BUS_AHB2_CLR 0x99C
#define STM32_RESET_BUS_AHB3_SET 0x9A0
#define STM32_RESET_BUS_AHB3_CLR 0x9A4
#define STM32_RESET_BUS_AHB4_SET 0x9A8
#define STM32_RESET_BUS_AHB4_CLR 0x9AC
#define STM32_RESET_BUS_AHB5_SET 0x190
#define STM32_RESET_BUS_AHB5_CLR 0x194
#define STM32_RE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (C) 2025 Savoir-faire Linux, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP2_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP2_RESET_H_
/**
* Pack RCC register offset and bit in one 32-bit value.
*
* 5 LSBs are used to keep... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32N6_RESET_H_
#def<|fim_suffix|>#define STM32_RESET_BUS_AHB4 0x21C
#define STM32_RESET_BUS_AHB5 0x220
#define STM32_RESET_BUS_APB1L 0x224
#define STM32_RESET_BUS_APB1H 0x2... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Ident<|fim_suffix|>_BUS_AHB1 0x28
#define STM32_RESET_BUS_APB1L 0x38
#define STM32_RESET_BUS_APB1H 0x40
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U0_RESET_H_ */
<|fim_middle|>ifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U3_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U3_RESET_H_
#include "s<|fim_suffix|>BINDINGS_RESET_STM32U3_RESET_H_ */
<|fim_middle|>tm32-common.h"
/* RCC b... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Google Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U5_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U5_RESET_H_
#include "stm32-common.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x60
#define STM32_RESET_BU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>R_INCLUDE_DT_BINDINGS_RESET_STM32WB0_RESET_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB0_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB0_RESET_H_
#include "stm32-common.h"
/* RCC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_BUS_APB1L 0x38
#define STM32_RESET_BUS_APB1H 0x3C
#define STM32_RESET_BUS_APB2 0x40
#define STM32_RESET_BUS_APB3 0x44
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB_L_RESET_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Google Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>on.h"
/* RCC bus reset register offset */
#define STM32_RESET_BUS_AHB1 0x60
#define STM32_RESET_BUS_AHB2 0x64
#define STM32_RESET_BUS_AHB4 0x6C
#define STM32_RESET_BUS_AHB5 0x70
#define STM32_RESET_BUS_APB1L 0x74
#define STM32_RESET_BUS_APB1H 0x78
#define STM32_RESET_BUS_APB2 0x7C
#define STM32_RESE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Synaptics, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief List reset subsystem IDs for Synaptics SR100 family.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SYNA_SR100_RESET_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_SYNA_SR100_RESET_H_
#include <zephyr/sys/util_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Croxel Inc.
*
* SPDX-License-Identifier: Apache<|fim_suffix|>fine ADXL345_DT_RANGE_2G 0
#define ADXL345_DT_RANGE_4G 1
#define ADXL345_DT_RANGE_8G 2
#define ADXL345_DT_RANGE_16G 3
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADI_ADX345_H_ */
<|fim_mid... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>zation without interpolation */
#define ADXL355_DT_EXTERNAL_SYNC_NO_INTERPOLATION 1
/** External synchronization with interpolation */
#define ADXL355_DT_EXTERNAL_SYNC_WITH_INTERPOLATION 2
/** @} */
/**
* @}
*/
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_ADXL355_H_ */
<|fim_prefix|>/*
* Copyright (... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0x2
#define ADXL362_FIFO_MODE_TRIGGERED 0x3
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADI_ADX362_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Analog Devices Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADI_ADX362_H_
#define ZEPHYR_I... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Analog Devices Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADI_ADX367_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_ADI_ADX367_H_
/**
* @defgroup adxl367 ADXL367 DT Options
* @ingroup sensor_interface
* @{
*/
/**
* @defgroup adxl367_fifo_mode FIFO mode o... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ensor_interface
* @{
*/
/**
* @defgroup ADXL372_FIFO_MODE FIFO mode options
* @{
*/
#define ADXL372_FIFO_MODE_BYPASSED 0x0
#define ADXL372_FIFO_MODE_STREAMED 0x1
#define ADXL372_FIFO_MODE_TRIGGERED 0x2
#define ADXL372_FIFO_MODE_OLD_SAVED 0x3
/** @} */
/** @} */
#endif /... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Croxel Inc.
* Copyright (c) 2025 CogniPilot Foundation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_BRCM_AFBR_S50_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_BRCM_<|fim_suffix|>asurement Modes
* @{
*/
#define AFBR_S50_DT_MODE_SHORT_RANGE 1
#def... | fim | zephyrproject-rtos/zephyr | c |
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