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/*
* Copyright (c) 2022 Vestas Wind Systems A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_KINETIS_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_KINETIS_GPIO_H_
/**
* @name GPIO drive strength flags
*
* The drive strength flags are a Zephyr specific extension of... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2023, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_SIUL2_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_SIUL2_GPIO_H_
/**
* @brief NXP SIUL2 GPIO specific flags
*
* The driver flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>VE_STRENGTH_X3 \
((0x2U << PCA_SERIES_GPIO_DRIVE_STRENGTH_POS) | \
(0x1U << PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_POS))
#define PCA_SERIES_GPIO_DRIVE_STRENGTH_X4 \
((0x3U << PCA_SERIES_GPIO_DRIVE_STRENGTH_POS) | \
(0x1U << PCA_SERIES_GPIO_DRIVE_STRENGTH_ENABLE_POS))
/** Default drive strength on de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> pin */
/** @} */
#endif /* INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_RASPBERRYPI_CSI_CONNECTOR_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file<|fim_middle|>
* @brief Raspberry Pi CSI camera connector pin constants
* @ingroup raspberrypi-cs... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Realtek Bee GPIO Controller specific definitions
*
* This file contains the GPIO configuration flags specific to the Realtek Bee
* series SoCs, used in Device Tree bindings.
*/
#ifndef ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
* Author: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_REALTEK_GPIO_H_
/** Enable input detect */... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_
#define RENESAS_GPIO_DS_POS <|fim_suffix|>x0 << RENESAS_GPIO_DRIV... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RTK0EG0019B01002BJ_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RTK0EG0019B01002BJ_H_
#define RTK0EG0<|fim_suffix|>ine RTK0EG0019B01002BJ_CN1_LED_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
* follows:
* - Bit 8..9: Pin driving ability value
* - Bit 10: Digital Noise Filter ON/OFF
* - Bit 11..12: Digital Noise Filter Number value
* - Bit 13..14: Digital Noise Filter Clock Selection value
* example:
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>IO_H_
/**
* @brief RZ/A2M specific GPIO Flags
*
* The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
* follows:
*
* - Bit 8: Drive strength
*/
/** Normal drive */
#define RZA2M_GPIO_DRIVE_NORMAL (0U << 8U)
/** High drive */
#define RZA2M_GPIO_DRIVE_HIGH (1U << 8U)
#endi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZT2M_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZT2M_H_
#include <zephyr/sys/util.h>
#define RZT2M_GPIO_DRIVE_OFFSET 8
#define RZT2M_GPIO_DRIVE_MAS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 4U /**< Schmitt trigger control shift within DRCTL field */
#define RZTN_GPIO_SLEW_RATE_SHIFT 5U /**< Slew rate control shift within DRCTL field */
/** @endcond */
#define RZTN_GPIO_DRCTL_SET(drive_ability, schmitt_trig, slew_rate) \
(((drive_ability) | ((schmitt_trig)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>e debounce flag is a Zephyr specific extension of the standard GPIO flags
* specified by the Linux GPIO binding. Only applicable for Semtech SX1509B GPIO
* controllers.
*/
#define SX1509B_GPIO_DEBOUNCE (1U << 8)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SEMTECH_SX1509B_H_ */
<|fim_prefix|>/*
* Copyri... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>f Enable hardware control/data source for a pin.
*
* Configures a pin to be controlled by a hardware data source (if
* supported).
*/
#define DW_GPIO_HW_MODE (1U << 9)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_SNPS_DESIGNWARE_GPIO_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 Vestas <|fim_middle|>Wind... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Teslabs Engineering S.L.
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ST Morpho header pin constants
* @ingroup st-morpho-header
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_
/**... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_STM32_GPIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_STM32_GPIO_H_
/**
* @brief STM32 GPIO specific flags
* @defgroup gpio_interface_stm32 STM32 GPIO specific flags
* @in... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>CC13XX_CC26XX_GPIO_DS_POS)
/** @endcond */
/** Default drive strength. */
#define CC13XX_CC26XX_GPIO_DS_DFLT (0x0U << CC13XX_CC26XX_GPIO_DS_POS)
/** Alternative drive strength. */
#define CC13XX_CC26XX_GPIO_DS_ALT (0x3U << CC13XX_CC26XX_GPIO_DS_POS)
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_I<|fim_suffix|>_I2C_I2C_H_ */
<|fim_middle|>NCLUDE_DT_BINDINGS_I2C_I2C_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_I2C_H_
#define I2C_BITRATE_STANDARD 100000 /* 100 Kbit/s */
#define I2C_BITRATE_FAST 400000... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 ITE Technology Corpor<|fim_suffix|>ACE5 6
#define SMB_SWITCH_INTERFACE6 7
#define SMB_SWITCH_INTERFACE7 8
#define SMB_SWITCH_INTERFACE8 9
#define SMB_SWITCH_INTERFACE9 10
#define SMB_SWITCH_INTERFACE10 11
#define SMB_SWITCH_INTERFACE11 12
#define SMB_SWITCH_INTERFACE12 13
#e... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>efine I2C_CHD_LOCATE 3
#define I2C_CHE_LOCATE 4
#define I2C_CHF_LOCATE 5
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_I2C_H_ */
<|fim_prefix|>/*
* Copyright (c) 2022 ITE Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_I2C_H_
#de... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_NPCX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_NPCX_H_
#define NPCX_I2C_CTRL_PORT(ctrl, port) (((ctrl & 0xf) << 4) | (port & 0xf))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_NPC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> * @brief Single tap / click gesture
*/
#define CST8XX_GESTURE_CODE_SINGLE_CLICK 0x05
/**
* @brief Double tap / click gesture
*/
#define CST8XX_GESTURE_CODE_DOUBLE_CLICK 0x0B
/**
* @brief Long press gesture
*/
#define CST8XX_GESTURE_CODE_LONG_PRESS 0x0C
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INPUT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>al data */
#define ESP32_TOUCH_FILTER_SMOOTH_MODE_OFF 0
#define ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_2 1
#define ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_4 2
#define ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_8 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_ESP32_TOUCH_SENSOR_INPUT_H_ */
<|fim_prefix|>/*
* Copyright (c) ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>/
#define INPUT_KEY_KPSLASH 98 /**< Keypad Slash Key */
#define INPUT_KEY_L 38 /**< L Key */
#define INPUT_KEY_LEFT 105 /**< Left Key */
#define INPUT_KEY_LEFTALT 56 /**< Left Alt Key */
#define INPUT_KEY_LEFTBRACE 26 /**< Left Brace Key */
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>) \
((((row) & 0xff) << 24) | (((col) & 0xff) << 16) | ((code) & 0xffff))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_KEYMAP_H_ */
<|fim_prefix|>/*
* Copyright<|fim_middle|> 2024 Google LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_KEYMAP_H_
#define ZEPHYR_I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
* SPDX-License-Identifier: Apache-2.0
*/
#if<|fim_suffix|>2_TSC_H_
#define TSC_IO1 0x1UL
#define TSC_IO2 0x2UL
#define TSC_IO3 0x4UL
#define TSC_IO4 0x8UL
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32_TSC_H_ */
<|fim_middle|>ndef ZEPHYR_INCLUDE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INPUTMUX_TRIGGER_PORTS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INPUTMUX_TRIGGER_PORTS_H_
#define LPC55S69_DMA0_OTRIG_BASE 0x16000000
#define LPC55S69_DMA0_ITRIG_BASE 0x0E00000F
#define LPC55S69_DMA1_OT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PHYS_TIMER 29
#define GIC_INT_NS_PHYS_TIMER 30
#define GIC_INT_LEGACY_IRQ 31
/* BIT(0) reserved for IRQ_ZERO_LATENCY */
#define IRQ_TYPE_LEVEL BIT(1)
#define IRQ_TYPE_EDGE BIT(2)
#define GIC_SPI 0x0
#define GIC_PPI 0x1
#define IRQ_DEFAULT_PRIORITY 0xa0
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTE... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>TR_SOURCE 21
#define I2C_EXT0_INTR_SOURCE 22
#define TG0_T0_LEVEL_INTR_SOURCE 23
#define TG0_WDT_LEVEL_INTR_SOURCE 24
#define CACHE_IA_INTR_SOURCE 25
#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 26
#define SYSTIMER_TARGET1_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DEBUG_INTR_SOURCE 54
#define DMA_APBPERI_PMS_INTR_SOURCE 55
#define CORE0_IRAM0_PMS_INTR_SOURCE 56
#define CORE0_DRAM0_PMS_INTR_SOURCE 57
#define CORE0_PIF_PMS_INTR_SOURCE 58
#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59
#define BAK_PMS_VIOLATE_INTR_SOURCE ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ESP32-C5 interrupt multiplexer definitions for device tree bindings
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C5_INTMUX_H_
#define ZEPHYR_INCLUDE_DT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_
#define WIFI_MAC_INTR_SOURCE 0 ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32H2_INTMUX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32H2_INTMUX_H_
#define PMU_INTR_SOURCE 0
#d... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Interrupt source definitions for Espressif ESP32-P4
*
* Maps peripheral interrupt sources to CLIC interrupt matrix indices.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>* SPI2, level */
#define SPI3_INTR_SOURCE 31 /* SPI3, level */
#define I2S0_INTR_SOURCE 32 /* I2S0, level */
#define I2S1_INTR_SOURCE 33 /* I2S1, level */
#define UART0_INTR_SOURCE 34 /* UART0, level */
#define UART1_INTR_SOURC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S2_XTENSA_INTMUX_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S2_XTENSA_INTMUX_H_
#define WIFI_MAC_INTR_SOURCE ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> /* interrupt of general DMA TX channel 3, LEVEL*/
#define DMA_OUT_CH4_INTR_SOURCE 75 /* interrupt of general DMA TX channel 4, LEVEL*/
#define RSA_INTR_SOURCE 76 /* interrupt of RSA accelerator, level*/
#define AES_INTR_SOURCE 77 /* interrupt of A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fine XMC4XXX_INTC_PORT_POS 0
#define XMC4XXX_INTC_PORT_MASK 0xf
#define XMC4XXX_INTC_PIN_POS 4
#define XMC4XXX_INTC_PIN_MASK 0xf
#define XMC4XXX_INTC_LINE_POS 8
#define XMC4XXX_INTC_LINE_MASK 0x7
#define XMC4XXX_INTC_ERU_SRC_POS 11
#define XMC4XXX_INTC_ERU_SRC_MASK 0x7
#define XMC4XXX_INTC_GET_P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_<|fim_suffix|>PT_CONTROLLER_INTEL_IOAPIC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_INTEL_IOAPIC_H_
#define IRQ_TYPE_LEVEL 0x00008000
#define IRQ_TYPE_EDGE 0x00000000
#define IRQ_TYPE_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT8XXX2_WUC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT8XXX2_WUC_H_
#include <zephyr/dt-bindings/dt-util.h>
/** WUC rese... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ine IT8XXX2_IRQ_WU138 138
#define IT8XXX2_IRQ_WU139 139
#define IT8XXX2_IRQ_WU140 140
#define IT8XXX2_IRQ_WU141 141
#define IT8XXX2_IRQ_WU142 142
#define IT8XXX2_IRQ_WU143 143
/* Group 18 */
#define IT8XXX2_IRQ_WU123 144
#define IT8XXX2_IRQ_WU124 145
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 ITE Corporation. All Rights Reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
#define IRQ_TYPE_NONE 0
#define IRQ_TYPE_EDGE_RISIN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 ITE Corporation. All Rights Reserved.
*
<|fim_suffix|>ED_REG 0
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_ */
<|fim_middle|>* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_
#define ZEP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Microchip Technology
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_MCHP_XEC_ECIA_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_MCHP_XEC_ECIA_H_
/* Encode peripheral's GIRQ and GIR<|fim_suffix|>NCLUDE_DT_BINDINGS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>TMUX_CH3_IRQ 27
#define INTMUX_CH4_IRQ 28
#define INTMUX_CH5_IRQ 29
#define INTMUX_CH6_IRQ 30
#define INTMUX_CH7_IRQ 31
#endif
<|fim_prefix|>/*
* Copyright (c) 2018 Foundries.io Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_OPENISA_INTMUX_H_
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_RTS5817_INTC_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_RTS5817_INTC_H_
#define IRQ_NUM_SIE 0
#define IRQ_NUM_MC 1
#define IRQ_NUM_SENSOR_SPI 4
#define IRQ_NUM_SPI_MASTER 5
#define IRQ_NUM_AES 6
#define IRQ_NUM_SHA 7
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright (C) 2023 BeagleBoard.org Foundation
* Copyright (C) 2023 S Prashanth
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_TI_VIM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_<|fim_suffix|>e IRQ_TYPE_LEVEL BIT(1)
#define IRQ_TYPE_EDGE BI... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_IPC_SERVICE_STATIC_VRINGS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_IPC_SERVICE_STATIC_VRINGS_H_
#include <zep<|fim_suffix|>S_H_ */
<|fim_middle|>hyr/dt-bindings/dt-ut... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Seagate Technology LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LED_LED_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_LED_LED_H_
/* Standard LED colors */
#define LED_COLOR_ID_WHITE 0
#define LED_COLOR_ID_RED 1
#define LED<|fim_suffix|>... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021, Seagate Technology LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LED_SEAGATE_LEGEND_B1414_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_LED_SEAGATE_LEGEND_B1414_H_
/*
* At 6 MHz: 1 bit in 166.666 ns
* 1200 ns -> 7.2 bits
* 300 ns -> 1.8 bits
* 900 ns ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ONE_FRAME (0xFCU)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LED_WORLDSEMI_WS2812C_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 Martin Kiepfer <mrmarteng@teleschirm.org>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LED_WORLDSEMI_WS2812C_H_
#define ZEPHYR_INCLUDE_DT_BINDING... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_LORA_SX126X_H_ */
<|fim_prefix|>/*
* Copyright (c) 2020 Andreas Sandberg
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEP<|fim_middle|>HYR_INCLUDE_DT_BINDINGS_LORA_SX126X_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_LORA_SX126X_H_
#define SX126X_DIO3_TCXO_1V6 0x00
#define SX126X_DIO3_TCXO_1V7 0x01
#d... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Fabian Blatz <fabianblatz@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @ingroup lvgl_keypad_dt
* @brief Devicetree definitions for LVGL keypad input keys.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LVGL_LVGL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_LVGL_LVGL_H_
/**
* @... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>6
/** Reserved, do not use */
#define BCM2711_MBOX0_CH_RESERVED 7
/** ARM -> VC */
#define BCM2711_MBOX0_CH_ARM_TO_VC 8
/** VC -> ARM */
#define BCM2711_MBOX0_CH_VC_TO_ARM 9
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MBOX_BRCM_BCM2711_MBOX_H_ */
<|fim_prefix|>/*
* Copyright (c) 2026 Muhammad Waleed ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_ARM_MPU_FLASH DT_MEM_ARM(ATTR_MPU_FLASH)
/** Private Peripheral Bus region. */
#define DT_MEM_ARM_MPU_PPB DT_MEM_ARM(ATTR_MPU_PPB)
/** I/O (peripheral) memory region. */
#define DT_MEM_ARM_MPU_IO DT_MEM_ARM(ATTR_MPU_IO)
/** External memory region. */
#define DT_MEM_ARM_MPU_EXTMEM ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ros: combinations of generic + arch-specific attributes.
*
* Following the subsystem's composable-bitmask design, each macro is
* built from the generic DT_MEM_CACHEABLE flag and architecture-specific
* sub-attributes rather than standalone one-hot enumerations.
*/
/** @brief Normal non-cacheable me... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief RISC-V memory attribute DT binding definitions.
* @ingroup dt_binding_mem_attr_riscv
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_RISCV_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_R... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>e <zephyr/sys/util_macro.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
/**
* @defgroup dt_binding_mem_attr_software Software-defined memory attributes
* @ingroup dt_memory_attr_software
* @{
*/
/** @cond INTERNAL_HIDDEN */
#define DT_MEM_SW_MASK DT_MEM_SW_ATTR_MASK
#define DT_MEM_SW(x... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Carlo Caione <ccaione@baylibre.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Xtensa memory attribute DT binding definitions.
* @ingroup dt_binding_mem_attr_xtensa
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_XTENSA_H_
#define ZEPHYR_INCLUDE_DT_BIN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> unknown. */
#define DT_MEM_ARCH_ATTR_UNKNOWN BIT(31)
/** @} */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_H_ */
<|fim_prefix|>/**
* @file
* @brief Generic devicetree memory attribute definitions.
* @ingroup dt_memory_attr
*
* Copyright (c) 2023 Carlo Caione <ccaione@baylibre.com>
*
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>B_CS_SETUP_HOLD_7 6 /**< CS Setup/Hold 7 clock cycles */
#define ADI_MAX32_HPB_CS_SETUP_HOLD_8 7 /**< CS Setup/Hold 8 clock cycles */
#define ADI_MAX32_HPB_CS_SETUP_HOLD_9 8 /**< CS Setup/Hold 9 clock cycles */
#define ADI_MAX32_HPB_CS_SETUP_HOLD_10 9 /**< CS Setup/Hold 10 clock cycles */
#define A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ine FLEXRAM_NONE 0
#define FLEXRAM_OCRAM 1
#define FLEXRAM_DTCM 2
#define FLEXRAM_ITCM 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_NXP_FLEXRAM_H_ */
<|fim_prefix|>/*
* Copyright 2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_B<|fim_middle|>INDINGS_MEMORY_C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024-2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_RENESAS_RA_SDRAM_H_
#define SDRAM_TRAS_1CYCLES (1)
#define SDRAM_TRAS_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Georgij Cernysiov
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SRAM_H_
/* NOR/SRAM Bank */
#define STM32_FMC_NORSRAM_BANK1 0x... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMORY_CONTROLLER_STM32_FMC_SDRAM_H_
#<|fim_suffix|>1UL
#define STM32_FMC_SDRAM_NC_10 0x00000002UL
#define STM32_FMC_SDRAM_NC_11 0x00000003UL
/* Number of row address bits *... | fim | zephyrproject-rtos/zephyr | c |
/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree binding constants for Infineon AutAnalog Autonomous Controller.
*
* These consta... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree binding constants for Infineon HPPASS Autonomous Controller.
*
* T... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>define IT8801_ALT_FUNC_2 1U
#define IT8801_ALT_FUNC_3 2U
#define IT8801_ALT_DEFAULT 3U
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MFD_IT8801_ALTCTRL_H_ */
<|fim_prefix|><|fim_middle|>/*
* Copyright (c) 2024 ITE Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_B... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BI<|fim_suffix|>E_TWI 3
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MFD_MCHP_SAM_FLEXCOMM_H_ */
<|fim_middle|>NDINGS_MFD_MCHP_SAM_FLEXCOMM_H_
#define ZEPHYR_INCLUDE_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>E_8080_BUS_8_BIT 0x8 /**< Intel 8080 parallel bus, 8-bit width */
/** @} */
/**
* @name Color coding for MIPI DBI Type A or Type B interface.
* @{
*/
/**
* RGB332 (8 bpp).
*
* - For 8-bit data bus width, 1 pixel is sent in 1 cycle.
* - For 16-bit data bus width, 2 pixels are sent in 1 cycle.
*/
... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DSI_MIPI_DSI_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MIPI_DSI_MIPI_DSI_H_
/**
* @addtogroup mipi_dsi_interface
* @{
*/
/**
* @name MIPI-DSI Pixel formats.
* @{
*/
/** RGB888 (2... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_IFX_CYW20829_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_IFX_CY... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>NCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF54H20_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MIS<|fim_middle|>C_NORDIC_DOMAIN_ID_NRF54H20_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_
#define NRF_DOMAIN_ID_APPLICATION 2
#define NRF_<|fim_suffix|>OBALFAST 12
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
/* autogenerated using Nordic HAL utils/gen_offsets.py script */
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF54H20_H_
#define N... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
/* autogenerated using Nordic HAL utils/gen_offsets.py script */
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_
#define NRF_FIC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF54H20_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF54H20_H_
#define NRF_OWNER_ID_NONE <|fim_suffix|>DIOCORE 3
#endif /* ZEPHYR_I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_
#define NRF_OWN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_CTRL_DT_CONST_H__
#define NXP_RTXXX_DSP_REGION_RESET 0
#define NXP_RTXXX_DSP_REGION_TEXT 1
#define NXP_RTXXX_DSP_REGION_DATA 2
#define NXP_RTXXX_DSP_REGION_MAX 3
#endif
<|fim_prefix|>/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __NXP_RTXX<|fim_middle|>X_DSP_CTRL_D... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>low. */
#define RA_ELC_EVENT_RTC_ALARM 0x019 /**< Alarm interrupt. */
#define RA_ELC_EVENT_RTC_PERIOD 0x01A /**< Periodic interrupt. */
#define RA_ELC_EVENT_RTC_CARRY 0x01B /**< Carry interrupt. */
#define RA_ELC_EVENT_ADC0_SCAN_END 0x01C /**< End of A/D scan... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA2L1 Event Link Controller (ELC).
* @ingroup dt_renesas_ra2l1_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA2L1_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>T_GPT1_COMPARE_E 0x0CD /**< Compare match E. */
#define RA_ELC_EVENT_GPT1_COMPARE_F 0x0CE /**< Compare match F. */
#define RA_ELC_EVENT_GPT1_COUNTER_OVERFLOW 0x0CF /**< Overflow. */
#define RA_ELC_EVENT_GPT1_COUNTER_UNDERFLOW 0x0D0 /**< Underflow. */
#define RA_ELC_EVENT_GPT1_PC ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>M Timer H */
#define RA_ELC_PERIPHERAL_ADC0 8 /**< ADC0 */
#define RA_ELC_PERIPHERAL_ADC0_B 9 /**< ADC0 Group B */
#define RA_ELC_PERIPHERAL_DAC0 12 /**< DAC0 */
#define RA_ELC_PERIPHERAL_IOPORT1 14 /**< IOPORT1 */
#define RA_ELC_PERIPHERAL_IOPORT2 15 /**< IOPORT2 */
#define RA_ELC_PERIPHERAL_IOP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA4L1 Event Link Controller (ELC).
* @ingroup dt_renesas_ra4l1_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4L1_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA4M1 Event Link Controller (ELC).
* @ingroup dt_renesas_ra4m1_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M1_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA4M2 Event Link Controller (ELC).
* @ingroup dt_renesas_ra4m2_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4M2_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0x166 /**< End of A/D scanning operation. */
#define RA_ELC_EVENT_ADC1_SCAN_END_B 0x167 /**< A/D scan end interrupt for group B. */
#define RA_ELC_EVENT_ADC1_WINDOW_A 0x168 /**< Window A Compare match interrupt. */
#define RA_ELC_EVENT_ADC1_WINDOW_B 0x169 /**< Window B Compare... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_IOPORT2 15 /**< IOPORT2 */
#define RA_ELC_PERIPHERAL_IOPORT3 16 /**< IOPORT3 */
#define RA_ELC_PERIPHERAL_IOPORT4 17 /**< IOPORT4 */
#define RA_ELC_PERIPHERAL_I3C 23 /**< I3C */
/** @endcond */
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4T1_ELC_H_ */
<|fim_prefix|>/*
* C... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA4W1 Event Link Controller (ELC).
* @ingroup dt_renesas_ra4w1_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA4W1_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA6E1 Event Link Controller (ELC).
* @ingroup dt_renesas_ra6e1_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6E1_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA6E2 Event Link Controller (ELC).
* @ingroup dt_renesas_ra6e2_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6E2_ELC_H_
#define ZEPHYR_INC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA6M1 Event Link Controller (ELC).
* @ingroup dt_renesas_ra6m1_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M1_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA6M2 Event Link Controller (ELC).
* @ingroup dt_renesas_ra6m2_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M2_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0x092 /**< Reception complete interrupt. */
#define RA_ELC_EVENT_CAN1_MAILBOX_TX 0x093 /**< Transmission complete interrupt. */
#define RA_ELC_EVENT_IOPORT_EVENT_1 0x094 /**< Port 1 event. */
#define RA_ELC_EVENT_IOPORT_EVENT_2 0x095 /**< Port 2 event. */
#define RA_ELC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA6M4 Event Link Controller (ELC).
* @ingroup dt_renesas_ra6m4_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M4_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA6M5 Event Link Controller (ELC).
* @ingroup dt_renesas_ra6m5_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA6M5_ELC_H_
#define ZEPHYR_INC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>#define RA_ELC_EVENT_CAN1_CHERR 0x195 /**< Channel error. */
#define RA_ELC_EVENT_CAN1_COMFRX 0x196 /**< Common FIFO receive interrupt. */
#define RA_ELC_EVENT_CAN1_CF_DMAREQ 0x197 /**< Channel DMA request. */
#define RA_ELC_EVENT_CAN1_RXMB 0x198 /**< Rece... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2026 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA8E1 Event Link Controller (ELC).
* @ingroup dt_renesas_ra8e1_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8E1_ELC_H_
#define ZEPHYR_INC... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA8M1 Event Link Controller (ELC).
* @ingroup dt_renesas_ra8m1_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8M1_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree macros for the Renesas RA8T1 Event Link Controller (ELC).
* @ingroup dt_renesas_ra8t1_elc
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_RENESAS_RA_ELC_RA8T1_ELC_H_
#def... | fim | zephyrproject-rtos/zephyr | c |
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