text stringlengths 14 100k | source stringclasses 1
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<|fim_prefix|>/*
* SPDX-FileCopyrightText: <text>Copyright (c) 2026 Infineon Technologies AG,
* or an affiliate of Infineon Technologies AG. All rights reserved.</text>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree binding constants for Infineon AutAnalog CTB.
*
* These constants ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> PCIE_BDF_FUNC_SHIFT 8U
#define PCIE_BDF_FUNC_MASK 0x7U
#define PCIE_BDF(bus, dev, func) \
((((bus) & PCIE_BDF_BUS_MASK) << PCIE_BDF_BUS_SHIFT) | \
(((dev) & PCIE_BDF_DEV_MASK) << PCIE_BDF_DEV_SHIFT) | \
(((func) & PCIE_BDF_FUNC_MASK) << PCIE_BDF_FUNC_SHIFT))
#define PCIE_BDF_TO_BUS(bdf) (((bdf) >>... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: 2026 Aesc Silicon
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief <|fim_suffix|>itions
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AESC_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AESC_PINCTRL_H_
/** @brief Select mux function 0 */
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>B */
#define PIN_P5_4__UART3_CTS_A ALIF_PINMUX(5, 4, 2) /**< Port 5 Pin 4: UART3_CTS_A */
#define PIN_P5_4__LPPDM_C0_C ALIF_PINMUX(5, 4, 3) /**< Port 5 Pin 4: LPPDM_C0_C */
#define PIN_P5_4__SPI0_SS1_B ALIF_PINMUX(5, 4, 4) /**< Port 5 Pin 4: SPI0_SS1_B */
#define PIN_P5_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-FileCopyrightText: Copyright Alif Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ALIF_ENSEMBLE_E1C_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ALIF_ENSEMBLE_E1C_PINCTRL_H_
/**
* @file
* @brief Pinctrl definitions for Alif Ensemb... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>*/
#define PIN_P6_7__OSPI0_D7_C ALIF_PINMUX(6, 7, 1) /**< Port 6 Pin 7: OSPI0_D7_C */
#define PIN_P6_7__UART0_RTS_B ALIF_PINMUX(6, 7, 2) /**< Port 6 Pin 7: UART0_RTS_B */
#define PIN_P6_7__PDM_C2_A ALIF_PINMUX(6, 7, 3) /**< Port 6 Pin 7: PDM_C2_A */
#define PIN_P6_7__S... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2025 Linumiz GmbH
* Author: Sri Surya <srisurya@linumiz.com>
*/
/**
* @file
* @brief Devicetree pin control helpers for Ambiq Apollo2
* @ingroup pinctrl_apollo2
*/
#ifndef AMBIQ_APOLLO2_PINCTRL_H
#define AMBIQ_APOLLO2_PINCTRL_H
/**
*... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree pin control helpers for Ambiq Apollo3
* @ingroup pinctrl_apollo3
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMBIQ_APOLLO3_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>MUX(82, 4)
#define DISP_PCLK_P82 APOLLO4_PINMUX(82, 5)
#define CT82_P82 APOLLO4_PINMUX(82, 6)
#define NCE82_P82 APOLLO4_PINMUX(82, 7)
#define OBSBUS2_P82 APOLLO4_PINMUX(82, 8)
#define FPIO_P82 APOLLO4_PINMUX(82, 11)
#define MSPI2_9_P83 APOLLO4_PINMUX(83, 0)
#define XT32KHZ_P83 APOLLO4_PINMUX(83, 1)
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Ambiq Micro Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Devicetree pin control helpers for Ambiq Apollo5
* @ingroup pinctrl_apollo5
*/
#ifndef __APOLLO5_PINCTRL_H__
#define __APOLLO5_PINCTRL_H__
/**
* @addtogroup ambiq_pinctrl Ambiq pin control ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMEBAD_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMEBAD_PINCTRL_H_
/* PINMUX Function definitions */
#define AMEBA_GPIO 0
#define AMEBA_UART ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*<|fim_suffix|>3 77
#define AMEBA_KEY_COL4 78
#define AMEBA_KEY_COL5 79
#define AMEBA_KEY_COL6 80
#define AMEBA_KEY_COL7 81
/* Define pins number: bit[14:13] port, bit[12:8] pin, bit[7:0] functi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Realtek Semiconductor Corp.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMEBAG2_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMEBAG2_PINCTRL_H_
/**
* @file
* @brief Realtek AmebaG2 Pinctrl Devicetree bindings
*/
/**
* @n... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define MPS2_ALT_FUNC_POS 0
#define MPS2_ALT_FUNC_MASK 0x3
#define MPS2_EXP_NUM_POS 2
#define MPS2_EXP_NUM_MASK 0x3F
#define MPS2_PINCTRL_FUNC_UART 0
#define MPS2_PINCTRL_FU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PI, 26)
#define SPI4_MOSI_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 27)
#define SPI4_MISO_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 28)
#define SPI4_SCK_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 29)
#define SBCON3_SDA_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_I2C, 30)
#define SBCON3_SCL_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_I... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_PINCTRL_FUNC_UART, 0)
#define UART3_TXD_EXP MPS4_PINMUX(MPS4_PINCTRL_FUNC_UART, 1)
#define SPI3_SS_EXP MPS4_PINMUX(MPS4_PINCTRL_FUNC_SPI, 10)
#define SPI3_MOSI_EXP MPS4_PINMUX(MPS4_PINCTRL_FUNC_SPI, 11)
#define SPI3_MISO_EXP MPS4_PINMUX(MPS4_PINCTRL_FUNC_SPI, 12)
#define SPI3_SCK_EXP MPS4_PINMUX(... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#define V2M_BEETLE_ALT_FUNC_POS 0
#define V2M_BEETLE_ALT_FUNC_MASK 0x7
#define V2M_BEETLE_EXP_NUM_POS 3
#define V2M_BEETLE_EXP_NUM_MASK 0x1F8
#define V2M_BEETLE_PINCTRL_FUNC_UART 0
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Telink Semiconductor
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_B91_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_B91_PINCTRL_H_
/* IDs for GPIO functions */
#define B91_FUNC_A 0x00
#define B91_FUNC_B 0x01
#defin... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Muhammad Waleed Badar
*
<|fim_suffix|>ne I2C4_SDA_GPIO8 BCM2711_PINMUX(8, BCM2711_FSEL_ALT5)
#define I2C4_SCL_GPIO9 BCM2711_PINMUX(9, BCM2711_FSEL_ALT5)
/* I2C5 pinmux definitions */
#define I2C5_SDA_GPIO10 BCM2711_PINMUX(10, BCM2711_FSEL_ALT5)
#define I2C5_SCL_GPIO11... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_BEE_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_BEE_PINCTRL_H_
/**
* @file
* @brief Realtek BEE Pinctrl Devicetree Bindings
*/
/** Position o... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CC13XX_CC26XX_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CC13XX_CC26XX_PINCTRL_H_
/* Adapted from hal/ti/simplelink/source/ti/devices/cc13x2... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Texas Instruments Incorporated
* Copyright (c) 2024 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef CC23X0_PINCTRL_COMMON_H_
#define CC23X0_PINCTRL_COMMON_H_
/*
* The whole TI CC23X0 pin configuration information is encoded in a 32-bit
* bitfield organized... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>X_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, USART1, 3)
#define USART1_CTS_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, USART1, 0)
#define USART1_CTS_PC3_1 CH32V003_PINMUX_DEFINE(PC, 3, USART1, 1)
#define USART1_CTS_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, USART1, 2)
#define USART1_CTS_PC6_3 CH32V003_PINMUX_DEFINE(PC, 6, USA... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Michael Hope <michaelh@juju.nz>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __CH32V00X_PINCTRL_H__
#define __CH32V00X_PINCTRL_H__
#define CH32V00X_PINMUX_PORT_PA 0
#define CH32V00X_PINMUX_PORT_PB 1
#define CH32V00X_PINMUX_PORT_PC 2
#define CH32V00X_PINMUX_PORT_PD 3
/*... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EFINE(PA, 0, USART2, 0)
#define USART2_CTS_PD3_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 3, USART2, 1)
#define USART2_RTS_PA1_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, USART2, 0)
#define USART2_RTS_PD4_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 4, USART2, 1)
#define USART3_CK_PB12_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 12, USART3... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 ELAN Microelectronics Corp.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_EM32F967_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_EM32F967_PINCTRL_H_
/**
* @brief EM32F967 Pin Control Definitions (STM32-style)
*
* This header def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 6
#define PMOD_PWM_MODE3 7
#define ARDUINO_GPIO 8
#define ARDUINO_UART 9
#define ARDUINO_SPI 10
#define ARDUINO_I2C 11
#define ARDUINO_PWM 12
#define ARDUINO_ADC 13
#define NOT_PINMUX 14
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_EMSDP_PINCT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>PORT_MSK 0x7
#define ENE_KB106X_PINMUX_PIN_POS 0
#define ENE_KB106X_PINMUX_PIN_MSK 0x1f
#define ENE_KB106X_PINMUX_FUNC_POS 8
#define ENE_KB106X_PINMUX_FUNC_MSK 0xf
#define ENE_KB106X_EXTENDED_BANK 0x80
/*
* f is function number
* b[7:5] = pin bank
* b[4:0] = pin position in bank
* b[11:8] = functi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) ENE Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ENE_KB1200_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ENE_KB1200_PINCTRL_H_
#include <zephyr/dt-bindings/dt-util.h>
#define PINMUX_FUNC_GPIO 0x00
#define PINMUX_FU... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022-2026 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP_PINCTRL_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP_PINCTRL_COMMON_H_
#include <zephyr/dt-bindings/dt-util.h>
/** @brief GPIO pi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>DATA_IN15 155
#define ESP_I2S0O_DATA_OUT15 155
#define ESP_I2S0O_DATA_OUT16 156
#define ESP_I2S0O_DATA_OUT17 157
#define ESP_I2S0O_DATA_OUT18 158
#define ESP_I2S0O_DATA_OUT19 159
#define ESP_I2S0O_DATA_OUT20 160
#define ESP_I2S0O_DATA_OUT21 161
#define ESP_I2S0O_DATA_OUT22 162
#define ESP_I2S0O_D... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ESP32-C2 GPIO signal map definitions
* @ingroup pinctrl_esp32c2
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>UX(6, ESP_NOSIG, ESP_U1DTR_OUT)
#define UART1_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT)
#define UART1_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT)
#define UART1_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT)
#define UART1_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT)
#define ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ESP32-C3 GPIO signal map definitions
* @ingroup pinctrl_esp32c3
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C3_GPIO_SIGMAP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>SIG, ESP_U1DTR_OUT)
#define UART1_DTR_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1DTR_OUT)
#define UART1_DTR_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1DTR_OUT)
#define UART1_DTR_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1DTR_OUT)
#define UART1_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT)
#define UART1_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>fine ESP_SDIO_TOHOST_INT_OUT 96 /**< SDIO to-host interrupt output */
/* Generic input function signals */
#define ESP_SIG_IN_FUNC_97 97 /**< Generic input function 97 */
#define ESP_SIG_IN_FUNC97 97 /**< Generic input function 97 (alias) */
#define ESP_SIG_IN_FUNC_98 98 /**< Generic input functio... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ESP32-C6 GPIO signal map definitions
* @ingroup pinctrl_esp32c6
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C6_GPIO_SIGMAP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ESP32-H2 GPIO signal map definitions
* @ingroup pinctrl_esp32h2
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32H2_GPIO_SIGMAP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Derived from components/soc/esp32p4/include/soc/gpio_sig_map.h
*/
/**
* @file
* @brief GPIO signal map for Espressif ESP32-P4
*
* Maps peripheral signals to GPIO matrix input/output indice... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief ESP32-S2 GPIO signal map definitions
* @ingroup pinctrl_esp32s2
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S2_GPIO_SIGMAP_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S2... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>5
#define ESP_SUBSPID5_IN 156
#define ESP_SUBSPID5_OUT 156
#define ESP_SUBSPID6_IN 157
#define ESP_SUBSPID6_OUT 157
#define ESP_SUBSPID7_IN 158
#define ESP_SUBSPID7_OUT 158
#define ESP_SUBSPIDQS_IN 159
#define ES... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>OCALTECH_IOCTRL_BASE 0x40000000U
#define FOCALTECH_PINCTRL_VALUE_POS 0U
#define FOCALTECH_PINCTRL_BIT_POS 1U
#define FOCALTECH_PINCTRL_REG_POS 6U
#define FOCALTECH_PINCTRL_VALUE_MASK 0x1U
#define FOCALTECH_PINCTRL_BIT_MASK 0x1FU
#define FOCALTECH_PINCTRL_REG_MASK 0xFFFFFU
#define FOCALTECH_PINM... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 Silicon Labs
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_S1_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_S1_H_
#define GECKO_PORT_A 0
#define GECKO_PORT_B 1
#define GECKO_PORT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> UART RX */
#define GECKO_FUN_UART_RX 1U
/** UART RTS */
#define GECKO_FUN_UART_RTS 2U
/** UART CTS */
#define GECKO_FUN_UART_CTS 3U
/** UART LOCATION */
#define GECKO_FUN_UART_LOC 4U
#define GECKO_FUN_SPI_MISO 5U
#define GECKO_FUN_SPI_MOSI 6U
#define GECKO_FUN_SPI_CSN 7U
#define GECKO_FUN_SPI_SCK 8U
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_
/**
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QM_PINCTRL_H_
/* values for pad field */
#define SC_P_UART0_RTS_B 23
#define SC_P_UART0_CTS_B 24
#define SC_P_ESAI0_FSR... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2023, 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_
/* values for pad field */
#define SC_P_ESAI0_FSR 55
#define SC_P_ESAI0_FST 56
#define SC_P_ESAI0_SCKR ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021 ITE Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IT8XXX2_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IT8XXX2_PINCTRL_H_
#define NO_FUNC 0
/**
* @brief PIN alternate function.
*/
#define IT8XXX2_ALT_FUNC_1 0U
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>SSP0_SCK_PIO1_29 IOCON_MUX(53, IOCON_TYPE_A, 1) /* PIO1_29 */
#define CT32B0_CAP1_PIO1_29 IOCON_MUX(53, IOCON_TYPE_A, 2) /* PIO1_29 */
#define U0_DTRn_PIO1_29 IOCON_MUX(53, IOCON_TYPE_A, 3) /* PIO1_29 */
#define ADC_10_PIO1_29 IOCON_MUX(53, IOCON_TYPE_A, 4) /* PIO1_29 */
#define PIO1_30_PIO1_30 IOCON_MUX(... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2023-2024 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_
/**
* @brief Pin modes
*/
#define MAX32_MODE_GPIO 0x00
#define MAX32_MODE_AF1 0x01
#define MAX32_M... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 Microchip Technology Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MCHP_XEC_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MCHP_XEC_PINCTRL_H_
#include <zephyr/dt-bindings/dt-util.h>
#define MCHP_GPIO 0x0
#define MCHP_AF0 0... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Texas Instruments
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MSPM0_DT_BINDINGS_PINCTRL_H_
#define _MSPM0_DT_BINDINGS_PINCTRL_H_
#define MSP_PORT_INDEX_BY_N<|fim_suffix|>10 (0x0000000A)
#define MSPM0_PIN_FUNCTION_11 (0x0000000B)
#define MSPM0_PIN_FUNCTION_12 ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>GS_PINCTRL_NPCX_PINCTRL_H_ */
<|fim_prefix|>/*
* Copyri<|fim_middle|>ght (c) 2021 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NPCX_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NPCX_PINCTRL_H_
/**
* @brief NPCX specifi... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne NRF_FUN_EXMIF_DQ3 39U
/** EXMIF DQ4 */
#define NRF_FUN_EXMIF_DQ4 40U
/** EXMIF DQ5 */
#define NRF_FUN_EXMIF_DQ5 41U
/** EXMIF DQ6 */
#define NRF_FUN_EXMIF_DQ6 42U
/** EXMIF DQ7 */
#define NRF_FUN_EXMIF_DQ7 43U
/** EXMIF CS0 */
#define NRF_FUN_EXMIF_CS0 44U
/** EXMIF CS1 */
#define NRF_FUN_EXMIF_CS1 45U... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>@param mfp Multi-function value (0..15)
*/
#define NUMICRO_PINMUX(port, pin, mfp) \
(((((port) - 'A') & NUMICRO_PORT_MASK) << NUMICRO_PORT_SHIFT) | \
(((pin) & NUMICRO_PIN_MASK) << NUMICRO_PIN_SHIFT) | \
(((mfp) & NUMICRO_MFP_MASK) << NUMICRO_MFP_SHIFT))
#define NUMICRO_PORT(pinmux) \
(((pinmu... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright 2022, 2024-2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_SIUL2_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_SIUL2_PINCTRL_H_
#include <zephyr/dt-bindings/dt-util.h>
/*
* The NXP S32 pinmux configuration is encoded in ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>nctrl `slew-rate` devicetree property values. The value
* corresponds to what is written to the Speed field in the MIO_PIN_xx SLCR register.
*
* @{
*/
#define IO_SPEED_SLOW 0
#define IO_SPEED_FAST 1
/** @} */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_PINCTRL_ZYNQ_H_ */
<|fim_prefix|>/*
* Copyrig... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2024 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ZYNQMP_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ZYNQMP_PINCTRL_H_
/*
* The offset is defined at `pictrl_soc.h` for the ZynqMP platform
*/
#define FUNCTION_OFFSET... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyrig<|fim_suffix|>RL_PAD23 QUICKLOGIC_EOS_S3_PINMUX(23, 0x0)
#define USB_DN_PAD28 QUICKLOGIC_EOS_S3_PINMUX(28, 0x0)
#define USB_DP_PAD31 QUICKLOGIC_EOS_S3_PINMUX(31, 0x0)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_QUICKLOGIC_EOS_S3_PINCTRL_H_ */
<|fim_middle|>ht (c) 2023 Antmicro <www.antmic... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>TEK_RTS5912_FUNC1 BIT(8) /* Function mode use BIT0~2 */
#define REALTEK_RTS5912_FUNC2 BIT(9)
#define REALTEK_RTS5912_FUNC3 ((BIT(8)) | (BIT(9)))
#define REALTEK_RTS5912_FUNC4 BIT(10)
#define REALTEK_RTS5912_INPUT_OUTPUT_POS 0
#define REALTEK_RTS5912_INPUT_DETECTION_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77951_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77951_H_
#include "pinctrl-rcar-common.h"
/* Pins declaration */
#define PIN_NONE ... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021 IoT.bzh
* Copyright (c) 2023-2024 EPAM Systems
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A77961_H_
#include "pinctrl-rcar-common.h"
/* Pins declaration */
#... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2023 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F0_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F0_H_
#include "pinctrl-rcar-common.h"
/* Pins declaration */
#define PIN_NONE ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Pin control (pinctrl) definitions for R-Car V4H Sparrowhawk board
*
* This header provides macro constants for encoding pin function selections
* and pin indices for R-Car V4H ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>FUNC_MSIOF7_SS1_B RCAR_ALTSEL_FUNC(7, 1, 1)
#define FUNC_MSIOF7_SYNC_B RCAR_ALTSEL_FUNC(7, 0, 1)
/* GP7 ALTSEL function 2 */
#define FUNC_RX4_B RCAR_ALTSEL_FUNC(7, 30, 2)
#define FUNC_TX4_B RCAR_ALTSEL_FUNC(7, 26, 2)
#define FUNC_CTS4_N_B RCAR_ALTSEL_FUNC(7, 24, 2)
#define FUNC_RTS4_N_B RCAR_A... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|> 0x2 /**< GPT0 function. */
#define RA_PSEL_GPT1 0x3 /**< GPT1 function. */
#define RA_PSEL_SCI_0 0x4 /**< SCI0 function. */
#define RA_PSEL_SCI_2 0x4 /**< SCI2 function. */
#define RA_PSEL_SCI_4 0x4 /**< SCI4 function. */
#define RA_PSEL_SCI_6 0x4 /**< SCI6... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA0_H__
#define <|fim_suffix|>ne RA_PSEL_P1nPFS_SDA00A 0x3
/** SAU_UART0 TXD0A */
#define RA_PSEL_P1nPFS_TXD0A 0x3
/** SAU_SPI00 SO00A */
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021-2023 IoT.bzh
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Utility macro definitions to encode GPIO pin function for
* Renesas R-Car Gen4 SoC.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PIN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Renesas RX pin control (pinctrl) definitions for Zephyr.
*
* This header provides macro constants for encoding pin function selections
* and pin indices for Renesas RX SoCs. Th... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>P_IO_SD0_CLK 0xFFFF0600 /* CD0_CLK */
#define BSP_IO_SD0_CMD 0xFFFF0601 /* CD0_CMD */
#define BSP_IO_SD0_RST_N 0xFFFF0602 /* CD0_RST_N */
#define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */
#define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */
#define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */
#define... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA2M_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA2M_H_
#define RZA2M_PIN_NUM_IN_PORT 8
/* Port names as labeled in the H... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>A7 0xFFFF1107 /* SD0_DATA7 */
#define BSP_IO_SD1_CLK 0xFFFF1200 /* SD1_CLK */
#define BSP_IO_SD1_CMD 0xFFFF1201 /* SD1_CMD */
#define BSP_IO_SD1_DATA0 0xFFFF1300 /* SD1_DATA0 */
#define BSP_IO_SD1_DATA1 0xFFFF1301 /* SD1_DATA1 */
#define BSP_IO_SD1_DATA2 0xFFFF1302 /* SD1_DATA2 */
#define BSP_IO_SD1_DAT... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ine BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */
#define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */
#define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */
/* FILNUM */
#define RZG_FILNUM_4_STAGE 0
#define RZG_FILNUM_8_STAGE 1
#define RZG_FILNUM_12_STAGE 2
#define RZG_FILNUM_16_STAGE 3
/* FILCLKSEL */
#de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>or.
*
* @return Encoded pinmux value.
*/
#define RZG_PINMUX(port, pin, func) (port | pin | ((func) << 4))
/**
* @brief Encode filter stage count and clock selection into one configuration value.
*
* Encoding:
* - bits [3:2] = FILNUM (masked to 2 bits)
* - bits [1:0] = FILCLKSEL (masked to 2 bits)... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025-2026 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Renesas RZ/N pin control (pinctrl) definitions for Zephyr.
*
* This header provides macro constants for encoding pin function selections
* and pin indices for Renesas RZ/N Se... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025-2026 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Renesas RZ/T pin control (pinctrl) definitions for Zephyr.
*
* This header provides macro constants for encoding pin function selections
* and pin indices for Renesas RZ/T Se... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_
/* Superset list of all possible IO ports. */
#define PORT... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2025 Renesas Electronics Corporation
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV2H_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV2H_H_
/* Superset list of all possible IO ports. */
#define PORT_00 0x0000 /* IO port 0 ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>ne BSP_IO_SD1CLK 0xFFFF0B00 /* SD1CLK */
#define BSP_IO_SD1CMD 0xFFFF0B01 /* SD1CMD */
#define BSP_IO_SD1DAT0 0xFFFF0C00 /* SD1DAT0 */
#define BSP_IO_SD1DAT1 0xFFFF0C01 /* SD1DAT1 */
#define BSP_IO_SD1DAT2 0xFFFF0C02 /* SD1DAT2 */
#define BSP_IO_SD1DAT3 0xFFFF0C03 /* SD1DAT3 */
#define BSP_IO_PCIE0_RSTO... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>BINDINGS_PINCTRL_RENESAS_RZT2M_PINCTRL_H_ */
<|fim_prefix|>/*
* Copyright (c) 2023 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RZT2M_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PIN<|fim_middle|>CTRL_RENESAS_RZT2M_PINCTRL_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2021, Yonatan Schachter
* Copyright (c) 2024, Andrew Featherstone
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_PINCTRL_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_PINCTRL_COMMON_H_
#define RP2_ALT_FUNC_POS 0
#de... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>IO_FUNC_NULL)
#define ADC_CH3_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_NULL)
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2040_PINCTRL_H_ */
<|fim_prefix|>/*
* Copyright (c) 2021, Yonatan Schachter
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RP... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>UNC_UART_ALT)
#define UART0_TX_P18 RP2XXX_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_UART_ALT)
#define UART0_RX_P19 RP2XXX_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_UART_ALT)
#define UART1_TX_P22 RP2XXX_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART_ALT)
#define UART1_RX_P23 RP2XXX_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART_ALT)
#define ... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>erstone
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350A_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350A_PINCTRL_H_
#include "rpi-pico-rp2350-pinctrl-common.h"
/* ADC channel allocations differ between the RP2350A and RP235... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350B_PINCTRL_H_ */
<|fim_prefix|>/*
* Copyright (c) 2024, Andrew Featherstone
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350B_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2350B_PINCTRL_... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief RTL8752H Pin Control (Pinmux) Header
*
* This file defines the pinmux functions and pin assignments for the
* Realtek RTL8752H series SoC.
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2026, Realtek Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief RTL87X2G Pin Control (Pinmux) Header
*
* This file defines the pinmux functions and pin assignments for the
* Realtek RTL87X2G series SoC.
*/
#ifndef ZEPHYR_INCLUDE_DT_BIN... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2025 Realtek Semiconductor, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RTS5817_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RTS5817_PINCTRL_H_
/**
* Fields:
*
* - pin [ 7 : 0 ]
* - func [ 10 : 8 ]
*/
#define RTS_FP_PIN_... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>
*
* @param port Port name ('A' to 'E')
* @param pin Port pin number (0 to 31)
* @param mux Alternate function number (0 to 7)
*/
#define RV32M1_MUX(port, pin, mux) \
(((((port) - 'A') & 0xF) << 28) | \
(((pin) & 0x3F) << 22) | \
(((mux) & 0x7) << 8))
#endif /* Z... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>EL_POS) & SF32LB_FSEL_MSK))
#endif /* _INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SF32LB_COMMON_PINCTRL_H_ */
<|fim_prefix|>/*
* Copyright (c) 2025 Core Devices LLC
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SF32LB_COMMON_PINCTRL_H_
#define _INCLUDE_ZEPHYR_DT_BINDING... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 GARDENA GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SI32_PINCTRL_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SI32_PINCTRL_
#define SI32_SIGNAL_USART0_TX 0
#define SI32_SIGNAL_USART0_RX 1
#define SI32_SIGNAL_USART0_RTS 2
#def... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2022 Antmicro <www.antmicro.com>
<|fim_suffix|>MUX_IOF1 0x01
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SIFIVE_PINCTRL_H_ */
<|fim_middle|>*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SIFIVE_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_P... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>0xFF, 3, 0, 8, 0)
#define UART0_CLK_HP25 SIWX91X_GPIO(2, 0xFF, 0, 1, 9, 0)
#define UART0_CLK_HP52 SIWX91X_GPIO(2, 0xFF, 16, 3, 4, 0)
#define UART0_CLK_ULP0 SIWX91X_GPIO(2, 6, 22, 4, 0, 0)
#define UART0_CTS_HP6 SIWX91X_GPIO(2, 0xFF, 1, 0, 6, 0)
#define UART0_CTS... | fim | zephyrproject-rtos/zephyr | c |
<|fim_suffix|>)
#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0,... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Silicon Labs
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_
#include <zephyr/dt-bindings/dt-util.h>
/*
* Silabs Series 2 DBUS configuration is encode... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2024 Silicon Laboratories Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_SIWX91X_H_
#define INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_SIWX91X_H_
#include <zephyr/dt-bindings/dt-util.h>
#if !defined(FIELD_PREP)
/* Ups... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2022, Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SMARTBOND_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SMARTBOND_PINCTRL_H_
/** Definitions of pin functions */
#define SMARTBOND_FUNC_GPIO 0
#define SMARTBOND_F... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_COMMON_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_COMMON_H_
/**
* @brief numerical IDs for IO ports
*/
#define STM32_PORTA 0 /* IO port A */
... | fim | zephyrproject-rtos/zephyr | c |
<|fim_prefix|>/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_H_
#include <zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h>
/**
* Originally derived f<|fim_suf... | fim | zephyrproject-rtos/zephyr | c |
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_AFIO_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_AFIO_H_
#define STM32_REMAP_REG_MASK 0x1U
#define STM32_REMAP_REG_SHIFT 0U
#define STM32_REMAP_SHIFT_MASK 0x1FU
#def... | fim | zephyrproject-rtos/zephyr | c |
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