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46 Chapter 1 Computer Abstractions and Technology each wafer, creating the transistors, conductors, and insulators discussed earlier. Today’s integrated circuits contain only one layer of transistors but may have from two to eight levels of metal conductor, separated by layers of insulators. A single microscopic flaw ... | clipped_hennesy_Page_44_Chunk5401 |
The first equation is straightforward to derive. The second is an approximation, since it does not subtract the area near the border of the round wafer that cannot accommodate the rectangular dies (see Figure 1.19). The final equation is based on empirical observations of yields at integrated circuit factories, with ... | clipped_hennesy_Page_45_Chunk5402 |
48 Chapter 1 Computer Abstractions and Technology SPEC CPU Benchmark A computer user who runs the same programs day in and day out would be the perfect candidate to evaluate a new computer. The set of programs run would form a workload. To evaluate two computer systems, a user would simply compare the execution time o... | clipped_hennesy_Page_46_Chunk5403 |
The formula for the geometric mean is n i = 1 n Execution time ratio i where Execution time ratioi is the execution time, normalized to the reference computer, for the ith program of a total of n in the workload, and i = 1 n ai means the product a1 × a2 × … × an SPEC Power Benchmark Today, SPEC o... | clipped_hennesy_Page_47_Chunk5404 |
50 Chapter 1 Computer Abstractions and Technology system. Performance is measured in throughput, and the units are business operations per second. Once again, to simplify the marketing of computers, SPEC boils these numbers down to a single number, called “overall ssj_ops per Watt.” The formula for this single summariz... | clipped_hennesy_Page_48_Chunk5405 |
1.8 Fallacies and Pitfalls The purpose of a section on fallacies and pitfalls, which will be found in every chapter, is to explain some commonly held misconceptions that you might encounter. We call such misbeliefs fallacies. When discussing a fallacy, we try to give a counterexample. We also discuss pitfalls, or easil... | clipped_hennesy_Page_49_Chunk5406 |
52 Chapter 1 Computer Abstractions and Technology The performance enhancement possible with a given improvement is limited by the amount that the improved feature is used. This concept also yields what we call the law of diminishing returns in everyday life. We can use Amdahl’s law to estimate performance improvements ... | clipped_hennesy_Page_50_Chunk5407 |
two of the three factors to compare performance. Although using two of the three factors may be valid in a limited context, the concept is also easily misused. Indeed, nearly all proposed alternatives to the use of time as the performance metric have led eventually to misleading claims, distorted results, or incorrect... | clipped_hennesy_Page_51_Chunk5408 |
54 Chapter 1 Computer Abstractions and Technology 1.9 Concluding Remarks Although it is difficult to predict exactly what level of cost/performance comput ers will have in the future, it’s a safe bet that they will be much better than they are today. To participate in these advances, computer designers and programmers... | clipped_hennesy_Page_52_Chunk5409 |
typically today via multiple processors, and exploiting locality of accesses to a memory hierarchy, typically via caches. Power has replaced die area as the most critical resource of microprocessor design. Conserving power while trying to increase performance has forced the hardware industry to switch to multicore micr... | clipped_hennesy_Page_53_Chunk5410 |
56 Chapter 1 Computer Abstractions and Technology The historical perspective for this chapter provides a background for some of the key ideas presented in this opening chapter. Its purpose is to give you the human story behind the technological advances and to place achievements in their historical context. By understa... | clipped_hennesy_Page_54_Chunk5411 |
1. virtual worlds 14. operating system 2. desktop computers 15. compiler 3. servers 16. bit 4. low-end servers 17. instruction 5. supercomputers 18. assembly language 6. terabyte 19. machine language 7. petabyte 20. C 8. data centers 21. assembler 9. embedded computers 22. high-level language 10. multicore processors 2... | clipped_hennesy_Page_55_Chunk5412 |
58 Chapter 1 Computer Abstractions and Technology 1.1.12 [2] <1.1> Personal computer delivering good performance to single users at low cost 1.1.13 [2] <1.2> Program that translates statements in high-level language to assembly language 1.1.14 [2] <1.2> Program that translates symbolic instructions to binary instruct... | clipped_hennesy_Page_56_Chunk5413 |
1.2.1 [10] <1.3> For a color display using 8 bits for each of the primary colors (red, green, blue) per pixel, what should be the minimum size in bytes of the frame buffer to store a frame? 1.2.2 [5] <1.3> How many frames could it store, assuming the memory contains no other information? 1.2.3 [5] <1.3> If a 256 Kbytes... | clipped_hennesy_Page_57_Chunk5414 |
60 Chapter 1 Computer Abstractions and Technology 1.3.3 [10] <1.4> We are trying to reduce the time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction? For problems below, use the information in the following table. Processor Clock Rate No. Instructions Tim... | clipped_hennesy_Page_58_Chunk5415 |
The following table shows the number of instructions for a program. Arith Store Load Branch Total a. 650 100 600 50 1400 b. 750 250 500 500 2000 1.4.4 [5] <1.4> Assuming that arith instructions take 1 cycle, load and store 5 cycles, and branches 2 cycles, what is the execution time of the program in a 2 GHz processor? ... | clipped_hennesy_Page_59_Chunk5416 |
62 Chapter 1 Computer Abstractions and Technology No. Instructions Compute Load Store Branch Total a. Program1 600 600 200 50 1450 b. Program 2 900 500 100 200 1700 1.5.4 [5] <1.4> Assuming that computes take 1 cycle, loads and store instructions take 10 cycles, and branches take 3 cycles, find the execution time on a ... | clipped_hennesy_Page_60_Chunk5417 |
CPI Class A CPI Class B CPI Class C CPI Class D CPI Class E a. P1 1 2 3 4 5 P2 3 3 3 5 5 b. P1 1 2 3 4 5 P2 2 2 2 2 6 1.6.4 [5] <1.4> Assume that peak performance is defined as the fastest rate that a computer can execute any instruction sequence. What are the peak performances of P1 and P2 expressed in instructions pe... | clipped_hennesy_Page_61_Chunk5418 |
64 Chapter 1 Computer Abstractions and Technology Consider the following values for voltage in each generation. Processor Voltage 80286 (1982) 5 80386 (1985) 5 80486 (1989) 5 Pentium (1993) 5 Pentium Pro (1997) 3.3 Pentium 4 Willamette (2001) 1.75 Pentium 4 Prescott (2004) 1.25 Core 2 Ketsfield (2007) 1.1 1.7.4 [5] <1.... | clipped_hennesy_Page_62_Chunk5419 |
Capacitance Voltage Clock Rate Area a. 1 1/21/2 1.15 1/21/2 b. 1 1/21/4 1.2 1/21/4 1.8.4 [5] <1.5> Find the scaling factor for the dynamic power. 1.8.5 [5] <1.5> Find the scaling of the capacitance per unit area unit. 1.8.6 [5] <1.5> Assuming a Core 2 processor with a clock rate of 2.667 GHz, a power consumption of 95 ... | clipped_hennesy_Page_63_Chunk5420 |
66 Chapter 1 Computer Abstractions and Technology 1.9.4 [5] <1.5> Determine the static power at 0.8 V, assuming a static to dynamic power ratio of 0.6. 1.9.5 [5] <1.5> Determine the static and dynamic power dissipation assuming the rates obtained in problem 1.9.1. 1.9.6 [10] <1.5> Determine the geometric mean of the po... | clipped_hennesy_Page_64_Chunk5421 |
The table below shows the number of instructions per processor core on a multicore processor as well as the average CPI for executing the program on 1, 2, 4, or 8 cores. Using this data, you will be exploring the speedup of applications on multicore processors. Cores per Processor Instructions per Core Average CPI a... | clipped_hennesy_Page_65_Chunk5422 |
68 Chapter 1 Computer Abstractions and Technology Exercise 1.11 The following table shows manufacturing data for various processors. Wafer Diameter Dies per Wafer Defects per Unit Area Cost per Wafer a. 15 cm 84 0.020 defects/cm2 12 b. 20 cm 100 0.031 defects/cm2 15 1.11.1 [10] <1.7> Find the yield. 1.11.2 [5] <1.7> Fi... | clipped_hennesy_Page_66_Chunk5423 |
The following table shows data for further benchmarks. Name CPI Clock Rate SPECratio a. libquantum 1.61 4 GHz 19.8 b. astar 1.79 4 GHz 9.1 1.12.4 [5] <1.7> Find the increase in CPU time if the number of instructions of the benchmark is increased by 10% without affecting the CPI. 1.12.5 [5] <1.7> Find the increase in CP... | clipped_hennesy_Page_67_Chunk5424 |
70 Chapter 1 Computer Abstractions and Technology 1.13.4 [10] <1.8> If the execution time is reduced by an additional 10% with out affecting to the CPI and with a clock rate of 4 GHz, determine the number of instructions. 1.13.5 [10] <1.8> Determine the clock rate required to give a further 10% reduc tion in CPU time... | clipped_hennesy_Page_68_Chunk5425 |
Processor Instr. Count No. Instructions CPI L/S FP Branch L/S FP Branch Clock Rate a. P1 1.00E+06 50% 40% 10% 0.75 1.0 1.5 4 GHz P2 5.00E+06 40% 40% 20% 1.25 0.8 1.25 3 GHz b. P1 5.00E+06 30% 30% 40% 1.5 1.0 2.0 4 GHz P2 2.00E+06 40% 30% 30% 1.25 1.0 2.5 3 GHz 1.14.4 [10] <1.8> Find the MFLOPS figures for the programs.... | clipped_hennesy_Page_69_Chunk5426 |
72 Chapter 1 Computer Abstractions and Technology Assume that each processor has a 2 GHz clock rate. 1.15.4 [10] <1.8> How much must we improve the CPI of FP instructions if we want the program to run two times faster? 1.15.5 [10] <1.8> How much must we improve the CPI of L/S instructions if we want the program to run ... | clipped_hennesy_Page_70_Chunk5427 |
No. Processors Routine A (ms) Routine B (ms) Routine C (ms) Routine D (ms) Routine E (ms) Routing Time (ms) 2 40 78 9 70 4 11 4 29 60 4 36 2 13 8 15 45 3 19 3 17 16 7 35 1 11 2 22 32 4 23 1 6 1 23 64 2 12 0.5 3 1 26 1.16.4 [10] <1.8> For each doubling of the number of processors, determine the ratio of new to old compu... | clipped_hennesy_Page_71_Chunk5428 |
2 I speak Spanish to God, Italian to women, French to men, and German to my horse. Charles V, Holy Roman Emperor (1500–1558) Instructions: Language of the Computer 2.1 Introduction 76 2.2 Operations of the Computer Hardware 77 2.3 Operands of the Computer Hardware 80 2.4 Signed and Unsigned Numbers 87 2.5 Representing... | clipped_hennesy_Page_72_Chunk5429 |
2.8 Supporting Procedures in Computer Hardware 112 2.9 Communicating with People 122 2.10 MIPS Addressing for 32-Bit Immediates and Addresses 128 2.11 Parallelism and Instructions: Synchronization 137 2.12 Translating and Starting a Program 139 2.13 A C Sort Example to Put It All Together 149 2.14 Arrays versus Pointe... | clipped_hennesy_Page_73_Chunk5430 |
76 Chapter 2 Instructions: Language of the Computer 2.1 Introduction To command a computer’s hardware, you must speak its language. The words of a computer’s language are called instructions, and its vocabulary is called an instruction set. In this chapter, you will see the instruction set of a real computer, both in t... | clipped_hennesy_Page_74_Chunk5431 |
By learning how to represent instructions, you will also discover the secret of computing: the stored-program concept. Moreover, you will exercise your “foreign language” skills by writing programs in the language of the computer and running them on the simulator that comes with this book. You will also see the impac... | clipped_hennesy_Page_75_Chunk5432 |
78 Chapter 2 Instructions: Language of the Computer MIPS operands Name Example Comments 32 registers $s0–$s7, $t0–$t9, $zero, $a0–$a3, $v0–$v1, $gp, $fp, $sp, $ra, $at Fast locations for data. In MIPS, data must be in registers to perform arithmetic, register $zero always equals 0, and register $at is reserved by the a... | clipped_hennesy_Page_76_Chunk5433 |
The natural number of operands for an operation like addition is three: the two numbers being added together and a place to put the sum. Requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple: hardware for a variable number of operands ... | clipped_hennesy_Page_77_Chunk5434 |
80 Chapter 2 Instructions: Language of the Computer The compiler must break this statement into several assembly instructions, since only one operation is performed per MIPS instruction. The first MIPS instruction calculates the sum of g and h. We must place the result somewhere, so the compiler creates a temporary va... | clipped_hennesy_Page_78_Chunk5435 |
are also visible to the programmer when the computer is completed, so you can think of registers as the bricks of computer construction. The size of a register in the MIPS architecture is 32 bits; groups of 32 bits occur so frequently that they are given the name word in the MIPS architecture. One major difference betw... | clipped_hennesy_Page_79_Chunk5436 |
82 Chapter 2 Instructions: Language of the Computer The compiled program is very similar to the prior example, except we replace the variables with the register names mentioned above plus two temporary registers, $t0 and $t1, which correspond to the temporary variables above: add $t0,$s1,$s2 # register $t0 contains g +... | clipped_hennesy_Page_80_Chunk5437 |
The data transfer instruction that copies data from memory to a register is traditionally called load. The format of the load instruction is the name of the operation followed by the register to be loaded, then a constant and register used to access memory. The sum of the constant portion of the instruction and the co... | clipped_hennesy_Page_81_Chunk5438 |
84 Chapter 2 Instructions: Language of the Computer In addition to associating variables with registers, the compiler allocates data structures like arrays and structures to locations in memory. The compiler can then place the proper starting address into the data transfer instructions. Since 8-bit bytes are useful in ... | clipped_hennesy_Page_82_Chunk5439 |
The instruction complementary to load is traditionally called store; it copies data from a register to memory. The format of a store is similar to that of a load: the name of the operation, followed by the register to be stored, then offset to select the array element, and finally the base register. Once again, the MIP... | clipped_hennesy_Page_83_Chunk5440 |
86 Chapter 2 Instructions: Language of the Computer Many programs have more variables than computers have registers. Consequently, the compiler tries to keep the most frequently used variables in registers and places the rest in memory, using loads and stores to move variables between registers and memory. The process... | clipped_hennesy_Page_84_Chunk5441 |
Constant operands occur frequently, and by including constants inside arithmetic instructions, operations are much faster and use less energy than if constants were loaded from memory. The constant zero has another role, which is to simplify the instruction set by offering useful variations. For example, the move opera... | clipped_hennesy_Page_85_Chunk5442 |
88 Chapter 2 Instructions: Language of the Computer can be one of two values, which can be thought of as several alternatives: high or low, on or off, true or false, or 1 or 0. Generalizing the point, in any number base, the value of ith digit d is d × Basei where i starts at 0 and increases from right to left. This le... | clipped_hennesy_Page_86_Chunk5443 |
(x31 × 231) + (x30 × 230) + (x29 × 229) + . . . + (x1 × 21) + (x0 × 20) Keep in mind that the binary bit patterns above are simply representatives of numbers. Numbers really have an infinite number of digits, with almost all being 0 except for a few of the rightmost digits. We just don’t normally show leading 0s. Hardw... | clipped_hennesy_Page_87_Chunk5444 |
90 Chapter 2 Instructions: Language of the Computer The positive half of the numbers, from 0 to 2,147,483,647ten (231 - 1), use the same representation as before. The following bit pattern (1000 . . . 0000two) rep resents the most negative number -2,147,483,648ten (-231). It is followed by a declining set of negative ... | clipped_hennesy_Page_88_Chunk5445 |
Unlike the numbers discussed above, memory addresses naturally start at 0 and con- tinue to the largest address. Put another way, negative addresses make no sense. Thus, programs want to deal sometimes with numbers that can be positive or negative and sometimes with numbers that can be only positive. Some programming ... | clipped_hennesy_Page_89_Chunk5446 |
92 Chapter 2 Instructions: Language of the Computer Going the other direction, 1111 1111 1111 1111 1111 1111 1111 1110two is first inverted and then incremented: 0000 0000 0000 0000 0000 0000 0000 0001two + 1two = 0000 0000 0000 0000 0000 0000 0000 0010two = 2ten Our next shortcut tells us how to convert a binary numbe... | clipped_hennesy_Page_90_Chunk5447 |
Let’s negate the 16‑bit version of 2 using the earlier shortcut. Thus, 0000 0000 0000 0010two becomes 1111 1111 1111 1101two + 1two = 1111 1111 1111 1110two Creating a 32‑bit version of the negative number means copying the sign bit 16 times and placing it on the left: 1111 1111 1111 1111 1111 1111 1111 1110two = –2ten... | clipped_hennesy_Page_91_Chunk5448 |
94 Chapter 2 Instructions: Language of the Computer A third alternative representation to two’s complement and sign and magnitude is called one’s complement. The negative of a one’s complement is found by inverting each bit, from 0 to 1 and from 1 to 0, which helps explain its name since the complement of x is 2n – x –... | clipped_hennesy_Page_92_Chunk5449 |
Translating a MIPS Assembly Instruction into a Machine Instruction Let’s do the next step in the refinement of the MIPS language as an example. We’ll show the real MIPS language version of the instruction represented symbolically as add $t0,$s1,$s2 first as a combination of decimal numbers and then of binary numbers. T... | clipped_hennesy_Page_93_Chunk5450 |
96 Chapter 2 Instructions: Language of the Computer Hexadecimal Binary Hexadecimal Binary Hexadecimal Binary Hexadecimal Binary 0hex 0000two 4hex 0100two 8hex 1000two chex 1100two 1hex 0001two 5hex 0101two 9hex 1001two dhex 1101two 2hex 0010two 6hex 0110two ahex 1010two ehex 1110two 3hex 0011two 7hex 0111two bhex 1011t... | clipped_hennesy_Page_94_Chunk5451 |
2.5 Representing Instructions in the Computer 97 Here is the meaning of each name of the fields in MIPS instructions: ■ ■op: Basic operation of the instruction, traditionally called the opcode. ■ ■rs: The first register source operand. ■ ■rt: The second register source operand. ■ ■rd: The register destination operand. ... | clipped_hennesy_Page_95_Chunk5452 |
98 Chapter 2 Instructions: Language of the Computer Here, 19 (for $s3) is placed in the rs field, 8 (for $t0) is placed in the rt field, and 32 is placed in the address field. Note that the meaning of the rt field has changed for this instruction: in a load word instruction, the rt field specifies the destination regis... | clipped_hennesy_Page_96_Chunk5453 |
For convenience, let’s first represent the machine language instructions using decimal numbers. From Figure 2.5, we can determine the three machine lan guage instructions: ANSWER Note the similarity of the binary representations of the first and last instruc tions. The only difference is in the third bit from the lef... | clipped_hennesy_Page_97_Chunk5454 |
100 Chapter 2 Instructions: Language of the Computer Today’s computers are built on two key principles: 1. Instructions are represented as numbers. 2. Programs are stored in memory to be read or written, just like numbers. These principles lead to the stored-program concept; its invention let the computing genie out of... | clipped_hennesy_Page_98_Chunk5455 |
What MIPS instruction does this represent? Chose from one of the four options below. Check Yourself FIGURE 2.7 The stored-program concept. Stored programs allow a computer that performs accounting to become, in the blink of an eye, a computer that helps an author write a book. The switch hap pens simply by loading mem... | clipped_hennesy_Page_99_Chunk5456 |
102 Chapter 2 Instructions: Language of the Computer 2.6 Logical Operations Although the first computers operated on full words, it soon became clear that it was useful to operate on fields of bits within a word or even on individual bits. Examining characters within a word, each of which is stored as 8 bits, is one ex... | clipped_hennesy_Page_100_Chunk5457 |
instruction performs the operation above, assuming that the original value was in register $s0 and the result should go in register $t2: sll $t2,$s0,4 # reg $t2 = reg $s0 << 4 bits We delayed explaining the shamt field in the R-format. Used in shift instructions, it stands for shift amount. Hence, the machine language... | clipped_hennesy_Page_101_Chunk5458 |
104 Chapter 2 Instructions: Language of the Computer As you can see, AND can apply a bit pattern to a set of bits to force 0s where there is a 0 in the bit pattern. Such a bit pattern in conjunction with AND is traditionally called a mask, since the mask “conceals” some bits. To place a value into one of these seas of... | clipped_hennesy_Page_102_Chunk5459 |
packed within a word and to match an externally enforced interface such as an I/O device. All fields must fit within a single word. Fields are unsigned integers that can be as short as 1 bit. C compilers insert and extract fields using logical instructions in MIPS: and, or, sll, and srl. Which operations can isolate a ... | clipped_hennesy_Page_103_Chunk5460 |
106 Chapter 2 Instructions: Language of the Computer Compiling if-then-else into Conditional Branches In the following code segment, f, g, h, i, and j are variables. If the five vari ables f through j correspond to the five registers $s0 through $s4, what is the compiled MIPS code for this C if statement? if (i == j) ... | clipped_hennesy_Page_104_Chunk5461 |
Notice that the assembler relieves the compiler and the assembly language pro grammer from the tedium of calculating addresses for branches, just as it does for calculating data addresses for loads and stores (see Section 2.12). Compilers frequently create branches and labels where they do not appear in the programmin... | clipped_hennesy_Page_105_Chunk5462 |
108 Chapter 2 Instructions: Language of the Computer The first step is to load save[i] into a temporary register. Before we can load save[i] into a temporary register, we need to have its address. Before we can add i to the base of array save to form the address, we must multiply the index i by 4 due to the byte addres... | clipped_hennesy_Page_106_Chunk5463 |
registers and sets a third register to 1 if the first is less than the second; otherwise, it is set to 0. The MIPS instruction is called set on less than, or slt. For example, slt $t0, $s3, $s4 # $t0 = 1 if $s3 < $s4 means that register $t0 is set to 1 if the value in register $s3 is less than the value in register $s4... | clipped_hennesy_Page_107_Chunk5464 |
110 Chapter 2 Instructions: Language of the Computer Signed versus Unsigned Comparison Suppose register $s0 has the binary number 1111 1111 1111 1111 1111 1111 1111 1111two and that register $s1 has the binary number 0000 0000 0000 0000 0000 0000 0000 0001two What are the values of registers $t0 and $t1 after these two... | clipped_hennesy_Page_108_Chunk5465 |
Case/Switch Statement Most programming languages have a case or switch statement that allows the pro grammer to select one of many alternatives depending on a single value. The simplest way to implement switch is via a sequence of conditional tests, turning the switch statement into a chain of if-then-else statement... | clipped_hennesy_Page_109_Chunk5466 |
112 Chapter 2 Instructions: Language of the Computer II. Why does C provide two sets of operators for AND (& and &&) and two sets of operators for OR (| and ||), while MIPS doesn’t? 1. Logical operations AND and OR implement & and |, while conditional branches implement && and ||. 2. The previous statement has it backw... | clipped_hennesy_Page_110_Chunk5467 |
As mentioned above, registers are the fastest place to hold data in a computer, so we want to use them as much as possible. MIPS software follows the following convention for procedure calling in allocating its 32 registers: ■ ■$a0-$a3: four argument registers in which to pass parameters ■ ■$v0-$v1: two value registers... | clipped_hennesy_Page_111_Chunk5468 |
114 Chapter 2 Instructions: Language of the Computer Using More Registers Suppose a compiler needs more registers for a procedure than the four argument and two return value registers. Since we must cover our tracks after our mission is complete, any registers needed by the caller must be restored to the values that th... | clipped_hennesy_Page_112_Chunk5469 |
The next step is to save the registers used by the procedure. The C assignment statement in the procedure body is identical to the example on page 79, which uses two temporary registers. Thus, we need to save three registers: $s0, $t0, and $t1. We “push” the old values onto the stack by creating space for three words ... | clipped_hennesy_Page_113_Chunk5470 |
116 Chapter 2 Instructions: Language of the Computer we can drop two stores and two loads from the code. We still must save and restore $s0, since the callee must assume that the caller needs its value. FIGURE 2.10 The values of the stack pointer and the stack (a) before, (b) during, and (c) after the procedure call. T... | clipped_hennesy_Page_114_Chunk5471 |
Compiling a Recursive C Procedure, Showing Nested Procedure Linking Let’s tackle a recursive procedure that calculates factorial: int fact (int n) { if (n < 1) return (1); else return (n * fact(n – 1)); } What is the MIPS assembly code? The parameter variable n corresponds to the argument register $a0. The compiled pr... | clipped_hennesy_Page_115_Chunk5472 |
118 Chapter 2 Instructions: Language of the Computer The next instruction is where fact returns. Now the old return address and old argument are restored, along with the stack pointer: lw $a0, 0($sp) # return from jal: restore argument n lw $ra, 4($sp) # restore the return address addi $sp, $sp, 8 # adjust stack pointe... | clipped_hennesy_Page_116_Chunk5473 |
Allocating Space for New Data on the Stack The final complexity is that the stack is also used to store variables that are local to the procedure but do not fit in registers, such as local arrays or structures. The segment of the stack containing a procedure’s saved registers and local variables is called a procedure f... | clipped_hennesy_Page_117_Chunk5474 |
120 Chapter 2 Instructions: Language of the Computer Allocating Space for New Data on the Heap In addition to automatic variables that are local to procedures, C programmers need space in memory for static variables and for dynamic data structures. Figure 2.13 shows the MIPS convention for allocation of memory. The st... | clipped_hennesy_Page_118_Chunk5475 |
Figure 2.14 summarizes the register conventions for the MIPS assembly language. Name Register number Usage Preserved on call? $zero 0 The constant value 0 n.a. $v0–$v1 2–3 Values for results and expression evaluation no $a0–$a3 4–7 Arguments no $t0–$t7 8–15 Temporaries no $s0–$s7 16–23 Saved yes $t8–$t9 24–25 More tem... | clipped_hennesy_Page_119_Chunk5476 |
122 Chapter 2 Instructions: Language of the Computer addi$a0, $a0, –1 # subtract 1 from n j sum # go to sum sum_exit: add$v0, $a1, $zero # return value acc jr $ra # return to caller Which of the following statements about C and Java are generally true? 1. C programmers manage data explicitly, while it’s automatic in Ja... | clipped_hennesy_Page_120_Chunk5477 |
Base 2 is not natural to human beings; we have 10 fingers and so find base 10 natural. Why didn’t computers use decimal? In fact, the first commercial computer did offer decimal arithmetic. The problem was that the computer still used on and off signals, so a decimal digit was simply represented by several binary digit... | clipped_hennesy_Page_121_Chunk5478 |
124 Chapter 2 Instructions: Language of the Computer Signed versus unsigned applies to loads as well as to arithmetic. The function of a signed load is to copy the sign repeatedly to fill the rest of the register—called sign extension—but its purpose is to place a correct representation of the number within that regist... | clipped_hennesy_Page_122_Chunk5479 |
Below is the basic MIPS assembly code segment. Assume that base addresses for arrays x and y are found in $a0 and $a1, while i is in $s0. strcpy adjusts the stack pointer and then saves the saved register $s0 on the stack: strcpy: addi $sp,$sp,–4 # adjust stack for 1 more item sw $s0, 0($sp) # save $s0 To initialize i ... | clipped_hennesy_Page_123_Chunk5480 |
126 Chapter 2 Instructions: Language of the Computer If we don’t loop back, it was the last character of the string; we restore $s0 and the stack pointer, and then return. L2: lw $s0, 0($sp) # y[i] == 0: end of string. Re store old $s0 addi $sp,$sp,4 # pop 1 word off stack jr $ra # return String copies usually use poi... | clipped_hennesy_Page_124_Chunk5481 |
Latin Malayalam Tagbanwa General Punctuation Greek Sinhala Khmer Spacing Modifier Letters Cyrillic Thai Mongolian Currency Symbols Armenian Lao Limbu Combining Diacritical Marks Hebrew Tibetan Tai Le Combining Marks for Symbols Arabic Myanmar Kangxi Radicals Superscripts and Subscripts Syriac Georgian Hiragana Number F... | clipped_hennesy_Page_125_Chunk5482 |
128 Chapter 2 Instructions: Language of the Computer 2.10 MIPS Addressing for 32-Bit Immediates and Addresses Although keeping all MIPS instructions 32 bits long simplifies the hardware, there are times where it would be convenient to have a 32-bit constant or 32-bit address. This section starts with the general solut... | clipped_hennesy_Page_126_Chunk5483 |
The machine language version of lui $t0, 255 # $t0 is register 8: 001111 00000 01000 0000 0000 1111 1111 Contents of register $t0 after executing lui $t0, 255: 0000 0000 1111 1111 0000 0000 0000 0000 FIGURE 2.17 The effect of the lui instruction. The instruction lui transfers the 16-bit immediate constant field value i... | clipped_hennesy_Page_127_Chunk5484 |
130 Chapter 2 Instructions: Language of the Computer 2 10000 6 bits 26 bits where the value of the jump opcode is 2 and the jump address is 10000. Unlike the jump instruction, the conditional branch instruction must specify two operands in addition to the branch address. Thus, bne $s0,$s1,Exit # go to Exit if $s0 ≠ $s1... | clipped_hennesy_Page_128_Chunk5485 |
times as far by interpreting the field as a relative word address rather than as a relative byte address. Similarly, the 26-bit field in jump instructions is also a word address, meaning that it represents a 28-bit byte address. Elaboration: Since the PC is 32 bits, 4 bits must come from somewhere else for jumps. The ... | clipped_hennesy_Page_129_Chunk5486 |
132 Chapter 2 Instructions: Language of the Computer Remember that MIPS instructions have byte addresses, so addresses of sequential words differ by 4, the number of bytes in a word. The bne instruc tion on the fourth line adds 2 words or 8 bytes to the address of the following instruction (80016), specifying the bra... | clipped_hennesy_Page_130_Chunk5487 |
3. Base or displacement addressing, where the operand is at the memory loca tion whose address is the sum of a register and a constant in the instruction 4. PC-relative addressing, where the branch address is the sum of the PC and a constant in the instruction 5. Pseudodirect addressing, where the jump address is the... | clipped_hennesy_Page_131_Chunk5488 |
134 Chapter 2 Instructions: Language of the Computer Although we show MIPS as having 32-bit addresses, nearly all microprocessors (including MIPS) have 64-bit address extensions (see Appendix E). These exten sions were in response to the needs of software for larger programs. The process of instruction set extension a... | clipped_hennesy_Page_132_Chunk5489 |
op(31:26) 28–26 31–29 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111) 0(000) Rformat Bltz/gez jump jump & link branch eq branch ne blez bgtz 1(001) add immediate addiu set less than imm. set less than imm. unsigned andi ori xori load upper immediate 2(010) TLB FlPt 3(011) 4(100) load byte load half lwl load wo... | clipped_hennesy_Page_133_Chunk5490 |
136 Chapter 2 Instructions: Language of the Computer Figure 2.20 shows all the MIPS instruction formats. Figure 2.1 on page 78 shows the MIPS assembly language revealed in this chapter. The remaining hidden portion of MIPS instructions deals mainly with arithmetic and real numbers, which are covered in the next chapte... | clipped_hennesy_Page_134_Chunk5491 |
2.11 Parallelism and Instructions: Synchronization Parallel execution is easier when tasks are independent, but often they need to cooperate. Cooperation usually means some tasks are writing new values that others must read. To know when a task is finished writing so that it is safe for another to read, the tasks need... | clipped_hennesy_Page_135_Chunk5492 |
138 Chapter 2 Instructions: Language of the Computer some other processor had already claimed access and 0 otherwise. In the latter case, the value is also changed to 1, preventing any competing exchange in another processor from also retrieving a 0. For example, consider two processors that each try to do the exchange... | clipped_hennesy_Page_136_Chunk5493 |
conditional also fails if the processor does a context switch between the two instructions (see Chapter 5). Since the store conditional will fail after either another attempted store to the load linked address or any exception, care must be taken in choosing which instructions are inserted between the two instructions.... | clipped_hennesy_Page_137_Chunk5494 |
140 Chapter 2 Instructions: Language of the Computer Assembler Since assembly language is an interface to higher-level software, the assembler can also treat common variations of machine language instructions as if they were instructions in their own right. The hardware need not implement these instructions; however, t... | clipped_hennesy_Page_138_Chunk5495 |
to create the assembly language instruction move that copies the contents of one register to another. Thus the MIPS assembler accepts this instruction even though it is not found in the MIPS architecture: move $t0,$t1 # register $t0 gets register $t1 The assembler converts this assembly language instruction into the ma... | clipped_hennesy_Page_139_Chunk5496 |
142 Chapter 2 Instructions: Language of the Computer ■ ■The symbol table contains the remaining labels that are not defined, such as external references. ■ ■The debugging information contains a concise description of how the mod ules were compiled so that a debugger can associate machine instructions with C source fil... | clipped_hennesy_Page_140_Chunk5497 |
Linking Object Files Link the two object files below. Show updated addresses of the first few instructions of the completed executable file. We show the instructions in assembly language just to make the example understandable; in reality, the instructions would be numbers. Note that in the object files we have highl... | clipped_hennesy_Page_141_Chunk5498 |
144 Chapter 2 Instructions: Language of the Computer Procedure A needs to find the address for the variable labeled X to put in the load instruction and to find the address of procedure B to place in the jal instruction. Procedure B needs the address of the variable labeled Y for the store instruction and the address ... | clipped_hennesy_Page_142_Chunk5499 |
1. The jals are easy because they use pseudodirect addressing. The jal at address 40 0004hex gets 40 0100hex (the address of procedure B) in its address field, and the jal at 40 0104hex gets 40 0000hex (the address of procedure A) in its address field. 2. The load and store addresses are harder because they are relativ... | clipped_hennesy_Page_143_Chunk5500 |
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