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146 Chapter 2 Instructions: Language of the Computer ■ ■The library routines become part of the executable code. If a new version of the library is released that fixes bugs or supports new hardware devices, the statically linked program keeps using the old version. ■ ■It loads all routines in the library that are calle... | clipped_hennesy_Page_144_Chunk5501 |
FIGURE 2.22 Dynamically linked library via lazy procedure linkage. (a) Steps for the first time a call is made to the DLL routine. (b) The steps to find the routine, remap it, and link it are skipped on subsequent calls. As we will see in Chapter 5, the operating system may avoid copying the desired routine by remappin... | clipped_hennesy_Page_145_Chunk5502 |
148 Chapter 2 Instructions: Language of the Computer The upside of interpretation is portability. The availability of software Java vir tual machines meant that most people could write and run Java programs shortly after Java was announced. Today, Java virtual machines are found in hundreds of millions of devices, in ... | clipped_hennesy_Page_146_Chunk5503 |
2.13 A C Sort Example to Put It All Together One danger of showing assembly language code in snippets is that you will have no idea what a full assembly language program looks like. In this section, we derive the MIPS code from two procedures written in C: one to swap array elements and one to sort them. The Procedure... | clipped_hennesy_Page_147_Chunk5504 |
150 Chapter 2 Instructions: Language of the Computer This register allocation corresponds to the variable declarations in the first part of the swap procedure in Figure 2.24. Code for the Body of the Procedure swap The remaining lines of C code in swap are temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; Recall that the memo... | clipped_hennesy_Page_148_Chunk5505 |
version of the program. Once again, we present this procedure in several steps, concluding with the full procedure. Register Allocation for sort The two parameters of the procedure sort, v and n, are in the parameter registers $a0 and $a1, and we assign register $s0 to i and register $s1 to j. Code for the Body of the... | clipped_hennesy_Page_149_Chunk5506 |
152 Chapter 2 Instructions: Language of the Computer (Remember that move is a pseudoinstruction provided by the assembler for the convenience of the assembly language programmer; see page 141.) It also takes just one instruction to increment i, the last part of the for statement: addi $s0, $s0, 1 # i += 1 The loop shou... | clipped_hennesy_Page_150_Chunk5507 |
The second test exits if v[j] > v[j + 1] is not true, or exits if v[j] ≤ v[j + 1]. First we create the address by multiplying j by 4 (since we need a byte address) and add it to the base address of v: sll $t1, $s1, 2 # reg $t1 = j * 4 add $t2, $a0, $t1 # reg $t2 = v + (j * 4) Now we load v[j]: lw $t3, 0($t2) # reg $t3 ... | clipped_hennesy_Page_151_Chunk5508 |
154 Chapter 2 Instructions: Language of the Computer Passing Parameters in sort The problem comes when we want to pass parameters because the sort procedure needs the values in registers $a0 and $a1, yet the swap procedure needs to have its parameters placed in those same registers. One solution is to copy the paramet... | clipped_hennesy_Page_152_Chunk5509 |
Saving registers sort: addi $sp,$sp, –20 # make room on stack for 5 registers sw $ra, 16($sp)# save $ra on stack sw $s3,12($sp) # save $s3 on stack sw $s2, 8($sp)# save $s2 on stack sw $s1, 4($sp)# save $s1 on stack sw $s0, 0($sp)# save $s0 on stack Procedure body Move parameters move $s2, $a0 # copy parameter $a0 into... | clipped_hennesy_Page_153_Chunk5510 |
156 Chapter 2 Instructions: Language of the Computer Figure 2.28 shows the impact of compiler optimization on sort program perfor mance, compile time, clock cycles, instruction count, and CPI. Note that unopti mized code has the best CPI, and O1 optimization has the lowest instruction count, but O3 is the fastest, re... | clipped_hennesy_Page_154_Chunk5511 |
2.14 Arrays versus Pointers A challenge for any new C programmer is understanding pointers. Comparing assembly code that uses arrays and array indices to the assembly code that uses pointers offers insights about pointers. This section shows C and MIPS assembly versions of two procedures to clear a sequence of words in... | clipped_hennesy_Page_155_Chunk5512 |
158 Chapter 2 Instructions: Language of the Computer sw $zero, 0($t2) # array[i] = 0 This instruction is the end of the body of the loop, so the next step is to increment i: addi $t0,$t0,1 # i = i + 1 The loop test checks if i is less than size: slt $t3,$t0,$a1 # $t3 = (i < size) bne $t3,$zero,loop1 # if (i < size) go ... | clipped_hennesy_Page_156_Chunk5513 |
Pointer Version of Clear The second procedure that uses pointers allocates the two parameters array and size to the registers $a0 and $a1 and allocates p to register $t0. The code for the second procedure starts with assigning the pointer p to the address of the first element of the array: move $t0,$a0 # p = address of... | clipped_hennesy_Page_157_Chunk5514 |
160 Chapter 2 Instructions: Language of the Computer Note that this program calculates the address of the end of the array in every iteration of the loop, even though it does not change. A faster version of the code moves this calculation outside the loop: move $t0,$a0 # p = address of array[0] sll $t1,$a1,2 # $t1 = si... | clipped_hennesy_Page_158_Chunk5515 |
People used to be taught to use pointers in C to get greater efficiency than that available with arrays: “Use pointers, even if you can’t understand the code.” Mod ern optimizing compilers can produce code for the array version that is just as good. Most programmers today prefer that the compiler do the heavy lifting.... | clipped_hennesy_Page_159_Chunk5516 |
162 Chapter 2 Instructions: Language of the Computer ARM MIPS Date announced 1985 1985 Instruction size (bits) 32 32 Address space (size, model) 32 bits, flat 32 bits, flat Data alignment Aligned Aligned Data addressing modes 9 3 Integer registers (number, model, size) 15 GPR ´ 32 bits 31 GPR ´ 32 bits I/O Memory mappe... | clipped_hennesy_Page_160_Chunk5517 |
by any amount, add it to the other registers to form the address, and then update one register with this new address. Compare and Conditional Branch MIPS uses the contents of registers to evaluate conditional branches. ARM uses the traditional four condition code bits stored in the program status word: negative, zero,... | clipped_hennesy_Page_161_Chunk5518 |
164 Chapter 2 Instructions: Language of the Computer Unique Features of ARM Figure 2.35 shows a few arithmetic-logical instructions not found in MIPS. Since it does not have a dedicated register for 0, it has separate opcodes to perform some operations that MIPS can do with $zero. In addition, ARM has support for multi... | clipped_hennesy_Page_162_Chunk5519 |
ARM also has instructions to save groups of registers, called block loads and stores. Under control of a 16-bit mask within the instructions, any of the 16 regis ters can be loaded or stored into memory in a single instruction. These instructions can save and restore registers on procedure entry and return. These ins... | clipped_hennesy_Page_163_Chunk5520 |
166 Chapter 2 Instructions: Language of the Computer ■ ■1978: The Intel 8086 architecture was announced as an assembly language– compatible extension of the then successful Intel 8080, an 8-bit microproces sor. The 8086 is a 16-bit architecture, with all internal registers 16 bits wide. Unlike MIPS, the registers hav... | clipped_hennesy_Page_164_Chunk5521 |
versions of existing MMX and SSE instructions that operate on 64 bits of data in parallel. Not only does this change enable more multimedia opera tions, it gives the compiler a different target for floating-point operations than the unique stack architecture. Compilers can choose to use the eight SSE registers as floa... | clipped_hennesy_Page_165_Chunk5522 |
168 Chapter 2 Instructions: Language of the Computer This history illustrates the impact of the “golden handcuffs” of compatibility on the x86, as the existing software base at each step was too important to jeopardize with significant architectural changes. If you looked over the life of the x86, on average the archi... | clipped_hennesy_Page_166_Chunk5523 |
Source/destination operand type Second source operand Register Register Register Immediate Register Memory Memory Register Memory Immediate FIGURE 2.37 Instruction types for the arithmetic, logical, and data transfer instructions. The x86 allows the combinations shown. The only restriction is the absence of a memory-m... | clipped_hennesy_Page_167_Chunk5524 |
170 Chapter 2 Instructions: Language of the Computer Mode Description Register restrictions MIPS equivalent Register indirect Address is in a register. Not ESP or EBP lw $s0,0($s1) Based mode with 8- or 32-bit displacement Address is contents of base register plus displacement. Not ESP lw $s0,100($s1) # <= 16bit # dis... | clipped_hennesy_Page_168_Chunk5525 |
The first two categories are unremarkable, except that the arithmetic and logic instruction operations allow the destination to be either a register or a memory location. Figure 2.39 shows some typical x86 instructions and their functions. Instruction Function je name if equal(condition code) {EIP=name}; EIP–128 <= nam... | clipped_hennesy_Page_169_Chunk5526 |
172 Chapter 2 Instructions: Language of the Computer Instruction Meaning Control Conditional and unconditional branches jnz, jz Jump if condition to EIP + 8-bit offset; JNE (for JNZ), JE (for JZ) are alternative names jmp Unconditional jump—8-bit or 16-bit offset call Subroutine call—16-bit offset; return address pushe... | clipped_hennesy_Page_170_Chunk5527 |
FIGURE 2.41 Typical x86 instruction formats. Figure 2.42 shows the encoding of the postbyte. Many instructions contain the 1-bit field w, which says whether the operation is a byte or a double word. The d field in MOV is used in instructions that may move to or from memory and shows the direction of the move. The ADD i... | clipped_hennesy_Page_171_Chunk5528 |
174 Chapter 2 Instructions: Language of the Computer 2.18 Fallacies and Pitfalls Fallacy: More powerful instructions mean higher performance. Part of the power of the Intel x86 is the prefixes that can modify the execution of the following instruction. One prefix can repeat the following instruction until a counter cou... | clipped_hennesy_Page_172_Chunk5529 |
This battle between compilers and assembly language coders is one situation in which humans are losing ground. For example, C offers the programmer a chance to give a hint to the compiler about which variables to keep in registers versus spilled to memory. When compilers were poor at register allocation, such hints w... | clipped_hennesy_Page_173_Chunk5530 |
176 Chapter 2 Instructions: Language of the Computer 2.19 Concluding Remarks The two principles of the stored-program computer are the use of instructions that are indistinguishable from numbers and the use of alterable memory for programs. These principles allow a single machine to aid environmental scientists, financ... | clipped_hennesy_Page_174_Chunk5531 |
3. Make the common case fast. Examples of making the common MIPS case fast include PC-relative addressing for conditional branches and immediate addressing for larger constant operands. 4. Good design demands good compromises. One MIPS example was the com promise between providing for larger addresses and constants in... | clipped_hennesy_Page_175_Chunk5532 |
178 Chapter 2 Instructions: Language of the Computer MIPS instructions Name Format Pseudo MIPS Name Format add add R move move R subtract sub R multiply mult R add immediate addi I multiply immediate multi I load word lw I load immediate li I store word sw I branch less than blt I load half lh I branch less than or equ... | clipped_hennesy_Page_176_Chunk5533 |
Instruction class MIPS examples HLL correspondence Frequency Integer Ft. pt. Arithmetic add, sub, addi Operations in assignment statements 16% 48% Data transfer lw, sw, lb, lbu, lh, lhu, sb, lui References to data structures, such as arrays 35% 36% Logical and, or, nor, andi, ori, sll, srl 0perations in assignment stat... | clipped_hennesy_Page_177_Chunk5534 |
180 Chapter 2 Instructions: Language of the Computer they are quite convenient and result in more readable code (for example, the li and move instructions). If you choose to use pseudoinstructions for these reasons, please add a sentence or two to your solution stating which pseudoinstructions you have used and why. Ex... | clipped_hennesy_Page_178_Chunk5535 |
a. f = g – f; b. f = i + (h – 2); 2.2.1 [5] <2.2> For the C statements above, what is the corresponding MIPS assembly code? Use a minimal number of MIPS assembly instructions. 2.2.2 [5] <2.2> For the C statements above, how many MIPS assembly instruc- tions are needed to perform the C statement? 2.2.3 [5] <2.2> If the ... | clipped_hennesy_Page_179_Chunk5536 |
182 Chapter 2 Instructions: Language of the Computer The following problems deal with translating from MIPS to C. Assume that the variables g, h, i, and j are given and could be considered 32-bit integers as declared in a C program. a. addi f, f, –4 b. add i, g, h add f, i, f 2.3.4 [5] <2.2> For the MIPS statements abo... | clipped_hennesy_Page_180_Chunk5537 |
2.4.4 [10] <2.2, 2.3> For the MIPS assembly instructions above, what is the cor- responding C statement? 2.4.5 [5] <2.2, 2.3> For the MIPS assembly instructions above, rewrite the assem- bly code to minimize the number if MIPS instructions (if possible) needed to carry out the same function. 2.4.6 [5] <2.2, 2.3> How ma... | clipped_hennesy_Page_181_Chunk5538 |
184 Chapter 2 Instructions: Language of the Computer The following problems explore the translation of hexadecimal numbers to other number formats. a. 0xabcdef12 b. 0x10203040 2.5.4 [5] <2.3> Translate the hexadecimal numbers above into decimal. 2.5.5 [5] <2.3> Show how the data in the table would be arranged in memory... | clipped_hennesy_Page_182_Chunk5539 |
2.6.4 [5] <2.2, 2.3> For the MIPS assembly instructions above, what is the corresponding C statement? 2.6.5 [5] <2.2, 2.3> For the MIPS assembly above, assume that the registers $s0, $s1, $s2, and $s3 contain the values 0x0000000a, 0x00000014, 0x0000001e, and 0x00000028, respectively. Also, assume that register $s6 con... | clipped_hennesy_Page_183_Chunk5540 |
186 Chapter 2 Instructions: Language of the Computer 2.7.4 [5] <2.4> For the base ten numbers above, convert to 2’s complement binary. 2.7.5 [5] <2.4> For the base ten numbers above, convert to 2’s complement hexadecimal. 2.7.6 [5] <2.4> For the base ten numbers above, convert the negated values from the table to 2’s ... | clipped_hennesy_Page_184_Chunk5541 |
a. add $s0, $s0, $s1 add $s0, $s0, $s1 b. add $s0, $s0, $s1 add $s0, $s0, $s1 add $s0, $s0, $s1 2.8.4 [5] <2.4> Assume that register $s0 = 0x70000000 and $s1 = 0x10000000. For the table above, will there be overflow? 2.8.5 [5] <2.4> Assume that register $s0 = 0x40000000 and $s1 = 0x20000000. For the table above, will t... | clipped_hennesy_Page_185_Chunk5542 |
188 Chapter 2 Instructions: Language of the Computer 2.9.5 [5] <2.4> Assume that register $s0 = 0x70000000 and $s1 has the value as given in the table. If the instruction: add $s0, $s0, $s1 is executed, what is the result in hex? 2.9.6 [5] <2.4> Assume that register $s0 = 0x70000000 and $s1 has the value as given in th... | clipped_hennesy_Page_186_Chunk5543 |
Exercise 2.11 In the following problems, the data table contains bits that represent the opcode of an instruction. You will be asked to translate the entries into assembly code and determine what format of MIPS instruction the bits represent. a. 0x01084020 b. 0x02538822 2.11.1 [5] <2.4, 2.5> What binary number does the... | clipped_hennesy_Page_187_Chunk5544 |
190 Chapter 2 Instructions: Language of the Computer 2.12.2 [5] <2.5> If the instruction set of the MIPS processor is modified, the instruction format must also be changed. For each of the suggested changes above, show the size of the bit fields of an I-type format instruction. What is the total number of bits needed f... | clipped_hennesy_Page_188_Chunk5545 |
2.13.3 [5] <2.6> For the lines above, what is the value of $t2 for the following sequence of instructions? srl $t2, $t0, 3 andi $t2, $t2, 0xFFEF In the following exercise, the data table contains various MIPS logical operations. You will be asked to find the result of these operations given values for registers $t0 and... | clipped_hennesy_Page_189_Chunk5546 |
192 Chapter 2 Instructions: Language of the Computer 2.14.1 [20] <2.6> Find the shortest sequence of MIPS instructions that extracts a field from $t0 for the constant values i = 22 and j = 5 and places the field into $t1 in the format shown in the data table. 2.14.2 [5] <2.6> Find the shortest sequence of MIPS instruct... | clipped_hennesy_Page_190_Chunk5547 |
2.15.1 [5] <2.6> The logical instructions above are not included in the MIPS instruction set, but are described above. If the value of $t2 = 0x00FFA5A5 and the value of $t3 = 0xFFFF003C, what is the result in $t1? 2.15.2 [10] <2.6> The logical instructions above are not included in the MIPS instruction set, but can be ... | clipped_hennesy_Page_191_Chunk5548 |
194 Chapter 2 Instructions: Language of the Computer Note the result of executing these instructions on particular registers. What is the value of $t2 after the following instructions? slt $t2, $t0, $t1 beq $t2, $0, ELSE j DONE ELSE: addi $t2, $0, 2 DONE: 2.16.2 [5] <2.7> Suppose that register $t0 contains a value from... | clipped_hennesy_Page_192_Chunk5549 |
address as shown in the data table above? Is it possible to use the branch-on-equal (beq) MIPS assembly instruction to set the PC to the address as shown in the data table above? Note the format of the J-type instruction. Exercise 2.17 For these problems, there are several instructions that are not included in the MIPS... | clipped_hennesy_Page_193_Chunk5550 |
196 Chapter 2 Instructions: Language of the Computer 2.17.6 [5] <2.7> For the loops written in MIPS assembly above, assume that the register $t1 is initialized to the value N. How many MIPS instructions are executed? Exercise 2.18 For these problems, the table holds some C code. You will be asked to evaluate these C co... | clipped_hennesy_Page_194_Chunk5551 |
2.18.5 [5] <2.7> Translate the loops above into C. Assume that the C-level inte- ger i is held in register $t1, $s2 holds the C-level integer called result, and $s0 holds the base address of the integer MemArray. 2.18.6 [5] <2.7> Rewrite the loop to reduce the number of MIPS instructions executed. Exercise 2.19 For the... | clipped_hennesy_Page_195_Chunk5552 |
198 Chapter 2 Instructions: Language of the Computer using the MIPS calling convention from Figure 2.14. The function declaration for func is “int func(int a, int b);”. The code for function f is as follows: a. int f(int a, int b, int c, int d){ return func(func(a,b),c+d); } b. int f(int a, int b, int c, int d){ if(a+b... | clipped_hennesy_Page_196_Chunk5553 |
b. FACT: addi $sp, $sp, 8 sw $ra, 4($sp) sw $a0, 0($sp) add $s0, $0, $a0 slti $t0, $a0, 2 beq $t0, $0, L1 mul $v0, $s0, $v0 addi $sp, $sp, -8 jr $ra L1: addi $a0, $a0, -1 jal FACT addi $v0, $0, 1 lw $a0, 0($sp) lw $ra, 4($sp) addi $sp, $sp, -8 jr $ra 2.20.1 [5] <2.8> The MIPS assembly program above computes the factori... | clipped_hennesy_Page_197_Chunk5554 |
200 Chapter 2 Instructions: Language of the Computer a. FIB: addi $sp, $sp, –12 sw $ra, 0($sp) sw $s1, 4($sp) sw $a0, 8($sp) slti $t0, $a0, 1 beq $t0, $0, L1 addi $v0, $a0, $0 j EXIT L1: addi $a0, $a0, –1 jal FIB addi $s1, $v0, $0 addi $a0, $a0, –1 jal FIB add $v0, $v0, $s1 EXIT: lw $ra, 0($sp) lw $a0, 8($sp) lw $s1, 4... | clipped_hennesy_Page_198_Chunk5555 |
instructions used to execute your solution from 2.20.2 versus the recursive version of the factorial program? 2.20.6 [5] <2.8> Show the contents of the stack after each function call, assum- ing that the input is 4. Exercise 2.21 Assume that the stack and the static data segments are empty and that the stack and global... | clipped_hennesy_Page_199_Chunk5556 |
202 Chapter 2 Instructions: Language of the Computer The following three problems in this Exercise refer to this function, written in MIPS assembly following the calling conventions from Figure 2.14: a. f: add $v0,$a1,$a0 bnez $a2,L sub $v0,$a0,$a1 L: jr $v0 b. f: add $a2,$a3,$a2 slt $a2,$a2,$a0 move $v0,$a1 beqz $a2, ... | clipped_hennesy_Page_200_Chunk5557 |
2.22.3 [5] <2.5, 2.9> Translate the hexadecimal ASCII values to text. Exercise 2.23 In this exercise, you will be asked to write an MIPS assembly program that converts strings into the number format as specified in the table. a. positive and negative integer decimal strings b. positive hexadecimal integers 2.23.1 [10] ... | clipped_hennesy_Page_201_Chunk5558 |
204 Chapter 2 Instructions: Language of the Computer What value is stored at the address pointed to by register $t2? Assume that the memory location pointed to $t2 is initialized to 0x0000 0000. 2.24.3 [5] <2.9> Assume that the data (in hexadecimal) at address 0x1000 0000 is: 1000 0000 11 00 00 FF What value is stored ... | clipped_hennesy_Page_202_Chunk5559 |
2.25.6 [5] <2.6, 2.10> What is the value of register $t0 after the sequence of code in the table above? 2.25.7 [5] <2.6, 2.10> Write C code that is equivalent to the assembly code in the table. Assume that the largest constant that you can load into a 32-bit integer is 16 bits. Exercise 2.26 For this exercise, you will... | clipped_hennesy_Page_203_Chunk5560 |
206 Chapter 2 Instructions: Language of the Computer changes above, what is the impact on the range of addresses for a jump instruc- tion? Assume that instructions remain 32 bits long and any changes made to the instruction format of J-type instructions only impact the address field of the jump instruction. 2.26.6 [10]... | clipped_hennesy_Page_204_Chunk5561 |
2.27.5 [10] <2.10> By reducing the size of the immediate fields of the I-type and J-type instructions, we can save on the number of bits needed to represent these types of instructions. If the immediate field of I-type instructions were 8 bits and the immediate field of J-type instructions were 18 bits, rewrite the MIP... | clipped_hennesy_Page_205_Chunk5562 |
208 Chapter 2 Instructions: Language of the Computer b. Processor 1 Processor 2 Cycle Processor 1 Mem Processor 2 $t1 $t0 ($s1) $t1 $t0 0 1 2 99 30 40 ll $t1,0($s1) 1 ll $t1,0($s1) 2 addi $t1,$t1,1 3 sc $t1,0($s1) 4 sc $t0,0($s1) 5 2.28.4 [5] <2.11> Fill out the table with the value of the registers for each given cycl... | clipped_hennesy_Page_206_Chunk5563 |
means that ll/sc always succeeds, the lock is always free when we want to lock(), and if there is a branch we take the path that completes the operation with fewer executed instructions. 2.29.4 [10] <2.11> Using your code from 2.29.2 as an example, explain what happens when two processors begin to execute this critical... | clipped_hennesy_Page_207_Chunk5564 |
210 Chapter 2 Instructions: Language of the Computer 2.30.2 [5] <2.12> Does the instruction in the table above need to be edited dur- ing the link phase? Why? Exercise 2.31 The table below contains the link-level details of two different procedures. In this exercise, you will be taking the place of the linker. a. Proce... | clipped_hennesy_Page_208_Chunk5565 |
2.31.1 [5] <2.12> Link the object files above to form the executable file header. Assume that Procedure A has a text size of 0x140 and data size of 0x40 and Pro- cedure B has a text size of 0x300 and data size of 0x50. Also assume the memory allocation strategy as shown in Figure 2.13. 2.31.2 [5] <2.12> What limitation... | clipped_hennesy_Page_209_Chunk5566 |
212 Chapter 2 Instructions: Language of the Computer 2.32.6 [10] <2.13> When sorting a 10-element array that was sorted in descend- ing order (opposite of the order that sort() creates), how many more (or fewer) instructions are executed as a result of this change? Exercise 2.33 The problems in this Exercise refer to t... | clipped_hennesy_Page_210_Chunk5567 |
Exercise 2.34 The table below contains ARM assembly code. In the following problems, you will translate ARM assembly code to MIPS. a. ADD r0, r1, r2 ;r0 = r1 + r2 ADC r0, r1, r2 ;r0 = r1 + r2 + Carrybit b. CMP r0, #4 ;if (r0 != 4) { ADDNE r1, r1, r0 ;r1 += r0 } 2.34.1 [5] <2.16> For the table above, translate this ARM ... | clipped_hennesy_Page_211_Chunk5568 |
214 Chapter 2 Instructions: Language of the Computer 2.35.2 [5] <2.16> For the ARM assembly instructions above, write a sequence of MIPS assembly instructions to accomplish the same data transfer. In the following problems, you will compare code written using the ARM and MIPS instruction sets. The following table shows... | clipped_hennesy_Page_212_Chunk5569 |
The following table contains MIPS instructions. a. addi r3, r2, 0x2 b. addi r3, r2, –1 2.36.4 [5] <2.16> For the MIPS assembly code above, write the equivalent ARM assembly code. Exercise 2.37 This exercise explores the differences between the MIP and x86 instruction sets. The following table contains x86 assembly code... | clipped_hennesy_Page_213_Chunk5570 |
216 Chapter 2 Instructions: Language of the Computer Exercise 2.38 The x86 instruction set includes the REP prefix that causes the instruction to be repeated a given number of times or until a condition is satisfied. Note that x86 instructions refer to 8 bits as a byte, 16 bits as a word, and 32 bits as a double word. ... | clipped_hennesy_Page_214_Chunk5571 |
b. void f(int a[], int n){ int i; for(i=0;i!=n;i++) a[i]=0; } f: push %ebp ; 1B, push %ebp to stack mov %esp,%ebp ; 2B, move %esp to %ebp mov 12(%ebp),%edx ; 3B, move 2nd arg into %edx mov 8(%ebp),%ecx ; 3B, move 1st arg into %ecx test %edx,%edx ; 2B, set flags based on %edx jz D ; 2B, jump if %edx was 0 xor %eax,%eax ... | clipped_hennesy_Page_215_Chunk5572 |
218 Chapter 2 Instructions: Language of the Computer 2.39.2 [5] <2.18> Suppose that new, more powerful arithmetic instructions are added to the instruction set. On average, through the use of these more power- ful arithmetic instructions, we can reduce the number of arithmetic instructions needed to execute a program b... | clipped_hennesy_Page_216_Chunk5573 |
b. ; void f(int a[], int n); f: move $t0,$0 ; i=0; addi $t1,$a1,-1 ; n-1 L: add $t2,$t0,$a0 ; address of a[i] lw $t3,1($t2) ; read a[i+1] sw $t3,0($t2) ; a[i]=a[i+1] addi $t0,$t0,1 ; i=i+1 bne $t0,$t1,L ; repeat if i!=n-1 jr $ra ; return Note that in MIPS assembly the “;” character denotes that the remainder of the lin... | clipped_hennesy_Page_217_Chunk5574 |
220 Chapter 2 Instructions: Language of the Computer using a pointer to an automatic variable arr outside the function in which it is defined. my_alloc in C MIPS Code for my_alloc int *my_alloc(int n){ int arr[n]; return arr; } my_alloc: addu $sp,$sp,-4 ; Push sw $fp,0($sp) ; $fp to stack move $fp,$sp ; Save $sp in $fp... | clipped_hennesy_Page_218_Chunk5575 |
§2.2, page 80: MIPS, C, Java §2.3, page 87: 2) Very slow §2.4, page 93: 3) –8ten §2.5, page 101: 4) sub $s2, $s0, $s1 §2.6, page 105: Both. AND with a mask pattern of 1s will leaves 0s everywhere but the desired field. Shifting left by the right amount removes the bits from the left of the field. Shifting right by the ... | clipped_hennesy_Page_219_Chunk5576 |
3 Numerical precision is the very soul of science. Sir D’arcy Wentworth Thompson On Growth and Form, 1917 Arithmetic for Computers 3.1 Introduction 224 3.2 Addition and Subtraction 224 3.3 Multiplication 230 3.4 Division 236 3.5 Floating Point 242 3.6 Parallelism and Computer Arithmetic: Associativity 270 3.7 Real Stu... | clipped_hennesy_Page_220_Chunk5577 |
3.9 Concluding Remarks 280 3.10 Historical Perspective and Further Reading 283 3.11 Exercises 283 The Five Classic Components of a Computer | clipped_hennesy_Page_221_Chunk5578 |
224 Chapter 3 Arithmetic for Computers 3.1 Introduction Computer words are composed of bits; thus, words can be represented as binary numbers. Chapter 2 shows that integers can be represented either in decimal or binary form, but what about the other numbers that commonly occur? For example: ■ ■What about fractions and... | clipped_hennesy_Page_222_Chunk5579 |
3.2 Addition and Subtraction 225 Subtracting 6ten from 7ten can be done directly: 0000 0000 0000 0000 0000 0000 0000 0111two = 7ten – 0000 0000 0000 0000 0000 0000 0000 0110two = 6ten = 0000 0000 0000 0000 0000 0000 0000 0001two = 1ten or via addition using the two’s complement representation of -6: 0000 0000 0000 0000... | clipped_hennesy_Page_223_Chunk5580 |
226 Chapter 3 Arithmetic for Computers The lack of a 33rd bit means that when overflow occurs, the sign bit is set with the value of the result instead of the proper sign of the result. Since we need just one extra bit, only the sign bit can be wrong. Hence, overflow occurs when adding two positive numbers and the sum ... | clipped_hennesy_Page_224_Chunk5581 |
3.2 Addition and Subtraction 227 The computer designer must decide how to handle arithmetic overflows. Although some languages like C and Java ignore integer overflow, languages like Ada and Fortran require that the program be notified. The programmer or the programming environment must then decide what to do when over... | clipped_hennesy_Page_225_Chunk5582 |
228 Chapter 3 Arithmetic for Computers to the largest positive number or most negative number, rather than a modulo calculation as in two’s complement arithmetic. Saturation is likely what you want for media operations. For example, the volume knob on a radio set would be frustrating if, as you turned, it would get con... | clipped_hennesy_Page_226_Chunk5583 |
3.2 Addition and Subtraction 229 Summary A major point of this section is that, independent of the representation, the finite word size of computers means that arithmetic operations can create results that are too large to fit in this fixed word size. It’s easy to detect overflow in unsigned numbers, although these are... | clipped_hennesy_Page_227_Chunk5584 |
230 Chapter 3 Arithmetic for Computers 3.3 Multiplication Now that we have completed the explanation of addition and subtraction, we are ready to build the more vexing operation of multiplication. First, let’s review the multiplication of decimal numbers in longhand to remind ourselves of the steps of multiplication an... | clipped_hennesy_Page_228_Chunk5585 |
Now that we have reviewed the basics of multiplication, the traditional next step is to provide the highly optimized multiply hardware. We break with tradition in the belief that you will gain a better understanding by seeing the evolution of the multiply hardware and algorithm through multiple generations. For now, le... | clipped_hennesy_Page_229_Chunk5586 |
232 Chapter 3 Arithmetic for Computers the Product register. The left shift in step 2 has the effect of moving the intermediate operands to the left, just as when multiplying with paper and pencil. The shift right in step 3 gives us the next bit of the multiplier to examine in the following iteration. These three steps... | clipped_hennesy_Page_230_Chunk5587 |
two 32-bit numbers. The relative importance of arithmetic operations like multiply varies with the program, but addition and subtraction may be anywhere from 5 to 100 times more popular than multiply. Accordingly, in many applications, multiply can take multiple clock cycles without significantly affecting performance.... | clipped_hennesy_Page_231_Chunk5588 |
234 Chapter 3 Arithmetic for Computers A Multiply Algorithm Using 4-bit numbers to save space, multiply 2ten × 3ten, or 0010two × 0011two. Figure 3.7 shows the value of each register for each of the steps labeled according to Figure 3.5, with the final value of 0000 0110two or 6ten. Color is used to indicate the regist... | clipped_hennesy_Page_232_Chunk5589 |
Faster Multiplication Moore’s law has provided so much more in resources that hardware designers can now build much faster multiplication hardware. Whether the multiplicand is to be added or not is known at the beginning of the multiplication by looking at each of the 32 multiplier bits. Faster multiplications are poss... | clipped_hennesy_Page_233_Chunk5590 |
236 Chapter 3 Arithmetic for Computers 3.4 Division The reciprocal operation of multiply is divide, an operation that is even less frequent and even more quirky. It even offers the opportunity to perform a mathematically invalid operation: dividing by 0. Let’s start with an example of long division using decimal number... | clipped_hennesy_Page_234_Chunk5591 |
Divide’s two operands, called the dividend and divisor, and the result, called the quotient, are accompanied by a second result, called the remainder. Here is another way to express the relationship between the components: Dividend = Quotient × Divisor + Remainder where the remainder is smaller than the divisor. Infreq... | clipped_hennesy_Page_235_Chunk5592 |
238 Chapter 3 Arithmetic for Computers 33rd repetition? . Shift the Quotient register to the left, setting the new rightmost bit to 1 Remainder < 0 Remainder ≥ 0 Test Remainder Start 3. Shift the Divisor register right 1 bit No: < 33 repetitions Yes: 33 repetitions Done 1. Subtract the Divisor register from the Remaind... | clipped_hennesy_Page_236_Chunk5593 |
Figure 3.10 shows three steps of the first division algorithm. Unlike a human, the computer isn’t smart enough to know in advance whether the divisor is smaller than the dividend. It must first subtract the divisor in step 1; remember that this is how we performed the comparison in the set on less than instruction. If ... | clipped_hennesy_Page_237_Chunk5594 |
240 Chapter 3 Arithmetic for Computers Checking the results: 7 = 3 × 2 + (+1) = 6 + 1 If we change the sign of the dividend, the quotient must change as well: –7 ÷ +2: Quotient = –3 Iteration Step Quotient Divisor Remainder 0 Initial values 0000 0010 0000 0000 0111 1 1: Rem = Rem – Div 0000 0010 0000 1110 0111 2b: Rem ... | clipped_hennesy_Page_238_Chunk5595 |
Rewriting our basic formula to calculate the remainder: Remainder = (Dividend – Quotient × Divisor) = –7 – (–3 × +2) = –7–(–6) = –1 So, –7 ÷ +2: Quotient = –3, Remainder = –1 Checking the results again: –7 = –3 × 2 + (–1) = – 6 – 1 The reason the answer isn’t a quotient of –4 and a remainder of +1, which would also fit... | clipped_hennesy_Page_239_Chunk5596 |
242 Chapter 3 Arithmetic for Computers As we might expect from the algorithm above, Hi contains the remainder, and Lo contains the quotient after the divide instruction completes. To handle both signed integers and unsigned integers, MIPS has two instruc- tions: divide (div) and divide unsigned (divu). The MIPS assembl... | clipped_hennesy_Page_240_Chunk5597 |
MIPS assembly language Category Instruction Example Meaning Comments Arithmetic add add $s1,$s2,$s3 $s1 = $s2 + $s3 Three operands; overflow detected subtract sub $s1,$s2,$s3 $s1 = $s2 – $s3 Three operands; overflow detected add immediate addi $s1,$s2,100 $s1 = $s2 + 100 + constant; overflow detected add unsigned addu ... | clipped_hennesy_Page_241_Chunk5598 |
244 Chapter 3 Arithmetic for Computers Notice that in the last case, the number didn’t represent a small fraction, but it was bigger than we could represent with a 32-bit signed integer. The alternative notation for the last two numbers is called scientific notation, which has a single digit to the left of the decimal ... | clipped_hennesy_Page_242_Chunk5599 |
23-bit number. This representation is called sign and magnitude, since the sign is a separate bit from the rest of the number. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s exponent fraction 1 bit 8 bits 23 bits In general, floating-point numbers are of the form (-1)S × F × 2E ... | clipped_hennesy_Page_243_Chunk5600 |
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