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246 Chapter 3 Arithmetic for Computers exponent range, its primary advantage is its greater precision because of the much larger significand. These formats go beyond MIPS. They are part of the IEEE 754 floating-point standard, found in virtually every computer invented since 1980. This standard has greatly improved bot... | clipped_hennesy_Page_244_Chunk5601 |
IEEE 754 even has a symbol for the result of invalid operations, such as 0/0 or subtracting infinity from infinity. This symbol is NaN, for Not a Number. The purpose of NaNs is to allow programmers to postpone some tests and decisions to a later time in the program when they are convenient. The designers of IEEE 754 al... | clipped_hennesy_Page_245_Chunk5602 |
248 Chapter 3 Arithmetic for Computers Let’s show the representation. Floating-Point Representation Show the IEEE 754 binary representation of the number -0.75ten in single and double precision. The number -0.75ten is also -3/4ten or -3/22 ten It is also represented by the binary fraction -11two/22 ten or -0.11two In s... | clipped_hennesy_Page_246_Chunk5603 |
The double precision representation is (-1)1 × (1 + .1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000two) × 2(1022-1023) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 bit 11 bits 20 bits 0 0 0 0 0 0... | clipped_hennesy_Page_247_Chunk5604 |
250 Chapter 3 Arithmetic for Computers on the significands, but extra bookkeeping is necessary to handle the exponents and normalize the result. We first give an intuitive derivation of the algorithms in decimal and then give a more detailed, binary version in the figures. Elaboration: In an attempt to increase range w... | clipped_hennesy_Page_248_Chunk5605 |
Step 3. This sum is not in normalized scientific notation, so we need to adjust it: 10.015ten × 101 = 1.0015ten × 102 Thus, after the addition we may have to shift the sum to put it into normalized form, adjusting the exponent appropriately. This example shows shifting to the right, but if one number were positive and ... | clipped_hennesy_Page_249_Chunk5606 |
252 Chapter 3 Arithmetic for Computers Still normalized? 4. Round the significand to the appropriate number of bits Yes Overflow or underflow? Start No Yes Done 1. Compare the exponents of the two numbers; shift the smaller number to the right until its exponent would match the larger exponent 2. Add the significands 3... | clipped_hennesy_Page_250_Chunk5607 |
Binary Floating-Point Addition Try adding the numbers 0.5ten and -0.4375ten in binary using the algorithm in Figure 3.15. Let’s first look at the binary version of the two numbers in normalized scien- tific notation, assuming that we keep 4 bits of precision: 0.5ten = 1/2ten = 1/21 ten = 0.1two = 0.1two × 20 = 1.000two... | clipped_hennesy_Page_251_Chunk5608 |
254 Chapter 3 Arithmetic for Computers Compare exponents Small ALU Exponent difference Control Exponent Sign Fraction Big ALU Exponent Sign Fraction 0 1 0 1 0 1 Shift right 0 1 0 1 Increment or decrement Shift left or right Rounding hardware Exponent Sign Fraction Shift smaller number right Add Normalize Round FIGURE 3... | clipped_hennesy_Page_252_Chunk5609 |
Floating-Point Multiplication Now that we have explained floating-point addition, let’s try floating-point multiplication. We start by multiplying decimal numbers in scientific notation by hand: 1.110ten × 1010 × 9.200ten × 10-5. Assume that we can store only four digits of the significand and two digits of the exponen... | clipped_hennesy_Page_253_Chunk5610 |
256 Chapter 3 Arithmetic for Computers Assuming that we can keep only three digits to the right of the decimal point, the product is 10.212 × 105. Step 3. This product is unnormalized, so we need to normalize it: 10.212ten × 105 = 1.0212ten × 106 Thus, after the multiplication, the product can be shifted right one digi... | clipped_hennesy_Page_254_Chunk5611 |
In binary, the task is multiplying 1.000two × 2-1 by - 1.110two × 2-2. Step 1. Adding the exponents without bias: -1 + (-2) = -3 or, using the biased representation: (-1 + 127) + (-2 + 127) - 127 = (-1 - 2) + (127 + 127 - 127) = -3 + 127 = 124 Step 2. Multiplying the significands: 1.000two x 1.110two 0000 1000 1000 100... | clipped_hennesy_Page_255_Chunk5612 |
258 Chapter 3 Arithmetic for Computers 5. Set the sign of the product to positive if the signs of the original operands are the same; if they differ make the sign negative Still normalized? 4. Round the significand to the appropriate number of bits Yes Overflow or underflow? Start No Yes Done 1. Add the biased exponent... | clipped_hennesy_Page_256_Chunk5613 |
Floating-Point Instructions in MIPS MIPS supports the IEEE 754 single precision and double precision formats with these instructions: ■ ■Floating-point addition, single (add.s) and addition, double (add.d) ■ ■Floating-point subtraction, single (sub.s) and subtraction, double (sub.d) ■ ■Floating-point multiplication, si... | clipped_hennesy_Page_257_Chunk5614 |
260 Chapter 3 Arithmetic for Computers MIPS floating-point operands Name Example Comments 32 floating- point registers $f0, $f1, $f2, . . . , $f31 MIPS floating-point registers are used in pairs for double precision numbers. 230 memory words Memory[0], Memory[4], . . . , Memory[4294967292] Accessed only by data transfe... | clipped_hennesy_Page_258_Chunk5615 |
op(31:26): 28–26 31–29 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111) 0(000) Rfmt Bltz/gez j jal beq bne blez bgtz 1(001) addi addiu slti sltiu ANDi ORi xORi lui 2(010) TLB FlPt 3(011) 4(100) lb lh lwl lw lbu lhu lwr 5(101) sb sh swl sw swr 6(110) lwc0 lwc1 7(111) swc0 swc1 op(31:26) = 010001 (FlPt), (rt(16:16... | clipped_hennesy_Page_259_Chunk5616 |
262 Chapter 3 Arithmetic for Computers One issue that architects face in supporting floating-point arithmetic is whether to use the same registers used by the integer instructions or to add a special set for floating point. Because programs normally perform integer operations and floating-point operations on different ... | clipped_hennesy_Page_260_Chunk5617 |
(Many compilers would divide 5.0 by 9.0 at compile time and save the single constant 5.0/9.0 in memory, thereby avoiding the divide at runtime.) Next, we load the constant 32.0 and then subtract it from fahr ($f12): lwc1 $f18, const32($gp)# $f18 = 32.0 sub.s $f18, $f12, $f18 # $f18 = fahr – 32.0 Finally, we multiply th... | clipped_hennesy_Page_261_Chunk5618 |
264 Chapter 3 Arithmetic for Computers The body of the procedure starts with saving the loop termination value of 32 in a temporary register and then initializing the three for loop variables: mm:... li $t1, 32 # $t1 = 32 (row size/loop end) li $s0, 0 # i = 0; initialize 1st for loop L1: li $s1, 0 # j = 0; restart 2nd ... | clipped_hennesy_Page_262_Chunk5619 |
sll $t0, $s0, 5 # $t0 = i * 25 (size of row of y) addu $t0, $t0, $s2 # $t0 = i * size(row) + k sll $t0, $t0, 3 # $t0 = byte offset of [i][k] addu $t0, $a1, $t0 # $t0 = byte address of y[i][k] l.d $f18, 0($t0) # $f18 = 8 bytes of y[i][k] Now that we have loaded all the data, we are finally ready to do some floating-poin... | clipped_hennesy_Page_263_Chunk5620 |
266 Chapter 3 Arithmetic for Computers Elaboration: Another reason for separate integers and floating-point registers is that microprocessors in the 1980s didn’t have enough transistors to put the floating-point unit on the same chip as the integer unit. Hence, the floating-point unit, including the floating- point reg... | clipped_hennesy_Page_264_Chunk5621 |
Rounding with Guard Digits Add 2.56ten × 100 to 2.34ten × 102, assuming that we have three significant decimal digits. Round to the nearest decimal number with three significant decimal digits, first with guard and round digits, and then without them. First we must shift the smaller number to the right to align the exp... | clipped_hennesy_Page_265_Chunk5622 |
268 Chapter 3 Arithmetic for Computers IEEE 754 has four rounding modes: always round up (toward +∞), always round down (toward – ∞), truncate, and round to nearest even. The final mode determines what to do if the number is exactly halfway in between. The U.S. Internal Revenue Service (IRS) always rounds 0.50 dollars ... | clipped_hennesy_Page_266_Chunk5623 |
Bit patterns have no inherent meaning. They may represent signed integers, unsigned integers, floating-point numbers, instructions, and so on. What is represented depends on the instruction that operates on the bits in the word. The major difference between computer numbers and numbers in the real world is that compute... | clipped_hennesy_Page_267_Chunk5624 |
270 Chapter 3 Arithmetic for Computers Elaboration: To accommodate comparisons that may include NaNs, the standard includes ordered and unordered as options for compares. Hence, the full MIPS instruction set has many flavors of compares to support NaNs. (Java does not support unordered compares.) In an attempt to squee... | clipped_hennesy_Page_268_Chunk5625 |
Given the great range of numbers that can be represented in floating point, problems occur when adding two large numbers of opposite signs plus a small number, as we shall see: x + (y + z) = -1.5ten × 1038 + (1.5ten × 1038 + 1.0) = -1.5ten × 1038 + (1.5ten × 1038) = 0.0 (x + y) + z = (-1.5ten × 1038 + 1.5ten × 1038) + ... | clipped_hennesy_Page_269_Chunk5626 |
272 Chapter 3 Arithmetic for Computers 3.7 Real Stuff: Floating Point in the x86 The x86 has regular multiply and divide instructions that operate entirely on its normal registers, unlike the reliance on separate Hi and Lo registers in MIPS. (In fact, later versions of the MIPS instruction set have added similar instru... | clipped_hennesy_Page_270_Chunk5627 |
The x86 floating-point operations can be divided into four major classes: 1. Data movement instructions, including load, load constant, and store 2. Arithmetic instructions, including add, subtract, multiply, divide, square root, and absolute value 3. Comparison, including instructions to send the result to the integer... | clipped_hennesy_Page_271_Chunk5628 |
274 Chapter 3 Arithmetic for Computers Instruction Operands Comment FADD Both operands in stack; result replaces top of stack. FADD ST(i) One source operand is ith register below the top of stack; result replaces the top of stack. FADD ST(i), ST One source operand is the top of stack; result replaces ith register below... | clipped_hennesy_Page_272_Chunk5629 |
Data transfer Arithmetic Compare MOV{A/U}{SS/PS/SD/ PD} xmm, mem/xmm ADD{SS/PS/SD/PD} xmm, mem/xmm CMP{SS/PS/SD/ PD} SUB{SS/PS/SD/PD} xmm, mem/xmm MOV {H/L} {PS/PD} xmm, mem/xmm MUL{SS/PS/SD/PD} xmm, mem/xmm DIV{SS/PS/SD/PD} xmm, mem/xmm SQRT{SS/PS/SD/PD} mem/xmm MAX {SS/PS/SD/PD} mem/xmm MIN{SS/PS/SD/PD} mem/xmm FIGUR... | clipped_hennesy_Page_273_Chunk5630 |
276 Chapter 3 Arithmetic for Computers 1111 1111 1111 1111 1111 1111 1111 1011two According to this fallacy, shifting right by two should divide by 4ten (22): 0011 1111 1111 1111 1111 1111 1111 1110two With a 0 in the sign bit, this result is clearly wrong. The value created by the shift right is actually 1,073,741,822... | clipped_hennesy_Page_274_Chunk5631 |
■ ■September 1994: A math professor at Lynchburg College in Virginia, Thomas Nicely, discovers the bug. After calling Intel technical support and getting no official reaction, he posts his discovery on the Internet. It quickly gained a following, and some pointed out that even small errors become big when multiplied by... | clipped_hennesy_Page_275_Chunk5632 |
278 Chapter 3 Arithmetic for Computers and word processor users need not worry. . . . There are maybe several dozen people that this would affect. So far, we’ve only heard from one. . . . [Only] theoretical mathematicians (with Pentium computers purchased before the summer) should be concerned.” What irked many was tha... | clipped_hennesy_Page_276_Chunk5633 |
MIPS core instructions Name Format MIPS arithmetic core Name Format add add R multiply mult R add immediate addi I multiply unsigned multu R add unsigned addu R divide div R add immediate unsigned addiu I divide unsigned divu R subtract sub R move from Hi mfhi R subtract unsigned subu R move from Lo mflo R AND AND R mo... | clipped_hennesy_Page_277_Chunk5634 |
280 Chapter 3 Arithmetic for Computers 3.9 Concluding Remarks A side effect of the stored-program computer is that bit patterns have no inherent meaning. The same bit pattern may represent a signed integer, unsigned integer, floating-point number, instruction, and so on. It is the instruction that operates on the word ... | clipped_hennesy_Page_278_Chunk5635 |
Remaining MIPS-32 Name Format Pseudo MIPS Name Format exclusive or (rs ⊕ rt) xor R absolute value abs rd,rs exclusive or immediate xori I negate (signed or unsigned) negs rd,rs shift right arithmetic sra R rotate left rol rd,rs,rt shift left logical variable sllv R rotate right ror rd,rs,rt shift right logical variable... | clipped_hennesy_Page_279_Chunk5636 |
282 Chapter 3 Arithmetic for Computers Core MIPS Name Integer Fl. pt. Arithmetic core + MIPS-32 Name Integer Fl. pt. add add 0.0% 0.0% FP add double add.d 0.0% 10.6% add immediate addi 0.0% 0.0% FP subtract double sub.d 0.0% 4.9% add unsigned addu 5.2% 3.5% FP multiply double mul.d 0.0% 15.0% add immediate unsigned add... | clipped_hennesy_Page_280_Chunk5637 |
Historical Perspective and Further Reading This section surveys the history of the floating point going back to von Neumann, including the surprisingly controversial IEEE standards effort, plus the rationale for the 80-bit stack architecture for floating point in the x86. See Section 3.10. 3.11 Exercises Contributed b... | clipped_hennesy_Page_281_Chunk5638 |
284 Chapter 3 Arithmetic for Computers 3.1.4 [5] <3.2> What is A – B if they represent unsigned 12-bit octal numbers? The result should be written in octal. Show your work. 3.1.5 [5] <3.2> What is A – B if they represent signed 12-bit octal numbers stored in sign-magnitude format? The result should be written in octal.... | clipped_hennesy_Page_282_Chunk5639 |
3.2.5 [5] <3.2> What is A – B if they represent signed 16-bit hexadecimal numbers stored in sign-magnitude format? The result should be written in hexa- decimal. Show your work. 3.2.6 [10] <3.2> Convert A into a binary number. What makes base 16 (hexa- decimal) an attractive numbering system for representing values in... | clipped_hennesy_Page_283_Chunk5640 |
286 Chapter 3 Arithmetic for Computers 3.3.6 [10] <3.2> Assume A and B are unsigned 8-bit integers. Calculate A + B using saturating arithmetic. The result should be written in decimal. Show your work. Exercise 3.4 Let’s look in more detail at multiplication. We will use the numbers in the follow- ing table. A B a. 62 ... | clipped_hennesy_Page_284_Chunk5641 |
right side (turning a shift into a rotate), or the value that is already in the leftmost bit can simply be retained (called an arithmetic shift right, because it preserves the sign of the number that is being shift). Using a table similar to that shown in Figure 3.7, calculate the product of the 6-bit two’s complement ... | clipped_hennesy_Page_285_Chunk5642 |
288 Chapter 3 Arithmetic for Computers Exercise 3.6 In this exercise we will look at a couple of other ways to improve the performance of multiplication, based primarily on doing more shifts and fewer arithmetic operations. The following table shows pairs of hexadecimal numbers. A B a. 33 55 b. 8a 6d 3.6.1 [20] <3.3> ... | clipped_hennesy_Page_286_Chunk5643 |
Exercise 3.7 Let’s look in more detail at division. We will use the octal numbers in the following table. A B a. 74 21 b. 76 52 3.7.1 [20] <3.4> Using a table similar to that shown in Figure 3.11, calculate A divided by B using the hardware described in Figure 3.9. You should show the con- tents of each register on eac... | clipped_hennesy_Page_287_Chunk5644 |
290 Chapter 3 Arithmetic for Computers 3.7.6 [60] <3.4> Write an MIPS assembly language program to calculate A divided by B, using the approach described in Figure 3.12. Assume A and B are signed integers. Exercise 3.8 Figure 3.10 describes a restoring division algorithm, because when subtracting the divisor from the ... | clipped_hennesy_Page_288_Chunk5645 |
3.8.5 [60] <3.4> Write an MIPS assembly language program to calculate A divided by B using nonperforming division. Assume A and B are 6-bit two’s com- plement signed integers. 3.8.6 [60] <3.4> How does the performance of non-restoring and nonperform- ing division compare? Demonstrate by showing the number of steps nec... | clipped_hennesy_Page_289_Chunk5646 |
292 Chapter 3 Arithmetic for Computers 3.10.3 [10] <3.5> What decimal number does the bit pattern represent if it is a floating point number? Use the IEEE 754 standard. The following table shows decimal numbers. a. 63.25 b. 146987.40625 3.10.4 [10] <3.5> Write down the binary representation of the decimal number, assum... | clipped_hennesy_Page_290_Chunk5647 |
A hidden 1 is assumed. Write down the bit pattern assuming a modified version of this format, which uses an excess-16 format to store the exponent. Comment on how the range and accuracy of this 16-bit floating point format compares to the single precision IEEE 754 standard. 3.11.3 [20] <3.5> The Hewlett-Packard 2114, 2... | clipped_hennesy_Page_291_Chunk5648 |
294 Chapter 3 Arithmetic for Computers A B a. –8.0546875 × 100 –1.79931640625 × 10–1 b. 8.59375 × 10–2 8.125 × 10–1 3.12.1 [30] <3.5> Calculate the product of A and B by hand, assuming A and B are stored in the modified 16-bit NVIDIA format described in 3.11.2. Assume 1 guard, 1 round bit, and 1 sticky bit, and round t... | clipped_hennesy_Page_292_Chunk5649 |
3.12.5 [60] <3.5> Write the loop in MIPS assembly language. 3.12.6 [60] <3.5> Describe in detail one technique for performing floating point division in a digital computer. Be sure to include references to the sources you used. Exercise 3.13 Operations performed on fixed-point integers behave the way one expects—the co... | clipped_hennesy_Page_293_Chunk5650 |
296 Chapter 3 Arithmetic for Computers 3.13.5 [30] <3.3, 3.5, 3.6> Calculate A × (B × C) by hand, assuming A, B, and C are stored in the modified 16-bit NVIDIA format described in 3.11.2 (and also described in the text). Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps, ... | clipped_hennesy_Page_294_Chunk5651 |
3.14.5 [10] <3.2, 3.3, 3.5, 3.6> What do you get if you add A to itself B times? What is A × B? Are they the same? What should they be? 3.14.6 [60] <3.2, 3.3, 3.4, 3.5, 3.6> What do you get if you take the square root of B and then multiply that value by itself? What should you get? Do for both single and double precis... | clipped_hennesy_Page_295_Chunk5652 |
4 In a major matter, no details are small. French Proverb The Processor 4.1 Introduction 300 4.2 Logic Design Conventions 303 4.3 Building a Datapath 307 4.4 A Simple Implementation Scheme 316 4.5 An Overview of Pipelining 330 4.6 Pipelined Datapath and Control 344 4.7 Data Hazards: Forwarding versus Stalling 363 4.8 ... | clipped_hennesy_Page_296_Chunk5653 |
4.10 Parallelism and Advanced Instruction-Level Parallelism 391 4.11 Real Stuff: the AMD Opteron X4 (Barcelona) Pipeline 404 4.12 Advanced Topic: an Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 406 4.13 Fallacies and Pitfalls 407 4.... | clipped_hennesy_Page_297_Chunk5654 |
300 Chapter 4 The Processor 4.1 Introduction Chapter 1 explains that the performance of a computer is determined by three key factors: instruction count, clock cycle time, and clock cycles per instruction (CPI). Chapter 2 explains that the compiler and the instruction set architecture determine the instruction count r... | clipped_hennesy_Page_298_Chunk5655 |
4.1 Introduction 301 This subset does not include all the integer instructions (for example, shift, multiply, and divide are missing), nor does it include any floating-point instructions. How- ever, the key principles used in creating a datapath and designing the control are illustrated. The implementation of the rema... | clipped_hennesy_Page_299_Chunk5656 |
302 Chapter 4 The Processor Figure 4.1 shows the high-level view of a MIPS implementation, focusing on the various functional units and their interconnection. Although this figure shows most of the flow of data through the processor, it omits two important aspects of instruction execution. FIGURE 4.1 An abstract view o... | clipped_hennesy_Page_300_Chunk5657 |
might better be called a data selector. Appendix C describes the multiplexor, which selects from among several inputs based on the setting of its control lines. The control lines are set based primarily on information taken from the instruction being executed. The second omission in Figure 4.1 is that several of the ... | clipped_hennesy_Page_301_Chunk5658 |
304 Chapter 4 The Processor you have little or no background in digital logic, you will find it helpful to read Appendix C before continuing. The datapath elements in the MIPS implementation consist of two different types of logic elements: elements that operate on data values and elements that contain state. The eleme... | clipped_hennesy_Page_302_Chunk5659 |
element. Given a set of inputs, it always produces the same output because it has no internal storage. Other elements in the design are not combinational, but instead contain state. An element contains state if it has some internal storage. We call these elements state elements because, if we pulled the power plug on t... | clipped_hennesy_Page_303_Chunk5660 |
306 Chapter 4 The Processor The inputs are values that were written in a previous clock cycle, while the outputs are values that can be used in a following clock cycle. Figure 4.3 shows the two state elements surrounding a block of combinational logic, which operates in a single clock cycle: all signals must propagate ... | clipped_hennesy_Page_304_Chunk5661 |
the chosen clock edge. With an edge-triggered timing methodology, there is no feedback within a single clock cycle, and the logic in Figure 4.4 works correctly. In Appendix C, we briefly discuss additional timing constraints (such as setup and hold times) as well as other timing methodologies. For the 32-bit MIPS archi... | clipped_hennesy_Page_305_Chunk5662 |
308 Chapter 4 The Processor operation. We will draw such an ALU with the label Add, as in Figure 4.5, to indicate that it has been permanently made an adder and cannot perform the other ALU functions. To execute any instruction, we must start by fetching the instruction from memory. To prepare for executing the next in... | clipped_hennesy_Page_306_Chunk5663 |
input to the register file that specifies the register number to be read and an output from the register file that will carry the value that has been read from the registers. To write a data word, we will need two inputs: one to specify the register number to be written and one to supply the data to be written into t... | clipped_hennesy_Page_307_Chunk5664 |
310 Chapter 4 The Processor In addition, we will need a unit to sign-extend the 16‑bit offset field in the instruction to a 32‑bit signed value, and a data memory unit to read from or write to. The data memory must be written on store instructions; hence, data memory has read and write control signals, an address input... | clipped_hennesy_Page_308_Chunk5665 |
■ ■The architecture also states that the offset field is shifted left 2 bits so that it is a word offset; this shift increases the effective range of the offset field by a factor of 4. To deal with the latter complication, we will need to shift the offset field by 2. As well as computing the branch target address, we m... | clipped_hennesy_Page_309_Chunk5666 |
312 Chapter 4 The Processor FIGURE 4.9 The datapath for a branch uses the ALU to evaluate the branch condition and a separate adder to compute the branch target as the sum of the incremented PC and the sign-extended, lower 16 bits of the instruction (the branch displacement), shifted left 2 bits. The unit labeled Shift... | clipped_hennesy_Page_310_Chunk5667 |
Elaboration: In the MIPS instruction set, branches are delayed, meaning that the instruction immediately following the branch is always executed, independent of whether the branch condition is true or false. When the condition is false, the execution looks like a normal branch. When the condition is true, a delayed b... | clipped_hennesy_Page_311_Chunk5668 |
314 Chapter 4 The Processor To create a datapath with only a single register file and a single ALU, we must support two different sources for the second ALU input, as well as two different sources for the data stored into the register file. Thus, one multiplexor is placed at the ALU input and another at the data input... | clipped_hennesy_Page_312_Chunk5669 |
ALU control is different in a number of ways, and it will be useful to design it first before we design the rest of the control unit. I. Which of the following is correct for a load instruction? Refer to Figure 4.10. a. MemtoReg should be set to cause the data from memory to be sent to the register file. b. MemtoReg sh... | clipped_hennesy_Page_313_Chunk5670 |
316 Chapter 4 The Processor b. having separate memories is less expensive. c. the processor operates in one cycle and cannot use a single-ported memory for two different accesses within that cycle 4.4 A Simple Implementation Scheme In this section, we look at what might be thought of as the simplest possible imple- men... | clipped_hennesy_Page_314_Chunk5671 |
that directly controls the ALU by generating one of the 4‑bit combinations shown previously. In Figure 4.12, we show how to set the ALU control inputs based on the 2‑bit ALUOp control and the 6‑bit function code. Later in this chapter we will see how the ALUOp bits are generated from the main control unit. Instruction ... | clipped_hennesy_Page_315_Chunk5672 |
318 Chapter 4 The Processor combinations, we show only the truth table entries for which the ALU control must have a specific value. Throughout this chapter, we will use this practice of showing only the truth table entries for outputs that must be asserted and not showing those that are all deasserted or don’t care. (... | clipped_hennesy_Page_316_Chunk5673 |
Field 0 rs rt rd shamt funct Bit positions 31:26 25:21 20:16 15:11 10:6 5:0 a. R-type instruction Field 35 or 43 rs rt address Bit positions 31:26 25:21 20:16 15:0 b. Load or store instruction Field 4 rs rt address Bit positions 31:26 25:21 20:16 15:0 c. Branch instruction FIGURE 4.14 The three instruction classes (R-t... | clipped_hennesy_Page_317_Chunk5674 |
320 Chapter 4 The Processor Using this information, we can add the instruction labels and extra multiplexor (for the Write register number input of the register file) to the simple datapath. Figure 4.15 shows these additions plus the ALU control block, the write signals for state elements, the read signal for the data ... | clipped_hennesy_Page_318_Chunk5675 |
Signal name Effect when deasserted Effect when asserted RegDst The register destination number for the Write register comes from the rt field (bits 20:16). The register destination number for the Write register comes from the rd field (bits 15:11). RegWrite None. The register on the Write register input is written with... | clipped_hennesy_Page_319_Chunk5676 |
322 Chapter 4 The Processor FIGURE 4.17 The simple datapath with the control unit. The input to the control unit is the 6‑bit opcode field from the instruction. The outputs of the control unit consist of three 1‑bit signals that are used to control multiplexors (RegDst, ALUSrc, and MemtoReg), three signals for control... | clipped_hennesy_Page_320_Chunk5677 |
Figure 4.19 shows the operation of the datapath for an R-type instruction, such as add $t1,$t2,$t3. Although everything occurs in one clock cycle, we can think of four steps to execute the instruction; these steps are ordered by the flow of information: 1. The instruction is fetched, and the PC is incremented. 2. Two r... | clipped_hennesy_Page_321_Chunk5678 |
324 Chapter 4 The Processor 3. The ALU computes the sum of the value read from the register file and the sign-extended, lower 16 bits of the instruction (offset). 4. The sum from the ALU is used as the address for the data memory. 5. The data from the memory unit is written into the register file; the register destinat... | clipped_hennesy_Page_322_Chunk5679 |
Finally, we can show the operation of the branch-on-equal instruction, such as beq $t1,$t2,offset, in the same fashion. It operates much like an R‑format instruction, but the ALU output is used to determine whether the PC is written with PC + 4 or the branch target address. Figure 4.21 shows the four steps in execution... | clipped_hennesy_Page_323_Chunk5680 |
326 Chapter 4 The Processor 3. The ALU performs a subtract on the data values read from the register file. The value of PC + 4 is added to the sign-extended, lower 16 bits of the instruction (offset) shifted left by two; the result is the branch target address. 4. The Zero result from the ALU is used to decide which ad... | clipped_hennesy_Page_324_Chunk5681 |
Finalizing Control Now that we have seen how the instructions operate in steps, let’s continue with the control implementation. The control function can be precisely defined using the contents of Figure 4.18. The outputs are the control lines, and the input is the 6‑bit opcode field, Op [5:0]. Thus, we can create a tru... | clipped_hennesy_Page_325_Chunk5682 |
328 Chapter 4 The Processor Implementing Jumps Figure 4.17 shows the implementation of many of the instructions we looked at in Chapter 2. One class of instructions missing is that of the jump instruction. Extend the datapath and control of Figure 4.17 to include the jump instruction. Describe how to set any new cont... | clipped_hennesy_Page_326_Chunk5683 |
the clock cycle is determined by the longest possible path in the processor. This path is almost certainly a load instruction, which uses five functional units in series: the instruction memory, the register file, the ALU, the data memory, and the register file. Although the CPI is 1 (see Chapter 1), the overall perfor... | clipped_hennesy_Page_327_Chunk5684 |
330 Chapter 4 The Processor The penalty for using the single-cycle design with a fixed clock cycle is significant, but might be considered acceptable for this small instruction set. Historically, early computers with very simple instruction sets did use this implementation technique. However, if we tried to implemen... | clipped_hennesy_Page_328_Chunk5685 |
The pipelined approach takes much less time, as Figure 4.25 shows. As soon as the washer is finished with the first load and placed in the dryer, you load the washer with the second dirty load. When the first load is dry, you place it on the table to start folding, move the wet load to the dryer, and the next dirty loa... | clipped_hennesy_Page_329_Chunk5686 |
332 Chapter 4 The Processor If all the stages take about the same amount of time and there is enough work to do, then the speed-up due to pipelining is equal to the number of stages in the pipeline, in this case four: washing, drying, folding, and putting away. There- fore, pipelined laundry is potentially four times f... | clipped_hennesy_Page_330_Chunk5687 |
Figure 4.26 shows the time required for each of the eight instructions. The single-cycle design must allow for the slowest instruction—in Figure 4.26 it is lw—so the time required for every instruction is 800 ps. Similarly to Figure 4.25, Figure 4.27 compares nonpipelined and pipelined execution of three load word ins... | clipped_hennesy_Page_331_Chunk5688 |
334 Chapter 4 The Processor Moreover, even our claim of fourfold improvement for our example is not reflected in the total execution time for the three instructions: it’s 1400 ps versus 2400 ps. Of course, this is because the number of instructions is not large. What would happen if we increased the number of instructi... | clipped_hennesy_Page_332_Chunk5689 |
Pipelining improves performance by increasing instruction throughput, as opposed to decreasing the execution time of an individual instruction, but instruction throughput is the important metric because real programs execute billions of instructions. Designing Instruction Sets for Pipelining Even with this simple expla... | clipped_hennesy_Page_333_Chunk5690 |
336 Chapter 4 The Processor As we said above, the MIPS instruction set was designed to be pipelined, making it fairly easy for designers to avoid structural hazards when designing a pipeline. Suppose, however, that we had a single memory instead of two memories. If the pipeline in Figure 4.27 had a fourth instruction... | clipped_hennesy_Page_334_Chunk5691 |
Figure 4.29 shows the connection to forward the value in $s0 after the execu tion stage of the add instruction as input to the execution stage of the sub instruction. ANSWER FIGURE 4.28 Graphical representation of the instruction pipeline, similar in spirit to the laundry pipeline in Figure 4.25. Here we use symbols r... | clipped_hennesy_Page_335_Chunk5692 |
338 Chapter 4 The Processor load of $s0 instead of an add. As we can imagine from looking at Figure 4.29, the desired data would be available only after the fourth stage of the first instruction in the dependence, which is too late for the input of the third stage of sub. Hence, even with forwarding, we would have to ... | clipped_hennesy_Page_336_Chunk5693 |
lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1,$t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1,$t4 sw $t5, 16($t0) Find the hazards in the preceding code segment and reorder the instructions to avoid any pipeline stalls. Both add instructions have a hazard because of their respective dependence on the immediately preceding... | clipped_hennesy_Page_337_Chunk5694 |
340 Chapter 4 The Processor pipeline, we have to wait until the second stage to examine the dry uniform to see if we need to change the washer setup or not. What to do? Here is the first of two solutions to control hazards in the laundry room and its computer equivalent. Stall: Just operate sequentially until the first... | clipped_hennesy_Page_338_Chunk5695 |
Performance of “Stall on Branch” Estimate the impact on the clock cycles per instruction (CPI) of stalling on branches. Assume all other instructions have a CPI of 1. Figure 3.27 in Chapter 3 shows that branches are 17% of the instructions executed in SPECint2006. Since the other instructions run have a CPI of 1, and b... | clipped_hennesy_Page_339_Chunk5696 |
342 Chapter 4 The Processor One popular approach to dynamic prediction of branches is keeping a history for each branch as taken or untaken, and then using the recent past behavior to predict the future. As we will see later, the amount and type of history kept have become extensive, with the result being that dynamic ... | clipped_hennesy_Page_340_Chunk5697 |
Elaboration: There is a third approach to the control hazard, called delayed decision mentioned above. In our analogy, whenever you are going to make such a decision about laundry, just place a load of nonfootball clothes in the washer while waiting for football uniforms to dry. As long as you have enough dirty clothes... | clipped_hennesy_Page_341_Chunk5698 |
344 Chapter 4 The Processor Outside the memory system, the effective operation of the pipeline is usually the most important factor in determining the CPI of the processor and hence its performance. As we will see in Section 4.10, understanding the performance of a modern multiple-issue pipelined processor is complex a... | clipped_hennesy_Page_342_Chunk5699 |
pipeline, which in turn means that up to five instructions will be in execution during any single clock cycle. Thus, we must separate the datapath into five pieces, with each piece named corresponding to a stage of instruction execution: 1. IF: Instruction fetch 2. ID: Instruction decode and register file read 3. EX: E... | clipped_hennesy_Page_343_Chunk5700 |
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