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A-44 Appendix A Graphics and Computing GPUs values of the attributes at each pixel location. The value of a given attribute U in an (x,y) plane can be expressed using plane equations of the form: U(x,y) = Aux + Buy + Cu where A, B, and C are interpolation parameters associated with each attribute U. The interpolation p... | clipped_hennesy_Page_744_Chunk6101 |
Double precision Newer GPUs such as the Tesla T10P also support IEEE 754 64-bit double precision operations in hardware. Standard floating-point arithmetic operations in double precision include addition, multiplication, and conversions between different floating-point and integer formats. The 2008 IEEE 754 floating-p... | clipped_hennesy_Page_745_Chunk6102 |
A-46 Appendix A Graphics and Computing GPUs precision FMA unit enables full-speed denormalized number support on both inputs and outputs. Figure A.6.2 shows a block diagram of an FMA unit. As shown in Figure A.6.2, the significands of A and B are multiplied to form a 106-bit product, with the results left in carry-save... | clipped_hennesy_Page_746_Chunk6103 |
Texture/Processor Cluster (TPC) Each TPC contains a geometry controller, an SM controller (SMC), two streaming multiprocessors (SMs), and a texture unit as shown in Figure A.7. 2. The geometry controller maps the logical graphics vertex pipeline into recir- culation on the physical SMs by directing all primitive and ve... | clipped_hennesy_Page_747_Chunk6104 |
A-48 Appendix A Graphics and Computing GPUs contains a streaming cache to capture filtering locality, it streams hits mixed with misses without stalling. Streaming Multiprocessor (SM) The SM is a unified graphics and computing multiprocessor that executes vertex, geometry, and pixel-fragment shader programs and paralle... | clipped_hennesy_Page_748_Chunk6105 |
To efficiently execute hundreds of parallel threads while running several different programs, the SM is hardware multithreaded. It manages and executes up to 768 concurrent threads in hardware with zero scheduling overhead. Each thread has its own thread execution state and can execute an independent code path. A warp ... | clipped_hennesy_Page_749_Chunk6106 |
add and multiply operations are compatible with the IEEE 754 standard for single precision FP numbers, including not-a-number (NaN) and infinity. The add and multiply operations use IEEE round-to-nearest-even as the default rounding mode. The SP core also implements all of the 32-bit and 64-bit integer arithmetic, comp... | clipped_hennesy_Page_750_Chunk6107 |
Antialiasing support includes up to 16× multisampling and supersampling. The coverage-sampling antialiasing (CSAA) algorithm computes and stores Boolean coverage at up to 16 samples and compresses redundant color, depth, and stencil information into the memory footprint and a bandwidth of four or eight samples for impr... | clipped_hennesy_Page_751_Chunk6108 |
FIGURE A.7.3 SGEMM dense matrix-matrix multiplication performance rates. The graph shows single precision GFLOPS rates achieved in multiplying square N×N matrices (solid lines) and thin N×64 and 64×N matrices (dashed lines). Adapted from Figure 6 of Volkov and Demmel [2008]. The black lines are a 1.35 GHz GeForce 8800 ... | clipped_hennesy_Page_752_Chunk6109 |
problem becomes large enough that SGEMM can leverage the GPU parallelism and overcome the CPU–GPU system and copy overhead. Volkov’s SGEMM matrix- matrix multiply achieves 206 GFLOPS, about 60% of the GeForce 8800 GTX peak multiply-add rate, while the QR factorization reached 192 GFLOPS, about 4.3 times the quad-core C... | clipped_hennesy_Page_753_Chunk6110 |
Sorting Performance In contrast to the applications just discussed, sort requires far more substantial coordination among parallel threads, and parallel scaling is correspondingly harder to obtain. Nevertheless, a variety of well-known sorting algorithms can be efficiently parallelized to run well on the GPU. Satish, e... | clipped_hennesy_Page_754_Chunk6111 |
from this graph that the GPU radix sort achieved the highest sorting rate for all sequences of 8K-elements and larger. In this range, it is on average 2.6 times faster than the quicksort-based routine and roughly 2 times faster than the radix sort rou- tines, all of which were using the eight available CPU cores. The ... | clipped_hennesy_Page_755_Chunk6112 |
Given a matrix A in CSR form and a vector x, we can compute a single row of the product y = Ax using the multiply_row() procedure shown in Figure A.8.2. Computing the full product is then simply a matter of looping over all rows and computing the result for that row using multiply_row(), as in the serial C code shown i... | clipped_hennesy_Page_756_Chunk6113 |
void csrmul_serial(unsigned int *Ap, unsigned int *Aj, float *Av, unsigned int num_rows, float *x, float *y) { for(unsigned int row=0; row<num_rows; ++row) { unsigned int row_begin = Ap[row]; unsigned int row_end = Ap[row+1]; y[row] = multiply_row(row_end-row_begin, Aj+row_begin, Av+row_begin, x); } } FIGURE A.8.3 Seri... | clipped_hennesy_Page_757_Chunk6114 |
A-58 Appendix A Graphics and Computing GPUs The pattern that we see here is a very common one. The original serial algorithm is a loop whose iterations are independent of each other. Such loops can be parallelized quite easily by simply assigning one or more iterations of the loop to each parallel thread. The programmi... | clipped_hennesy_Page_758_Chunk6115 |
__global__ void csrmul_cached(unsigned int *Ap, unsigned int *Aj, float *Av, unsigned int num_rows, const float *x, float *y) { // Cache the rows of x[] corresponding to this block. __shared__ float cache[blocksize]; unsigned int block_begin = blockIdx.x * blockDim.x; unsigned int block_end = block_begin + blockDim.x; ... | clipped_hennesy_Page_759_Chunk6116 |
These are fairly simple kernels whose purpose is to illustrate basic techniques in writing CUDA programs, rather than how to achieve maximal performance. Numerous possible avenues for optimization are available, several of which are explored by Williams, et al. [2007] on a handful of different multicore architectures. ... | clipped_hennesy_Page_760_Chunk6117 |
because addition is associative, we are free to change the order in which elements are added together. For instance, we can imagine adding pairs of consecutive elements in parallel, and then adding these partial sums, and so on. One simple scheme for doing this is from Hillis and Steele [1989]. An implementation of the... | clipped_hennesy_Page_761_Chunk6118 |
A-62 Appendix A Graphics and Computing GPUs While simple, this algorithm is not as efficient as we would like. Examining the serial implementation, we see that it performs O(n) additions. The parallel implementation, in contrast, performs O(n log n) additions. For this reason, it is not work efficient, since it does mo... | clipped_hennesy_Page_762_Chunk6119 |
__global__ void plus_reduce(int *input, unsigned int N, int *total) { unsigned int tid = threadIdx.x; unsigned int i = blockIdx.x*blockDim.x + threadIdx.x; // Each block loads its elements into shared memory, padding // with 0 if N is not a multiple of blocksize __shared__ int x[blocksize]; x[tid] = (i<N) ? input[i] : ... | clipped_hennesy_Page_763_Chunk6120 |
A-64 Appendix A Graphics and Computing GPUs all values with a 0 in the designated bit will come before all values with a 1 in that bit. To produce the correct output, this partitioning must be stable. Implementing the partitioning procedure is a simple application of scan. Thread i holds the value xi and must calculate... | clipped_hennesy_Page_764_Chunk6121 |
A similar strategy can be applied for implementing a radix sort kernel that sorts an array of large length, rather than just a one-block array. The fundamental step remains the scan procedure, although when the computation is partitioned across multiple kernels, we must double-buffer the array of values rather than doi... | clipped_hennesy_Page_765_Chunk6122 |
void accel_on_all_bodies() { int i, j; float3 acc(0.0f, 0.0f, 0.0f); for (i = 0; i < N; i++) { for (j = 0; j < N; j++) { acc = body_body_interaction(acc, body[i], body[j]); } accel[i] = acc; } } FIGURE A.8.12 Serial code to compute all pair-wise forces on N bodies. __global__ void accel_on_one_body() { int i = threadId... | clipped_hennesy_Page_766_Chunk6123 |
The outer loop is replaced by a CUDA kernel grid that launches N threads, one for each body. Optimization for GPU Execution The CUDA code shown is functionally correct, but is not efficient, as it ignores key architectural features. Better performance can be achieved with three main optimizations. First, shared memory ... | clipped_hennesy_Page_767_Chunk6124 |
The loop that formerly iterated over all bodies now jumps by the block dimension p. Each iteration of the outer loop loads p successive positions into shared memory (one position per thread). The threads synchronize, and then p force calculations are computed by each thread. A second synchronization is required to ensu... | clipped_hennesy_Page_768_Chunk6125 |
done, the q partial results can be collected and summed to compute the final result. Using two or four threads per body leads to large improvements for small N. As an example, the performance on the 8800 GTX jumps by 110% when N = 1024 (one thread achieves 90 GFLOPS, where four achieve 190 GFLOPS). Performance degrades... | clipped_hennesy_Page_769_Chunk6126 |
The graph also shows the results of compiling the CUDA version of the code for a CPU, where the performance improves by 24%. CUDA, as a programming language, exposes parallelism, allowing the compiler to make better use of the SSE vector unit on a single core. The CUDA version of the N-body code naturally maps to multi... | clipped_hennesy_Page_770_Chunk6127 |
On a GeForce 8800, the all-pairs N-body algorithm delivers more than 240 GFLOPS of performance, compared to less than 2 GFLOPS on recent sequential processors. Compiling and executing the CUDA version of the code on a CPU demonstrates that the problem scales well to multicore CPUs, but is still significantly slower tha... | clipped_hennesy_Page_771_Chunk6128 |
spherical shell of bodies rotating about the z-axis. One phenomenon of interest to astrophysicists is the clustering that occurs, along with the merging of galaxies over time. For the interested reader, the CUDA code for this application is available in the CUDA SDK from www.nvidia.com/CUDA. A.9 Fallacies and Pitfalls... | clipped_hennesy_Page_772_Chunk6129 |
exponentially. Put another way, given a constant manufacturing cost, the number of transistors will increase exponentially. Gordon Moore [1965] predicted that this progression would provide roughly two times the number of transistors for the same manufacturing cost every year, and later revised it to doubling every two... | clipped_hennesy_Page_773_Chunk6130 |
However, there is nothing preventing GPU architects from exposing the parallel processor cores to programmers without the graphics API or the arcane graphics languages. In fact, the Tesla architecture family of GPUs exposes the processors through a software environment known as CUDA, which allows programmers to develop... | clipped_hennesy_Page_774_Chunk6131 |
without stalling. Memory latency is long, so it is avoided by striving to run in the cache. At some point, program working set demands may be larger than any cache. Some CPUs have used multithreading to tolerate latency, but the number of threads per core has generally been limited to a small number. The GPU strategy i... | clipped_hennesy_Page_775_Chunk6132 |
A.10 Concluding Remarks GPUs are massively parallel processors and have become widely used, not only for 3D graphics, but also for many other applications. This wide application was made possible by the evolution of graphics devices into programmable processors. The graphics application programming model for GPUs is us... | clipped_hennesy_Page_776_Chunk6133 |
Historical Perspective and Further Reading This section, which appears on the CD, surveys the history of programmable real- time graphics processing units (GPUs) from the early 1980s through today as they declined in price by two orders of magnitude and increased in performance by two orders of magnitude. It traces th... | clipped_hennesy_Page_777_Chunk6134 |
B Fear of serious injury cannot alone justify suppression of free speech and assembly. Louis Brandeis Whitney v. California, 1927 Assemblers, Linkers, and the SPIM Simulator James R. Larus Microsoft Research Microsoft A P P E N D I X | clipped_hennesy_Page_778_Chunk6135 |
B.1 Introduction B-3 B.2 Assemblers B-10 B.3 Linkers B-18 B.4 Loading B-19 B.5 Memory Usage B-20 B.6 Procedure Call Convention B-22 B.7 Exceptions and Interrupts B-33 B.8 Input and Output B-38 B.9 SPIM B-40 B.10 MIPS R2000 Assembly Language B-45 B.11 Concluding Remarks B-81 B.12 Exercises B-82 B.1 Introduction Encoding... | clipped_hennesy_Page_779_Chunk6136 |
B-4 Appendix B Assemblers, Linkers, and the SPIM Simulator FIGURE B.1.1 The process that produces an executable file. An assembler translates a file of assembly language into an object file, which is linked with other files and libraries into an executable file. Object file Source file Assembler Linker Assembler Assemb... | clipped_hennesy_Page_780_Chunk6137 |
B.1 Introduction B-5 easier to read, because operations and operands are written with symbols rather than with bit patterns. However, this assembly language is still difficult to follow, because memory locations are named by their address rather than by a symbolic label. Figure B.1.4 shows assembly language that labels... | clipped_hennesy_Page_781_Chunk6138 |
B-6 Appendix B Assemblers, Linkers, and the SPIM Simulator high-level language (such as C or Pascal) into an equivalent program in machine or assembly language. The high-level language is called the source language, and the compiler’s output is its target language. Assembly language’s other role is as a language in wh... | clipped_hennesy_Page_782_Chunk6139 |
B.1 Introduction B-7 When to Use Assembly Language The primary reason to program in assembly language, as opposed to an available high-level language, is because the speed or size of a program is critically important. For example, consider a computer that controls a piece of machinery, such as a car’s brakes. A compute... | clipped_hennesy_Page_783_Chunk6140 |
B-8 Appendix B Assemblers, Linkers, and the SPIM Simulator uncertainty about the time cost of operations, programmers may find it difficult to ensure that a high-level language program responds within a definite time interval—say, 1 millisecond after a sensor detects that a tire is skidding. An assembly language progra... | clipped_hennesy_Page_784_Chunk6141 |
B.1 Introduction B-9 This improvement is not necessarily an indication that the high-level language’s compiler has failed. Compilers typically are better than programmers at produc- ing uniformly high-quality machine code across an entire program. Programmers, however, understand a program’s algorithms and behavior a... | clipped_hennesy_Page_785_Chunk6142 |
B-10 Appendix B Assemblers, Linkers, and the SPIM Simulator To compound the problem, longer programs are more difficult to read and understand, and they contain more bugs. Assembly language exacerbates the prob lem because of its complete lack of structure. Common programming idioms, such as if-then statements and loo... | clipped_hennesy_Page_786_Chunk6143 |
be referenced from files other than the one in which it is defined. A label is local if the object can be used only within the file in which it is defined. In most assem blers, labels are local by default and must be explicitly declared global. Subroutines and global variables require external labels since they are r... | clipped_hennesy_Page_787_Chunk6144 |
B-12 Appendix B Assemblers, Linkers, and the SPIM Simulator An assembler’s first pass reads each line of an assembly file and breaks it into its component pieces. These pieces, which are called lexemes, are individual words, numbers, and punctuation characters. For example, the line ble $t0, 100, loop contains six lexe... | clipped_hennesy_Page_788_Chunk6145 |
Elaboration: If an assembler’s speed is important, this two-step process can be done in one pass over the assembly file with a technique known as backpatching. In its pass over the file, the assembler builds a (possibly incomplete) binary representation of every instruction. If the instruction references a label that h... | clipped_hennesy_Page_789_Chunk6146 |
B-14 Appendix B Assemblers, Linkers, and the SPIM Simulator This relocation information is necessary because the assembler does not know which memory locations a procedure or piece of data will occupy after it is linked with the rest of the program. Procedures and data from a file are stored in a con- tiguous piece of ... | clipped_hennesy_Page_790_Chunk6147 |
specify data in a human-readable form that the assembler translates to binary. Other layout directives are described in Section B.10. String Directive Define the sequence of bytes produced by this directive: .asciiz “The quick brown fox jumps over the lazy dog” .byte 84, 104, 101, 32, 113, 117, 105, 99 .byte 107, 32, 9... | clipped_hennesy_Page_791_Chunk6148 |
B-16 Appendix B Assemblers, Linkers, and the SPIM Simulator mov $a1, $7 # Load value into # second arg jal printf # Call the printf routine The .data directive tells the assembler to store the string in the program’s data segment, and the .text directive tells the assembler to store the instruc tions in its text segme... | clipped_hennesy_Page_792_Chunk6149 |
la $a0, int_str mov $a1, $a0 jal printf This example illustrates a drawback of macros. A programmer who uses this macro must be aware that print_int uses register $a0 and so cannot correctly print the value in that register. Some assemblers also implement pseudoinstructions, which are instructions pro vided by an asse... | clipped_hennesy_Page_793_Chunk6150 |
B-18 Appendix B Assemblers, Linkers, and the SPIM Simulator B.3 Linkers Separate compilation permits a program to be split into pieces that are stored in different files. Each file contains a logically related collection of subroutines and data structures that form a module in a larger program. A file can be compiled a... | clipped_hennesy_Page_794_Chunk6151 |
the assembler could not know where a module’s instructions or data would be placed relative to other modules. When the linker places a module in memory, all absolute references must be relocated to reflect its true location. Since the linker has relocation information that identifies all relocatable references, it can... | clipped_hennesy_Page_795_Chunk6152 |
B-20 Appendix B Assemblers, Linkers, and the SPIM Simulator system kernel brings a program into memory and starts it running. To start a program, the operating system performs the following steps: 1. It reads the executable file’s header to determine the size of the text and data segments. 2. It creates a new address s... | clipped_hennesy_Page_796_Chunk6153 |
FIGURE B.5.1 Layout of memory. Dynamic data Static data Reserved Stack segment Data segment Text segment 7fff fffchex 10000000hex 400000hex Because the data segment begins far above the program at address 10000000hex, load and store instructions cannot directly reference data objects with their 16-bit offset fields (se... | clipped_hennesy_Page_797_Chunk6154 |
B-22 Appendix B Assemblers, Linkers, and the SPIM Simulator finds and returns a new block of memory. Since a compiler cannot predict how much memory a program will allocate, the operating system expands the dynamic data area to meet demand. As the upward arrow in the figure indicates, malloc expands the dynamic area wi... | clipped_hennesy_Page_798_Chunk6155 |
■ ■Registers $t0–$t9 (8–15, 24, 25) are caller-saved registers that are used to hold temporary quantities that need not be preserved across calls (see Section 2.8 in Chapter 2). ■ ■Registers $s0–$s7 (16–23) are callee-saved registers that hold long-lived values that should be preserved across calls. ■ ■Register $gp (28... | clipped_hennesy_Page_799_Chunk6156 |
B-24 Appendix B Assemblers, Linkers, and the SPIM Simulator stack pointer. The executing procedure uses the frame pointer to quickly access values in its stack frame. For example, an argument in the stack frame can be loaded into register $v0 with the instruction lw $v0, 0($fp) Register name Number Usage $zero 0 consta... | clipped_hennesy_Page_800_Chunk6157 |
A stack frame may be built in many different ways; however, the caller and callee must agree on the sequence of steps. The steps below describe the calling convention used on most MIPS machines. This convention comes into play at three points during a procedure call: immediately before the caller invokes the callee, ju... | clipped_hennesy_Page_801_Chunk6158 |
B-26 Appendix B Assemblers, Linkers, and the SPIM Simulator Before a called routine starts running, it must take the following steps to set up its stack frame: 1. Allocate memory for the frame by subtracting the frame’s size from the stack pointer. 2. Save callee-saved registers in the frame. A callee must save the val... | clipped_hennesy_Page_802_Chunk6159 |
to the active stack frame, which permits a single load or store instruction to access values in the frame. In addition, recursion is a valuable programming technique. Procedure Call Example As an example, consider the C routine main () { printf (“The factorial of 10 is %d\n”, fact (10)); } int fact (int n) { if (n < 1... | clipped_hennesy_Page_803_Chunk6160 |
B-28 Appendix B Assemblers, Linkers, and the SPIM Simulator li $a0,10 # Put argument (10) in $a0 jal fact # Call factorial function la $a0,$LC # Put format string in $a0 move $a1,$v0 # Move fact result to $a1 jal printf # Call the print function Finally, after printing the factorial, main returns. But first, it must re... | clipped_hennesy_Page_804_Chunk6161 |
jal fact # Call factorial function lw $v1,0($fp) # Load n mul $v0,$v0,$v1 # Compute fact(n-1) * n Finally, the factorial routine restores the callee-saved registers and returns the value in register $v0: $L1: # Result is in $v0 lw $ra, 20($sp) # Restore $ra lw $fp, 16($sp) # Restore $fp addiu $sp, $sp, 32 # Pop stack j... | clipped_hennesy_Page_805_Chunk6162 |
B-30 Appendix B Assemblers, Linkers, and the SPIM Simulator ANSWER Elaboration: The difference between the MIPS compiler and the gcc compiler is that the MIPS compiler usually does not use a frame pointer, so this register is available as another callee-saved register, $s8. This change saves a couple of instructions in... | clipped_hennesy_Page_806_Chunk6163 |
lifetime of the function, which includes several calls that could potentially modify registers. .text .globl tak tak: subu $sp, $sp, 40 sw $ra, 32($sp) sw $s0, 16($sp) # x move $s0, $a0 sw $s1, 20($sp) # y move $s1, $a1 sw $s2, 24($sp) # z move $s2, $a2 sw $s3, 28($sp) # temporary The routine then begins execution by t... | clipped_hennesy_Page_807_Chunk6164 |
B-32 Appendix B Assemblers, Linkers, and the SPIM Simulator addiu $a0, $s2, -1 move $a1, $s0 move $a2, $s1 move $s0, $v0 jal tak # tak (z - 1, x, y) After the three inner recursive calls, we are ready for the final recursive call. After the call, the function’s result is in $v0 and control jumps to the function’s epilo... | clipped_hennesy_Page_808_Chunk6165 |
li $a2, 6 jal tak # tak(18, 12, 6) move $a0, $v0 li $v0, 1 # print_int syscall syscall lw $ra, 16($sp) addiu $sp, $sp, 24 jr $ra B.7 Exceptions and Interrupts Section 4.9 of Chapter 4 describes the MIPS exception facility, which responds both to exceptions caused by errors during an instruction’s execution and to exter... | clipped_hennesy_Page_809_Chunk6166 |
B-34 Appendix B Assemblers, Linkers, and the SPIM Simulator These seven registers are part of coprocessor 0’s register set. They are accessed by the mfc0 and mtc0 instructions. After an exception, register EPC contains the address of the instruction that was executing when the exception occurred. If the exception was c... | clipped_hennesy_Page_810_Chunk6167 |
is raised at a given hardware or software level. The exception code register describes the cause of an exception through the following codes: Number Name Cause of exception 0 Int interrupt (hardware) 4 AdEL address error exception (load or instruction fetch) 5 AdES address error exception (store) 6 IBE bus error on ins... | clipped_hennesy_Page_811_Chunk6168 |
B-36 Appendix B Assemblers, Linkers, and the SPIM Simulator such as page faults are requests from a process to the operating system to perform a service, such as bringing in a page from disk. The operating system processes these requests and resumes the process. The final type of exceptions are interrupts from external... | clipped_hennesy_Page_812_Chunk6169 |
mfc0 $k0, $13 # Move Cause into $k0 srl $a0, $k0, 2 # Extract ExcCode field andi $a0, $a0, Oxf bgtz $a0, done # Branch if ExcCode is Int (0) mov $a0, $k0 # Move Cause into $a0 mfco $a1, $14 # Move EPC into $a1 jal print_excp # Print exception error message Before returning, the exception handler clears the Cause regist... | clipped_hennesy_Page_813_Chunk6170 |
B-38 Appendix B Assemblers, Linkers, and the SPIM Simulator Elaboration: On real MIPS processors, the return from an exception handler is more complex. The exception handler cannot always jump to the instruction following EPC. For example, if the instruction that caused the exception was in a branch instruction’s delay... | clipped_hennesy_Page_814_Chunk6171 |
Bit 1 of the Receiver Control register is the keyboard “interrupt enable.” This bit may be both read and written by a program. The interrupt enable is initially 0. If it is set to 1 by a program, the terminal requests an interrupt at hardware level 1 whenever a character is typed, and the ready bit becomes 1. However, ... | clipped_hennesy_Page_815_Chunk6172 |
B-40 Appendix B Assemblers, Linkers, and the SPIM Simulator and is read-only. If this bit is 1, the transmitter is ready to accept a new character for output. If it is 0, the transmitter is still busy writing the previous character. Bit 1 is “interrupt enable’’ and is readable and writable. If this bit is set to 1, the... | clipped_hennesy_Page_816_Chunk6173 |
MIPS programs. It contains a debugger and provides a few operating system–like services. SPIM is much slower than a real computer (100 or more times). However, its low cost and wide availability cannot be matched by real hardware! An obvious question is, “Why use a simulator when most people have PCs that contain proc... | clipped_hennesy_Page_817_Chunk6174 |
B-42 Appendix B Assemblers, Linkers, and the SPIM Simulator By default, SPIM simulates the richer virtual machine, since this is the machine that most programmers will find useful. However, SPIM can also simulate the delayed branches and loads in the actual hardware. Below, we describe the virtual machine and only ment... | clipped_hennesy_Page_818_Chunk6175 |
Another surprise (which occurs on the real machine as well) is that a pseudo- instruction expands to several machine instructions. When you single-step or exam ine memory, the instructions that you see are different from the source program. The correspondence between the two sets of instructions is fairly simple, sinc... | clipped_hennesy_Page_819_Chunk6176 |
B-44 Appendix B Assemblers, Linkers, and the SPIM Simulator li $v0, 4 # system call code for print_str la $a0, str # address of string to print syscall # print the string li $v0, 1 # system call code for print_int li $a0, 5 # integer to print syscall # print it The print_int system call is passed an integer and prints ... | clipped_hennesy_Page_820_Chunk6177 |
Warning: Programs that use these syscalls to read from the terminal should not use memory-mapped I/O (see Section B.8). sbrk returns a pointer to a block of memory containing n additional bytes. exit stops the program SPIM is running. exit2 terminates the SPIM program, and the argument to exit2 becomes the value retur... | clipped_hennesy_Page_821_Chunk6178 |
B-46 Appendix B Assemblers, Linkers, and the SPIM Simulator object must be stored at even addresses, and a full word object must be stored at addresses that are a multiple of four. However, MIPS provides some instructions to manipulate unaligned data (lwl, lwr, swl, and swr). Elaboration: The MIPS assembler (and SPIM) ... | clipped_hennesy_Page_822_Chunk6179 |
lui $at, 4096 addu $at, $at, $a1 lw $a0, 8($at) The first instruction loads the upper bits of the label’s address into register $at, which is the register that the assembler reserves for its own use. The second instruction adds the contents of register $a1 to the label’s partial address. Finally, the load instruction u... | clipped_hennesy_Page_823_Chunk6180 |
B-48 Appendix B Assemblers, Linkers, and the SPIM Simulator .asciiz str Store the string str in memory and null-terminate it. .byte b1,..., bn Store the n values in successive bytes of memory. .data <addr> Subsequent items are stored in the data segment. If the optional argument addr is present, subse quent items are... | clipped_hennesy_Page_824_Chunk6181 |
.text <addr> Subsequent items are put in the user text segment. In SPIM, these items may only be instructions or words (see the .word directive below). If the optional argument addr is present, subsequent items are stored starting at address addr. .word w1,..., wn Store the n 32-bit quantities in successive memory... | clipped_hennesy_Page_825_Chunk6182 |
B-50 Appendix B Assemblers, Linkers, and the SPIM Simulator FIGURE B.10.2 MIPS opcode map. The values of each field are shown to its left. The first column shows the values in base 10, and the second shows base 16 for the op field (bits 31 to 26) in the third column. This op field completely specifies the MIPS operatio... | clipped_hennesy_Page_826_Chunk6183 |
mov.f neg.f round.w.f trunc.w.f cell.w.f floor.w.f movz.f movn.f 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 clz clo funct(5:0) madd maddu mul msub msubu (16:16) movf movt 0 1 (16:16... | clipped_hennesy_Page_826_Chunk6184 |
Pseudoinstructions follow roughly the same conventions, but omit instruction encoding information. For example: Multiply (without overflow) mul rdest, rsrc1, src2 pseudoinstruction In pseudoinstructions, rdest and rsrc1 are registers and src2 is either a regis ter or an immediate value. In general, the assembler and S... | clipped_hennesy_Page_827_Chunk6185 |
B-52 Appendix B Assemblers, Linkers, and the SPIM Simulator AND and rd, rs, rt 0 rs rt rd 0 0x24 6 5 5 5 5 6 Put the logical AND of registers rs and rt into register rd. AND immediate andi rt, rs, imm 0xc rs rt imm 6 5 5 16 Put the logical AND of register rs and the zero-extended immediate into reg- ister rt. Count lea... | clipped_hennesy_Page_828_Chunk6186 |
Divide (with overflow) div rdest, rsrc1, src2 pseudoinstruction Divide (without overflow) divu rdest, rsrc1, src2 pseudoinstruction Put the quotient of register rsrc1 and src2 into register rdest. Multiply mult rs, rt 0 rs rt 0 0x18 6 5 5 10 6 Unsigned multiply multu rs, rt 0 rs rt 0 0x19 6 5 5 10 6 Multiply registers ... | clipped_hennesy_Page_829_Chunk6187 |
B-54 Appendix B Assemblers, Linkers, and the SPIM Simulator Multiply add madd rs, rt 0x1c rs rt 0 0 6 5 5 10 6 Unsigned multiply add maddu rs, rt 0x1c rs rt 0 1 6 5 5 10 6 Multiply registers rs and rt and add the resulting 64-bit product to the 64-bit value in the concatenated registers lo and hi. Multiply subtract msu... | clipped_hennesy_Page_830_Chunk6188 |
NOT not rdest, rsrc pseudoinstruction Put the bitwise logical negation of register rsrc into register rdest. OR or rd, rs, rt 0 rs rt rd 0 0x25 6 5 5 5 5 6 Put the logical OR of registers rs and rt into register rd. OR immediate ori rt, rs, imm 0xd rs rt imm 6 5 5 16 Put the logical OR of register rs and the zero-exten... | clipped_hennesy_Page_831_Chunk6189 |
B-56 Appendix B Assemblers, Linkers, and the SPIM Simulator Shift right arithmetic sra rd, rt, shamt 0 rs rt rd shamt 3 6 5 5 5 5 6 Shift right arithmetic variable srav rd, rt, rs 0 rs rt rd 0 7 6 5 5 5 5 6 Shift right logical srl rd, rt, shamt 0 rs rt rd shamt 2 6 5 5 5 5 6 Shift right logical variable srlv rd, rt, rs... | clipped_hennesy_Page_832_Chunk6190 |
Subtract (without overflow) subu rd, rs, rt 0 rs rt rd 0 0x23 6 5 5 5 5 6 Put the difference of registers rs and rt into register rd. Exclusive OR xor rd, rs, rt 0 rs rt rd 0 0x26 6 5 5 5 5 6 Put the logical XOR of registers rs and rt into register rd. XOR immediate xori rt, rs, imm 0xe rs rt Imm 6 5 5 16 Put the logic... | clipped_hennesy_Page_833_Chunk6191 |
B-58 Appendix B Assemblers, Linkers, and the SPIM Simulator Set less than unsigned sltu rd, rs, rt 0 rs rt rd 0 0x2b 6 5 5 5 5 6 Set register rd to 1 if register rs is less than rt, and to 0 otherwise. Set less than immediate slti rt, rs, imm 0xa rs rt imm 6 5 5 16 Set less than unsigned immediate sltiu rt, rs, imm 0xb... | clipped_hennesy_Page_834_Chunk6192 |
Set greater than unsigned sgtu rdest, rsrc1, rsrc2 pseudoinstruction Set register rdest to 1 if register rsrc1 is greater than rsrc2, and to 0 otherwise. Set less than equal sle rdest, rsrc1, rsrc2 pseudoinstruction Set less than equal unsigned sleu rdest, rsrc1, rsrc2 pseudoinstruction Set register rdest to 1 if regis... | clipped_hennesy_Page_835_Chunk6193 |
B-60 Appendix B Assemblers, Linkers, and the SPIM Simulator the instruction in the branch’s delay slot if the branch is not taken. Do not use these instructions; they may be removed in subsequent versions of the architecture. SPIM implements these instructions, but they are not described further. Branch instruction b ... | clipped_hennesy_Page_836_Chunk6194 |
Branch on greater than equal zero and link bgezal rs, label 1 rs 0x11 Offset 6 5 5 16 Conditionally branch the number of instructions specified by the offset if register rs is greater than or equal to 0. Save the address of the next instruction in reg- ister 31. Branch on greater than zero bgtz rs, label 7 rs 0 Offset... | clipped_hennesy_Page_837_Chunk6195 |
B-62 Appendix B Assemblers, Linkers, and the SPIM Simulator Branch on not equal bne rs, rt, label 5 rs rt Offset 6 5 5 16 Conditionally branch the number of instructions specified by the offset if register rs is not equal to rt. Branch on equal zero beqz rsrc, label pseudoinstruction Conditionally branch to the instru... | clipped_hennesy_Page_838_Chunk6196 |
Branch on less than equal unsigned bleu rsrc1, src2, label pseudoinstruction Conditionally branch to the instruction at the label if register rsrc1 is less than or equal to src2. Branch on less than blt rsrc1, rsrc2, label pseudoinstruction Branch on less than unsigned bltu rsrc1, rsrc2, label pseudoinstruction Conditi... | clipped_hennesy_Page_839_Chunk6197 |
B-64 Appendix B Assemblers, Linkers, and the SPIM Simulator Jump and link register jalr rs, rd 0 rs 0 rd 0 9 6 5 5 5 5 6 Unconditionally jump to the instruction whose address is in register rs. Save the address of the next instruction in register rd (which defaults to 31). Jump register jr rs 0 rs 0 8 6 5 15 6 Uncondit... | clipped_hennesy_Page_840_Chunk6198 |
Trap if greater equal tge rs, rt 0 rs rt 0 0x30 6 5 5 10 6 Unsigned trap if greater equal tgeu rs, rt 0 rs rt 0 0x31 6 5 5 10 6 If register rs is greater than or equal to register rt, raise a Trap exception. Trap if greater equal immediate tgei rs, imm 1 rs 8 imm 6 5 5 16 Unsigned trap if greater equal immediate tgeiu ... | clipped_hennesy_Page_841_Chunk6199 |
B-66 Appendix B Assemblers, Linkers, and the SPIM Simulator Unsigned trap if less than immediate tltiu rs, imm 1 rs b imm 6 5 5 16 If register rs is less than the sign-extended value imm, raise a Trap exception. Load Instructions Load address la rdest, address pseudoinstruction Load computed address—not the contents of... | clipped_hennesy_Page_842_Chunk6200 |
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