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546 Chapter 5 Large and Fast: Exploiting Memory Hierarchy were privileged. This laissez-faire attitude causes problems for VMMs for all of these architectures, including the x86, which we use here as an example. Figure 5.41 describes the 18 instructions that cause problems for virtualization [Robin and Irvine, 2000]. T... | clipped_hennesy_Page_544_Chunk5901 |
technique is called paravirtualization, and the open source Xen VMM is a good example. The Xen VMM provides a guest OS with a virtual machine abstraction that uses only the easy-to-virtualize parts of the physical x86 hardware on which the VMM runs. 5.12 Concluding Remarks The difficulty of building a memory system to ... | clipped_hennesy_Page_545_Chunk5902 |
548 Chapter 5 Large and Fast: Exploiting Memory Hierarchy As we will see in Chapter 7, memory systems are a central design issue for parallel processors. The growing importance of the memory hierarchy in determining system performance means that this important area will continue to be a focus of both designers and rese... | clipped_hennesy_Page_546_Chunk5903 |
5.1.4 [10] <5.1, 5.2> Communication bandwidth and server processing band width are two important factors to consider when designing a memory hierarchy. How can the bandwidths be improved? What is the cost of improving them? 5.1.5 [5] <5.1, 5.8> Now consider multiple clients simultaneously accessing the server. Will su... | clipped_hennesy_Page_547_Chunk5904 |
550 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.2.4 [10] <5.1> How many 16-byte cache lines are needed to store all 32-bit matrix elements being referenced? 5.2.5 [5] <5.1> References to which variables exhibit temporal locality? 5.2.6 [5] <5.1> References to which variables exhibit spatial locality? Exerci... | clipped_hennesy_Page_548_Chunk5905 |
of the closest direct-mapped cache with 16-word blocks of equal size or greater. Explain why the second cache, despite its larger data size, might provide slower performance than the first cache. 5.3.5 [20] <5.2, 5.3> Generate a series of read requests that have a lower miss rate on a 2 KB 2-way set associative cache t... | clipped_hennesy_Page_549_Chunk5906 |
552 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.4.6 [20] <5.2> List the final state of the cache, with each valid entry represented as a record of <index, tag, data>. Exercise 5.5 Recall that we have two write policies and write allocation policies, and their com binations can be implemented either in L1 o... | clipped_hennesy_Page_550_Chunk5907 |
Exercise 5.6 Media applications that play audio or video files are part of a class of workloads called “streaming” workloads; i.e., they bring in large amounts of data but do not reuse much of it. Consider a video streaming workload that accesses a 512 KB working set sequentially with the following address stream: 0, 2... | clipped_hennesy_Page_551_Chunk5908 |
554 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Exercise 5.7 In this exercise, we will look at the different ways capacity affects overall perfor mance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions.... | clipped_hennesy_Page_552_Chunk5909 |
Exercise 5.8 This exercise examines the impact of different cache designs, specifically compar ing associative caches to the direct-mapped caches from Section 5.2. For these exercises, refer to the table of address streams shown in Exercise 5.3. 5.8.1 [10] <5.3> Using the references from Exercise 5.3, show the final c... | clipped_hennesy_Page_553_Chunk5910 |
556 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.8.5 [10] <5.3> It is possible to have an even greater cache hierarchy than two levels. Given the processor above with a second level, direct-mapped cache, a designer wants to add a third level cache that takes 50 cycles to access and will reduce the global mis... | clipped_hennesy_Page_554_Chunk5911 |
Keeping “frequently used” (or “hot”) pages in DRAM can save disk accesses, but how do we determine the exact meaning of “frequently used” for a given system? Data engineers use the cost ratio between DRAM and disk access to quantify the reuse time threshold for hot pages. The cost of a disk access is $Disk /accesses_pe... | clipped_hennesy_Page_555_Chunk5912 |
558 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Page table Valid Physical Page or in Disk 1 5 0 Disk 0 Disk 1 6 1 9 1 11 0 Disk 1 4 0 Disk 0 Disk 1 3 1 12 5.10.1 [10] <5.4> Given the address stream in the table, and the initial TLB and page table states shown above, show the final state of the system. Also li... | clipped_hennesy_Page_556_Chunk5913 |
5.10.5 [10] <5.4> Given the parameters in the table above, calculate the total page table size for a system running 5 applications that utilize half of the memory available, given a two level page table approach with 256 entries. Assume each entry of the main page table is 6 bytes. Calculate the minimum and maximum amo... | clipped_hennesy_Page_557_Chunk5914 |
560 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.11.4 [5] <5.4> Under what scenarios would entry 2’s valid bit be set to zero? 5.11.5 [5] <5.4> What happens when an instruction writes to VA page 30? When would a software managed TLB be faster than a hardware managed TLB? 5.11.6 [5] <5.4> What happens when an... | clipped_hennesy_Page_558_Chunk5915 |
5.12.4 [10] <5.3, 5.5> Which address should be evicted at each replacement to maximize the number of hits? How many hits does this address sequence exhibit if you follow this “optimal” policy? 5.12.5 [10] <5.3, 5.5> Describe why it is difficult to implement a cache replacement policy that is optimal for all address seq... | clipped_hennesy_Page_559_Chunk5916 |
562 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.13.4 [10] <5.6> For a benchmark with native execution CPI of 1, what are the CPI numbers if using shadow page tables vs. NPT (assuming only page table virtualization overhead)? 5.13.5 [10] <5.6> What techniques can be used to reduce page table shadowing induce... | clipped_hennesy_Page_560_Chunk5917 |
5.14.4 [20] <5.6> Section 5.6 discusses virtualization under the assumption that the virtualized system is running the same ISA as the underlying hardware. However, one possible use of virtualization is to emulate non-native ISAs. An example of this is QEMU, which emulates a variety of ISAs such as MIPS, SPARC, and Pow... | clipped_hennesy_Page_561_Chunk5918 |
564 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.16.1 [15] <5.8> List the possible values of the given cache block for a correct cache coherence protocol implementation. List at least one more possible value of the block if the protocol doesn’t ensure cache coherency. 5.16.2 [15] <5.8> For a snooping protoco... | clipped_hennesy_Page_562_Chunk5919 |
The next table shows hit latencies. Private Cache Shared Cache Memory a. 5 20 180 b. 10 50 120 5.17.1 [15] <5.10> Which cache design is better for each of these benchmarks? Use data to support your conclusion. 5.17.2 [15] <5.10> Shared cache latency increases with the CMP size. Choose the best design if the shared cach... | clipped_hennesy_Page_563_Chunk5920 |
566 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Some processing functions on a log are: a. topK_sourceIP (int hour); b. browser_histogram (int srcIP); // browsers of a given IP 5.18.1 [5] <5.11> Which fields in a log entry will be accessed for the given log processing function? Assuming 64-byte cache blocks a... | clipped_hennesy_Page_564_Chunk5921 |
§5.1, page 457: 1 and 4. (3 is false because the cost of the memory hierarchy varies per computer, but in 2008 the highest cost is usually the DRAM.) §5.2, page 475: 1 and 4: A lower miss penalty can enable smaller blocks, since you don’t have that much latency to amortize, yet higher memory bandwidth usually leads to ... | clipped_hennesy_Page_565_Chunk5922 |
6 Combining bandwidth and storage . . . enables swift and reliable access to the ever-expanding troves of content on the proliferating disks and . . . repositories of the Internet. George Gilder The End Is Drawing Nigh, 2000 Storage and Other I/O Topics 6.1 Introduction 570 6.2 Dependability, Reliability, and Availabi... | clipped_hennesy_Page_566_Chunk5923 |
6.7 I/O Performance Measures: Examples from Disk and File Systems 596 6.8 Designing an I/O System 598 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 599 6.10 Real Stuff: Sun Fire x4150 Server 606 6.11 Advanced Topics: Networks 612 6.12 Fallacies and Pitfalls 613 6.13 Concluding Remarks 617 6.14 Historic... | clipped_hennesy_Page_567_Chunk5924 |
570 Chapter 6 Storage and Other I/O Topics 6.1 Introduction Although users can get frustrated if their computer hangs and must be rebooted, they become apoplectic if their storage system crashes and they lose information. Thus, the standard for dependability is much higher for storage than for computa tion. Networks a... | clipped_hennesy_Page_568_Chunk5925 |
with others throughput is crucial. Furthermore, performance depends on many aspects of the system: the device characteristics, the connection between the device and the rest of the system, the memory hierarchy, and the operating system. All of the components, from the individual I/O devices to the processor to the sys... | clipped_hennesy_Page_569_Chunk5926 |
572 Chapter 6 Storage and Other I/O Topics In Chapter 1, we briefly discussed four important I/O devices: mice, graphics displays, disks, and networks. In this chapter we go into much more depth on storage and related items. On the CD, there is an advanced topics section on networks, which are well covered in other bo... | clipped_hennesy_Page_570_Chunk5927 |
6.2 Dependability, Reliability, and Availability Users crave dependable storage, but how do you define it? In the computer indus try, it is harder than looking it up in the dictionary. After considerable debate, the following is considered the standard definition [Laprie, 1985]: Computer system dependability is the qu... | clipped_hennesy_Page_571_Chunk5928 |
574 Chapter 6 Storage and Other I/O Topics Note that reliability and availability are actually quantifiable measures, rather than just synonyms for dependability. What is the cause of failures? Figure 6.3 summarizes many papers that have col lected data on reasons for computer systems and telecommunications systems to... | clipped_hennesy_Page_572_Chunk5929 |
Which of the following are true about dependability? 1. If a system is up, then all its components are accomplishing their expected service. 2. Availability is a quantitative measure of the percentage of time a system is accomplishing its expected service. 3. Reliability is a quantitative measure of continuous service ... | clipped_hennesy_Page_573_Chunk5930 |
576 Chapter 6 Storage and Other I/O Topics Disk manufacturers report minimum seek time, maximum seek time, and average seek time in their manuals. The first two are easy to measure, but the aver age is open to wide interpretation because it depends on the seek distance. The industry has decided to calculate average se... | clipped_hennesy_Page_574_Chunk5931 |
Disk Read Time What is the average time to read or write a 512-byte sector for a typical disk rotating at 15,000 RPM? The advertised average seek time is 4 ms, the transfer rate is 100 MB/sec, and the controller overhead is 0.2 ms. Assume that the disk is idle so that there is no waiting time. Average disk access time ... | clipped_hennesy_Page_575_Chunk5932 |
578 Chapter 6 Storage and Other I/O Topics FIGURE 6.4 Six magnetic disks, varying in diameter from 14 inches down to 1.8 inches. The pictured disks were introduced over more than 15 years ago and hence are not intended to be represen tative of the best capacity of modern disks of these diameters. This photograph does,... | clipped_hennesy_Page_576_Chunk5933 |
Characteristics Seagate ST33000655SS Seagate ST31000340NS Seagate ST973451SS Seagate ST9160821AS Disk diameter (inches) 3.50 3.50 2.50 2.50 Formatted data capacity (GB) 147 1000 73 160 Number of disk surfaces (heads) 2 4 2 2 Rotation speed (RPM) 15,000 7200 15,000 5400 Internal disk cache size (MB) 16 32 16 8 External ... | clipped_hennesy_Page_577_Chunk5934 |
580 Chapter 6 Storage and Other I/O Topics 6.4 Flash Storage. Many have tried to invent a technology to replace disks, and many have failed: CCD memory, bubble memory, and holographic memory were all found wanting. By the time a new technology would ship, disks made advances as predicted earlier, costs dropped accordi... | clipped_hennesy_Page_578_Chunk5935 |
diameter hard disks are disappearing from some embedded markets. For example, in 2008 the Apple iPod Shuffle MP3 player sold for $50 and held 1 GB, while the smallest disk holds 4 GB and sells for more than the whole MP3 player. Flash memory is a type of electrically erasable programmable read-only mem ory (EEPROM). ... | clipped_hennesy_Page_579_Chunk5936 |
582 Chapter 6 Storage and Other I/O Topics gigabyte continues to decline, it will be interesting to see whether the higher performance and energy efficiency of flash memory will yield opportunities in the desktop and server markets as well. Which of the following are true about flash memory? 1. Like DRAM, flash is a se... | clipped_hennesy_Page_580_Chunk5937 |
need to support a range of devices with widely varying latencies and data transfer rates also makes bus design challenging. As it became difficult to run many parallel wires at high speed due to clock skew and reflection (see Appendix C), the industry transitioned from parallel shared buses to high-speed serial point-... | clipped_hennesy_Page_581_Chunk5938 |
584 Chapter 6 Storage and Other I/O Topics clock skew or synchronization problems. All the examples in Figure 6.8 are asynchronous. To coordinate the transmission of data between sender and receiver, an asyn chronous bus uses a handshaking protocol. A handshaking protocol consists of a series of steps in which the se... | clipped_hennesy_Page_582_Chunk5939 |
include the north bridge inside the microprocessor, and the south bridge chip of the Intel 975 includes a RAID controller (see Section 6.9). These I/O interconnects provide electrical connectivity among I/O devices, processors, and memory, and also define the lowest-level protocol for commu nication. Above this basic ... | clipped_hennesy_Page_583_Chunk5940 |
586 Chapter 6 Storage and Other I/O Topics 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System A bus or network protocol defines how a word or block of data should be commu nicated on a set of wires. This still leaves several other tasks that must be performed to actually cause data to be tran... | clipped_hennesy_Page_584_Chunk5941 |
As we will see in answering these questions, the operating system plays a major role in handling I/O, acting as the interface between the hardware and the program that requests I/O. The responsibilities of the operating system arise from three characteristics of I/O systems: 1. Multiple programs using the processor sh... | clipped_hennesy_Page_585_Chunk5942 |
588 Chapter 6 Storage and Other I/O Topics 2. The device must be able to notify the OS when the I/O device has completed an operation or has encountered an error. For example, when a disk completes a seek, it will notify the OS. 3. Data must be transferred between memory and an I/O device. For example, the block being... | clipped_hennesy_Page_586_Chunk5943 |
Elaboration: The alternative to memory-mapped I/O is to use dedicated I/O instructions in the processor. These I/O instructions can specify both the device number and the command word (or the location of the command word in memory). The processor communicates the device address via a set of wires normally included as ... | clipped_hennesy_Page_587_Chunk5944 |
590 Chapter 6 Storage and Other I/O Topics 2. In addition to the fact that an I/O interrupt has occurred, we would like to convey further information, such as the identity of the device generating the interrupt. Furthermore, the interrupts represent devices that may have dif ferent priorities and whose interrupt reque... | clipped_hennesy_Page_588_Chunk5945 |
3. Save the interrupt mask field of the Status register. 4. Change the interrupt mask field to disable all interrupts of equal or lower priority. 5. Save the processor state needed to handle the interrupt. 6. To allow higher-priority interrupts, set the interrupt enable bit of the Cause register to 1. 7. Call the appro... | clipped_hennesy_Page_589_Chunk5946 |
592 Chapter 6 Storage and Other I/O Topics Elaboration: The two least significant bits of the pending interrupt and interrupt mask fields are for software interrupts, which are lower priority. These are typically used by higher-priority interrupts to leave work for lower-priority interrupts to do once the immedi- ate r... | clipped_hennesy_Page_590_Chunk5947 |
becomes the master and directs the reads or writes between itself and memory. There are three steps in a DMA transfer: 1. The processor sets up the DMA by supplying the identity of the device, the operation to perform on the device, the memory address that is the source or destination of the data to be transferred, an... | clipped_hennesy_Page_591_Chunk5948 |
594 Chapter 6 Storage and Other I/O Topics Direct Memory Access and the Memory System When DMA is incorporated into an I/O system, the relationship between the memory system and processor changes. Without DMA, all accesses to the memory system come from the processor and thus proceed through address translation and ... | clipped_hennesy_Page_592_Chunk5949 |
In a system with virtual memory, should DMA work with virtual addresses or physical addresses? The obvious problem with virtual addresses is that the DMA unit will need to translate the virtual addresses to physical addresses. The major problem with the use of a physical address in a DMA transfer is that the transfer c... | clipped_hennesy_Page_593_Chunk5950 |
596 Chapter 6 Storage and Other I/O Topics 6.7 I/O Performance Measures: Examples from Disk and File Systems How should we compare I/O systems? This is a complex question, because I/O performance depends on many aspects of the system, and different applications stress different aspects of the I/O system. Furthermore, ... | clipped_hennesy_Page_594_Chunk5951 |
as well as gracefully handling certain types of failures. These applications are extremely critical and cost-sensitive. For example, banks normally use TP systems because they are concerned about a range of characteristics. These include making sure transactions aren’t lost, handling transactions quickly, and minimizin... | clipped_hennesy_Page_595_Chunk5952 |
598 Chapter 6 Storage and Other I/O Topics Are the following true or false? Unlike processor benchmarks, I/O benchmarks 1. concentrate on throughput rather than latency 2. can require that the data set scale in size or number of users to achieve per formance milestones 3. often report cost performance 6.8 Designing an... | clipped_hennesy_Page_596_Chunk5953 |
The easiest way to understand this methodology is with an example. We’ll do a simple analysis of the I/O system of the Sun Fire x4150 server in Section 6.10 to show how this methodology works. 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks Amdahl’s law in Chapter 1 reminds us that neglecting I/O in thi... | clipped_hennesy_Page_597_Chunk5954 |
600 Chapter 6 Storage and Other I/O Topics The improvement in CPU performance after six years is 90 11 = 8 However, the improvement in elapsed time is only 100 21 = 4.7 and the I/O time has increased from 10% to 47% of the elapsed time. Hence, the parallel revolution needs to come to I/O as well as to compu... | clipped_hennesy_Page_598_Chunk5955 |
Figure 6.12 shows the evolution and example cost in number of extra check disks. To keep track of the evolution, the authors numbered the stages of RAID, and they are still used today. No Redundancy (RAID 0) Simply spreading data over multiple disks, called striping, automatically forces accesses to several disks. Stri... | clipped_hennesy_Page_599_Chunk5956 |
602 Chapter 6 Storage and Other I/O Topics Mirroring (RAID 1) This traditional scheme for tolerating disk failure, called mirroring or shadowing, uses twice as many disks as does RAID 0. Whenever data is written to one disk, that data is also written to a redundant disk, so that there are always two copies of the infor... | clipped_hennesy_Page_600_Chunk5957 |
recalculate the new parity, as in the left in Figure 6.13. A “small write” would require reading the old data and old parity, adding the new information, and then writing the new parity to the parity disk and the new data to the data disk. The key insight to reduce this overhead is that parity is simply a sum of info... | clipped_hennesy_Page_601_Chunk5958 |
604 Chapter 6 Storage and Other I/O Topics Figure 6.14 shows how data is distributed in RAID 4 versus RAID 5. As the organization on the right shows, in RAID 5 the parity associated with each row of data blocks is no longer restricted to a single disk. This organization allows multiple writes to occur simultaneously a... | clipped_hennesy_Page_602_Chunk5959 |
replaced without having to turn off the system. RAIDs have enough redundancy to allow continuous operation, but hot-swapping disks place demands on the physical and electrical design of the array and the disk interfaces. Second, another failure could occur during repair, so the repair time affects the chances of losin... | clipped_hennesy_Page_603_Chunk5960 |
606 Chapter 6 Storage and Other I/O Topics Elaboration: One issue is how mirroring interacts with striping. Suppose you had, say, four disks’ worth of data to store and eight physical disks to use. Would you create four pairs of disks—each organized as RAID 1—and then stripe data across the four RAID 1 pairs? Alternati... | clipped_hennesy_Page_604_Chunk5961 |
FIGURE 6.15 A standard 19-inch rack populated with 42 1U servers. This rack has 42 1U “pizza box” servers. Source: http://gchelpdesk.ualberta.ca/news/07mar06/cbhd_news_07mar06.php. Hence, the smallest rack mount computer is 19 inches wide and 1.75 inches tall, often called 1U computers or 1U servers. Because of their ... | clipped_hennesy_Page_605_Chunk5962 |
608 Chapter 6 Storage and Other I/O Topics Figure 6.16 shows the Sun Fire x4150, an example of a 1U server. Maximally configured, this 1U box contains: ■ ■8 2.66 GHz processors, spread across two sockets (2 Intel Xeon 5345) ■ ■64 GB of DDR2-667 DRAM, spread across 16 4GB FBDIMMs ■ ■8 15,000 RPM 73 GB SAS 2.5-inch disk ... | clipped_hennesy_Page_606_Chunk5963 |
Figure 6.17 shows the connectivity and bandwidths of the chips on the mother board. Figures 6.9 and 6.10 describe the I/O chip set for the Intel 5345, and Figure 6.5 describes the SAS disks in the Sun Fire x4150. To clarify the advice on designing an I/O system in Section 6.8, let’s perform a simple performance evalu... | clipped_hennesy_Page_607_Chunk5964 |
610 Chapter 6 Storage and Other I/O Topics ■ ■The workload consists of 64 KB reads ■ ■Each processor sustains 1 billion instructions per second Find the maximum sustainable I/O rate for a fully loaded Sun Fire x4150 for random reads and sequential reads. Assume that the reads can always be done on an idle disk if one e... | clipped_hennesy_Page_608_Chunk5965 |
Once the data gets to the MCB, it needs to be written into the DRAM. The bandwidth of a DDR2 667 MHz FBDIMM is 5336 MB/second. A single DIMM can perform 5336 MB/sec 64 KB = 83,375 IOPS The memory is not a bottleneck even with one DIMM, and we have 16 in a fully configured Sun Fire x4150. The final link in the cha... | clipped_hennesy_Page_609_Chunk5966 |
612 Chapter 6 Storage and Other I/O Topics save the power (and cost) of 14 4GB DIMMs. A single socket can support 13,333 IOPS, so we can also reduce the number of Intel E5345 sockets by one. Using the numbers in Figure 6.18, the total system power is now: Idle Powerrandom reads = 154 + 2 ´ 10 + 8 ´ 8 + 15 = 253 watts P... | clipped_hennesy_Page_610_Chunk5967 |
read books on networking, Section 6.11 on the CD gives a quick overview of the topics and terminology, including Internetworking, the OSI model, protocol families such as TCP/IP, long-haul networks such as ATM, local area networks such as Ethernet, and wireless networks such as IEEE 802.11. 6.12 Fallacies and Pitfalls ... | clipped_hennesy_Page_611_Chunk5968 |
614 Chapter 6 Storage and Other I/O Topics A second study of more than 100,000 ATA disks, which had a quoted AFR of about 1.5%, saw failure rates of 1.7% for drives in their first year rise to 8.6% for drives in their third year, or about five to six times the specified rate [Pinheiro, Weber, and Barroso, 2007]. Fall... | clipped_hennesy_Page_612_Chunk5969 |
two nodes, but it doesn’t point to where the problem is. Intermediate checks can discover which component is broken. You need both for repair. Pitfall: Moving functions from the CPU to the I/O processor, expecting to improve performance without a careful analysis. There are many examples of this pitfall trapping people... | clipped_hennesy_Page_613_Chunk5970 |
616 Chapter 6 Storage and Other I/O Topics and so while desktops are by far the largest market for disks, desktops are a small market for tapes. Alas, the larger market has led disks to improve much more quickly than tapes. Starting in 2000 to 2002, the largest popular disk was larger than the largest popular tape. In... | clipped_hennesy_Page_614_Chunk5971 |
Depending on the relative location of the data on the disk, reordering could make it worse, as Figure 6.19 shows. The disk-scheduled reads complete in three-quarters of a disk revolution, but the OS-scheduled reads take three revolutions. Pitfall: Using the peak transfer rate of a portion of the I/O system to make perf... | clipped_hennesy_Page_615_Chunk5972 |
618 Chapter 6 Storage and Other I/O Topics widely varying schemes for interfacing I/O devices. In the low-end and midrange systems, buffered DMA is likely to be the dominant transfer mechanism. In the high-end systems, latency and bandwidth may both be important, and cost may be secondary. Multiple paths to I/O devices... | clipped_hennesy_Page_616_Chunk5973 |
6.15 Exercises Contributed by Perry Alexander of the University of Kansas Exercise 6.1 Figure 6.2 describes numerous I/O devices in terms of their behavior, partner, and data rate. However, these classifications often do not provide a complete picture of data flow within a system. Explore device classifications for the... | clipped_hennesy_Page_617_Chunk5974 |
620 Chapter 6 Storage and Other I/O Topics Exercise 6.3 Average and minimum times for reading and writing to storage devices are common measurements used to compare devices. Using techniques from Chap ter 6, calculate values related to read and write time for disks with the following characteristics. Average Seek Ti... | clipped_hennesy_Page_618_Chunk5975 |
Exercise 6.5 FLASH memory is one of the first true competitors for traditional disk drives. Explore the implications of FLASH memory by answering questions about the following applications. a. Aircraft Control System b. Phone Switch 6.5.1 [5] <6.2, 6.3, 6.4> As we move towards solid state drives constructed from FLASH... | clipped_hennesy_Page_619_Chunk5976 |
622 Chapter 6 Storage and Other I/O Topics Exercise 6.7 I/O can be performed either synchronously or asynchronously. Explore the differ ences by answering performance questions about the following peripherals. a. Printer b. Scanner 6.7.1 [5] <6.5> What would be the most appropriate bus type (synchronous or asynchronou... | clipped_hennesy_Page_620_Chunk5977 |
questions about communicating with I/O subsystems for the following applica tions using combinations of these techniques. a. Auto Pilot b. Automated Thermostat 6.9.1 [5] <6.6> Describe device polling. Would each application in the table be appropriate for communication using polling techniques? Explain. 6.9.2 [5] <6.... | clipped_hennesy_Page_621_Chunk5978 |
624 Chapter 6 Storage and Other I/O Topics 6.10.4 [5] <6.6> What happens if the interrupt enable bit of the Cause register is not set when handling an interrupt? What value could the interrupt mask value take to accomplish the same thing? 6.10.5 [5] <6.6> Most interrupt handling systems are implemented in the operat i... | clipped_hennesy_Page_622_Chunk5979 |
situations, data throughput dominates in others. Explore I/O performance evalua tion by answering the questions for the following applications. a. Mathematical Computations b. Online Chat 6.12.1 [10] <6.7> For each application in the table, does I/O performance domi nate system performance? 6.12.2 [10] <6.7> For each... | clipped_hennesy_Page_623_Chunk5980 |
626 Chapter 6 Storage and Other I/O Topics things about RAID arrays that we will explore in the context of the following activities. a. High-Performance Mathematical Computations b. Online Video Services 6.14.1 [10] <6.9> RAID 0 uses striping to force parallel access among many disks. Why does striping improve disk pe... | clipped_hennesy_Page_624_Chunk5981 |
6.15.5 [5] <6.9> RAID 4 and RAID 5 speed improvements grow with respect to RAID 3 as the size of the protected block grows. Why is this the case? Is there a situ ation where RAID 4 and RAID 5 would be no more efficient than RAID 3? Exercise 6.16 The emergence of web servers for ecommerce, online storage, and communica... | clipped_hennesy_Page_625_Chunk5982 |
628 Chapter 6 Storage and Other I/O Topics 6.17.2 [15] <6.8, 6.10> For the application listed above, find a server available in the marketplace that you feel would be appropriate for running the application. Before evaluating the server, identify reasons why it was selected. 6.17.3 [20] <6.8, 6.10> Using metrics simila... | clipped_hennesy_Page_626_Chunk5983 |
6.19.2 [5] <6.9, 6.12> Given that your company operates a global search engine with a large disk farm, does upgrading to either RAID 0 or RAID 1 make economic sense given that your income model is based on the number of advertisements served? 6.19.3 [5] <6.9, 6.12> Repeat 6.19.2 for a large disk farm operated by an onl... | clipped_hennesy_Page_627_Chunk5984 |
7 There are finer fish in the sea than have ever been caught. Irish proverb Multicores, Multiprocessors, and Clusters 7.1 Introduction 632 7.2 The Difficulty of Creating Parallel Processing Programs 634 7.3 Shared Memory Multiprocessors 638 7.4 Clusters and Other Message-Passing Multiprocessors 641 7.5 Hardware Multi... | clipped_hennesy_Page_628_Chunk5985 |
7.6 SISD, MIMD, SIMD, SPMD, and Vector 648 7.7 Introduction to Graphics Processing Units 654 7.8 Introduction to Multiprocessor Network Topologies 660 7.9 Multiprocessor Benchmarks 664 7.10 Roofline: A Simple Performance Model 667 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 675 7.12 Fallacies... | clipped_hennesy_Page_629_Chunk5986 |
632 Chapter 7 Multicores, Multiprocessors, and Clusters 7.1 Introduction Computer architects have long sought the El Dorado of computer design: to create powerful computers simply by connecting many existing smaller ones. This golden vision is the fountainhead of multiprocessors. Ideally, customers order as many proce... | clipped_hennesy_Page_630_Chunk5987 |
7.1 Introduction 633 The tall challenge facing the industry is to create hardware and software that will make it easy to write correct parallel processing programs that will execute efficiently in performance and power as the number of cores per chip scales geometrically. This sudden shift in microprocessor design has... | clipped_hennesy_Page_631_Chunk5988 |
634 Chapter 7 Multicores, Multiprocessors, and Clusters describes multithreading, a term often confused with multiprocessing, in part because it relies upon similar concurrency in programs. Section 7.6 describes an older classification scheme than in Figure 7.1. In addition, it describes two styles of instruction set a... | clipped_hennesy_Page_632_Chunk5989 |
Why is it difficult to write parallel processing programs that are fast, especially as the number of processors increases? In Chapter 1, we used the analogy of eight reporters trying to write a single story in hopes of doing the work eight times faster. To succeed, the task must be broken into eight equal-sized pieces,... | clipped_hennesy_Page_633_Chunk5990 |
636 Chapter 7 Multicores, Multiprocessors, and Clusters Substituting for the goal of a speed-up of 90 into the formula above: 90 = 1 _____________________________________ (1 − Fraction time affected) + Fraction time affected 100 Then simplifying the formula and solving for fraction time affected: 90 × (1 – 0... | clipped_hennesy_Page_634_Chunk5991 |
Thus, for this problem size, we get about 55% of the potential speed-up with 10 processors, but only 10% with 100. Look what happens when we increase the matrix. The sequential program now takes 10t + 10,000t = 10,010t. The execution time for 10 processors is Execution time after improvement = 10,000t _______ 10 + ... | clipped_hennesy_Page_635_Chunk5992 |
638 Chapter 7 Multicores, Multiprocessors, and Clusters If one processor has 2% of the parallel load, then it must do 2% × 10,000 or 200 additions, and the other 99 will share the remaining 9800. Since they are operating simultaneously, we can just calculate the execution time as a maximum Execution time after improve... | clipped_hennesy_Page_636_Chunk5993 |
much faster than others, depending on which processor asks for which word. Such machines are called nonuniform memory access (NUMA) multiprocessors. As you might expect, the programming challenges are harder for a NUMA multiprocessor than for a UMA multiprocessor, but NUMA machines can scale to larger sizes and NUM... | clipped_hennesy_Page_637_Chunk5994 |
640 Chapter 7 Multicores, Multiprocessors, and Clusters sum[Pn] = 0; for (i = 1000*Pn; i < 1000*(Pn+1); i = i + 1) sum[Pn] = sum[Pn] + A[i]; /* sum the assigned areas*/ The next step is to add these many partial sums. This step is called a reduction. We divide to conquer. Half of the processors add pairs of partial sum... | clipped_hennesy_Page_638_Chunk5995 |
7.4 Clusters and Other Message-Passing Multiprocessors The alternative approach to sharing an address space is for the processors to each have their own private physical address space. Figure 7.4 shows the classic organi zation of a multiprocessor with multiple private address spaces. This alternative multiprocessor ... | clipped_hennesy_Page_639_Chunk5996 |
642 Chapter 7 Multicores, Multiprocessors, and Clusters One drawback of clusters has been that the cost of administering a cluster of n machines is about the same as the cost of administering n independent machines, while the cost of administering a shared memory multiprocessor with n processors is about the same as a... | clipped_hennesy_Page_640_Chunk5997 |
Since this computer has multiple address spaces, the first step is distributing the 100 subsets to each of the local memories. The processor containing the 100,000 numbers sends the subsets to each of the 100 processor-memory nodes. The next step is to get the sum of each subset. This step is simply a loop that every ... | clipped_hennesy_Page_641_Chunk5998 |
644 Chapter 7 Multicores, Multiprocessors, and Clusters Elaboration: This example assumes implicitly that message passing is about as fast as addition. In reality, message sending and receiving is much slower. An optimization to better balance computation and communication might be to have fewer nodes receive many su... | clipped_hennesy_Page_642_Chunk5999 |
if someone developed software that could run on those computers and then gave each PC an independent piece of the problem to work on. The first example was the Search for ExtraTerrestrial Intelligence (SETI). Over 5 million computer users in more than 200 countries have signed up for SETI@home and have collectively con... | clipped_hennesy_Page_643_Chunk6000 |
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