text stringlengths 1 7.76k | source stringlengths 17 81 |
|---|---|
546 Chapter 5 Large and Fast: Exploiting Memory Hierarchy were privileged. This laissez-faire attitude causes problems for VMMs for all of these architectures, including the x86, which we use here as an example. Figure 5.41 describes the 18 instructions that cause problems for virtualization [Robin and Irvine, 2000]. The two broad classes are instructions that ■ ■Read control registers in user mode that reveals that the guest operating sys tem is running in a virtual machine (such as POPF, mentioned earlier) ■ ■Check protection as required by the segmented architecture but assume that the operating system is running at the highest privilege level To simplify implementations of VMMs on the x86, both AMD and Intel have proposed extensions to the architecture via a new mode. Intel’s VT-x provides a new execution mode for running VMs, an architected definition of the VM state, instructions to swap VMs rapidly, and a large set of parameters to select the circumstances where a VMM must be invoked. Altogether, VT-x adds 11 new instructions for the x86. AMD’s Pacifica makes similar proposals. An alternative to modifying the hardware is to make small modifications to the operating system to avoid using the troublesome pieces of the architecture. This Problem category Problem x86 instructions Access sensitive registers without trapping when running in user mode Store global descriptor table register (SGDT) Store local descriptor table register (SLDT) Store interrupt descriptor table register (SIDT) Store machine status word (SMSW) Push flags (PUSHF, PUSHFD) Pop flags (POPF, POPFD) When accessing virtual memory mechanisms in user mode, instructions fail the x86 protection checks Load access rights from segment descriptor (LAR) Load segment limit from segment descriptor (LSL) Verify if segment descriptor is readable (VERR) Verify if segment descriptor is writable (VERW) Pop to segment register (POP CS, POP SS, . . .) Push segment register (PUSH CS, PUSH SS, . . .) Far call to different privilege level (CALL) Far return to different privilege level (RET) Far jump to different privilege level (JMP) Software interrupt (INT) Store segment selector register (STR) Move to/from segment registers (MOVE) FIGURE 5.41 Summary of 18 x86 instructions that cause problems for virtualization [Robin and Irvine, 2000]. The first five instructions in the top group allow a program in user mode to read a control register, such as a descriptor table registers, without causing a trap. The pop flags instruction modifies a control register with sensitive information but fails silently when in user mode. The protection checking of the segmented architecture of the x86 is the downfall of the bottom group, as each of these instructions checks the privilege level implicitly as part of instruction execution when reading a control register. The checking assumes that the OS must be at the highest privilege level, which is not the case for guest VMs. Only the Move to segment register tries to modify control state, and protection checking foils it as well. | clipped_hennesy_Page_544_Chunk5901 |
technique is called paravirtualization, and the open source Xen VMM is a good example. The Xen VMM provides a guest OS with a virtual machine abstraction that uses only the easy-to-virtualize parts of the physical x86 hardware on which the VMM runs. 5.12 Concluding Remarks The difficulty of building a memory system to keep pace with faster processors is underscored by the fact that the raw material for main memory, DRAMs, is essen tially the same in the fastest computers as it is in the slowest and cheapest. It is the principle of locality that gives us a chance to overcome the long latency of memory access—and the soundness of this strategy is demonstrated at all levels of the memory hierarchy. Although these levels of the hierarchy look quite different in quantitative terms, they follow similar strategies in their opera tion and exploit the same properties of locality. Multilevel caches make it possible to use more cache optimizations more easily for two reasons. First, the design parameters of a lower-level cache are different from a first-level cache. For example, because a lower-level cache will be much larger, it is possible to use larger block sizes. Second, a lower-level cache is not constantly being used by the processor, as a first-level cache is. This allows us to consider having the lower-level cache do something when it is idle that may be useful in preventing future misses. Another trend is to seek software help. Efficiently managing the memory hier archy using a variety of program transformations and hardware facilities is a major focus of compiler enhancements. Two different ideas are being explored. One idea is to reorganize the program to enhance its spatial and temporal locality. This approach focuses on loop-oriented programs that use large arrays as the major data structure; large linear algebra problems are a typical example. By restructuring the loops that access the arrays, substantially improved locality—and, therefore, cache performance—can be obtained. The discussion on page 544 showed how effective even a simple change of loop structure could be. Another approach is prefetching. In prefetching, a block of data is brought into the cache before it is actually referenced. Many microprocessors use hardware prefetching to try to predict accesses that may be difficult for software to notice. A third approach is special cache-aware instructions that optimize memory transfer. For example, the microprocessors in Section 7.10 in Chapter 7 use an optimization that does not fetch the contents of a block from memory on a write miss because the program is going to write the full block. This optimization significantly reduces memory traffic for one kernel. prefetching A technique in which data blocks needed in the future are brought into the cache early by the use of special instructions that specify the address of the block. 5.12 Concluding Remarks 547 | clipped_hennesy_Page_545_Chunk5902 |
548 Chapter 5 Large and Fast: Exploiting Memory Hierarchy As we will see in Chapter 7, memory systems are a central design issue for parallel processors. The growing importance of the memory hierarchy in determining system performance means that this important area will continue to be a focus of both designers and researchers for some years to come. Historical Perspective and Further Reading This history section gives an overview of memory technologies, from mercury delay lines to DRAM, the invention of the memory hierarchy, protection mech anisms, and virtual machines, and concludes with a brief history of operating systems, including CTSS, MULTICS, UNIX, BSD UNIX, MS-DOS, Windows, and Linux. 5.14 Exercises Contributed by Jichuan Chang, Jacob Leverich, Kevin Lim, and Parthasarathy Ranganathan (all of Hewlett-Packard) Exercise 5.1 In this exercise we consider memory hierarchies for various applications, listed in the following table. a. Software version control b. Making phone calls 5.1.1 [10] <5.1> Assuming both client and server are involved in the process, first name the client and server systems. Where can caches be placed to speed up the process? 5.1.2 [10] <5.1> Design a memory hierarchy for the system. Show the typical size and latency at various levels of the hierarchy. What is the relationship between cache size and its access latency? 5.1.3 [15] <5.1> What are the units of data transfers between hierarchies? What is the relationship between the data location, data size, and transfer latency? 5.13 | clipped_hennesy_Page_546_Chunk5903 |
5.1.4 [10] <5.1, 5.2> Communication bandwidth and server processing band width are two important factors to consider when designing a memory hierarchy. How can the bandwidths be improved? What is the cost of improving them? 5.1.5 [5] <5.1, 5.8> Now consider multiple clients simultaneously accessing the server. Will such scenarios improve the spatial and temporal locality? 5.1.6 [10] <5.1, 5.8> Give an example of where the cache can provide out-of-date data. How should the cache be designed to mitigate or avoid such issues? Exercise 5.2 In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. a. for (I=0; I<8; I++) for (J=0; J<8000; J++) A[I][J]=B[I][0]+A[J][I]; b. for (J=0; J<8000; J++) for (I=0; I<8; I++) A[I][J]=B[I][0]+A[J][I]; 5.2.1 [5] <5.1> How many 32-bit integers can be stored in a 16-byte cache line? 5.2.2 [5] <5.1> References to which variables exhibit temporal locality? 5.2.3 [5] <5.1> References to which variables exhibit spatial locality? Locality is affected by both the reference order and data layout. The same compu tation can also be written below in Matlab, which differs from C by contiguously storing matrix elements within the same column. a. for I=1:8 for J=1:8000 A(I,J)=B(I,0)+A(J,I); end end b. for J=1:8000 for I=1:8 A(I,J)=B(I,0)+A(J,I); end end 5.14 Exercises 549 | clipped_hennesy_Page_547_Chunk5904 |
550 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.2.4 [10] <5.1> How many 16-byte cache lines are needed to store all 32-bit matrix elements being referenced? 5.2.5 [5] <5.1> References to which variables exhibit temporal locality? 5.2.6 [5] <5.1> References to which variables exhibit spatial locality? Exercise 5.3 Caches are important to providing a high-performance memory hierarchy to pro cessors. Below is a list of 32-bit memory address references, given as word addresses. a. 3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 b. 21, 166, 201, 143, 61, 166, 62, 133, 111, 143, 144, 61 5.3.1 [10] <5.2> For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. 5.3.2 [10] <5.2> For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also list if each reference is a hit or a miss, assuming the cache is initially empty. 5.3.3 [20] <5.2, 5.3> You are asked to optimize a cache design for the given references. There are three direct-mapped cache designs possible, all with a total of 8 words of data: C1 has 1-word blocks, C2 has 2-word blocks, and C3 has 4-word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is 25 cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles, and C3 takes 5 cycles, which is the best cache design? There are many different design parameters that are important to a cache’s overall performance. The table below lists parameters for different direct-mapped cache designs. Cache Data Size Cache Block Size Cache Access Time a. 32 KB 2 words 1 cycle b. 32 KB 4 words 2 cycle 5.3.4 [15] <5.2> Calculate the total number of bits required for the cache listed in the table, assuming a 32-bit address. Given that total size, find the total size | clipped_hennesy_Page_548_Chunk5905 |
of the closest direct-mapped cache with 16-word blocks of equal size or greater. Explain why the second cache, despite its larger data size, might provide slower performance than the first cache. 5.3.5 [20] <5.2, 5.3> Generate a series of read requests that have a lower miss rate on a 2 KB 2-way set associative cache than the cache listed in the table. Iden tify one possible solution that would make the cache listed in the table have an equal or lower miss rate than the 2 KB cache. Discuss the advantages and disadvantages of such a solution. 5.3.6 [15] <5.2> The formula shown on page 457 shows the typical method to index a direct-mapped cache, specifically (Block address) modulo (Number of blocks in the cache). Assuming a 32-bit address and 1024 blocks in the cache, consider a different indexing function, specifically (Block address[31:27] XOR Block address[26:22]). Is it possible to use this to index a direct-mapped cache? If so, explain why and discuss any changes that might need to be made to the cache. If it is not possible, explain why. Exercise 5.4 For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag Index Offset a. 31–10 9–5 4–0 b. 31–12 11–6 5–0 5.4.1 [5] <5.2> What is the cache line size (in words)? 5.4.2 [5] <5.2> How many entries does the cache have? 5.4.3 [5] <5.2> What is the ratio between total bits required for such a cache implementation over the data storage bits? Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 5.4.4 [10] <5.2> How many blocks are replaced? 5.4.5 [10] <5.2> What is the hit ratio? 5.14 Exercises 551 | clipped_hennesy_Page_549_Chunk5906 |
552 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.4.6 [20] <5.2> List the final state of the cache, with each valid entry represented as a record of <index, tag, data>. Exercise 5.5 Recall that we have two write policies and write allocation policies, and their com binations can be implemented either in L1 or L2 cache. L1 L2 a. Write through, non-write allocate Write back, write allocate b. Write through, write allocate Write back, write allocate 5.5.1 [5] <5.2, 5.5> Buffers are employed between different levels of memory hierarchy to reduce access latency. For this given configuration, list the possible buffers needed between L1 and L2 caches, as well as L2 cache and memory. 5.5.2 [20] <5.2, 5.5> Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block. 5.5.3 [20] <5.2, 5.5> For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), configuration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block. Consider the following program and cache behaviors. Data Reads per 1000 Instructions Data Writes per 1000 Instructions Instruction Cache Miss Rate Data Cache Miss Rate Block Size (byte) a. 250 100 0.30% 2% 64 b. 200 100 0.30% 2% 64 5.5.4 [5] <5.2, 5.5> For a write-through, write-allocate cache, what are the minimum read and write bandwidths (measured by byte per cycle) needed to achieve a CPI of 2? 5.5.5 [5] <5.2, 5.5> For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what are the minimal read and write bandwidths needed for a CPI of 2? 5.5.6 [5] <5.2, 5.5> What are the minimal bandwidths needed to achieve the performance of CPI=1.5? | clipped_hennesy_Page_550_Chunk5907 |
Exercise 5.6 Media applications that play audio or video files are part of a class of workloads called “streaming” workloads; i.e., they bring in large amounts of data but do not reuse much of it. Consider a video streaming workload that accesses a 512 KB working set sequentially with the following address stream: 0, 2, 4, 6, 8, 10, 12, 14, 16, … 5.6.1 [5] <5.5, 5.3> Assume a 64 KB direct-mapped cache with a 32-byte line. What is the miss rate for the address stream above? How is this miss rate sensitive to the size of the cache or the working set? How would you categorize the misses this workload is experiencing, based on the 3C model? 5.6.2 [5] <5.5, 5.1> Re-compute the miss rate when the cache line size is 16 bytes, 64 bytes, and 128 bytes. What kind of locality is this workload exploiting? 5.6.3 [10] <5.10> “Prefetching” is a technique that leverages predictable address patterns to speculatively bring in additional cache lines when a particular cache line is accessed. One example of prefetching is a stream buffer that prefetches sequentially adjacent cache lines into a separate buffer when a particular cache line is brought in. If the data is found in the prefetch buffer, it is considered as a hit and moved into the cache and the next cache line is prefetched. Assume a two-entry stream buffer and assume that the cache latency is such that a cache line can be loaded before the computation on the previous cache line is completed. What is the miss rate for the address stream above? Cache block size (B) can affect both miss rate and miss latency. Assuming a 1-CPI machine with an average of 1.35 references (both instruction and data) per instruction, help find the optimal block size given the following miss rates for vari ous block sizes. 8 16 32 64 128 a. 4% 3% 2% 1.5% 1% b. 8% 7% 6% 5% 4% 5.6.4 [10] <5.2> What is the optimal block size for a miss latency of 20×B cycles? 5.6.5 [10] <5.2> What is the optimal block size for a miss latency of 24+B cycles? 5.6.6 [10] <5.2> For constant miss latency, what is the optimal block size? 5.14 Exercises 553 | clipped_hennesy_Page_551_Chunk5908 |
554 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Exercise 5.7 In this exercise, we will look at the different ways capacity affects overall perfor mance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. The following table shows data for L1 caches attached to each of two processors, P1 and P2. L1 Size L1 Miss Rate L1 Hit Time a. P1 2 KB 8.0% 0.66 ns P2 4 KB 6.0% 0.90 ns b. P1 16 KB 3.4% 1.08 ns P2 32 KB 2.9% 2.02 ns 5.7.1 [5] <5.3> Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates? 5.7.2 [5] <5.3> What is the AMAT for P1 and P2? 5.7.3 [5] <5.3> Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster? For the next three problems, we will consider the addition of an L2 cache to P1 to presumably make up for its limited L1 cache capacity. Use the L1 cache capacities and hit times from the previous table when solving these problems. The L2 miss rate indicated is its local miss rate. L2 Size L2 Miss Rate L2 Hit Time a. 1 MB 95% 5.62 ns b. 8 MB 68% 23.52 ns 5.7.4 [10] <5.3> What is the AMAT for P1 with the addition of an L2 cache? Is the AMAT better or worse with the L2 cache? 5.7.5 [5] <5.3> Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 with the addition of an L2 cache? 5.7.6 [10] <5.3> Which processor is faster, now that P1 has an L2 cache? If P1 is faster, what miss rate would P2 need in its L1 cache to match P1’s performance? If P2 is faster, what miss rate would P1 need in its L1 cache to match P2’s performance? | clipped_hennesy_Page_552_Chunk5909 |
Exercise 5.8 This exercise examines the impact of different cache designs, specifically compar ing associative caches to the direct-mapped caches from Section 5.2. For these exercises, refer to the table of address streams shown in Exercise 5.3. 5.8.1 [10] <5.3> Using the references from Exercise 5.3, show the final cache contents for a three-way set associative cache with two-word blocks and a total size of 24 words. Use LRU replacement. For each reference identify the index bits, the tag bits, the block offset bits, and if it is a hit or a miss. 5.8.2 [10] <5.3> Using the references from Exercise 5.3, show the final cache contents for a fully associative cache with one-word blocks and a total size of 8 words. Use LRU replacement. For each reference identify the index bits, the tag bits, and if it is a hit or a miss. 5.8.3 [15] <5.3> Using the references from Exercise 5.3, what is the miss rate for a fully associative cache with two-word blocks and a total size of 8 words, using LRU replacement? What is the miss rate using MRU (most recently used) replacement? Finally what is the best possible miss rate for this cache, given any replacement policy? Multilevel caching is an important technique to overcome the limited amount of space that a first level cache can provide while still maintaining its speed. Consider a processor with the following parameters: Base CPI, No Memory Stalls Processor Speed Main Memory Access Time First Level Cache Miss Rate per Instruction Second Level Cache, Direct-Mapped Speed Global Miss Rate with Second Level Cache, Direct-Mapped Second Level Cache, Eight-Way Set Associative Speed Global Miss Rate with Second Level Cache, Eight-Way Set Associative a. 1.5 2 GHz 100 ns 7% 12 cycles 3.5% 28 cycles 1.5% b. 1.0 2 GHz 150 ns 3% 15 cycles 5.0% 20 cycles 2.0% 5.8.4 [10] <5.3> Calculate the CPI for the processor in the table using: 1) only a first level cache, 2) a second level direct-mapped cache, and 3) a second level eight- way set associative cache. How do these numbers change if main memory access time is doubled? If it is cut in half? 5.14 Exercises 555 | clipped_hennesy_Page_553_Chunk5910 |
556 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.8.5 [10] <5.3> It is possible to have an even greater cache hierarchy than two levels. Given the processor above with a second level, direct-mapped cache, a designer wants to add a third level cache that takes 50 cycles to access and will reduce the global miss rate to 1.3%. Would this provide better performance? In general, what are the advantages and disadvantages of adding a third level cache? 5.8.6 [20] <5.3> In older processors such as the Intel Pentium or Alpha 21264, the second level of cache was external (located on a different chip) from the main processor and the first level cache. While this allowed for large second level caches, the latency to access the cache was much higher, and the bandwidth was typically lower because the second level cache ran at a lower frequency. Assume a 512 KB off- chip second level cache has a global miss rate of 4%. If each additional 512 KB of cache lowered global miss rates by 0.7%, and the cache had a total access time of 50 cycles, how big would the cache have to be to match the performance of the second level direct-mapped cache listed in the table? Of the eight-way set associative cache? Exercise 5.9 For a high-performance system such as a B-tree index for a database, the page size is determined mainly by the data size and disk performance. Assume that on aver age a B-tree index page is 70% full with fix-sized entries. The utility of a page is its B-tree depth, calculated as log2(entries). The following table shows that for 16-byte entries, and a 10-year-old disk with a 10 ms latency and 10 MB/s transfer rate, the optimal page size is 16K. Page Size (KB) Page Utility or B-Tree Depth (Number of Disk Accesses Saved) Index Page Access Cost (ms) Utility/Cost 2 6.49 (or log2(2048/16×0.7)) 10.2 0.64 4 7.49 10.4 0.72 8 8.49 10.8 0.79 16 9.49 11.6 0.82 32 10.49 13.2 0.79 64 11.49 16.4 0.70 128 12.49 22.8 0.55 256 13.49 35.6 0.38 5.9.1 [10] <5.4> What is the best page size if entries now become 128 bytes? 5.9.2 [10] <5.4> Based on 5.9.1, what is the best page size if pages are half full? 5.9.3 [20] <5.4> Based on 5.9.2, what is the best page size if using a modern disk with a 3 ms latency and 100 MB/s transfer rate? Explain why future servers are likely to have larger pages. | clipped_hennesy_Page_554_Chunk5911 |
Keeping “frequently used” (or “hot”) pages in DRAM can save disk accesses, but how do we determine the exact meaning of “frequently used” for a given system? Data engineers use the cost ratio between DRAM and disk access to quantify the reuse time threshold for hot pages. The cost of a disk access is $Disk /accesses_per_ sec, while the cost to keep a page in DRAM is $DRAM_MB/page_size. The typical DRAM and disk costs and typical database page sizes at several time points are listed below: Year DRAM Cost ($/MB) Page Size (KB) Disk Cost ($/disk) Disk Access Rate (access/sec) 1987 5000 1 15000 15 1997 15 8 2000 64 2007 0.05 64 80 83 5.9.4 [10] <5.1, 5.4> What are the reuse time thresholds for these three technology generations? 5.9.5 [10] <5.4> What are the reuse time thresholds if we keep using the same 4K page size? What’s the trend here? 5.9.6 [20] <5.4> What other factors can be changed to keep using the same page size (thus avoiding software rewrite)? Discuss their likeliness with current technology and cost trends. Exercise 5.10 As described in Section 5.4, virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following table is a stream of virtual ad dresses as seen on a system. Assume 4 KB pages, a 4-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. a. 4669, 2227, 13916, 34587, 48870, 12608, 49225 b. 12948, 49419, 46814, 13975, 40004, 12707, 52236 TLB Valid Tag Physical Page Number 1 11 12 1 7 4 1 3 6 0 4 9 5.14 Exercises 557 | clipped_hennesy_Page_555_Chunk5912 |
558 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Page table Valid Physical Page or in Disk 1 5 0 Disk 0 Disk 1 6 1 9 1 11 0 Disk 1 4 0 Disk 0 Disk 1 3 1 12 5.10.1 [10] <5.4> Given the address stream in the table, and the initial TLB and page table states shown above, show the final state of the system. Also list for each reference if it is a hit in the TLB, a hit in the page table, or a page fault. 5.10.2 [15] <5.4> Repeat Exercise 5.10.1, but this time use 16 KB pages instead of 4 KB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages? 5.10.3 [15] <5.3, 5.4> Show the final contents of the TLB if it is 2-way set associative. Also show the contents of the TLB if it is direct mapped. Discuss the importance of having a TLB to high performance. How would virtual memory accesses be handled if there were no TLB? There are several parameters that impact the overall size of the page table. Listed below are several key page table parameters. Virtual Address Size Page Size Page Table Entry Size a. 32 bits 8 KB 4 bytes b. 64 bits 8 KB 6 bytes 5.10.4 [5] <5.4> Given the parameters in the table above, calculate the total page table size for a system running 5 applications that utilize half of the memory available. | clipped_hennesy_Page_556_Chunk5913 |
5.10.5 [10] <5.4> Given the parameters in the table above, calculate the total page table size for a system running 5 applications that utilize half of the memory available, given a two level page table approach with 256 entries. Assume each entry of the main page table is 6 bytes. Calculate the minimum and maximum amount of memory required. 5.10.6 [10] <5.4> A cache designer wants to increase the size of a 4 KB virtually indexed, physically tagged cache. Given the page size listed in the table above, is it possible to make a 16 KB direct-mapped cache, assuming 2 words per block? How would the designer increase the data size of the cache? Exercise 5.11 In this exercise, we will examine space/time optimizations for page tables. The fol lowing table shows parameters of a virtual memory system. Virtual Address (bits) Physical DRAM Installed Page Size PTE Size (byte) a. 43 16 GB 4 KB 4 b. 38 8 GB 16 KB 4 5.11.1 [10] <5.4> For a single-level page table, how many page table entries (PTEs) are needed? How much physical memory is needed for storing the page table? 5.11.2 [10] <5.4> Using a multilevel page table can reduce the physical memory consumption of page tables, by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB? 5.11.3 [15] <5.4> An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common case and worst case numbers of memory references needed for servicing a TLB miss? The following table shows the contents of a 4-entry TLB. Entry-ID Valid VA Page Modified Protection PA Page 1 1 140 1 RW 30 2 0 40 0 RX 34 3 1 200 1 RO 32 4 1 280 0 RW 31 5.14 Exercises 559 | clipped_hennesy_Page_557_Chunk5914 |
560 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.11.4 [5] <5.4> Under what scenarios would entry 2’s valid bit be set to zero? 5.11.5 [5] <5.4> What happens when an instruction writes to VA page 30? When would a software managed TLB be faster than a hardware managed TLB? 5.11.6 [5] <5.4> What happens when an instruction writes to VA page 200? Exercise 5.12 In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. You may find it helpful to draw a table like those found on page 482 to solve the problems in this exercise, as demonstrated below on the address sequence “0, 1, 2, 3, 4.” Address of Memory Block Accessed Hit or Miss Evicted Block Contents of Cache Blocks after Reference Set 0 Set 0 Set 1 Set 1 0 Miss Mem[0] 1 Miss Mem[0] Mem[1] 2 Miss Mem[0] Mem[2] Mem[1] 3 Miss Mem[0] Mem[2] Mem[1] Mem[3] 4 Miss 0 Mem[4] Mem[2] Mem[1] Mem[3] … The following table shows address sequences. Address Sequence a. 0, 2, 4, 8, 10, 12, 14, 16, 0 b. 1, 3, 5, 1, 3, 1, 3, 5, 3 5.12.1 [5] <5.3, 5.5> Assuming an LRU replacement policy, how many hits does this address sequence exhibit? 5.12.2 [5] <5.3, 5.5> Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? 5.12.3 [5] <5.3, 5.5> Simulate a random replacement policy by flipping a coin. For example, “heads” means to evict the first block in a set and “tails” means to evict the second block in a set. How many hits does this address sequence exhibit? | clipped_hennesy_Page_558_Chunk5915 |
5.12.4 [10] <5.3, 5.5> Which address should be evicted at each replacement to maximize the number of hits? How many hits does this address sequence exhibit if you follow this “optimal” policy? 5.12.5 [10] <5.3, 5.5> Describe why it is difficult to implement a cache replacement policy that is optimal for all address sequences. 5.12.6 [10] <5.3, 5.5> Assume you could make a decision upon each memory reference whether or not you want the requested address to be cached. What impact could this have on miss rate? Exercise 5.13 To support multiple virtual machines, two levels of memory virtualization are need ed. Each virtual machine still controls the mapping of virtual address (VA) to physi cal address (PA), while the hypervisor maps the physical address (PA) of each virtual machine to the actual machine address (MA). To accelerate such mappings, a soft ware approach called “shadow paging” duplicates each virtual machine’s page tables in the hypervisor, and intercepts VA to PA mapping changes to keep both copies consistent. To remove the complexity of shadow page tables, a hardware approach called nested page table (or extended page table) explicitly supports two classes of page tables (VA⇨PA and PA⇨MA) and can walk such tables purely in hardware. Consider the following sequence of operations: (1) Create process; (2) TLB miss; (3) page fault; (4) context switch; 5.13.1 [10] <5.4, 5.6> What would happen for the given operation sequence for shadow page table and nested page table, respectively? 5.13.2 [10] <5.4, 5.6> Assuming an x86-based 4-level page table in both guest and nested page table, how many memory references are needed to service a TLB miss for native vs. nested page table? 5.13.3 [15] <5.4, 5.6> Among TLB miss rate, TLB miss latency, page fault rate, and page fault handler latency, which metrics are more important for shadow page table? Which are important for nested page table? The following table shows parameters for a shadow paging system. TLB Misses per 1000 Instructions NPT TLB Miss Latency Page Faults per 1000 Instructions Shadowing Page Fault Overhead 0.2 200 cycles 0.001 30,000 cycles 5.14 Exercises 561 | clipped_hennesy_Page_559_Chunk5916 |
562 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.13.4 [10] <5.6> For a benchmark with native execution CPI of 1, what are the CPI numbers if using shadow page tables vs. NPT (assuming only page table virtualization overhead)? 5.13.5 [10] <5.6> What techniques can be used to reduce page table shadowing induced overhead? 5.13.6 [10] <5.6> What techniques can be used to reduce NPT induced overhead? Exercise 5.14 One of the biggest impediments to widespread use of virtual machines is the per formance overhead incurred by running a virtual machine. The table below lists various performance parameters and application behavior. Base CPI Priviliged O/S Accesses per 10,000 Instructions Performance Impact to Trap to the Guest O/S Performance Impact to Trap to VMM I/O Accesses per 10,000 Instructions I/O Access Time (Includes Time to Trap to Guest O/S) a. 1.5 120 15 cycles 175 cycles 30 1100 cycles b. 1.75 90 20 cycles 140 cycles 25 1200 cycles 5.14.1 [10] <5.6> Calculate the CPI for the system listed above assuming that there are no accesses to I/O. What is the CPI if the VMM performance impact doubles? If it is cut in half? If a virtual machine software company wishes to obtain a 10% performance degradation, what is the longest possible penalty to trap to the VMM? 5.14.2 [10] <5.6> I/O accesses often have a large impact on overall system performance. Calculate the CPI of a machine using the performance characteristics above, assuming a non-virtualized system. Calculate the CPI again, this time using a virtualized system. How do these CPIs change if the system has half the I/O accesses? Explain why I/O bound applications have a smaller impact from virtualization. 5.14.3 [30] <5.4, 5.6> Compare and contrast the ideas of virtual memory and virtual machines. How do the goals of each compare? What are the pros and cons of each? List a few cases where virtual memory is desired, and a few cases where virtual machines are desired. | clipped_hennesy_Page_560_Chunk5917 |
5.14.4 [20] <5.6> Section 5.6 discusses virtualization under the assumption that the virtualized system is running the same ISA as the underlying hardware. However, one possible use of virtualization is to emulate non-native ISAs. An example of this is QEMU, which emulates a variety of ISAs such as MIPS, SPARC, and PowerPC. What are some of the difficulties involved in this kind of virtualization? Is it possible for an emulated system to run faster than on its native ISA? Exercise 5.15 In this exercise, we will explore the control unit for a cache controller for a pro cessor with a write buffer. Use the finite state machine found in Figure 5.34 as a starting point for designing your own finite state machines. Assume that the cache controller is for the simple direct-mapped cache described on page 529, but you will add a write buffer with a capacity of one block. Recall that the purpose of a write buffer is to serve as temporary storage so that the processor doesn’t have to wait for two memory accesses on a dirty miss. Rather than writing back the dirty block before reading the new block, it buffers the dirty block and immediately begins reading the new block. The dirty block can then be written to main memory while the processor is working. 5.15.1 [10] <5.5, 5.7> What should happen if the processor issues a request that hits in the cache while a block is being written back to main memory from the write buffer? 5.15.2 [10] <5.5, 5.7> What should happen if the processor issues a request that misses in the cache while a block is being written back to main memory from the write buffer? 5.15.3 [30] <5.5, 5.7> Design a finite state machine to enable the use of a write buffer. Exercise 5.16 Cache coherence concerns the views of multiple processors on a given cache block. The following table shows two processors and their read/write operations on two different words of a cache block X (initially X[0] = X[1] = 0). P1 P2 a. X[0] ++; X[1] = 3; X[0] = 5; X[1] +=2; b. X[0] =10; X[1] = 3; X[0] = 5; X[1] +=2; 5.14 Exercises 563 | clipped_hennesy_Page_561_Chunk5918 |
564 Chapter 5 Large and Fast: Exploiting Memory Hierarchy 5.16.1 [15] <5.8> List the possible values of the given cache block for a correct cache coherence protocol implementation. List at least one more possible value of the block if the protocol doesn’t ensure cache coherency. 5.16.2 [15] <5.8> For a snooping protocol, list a valid operation sequence on each processor/cache to finish the above read/write operations. 5.16.3 [10] <5.8> What are the best-case and worst-case numbers of cache misses needed to execute the listed read/write instructions? Memory consistency concerns the views of multiple data items. The following ta ble shows two processors and their read/write operations on different cache blocks (A and B initially 0). P1 P2 a. A = 1; B = 2; A+=2; B++; C = B; D = A; b. A = 1; B = 2; A=5; B++; C = B; D = A; 5.16.4 [15] <5.8> List the possible values of C and D for an implementation that ensures both consistency assumptions on page 538. 5.16.5 [15] <5.8> List at least one more possible pair of values for C and D if such assumptions are not maintained. 5.16.6 [15] <5.2, 5.8> For various combinations of write policies and write allocation policies, which combinations make the protocol implementation simpler? Exercise 5.17 Both Barcelona and Nehalem are chip multiprocessors (CMPs), having multiple cores and their caches on a single chip. CMP on-chip L2 cache design has interest ing trade-offs. The following table shows the miss rates and hit latencies for two benchmarks with private vs. shared L2 cache designs. Assume L1 cache misses once every 32 instructions. Private Shared Benchmark A misses-per-instruction 0.30% 0.12% Benchmark B misses-per-instruction 0.06% 0.03% | clipped_hennesy_Page_562_Chunk5919 |
The next table shows hit latencies. Private Cache Shared Cache Memory a. 5 20 180 b. 10 50 120 5.17.1 [15] <5.10> Which cache design is better for each of these benchmarks? Use data to support your conclusion. 5.17.2 [15] <5.10> Shared cache latency increases with the CMP size. Choose the best design if the shared cache latency doubles. Off-chip bandwidth becomes the bottleneck as the number of CMP cores increases. Choose the best design if off- chip memory latency doubles. 5.17.3 [10] <5.10> Discuss the pros and cons of shared vs. private L2 caches for both single-threaded, multi-threaded, and multiprogrammed workloads, and reconsider them if having on-chip L3 caches. 5.17.4 [15] <5.10> Assume both benchmarks have a base CPI of 1 (ideal L2 cache). If having non-blocking cache improves the average number of concurrent L2 misses from 1 to 2, how much performance improvement does this provide over a shared L2 cache? How much improvement can be achieved over private L2? 5.17.5 [10] <5.10> Assume new generations of processors double the number of cores every 18 months. To maintain the same level of per-core performance, how much more off-chip memory bandwidth is needed for a 2012 processor? 5.17.6 [15] <5.10> Consider the entire memory hierarchy. What kinds of optimizations can improve the number of concurrent misses? Exercise 5.18 In this exercise we show the definition of a web server log and examine code opti mizations to improve log processing speed. The data structure for the log is defined as follows: struct entry { int srcIP; // remote IP address char URL[128]; // request URL (e.g., “GET index.html”) long long refTime; // reference time int status; // connection status char browser[64]; // client browser name } log [NUM_ENTRIES]; 5.14 Exercises 565 | clipped_hennesy_Page_563_Chunk5920 |
566 Chapter 5 Large and Fast: Exploiting Memory Hierarchy Some processing functions on a log are: a. topK_sourceIP (int hour); b. browser_histogram (int srcIP); // browsers of a given IP 5.18.1 [5] <5.11> Which fields in a log entry will be accessed for the given log processing function? Assuming 64-byte cache blocks and no prefetching, how many cache misses per entry does the given function incur on average? 5.18.2 [10] <5.11> How can you reorganize the data structure to improve cache utilization and access locality? Show your structure definition code. 5.18.3 [10] <5.11> Give an example of another log processing function that would prefer a different data structure layout. If both functions are important, how would you rewrite the program to improve the overall performance? Supplement the discussion with code snippet and data. For the problems below, use data from “Cache Performance for SPEC CPU2000 Benchmarks” (http://www.cs.wisc.edu/multifacet/misc/spec2000cache-data/) for the pairs of benchmarks shown in the following table. a. Mesa / gcc b. mcf / swim 5.18.4 [10] <5.11> For 64 KB data caches with varying set associativities, what are the miss rates broken down by miss types (cold, capacity, and conflict misses) for each benchmark? 5.18.5 [10] <5.11> Select the set associativity to be used by a 64 KB L1 data cache shared by both benchmarks. If the L1 cache has to be directly mapped, select the set associativity for the 1 MB L2 cache. 5.18.6 [20] <5.11> Give an example in the miss rate table where higher set associativity actually increases miss rate. Construct a cache configuration and reference stream to demonstrate this. | clipped_hennesy_Page_564_Chunk5921 |
§5.1, page 457: 1 and 4. (3 is false because the cost of the memory hierarchy varies per computer, but in 2008 the highest cost is usually the DRAM.) §5.2, page 475: 1 and 4: A lower miss penalty can enable smaller blocks, since you don’t have that much latency to amortize, yet higher memory bandwidth usually leads to larger blocks, since the miss penalty is only slightly larger. §5.3, page 491: 1. §5.4, page 517: 1-a, 2-c, 3-b, 4-d. §5.5, page 525: 2. (Both large block sizes and prefetching may reduce compulsory misses, so 1 is false.) Answers to Check Yourself 5.14 Exercises 567 | clipped_hennesy_Page_565_Chunk5922 |
6 Combining bandwidth and storage . . . enables swift and reliable access to the ever-expanding troves of content on the proliferating disks and . . . repositories of the Internet. George Gilder The End Is Drawing Nigh, 2000 Storage and Other I/O Topics 6.1 Introduction 570 6.2 Dependability, Reliability, and Availability 573 6.3 Disk Storage 575 6.4 Flash Storage 580 6.5 Connecting Processors, Memory, and I/O Devices 582 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System 586 Computer Organization and Design. DOI: 10.1016/B978-0-12-374750-1.00006-2 © 2012 Elsevier, Inc. All rights reserved. | clipped_hennesy_Page_566_Chunk5923 |
6.7 I/O Performance Measures: Examples from Disk and File Systems 596 6.8 Designing an I/O System 598 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 599 6.10 Real Stuff: Sun Fire x4150 Server 606 6.11 Advanced Topics: Networks 612 6.12 Fallacies and Pitfalls 613 6.13 Concluding Remarks 617 6.14 Historical Perspective and Further Reading 618 6.15 Exercises 619 The Five Classic Components of a Computer | clipped_hennesy_Page_567_Chunk5924 |
570 Chapter 6 Storage and Other I/O Topics 6.1 Introduction Although users can get frustrated if their computer hangs and must be rebooted, they become apoplectic if their storage system crashes and they lose information. Thus, the standard for dependability is much higher for storage than for computa tion. Networks also plan for failures in communication, including several mecha nisms to detect and recover from such failures. Hence, I/O systems generally place much greater emphasis on dependability and cost, while processors and memory focus on performance and cost. I/O systems must also plan for expandability and for diversity of devices, which is not a concern for processors. Expandability is related to storage capacity, which is another design parameter for I/O systems; systems may need a lower bound of storage capacity to fulfill their role. Although performance plays a smaller role for I/O, it is more complex. For example, with some devices we may care primarily about access latency, while FIGURE 6.1 A typical collection of I/O devices. The connections between the I/O devices, processor, and memory are historically called buses, although the term means shared parallel wires and most I/O connections today are closer to dedicated serial lines. Communication among the devices and the pro cessor uses both interrupts and protocols on the interconnect, as we will see in this chapter. Figure 6.9 shows the organization for a desktop PC. Disk Disk Processor Cache Memory-I/O Interconnect Main memory I/O controller I/O controller I/O controller Graphics output Network Interrupts | clipped_hennesy_Page_568_Chunk5925 |
with others throughput is crucial. Furthermore, performance depends on many aspects of the system: the device characteristics, the connection between the device and the rest of the system, the memory hierarchy, and the operating system. All of the components, from the individual I/O devices to the processor to the system software, will affect the dependability, expandability, and performance of tasks that include I/O. Figure 6.1 shows the structure of a simple system with its I/O. I/O devices are incredibly diverse. Three characteristics are useful in organizing this wide variety: ■ ■Behavior: Input (read once), output (write only, cannot be read), or storage (can be reread and usually rewritten). ■ ■Partner: Either a human or a machine is at the other end of the I/O device, either feeding data on input or reading data on output. ■ ■Data rate: The peak rate at which data can be transferred between the I/O device and the main memory or processor. It is useful to know the maximum demand the device may generate when designing an I/O system. For example, a keyboard is an input device used by a human with a peak data rate of about 10 bytes per second. Figure 6.2 shows some of the I/O devices connected to computers. Device Behavior Partner Data rate (Mbit/sec) Keyboard Input Human 30,000.0001 Mouse Input Human 30,000.0038 Voice input Input Human 30,000.2640 Sound input Input Machine 30,003.0000 Scanner Input Human 30,003.2000 Voice output Output Human 30,000.2640 Sound output Output Human 30,008.0000 Laser printer Output Human 30,003.2000 Graphics display Output Human 800.0000–8000.0000 Cable modem Input or output Machine 0.1280–6.0000 Network/LAN Input or output Machine 100.0000–10000.0000 Network/wireless LAN Input or output Machine 11.0000–54.0000 Optical disk Storage Machine 30,080.0000–220.0000 Magnetic tape Storage Machine 005.0000–120.0000 Flash memory Storage Machine 32.0000–200.0000 Magnetic disk Storage Machine 800.0000–3000.0000 FIGURE 6.2 The diversity of I/O devices. I/O devices can be distinguished by whether they serve as input, output, or storage devices; their communication partner (people or other computers); and their peak communication rates. The data rates span eight orders of magnitude. Note that a network can be an input or an output device, but cannot be used for storage. Transfer rates for devices are always quoted in base 10, so that 10 Mbit/sec = 10,000,000 bits/sec. 6.1 Introduction 571 | clipped_hennesy_Page_569_Chunk5926 |
572 Chapter 6 Storage and Other I/O Topics In Chapter 1, we briefly discussed four important I/O devices: mice, graphics displays, disks, and networks. In this chapter we go into much more depth on storage and related items. On the CD, there is an advanced topics section on networks, which are well covered in other books. How we should assess I/O performance often depends on the application. In some environments, we may care primarily about system throughput. In these cases, I/O bandwidth will be most important. Even I/O bandwidth can be mea sured in two different ways: 1. How much data can we move through the system in a certain time? 2. How many I/O operations can we do per unit of time? Which performance measurement is best may depend on the environment. For example, in many multimedia applications, most I/O requests are for long streams of data, and transfer bandwidth is the important characteristic. In another environment, we may wish to process a large number of small, unrelated accesses to an I/O device. An example of such an environment might be a tax-processing office of the U.S. National Income Tax Service (NITS). NITS mostly cares about processing a large number of forms in a given time; each tax form is stored sepa rately and is fairly small. A system oriented toward large file transfer may be satis factory, but an I/O system that can support the simultaneous transfer of many small files may be cheaper and faster for processing millions of tax forms. In other applications, we care primarily about response time, which you will recall is the total elapsed time to accomplish a particular task. If the I/O requests are extremely large, response time will depend heavily on bandwidth, but in many environments, most accesses will be small, and the I/O system with the lowest latency per access will deliver the best response time. On single-user machines such as desktop computers and laptops, response time is the key performance characteristic. A large number of applications, especially in the vast commercial market for computing, require both high throughput and short response times. Examples include automatic teller machines (ATMs), order entry and inventory tracking systems, file servers, and Web servers. In such environments, we care about both how long each task takes and how many tasks we can process in a second. The number of ATM requests you can process per hour doesn’t matter if each one takes 15 minutes—you won’t have any customers left! Similarly, if you can process each ATM request quickly but can only handle a small number of requests at once, you won’t be able to support many ATMs, or the cost of the computer per ATM will be very high. In summary, the three classes of desktop, server, and embedded computers are sensitive to I/O dependability and cost. Desktop and embedded systems are more focused on response time and diversity of I/O devices, while server systems are more focused on throughput and expandability of I/O devices. I/O requests Reads or writes to I/O devices. | clipped_hennesy_Page_570_Chunk5927 |
6.2 Dependability, Reliability, and Availability Users crave dependable storage, but how do you define it? In the computer indus try, it is harder than looking it up in the dictionary. After considerable debate, the following is considered the standard definition [Laprie, 1985]: Computer system dependability is the quality of delivered service such that reliance can justifiably be placed on this service. The service delivered by a system is its observed actual behavior as perceived by other system(s) interacting with this system’s users. Each module also has an ideal specified behavior, where a service specification is an agreed description of the expected behavior. A system failure occurs when the actual behavior deviates from the specified behavior. Thus, you need a reference specification of expected behavior to be able to determine dependability. Users can then see a system alternating between two states of delivered service with respect to the service specification: 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the speci fied service Transitions from state 1 to state 2 are caused by failures, and transitions from state 2 to state 1 are called restorations. Failures can be permanent or intermittent. The latter is the more difficult case; it is harder to diagnose the problem when a system oscillates between the two states. Permanent failures are far easier to diagnose. This definition leads to two related terms: reliability and availability. Reliability is a measure of the continuous service accomplishment—or, equiva lently, of the time to failure—from a reference point. Hence, the mean time to failure (MTTF) of disks in Figure 6.5 below is a reliability measure. A related term is annual failure rate (AFR), which is just the percentage of devices that would be expected to fail in a year for a given MTTF. Service interruption is measured as mean time to repair (MTTR). Mean time between failures (MTBF) is simply the sum of MTTF + MTTR. Although MTBF is widely used, MTTF is often the more appropriate term. Availability is a measure of service accomplishment with respect to the alter nation between the two states of accomplishment and interruption. Availability is statistically quantified as Availability = MTTF (MTTF + MTTR) 6.2 Dependability, Reliability, and Availability 573 | clipped_hennesy_Page_571_Chunk5928 |
574 Chapter 6 Storage and Other I/O Topics Note that reliability and availability are actually quantifiable measures, rather than just synonyms for dependability. What is the cause of failures? Figure 6.3 summarizes many papers that have col lected data on reasons for computer systems and telecommunications systems to fail. Clearly, human operators are a significant source of failures. Operator Software Hardware System Year data collected 42% 25% 18% Datacenter (Tandem) 1985 15% 55% 14% Datacenter (Tandem) 1989 18% 44% 39% Datacenter (DEC VAX) 1985 50% 20% 30% Datacenter (DEC VAX) 1993 50% 14% 19% U.S. public telephone network 1996 54% 7% 30% U.S. public telephone network 2000 60% 25% 15% Internet services 2002 FIGURE 6.3 Summary of studies of reasons for failures. Although it is difficult to collect data to determine whether operators are the cause of errors, since operators often record the reasons for failures, these studies did capture that data. There were often other categories, such as environmental reasons for outages, but they were generally small. The top two rows come from a classic paper by Jim Gray [1990], which is still widely quoted almost 20 years after the data was collected. The next two rows are from a paper by Murphy and Gent, who studied causes of outages in VAX systems over time [“Measuring system and software reliability using an automated data collection process,” Quality and Reliability Engineering International 11:5, September–October 1995, 341–53]. The fifth and sixth rows are studies of FCC failure data about the U.S. public switched telephone network by Kuhn [“Sources of failure in the public switched telephone network,” IEEE Computer 30:4, April 1997, 31–36] and by Patty Enriquez. The study of three Internet services is from Oppenheimer, Ganapath, and Patterson [2003]. To increase MTTF, you can improve the quality of the components or design systems to continue operation in the presence of components that have failed. Hence, failure needs to be defined with respect to a context. A failure in a compo nent may not lead to a failure of the system. To make this distinction clear, the term fault is used to mean failure of a component. Here are three ways to improve MTTF: 1. Fault avoidance: Preventing fault occurrence by construction. 2. Fault tolerance: Using redundancy to allow the service to comply with the service specification despite faults occurring, which applies primarily to hardware faults. Section 6.9 describes the RAID approaches to making storage dependable via fault tolerance. 3. Fault forecasting: Predicting the presence and creation of faults, which applies to hardware and software faults, allowing the component to be replaced before it fails. Shrinking MTTR can help availability as much as increasing MTTF. For example, tools for fault detection, diagnosis, and repair can help reduce the time to repair faults by people, software, and hardware. | clipped_hennesy_Page_572_Chunk5929 |
Which of the following are true about dependability? 1. If a system is up, then all its components are accomplishing their expected service. 2. Availability is a quantitative measure of the percentage of time a system is accomplishing its expected service. 3. Reliability is a quantitative measure of continuous service accomplishment by a system. 4. The major source of outages today is software. 6.3 Disk Storage As mentioned in Chapter 1, magnetic disks rely on a rotating platter coated with a magnetic surface and use a moveable read/write head to access the disk. Disk stor age is nonvolatile—the data remains even when power is removed. A magnetic disk consists of a collection of platters (1–4), each of which has two recordable disk surfaces. The stack of platters is rotated at 5400 to 15,000 RPM and has a diameter from 1-inch to just over 3.5 inches. Each disk surface is divided into concentric circles, called tracks. There are typically 10,000 to 50,000 tracks per surface. Each track is in turn divided into sectors that contain the information; each track may have 100 to 500 sectors. Sectors are typically 512 bytes in size, although there is an initiative to increase the sector size to 4096 bytes. The sequence recorded on the magnetic media is a sector number, a gap, the information for that sector including error correction code (see Appendix C, page C-66), a gap, the sector number of the next sector, and so on. Originally, all tracks had the same number of sectors and hence the same num ber of bits. With the introduction of zone bit recording (ZBR) in the early 1990s, disk drives changed to a varying number of sectors (and hence bits) per track, instead keeping the spacing between bits constant. ZBR increases the number of bits on the outer tracks and thus increases the drive capacity. As we saw in Chapter 1, to read and write information the read/write heads must be moved so that they are over the correct location. The disk heads for each surface are connected together and move in conjunction, so that every head is over the same track of every surface. The term cylinder is used to refer to all the tracks under the heads at a given point on all surfaces. To access data, the operating system must direct the disk through a three-stage process. The first step is to position the head over the proper track. This operation is called a seek, and the time to move the head to the desired track is called the seek time. Check Yourself nonvolatile Storage device where data retains its value even when power is removed. track One of thousands of concentric circles that makes up the surface of a magnetic disk. sector One of the segments that make up a track on a magnetic disk; a sector is the smallest amount of information that is read or written on a disk. seek The process of positioning a read/write head over the proper track on a disk. 6.3 Disk Storage 575 | clipped_hennesy_Page_573_Chunk5930 |
576 Chapter 6 Storage and Other I/O Topics Disk manufacturers report minimum seek time, maximum seek time, and average seek time in their manuals. The first two are easy to measure, but the aver age is open to wide interpretation because it depends on the seek distance. The industry has decided to calculate average seek time as the sum of the time for all possible seeks divided by the number of possible seeks. Average seek times are usually advertised as 3 ms to 13 ms, but, depending on the application and sched uling of disk requests, the actual average seek time may be only 25% to 33% of the advertised number because of locality of disk references. This locality arises both because of successive accesses to the same file and because the operating system tries to schedule such accesses together. Once the head has reached the correct track, we must wait for the desired sec tor to rotate under the read/write head. This time is called the rotational latency or rotational delay. The average latency to the desired information is halfway around the disk. Because the disks rotate at 5400 RPM to 15,000 RPM, the average rotational latency is between Average rotational latency = 0.5 rotation 5400 RPM = 0.5 rotation 5400 RPM/( 60 seconds minute ) = 0.0056 seconds = 5.6 ms and Average rotational latency = 0.5 rotation 15,000 RPM = 0.5 rotation 15,000 RPM/( 60 seconds minute ) = 0.0020 seconds = 2.0 ms The last component of a disk access, transfer time, is the time to transfer a block of bits. The transfer time is a function of the sector size, the rotation speed, and the recording density of a track. Transfer rates in 2008 were between 70 and 125 MB/sec. The one complication is that most disk controllers have a built-in cache that stores sectors as they are passed over; transfer rates from the cache are typically higher and may be up to 375 MB/sec (3 Gbit/sec) in 2008. Today, most disk transfers are multiple sectors in length. A disk controller usually handles the detailed control of the disk and the transfer between the disk and the memory. The controller adds the final component of disk access time, controller time, which is the overhead the controller imposes in performing an I/O access. The average time to perform an I/O operation will con sist of these four times plus any wait time incurred because other processes are using the disk. rotational latency Also called rotational delay. The time required for the desired sector of a disk to rotate under the read/write head; usually assumed to be half the rotation time. | clipped_hennesy_Page_574_Chunk5931 |
Disk Read Time What is the average time to read or write a 512-byte sector for a typical disk rotating at 15,000 RPM? The advertised average seek time is 4 ms, the transfer rate is 100 MB/sec, and the controller overhead is 0.2 ms. Assume that the disk is idle so that there is no waiting time. Average disk access time is equal to average seek time + average rotational delay + transfer time + controller overhead. Using the advertised average seek time, the answer is 4.0 ms + 0.5 rotation 15,000 RPM + 0.5 KB 100 MB/sec + 0.2 ms = 4.0 + 2.0 + 0.005 + 0.2 = 6.2 ms If the measured average seek time is 25% of the advertised average time, the answer is 1.0 ms + 2.0 ms + 0.005 ms + 0.2 ms = 3.2 ms Notice that when we consider measured average seek time, as opposed to advertised average seek time, the rotational latency can be the largest compo nent of the access time. Disk densities have continued to increase for more than 50 years. The impact of this compounded improvement in density and the reduction in physical size of a disk drive has been amazing, as Figure 6.4 shows. The aims of different disk designers have led to a wide variety of drives being available at any particular time. Figure 6.5 shows the characteristics of four magnetic disks. In 2008, these disks from a single manufacturer cost between $0.30 and $5.00 per gigabyte. In the broader market, prices generally range between $0.20 and $2.00 per gigabyte, depending on size, interface, and performance. While disks will remain viable for the foreseeable future, the conventional wisdom about where block numbers are found has not. The assumptions of the sector-track-cylinder model are that nearby blocks are on the same track, blocks in the same cylinder take less time to access since there is no seek time, and some tracks are closer than others. The reason for the breakdown was the raising of the level of the interfaces. Higher-level intelligent interfaces like ATA and SCSI required a microprocessor inside a disk, which lead to performance optimizations. To speed-up sequential transfers, these higher-level interfaces organize disks more like tapes than like random access devices. The logical blocks are ordered in serpentine fashion across a single surface, trying to capture all the sectors that are recorded at the same bit density. Hence, sequential blocks may be on different tracks. We will see an example in Figure 6.19 of the pitfall of assuming the conventional sector-track-cylinder model. EXAMPLE ANSWER Advanced Technology Attachment (ATA) A command set used as a standard for I/O devices that is popular in the PC. Small Computer Systems Interface (SCSI) A command set used as a standard for I/O devices. 6.3 Disk Storage 577 | clipped_hennesy_Page_575_Chunk5932 |
578 Chapter 6 Storage and Other I/O Topics FIGURE 6.4 Six magnetic disks, varying in diameter from 14 inches down to 1.8 inches. The pictured disks were introduced over more than 15 years ago and hence are not intended to be represen tative of the best capacity of modern disks of these diameters. This photograph does, however, accurately portray their relative physical sizes. The widest disk is the DEC R81, containing four 14-inch diameter plat ters and storing 456 MB. It was manufactured in 1985. The 8-inch diameter disk comes from Fujitsu, and this 1984 disk stores 130 MB on six platters. The Micropolis RD53 has five 5.25-inch platters and stores 85 MB. The IBM 0361 also has five platters, but these are just 3.5 inches in diameter. This 1988 disk holds 320 MB. In 2008, the most dense 3.5-inch disk had 2 platters and held 1 TB in the same space, yielding an increase in density of about 3000 times! The Conner CP 2045 has two 2.5-inch platters containing 40 MB and was made in 1990. The smallest disk in this photograph is the Integral 1820. This single 1.8-inch platter contains 20 MB and was made in 1992. Elaboration: These high-level interfaces let disk controllers add caches, which allow for fast access to data that was recently read between transfers requested by the processor. They use write-through and do not update on a write miss, and often also include prefetch algorithms to try to anticipate demand. Controllers also use a com mand queue that allow the disk to decide in what order to perform the commands to maximize performance while maintaining correct behavior. Of course, such capabilities complicate the measurement of disk performance and increase the importance of workload choice when comparing disks. | clipped_hennesy_Page_576_Chunk5933 |
Characteristics Seagate ST33000655SS Seagate ST31000340NS Seagate ST973451SS Seagate ST9160821AS Disk diameter (inches) 3.50 3.50 2.50 2.50 Formatted data capacity (GB) 147 1000 73 160 Number of disk surfaces (heads) 2 4 2 2 Rotation speed (RPM) 15,000 7200 15,000 5400 Internal disk cache size (MB) 16 32 16 8 External interface, bandwidth (MB/sec) SAS, 375 SATA, 375 SAS, 375 SATA, 150 Sustained transfer rate (MB/sec) 73–125 105 79–112 44 Minimum seek (read/write) (ms) 0.2/0.4 0.8/1.0 0.2/0.4 1.5/2.0 Average seek read/write (ms) 3.5/4.0 8.5/9.5 2.9/3.3 12.5/13.0 Mean time to failure (MTTF) (hours) 1,400,000 @ 25°C 1,200,000 @ 25°C 1,600,000 @ 25°C — Annual failure rate (AFR) (percent) 0.62% 0.73% 0.55% — Contact start-stop cycles — 50,000 — >600,000 Warranty (years) 5 5 5 5 Nonrecoverable read errors per bits read <1 sector per 1016 <1 sector per 1015 <1 sector per 1016 <1 sector per 1014 Temperature, shock (operating) 5°–55°C, 60 G 5°–55°C, 63 G 5°–55°C, 60 G 0°–60°C, 350 G Size: dimensions (in.), weight (pounds) 1.0" × 4.0" × 5.8", 1.5 lbs 1.0" × 4.0" × 5.8", 1.4 lbs 0.6" × 2.8" × 3.9", 0.5 lbs 0.4" × 2.8" × 3.9", 0.2 lbs Power: operating/idle/ standby (watts) 15/11/— 11/8/1 8/5.8/— 1.9/0.6/0.2 GB/cu. in., GB/watt 6 GB/cu.in., 10 GB/W 43 GB/cu.in., 91 GB/W 11 GB/cu.in., 9 GB/W 37 GB/cu.in., 84 GB/W Price in 2008, $/GB ~ $250, ~ $1.70/GB ~ $275, ~ $0.30/GB ~ $350, ~ $5.00/GB ~ $100, ~ $0.60/GB FIGURE 6.5 Characteristics of four magnetic disks by a single manufacturer in 2008. The three leftmost drives are for servers and desktops while the rightmost drive is for laptops. Note that the third drive is only 2.5 inches in diameter, but it is a high performance drive with the highest reliability and fastest seek time. The disks shown here are either serial versions of the interface to SCSI (SAS), a standard I/O bus for many systems, or serial version of ATA (SATA), a standard I/O bus for PCs. The transfer rates from the caches is 3–5 times faster than the transfer rate from the disk surface. The much lower cost per gigabyte of the SATA 3.5-inch drive is primarily due to the hyper-competitive PC market, although there are differences in performance in I/Os per second due to faster rotation and faster seek times for SAS. The service life for these disks is five years. Note that the quoted MTTF assumes nominal power and temperature. Disk lifetimes can be much shorter if temperature and vibration are not controlled. See the link to Seagate at www.seagate.com for more information on these drives. Which of the following are true about disk drives? 1. 3.5-inch disks perform more IOs per second than 2.5-inch disks. 2. 2.5-inch disks offer the highest gigabytes per watt. 3. It takes hours to read the contents of a high capacity disk sequentially. 4. It takes months to read the contents of a high capacity disk using random 512-byte sectors. Check Yourself 6.3 Disk Storage 579 | clipped_hennesy_Page_577_Chunk5934 |
580 Chapter 6 Storage and Other I/O Topics 6.4 Flash Storage. Many have tried to invent a technology to replace disks, and many have failed: CCD memory, bubble memory, and holographic memory were all found wanting. By the time a new technology would ship, disks made advances as predicted earlier, costs dropped accordingly, and the challenging product would be unattractive in the marketplace. The first credible challenger is flash memory. This semiconductor memory is nonvolatile like disks, but latency is 100–1000 times faster than disk, and it is smaller, more power efficient, and more shock resistant. Equally important, because of the popularity of flash memory in cell phones, digital cameras, and MP3 players, there is a large market to pay for the investment in improving flash memory technology. Recently, flash memory cost per gigabyte has been falling 50% per year. In 2008, the price per gigabyte of flash was $4 to $10 per gigabyte, or about 2 to 40 times higher than disk and 5 to 10 times lower than DRAM. Figure 6.6 compares three flash-based products. Characteristics Kingston SecureDigital (SD) SD4/8 GB Transend Type I CompactFlash TS16GCF133 RiDATA Solid State Disk 2.5 inch SATA Formatted data capacity (GB) 8 16 32 Bytes per sector 512 512 512 Data transfer rate (read/write MB/sec) 4 20/18 68/50 Power operating/standby (W) 0.66/0.15 0.66/0.15 2.1/— Size: height × width × depth (inches) 0.94 × 1.26 × 0.08 1.43 × 1.68 × 0.13 0.35 × 2.75 × 4.00 Weight in grams (454 grams/pound) 2.5 11.4 52 Mean time between failures (hours) > 1,000,000 > 1,000,000 > 4,000,000 GB/cu. in., GB/watt 84 GB/cu.in., 12 GB/W 51 GB/cu.in., 24 GB/W 8 GB/cu.in., 16 GB/W Best price (2008) ~ $30 ~ $70 ~ $300 FIGURE 6.6 Characteristics of three flash storage products. The CompactFlash standard package was proposed by Sandisk Corporation in 1994 for the PCMCIA-ATA cards of portable PCs. Because it follows the ATA interface, it simulates a disk interface, including seek commands, logical tracks, and so on. The RiDATA product imitates an SATA 2.5-inch disk interface. Although its cost per gigabyte is higher than disks, flash memory is popular in mobile devices in part because it comes in smaller capacities. As a result, the 1-inch | clipped_hennesy_Page_578_Chunk5935 |
diameter hard disks are disappearing from some embedded markets. For example, in 2008 the Apple iPod Shuffle MP3 player sold for $50 and held 1 GB, while the smallest disk holds 4 GB and sells for more than the whole MP3 player. Flash memory is a type of electrically erasable programmable read-only mem ory (EEPROM). The first flash memory, called NOR flash because of the similarity of the storage cell to a standard NOR gate, was a direct competitor with other EEPROMs and is randomly addressable like any memory. A few years later, NAND flash memory offered greater storage density, but memory could only be read and written in blocks as wiring needed for random accesses was removed. NAND flash is much less expensive per gigabyte and much more popular than NOR flash; all of the products in Figure 6.6 use NAND flash. Figure 6.7 compares the key characteristics of NOR versus NAND flash memory. Unlike disks and DRAM, but like other EEPROM technologies, flash memory bits wear out (see Figure 6.7). To cope with such limits, most NAND flash products include a controller to spread the writes by remapping blocks that have been written many times to less trodden blocks. This technique is called wear leveling. With wear leveling, consumer products like cell phones, digital cameras, MP3 players, or memory keys are very unlikely to exceed the write limits in the flash. Such controllers lower the potential performance of flash, but they are needed unless higher-level software monitors block wear. However, controllers can also improve yield by mapping out memory cells that were manufactured incorrectly. Write limits are one reason flash memory is not popular in desktop and server computers. However, in 2008 the first laptops are being sold with flash memory instead of hard disks at a considerable price premium to offer faster boot times, smaller size, and longer battery life. There are also flash memories available in standard disk form factors, as Figure 6.6 shows. Combining both ideas, hybrid hard disks include, say, a gigabyte of flash memory so that laptops can boot more quickly and save energy by allowing the disks to remain idle more frequently. In the coming years, it appears that flash will compete successfully with hard disks for many battery-operated devices. As capacity increases and the cost per Characteristics NOR Flash Memory NAND Flash Memory Typical use BIOS memory USB key Minimum access size (bytes) 512 bytes 2048 bytes Read time (microseconds) 0.08 25 Write time (microseconds) 10.00 1500 to erase + 250 Read bandwidth (MBytes/second) 10 40 Write bandwidth (MBytes/second) 0.4 8 Wearout (writes per cell) 100,000 10,000 to 100,000 Best price/GB (2008) $65 $4 FIGURE 6.7 Characteristics of NOR versus NAND flash memory in 2008. These devices can read bytes and 16-bit words despite their large access sizes. 6.4 Flash Storage 581 | clipped_hennesy_Page_579_Chunk5936 |
582 Chapter 6 Storage and Other I/O Topics gigabyte continues to decline, it will be interesting to see whether the higher performance and energy efficiency of flash memory will yield opportunities in the desktop and server markets as well. Which of the following are true about flash memory? 1. Like DRAM, flash is a semiconductor memory. 2. Like disks, flash does not lose information if it loses power. 3. The read access time of NOR flash is similar to DRAM. 4. The read bandwidth of NAND flash is similar to disk. 6.5 Connecting Processors, Memory, and I/O Devices In a computer system, the various subsystems must have interfaces to one another. For example, the memory and processor need to communicate, as do the proces sor and the I/O devices. For many years, this has been done with a bus. A bus is a shared communication link, which uses one set of wires to connect multiple sub systems. The two major advantages of the bus organization are versatility and low cost. By defining a single connection scheme, new devices can easily be added, and peripherals can even be moved between computer systems that use the same kind of bus. Furthermore, buses are cost-effective, because a single set of wires is shared in multiple ways. The major disadvantage of a bus is that it creates a communication bottleneck, possibly limiting the maximum I/O throughput. When I/O must pass through a single bus, the bandwidth of that bus limits the maximum I/O throughput. Designing a bus system capable of meeting the demands of the processor as well as connecting large numbers of I/O devices to the machine presents a major challenge. Buses are traditionally classified as processor-memory buses or I/O buses. Processor-memory buses are short, generally high speed, and matched to the memory system so as to maximize memory-processor bandwidth. I/O buses, by contrast, can be lengthy, can have many types of devices connected to them, and often have a wide range in the data bandwidth of the devices connected to them. I/O buses do not typically interface directly to the memory but use either a processor- memory or a backplane bus to connect to memory. Other buses with different characteristics have emerged for special functions, such as graphics buses. One reason bus design is so difficult is that the maximum bus speed is largely limited by physical factors: the length of the bus and the number of devices. These physical limits prevent us from running the bus arbitrarily fast. In addition, the Check Yourself processor-memory bus A bus that connects processor and memory and that is short, generally high speed, and matched to the memory system so as to maximize memory- processor bandwidth. backplane bus A bus that is designed to allow processors, memory, and I/O devices to coexist on a single bus. | clipped_hennesy_Page_580_Chunk5937 |
need to support a range of devices with widely varying latencies and data transfer rates also makes bus design challenging. As it became difficult to run many parallel wires at high speed due to clock skew and reflection (see Appendix C), the industry transitioned from parallel shared buses to high-speed serial point-to-point interconnections with switches. Thus, such I/O networks have generally replaced I/O buses in our systems. As a result of this transition, this section has been revised in this edition to emphasize the general problem of connecting I/O devices, processors, and mem ory, rather than focusing exclusively on buses. Connection Basics Let’s consider a typical I/O transaction. A transaction includes two parts: sending the address and receiving or sending the data. Bus transactions are typically defined by what they do to memory. A read transaction transfers data from mem ory (to either the processor or an I/O device), and a write transaction writes data to the memory. Clearly, this terminology is confusing. To avoid this, we’ll try to use the terms input and output, which are always defined from the perspective of the processor: an input operation is inputting data from the device to memory, where the processor can read it, and an output operation is outputting data to a device from memory where the processor wrote it. The I/O interconnect serves as a way of expanding the machine and connecting new peripherals. To make this easier, the computer industry has developed several standards. The standards serve as a specification for the computer manufacturer and for the peripheral manufacturer. A standard assures the computer designer that peripherals will be available for a new machine, and it ensures the peripheral builder that users will be able to hook up their new equipment. Figure 6.8 sum marizes the key characteristics of the five popular I/O standards: Firewire, USB, PCI Express (PCIe), Serial ATA (SATA), and Serial Attached SCSI (SAS). They connect a variety of devices to the desktop computer, from keyboards to cameras to disks. Traditional buses are synchronous. That means the bus includes a clock in the control lines and a fixed protocol for communicating that is relative to the clock. For example, for performing a read from memory, we might have a protocol that transmits the address and read command on the first clock cycle, using the control lines to indicate the type of request. The memory might then be required to respond with the data word on the fifth clock. This type of protocol can be implemented easily in a small finite-state machine. Because the protocol is predeter mined and involves little logic, the bus can run fast, and the interface logic will be small. Synchronous buses have two major disadvantages, however. First, every device on the bus must run at the same clock rate. Second, because of clock skew problems, synchronous buses cannot be long if they are fast (see Appendix C). These problems led to asynchronous interconnects, which are not clocked. Because they are not clocked, asynchronous interconnects can accommodate a wide variety of devices, and the bus can be lengthened without worrying about I/O transaction A sequence of operations over the interconnect that includes a request and may include a response, either of which may carry data. A transaction is initiated by a single request and may take many individual bus operations. synchronous bus A bus that includes a clock in the control lines and a fixed protocol for communicating that is relative to the clock. asynchronous interconnect Uses a handshaking protocol for coordinating usage rather than a clock; can accommodate a wide variety of devices of differing speeds. 6.5 Connecting Processors, Memory, and I/O Devices 583 | clipped_hennesy_Page_581_Chunk5938 |
584 Chapter 6 Storage and Other I/O Topics clock skew or synchronization problems. All the examples in Figure 6.8 are asynchronous. To coordinate the transmission of data between sender and receiver, an asyn chronous bus uses a handshaking protocol. A handshaking protocol consists of a series of steps in which the sender and receiver proceed to the next step only when both parties agree. The protocol is implemented with an additional set of control lines. The I/O Interconnects of the x86 Processors Figure 6.9 shows the I/O system of a traditional PC. The processor connects to peripherals via two main chips. The chip next to the processor is the memory controller hub, commonly called the north bridge, and the one connected to it is the I/O controller hub, called the south bridge. The north bridge is basically a DMA controller, connecting the processor to memory, possibly a graphics card, and the south bridge chip. The south bridge connects the north bridge to a cornucopia of I/O buses. Intel, AMD, NVIDIA, and others offer a wide variety of these chip sets to connect the processor to the outside world. Figure 6.10 shows three examples of the chip sets. Note that AMD swallowed the north bridge chip in the Opteron and later products, thereby reducing the chip count and the latency to memory and graphics cards by skipping a chip crossing. As Moore’s law continues, an increasing number of I/O controllers that were formerly available as optional cards that connected to I/O buses have been co-opted into these chip sets. For example, the AMD Opteron X4 and the Intel Nehalem handshaking protocol A series of steps used to coordinate asynchronous bus transfers in which the sender and receiver proceed to the next step only when both parties agree that the current step has been completed. Characteristic Firewire (1394) USB 2.0 PCI Express Serial ATA Serial Attached SCSI Intended use External External Internal Internal External Devices per channel 63 127 1 1 4 Basic data width (signals) 4 2 2 per lane 4 4 Theoretical peak bandwidth 50 MB/sec (Firewire 400) or 100 MB/sec (Firewire 800) 0.2 MB/sec (low speed), 1.5 MB/sec (full speed), or 60 MB/sec (high speed) 250 MB/sec per lane (1x); PCIe cards come as 1x, 2x, 4x, 8x, 16x, or 32x 300 MB/ sec 300 MB/sec Hot pluggable Yes Yes Depends on form factor Yes Yes Maximum bus length (copper wire) 4.5 meters 5 meters 0.5 meters 1 meter 8 meters Standard name IEEE 1394, 1394b USB Implementors Forum PCI-SIG SATA-IO T10 committee FIGURE 6.8 Key characteristics of five dominant I/O standards. The intended use column indicates whether it is designed to be used with cables external to the computer or just inside the computer with short cables or wire on printed circuit boards. PCIe can support simultaneous reads and writes, so some publications double the bandwidth per lane assuming a 50/50 split of read versus write bandwidth. | clipped_hennesy_Page_582_Chunk5939 |
include the north bridge inside the microprocessor, and the south bridge chip of the Intel 975 includes a RAID controller (see Section 6.9). These I/O interconnects provide electrical connectivity among I/O devices, processors, and memory, and also define the lowest-level protocol for commu nication. Above this basic level, we must define hardware and software protocols for controlling data transfers between I/O devices and memory, and for the pro cessor to specify commands to the I/O devices. These topics are covered in the next section. Both networks and buses connect components together. Which of the following are true about them? 1. I/O networks and I/O buses are almost always standardized. 2. I/O networks and I/O buses are almost always synchronous. Check Yourself Parallel ATA (100 MB / sec) PCIe x16 (or 2 PCIe x8) (4 GB / sec) PCIe x4 (1 GB / sec) PCIe x4 (1 GB / sec) ESI (2 GB/sec) PCIe x8 (2 GB/sec) Serial ATA (300 MB/sec) Disk Intel Xeon 5300 processor Intel Xeon 5300 processor Memory controller hub (north bridge) 5000P Main memory DIMMs FB DDR2 667 (5.3 GB/sec) Disk LPC (1 MB/sec) Keyboard, mouse, ... USB 2.0 (60 MB/sec) I/O controller hub (south bridge) Entreprise South Bridge 2 Front Side Bus (1333 MHz, 10.5 GB / sec) CD / DVD PCI-X bus (1 GB / sec) PCI-X bus (1 GB / sec) FIGURE 6.9 Organization of the I/O system on an Intel server using the Intel 5000P chip set. If you assume reads and writes are each half the traffic, you can double the bandwidth per link for PCIe. 6.5 Connecting Processors, Memory, and I/O Devices 585 | clipped_hennesy_Page_583_Chunk5940 |
586 Chapter 6 Storage and Other I/O Topics 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System A bus or network protocol defines how a word or block of data should be commu nicated on a set of wires. This still leaves several other tasks that must be performed to actually cause data to be transferred from a device and into the memory address space of some user program. This section focuses on these tasks and will answer such questions as the following: ■ ■How is a user I/O request transformed into a device command and commu nicated to the device? ■ ■How is data actually transferred to or from a memory location? ■ ■What is the role of the operating system? Intel 5000P chip set Intel 975X chip set AMD 580X CrossFire Target segment Server Performance PC Server/Performance PC Front Side Bus (64 bit) 1066/1333 MHz 800/1066 MHz — Memory controller hub (“north bridge”) Product name Blackbird 5000P MCH 975X MCH Pins 1432 1202 Memory type, speed DDR2 FBDIMM 667/533 DDR2 800/667/533 Memory buses, widths 4 × 72 1 × 72 Number of DIMMs, DRAM/DIMM 16, 1 GB/2 GB/4 GB 4, 1 GB/2 GB Maximum memory capacity 64 GB 8 GB Memory error correction available? Yes No PCIe/External Graphics Interface 1 PCIe x16 or 2 PCIe x 1 PCIe x16 or 2 PCIe x8 South bridge interface PCIe x8, ESI PCIe x8 I/O controller hub (“south bridge”) Product name 6321 ESB ICH7 580X CrossFire Package size, pins 1284 652 549 PCI-bus: width, speed Two 64-bit, 133 MHz 32-bit, 33 MHz, 6 masters — PCI Express ports Three PCIe x4 Two PCIe x16, Four PCI x1 Ethernet MAC controller, interface — 1000/100/10 Mbit — USB 2.0 ports, controllers 6 8 10 ATA ports, speed One 100 Two 100 One 133 Serial ATA ports 6 2 4 AC-97 audio controller, interface — Yes Yes I/O management SMbus 2.0, GPIO SMbus 2.0, GPIO ASF 2.0, GPIO FIGURE 6.10 Two I/O chip sets from Intel and one from AMD. Note that the north bridge functions are included on the AMD microprocessor, as they are on the more recent Intel Nehalem. | clipped_hennesy_Page_584_Chunk5941 |
As we will see in answering these questions, the operating system plays a major role in handling I/O, acting as the interface between the hardware and the program that requests I/O. The responsibilities of the operating system arise from three characteristics of I/O systems: 1. Multiple programs using the processor share the I/O system. 2. I/O systems often use interrupts (externally generated exceptions) to com municate information about I/O operations. Because interrupts cause a transfer to kernel or supervisor mode, they must be handled by the operat ing system (OS). 3. The low-level control of an I/O device is complex, because it requires man aging a set of concurrent events and because the requirements for correct device control are often very detailed. The three characteristics of I/O systems above lead to several different functions the OS must provide: ■ ■The OS guarantees that a user’s program accesses only the portions of an I/O device to which the user has rights. For example, the OS must not allow a program to read or write a file on disk if the owner of the file has not granted access to this program. In a system with shared I/O devices, protection could not be provided if user programs could perform I/O directly. ■ ■The OS provides abstractions for accessing devices by supplying routines that handle low-level device operations. ■ ■The OS handles the interrupts generated by I/O devices, just as it handles the exceptions generated by a program. ■ ■The OS tries to provide equitable access to the shared I/O resources, as well as schedule accesses to enhance system throughput. To perform these functions on behalf of user programs, the operating system must be able to communicate with the I/O devices and to prevent the user program from communicating with the I/O devices directly. Three types of communication are required 1. The OS must be able to give commands to the I/O devices. These commands include not only operations like read and write, but also other operations to be done on the device, such as a disk seek. Hardware/ Software Interface 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System 587 | clipped_hennesy_Page_585_Chunk5942 |
588 Chapter 6 Storage and Other I/O Topics 2. The device must be able to notify the OS when the I/O device has completed an operation or has encountered an error. For example, when a disk completes a seek, it will notify the OS. 3. Data must be transferred between memory and an I/O device. For example, the block being read on a disk read must be moved from disk to memory. In the next few subsections, we will see how these communications are performed. Giving Commands to I/O Devices To give a command to an I/O device, the processor must be able to address the device and to supply one or more command words. Two methods are used to address the device: memory-mapped I/O and special I/O instructions. In memory- mapped I/O, portions of the address space are assigned to I/O devices. Reads and writes to those addresses are interpreted as commands to the I/O device. For example, a write operation can be used to send data to an I/O device where the data will be interpreted as a command. When the processor places the address and data on the memory bus, the memory system ignores the operation because the address indicates a portion of the memory space used for I/O. The device controller, however, sees the operation, records the data, and transmits it to the device as a command. User programs are prevented from issuing I/O operations directly, because the OS does not provide access to the address space assigned to the I/O devices, and thus the addresses are protected by the address translation. Memory-mapped I/O can also be used to transmit data by writing or reading to select addresses. The device uses the address to determine the type of command, and the data may be provided by a write or obtained by a read. In any event, the address encodes both the device identity and the type of transmission between processor and device. Actually performing a read or write of data to fulfill a program request usually requires several separate I/O operations. Furthermore, the processor may have to interrogate the status of the device between individual commands to determine whether the command completed successfully. For example, a simple printer has two I/O device registers—one for status information and one for data to be printed. The Status register contains a done bit, set by the printer when it has printed a character, and an error bit, indicating that the printer is jammed or out of paper. Each byte of data to be printed is put into the Data register. The processor must then wait until the printer sets the done bit before it can place another character in the buffer. The processor must also check the error bit to determine if a problem has occurred. Each of these operations requires a separate I/O device access. memory-mapped I/O An I/O scheme in which portions of address space are assigned to I/O devices, and reads and writes to those addresses are interpreted as commands to the I/O device. | clipped_hennesy_Page_586_Chunk5943 |
Elaboration: The alternative to memory-mapped I/O is to use dedicated I/O instructions in the processor. These I/O instructions can specify both the device number and the command word (or the location of the command word in memory). The processor communicates the device address via a set of wires normally included as part of the I/O bus. The actual command can be transmitted over the data lines in the bus. Examples of computers with I/O instructions are the Intel x86 and the IBM 370 computers. By making the I/O instructions illegal to execute when not in kernel or supervisor mode, user programs can be prevented from accessing the devices directly. Communicating with the Processor The process of periodically checking status bits to see if it is time for the next I/O operation, as in the previous example, is called polling. Polling is the simplest way for an I/O device to communicate with the processor. The I/O device simply puts the information in a Status register, and the processor must come and get the information. The processor is totally in control and does all the work. Polling can be used in several different ways. Real-time embedded applications poll the I/O devices, since the I/O rates are predetermined and it makes I/O over head more predictable, which is helpful for real time. As we will see, this allows polling to be used even when the I/O rate is somewhat higher. The disadvantage of polling is that it can waste a lot of processor time, because processors are so much faster than I/O devices. The processor may read the Status register many times, only to find that the device has not yet completed a compara tively slow I/O operation, or that the mouse has not budged since the last time it was polled. When the device completes an operation, we must still read the status to determine whether it was successful. The overhead in a polling interface was recognized long ago, leading to the invention of interrupts to notify the processor when an I/O device requires atten tion from the processor. Interrupt-driven I/O, which is used by almost all systems for at least some devices, employs I/O interrupts to indicate to the processor that an I/O device needs attention. When a device wants to notify the processor that it has completed some operation or needs attention, it causes the processor to be interrupted. An I/O interrupt is just like the exceptions we saw in Chapters 4 and 5, with two important distinctions: 1. An I/O interrupt is asynchronous with respect to the instruction execution. That is, the interrupt is not associated with any instruction and does not prevent the instruction completion. This is very different from either page fault exceptions or exceptions such as arithmetic overflow. Our control unit need only check for a pending I/O interrupt at the time it starts a new instruction. I/O instruction A dedicated instruction that is used to give a command to an I/O device and that specifies both the device number and the command word (or the location of the command word in memory). polling The process of periodically checking the status of an I/O device to determine the need to service the device. interrupt-driven I/O An I/O scheme that employs interrupts to indicate to the processor that an I/O device needs attention. 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System 589 | clipped_hennesy_Page_587_Chunk5944 |
590 Chapter 6 Storage and Other I/O Topics 2. In addition to the fact that an I/O interrupt has occurred, we would like to convey further information, such as the identity of the device generating the interrupt. Furthermore, the interrupts represent devices that may have dif ferent priorities and whose interrupt requests have different urgencies asso ciated with them. To communicate information to the processor, such as the identity of the device raising the interrupt, a system can use either vectored interrupts or an exception Cause register. When the processor recognizes the interrupt, the device can send either the vector address or a status field to place in the Cause register. As a result, when the OS gets control, it knows the identity of the device that caused the interrupt and can immediately interrogate the device. An interrupt mechanism eliminates the need for the processor to poll the device and instead allows the processor to focus on executing programs. Interrupt Priority Levels To deal with the different priorities of the I/O devices, most interrupt mechanisms have several levels of priority; UNIX operating systems use four to six levels. These priorities indicate the order in which the processor should process interrupts. Both internally generated exceptions and external I/O interrupts have priorities; typically, I/O interrupts have lower priority than internal exceptions. There may be multiple I/O interrupt priorities, with high-speed devices associated with the higher priorities. To support priority levels for interrupts, MIPS provides the primitives that let the operating system implement the policy, similar to the way that MIPS handles TLB misses. Figure 6.11 shows the key registers, and Section B.7 in Appendix B gives more details. The Status register determines who can interrupt the computer. If the interrupt enable bit is 0, then none can interrupt. A more refined blocking of interrupts is available in the interrupt mask field. There is a bit in the mask corresponding to each bit in the pending interrupt field of the Cause register. To enable the corre sponding interrupt, there must be a 1 in the mask field at that bit position. Once an interrupt occurs, the operating system can find the reason in the exception code field of the Status register: 0 means an interrupt occurred, with other values for the exceptions mentioned in Chapter 5. Here are the steps that must occur in handling an interrupt: 1. Logically AND the pending interrupt field and the interrupt mask field to see which enabled interrupts could be the culprit. Copies are made of these two registers using the mfc0 instruction. 2. Select the higher priority of these interrupts. The software convention is that the leftmost is the highest priority. | clipped_hennesy_Page_588_Chunk5945 |
3. Save the interrupt mask field of the Status register. 4. Change the interrupt mask field to disable all interrupts of equal or lower priority. 5. Save the processor state needed to handle the interrupt. 6. To allow higher-priority interrupts, set the interrupt enable bit of the Cause register to 1. 7. Call the appropriate interrupt routine. 8. Before restoring state, set the interrupt enable bit of the Cause register to 0. This allows you to restore the interrupt mask field. Appendix B shows an exception handler for a simple I/O task on pages B-36 to B-37. How do the interrupt priority levels (IPLs) correspond to these mechanisms? The IPL is an operating system invention. It is stored in the memory of the process, and every process is given an IPL. At the lowest IPL, all interrupts are permitted. Conversely, at the highest IPL, all interrupts are blocked. Raising and lowering the IPL involves changes to the interrupt mask field of the Status register. 15 8 4 1 0 Interrupt mask User mode Exception level Interrupt enable 15 31 8 6 2 Pending interrupts Branch delay Exception code FIGURE 6.11 The Cause and Status registers. This version of the Cause register corresponds to the MIPS-32 architecture. The earlier MIPS I architecture had three nested sets of kernel/user and interrupt enable bits to support nested interrupts. Section B.7 in Appendix B has more details about these registers. 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System 591 | clipped_hennesy_Page_589_Chunk5946 |
592 Chapter 6 Storage and Other I/O Topics Elaboration: The two least significant bits of the pending interrupt and interrupt mask fields are for software interrupts, which are lower priority. These are typically used by higher-priority interrupts to leave work for lower-priority interrupts to do once the immedi- ate reason for the interrupt is handled. Once the higher-priority interrupt is finished, the lower-priority tasks will be noticed and handled. Transferring the Data between a Device and Memory We have seen two different methods that enable a device to communicate with the processor. These two techniques—polling and I/O interrupts—form the basis for two methods of implementing the transfer of data between the I/O device and memory. Both these techniques work best with lower-bandwidth devices, where we are more interested in reducing the cost of the device controller and interface than in providing a high-bandwidth transfer. Both polling and interrupt-driven transfers put the burden of moving data and managing the transfer on the proces sor. After looking at these two schemes, we will examine a scheme more suitable for higher-performance devices or collections of devices. We can use the processor to transfer data between a device and memory based on polling. In real-time applications, the processor loads data from I/O device registers and stores them into memory. An alternative mechanism is to make the transfer of data interrupt driven. In this case, the OS would still transfer data in small numbers of bytes from or to the device. But because the I/O operation is interrupt driven, the OS simply works on other tasks while data is being read from or written to the device. When the OS recognizes an interrupt from the device, it reads the status to check for errors. If there are none, the OS can supply the next piece of data, for example, by a sequence of memory-mapped writes. When the last byte of an I/O request has been transmitted and the I/O operation is completed, the OS can inform the pro gram. The processor and OS do all the work in this process, accessing the device and memory for each data item transferred. Interrupt-driven I/O relieves the processor from having to wait for every I/O event, although if we used this method for transferring data from or to a hard disk, the overhead could still be intolerable, since it could consume a large fraction of the processor when the disk was transferring. For high-bandwidth devices like hard disks, the transfers consist primarily of relatively large blocks of data (hundreds to thousands of bytes). Thus, computer designers invented a mechanism for offloading the processor and having the device controller transfer data directly to or from the memory without involving the processor. This mechanism is called direct memory access (DMA). The interrupt mechanism is still used by the device to communicate with the processor, but only on completion of the I/O transfer or when an error occurs. DMA is implemented with a specialized controller that transfers data between an I/O device and memory independent of the processor. The DMA controller direct memory access (DMA) A mechanism that provides a device controller with the ability to transfer data directly to or from the memory without involving the processor. | clipped_hennesy_Page_590_Chunk5947 |
becomes the master and directs the reads or writes between itself and memory. There are three steps in a DMA transfer: 1. The processor sets up the DMA by supplying the identity of the device, the operation to perform on the device, the memory address that is the source or destination of the data to be transferred, and the number of bytes to transfer. 2. The DMA starts the operation on the device and arbitrates for the interconnect. When the data is available (from the device or memory), it transfers the data. The DMA device supplies the memory address for the read or the write. If the request requires more than one transfer, the DMA unit generates the next memory address and initiates the next transfer. Using this mechanism, a DMA unit can complete an entire transfer, which may be thousands of bytes in length, without bothering the processor. Many DMA controllers contain some memory to allow them to deal flexibly either with delays in transfer or with those incurred while waiting to become the master. 3. Once the DMA transfer is complete, the controller interrupts the processor, which can then determine by interrogating the DMA device or examining memory whether the entire operation completed successfully. There may be multiple DMA devices in a computer system. For example, in a system with a single processor-memory bus and multiple I/O buses, each I/O bus controller will often contain a DMA processor that handles any transfers between a device on the I/O bus and the memory. Unlike either polling or interrupt-driven I/O, DMA can be used to interface a hard disk without consuming all the processor cycles for a single I/O. Of course, if the processor is also contending for memory, it will be delayed when the memory is busy doing a DMA transfer. By using caches, the processor can avoid having to access memory most of the time, thereby leaving most of the memory bandwidth free for use by I/O devices. Elaboration: To further reduce the need to interrupt the processor and occupy it in handling an I/O request that may involve doing several actual operations, the I/O con troller can be made more intelligent. Intelligent controllers are often called I/O proces sors (as well as I/O controllers or channel controllers). These specialized processors basically execute a series of I/O operations, called an I/O program. The program may be stored in the I/O processor, or it may be stored in memory and fetched by the I/O processor. When using an I/O processor, the operating system typically sets up an I/O program that indicates the I/O operations to be done as well as the size and transfer address for any reads or writes. The I/O processor then takes the operations from the I/O program and interrupts the processor only when the entire program is completed. DMA processors are essentially special-purpose processors (usually single-chip and nonprogrammable), while I/O processors are often implemented with general-purpose microprocessors, which run a specialized I/O program. master A unit on the I/O interconnect that can initiate transfer requests. 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System 593 | clipped_hennesy_Page_591_Chunk5948 |
594 Chapter 6 Storage and Other I/O Topics Direct Memory Access and the Memory System When DMA is incorporated into an I/O system, the relationship between the memory system and processor changes. Without DMA, all accesses to the memory system come from the processor and thus proceed through address translation and cache access as if the processor generated the references. With DMA, there is another path to the memory system—one that does not go through the address translation mechanism or the cache hierarchy. This difference generates some problems in both virtual memory systems and systems with caches. These problems are usually solved with a combination of hardware techniques and software support. The difficulties in having DMA in a virtual memory system arise because pages have both a physical and a virtual address. DMA also creates problems for systems with caches, because there can be two copies of a data item: one in the cache and one in memory. Because the DMA processor issues memory requests directly to the memory rather than through the processor cache, the value of a memory location seen by the DMA unit and the processor may differ. Consider a read from disk that the DMA unit places directly into memory. If some of the locations into which the DMA writes are in the cache, the processor will receive the old value when it does a read. Similarly, if the cache is write-back, the DMA may read a value directly from memory when a newer value is in the cache, and the value has not been written back. This is called the stale data problem or coherence problem (see Chapter 5). We have looked at three different methods for transferring data between an I/O device and memory. In moving from polling to an interrupt-driven to a DMA interface, we shift the burden for managing an I/O operation from the processor to a progressively more intelligent I/O controller. These methods have the advantage of freeing up processor cycles. Their disadvantage is that they increase the cost of the I/O system. Because of this, a given computer system can choose which point along this spectrum is appropriate for the I/O devices connected to it. Before discussing the design of I/O systems, let’s look briefly at performance measures of them in the next section. In ranking the three ways of doing I/O, which statements are true? 1. If we want the lowest latency for an I/O operation to a single I/O device, the order is polling, DMA, and interrupt driven. 2. In terms of lowest impact on processor utilization from a single I/O device, the order is DMA, interrupt driven, and polling. Check Yourself | clipped_hennesy_Page_592_Chunk5949 |
In a system with virtual memory, should DMA work with virtual addresses or physical addresses? The obvious problem with virtual addresses is that the DMA unit will need to translate the virtual addresses to physical addresses. The major problem with the use of a physical address in a DMA transfer is that the transfer cannot easily cross a page boundary. If an I/O request crossed a page boundary, then the memory locations to which it was being transferred would not necessarily be contiguous in the virtual memory. Consequently, if we use physical addresses, we must constrain all DMA transfers to stay within one page. One method to allow the system to initiate DMA transfers that cross page boundaries is to make the DMA work on virtual addresses. In such a system, the DMA unit has a small number of map entries that provide virtual-to-physical mapping for a transfer. The operating system provides the mapping when the I/O is initiated. By using this mapping, the DMA unit need not worry about the loca tion of the virtual pages involved in the transfer. Another technique is for the operating system to break the DMA transfer into a series of transfers, each confined within a single physical page. The transfers are then chained together and handed to an I/O processor or intelligent DMA unit that executes the entire sequence of transfers; alternatively, the operating system can individually request the transfers. Whichever method is used, the operating system must still cooperate by not remapping pages while a DMA transfer involving that page is in progress. The coherency problem for I/O data is avoided by using one of three major tech niques. One approach is to route the I/O activity through the cache. This ensures that reads see the latest value while writes update any data in the cache. Routing all I/O through the cache is expensive and potentially has a large negative perfor mance impact on the processor, since the I/O data is rarely used immediately and may displace useful data that a running program needs. A second choice is to have the OS selectively invalidate the cache for an I/O read or force write-backs to occur for an I/O write (often called cache flushing). This approach requires some small amount of hardware support and is probably more efficient if the software can perform the function easily and efficiently. Because this flushing of large parts of the cache need only happen on DMA block accesses, it will be relatively infrequent. The third approach is to provide a hardware mechanism for selectively flushing (or invalidating) cache entries. Hardware invalidation to ensure cache coherence is typical in multiprocessor systems, and the same technique can be used for I/O; Chapter 5 discusses this topic in detail. Hardware/ Software Interface Hardware/ Software Interface 6.6 Interfacing I/O Devices to the Processor, Memory, and Operating System 595 | clipped_hennesy_Page_593_Chunk5950 |
596 Chapter 6 Storage and Other I/O Topics 6.7 I/O Performance Measures: Examples from Disk and File Systems How should we compare I/O systems? This is a complex question, because I/O performance depends on many aspects of the system, and different applications stress different aspects of the I/O system. Furthermore, a design can make com plex tradeoffs between response time and throughput, making it impossible to measure just one aspect in isolation. For example, handling a request as early as possible generally minimizes response time, although greater throughput can be achieved if we try to handle related requests together. Accordingly, we may increase throughput on a disk by grouping requests that access locations that are close together. Such a policy will increase the response time for some requests, probably leading to a larger variation in response time. Although throughput will be higher, some benchmarks constrain the maximum response time to any request, making such optimizations potentially problematic. In this section, we give some examples of measurements proposed for deter mining the performance of storage systems. These benchmarks are affected by a variety of system features, including the disk technology, the way disks are con nected, the memory system, the processor, and the file system provided by the operating system. Before we discuss these benchmarks, we need to address a confusing point about terminology and units. The performance of I/O systems depends on the rate at which the system transfers data. The transfer rate depends on the clock rate, which is typically given in GHz = 109 cycles per second. The transfer rate is usually quoted in GB/sec. In I/O systems, GBs are measured using base 10 (i.e., 1 GB = 109 = 1,000,000,000 bytes), unlike main memory where base 2 is used (i.e., 1 GB = 230 = 1,073,741,824 bytes). In addition to adding confusion, this difference introduces the need to convert between base 10 (1K = 1000) and base 2 (1K = 1024), because many I/O accesses are for data blocks that have a size that is a power of 2. Rather than complicate all our examples by accurately converting one of the two measurements, we make note here of this distinction and the fact that treating the two measures as if the units were identical introduces a small error. We illus trate this error in Section 6.12. Transaction Processing I/O Benchmarks Transaction processing (TP) applications involve both a response time require ment and a performance measurement based on throughput. Furthermore, most of the I/O accesses are small. Because of this, TP applications are chiefly concerned with I/O rate, measured as the number of accesses per second, as opposed to data rate, measured as bytes of data per second. TP applications generally involve changes to a large database, with the system meeting some response time requirements transaction processing A type of application that involves handling small short operations (called transactions) that typically require both I/O and computation. Transaction processing applications typically have both response time requirements and a perfor mance measurement based on the throughput of transactions. I/O rate Performance measure of I/Os per unit time, such as reads per second. data rate Performance measure of bytes per unit time, such as GB/second. | clipped_hennesy_Page_594_Chunk5951 |
as well as gracefully handling certain types of failures. These applications are extremely critical and cost-sensitive. For example, banks normally use TP systems because they are concerned about a range of characteristics. These include making sure transactions aren’t lost, handling transactions quickly, and minimizing the cost of processing each transaction. Although dependability in the face of failure is an absolute requirement in such systems, both response time and throughput are critical to building cost-effective systems. A number of transaction processing benchmarks have been developed. The best-known set of benchmarks is a series developed by the Transaction Processing Council (TPC). TPC-C, initially created in 1992, simulates a complex query environment. TPC-H models ad hoc decision support—the queries are unrelated, and knowledge of past queries cannot be used to optimize future queries; the result is that query execution times can be very long. TPC-W is a Web-based transaction benchmark that simulates the activities of a business-oriented transactional Web server. It exercises the database system as well as the underlying Web server software. TPC-App is an application server and Web services benchmark. The most recent is TPC-E, which simulates the transaction processing workload of a brokerage firm. The TPC benchmarks are described at www.tpc.org. All the TPC benchmarks measure performance in transactions per second. In addition, they include a response time requirement, so that throughput perfor mance is measured only when the response time limit is met. To model real-world systems, higher transaction rates are also associated with larger systems, both in terms of users and the size of the database to which the transactions are applied. Hence, storage capacity must scale with performance. Finally, the system cost for a benchmark system must also be included, allowing accurate comparisons of cost/ performance. File System and Web I/O Benchmarks In addition to processor benchmarks, SPEC offers both a file server benchmark (SPECSFS) and a Web server benchmark (SPECWeb). SPECSFS is a benchmark for measuring NFS (Network File System) performance using a script of file server requests; it tests the performance of the I/O system, including both disk and net work I/O, as well as the processor. SPECSFS is a throughput-oriented benchmark but with important response time requirements. SPECWeb is a Web server bench mark that simulates multiple clients requesting both static and dynamic pages from a server, as well as clients posting data to the server (see Chapter 1). The most recent SPEC effort is to measure power. SPECPower measures power and performance characteristics of small servers. Sun recently announced filebench, a file system benchmark framework. Instead of a standard workload, it provides a language that lets you describe the workload you’d like to run on your file systems. However, there are examples of file workloads that are supposed to emulate common applications of file systems. 6.7 I/O Performance Measures: Examples from Disk and File Systems 597 | clipped_hennesy_Page_595_Chunk5952 |
598 Chapter 6 Storage and Other I/O Topics Are the following true or false? Unlike processor benchmarks, I/O benchmarks 1. concentrate on throughput rather than latency 2. can require that the data set scale in size or number of users to achieve per formance milestones 3. often report cost performance 6.8 Designing an I/O System There are two primary types of specifications that designers encounter in I/O sys tems: latency constraints and bandwidth constraints. In both cases, knowledge of the traffic pattern affects the design and analysis. Latency constraints involve ensuring that the latency to complete an I/O opera tion is bounded by a certain amount. In the simple case, the system may be unloaded, and the designer must ensure that some latency bound is met either because it is critical to the application or because the device must receive certain guaranteed service to prevent errors. Likewise, determining the latency on an unloaded system is relatively easy, since it involves tracing the path of the I/O operation and summing the individual latencies. Finding the average latency (or distribution of latency) under a load is much harder. Such problems are tackled either by queuing theory (when the behavior of the workload requests and I/O service times can be approximated by simple distributions) or by simulation (when the behavior of I/O events is complex). Both topics are beyond the limits of this text. Designing an I/O system to meet a set of bandwidth constraints given a work load is the other typical problem designers face. Alternatively, the designer may be given a partially configured I/O system and be asked to balance the system to main tain the maximum bandwidth achievable, as dictated by the preconfigured portion of the system. This latter design problem is a simplified version of the first. The general approach to designing such a system is as follows: 1. Find the weakest link in the I/O system, which is the component in the I/O path that will constrain the design. Depending on the workload, this com ponent can be anywhere, including the processors, the memory system, the I/O controllers, or the devices. Both the workload and configuration limits may dictate where the weakest link is located. 2. Configure this component to sustain the required bandwidth. 3. Determine the requirements for the rest of the system and configure them to support this bandwidth. Check Yourself | clipped_hennesy_Page_596_Chunk5953 |
The easiest way to understand this methodology is with an example. We’ll do a simple analysis of the I/O system of the Sun Fire x4150 server in Section 6.10 to show how this methodology works. 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks Amdahl’s law in Chapter 1 reminds us that neglecting I/O in this parallel revolu tion is foolhardy. A simple example demonstrates this. Impact of I/O on System Performance Suppose we have a benchmark that executes in 100 seconds of elapsed time, of which 90 seconds is CPU time and the rest is I/O time. Suppose the number of processors doubles every two years, but the processors remain the same speed, and I/O time doesn’t improve. How much faster will our program run at the end of six years? We know that Elapsed time = CPU time + I/O time 100 = 90 + I/O time I/O time = 10 seconds The new CPU times and the resulting elapsed times are computed in the fol lowing table. EXAMPLE ANSWER After n years CPU time I/O time Elapsed time % I/O time 0 years 90 seconds 10 seconds 100 seconds 10% 2 years 90 2 = 45 seconds 10 seconds 55 seconds 18% 4 years 45 2 = 23 seconds 10 seconds 33 seconds 31% 6 years 23 2 = 11 seconds 10 seconds 21 seconds 47% 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 599 | clipped_hennesy_Page_597_Chunk5954 |
600 Chapter 6 Storage and Other I/O Topics The improvement in CPU performance after six years is 90 11 = 8 However, the improvement in elapsed time is only 100 21 = 4.7 and the I/O time has increased from 10% to 47% of the elapsed time. Hence, the parallel revolution needs to come to I/O as well as to computation, or the effort spent in parallelizing could be squandered whenever programs do I/O, which they all must do. Accelerating I/O performance was the original motivation of disk arrays (see Section 6.14 on the CD). In the late 1980s, the high performance storage of choice was large, expensive disks, such as the larger ones in Figure 6.4. The argument was that by replacing a few large disks with many small disks, performance would improve because there would be more read heads. This shift is a good match for multiple processors as well, since many read/write heads mean the storage system could support many more independent accesses as well as large transfers spread across many disks. That is, you could get both high I/Os per second and high data transfer rates. In addition to higher performance, there could be advantages in cost, power, and floor space, since smaller disks are generally more efficient per gigabyte than larger disks. The flaw in the argument was that disk arrays could make reliability much worse. These smaller, inexpensive drives had lower MTTF ratings than the large drives, but more importantly, by replacing a single drive with, say, 50 small drives, the failure rate would go up by at least a factor of 50! The solution was to add redundancy so that the system could cope with disk failures without losing information. By having many small disks, the cost of extra redundancy to improve dependability is small, relative to the solutions for a few large disks. Thus, dependability was more affordable if you constructed a redundant array of inexpensive disks. This observation led to its name: redundant arrays of inexpensive disks, abbreviated RAID. In retrospect, although its invention was motivated by performance, depen dability was the key reason for the widespread popularity of RAID. The parallel revolution has resurfaced the original performance side of the argument for RAID. The rest of this section surveys the options for dependability and their impacts on cost and performance. How much redundancy do you need? Do you need extra information to find the faults? Does it matter how you organize the data and the extra check information on these disks? The paper that coined the term gave an evolutionary answer to these questions, starting with the simplest but most expensive solution. redundant arrays of inexpensive disks (RAID) An organization of disks that uses an array of small and inexpensive disks so as to increase both performance and reliability. | clipped_hennesy_Page_598_Chunk5955 |
Figure 6.12 shows the evolution and example cost in number of extra check disks. To keep track of the evolution, the authors numbered the stages of RAID, and they are still used today. No Redundancy (RAID 0) Simply spreading data over multiple disks, called striping, automatically forces accesses to several disks. Striping across a set of disks makes the collection appear to software as a single large disk, which simplifies storage management. It also improves performance for large accesses, since many disks can operate at once. Video-editing systems, for example, often stripe their data and may not worry about dependability as much as, say, databases. RAID 0 is something of a misnomer, as there is no redundancy. However, RAID levels are often left to the operator to set when creating a storage system, and RAID 0 is often listed as one of the options. Hence, the term RAID 0 has become widely used. striping Allocation of logically sequential blocks to separate disks to allow higher performance than a single disk can deliver. FIGURE 6.12 RAID for an example of four data disks showing extra check disks per RAID level and companies that use each level. Figures 6.13 and 6.14 explain the difference between RAID 3, RAID 4, and RAID 5. RAID 0 (No redundancy) Widely used Data disks RAID 1 (Mirroring) EMC, HP(Tandem), IBM RAID 2 (Error detection and correction code) Unused RAID 3 (Bit-interleaved parity) Storage concepts RAID 4 (Block-interleaving parity) Network appliance RAID 5 (Distributed block- interleaved parity) Widely used RAID 6 (P + Q redundancy) Recently popular Redundant check disks 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 601 | clipped_hennesy_Page_599_Chunk5956 |
602 Chapter 6 Storage and Other I/O Topics Mirroring (RAID 1) This traditional scheme for tolerating disk failure, called mirroring or shadowing, uses twice as many disks as does RAID 0. Whenever data is written to one disk, that data is also written to a redundant disk, so that there are always two copies of the information. If a disk fails, the system just goes to the “mirror” and reads its contents to get the desired information. Mirroring is the most expensive RAID solution, since it requires the most disks. Error Detecting and Correcting Code (RAID 2) RAID 2 borrows an error detection and correction scheme most often used for memories (see Appendix C). Since RAID 2 has fallen into disuse, we’ll not describe it here. Bit-Interleaved Parity (RAID 3) The cost of higher availability can be reduced to 1/n, where n is the number of disks in a protection group. Rather than have a complete copy of the original data for each disk, we need only add enough redundant information to restore the lost information on a failure. Reads or writes go to all disks in the group, with one extra disk to hold the check information in case there is a failure. RAID 3 is popular in applications with large data sets, such as multimedia and some scientific codes. Parity is one such scheme. Readers unfamiliar with parity can think of the redundant disk as having the sum of all the data in the other disks. When a disk fails, then you subtract all the data in the good disks from the parity disk; the remaining information must be the missing information. Parity is simply the sum modulo two. Unlike RAID 1, many disks must be read to determine the missing data. The assumption behind this technique is that taking longer to recover from failure but spending less on redundant storage is a good tradeoff. Block-Interleaved Parity (RAID 4) RAID 4 uses the same ratio of data disks and check disks as RAID 3, but they access data differently. The parity is stored as blocks and associated with a set of data blocks. In RAID 3, every access went to all disks. However, some applications prefer smaller accesses, allowing independent accesses to occur in parallel. That is the purpose of the RAID levels 4 to 6. Since error detection information in each sector is checked on reads to see if the data is correct, such “small reads” to each disk can occur independently as long as the minimum access is one sector. In the RAID context, a small access goes to just one disk in a protection group while a large access goes to all the disks in a protection group. Writes are another matter. It would seem that each small write would demand that all other disks be accessed to read the rest of the information needed to mirroring Writing the identical data to multiple disks to increase data availability. protection group The group of data disks or blocks that share a common check disk or block. | clipped_hennesy_Page_600_Chunk5957 |
recalculate the new parity, as in the left in Figure 6.13. A “small write” would require reading the old data and old parity, adding the new information, and then writing the new parity to the parity disk and the new data to the data disk. The key insight to reduce this overhead is that parity is simply a sum of infor mation; by watching which bits change when we write the new information, we need only change the corresponding bits on the parity disk. The right of Figure 6.13 shows the shortcut. We must read the old data from the disk being written, compare old data to the new data to see which bits change, read the old parity, change the corresponding bits, then write the new data and new parity. Thus, the small write involves four disk accesses to two disks instead of accessing all disks. This organization is RAID 4. Distributed Block-Interleaved Parity (RAID 5) RAID 4 efficiently supports a mixture of large reads, large writes, and small reads, plus it allows small writes. One drawback to the system is that the parity disk must be updated on every write, so the parity disk is the bottleneck for back-to-back writes. To fix the parity-write bottleneck, the parity information can be spread through out all the disks so that there is no single bottleneck for writes. The distributed parity organization is RAID 5. FIGURE 6.13 Small write update on RAID 4. This optimization for small writes reduces the number of disk accesses as well as the number of disks occupied. This figure assumes we have four blocks of data and one block of parity. The naive RAID 4 parity calculation in the left of the figure reads blocks D1, D2, and D3 before adding block D0¢ to calculate the new parity P¢. (In case you were wondering, the new data D0¢ comes directly from the CPU, so disks are not involved in reading it.) The RAID 4 shortcut on the right reads the old value D0 and compares it to the new value D0¢ to see which bits will change. You then read the old parity P and then change the corresponding bits to form P¢. The logical function exclusive OR does exactly what we want. This example replaces three disk reads (D1, D2, D3) and two disk writes (D0¢, P¢) involving all the disks for two disk reads (D0, P) and two disk writes (D0¢, P¢), which involve just two disks. Increasing the size of the parity group increases the savings of the shortcut. RAID 5 uses the same shortcut. D0′ D0 D1 D2 D3 P D0′ D1 D2 D3 P′ New Data 1. Read 2. Read 3. Read 4. Write 5. Write XOR D0′ D0 D1 D2 D3 P D0′ D1 D2 D3 P′ + New Data1. Read 2. Read 3. Write 4. Write XOR + XOR + 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 603 | clipped_hennesy_Page_601_Chunk5958 |
604 Chapter 6 Storage and Other I/O Topics Figure 6.14 shows how data is distributed in RAID 4 versus RAID 5. As the organization on the right shows, in RAID 5 the parity associated with each row of data blocks is no longer restricted to a single disk. This organization allows multiple writes to occur simultaneously as long as the parity blocks are not located on the same disk. For example, a write to block 8 on the right must also access its parity block P2, thereby occupying the first and third disks. A second write to block 5 on the right, implying an update to its parity block P1, accesses the second and fourth disks and thus could occur concurrently with the write to block 8. Those same writes to the organization on the left result in changes to blocks P1 and P2, both on the fifth disk, which is a bottleneck. P + Q Redundancy (RAID 6) Parity-based schemes protect against a single self-identifying failure. When a single failure correction is not sufficient, parity can be generalized to have a second calcu lation over the data and another check disk of information. This second check block allows recovery from a second failure. Thus, the storage overhead is twice that of RAID 5. The small write shortcut of Figure 6.13 works as well, except now there are six disk accesses instead of four to update both P and Q information. RAID Summary RAID 1 and RAID 5 are widely used in servers; one estimate is that 80% of disks in servers are found in a RAID organization. One weakness of the RAID systems is repair. First, to avoid making the data unavailable during repair, the array must be designed to allow the failed disks to be FIGURE 6.14 Block-interleaved parity (RAID 4) versus distributed block-interleaved parity (RAID 5). By distributing parity blocks to all disks, some small writes can be performed in parallel. 0 4 8 12 16 20 . . . 1 5 9 13 17 21 . . . 2 6 10 14 18 22 . . . 3 7 11 15 19 23 . . . P0 P1 P2 P3 P4 P5 . . . 0 4 8 12 P4 20 . . . 1 5 9 P3 16 21 . . . 2 6 P2 13 17 22 . . . 3 P1 10 14 18 23 . . . P0 7 11 15 19 P5 . . . RAID 4 RAID 5 | clipped_hennesy_Page_602_Chunk5959 |
replaced without having to turn off the system. RAIDs have enough redundancy to allow continuous operation, but hot-swapping disks place demands on the physical and electrical design of the array and the disk interfaces. Second, another failure could occur during repair, so the repair time affects the chances of losing data: the longer the repair time, the greater the chances of another failure that will lose data. Rather than having to wait for the operator to bring in a good disk, some systems include standby spares so that the data can be reconstructed immediately upon discovery of the failure. The operator can then replace the failed disks in a more leisurely fashion. Note that a human operator ultimately determines which disks to remove. As Figure 6.3 shows, operators are only human, so they occasionally remove the good disk instead of the broken disk, leading to an unrecoverable disk failure. In addition to designing the RAID system for repair, there are questions about how disk technology changes over time. Although disk manufacturers quote very high MTTF for their products, those numbers are under nominal conditions. If a particular disk array has been subject to temperature cycles due to, say, the failure of the air conditioning system, or to shaking due to a poor rack design, construc tion, or installation, the failure rates can be three to six times higher (see the fallacy on page 613). The calculation of RAID reliability assumes independence between disk failures, but disk failures could be correlated, because such damage due to the environment would likely happen to all the disks in the array. Another concern is that since disk bandwidth is growing more slowly than disk capacity, the time to repair a disk in a RAID system is increasing, which in turn increases the chances of a second failure. For example, a 1000 GB SATA disk could take almost three hours to read sequentially, assuming no interference. Given that the damaged RAID is likely to continue to serve data, reconstruction could be stretched considerably. Besides increasing that time, another concern is that reading much more data during reconstruction means increasing the chance of an uncorrectable read media failure, which would result in data loss. Other arguments for concern about simultaneous multiple failures are the increasing number of disks in arrays and the use of SATA disks, which are slower and have higher capacity than traditional enterprise disks. Hence, these trends have led to a growing interest in protecting against more than one failure, and so RAID 6 is increasingly being offered as an option and being used in the field. Which of the following are true about RAID levels 1, 3, 4, 5, and 6? 1. RAID systems rely on redundancy to achieve high availability. 2. RAID 1 (mirroring) has the highest check disk overhead. 3. For small writes, RAID 3 (bit-interleaved parity) has the worst throughput. 4. For large writes, RAID 3, 4, and 5 have the same throughput. hot-swapping Replacing a hardware component while the system is running. standby spares Reserve hardware resources that can immediately take the place of a failed component. Check Yourself 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 605 | clipped_hennesy_Page_603_Chunk5960 |
606 Chapter 6 Storage and Other I/O Topics Elaboration: One issue is how mirroring interacts with striping. Suppose you had, say, four disks’ worth of data to store and eight physical disks to use. Would you create four pairs of disks—each organized as RAID 1—and then stripe data across the four RAID 1 pairs? Alternatively, would you create two sets of four disks—each organized as RAID 0—and then mirror writes to both RAID 0 sets? The RAID terminology has evolved to call the former RAID 1 + 0 or RAID 10 (“striped mirrors”) and the latter RAID 0 + 1 or RAID 01 (“mirrored stripes”). 6.10 Real Stuff: Sun Fire x4150 Server In addition to the revolution in how microprocessors are constructed, we are see ing a revolution in how software is delivered. Instead of the traditional model of software sold on a CD or shipped over the Internet to be installed in your com puter, the alternative is software as a service. That is, you go over the Internet to do your work on a computer that runs the software you want to use to provide the service that you desire. The most popular example is likely Web searching, but there are services for photo editing and storage, document processing, database storage, virtual worlds, and so on. If you looked hard, you can probably find service version of almost every program you use on your desktop computer. This shift has led to the construction of large data centers to hold the comput ers and disks to run the services used by millions of external users. What should computers look like if they are designed to be placed in these large data centers? They certainly all don’t need displays and keyboards. Clearly, space efficiency and power efficiency will be important if you have 10,000 of them in a datacenter, in addition to the traditional concerns of cost and performance. The related question is what should storage look like in a datacenter? While there are many options, one popular version is to include disks with the processor and memory, and make this whole unit the building block. To overcome concerns about reliability, the application itself makes redundant copies and is responsible for keeping them consistent and recovering from failures. The IT industry has largely agreed to some standards in the physical design of computers for the datacenter, specifically the rack used to hold the computers in the datacenter. The most popular is the 19-inch rack, which is 19 inches wide (482.6 mm). Computers designed for the rack are labeled, naturally enough, rack mount, but are also called a subrack or simply a shelf. Because the traditional placement of holes in which to attach the shelves is 1.75 inches (44.45 mm) apart, this distance is commonly called a rack unit or simply unit (U). The most popular 19-inch rack is 42 U high, which is 42 x 1.75 or 73.5 inches high. The depth of the shelf varies. | clipped_hennesy_Page_604_Chunk5961 |
FIGURE 6.15 A standard 19-inch rack populated with 42 1U servers. This rack has 42 1U “pizza box” servers. Source: http://gchelpdesk.ualberta.ca/news/07mar06/cbhd_news_07mar06.php. Hence, the smallest rack mount computer is 19 inches wide and 1.75 inches tall, often called 1U computers or 1U servers. Because of their dimensions, they have earned the nickname pizza boxes. Figure 6.15 shows an example of a standard rack populated with 42 1U servers. 6.10 Real Stuff: Sun Fire x4150 Server 607 | clipped_hennesy_Page_605_Chunk5962 |
608 Chapter 6 Storage and Other I/O Topics Figure 6.16 shows the Sun Fire x4150, an example of a 1U server. Maximally configured, this 1U box contains: ■ ■8 2.66 GHz processors, spread across two sockets (2 Intel Xeon 5345) ■ ■64 GB of DDR2-667 DRAM, spread across 16 4GB FBDIMMs ■ ■8 15,000 RPM 73 GB SAS 2.5-inch disk drives ■ ■1 RAID controller (Supporting RAID 0, RAID 1, RAID 5, and RAID 6) ■ ■4 10/100/1000 Ethernet ports ■ ■3 PCI Express x8 ports ■ ■4 external and 1 internal USB 2.0 ports 3 PCI Express Slots System Status LEDs Video 4 Gigabit NICs 2 USB Ports Management Serial Management NIC 2 Redundant Power Supplies FIGURE 6.16 The front and rear of the Sun Fire x4150 1U server. The dimensions are 1.75 inches high by 19 inches wide. The eight 2.5-inch disks drives can be replaced from the front. In the upper right is a DVD and two USB ports. The picture below labels the items at the rear of the server. It has redundant power supplies and fans to allow the server to continue operating despite failures of one of these components. | clipped_hennesy_Page_606_Chunk5963 |
Figure 6.17 shows the connectivity and bandwidths of the chips on the mother board. Figures 6.9 and 6.10 describe the I/O chip set for the Intel 5345, and Figure 6.5 describes the SAS disks in the Sun Fire x4150. To clarify the advice on designing an I/O system in Section 6.8, let’s perform a simple performance evaluation to see where the bottlenecks might be for a hypothetical application. I/O System Design Make the following assumptions about the Sun Fire x4150: ■ ■The user program uses 200,000 instructions per I/O operation ■ ■The operating system averages 100,000 instructions per I/O operation EXAMPLE A2 A3 A1 A0 B2 B3 B1 B0 D1 D0 D2 D3 C1 C0 C2 C3 Intel Xeon 5100/5300 Intel Xeon 5100/5300 FSB 1333 MT/s FSB 1333 MT/s 10.5 GB/s 10.5 GB/s Dual FSB to MCH XEON TM Channel A 5.3 GB/s Channel B 5.3 GB/s Channel C 5.3 GB/s Channel D 5.3 GB/s PCIe x16 - 2 PCIe x16 - 1 PCIe x16 - 0 PCIe x8 PCIe x8 PCIe x8 8x SAS HDDs MCH Blackford 5000P 2x USB PCI 32-bit 33 MHz PCIe x4 2x Rear USB 2.0 1x Internal USB 2.0 CD/DVD 2x Front USB 2.0 2x 1GB Ethernet 2 & 3 2x 1GB Ethernet 0 & 1 Serial RJ-45 Management 10/100 Ethernet VGA Video USB to IDE USB Hub IOH ESB-2 USB IDE PCIe ESI (PCIe) PCI-E SAS/RAID Controller DIMMs DIMMs DIMMs DIMMs XEON TM AST2000 Q62611.1 GP 0608 TAN A2 FIGURE 6.17 Logical connections and bandwidths of components in the Sun Fire x4150. The three PCIe connectors allow x16 boards to be plugged in, but it only provides eight lanes of bandwidth to the MCH. Source: Figure 5 of “SUN FIRE™ X4150 AND X4450. SERVER ARCHITECTURE” (see www.sun.com/servers/x64/x4150/). 6.10 Real Stuff: Sun Fire x4150 Server 609 | clipped_hennesy_Page_607_Chunk5964 |
610 Chapter 6 Storage and Other I/O Topics ■ ■The workload consists of 64 KB reads ■ ■Each processor sustains 1 billion instructions per second Find the maximum sustainable I/O rate for a fully loaded Sun Fire x4150 for random reads and sequential reads. Assume that the reads can always be done on an idle disk if one exists (i.e., ignore disk conflicts) and that the RAID controller is not the bottleneck. Let’s first find the I/O rate of a single processor. Each I/O takes 200,000 user instructions and 100,000 OS instructions, so Maximum I/O rate of 1 processor = Instruction execution rate Instructions per I/O = 1 ´ 109 (200 + 100) ´ 103 = 3,333 I/Os second As a single Intel 5345 socket has four processors, it can perform 13,333 IOPS. Two sockets with eight processors can perform 26,667 IOPS. Let’s determine IOPS per disks for random and sequential reads for the 2.5-inch SAS disk described in Figure 6.5. Rather than use the average seek time from the disk manufacturer, let’s assume that it is only a quarter of that time, as is often the case (see Section 6.3). The time per random read of a single disk: Time per I/O at disk = Seek + rotational time + Transfer time = 2.9 4 ms + 2.0 ms + 64 KB 112 MB/sec = 3.3 ms Thus, each disk can complete 1000 ms/3.3 ms or 303 I/Os per second, and eight disks perform 2424 random reads per second. For sequential reads, it’s just the transfer size divided by the disk bandwidth: 112 MB/sec 64 KB = 1750 IOPS Eight disks can perform 14,000 sequential 64 KB reads. We need to see if the paths from the disks to memory and the processors are a bottleneck. Let’s start with the PCI Express interconnect from the RAID card to the north bridge chip. Each lane of a PCIe is 250 MB/second, so eight lanes can perform 2 GB/second. Max I/O rate of PCIe x8 = PCI bandwidth Bytes per I/O = 2 ´ 109 64 ´ 103 = 31,250 I/Os second Even eight disks transferring sequentially use less than half the PCIe x8 link. ANSWER | clipped_hennesy_Page_608_Chunk5965 |
Once the data gets to the MCB, it needs to be written into the DRAM. The bandwidth of a DDR2 667 MHz FBDIMM is 5336 MB/second. A single DIMM can perform 5336 MB/sec 64 KB = 83,375 IOPS The memory is not a bottleneck even with one DIMM, and we have 16 in a fully configured Sun Fire x4150. The final link in the chain is the Front Side Bus that connects north bridge hub to the Intel 5345 socket. Its peak bandwidth is 10.6 GB/sec, but Section 7.10 suggests you get no more than half peak. Each I/O transfers 64 KB, so Max I/O rate of FSB = Bus bandwidth Bytes per I/O = 5.3 ´ 109 64 ´ 103 = 81,540 I/Os second There is one Front Side Bus per socket, so the dual FSB peak is over 150,000 IOPS, and once again, the FSB is not a bottleneck. Hence, a fully configured Sun Fire x4150 can sustain the peak bandwidth of the eight disks, which is 2424 random reads per second or 14,000 sequential reads per second. Notice the significant number of simplifying assumptions that are needed to do this example. In practice, many of these simplifications might not hold for critical I/O-intensive applications. For this reason, running a realistic workload or relevant benchmark is often the only plausible way to evaluate I/O performance. As mention at the beginning of this section, these new datacenters are concerned about power and space as well as cost and performance. Figure 6.18 shows the idle and peak power required by a fully configured Sun Fire x4150, with a breakdown by each component. Let’s look at the alternative configurations of the Sun Fire x4150 to conserve power. I/O System Power Evaluation Reconfigure a Sun Fire x4150 to minimize power, assuming that the workload in the example above is the only activity on this 1U server. To achieve the 2424 random 64 KB reads per second from the prior example, we need all eight disks and the PCI RAID controller. From the calculations above, a single DIMM can support over 80,000 IOPS, so we can save power in memory. The Sun Fire x4150 minimum memory is two DIMMs, so we can EXAMPLE ANSWER 6.10 Real Stuff: Sun Fire x4150 Server 611 | clipped_hennesy_Page_609_Chunk5966 |
612 Chapter 6 Storage and Other I/O Topics save the power (and cost) of 14 4GB DIMMs. A single socket can support 13,333 IOPS, so we can also reduce the number of Intel E5345 sockets by one. Using the numbers in Figure 6.18, the total system power is now: Idle Powerrandom reads = 154 + 2 ´ 10 + 8 ´ 8 + 15 = 253 watts Peak Powerrandom reads = 215 + 2 ´ 11 + 8 ´ 8 + 15 = 316 watts or a reduction in power by a factor of 1.6 to 1.7. The original system can performance 14,000 64 KB sequential reads per second. We still need all the disks and the disk controller, and the same number of DIMMs can handle this higher load. This workload exceeds a processing power of the single Intel E5345 socket, so we need to add a second one. Idle Powersequential reads = 154 + 22 + 2 ´ 10 + 8 ´ 8 + 15 = 275 watts Peak Powersequential reads = 215 + 79 + 2 ´ 11 + 8 ´ 8 + 15 = 395 watts or a reduction in power by a factor of 1.4 to 1.5. Advanced Topics: Networks Networks are growing in popularity over time, and unlike other I/O devices, there are many books and courses on them. For readers who have not taken courses or 6.11 FIGURE 6.18 Idle and peak power of a fully configured Sun Fire x4150. These experiments came while running SPECJBB with 29 different configurations, so the peak power could be different when running different applications (source: www.sun.com/servers/x64/ x4150/calc). Components System Item Idle Peak Number Idle Peak Single Intel 2.66 GHz E5345 socket, Intel 5000 MCB/IOH chip set, Ethernet controllers, power supplies, fans, . . . 154 W 215 W 1 154 W 37% 215 W 39% Additional Intel 2.66 GHz E5345 socket 22 W 79 W 1 22 W 5% 79 W 14% 4 GB DDR2-667 5300 FBDIMM 10 W 11 W 16 160 W 39% 176 W 32% 73 GB SAS 15K Disk drives 8 W 8 W 8 64 W 15% 64 W 12% PCIe x8 RAID Disk controller 15 W 15 W 1 15 W 4% 15 W 3% Total — — — 415 W 100% 549 W 100% | clipped_hennesy_Page_610_Chunk5967 |
read books on networking, Section 6.11 on the CD gives a quick overview of the topics and terminology, including Internetworking, the OSI model, protocol families such as TCP/IP, long-haul networks such as ATM, local area networks such as Ethernet, and wireless networks such as IEEE 802.11. 6.12 Fallacies and Pitfalls Fallacy: The rated mean time to failure of disks is 1,200,000 hours or almost 140 years, so disks practically never fail. Marketing practices of disk manufacturers have misled users. How is such an MTTF calculated? Early in the process, manufacturers will put thousands of disks in a room, run them for a few months, and count the number that fail. They com pute MTTF as the total number of hours that the disks were cumulatively available divided by the number that failed. One problem is that this number far exceeds the lifetime of a disk, which is commonly assumed to be five years or 43,800 hours. For this large MTTF to make some sense, disk manufacturers argue that the calculation corresponds to a user who buys a disk, and then keeps replacing the disk every five years—the planned lifetime of the disk. The claim is that if many customers (and their great- grandchildren) did this for the next century, on average they would replace a disk 27 times before a failure, or about 140 years. A more useful measure would be percentage of disks that fail in a year, called annual failure rate (AFR). Assume 1000 disks with a 1,200,000-hour MTTF and that the disks are used 24 hours a day. If you replaced failed disks with a new one having the same reliability characteristics, the number that would fail per year (8,760 hours) is Failed disks = 1000 drives ´ 8760 hours/drive 1,200,000 hours/failure = 7.3 Stated alternatively, the AFR is 0.73%. Disk manufacturers are starting to quote AFR as well as MTTB to give users better intuition about what to expect about their products. Fallacy: Disk failure rates in the field match their specifications. Two recent studies evaluated large collections of disks to check the relationship between results in the field compared to specifications. One study was of almost 100,000 ATA and SCSI disks that had quoted MTTF of 1,000,000 to 1,500,000 hours, or AFR of 0.6% to 0.8%. They found AFRs of 2% to 4% to be common, often three to five times higher than the specified rates [Schroeder and Gibson, 2007]. 6.12 Fallacies and Pitfalls 613 | clipped_hennesy_Page_611_Chunk5968 |
614 Chapter 6 Storage and Other I/O Topics A second study of more than 100,000 ATA disks, which had a quoted AFR of about 1.5%, saw failure rates of 1.7% for drives in their first year rise to 8.6% for drives in their third year, or about five to six times the specified rate [Pinheiro, Weber, and Barroso, 2007]. Fallacy: A GB/sec interconnect can transfer 1 GB of data in 1 second. First, you generally cannot use 100% of any computer resource. For a bus, you would be fortunate to get 70% to 80% of the peak bandwidth. Time to send the address, time to acknowledge the signals, and stalls while waiting to use a busy bus are among the reasons you cannot use 100% of a bus. Second, the definition of a gigabyte of storage and a gigabyte per second of bandwidth do not agree. As we discussed on page 596, I/O bandwidth measures are usually quoted in base 10 (i.e., 1 GB/sec = 109 bytes/sec), while 1 GB of data is typically a base 2 measure (i.e., 1 GB = 230 bytes). How significant is this distinc tion? If we could use 100% of the bus for data transfer, the time to transfer 1 GB of data on a 1 GB/sec interconnect is actually 230 109 = 1,073,741,824 1,000,000,000 = 1.073741824 » 1.07 seconds Pitfall: Trying to provide features only within the network versus end to end. The concern is providing at a lower-level features that can only be accomplished at the highest level, thus only partially satisfying the communication demand. Saltzer, Reed, and Clark [1984] give the end-to-end argument, as follows: The function in question can completely and correctly be specified only with the knowledge and help of the application standing at the endpoints of the commu nication system. Therefore, providing that questioned function as a feature of the communication system itself is not possible. Their example of the pitfall was a network at MIT that used several gateways, each of which added a checksum from one gateway to the next. The programmers of the application assumed the checksum guaranteed accuracy, incorrectly believ ing that the message was protected while stored in the memory of each gateway. One gateway developed a transient failure that swapped one pair of bytes per mil lion bytes transferred. Over time the source code of one operating system was repeatedly passed through the gateway, thereby corrupting the code. The only solution was to correct the infected source files by comparing to paper listings and repairing the code by hand! Had the checksums been calculated and checked by the application running on the end systems, safety would have been assured. There is a useful role for intermediate checks, however, provided that end-to-end checking is available. End-to-end checking may show that something is broken between | clipped_hennesy_Page_612_Chunk5969 |
two nodes, but it doesn’t point to where the problem is. Intermediate checks can discover which component is broken. You need both for repair. Pitfall: Moving functions from the CPU to the I/O processor, expecting to improve performance without a careful analysis. There are many examples of this pitfall trapping people, although I/O processors, when properly used, can certainly enhance performance. A frequent instance of this fallacy is the use of intelligent I/O interfaces, which, because of the higher overhead to set up an I/O request, can turn out to have worse latency than a processor-directed I/O activity (although if the processor is freed up sufficiently, system throughput may still increase). Frequently, performance falls when the I/O processor has much lower performance than the main processor. Consequently, a small amount of main processor time is replaced with a larger amount of I/O pro cessor time. Workstation designers have seen both these phenomena repeatedly. Myer and Sutherland [1968] wrote a classic paper on the tradeoff of complex ity and performance in I/O controllers. Borrowing the religious concept of the “wheel of reincarnation,” they eventually noticed they were caught in a loop of continuously increasing the power of an I/O processor until it needed its own simpler coprocessor: We approached the task by starting with a simple scheme and then adding commands and features that we felt would enhance the power of the machine. Gradually the [display] processor became more complex . . . . Finally the display processor came to resemble a full-fledged computer with some special graphics features. And then a strange thing happened. We felt compelled to add to the processor a second, subsidiary processor, which, itself, began to grow in complexity. It was then that we discovered the disturbing truth. Designing a display processor can become a never-ending cyclical process. In fact, we found the process so frustrating that we have come to call it the “wheel of reincarnation.” Pitfall: Using magnetic tapes to back up disks. This is both a fallacy and a pitfall. Magnetic tapes have been part of computer systems as long as disks because they use similar technology as disks, and hence historically have followed the same density improvements. The historic cost/ performance difference between disks and tapes is based on a sealed, rotating disk having lower access time than sequential tape access; but removable spools of magnetic tape mean many tapes can be used per reader, and they can be very long and so have high capacity. Hence, in the past a single magnetic tape could hold the contents of many disks, and since it was 10 to 100 times cheaper per gigabyte than disks, it was a useful backup medium. The claim was that magnetic tapes must track disks since innovations in disks must help tapes. This claim was important because tapes were a small market and could not afford a separate large research and development effort. One reason the market is small is that desktop owners generally do not back up disks onto tape, 6.12 Fallacies and Pitfalls 615 | clipped_hennesy_Page_613_Chunk5970 |
616 Chapter 6 Storage and Other I/O Topics and so while desktops are by far the largest market for disks, desktops are a small market for tapes. Alas, the larger market has led disks to improve much more quickly than tapes. Starting in 2000 to 2002, the largest popular disk was larger than the largest popular tape. In that same time frame, the price per gigabyte of ATA disks dropped below that of tapes. Tape advocates claim that tapes have compatibility requirements that are not imposed on disks; tape readers must read or write the current and previous generation of tapes, and must read the last four generations of tapes. As disks are closed systems, disk heads need only read the platters enclosed with them, and this advantage explains why disks are improving much more rapidly. Today, some organizations have dropped tapes altogether, using networks and remote disks to replicate the data geographically. Indeed, many companies offering software as a service use inexpensive components but replicate data at an applica tion level across multiples sites. The sites are picked so that disasters would not take out both sites, enabling instantaneous recovery time. (Long recovery time for site disasters is another serious drawback to the serial nature of magnetic tapes.) Such a solution depends on advances in disk capacity and network bandwidth to make economic sense, but these two are getting much greater investment and hence have better recent records of accomplishment than tape. Fallacy: Operating systems are the best place to schedule disk accesses. As mentioned in Section 6.3, higher-level interfaces like ATA and SCSI offer logical block addresses to the host operating system. Given this high-level abstraction, the best an OS can do to try to help performance is to sort the logical block addresses into increasing order. However, since the disk knows the actual mapping of the logical addresses onto the physical geometry of sectors, tracks, and surfaces, it can reduce the rotational and seek latencies by rescheduling. For example, suppose the workload is four reads [Anderson, 2003]: Operation Starting LBA Length Read 724 8 Read 100 16 Read 9987 1 Read 26 128 The host might reorder the four reads into logical block order: Operation Starting LBA Length Read 26 128 Read 100 16 Read 724 8 Read 9987 1 | clipped_hennesy_Page_614_Chunk5971 |
Depending on the relative location of the data on the disk, reordering could make it worse, as Figure 6.19 shows. The disk-scheduled reads complete in three-quarters of a disk revolution, but the OS-scheduled reads take three revolutions. Pitfall: Using the peak transfer rate of a portion of the I/O system to make perfor mance projections or performance comparisons. Many of the components of an I/O system, from the devices to the controllers to the buses, are specified using their peak bandwidths. In practice, these peak band width measurements are often based on unrealistic assumptions about the system or are unattainable because of other system limitations. For example, in quoting bus performance, the peak transfer rate is sometimes specified using a memory system that is impossible to build. For networked systems, the software overhead of initiating communication is ignored. The 32-bit, 33MHz PCI bus has a peak bandwidth of about 133 MB/sec. In practice, even for long transfers, it is difficult to sustain more than about 80 MB/sec for realistic memory systems. Amdahl’s law also reminds us that the throughput of an I/O system will be limited by the lowest-performance component in the I/O path. 6.13 Concluding Remarks I/O systems are evaluated on several different characteristics: dependability; the variety of I/O devices supported; the maximum number of I/O devices; cost; and performance, measured both in latency and in throughput. These goals lead to FIGURE 6.19 Example showing OS versus disk schedule accesses, labeled host-ordered versus drive-ordered. The former takes three revolutions to complete the four reads, while the latter completes them in just three-fourths of a revolution (from Anderson [2003]). Host-ordered queue Drive-ordered queue 724 100 26 9987 6.13 Concluding Remarks 617 | clipped_hennesy_Page_615_Chunk5972 |
618 Chapter 6 Storage and Other I/O Topics widely varying schemes for interfacing I/O devices. In the low-end and midrange systems, buffered DMA is likely to be the dominant transfer mechanism. In the high-end systems, latency and bandwidth may both be important, and cost may be secondary. Multiple paths to I/O devices with limited buffering often charac terize high-end I/O systems. Typically, being able to access the data on an I/O device at any time (high availability) becomes more important as systems grow. As a result, redundancy and error correction mechanisms become more and more prevalent as we enlarge the system. Storage and networking demands are growing at unprecedented rates, in part because of increasing demands for all information to be at your fingertips. One estimate is that the amount of information created in 2002 was 5 exabytes— equivalent to 500,000 copies of the text in the U.S. Library of Congress—and that the total amount of information in the world was doubling every three years [Lyman and Varian, 2003]. Future directions of I/O include expanding the reach of wired and wireless net works, with nearly every device potentially having an IP address, and the expanding role of flash memory in storage systems. The performance of an I/O system, whether measured by bandwidth or latency, depends on all the elements in the path between the device and memory, includ ing the operating system that generates the I/O commands. The bandwidth of the interconnect, the memory, and the device determine the maximum transfer rate from or to the device. Similarly, the latency depends on the device latency, together with any latency imposed by the memory system or buses. The effective bandwidth and response latency also depend on other I/O requests that may cause contention for some resource in the path. Finally, the operating system is a bottleneck. In some cases, the OS takes a long time to deliver an I/O request from a user program to an I/O device, leading to high latency. In other cases, the operating system effectively limits the I/O bandwidth because of limitations in the number of concurrent I/O operations it can support. Keep in mind that while performance can help sell an I/O system, users over whelmingly demand capacity and dependability from their I/O systems. Historical Perspective and Further Reading The history of I/O systems is a fascinating one. Section 6.14 gives a brief history of magnetic disks, RAID, flash memory, databases, the Internet, the World Wide Web, and how Ethernet continues to triumph over its challengers. Understanding Program Performance 6.14 | clipped_hennesy_Page_616_Chunk5973 |
6.15 Exercises Contributed by Perry Alexander of the University of Kansas Exercise 6.1 Figure 6.2 describes numerous I/O devices in terms of their behavior, partner, and data rate. However, these classifications often do not provide a complete picture of data flow within a system. Explore device classifications for the following devices. a. Auto Pilot b. Automated Thermostat 6.1.1 [5] <6.1> For the devices listed in the table, identify I/O interfaces and classify them in terms of their behavior and partner. 6.1.2 [5] <6.1> For the interfaces identified in the previous problem, estimate their data rate. 6.1.3 [5] <6.1> For the interfaces identified in the previous problem, determine whether data rate or operation rate is the best performance measurement. Exercise 6.2 Mean Time Between Failures (MTBF), Mean Time To Replacement (MTTR), and Mean Time To Failure (MTTF) are useful metrics for evaluating the reliability and availability of a storage resource. Explore these concepts by answering the ques tions about devices with the following metrics. MTTF MTTR a. 3 Years 1 Day b. 7 Years 3 Days 6.2.1 [5] <6.1, 6.2> Calculate the MTBF for each of the devices in the table. 6.2.2 [5] <6.1, 6.2> Calculate the availability for each of the devices in the table. 6.2.3 [5] <6.1, 6.2> What happens to availability as the MTTR approaches 0? Is this a realistic situation? 6.2.4 [5] <6.1, 6.2> What happens to availability as the MTTR gets very high, i.e., a device is difficult to repair? Does this imply the device has low availability? 6.15 Exercises 619 | clipped_hennesy_Page_617_Chunk5974 |
620 Chapter 6 Storage and Other I/O Topics Exercise 6.3 Average and minimum times for reading and writing to storage devices are common measurements used to compare devices. Using techniques from Chap ter 6, calculate values related to read and write time for disks with the following characteristics. Average Seek Time RPM Disk Transfer Rate Controller Transfer Rate a. 10 ms 7500 90 MB/s 100 MB/s b. 7 ms 10,000 40 MB/s 200 MB/s 6.3.1 [10] <6.2, 6.3> Calculate the average time to read or write a 1024-byte sector for each disk listed in the table. 6.3.2 [10] <6.2, 6.3> Calculate the minimum time to read or write a 2048-byte sector for each disk listed in the table. 6.3.3 [10] <6.2, 6.3> For each disk in the table, determine the dominant factor for performance. Specifically, if you could make an improvement to any aspect of the disk, what would you choose? If there is no dominant factor, explain why. Exercise 6.4 Ultimately, storage system design requires consideration of usage scenarios as well as disk parameters. Different situations require different metrics. Let’s try to systematically evaluate disk systems. Explore differences in how storage systems should be evaluated by answering the questions about the following applications. a. Aircraft Control System b. Phone Switch 6.4.1 [5] <6.2, 6.3> For each application, would decreasing the sector size during reads and writes improve performance? Explain your answer. 6.4.2 [5] <6.2, 6.3> For each application, would increasing disk rotation speed improve performance? Explain your answer. 6.4.3 [5] <6.2, 6.3> For each application, would increasing disk rotation speed improve system performance given that MTTF is decreased? Explain your answer. | clipped_hennesy_Page_618_Chunk5975 |
Exercise 6.5 FLASH memory is one of the first true competitors for traditional disk drives. Explore the implications of FLASH memory by answering questions about the following applications. a. Aircraft Control System b. Phone Switch 6.5.1 [5] <6.2, 6.3, 6.4> As we move towards solid state drives constructed from FLASH memory, what will change about disk read times assuming that the data transfer rate stays constant? 6.5.2 [10] <6.2, 6.3, 6.4> Would each application benefit from a solid state FLASH drive given that cost is a design factor? 6.5.3 [10] <6.2, 6.3, 6.4> Would each application be inappropriate for a solid state FLASH drive given that cost is NOT a design factor? Exercise 6.6 Explore the nature of FLASH memory by answering the questions related to per formance for FLASH memories with the following characteristics. Data Transfer Rate Controller Transfer Rate a. 120 MB/s 100 MB/s b. 100 MB/s 90 MB/s 6.6.1 [10] <6.2, 6.3, 6.4> Calculate the average time to read or write a 1024-byte sector for each FLASH memory listed in the table. 6.6.2 [10] <6.2, 6.3, 6.4> Calculate the minimum time to read or write a 512-byte sector for each FLASH memory listed in the table. 6.6.3 [5] <6.2, 6.3, 6.4> Figure 6.6 shows that FLASH memory read and write access times increase as FLASH memory gets larger. Is this unexpected? What fac tors cause this? 6.15 Exercises 621 | clipped_hennesy_Page_619_Chunk5976 |
622 Chapter 6 Storage and Other I/O Topics Exercise 6.7 I/O can be performed either synchronously or asynchronously. Explore the differ ences by answering performance questions about the following peripherals. a. Printer b. Scanner 6.7.1 [5] <6.5> What would be the most appropriate bus type (synchronous or asynchronous) for handling communications between a CPU and the peripherals listed in the table? 6.7.2 [5] <6.5> What problems would long, synchronous busses cause for con nections between a CPU and the peripherals listed in the table? 6.7.3 [5] <6.5> What problems would asynchronous busses cause for connec tions between a CPU and the peripherals listed in the table? Exercise 6.8 Among the most common bus types used in practice today are FireWire (IEEE 1394), USB, PCI, and SATA. Although all four are asynchronous, they are imple mented in different ways giving them different characteristics. Explore differ ent bus structures by answering questions about the busses and the following peripherals. a. Mouse b. Graphics Coprocessor 6.8.1 [5] <6.5> Select an appropriate bus (FireWire, USB, PCI, or SATA) for the peripherals listed in the table. Explain why the bus selected is appropriate. (See Figure 6.8 for key characteristics of each bus.) 6.8.2 [20] <6.5> Use online or library resources and summarize the communica tion structure for each bus type. Identify what the bus controller does and where the control physically is. 6.8.3 [15] <6.5> Outline limitations of each of the bus types. Explain why those limitations must be taken into consideration when using the bus. Exercise 6.9 Communicating with I/O devices is achieved using combinations of polling, interrupt handling, memory mapping, and special I/O commands. Answer the | clipped_hennesy_Page_620_Chunk5977 |
questions about communicating with I/O subsystems for the following applica tions using combinations of these techniques. a. Auto Pilot b. Automated Thermostat 6.9.1 [5] <6.6> Describe device polling. Would each application in the table be appropriate for communication using polling techniques? Explain. 6.9.2 [5] <6.6> Describe interrupt driven communication. For each application in the table, if polling is inappropriate, explain how interrupt driven techniques could be used. 6.9.3 [10] <6.6> For the applications listed in the table, outline a design for memory mapped communication. Identify reserved memory locations and out line their contents. 6.9.4 [10] <6.6> For the applications listed in the table, outline a design for com mands implementing command driven communication. Identify commands and their interaction with the device. 6.9.5 [5] <6.6> Does it make sense to define I/O subsystems that use a combi nation of memory mapping and command driven communication? Explain your answer. Exercise 6.10 Section 6.6 defines an eight-step process for handling interrupts. The Cause and Status registers together provide information on the cause of the interrupt and the status of the interrupt handling system. Explore interrupt handling by answering the questions about the following combinations of interrupts. a. Ethernet Controller Data Mouse Controller Reboot b. Mouse Controller Power Down Overheat 6.10.1 [5] <6.6> When an interrupt is detected, the Status register is saved and all but the highest priority interrupt is disabled. Why are low-priority interrupts disabled? Why is the status register saved prior to disabling interrupts? 6.10.2 [10] <6.6> Prioritize interrupts from the devices listed in each table row. 6.10.3 [10] <6.6> Outline how an interrupt from each of the devices listed in the table would be handled. 6.15 Exercises 623 | clipped_hennesy_Page_621_Chunk5978 |
624 Chapter 6 Storage and Other I/O Topics 6.10.4 [5] <6.6> What happens if the interrupt enable bit of the Cause register is not set when handling an interrupt? What value could the interrupt mask value take to accomplish the same thing? 6.10.5 [5] <6.6> Most interrupt handling systems are implemented in the operat ing system. What hardware support could be added to make interrupt handling more efficient? Contrast your solution to potential hardware support for function calls. 6.10.6 [5] <6.6> In some interrupt handling implementations, an interrupt causes an immediate jump to an interrupt vector. Instead of a Cause register where each interrupt sets a bit, each interrupt has its own interrupt vector. Can the same priority interrupt system be implemented using this approach? Is there any advan tage to this approach? Exercise 6.11 Direct Memory Access (DMA) allows devices to access memory directly rather than working through the CPU. This can dramatically speed up the performance of peripherals, but adds complexity to memory system implementations. Explore DMA implications by answering the questions about the following peripherals. a. Mouse Controller b. Ethernet Controller 6.11.1 [5] <6.6> Does the CPU relinquish control of memory when DMA is active? For example, can a peripheral simply communicate with memory directly, avoiding the CPU completely? 6.11.2 [10] <6.6> Of the peripherals listed in the table, which would benefit from DMA? What criteria determine if DMA is appropriate? 6.11.3 [10] <6.6> Of the peripherals listed in the table, which could cause coher ency problems with cache contents? What criteria determine if coherency issues must be addressed? 6.11.4 [5] <6.6> Describe what problems could occur when mixing DMA and virtual memory. Which of the peripherals in the table could introduce such prob lems? How can they be avoided? Exercise 6.12 Metrics for I/O performance may vary dramatically from application to applica tion. Where the number of transactions processed dominates performance in some | clipped_hennesy_Page_622_Chunk5979 |
situations, data throughput dominates in others. Explore I/O performance evalua tion by answering the questions for the following applications. a. Mathematical Computations b. Online Chat 6.12.1 [10] <6.7> For each application in the table, does I/O performance domi nate system performance? 6.12.2 [10] <6.7> For each application in the table, is I/O performance best mea sured using raw data throughput? 6.12.3 [5] <6.7> For each application in the table, is I/O performance best mea sured using the number of transactions processed? 6.12.4 [5] <6.7> Is there a relationship between the performance measures from the previous two problems and choosing whether to use polling or interrupt driven communication? What about the choice of using memory mapped or command driven I/O? Exercise 6.13 Benchmarks play an important role in evaluating and selecting peripheral devices. For benchmarks to be useful, they must exhibit properties similar to those experi enced by a device under normal use. Explore benchmarks and device selection by answering questions about the following applications. a. Mathematical Computations b. Online Chat 6.13.1 [5] <6.7> For each application in the table, define characteristics that a set of benchmarks should exhibit when evaluating an I/O subsystem. 6.13.2 [15] <6.7> Using online or library resources, identify a set of standard benchmarks for applications in the table. Why do standard benchmarks help? 6.13.3 [5] <6.7> Does it make sense to evaluate an I/O subsystem outside the larger system it is a part of? How about evaluating a CPU? Exercise 6.14 RAID is among the most popular approaches to parallelism and redundancy in storage systems. The name Redundant Arrays of Inexpensive Disks implies several 6.15 Exercises 625 | clipped_hennesy_Page_623_Chunk5980 |
626 Chapter 6 Storage and Other I/O Topics things about RAID arrays that we will explore in the context of the following activities. a. High-Performance Mathematical Computations b. Online Video Services 6.14.1 [10] <6.9> RAID 0 uses striping to force parallel access among many disks. Why does striping improve disk performance? For each of the activities listed in the table, will striping help better achieve their goals? 6.14.2 [5] <6.9> RAID 1 mirrors data among several disks. Assuming that inex pensive disks have lower MTBF than expensive disks, how can redundancy using inexpensive disks result in a system with lower MTBF? Use the mathematical defi nition of MTBF to explain your answer. For each of the activities listed in the table, will RAID 1 help better achieve their goals? 6.14.3 [5] <6.9> Like RAID 1, RAID 3 provides higher data availability. Explain the trade-off between RAID 1 and RAID 3. Would each of the applications listed in the table benefit from RAID 3 over RAID 1? Exercise 6.15 RAID 3, RAID 4, and RAID 5 all use parity system to protect blocks of data. Specifically, a parity block is associated with a collection of data blocks. Each row in the following table shows the values of the data and parity blocks, as described in Figure 6.13. New D0 D0 D1 D2 D3 P a. 7453 AB9C AABB 0098 549C 2FFF b. F245 7453 DD25 AABB FEFE FEFF 6.15.1 [10] <6.9> Calculate the new RAID 3 parity value P’ for data in lines a and b in the table. 6.15.2 [10] <6.9> Calculate the new RAID 4 parity value P’ for data in lines a and b in the table. 6.15.3 [5] <6.9> Is RAID 3 or RAID 4 more efficient? Are there reasons why RAID 3 would be preferable to RAID 4? 6.15.4 [5] <6.9> RAID 4 and RAID 5 use roughly the same mechanism to calcu late and store parity for data blocks. How does RAID 5 differ from RAID 4 and for what applications would RAID 5 be more efficient? | clipped_hennesy_Page_624_Chunk5981 |
6.15.5 [5] <6.9> RAID 4 and RAID 5 speed improvements grow with respect to RAID 3 as the size of the protected block grows. Why is this the case? Is there a situ ation where RAID 4 and RAID 5 would be no more efficient than RAID 3? Exercise 6.16 The emergence of web servers for ecommerce, online storage, and communication has made disk servers critical applications. Availability and speed are well-known metrics for disk servers, but power consumption is becoming increasingly impor tant. Answer the questions about configuration and evaluation of disk servers with the following parameters. Program Instructions/ I/O Operation OS Instructions/ I/O Operation Workload (KB reads) Processor Speed (Instructions/ Second) a. 100,000 150,000 64 2 Billion b. 200,000 200,000 128 3 Billion 6.16.1 [10] <6.8, 6.10> Find the maximum sustained I/O rate for random reads and writes. Ignore disk conflicts and assume the RAID controller is not the bottleneck. Follow the same approach as outlined in Section 6.10 making similar assumptions where necessary. 6.16.2 [10] <6.8, 6.10> Assume we are configuring a Sun Fire x4150 server as described in Section 6.10. Determine if a configuration of 8 disks presents an I/O bottleneck. Repeat for configurations of 16, 4, and 2 disks. 6.16.3 [10] <6.8, 6.10> Determine if the PCI bus, DIMM, or the Front Side Bus presents an I/O bottleneck. Use the same parameters and assumptions used in Section 6.10. 6.16.4 [5] <6.8, 6.10> Explain why real systems tend to use benchmarks or real applications to assess actual performance. Exercise 6.17 Determining the performance of a single server with relatively complete data is an easy task. However, when comparing servers from different vendors providing dif ferent data, choosing among alternatives can be difficult. Explore the process of find ing and evaluating servers by answering questions about the following application. Database Server 6.17.1 [15] <6.8, 6.10> For the application listed above, identify runtime charac teristics for an operational system. Choose characteristics that will support evalua tion similar to that performed for Exercise 6.16. 6.15 Exercises 627 | clipped_hennesy_Page_625_Chunk5982 |
628 Chapter 6 Storage and Other I/O Topics 6.17.2 [15] <6.8, 6.10> For the application listed above, find a server available in the marketplace that you feel would be appropriate for running the application. Before evaluating the server, identify reasons why it was selected. 6.17.3 [20] <6.8, 6.10> Using metrics similar to those used in Chapter 6 and Exercise 6.16, assess the server you identified in 6.17.2 in comparison to the Sun Fire x4150 server evaluated in Exercise 6.16. Which would you choose? Did the results of your analysis surprise you? Specifically, would you choose differently? 6.17.4 [15] <6.8, 6.10> Identify a standard benchmark set that would be useful for comparing the server you identified in 6.17.2 with the Sun Fire x4150. Exercise 6.18 Measurements and statistics provided by storage vendors must be carefully inter preted to gain meaningful predictions about their system behavior. The following table provides data for various disk drives. # of Drives Hours/Drive Hours/Failure a. 1000 10,512 1,200,000 b. 1250 8760 1,200,000 6.18.1 [10] <6.12> Calculate annual failure rate (AFR) for disks in the table. 6.18.2 [10] <6.12> Assume that annual failure rate varies over the lifetime of disks in the previous table. Specifically, assume that AFR is three times as high in the 1st month of operation and doubles every year starting in the 5th year. How many disks would be replaced after 7 years of operation? What about 10 years? 6.18.3 [10] <6.12> Assume that disks with lower failure rates are more expen sive. Specifically, disks are available at a higher cost that will start doubling their failure rate in year 8 rather than year 5. How much more would you pay for disks if your intent is to keep them for 7 years? What about 10 years? Exercise 6.19 For disks in the table in Exercise 6.18, assume that your vendor offers a RAID 0 configuration that will increase storage system throughput by 70% and a RAID 1 configuration that will drop AFR of disk pairs by 2. Assume that the cost of each solution is 1.6 times the original solution cost. 6.19.1 [5] <6.9, 6.12> Given only the original problem parameters, would you recommend upgrading to either RAID 0 or RAID 1 assuming individual disk parameters remain the same in the previous table? | clipped_hennesy_Page_626_Chunk5983 |
6.19.2 [5] <6.9, 6.12> Given that your company operates a global search engine with a large disk farm, does upgrading to either RAID 0 or RAID 1 make economic sense given that your income model is based on the number of advertisements served? 6.19.3 [5] <6.9, 6.12> Repeat 6.19.2 for a large disk farm operated by an online backup company. Does upgrading to either RAID 0 or RAID 1 make economic sense given that your income model is based on the availability of your server? Exercise 6.20 Day-to-day evaluation and maintenance of operational computer systems involves many of the concepts discussed in Chapter 6. Explore the intricacies of evaluating systems by exploring the following questions. 6.20.1 [20] <6.10, 6.12> Configure the Sun Fire x4150 to provide 10 terabytes of storage for a processor array of 1000 processors running bioinformatics simula tions. Your configuration should minimize power consumption while addressing throughput and availability concerns for the disk array. Make sure you consider the properties of large simulations when performing your configuration. 6.20.2 [20] <6.10, 6.12> Recommend a backup and data archiving system for the disk array from 6.20.1. Compare and contrast disk, tape, and online backup capa bilities. Use Internet and library resources to identify potential servers. Assess cost and suitability for the application using parameters described in Chapter 6. Select parameters for comparison using properties of the application as well as specified requirements. 6.20.3 [15] <6.10, 6.12> Competing vendors for the systems you identified in 6.20.2 have offered to allow you to evaluate their systems on site. Identify the benchmarks you will use to determine which system is best for your applica tion. Determine how long it will take you to gather enough data to make your determination. §6.2, page 575: 2 and 3 are true. §6.3, page 579: 3 and 4 are true. §6.4, page 582: All are true (assuming 40 MB/s is comparable to100 MB/s). §6.5, page 585: 1 is true. §6.6, page 594: 1 and 2. §6.7, page 598: 1 and 2. 3 is false, since most TPC benchmarks include cost. §6.9, page 605: All are true. Answers to Check Yourself 6.15 Exercises 629 | clipped_hennesy_Page_627_Chunk5984 |
7 There are finer fish in the sea than have ever been caught. Irish proverb Multicores, Multiprocessors, and Clusters 7.1 Introduction 632 7.2 The Difficulty of Creating Parallel Processing Programs 634 7.3 Shared Memory Multiprocessors 638 7.4 Clusters and Other Message-Passing Multiprocessors 641 7.5 Hardware Multithreading 645 Computer Organization and Design. DOI: 10.1016/B978-0-12-374750-1.00007-4 © 2012 Elsevier, Inc. All rights reserved. | clipped_hennesy_Page_628_Chunk5985 |
7.6 SISD, MIMD, SIMD, SPMD, and Vector 648 7.7 Introduction to Graphics Processing Units 654 7.8 Introduction to Multiprocessor Network Topologies 660 7.9 Multiprocessor Benchmarks 664 7.10 Roofline: A Simple Performance Model 667 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 675 7.12 Fallacies and Pitfalls 684 7.13 Concluding Remarks 686 7.14 Historical Perspective and Further Reading 688 7.15 Exercises 688 Multiprocessor or Cluster Organization Computer Computer Computer Computer Network | clipped_hennesy_Page_629_Chunk5986 |
632 Chapter 7 Multicores, Multiprocessors, and Clusters 7.1 Introduction Computer architects have long sought the El Dorado of computer design: to create powerful computers simply by connecting many existing smaller ones. This golden vision is the fountainhead of multiprocessors. Ideally, customers order as many processors as they can afford and receive a commensurate amount of performance. Thus, multiprocessor software must be designed to work with a variable number of processors. As mentioned in Chapter 1, power has become the overriding issue for both datacenters and microprocessors. Replacing large inefficient processors with many smaller, efficient processors can deliver better performance per watt or per joule both in the large and in the small, if software can efficiently use them. Thus, improved power efficiency joins scalable performance in the case for multi processors. Since multiprocessor software must scale, some designs support operation in the presence of broken hardware; that is, if a single processor fails in a multipro cessor with n processors, these system would continue to provide service with n - 1 processors. Hence, multiprocessors can also improve availability (see Chapter 6). High performance can mean high throughput for independent jobs, called job- level parallelism or process-level parallelism. These parallel jobs are independent applications, and they are an important and popular use of parallel computers. This approach is in contrast to running a single job on multiple processors. We use the term parallel processing program to refer to a single program that runs on multi ple processors simultaneously. There have long been scientific problems that have needed much faster com puters, and this class of problems has been used to justify many novel parallel computers over the past decades. We will cover several of them in this chapter. Some of these problems can be handled simply, using a cluster composed of microprocessors housed in many independent servers or PCs. In addition, clus ters can serve equally demanding applications outside the sciences, such as search engines, Web servers, email servers, and databases. As described in Chapter 1, multiprocessors have been shoved into the spot light because the power problem means that future increases in performance will apparently come from more processors per chip rather than higher clock rates and improved CPI. They are called multicore microprocessors instead of multiprocessor microprocessors, presumably to avoid redundancy in naming. Hence, processors are often called cores in a multicore chip. The number of cores is expected to double every two years. Thus, programmers who care about performance must become parallel programmers, for sequential programs mean slow programs. multiprocessor A computer system with at least two processors. This is in contrast to a uniprocessor, which has one. job-level parallelism or process-level parallelism Utilizing multiple processors by running independent programs simultaneously. parallel processing program A single program that runs on multiple processors simultaneously. cluster A set of computers connected over a local area network (LAN) that functions as a single large multiprocessor. multicore microprocessor A microprocessor containing multiple processors (“cores”) in a single integrated circuit. “Over the Mountains Of the Moon, Down the Valley of the Shadow, Ride, boldly ride” The shade replied,— “If you seek for El Dorado!” Edgar Allan Poe, “El Dorado,” stanza 4, 1849 | clipped_hennesy_Page_630_Chunk5987 |
7.1 Introduction 633 The tall challenge facing the industry is to create hardware and software that will make it easy to write correct parallel processing programs that will execute efficiently in performance and power as the number of cores per chip scales geometrically. This sudden shift in microprocessor design has caught many off guard, so there is a great deal of confusion about the terminology and what it means. Figure 7.1 tries to clarify the terms serial, parallel, sequential, and concurrent. The columns of this figure represent the software, which is either inherently sequential or concurrent. The rows of the figure represent the hardware, which is either serial or parallel. For example, the programmers of compilers think of them as sequential programs: the steps are lexical analysis, parsing, code generation, optimization, and so on. In contrast, the programmers of operating systems normally think of them as concurrent programs: cooperating processes handling I/O events due to independent jobs running on a computer. Software Sequential Concurrent Hardware Serial Matrix Multiply written in MatLab running on an Intel Pentium 4 Windows Vista Operating System running on an Intel Pentium 4 Parallel Matrix Multiply written in MATLAB running on an Intel Xeon e5345 (Clovertown) Windows Vista Operating System running on an Intel Xeon e5345 (Clovertown) FIGURE 7.1 Hardware/software categorization and examples of application perspective on concurrency versus hardware perspective on parallelism. The point of these two axes of Figure 7.1 is that concurrent software can run on serial hardware, such as operating systems for the Intel Pentium 4 uniprocessor, or on parallel hardware, such as an OS on the more recent Intel Xeon e5345 (Clovertown). The same is true for sequential software. For example, the MATLAB programmer writes a matrix multiply thinking about it sequentially, but it could run serially on Pentium 4 hardware or in parallel on Xeon e5345 hardware. You might guess that the only challenge of the parallel revolution is figuring out how to make naturally sequential software have high performance on parallel hardware, but it is also to make concurrent programs have high performance on multiprocessors as the number of processors increases. With this distinction made, in the rest of this chapter we will use parallel processing program or parallel software to mean either sequential or concurrent software running on parallel hardware. The next section describes why it is hard to create efficient parallel processing programs. Sections 7.3 and 7.4 describe the two alternatives of a fundamental parallel hardware characteristic, which is whether or not all the processors in the systems rely upon a single physical address. The two popular versions of these alternatives are called shared memory multiprocessors and clusters. Section 7.5 then | clipped_hennesy_Page_631_Chunk5988 |
634 Chapter 7 Multicores, Multiprocessors, and Clusters describes multithreading, a term often confused with multiprocessing, in part because it relies upon similar concurrency in programs. Section 7.6 describes an older classification scheme than in Figure 7.1. In addition, it describes two styles of instruction set architectures that support running of sequential applications on parallel hardware, namely SIMD and vector. Section 7.7 describes a relatively new style of computer from the graphics hardware community, called a graphics pro cessing unit (GPU). Appendix A describes GPUs in more detail. We next discuss the difficulty of finding parallel benchmarks in Section 7.9. This section is followed by a description of a new, simple, yet insightful performance model that helps in the design of applications as well as architectures. We use this model in Section 7.11 to evaluate four recent multicore computers on two application kernels. We close with fallacies and pitfalls and our conclusions for parallelism. Before proceeding further down the path to parallelism, don’t forget our initial incursions from the prior chapters: ■ ■Chapter 2, Section 2.11: Parallelism and Instructions: Synchronization ■ ■Chapter 3, Section 3.6: Parallelism and Computer Arithmetic: Associativity ■ ■Chapter 4, Section 4.10: Parallelism and Advanced Instruction-Level Parallelism ■ ■Chapter 5, Section 5.8: Parallelism and Memory Hierarchies: Cache Coherence ■ ■Chapter 6, Section 6.9: Parallelism and I/O: Redundant Arrays of Inexpensive Disks True or false: To benefit from a multiprocessor, an application must be concurrent. 7.2 The Difficulty of Creating Parallel Processing Programs The difficulty with parallelism is not the hardware; it is that too few important application programs have been rewritten to complete tasks sooner on multi processors. It is difficult to write software that uses multiple processors to complete one task faster, and the problem gets worse as the number of processors increases. Why has this been so? Why have parallel processing programs been so much harder to develop than sequential programs? The first reason is that you must get better performance and efficiency from a parallel processing program on a multiprocessor; otherwise, you would just use a sequential program on a uniprocessor, as programming is easier. In fact, uniprocessor design techniques such as superscalar and out-of-order execution take advantage of instruction-level parallelism (see Chapter 4), normally without the involvement of the programmer. Such innovations reduced the demand for rewriting programs for multiprocessors, since programmers could do nothing and yet their sequential programs would run faster on new computers. Check Yourself | clipped_hennesy_Page_632_Chunk5989 |
Why is it difficult to write parallel processing programs that are fast, especially as the number of processors increases? In Chapter 1, we used the analogy of eight reporters trying to write a single story in hopes of doing the work eight times faster. To succeed, the task must be broken into eight equal-sized pieces, because otherwise some reporters would be idle while waiting for the ones with larger pieces to finish. Another performance danger would be that the reporters would spend too much time communicating with each other instead of writing their pieces of the story. For both this analogy and parallel programming, the challenges include scheduling, load balancing, time for synchronization, and overhead for communication between the parties. The challenge is stiffer with the more reporters for a newspaper story and the more processors for parallel programming. Our discussion in Chapter 1 reveals another obstacle, namely Amdahl’s law. It reminds us that even small parts of a program must be parallelized if the program is to make good use of many cores. Speed-up Challenge Suppose you want to achieve a speed-up of 90 times faster with 100 processors. What percentage of the original computation can be sequential? Amdahl’s law (Chapter 1) says Execution time after improvement = Execution time affected by improvement Amount of improvement + Execution time unaffected We can reformulate Amdahl’s in terms of speed-up versus the original execu tion time: EXAMPLE ANSWER Speed-up = Execution time before ________________________________________________________________ (Execution time before - Execution time affected) + Execution time affected 100 This formula is usually rewritten assuming that the execution time before is 1 for some unit of time, and the execution time affected by improvement is considered the fraction of the original execution time: Speed-up = 1 __________________________________________ (1 − Fraction time affected) + Fraction time affected __________________ 100 7.2 The Difficulty of Creating Parallel Processing Programs 635 | clipped_hennesy_Page_633_Chunk5990 |
636 Chapter 7 Multicores, Multiprocessors, and Clusters Substituting for the goal of a speed-up of 90 into the formula above: 90 = 1 _____________________________________ (1 − Fraction time affected) + Fraction time affected 100 Then simplifying the formula and solving for fraction time affected: 90 × (1 – 0.99 × Fraction time affected) = 1 90 - (90 × 0.99 × Fraction time affected) = 1 90 - 1 = 90 × 0.99 × Fraction time affected Fraction time affected = 89/89.1 = 0.999 Thus, to achieve a speed-up of 90 from 100 processors, the sequential percent age can only be 0.1%. Yet, there are applications with substantial parallelism. Speed-up Challenge: Bigger Problem Suppose you want to perform two sums: one is a sum of 10 scalar variables, and one is a matrix sum of a pair of two-dimensional arrays, with dimensions 10 by 10. What speed-up do you get with 10 versus 100 processors? Next, cal culate the speed-ups assuming the matrices grow to 100 by 100. If we assume performance is a function of the time for an addition, t, then there are 10 additions that do not benefit from parallel processors and 100 additions that do. If the time for a single processor is 110 t, the execution time for 10 processors is Execution time after improvement = Execution time affected by improvement _________________________________ Amount of improvement + Execution time unaffected Execution time affected improvement = 100t ____ 10 + 10t = 20t so the speed-up with 10 processors is 110t/20t = 5.5. The execution time for 100 processors is Execution time after improvement = 100t ____ 100 + 10t = 11t so the speed-up with 100 processors is 110t/11t = 10. EXAMPLE ANSWER | clipped_hennesy_Page_634_Chunk5991 |
Thus, for this problem size, we get about 55% of the potential speed-up with 10 processors, but only 10% with 100. Look what happens when we increase the matrix. The sequential program now takes 10t + 10,000t = 10,010t. The execution time for 10 processors is Execution time after improvement = 10,000t _______ 10 + 10t = 1010t so the speed-up with 10 processors is 10,010t/1010t = 9.9. The execution time for 100 processors is Execution time after improvement = 10,000t _______ 100 + 10t = 110t so the speed-up with 100 processors is 10,010t/110t = 91. Thus, for this larger problem size, we get about 99% of the potential speed-up with 10 processors and more than 90% with 100. These examples show that getting good speed-up on a multiprocessor while keeping the problem size fixed is harder than getting good speed-up by increasing the size of the problem. This allows us to introduce two terms that describe ways to scale up. Strong scaling means measuring speed-up while keeping the problem size fixed. Weak scaling means that the program size grows proportionally to the increase in the number of processors. Let’s assume that the size of the problem, M, is the working set in main memory, and we have P processors. Then the memory per processor for strong scaling is approximately M/P, and for weak scaling, it is approximately M. Depending on the application, you can argue for either scaling approach. For example, the TPC-C debit-credit database benchmark (Chapter 6) requires that you scale up the number of customer accounts to achieve higher transactions per minute. The argument is that it’s nonsensical to think that a given customer base is suddenly going to start using ATMs 100 times a day just because the bank gets a faster computer. Instead, if you’re going to demonstrate a system that can perform 100 times the numbers of transactions per minute, you should run the experiment with 100 times as many customers. This final example shows the importance of load balancing. Speed-up Challenge: Balancing Load To achieve the speed-up of 91 on the previous larger problem with 100 proces sors, we assumed the load was perfectly balanced. That is, each of the 100 processors had 1% of the work to do. Instead, show the impact on speed-up if one processor’s load is higher than all the rest. Calculate at 2% and 5%. strong scaling Speed-up achieved on a multi processor without increasing the size of the problem. weak scaling Speed-up achieved on a multi processor while increasing the size of the problem proportionally to the increase in the number of processors. EXAMPLE 7.2 The Difficulty of Creating Parallel Processing Programs 637 | clipped_hennesy_Page_635_Chunk5992 |
638 Chapter 7 Multicores, Multiprocessors, and Clusters If one processor has 2% of the parallel load, then it must do 2% × 10,000 or 200 additions, and the other 99 will share the remaining 9800. Since they are operating simultaneously, we can just calculate the execution time as a maximum Execution time after improvement = Max ( 9800t _____ 99 , 200t ____ 1 ) + 10t = 210t The speed-up drops to 10,010t/210t = 48. If one processor has 5% of the load, it must perform 500 additions: Execution time after improvement = Max ( 9500t _____ 99 , 500t ____ 1 ) + 10t = 510t The speed-up drops even further to 10,010t/510t = 20. This example dem onstrates the value of balancing load, for just a single processor with twice the load of the others cuts speed-up almost in half, and five times the load on one processor reduces the speed-up by almost a factor of five. True or false: Strong scaling is not bound by Amdahl’s law. 7.3 Shared Memory Multiprocessors Given the difficulty of rewriting old programs to run well on parallel hardware, a natural question is what computer designers can do to simplify the task. One answer was to provide a single physical address space that all processors can share, so that programs need not concern themselves with where they are run, merely that they may be executed in parallel. In this approach, all variables of a program can be made available at any time to any processor. The alternative is to have a separate address space per processor that requires that sharing must be explicit; we’ll describe this option in the next section. When the physical address space is common—which is usually the case for multicore chips—then the hardware typically provides cache coherence to give a consistent view of the shared memory (see Section 5.8 of Chapter 5). A shared memory multiprocessor (SMP) is one that offers the programmer a single physical address space across all processors, although a more accurate term would have been shared-address multiprocessor. Note that such systems can still run independent jobs in their own virtual address spaces, even if they all share a physical address space. Processors communicate through shared variables in memory, with all processors capable of accessing any memory location via loads and stores. Figure 7.2 shows the classic organization of an SMP. Single address space multiprocessors come in two styles. The first takes about the same time to access main memory no matter which processor requests it and no matter which word is requested. Such machines are called uniform memory access (UMA) multiprocessors. In the second style, some memory accesses are ANSWER Check Yourself shared memory multiprocessor (SMP) A parallel processor with a single address space, implying implicit communication with loads and stores. uniform memory access (UMA) A multiprocessor in which accesses to main memory take about the same amount of time no matter which processor requests the access and no matter which word is asked. | clipped_hennesy_Page_636_Chunk5993 |
much faster than others, depending on which processor asks for which word. Such machines are called nonuniform memory access (NUMA) multiprocessors. As you might expect, the programming challenges are harder for a NUMA multiprocessor than for a UMA multiprocessor, but NUMA machines can scale to larger sizes and NUMAs can have lower latency to nearby memory. As processors operating in parallel will normally share data, they also need to coordinate when operating on shared data; otherwise, one processor could start working on data before another is finished with it. This coordination is called synchronization. When sharing is supported with a single address space, there must be a separate mechanism for synchronization. One approach uses a lock for a shared variable. Only one processor at a time can acquire the lock, and other processors interested in shared data must wait until the original processor unlocks the variable. Section 2.11 of Chapter 2 describes the instructions for locking in MIPS. A Simple Parallel Processing Program for a Shared Address Space Suppose we want to sum 100,000 numbers on a shared memory multipro cessor computer with uniform memory access time. Let’s assume we have 100 processors. The first step again would be to split the set of numbers into subsets of the same size. We do not allocate the subsets to a different memory space, since there is a single memory space for this machine; we just give different starting addresses to each processor. Pn is the number that identifies the processor, between 0 and 99. All processors start the program by running a loop that sums their subset of numbers: EXAMPLE ANSWER Processor Memory I/O Processor Processor Cache Cache Cache Interconnection Network . . . . . . FIGURE 7.2 Classic organization of a shared memory multiprocessor. nonuniform memory access (NUMA) A type of single address space multiprocessor in which some memory accesses are much faster than others depending on which processor asks for which word. synchronization The process of coordinating the behavior of two or more processes, which may be running on different processors. lock A synchronization device that allows access to data to only one processor at a time. 7.3 Shared Memory Multiprocessors 639 | clipped_hennesy_Page_637_Chunk5994 |
640 Chapter 7 Multicores, Multiprocessors, and Clusters sum[Pn] = 0; for (i = 1000*Pn; i < 1000*(Pn+1); i = i + 1) sum[Pn] = sum[Pn] + A[i]; /* sum the assigned areas*/ The next step is to add these many partial sums. This step is called a reduction. We divide to conquer. Half of the processors add pairs of partial sums, and then a quarter add pairs of the new partial sums, and so on until we have the single, final sum. Figure 7.3 illustrates the hierarchical nature of this reduction. In this example, the two processors must synchronize before the “consumer” processor tries to read the result from the memory location written by the “producer” processor; otherwise, the consumer may read the old value of the data. We want each processor to have its own version of the loop counter variable i, so we must indicate that it is a “private” variable. Here is the code (half is private also): half = 100; /* 100 processors in multiprocessor*/ repeat synch(); /* wait for partial sum completion*/ if (half%2 != 0 && Pn == 0) sum[0] = sum[0] + sum[half-1]; /* Conditional sum needed when half is odd; Processor0 gets missing element */ half = half/2; /* dividing line on who sums */ if (Pn < half) sum[Pn] = sum[Pn] + sum[Pn+half]; until (half == 1); /* exit with final sum in Sum[0] */ True or false: Shared memory multiprocessors cannot take advantage of job- level parallelism. reduction A function that processes a data structure and returns a single value. Check Yourself 0 0 1 0 1 2 3 0 1 2 3 4 5 6 7 (half = 1) (half = 2) (half = 4) FIGURE 7.3 The last four levels of a reduction that sums results from each processor, from bottom to top. For all processors whose number i is less than half, add the sum produced by processor number (i + half) to its sum. Elaboration: An alternative to sharing the physical address space would be to have separate physical address spaces but share a common virtual address space, leaving it up to the operating system to handle communication. This approach has been tried, but it has too high an overhead to offer a practical shared memory abstraction to the programmer. | clipped_hennesy_Page_638_Chunk5995 |
7.4 Clusters and Other Message-Passing Multiprocessors The alternative approach to sharing an address space is for the processors to each have their own private physical address space. Figure 7.4 shows the classic organi zation of a multiprocessor with multiple private address spaces. This alternative multiprocessor must communicate via explicit message passing, which tradition ally is the name of such style of computers. Provided the system has routines to send and receive messages, coordination is built in with message passing, since one processor knows when a message is sent, and the receiving processor knows when a message arrives. If the sender needs confirmation that the message has arrived, the receiving processor can then send an acknowledgment message back to the sender. FIGURE 7.4 Classic organization of a multiprocessor with multiple private address spaces, traditionally called a message-passing multiprocessor. Note that unlike the SMP in Figure 7.2, the interconnection network is not between the caches and memory but is instead between processor-memory nodes. Cache Cache Cache Memory Memory Memory Interconnection Network . . . . . . Processor Processor Processor . . . Some concurrent applications run well on parallel hardware, independent of whether it offers shared addresses or message passing. In particular, job-level par allelism and applications with little communication—like Web search, mail serv ers, and file servers—do not require shared addressing to run well. There were several attempts to build high-performance computers based on high- performance message-passing networks, and they did offer better absolute commu nication performance than clusters built using local area networks. The problem was that they were much more expensive. Few applications could justify the higher communication performance, given the much higher costs. Hence, clusters have become the most widespread example today of the message-passing parallel com puter. Clusters are generally collections of commodity computers that are connected to each other over their I/O interconnect via standard network switches and cables. Each runs a distinct copy of the operating system. Virtually every Internet service relies on clusters of commodity servers and switches. message passing Communicating between multiple processors by explicitly sending and receiving information. send message routine A routine used by a processor in machines with private memories to pass to another processor. receive message routine A routine used by a processor in machines with private memories to accept a message from another processor. clusters Collections of computers connected via I/O over standard network switches to form a message-passing multiprocessor. 7.4 Clusters and Other Message-Passing Multiprocessors 641 | clipped_hennesy_Page_639_Chunk5996 |
642 Chapter 7 Multicores, Multiprocessors, and Clusters One drawback of clusters has been that the cost of administering a cluster of n machines is about the same as the cost of administering n independent machines, while the cost of administering a shared memory multiprocessor with n processors is about the same as administering a single machine. This weakness is one of the reasons for the popularity of virtual machines (Chapter 5), since VMs make clusters easier to administer. For example, VMs make it possible to stop or start programs atomically, which simplifies software upgrades. VMs can even migrate a program from one computer in a cluster to another without stopping the program, allowing a program to migrate from failing hardware. Another drawback to clusters is that the processors in a cluster are usually connected using the I/O interconnect of each computer, whereas the cores in a multiprocessor are usually connected on the memory interconnect of the computer. The memory interconnect has higher bandwidth and lower latency, allowing much better communication performance. A final weakness is the overhead in the division of memory: a cluster of n machi nes has n independent memories and n copies of the operating system, but a shared memory multiprocessor allows a single program to use almost all the memory in the computer, and it only needs a single copy of the OS. Memory Efficiency Suppose a single shared memory processor has 20 GB of main memory, five clustered computers each have 4 GB, and the OS occupies 1 GB. How much more space is there for users with shared memory? The ratio of memory available for user programs on the shared memory computer versus the cluster would be 20 − 1 _________ 5 × (4 − 1) = 19 ___ 15 ≈ 1.25 so shared memory computers have about 25% more space. Let’s redo the summing example from the prior section to see the impact of multiple private memories and explicit communication. A Simple Parallel Processing Program for Message Passing Suppose we want to sum 100,000 numbers in a message-passing multiprocessor with 100 processors, each with multiple private memories. EXAMPLE ANSWER EXAMPLE | clipped_hennesy_Page_640_Chunk5997 |
Since this computer has multiple address spaces, the first step is distributing the 100 subsets to each of the local memories. The processor containing the 100,000 numbers sends the subsets to each of the 100 processor-memory nodes. The next step is to get the sum of each subset. This step is simply a loop that every processor follows: read a word from local memory and add it to a local variable: sum = 0; for (i = 0; i<1000; i = i + 1) /* loop over each array */ sum = sum + AN[i]; /* sum the local arrays */ The last step is the reduction that adds these 100 partial sums. The hard part is that each partial sum is located in a different processor. Hence, we must use the interconnection network to send partial sums to accumulate the final sum. Rather than sending all the partial sums to a single processor, which would result in sequentially adding the partial sums, we again divide to conquer. First, half of the processors send their partial sums to the other half of the processors, where two partial sums are added together. Then one-quarter of the processors (half of the half) send this new partial sum to the other quarter of the processors (the remaining half of the half) for the next round of sums. This halving, sending, and receiving continue until there is a single sum of all numbers. Let Pn represent the number of the processor, send(x,y) be a rou tine that sends over the interconnection network to processor number x the value y, and receive() be a function that accepts a value from the network for this processor. Here is the code: limit = 100; half = 100;/* 100 processors */ repeat half = (half+1)/2; /* send vs. receive dividing line*/ if (Pn >= half && Pn < limit) send(Pn - half, sum); if (Pn < (limit/2)) sum = sum + receive(); limit = half; /* upper limit of senders */ until (half == 1); /* exit with final sum */ This code divides all processors into senders or receivers, and each receiving processor gets only one message, so we can presume that a receiving processor will stall until it receives a message. Thus, send and receive can be used as primitives for synchronization as well as for communication, as the processors are aware of the transmission of data. If there is an odd number of nodes, the middle node does not participate in send/receive. The limit is then set so that this node is the highest node in the next iteration. ANSWER 7.4 Clusters and Other Message-Passing Multiprocessors 643 | clipped_hennesy_Page_641_Chunk5998 |
644 Chapter 7 Multicores, Multiprocessors, and Clusters Elaboration: This example assumes implicitly that message passing is about as fast as addition. In reality, message sending and receiving is much slower. An optimization to better balance computation and communication might be to have fewer nodes receive many sums from other processors. Computers that rely on message passing for communication rather than cache- coherent shared memory are much easier for hardware designers (see Section 5.8 of Chapter 5). The advantage for programmers is that communication is explicit, which means there are fewer performance surprises than with the implicit com munication in cache-coherent shared memory computers. The downside for pro grammers is that it’s harder to port a sequential program to a message-passing computer, since every communication must be identified in advance or the pro gram doesn’t work. Cache-coherent shared memory allows the hardware to figure out what data needs to be communicated, which makes porting easier. There are differences of opinion as to which is the shortest path to high performance, given the pros and cons of implicit communication. A weakness of separate memories for user memory turns into a strength in system availability. Since a cluster consists of independent computers connected through a local area network, it is much easier to replace a machine without bringing down the system in a cluster than in an SMP. Fundamentally, the shared address means that it is difficult to isolate a processor and replace a processor without heroic work by the operating system. Since the cluster software is a layer that runs on top of local operating systems running on each computer, it is much easier to disconnect and replace a broken machine. Given that clusters are constructed from whole computers and independent, scalable networks, this isolation also makes it easier to expand the system without bringing down the application that runs on top of the cluster. Lower cost, high availability, improved power efficiency, and rapid, incremental expandability make clusters attractive to service providers for the World Wide Web. The search engines that millions of us use every day depend upon this technology. eBay, Google, Microsoft, Yahoo, and others all have multiple datacenters each with clusters of tens of thousands of processors. Clearly, the use of multiple processors in Internet service companies has been hugely successful. Elaboration: Another form of large scale computing is grid computing, where the comput ers are spread across large areas, and then the programs that run across them must communicate via long haul networks. The most popular and unique form of grid computing was pioneered by the SETI@home project. It was observed that millions of PCs are idle at any one time doing nothing useful, and they could be harvested and put to good uses Hardware/ Software Interface | clipped_hennesy_Page_642_Chunk5999 |
if someone developed software that could run on those computers and then gave each PC an independent piece of the problem to work on. The first example was the Search for ExtraTerrestrial Intelligence (SETI). Over 5 million computer users in more than 200 countries have signed up for SETI@home and have collectively contributed over 19 billion hours of computer processing time. By the end of 2006, the SETI@home grid operated at 257 TeraFLOPS. 1. True or false: Like SMPs, message-passing computers rely on locks for synchronization. 2. True or false: Unlike SMPs, message-passing computers need multiple copies of the parallel processing program and the operating system. 7.5 Hardware Multithreading Hardware multithreading allows multiple threads to share the functional units of a single processor in an overlapping fashion. To permit this sharing, the processor must duplicate the independent state of each thread. For example, each thread would have a separate copy of the register file and the PC. The memory itself can be shared through the virtual memory mechanisms, which already support multi programming. In addition, the hardware must support the ability to change to a different thread relatively quickly. In particular, a thread switch should be much more efficient than a process switch, which typically requires hundreds to thou sands of processor cycles while a thread switch can be instantaneous. There are two main approaches to hardware multithreading. Fine-grained multithreading switches between threads on each instruction, resulting in inter leaved execution of multiple threads. This interleaving is often done in a round- robin fashion, skipping any threads that are stalled at that time. To make fine-grained multithreading practical, the processor must be able to switch threads on every clock cycle. One key advantage of fine-grained multithreading is that it can hide the throughput losses that arise from both short and long stalls, since instructions from other threads can be executed when one thread stalls. The primary disadvan tage of fine-grained multithreading is that it slows down the execution of the indi vidual threads, since a thread that is ready to execute without stalls will be delayed by instructions from other threads. Coarse-grained multithreading was invented as an alternative to fine-grained multithreading. Coarse-grained multithreading switches threads only on costly stalls, such as second-level cache misses. This change relieves the need to have thread switching be essentially free and is much less likely to slow down the execu tion of an individual thread, since instructions from other threads will only be issued when a thread encounters a costly stall. Coarse-grained multithreading suffers, however, from a major drawback: it is limited in its ability to overcome Check Yourself hardware multithreading Increasing utilization of a processor by switching to another thread when one thread is stalled. fine-grained multithreading A version of hardware multithreading that suggests switching between threads after every instruction. coarse-grained multithreading A version of hardware multithreading that suggests switching between threads only after significant events, such as a cache miss. 7.5 Hardware Multithreading 645 | clipped_hennesy_Page_643_Chunk6000 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.