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646 Chapter 7 Multicores, Multiprocessors, and Clusters throughput losses, especially from shorter stalls. This limitation arises from the pipeline start-up costs of coarse-grained multithreading. Because a processor with coarse-grained multithreading issues instructions from a single thread, when a stall occurs, the p... | clipped_hennesy_Page_644_Chunk6001 |
In the SMT case, thread-level parallelism and instruction-level parallelism are both exploited, with multiple threads using the issue slots in a single clock cycle. Ideally, the issue slot usage is limited by imbalances in the resource needs and resource availability over multiple threads. In practice, other factors ca... | clipped_hennesy_Page_645_Chunk6002 |
648 Chapter 7 Multicores, Multiprocessors, and Clusters Second, a key performance challenge is tolerating latency due to cache misses. Fine-grained computers like the UltraSPARC T2 switch to another thread on a miss, which is probably more effective in hiding memory latency than trying to fill unused issue slots as in ... | clipped_hennesy_Page_646_Chunk6003 |
While it is hard to provide examples of useful computers that would be classified as multiple instruction streams and single data stream (MISD), the inverse makes much more sense. SIMD computers operate on vectors of data. For example, a single SIMD instruction might add 64 numbers by sending 64 data streams to 64 AL... | clipped_hennesy_Page_647_Chunk6004 |
650 Chapter 7 Multicores, Multiprocessors, and Clusters This very low cost parallelism for narrow integer data was the original inspiration of the MMX instructions of the x86. As Moore’s law continued, more hardware was added to these multimedia extensions, and now SSE2 supports the simultaneous execution of a pair o... | clipped_hennesy_Page_648_Chunk6005 |
Here is the conventional MIPS code for DAXPY: l.d $f0,a($sp) ;load scalar a addiu r4,$s0,#512 ;upper bound of what to load loop: l.d $f2,0($s0) ;load x(i) mul.d $f2,$f2,$f0 ;a × x(i) l.d $f4,0($s1) ;load y(i) add.d $f4,$f4,$f2 ;a × x(i) + y(i) s.d $f4,0($s1) ;store into y(i) addiu $s0,$s0,#8 ;increment index to x addiu... | clipped_hennesy_Page_649_Chunk6006 |
652 Chapter 7 Multicores, Multiprocessors, and Clusters Elaboration: The loop in the example above exactly matched the vector length. When loops are shorter, vector architectures use a register that reduces the length of vector operations. When loops are larger, we add bookkeeping code to iterate full-length vector ope... | clipped_hennesy_Page_650_Chunk6007 |
Vector versus Multimedia Extensions Like multimedia extensions found in the x86 SSE instructions, a vector instruction specifies multiple operations. However, multimedia extensions typically specify a few operations while vector specifies dozens of operations. Unlike multimedia extensions, the number of elements in a... | clipped_hennesy_Page_651_Chunk6008 |
654 Chapter 7 Multicores, Multiprocessors, and Clusters 7.7 Introduction to Graphics Processing Units A major justification for adding SIMD instructions to existing architectures was that many microprocessors were connected to graphics displays in PCs and work stations, so an increasing fraction of processing time was... | clipped_hennesy_Page_652_Chunk6009 |
The language compilers target industry-standard intermediate languages instead of machine instructions. GPU driver software generates optimized GPU-specific machine instructions. While these APIs and languages evolve rapidly to embrace new GPU resources enabled by Moore’s law, the freedom from backward binary instru... | clipped_hennesy_Page_653_Chunk6010 |
656 Chapter 7 Multicores, Multiprocessors, and Clusters 2 to 32 GB. Finally, keep in mind that for general-purpose computation, you must include the time to transfer the data between CPU memory and GPU memory, since the GPU is a coprocessor. ■ ■Given the reliance on many threads to deliver good memory bandwidth, GPUs ... | clipped_hennesy_Page_654_Chunk6011 |
see the similarities to approaches presented in prior sections, such as fine-grained multithreading and vectors. To help you with that transition to the new vocabulary, we present a quick introduction to the terms and ideas in the Tesla GPU architecture and the CUDA programming environment. A discrete GPU chip sits on ... | clipped_hennesy_Page_655_Chunk6012 |
658 Chapter 7 Multicores, Multiprocessors, and Clusters Figure 7.7 combines all these features together and compares a Tesla multiprocessor to a Sun UltraSPARC T2 core, which is described in Sections 7.5 and 7.11. Both are hardware multithreaded by scheduling threads over time, shown on the vertical axis. Each Tesla mu... | clipped_hennesy_Page_656_Chunk6013 |
switching every two or four clock cycles versus every clock cycle, and the hardware was much simpler by restricting the frequency of switching. The CUDA programming environment has its own terminology as well. A CUDA program is a unified C/C++ program for a heterogeneous CPU and GPU system. It executes on the CPU and d... | clipped_hennesy_Page_657_Chunk6014 |
660 Chapter 7 Multicores, Multiprocessors, and Clusters In contrast to vector architectures, which rely on a vectorizing compiler to recognize data-level parallelism at compile time and generate vector instructions, hardware implementations of Tesla architecture discovers data-level parallelism among threads at runtime... | clipped_hennesy_Page_658_Chunk6015 |
black square, and the switch is shown as a colored circle. In this section, all links are bidirectional; that is, information can flow in either direction. All networks consist of switches whose links go to processor-memory nodes and to other switches. The first improvement over a bus is a network that connects a sequ... | clipped_hennesy_Page_659_Chunk6016 |
662 Chapter 7 Multicores, Multiprocessors, and Clusters frequently add extra links to these simple topologies to improve performance and reliability. An alternative to placing a processor at every node in a network is to leave only the switch at some of these nodes. The switches are smaller than processor- memory-swi... | clipped_hennesy_Page_660_Chunk6017 |
it easier to assign more wires to the link, as the power to drive many wires from a chip is less if the wires are short. Shorter wires are also cheaper than longer wires. Another practical limitation is that the three-dimensional drawings must be mapped onto chips that are essentially two-dimensional media. The final c... | clipped_hennesy_Page_661_Chunk6018 |
664 Chapter 7 Multicores, Multiprocessors, and Clusters 7.9 Multiprocessor Benchmarks As we saw in Chapter 1, benchmarking systems is always a sensitive topic, because it is a highly visible way to try to determine which system is better. The results affect not only the sales of commercial systems, but also the reputat... | clipped_hennesy_Page_662_Chunk6019 |
Benchmark Scaling? Reprogram? Description Linpack Weak Yes Dense matrix linear algebra [Dongarra, 1979] SPECrate Weak No Independent job parallelism [Henning, 2007] Stanford Parallel Applications for Shared Memory SPLASH 2 [Woo et al., 1995] Strong (although offers two problem sizes) No Complex 1D FFT Blocked LU Decomp... | clipped_hennesy_Page_663_Chunk6020 |
666 Chapter 7 Multicores, Multiprocessors, and Clusters a parallel benchmark suite similar in goals to the SPEC CPU benchmark suite. It includes both kernels and applications, including many from the high-performance computing community. This benchmark requires strong scaling, although it comes with two data sets. ■ ■T... | clipped_hennesy_Page_664_Chunk6021 |
7.10 Roofline: A Simple Performance Model This section is based on a paper by Williams and Patterson [2008]. In the recent past, conventional wisdom in computer architecture led to similar microproces sor designs. Nearly every desktop and server computer used caches, pipelining, superscalar instruction issue, branch p... | clipped_hennesy_Page_665_Chunk6022 |
668 Chapter 7 Multicores, Multiprocessors, and Clusters The ratio of floating-point operations per byte of memory accessed is called the arithmetic intensity. It can be calculated by taking the total number of floating- point operations for a program divided by the total number of data bytes transferred to main memory ... | clipped_hennesy_Page_666_Chunk6023 |
actual floating-point performance can be no higher than the horizontal line, since that is a hardware limit. How could we plot the peak memory performance? Since X-axis is FLOPs/ byte and the Y-axis is FLOPs/second, bytes/second is just a diagonal line at a 45-degree angle in this figure. Hence, we can plot a third lin... | clipped_hennesy_Page_667_Chunk6024 |
670 Chapter 7 Multicores, Multiprocessors, and Clusters Note that the “ridge point,” where the diagonal and horizontal roofs meet, offers an interesting insight into the computer. If it is far to the right, then only kernels with very high arithmetic intensity can achieve the maximum performance of that computer. If i... | clipped_hennesy_Page_668_Chunk6025 |
The roofline model gives an upper bound to performance. Suppose your program is far below that bound. What optimizations should you perform, and in what order? To reduce computational bottlenecks, the following two optimizations can help almost any kernel: 1. Floating-point operation mix. Peak floating-point performanc... | clipped_hennesy_Page_669_Chunk6026 |
672 Chapter 7 Multicores, Multiprocessors, and Clusters FIGURE 7.15 Roofline model with ceilings. The top graph shows the computational “ceilings” of 8 GFLOPs/sec if the floating-point operation mix is imbalanced and 2 GFLOPs/sec if the optimizations to increase ILP and SIMD are also missing. The bottom graph shows the... | clipped_hennesy_Page_670_Chunk6027 |
The computational roofline can be found from the manuals, and the memory roofline can be found from running the stream benchmark. The computational ceilings, such as floating-point balance, also come from the manuals for that com puter. The memory ceiling requires running experiments on each computer to determine the ... | clipped_hennesy_Page_671_Chunk6028 |
674 Chapter 7 Multicores, Multiprocessors, and Clusters The next section uses the roofline model to demonstrate the difference for four recent multicore microprocessors for two real application kernels. While the examples above show how to help programmers improve performance, the model can also be used by architects t... | clipped_hennesy_Page_672_Chunk6029 |
Elaboration: An alternative to the Stream benchmark is to use the raw DRAM bandwidth as the roofline. While the DRAMs definitely set a hard bound, actual memory performance is often so far from that boundary that it’s not that useful as an upper bound. That is, no program can go close to that bound. The downside to usi... | clipped_hennesy_Page_673_Chunk6030 |
676 Chapter 7 Multicores, Multiprocessors, and Clusters Four Multicore Systems Figure 7.17 shows the basic organization of the four systems, and Figure 7.18 lists the key characteristics of the examples of this section. These are all dual socket systems. Figure 7.19 shows the roofline performance model for each system.... | clipped_hennesy_Page_674_Chunk6031 |
The Intel Xeon e5345 (code-named “Clovertown”) contains four cores per socket by packaging two dual core chips into a single socket. These two chips share a front side bus that is attached to a separate north bridge chip set (see Chapter 6). This north bridge chip set supports two front side buses and hence two sockets... | clipped_hennesy_Page_675_Chunk6032 |
678 Chapter 7 Multicores, Multiprocessors, and Clusters FIGURE 7.19 Roofline model for multicore multiprocessors in Figure 7.15. The ceilings are the same as in Figure 7.13. Starting from the upper left hand corner, the computers are: (a) Intel Xeon e5345 (Clovertown), (b) AMD Opteron X4 2356 (Barcelona), (c) Sun Ultra... | clipped_hennesy_Page_676_Chunk6033 |
The IBM Cell QS20 is again different from the two x86 microarchitectures and from UltraSPARC T2. It is a heterogeneous design, with a relatively simple PowerPC core and with eight SPEs (Synergistic Processing Elements) that have their own unique SIMD-style instruction set. Each SPE also has its own local memory instead... | clipped_hennesy_Page_677_Chunk6034 |
680 Chapter 7 Multicores, Multiprocessors, and Clusters y = A × x where A is a sparse matrix and x and y are dense vectors. Fourteen sparse matrices taken from a variety of real applications were used to evaluate SpMV performance, but only the median performance is reported here. The arithmetic intensity varies from ... | clipped_hennesy_Page_678_Chunk6035 |
Each point involves reading and writing about 75 double precision floating- point numbers and about 1300 floating-point operations. Like SpMV, LBMHD tends to get a small fraction of peak performance on uniprocessors because of the complexity of the data structures and the irregularity of memory access patterns. The FLO... | clipped_hennesy_Page_679_Chunk6036 |
682 Chapter 7 Multicores, Multiprocessors, and Clusters ■ ■Loop Unrolling and Reordering: To expose sufficient parallelism and improve cache utilization, the loops were unrolled and then reordered to group state ments with similar addresses. ■ ■“SIMD-ize”: The compilers of the two x86 systems could not generate good S... | clipped_hennesy_Page_680_Chunk6037 |
FIGURE 7.22 Base versus fully optimized performance of the four cores on the two kernels. Note the high fraction of fully optimized performance delivered by the Sun UltraSPARC T2 (Niagara 2). There is no base performance column for the IBM Cell because there is no way to port the code to the SPEs without caches. While... | clipped_hennesy_Page_681_Chunk6038 |
684 Chapter 7 Multicores, Multiprocessors, and Clusters running on the SPE. Hence, there is no base code column for the IBM Cell in Figure 7.22, and you needed to change the program to issue DMA commands to transfer data back and forth between local store and memory. The good news is that DMA played the role of softwar... | clipped_hennesy_Page_682_Chunk6039 |
The supercomputer industry used this metric in marketing, and the fallacy is exacerbated with parallel machines. Not only are marketers using the nearly unattainable peak performance of a uniprocessor node, but also they are then multiplying it by the total number of processors, assuming perfect speed-up! Amdahl’s la... | clipped_hennesy_Page_683_Chunk6040 |
686 Chapter 7 Multicores, Multiprocessors, and Clusters 7.13 Concluding Remarks The dream of building computers by simply aggregating processors has been around since the earliest days of computing. Progress in building and using effec tive and efficient parallel processors, however, has been slow. This rate of progre... | clipped_hennesy_Page_684_Chunk6041 |
path to higher performance for sequential applications. Hence, programmers who need higher performance must parallelize their codes or write new parallel processing programs. ■ ■Multiple processors on the same chip allow a very different speed of commu nication than multiple chip designs, offering both much lower l... | clipped_hennesy_Page_685_Chunk6042 |
688 Chapter 7 Multicores, Multiprocessors, and Clusters 7.14 Historical Perspective and Further Reading This section on the CD gives the rich and often disastrous history of multiproces sors over the last 50 years. 7.15 Exercises Contributed by David Kaeli of Northeastern University Exercise 7.1 First, write down a ... | clipped_hennesy_Page_686_Chunk6043 |
7.2.1 [10] <7.2> Consider the following binary search algorithm (a classic divide and conquer algorithm) that searches for a value X in an sorted N-element array A and returns the index of matched entry: BinarySearch(A[0..N-1], X) { low = 0 high = N - 1 while (low <= high) { mid = (low + high) / 2 if (A[mid] > X) high ... | clipped_hennesy_Page_687_Chunk6044 |
690 Chapter 7 Multicores, Multiprocessors, and Clusters Instructions have the following associated latencies (in cycles): ADD.D L.D S.D DADDIU 4 6 1 2 7.3.1 [10] <7.2> How many cycles does it take for all instructions in a single iteration of the above loop to execute? 7.3.2 [10] <7.2> When an instruction in a later it... | clipped_hennesy_Page_688_Chunk6045 |
else var middle = length(m) / 2 for each x in m up to middle add x to left for each x in m after middle add x to right left = Mergesort(left) right = Mergesort(right) result = Merge(left, right) return result The merge step is carried out by the following code: Merge(left,right) var list result while length(left) > 0 a... | clipped_hennesy_Page_689_Chunk6046 |
692 Chapter 7 Multicores, Multiprocessors, and Clusters 4 large eggs 1 teaspoon vanilla extract 1/2 teaspoon salt 1/4 teaspoon nutmeg 1 1/2 cups flour 1 cup blueberries The recipe for a single cake is as follows: Step 1: Preheat oven to 325°F (160°C). Grease and flour your cake pan. Step 2: In large bowl, beat togethe... | clipped_hennesy_Page_690_Chunk6047 |
for each element i and j with 1 ≤ i ≤ m and 1 ≤ j ≤ p. Now we want to see if we can parallelize the computation of C. Assume that matrices are laid out in memory sequentially as follows: a1,1, a2,1, a3,1, a4,1, …, etc.. 7.6.1 [10] <7.3> Assume that we are going to compute C on both a single core shared memory machine a... | clipped_hennesy_Page_691_Chunk6048 |
694 Chapter 7 Multicores, Multiprocessors, and Clusters In the following proplems, assume that all nodes have the same number of CPUs and the same amount memory (i.e., CPUs and memory are evenly divided between the nodes of the CC-NUMA machine). 7.8.1 [15] <7.3> If we have P CPU in the system, with T nodes in the CC- N... | clipped_hennesy_Page_692_Chunk6049 |
Exercise 7.10 On a CC-NUMA system, the cost of accessing non-local memory can limit our ability to utilize multiprocessing effectively. The following table shows the costs associated with access data in local memory versus non-local memory and the locality of our application expresses as the proportion of access that a... | clipped_hennesy_Page_693_Chunk6050 |
696 Chapter 7 Multicores, Multiprocessors, and Clusters knowledge of all forks. Further, if we impose the policy that philosophers will always request to pick up their left fork before requesting to pick up their right fork, then we can guarantee to avoid deadlock. 7.11.3 [10] <7.4> �We can implement requests to the wa... | clipped_hennesy_Page_694_Chunk6051 |
7.12.2 [10] <7.5> Now assume you have 2 SS CPUs. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards? 7.12.3 [10] <7.5> Assume that you have 1 MT CPU. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards? Exercise... | clipped_hennesy_Page_695_Chunk6052 |
698 Chapter 7 Multicores, Multiprocessors, and Clusters 7.14.2 [20] <7.6> For an 8-wide SIMD machine (i.e., 8 parallel SIMD functional units), write an assembly program in using your own SIMD extensions to MIPS to execute the loop. Compare the number of instructions executed on the SIMD machine to the MIMD machine. Exe... | clipped_hennesy_Page_696_Chunk6053 |
7.17.1 [90] <7.7> Using the “template” SDK sample as a starting point, write a CUDA program to perform the following vector operations: 1) a − b (vector-vector subtraction) 2) a · b (vector dot product) The dot product of two vectors a = [a1, a2, … , an] and b = [b1, b2, … , bn] is defined as: a · b = i = 1 n ai... | clipped_hennesy_Page_697_Chunk6054 |
700 Chapter 7 Multicores, Multiprocessors, and Clusters 7.19.2 [10] <7.8> Compare the resiliency to failure of n-cube to a fully-connected interconnection network. Plot a comparison of reliability as a function of the added number of links for the two topologies. Exercise 7.20 Benchmarking is field of study that invol... | clipped_hennesy_Page_698_Chunk6055 |
7.21.2 [10] <7.9> In terms of storage space, assuming that each element in matrix X is single precision floating point, compute the amount of storage used to store the Matrix above in Yale Sparse Matrix Format. 7.21.3 [15] <7.9> Perform matrix multiplication of Matrix X by Matrix Y shown below. [2, 4, 1, 99, 7, 2] Put ... | clipped_hennesy_Page_699_Chunk6056 |
702 Chapter 7 Multicores, Multiprocessors, and Clusters All three CPUs have the ability to perform integer arithmetic, though CPU B can not perform floating point arithmetic. CPU A and B have an instruction set similar to a MIPS processor. CPU C can only perform floating point add and subtract operations, as well as m... | clipped_hennesy_Page_700_Chunk6057 |
§7.1, page 634: False. Job-level parallelism can help sequential applications and sequential applications can be made to run on parallel hardware, although it is more challenging. §7.2, page 638: False. Weak scaling can compensate for a serial portion of the program that would otherwise limit scalability. §7.3, page 64... | clipped_hennesy_Page_701_Chunk6058 |
A Imagination is more important than knowledge. Albert Einstein On Science, 1930s Graphics and Computing GPUs John Nickolls Director of Architecture NVIDIA David Kirk Chief Scientist NVIDIA A P P E N D I X | clipped_hennesy_Page_702_Chunk6059 |
A.1 Introduction A-3 A.2 GPU System Architectures A-7 A.3 Programming GPUs A-12 A.4 Multithreaded Multiprocessor Architecture A-25 A.5 Parallel Memory System A-36 A.6 Floating-point Arithmetic A-41 A.7 Real Stuff: The NVIDIA GeForce 8800 A-46 A.8 Real Stuff: Mapping Applications to GPUs A-55 A.9 Fallacies and Pitfalls... | clipped_hennesy_Page_703_Chunk6060 |
hardware for triangle setup and rasterization (dicing triangles into individual pixels) and texture mapping and shading (applying “decals” or patterns to pixels and blending colors). In 2000, the single chip graphics processor incorporated almost every detail of the traditional high-end workstation graphics pipeline an... | clipped_hennesy_Page_704_Chunk6061 |
soon to be manycore, is a complementary, primarily serial processor companion to the massively parallel manycore GPU. Together, these two types of processors comprise a heterogeneous multiprocessor system. The best performance for many applications comes from using both the CPU and the GPU. This appendix will help you ... | clipped_hennesy_Page_705_Chunk6062 |
GPU Unifies Graphics and Computing With the addition of CUDA and GPU computing to the capabilities of the GPU, it is now possible to use the GPU as both a graphics processor and a computing processor at the same time, and to combine these uses in visual computing applications. The underlying processor architecture of t... | clipped_hennesy_Page_706_Chunk6063 |
that is desired. So, all applications are now possible, which will stimulate new visual computing approaches. A.2 GPU System Architectures In this section, we survey GPU system architectures in common use today. We discuss system configurations, GPU functions and services, standard programming interfaces, and a basic G... | clipped_hennesy_Page_707_Chunk6064 |
A-8 Appendix A Graphics and Computing GPUs as a VGA (video graphics array) which was attached to the PCI bus. Graphics subsystems with built-in processing elements (GPUs) did not exist in the PC landscape of 1990. Figure A.2.2 illustrates two configurations in common use today. These are characterized by a separate GPU... | clipped_hennesy_Page_708_Chunk6065 |
is attached to the chipset, also via PCI-Express with the same available bandwidth. In both cases, the GPUs and CPUs may access each other’s memory, albeit with less available bandwidth than their access to the more directly attached memories. In the case of the AMD system, the north bridge or memory controller is inte... | clipped_hennesy_Page_709_Chunk6066 |
A-10 Appendix A Graphics and Computing GPUs Graphics Logical Pipeline The graphics logical pipeline is described in Section A.3. Figure A.2.3 illustrates the major processing stages, and highlights the important programmable stages (vertex, geometry, and pixel shader stages). FIGURE A.2.3 Graphics logical pipeline. Pro... | clipped_hennesy_Page_710_Chunk6067 |
processor cores. By using many simpler cores and optimizing for data-parallel behavior among groups of threads, more of the per-chip transistor budget is devoted to computation, and less to on-chip caches and overhead. Processor Array A unified GPU processor array contains many processor cores, typically organized into... | clipped_hennesy_Page_711_Chunk6068 |
A-12 Appendix A Graphics and Computing GPUs The processor array architecture is scalable to smaller and larger GPU configu rations by scaling the number of multiprocessors and the number of memory partitions. Figure A.2.5 shows seven clusters of two SMs sharing a texture unit and a texture L1 cache. The texture unit d... | clipped_hennesy_Page_712_Chunk6069 |
vertex or one pixel. It has remained an effective paradigm as GPUs have rapidly increased their parallelism and performance since the late 1990s. This section briefly describes programming GPUs for real-time graphics applications using graphics APIs and programming languages. It then describes programming GPUs for visu... | clipped_hennesy_Page_713_Chunk6070 |
A-14 Appendix A Graphics and Computing GPUs including transforming the vertex 3D position into a screen position and lighting the vertex to determine its color. The geometry shader program executes per-primitive processing and can add or drop primitives. The setup and rasterizer unit generates pixel fragments (fragment... | clipped_hennesy_Page_714_Chunk6071 |
access, pointers, file I/O, and recursion. HLSL and Cg assume that programs live within a logical graphics pipeline, and thus I/O is implicit. For example, a pixel fragment shader may expect the geometric normal and multiple texture coordinates to have been interpolated from vertex values by upstream fixed-function sta... | clipped_hennesy_Page_715_Chunk6072 |
A-16 Appendix A Graphics and Computing GPUs Although this shader program is only three lines long, it activates a lot of GPU hardware. For each texture fetch, the GPU texture subsystem makes multiple memory accesses to sample image colors in the vicinity of the sampling coordinates, and then interpolates the final resu... | clipped_hennesy_Page_716_Chunk6073 |
The compiled Cg shader executes 1400 instructions to compute the color of one skin pixel. As GPUs have evolved superior floating-point performance and very high streaming memory bandwidth for real-time graphics, they have attracted highly parallel applications beyond traditional graphics. At first, access to this power... | clipped_hennesy_Page_717_Chunk6074 |
A-18 Appendix A Graphics and Computing GPUs that many sophisticated programs can be readily expressed with a few easily understood abstractions. Since NVIDIA released CUDA in 2007, developers have rapidly developed scalable parallel programs for a wide range of applications, including seismic data processing, computati... | clipped_hennesy_Page_718_Chunk6075 |
A.3 Programming GPUs A-19 The CUDA Paradigm CUDA is a minimal extension of the C and C++ programming languages. The programmer writes a serial program that calls parallel kernels, which may be simple functions or full programs. A kernel executes in parallel across a set of parallel threads. The programmer organizes the... | clipped_hennesy_Page_719_Chunk6076 |
A-20 Appendix A Graphics and Computing GPUs Parallel execution and thread management is automatic. All thread creation, scheduling, and termination is handled for the programmer by the underlying sys- tem. Indeed, a Tesla architecture GPU performs all thread management directly in hardware. The threads of a block execu... | clipped_hennesy_Page_720_Chunk6077 |
into threads and thread blocks allows intuitive problem decompositions, as the number of blocks can be dictated by the size of the data being processed rather than by the number of processors in the system. It also allows the same CUDA program to scale to widely varying numbers of processor cores. To manage this proce... | clipped_hennesy_Page_721_Chunk6078 |
A-22 Appendix A Graphics and Computing GPUs The CUDA programming model is similar in style to the familiar single-program multiple data (SPMD) model—it expresses parallelism explicitly, and each kernel executes on a fixed number of threads. However, CUDA is more flexible than most realizations of SPMD, because each ke... | clipped_hennesy_Page_722_Chunk6079 |
coarse-grained data parallelism. Independent grids express coarse-grained task parallelism. A kernel is simply C code for one thread of the hierarchy. Restrictions For efficiency, and to simplify its implementation, the CUDA programming model has some restrictions. Threads and thread blocks may only be created by invok... | clipped_hennesy_Page_723_Chunk6080 |
A-24 Appendix A Graphics and Computing GPUs with a simple scheduler that introduces minimal runtime overhead. In fact, the Tesla GPU architecture implements hardware management and scheduling of threads and thread blocks. Task parallelism can be expressed at the thread block level but is difficult to express within a t... | clipped_hennesy_Page_724_Chunk6081 |
A.4 Multithreaded Multiprocessor Architecture To address different market segments, GPUs implement scalable numbers of multiprocessors—in fact, GPUs are multiprocessors composed of multiprocessors. Furthermore, each multiprocessor is highly multithreaded to execute many fine- grained vertex and pixel shader threads e... | clipped_hennesy_Page_725_Chunk6082 |
A-26 Appendix A Graphics and Computing GPUs A graphics vertex or pixel shader program is a program for a single thread that processes a vertex or a pixel. Similarly, a CUDA program is a C program for a single thread that computes a result. Graphics and computing programs instantiate many parallel threads to render comp... | clipped_hennesy_Page_726_Chunk6083 |
The pipelined SFUs execute thread instructions that compute special functions and interpolate pixel attributes from primitive vertex attributes. These instructions can execute concurrently with instructions on the SPs. The SFU is described later. The multiprocessor executes texture fetch instructions on the texture uni... | clipped_hennesy_Page_727_Chunk6084 |
A-28 Appendix A Graphics and Computing GPUs SP cores over four clocks. The Tesla SM multiprocessor described in Section A.7 also uses a warp size of 32 parallel threads, executing four threads per SP core for efficiency on plentiful pixel threads and computing threads. Thread blocks consist of one or more warps. This e... | clipped_hennesy_Page_728_Chunk6085 |
to multiple data lanes. An instruction for a SIMD processor controls a vector of multiple data lanes together, whereas an instruction for a SIMT processor controls an individual thread, and the SIMT instruction unit issues an instruction to a warp of independent parallel threads for efficiency. The SIMT processor finds... | clipped_hennesy_Page_729_Chunk6086 |
programmer can ignore the pipeline latency. For this multiprocessor, a round-robin schedule of eight warps has a period of 32 cycles between successive instructions for the same warp. If the program can keep 256 threads active per multiprocessor, instruction latencies up to 32 cycles can be hidden from an individual se... | clipped_hennesy_Page_730_Chunk6087 |
generally compute (x, y, z, w) position vectors, while pixel shader programs compute (red, green, blue, alpha) color vectors. However, shader programs are becoming longer and more scalar, and it is increasingly difficult to fully occupy even two components of a legacy GPU four-component vector architecture. In effect, ... | clipped_hennesy_Page_731_Chunk6088 |
A-32 Appendix A Graphics and Computing GPUs Basic PTX GPU Thread Instructions Group Instruction Example Meaning Comments Arithmetic arithmetic .type = .s32, .u32, .f32, .s64, .u64, .f64 add.type add.f32 d, a, b d = a + b; sub.type sub.f32 d, a, b d = a – b; mul.type mul.f32 d, a, b d = a * b; mad.type mad.f32 d, a, b, ... | clipped_hennesy_Page_732_Chunk6089 |
Source operands are scalar 32-bit or 64-bit values in registers, an immediate value, or a constant; predicate operands are 1-bit Boolean values. Destinations are registers, except for store to memory. Instructions are predicated by prefixing them with @p or @!p, where p is a predicate register. Memory and texture instr... | clipped_hennesy_Page_733_Chunk6090 |
A-34 Appendix A Graphics and Computing GPUs To improve memory bandwidth and reduce overhead, the local and global load/ store instructions coalesce individual parallel thread requests from the same SIMT warp together into a single memory block request when the addresses fall in the same block and meet alignment criteri... | clipped_hennesy_Page_734_Chunk6091 |
Special Function Unit (SFU) Certain thread instructions can execute on the SFUs, concurrently with other thread instructions executing on the SPs. The SFU implements the special function instructions of Figure A.4.3, which compute 32-bit floating-point approximations to reciprocal, reciprocal square root, and key trans... | clipped_hennesy_Page_735_Chunk6092 |
Coupling eight streaming processor cores together closely into a multiprocessor and then implementing a scalable number of such multiprocessors makes a two- level multiprocessor composed of multiprocessors. The CUDA programming model exploits the two-level hierarchy by providing individual threads for fine-grained para... | clipped_hennesy_Page_736_Chunk6093 |
To supply these requirements, GPU memory systems have the following characteristics: ■ ■They are wide, meaning there are a large number of pins to convey data between the GPU and its memory devices, and the memory array itself comprises many DRAM chips to provide the full total data bus width. ■ ■They are fast, meaning... | clipped_hennesy_Page_737_Chunk6094 |
different DRAM banks, and wait until enough traffic for a particular DRAM row is pending before activating that row and transferring all the traffic at once. Note that accumulating pending requests, while good for DRAM row locality and thus efficient use of the data bus, leads to longer average latency as seen by the r... | clipped_hennesy_Page_738_Chunk6095 |
translation; hardware reads the page tables from local memory to respond to misses on behalf of a hierarchy of translation lookaside buffers spread out among the processors and rendering engines. In addition to physical page bits, GPU page table entries specify the compression algorithm for each page. Page sizes range ... | clipped_hennesy_Page_739_Chunk6096 |
A-40 Appendix A Graphics and Computing GPUs Each streaming multiprocessor contains eight physical thread processors. During one shared memory clock cycle, each thread processor can process two threads’ worth of instructions, so 16 threads’ worth of shared memory requests must be handled in each clock. Because each thre... | clipped_hennesy_Page_740_Chunk6097 |
Surfaces Surface is a generic term for a one-dimensional, two-dimensional, or three- dimensional array of pixel values and an associated format. A variety of formats are defined; for example, a pixel may be defined as four 8-bit RGBA integer components, or four 16-bit floating-point components. A program kernel does no... | clipped_hennesy_Page_741_Chunk6098 |
Some fixed-function logic within a GPU, such as texture-filtering hardware, continues to use proprietary numeric formats. Recent GPUs also provide IEEE 754 compatible double precision 64-bit floating-point instructions. Supported Formats The IEEE 754 standard for floating-point arithmetic [2008] specifies basic and st... | clipped_hennesy_Page_742_Chunk6099 |
sine, binary exponential, binary logarithm, reciprocal, and reciprocal square root. Attribute interpolation instructions provide efficient generation of pixel attributes, derived from plane equation evaluation. The special function unit (SFU) introduced in Section A.4 computes special functions and interpolates planar ... | clipped_hennesy_Page_743_Chunk6100 |
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