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instruction performs the operation above, assuming that the original value was in register $s0 and the result should go in register $t2: sll $t2,$s0,4 # reg $t2 = reg $s0 << 4 bits We delayed explaining the shamt field in the R-format. Used in shift instructions, it stands for shift amount. Hence, the machine language... | Hennesey_Page_101_Chunk101 |
104 Chapter 2 Instructions: Language of the Computer As you can see, AND can apply a bit pattern to a set of bits to force 0s where there is a 0 in the bit pattern. Such a bit pattern in conjunction with AND is traditionally called a mask, since the mask “conceals” some bits. To place a value into one of these seas of... | Hennesey_Page_102_Chunk102 |
packed within a word and to match an externally enforced interface such as an I/O device. All fields must fit within a single word. Fields are unsigned integers that can be as short as 1 bit. C compilers insert and extract fields using logical instructions in MIPS: and, or, sll, and srl. Which operations can isolate a ... | Hennesey_Page_103_Chunk103 |
106 Chapter 2 Instructions: Language of the Computer Compiling if-then-else into Conditional Branches In the following code segment, f, g, h, i, and j are variables. If the five vari ables f through j correspond to the five registers $s0 through $s4, what is the compiled MIPS code for this C if statement? if (i == j) ... | Hennesey_Page_104_Chunk104 |
Notice that the assembler relieves the compiler and the assembly language pro grammer from the tedium of calculating addresses for branches, just as it does for calculating data addresses for loads and stores (see Section 2.12). Compilers frequently create branches and labels where they do not appear in the programmin... | Hennesey_Page_105_Chunk105 |
108 Chapter 2 Instructions: Language of the Computer The first step is to load save[i] into a temporary register. Before we can load save[i] into a temporary register, we need to have its address. Before we can add i to the base of array save to form the address, we must multiply the index i by 4 due to the byte addres... | Hennesey_Page_106_Chunk106 |
registers and sets a third register to 1 if the first is less than the second; otherwise, it is set to 0. The MIPS instruction is called set on less than, or slt. For example, slt $t0, $s3, $s4 # $t0 = 1 if $s3 < $s4 means that register $t0 is set to 1 if the value in register $s3 is less than the value in register $s4... | Hennesey_Page_107_Chunk107 |
110 Chapter 2 Instructions: Language of the Computer Signed versus Unsigned Comparison Suppose register $s0 has the binary number 1111 1111 1111 1111 1111 1111 1111 1111two and that register $s1 has the binary number 0000 0000 0000 0000 0000 0000 0000 0001two What are the values of registers $t0 and $t1 after these two... | Hennesey_Page_108_Chunk108 |
Case/Switch Statement Most programming languages have a case or switch statement that allows the pro grammer to select one of many alternatives depending on a single value. The simplest way to implement switch is via a sequence of conditional tests, turning the switch statement into a chain of if-then-else statement... | Hennesey_Page_109_Chunk109 |
112 Chapter 2 Instructions: Language of the Computer II. Why does C provide two sets of operators for AND (& and &&) and two sets of operators for OR (| and ||), while MIPS doesn’t? 1. Logical operations AND and OR implement & and |, while conditional branches implement && and ||. 2. The previous statement has it backw... | Hennesey_Page_110_Chunk110 |
As mentioned above, registers are the fastest place to hold data in a computer, so we want to use them as much as possible. MIPS software follows the following convention for procedure calling in allocating its 32 registers: ■ ■$a0-$a3: four argument registers in which to pass parameters ■ ■$v0-$v1: two value registers... | Hennesey_Page_111_Chunk111 |
114 Chapter 2 Instructions: Language of the Computer Using More Registers Suppose a compiler needs more registers for a procedure than the four argument and two return value registers. Since we must cover our tracks after our mission is complete, any registers needed by the caller must be restored to the values that th... | Hennesey_Page_112_Chunk112 |
The next step is to save the registers used by the procedure. The C assignment statement in the procedure body is identical to the example on page 79, which uses two temporary registers. Thus, we need to save three registers: $s0, $t0, and $t1. We “push” the old values onto the stack by creating space for three words ... | Hennesey_Page_113_Chunk113 |
116 Chapter 2 Instructions: Language of the Computer we can drop two stores and two loads from the code. We still must save and restore $s0, since the callee must assume that the caller needs its value. FIGURE 2.10 The values of the stack pointer and the stack (a) before, (b) during, and (c) after the procedure call. T... | Hennesey_Page_114_Chunk114 |
Compiling a Recursive C Procedure, Showing Nested Procedure Linking Let’s tackle a recursive procedure that calculates factorial: int fact (int n) { if (n < 1) return (1); else return (n * fact(n – 1)); } What is the MIPS assembly code? The parameter variable n corresponds to the argument register $a0. The compiled pr... | Hennesey_Page_115_Chunk115 |
118 Chapter 2 Instructions: Language of the Computer The next instruction is where fact returns. Now the old return address and old argument are restored, along with the stack pointer: lw $a0, 0($sp) # return from jal: restore argument n lw $ra, 4($sp) # restore the return address addi $sp, $sp, 8 # adjust stack pointe... | Hennesey_Page_116_Chunk116 |
Allocating Space for New Data on the Stack The final complexity is that the stack is also used to store variables that are local to the procedure but do not fit in registers, such as local arrays or structures. The segment of the stack containing a procedure’s saved registers and local variables is called a procedure f... | Hennesey_Page_117_Chunk117 |
120 Chapter 2 Instructions: Language of the Computer Allocating Space for New Data on the Heap In addition to automatic variables that are local to procedures, C programmers need space in memory for static variables and for dynamic data structures. Figure 2.13 shows the MIPS convention for allocation of memory. The st... | Hennesey_Page_118_Chunk118 |
Figure 2.14 summarizes the register conventions for the MIPS assembly language. Name Register number Usage Preserved on call? $zero 0 The constant value 0 n.a. $v0–$v1 2–3 Values for results and expression evaluation no $a0–$a3 4–7 Arguments no $t0–$t7 8–15 Temporaries no $s0–$s7 16–23 Saved yes $t8–$t9 24–25 More tem... | Hennesey_Page_119_Chunk119 |
122 Chapter 2 Instructions: Language of the Computer addi$a0, $a0, –1 # subtract 1 from n j sum # go to sum sum_exit: add$v0, $a1, $zero # return value acc jr $ra # return to caller Which of the following statements about C and Java are generally true? 1. C programmers manage data explicitly, while it’s automatic in Ja... | Hennesey_Page_120_Chunk120 |
Base 2 is not natural to human beings; we have 10 fingers and so find base 10 natural. Why didn’t computers use decimal? In fact, the first commercial computer did offer decimal arithmetic. The problem was that the computer still used on and off signals, so a decimal digit was simply represented by several binary digit... | Hennesey_Page_121_Chunk121 |
124 Chapter 2 Instructions: Language of the Computer Signed versus unsigned applies to loads as well as to arithmetic. The function of a signed load is to copy the sign repeatedly to fill the rest of the register—called sign extension—but its purpose is to place a correct representation of the number within that regist... | Hennesey_Page_122_Chunk122 |
Below is the basic MIPS assembly code segment. Assume that base addresses for arrays x and y are found in $a0 and $a1, while i is in $s0. strcpy adjusts the stack pointer and then saves the saved register $s0 on the stack: strcpy: addi $sp,$sp,–4 # adjust stack for 1 more item sw $s0, 0($sp) # save $s0 To initialize i ... | Hennesey_Page_123_Chunk123 |
126 Chapter 2 Instructions: Language of the Computer If we don’t loop back, it was the last character of the string; we restore $s0 and the stack pointer, and then return. L2: lw $s0, 0($sp) # y[i] == 0: end of string. Re store old $s0 addi $sp,$sp,4 # pop 1 word off stack jr $ra # return String copies usually use poi... | Hennesey_Page_124_Chunk124 |
Latin Malayalam Tagbanwa General Punctuation Greek Sinhala Khmer Spacing Modifier Letters Cyrillic Thai Mongolian Currency Symbols Armenian Lao Limbu Combining Diacritical Marks Hebrew Tibetan Tai Le Combining Marks for Symbols Arabic Myanmar Kangxi Radicals Superscripts and Subscripts Syriac Georgian Hiragana Number F... | Hennesey_Page_125_Chunk125 |
128 Chapter 2 Instructions: Language of the Computer 2.10 MIPS Addressing for 32-Bit Immediates and Addresses Although keeping all MIPS instructions 32 bits long simplifies the hardware, there are times where it would be convenient to have a 32-bit constant or 32-bit address. This section starts with the general solut... | Hennesey_Page_126_Chunk126 |
The machine language version of lui $t0, 255 # $t0 is register 8: 001111 00000 01000 0000 0000 1111 1111 Contents of register $t0 after executing lui $t0, 255: 0000 0000 1111 1111 0000 0000 0000 0000 FIGURE 2.17 The effect of the lui instruction. The instruction lui transfers the 16-bit immediate constant field value i... | Hennesey_Page_127_Chunk127 |
130 Chapter 2 Instructions: Language of the Computer 2 10000 6 bits 26 bits where the value of the jump opcode is 2 and the jump address is 10000. Unlike the jump instruction, the conditional branch instruction must specify two operands in addition to the branch address. Thus, bne $s0,$s1,Exit # go to Exit if $s0 ≠ $s1... | Hennesey_Page_128_Chunk128 |
times as far by interpreting the field as a relative word address rather than as a relative byte address. Similarly, the 26-bit field in jump instructions is also a word address, meaning that it represents a 28-bit byte address. Elaboration: Since the PC is 32 bits, 4 bits must come from somewhere else for jumps. The ... | Hennesey_Page_129_Chunk129 |
132 Chapter 2 Instructions: Language of the Computer Remember that MIPS instructions have byte addresses, so addresses of sequential words differ by 4, the number of bytes in a word. The bne instruc tion on the fourth line adds 2 words or 8 bytes to the address of the following instruction (80016), specifying the bra... | Hennesey_Page_130_Chunk130 |
3. Base or displacement addressing, where the operand is at the memory loca tion whose address is the sum of a register and a constant in the instruction 4. PC-relative addressing, where the branch address is the sum of the PC and a constant in the instruction 5. Pseudodirect addressing, where the jump address is the... | Hennesey_Page_131_Chunk131 |
134 Chapter 2 Instructions: Language of the Computer Although we show MIPS as having 32-bit addresses, nearly all microprocessors (including MIPS) have 64-bit address extensions (see Appendix E). These exten sions were in response to the needs of software for larger programs. The process of instruction set extension a... | Hennesey_Page_132_Chunk132 |
op(31:26) 28–26 31–29 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111) 0(000) Rformat Bltz/gez jump jump & link branch eq branch ne blez bgtz 1(001) add immediate addiu set less than imm. set less than imm. unsigned andi ori xori load upper immediate 2(010) TLB FlPt 3(011) 4(100) load byte load half lwl load wo... | Hennesey_Page_133_Chunk133 |
136 Chapter 2 Instructions: Language of the Computer Figure 2.20 shows all the MIPS instruction formats. Figure 2.1 on page 78 shows the MIPS assembly language revealed in this chapter. The remaining hidden portion of MIPS instructions deals mainly with arithmetic and real numbers, which are covered in the next chapte... | Hennesey_Page_134_Chunk134 |
2.11 Parallelism and Instructions: Synchronization Parallel execution is easier when tasks are independent, but often they need to cooperate. Cooperation usually means some tasks are writing new values that others must read. To know when a task is finished writing so that it is safe for another to read, the tasks need... | Hennesey_Page_135_Chunk135 |
138 Chapter 2 Instructions: Language of the Computer some other processor had already claimed access and 0 otherwise. In the latter case, the value is also changed to 1, preventing any competing exchange in another processor from also retrieving a 0. For example, consider two processors that each try to do the exchange... | Hennesey_Page_136_Chunk136 |
conditional also fails if the processor does a context switch between the two instructions (see Chapter 5). Since the store conditional will fail after either another attempted store to the load linked address or any exception, care must be taken in choosing which instructions are inserted between the two instructions.... | Hennesey_Page_137_Chunk137 |
140 Chapter 2 Instructions: Language of the Computer Assembler Since assembly language is an interface to higher-level software, the assembler can also treat common variations of machine language instructions as if they were instructions in their own right. The hardware need not implement these instructions; however, t... | Hennesey_Page_138_Chunk138 |
to create the assembly language instruction move that copies the contents of one register to another. Thus the MIPS assembler accepts this instruction even though it is not found in the MIPS architecture: move $t0,$t1 # register $t0 gets register $t1 The assembler converts this assembly language instruction into the ma... | Hennesey_Page_139_Chunk139 |
142 Chapter 2 Instructions: Language of the Computer ■ ■The symbol table contains the remaining labels that are not defined, such as external references. ■ ■The debugging information contains a concise description of how the mod ules were compiled so that a debugger can associate machine instructions with C source fil... | Hennesey_Page_140_Chunk140 |
Linking Object Files Link the two object files below. Show updated addresses of the first few instructions of the completed executable file. We show the instructions in assembly language just to make the example understandable; in reality, the instructions would be numbers. Note that in the object files we have highl... | Hennesey_Page_141_Chunk141 |
144 Chapter 2 Instructions: Language of the Computer Procedure A needs to find the address for the variable labeled X to put in the load instruction and to find the address of procedure B to place in the jal instruction. Procedure B needs the address of the variable labeled Y for the store instruction and the address ... | Hennesey_Page_142_Chunk142 |
1. The jals are easy because they use pseudodirect addressing. The jal at address 40 0004hex gets 40 0100hex (the address of procedure B) in its address field, and the jal at 40 0104hex gets 40 0000hex (the address of procedure A) in its address field. 2. The load and store addresses are harder because they are relativ... | Hennesey_Page_143_Chunk143 |
146 Chapter 2 Instructions: Language of the Computer ■ ■The library routines become part of the executable code. If a new version of the library is released that fixes bugs or supports new hardware devices, the statically linked program keeps using the old version. ■ ■It loads all routines in the library that are calle... | Hennesey_Page_144_Chunk144 |
FIGURE 2.22 Dynamically linked library via lazy procedure linkage. (a) Steps for the first time a call is made to the DLL routine. (b) The steps to find the routine, remap it, and link it are skipped on subsequent calls. As we will see in Chapter 5, the operating system may avoid copying the desired routine by remappin... | Hennesey_Page_145_Chunk145 |
148 Chapter 2 Instructions: Language of the Computer The upside of interpretation is portability. The availability of software Java vir tual machines meant that most people could write and run Java programs shortly after Java was announced. Today, Java virtual machines are found in hundreds of millions of devices, in ... | Hennesey_Page_146_Chunk146 |
2.13 A C Sort Example to Put It All Together One danger of showing assembly language code in snippets is that you will have no idea what a full assembly language program looks like. In this section, we derive the MIPS code from two procedures written in C: one to swap array elements and one to sort them. The Procedure... | Hennesey_Page_147_Chunk147 |
150 Chapter 2 Instructions: Language of the Computer This register allocation corresponds to the variable declarations in the first part of the swap procedure in Figure 2.24. Code for the Body of the Procedure swap The remaining lines of C code in swap are temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; Recall that the memo... | Hennesey_Page_148_Chunk148 |
version of the program. Once again, we present this procedure in several steps, concluding with the full procedure. Register Allocation for sort The two parameters of the procedure sort, v and n, are in the parameter registers $a0 and $a1, and we assign register $s0 to i and register $s1 to j. Code for the Body of the... | Hennesey_Page_149_Chunk149 |
152 Chapter 2 Instructions: Language of the Computer (Remember that move is a pseudoinstruction provided by the assembler for the convenience of the assembly language programmer; see page 141.) It also takes just one instruction to increment i, the last part of the for statement: addi $s0, $s0, 1 # i += 1 The loop shou... | Hennesey_Page_150_Chunk150 |
The second test exits if v[j] > v[j + 1] is not true, or exits if v[j] ≤ v[j + 1]. First we create the address by multiplying j by 4 (since we need a byte address) and add it to the base address of v: sll $t1, $s1, 2 # reg $t1 = j * 4 add $t2, $a0, $t1 # reg $t2 = v + (j * 4) Now we load v[j]: lw $t3, 0($t2) # reg $t3 ... | Hennesey_Page_151_Chunk151 |
154 Chapter 2 Instructions: Language of the Computer Passing Parameters in sort The problem comes when we want to pass parameters because the sort procedure needs the values in registers $a0 and $a1, yet the swap procedure needs to have its parameters placed in those same registers. One solution is to copy the paramet... | Hennesey_Page_152_Chunk152 |
Saving registers sort: addi $sp,$sp, –20 # make room on stack for 5 registers sw $ra, 16($sp)# save $ra on stack sw $s3,12($sp) # save $s3 on stack sw $s2, 8($sp)# save $s2 on stack sw $s1, 4($sp)# save $s1 on stack sw $s0, 0($sp)# save $s0 on stack Procedure body Move parameters move $s2, $a0 # copy parameter $a0 into... | Hennesey_Page_153_Chunk153 |
156 Chapter 2 Instructions: Language of the Computer Figure 2.28 shows the impact of compiler optimization on sort program perfor mance, compile time, clock cycles, instruction count, and CPI. Note that unopti mized code has the best CPI, and O1 optimization has the lowest instruction count, but O3 is the fastest, re... | Hennesey_Page_154_Chunk154 |
2.14 Arrays versus Pointers A challenge for any new C programmer is understanding pointers. Comparing assembly code that uses arrays and array indices to the assembly code that uses pointers offers insights about pointers. This section shows C and MIPS assembly versions of two procedures to clear a sequence of words in... | Hennesey_Page_155_Chunk155 |
158 Chapter 2 Instructions: Language of the Computer sw $zero, 0($t2) # array[i] = 0 This instruction is the end of the body of the loop, so the next step is to increment i: addi $t0,$t0,1 # i = i + 1 The loop test checks if i is less than size: slt $t3,$t0,$a1 # $t3 = (i < size) bne $t3,$zero,loop1 # if (i < size) go ... | Hennesey_Page_156_Chunk156 |
Pointer Version of Clear The second procedure that uses pointers allocates the two parameters array and size to the registers $a0 and $a1 and allocates p to register $t0. The code for the second procedure starts with assigning the pointer p to the address of the first element of the array: move $t0,$a0 # p = address of... | Hennesey_Page_157_Chunk157 |
160 Chapter 2 Instructions: Language of the Computer Note that this program calculates the address of the end of the array in every iteration of the loop, even though it does not change. A faster version of the code moves this calculation outside the loop: move $t0,$a0 # p = address of array[0] sll $t1,$a1,2 # $t1 = si... | Hennesey_Page_158_Chunk158 |
People used to be taught to use pointers in C to get greater efficiency than that available with arrays: “Use pointers, even if you can’t understand the code.” Mod ern optimizing compilers can produce code for the array version that is just as good. Most programmers today prefer that the compiler do the heavy lifting.... | Hennesey_Page_159_Chunk159 |
162 Chapter 2 Instructions: Language of the Computer ARM MIPS Date announced 1985 1985 Instruction size (bits) 32 32 Address space (size, model) 32 bits, flat 32 bits, flat Data alignment Aligned Aligned Data addressing modes 9 3 Integer registers (number, model, size) 15 GPR ´ 32 bits 31 GPR ´ 32 bits I/O Memory mappe... | Hennesey_Page_160_Chunk160 |
by any amount, add it to the other registers to form the address, and then update one register with this new address. Compare and Conditional Branch MIPS uses the contents of registers to evaluate conditional branches. ARM uses the traditional four condition code bits stored in the program status word: negative, zero,... | Hennesey_Page_161_Chunk161 |
164 Chapter 2 Instructions: Language of the Computer Unique Features of ARM Figure 2.35 shows a few arithmetic-logical instructions not found in MIPS. Since it does not have a dedicated register for 0, it has separate opcodes to perform some operations that MIPS can do with $zero. In addition, ARM has support for multi... | Hennesey_Page_162_Chunk162 |
ARM also has instructions to save groups of registers, called block loads and stores. Under control of a 16-bit mask within the instructions, any of the 16 regis ters can be loaded or stored into memory in a single instruction. These instructions can save and restore registers on procedure entry and return. These ins... | Hennesey_Page_163_Chunk163 |
166 Chapter 2 Instructions: Language of the Computer ■ ■1978: The Intel 8086 architecture was announced as an assembly language– compatible extension of the then successful Intel 8080, an 8-bit microproces sor. The 8086 is a 16-bit architecture, with all internal registers 16 bits wide. Unlike MIPS, the registers hav... | Hennesey_Page_164_Chunk164 |
versions of existing MMX and SSE instructions that operate on 64 bits of data in parallel. Not only does this change enable more multimedia opera tions, it gives the compiler a different target for floating-point operations than the unique stack architecture. Compilers can choose to use the eight SSE registers as floa... | Hennesey_Page_165_Chunk165 |
168 Chapter 2 Instructions: Language of the Computer This history illustrates the impact of the “golden handcuffs” of compatibility on the x86, as the existing software base at each step was too important to jeopardize with significant architectural changes. If you looked over the life of the x86, on average the archi... | Hennesey_Page_166_Chunk166 |
Source/destination operand type Second source operand Register Register Register Immediate Register Memory Memory Register Memory Immediate FIGURE 2.37 Instruction types for the arithmetic, logical, and data transfer instructions. The x86 allows the combinations shown. The only restriction is the absence of a memory-m... | Hennesey_Page_167_Chunk167 |
170 Chapter 2 Instructions: Language of the Computer Mode Description Register restrictions MIPS equivalent Register indirect Address is in a register. Not ESP or EBP lw $s0,0($s1) Based mode with 8- or 32-bit displacement Address is contents of base register plus displacement. Not ESP lw $s0,100($s1) # <= 16bit # dis... | Hennesey_Page_168_Chunk168 |
The first two categories are unremarkable, except that the arithmetic and logic instruction operations allow the destination to be either a register or a memory location. Figure 2.39 shows some typical x86 instructions and their functions. Instruction Function je name if equal(condition code) {EIP=name}; EIP–128 <= nam... | Hennesey_Page_169_Chunk169 |
172 Chapter 2 Instructions: Language of the Computer Instruction Meaning Control Conditional and unconditional branches jnz, jz Jump if condition to EIP + 8-bit offset; JNE (for JNZ), JE (for JZ) are alternative names jmp Unconditional jump—8-bit or 16-bit offset call Subroutine call—16-bit offset; return address pushe... | Hennesey_Page_170_Chunk170 |
FIGURE 2.41 Typical x86 instruction formats. Figure 2.42 shows the encoding of the postbyte. Many instructions contain the 1-bit field w, which says whether the operation is a byte or a double word. The d field in MOV is used in instructions that may move to or from memory and shows the direction of the move. The ADD i... | Hennesey_Page_171_Chunk171 |
174 Chapter 2 Instructions: Language of the Computer 2.18 Fallacies and Pitfalls Fallacy: More powerful instructions mean higher performance. Part of the power of the Intel x86 is the prefixes that can modify the execution of the following instruction. One prefix can repeat the following instruction until a counter cou... | Hennesey_Page_172_Chunk172 |
This battle between compilers and assembly language coders is one situation in which humans are losing ground. For example, C offers the programmer a chance to give a hint to the compiler about which variables to keep in registers versus spilled to memory. When compilers were poor at register allocation, such hints w... | Hennesey_Page_173_Chunk173 |
176 Chapter 2 Instructions: Language of the Computer 2.19 Concluding Remarks The two principles of the stored-program computer are the use of instructions that are indistinguishable from numbers and the use of alterable memory for programs. These principles allow a single machine to aid environmental scientists, financ... | Hennesey_Page_174_Chunk174 |
3. Make the common case fast. Examples of making the common MIPS case fast include PC-relative addressing for conditional branches and immediate addressing for larger constant operands. 4. Good design demands good compromises. One MIPS example was the com promise between providing for larger addresses and constants in... | Hennesey_Page_175_Chunk175 |
178 Chapter 2 Instructions: Language of the Computer MIPS instructions Name Format Pseudo MIPS Name Format add add R move move R subtract sub R multiply mult R add immediate addi I multiply immediate multi I load word lw I load immediate li I store word sw I branch less than blt I load half lh I branch less than or equ... | Hennesey_Page_176_Chunk176 |
Instruction class MIPS examples HLL correspondence Frequency Integer Ft. pt. Arithmetic add, sub, addi Operations in assignment statements 16% 48% Data transfer lw, sw, lb, lbu, lh, lhu, sb, lui References to data structures, such as arrays 35% 36% Logical and, or, nor, andi, ori, sll, srl 0perations in assignment stat... | Hennesey_Page_177_Chunk177 |
180 Chapter 2 Instructions: Language of the Computer they are quite convenient and result in more readable code (for example, the li and move instructions). If you choose to use pseudoinstructions for these reasons, please add a sentence or two to your solution stating which pseudoinstructions you have used and why. Ex... | Hennesey_Page_178_Chunk178 |
a. f = g – f; b. f = i + (h – 2); 2.2.1 [5] <2.2> For the C statements above, what is the corresponding MIPS assembly code? Use a minimal number of MIPS assembly instructions. 2.2.2 [5] <2.2> For the C statements above, how many MIPS assembly instruc- tions are needed to perform the C statement? 2.2.3 [5] <2.2> If the ... | Hennesey_Page_179_Chunk179 |
182 Chapter 2 Instructions: Language of the Computer The following problems deal with translating from MIPS to C. Assume that the variables g, h, i, and j are given and could be considered 32-bit integers as declared in a C program. a. addi f, f, –4 b. add i, g, h add f, i, f 2.3.4 [5] <2.2> For the MIPS statements abo... | Hennesey_Page_180_Chunk180 |
2.4.4 [10] <2.2, 2.3> For the MIPS assembly instructions above, what is the cor- responding C statement? 2.4.5 [5] <2.2, 2.3> For the MIPS assembly instructions above, rewrite the assem- bly code to minimize the number if MIPS instructions (if possible) needed to carry out the same function. 2.4.6 [5] <2.2, 2.3> How ma... | Hennesey_Page_181_Chunk181 |
184 Chapter 2 Instructions: Language of the Computer The following problems explore the translation of hexadecimal numbers to other number formats. a. 0xabcdef12 b. 0x10203040 2.5.4 [5] <2.3> Translate the hexadecimal numbers above into decimal. 2.5.5 [5] <2.3> Show how the data in the table would be arranged in memory... | Hennesey_Page_182_Chunk182 |
2.6.4 [5] <2.2, 2.3> For the MIPS assembly instructions above, what is the corresponding C statement? 2.6.5 [5] <2.2, 2.3> For the MIPS assembly above, assume that the registers $s0, $s1, $s2, and $s3 contain the values 0x0000000a, 0x00000014, 0x0000001e, and 0x00000028, respectively. Also, assume that register $s6 con... | Hennesey_Page_183_Chunk183 |
186 Chapter 2 Instructions: Language of the Computer 2.7.4 [5] <2.4> For the base ten numbers above, convert to 2’s complement binary. 2.7.5 [5] <2.4> For the base ten numbers above, convert to 2’s complement hexadecimal. 2.7.6 [5] <2.4> For the base ten numbers above, convert the negated values from the table to 2’s ... | Hennesey_Page_184_Chunk184 |
a. add $s0, $s0, $s1 add $s0, $s0, $s1 b. add $s0, $s0, $s1 add $s0, $s0, $s1 add $s0, $s0, $s1 2.8.4 [5] <2.4> Assume that register $s0 = 0x70000000 and $s1 = 0x10000000. For the table above, will there be overflow? 2.8.5 [5] <2.4> Assume that register $s0 = 0x40000000 and $s1 = 0x20000000. For the table above, will t... | Hennesey_Page_185_Chunk185 |
188 Chapter 2 Instructions: Language of the Computer 2.9.5 [5] <2.4> Assume that register $s0 = 0x70000000 and $s1 has the value as given in the table. If the instruction: add $s0, $s0, $s1 is executed, what is the result in hex? 2.9.6 [5] <2.4> Assume that register $s0 = 0x70000000 and $s1 has the value as given in th... | Hennesey_Page_186_Chunk186 |
Exercise 2.11 In the following problems, the data table contains bits that represent the opcode of an instruction. You will be asked to translate the entries into assembly code and determine what format of MIPS instruction the bits represent. a. 0x01084020 b. 0x02538822 2.11.1 [5] <2.4, 2.5> What binary number does the... | Hennesey_Page_187_Chunk187 |
190 Chapter 2 Instructions: Language of the Computer 2.12.2 [5] <2.5> If the instruction set of the MIPS processor is modified, the instruction format must also be changed. For each of the suggested changes above, show the size of the bit fields of an I-type format instruction. What is the total number of bits needed f... | Hennesey_Page_188_Chunk188 |
2.13.3 [5] <2.6> For the lines above, what is the value of $t2 for the following sequence of instructions? srl $t2, $t0, 3 andi $t2, $t2, 0xFFEF In the following exercise, the data table contains various MIPS logical operations. You will be asked to find the result of these operations given values for registers $t0 and... | Hennesey_Page_189_Chunk189 |
192 Chapter 2 Instructions: Language of the Computer 2.14.1 [20] <2.6> Find the shortest sequence of MIPS instructions that extracts a field from $t0 for the constant values i = 22 and j = 5 and places the field into $t1 in the format shown in the data table. 2.14.2 [5] <2.6> Find the shortest sequence of MIPS instruct... | Hennesey_Page_190_Chunk190 |
2.15.1 [5] <2.6> The logical instructions above are not included in the MIPS instruction set, but are described above. If the value of $t2 = 0x00FFA5A5 and the value of $t3 = 0xFFFF003C, what is the result in $t1? 2.15.2 [10] <2.6> The logical instructions above are not included in the MIPS instruction set, but can be ... | Hennesey_Page_191_Chunk191 |
194 Chapter 2 Instructions: Language of the Computer Note the result of executing these instructions on particular registers. What is the value of $t2 after the following instructions? slt $t2, $t0, $t1 beq $t2, $0, ELSE j DONE ELSE: addi $t2, $0, 2 DONE: 2.16.2 [5] <2.7> Suppose that register $t0 contains a value from... | Hennesey_Page_192_Chunk192 |
address as shown in the data table above? Is it possible to use the branch-on-equal (beq) MIPS assembly instruction to set the PC to the address as shown in the data table above? Note the format of the J-type instruction. Exercise 2.17 For these problems, there are several instructions that are not included in the MIPS... | Hennesey_Page_193_Chunk193 |
196 Chapter 2 Instructions: Language of the Computer 2.17.6 [5] <2.7> For the loops written in MIPS assembly above, assume that the register $t1 is initialized to the value N. How many MIPS instructions are executed? Exercise 2.18 For these problems, the table holds some C code. You will be asked to evaluate these C co... | Hennesey_Page_194_Chunk194 |
2.18.5 [5] <2.7> Translate the loops above into C. Assume that the C-level inte- ger i is held in register $t1, $s2 holds the C-level integer called result, and $s0 holds the base address of the integer MemArray. 2.18.6 [5] <2.7> Rewrite the loop to reduce the number of MIPS instructions executed. Exercise 2.19 For the... | Hennesey_Page_195_Chunk195 |
198 Chapter 2 Instructions: Language of the Computer using the MIPS calling convention from Figure 2.14. The function declaration for func is “int func(int a, int b);”. The code for function f is as follows: a. int f(int a, int b, int c, int d){ return func(func(a,b),c+d); } b. int f(int a, int b, int c, int d){ if(a+b... | Hennesey_Page_196_Chunk196 |
b. FACT: addi $sp, $sp, 8 sw $ra, 4($sp) sw $a0, 0($sp) add $s0, $0, $a0 slti $t0, $a0, 2 beq $t0, $0, L1 mul $v0, $s0, $v0 addi $sp, $sp, -8 jr $ra L1: addi $a0, $a0, -1 jal FACT addi $v0, $0, 1 lw $a0, 0($sp) lw $ra, 4($sp) addi $sp, $sp, -8 jr $ra 2.20.1 [5] <2.8> The MIPS assembly program above computes the factori... | Hennesey_Page_197_Chunk197 |
200 Chapter 2 Instructions: Language of the Computer a. FIB: addi $sp, $sp, –12 sw $ra, 0($sp) sw $s1, 4($sp) sw $a0, 8($sp) slti $t0, $a0, 1 beq $t0, $0, L1 addi $v0, $a0, $0 j EXIT L1: addi $a0, $a0, –1 jal FIB addi $s1, $v0, $0 addi $a0, $a0, –1 jal FIB add $v0, $v0, $s1 EXIT: lw $ra, 0($sp) lw $a0, 8($sp) lw $s1, 4... | Hennesey_Page_198_Chunk198 |
instructions used to execute your solution from 2.20.2 versus the recursive version of the factorial program? 2.20.6 [5] <2.8> Show the contents of the stack after each function call, assum- ing that the input is 4. Exercise 2.21 Assume that the stack and the static data segments are empty and that the stack and global... | Hennesey_Page_199_Chunk199 |
202 Chapter 2 Instructions: Language of the Computer The following three problems in this Exercise refer to this function, written in MIPS assembly following the calling conventions from Figure 2.14: a. f: add $v0,$a1,$a0 bnez $a2,L sub $v0,$a0,$a1 L: jr $v0 b. f: add $a2,$a3,$a2 slt $a2,$a2,$a0 move $v0,$a1 beqz $a2, ... | Hennesey_Page_200_Chunk200 |
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