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might better be called a data selector. Appendix C describes the multiplexor, which selects from among several inputs based on the setting of its control lines. The control lines are set based primarily on information taken from the instruction being executed. The second omission in Figure 4.1 is that several of the ... | Hennesey_Page_301_Chunk301 |
304 Chapter 4 The Processor you have little or no background in digital logic, you will find it helpful to read Appendix C before continuing. The datapath elements in the MIPS implementation consist of two different types of logic elements: elements that operate on data values and elements that contain state. The eleme... | Hennesey_Page_302_Chunk302 |
element. Given a set of inputs, it always produces the same output because it has no internal storage. Other elements in the design are not combinational, but instead contain state. An element contains state if it has some internal storage. We call these elements state elements because, if we pulled the power plug on t... | Hennesey_Page_303_Chunk303 |
306 Chapter 4 The Processor The inputs are values that were written in a previous clock cycle, while the outputs are values that can be used in a following clock cycle. Figure 4.3 shows the two state elements surrounding a block of combinational logic, which operates in a single clock cycle: all signals must propagate ... | Hennesey_Page_304_Chunk304 |
the chosen clock edge. With an edge-triggered timing methodology, there is no feedback within a single clock cycle, and the logic in Figure 4.4 works correctly. In Appendix C, we briefly discuss additional timing constraints (such as setup and hold times) as well as other timing methodologies. For the 32-bit MIPS archi... | Hennesey_Page_305_Chunk305 |
308 Chapter 4 The Processor operation. We will draw such an ALU with the label Add, as in Figure 4.5, to indicate that it has been permanently made an adder and cannot perform the other ALU functions. To execute any instruction, we must start by fetching the instruction from memory. To prepare for executing the next in... | Hennesey_Page_306_Chunk306 |
input to the register file that specifies the register number to be read and an output from the register file that will carry the value that has been read from the registers. To write a data word, we will need two inputs: one to specify the register number to be written and one to supply the data to be written into t... | Hennesey_Page_307_Chunk307 |
310 Chapter 4 The Processor In addition, we will need a unit to sign-extend the 16‑bit offset field in the instruction to a 32‑bit signed value, and a data memory unit to read from or write to. The data memory must be written on store instructions; hence, data memory has read and write control signals, an address input... | Hennesey_Page_308_Chunk308 |
■ ■The architecture also states that the offset field is shifted left 2 bits so that it is a word offset; this shift increases the effective range of the offset field by a factor of 4. To deal with the latter complication, we will need to shift the offset field by 2. As well as computing the branch target address, we m... | Hennesey_Page_309_Chunk309 |
312 Chapter 4 The Processor FIGURE 4.9 The datapath for a branch uses the ALU to evaluate the branch condition and a separate adder to compute the branch target as the sum of the incremented PC and the sign-extended, lower 16 bits of the instruction (the branch displacement), shifted left 2 bits. The unit labeled Shift... | Hennesey_Page_310_Chunk310 |
Elaboration: In the MIPS instruction set, branches are delayed, meaning that the instruction immediately following the branch is always executed, independent of whether the branch condition is true or false. When the condition is false, the execution looks like a normal branch. When the condition is true, a delayed b... | Hennesey_Page_311_Chunk311 |
314 Chapter 4 The Processor To create a datapath with only a single register file and a single ALU, we must support two different sources for the second ALU input, as well as two different sources for the data stored into the register file. Thus, one multiplexor is placed at the ALU input and another at the data input... | Hennesey_Page_312_Chunk312 |
ALU control is different in a number of ways, and it will be useful to design it first before we design the rest of the control unit. I. Which of the following is correct for a load instruction? Refer to Figure 4.10. a. MemtoReg should be set to cause the data from memory to be sent to the register file. b. MemtoReg sh... | Hennesey_Page_313_Chunk313 |
316 Chapter 4 The Processor b. having separate memories is less expensive. c. the processor operates in one cycle and cannot use a single-ported memory for two different accesses within that cycle 4.4 A Simple Implementation Scheme In this section, we look at what might be thought of as the simplest possible imple- men... | Hennesey_Page_314_Chunk314 |
that directly controls the ALU by generating one of the 4‑bit combinations shown previously. In Figure 4.12, we show how to set the ALU control inputs based on the 2‑bit ALUOp control and the 6‑bit function code. Later in this chapter we will see how the ALUOp bits are generated from the main control unit. Instruction ... | Hennesey_Page_315_Chunk315 |
318 Chapter 4 The Processor combinations, we show only the truth table entries for which the ALU control must have a specific value. Throughout this chapter, we will use this practice of showing only the truth table entries for outputs that must be asserted and not showing those that are all deasserted or don’t care. (... | Hennesey_Page_316_Chunk316 |
Field 0 rs rt rd shamt funct Bit positions 31:26 25:21 20:16 15:11 10:6 5:0 a. R-type instruction Field 35 or 43 rs rt address Bit positions 31:26 25:21 20:16 15:0 b. Load or store instruction Field 4 rs rt address Bit positions 31:26 25:21 20:16 15:0 c. Branch instruction FIGURE 4.14 The three instruction classes (R-t... | Hennesey_Page_317_Chunk317 |
320 Chapter 4 The Processor Using this information, we can add the instruction labels and extra multiplexor (for the Write register number input of the register file) to the simple datapath. Figure 4.15 shows these additions plus the ALU control block, the write signals for state elements, the read signal for the data ... | Hennesey_Page_318_Chunk318 |
Signal name Effect when deasserted Effect when asserted RegDst The register destination number for the Write register comes from the rt field (bits 20:16). The register destination number for the Write register comes from the rd field (bits 15:11). RegWrite None. The register on the Write register input is written with... | Hennesey_Page_319_Chunk319 |
322 Chapter 4 The Processor FIGURE 4.17 The simple datapath with the control unit. The input to the control unit is the 6‑bit opcode field from the instruction. The outputs of the control unit consist of three 1‑bit signals that are used to control multiplexors (RegDst, ALUSrc, and MemtoReg), three signals for control... | Hennesey_Page_320_Chunk320 |
Figure 4.19 shows the operation of the datapath for an R-type instruction, such as add $t1,$t2,$t3. Although everything occurs in one clock cycle, we can think of four steps to execute the instruction; these steps are ordered by the flow of information: 1. The instruction is fetched, and the PC is incremented. 2. Two r... | Hennesey_Page_321_Chunk321 |
324 Chapter 4 The Processor 3. The ALU computes the sum of the value read from the register file and the sign-extended, lower 16 bits of the instruction (offset). 4. The sum from the ALU is used as the address for the data memory. 5. The data from the memory unit is written into the register file; the register destinat... | Hennesey_Page_322_Chunk322 |
Finally, we can show the operation of the branch-on-equal instruction, such as beq $t1,$t2,offset, in the same fashion. It operates much like an R‑format instruction, but the ALU output is used to determine whether the PC is written with PC + 4 or the branch target address. Figure 4.21 shows the four steps in execution... | Hennesey_Page_323_Chunk323 |
326 Chapter 4 The Processor 3. The ALU performs a subtract on the data values read from the register file. The value of PC + 4 is added to the sign-extended, lower 16 bits of the instruction (offset) shifted left by two; the result is the branch target address. 4. The Zero result from the ALU is used to decide which ad... | Hennesey_Page_324_Chunk324 |
Finalizing Control Now that we have seen how the instructions operate in steps, let’s continue with the control implementation. The control function can be precisely defined using the contents of Figure 4.18. The outputs are the control lines, and the input is the 6‑bit opcode field, Op [5:0]. Thus, we can create a tru... | Hennesey_Page_325_Chunk325 |
328 Chapter 4 The Processor Implementing Jumps Figure 4.17 shows the implementation of many of the instructions we looked at in Chapter 2. One class of instructions missing is that of the jump instruction. Extend the datapath and control of Figure 4.17 to include the jump instruction. Describe how to set any new cont... | Hennesey_Page_326_Chunk326 |
the clock cycle is determined by the longest possible path in the processor. This path is almost certainly a load instruction, which uses five functional units in series: the instruction memory, the register file, the ALU, the data memory, and the register file. Although the CPI is 1 (see Chapter 1), the overall perfor... | Hennesey_Page_327_Chunk327 |
330 Chapter 4 The Processor The penalty for using the single-cycle design with a fixed clock cycle is significant, but might be considered acceptable for this small instruction set. Historically, early computers with very simple instruction sets did use this implementation technique. However, if we tried to implemen... | Hennesey_Page_328_Chunk328 |
The pipelined approach takes much less time, as Figure 4.25 shows. As soon as the washer is finished with the first load and placed in the dryer, you load the washer with the second dirty load. When the first load is dry, you place it on the table to start folding, move the wet load to the dryer, and the next dirty loa... | Hennesey_Page_329_Chunk329 |
332 Chapter 4 The Processor If all the stages take about the same amount of time and there is enough work to do, then the speed-up due to pipelining is equal to the number of stages in the pipeline, in this case four: washing, drying, folding, and putting away. There- fore, pipelined laundry is potentially four times f... | Hennesey_Page_330_Chunk330 |
Figure 4.26 shows the time required for each of the eight instructions. The single-cycle design must allow for the slowest instruction—in Figure 4.26 it is lw—so the time required for every instruction is 800 ps. Similarly to Figure 4.25, Figure 4.27 compares nonpipelined and pipelined execution of three load word ins... | Hennesey_Page_331_Chunk331 |
334 Chapter 4 The Processor Moreover, even our claim of fourfold improvement for our example is not reflected in the total execution time for the three instructions: it’s 1400 ps versus 2400 ps. Of course, this is because the number of instructions is not large. What would happen if we increased the number of instructi... | Hennesey_Page_332_Chunk332 |
Pipelining improves performance by increasing instruction throughput, as opposed to decreasing the execution time of an individual instruction, but instruction throughput is the important metric because real programs execute billions of instructions. Designing Instruction Sets for Pipelining Even with this simple expla... | Hennesey_Page_333_Chunk333 |
336 Chapter 4 The Processor As we said above, the MIPS instruction set was designed to be pipelined, making it fairly easy for designers to avoid structural hazards when designing a pipeline. Suppose, however, that we had a single memory instead of two memories. If the pipeline in Figure 4.27 had a fourth instruction... | Hennesey_Page_334_Chunk334 |
Figure 4.29 shows the connection to forward the value in $s0 after the execu tion stage of the add instruction as input to the execution stage of the sub instruction. ANSWER FIGURE 4.28 Graphical representation of the instruction pipeline, similar in spirit to the laundry pipeline in Figure 4.25. Here we use symbols r... | Hennesey_Page_335_Chunk335 |
338 Chapter 4 The Processor load of $s0 instead of an add. As we can imagine from looking at Figure 4.29, the desired data would be available only after the fourth stage of the first instruction in the dependence, which is too late for the input of the third stage of sub. Hence, even with forwarding, we would have to ... | Hennesey_Page_336_Chunk336 |
lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1,$t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1,$t4 sw $t5, 16($t0) Find the hazards in the preceding code segment and reorder the instructions to avoid any pipeline stalls. Both add instructions have a hazard because of their respective dependence on the immediately preceding... | Hennesey_Page_337_Chunk337 |
340 Chapter 4 The Processor pipeline, we have to wait until the second stage to examine the dry uniform to see if we need to change the washer setup or not. What to do? Here is the first of two solutions to control hazards in the laundry room and its computer equivalent. Stall: Just operate sequentially until the first... | Hennesey_Page_338_Chunk338 |
Performance of “Stall on Branch” Estimate the impact on the clock cycles per instruction (CPI) of stalling on branches. Assume all other instructions have a CPI of 1. Figure 3.27 in Chapter 3 shows that branches are 17% of the instructions executed in SPECint2006. Since the other instructions run have a CPI of 1, and b... | Hennesey_Page_339_Chunk339 |
342 Chapter 4 The Processor One popular approach to dynamic prediction of branches is keeping a history for each branch as taken or untaken, and then using the recent past behavior to predict the future. As we will see later, the amount and type of history kept have become extensive, with the result being that dynamic ... | Hennesey_Page_340_Chunk340 |
Elaboration: There is a third approach to the control hazard, called delayed decision mentioned above. In our analogy, whenever you are going to make such a decision about laundry, just place a load of nonfootball clothes in the washer while waiting for football uniforms to dry. As long as you have enough dirty clothes... | Hennesey_Page_341_Chunk341 |
344 Chapter 4 The Processor Outside the memory system, the effective operation of the pipeline is usually the most important factor in determining the CPI of the processor and hence its performance. As we will see in Section 4.10, understanding the performance of a modern multiple-issue pipelined processor is complex a... | Hennesey_Page_342_Chunk342 |
pipeline, which in turn means that up to five instructions will be in execution during any single clock cycle. Thus, we must separate the datapath into five pieces, with each piece named corresponding to a stage of instruction execution: 1. IF: Instruction fetch 2. ID: Instruction decode and register file read 3. EX: E... | Hennesey_Page_343_Chunk343 |
346 Chapter 4 The Processor There are, however, two exceptions to this left-to-right flow of instructions: ■ ■The write-back stage, which places the result back into the register file in the middle of the datapath ■ ■The selection of the next value of the PC, choosing between the incremented PC and the branch address f... | Hennesey_Page_344_Chunk344 |
Figure 4.34 seems to suggest that three instructions need three datapaths. Instead, we add registers to hold data so that portions of a single datapath can be shared during instruction execution. For example, as Figure 4.34 shows, the instruction memory is used during only one of the five stages of an instruction, allo... | Hennesey_Page_345_Chunk345 |
348 Chapter 4 The Processor Notice that there is no pipeline register at the end of the write-back stage. All instructions must update some state in the processor—the register file, memory, or the PC—so a separate pipeline register is redundant to the state that is updated. For example, a load instruction will place it... | Hennesey_Page_346_Chunk346 |
FIGURE 4.36 IF and ID: First and second pipe stages of an instruction, with the active portions of the datapath in Figure 4.35 highlighted. The highlighting convention is the same as that used in Figure 4.28. As in Section 4.2, there is no confusion when reading and writing registers, because the contents change only o... | Hennesey_Page_347_Chunk347 |
350 Chapter 4 The Processor 3. Execute or address calculation: Figure 4.37 shows that the load instruction reads the contents of register 1 and the sign-extended immediate from the ID/EX pipeline register and adds them using the ALU. That sum is placed in the EX/MEM pipeline register. 4. Memory access: The top portion ... | Hennesey_Page_348_Chunk348 |
FIGURE 4.38 MEM and WB: The fourth and fifth pipe stages of a load instruction, highlighting the portions of the datapath in Figure 4.35 used in this pipe stage. Data memory is read using the address in the EX/MEM pipeline registers, and the data is placed in the MEM/WB pipeline register. Next, data is read from the ME... | Hennesey_Page_349_Chunk349 |
352 Chapter 4 The Processor 1. Instruction fetch: The instruction is read from memory using the address in the PC and then is placed in the IF/ID pipeline register. This stage occurs before the instruction is identified, so the top portion of Figure 4.36 works for store as well as load. 2. Instruction decode and regist... | Hennesey_Page_350_Chunk350 |
FIGURE 4.39 EX: The third pipe stage of a store instruction. Unlike the third stage of the load instruction in Figure 4.37, the second register value is loaded into the EX/MEM pipeline register to be used in the next stage. Although it wouldn’t hurt to always write this second register into the EX/MEM pipeline registe... | Hennesey_Page_351_Chunk351 |
354 Chapter 4 The Processor FIGURE 4.40 MEM and WB: The fourth and fifth pipe stages of a store instruction. In the fourth stage, the data is written into data memory for the store. Note that the data comes from the EX/MEM pipeline register and that nothing is changed in the MEM/WB pipeline register. Once the data is w... | Hennesey_Page_352_Chunk352 |
FIGURE 4.41 The corrected pipelined datapath to handle the load instruction properly. The write register number now comes from the MEM/WB pipeline register along with the data. The register number is passed from the ID pipe stage until it reaches the MEM/WB pipeline register, adding five more bits to the last three pi... | Hennesey_Page_353_Chunk353 |
356 Chapter 4 The Processor Graphically Representing Pipelines Pipelining can be difficult to understand, since many instructions are simulta neously executing in a single datapath in every clock cycle. To aid understanding, there are two basic styles of pipeline figures: multiple-clock-cycle pipeline diagrams, such ... | Hennesey_Page_354_Chunk354 |
FIGURE 4.43 Multiple-clock-cycle pipeline diagram of five instructions. This style of pipeline representation shows the complete execution of instructions in a single figure. Instructions are listed in instruction execution order from top to bottom, and clock cycles move from left to right. Unlike Figure 4.28, here we... | Hennesey_Page_355_Chunk355 |
358 Chapter 4 The Processor A group of students were debating the efficiency of the five-stage pipeline when one student pointed out that not all instructions are active in every stage of the pipeline. After deciding to ignore the effects of hazards, they made the following five statements. Which ones are correct? 1. A... | Hennesey_Page_356_Chunk356 |
Pipelined Control Just as we added control to the single-cycle datapath in Section 4.3, we now add control to the pipelined datapath. We start with a simple design that views the problem through rose-colored glasses; in Sections 4.7 through 4.9, we remove these glasses to reveal the pipeline hazards of the real world. ... | Hennesey_Page_357_Chunk357 |
360 Chapter 4 The Processor Instruction opcode ALUOp Instruction operation Function code Desired ALU action ALU control input LW 00 load word XXXXXX add 0010 SW 00 store word XXXXXX add 0010 Branch equal 01 branch equal XXXXXX subtract 0110 R-type 10 add 100000 add 0010 R-type 10 subtract 100010 subtract 0110 R-type 10... | Hennesey_Page_358_Chunk358 |
As was the case for the single-cycle implementation, we assume that the PC is written on each clock cycle, so there is no separate write signal for the PC. By the same argument, there are no separate write signals for the pipeline registers (IF/ID, ID/EX, EX/MEM, and MEM/WB), since the pipeline registers are also writt... | Hennesey_Page_359_Chunk359 |
362 Chapter 4 The Processor 4. Memory access: The control lines set in this stage are Branch, MemRead, and MemWrite. These signals are set by the branch equal, load, and store instructions, respectively. Recall that PCSrc in Figure 4.48 selects the next sequential address unless control asserts Branch and the ALU resul... | Hennesey_Page_360_Chunk360 |
Implementing control means setting the nine control lines to these values in each stage for each instruction. The simplest way to do this is to extend the pipeline registers to include control information. Since the control lines start with the EX stage, we can create the control infor mation during instruction decod... | Hennesey_Page_361_Chunk361 |
364 Chapter 4 The Processor Figure 4.52 shows that the values read for register $2 would not be the result of the sub instruction unless the read occurred during clock cycle 5 or later. Thus, the instructions that would get the correct value of -20 are add and sw; the AND and OR instructions would get the incorrect val... | Hennesey_Page_362_Chunk362 |
an instruction tries to use a register in its EX stage that an earlier instruction intends to write in its WB stage, we actually need the values as inputs to the ALU. A notation that names the fields of the pipeline registers allows for a more pre cise notation of dependences. For example, “ID/EX.RegisterRs” refers to... | Hennesey_Page_363_Chunk363 |
366 Chapter 4 The Processor Because some instructions do not write registers, this policy is inaccurate; sometimes it would forward when it shouldn’t. One solution is simply to check to see if the RegWrite signal will be active: examining the WB control field of the pipeline register during the EX and MEM stages determ... | Hennesey_Page_364_Chunk364 |
Note that the EX/MEM.RegisterRd field is the register destination for either an ALU instruction (which comes from the Rd field of the instruction) or a load (which comes from the Rt field). This case forwards the result from the previous instruction to either input of the ALU. If the previous instruction is going to wr... | Hennesey_Page_365_Chunk365 |
368 Chapter 4 The Processor FIGURE 4.54 On the top are the ALU and pipeline registers before adding forwarding. On the bottom, the multiplexors have been expanded to add the forwarding paths, and we show the forwarding unit. The new hardware is shown in color. This figure is a stylized drawing, however, leaving out de... | Hennesey_Page_366_Chunk366 |
it is not register 0, then steer the multiplexor to pick the value instead from the pipeline register EX/MEM. 2. MEM hazard: if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd ≠ 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt... | Hennesey_Page_367_Chunk367 |
370 Chapter 4 The Processor register destination for either an ALU instruction (which comes from the Rd field of the instruction) or a load (which comes from the Rt field). Section 4.12 on the CD shows two pieces of MIPS code with hazards that cause forwarding, if you would like to see more illustrated examples using s... | Hennesey_Page_368_Chunk368 |
Elaboration: Forwarding can also help with hazards when store instructions are dependent on other instructions. Since they use just one data value during the MEM stage, forwarding is easy. However, consider loads immediately followed by stores, useful when performing memory-to-memory copies in the MIPS architecture. S... | Hennesey_Page_369_Chunk369 |
372 Chapter 4 The Processor Data Hazards and Stalls As we said in Section 4.5, one case where forwarding cannot save the day is when an instruction tries to read a register following a load instruction that writes the same register. Figure 4.58 illustrates the problem. The data is still being read from memory in clock ... | Hennesey_Page_370_Chunk370 |
The first line tests to see if the instruction is a load: the only instruction that reads data memory is a load. The next two lines check to see if the destination register field of the load in the EX stage matches either source register of the instruction in the ID stage. If the condition holds, the instruction stalls... | Hennesey_Page_371_Chunk371 |
374 Chapter 4 The Processor FIGURE 4.59 The way stalls are really inserted into the pipeline. A bubble is inserted beginning in clock cycle 4, by changing the and instruction to a nop. Note that the and instruction is really fetched and decoded in clock cycles 2 and 3, but its EX stage is delayed until clock cycle 5 (v... | Hennesey_Page_372_Chunk372 |
FIGURE 4.60 Pipelined control overview, showing the two multiplexors for forwarding, the hazard detection unit, and the forwarding unit. Although the ID and EX stages have been simplified—the sign-extended immediate and branch logic are missing— this drawing gives the essence of the forwarding hardware requirements. 0 ... | Hennesey_Page_373_Chunk373 |
376 Chapter 4 The Processor at every clock cycle to sustain the pipeline, yet in our design the decision about whether to branch doesn’t occur until the MEM pipeline stage. As mentioned in Section 4.5, this delay in determining the proper instruction to fetch is called a control hazard or branch hazard, in contrast to ... | Hennesey_Page_374_Chunk374 |
Assume Branch Not Taken As we saw in Section 4.5, stalling until the branch is complete is too slow. A com mon improvement over branch stalling is to assume that the branch will not be taken and thus continue execution down the sequential instruction stream. If the branch is taken, the instructions that are being fetc... | Hennesey_Page_375_Chunk375 |
378 Chapter 4 The Processor 1. During ID, we must decode the instruction, decide whether a bypass to the equality unit is needed, and complete the equality comparison so that if the instruction is a branch, we can set the PC to the branch target address. For warding for the operands of branches was formerly handled by... | Hennesey_Page_376_Chunk376 |
FIGURE 4.62 The ID stage of clock cycle 3 determines that a branch must be taken, so it selects 72 as the next PC address and zeros the instruction fetched for the next clock cycle. Clock cycle 4 shows the instruction at location 72 being fetched and the single bubble or nop instruction in the pipeline as a result of t... | Hennesey_Page_377_Chunk377 |
380 Chapter 4 The Processor Dynamic Branch Prediction Assuming a branch is not taken is one simple form of branch prediction. In that case, we predict that branches are untaken, flushing the pipeline when we are wrong. For the simple five-stage pipeline, such an approach, possibly coupled with compiler-based prediction... | Hennesey_Page_378_Chunk378 |
Ideally, the accuracy of the predictor would match the taken branch frequency for these highly regular branches. To remedy this weakness, 2-bit prediction schemes are often used. In a 2-bit scheme, a prediction must be wrong twice before it is changed. Figure 4.63 shows the finite-state machine for a 2-bit predictio... | Hennesey_Page_379_Chunk379 |
382 Chapter 4 The Processor Delayed branching was a simple and effective solution for a five-stage pipeline issuing one instruction each clock cycle. As processors go to both longer pipelines and issuing multiple instructions per clock cycle (see Section 4.10), the branch delay becomes longer, and a single delay slot i... | Hennesey_Page_380_Chunk380 |
one approach to eliminate that penalty. Another approach is to use a cache to hold the destination program counter or destination instruction using a branch target buffer. The 2-bit dynamic prediction scheme uses only information about a particular branch. Researchers noticed that using information about both a local b... | Hennesey_Page_381_Chunk381 |
384 Chapter 4 The Processor 4.9 Exceptions Control is the most challenging aspect of processor design: it is both the hardest part to get right and the hardest part to make fast. One of the hardest parts of con trol is implementing exceptions and interrupts—events other than branches or jumps that change the normal fl... | Hennesey_Page_382_Chunk382 |
the term exception to refer to any unexpected change in control flow without distinguishing whether the cause is internal or external; we use the term interrupt only when the event is externally caused. Here are five examples showing whether the situation is internally generated by the processor or externally generated... | Hennesey_Page_383_Chunk383 |
386 Chapter 4 The Processor methods used to communicate the reason for an exception. The method used in the MIPS architecture is to include a status register (called the Cause register), which holds a field that indicates the reason for the exception. A second method, is to use vectored interrupts. In a vectored interr... | Hennesey_Page_384_Chunk384 |
A new control signal, called ID.Flush, is ORed with the stall signal from the hazard detection unit to flush during ID. To flush the instruction in the EX phase, we use a new signal called EX.Flush to cause new multiplexors to zero the control lines. To start fetching instructions from location 8000 0180hex, which is... | Hennesey_Page_385_Chunk385 |
388 Chapter 4 The Processor The final step is to save the address of the offending instruction in the exception program counter (EPC). In reality, we save the address + 4, so the exception handling routine must first subtract 4 from the saved value. Figure 4.66 shows a stylized version of the datapath, including the b... | Hennesey_Page_386_Chunk386 |
FIGURE 4.67 The result of an exception due to arithmetic overflow in the add instruction. The overflow is detected during the EX stage of clock 6, saving the address following the add in the EPC register (4C + 4 = 50hex). Overflow causes all the Flush signals to be set near the end of this clock cycle, deasserting cont... | Hennesey_Page_387_Chunk387 |
390 Chapter 4 The Processor The EPC captures the address of the interrupted instructions, and the MIPS Cause register records all possible exceptions in a clock cycle, so the exception software must match the exception to the instruction. An important clue is know ing in which pipeline stage a type of exception can oc... | Hennesey_Page_388_Chunk388 |
Which exception should be recognized first in this sequence? 1. add $1, $2, $1 # arithmetic overflow 2. XXX $1, $2, $1 # undefined instruction 3. sub $1, $2, $1 # hardware error 4.10 Parallelism and Advanced Instruction- Level Parallelism Be forewarned: this section is a brief overview of fascinating but advanced topi... | Hennesey_Page_389_Chunk389 |
392 Chapter 4 The Processor There are two major ways to implement a multiple-issue processor, with the major difference being the division of work between the compiler and the hardware. Because the division of work dictates whether decisions are being made statically (that is, at compile time) or dynamically (that is... | Hennesey_Page_390_Chunk390 |
a branch or a load across a store. The processor hardware can perform the same transformation at runtime using techniques we discuss later in this section. The recovery mechanisms used for incorrect speculation are rather different. In the case of speculation in software, the compiler usually inserts additional instruc... | Hennesey_Page_391_Chunk391 |
394 Chapter 4 The Processor An Example: Static Multiple Issue with the MIPS ISA To give a flavor of static multiple issue, we consider a simple two-issue MIPS pro cessor, where one of the instructions can be an integer ALU operation or branch and the other can be a load or store. Such a design is like that used in so... | Hennesey_Page_392_Chunk392 |
two registers for the ALU operation and two more for a store, and also one write port for an ALU operation and one write port for a load. Since the ALU is tied up for the ALU operation, we also need a separate adder to calculate the effective address for data transfers. Without these extra resources, our two-issue pipe... | Hennesey_Page_393_Chunk393 |
396 Chapter 4 The Processor one-instruction use latency, since the results cannot be used in the paired load or store. To effectively exploit the parallelism available in a multiple-issue processor, more ambitious compiler or hardware scheduling techniques are needed, and static multiple issue requires that the compile... | Hennesey_Page_394_Chunk394 |
An important compiler technique to get more performance from loops is loop unrolling, where multiple copies of the loop body are made. After unrolling, there is more ILP available by overlapping instructions from different iterations. Loop Unrolling for Multiple-Issue Pipelines See how well loop unrolling and schedulin... | Hennesey_Page_395_Chunk395 |
398 Chapter 4 The Processor in a given clock cycle. Obviously, achieving good performance on such a processor still requires the compiler to try to schedule instructions to move dependences apart and thereby improve the instruction issue rate. Even with such compiler scheduling, there is an important difference between... | Hennesey_Page_396_Chunk396 |
Dynamic Pipeline Scheduling Dynamic pipeline scheduling chooses which instructions to execute next, possibly reordering them to avoid stalls. In such processors, the pipeline is divided into three major units: an instruction fetch and issue unit, multiple functional units (a dozen or more in high-end designs in 2008), ... | Hennesey_Page_397_Chunk397 |
400 Chapter 4 The Processor The combination of buffering operands in the reservation stations and results in the reorder buffer provides a form of register renaming, just like that used by the compiler in our earlier loop-unrolling example on page 397. To see how this conceptually works, consider the following steps: 1... | Hennesey_Page_398_Chunk398 |
Given that compilers can also schedule code around data dependences, you might ask why a superscalar processor would use dynamic scheduling. There are three major reasons. First, not all stalls are predictable. In particular, cache misses (see Chapter 5) cause unpredictable stalls. Dynamic scheduling allows the process... | Hennesey_Page_399_Chunk399 |
402 Chapter 4 The Processor Modern, high-performance microprocessors are capable of issuing several instructions per clock; unfortunately, sustaining that issue rate is very difficult. For example, despite the existence of processors with four to six issues per clock, very few applications can sustain more than two ins... | Hennesey_Page_400_Chunk400 |
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