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2.22.3 [5] <2.5, 2.9> Translate the hexadecimal ASCII values to text. Exercise 2.23 In this exercise, you will be asked to write an MIPS assembly program that converts strings into the number format as specified in the table. a. positive and negative integer decimal strings b. positive hexadecimal integers 2.23.1 [10] <2.9> Write a program in MIPS assembly language to convert an ASCII number string with the conditions listed in the table above, to an integer. Your program should expect register $a0 to hold the address of a null-terminated string containing some combination of the digits 0 through 9. Your program should compute the integer value equivalent to this string of digits, then place the number in register $v0. If a non-digit character appears anywhere in the string, your program should stop with the value –1 in register $v0. For example, if register $a0 points to a sequence of three bytes 50ten, 52ten, 0ten (the null-terminated string “24”), then when the program stops, register $v0 should contain the value 24ten. Exercise 2.24 Assume that the register $t1 contains the address 0x1000 0000 and the register $t2 contains the address 0x1000 0010. Note the MIPS architecture utilizes big- endian addressing. a. lbu $t0, 0($t1) sw $t0, 0($t2) b. lb $t0, 0($t1) sh $t0, 0($t2) 2.24.1 [5] <2.9> Assume that the data (in hexadecimal) at address 0x1000 0000 is: 1000 0000 12 34 56 78 What value is stored at the address pointed to by register $t2? Assume that the memory location pointed to $t2 is initialized to 0xFFFF FFFF. 2.24.2 [5] <2.9> Assume that the data (in hexadecimal) at address 0x1000 0000 is: 1000 0000 80 80 80 80 2.21 Exercises 203
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204 Chapter 2 Instructions: Language of the Computer What value is stored at the address pointed to by register $t2? Assume that the memory location pointed to $t2 is initialized to 0x0000 0000. 2.24.3 [5] <2.9> Assume that the data (in hexadecimal) at address 0x1000 0000 is: 1000 0000 11 00 00 FF What value is stored at the address pointed to by register $t2? Assume that the memory location pointed to $t2 is initialized to 0x5555 5555. Exercise 2.25 In this exercise, you will explore 32-bit constants in MIPS. For the following prob- lems, you will be using the binary data in the table below. a. 0010 0000 0000 0001 0100 1001 0010 0100two b. 0000 1111 1011 1110 0100 0000 0000 0000two 2.25.1 [10] <2.10> Write the MIPS assembly code that creates the 32-bit con- stants listed above and stores that value to register $t1. 2.25.2 [5] <2.6, 2.10> If the current value of the PC is 0x00000000, can you use a single jump instruction to get to the PC address as shown in the table above? 2.25.3 [5] <2.6, 2.10> If the current value of the PC is 0x00000600, can you use a single branch instruction to get to the PC address as shown in the table above? 2.25.4 [5] <2.6, 2.10> If the current value of the PC is 0x1FFFf000, can you use a single branch instruction to get to the PC address as shown in the table above? 2.25.5 [10] <2.10> If the immediate field of an MIPS instruction was only 8 bits wide, write the MIPS code that creates the 32-bit constants listed above and stores that value to register $t1. Do not use the lui instruction. For the following problems, you will be using the MIPS assembly code as listed in the table. a. lui $t0, 0x1234 addi $t0, $t0, 0x5678 b. lui $t0, 0x1234 andi $t0, $t0, 0x5678
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2.25.6 [5] <2.6, 2.10> What is the value of register $t0 after the sequence of code in the table above? 2.25.7 [5] <2.6, 2.10> Write C code that is equivalent to the assembly code in the table. Assume that the largest constant that you can load into a 32-bit integer is 16 bits. Exercise 2.26 For this exercise, you will explore the range of branch and jump instructions in MIPS. For the following problems, use the hexadecimal data in the table below. a. 0x00020000 b. 0xFFFFFF00 2.26.1 [10] <2.6, 2.10> If the PC is at address 0x00000000, how many branch (no jump instructions) do you need to get to the address in the table above? 2.26.2 [10] <2.6, 2.10> If the PC is at address 0x00000000, how many jump instructions (no jump register instructions or branch instructions) are required to get to the target address in the table above? 2.26.3 [10] <2.6, 2.10> In order to reduce the size of MIPS programs, MIPS designers have decided to cut the immediate field of I-type instructions from 16 bits to 8 bits. If the PC is at address 0x0000000, how many branch instructions are needed to set the PC to the address in the table above? For the following problems, you will be using making modifications to the MIPS instruction set architecture. a. 128 registers b. Four times as many different operations 2.26.4 [10] <2.6, 2.10> If the instruction set of the MIPS processor is modified, the instruction format must also be changed. For each of the suggested changes above, what is the impact on the range of addresses for a beq instruction? Assume that all instructions remain 32 bits long and any changes made to the instruction format of i-type instructions only increase/decrease the immediate field of the beq instruction. 2.26.5 [10] <2.6, 2.10> If the instruction set of the MIPS processor is modi- fied, the instruction format must also be changed. For each of the suggested 2.21 Exercises 205
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206 Chapter 2 Instructions: Language of the Computer changes above, what is the impact on the range of addresses for a jump instruc- tion? Assume that instructions remain 32 bits long and any changes made to the instruction format of J-type instructions only impact the address field of the jump instruction. 2.26.6 [10] <2.6, 2.10> If the instruction set of the MIPS processor is modified, the instruction format must also be changed. For each of the suggested changes above, what is the impact on the range of addresses for a jump register instruction, assuming that each instruction must be 32 bits. Exercise 2.27 In the following problems, you will be exploring different addressing modes in the MIPS instruction set architecture. These different addressing modes are listed in the table below. a. Base or Displacement Addressing b. Pseudodirect Addressing 2.27.1 [5] <2.10> In the table above are different addressing modes of the MIPS instruction set. Give an example MIPS instructios that shows the MIPS addressing mode. 2.27.2 [5] <2.10> For the instructions in 2.27.1, what is the instruction format type used for the given instruction? 2.27.3 [5] <2.10> List the benefits and drawbacks of a particular MIPS address- ing mode. Write MIPS code that shows these benefits and drawbacks. In the following problems, you will be using the MIPS assembly code as listed below to explore the trade-offs of the immediate field in the MIPS I-type instructions. a. 0x00400000 beq $s0, $0, FAR ... 0x00403100 FAR: addi $s0, $s0, 1 b. 0x00000100 j AWAY ... 0x04000010 AWAY: addi $s0, $s0, 1 2.27.4 [15] <2.10> For the MIPS statements above, show the bit-level instruc- tion representation of each of the instructions in hexadecimal.
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2.27.5 [10] <2.10> By reducing the size of the immediate fields of the I-type and J-type instructions, we can save on the number of bits needed to represent these types of instructions. If the immediate field of I-type instructions were 8 bits and the immediate field of J-type instructions were 18 bits, rewrite the MIPS code above to reflect this change. Avoid using the lui instruction. 2.27.6 [5] <2.10> How many extra instructions are needed to do execute your code in 2.27.5 MIPS statements in the table versus the code shown in the table above? Exercise 2.28 The following table contains MIPS assembly code for a lock. Refer to the definition of the ll and sc pairs of MIPS instructions. a. try: MOV R3,R4 LL R2,0(R2) ADDI R2,R2, 1 SC R3,0(R1) BEQZ R3,try MOV R4,R2 2.28.1 [5] <2.11> For each test and fail of the store conditional, how many instructions need to be executed? 2.28.2 [5] <2.11> For the load locked/store conditional code above, explain why this code may fail. 2.28.3 [15] <2.11> Rewrite the code above so that the code may operate cor- rectly. Be sure to avoid any race conditions. Each entry in the following table has code and also shows the contents of various registers. The notation “($s1)” shows the contents of a memory location pointed to by register $s1. The assembly code in each table is executed in the cycle shown on parallel processors with a shared memory space. a. Processor 1 Processor 2 Cycle Processor 1 Mem Processor 2 $t1 $t0 ($s1) $t1 $t0 0 1 2 99 30 40 ll $t1, 0($s1) 1 ll $t1, 0($s1) 2 sc $t0, 0($s1) 3 sc $t0, 0($s1) 4 2.21 Exercises 207
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208 Chapter 2 Instructions: Language of the Computer b. Processor 1 Processor 2 Cycle Processor 1 Mem Processor 2 $t1 $t0 ($s1) $t1 $t0 0 1 2 99 30 40 ll $t1,0($s1) 1 ll $t1,0($s1) 2 addi $t1,$t1,1 3 sc $t1,0($s1) 4 sc $t0,0($s1) 5 2.28.4 [5] <2.11> Fill out the table with the value of the registers for each given cycle. Exercise 2.29 The first three problems in this Exercise refer to a critical section of the form lock(lk); operation unlock(lk); where the “operation” updates the shared variable shvar using the local (non- shared) variable x as follows: Operation a. shvar=max(shvar,x); b. if(shvar>0) shvar=max(shvar,x); 2.29.1 [10] <2.11> Write the MIPS assembly code for this critical section, assum- ing that the address of the lk variable is in $a0, the address of the shvar variable is in $a1, and the value of variable x is in $a2. Your critical section should not con- tain any function calls, i.e., you should include the MIPS instructions for lock(), unlock(), max(), and min() operations. Use ll/sc instructions to implement the lock() operation, and the unlock() operation is simply an ordinary store instruction. 2.29.2 [10] <2.11> Repeat problem 2.29.1, but this time use ll/sc to per- form an atomic update of the shvar variable directly, without using lock() and unlock(). Note that in this problem there is no variable lk. 2.29.3 [10] <2.11> Compare the best-case performance of your code from 2.29.1 and 2.29.2, assuming that each instruction takes one cycle to execute. Note: best-case
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means that ll/sc always succeeds, the lock is always free when we want to lock(), and if there is a branch we take the path that completes the operation with fewer executed instructions. 2.29.4 [10] <2.11> Using your code from 2.29.2 as an example, explain what happens when two processors begin to execute this critical section at the same time, assuming that each processor executes exactly one instruction per cycle. 2.29.5 [10] <2.11> Explain why in your code from 2.29.2 register $a1 contains the address of variable shvar and not the value of that variable, and why register $a2 contains the value of variable x and not its address. 2.29.6 [10] <2.11> If we want to atomically perform the same operation on two shared variables (e.g., shvar1 and shvar2) in the same critical section, we can do this easily using the approach from 2.29.1 (simply put both updates between the lock operation and the corresponding unlock operation). Explain why we cannot do this using the approach from 2.29.2. i.e., why we cannot use ll/sc to access both shared variables in a way that guarantees that both updates are executed together as a single atomic operation. Exercise 2.30 Assembler instructions are not a part of the MIPS instruction set, but often appear in MIPS programs. The table below contains some MIPS assembly instructions that get translated to actual MIPS instructions. a. clear $t0 b. beq $t1, large, LOOP 2.30.1 [5] <2.12> For each assembly instruction in the table above, produce a minimal sequence of actual MIPS instructions to accomplish the same thing. You may need to use temporary registers in some cases. In the table large refers to a number that requires 32 bits to represent and small to a number that can fit into 16 bits. The table below contains some MIPS assembly instructions that get translated to actual MIPS instructions. a. bltu $s0, $t1, Loop b. ulw $v0, v 2.21 Exercises 209
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210 Chapter 2 Instructions: Language of the Computer 2.30.2 [5] <2.12> Does the instruction in the table above need to be edited dur- ing the link phase? Why? Exercise 2.31 The table below contains the link-level details of two different procedures. In this exercise, you will be taking the place of the linker. a. Procedure A Procedure B Text Segment Address Instruction Text Segment Address Instruction 0 lbu $a0, 0($gp) 0 sw $a1, 0($gp) 4 jal 0 4 jal 0 Data Segment 0 (X) Data Segment 0 (Y) … … … … Relocation Info Address Instruction Type Dependency Relocation Info Address Instruction Type Dependency 0 lbu X 0 sw Y 4 jal B 4 jal A Symbol Table Address Symbol Symbol Table Address Symbol — X — Y — B — A b. Procedure A Procedure B Text Segment Address Instruction Text Segment Address Instruction 0 lui $at, 0 0 sw $a0, 0($gp) 4 ori $a0, $at, 0 4 jmp 0 … … … … 0x84 jr $ra 0x180 jal 0 … … … … Data Segment 0 (X) Data Segment 0 (Y) … … … … Relocation Info Address Instruction Type Dependency Relocation Info Address Instruction Type Dependency 0 lui X 0 sw Y 4 ori X 4 jmp FOO 0x180 jal A Symbol Table Address Symbol Symbol Table Address Symbol — X — Y 0x180 FOO — A
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2.31.1 [5] <2.12> Link the object files above to form the executable file header. Assume that Procedure A has a text size of 0x140 and data size of 0x40 and Pro- cedure B has a text size of 0x300 and data size of 0x50. Also assume the memory allocation strategy as shown in Figure 2.13. 2.31.2 [5] <2.12> What limitations, if any, are there on the size of an executable? 2.31.3 [5] <2.12> Given your understanding of the limitations of branch and jump instructions, why might an assembler have problems directly implementing branch and jump instructions an object file? Exercise 2.32 The first three problems in this exercise assume that the function swap, instead of the code in Figure 2.24, is defined in C as follows: a. void swap(int *p, int *q){ int temp; temp=*p; *p=*q; *q=temp; } b. void swap(int *p, int *q){ *p=*p+*q; *q=*p-*q; *p=*p-*q; } 2.32.1 [10] <2.13> Translate this function into MIPS assembler code. 2.32.2 [5] <2.13> What needs to change in the sort function? 2.32.3 [5] <2.13> If we were sorting 8-bit bytes, not 32-bit words, how would your MIPS code for swap in 2.32.1 change? For the remaining three problems in this Exercise, we assume that the sort func- tion from Figure 2.27 is changed in the following way: a. Use the swap function from the beginning of this exercise. b. Sort an array of n bytes instead of n words. 2.32.4 [5] <2.13> Does this change affect the code for saving and restoring reg- isters in Figure 2.27? 2.32.5 [10] <2.13> When sorting a 10-element array that was already sorted, how many more (or fewer) instructions are executed as a result of this change? 2.21 Exercises 211
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212 Chapter 2 Instructions: Language of the Computer 2.32.6 [10] <2.13> When sorting a 10-element array that was sorted in descend- ing order (opposite of the order that sort() creates), how many more (or fewer) instructions are executed as a result of this change? Exercise 2.33 The problems in this Exercise refer to the following function, given as array code: a. void copy(int a[], int b[], int n){ int i; for(i=0;i!=n;i++) a[i]=b[i]; } b. void shift(int a[], int n){ int i; for(i=0;i!=n-1;i++) a[i]=a[i+1]; } 2.33.1 [10] <2.14> Translate this function into MIPS assembly. 2.33.2 [10] <2.14> Convert this function into pointer-based code (in C). 2.33.3 [10] <2.14> Translate your pointer-based C code from 2.33.2 into MIPS assembly. 2.33.4 [5] <2.14> Compare the worst-case number of executed instructions per non-last loop iteration in your array-based code from 2.33.1 and your pointer-based code from 2.33.3. Note: the worst case occurs when branch con- ditions are such that the longest path through the code is taken, i.e., if there is an if statement, the result of the condition check is such that the path with more instructions is taken. However, if the result of the condition check would cause the loop to exit, then we assume that the path that keeps us in the loop is taken. 2.33.5 [5] <2.14> Compare the number of temporary registers (t-registers) needed for your array-based code from 2.33.1 and for your pointer-based code from 2.33.3. 2.33.6 [5] <2.14> What would change in your answer from 2.33.4 if registers $t0–$t7 and $a0–$a3 in the MIPS calling convention were all callee-saved, just like $s0–$s7?
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Exercise 2.34 The table below contains ARM assembly code. In the following problems, you will translate ARM assembly code to MIPS. a. ADD r0, r1, r2 ;r0 = r1 + r2 ADC r0, r1, r2 ;r0 = r1 + r2 + Carrybit b. CMP r0, #4 ;if (r0 != 4) { ADDNE r1, r1, r0 ;r1 += r0 } 2.34.1 [5] <2.16> For the table above, translate this ARM assembly code to MIPS assembly code. Assume that ARM registers r0, r1, and r2 hold the same values as MIPS registers $s0, $s1, and $s2, respectively. Use MIPS temporary registers ($t0, etc.) where necessary. 2.34.2 [5] <2.16> For the ARM assembly instructions in the table above, show the bit fields that represent the ARM instructions. The table below contains MIPS assembly code. In the following problems, you will translate MIPS assembly code to ARM. a. nor $t0, #s0, 0 and $s1, $s1, $t0 b. sll $s1, $s2, 16 srl $s2, $s2, 16 or $s1, $s1, $s2 2.34.3 [5] <2.16> For the table above, find the ARM assembly code that corre- sponds to the sequence of MIPS assembly code. 2.34.4 [5] <2.16> Show the bit fields that represent the ARM assembly code. Exercise 2.35 The ARM processor has a few different addressing modes that are not supported in MIPS. The following problems explore these new addressing modes. a. LDR r0, [r1, #4] ; r0 = memory[r1+4], r1 += 4 b. LDMIA r0!, {r1-r3} ; r1 = memory[r0], r2 = memory[r0+4] ; r3 = memory[r0+8], r0 += 3*4 2.35.1 [5] <2.16> Identify the type of addressing mode of the ARM assembly instructions in the table above. 2.21 Exercises 213
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214 Chapter 2 Instructions: Language of the Computer 2.35.2 [5] <2.16> For the ARM assembly instructions above, write a sequence of MIPS assembly instructions to accomplish the same data transfer. In the following problems, you will compare code written using the ARM and MIPS instruction sets. The following table shows code written in the ARM instruc- tion set. a. MOV r0, #10 ;init loop counter to 10 LOOP: ADD r0, r1 ;add r1 to r0 SUBS r0, 1 ;decrement counter BNE LOOP ;if Z=0 repeat loop b. ADD r0, r1 ;r0 = r0 + r1 ADC r2, r3 ;r2 = r2 + r3 + carry 2.35.3 [10] <2.16> For the ARM assembly code above, write an equivalent MIPS assembly code routine. 2.35.4 [5] <2.16> What is the total number of ARM assembly instructions required to execute the code? What is the total number of MIPS assembly instruc- tions required to execute the code? 2.35.5 [5] <2.16> Assuming that the average CPI of the MIPS assembly routine is the same as the average CPI of the ARM assembly routine, and the MIPS proces- sor has an operation frequency that is 1.5 times that of the ARM processor, how much faster is the ARM processor than the MIPS processor? Exercise 2.36 The ARM processor has an interesting way of supporting immediate constants. This exercise investigates those differences. The following table contains ARM instructions. a. ADD, r3, r2, r1, LSR #4 ;r3 = r2 + (r1 >> 4) b. ADD, r3, r2, r2 ;r3 = r2 + r1 2.36.1 [5] <2.16> Write the equivalent MIPS code for the ARM assembly code above. 2.36.2 [5] <2.16> If the register R1 had the constant value of 8, rewrite your MIPS code to minimize the number of MIPS assembly instructions needed. 2.36.3 [5] <2.16> If the register R1 had the constant value of 0x06000000, rewrite your MIPS code to minimize the number of MIPS assembly instructions needed.
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The following table contains MIPS instructions. a. addi r3, r2, 0x2 b. addi r3, r2, –1 2.36.4 [5] <2.16> For the MIPS assembly code above, write the equivalent ARM assembly code. Exercise 2.37 This exercise explores the differences between the MIP and x86 instruction sets. The following table contains x86 assembly code. a. START: mov eax, 3 push eax mov eax, 4 mov ecx, 4 add eax, ecx pop ecx add eax, ecx b. START: mov ecx, 100 mov eax, 0 LOOP: add eax, ecx dec ecx cmp ecx, 0 jne LOOP DONE: 2.37.1 [10] <2.17> Write pseudo code for the given routine. 2.37.2 [10] <2.17> For the code in the table above, what is the equivalent MIPS for the given routine? The following table contains x86 assembly instructions. a. push eax b. test eax, 0x00200010 2.37.3 [5] <2.17> For each assembly instruction, show the size of each of the bit fields that represent the instruction. Treat the label MY_FUNCTION as a 32-bit constant. 2.37.4 [10] <2.17> Write equivalent MIPS assembly statements. 2.21 Exercises 215
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216 Chapter 2 Instructions: Language of the Computer Exercise 2.38 The x86 instruction set includes the REP prefix that causes the instruction to be repeated a given number of times or until a condition is satisfied. Note that x86 instructions refer to 8 bits as a byte, 16 bits as a word, and 32 bits as a double word. The first three problems in this Exercise refer to the following x86 instruction: Instruction Interpretation a. REP MOVSW Repeat until ECX is zero: Mem16[EDI]=Mem16[ESI], EDI=EDI+2, ESI=ESI+2, ECX=ECX-1 b. REPNE SCASB Repeat until ECX is zero: If Mem8[EDI] == AL then go to next instruction, otherwise EDI=EDI+1, ECX=ECI+1. Note: AL is the least- significant byte of the EAX register. 2.38.1 [5] <2.17> What would be a typical use for this instruction? 2.38.2 [5] <2.17> Write MIPS code that performs the same operation, assuming that $a0 corresponds to ECX, $a1 to EDI, $a2 to ESI, and $a3 to EAX. 2.38.3 [5] <2.17> If the x86 instruction takes one cycle to read memory, one cycle to write memory, and one cycle for each register update, and if MIPS takes one cycle per instruction, what is the speedup of using this x86 instruction instead of the equivalent MIPS code when ECX is very large? Assume that the clock cycle time for x86 and MIPS is the same. The remaining three problems in this exercise refer to the following function, given in both C and x86 assembly. For each x86 instruction, we also show its length in the x86 variable-length instruction format and the interpretation (what the instruc- tion does). Note that the x86 architecture has very few registers compared to MIPS, and as a result the x86 calling convention is to push all arguments onto the stack. The return value of an x86 function is passed back to the caller in the EAX register. C Code x86 Code a. int f(int a, int b, int c, int d){ if(a>b) return c; return d; } f: push %ebp ; 1B, push %ebp to stack mov %esp,%ebp ; 2B, move %esp to %ebp mov 12(%ebp),%eax ; 3B, load 2nd arg into %eax cmp %eax,8(%ebp) ; 3B, compare %eax w/ 1st arg mov 16(%ebp),%edx ; 3B, load 3rd arg into %edx jle S ; 2B, jump if cmp result is <= pop %ebp ; 1B, restore %ebp mov %edx,%eax ; 2B, move %edx into %eax ret ; 1B, return S: mov 20(%ebp),%edx ; 3B, load 4th arg into %edx pop %ebp ; 1B, restore %ebp mov %edx,%eax ; 2B, move %edx into %eax ret ; 1B, return
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b. void f(int a[], int n){ int i; for(i=0;i!=n;i++) a[i]=0; } f: push %ebp ; 1B, push %ebp to stack mov %esp,%ebp ; 2B, move %esp to %ebp mov 12(%ebp),%edx ; 3B, move 2nd arg into %edx mov 8(%ebp),%ecx ; 3B, move 1st arg into %ecx test %edx,%edx ; 2B, set flags based on %edx jz D ; 2B, jump if %edx was 0 xor %eax,%eax ; 2B, zero into %eax L: movl 0,(%ecx,%eax,4) ; 7B, Mem[%ecx+4*%eax]=0 add 1,%eax ; 3B, add 1 to %eax cmp %edx,%eax ; 2B, compare %edx and %eax jne L ; 2B, jump if cmp was != D: pop %ebp ; 1B, restore %ebp ret ; 1B, return 2.21 Exercises 217 2.38.4 [5] <2.17> Translate this function into MIPS assembly. Compare the size (how many bytes of instruction memory are needed) for this x86 code and for your MIPS code. 2.38.5 [5] <2.17> If the processor can execute two instructions per cycle, it must at least be able to read two consecutive instructions in each cycle. Explain how it would be done in MIPS and how it would be done in x86. 2.38.6 [5] <2.17> If each MIPS instruction takes one cycle, and if each x86 instruction takes one cycle plus a cycle for each memory read or write it has to perform, what is the speedup of using x86 instead of MIPS? Assume that the clock cycle time is the same in both x86 and MIPS, and that the execution takes the short- est possible path through the function (i.e., every loop is exited immediately and every if statement takes the direction that leads toward the return from the func- tion). Note that the x86 ret instruction reads the return address from the stack. Exercise 2.39 The CPI of the different instruction types is given in the following table. Arithmetic Load/Store Branch a. 1 10 3 b. 4 40 3 2.39.1 [5] <2.18> Assume the following instruction breakdown given for execut- ing a given program: Instructions (in millions) Arithmetic 500 Load/Store 300 Branch 100 What is the execution time for the processor if the operation frequency is 5 GHz?
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218 Chapter 2 Instructions: Language of the Computer 2.39.2 [5] <2.18> Suppose that new, more powerful arithmetic instructions are added to the instruction set. On average, through the use of these more power- ful arithmetic instructions, we can reduce the number of arithmetic instructions needed to execute a program by 25%, and the cost of increasing the clock cycle time by only 10%. Is this a good design choice? Why? 2.39.3 [5] <2.18> Suppose that we find a way to double the performance of arithmetic instructions. What is the overall speedup of our machine? What if we find a way to improve the performance of arithmetic instructions by 10 times? The following table shows the proportions of instruction execution for the differ- ent instruction types. Arithmetic Load/Store Branch a. 70% 10% 20% b. 50% 40% 10% 2.39.4 [5] <2.18> Given the instruction mix above and the assumption that an arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, find the average CPI. 2.39.5 [5] <2.18> For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all? 2.39.6 [5] <2.18> For a 50% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all? Exercise 2.40 The first three problems in this Exercise refer to the following function, given in MIPS assembly. Unfortunately, the programmer of this function has fallen prey to the pitfall of assuming that MIPS is a word-addressed machine, but in fact MIPS is byte-addressed. a. ; int f(int *a, int n, int x); f: move $v0,$0 ; ret=0 move $t0,$a0 ; ptr=a add $t1,$a1,$a0 ; &(a[n]) L: lw $t2,0($t0) ; read *p bne $t2,$a2,S ; if(*p==x) addi $v0,$v0,1 ; ret++; S: addi $t0,$t0,1 ; p=p+1 bne $t0,$t1,L ; repeat if p!=&(a[n]) jr $ra ; return ret
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b. ; void f(int a[], int n); f: move $t0,$0 ; i=0; addi $t1,$a1,-1 ; n-1 L: add $t2,$t0,$a0 ; address of a[i] lw $t3,1($t2) ; read a[i+1] sw $t3,0($t2) ; a[i]=a[i+1] addi $t0,$t0,1 ; i=i+1 bne $t0,$t1,L ; repeat if i!=n-1 jr $ra ; return Note that in MIPS assembly the “;” character denotes that the remainder of the line is a comment. 2.40.1 [5] <2.18> The MIPS architecture requires word-sized accesses (lw and sw) to be word-aligned, i.e., the lowermost 2 bits of the address must both be zero. If an address is not word-aligned, the processor raises a “bus error” exception. Explain how this alignment requirement affects the execution of this function. 2.40.2 [5] <2.18> If “a” was a pointer to the beginning of an array of 1-byte elements, and if we replaced lw and sw with lb (load byte) and sb (store byte), respectively, would this function be correct? Note: lb reads a byte from memory, sign-extends it, and places it into the destination register, while sb stores the least- significant byte of the register into memory. 2.40.3 [5] <2.18> Change this code to make it correct for 32-bit integers. The remaining three problems in this exercise refer to a program that allocates memory for an array, fills the array with some numbers, calls the sort function from Figure 2.27, and then prints out the array. The main function of the program is as follows (given as both C and MIPS code): Main Code in C MIPS Version of the Main Code main(){ int *v; int n=5; v=my_alloc(5); my_init(v,n); sort(v,n); . . . main: li $s0,5 move $a0,$s0 jal my_alloc move $s1,$v0 move $a0,$s1 move $a1,$s0 jal my_init move $a0,$s1 move $a1,$s0 jal sort The my_alloc function is defined as follows (given as both C and MIPS code). Note that the programmer of this function has fallen prey to the pitfall of 2.21 Exercises 219
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220 Chapter 2 Instructions: Language of the Computer using a pointer to an automatic variable arr outside the function in which it is defined. my_alloc in C MIPS Code for my_alloc int *my_alloc(int n){ int arr[n]; return arr; } my_alloc: addu $sp,$sp,-4 ; Push sw $fp,0($sp) ; $fp to stack move $fp,$sp ; Save $sp in $fp sll $t0,$a0,2 ; We need 4*n bytes sub $sp,$sp,$t0 ; Make room for arr move $v0,$sp ; Return address of arr move $sp,$fp ; Restore $sp from $fp lw $fp,0(sp) ; Pop $fp addiu $sp,$sp,4 ; from stack jr ra The my_init function is defined as follows (MIPS code): a. my_init: move $t0,$0 ; i=0 move $t1,$a0 L: addi $t2,$t0,10 sw $t2,0($t1) ; v[i]=i+10 addiu $t1,$t1,4 addiu $t0,$t0,1 ; i=i+1 bne $t0,$a1,L ; until i==n jr $ra b. my_init: move $t0,$0 ; i=0 move $t1,$a0 L: sll $t2,$t0,1 addi $t2,$t2,100 sw $t2,0($t1) ; a[i]=100+2*i; addiu $t1,$t1,4 addiu $t0,$t0,1 ; i=i+1 bne $t0,$a1,L ; until i==n jr $ra 2.40.4 [5] <2.18> What are the contents (values of all five elements) of array v right before the “jal sort” instruction in the main code is executed? 2.40.5 [15] <2.18, 2.13> What are the contents of array v right before the sort function enters its outer loop for the first time? Assume that registers $sp, $s0, $s1, $s2, and $s3 have values of 0x1000, 20, 40, 7, and 1, respectively, at the begin- ning of the main code (right before “li $s0, 5” is executed). 2.40.6 [10] <2.18, 2.13> What are the contents of the 5-element array pointed by v right after “jal sort” returns to the main code?
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§2.2, page 80: MIPS, C, Java §2.3, page 87: 2) Very slow §2.4, page 93: 3) –8ten §2.5, page 101: 4) sub $s2, $s0, $s1 §2.6, page 105: Both. AND with a mask pattern of 1s will leaves 0s everywhere but the desired field. Shifting left by the right amount removes the bits from the left of the field. Shifting right by the appropriate amount puts the field into the rightmost bits of the word, with 0s in the rest of the word. Note that AND leaves the field where it was originally, and the shift pair moves the field into the rightmost part of the word. §2.7, page 111: I. All are true. II. 1). §2.8, page 122: Both are true. §2.9, page 127: I. 2) II. 3) §2.10, page 136: I. 4) +-128K. II. 6) a block of 256M. III. 4) sll §2.11, page 139: Both are true. §2.12, page 148: 4) Machine independence. Answers to Check Yourself 2.21 Exercises 221
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3 Numerical precision is the very soul of science. Sir D’arcy Wentworth Thompson On Growth and Form, 1917 Arithmetic for Computers 3.1 Introduction 224 3.2 Addition and Subtraction 224 3.3 Multiplication 230 3.4 Division 236 3.5 Floating Point 242 3.6 Parallelism and Computer Arithmetic: Associativity 270 3.7 Real Stuff: Floating Point in the x86 272 3.8 Fallacies and Pitfalls 275 Computer Organization and Design. DOI: 10.1016/B978-0-12-374750-1.00003-7 © 2012 Elsevier, Inc. All rights reserved.
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3.9 Concluding Remarks 280 3.10 Historical Perspective and Further Reading 283 3.11 Exercises 283 The Five Classic Components of a Computer
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224 Chapter 3 Arithmetic for Computers 3.1 Introduction Computer words are composed of bits; thus, words can be represented as binary numbers. Chapter 2 shows that integers can be represented either in decimal or binary form, but what about the other numbers that commonly occur? For example: ■ ■What about fractions and other real numbers? ■ ■What happens if an operation creates a number bigger than can be represented? ■ ■And underlying these questions is a mystery: How does hardware really multiply or divide numbers? The goal of this chapter is to unravel these mysteries including representation of real numbers, arithmetic algorithms, hardware that follows these algorithms, and the implications of all this for instruction sets. These insights may explain quirks that you have already encountered with computers. 3.2 Addition and Subtraction Addition is just what you would expect in computers. Digits are added bit by bit from right to left, with carries passed to the next digit to the left, just as you would do by hand. Subtraction uses addition: the appropriate operand is simply negated before being added. Binary Addition and Subtraction Let’s try adding 6ten to 7ten in binary and then subtracting 6ten from 7ten in binary. 0000 0000 0000 0000 0000 0000 0000 0111two = 7ten + 0000 0000 0000 0000 0000 0000 0000 0110two = 6ten = 0000 0000 0000 0000 0000 0000 0000 1101two = 13ten The 4 bits to the right have all the action; Figure 3.1 shows the sums and carries. The carries are shown in parentheses, with the arrows showing how they are passed. Subtraction: Addition’s Tricky Pal No. 10, Top Ten Courses for Athletes at a Football Factory, David Letterman et al., Book of Top Ten Lists, 1990 EXAMPLE
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3.2 Addition and Subtraction 225 Subtracting 6ten from 7ten can be done directly: 0000 0000 0000 0000 0000 0000 0000 0111two = 7ten – 0000 0000 0000 0000 0000 0000 0000 0110two = 6ten = 0000 0000 0000 0000 0000 0000 0000 0001two = 1ten or via addition using the two’s complement representation of -6: 0000 0000 0000 0000 0000 0000 0000 0111two = 7ten + 1111 1111 1111 1111 1111 1111 1111 1010two = –6ten = 0000 0000 0000 0000 0000 0000 0000 0001two = 1ten ANSWER Recall that overflow occurs when the result from an operation cannot be represented with the available hardware, in this case a 32-bit word. When can overflow occur in addition? When adding operands with different signs, overflow cannot occur. The reason is the sum must be no larger than one of the operands. For example, -10 + 4 = -6. Since the operands fit in 32 bits and the sum is no larger than an operand, the sum must fit in 32 bits as well. Therefore, no overflow can occur when adding positive and negative operands. There are similar restrictions to the occurrence of overflow during subtract, but it’s just the opposite principle: when the signs of the operands are the same, overflow cannot occur. To see this, remember that x - y = x + (-y) because we subtract by negating the second operand and then add. Therefore, when we subtract operands of the same sign we end up by adding operands of different signs. From the prior paragraph, we know that overflow cannot occur in this case either. Knowing when overflow cannot occur in addition and subtraction is all well and good, but how do we detect it when it does occur? Clearly, adding or subtracting two 32-bit numbers can yield a result that needs 33 bits to be fully expressed. FIGURE 3.1 Binary addition, showing carries from right to left. The rightmost bit adds 1 to 0, resulting in the sum of this bit being 1 and the carry out from this bit being 0. Hence, the operation for the second digit to the right is 0 + 1 + 1. This generates a 0 for this sum bit and a carry out of 1. The third digit is the sum of 1 + 1 + 1, resulting in a carry out of 1 and a sum bit of 1. The fourth bit is 1 + 0 + 0, yielding a 1 sum and no carry. (0) 0 0 0 (0) (0) 0 0 0 (0) (1) 0 0 1 (1) (1) 1 1 1 (1) (0) 1 1 0 (0) (Carries) 1 0 1 (0) . . . . . . . . .
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226 Chapter 3 Arithmetic for Computers The lack of a 33rd bit means that when overflow occurs, the sign bit is set with the value of the result instead of the proper sign of the result. Since we need just one extra bit, only the sign bit can be wrong. Hence, overflow occurs when adding two positive numbers and the sum is negative, or vice versa. This means a carry out occurred into the sign bit. Overflow occurs in subtraction when we subtract a negative number from a positive number and get a negative result, or when we subtract a positive number from a negative number and get a positive result. This means a borrow occurred from the sign bit. Figure 3.2 shows the combination of operations, operands, and results that indicate an overflow. We have just seen how to detect overflow for two’s complement numbers in a computer. What about overflow with unsigned integers? Unsigned integers are commonly used for memory addresses where overflows are ignored. The computer designer must therefore provide a way to ignore overflow in some cases and to recognize it in others. The MIPS solution is to have two kinds of arithmetic instructions to recognize the two choices: ■ ■Add (add), add immediate (addi), and subtract (sub) cause exceptions on overflow. ■ ■Add unsigned (addu), add immediate unsigned (addiu), and subtract unsigned (subu) do not cause exceptions on overflow. Because C ignores overflows, the MIPS C compilers will always generate the unsigned versions of the arithmetic instructions addu, addiu, and subu, no matter what the type of the variables. The MIPS Fortran compilers, however, pick the appropriate arithmetic instructions, depending on the type of the operands. Operation Operand A Operand B Result indicating overflow A + B ≥ 0 ≥ 0 < 0 A + B < 0 < 0 ≥ 0 A – B ≥ 0 < 0 < 0 A – B < 0 ≥ 0 ≥ 0 FIGURE 3.2 Overflow conditions for addition and subtraction. Appendix C describes the hardware that performs addition and subtraction, which is called an Arithmetic Logic Unit or ALU. Arithmetic Logic Unit (ALU) Hardware that performs addition, subtraction, and usually logical operations such as AND and OR.
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3.2 Addition and Subtraction 227 The computer designer must decide how to handle arithmetic overflows. Although some languages like C and Java ignore integer overflow, languages like Ada and Fortran require that the program be notified. The programmer or the programming environment must then decide what to do when overflow occurs. MIPS detects overflow with an exception, also called an interrupt on many computers. An exception or interrupt is essentially an unscheduled procedure call. The address of the instruction that overflowed is saved in a register, and the computer jumps to a predefined address to invoke the appropriate routine for that exception. The interrupted address is saved so that in some situations the program can continue after corrective code is executed. (Section 4.9 covers exceptions in more detail; Chapters 5 and 6 describe other situations where exceptions and interrupts occur.) MIPS includes a register called the exception program counter (EPC) to contain the address of the instruction that caused the exception. The instruction move from system control (mfc0) is used to copy EPC into a general-purpose register so that MIPS software has the option of returning to the offending instruction via a jump register instruction. Arithmetic for Multimedia Since every desktop microprocessor by definition has its own graphical displays, as transistor budgets increased it was inevitable that support would be added for graphics operations. Many graphics systems originally used 8 bits to represent each of the three primary colors plus 8 bits for a location of a pixel. The addition of speakers and microphones for teleconferencing and video games suggested support of sound as well. Audio samples need more than 8 bits of precision, but 16 bits are sufficient. Every microprocessor has special support so that bytes and halfwords take up less space when stored in memory (see Section 2.9), but due to the infrequency of arithmetic operations on these data sizes in typical integer programs, there is little support beyond data transfers. Architects recognized that many graphics and audio applications would perform the same operation on vectors of this data. By partitioning the carry chains within a 64-bit adder, a processor could perform simultaneous operations on short vectors of eight 8-bit operands, four 16-bit operands, or two 32-bit operands. The cost of such partitioned adders was small. These extensions have been called vector or SIMD, for single instruction, multiple data (see Section 2.17 and Chapter 7). One feature not generally found in general-purpose microprocessors is saturating operations. Saturation means that when a calculation overflows, the result is set Hardware/ Software Interface exception Also called interrupt. An unscheduled event that disrupts program execution; used to detect overflow. interrupt An exception that comes from outside of the processor. (Some architectures use the term interrupt for all exceptions.)
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228 Chapter 3 Arithmetic for Computers to the largest positive number or most negative number, rather than a modulo calculation as in two’s complement arithmetic. Saturation is likely what you want for media operations. For example, the volume knob on a radio set would be frustrating if, as you turned, it would get continuously louder for a while and then immediately very soft. A knob with saturation would stop at the highest volume no matter how far you turned it. Figure 3.3 shows arithmetic and logical operations found in many multimedia extensions to modern instruction sets. Instruction category Operands Unsigned add/subtract Eight 8-bit or Four 16-bit Saturating add/subtract Eight 8-bit or Four 16-bit Max/min/minimum Eight 8-bit or Four 16-bit Average Eight 8-bit or Four 16-bit Shift right/left Eight 8-bit or Four 16-bit FIGURE 3.3 Summary of multimedia support for desktop computers. Elaboration: MIPS can trap on overflow, but unlike many other computers, there is no conditional branch to test overflow. A sequence of MIPS instructions can discover overflow. For signed addition, the sequence is the following (see the Elaboration on page 104 in Chapter 2 for a description of the xor instruction): addu $t0, $t1, $t2 # $t0 = sum, but don’t trap xor $t3, $t1, $t2 # Check if signs differ slt $t3, $t3, $zero # $t3 = 1 if signs differ bne $t3, $zero, No_overflow # $t1, $t2 signs ≠, # so no overflow xor $t3, $t0, $t1 # signs =; sign of sum match too? # $t3 negative if sum sign different slt $t3, $t3, $zero # $t3 = 1 if sum sign different bne $t3, $zero, Overflow # All 3 signs ≠; go to overflow For unsigned addition ($t0 = $t1 + $t2), the test is addu $t0, $t1, $t2 # $t0 = sum nor $t3, $t1, $zero # $t3 = NOT $t1 # (2’s comp – 1: 232 – $t1 – 1) sltu $t3, $t3, $t2 # (232 – $t1 – 1) < $t2 # ⇒ 232 – 1 < $t1 + $t2 bne $t3,$zero,Overflow # if(232–1<$t1+$t2) goto overflow
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3.2 Addition and Subtraction 229 Summary A major point of this section is that, independent of the representation, the finite word size of computers means that arithmetic operations can create results that are too large to fit in this fixed word size. It’s easy to detect overflow in unsigned numbers, although these are almost always ignored because programs don’t want to detect overflow for address arithmetic, the most common use of natural numbers. Two’s complement presents a greater challenge, yet some software systems require detection of overflow, so today all computers have a way to detect it. The rising popularity of multimedia applications led to arithmetic instructions that support narrower operations that can easily operate in parallel. Some programming languages allow two’s complement integer arithmetic on variables declared byte and half. What MIPS instructions would be used? 1. Load with lbu, lhu; arithmetic with add, sub, mult, div; then store using sb, sh. 2. Load with lb, lh; arithmetic with add, sub, mult, div; then store using sb, sh. 3. Load with lb, lh; arithmetic with add, sub, mult, div, using AND to mask result to 8 or 16 bits after each operation; then store using sb, sh. Elaboration: In the preceding text, we said that you copy EPC into a register via mfc0 and then return to the interrupted code via jump register. This leads to an interesting question: since you must first transfer EPC to a register to use with jump register, how can jump register return to the interrupted code and restore the original values of all registers? Either you restore the old registers first, thereby destroying your return address from EPC, which you placed in a register for use in jump register, or you restore all registers but the one with the return address so that you can jump—meaning an exception would result in changing that one register at any time during program execution! Neither option is satisfactory. To rescue the hardware from this dilemma, MIPS programmers agreed to reserve registers $k0 and $k1 for the operating system; these registers are not restored on exceptions. Just as the MIPS compilers avoid using register $at so that the assembler can use it as a temporary register (see Hardware/Software Interface in Section 2.10), compilers also abstain from using registers $k0 and $k1 to make them available for the operating system. Exception routines place the return address in one of these registers and then use jump register to restore the instruction address. Elaboration: The speed of addition is increased by determining the carry in to the high-order bits sooner. There are a variety of schemes to anticipate the carry so that the worst-case scenario is a function of the log 2 of the number of bits in the adder. These anticipatory signals are faster because they go through fewer gates in sequence, but it takes many more gates to anticipate the proper carry. The most popular is carry lookahead, which Section C.6 in Appendix C on the CD describes. Check Yourself
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230 Chapter 3 Arithmetic for Computers 3.3 Multiplication Now that we have completed the explanation of addition and subtraction, we are ready to build the more vexing operation of multiplication. First, let’s review the multiplication of decimal numbers in longhand to remind ourselves of the steps of multiplication and the names of the operands. For reasons that will become clear shortly, we limit this decimal example to using only the digits 0 and 1. Multiplying 1000ten by 1001ten: Multiplication is vexation, Division is as bad; The rule of three doth puzzle me, And practice drives me mad. Anonymous, Elizabethan manuscript, 1570 Multiplicand 1000ten Multiplier x 1001ten 1000 0000 0000 1000 Product 1001000ten The first operand is called the multiplicand and the second the multiplier. The final result is called the product. As you may recall, the algorithm learned in grammar school is to take the digits of the multiplier one at a time from right to left, multiplying the multiplicand by the single digit of the multiplier, and shifting the intermediate product one digit to the left of the earlier intermediate products. The first observation is that the number of digits in the product is considerably larger than the number in either the multiplicand or the multiplier. In fact, if we ignore the sign bits, the length of the multiplication of an n-bit multiplicand and an m-bit multiplier is a product that is n + m bits long. That is, n + m bits are required to represent all possible products. Hence, like add, multiply must cope with overflow because we frequently want a 32-bit product as the result of multiplying two 32-bit numbers. In this example, we restricted the decimal digits to 0 and 1. With only two choices, each step of the multiplication is simple: 1. Just place a copy of the multiplicand (1 × multiplicand) in the proper place if the multiplier digit is a 1, or 2. Place 0 (0 × multiplicand) in the proper place if the digit is 0. Although the decimal example above happens to use only 0 and 1, multiplication of binary numbers must always use 0 and 1, and thus always offers only these two choices.
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Now that we have reviewed the basics of multiplication, the traditional next step is to provide the highly optimized multiply hardware. We break with tradition in the belief that you will gain a better understanding by seeing the evolution of the multiply hardware and algorithm through multiple generations. For now, let’s assume that we are multiplying only positive numbers. Sequential Version of the Multiplication Algorithm and Hardware This design mimics the algorithm we learned in grammar school; Figure 3.4 shows the hardware. We have drawn the hardware so that data flows from top to bottom to resemble more closely the paper-and-pencil method. Let’s assume that the multiplier is in the 32-bit Multiplier register and that the 64-bit Product register is initialized to 0. From the paper-and-pencil example above, it’s clear that we will need to move the multiplicand left one digit each step, as it may be added to the intermediate products. Over 32 steps, a 32-bit multipli- cand would move 32 bits to the left. Hence, we need a 64-bit Multiplicand register, initialized with the 32-bit multiplicand in the right half and zero in the left half. This register is then shifted left 1 bit each step to align the multiplicand with the sum being accumulated in the 64-bit Product register. Figure 3.5 shows the three basic steps needed for each bit. The least significant bit of the multiplier (Multiplier0) determines whether the multiplicand is added to FIGURE 3.4 First version of the multiplication hardware. The Multiplicand register, ALU, and Product register are all 64 bits wide, with only the Multiplier register containing 32 bits. ( Appendix C describes ALUs.) The 32-bit multiplicand starts in the right half of the Multiplicand register and is shifted left 1 bit on each step. The multiplier is shifted in the opposite direction at each step. The algorithm starts with the product initialized to 0. Control decides when to shift the Multiplicand and Multiplier registers and when to write new values into the Product register. Multiplicand Shift left 64 bits 64-bit ALU Product Write 64 bits Control test Multiplier Shift right 32 bits 3.3 Multiplication 231
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232 Chapter 3 Arithmetic for Computers the Product register. The left shift in step 2 has the effect of moving the intermediate operands to the left, just as when multiplying with paper and pencil. The shift right in step 3 gives us the next bit of the multiplier to examine in the following iteration. These three steps are repeated 32 times to obtain the product. If each step took a clock cycle, this algorithm would require almost 100 clock cycles to multiply FIGURE 3.5 The first multiplication algorithm, using the hardware shown in Figure 3.4. If the least significant bit of the multiplier is 1, add the multiplicand to the product. If not, go to the next step. Shift the multiplicand left and the multiplier right in the next two steps. These three steps are repeated 32 times. 32nd repetition? 1a. Add multiplicand to product and place the result in Product register Multiplier0 = 0 1. Test Multiplier0 Start Multiplier0 = 1 2. Shift the Multiplicand register left 1 bit 3. Shift the Multiplier register right 1 bit No: < 32 repetitions Yes: 32 repetitions Done
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two 32-bit numbers. The relative importance of arithmetic operations like multiply varies with the program, but addition and subtraction may be anywhere from 5 to 100 times more popular than multiply. Accordingly, in many applications, multiply can take multiple clock cycles without significantly affecting performance. Yet Amdahl’s law (see Section 1.8) reminds us that even a moderate frequency for a slow operation can limit performance. This algorithm and hardware are easily refined to take 1 clock cycle per step. The speed-up comes from performing the operations in parallel: the multiplier and multiplicand are shifted while the multiplicand is added to the product if the multiplier bit is a 1. The hardware just has to ensure that it tests the right bit of the multiplier and gets the preshifted version of the multiplicand. The hardware is usually further optimized to halve the width of the adder and registers by noticing where there are unused portions of registers and adders. Figure 3.6 shows the revised hardware. Replacing arithmetic by shifts can also occur when multiplying by constants. Some compilers replace multiplies by short constants with a series of shifts and adds. Because one bit to the left represents a number twice as large in base 2, shifting the bits left has the same effect as multiplying by a power of 2. As mentioned in Chapter 2, almost every compiler will perform the strength reduction optimization of substituting a left shift for a multiply by a power of 2. Hardware/ Software Interface FIGURE 3.6 Refined version of the multiplication hardware. Compare with the first version in Figure 3.4. The Multiplicand register, ALU, and Multiplier register are all 32 bits wide, with only the Product register left at 64 bits. Now the product is shifted right. The separate Multiplier register also disappeared. The multiplier is placed instead in the right half of the Product register. These changes are highlighted in color. (The Product register should really be 65 bits to hold the carry out of the adder, but it’s shown here as 64 bits to highlight the evolution from Figure 3.4.) Multiplicand 32 bits 32-bit ALU Product Write 64 bits Control test Shift right 3.3 Multiplication 233
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234 Chapter 3 Arithmetic for Computers A Multiply Algorithm Using 4-bit numbers to save space, multiply 2ten × 3ten, or 0010two × 0011two. Figure 3.7 shows the value of each register for each of the steps labeled according to Figure 3.5, with the final value of 0000 0110two or 6ten. Color is used to indicate the register values that change on that step, and the bit circled is the one examined to determine the operation of the next step. Signed Multiplication So far, we have dealt with positive numbers. The easiest way to understand how to deal with signed numbers is to first convert the multiplier and multiplicand to positive numbers and then remember the original signs. The algorithms should then be run for 31 iterations, leaving the signs out of the calculation. As we learned in grammar school, we need negate the product only if the original signs disagree. It turns out that the last algorithm will work for signed numbers, provided that we remember that we are dealing with numbers that have infinite digits, and we are only representing them with 32 bits. Hence, the shifting steps would need to extend the sign of the product for signed numbers. When the algorithm completes, the lower word would have the 32-bit product. EXAMPLE ANSWER Iteration Step Multiplier Multiplicand Product 0 Initial values 0011 0000 0010 0000 0000 1 1a: 1 ⇒ Prod = Prod + Mcand 0011 0000 0010 0000 0010 2: Shift left Multiplicand 0011 0000 0100 0000 0010 3: Shift right Multiplier 0001 0000 0100 0000 0010 2 1a: 1 ⇒ Prod = Prod + Mcand 0001 0000 0100 0000 0110 2: Shift left Multiplicand 0001 0000 1000 0000 0110 3: Shift right Multiplier 0000 0000 1000 0000 0110 3 1: 0 ⇒ No operation 0000 0000 1000 0000 0110 2: Shift left Multiplicand 0000 0001 0000 0000 0110 3: Shift right Multiplier 0000 0001 0000 0000 0110 4 1: 0 ⇒ No operation 0000 0001 0000 0000 0110 2: Shift left Multiplicand 0000 0010 0000 0000 0110 3: Shift right Multiplier 0000 0010 0000 0000 0110 FIGURE 3.7 Multiply example using algorithm in Figure 3.5. The bit examined to determine the next step is circled in color.
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Faster Multiplication Moore’s law has provided so much more in resources that hardware designers can now build much faster multiplication hardware. Whether the multiplicand is to be added or not is known at the beginning of the multiplication by looking at each of the 32 multiplier bits. Faster multiplications are possible by essentially providing one 32-bit adder for each bit of the multiplier: one input is the multiplicand ANDed with a multiplier bit, and the other is the output of a prior adder. A straightforward approach would be to connect the outputs of adders on the right to the inputs of adders on the left, making a stack of adders 32 high. An alternative way to organize these 32 additions is in a parallel tree, as Figure 3.8 shows. Instead of waiting for 32 add times, we wait just the log2 (32) or five 32-bit add times. Figure 3.8 shows how this is a faster way to connect them. In fact, multiply can go even faster than five add times because of the use of carry save adders (see Section C.6 in Appendix C) and because it is easy to pipeline such a design to be able to support many multiplies simultaneously (see Chapter 4). Multiply in MIPS MIPS provides a separate pair of 32-bit registers to contain the 64-bit product, called Hi and Lo. To produce a properly signed or unsigned product, MIPS has two instructions: multiply (mult) and multiply unsigned (multu). To fetch the integer 32-bit product, the programmer uses move from lo (mflo). The MIPS assembler generates a pseudoinstruction for multiply that specifies three general- purpose registers, generating mflo and mfhi instructions to place the product into registers. Summary Multiplication hardware is simply shifts and add, derived from the paper-and- pencil method learned in grammar school. Compilers even use shift instructions for multiplications by powers of 2. Both MIPS multiply instructions ignore overflow, so it is up to the software to check to see if the product is too big to fit in 32 bits. There is no overflow if Hi is 0 for multu or the replicated sign of Lo for mult. The instruction move from hi (mfhi) can be used to transfer Hi to a general-purpose register to test for overflow. Hardware/ Software Interface 3.3 Multiplication 235
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236 Chapter 3 Arithmetic for Computers 3.4 Division The reciprocal operation of multiply is divide, an operation that is even less frequent and even more quirky. It even offers the opportunity to perform a mathematically invalid operation: dividing by 0. Let’s start with an example of long division using decimal numbers to recall the names of the operands and the grammar school division algorithm. For reasons similar to those in the previous section, we limit the decimal digits to just 0 or 1. The example is dividing 1,001,010ten by 1000ten: 1001ten Quotient Divisor 1000ten 1001010ten Dividend -1000 10 101 1010 -1000 10ten Remainder Divide et impera. Latin for “Divide and rule,” ancient political maxim cited by Machiavelli, 1532 FIGURE 3.8 Fast multiplication hardware. Rather than use a single 32-bit adder 31 times, this hardware “unrolls the loop” to use 31 adders and then organizes them to minimize delay. Product1 Product0 Product63 Product62 Product47..16 1 bit 1 bit 1 bit 1 bit . . . . . . . . . . . . . . . . . . 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits Mplier31 • Mcand Mplier30 • Mcand Mplier29 • Mcand Mplier28 • Mcand Mplier3 • Mcand Mplier2 • Mcand Mplier1 • Mcand Mplier0 • Mcand
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Divide’s two operands, called the dividend and divisor, and the result, called the quotient, are accompanied by a second result, called the remainder. Here is another way to express the relationship between the components: Dividend = Quotient × Divisor + Remainder where the remainder is smaller than the divisor. Infrequently, programs use the divide instruction just to get the remainder, ignoring the quotient. The basic grammar school division algorithm tries to see how big a number can be subtracted, creating a digit of the quotient on each attempt. Our carefully selected decimal example uses only the numbers 0 and 1, so it’s easy to figure out how many times the divisor goes into the portion of the dividend: it’s either 0 times or 1 time. Binary numbers contain only 0 or 1, so binary division is restricted to these two choices, thereby simplifying binary division. Let’s assume that both the dividend and the divisor are positive and hence the quotient and the remainder are nonnegative. The division operands and both results are 32-bit values, and we will ignore the sign for now. A Division Algorithm and Hardware Figure 3.9 shows hardware to mimic our grammar school algorithm. We start with the 32-bit Quotient register set to 0. Each iteration of the algorithm needs to move the divisor to the right one digit, so we start with the divisor placed in the left half of the 64-bit Divisor register and shift it right 1 bit each step to align it with the dividend. The Remainder register is initialized with the dividend. dividend A number being divided. divisor A number that the dividend is divided by. quotient The primary result of a division; a number that when multiplied by the divisor and added to the remainder produces the dividend. remainder The secondary result of a division; a number that when added to the product of the quotient and the divisor produces the dividend. FIGURE 3.9 First version of the division hardware. The Divisor register, ALU, and Remainder register are all 64 bits wide, with only the Quotient register being 32 bits. The 32-bit divisor starts in the left half of the Divisor register and is shifted right 1 bit each iteration. The remainder is initialized with the dividend. Control decides when to shift the Divisor and Quotient registers and when to write the new value into the Remainder register. Divisor Shift right 64 bits 64-bit ALU Remainder Write 64 bits Control test Quotient Shift left 32 bits 3.4 Division 237
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238 Chapter 3 Arithmetic for Computers 33rd repetition? . Shift the Quotient register to the left, setting the new rightmost bit to 1 Remainder < 0 Remainder ≥ 0 Test Remainder Start 3. Shift the Divisor register right 1 bit No: < 33 repetitions Yes: 33 repetitions Done 1. Subtract the Divisor register from the Remainder register and place the result in the Remainder register 2b. Restore the original value by adding the Divisor register to the Remainder register and placing the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0 2a FIGURE 3.10 A division algorithm, using the hardware in Figure 3.9. If the remainder is positive, the divisor did go into the dividend, so step 2a generates a 1 in the quotient. A negative remainder after step 1 means that the divisor did not go into the dividend, so step 2b generates a 0 in the quotient and adds the divisor to the remainder, thereby reversing the subtraction of step 1. The final shift, in step 3, aligns the divisor properly, relative to the dividend for the next iteration. These steps are repeated 33 times.
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Figure 3.10 shows three steps of the first division algorithm. Unlike a human, the computer isn’t smart enough to know in advance whether the divisor is smaller than the dividend. It must first subtract the divisor in step 1; remember that this is how we performed the comparison in the set on less than instruction. If the result is positive, the divisor was smaller or equal to the dividend, so we generate a 1 in the quotient (step 2a). If the result is negative, the next step is to restore the original value by adding the divisor back to the remainder and generate a 0 in the quotient (step 2b). The divisor is shifted right and then we iterate again. The remainder and quotient will be found in their namesake registers after the iterations are complete. A Divide Algorithm Using a 4-bit version of the algorithm to save pages, let’s try dividing 7ten by 2ten, or 0000 0111two by 0010two. Figure 3.11 shows the value of each register for each of the steps, with the quotient being 3ten and the remainder 1ten. Notice that the test in step 2 of whether the remainder is positive or negative simply tests whether the sign bit of the Remainder register is a 0 or 1. The surprising requirement of this algorithm is that it takes n + 1 steps to get the proper quotient and remainder. This algorithm and hardware can be refined to be faster and cheaper. The speed- up comes from shifting the operands and the quotient simultaneously with the subtraction. This refinement halves the width of the adder and registers by noticing where there are unused portions of registers and adders. Figure 3.12 shows the revised hardware. Signed Division So far, we have ignored signed numbers in division. The simplest solution is to remember the signs of the divisor and dividend and then negate the quotient if the signs disagree. Elaboration: The one complication of signed division is that we must also set the sign of the remainder. Remember that the following equation must always hold: Dividend = Quotient × Divisor + Remainder To understand how to set the sign of the remainder, let’s look at the example of dividing all the combinations of ±7ten by ±2ten. The first case is easy: +7 ÷ +2: Quotient = +3, Remainder = +1 EXAMPLE ANSWER 3.4 Division 239
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240 Chapter 3 Arithmetic for Computers Checking the results: 7 = 3 × 2 + (+1) = 6 + 1 If we change the sign of the dividend, the quotient must change as well: –7 ÷ +2: Quotient = –3 Iteration Step Quotient Divisor Remainder 0 Initial values 0000 0010 0000 0000 0111 1 1: Rem = Rem – Div 0000 0010 0000 1110 0111 2b: Rem < 0 ⇒ +Div, sll Q, Q0 = 0 0000 0010 0000 0000 0111 3: Shift Div right 0000 0001 0000 0000 0111 2 1: Rem = Rem – Div 0000 0001 0000 1111 0111 2b: Rem < 0 ⇒ +Div, sll Q, Q0 = 0 0000 0001 0000 0000 0111 3: Shift Div right 0000 0000 1000 0000 0111 3 1: Rem = Rem – Div 0000 0000 1000 1111 1111 2b: Rem < 0 ⇒ +Div, sll Q, Q0 = 0 0000 0000 1000 0000 0111 3: Shift Div right 0000 0000 0100 0000 0111 4 1: Rem = Rem – Div 0000 0000 0100 0000 0011 2a: Rem ≥ 0 ⇒ sll Q, Q0 = 1 0001 0000 0100 0000 0011 3: Shift Div right 0001 0000 0010 0000 0011 5 1: Rem = Rem – Div 0001 0000 0010 0000 0001 2a: Rem ≥ 0 ⇒ sll Q, Q0 = 1 0011 0000 0010 0000 0001 3: Shift Div right 0011 0000 0001 0000 0001 FIGURE 3.11 Division example using the algorithm in Figure 3.10. The bit examined to determine the next step is circled in color. FIGURE 3.12 An improved version of the division hardware. The Divisor register, ALU, and Quotient register are all 32 bits wide, with only the Remainder register left at 64 bits. Compared to Figure 3.9, the ALU and Divisor registers are halved and the remainder is shifted left. This version also combines the Quotient register with the right half of the Remainder register. (As in Figure 3.6, the Remainder register should really be 65 bits to make sure the carry out of the adder is not lost.) Divisor 32 bits 32-bit ALU Remainder Write 64 bits Control test Shift left Shift right
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Rewriting our basic formula to calculate the remainder: Remainder = (Dividend – Quotient × Divisor) = –7 – (–3 × +2) = –7–(–6) = –1 So, –7 ÷ +2: Quotient = –3, Remainder = –1 Checking the results again: –7 = –3 × 2 + (–1) = – 6 – 1 The reason the answer isn’t a quotient of –4 and a remainder of +1, which would also fit this formula, is that the absolute value of the quotient would then change depending on the sign of the dividend and the divisor! Clearly, if –(x ÷ y) ≠ (–x) ÷ y programming would be an even greater challenge. This anomalous behavior is avoided by following the rule that the dividend and remainder must have the same signs, no matter what the signs of the divisor and quotient. We calculate the other combinations by following the same rule: +7 ÷ –2: Quotient = –3, Remainder = +1 –7 ÷ –2: Quotient = +3, Remainder = –1 Thus the correctly signed division algorithm negates the quotient if the signs of the operands are opposite and makes the sign of the nonzero remainder match the dividend. Faster Division We used many adders to speed up multiply, but we cannot do the same trick for divide. The reason is that we need to know the sign of the difference before we can perform the next step of the algorithm, whereas with multiply we could calculate the 32 partial products immediately. There are techniques to produce more than one bit of the quotient per step. The SRT division technique tries to guess several quotient bits per step, using a table lookup based on the upper bits of the dividend and remainder. It relies on subsequent steps to correct wrong guesses. A typical value today is 4 bits. The key is guessing the value to subtract. With binary division, there is only a single choice. These algorithms use 6 bits from the remainder and 4 bits from the divisor to index a table that determines the guess for each step. The accuracy of this fast method depends on having proper values in the lookup table. The fallacy on page 276 in Section 3.8 shows what can happen if the table is incorrect. Divide in MIPS You may have already observed that the same sequential hardware can be used for both multiply and divide in Figures 3.6 and 3.12. The only requirement is a 64-bit register that can shift left or right and a 32-bit ALU that adds or subtracts. Hence, MIPS uses the 32-bit Hi and 32-bit Lo registers for both multiply and divide. 3.4 Division 241
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242 Chapter 3 Arithmetic for Computers As we might expect from the algorithm above, Hi contains the remainder, and Lo contains the quotient after the divide instruction completes. To handle both signed integers and unsigned integers, MIPS has two instruc- tions: divide (div) and divide unsigned (divu). The MIPS assembler allows divide instructions to specify three registers, generating the mflo or mfhi instructions to place the desired result into a general-purpose register. Summary The common hardware support for multiply and divide allows MIPS to provide a single pair of 32-bit registers that are used both for multiply and divide. Figure 3.13 summarizes the additions to the MIPS architecture for the last two sections. MIPS divide instructions ignore overflow, so software must determine whether the quotient is too large. In addition to overflow, division can also result in an improper calculation: division by 0. Some computers distinguish these two anomalous events. MIPS software must check the divisor to discover division by 0 as well as overflow. Elaboration: An even faster algorithm does not immediately add the divisor back if the remainder is negative. It simply adds the dividend to the shifted remainder in the following step, since (r + d) × 2 – d = r × 2 + d × 2 – d = r × 2 + d. This nonrestoring division algorithm, which takes 1 clock cycle per step, is explored further in the exercises; the algorithm here is called restoring division. A third algorithm that doesn’t save the result of the subtract if its negative is called a nonperforming division algorithm. It averages one-third fewer arithmetic operations. 3.5 Floating Point Going beyond signed and unsigned integers, programming languages support numbers with fractions, which are called reals in mathematics. Here are some examples of reals: 3.14159265 . . .ten (pi) 2.71828 . . .ten (e) 0.000000001ten or 1.0ten × 10-9 (seconds in a nanosecond) 3,155,760,000ten or 3.15576ten × 109 (seconds in a typical century) Hardware/ Software Interface Speed gets you nowhere if you’re headed the wrong way. American proverb
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MIPS assembly language Category Instruction Example Meaning Comments Arithmetic add add $s1,$s2,$s3 $s1 = $s2 + $s3 Three operands; overflow detected subtract sub $s1,$s2,$s3 $s1 = $s2 – $s3 Three operands; overflow detected add immediate addi $s1,$s2,100 $s1 = $s2 + 100 + constant; overflow detected add unsigned addu $s1,$s2,$s3 $s1 = $s2 + $s3 Three operands; overflow undetected subtract unsigned subu $s1,$s2,$s3 $s1 = $s2 – $s3 Three operands; overflow undetected add immediate unsigned addiu $s1,$s2,100 $s1 = $s2 + 100 + constant; overflow undetected move from coprocessor register mfc0 $s1,$epc $s1 = $epc Copy Exception PC + special regs multiply mult $s2,$s3 Hi, Lo = $s2 × $s3 64-bit signed product in Hi, Lo multiply unsigned multu $s2,$s3 Hi, Lo = $s2 × $s3 64-bit unsigned product in Hi, Lo divide div $s2,$s3 Lo = $s2 / $s3, Hi = $s2 mod $s3 Lo = quotient, Hi = remainder divide unsigned divu $s2,$s3 Lo = $s2 / $s3, Hi = $s2 mod $s3 Unsigned quotient and remainder move from Hi mfhi $s1 $s1 = Hi Used to get copy of Hi move from Lo mflo $s1 $s1 = Lo Used to get copy of Lo Data transfer load word lw $s1,20($s2) $s1 = Memory[$s2 + 20] Word from memory to register store word sw $s1,20($s2) Memory[$s2 + 20] = $s1 Word from register to memory load half unsigned lhu $s1,20($s2) $s1 = Memory[$s2 + 20] Halfword memory to register store half sh $s1,20($s2) Memory[$s2 + 20] = $s1 Halfword register to memory load byte unsigned lbu $s1,20($s2) $s1 = Memory[$s2 + 20] Byte from memory to register store byte sb $s1,20($s2) Memory[$s2 + 20] = $s1 Byte from register to memory load linked word ll $s1,20($s2) $s1 = Memory[$s2 + 20] Load word as 1st half of atomic swap store conditional word sc $s1,20($s2) Memory[$s2+20]=$s1;$s1=0 or 1 Store word as 2nd half atomic swap load upper immediate lui $s1,100 $s1 = 100 * 216 Loads constant in upper 16 bits Logical AND AND $s1,$s2,$s3 $s1 = $s2 & $s3 Three reg. operands; bit-by-bit AND OR OR $s1,$s2,$s3 $s1 = $s2 | $s3 Three reg. operands; bit-by-bit OR NOR NOR $s1,$s2,$s3 $s1 = ~ ($s2 |$s3) Three reg. operands; bit-by-bit NOR AND immediate ANDi $s1,$s2,100 $s1 = $s2 & 100 Bit-by-bit AND with constant OR immediate ORi $s1,$s2,100 $s1 = $s2 | 100 Bit-by-bit OR with constant shift left logical sll $s1,$s2,10 $s1 = $s2 << 10 Shift left by constant shift right logical srl $s1,$s2,10 $s1 = $s2 >> 10 Shift right by constant Condi- tional branch branch on equal beq $s1,$s2,25 if ($s1 == $s2) go to PC + 4 + 100 Equal test; PC-relative branch branch on not equal bne $s1,$s2,25 if ($s1 != $s2) go to PC + 4 + 100 Not equal test; PC-relative set on less than slt $s1,$s2,$s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0 Compare less than; two’s complement set less than immediate slti $s1,$s2,100 if ($s2 < 100) $s1 = 1; else $s1=0 Compare < constant; two’s complement set less than unsigned sltu $s1,$s2,$s3 if ($s2 < $s3) $s1 = 1; else $s1=0 Compare less than; natural numbers set less than immediate unsigned sltiu $s1,$s2,100 if ($s2 < 100) $s1 = 1; else $s1 = 0 Compare < constant; natural numbers Uncondi- tional jump jump j 2500 go to 10000 Jump to target address jump register jr $ra go to $ra For switch, procedure return jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call FIGURE 3.13 MIPS core architecture. The memory and registers of the MIPS architecture are not included for space reasons, but this section added the Hi and Lo registers to support multiply and divide. MIPS machine language is listed in the MIPS Reference Data Card at the front of this book. 3.5 Floating Point 243
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244 Chapter 3 Arithmetic for Computers Notice that in the last case, the number didn’t represent a small fraction, but it was bigger than we could represent with a 32-bit signed integer. The alternative notation for the last two numbers is called scientific notation, which has a single digit to the left of the decimal point. A number in scientific notation that has no leading 0s is called a normalized number, which is the usual way to write it. For example, 1.0ten × 10-9 is in normalized scientific notation, but 0.1ten × 10-8 and 10.0ten × 10 -10 are not. Just as we can show decimal numbers in scientific notation, we can also show binary numbers in scientific notation: 1.0two × 2-1 To keep a binary number in normalized form, we need a base that we can increase or decrease by exactly the number of bits the number must be shifted to have one nonzero digit to the left of the decimal point. Only a base of 2 fulfills our need. Since the base is not 10, we also need a new name for decimal point; binary point will do fine. Computer arithmetic that supports such numbers is called floating point because it represents numbers in which the binary point is not fixed, as it is for integers. The programming language C uses the name float for such numbers. Just as in scientific notation, numbers are represented as a single nonzero digit to the left of the binary point. In binary, the form is 1.xxxxxxxxxtwo × 2yyyy (Although the computer represents the exponent in base 2 as well as the rest of the number, to simplify the notation we show the exponent in decimal.) A standard scientific notation for reals in normalized form offers three advantages. It simplifies exchange of data that includes floating-point numbers; it simplifies the floating-point arithmetic algorithms to know that numbers will always be in this form; and it increases the accuracy of the numbers that can be stored in a word, since the unnecessary leading 0s are replaced by real digits to the right of the binary point. Floating-Point Representation A designer of a floating-point representation must find a compromise between the size of the fraction and the size of the exponent, because a fixed word size means you must take a bit from one to add a bit to the other. This tradeoff is between precision and range: increasing the size of the fraction enhances the precision of the fraction, while increasing the size of the exponent increases the range of numbers that can be represented. As our design guideline from Chapter 2 reminds us, good design demands good compromise. Floating-point numbers are usually a multiple of the size of a word. The representation of a MIPS floating-point number is shown below, where s is the sign of the floating-point number (1 meaning negative), exponent is the value of the 8-bit exponent field (including the sign of the exponent), and fraction is the scientific notation A notation that renders numbers with a single digit to the left of the decimal point. normalized A number in floating-point notation that has no leading 0s. floating point Computer arithmetic that represents numbers in which the binary point is not fixed. fraction The value, generally between 0 and 1, placed in the fraction field. exponent In the numerical representation system of floating-point arithmetic, the value that is placed in the exponent field.
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23-bit number. This representation is called sign and magnitude, since the sign is a separate bit from the rest of the number. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s exponent fraction 1 bit 8 bits 23 bits In general, floating-point numbers are of the form (-1)S × F × 2E F involves the value in the fraction field and E involves the value in the exponent field; the exact relationship to these fields will be spelled out soon. (We will shortly see that MIPS does something slightly more sophisticated.) These chosen sizes of exponent and fraction give MIPS computer arithmetic an extraordinary range. Fractions almost as small as 2.0ten × 10-38 and numbers almost as large as 2.0ten × 1038 can be represented in a computer. Alas, extraordinary differs from infinite, so it is still possible for numbers to be too large. Thus, overflow interrupts can occur in floating-point arithmetic as well as in integer arithmetic. Notice that overflow here means that the exponent is too large to be represented in the exponent field. Floating point offers a new kind of exceptional event as well. Just as programmers will want to know when they have calculated a number that is too large to be represented, they will want to know if the nonzero fraction they are calculating has become so small that it cannot be represented; either event could result in a program giving incorrect answers. To distinguish it from overflow, we call this event underflow. This situation occurs when the negative exponent is too large to fit in the exponent field. One way to reduce chances of underflow or overflow is to offer another format that has a larger exponent. In C this number is called double, and operations on doubles are called double precision floating-point arithmetic; single precision floating point is the name of the earlier format. The representation of a double precision floating-point number takes two MIPS words, as shown below, where s is still the sign of the number, exponent is the value of the 11-bit exponent field, and fraction is the 52-bit number in the fraction field. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s exponent fraction 1 bit 11 bits 20 bits fraction (continued) 32 bits MIPS double precision allows numbers almost as small as 2.0ten × 10-308 and almost as large as 2.0ten × 10308. Although double precision does increase the overflow (floating- point) A situation in which a positive exponent becomes too large to fit in the exponent field. underflow (floating- point) A situation in which a negative exponent becomes too large to fit in the exponent field. double precision A floating-point value represented in two 32-bit words. single precision A floating-point value represented in a single 32-bit word. 3.5 Floating Point 245
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246 Chapter 3 Arithmetic for Computers exponent range, its primary advantage is its greater precision because of the much larger significand. These formats go beyond MIPS. They are part of the IEEE 754 floating-point standard, found in virtually every computer invented since 1980. This standard has greatly improved both the ease of porting floating-point programs and the quality of computer arithmetic. To pack even more bits into the significand, IEEE 754 makes the leading 1-bit of normalized binary numbers implicit. Hence, the number is actually 24 bits long in single precision (implied 1 and a 23-bit fraction), and 53 bits long in double precision (1 + 52). To be precise, we use the term significand to represent the 24- or 53-bit number that is 1 plus the fraction, and fraction when we mean the 23- or 52-bit number. Since 0 has no leading 1, it is given the reserved exponent value 0 so that the hardware won’t attach a leading 1 to it. Thus 00 . . . 00two represents 0; the representation of the rest of the numbers uses the form from before with the hidden 1 added: (-1)S × (1 + Fraction) × 2E where the bits of the fraction represent a number between 0 and 1 and E specifies the value in the exponent field, to be given in detail shortly. If we number the bits of the fraction from left to right s1, s2, s3, . . . , then the value is (-1)S × (1 + (s1 × 2-1) + (s2 × 2-2) + (s3 × 2-3) + (s4 × 2-4) + …) × 2E Figure 3.14 shows the encodings of IEEE 754 floating-point numbers. Other features of IEEE 754 are special symbols to represent unusual events. For example, instead of interrupting on a divide by 0, software can set the result to a bit pattern representing +∞ or -∞; the largest exponent is reserved for these special symbols. When the programmer prints the results, the program will print an infinity symbol. (For the mathematically trained, the purpose of infinity is to form topological closure of the reals.) Single precision Double precision Object represented Exponent Fraction Exponent Fraction 0 0 0 0 0 0 Nonzero 0 Nonzero ± denormalized number 1–254 Anything 1–2046 Anything ± floating-point number 255 0 2047 0 ± infinity 255 Nonzero 2047 Nonzero NaN (Not a Number) FIGURE 3.14 IEEE 754 encoding of floating-point numbers. A separate sign bit determines the sign. Denormalized numbers are described in the Elaboration on page 270. This information is also found in Column 4 of the MIPS Reference Data Card at the front of this book.
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IEEE 754 even has a symbol for the result of invalid operations, such as 0/0 or subtracting infinity from infinity. This symbol is NaN, for Not a Number. The purpose of NaNs is to allow programmers to postpone some tests and decisions to a later time in the program when they are convenient. The designers of IEEE 754 also wanted a floating-point representation that could be easily processed by integer comparisons, especially for sorting. This desire is why the sign is in the most significant bit, allowing a quick test of less than, greater than, or equal to 0. (It’s a little more complicated than a simple integer sort, since this notation is essentially sign and magnitude rather than two’s complement.) Placing the exponent before the significand also simplifies the sorting of floating-point numbers using integer comparison instructions, since numbers with bigger exponents look larger than numbers with smaller exponents, as long as both exponents have the same sign. Negative exponents pose a challenge to simplified sorting. If we use two’s complement or any other notation in which negative exponents have a 1 in the most significant bit of the exponent field, a negative exponent will look like a big number. For example, 1.0two × 2-1 would be represented as 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . (Remember that the leading 1 is implicit in the significand.) The value 1.0two × 2+1 would look like the smaller binary number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . The desirable notation must therefore represent the most negative exponent as 00 . . . 00two and the most positive as 11 . . . 11two. This convention is called biased notation, with the bias being the number subtracted from the normal, unsigned representation to determine the real value. IEEE 754 uses a bias of 127 for single precision, so an exponent of -1 is represented by the bit pattern of the value -1 + 127ten, or 126ten = 0111 1110two, and +1 is represented by 1 + 127, or 128ten = 1000 0000two. The exponent bias for double precision is 1023. Biased exponent means that the value represented by a floating-point number is really (-1)S × (1 + Fraction) × 2(Exponent - Bias) The range of single precision numbers is then from as small as ±1.0000 0000 0000 0000 0000 000two × 2-126 to as large as ±1.1111 1111 1111 1111 1111 111two × 2+127. 3.5 Floating Point 247
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248 Chapter 3 Arithmetic for Computers Let’s show the representation. Floating-Point Representation Show the IEEE 754 binary representation of the number -0.75ten in single and double precision. The number -0.75ten is also -3/4ten or -3/22 ten It is also represented by the binary fraction -11two/22 ten or -0.11two In scientific notation, the value is -0.11two × 20 and in normalized scientific notation, it is -1.1two × 2-1 The general representation for a single precision number is (-1)S × (1 + Fraction) × 2(Exponent - 127) Subtracting the bias 127 from the exponent of -1.1two × 2-1 yields (-1)1 × (1 + .1000 0000 0000 0000 0000 000two) × 2(126-127) The single precision binary representation of -0.75ten is then 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 bit 8 bits 23 bits EXAMPLE ANSWER
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The double precision representation is (-1)1 × (1 + .1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000two) × 2(1022-1023) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 bit 11 bits 20 bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 bits Now let’s try going the other direction. Converting Binary to Decimal Floating Point What decimal number is represented by this single precision float? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . The sign bit is 1, the exponent field contains 129, and the fraction field contains 1 × 2-2 = 1/4, or 0.25. Using the basic equation, (-1)S × (1 + Fraction) × 2(Exponent - Bias) = (-1)1 × (1 + 0.25) × 2(129-127) = -1 × 1.25 × 22 = -1.25 × 4 = -5.0 In the next subsections, we will give the algorithms for floating-point addition and multiplication. At their core, they use the corresponding integer operations EXAMPLE ANSWER 3.5 Floating Point 249
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250 Chapter 3 Arithmetic for Computers on the significands, but extra bookkeeping is necessary to handle the exponents and normalize the result. We first give an intuitive derivation of the algorithms in decimal and then give a more detailed, binary version in the figures. Elaboration: In an attempt to increase range without removing bits from the signifi- cand, some computers before the IEEE 754 standard used a base other than 2. For example, the IBM 360 and 370 mainframe computers use base 16. Since changing the IBM exponent by one means shifting the significand by 4 bits, “normalized” base 16 numbers can have up to 3 leading bits of 0s! Hence, hexadecimal digits mean that up to 3 bits must be dropped from the significand, which leads to surprising problems in the accuracy of floating-point arithmetic. Recent IBM mainframes support IEEE 754 as well as the hex format. Floating-Point Addition Let’s add numbers in scientific notation by hand to illustrate the problems in floating-point addition: 9.999ten × 101 + 1.610ten × 10-1. Assume that we can store only four decimal digits of the significand and two decimal digits of the exponent. Step 1. To be able to add these numbers properly, we must align the decimal point of the number that has the smaller exponent. Hence, we need a form of the smaller number, 1.610ten × 10-1, that matches the larger exponent. We obtain this by observing that there are multiple representations of an unnormalized floating-point number in scientific notation: 1.610ten × 10-1 = 0.1610ten × 100 = 0.01610ten × 101 The number on the right is the version we desire, since its exponent matches the exponent of the larger number, 9.999ten × 101. Thus, the first step shifts the significand of the smaller number to the right until its corrected exponent matches that of the larger number. But we can represent only four decimal digits so, after shifting, the number is really 0.016ten × 101 Step 2. Next comes the addition of the significands: 9.999ten + 0.016ten 10.015ten The sum is 10.015ten × 101.
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Step 3. This sum is not in normalized scientific notation, so we need to adjust it: 10.015ten × 101 = 1.0015ten × 102 Thus, after the addition we may have to shift the sum to put it into normalized form, adjusting the exponent appropriately. This example shows shifting to the right, but if one number were positive and the other were negative, it would be possible for the sum to have many leading 0s, requiring left shifts. Whenever the exponent is increased or decreased, we must check for overflow or underflow—that is, we must make sure that the exponent still fits in its field. Step 4. Since we assumed that the significand can be only four digits long (excluding the sign), we must round the number. In our grammar school algorithm, the rules truncate the number if the digit to the right of the desired point is between 0 and 4 and add 1 to the digit if the number to the right is between 5 and 9. The number 1.0015ten × 102 is rounded to four digits in the significand to 1.002ten × 102 since the fourth digit to the right of the decimal point was between 5 and 9. Notice that if we have bad luck on rounding, such as adding 1 to a string of 9s, the sum may no longer be normalized and we would need to perform step 3 again. Figure 3.15 shows the algorithm for binary floating-point addition that follows this decimal example. Steps 1 and 2 are similar to the example just discussed: adjust the significand of the number with the smaller exponent and then add the two significands. Step 3 normalizes the results, forcing a check for overflow or underflow. The test for overflow and underflow in step 3 depends on the precision of the operands. Recall that the pattern of all 0 bits in the exponent is reserved and used for the floating-point representation of zero. Moreover, the pattern of all 1 bits in the exponent is reserved for indicating values and situations outside the scope of normal floating-point numbers (see the Elaboration on page 270). Thus, for single precision, the maximum exponent is 127, and the minimum exponent is -126. The limits for double precision are 1023 and -1022. 3.5 Floating Point 251
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252 Chapter 3 Arithmetic for Computers Still normalized? 4. Round the significand to the appropriate number of bits Yes Overflow or underflow? Start No Yes Done 1. Compare the exponents of the two numbers; shift the smaller number to the right until its exponent would match the larger exponent 2. Add the significands 3. Normalize the sum, either shifting right and incrementing the exponent or shifting left and decrementing the exponent No Exception FIGURE 3.15 Floating-point addition. The normal path is to execute steps 3 and 4 once, but if rounding causes the sum to be unnormalized, we must repeat step 3.
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Binary Floating-Point Addition Try adding the numbers 0.5ten and -0.4375ten in binary using the algorithm in Figure 3.15. Let’s first look at the binary version of the two numbers in normalized scien- tific notation, assuming that we keep 4 bits of precision: 0.5ten = 1/2ten = 1/21 ten = 0.1two = 0.1two × 20 = 1.000two × 2-1 -0.4375ten = -7/16ten = -7/24 ten = -0.0111two = -0.0111two × 20 = -1.110two × 2-2 Now we follow the algorithm: Step 1. The significand of the number with the lesser exponent (-1.11two × 2-2) is shifted right until its exponent matches the larger number: -1.110two × 2-2 = -0.111two × 2-1 Step 2. Add the significands: 1.000two × 2-1 + (-0.111two × 2-1) = 0.001two × 2-1 Step 3. Normalize the sum, checking for overflow or underflow: 0.001two × 2-1 = 0.010two × 2-2 = 0.100two × 2-3 = 1.000two × 2-4 Since 127 ≥ -4 ≥ -126, there is no overflow or underflow. (The biased exponent would be -4 + 127, or 123, which is between 1 and 254, the smallest and largest unreserved biased exponents.) Step 4. Round the sum: 1.000two × 2-4 The sum already fits exactly in 4 bits, so there is no change to the bits due to rounding. This sum is then 1.000two × 2-4 = 0.0001000two = 0.0001two = 1/24 ten = 1/16ten = 0.0625ten This sum is what we would expect from adding 0.5ten to -0.4375ten. EXAMPLE ANSWER 3.5 Floating Point 253
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254 Chapter 3 Arithmetic for Computers Compare exponents Small ALU Exponent difference Control Exponent Sign Fraction Big ALU Exponent Sign Fraction 0 1 0 1 0 1 Shift right 0 1 0 1 Increment or decrement Shift left or right Rounding hardware Exponent Sign Fraction Shift smaller number right Add Normalize Round FIGURE 3.16 Block diagram of an arithmetic unit dedicated to floating-point addition. The steps of Figure 3.15 correspond to each block, from top to bottom. First, the exponent of one operand is subtracted from the other using the small ALU to determine which is larger and by how much. This difference controls the three multiplexors; from left to right, they select the larger exponent, the significand of the smaller number, and the significand of the larger number. The smaller significand is shifted right, and then the significands are added together using the big ALU. The normalization step then shifts the sum left or right and increments or decrements the exponent. Rounding then creates the final result, which may require normalizing again to produce the final result. Many computers dedicate hardware to run floating-point operations as fast as possible. Figure 3.16 sketches the basic organization of hardware for floating-point addition.
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Floating-Point Multiplication Now that we have explained floating-point addition, let’s try floating-point multiplication. We start by multiplying decimal numbers in scientific notation by hand: 1.110ten × 1010 × 9.200ten × 10-5. Assume that we can store only four digits of the significand and two digits of the exponent. Step 1. Unlike addition, we calculate the exponent of the product by simply adding the exponents of the operands together: New exponent = 10 + (-5) = 5 Let’s do this with the biased exponents as well to make sure we obtain the same result: 10 + 127 = 137, and -5 + 127 = 122, so New exponent = 137 + 122 = 259 This result is too large for the 8-bit exponent field, so something is amiss! The problem is with the bias because we are adding the biases as well as the exponents: New exponent = (10 + 127) + (-5 + 127) = (5 + 2 × 127) = 259 Accordingly, to get the correct biased sum when we add biased numbers, we must subtract the bias from the sum: New exponent = 137 + 122 - 127 = 259 - 127 = 132 = (5 + 127) and 5 is indeed the exponent we calculated initially. Step 2. Next comes the multiplication of the significands: 1.110ten x 9.200ten 0000 0000 2220 9990 10212000ten There are three digits to the right of the decimal point for each operand, so the decimal point is placed six digits from the right in the product significand: 10.212000ten 3.5 Floating Point 255
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256 Chapter 3 Arithmetic for Computers Assuming that we can keep only three digits to the right of the decimal point, the product is 10.212 × 105. Step 3. This product is unnormalized, so we need to normalize it: 10.212ten × 105 = 1.0212ten × 106 Thus, after the multiplication, the product can be shifted right one digit to put it in normalized form, adding 1 to the exponent. At this point, we can check for overflow and underflow. Underflow may occur if both operands are small—that is, if both have large negative exponents. Step 4. We assumed that the significand is only four digits long (excluding the sign), so we must round the number. The number 1.0212ten × 106 is rounded to four digits in the significand to 1.021ten × 106 Step 5. The sign of the product depends on the signs of the original operands. If they are both the same, the sign is positive; otherwise, it’s negative. Hence, the product is +1.021ten × 106 The sign of the sum in the addition algorithm was determined by addition of the significands, but in multiplication, the sign of the product is determined by the signs of the operands. Once again, as Figure 3.17 shows, multiplication of binary floating-point numbers is quite similar to the steps we have just completed. We start with calculating the new exponent of the product by adding the biased exponents, being sure to subtract one bias to get the proper result. Next is multiplication of significands, followed by an optional normalization step. The size of the exponent is checked for overflow or underflow, and then the product is rounded. If rounding leads to further normalization, we once again check for exponent size. Finally, set the sign bit to 1 if the signs of the operands were different (negative product) or to 0 if they were the same (positive product). Binary Floating-Point Multiplication Let’s try multiplying the numbers 0.5ten and -0.4375ten, using the steps in Figure 3.17. EXAMPLE
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In binary, the task is multiplying 1.000two × 2-1 by - 1.110two × 2-2. Step 1. Adding the exponents without bias: -1 + (-2) = -3 or, using the biased representation: (-1 + 127) + (-2 + 127) - 127 = (-1 - 2) + (127 + 127 - 127) = -3 + 127 = 124 Step 2. Multiplying the significands: 1.000two x 1.110two 0000 1000 1000 1000 1110000two The product is 1.110000two × 2-3, but we need to keep it to 4 bits, so it is 1.110two × 2-3. Step 3. Now we check the product to make sure it is normalized, and then check the exponent for overflow or underflow. The product is already normalized and, since 127 ≥ -3 ≥ -126, there is no overflow or underflow. (Using the biased representation, 254 ≥ 124 ≥ 1, so the exponent fits.) Step 4. Rounding the product makes no change: 1.110two × 2-3 Step 5. Since the signs of the original operands differ, make the sign of the product negative. Hence, the product is -1.110two × 2-3 Converting to decimal to check our results: -1.110two × 2-3 = -0.001110two = -0.00111two = -7/25 ten = -7/32ten = -0.21875ten The product of 0.5ten and - 0.4375ten is indeed - 0.21875ten. ANSWER 3.5 Floating Point 257
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258 Chapter 3 Arithmetic for Computers 5. Set the sign of the product to positive if the signs of the original operands are the same; if they differ make the sign negative Still normalized? 4. Round the significand to the appropriate number of bits Yes Overflow or underflow? Start No Yes Done 1. Add the biased exponents of the two numbers, subtracting the bias from the sum to get the new biased exponent 2. Multiply the significands 3. Normalize the product if necessary, shifting it right and incrementing the exponent No Exception FIGURE 3.17 Floating-point multiplication. The normal path is to execute steps 3 and 4 once, but if rounding causes the sum to be unnormalized, we must repeat step 3.
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Floating-Point Instructions in MIPS MIPS supports the IEEE 754 single precision and double precision formats with these instructions: ■ ■Floating-point addition, single (add.s) and addition, double (add.d) ■ ■Floating-point subtraction, single (sub.s) and subtraction, double (sub.d) ■ ■Floating-point multiplication, single (mul.s) and multiplication, double (mul.d) ■ ■Floating-point division, single (div.s) and division, double (div.d) ■ ■Floating-point comparison, single (c.x.s) and comparison, double (c.x.d), where x may be equal (eq), not equal (neq), less than (lt), less than or equal (le), greater than (gt), or greater than or equal (ge) ■ ■Floating-point branch, true (bc1t) and branch, false (bc1f) Floating-point comparison sets a bit to true or false, depending on the comparison condition, and a floating-point branch then decides whether or not to branch, depending on the condition. The MIPS designers decided to add separate floating-point registers—called $f0, $f1, $f2, . . .—used either for single precision or double precision. Hence, they included separate loads and stores for floating-point registers: lwc1 and swc1. The base registers for floating-point data transfers remain integer registers. The MIPS code to load two single precision numbers from memory, add them, and then store the sum might look like this: lwc1 $f4,x($sp) # Load 32-bit F.P. number into F4 lwc1 $f6,y($sp) # Load 32-bit F.P. number into F6 add.s $f2,$f4,$f6 # F2 = F4 + F6 single precision swc1 $f2,z($sp) # Store 32-bit F.P. number from F2 A double precision register is really an even-odd pair of single precision registers, using the even register number as its name. Thus, the pair of single precision registers $f2 and $f3 also form the double precision register named $f2. Figure 3.18 summarizes the floating-point portion of the MIPS architecture revealed in this chapter, with the additions to support floating point shown in color. Similar to Figure 2.19 in Chapter 2, Figure 3.19 shows the encoding of these instructions. 3.5 Floating Point 259
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260 Chapter 3 Arithmetic for Computers MIPS floating-point operands Name Example Comments 32 floating- point registers $f0, $f1, $f2, . . . , $f31 MIPS floating-point registers are used in pairs for double precision numbers. 230 memory words Memory[0], Memory[4], . . . , Memory[4294967292] Accessed only by data transfer instructions. MIPS uses byte addresses, so sequential word addresses differ by 4. Memory holds data structures, such as arrays, and spilled registers, such as those saved on procedure calls. MIPS floating-point assembly language Category Instruction Example Meaning Comments Arithmetic FP add single add.s $f2,$f4,$f6 $f2 = $f4 + $f6 FP add (single precision) FP subtract single sub.s $f2,$f4,$f6 $f2 = $f4 – $f6 FP sub (single precision) FP multiply single mul.s $f2,$f4,$f6 $f2 = $f4 × $f6 FP multiply (single precision) FP divide single div.s $f2,$f4,$f6 $f2 = $f4 / $f6 FP divide (single precision) FP add double add.d $f2,$f4,$f6 $f2 = $f4 + $f6 FP add (double precision) FP subtract double sub.d $f2,$f4,$f6 $f2 = $f4 – $f6 FP sub (double precision) FP multiply double mul.d $f2,$f4,$f6 $f2 = $f4 × $f6 FP multiply (double precision) FP divide double div.d $f2,$f4,$f6 $f2 = $f4 / $f6 FP divide (double precision) Data transfer load word copr. 1 lwc1 $f1,100($s2) $f1 = Memory[$s2 + 100] 32-bit data to FP register store word copr. 1 swc1 $f1,100($s2) Memory[$s2 + 100] = $f1 32-bit data to memory Condi- tional branch branch on FP true bc1t 25 if (cond == 1) go to PC + 4 + 100 PC-relative branch if FP cond. branch on FP false bc1f 25 if (cond == 0) go to PC + 4 + 100 PC-relative branch if not cond. FP compare single (eq,ne,lt,le,gt,ge) c.lt.s $f2,$f4 if ($f2 < $f4) cond = 1; else cond = 0 FP compare less than single precision FP compare double (eq,ne,lt,le,gt,ge) c.lt.d $f2,$f4 if ($f2 < $f4) cond = 1; else cond = 0 FP compare less than double precision MIPS floating-point machine language Name Format Example Comments add.s R 17 16 6 4 2 0 add.s $f2,$f4,$f6 sub.s R 17 16 6 4 2 1 sub.s $f2,$f4,$f6 mul.s R 17 16 6 4 2 2 mul.s $f2,$f4,$f6 div.s R 17 16 6 4 2 3 div.s $f2,$f4,$f6 add.d R 17 17 6 4 2 0 add.d $f2,$f4,$f6 sub.d R 17 17 6 4 2 1 sub.d $f2,$f4,$f6 mul.d R 17 17 6 4 2 2 mul.d $f2,$f4,$f6 div.d R 17 17 6 4 2 3 div.d $f2,$f4,$f6 lwc1 I 49 20 2 100 lwc1 $f2,100($s4) swc1 I 57 20 2 100 swc1 $f2,100($s4) bc1t I 17 8 1 25 bc1t 25 bc1f I 17 8 0 25 bc1f 25 c.lt.s R 17 16 4 2 0 60 c.lt.s $f2,$f4 c.lt.d R 17 17 4 2 0 60 c.lt.d $f2,$f4 Field size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits FIGURE 3.18 MIPS floating-point architecture revealed thus far. See Appendix B, Section B.10, for more detail. This information is also found in column 2 of the MIPS Reference Data Card at the front of this book.
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op(31:26): 28–26 31–29 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111) 0(000) Rfmt Bltz/gez j jal beq bne blez bgtz 1(001) addi addiu slti sltiu ANDi ORi xORi lui 2(010) TLB FlPt 3(011) 4(100) lb lh lwl lw lbu lhu lwr 5(101) sb sh swl sw swr 6(110) lwc0 lwc1 7(111) swc0 swc1 op(31:26) = 010001 (FlPt), (rt(16:16) = 0 => c = f, rt(16:16) = 1 => c = t), rs(25:21): 23–21 25–24 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111) 0(00) mfc1 cfc1 mtc1 ctc1 1(01) bc1.c 2(10) f = single f = double 3(11) op(31:26) = 010001 (FlPt), (f above: 10000 => f = s, 10001 => f = d), funct(5:0): 2–0 5–3 0(000) 1(001) 2(010) 3(011) 4(100) 5(101) 6(110) 7(111) 0(000) add.f sub.f mul.f div.f abs.f mov.f neg.f 1(001) 2(010) 3(011) 4(100) cvt.s.f cvt.d.f cvt.w.f 5(101) 6(110) c.f.f c.un.f c.eq.f c.ueq.f c.olt.f c.ult.f c.ole.f c.ule.f 7(111) c.sf.f c.ngle.f c.seq.f c.ngl.f c.lt.f c.nge.f c.le.f c.ngt.f FIGURE 3.19 MIPS floating-point instruction encoding. This notation gives the value of a field by row and by column. For example, in the top portion of the figure, lw is found in row number 4 (100two for bits 31–29 of the instruction) and column number 3 (011two for bits 28–26 of the instruction), so the corresponding value of the op field (bits 31–26) is 100011two. Underscore means the field is used elsewhere. For example, FlPt in row 2 and column 1 (op = 010001two) is defined in the bottom part of the figure. Hence sub.f in row 0 and column 1 of the bottom section means that the funct field (bits 5–0) of the instruction) is 000001two and the op field (bits 31–26) is 010001two. Note that the 5-bit rs field, specified in the middle portion of the figure, determines whether the operation is single precision (f = s, so rs = 10000) or double precision (f = d, so rs = 10001). Similarly, bit 16 of the instruction determines if the bc1.c instruction tests for true (bit 16 = 1 =>bc1.t) or false (bit 16 = 0 =>bc1.f). Instructions in color are described in Chapter 2 or this chapter, with Appendix B covering all instructions. This information is also found in column 2 of the MIPS Reference Data Card at the front of this book. 3.5 Floating Point 261
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262 Chapter 3 Arithmetic for Computers One issue that architects face in supporting floating-point arithmetic is whether to use the same registers used by the integer instructions or to add a special set for floating point. Because programs normally perform integer operations and floating-point operations on different data, separating the registers will only slightly increase the number of instructions needed to execute a program. The major impact is to create a separate set of data transfer instructions to move data between floating-point registers and memory. The benefits of separate floating-point registers are having twice as many registers without using up more bits in the instruction format, having twice the register bandwidth by having separate integer and floating-point register sets, and being able to customize registers to floating point; for example, some computers convert all sized operands in registers into a single internal format. Compiling a Floating-Point C Program into MIPS Assembly Code Let’s convert a temperature in Fahrenheit to Celsius: float f2c (float fahr) { return ((5.0/9.0) * (fahr – 32.0)); } Assume that the floating-point argument fahr is passed in $f12 and the result should go in $f0. (Unlike integer registers, floating-point register 0 can contain a number.) What is the MIPS assembly code? We assume that the compiler places the three floating-point constants in memory within easy reach of the global pointer $gp. The first two instruc tions load the constants 5.0 and 9.0 into floating-point registers: f2c: lwc1 $f16,const5($gp) # $f16 = 5.0 (5.0 in memory) lwc1 $f18,const9($gp) # $f18 = 9.0 (9.0 in memory) They are then divided to get the fraction 5.0/9.0: div.s $f16, $f16, $f18 # $f16 = 5.0 / 9.0 Hardware/ Software Interface EXAMPLE ANSWER
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(Many compilers would divide 5.0 by 9.0 at compile time and save the single constant 5.0/9.0 in memory, thereby avoiding the divide at runtime.) Next, we load the constant 32.0 and then subtract it from fahr ($f12): lwc1 $f18, const32($gp)# $f18 = 32.0 sub.s $f18, $f12, $f18 # $f18 = fahr – 32.0 Finally, we multiply the two intermediate results, placing the product in $f0 as the return result, and then return mul.s $f0, $f16, $f18 # $f0 = (5/9)*(fahr – 32.0) jr $ra # return Now let’s perform floating-point operations on matrices, code commonly found in scientific programs. Compiling Floating-Point C Procedure with Two-Dimensional Matrices into MIPS Most floating-point calculations are performed in double precision. Let’s per form matrix multiply of X = X + Y * Z. Let’s assume X, Y, and Z are all square matrices with 32 elements in each dimension. void mm (double x[][], double y[][], double z[][]) { int i, j, k; for (i = 0; i != 32; i = i + 1) for (j = 0; j != 32; j = j + 1) for (k = 0; k != 32; k = k + 1) x[i][j] = x[i][j] + y[i][k] * z[k][j]; } The array starting addresses are parameters, so they are in $a0, $a1, and $a2. Assume that the integer variables are in $s0, $s1, and $s2, respectively. What is the MIPS assembly code for the body of the procedure? Note that x[i][j] is used in the innermost loop above. Since the loop index is k, the index does not affect x[i][j], so we can avoid loading and storing x[i][j] each iteration. Instead, the compiler loads x[i][j] into a register outside the loop, accumulates the sum of the products of y[i][k] and z[k][j] in that same register, and then stores the sum into x[i][j] upon termination of the innermost loop. We keep the code simpler by using the assembly language pseudoinstructions li (which loads a constant into a register), and l.d and s.d (which the assembler turns into a pair of data transfer instructions, lwc1 or swc1, to a pair of floating-point registers). EXAMPLE ANSWER 3.5 Floating Point 263
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264 Chapter 3 Arithmetic for Computers The body of the procedure starts with saving the loop termination value of 32 in a temporary register and then initializing the three for loop variables: mm:... li $t1, 32 # $t1 = 32 (row size/loop end) li $s0, 0 # i = 0; initialize 1st for loop L1: li $s1, 0 # j = 0; restart 2nd for loop L2: li $s2, 0 # k = 0; restart 3rd for loop To calculate the address of x[i][j], we need to know how a 32 × 32, two- dimensional array is stored in memory. As you might expect, its layout is the same as if there were 32 single-dimension arrays, each with 32 elements. So the first step is to skip over the i “single-dimensional arrays,” or rows, to get the one we want. Thus, we multiply the index in the first dimension by the size of the row, 32. Since 32 is a power of 2, we can use a shift instead: sll $t2, $s0, 5 # $t2 = i * 25 (size of row of x) Now we add the second index to select the jth element of the desired row: addu $t2, $t2, $s1 # $t2 = i * size(row) + j To turn this sum into a byte index, we multiply it by the size of a matrix element in bytes. Since each element is 8 bytes for double precision, we can instead shift left by 3: sll $t2, $t2, 3 # $t2 = byte offset of [i][j] Next we add this sum to the base address of x, giving the address of x[i][j], and then load the double precision number x[i][j] into $f4: addu $t2, $a0, $t2 # $t2 = byte address of x[i][j] l.d $f4, 0($t2) # $f4 = 8 bytes of x[i][j] The following five instructions are virtually identical to the last five: calcu late the address and then load the double precision number z[k][j]. L3: sll $t0, $s2, 5 # $t0 = k * 25 (size of row of z) addu $t0, $t0, $s1 # $t0 = k * size(row) + j sll $t0, $t0, 3 # $t0 = byte offset of [k][j] addu $t0, $a2, $t0 # $t0 = byte address of z[k][j] l.d $f16, 0($t0) # $f16 = 8 bytes of z[k][j] Similarly, the next five instructions are like the last five: calculate the address and then load the double precision number y[i][k].
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sll $t0, $s0, 5 # $t0 = i * 25 (size of row of y) addu $t0, $t0, $s2 # $t0 = i * size(row) + k sll $t0, $t0, 3 # $t0 = byte offset of [i][k] addu $t0, $a1, $t0 # $t0 = byte address of y[i][k] l.d $f18, 0($t0) # $f18 = 8 bytes of y[i][k] Now that we have loaded all the data, we are finally ready to do some floating-point operations! We multiply elements of y and z located in registers $f18 and $f16, and then accumulate the sum in $f4. mul.d $f16, $f18, $f16 # $f16 = y[i][k] * z[k][j] add.d $f4, $f4, $f16 # f4 = x[i][j]+ y[i][k] * z[k][j] The final block increments the index k and loops back if the index is not 32. If it is 32, and thus the end of the innermost loop, we need to store the sum accumulated in $f4 into x[i][j]. addiu $s2, $s2, 1 # $k k + 1 bne $s2, $t1, L3 # if (k != 32) go to L3 s.d $f4, 0($t2) # x[i][j] = $f4 Similarly, these final four instructions increment the index variable of the middle and outermost loops, looping back if the index is not 32 and exiting if the index is 32. addiu $s1, $s1, 1 # $j = j + 1 bne $s1, $t1, L2 # if (j != 32) go to L2 addiu $s0, $s0, 1 # $i = i + 1 bne $s0, $t1, L1 # if (i != 32) go to L1 ... Elaboration: The array layout discussed in the example, called row-major order, is used by C and many other programming languages. Fortran instead uses column-major order, whereby the array is stored column by column. Elaboration: Only 16 of the 32 MIPS floating-point registers could originally be used for double precision operations: $f0, $f2, $f4, ..., $f30. Double precision is computed using pairs of these single precision registers. The odd-numbered floating- point registers were used only to load and store the right half of 64-bit floating-point numbers. MIPS-32 added l.d and s.d to the instruction set. MIPS-32 also added “paired single” versions of all floating-point instructions, where a single instruction results in two parallel floating-point operations on two 32-bit operands inside 64-bit registers. For example, add.ps $f0, $f2, $f4 is equivalent to add.s $f0, $f2, $f4 followed by add.s $f1, $f3, $f5. 3.5 Floating Point 265
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266 Chapter 3 Arithmetic for Computers Elaboration: Another reason for separate integers and floating-point registers is that microprocessors in the 1980s didn’t have enough transistors to put the floating-point unit on the same chip as the integer unit. Hence, the floating-point unit, including the floating- point registers, was optionally available as a second chip. Such optional accelerator chips are called coprocessors, and explain the acronym for floating-point loads in MIPS: lwc1 means load word to coprocessor 1, the floating-point unit. (Coprocessor 0 deals with virtual memory, described in Chapter 5.) Since the early 1990s, microprocessors have integrated floating point (and just about everything else) on chip, and hence the term coprocessor joins accumulator and core memory as quaint terms that date the speaker. Elaboration: As mentioned in Section 3.4, accelerating division is more challenging than multiplication. In addition to SRT, another technique to leverage a fast multiplier is Newton’s iteration, where division is recast as finding the zero of a function to find the reciprocal 1/x, which is then multiplied by the other operand. Iteration techniques cannot be rounded properly without calculating many extra bits. A TI chip solves this problem by calculating an extra-precise reciprocal. Elaboration: Java embraces IEEE 754 by name in its definition of Java floating-point data types and operations. Thus, the code in the first example could have well been generated for a class method that converted Fahrenheit to Celsius. The second example uses multiple dimensional arrays, which are not explicitly supported in Java. Java allows arrays of arrays, but each array may have its own length, unlike multiple dimensional arrays in C. Like the examples in Chapter 2, a Java version of this second example would require a good deal of checking code for array bounds, including a new length calculation at the end of row access. It would also need to check that the object reference is not null. Accurate Arithmetic Unlike integers, which can represent exactly every number between the smallest and largest number, floating-point numbers are normally approximations for a number they can’t really represent. The reason is that an infinite variety of real numbers exists between, say, 0 and 1, but no more than 253 can be represented exactly in double precision floating point. The best we can do is getting the floating-point representation close to the actual number. Thus, IEEE 754 offers several modes of rounding to let the programmer pick the desired approximation. Rounding sounds simple enough, but to round accurately requires the hardware to include extra bits in the calculation. In the preceding examples, we were vague on the number of bits that an intermediate representation can occupy, but clearly, if every intermediate result had to be truncated to the exact number of digits, there would be no opportunity to round. IEEE 754, therefore, always keeps two extra bits on the right during intermediate additions, called guard and round, respectively. Let’s do a decimal example to illustrate their value. guard The first of two extra bits kept on the right during intermediate calculations of floating- point numbers; used to improve rounding accuracy. round Method to make the intermediate floating‑point result fit the floating-point format; the goal is typically to find the nearest number that can be represented in the format.
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Rounding with Guard Digits Add 2.56ten × 100 to 2.34ten × 102, assuming that we have three significant decimal digits. Round to the nearest decimal number with three significant decimal digits, first with guard and round digits, and then without them. First we must shift the smaller number to the right to align the exponents, so 2.56ten × 100 becomes 0.0256ten × 102. Since we have guard and round digits, we are able to represent the two least significant digits when we align expo nents. The guard digit holds 5 and the round digit holds 6. The sum is 2.3400ten + 0.0256ten 2.3656ten Thus the sum is 2.3656ten × 102. Since we have two digits to round, we want values 0 to 49 to round down and 51 to 99 to round up, with 50 being the tiebreaker. Rounding the sum up with three significant digits yields 2.37ten × 102. Doing this without guard and round digits drops two digits from the calculation. The new sum is then 2.34ten + 0.02ten 2.36ten The answer is 2.36ten × 102, off by 1 in the last digit from the sum above. Since the worst case for rounding would be when the actual number is halfway between two floating-point representations, accuracy in floating point is normally measured in terms of the number of bits in error in the least significant bits of the significand; the measure is called the number of units in the last place, or ulp. If a number were off by 2 in the least significant bits, it would be called off by 2 ulps. Provided there is no overflow, underflow, or invalid operation exceptions, IEEE 754 guarantees that the computer uses the number that is within one-half ulp. Elaboration: Although the example above really needed just one extra digit, multiply can need two. A binary product may have one leading 0 bit; hence, the normalizing step must shift the product one bit left. This shifts the guard digit into the least significant bit of the product, leaving the round bit to help accurately round the product. EXAMPLE ANSWER units in the last place (ulp) The number of bits in error in the least significant bits of the significand between the actual number and the number that can be represented. 3.5 Floating Point 267
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268 Chapter 3 Arithmetic for Computers IEEE 754 has four rounding modes: always round up (toward +∞), always round down (toward – ∞), truncate, and round to nearest even. The final mode determines what to do if the number is exactly halfway in between. The U.S. Internal Revenue Service (IRS) always rounds 0.50 dollars up, possibly to the benefit of the IRS. A more equitable way would be to round up this case half the time and round down the other half. IEEE 754 says that if the least significant bit retained in a halfway case would be odd, add one; if it’s even, truncate. This method always creates a 0 in the least significant bit in the tie-breaking case, giving the rounding mode its name. This mode is the most commonly used, and the only one that Java supports. The goal of the extra rounding bits is to allow the computer to get the same results as if the intermediate results were calculated to infinite precision and then rounded. To support this goal and round to the nearest even, the standard has a third bit in addition to guard and round; it is set whenever there are nonzero bits to the right of the round bit. This sticky bit allows the computer to see the difference between 0.50 . . . 00 ten and 0.50 . . . 01ten when rounding. The sticky bit may be set, for example, during addition, when the smaller number is shifted to the right. Suppose we added 5.01ten × 10–1 to 2.34ten × 102 in the example above. Even with guard and round, we would be adding 0.0050 to 2.34, with a sum of 2.3450. The sticky bit would be set, since there are nonzero bits to the right. Without the sticky bit to remember whether any 1s were shifted off, we would assume the number is equal to 2.345000 . . . 00 and round to the nearest even of 2.34. With the sticky bit to remember that the number is larger than 2.345000 . . . 00, we round instead to 2.35. Elaboration: PowerPC, SPARC64, and AMD SSE5 architectures provide a single instruction that does a multiply and add on three registers: a = a + (b × c). Obviously, this instruction allows potentially higher floating-point performance for this common operation. Equally important is that instead of performing two roundings—-after the multiply and then after the add—which would happen with separate instructions, the multiply add instruction can perform a single rounding after the add. A single rounding step increases the precision of multiply add. Such operations with a single rounding are called fused multiply add. It was added to the revised IEEE 754 standard (see Section 3.10 on the CD). Summary The Big Picture that follows reinforces the stored-program concept from Chapter 2; the meaning of the information cannot be determined just by looking at the bits, for the same bits can represent a variety of objects. This section shows that computer arithmetic is finite and thus can disagree with natural arithmetic. For example, the IEEE 754 standard floating-point representation (-1)S × (1 + Fraction) × 2(Exponent - Bias) is almost always an approximation of the real number. Computer systems must take care to minimize this gap between computer arithmetic and arithmetic in the real world, and programmers at times need to be aware of the implications of this approximation. sticky bit A bit used in rounding in addition to guard and round that is set whenever there are nonzero bits to the right of the round bit. fused multiply add A floating-point instruction that performs both a multiply and an add, but rounds only once after the add.
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Bit patterns have no inherent meaning. They may represent signed integers, unsigned integers, floating-point numbers, instructions, and so on. What is represented depends on the instruction that operates on the bits in the word. The major difference between computer numbers and numbers in the real world is that computer numbers have limited size and hence limited precision; it’s possible to calculate a number too big or too small to be represented in a word. Programmers must remember these limits and write programs accordingly. C type Java type Data transfers Operations int int lw, sw, lui addu, addiu, subu, mult, div, AND, ANDi, OR, ORi, NOR, slt, slti unsigned int — lw, sw, lui addu, addiu, subu, multu, divu, AND, ANDi, OR, ORi, NOR, sltu, sltiu char — lb, sb, lui add, addi, sub, mult, div AND, ANDi, OR, ORi, NOR, slt, slti — char lh, sh, lui addu, addiu, subu, multu, divu, AND, ANDi, OR, ORi, NOR, sltu, sltiu float float lwc1, swc1 add.s, sub.s, mult.s, div.s, c.eq.s, c.lt.s, c.le.s double double l.d, s.d add.d, sub.d, mult.d, div.d, c.eq.d, c.lt.d, c.le.d In the last chapter, we presented the storage classes of the programming language C (see the Hardware/Software Interface section in Section 2.7). The table above shows some of the C and Java data types, the MIPS data transfer instructions, and instructions that operate on those types that appear in Chapter 2 and this chapter. Note that Java omits unsigned integers. Suppose there was a 16-bit IEEE 754 floating-point format with five exponent bits. What would be the likely range of numbers it could represent? 1. 1.0000 0000 00 × 20 to 1.1111 1111 11 × 231, 0 2. ±1.0000 0000 0 × 2-14 to ±1.1111 1111 1 × 215, ±0, ±∞, NaN 3. ±1.0000 0000 00 × 2-14 to ±1.1111 1111 11 × 215, ±0, ±∞, NaN 4. ±1.0000 0000 00 × 2-15 to ±1.1111 1111 11 × 214, ±0, ±∞, NaN The BIG Picture Hardware/ Software Interface Check Yourself 3.5 Floating Point 269
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270 Chapter 3 Arithmetic for Computers Elaboration: To accommodate comparisons that may include NaNs, the standard includes ordered and unordered as options for compares. Hence, the full MIPS instruction set has many flavors of compares to support NaNs. (Java does not support unordered compares.) In an attempt to squeeze every last bit of precision from a floating-point operation, the standard allows some numbers to be represented in unnormalized form. Rather than having a gap between 0 and the smallest normalized number, IEEE allows denormalized numbers (also known as denorms or subnormals). They have the same exponent as zero but a nonzero fraction. They allow a number to degrade in significance until it becomes 0, called gradual underflow. For example, the smallest positive single precision normalized number is 1.0000 0000 0000 0000 0000 000two × 2–126 but the smallest single precision denormalized number is 0.0000 0000 0000 0000 0000 001two × 2–126, or 1.0two × 2–149 For double precision, the denorm gap goes from 1.0 × 2–1022 to 1.0 × 2–1074. The possibility of an occasional unnormalized operand has given headaches to floating- point designers who are trying to build fast floating-point units. Hence, many computers cause an exception if an operand is denormalized, letting software complete the operation. Although software implementations are perfectly valid, their lower performance has lessened the popularity of denorms in portable floating-point software. Moreover, if programmers do not expect denorms, their programs may surprise them. 3.6 Parallelism and Computer Arithmetic: Associativity Programs have typically been written first to run sequentially before being rewritten to run concurrently, so a natural question is, “do the two versions get the same answer?” If the answer is no, you presume there is a bug in the parallel version that you need to track down. This approach assumes that computer arithmetic does not affect the results when going from sequential to parallel. That is, if you were to add a million numbers together, you would get the same results whether you used 1 processor or 1000 processors. This assumption holds for two’s complement integers, even if the computation overflows. Another way to say this is that integer addition is associative. Alas, because floating-point numbers are approximations of real numbers and because computer arithmetic has limited precision, it does not hold for floating- point numbers. That is, floating-point addition is not associative. Testing Associativity of Floating-Point Addition See if x + (y + z) = (x + y) + z. For example, suppose x = -1.5ten × 1038, y = 1.5ten × 1038, and z = 1.0, and that these are all single precision numbers. EXAMPLE
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Given the great range of numbers that can be represented in floating point, problems occur when adding two large numbers of opposite signs plus a small number, as we shall see: x + (y + z) = -1.5ten × 1038 + (1.5ten × 1038 + 1.0) = -1.5ten × 1038 + (1.5ten × 1038) = 0.0 (x + y) + z = (-1.5ten × 1038 + 1.5ten × 1038) + 1.0 = (0.0ten) + 1.0 = 1.0 Therefore x + (y + z) ≠ (x + y) + z, so floating-point addition is not associative. Since floating-point numbers have limited precision and result in approximations of real results, 1.5ten × 1038 is so much larger than 1.0ten that 1.5ten × 1038 + 1.0 is still 1.5ten × 1038. That is why the sum of x, y, and z is 0.0 or 1.0, depending on the order of the floating-point additions, and hence floating-point add is not associative. A more vexing version of this pitfall occurs on a parallel computer where the operating system scheduler may use a different number of processors depending on what other programs are running on a parallel computer. The unaware parallel programmer may be flummoxed by his or her program getting slightly different answers each time it is run for the same identical code and the same identical input, as the varying number of processors from each run would cause the floating-point sums to be calculated in different orders. Given this quandary, programmers who write parallel code with floating-point numbers need to verify whether the results are credible even if they don’t give the same exact answer as the sequential code. The field that deals with such issues is called numerical analysis, which is the subject of textbooks in its own right. Such concerns are one reason for the popularity of numerical libraries such as LAPACK and SCALAPAK, which have been validated in both their sequential and parallel forms. Elaboration: A subtle version of the associativity issue occurs when two processors perform a redundant computation that is executed in different order so they get slightly different answers, although both answers are considered accurate. The bug occurs if a conditional branch compares to a floating-point number and the two processors take different branches when common sense reasoning suggests they should take the same branch. ANSWER 3.6 Parallelism and Computer Arithmetic: Associativity 271
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272 Chapter 3 Arithmetic for Computers 3.7 Real Stuff: Floating Point in the x86 The x86 has regular multiply and divide instructions that operate entirely on its normal registers, unlike the reliance on separate Hi and Lo registers in MIPS. (In fact, later versions of the MIPS instruction set have added similar instructions.) The main differences are found in floating-point instructions. The x86 floating- point architecture is different from all other computers in the world. The x86 Floating-Point Architecture The Intel 8087 floating-point coprocessor was announced in 1980. This architecture extended the 8086 with about 60 floating-point instructions. Intel provided a stack architecture with its floating-point instructions: loads push numbers onto the stack, operations find operands in the two top elements of the stacks, and stores can pop elements off the stack. Intel supplemented this stack architecture with instructions and addressing modes that allow the architecture to have some of the benefits of a register-memory model. In addition to finding operands in the top two elements of the stack, one operand can be in memory or in one of the seven registers on-chip below the top of the stack. Thus, a complete stack instruction set is supplemented by a limited set of register-memory instructions. This hybrid is still a restricted register-memory model, however, since loads always move data to the top of the stack while incrementing the top-of-stack pointer, and stores can only move the top of stack to memory. Intel uses the notation ST to indicate the top of stack, and ST(i) to represent the ith register below the top of stack. Another novel feature of this architecture is that the operands are wider in the register stack than they are stored in memory, and all operations are performed at this wide internal precision. Unlike the maximum of 64 bits on MIPS, the x86 floating- point operands on the stack are 80 bits wide. Numbers are automatically converted to the internal 80-bit format on a load and converted back to the appropriate size on a store. This double extended precision is not supported by programming languages, although it has been useful to programmers of mathematical software. Memory data can be 32-bit (single precision) or 64-bit (double precision) floating-point numbers. The register-memory version of these instructions will then convert the memory operand to this Intel 80-bit format before perform- ing the operation. The data transfer instructions also will automatically convert 16- and 32-bit integers to floating point, and vice versa, for integer loads and stores.
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The x86 floating-point operations can be divided into four major classes: 1. Data movement instructions, including load, load constant, and store 2. Arithmetic instructions, including add, subtract, multiply, divide, square root, and absolute value 3. Comparison, including instructions to send the result to the integer processor so that it can branch 4. Transcendental instructions, including sine, cosine, log, and exponentiation Figure 3.20 shows some of the 60 floating-point operations. Note that we get even more combinations when we include the operand modes for these operations. Figure 3.21 shows the many options for floating-point add. Data transfer Arithmetic Compare Transcendental F{I}LD mem/ST(i) F{I}ADD{P} mem/ST(i) F{I}COM{P} FPATAN F{I}ST{P} mem/ ST(i) F{I}SUB{R}{P} mem/ST(i) F{I}UCOM{P}{P} F2XM1 FLDPI F{I}MUL{P} mem/ST(i) FSTSW AX/mem FCOS FLD1 F{I}DIV{R}{P} mem/ST(i) FPTAN FLDZ FSQRT FPREM FABS FSIN FRNDINT FYL2X FIGURE 3.20 The floating-point instructions of the x86. We use the curly brackets {} to show optional variations of the basic operations: {I} means there is an integer version of the instruction, {P} means this variation will pop one operand off the stack after the operation, and {R} means reverse the order of the operands in this operation. The first column shows the data transfer instructions, which move data to memory or to one of the registers below the top of the stack. The last three operations in the first column push constants on the stack: pi, 1.0, and 0.0. The second column contains the arithmetic operations described above. Note that the last three operate only on the top of stack. The third column is the compare instructions. Since there are no special floating-point branch instructions, the result of the compare must be transferred to the integer CPU via the FSTSW instruction, either into the AX register or into memory, followed by an SAHF instruction to set the condition codes. The floating-point comparison can then be tested using integer branch instructions. The final column gives the higher-level floating-point operations. Not all combinations suggested by the notation are provided. Hence, F{I}SUB{R}{P} operations represent these instructions found in the x86: FSUB, FISUB, FSUBR, FISUBR, FSUBP, FSUBRP. For the integer subtract instructions, there is no pop (FISUBP) or reverse pop (FISUBRP). The floating-point instructions are encoded using the ESC opcode of the 8086 and the postbyte address specifier (see Figure 2.47). The memory operations reserve 2 bits to decide whether the operand is a 32- or 64-bit floating point or a 16- or 32-bit integer. Those same 2 bits are used in versions that do not access memory to decide whether the stack should be popped after the operation and whether the top of stack or a lower register should get the result. 3.7 Real Stuff: Floating Point in the x86 273
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274 Chapter 3 Arithmetic for Computers Instruction Operands Comment FADD Both operands in stack; result replaces top of stack. FADD ST(i) One source operand is ith register below the top of stack; result replaces the top of stack. FADD ST(i), ST One source operand is the top of stack; result replaces ith register below the top of stack. FADD mem32 One source operand is a 32-bit location in memory; result replaces the top of stack. FADD mem64 One source operand is a 64-bit location in memory; result replaces the top of stack. FIGURE 3.21 The variations of operands for floating-point add in the x86. In the past, floating-point performance of the x86 family lagged far behind other computers. As a result, Intel created a more traditional floating-point architecture as part of SSE2. The Intel Streaming SIMD Extension 2 (SSE2) Floating-Point Architecture Chapter 2 notes that in 2001 Intel added 144 instructions to its architecture, including double precision floating-point registers and operations. It includes eight 64-bit registers that can be used for floating-point operands, giving the compiler a different target for floating-point operations than the unique stack architecture. Compilers can choose to use the eight SSE2 registers as floating-point registers like those found in other computers. AMD expanded the number to 16 registers as part of AMD64, which Intel relabeled EM64T for its use. Figure 3.22 summarizes the SSE and SSE2 instructions. In addition to holding a single precision or double precision number in a register, Intel allows multiple floating-point operands to be packed into a single 128-bit SSE2 register: four single precision or two double precision. Thus, the 16 floating- point registers for SSE2 are actually 128 bits wide. If the operands can be arranged in memory as 128-bit aligned data, then 128-bit data transfers can load and store multiple operands per instruction. This packed floating-point format is supported by arithmetic operations that can operate simultaneously on four singles (PS) or two doubles (PD). This architecture more than doubles performance over the stack architecture.
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Data transfer Arithmetic Compare MOV{A/U}{SS/PS/SD/ PD} xmm, mem/xmm ADD{SS/PS/SD/PD} xmm, mem/xmm CMP{SS/PS/SD/ PD} SUB{SS/PS/SD/PD} xmm, mem/xmm MOV {H/L} {PS/PD} xmm, mem/xmm MUL{SS/PS/SD/PD} xmm, mem/xmm DIV{SS/PS/SD/PD} xmm, mem/xmm SQRT{SS/PS/SD/PD} mem/xmm MAX {SS/PS/SD/PD} mem/xmm MIN{SS/PS/SD/PD} mem/xmm FIGURE 3.22 The SSE/SSE2 floating-point instructions of the x86. xmm means one operand is a 128-bit SSE2 register, and mem/xmm means the other operand is either in memory or it is an SSE2 register. We use the curly brackets {} to show optional variations of the basic operations: {SS} stands for Scalar Single precision floating point, or one 32-bit operand in a 128-bit register; {PS} stands for Packed Single precision floating point, or four 32-bit operands in a 128-bit register; {SD} stands for Scalar Double precision floating point, or one 64-bit operand in a 128-bit register; {PD} stands for Packed Double precision floating point, or two 64-bit operands in a 128-bit register; {A} means the 128-bit operand is aligned in memory; {U} means the 128-bit operand is unaligned in memory; {H} means move the high half of the 128-bit operand; and {L} means move the low half of the 128-bit operand. 3.8 Fallacies and Pitfalls Arithmetic fallacies and pitfalls generally stem from the difference between the limited precision of computer arithmetic and the unlimited precision of natural arithmetic. Fallacy: Just as a left shift instruction can replace an integer multiply by a power of 2, a right shift is the same as an integer division by a power of 2. Recall that a binary number x, where xi means the ith bit, represents the number . . . + (x3 × 23) + (x2 × 22) + (x1 × 21) + (x0 × 20) Shifting the bits of x right by n bits would seem to be the same as dividing by 2n. And this is true for unsigned integers. The problem is with signed integers. For example, suppose we want to divide -5ten by 4ten; the quotient should be -1ten. The two’s complement representation of -5ten is Thus mathematics may be defined as the subject in which we never know what we are talking about, nor whether what we are saying is true. Bertrand Russell, Recent Words on the Principles of Mathematics, 1901 3.8 Fallacies and Pitfalls 275
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276 Chapter 3 Arithmetic for Computers 1111 1111 1111 1111 1111 1111 1111 1011two According to this fallacy, shifting right by two should divide by 4ten (22): 0011 1111 1111 1111 1111 1111 1111 1110two With a 0 in the sign bit, this result is clearly wrong. The value created by the shift right is actually 1,073,741,822ten instead of -1ten. A solution would be to have an arithmetic right shift that extends the sign bit instead of shifting in 0s. A 2-bit arithmetic shift right of -5ten produces 1111 1111 1111 1111 1111 1111 1111 1110two The result is -2ten instead of -1ten; close, but no cigar. Pitfall: The MIPS instruction add immediate unsigned (addiu) sign-extends its 16-bit immediate field. Despite its name, add immediate unsigned (addiu) is used to add constants to signed integers when we don’t care about overflow. MIPS has no subtract immediate instruction, and negative numbers need sign extension, so the MIPS architects decided to sign-extend the immediate field. Fallacy: Only theoretical mathematicians care about floating-point accuracy. Newspaper headlines of November 1994 prove this statement is a fallacy (see Figure 3.23). The following is the inside story behind the headlines. The Pentium uses a standard floating-point divide algorithm that generates multiple quotient bits per step, using the most significant bits of divisor and dividend to guess the next 2 bits of the quotient. The guess is taken from a lookup table containing -2, -1, 0, +1, or +2. The guess is multiplied by the divisor and subtracted from the remainder to generate a new remainder. Like nonrestoring division, if a previous guess gets too large a remainder, the partial remainder is adjusted in a subsequent pass. Evidently, there were five elements of the table from the 80486 that Intel thought could never be accessed, and they optimized the PLA to return 0 instead of 2 in these situations on the Pentium. Intel was wrong: while the first 11 bits were always correct, errors would show up occasionally in bits 12 to 52, or the 4th to 15th decimal digits. The following is a timeline of the Pentium bug morality play. ■ ■July 1994: Intel discovers the bug in the Pentium. The actual cost to fix the bug was several hundred thousand dollars. Following normal bug fix procedures, it will take months to make the change, reverify, and put the corrected chip into production. Intel planned to put good chips into production in January 1995, estimating that 3 to 5 million Pentiums would be produced with the bug.
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■ ■September 1994: A math professor at Lynchburg College in Virginia, Thomas Nicely, discovers the bug. After calling Intel technical support and getting no official reaction, he posts his discovery on the Internet. It quickly gained a following, and some pointed out that even small errors become big when multiplied by big numbers: the fraction of people with a rare disease times the population of Europe, for example, might lead to the wrong estimate of the number of sick people. ■ ■November 7, 1994: Electronic Engineering Times puts the story on its front page, which is soon picked up by other newspapers. ■ ■November 22, 1994: Intel issues a press release, calling it a “glitch.” The Pentium “can make errors in the ninth digit. . . . Even most engineers and financial analysts require accuracy only to the fourth or fifth decimal point. Spreadsheet FIGURE 3.23 A sampling of newspaper and magazine articles from November 1994, including the New York Times, San Jose Mercury News, San Francisco Chronicle, and Infoworld. The Pentium floating-point divide bug even made the “Top 10 List” of the David Letterman Late Show on television. Intel eventually took a $300 million write-off to replace the buggy chips. 3.8 Fallacies and Pitfalls 277
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278 Chapter 3 Arithmetic for Computers and word processor users need not worry. . . . There are maybe several dozen people that this would affect. So far, we’ve only heard from one. . . . [Only] theoretical mathematicians (with Pentium computers purchased before the summer) should be concerned.” What irked many was that customers were told to describe their application to Intel, and then Intel would decide whether or not their application merited a new Pentium without the divide bug. ■ ■December 5, 1994: Intel claims the flaw happens once in 27,000 years for the typical spreadsheet user. Intel assumes a user does 1000 divides per day and multiplies the error rate assuming floating-point numbers are random, which is one in 9 billion, and then gets 9 million days, or 27,000 years. Things begin to calm down, despite Intel neglecting to explain why a typical customer would access floating-point numbers randomly. ■ ■December 12, 1994: IBM Research Division disputes Intel’s calculation of the rate of errors (you can access this article by visiting www.mkp.com/books_ catalog/cod/links.htm). IBM claims that common spreadsheet programs, recalculating for 15 minutes a day, could produce Pentium-related errors as often as once every 24 days. IBM assumes 5000 divides per second, for 15 minutes, yielding 4.2 million divides per day, and does not assume random distribution of numbers, instead calculating the chances as one in 100 million. As a result, IBM immediately stops shipment of all IBM personal computers based on the Pentium. Things heat up again for Intel. ■ ■December 21, 1994: Intel releases the following, signed by Intel’s president, chief executive officer, chief operating officer, and chairman of the board: “We at Intel wish to sincerely apologize for our handling of the recently publicized Pentium processor flaw. The Intel Inside symbol means that your computer has a microprocessor second to none in quality and performance. Thousands of Intel employees work very hard to ensure that this is true. But no microprocessor is ever perfect. What Intel continues to believe is technically an extremely minor problem has taken on a life of its own. Although Intel firmly stands behind the quality of the current version of the Pentium processor, we recognize that many users have concerns. We want to resolve these concerns. Intel will exchange the current version of the Pentium processor for an updated version, in which this floating- point divide flaw is corrected, for any owner who requests it, free of charge anytime during the life of their computer.” Analysts estimate that this recall cost Intel $500 million, and Intel engineers did not get a Christmas bonus that year. This story brings up a few points for everyone to ponder. How much cheaper would it have been to fix the bug in July 1994? What was the cost to repair the damage to Intel’s reputation? And what is the corporate responsibility in disclosing bugs in a product so widely used and relied upon as a microprocessor?
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MIPS core instructions Name Format MIPS arithmetic core Name Format add add R multiply mult R add immediate addi I multiply unsigned multu R add unsigned addu R divide div R add immediate unsigned addiu I divide unsigned divu R subtract sub R move from Hi mfhi R subtract unsigned subu R move from Lo mflo R AND AND R move from system control (EPC) mfc0 R AND immediate ANDi I floating-point add single add.s R OR OR R floating-point add double add.d R OR immediate ORi I floating-point subtract single sub.s R NOR NOR R floating-point subtract double sub.d R shift left logical sll R floating-point multiply single mul.s R shift right logical srl R floating-point multiply double mul.d R load upper immediate lui I floating-point divide single div.s R load word lw I floating-point divide double div.d R store word sw I load word to floating-point single lwc1 I load halfword unsigned lhu I store word to floating-point single swc1 I store halfword sh I load word to floating-point double ldc1 I load byte unsigned lbu I store word to floating-point double sdc1 I store byte sb I branch on floating-point true bc1t I load linked (atomic update) ll I branch on floating-point false bc1f I store cond. (atomic update) sc I floating-point compare single c.x.s R branch on equal beq I (x = eq, neq, lt, le, gt, ge) branch on not equal bne I floating-point compare double c.x.d R jump j J (x = eq, neq, lt, le, gt, ge) jump and link jal J jump register jr R set less than slt R set less than immediate slti I set less than unsigned sltu R set less than immediate unsigned sltiu I FIGURE 3.24 The MIPS instruction set. This book concentrates on the instructions in the left column. This information is also found in columns 1 and 2 of the MIPS Reference Data Card at the front of this book. In April 1997, another floating-point bug was revealed in the Pentium Pro and Pentium II microprocessors. When the floating-point-to-integer store instructions (fist, fistp) encounter a negative floating-point number that is too large to fit in a 16- or 32-bit word after being converted to integer, they set the wrong bit in the FPO status word (precision exception instead of invalid operation exception). To Intel’s credit, this time they publicly acknowledged the bug and offered a software patch to get around it—quite a different reaction from what they did in 1994. 3.8 Fallacies and Pitfalls 279
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280 Chapter 3 Arithmetic for Computers 3.9 Concluding Remarks A side effect of the stored-program computer is that bit patterns have no inherent meaning. The same bit pattern may represent a signed integer, unsigned integer, floating-point number, instruction, and so on. It is the instruction that operates on the word that determines its meaning. Computer arithmetic is distinguished from paper-and-pencil arithmetic by the constraints of limited precision. This limit may result in invalid operations through calculating numbers larger or smaller than the predefined limits. Such anomalies, called “overflow” or “underflow,” may result in exceptions or interrupts, emergency events similar to unplanned subroutine calls. Chapter 4 discusses exceptions in more detail. Floating-point arithmetic has the added challenge of being an approximation of real numbers, and care needs to be taken to ensure that the computer num- ber selected is the representation closest to the actual number. The challenges of imprecision and limited representation are part of the inspiration for the field of numerical analysis. The recent switch to parallelism will shine the searchlight on numerical analysis again, as solutions that were long considered safe on sequential computers must be reconsidered when trying to find the fastest algorithm for par- allel computers that still achieves a correct result. Over the years, computer arithmetic has become largely standardized, greatly enhancing the portability of programs. Two’s complement binary integer arithme- tic and IEEE 754 binary floating-point arithmetic are found in the vast majority of computers sold today. For example, every desktop computer sold since this book was first printed follows these conventions. With the explanation of computer arithmetic in this chapter comes a description of much more of the MIPS instruction set. One point of confusion is the instructions covered in these chapters versus instructions executed by MIPS chips versus the instructions accepted by MIPS assemblers. Two figures try to make this clear. Figure 3.24 lists the MIPS instructions covered in this chapter and Chapter 2. We call the set of instructions on the left-hand side of the figure the MIPS core. The instructions on the right we call the MIPS arithmetic core. On the left of Figure 3.25 are the instructions the MIPS processor executes that are not found in Figure 3.24. We call the full set of hardware instructions MIPS-32. On the right of Figure 3.25 are the instructions accepted by the assembler that are not part of MIPS-32. We call this set of instructions Pseudo MIPS. Figure 3.26 gives the popularity of the MIPS instructions for SPEC CPU2006 integer and floating-point benchmarks. All instructions are listed that were responsible for at least 0.2% of the instructions executed. Note that although programmers and compiler writers may use MIPS-32 to have a richer menu of options, MIPS core instructions dominate integer SPEC
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Remaining MIPS-32 Name Format Pseudo MIPS Name Format exclusive or (rs ⊕ rt) xor R absolute value abs rd,rs exclusive or immediate xori I negate (signed or unsigned) negs rd,rs shift right arithmetic sra R rotate left rol rd,rs,rt shift left logical variable sllv R rotate right ror rd,rs,rt shift right logical variable srlv R multiply and don’t check oflw (signed or uns.) muls rd,rs,rt shift right arithmetic variable srav R multiply and check oflw (signed or uns.) mulos rd,rs,rt move to Hi mthi R divide and check overflow div rd,rs,rt move to Lo mtlo R divide and don’t check overflow divu rd,rs,rt load halfword lh I remainder (signed or unsigned) rems rd,rs,rt load byte lb I load immediate li rd,imm load word left (unaligned) lwl I load address la rd,addr load word right (unaligned) lwr I load double ld rd,addr store word left (unaligned) swl I store double sd rd,addr store word right (unaligned) swr I unaligned load word ulw rd,addr load linked (atomic update) ll I unaligned store word usw rd,addr store cond. (atomic update) sc I unaligned load halfword (signed or uns.) ulhs rd,addr move if zero movz R unaligned store halfword ush rd,addr move if not zero movn R branch b Label multiply and add (S or uns.) madds R branch on equal zero beqz rs,L multiply and subtract (S or uns.) msubs I branch on compare (signed or unsigned) bxs rs,rt,L branch on ≥ zero and link bgezal I (x = lt, le, gt, ge) branch on < zero and link bltzal I set equal seq rd,rs,rt jump and link register jalr R set not equal sne rd,rs,rt branch compare to zero bxz I set on compare (signed or unsigned) sxs rd,rs,rt branch compare to zero likely bxzl I (x = lt, le, gt, ge) (x = lt, le, gt, ge) load to floating point (s or d) l.f rd,addr branch compare reg likely bxl I store from floating point (s or d) s.f rd,addr trap if compare reg tx R trap if compare immediate txi I (x = eq, neq, lt, le, gt, ge) return from exception rfe R system call syscall I break (cause exception) break I move from FP to integer mfc1 R move to FP from integer mtc1 R FP move (s or d) mov.f R FP move if zero (s or d) movz.f R FP move if not zero (s or d) movn.f R FP square root (s or d) sqrt.f R FP absolute value (s or d) abs.f R FP negate (s or d) neg.f R FP convert (w, s, or d) cvt.f.f R FP compare un (s or d) c.xn.f R FIGURE 3.25 Remaining MIPS-32 and Pseudo MIPS instruction sets. f means single (s) or double (d) precision floating-point instructions, and s means signed and unsigned (u) versions. MIPS-32 also has FP instructions for multiply and add/sub (madd.f/msub.f ), ceiling (ceil.f ), truncate (trunc.f ), round (round.f ), and reciprocal (recip.f ). The underscore represents the letter to include to represent that datatype. 3.9 Concluding Remarks 281
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282 Chapter 3 Arithmetic for Computers Core MIPS Name Integer Fl. pt. Arithmetic core + MIPS-32 Name Integer Fl. pt. add add 0.0% 0.0% FP add double add.d 0.0% 10.6% add immediate addi 0.0% 0.0% FP subtract double sub.d 0.0% 4.9% add unsigned addu 5.2% 3.5% FP multiply double mul.d 0.0% 15.0% add immediate unsigned addiu 9.0% 7.2% FP divide double div.d 0.0% 0.2% subtract unsigned subu 2.2% 0.6% FP add single add.s 0.0% 1.5% AND AND 0.2% 0.1% FP subtract single sub.s 0.0% 1.8% AND immediate ANDi 0.7% 0.2% FP multiply single mul.s 0.0% 2.4% OR OR 4.0% 1.2% FP divide single div.s 0.0% 0.2% OR immediate ORi 1.0% 0.2% load word to FP double l.d 0.0% 17.5% NOR NOR 0.4% 0.2% store word to FP double s.d 0.0% 4.9% shift left logical sll 4.4% 1.9% load word to FP single l.s 0.0% 4.2% shift right logical srl 1.1% 0.5% store word to FP single s.s 0.0% 1.1% load upper immediate lui 3.3% 0.5% branch on floating-point true bc1t 0.0% 0.2% load word lw 18.6% 5.8% branch on floating-point false bc1f 0.0% 0.2% store word sw 7.6% 2.0% floating-point compare double c.x.d 0.0% 0.6% load byte lbu 3.7% 0.1% multiply mul 0.0% 0.2% store byte sb 0.6% 0.0% shift right arithmetic sra 0.5% 0.3% branch on equal (zero) beq 8.6% 2.2% load half lhu 1.3% 0.0% branch on not equal (zero) bne 8.4% 1.4% store half sh 0.1% 0.0% jump and link jal 0.7% 0.2% jump register jr 1.1% 0.2% set less than slt 9.9% 2.3% set less than immediate slti 3.1% 0.3% set less than unsigned sltu 3.4% 0.8% set less than imm. uns. sltiu 1.1% 0.1% FIGURE 3.26 The frequency of the MIPS instructions for SPEC CPU2006 integer and floating point. All instructions that accounted for at least 0.2% of the instructions are included in the table. Pseudoinstructions are converted into MIPS-32 before execution, and hence do not appear here. CPU2006 execution, and the integer core plus arithmetic core dominate SPEC CPU2006 floating point, as the table below shows. Instruction subset Integer Fl. pt. MIPS core 98% 31% MIPS arithmetic core 2% 66% Remaining MIPS-32 0% 3% For the rest of the book, we concentrate on the MIPS core instructions—the integer instruction set excluding multiply and divide—to make the explanation of computer design easier. As you can see, the MIPS core includes the most popu- lar MIPS instructions; be assured that understanding a computer that runs the MIPS core will give you sufficient background to understand even more ambitious computers.
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Historical Perspective and Further Reading This section surveys the history of the floating point going back to von Neumann, including the surprisingly controversial IEEE standards effort, plus the rationale for the 80-bit stack architecture for floating point in the x86. See Section 3.10. 3.11 Exercises Contributed by Matthew Farrens, UC Davis Exercise 3.1 The book shows how to add and subtract binary and decimal numbers. However, other numbering systems are also very popular when dealing with computers. The octal (base 8) numbering system is one of these. The following table shows pairs of octal numbers. A B a. 3174 0522 b. 4165 1654 3.1.1 [5] <3.2> What is the sum of A and B if they represent unsigned 12-bit octal numbers? The result should be written in octal. Show your work. 3.1.2 [5] <3.2> What is the sum of A and B if they represent signed 12-bit octal numbers stored in sign-magnitude format? The result should be written in octal. Show your work. 3.1.3 [10] <3.2> Convert A into a decimal number, assuming it is unsigned. Repeat assuming it stored in sign-magnitude format. Show your work. The following table also shows pairs of octal numbers. A B a. 7040 0444 b. 4365 3412 3.10 Gresham’s Law (“Bad money drives out Good”) for computers would say, “The Fast drives out the Slow even if the Fast is wrong.” W. Kahan, 1992 Never give in, never give in, never, never, never—in nothing, great or small, large or petty—never give in. Winston Churchill, address at Harrow School, 1941 3.11 Exercises 283
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284 Chapter 3 Arithmetic for Computers 3.1.4 [5] <3.2> What is A – B if they represent unsigned 12-bit octal numbers? The result should be written in octal. Show your work. 3.1.5 [5] <3.2> What is A – B if they represent signed 12-bit octal numbers stored in sign-magnitude format? The result should be written in octal. Show your work. 3.1.6 [10] <3.2> Convert A into a binary number. What makes base 8 (octal) an attractive numbering system for representing values in computers? Exercise 3.2 Hexadecimal (base 16) is also a commonly used numbering system for represent- ing values in computers. In fact, it has become much more popular than octal. The following table shows pairs of hexadecimal numbers. A B a. 1446 672F b. 2460 4935 3.2.1 [5] <3.2> What is the sum of A and B if they represent unsigned 16-bit hexadecimal numbers? The result should be written in hexadecimal. Show your work. 3.2.2 [5] <3.2> What is the sum of A and B if they represent signed 16-bit hexa- decimal numbers stored in sign-magnitude format? The result should be written in hexadecimal. Show your work. 3.2.3 [10] <3.2> Convert A into a decimal number, assuming it is unsigned. Repeat assuming it stored in sign-magnitude format. Show your work. The following table also shows pairs of hexadecimal numbers. A B a. C352 36AE b. 5ED4 07A4 3.2.4 [5] <3.2> What is A – B if they represent unsigned 16-bit hexadecimal numbers? The result should be written in hexadecimal. Show your work.
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3.2.5 [5] <3.2> What is A – B if they represent signed 16-bit hexadecimal numbers stored in sign-magnitude format? The result should be written in hexa- decimal. Show your work. 3.2.6 [10] <3.2> Convert A into a binary number. What makes base 16 (hexa- decimal) an attractive numbering system for representing values in computers? Exercise 3.3 Overflow occurs when a result is too large to be represented accurately given a finite word size. Underflow occurs when a number is too small to be represented correctly—a negative result when doing unsigned arithmetic, for example. (The case when a positive result is generated by the addition of two negative integers is also referred to as underflow by many, but in this textbook, that is considered an overflow.) The following table shows pairs of decimal numbers. A B a. 216 255 b. 185 122 3.3.1 [5] <3.2> Assume A and B are unsigned 8-bit decimal integers. Calculate A – B. Is there overflow, underflow, or neither? 3.3.2 [5] <3.2> Assume A and B are signed 8-bit decimal integers stored in sign- magnitude format. Calculate A + B. Is there overflow, underflow, or neither? 3.3.3 [5] <3.2> Assume A and B are signed 8-bit decimal integers stored in sign- magnitude format. Calculate A – B. Is there overflow, underflow, or neither? The following table also shows pairs of decimal numbers. A B a. 15 139 b. 151 214 3.3.4 [10] <3.2> Assume A and B are signed 8-bit decimal integers stored in two’s complement format. Calculate A + B using saturating arithmetic. The result should be written in decimal. Show your work. 3.3.5 [10] <3.2> Assume A and B are signed 8-bit decimal integers stored in two’s complement format. Calculate A – B using saturating arithmetic. The result should be written in decimal. Show your work. 3.11 Exercises 285
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286 Chapter 3 Arithmetic for Computers 3.3.6 [10] <3.2> Assume A and B are unsigned 8-bit integers. Calculate A + B using saturating arithmetic. The result should be written in decimal. Show your work. Exercise 3.4 Let’s look in more detail at multiplication. We will use the numbers in the follow- ing table. A B a. 62 12 b. 35 26 3.4.1 [20] <3.3> Using a table similar to that shown in Figure 3.7, calculate the product of the octal unsigned 6-bit integers A and B using the hardware described in Figure 3.4. You should show the contents of each register on each step. 3.4.2 [20] <3.3> Using a table similar to that shown in Figure 3.7, calculate the product of the hexadecimal unsigned 8-bit integers A and B using the hardware described in Figure 3.6. You should show the contents of each register on each step. 3.4.3 [60] <3.3> Write an MIPS assembly language program to calculate the product of unsigned integers A and B, using the approach described in Figure 3.4. The following table shows pairs of octal numbers. A B a. 41 33 b. 60 26 3.4.4 [30] <3.3> When multiplying signed numbers, one way to get the correct answer is to convert the multiplier and multiplicand to positive numbers, save the original signs, and then adjust the final value accordingly. Using a table similar to that shown in Figure 3.7, calculate the product of A and B using the hardware described in Figure 3.4. You should show the contents of each register on each step, and include the step necessary to produce the correctly signed result. Assume A and B are stored in 6-bit sign-magnitude format. 3.4.5 [30] <3.3> When shifting a register one bit to the right, there are several ways to decide what the new entering bit should be. It can always be a zero, or always a one, or the incoming bit could be the one that is being pushed out of the
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right side (turning a shift into a rotate), or the value that is already in the leftmost bit can simply be retained (called an arithmetic shift right, because it preserves the sign of the number that is being shift). Using a table similar to that shown in Figure 3.7, calculate the product of the 6-bit two’s complement numbers A and B using the hardware described in Figure 3.6. The right shifts should be done using an arithmetic shift right. Note that the algorithm described in the text will need to be modified slightly to make this work—in particular, things must be done differ- ently if the multiplier is negative. You can find details by searching the web. Show the contents of each register on each step. 3.4.6 [60] <3.3> Write an MIPS assembly language program to calculate the product of the signed integers A and B. State if you are using the approach given in 3.4.4 or 3.4.5. Exercise 3.5 For many reasons, we would like to design multipliers that require less time. Many different approaches have been taken to accomplish this goal. In the following table, A represents the bit width of an integer, and B represents the number of time units (tu) taken to perform a step of an operation. A (bit width) B (time units) a. 8 4tu b. 64 8tu 3.5.1 [10] <3.3> Calculate the time necessary to perform a multiply using the approach given in Figures 3.4 and 3.5 if an integer is A bits wide and each step of the operation takes B time units. Assume that in step 1a an addition is always performed—either the multiplicand will be added, or a zero will be. Also assume that the registers have already been initialized (you are just counting how long it takes to do the multiplication loop itself). If this is being done in hardware, the shifts of the multiplicand and multiplier can be done simultaneously. If this is being done in software, they will have to be done one after the other. Solve for each case. 3.5.2 [10] <3.3> Calculate the time necessary to perform a multiply using the approach described in the text (31 adders stacked vertically) if an integer is A bits wide and an adder takes B time units. 3.5.3 [20] <3.3> Calculate the time necessary to perform a multiply using the approach given in Figure 3.8 if an integer is A bits wide and an adder takes B time units. 3.11 Exercises 287
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288 Chapter 3 Arithmetic for Computers Exercise 3.6 In this exercise we will look at a couple of other ways to improve the performance of multiplication, based primarily on doing more shifts and fewer arithmetic operations. The following table shows pairs of hexadecimal numbers. A B a. 33 55 b. 8a 6d 3.6.1 [20] <3.3> As discussed in the text, one possible performance enhancement is to do a shift and add instead of an actual multiplication. Since 9 × 6, for example, can be written (2 × 2 × 2 + 1) × 6, we can calculate 9 × 6 by shifting 6 to the left 3 times and then adding 6 to that result. Show the best way to calculate A × B using shifts and adds/subtracts. Assume that A and B are 8-bit unsigned integers. 3.6.2 [20] <3.3> Show the best way to calculate A × B using shifts and add, if A and B are 8-bit signed integers stored in sign-magnitude format. 3.6.3 [60] <3.3> Write an MIPS assembly language program that performs a mul- tiplication on signed integers using shifts and adds, using the approach described in 3.6.1. The following table shows further pairs of hexadecimal numbers. A B a. F6 7F b. 08 55 3.6.4 [30] <3.3> Booth’s algorithm is another approach to reducing the number of arithmetic operations necessary to perform a multiplication. This algorithm has been around for years and involves identifying runs of ones and zeros and per- forming only shifts instead of shifts and adds during the runs. Find a description of the algorithm on the web and explain in detail how it works. 3.6.5 [30] <3.3> Show the step-by-step result of multiplying A and B, using Booth’s algorithm. Assume A and B are 8-bit two’s complement integers, stored in hexadecimal format. 3.6.6 [60] <3.3> Write an MIPS assembly language program to perform the mul- tiplication of A and B using Booth’s algorithm.
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Exercise 3.7 Let’s look in more detail at division. We will use the octal numbers in the following table. A B a. 74 21 b. 76 52 3.7.1 [20] <3.4> Using a table similar to that shown in Figure 3.11, calculate A divided by B using the hardware described in Figure 3.9. You should show the con- tents of each register on each step. Assume A and B are unsigned 6-bit integers. 3.7.2 [30] <3.4> Using a table similar to that shown in Figure 3.11, calculate A divided by B using the hardware described in Figure 3.12. You should show the con- tents of each register on each step. Assume A and B are unsigned 6-bit integers. This algorithm requires a slightly different approach than that shown in Figure 3.10. You will want to think hard about this, do an experiment or two, or else go to the web to figure out how to make this work correctly. (Hint: one possible solution involves using the fact that Figure 3.12 implies the remainder register can be shifted either direction.) 3.7.3 [60] <3.4> Write an MIPS assembly language program to calculate A divided by B, using the approach described in Figure 3.9. Assume A and B are unsigned 6-bit integers. The following table shows further pairs of octal numbers. A B a. 72 07 b. 75 47 3.7.4 [30] <3.4> Using a table similar to that shown in Figure 3.11, calculate A divided by B using the hardware described in Figure 3.9. You should show the con- tents of each register on each step. Assume A and B are 6-bit signed integers in sign-magnitude format. Be sure to include how you are calculating the signs of the quotient and remainder. 3.7.5 [30] <3.4> Using a table similar to that shown in Figure 3.11, calculate A divided by B using the hardware described in Figure 3.12. You should show the contents of each register on each step. Assume A and B are 6-bit signed integers in sign-magnitude format. Be sure to include how you are calculating the signs of the quotient and remainder. 3.11 Exercises 289
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290 Chapter 3 Arithmetic for Computers 3.7.6 [60] <3.4> Write an MIPS assembly language program to calculate A divided by B, using the approach described in Figure 3.12. Assume A and B are signed integers. Exercise 3.8 Figure 3.10 describes a restoring division algorithm, because when subtracting the divisor from the remainder produces a negative result, the divisor is added back to the remainder (thus restoring the value). However, there are other algorithms that have been developed that eliminate the extra addition. Many references to these algorithms are easily found on the web. We will explore these algorithms using the pairs of octal numbers in the following table. A B a. 26 05 b. 37 15 3.8.1 [30] <3.4> Using a table similar to that shown in Figure 3.11, calculate A divided by B using non-restoring division. You should show the contents of each register on each step. Assume A and B are 6-bit unsigned integers. 3.8.2 [60] <3.4> Write an MIPS assembly language program to calculate A divided by B using non-restoring division. Assume A and B are 6-bit signed (two’s complement) integers. 3.8.3 [60] <3.4> How does the performance of restoring and non-restoring division compare? Demonstrate by showing the number of steps necessary to calculate A divided by B using each method. Assume A and B are 6-bit signed (sign-magnitude) integers. Writing a program to perform the restoring and non- restoring divisions is acceptable. The following table shows further pairs of octal numbers. A B a. 27 06 b. 54 12 3.8.4 [30] <3.4> Using a table similar to that shown in Figure 3.11, calculate A divided by B using non-performing division. You should show the contents of each register on each step. Assume A and B are 6-bit unsigned integers.
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3.8.5 [60] <3.4> Write an MIPS assembly language program to calculate A divided by B using nonperforming division. Assume A and B are 6-bit two’s com- plement signed integers. 3.8.6 [60] <3.4> How does the performance of non-restoring and nonperform- ing division compare? Demonstrate by showing the number of steps necessary to calculate A divided by B using each method. Assume A and B are signed 6-bit inte- gers, stored in sign-magnitude format. Writing a program to perform the nonper- forming and non-restoring divisions is acceptable. Exercise 3.9 Division is so time-consuming and difficult that the CRAY T3E Fortran Optimiza- tion guide states, “The best strategy for division is to avoid it whenever possible.” This exercise looks at the following different strategies for performing divisions. a. non-restoring division b. division by reciprocal multiplication 3.9.1 [30] <3.4> Describe the algorithm in detail. 3.9.2 [60] <3.4> Use a flow chart (or a high-level code snippet) to describe how the algorithm works. 3.9.3 [60] <3.4> Write an MIPS assembly language program to perform division using the algorithm. Exercise 3.10 In a Von Neumann architecture, groups of bits have no intrinsic meanings by themselves. What a bit pattern represents depends entirely on how it is used. The following table shows bit patterns expressed in hexademical notation. a. 0x0C000000 b. 0xC4630000 3.10.1 [5] <3.5> What decimal number does the bit pattern represent if it is a two’s complement integer? An unsigned integer? 3.10.2 [10] <3.5> If this bit pattern is placed into the Instruction Register, what MIPS instruction will be executed? 3.11 Exercises 291
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292 Chapter 3 Arithmetic for Computers 3.10.3 [10] <3.5> What decimal number does the bit pattern represent if it is a floating point number? Use the IEEE 754 standard. The following table shows decimal numbers. a. 63.25 b. 146987.40625 3.10.4 [10] <3.5> Write down the binary representation of the decimal number, assuming the IEEE 754 single precision format. 3.10.5 [10] <3.5> Write down the binary representation of the decimal number, assuming the IEEE 754 double precision format. 3.10.6 [10] <3.5> Write down the binary representation of the decimal number assuming it was stored using the single precision IBM format (base 16, instead of base 2, with 7 bits of exponent). Exercise 3.11 In the IEEE 754 floating point standard the exponent is stored in “bias” (also known as “Excess-N”) format. This approach was selected because we want an all-zero pattern to be as close to zero as possible. Because of the use of a hidden 1, if we were to represent the exponent in two’s complement format an all-zero pattern would actually be the number 1! (Remember, anything raised to the zeroth power is 1, so 1.00 = 1.) There are many other aspects of the IEEE 754 standard that exist in order to help hardware floating point units work more quickly. However, in many older machines floating point calculations were handled in software, and therefore other formats were used. The following table shows decimal numbers. a. –1.5625 × 10–1 b. 9.356875 × 102 3.11.1 [20] <3.5> Write down the binary bit pattern assuming a format similar to that employed by the DEC PDP-8 (the leftmost 12 bits are the exponent stored as a two’s complement number, and the rightmost 24 bits are the mantissa stored as a two’s complement number ). No hidden 1 is used. Comment on how the range and accuracy of this 36-bit pattern compares to the single and double precision IEEE 754 standards. 3.11.2 [20] <3.5> NVIDIA has a “half” format, which is similar to IEEE 754 except that it is only 16 bits wide. The leftmost bit is still the sign bit, the exponent is 5 bits wide and stored in excess-56 format, and the mantissa is 10 bits long.
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A hidden 1 is assumed. Write down the bit pattern assuming a modified version of this format, which uses an excess-16 format to store the exponent. Comment on how the range and accuracy of this 16-bit floating point format compares to the single precision IEEE 754 standard. 3.11.3 [20] <3.5> The Hewlett-Packard 2114, 2115, and 2116 used a format with the leftmost 16 bits being the mantissa stored in two’s complement format, followed by another 16-bit field which had the leftmost 8 bits as an extension of the mantissa (making the mantissa 24 bits long), and the rightmost 8 bits repre- senting the exponent. However, in an interesting twist, the exponent was stored in sign-magnitude format with the sign bit on the far right! Write down the bit pat- tern assuming this format. No hidden 1 is used. Comment on how the range and accuracy of this 32-bit pattern compares to the single precision IEEE 754 standard. The following table shows pairs of decimal numbers. A B a. 2.6125 × 101 4.150390625 × 10–1 b. –4.484375 × 101 1.3953125 × 101 3.11.4 [20] <3.5> Calculate the sum of A and B by hand, assuming A and B are stored in the modified 16-bit NVIDIA format described in 3.11.2. Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps. 3.11.5 [60] <3.5> Write an MIPS assembly language program to calculate the sum of A and B, assuming they are stored in the modified 16-bit NVIDIA format described in 3.11.2. Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. 3.11.6 [60] <3.5> Write an MIPS assembly language program to calculate the sum of A and B, assuming they are stored using the format described in 3.11.1. Now modify the program to calculate the sum assuming the format described in 3.11.3. Which format is easier for a programmer to deal with? How do they each compare to the IEEE 754 format? (Do not worry about sticky bits for this question.) Exercise 3.12 Floating point multiplication is even more complicated and challenging than float- ing point addition, and both pale in comparison to floating point division. The following table shows pairs of decimal numbers. 3.11 Exercises 293
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294 Chapter 3 Arithmetic for Computers A B a. –8.0546875 × 100 –1.79931640625 × 10–1 b. 8.59375 × 10–2 8.125 × 10–1 3.12.1 [30] <3.5> Calculate the product of A and B by hand, assuming A and B are stored in the modified 16-bit NVIDIA format described in 3.11.2. Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps; however, as is done in the example in the text, you can do the multiplication in human-readable format instead of using the techniques described in Exercises 3.4 through 3.6. Indicate if there is overflow or underflow. Write your answer as a 16-bit pattern, and also as a decimal number. How accurate is your result? How does it compare to the number you get if you do the multiplication on a calculator? 3.12.2 [60] <3.5> Write an MIPS assembly language program to calculate the product of A and B, assuming they are stored in IEEE 754 format. Indicate if there is overflow or underflow. (Remember, IEEE 754 assumes 1 guard, 1 round bit, and 1 sticky bit, and rounds to the nearest even.) 3.12.3 [60] <3.5> Write an MIPS assembly language program to calculate the product of A and B, assuming they are stored using the format described in 3.11.1. Now modify the program to calculate the sum assuming the format described in 3.11.3. Which format is easier for a programmer to deal with? How do they each compare to the IEEE 754 format? (Do not worry about sticky bits for this question.) The following table shows further pairs of decimal numbers. A B a. 8.625 × 101 –4.875 × 100 b. 1.84375 × 100 1.3203125 × 100 3.12.4 [30] <3.5> Calculate by hand A divided by B. Show all the steps neces- sary to achieve your answer. Assume there is a guard, a round bit, and a sticky bit, and use them if necessary. Write the final answer in both the 16-bit floating point format described in 3.11.2 and in decimal and compare the decimal result to that which you get if you use a calculator. The Livermore Loops are a set of floating point–intensive kernels taken from scientific programs run at Lawrence Livermore Laboratory. The following table identifies individual kernels from the set. a. Livermore Loop 3 b. Livermore Loop 9
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3.12.5 [60] <3.5> Write the loop in MIPS assembly language. 3.12.6 [60] <3.5> Describe in detail one technique for performing floating point division in a digital computer. Be sure to include references to the sources you used. Exercise 3.13 Operations performed on fixed-point integers behave the way one expects—the commutative, associative, and distributive laws all hold. This is not always the case when working with floating point numbers, however. Let’s first look at the associa- tive law. The following table shows sets of decimal numbers. A B C a. 3.984375 × 10–1 3.4375 × 10–1 1.771 × 103 b. 3.96875 × 100 8.46875 × 100 2.1921875 × 101 3.13.1 [20] <3.2, 3.5, 3.6> Calculate (A + B) + C by hand, assuming A, B, and C are stored in the modified 16-bit NVIDIA format described in 3.11.2 (and also described in the text). Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps, and write your answer in both the 16-bit float- ing point format and in decimal. 3.13.2 [20] <3.2, 3.5, 3.6> Calculate A + (B + C) by hand, assuming A, B, and C are stored in the modified 16-bit NVIDIA format described in 3.11.2 (and also described in the text). Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps, and write your answer in both the 16-bit float- ing point format and in decimal. 3.13.3 [10] <3.2, 3.5, 3.6> Based on your answers to 3.13.1 and 3.13.2, does (A + B) + C = A + (B + C)? The following table shows further sets of decimal numbers. A B C a. 3.41796875 10–3 6.34765625 × 10–3 1.05625 × 102 b. 1.140625 × 102 –9.135 × 102 9.84375 × 10–1 3.13.4 [30] <3.3, 3.5, 3.6> Calculate (A × B) × C by hand, assuming A, B, and C are stored in the modified 16-bit NVIDIA format described in 3.11.2 (and also described in the text). Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps, and write your answer in both the 16-bit float- ing point format and in decimal. 3.11 Exercises 295
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296 Chapter 3 Arithmetic for Computers 3.13.5 [30] <3.3, 3.5, 3.6> Calculate A × (B × C) by hand, assuming A, B, and C are stored in the modified 16-bit NVIDIA format described in 3.11.2 (and also described in the text). Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps, and write your answer in both the 16-bit float- ing point format and in decimal. 3.13.6 [10] <3.3, 3.5, 3.6> Based on your answers to 3.13.4 and 3.13.5, does (A × B) × C = A × (B × C)? Exercise 3.14 The Associative law is not the only one that does not always hold in dealing with floating point numbers. There are other oddities that occur as well. The following table shows sets of decimal numbers. A B C a. 1.666015625 × 100 1.9760 × 104 –1.9744 × 104 b. 3.48 × 102 6.34765625 × 10–2 –4.052734375 × 10–2 3.14.1 [30] <3.2, 3.3, 3.5, 3.6> Calculate A × (B + C) by hand, assuming A, B, and C are stored in the modified 16-bit NVIDIA format described in 3.11.2 (and also described in the text). Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps, and write your answer in both the 16-bit float- ing point format and in decimal. 3.14.2 [30] <3.2, 3.3, 3.5, 3.6> Calculate (A × B) + (A × C) by hand, assuming A, B, and C are stored in the modified 16-bit NVIDIA format described in 3.11.2 (and also described in the text). Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps, and write your answer in both the 16-bit floating point format and in decimal. 3.14.3 [10] <3.2, 3.3, 3.5, 3.6> Based on your answers to 3.14.1. and 3.14.2, does (A × B) + (A × C) = A × (B + C)? The following table shows pairs, each consisting of a fraction and an integer. A B a. –1/4 4 b. 1/10 10 3.14.4 [10] <3.5> Using the IEEE 754 floating point format, write down the bit pattern that would represent A. Can you represent A exactly?
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3.14.5 [10] <3.2, 3.3, 3.5, 3.6> What do you get if you add A to itself B times? What is A × B? Are they the same? What should they be? 3.14.6 [60] <3.2, 3.3, 3.4, 3.5, 3.6> What do you get if you take the square root of B and then multiply that value by itself? What should you get? Do for both single and double precision floating point numbers. (Write a program to do these calculations.) Exercise 3.15 Binary numbers are used in the mantissa field, but they do not have to be. IBM used base 16 numbers, for example, in some of their floating point formats. There are other approaches that are possible as well, each with their own particular advantages and disadvantages. The following table shows fractions to be repre- sented in various floating point formats. a. 1/3 b. 1/10 3.15.1 [10] <3.5, 3.6> Write down the bit pattern in the mantissa assuming a floating point format that uses binary numbers in the mantissa (essentially what you have been doing in this chapter). Assume there are 24 bits, and you do not need to normalize. Is this representation exact? 3.15.2 [10] <3.5, 3.6> Write down the bit pattern in the mantissa assuming a floating point format that uses Binary Coded Decimal (base 10) numbers in the mantissa instead of base 2. Assume there are 24 bits, and you do not need to nor- malize. Is this representation exact? 3.15.3 [10] <3.5, 3.6> Write down the bit pattern assuming that we are using base 15 numbers in the mantissa instead of base 2. (Base 16 numbers use the sym- bols 0–9 and A–F. Base 15 numbers would use 0–9 and A–E.) Assume there are 24 bits, and you do not need to normalize. Is this representation exact? 3.15.4 [20] <3.5, 3.6> Write down the bit pattern assuming that we are using base 30 numbers in the mantissa instead of base 2. (Base 16 numbers use the sym- bols 0–9 and A–F. Base 30 numbers would use 0–9 and A–T.) Assume there are 20 bits, and you do not need to normalize. Is this representation exact? Do you see any advantage to using this approach? §3.2, page 229: 2. §3.5, page 269: 3. Answers to Check Yourself 3.11 Exercises 297
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4 In a major matter, no details are small. French Proverb The Processor 4.1 Introduction 300 4.2 Logic Design Conventions 303 4.3 Building a Datapath 307 4.4 A Simple Implementation Scheme 316 4.5 An Overview of Pipelining 330 4.6 Pipelined Datapath and Control 344 4.7 Data Hazards: Forwarding versus Stalling 363 4.8 Control Hazards 375 4.9 Exceptions 384 Computer Organization and Design. DOI: 10.1016/B978-0-12-374750-1.00004-9 © 2012 Elsevier, Inc. All rights reserved.
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4.10 Parallelism and Advanced Instruction-Level Parallelism 391 4.11 Real Stuff: the AMD Opteron X4 (Barcelona) Pipeline 404 4.12 Advanced Topic: an Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 406 4.13 Fallacies and Pitfalls 407 4.14 Concluding Remarks 408 4.15 Historical Perspective and Further Reading 409 4.16 Exercises 409 The Five Classic Components of a Computer
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300 Chapter 4 The Processor 4.1 Introduction Chapter 1 explains that the performance of a computer is determined by three key factors: instruction count, clock cycle time, and clock cycles per instruction (CPI). Chapter 2 explains that the compiler and the instruction set architecture determine the instruction count required for a given program. However, the implementation of the processor determines both the clock cycle time and the number of clock cycles per instruction. In this chapter, we construct the datapath and control unit for two different implementations of the MIPS instruction set. This chapter contains an explanation of the principles and techniques used in implementing a processor, starting with a highly abstract and simplified overview in this section. It is followed by a section that builds up a datapath and constructs a simple version of a processor sufficient to implement an instruction set like MIPS. The bulk of the chapter covers a more realistic pipelined MIPS implementation, followed by a section that develops the concepts necessary to implement more complex instruction sets, like the x86. For the reader interested in understanding the high-level interpretation of instructions and its impact on program performance, this initial section and Section 4.5 present the basic concepts of pipelining. Recent trends are covered in Section 4.10, and Section 4.11 describes the recent AMD Opteron X4 (Barcelona) microprocessor. These sections provide enough background to understand the pipeline concepts at a high level. For the reader interested in understanding the processor and its performance in more depth, Sections 4.3, 4.4, and 4.6 will be useful. Those interested in learn ing how to build a processor should also cover 4.2, 4.7, 4.8, and 4.9. For readers with an interest in modern hardware design, Section 4.12 on the CD describes how hardware design languages and CAD tools are used to implement hardware, and then how to use a hardware design language to describe a pipelined imple- mentation. It also gives several more illustrations of how pipelining hardware executes. A Basic MIPS Implementation We will be examining an implementation that includes a subset of the core MIPS instruction set: ■ ■The memory-reference instructions load word (lw) and store word (sw) ■ ■The arithmetic-logical instructions add, sub, AND, OR, and slt ■ ■The instructions branch equal (beq) and jump (j), which we add last
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4.1 Introduction 301 This subset does not include all the integer instructions (for example, shift, multiply, and divide are missing), nor does it include any floating-point instructions. How- ever, the key principles used in creating a datapath and designing the control are illustrated. The implementation of the remaining instructions is similar. In examining the implementation, we will have the opportunity to see how the instruction set architecture determines many aspects of the implementation, and how the choice of various implementation strategies affects the clock rate and CPI for the computer. Many of the key design principles introduced in Chapter 1 can be illustrated by looking at the implementation, such as the guidelines Make the common case fast and Simplicity favors regularity. In addition, most concepts used to implement the MIPS subset in this chapter are the same basic ideas that are used to construct a broad spectrum of computers, from high-performance servers to general-purpose microprocessors to embedded processors. An Overview of the Implementation In Chapter 2, we looked at the core MIPS instructions, including the integer arithmetic-logical instructions, the memory-reference instructions, and the branch instructions. Much of what needs to be done to implement these instructions is the same, independent of the exact class of instruction. For every instruction, the first two steps are identical: 1. Send the program counter (PC) to the memory that contains the code and fetch the instruction from that memory. 2. Read one or two registers, using fields of the instruction to select the registers to read. For the load word instruction, we need to read only one register, but most other instructions require that we read two registers. After these two steps, the actions required to complete the instruction depend on the instruction class. Fortunately, for each of the three instruction classes (memory-reference, arithmetic-logical, and branches), the actions are largely the same, independent of the exact instruction. The simplicity and regularity of the MIPS instruction set simplifies the implementation by making the execution of many of the instruction classes similar. For example, all instruction classes, except jump, use the arithmetic-logical unit (ALU) after reading the registers. The memory-reference instructions use the ALU for an address calculation, the arithmetic-logical instructions for the operation execution, and branches for comparison. After using the ALU, the actions required to complete various instruction classes differ. A memory-reference instruction will need to access the memory either to read data for a load or write data for a store. An arithmetic-logical or load instruction must write the data from the ALU or memory back into a register. Lastly, for a branch instruction, we may need to change the next instruction address based on the comparison; otherwise, the PC should be incremented by 4 to get the address of the next instruction.
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302 Chapter 4 The Processor Figure 4.1 shows the high-level view of a MIPS implementation, focusing on the various functional units and their interconnection. Although this figure shows most of the flow of data through the processor, it omits two important aspects of instruction execution. FIGURE 4.1 An abstract view of the implementation of the MIPS subset showing the major functional units and the major connections between them. All instructions start by using the program counter to supply the instruction address to the instruction memory. After the instruction is fetched, the register operands used by an instruction are specified by fields of that instruction. Once the register operands have been fetched, they can be operated on to compute a memory address (for a load or store), to compute an arithmetic result (for an integer arithmetic-logical instruction), or a compare (for a branch). If the instruction is an arithmetic-logical instruction, the result from the ALU must be written to a register. If the operation is a load or store, the ALU result is used as an address to either store a value from the registers or load a value from memory into the registers. The result from the ALU or memory is written back into the register file. Branches require the use of the ALU output to determine the next instruction address, which comes either from the ALU (where the PC and branch offset are summed) or from an adder that increments the current PC by 4. The thick lines interconnecting the functional units represent buses, which consist of multiple signals. The arrows are used to guide the reader in knowing how information flows. Since signal lines may cross, we explicitly show when crossing lines are connected by the presence of a dot where the lines cross. Data PC Address Instruction Instruction memory Registers ALU Address Data Data memory Add Add 4 Register # Register # Register # First, in several places, Figure 4.1 shows data going to a particular unit as coming from two different sources. For example, the value written into the PC can come from one of two adders, the data written into the register file can come from either the ALU or the data memory, and the second input to the ALU can come from a register or the immediate field of the instruction. In practice, these data lines cannot simply be wired together; we must add a logic element that chooses from among the multiple sources and steers one of those sources to its destination. This selection is commonly done with a device called a multiplexor, although this device
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