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A stack frame may be built in many different ways; however, the caller and callee must agree on the sequence of steps. The steps below describe the calling convention used on most MIPS machines. This convention comes into play at three points during a procedure call: immediately before the caller invokes the callee, ju... | Hennesey_Page_801_Chunk801 |
B-26 Appendix B Assemblers, Linkers, and the SPIM Simulator Before a called routine starts running, it must take the following steps to set up its stack frame: 1. Allocate memory for the frame by subtracting the frame’s size from the stack pointer. 2. Save callee-saved registers in the frame. A callee must save the val... | Hennesey_Page_802_Chunk802 |
to the active stack frame, which permits a single load or store instruction to access values in the frame. In addition, recursion is a valuable programming technique. Procedure Call Example As an example, consider the C routine main () { printf (“The factorial of 10 is %d\n”, fact (10)); } int fact (int n) { if (n < 1... | Hennesey_Page_803_Chunk803 |
B-28 Appendix B Assemblers, Linkers, and the SPIM Simulator li $a0,10 # Put argument (10) in $a0 jal fact # Call factorial function la $a0,$LC # Put format string in $a0 move $a1,$v0 # Move fact result to $a1 jal printf # Call the print function Finally, after printing the factorial, main returns. But first, it must re... | Hennesey_Page_804_Chunk804 |
jal fact # Call factorial function lw $v1,0($fp) # Load n mul $v0,$v0,$v1 # Compute fact(n-1) * n Finally, the factorial routine restores the callee-saved registers and returns the value in register $v0: $L1: # Result is in $v0 lw $ra, 20($sp) # Restore $ra lw $fp, 16($sp) # Restore $fp addiu $sp, $sp, 32 # Pop stack j... | Hennesey_Page_805_Chunk805 |
B-30 Appendix B Assemblers, Linkers, and the SPIM Simulator ANSWER Elaboration: The difference between the MIPS compiler and the gcc compiler is that the MIPS compiler usually does not use a frame pointer, so this register is available as another callee-saved register, $s8. This change saves a couple of instructions in... | Hennesey_Page_806_Chunk806 |
lifetime of the function, which includes several calls that could potentially modify registers. .text .globl tak tak: subu $sp, $sp, 40 sw $ra, 32($sp) sw $s0, 16($sp) # x move $s0, $a0 sw $s1, 20($sp) # y move $s1, $a1 sw $s2, 24($sp) # z move $s2, $a2 sw $s3, 28($sp) # temporary The routine then begins execution by t... | Hennesey_Page_807_Chunk807 |
B-32 Appendix B Assemblers, Linkers, and the SPIM Simulator addiu $a0, $s2, -1 move $a1, $s0 move $a2, $s1 move $s0, $v0 jal tak # tak (z - 1, x, y) After the three inner recursive calls, we are ready for the final recursive call. After the call, the function’s result is in $v0 and control jumps to the function’s epilo... | Hennesey_Page_808_Chunk808 |
li $a2, 6 jal tak # tak(18, 12, 6) move $a0, $v0 li $v0, 1 # print_int syscall syscall lw $ra, 16($sp) addiu $sp, $sp, 24 jr $ra B.7 Exceptions and Interrupts Section 4.9 of Chapter 4 describes the MIPS exception facility, which responds both to exceptions caused by errors during an instruction’s execution and to exter... | Hennesey_Page_809_Chunk809 |
B-34 Appendix B Assemblers, Linkers, and the SPIM Simulator These seven registers are part of coprocessor 0’s register set. They are accessed by the mfc0 and mtc0 instructions. After an exception, register EPC contains the address of the instruction that was executing when the exception occurred. If the exception was c... | Hennesey_Page_810_Chunk810 |
is raised at a given hardware or software level. The exception code register describes the cause of an exception through the following codes: Number Name Cause of exception 0 Int interrupt (hardware) 4 AdEL address error exception (load or instruction fetch) 5 AdES address error exception (store) 6 IBE bus error on ins... | Hennesey_Page_811_Chunk811 |
B-36 Appendix B Assemblers, Linkers, and the SPIM Simulator such as page faults are requests from a process to the operating system to perform a service, such as bringing in a page from disk. The operating system processes these requests and resumes the process. The final type of exceptions are interrupts from external... | Hennesey_Page_812_Chunk812 |
mfc0 $k0, $13 # Move Cause into $k0 srl $a0, $k0, 2 # Extract ExcCode field andi $a0, $a0, Oxf bgtz $a0, done # Branch if ExcCode is Int (0) mov $a0, $k0 # Move Cause into $a0 mfco $a1, $14 # Move EPC into $a1 jal print_excp # Print exception error message Before returning, the exception handler clears the Cause regist... | Hennesey_Page_813_Chunk813 |
B-38 Appendix B Assemblers, Linkers, and the SPIM Simulator Elaboration: On real MIPS processors, the return from an exception handler is more complex. The exception handler cannot always jump to the instruction following EPC. For example, if the instruction that caused the exception was in a branch instruction’s delay... | Hennesey_Page_814_Chunk814 |
Bit 1 of the Receiver Control register is the keyboard “interrupt enable.” This bit may be both read and written by a program. The interrupt enable is initially 0. If it is set to 1 by a program, the terminal requests an interrupt at hardware level 1 whenever a character is typed, and the ready bit becomes 1. However, ... | Hennesey_Page_815_Chunk815 |
B-40 Appendix B Assemblers, Linkers, and the SPIM Simulator and is read-only. If this bit is 1, the transmitter is ready to accept a new character for output. If it is 0, the transmitter is still busy writing the previous character. Bit 1 is “interrupt enable’’ and is readable and writable. If this bit is set to 1, the... | Hennesey_Page_816_Chunk816 |
MIPS programs. It contains a debugger and provides a few operating system–like services. SPIM is much slower than a real computer (100 or more times). However, its low cost and wide availability cannot be matched by real hardware! An obvious question is, “Why use a simulator when most people have PCs that contain proc... | Hennesey_Page_817_Chunk817 |
B-42 Appendix B Assemblers, Linkers, and the SPIM Simulator By default, SPIM simulates the richer virtual machine, since this is the machine that most programmers will find useful. However, SPIM can also simulate the delayed branches and loads in the actual hardware. Below, we describe the virtual machine and only ment... | Hennesey_Page_818_Chunk818 |
Another surprise (which occurs on the real machine as well) is that a pseudo- instruction expands to several machine instructions. When you single-step or exam ine memory, the instructions that you see are different from the source program. The correspondence between the two sets of instructions is fairly simple, sinc... | Hennesey_Page_819_Chunk819 |
B-44 Appendix B Assemblers, Linkers, and the SPIM Simulator li $v0, 4 # system call code for print_str la $a0, str # address of string to print syscall # print the string li $v0, 1 # system call code for print_int li $a0, 5 # integer to print syscall # print it The print_int system call is passed an integer and prints ... | Hennesey_Page_820_Chunk820 |
Warning: Programs that use these syscalls to read from the terminal should not use memory-mapped I/O (see Section B.8). sbrk returns a pointer to a block of memory containing n additional bytes. exit stops the program SPIM is running. exit2 terminates the SPIM program, and the argument to exit2 becomes the value retur... | Hennesey_Page_821_Chunk821 |
B-46 Appendix B Assemblers, Linkers, and the SPIM Simulator object must be stored at even addresses, and a full word object must be stored at addresses that are a multiple of four. However, MIPS provides some instructions to manipulate unaligned data (lwl, lwr, swl, and swr). Elaboration: The MIPS assembler (and SPIM) ... | Hennesey_Page_822_Chunk822 |
lui $at, 4096 addu $at, $at, $a1 lw $a0, 8($at) The first instruction loads the upper bits of the label’s address into register $at, which is the register that the assembler reserves for its own use. The second instruction adds the contents of register $a1 to the label’s partial address. Finally, the load instruction u... | Hennesey_Page_823_Chunk823 |
B-48 Appendix B Assemblers, Linkers, and the SPIM Simulator .asciiz str Store the string str in memory and null-terminate it. .byte b1,..., bn Store the n values in successive bytes of memory. .data <addr> Subsequent items are stored in the data segment. If the optional argument addr is present, subse quent items are... | Hennesey_Page_824_Chunk824 |
.text <addr> Subsequent items are put in the user text segment. In SPIM, these items may only be instructions or words (see the .word directive below). If the optional argument addr is present, subsequent items are stored starting at address addr. .word w1,..., wn Store the n 32-bit quantities in successive memory... | Hennesey_Page_825_Chunk825 |
B-50 Appendix B Assemblers, Linkers, and the SPIM Simulator FIGURE B.10.2 MIPS opcode map. The values of each field are shown to its left. The first column shows the values in base 10, and the second shows base 16 for the op field (bits 31 to 26) in the third column. This op field completely specifies the MIPS operatio... | Hennesey_Page_826_Chunk826 |
Pseudoinstructions follow roughly the same conventions, but omit instruction encoding information. For example: Multiply (without overflow) mul rdest, rsrc1, src2 pseudoinstruction In pseudoinstructions, rdest and rsrc1 are registers and src2 is either a regis ter or an immediate value. In general, the assembler and S... | Hennesey_Page_827_Chunk827 |
B-52 Appendix B Assemblers, Linkers, and the SPIM Simulator AND and rd, rs, rt 0 rs rt rd 0 0x24 6 5 5 5 5 6 Put the logical AND of registers rs and rt into register rd. AND immediate andi rt, rs, imm 0xc rs rt imm 6 5 5 16 Put the logical AND of register rs and the zero-extended immediate into reg- ister rt. Count lea... | Hennesey_Page_828_Chunk828 |
Divide (with overflow) div rdest, rsrc1, src2 pseudoinstruction Divide (without overflow) divu rdest, rsrc1, src2 pseudoinstruction Put the quotient of register rsrc1 and src2 into register rdest. Multiply mult rs, rt 0 rs rt 0 0x18 6 5 5 10 6 Unsigned multiply multu rs, rt 0 rs rt 0 0x19 6 5 5 10 6 Multiply registers ... | Hennesey_Page_829_Chunk829 |
B-54 Appendix B Assemblers, Linkers, and the SPIM Simulator Multiply add madd rs, rt 0x1c rs rt 0 0 6 5 5 10 6 Unsigned multiply add maddu rs, rt 0x1c rs rt 0 1 6 5 5 10 6 Multiply registers rs and rt and add the resulting 64-bit product to the 64-bit value in the concatenated registers lo and hi. Multiply subtract msu... | Hennesey_Page_830_Chunk830 |
NOT not rdest, rsrc pseudoinstruction Put the bitwise logical negation of register rsrc into register rdest. OR or rd, rs, rt 0 rs rt rd 0 0x25 6 5 5 5 5 6 Put the logical OR of registers rs and rt into register rd. OR immediate ori rt, rs, imm 0xd rs rt imm 6 5 5 16 Put the logical OR of register rs and the zero-exten... | Hennesey_Page_831_Chunk831 |
B-56 Appendix B Assemblers, Linkers, and the SPIM Simulator Shift right arithmetic sra rd, rt, shamt 0 rs rt rd shamt 3 6 5 5 5 5 6 Shift right arithmetic variable srav rd, rt, rs 0 rs rt rd 0 7 6 5 5 5 5 6 Shift right logical srl rd, rt, shamt 0 rs rt rd shamt 2 6 5 5 5 5 6 Shift right logical variable srlv rd, rt, rs... | Hennesey_Page_832_Chunk832 |
Subtract (without overflow) subu rd, rs, rt 0 rs rt rd 0 0x23 6 5 5 5 5 6 Put the difference of registers rs and rt into register rd. Exclusive OR xor rd, rs, rt 0 rs rt rd 0 0x26 6 5 5 5 5 6 Put the logical XOR of registers rs and rt into register rd. XOR immediate xori rt, rs, imm 0xe rs rt Imm 6 5 5 16 Put the logic... | Hennesey_Page_833_Chunk833 |
B-58 Appendix B Assemblers, Linkers, and the SPIM Simulator Set less than unsigned sltu rd, rs, rt 0 rs rt rd 0 0x2b 6 5 5 5 5 6 Set register rd to 1 if register rs is less than rt, and to 0 otherwise. Set less than immediate slti rt, rs, imm 0xa rs rt imm 6 5 5 16 Set less than unsigned immediate sltiu rt, rs, imm 0xb... | Hennesey_Page_834_Chunk834 |
Set greater than unsigned sgtu rdest, rsrc1, rsrc2 pseudoinstruction Set register rdest to 1 if register rsrc1 is greater than rsrc2, and to 0 otherwise. Set less than equal sle rdest, rsrc1, rsrc2 pseudoinstruction Set less than equal unsigned sleu rdest, rsrc1, rsrc2 pseudoinstruction Set register rdest to 1 if regis... | Hennesey_Page_835_Chunk835 |
B-60 Appendix B Assemblers, Linkers, and the SPIM Simulator the instruction in the branch’s delay slot if the branch is not taken. Do not use these instructions; they may be removed in subsequent versions of the architecture. SPIM implements these instructions, but they are not described further. Branch instruction b ... | Hennesey_Page_836_Chunk836 |
Branch on greater than equal zero and link bgezal rs, label 1 rs 0x11 Offset 6 5 5 16 Conditionally branch the number of instructions specified by the offset if register rs is greater than or equal to 0. Save the address of the next instruction in reg- ister 31. Branch on greater than zero bgtz rs, label 7 rs 0 Offset... | Hennesey_Page_837_Chunk837 |
B-62 Appendix B Assemblers, Linkers, and the SPIM Simulator Branch on not equal bne rs, rt, label 5 rs rt Offset 6 5 5 16 Conditionally branch the number of instructions specified by the offset if register rs is not equal to rt. Branch on equal zero beqz rsrc, label pseudoinstruction Conditionally branch to the instru... | Hennesey_Page_838_Chunk838 |
Branch on less than equal unsigned bleu rsrc1, src2, label pseudoinstruction Conditionally branch to the instruction at the label if register rsrc1 is less than or equal to src2. Branch on less than blt rsrc1, rsrc2, label pseudoinstruction Branch on less than unsigned bltu rsrc1, rsrc2, label pseudoinstruction Conditi... | Hennesey_Page_839_Chunk839 |
B-64 Appendix B Assemblers, Linkers, and the SPIM Simulator Jump and link register jalr rs, rd 0 rs 0 rd 0 9 6 5 5 5 5 6 Unconditionally jump to the instruction whose address is in register rs. Save the address of the next instruction in register rd (which defaults to 31). Jump register jr rs 0 rs 0 8 6 5 15 6 Uncondit... | Hennesey_Page_840_Chunk840 |
Trap if greater equal tge rs, rt 0 rs rt 0 0x30 6 5 5 10 6 Unsigned trap if greater equal tgeu rs, rt 0 rs rt 0 0x31 6 5 5 10 6 If register rs is greater than or equal to register rt, raise a Trap exception. Trap if greater equal immediate tgei rs, imm 1 rs 8 imm 6 5 5 16 Unsigned trap if greater equal immediate tgeiu ... | Hennesey_Page_841_Chunk841 |
B-66 Appendix B Assemblers, Linkers, and the SPIM Simulator Unsigned trap if less than immediate tltiu rs, imm 1 rs b imm 6 5 5 16 If register rs is less than the sign-extended value imm, raise a Trap exception. Load Instructions Load address la rdest, address pseudoinstruction Load computed address—not the contents of... | Hennesey_Page_842_Chunk842 |
Load word lw rt, address 0x23 rs rt Offset 6 5 5 16 Load the 32-bit quantity (word) at address into register rt. Load word coprocessor 1 lwcl ft, address 0x31 rs rt Offset 6 5 5 16 Load the word at address into register ft in the floating-point unit. Load word left lwl rt, address 0x22 rs rt Offset 6 5 5 16 Load word r... | Hennesey_Page_843_Chunk843 |
B-68 Appendix B Assemblers, Linkers, and the SPIM Simulator Unaligned load halfword unsigned ulhu rdest, address pseudoinstruction Load the 16-bit quantity (halfword) at the possibly unaligned address into register rdest. The halfword is sign-extended by ulh, but not ulhu. Unaligned load word ulw rdest, address pseudo... | Hennesey_Page_844_Chunk844 |
Store word sw rt, address 0x2b rs rt Offset 6 5 5 16 Store the word from register rt at address. Store word coprocessor 1 swcl ft, address 0x31 rs ft Offset 6 5 5 16 Store the floating-point value in register ft of floating-point coprocessor at address. Store double coprocessor 1 sdcl ft, address 0x3d rs ft Offset 6 5 ... | Hennesey_Page_845_Chunk845 |
B-70 Appendix B Assemblers, Linkers, and the SPIM Simulator Unaligned store halfword ush rsrc, address pseudoinstruction Store the low halfword from register rsrc at the possibly unaligned address. Unaligned store word usw rsrc, address pseudoinstruction Store the word from register rsrc at the possibly unaligned addre... | Hennesey_Page_846_Chunk846 |
Move from lo mflo rd 0 0 rd 0 0x12 6 10 5 5 6 The multiply and divide unit produces its result in two additional registers, hi and lo. These instructions move values to and from these registers. The multiply, divide, and remainder pseudoinstructions that make this unit appear to operate on the general registers move th... | Hennesey_Page_847_Chunk847 |
B-72 Appendix B Assemblers, Linkers, and the SPIM Simulator Move double from coprocessor 1 mfc1.d rdest, frsrc1 pseudoinstruction Move floating-point registers frsrc1 and frsrc1 + 1 to CPU registers rdest and rdest + 1. Move to coprocessor 0 mtc0 rd, rt 0x10 4 rt rd 0 6 5 5 5 11 Move to coprocessor 1 mtc1 rd, fs 0x11 4... | Hennesey_Page_848_Chunk848 |
Move conditional on FP true movt rd, rs, cc 0 rs cc 1 rd 0 1 6 5 3 2 5 5 6 Move CPU register rs to register rd if FPU condition code flag number cc is 1. If cc is omitted from the instruction, condition code bit 0 is assumed. Floating-Point Instructions The MIPS has a floating-point coprocessor (numbered 1) that operat... | Hennesey_Page_849_Chunk849 |
B-74 Appendix B Assemblers, Linkers, and the SPIM Simulator Floating-point addition single add.s fd, fs, ft 0x11 0x10 ft fs fd 0 6 5 5 5 5 6 Compute the sum of the floating-point doubles (singles) in registers fs and ft and put it in register fd. Floating-point ceiling to word ceil.w.d fd, fs 0x11 0x11 0 fs fd 0xe 6 5 ... | Hennesey_Page_850_Chunk850 |
Compare the floating-point double (single) in register fs against the one in ft and set the floating-point condition flag cc to 1 if the first is less than or equal to the second. If cc is omitted, condition code flag 0 is assumed. Compare less than double c.lt.d cc fs, ft 0x11 0x11 ft fs cc 0 FC 0xc 6 5 5 5 3 2 2 4 Co... | Hennesey_Page_851_Chunk851 |
B-76 Appendix B Assemblers, Linkers, and the SPIM Simulator Convert double to integer cvt.w.d fd, fs 0x11 0x11 0 fs fd 0x24 6 5 5 5 5 6 Convert single to integer cvt.w.s fd, fs 0x11 0x10 0 fs fd 0x24 6 5 5 5 5 6 Convert the double or single precision floating-point number in register fs to an integer and put it in regi... | Hennesey_Page_852_Chunk852 |
Load floating-point single l.s fdest, address pseudoinstruction Load the floating-point double (single) at address into register fdest. Move floating-point double mov.d fd, fs 0x11 0x11 0 fs fd 6 6 5 5 5 5 6 Move floating-point single mov.s fd, fs 0x11 0x10 0 fs fd 6 6 5 5 5 5 6 Move the floating-point double (single) ... | Hennesey_Page_853_Chunk853 |
B-78 Appendix B Assemblers, Linkers, and the SPIM Simulator Move the floating-point double (single) from register fs to register fd if condition code flag cc is 1. If cc is omitted, condition code flag 0 is assumed. Move conditional floating-point double not zero movn.d fd, fs, rt 0x11 0x11 rt fs fd 0x13 6 5 5 5 5 6 M... | Hennesey_Page_854_Chunk854 |
Negate single neg.s fd, fs 0x11 0x10 0 fs fd 7 6 5 5 5 5 6 Negate the floating-point double (single) in register fs and put it in register fd. Floating-point round to word round.w.d fd, fs 0x11 0x11 0 fs fd 0xc 6 5 5 5 5 6 round.w.s fd, fs 0x11 0x10 0 fs fd 0xc Round the floating-point double (single) value in register... | Hennesey_Page_855_Chunk855 |
B-80 Appendix B Assemblers, Linkers, and the SPIM Simulator Floating-point subtract single sub.s fd, fs, ft 0x11 0x10 ft fs fd 1 6 5 5 5 5 6 Compute the difference of the floating-point doubles (singles) in registers fs and ft and put it in register fd. Floating-point truncate to word trunc.w.d fd, fs 0x11 0x11 0 fs fd... | Hennesey_Page_856_Chunk856 |
B.11 Concluding Remarks Programming in assembly language requires a programmer to trade helpful fea- tures of high-level languages—such as data structures, type checking, and control constructs—for complete control over the instructions that a computer executes. External constraints on some applications, such as respon... | Hennesey_Page_857_Chunk857 |
B-82 Appendix B Assemblers, Linkers, and the SPIM Simulator B.12 Exercises B.1 [5] <§B.5> Section B.5 described how memory is partitioned on most MIPS systems. Propose another way of dividing memory that meets the same goals. B.2 [20] <§B.6> Rewrite the code for fact to use fewer instructions. B.3 [5] <§B.7> Is it ever... | Hennesey_Page_858_Chunk858 |
B.10 [10] <§§B.6, B.9> Using SPIM, write and test a recursive program for solving the classic mathematical recreation, the Towers of Hanoi puzzle. (This will require the use of stack frames to support recursion.) The puzzle consists of three pegs (1, 2, and 3) and n disks (the number n can vary; typical values might b... | Hennesey_Page_859_Chunk859 |
1 INTRODUCTION A modern computer consists of one or more processors, some main memory, disks, printers, a keyboard, a mouse, a display, network interfaces, and various other input/output devices. All in all, a complex system.oo If every application pro- grammer had to understand how all these things work in detail, no ... | OS_Page_1_Chunk1 |
2 INTRODUCTION CHAP. 1 complete access to all the hardware and can execute any instruction the machine is capable of executing. The rest of the software runs in user mode, in which only a subset of the machine instructions is available. In particular, those instructions that affect control of the machine or do I/O )Inp... | OS_Page_2_Chunk2 |
SEC. 1.1 WHAT IS AN OPERATING SYSTEM? 3 system (such as the file system) run in user space. In such systems, it is difficult to draw a clear boundary. Everything running in kernel mode is clearly part of the operating system, but some programs running outside it are arguably also part of it, or at least closely associa... | OS_Page_3_Chunk3 |
4 INTRODUCTION CHAP. 1 providing application programmers (and application programs, naturally) a clean abstract set of resources instead of the messy hardware ones and managing these hardware resources. Depending on who is doing the talking, you might hear mostly about one function or the other. Let us now look at both... | OS_Page_4_Chunk4 |
SEC. 1.1 WHAT IS AN OPERATING SYSTEM? 5 Operating system Hardware Ugly interface Beautiful interface Application programs Figure 1-2. Operating systems turn ugly hardware into beautiful abstractions. It should be noted that the operating system’s real customers are the applica- tion programs (via the application progra... | OS_Page_5_Chunk5 |
6 INTRODUCTION CHAP. 1 few lines of printout might be from program 1, the next few from program 2, then some from program 3, and so forth. The result would be utter chaos. The operating system can bring order to the potential chaos by buffering all the output destined for the printer on the disk. When one program is fi... | OS_Page_6_Chunk6 |
SEC. 1.2 HISTORY OF OPERATING SYSTEMS 7 run, we will look at successive generations of computers to see what their operat- ing systems were like. This mapping of operating system generations to computer generations is crude, but it does provide some structure where there would other- wise be none. The progression given... | OS_Page_7_Chunk7 |
8 INTRODUCTION CHAP. 1 straightforward mathematical and numerical calculations, such as grinding out tables of sines, cosines, and logarithms, or computing artillery trajectories. By the early 1950s, the routine had improved somewhat with the introduction of punched cards. It was now possible to write programs on cards... | OS_Page_8_Chunk8 |
SEC. 1.2 HISTORY OF OPERATING SYSTEMS 9 1401 7094 1401 (a) (b) (c) (d) (e) (f) Card reader Tape drive Input tape Output tape System tape Printer Figure 1-3. An early batch system. (a) Programmers bring cards to 1401. (b) 1401 reads batch of jobs onto tape. (c) Operator carries input tape to 7094. (d) 7094 does computin... | OS_Page_9_Chunk9 |
10 INTRODUCTION CHAP. 1 $JOB, 10,7710802, MARVIN TANENBAUM $FORTRAN $LOAD $RUN $END Data for program FORTRAN program Figure 1-4. Structure of a typical FMS job. character-oriented, commercial computers, such as the 1401, which were widely used for tape sorting and printing by banks and insurance companies. Developing a... | OS_Page_10_Chunk10 |
SEC. 1.2 HISTORY OF OPERATING SYSTEMS 11 was an immediate success, and the idea of a family of compatible computers was soon adopted by all the other major manufacturers. The descendants of these ma- chines are still in use at computer centers today. Now adays they are often used for managing huge databases (e.g., for ... | OS_Page_11_Chunk11 |
12 INTRODUCTION CHAP. 1 Job 3 Job 2 Job 1 Operating system Memory partitions Figure 1-5. A multiprogramming system with three jobs in memory. Another major feature present in third-generation operating systems was the ability to read jobs from cards onto the disk as soon as they were brought to the computer room. Then,... | OS_Page_12_Chunk12 |
SEC. 1.2 HISTORY OF OPERATING SYSTEMS 13 of simultaneous timesharing users. Their model was the electricity system—when you need electric power, you just stick a plug in the wall, and within reason, as much power as you need will be there. The designers of this system, known as MULTICS (MULTiplexed Information and Comp... | OS_Page_13_Chunk13 |
14 INTRODUCTION CHAP. 1 and Saltzer, 1974). It also has an active Website, located at www.multicians.org, with much information about the system, its designers, and its users. Another major development during the third generation was the phenomenal growth of minicomputers, starting with the DEC PDP-1 in 1961. The PDP-1... | OS_Page_14_Chunk14 |
SEC. 1.2 HISTORY OF OPERATING SYSTEMS 15 1.2.4 The Fourth Generation (1980–Present): Personal Computers With the development of LSI (Large Scale Integration) circuits—chips con- taining thousands of transistors on a square centimeter of silicon—the age of the personal computer dawned. In terms of architecture, personal... | OS_Page_15_Chunk15 |
16 INTRODUCTION CHAP. 1 attempt to sell CP/M to end users one at a time (at least initially). After all this transpired, Kildall died suddenly and unexpectedly from causes that have not been fully disclosed. By the time the successor to the IBM PC, the IBM PC/AT, came out in 1983 with the Intel 80286 CPU, MS-DOS was fi... | OS_Page_16_Chunk16 |
SEC. 1.2 HISTORY OF OPERATING SYSTEMS 17 complete rewrite from scratch internally. It was a full 32-bit system. The lead de- signer for Windows NT was David Cutler, who was also one of the designers of the VAX VMS operating system, so some ideas from VMS are present in NT. In fact, so many ideas from VMS were present i... | OS_Page_17_Chunk17 |
18 INTRODUCTION CHAP. 1 x86-based computers, Linux is becoming a popular alternative to Windows for stu- dents and increasingly many corporate users. As an aside, throughout this book we will use the term x86 to refer to all mod- ern processors based on the family of instruction-set architectures that started with the ... | OS_Page_18_Chunk18 |
SEC. 1.2 HISTORY OF OPERATING SYSTEMS 19 differ in certain critical ways. Distributed systems, for example, often allow appli- cations to run on several processors at the same time, thus requiring more complex processor scheduling algorithms in order to optimize the amount of parallelism. Communication delays within th... | OS_Page_19_Chunk19 |
20 INTRODUCTION CHAP. 1 of the town (although not nearly as dominant as Symbian had been), but it did not take very long for Android, a Linux-based operating system released by Google in 2008, to overtake all its rivals. For phone manufacturers, Android had the advantage that it was open source and available under a pe... | OS_Page_20_Chunk20 |
SEC. 1.3 COMPUTER HARDWARE REVIEW 21 1.3.1 Processors The ‘‘brain’’ of the computer is the CPU. It fetches instructions from memory and executes them. The basic cycle of every CPU is to fetch the first instruction from memory, decode it to determine its type and operands, execute it, and then fetch, decode, and execute... | OS_Page_21_Chunk21 |
22 INTRODUCTION CHAP. 1 Pipelines cause compiler writers and operating system writers great headaches be- cause they expose the complexities of the underlying machine to them and they have to deal with them. Fetch unit Fetch unit Fetch unit Decode unit Decode unit Execute unit Execute unit Execute unit Execute unit Dec... | OS_Page_22_Chunk22 |
SEC. 1.3 COMPUTER HARDWARE REVIEW 23 of procedure call that has the additional property of switching from user mode to kernel mode. As a note on typography, we will use the lower-case Helvetica font to indicate system calls in running text, like this: read. It is worth noting that computers have traps other than the in... | OS_Page_23_Chunk23 |
24 INTRODUCTION CHAP. 1 time, it may inadvertently schedule two threads on the same CPU, with the other CPU completely idle. This choice is far less efficient than using one thread on each CPU. Beyond multithreading, many CPU chips now hav e four, eight, or more com- plete processors or cores on them. The multicore chi... | OS_Page_24_Chunk24 |
SEC. 1.3 COMPUTER HARDWARE REVIEW 25 Registers Cache Main memory Magnetic disk 1 nsec 2 nsec 10 nsec 10 msec <1 KB 4 MB 1-8 GB 1-4 TB Typical capacity Typical access time Figure 1-9. A typical memory hierarchy. The numbers are very rough approximations. typically 32 × 32 bits on a 32-bit CPU and 64 × 64 bits on a 64-bi... | OS_Page_25_Chunk25 |
26 INTRODUCTION CHAP. 1 Not every question is relevant to every caching situation. For caching lines of main memory in the CPU cache, a new item will generally be entered on every cache miss. The cache line to use is generally computed by using some of the high-order bits of the memory address referenced. For example, ... | OS_Page_26_Chunk26 |
SEC. 1.3 COMPUTER HARDWARE REVIEW 27 Flash memory is also commonly used as the storage medium in portable elec- tronic devices. It serves as film in digital cameras and as the disk in portable music players, to name just two uses. Flash memory is intermediate in speed between RAM and disk. Also, unlike disk memory, if ... | OS_Page_27_Chunk27 |
28 INTRODUCTION CHAP. 1 Information is written onto the disk in a series of concentric circles. At any giv en arm position, each of the heads can read an annular region called a track. Toget- her, all the tracks for a given arm position form a cylinder. Each track is divided into some number of sectors, typically 512 b... | OS_Page_28_Chunk28 |
SEC. 1.3 COMPUTER HARDWARE REVIEW 29 read sector 11,206 from disk 2. The controller then has to convert this linear sector number to a cylinder, sector, and head. This conversion may be complicated by the fact that outer cylinders have more sectors than inner ones and that some bad sec- tors have been remapped onto oth... | OS_Page_29_Chunk29 |
30 INTRODUCTION CHAP. 1 drivers while running and install them on the fly without the need to reboot. This way used to be rare but is becoming much more common now. Hot-pluggable devices, such as USB and IEEE 1394 devices (discussed below), always need dy- namically loaded drivers. Every controller has a small number o... | OS_Page_30_Chunk30 |
SEC. 1.3 COMPUTER HARDWARE REVIEW 31 puts the number of the device on the bus so the CPU can read it and know which device has just finished (many devices may be running at the same time). CPU Interrupt controller Disk controller Disk drive Current instruction Next instruction 1. Interrupt 3. Return 2. Dispatch to hand... | OS_Page_31_Chunk31 |
32 INTRODUCTION CHAP. 1 1.3.5 Buses The organization of Fig. 1-6 was used on minicomputers for years and also on the original IBM PC. However, as processors and memories got faster, the ability of a single bus (and certainly the IBM PC bus) to handle all the traffic was strained to the breaking point. Something had to ... | OS_Page_32_Chunk32 |
SEC. 1.3 COMPUTER HARDWARE REVIEW 33 a message through a single connection, known as a lane, much like a network packet. This is much simpler, because you do not have to ensure that all 32 bits arrive at the destination at exactly the same time. Parallelism is still used, because you can have multiple lanes in parallel... | OS_Page_33_Chunk33 |
34 INTRODUCTION CHAP. 1 I/O addresses 0x60 to 0x64, the floppy disk controller was interrupt 6 and used I/O addresses 0x3F0 to 0x3F7, and the printer was interrupt 7 and used I/O addresses 0x378 to 0x37A, and so on. So far, so good. The trouble came in when the user bought a sound card and a modem card and both happene... | OS_Page_34_Chunk34 |
SEC. 1.3 COMPUTER HARDWARE REVIEW 35 operating system loads them into the kernel. Then it initializes its tables, creates whatever background processes are needed, and starts up a login program or GUI. 1.4 THE OPERATING SYSTEM ZOO Operating systems have been around now for over half a century. During this time, quite a... | OS_Page_35_Chunk35 |
36 INTRODUCTION CHAP. 1 service. Internet providers run many server machines to support their customers and Websites use servers to store the Web pages and handle the incoming requests. Typical server operating systems are Solaris, FreeBSD, Linux and Windows Server 201x. 1.4.3 Multiprocessor Operating Systems An increa... | OS_Page_36_Chunk36 |
SEC. 1.4 THE OPERATING SYSTEM ZOO 37 1.4.6 Embedded Operating Systems Embedded systems run on the computers that control devices that are not gen- erally thought of as computers and which do not accept user-installed software. Typical examples are microwave ovens, TV sets, cars, DVD recorders, traditional phones, and M... | OS_Page_37_Chunk37 |
38 INTRODUCTION CHAP. 1 occur at a certain moment (or within a certain range), we have a hard real-time system. Many of these are found in industrial process control, avionics, military, and similar application areas. These systems must provide absolute guarantees that a certain action will occur by a certain time. A s... | OS_Page_38_Chunk38 |
SEC. 1.5 OPERATING SYSTEM CONCEPTS 39 an introduction. We will come back to each of them in great detail later in this book. To illustrate these concepts we will, from time to time, use examples, gener- ally drawn from UNIX. Similar examples typically exist in other systems as well, however, and we will study some of t... | OS_Page_39_Chunk39 |
40 INTRODUCTION CHAP. 1 typed a command requesting that a program be compiled. The shell must now cre- ate a new process that will run the compiler. When that process has finished the compilation, it executes a system call to terminate itself. If a process can create one or more other processes (referred to as child pr... | OS_Page_40_Chunk40 |
SEC. 1.5 OPERATING SYSTEM CONCEPTS 41 One UID, called the superuser (in UNIX), or Administrator (in Windows), has special power and may override many of the protection rules. In large in- stallations, only the system administrator knows the password needed to become superuser, but many of the ordinary users (especially... | OS_Page_41_Chunk41 |
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