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recalculate the new parity, as in the left in Figure 6.13. A “small write” would require reading the old data and old parity, adding the new information, and then writing the new parity to the parity disk and the new data to the data disk. The key insight to reduce this overhead is that parity is simply a sum of info... | Hennesey_Page_601_Chunk601 |
604 Chapter 6 Storage and Other I/O Topics Figure 6.14 shows how data is distributed in RAID 4 versus RAID 5. As the organization on the right shows, in RAID 5 the parity associated with each row of data blocks is no longer restricted to a single disk. This organization allows multiple writes to occur simultaneously a... | Hennesey_Page_602_Chunk602 |
replaced without having to turn off the system. RAIDs have enough redundancy to allow continuous operation, but hot-swapping disks place demands on the physical and electrical design of the array and the disk interfaces. Second, another failure could occur during repair, so the repair time affects the chances of losin... | Hennesey_Page_603_Chunk603 |
606 Chapter 6 Storage and Other I/O Topics Elaboration: One issue is how mirroring interacts with striping. Suppose you had, say, four disks’ worth of data to store and eight physical disks to use. Would you create four pairs of disks—each organized as RAID 1—and then stripe data across the four RAID 1 pairs? Alternati... | Hennesey_Page_604_Chunk604 |
FIGURE 6.15 A standard 19-inch rack populated with 42 1U servers. This rack has 42 1U “pizza box” servers. Source: http://gchelpdesk.ualberta.ca/news/07mar06/cbhd_news_07mar06.php. Hence, the smallest rack mount computer is 19 inches wide and 1.75 inches tall, often called 1U computers or 1U servers. Because of their ... | Hennesey_Page_605_Chunk605 |
608 Chapter 6 Storage and Other I/O Topics Figure 6.16 shows the Sun Fire x4150, an example of a 1U server. Maximally configured, this 1U box contains: ■ ■8 2.66 GHz processors, spread across two sockets (2 Intel Xeon 5345) ■ ■64 GB of DDR2-667 DRAM, spread across 16 4GB FBDIMMs ■ ■8 15,000 RPM 73 GB SAS 2.5-inch disk ... | Hennesey_Page_606_Chunk606 |
Figure 6.17 shows the connectivity and bandwidths of the chips on the mother board. Figures 6.9 and 6.10 describe the I/O chip set for the Intel 5345, and Figure 6.5 describes the SAS disks in the Sun Fire x4150. To clarify the advice on designing an I/O system in Section 6.8, let’s perform a simple performance evalu... | Hennesey_Page_607_Chunk607 |
610 Chapter 6 Storage and Other I/O Topics ■ ■The workload consists of 64 KB reads ■ ■Each processor sustains 1 billion instructions per second Find the maximum sustainable I/O rate for a fully loaded Sun Fire x4150 for random reads and sequential reads. Assume that the reads can always be done on an idle disk if one e... | Hennesey_Page_608_Chunk608 |
Once the data gets to the MCB, it needs to be written into the DRAM. The bandwidth of a DDR2 667 MHz FBDIMM is 5336 MB/second. A single DIMM can perform 5336 MB/sec 64 KB = 83,375 IOPS The memory is not a bottleneck even with one DIMM, and we have 16 in a fully configured Sun Fire x4150. The final link in the cha... | Hennesey_Page_609_Chunk609 |
612 Chapter 6 Storage and Other I/O Topics save the power (and cost) of 14 4GB DIMMs. A single socket can support 13,333 IOPS, so we can also reduce the number of Intel E5345 sockets by one. Using the numbers in Figure 6.18, the total system power is now: Idle Powerrandom reads = 154 + 2 ´ 10 + 8 ´ 8 + 15 = 253 watts P... | Hennesey_Page_610_Chunk610 |
read books on networking, Section 6.11 on the CD gives a quick overview of the topics and terminology, including Internetworking, the OSI model, protocol families such as TCP/IP, long-haul networks such as ATM, local area networks such as Ethernet, and wireless networks such as IEEE 802.11. 6.12 Fallacies and Pitfalls ... | Hennesey_Page_611_Chunk611 |
614 Chapter 6 Storage and Other I/O Topics A second study of more than 100,000 ATA disks, which had a quoted AFR of about 1.5%, saw failure rates of 1.7% for drives in their first year rise to 8.6% for drives in their third year, or about five to six times the specified rate [Pinheiro, Weber, and Barroso, 2007]. Fall... | Hennesey_Page_612_Chunk612 |
two nodes, but it doesn’t point to where the problem is. Intermediate checks can discover which component is broken. You need both for repair. Pitfall: Moving functions from the CPU to the I/O processor, expecting to improve performance without a careful analysis. There are many examples of this pitfall trapping people... | Hennesey_Page_613_Chunk613 |
616 Chapter 6 Storage and Other I/O Topics and so while desktops are by far the largest market for disks, desktops are a small market for tapes. Alas, the larger market has led disks to improve much more quickly than tapes. Starting in 2000 to 2002, the largest popular disk was larger than the largest popular tape. In... | Hennesey_Page_614_Chunk614 |
Depending on the relative location of the data on the disk, reordering could make it worse, as Figure 6.19 shows. The disk-scheduled reads complete in three-quarters of a disk revolution, but the OS-scheduled reads take three revolutions. Pitfall: Using the peak transfer rate of a portion of the I/O system to make perf... | Hennesey_Page_615_Chunk615 |
618 Chapter 6 Storage and Other I/O Topics widely varying schemes for interfacing I/O devices. In the low-end and midrange systems, buffered DMA is likely to be the dominant transfer mechanism. In the high-end systems, latency and bandwidth may both be important, and cost may be secondary. Multiple paths to I/O devices... | Hennesey_Page_616_Chunk616 |
6.15 Exercises Contributed by Perry Alexander of the University of Kansas Exercise 6.1 Figure 6.2 describes numerous I/O devices in terms of their behavior, partner, and data rate. However, these classifications often do not provide a complete picture of data flow within a system. Explore device classifications for the... | Hennesey_Page_617_Chunk617 |
620 Chapter 6 Storage and Other I/O Topics Exercise 6.3 Average and minimum times for reading and writing to storage devices are common measurements used to compare devices. Using techniques from Chap ter 6, calculate values related to read and write time for disks with the following characteristics. Average Seek Ti... | Hennesey_Page_618_Chunk618 |
Exercise 6.5 FLASH memory is one of the first true competitors for traditional disk drives. Explore the implications of FLASH memory by answering questions about the following applications. a. Aircraft Control System b. Phone Switch 6.5.1 [5] <6.2, 6.3, 6.4> As we move towards solid state drives constructed from FLASH... | Hennesey_Page_619_Chunk619 |
622 Chapter 6 Storage and Other I/O Topics Exercise 6.7 I/O can be performed either synchronously or asynchronously. Explore the differ ences by answering performance questions about the following peripherals. a. Printer b. Scanner 6.7.1 [5] <6.5> What would be the most appropriate bus type (synchronous or asynchronou... | Hennesey_Page_620_Chunk620 |
questions about communicating with I/O subsystems for the following applica tions using combinations of these techniques. a. Auto Pilot b. Automated Thermostat 6.9.1 [5] <6.6> Describe device polling. Would each application in the table be appropriate for communication using polling techniques? Explain. 6.9.2 [5] <6.... | Hennesey_Page_621_Chunk621 |
624 Chapter 6 Storage and Other I/O Topics 6.10.4 [5] <6.6> What happens if the interrupt enable bit of the Cause register is not set when handling an interrupt? What value could the interrupt mask value take to accomplish the same thing? 6.10.5 [5] <6.6> Most interrupt handling systems are implemented in the operat i... | Hennesey_Page_622_Chunk622 |
situations, data throughput dominates in others. Explore I/O performance evalua tion by answering the questions for the following applications. a. Mathematical Computations b. Online Chat 6.12.1 [10] <6.7> For each application in the table, does I/O performance domi nate system performance? 6.12.2 [10] <6.7> For each... | Hennesey_Page_623_Chunk623 |
626 Chapter 6 Storage and Other I/O Topics things about RAID arrays that we will explore in the context of the following activities. a. High-Performance Mathematical Computations b. Online Video Services 6.14.1 [10] <6.9> RAID 0 uses striping to force parallel access among many disks. Why does striping improve disk pe... | Hennesey_Page_624_Chunk624 |
6.15.5 [5] <6.9> RAID 4 and RAID 5 speed improvements grow with respect to RAID 3 as the size of the protected block grows. Why is this the case? Is there a situ ation where RAID 4 and RAID 5 would be no more efficient than RAID 3? Exercise 6.16 The emergence of web servers for ecommerce, online storage, and communica... | Hennesey_Page_625_Chunk625 |
628 Chapter 6 Storage and Other I/O Topics 6.17.2 [15] <6.8, 6.10> For the application listed above, find a server available in the marketplace that you feel would be appropriate for running the application. Before evaluating the server, identify reasons why it was selected. 6.17.3 [20] <6.8, 6.10> Using metrics simila... | Hennesey_Page_626_Chunk626 |
6.19.2 [5] <6.9, 6.12> Given that your company operates a global search engine with a large disk farm, does upgrading to either RAID 0 or RAID 1 make economic sense given that your income model is based on the number of advertisements served? 6.19.3 [5] <6.9, 6.12> Repeat 6.19.2 for a large disk farm operated by an onl... | Hennesey_Page_627_Chunk627 |
7 There are finer fish in the sea than have ever been caught. Irish proverb Multicores, Multiprocessors, and Clusters 7.1 Introduction 632 7.2 The Difficulty of Creating Parallel Processing Programs 634 7.3 Shared Memory Multiprocessors 638 7.4 Clusters and Other Message-Passing Multiprocessors 641 7.5 Hardware Multi... | Hennesey_Page_628_Chunk628 |
7.6 SISD, MIMD, SIMD, SPMD, and Vector 648 7.7 Introduction to Graphics Processing Units 654 7.8 Introduction to Multiprocessor Network Topologies 660 7.9 Multiprocessor Benchmarks 664 7.10 Roofline: A Simple Performance Model 667 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 675 7.12 Fallacies... | Hennesey_Page_629_Chunk629 |
632 Chapter 7 Multicores, Multiprocessors, and Clusters 7.1 Introduction Computer architects have long sought the El Dorado of computer design: to create powerful computers simply by connecting many existing smaller ones. This golden vision is the fountainhead of multiprocessors. Ideally, customers order as many proce... | Hennesey_Page_630_Chunk630 |
7.1 Introduction 633 The tall challenge facing the industry is to create hardware and software that will make it easy to write correct parallel processing programs that will execute efficiently in performance and power as the number of cores per chip scales geometrically. This sudden shift in microprocessor design has... | Hennesey_Page_631_Chunk631 |
634 Chapter 7 Multicores, Multiprocessors, and Clusters describes multithreading, a term often confused with multiprocessing, in part because it relies upon similar concurrency in programs. Section 7.6 describes an older classification scheme than in Figure 7.1. In addition, it describes two styles of instruction set a... | Hennesey_Page_632_Chunk632 |
Why is it difficult to write parallel processing programs that are fast, especially as the number of processors increases? In Chapter 1, we used the analogy of eight reporters trying to write a single story in hopes of doing the work eight times faster. To succeed, the task must be broken into eight equal-sized pieces,... | Hennesey_Page_633_Chunk633 |
636 Chapter 7 Multicores, Multiprocessors, and Clusters Substituting for the goal of a speed-up of 90 into the formula above: 90 = 1 _____________________________________ (1 − Fraction time affected) + Fraction time affected 100 Then simplifying the formula and solving for fraction time affected: 90 × (1 – 0... | Hennesey_Page_634_Chunk634 |
Thus, for this problem size, we get about 55% of the potential speed-up with 10 processors, but only 10% with 100. Look what happens when we increase the matrix. The sequential program now takes 10t + 10,000t = 10,010t. The execution time for 10 processors is Execution time after improvement = 10,000t _______ 10 + ... | Hennesey_Page_635_Chunk635 |
638 Chapter 7 Multicores, Multiprocessors, and Clusters If one processor has 2% of the parallel load, then it must do 2% × 10,000 or 200 additions, and the other 99 will share the remaining 9800. Since they are operating simultaneously, we can just calculate the execution time as a maximum Execution time after improve... | Hennesey_Page_636_Chunk636 |
much faster than others, depending on which processor asks for which word. Such machines are called nonuniform memory access (NUMA) multiprocessors. As you might expect, the programming challenges are harder for a NUMA multiprocessor than for a UMA multiprocessor, but NUMA machines can scale to larger sizes and NUM... | Hennesey_Page_637_Chunk637 |
640 Chapter 7 Multicores, Multiprocessors, and Clusters sum[Pn] = 0; for (i = 1000*Pn; i < 1000*(Pn+1); i = i + 1) sum[Pn] = sum[Pn] + A[i]; /* sum the assigned areas*/ The next step is to add these many partial sums. This step is called a reduction. We divide to conquer. Half of the processors add pairs of partial sum... | Hennesey_Page_638_Chunk638 |
7.4 Clusters and Other Message-Passing Multiprocessors The alternative approach to sharing an address space is for the processors to each have their own private physical address space. Figure 7.4 shows the classic organi zation of a multiprocessor with multiple private address spaces. This alternative multiprocessor ... | Hennesey_Page_639_Chunk639 |
642 Chapter 7 Multicores, Multiprocessors, and Clusters One drawback of clusters has been that the cost of administering a cluster of n machines is about the same as the cost of administering n independent machines, while the cost of administering a shared memory multiprocessor with n processors is about the same as a... | Hennesey_Page_640_Chunk640 |
Since this computer has multiple address spaces, the first step is distributing the 100 subsets to each of the local memories. The processor containing the 100,000 numbers sends the subsets to each of the 100 processor-memory nodes. The next step is to get the sum of each subset. This step is simply a loop that every ... | Hennesey_Page_641_Chunk641 |
644 Chapter 7 Multicores, Multiprocessors, and Clusters Elaboration: This example assumes implicitly that message passing is about as fast as addition. In reality, message sending and receiving is much slower. An optimization to better balance computation and communication might be to have fewer nodes receive many su... | Hennesey_Page_642_Chunk642 |
if someone developed software that could run on those computers and then gave each PC an independent piece of the problem to work on. The first example was the Search for ExtraTerrestrial Intelligence (SETI). Over 5 million computer users in more than 200 countries have signed up for SETI@home and have collectively con... | Hennesey_Page_643_Chunk643 |
646 Chapter 7 Multicores, Multiprocessors, and Clusters throughput losses, especially from shorter stalls. This limitation arises from the pipeline start-up costs of coarse-grained multithreading. Because a processor with coarse-grained multithreading issues instructions from a single thread, when a stall occurs, the p... | Hennesey_Page_644_Chunk644 |
In the SMT case, thread-level parallelism and instruction-level parallelism are both exploited, with multiple threads using the issue slots in a single clock cycle. Ideally, the issue slot usage is limited by imbalances in the resource needs and resource availability over multiple threads. In practice, other factors ca... | Hennesey_Page_645_Chunk645 |
648 Chapter 7 Multicores, Multiprocessors, and Clusters Second, a key performance challenge is tolerating latency due to cache misses. Fine-grained computers like the UltraSPARC T2 switch to another thread on a miss, which is probably more effective in hiding memory latency than trying to fill unused issue slots as in ... | Hennesey_Page_646_Chunk646 |
While it is hard to provide examples of useful computers that would be classified as multiple instruction streams and single data stream (MISD), the inverse makes much more sense. SIMD computers operate on vectors of data. For example, a single SIMD instruction might add 64 numbers by sending 64 data streams to 64 AL... | Hennesey_Page_647_Chunk647 |
650 Chapter 7 Multicores, Multiprocessors, and Clusters This very low cost parallelism for narrow integer data was the original inspiration of the MMX instructions of the x86. As Moore’s law continued, more hardware was added to these multimedia extensions, and now SSE2 supports the simultaneous execution of a pair o... | Hennesey_Page_648_Chunk648 |
Here is the conventional MIPS code for DAXPY: l.d $f0,a($sp) ;load scalar a addiu r4,$s0,#512 ;upper bound of what to load loop: l.d $f2,0($s0) ;load x(i) mul.d $f2,$f2,$f0 ;a × x(i) l.d $f4,0($s1) ;load y(i) add.d $f4,$f4,$f2 ;a × x(i) + y(i) s.d $f4,0($s1) ;store into y(i) addiu $s0,$s0,#8 ;increment index to x addiu... | Hennesey_Page_649_Chunk649 |
652 Chapter 7 Multicores, Multiprocessors, and Clusters Elaboration: The loop in the example above exactly matched the vector length. When loops are shorter, vector architectures use a register that reduces the length of vector operations. When loops are larger, we add bookkeeping code to iterate full-length vector ope... | Hennesey_Page_650_Chunk650 |
Vector versus Multimedia Extensions Like multimedia extensions found in the x86 SSE instructions, a vector instruction specifies multiple operations. However, multimedia extensions typically specify a few operations while vector specifies dozens of operations. Unlike multimedia extensions, the number of elements in a... | Hennesey_Page_651_Chunk651 |
654 Chapter 7 Multicores, Multiprocessors, and Clusters 7.7 Introduction to Graphics Processing Units A major justification for adding SIMD instructions to existing architectures was that many microprocessors were connected to graphics displays in PCs and work stations, so an increasing fraction of processing time was... | Hennesey_Page_652_Chunk652 |
The language compilers target industry-standard intermediate languages instead of machine instructions. GPU driver software generates optimized GPU-specific machine instructions. While these APIs and languages evolve rapidly to embrace new GPU resources enabled by Moore’s law, the freedom from backward binary instru... | Hennesey_Page_653_Chunk653 |
656 Chapter 7 Multicores, Multiprocessors, and Clusters 2 to 32 GB. Finally, keep in mind that for general-purpose computation, you must include the time to transfer the data between CPU memory and GPU memory, since the GPU is a coprocessor. ■ ■Given the reliance on many threads to deliver good memory bandwidth, GPUs ... | Hennesey_Page_654_Chunk654 |
see the similarities to approaches presented in prior sections, such as fine-grained multithreading and vectors. To help you with that transition to the new vocabulary, we present a quick introduction to the terms and ideas in the Tesla GPU architecture and the CUDA programming environment. A discrete GPU chip sits on ... | Hennesey_Page_655_Chunk655 |
658 Chapter 7 Multicores, Multiprocessors, and Clusters Figure 7.7 combines all these features together and compares a Tesla multiprocessor to a Sun UltraSPARC T2 core, which is described in Sections 7.5 and 7.11. Both are hardware multithreaded by scheduling threads over time, shown on the vertical axis. Each Tesla mu... | Hennesey_Page_656_Chunk656 |
switching every two or four clock cycles versus every clock cycle, and the hardware was much simpler by restricting the frequency of switching. The CUDA programming environment has its own terminology as well. A CUDA program is a unified C/C++ program for a heterogeneous CPU and GPU system. It executes on the CPU and d... | Hennesey_Page_657_Chunk657 |
660 Chapter 7 Multicores, Multiprocessors, and Clusters In contrast to vector architectures, which rely on a vectorizing compiler to recognize data-level parallelism at compile time and generate vector instructions, hardware implementations of Tesla architecture discovers data-level parallelism among threads at runtime... | Hennesey_Page_658_Chunk658 |
black square, and the switch is shown as a colored circle. In this section, all links are bidirectional; that is, information can flow in either direction. All networks consist of switches whose links go to processor-memory nodes and to other switches. The first improvement over a bus is a network that connects a sequ... | Hennesey_Page_659_Chunk659 |
662 Chapter 7 Multicores, Multiprocessors, and Clusters frequently add extra links to these simple topologies to improve performance and reliability. An alternative to placing a processor at every node in a network is to leave only the switch at some of these nodes. The switches are smaller than processor- memory-swi... | Hennesey_Page_660_Chunk660 |
it easier to assign more wires to the link, as the power to drive many wires from a chip is less if the wires are short. Shorter wires are also cheaper than longer wires. Another practical limitation is that the three-dimensional drawings must be mapped onto chips that are essentially two-dimensional media. The final c... | Hennesey_Page_661_Chunk661 |
664 Chapter 7 Multicores, Multiprocessors, and Clusters 7.9 Multiprocessor Benchmarks As we saw in Chapter 1, benchmarking systems is always a sensitive topic, because it is a highly visible way to try to determine which system is better. The results affect not only the sales of commercial systems, but also the reputat... | Hennesey_Page_662_Chunk662 |
Benchmark Scaling? Reprogram? Description Linpack Weak Yes Dense matrix linear algebra [Dongarra, 1979] SPECrate Weak No Independent job parallelism [Henning, 2007] Stanford Parallel Applications for Shared Memory SPLASH 2 [Woo et al., 1995] Strong (although offers two problem sizes) No Complex 1D FFT Blocked LU Decomp... | Hennesey_Page_663_Chunk663 |
666 Chapter 7 Multicores, Multiprocessors, and Clusters a parallel benchmark suite similar in goals to the SPEC CPU benchmark suite. It includes both kernels and applications, including many from the high-performance computing community. This benchmark requires strong scaling, although it comes with two data sets. ■ ■T... | Hennesey_Page_664_Chunk664 |
7.10 Roofline: A Simple Performance Model This section is based on a paper by Williams and Patterson [2008]. In the recent past, conventional wisdom in computer architecture led to similar microproces sor designs. Nearly every desktop and server computer used caches, pipelining, superscalar instruction issue, branch p... | Hennesey_Page_665_Chunk665 |
668 Chapter 7 Multicores, Multiprocessors, and Clusters The ratio of floating-point operations per byte of memory accessed is called the arithmetic intensity. It can be calculated by taking the total number of floating- point operations for a program divided by the total number of data bytes transferred to main memory ... | Hennesey_Page_666_Chunk666 |
actual floating-point performance can be no higher than the horizontal line, since that is a hardware limit. How could we plot the peak memory performance? Since X-axis is FLOPs/ byte and the Y-axis is FLOPs/second, bytes/second is just a diagonal line at a 45-degree angle in this figure. Hence, we can plot a third lin... | Hennesey_Page_667_Chunk667 |
670 Chapter 7 Multicores, Multiprocessors, and Clusters Note that the “ridge point,” where the diagonal and horizontal roofs meet, offers an interesting insight into the computer. If it is far to the right, then only kernels with very high arithmetic intensity can achieve the maximum performance of that computer. If i... | Hennesey_Page_668_Chunk668 |
The roofline model gives an upper bound to performance. Suppose your program is far below that bound. What optimizations should you perform, and in what order? To reduce computational bottlenecks, the following two optimizations can help almost any kernel: 1. Floating-point operation mix. Peak floating-point performanc... | Hennesey_Page_669_Chunk669 |
672 Chapter 7 Multicores, Multiprocessors, and Clusters FIGURE 7.15 Roofline model with ceilings. The top graph shows the computational “ceilings” of 8 GFLOPs/sec if the floating-point operation mix is imbalanced and 2 GFLOPs/sec if the optimizations to increase ILP and SIMD are also missing. The bottom graph shows the... | Hennesey_Page_670_Chunk670 |
The computational roofline can be found from the manuals, and the memory roofline can be found from running the stream benchmark. The computational ceilings, such as floating-point balance, also come from the manuals for that com puter. The memory ceiling requires running experiments on each computer to determine the ... | Hennesey_Page_671_Chunk671 |
674 Chapter 7 Multicores, Multiprocessors, and Clusters The next section uses the roofline model to demonstrate the difference for four recent multicore microprocessors for two real application kernels. While the examples above show how to help programmers improve performance, the model can also be used by architects t... | Hennesey_Page_672_Chunk672 |
Elaboration: An alternative to the Stream benchmark is to use the raw DRAM bandwidth as the roofline. While the DRAMs definitely set a hard bound, actual memory performance is often so far from that boundary that it’s not that useful as an upper bound. That is, no program can go close to that bound. The downside to usi... | Hennesey_Page_673_Chunk673 |
676 Chapter 7 Multicores, Multiprocessors, and Clusters Four Multicore Systems Figure 7.17 shows the basic organization of the four systems, and Figure 7.18 lists the key characteristics of the examples of this section. These are all dual socket systems. Figure 7.19 shows the roofline performance model for each system.... | Hennesey_Page_674_Chunk674 |
The Intel Xeon e5345 (code-named “Clovertown”) contains four cores per socket by packaging two dual core chips into a single socket. These two chips share a front side bus that is attached to a separate north bridge chip set (see Chapter 6). This north bridge chip set supports two front side buses and hence two sockets... | Hennesey_Page_675_Chunk675 |
678 Chapter 7 Multicores, Multiprocessors, and Clusters FIGURE 7.19 Roofline model for multicore multiprocessors in Figure 7.15. The ceilings are the same as in Figure 7.13. Starting from the upper left hand corner, the computers are: (a) Intel Xeon e5345 (Clovertown), (b) AMD Opteron X4 2356 (Barcelona), (c) Sun Ultra... | Hennesey_Page_676_Chunk676 |
The IBM Cell QS20 is again different from the two x86 microarchitectures and from UltraSPARC T2. It is a heterogeneous design, with a relatively simple PowerPC core and with eight SPEs (Synergistic Processing Elements) that have their own unique SIMD-style instruction set. Each SPE also has its own local memory instead... | Hennesey_Page_677_Chunk677 |
680 Chapter 7 Multicores, Multiprocessors, and Clusters y = A × x where A is a sparse matrix and x and y are dense vectors. Fourteen sparse matrices taken from a variety of real applications were used to evaluate SpMV performance, but only the median performance is reported here. The arithmetic intensity varies from ... | Hennesey_Page_678_Chunk678 |
Each point involves reading and writing about 75 double precision floating- point numbers and about 1300 floating-point operations. Like SpMV, LBMHD tends to get a small fraction of peak performance on uniprocessors because of the complexity of the data structures and the irregularity of memory access patterns. The FLO... | Hennesey_Page_679_Chunk679 |
682 Chapter 7 Multicores, Multiprocessors, and Clusters ■ ■Loop Unrolling and Reordering: To expose sufficient parallelism and improve cache utilization, the loops were unrolled and then reordered to group state ments with similar addresses. ■ ■“SIMD-ize”: The compilers of the two x86 systems could not generate good S... | Hennesey_Page_680_Chunk680 |
FIGURE 7.22 Base versus fully optimized performance of the four cores on the two kernels. Note the high fraction of fully optimized performance delivered by the Sun UltraSPARC T2 (Niagara 2). There is no base performance column for the IBM Cell because there is no way to port the code to the SPEs without caches. While... | Hennesey_Page_681_Chunk681 |
684 Chapter 7 Multicores, Multiprocessors, and Clusters running on the SPE. Hence, there is no base code column for the IBM Cell in Figure 7.22, and you needed to change the program to issue DMA commands to transfer data back and forth between local store and memory. The good news is that DMA played the role of softwar... | Hennesey_Page_682_Chunk682 |
The supercomputer industry used this metric in marketing, and the fallacy is exacerbated with parallel machines. Not only are marketers using the nearly unattainable peak performance of a uniprocessor node, but also they are then multiplying it by the total number of processors, assuming perfect speed-up! Amdahl’s la... | Hennesey_Page_683_Chunk683 |
686 Chapter 7 Multicores, Multiprocessors, and Clusters 7.13 Concluding Remarks The dream of building computers by simply aggregating processors has been around since the earliest days of computing. Progress in building and using effec tive and efficient parallel processors, however, has been slow. This rate of progre... | Hennesey_Page_684_Chunk684 |
path to higher performance for sequential applications. Hence, programmers who need higher performance must parallelize their codes or write new parallel processing programs. ■ ■Multiple processors on the same chip allow a very different speed of commu nication than multiple chip designs, offering both much lower l... | Hennesey_Page_685_Chunk685 |
688 Chapter 7 Multicores, Multiprocessors, and Clusters 7.14 Historical Perspective and Further Reading This section on the CD gives the rich and often disastrous history of multiproces sors over the last 50 years. 7.15 Exercises Contributed by David Kaeli of Northeastern University Exercise 7.1 First, write down a ... | Hennesey_Page_686_Chunk686 |
7.2.1 [10] <7.2> Consider the following binary search algorithm (a classic divide and conquer algorithm) that searches for a value X in an sorted N-element array A and returns the index of matched entry: BinarySearch(A[0..N-1], X) { low = 0 high = N - 1 while (low <= high) { mid = (low + high) / 2 if (A[mid] > X) high ... | Hennesey_Page_687_Chunk687 |
690 Chapter 7 Multicores, Multiprocessors, and Clusters Instructions have the following associated latencies (in cycles): ADD.D L.D S.D DADDIU 4 6 1 2 7.3.1 [10] <7.2> How many cycles does it take for all instructions in a single iteration of the above loop to execute? 7.3.2 [10] <7.2> When an instruction in a later it... | Hennesey_Page_688_Chunk688 |
else var middle = length(m) / 2 for each x in m up to middle add x to left for each x in m after middle add x to right left = Mergesort(left) right = Mergesort(right) result = Merge(left, right) return result The merge step is carried out by the following code: Merge(left,right) var list result while length(left) > 0 a... | Hennesey_Page_689_Chunk689 |
692 Chapter 7 Multicores, Multiprocessors, and Clusters 4 large eggs 1 teaspoon vanilla extract 1/2 teaspoon salt 1/4 teaspoon nutmeg 1 1/2 cups flour 1 cup blueberries The recipe for a single cake is as follows: Step 1: Preheat oven to 325°F (160°C). Grease and flour your cake pan. Step 2: In large bowl, beat togethe... | Hennesey_Page_690_Chunk690 |
for each element i and j with 1 ≤ i ≤ m and 1 ≤ j ≤ p. Now we want to see if we can parallelize the computation of C. Assume that matrices are laid out in memory sequentially as follows: a1,1, a2,1, a3,1, a4,1, …, etc.. 7.6.1 [10] <7.3> Assume that we are going to compute C on both a single core shared memory machine a... | Hennesey_Page_691_Chunk691 |
694 Chapter 7 Multicores, Multiprocessors, and Clusters In the following proplems, assume that all nodes have the same number of CPUs and the same amount memory (i.e., CPUs and memory are evenly divided between the nodes of the CC-NUMA machine). 7.8.1 [15] <7.3> If we have P CPU in the system, with T nodes in the CC- N... | Hennesey_Page_692_Chunk692 |
Exercise 7.10 On a CC-NUMA system, the cost of accessing non-local memory can limit our ability to utilize multiprocessing effectively. The following table shows the costs associated with access data in local memory versus non-local memory and the locality of our application expresses as the proportion of access that a... | Hennesey_Page_693_Chunk693 |
696 Chapter 7 Multicores, Multiprocessors, and Clusters knowledge of all forks. Further, if we impose the policy that philosophers will always request to pick up their left fork before requesting to pick up their right fork, then we can guarantee to avoid deadlock. 7.11.3 [10] <7.4> �We can implement requests to the wa... | Hennesey_Page_694_Chunk694 |
7.12.2 [10] <7.5> Now assume you have 2 SS CPUs. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards? 7.12.3 [10] <7.5> Assume that you have 1 MT CPU. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards? Exercise... | Hennesey_Page_695_Chunk695 |
698 Chapter 7 Multicores, Multiprocessors, and Clusters 7.14.2 [20] <7.6> For an 8-wide SIMD machine (i.e., 8 parallel SIMD functional units), write an assembly program in using your own SIMD extensions to MIPS to execute the loop. Compare the number of instructions executed on the SIMD machine to the MIMD machine. Exe... | Hennesey_Page_696_Chunk696 |
7.17.1 [90] <7.7> Using the “template” SDK sample as a starting point, write a CUDA program to perform the following vector operations: 1) a − b (vector-vector subtraction) 2) a · b (vector dot product) The dot product of two vectors a = [a1, a2, … , an] and b = [b1, b2, … , bn] is defined as: a · b = i = 1 n ai... | Hennesey_Page_697_Chunk697 |
700 Chapter 7 Multicores, Multiprocessors, and Clusters 7.19.2 [10] <7.8> Compare the resiliency to failure of n-cube to a fully-connected interconnection network. Plot a comparison of reliability as a function of the added number of links for the two topologies. Exercise 7.20 Benchmarking is field of study that invol... | Hennesey_Page_698_Chunk698 |
7.21.2 [10] <7.9> In terms of storage space, assuming that each element in matrix X is single precision floating point, compute the amount of storage used to store the Matrix above in Yale Sparse Matrix Format. 7.21.3 [15] <7.9> Perform matrix multiplication of Matrix X by Matrix Y shown below. [2, 4, 1, 99, 7, 2] Put ... | Hennesey_Page_699_Chunk699 |
702 Chapter 7 Multicores, Multiprocessors, and Clusters All three CPUs have the ability to perform integer arithmetic, though CPU B can not perform floating point arithmetic. CPU A and B have an instruction set similar to a MIPS processor. CPU C can only perform floating point add and subtract operations, as well as m... | Hennesey_Page_700_Chunk700 |
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