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­recalculate the new parity, as in the left in Figure 6.13. A “small write” would require reading the old data and old parity, adding the new information, and then writing the new parity to the parity disk and the new data to the data disk. The key insight to ­reduce this overhead is that parity is simply a sum of infor­ mation; by watching which bits change when we write the new information, we need only change the corresponding bits on the parity disk. The right of Figure 6.13 shows the shortcut. We must read the old data from the disk being written, compare old data to the new data to see which bits change, read the old parity, change the corresponding bits, then write the new data and new parity. Thus, the small write ­involves four disk accesses to two disks instead of accessing all disks. This organization is RAID 4. Distributed Block-Interleaved Parity (RAID 5) RAID 4 efficiently supports a mixture of large reads, large writes, and small reads, plus it allows small writes. One drawback to the system is that the parity disk must be updated on every write, so the parity disk is the bottleneck for back-to-back writes. To fix the parity-write bottleneck, the parity information can be spread through­ out all the disks so that there is no single bottleneck for writes. The dis­tributed parity organization is RAID 5. FIGURE 6.13 Small write update on RAID 4. This optimization for small writes reduces the number of disk accesses as well as the number of disks occupied. This figure assumes we have four blocks of data and one block of parity. The naive RAID 4 parity calculation in the left of the figure reads blocks D1, D2, and D3 before adding block D0¢ to calculate the new parity P¢. (In case you were wondering, the new data D0¢ comes directly from the CPU, so disks are not involved in reading it.) The RAID 4 shortcut on the right reads the old value D0 and compares it to the new value D0¢ to see which bits will change. You then read the old parity P and then change the corresponding bits to form P¢. The logical function exclusive OR does exactly what we want. This example replaces three disk reads (D1, D2, D3) and two disk writes (D0¢, P¢) involving all the disks for two disk reads (D0, P) and two disk writes (D0¢, P¢), which involve just two disks. Increasing the size of the parity group increases the savings of the shortcut. RAID 5 uses the same shortcut. D0′ D0 D1 D2 D3 P D0′ D1 D2 D3 P′ New Data 1. Read 2. Read 3. Read 4. Write 5. Write XOR D0′ D0 D1 D2 D3 P D0′ D1 D2 D3 P′ + New Data1. Read 2. Read 3. Write 4. Write XOR + XOR + 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 603
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604 Chapter 6 Storage and Other I/O Topics Figure 6.14 shows how data is distributed in RAID 4 versus RAID 5. As the organization on the right shows, in RAID 5 the parity associated with each row of data blocks is no longer restricted to a single disk. This organization allows multi­ple writes to occur simultaneously as long as the parity blocks are not located on the same disk. For example, a write to block 8 on the right must also access its parity block P2, thereby occupying the first and third disks. A second write to block 5 on the right, implying an update to its parity block P1, accesses the second and fourth disks and thus could occur concurrently with the write to block 8. Those same writes to the organization on the left result in changes to blocks P1 and P2, both on the fifth disk, which is a bottleneck. P + Q Redundancy (RAID 6) Parity-based schemes protect against a single self-identifying failure. When a single failure correction is not sufficient, parity can be generalized to have a second calcu­ lation over the data and another check disk of information. This second check block allows recovery from a second failure. Thus, the storage overhead is twice that of RAID 5. The small write shortcut of Figure 6.13 works as well, except now there are six disk accesses instead of four to update both P and Q information. RAID Summary RAID 1 and RAID 5 are widely used in servers; one estimate is that 80% of disks in servers are found in a RAID organization. One weakness of the RAID systems is repair. First, to avoid making the data unavailable during repair, the array must be designed to allow the failed disks to be FIGURE 6.14 Block-interleaved parity (RAID 4) versus distributed block-interleaved par­ity (RAID 5). By distributing parity blocks to all disks, some small writes can be performed in parallel. 0 4 8 12 16 20 . . . 1 5 9 13 17 21 . . . 2 6 10 14 18 22 . . . 3 7 11 15 19 23 . . . P0 P1 P2 P3 P4 P5 . . . 0 4 8 12 P4 20 . . . 1 5 9 P3 16 21 . . . 2 6 P2 13 17 22 . . . 3 P1 10 14 18 23 . . . P0 7 11 15 19 P5 . . . RAID 4 RAID 5
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replaced without having to turn off the system. RAIDs have enough redun­dancy to allow continuous operation, but hot-swapping disks place demands on the physical and electrical design of the array and the disk interfaces. Second, another failure could occur during repair, so the repair time affects the chances of losing data: the longer the repair time, the greater the chances of another failure that will lose data. Rather than having to wait for the operator to bring in a good disk, some systems include standby spares so that the data can be reconstructed immediately upon discovery of the failure. The operator can then replace the failed disks in a more leisurely fashion. Note that a human operator ultimately determines which disks to remove. As Figure 6.3 shows, operators are only human, so they occasionally remove the good disk instead of the broken disk, leading to an unrecoverable disk failure. In addition to designing the RAID system for repair, there are questions about how disk technology changes over time. Although disk manufacturers quote very high MTTF for their products, those numbers are under nominal conditions. If a particular disk array has been subject to temperature cycles due to, say, the failure of the air conditioning system, or to shaking due to a poor rack design, construc­ tion, or installation, the failure rates can be three to six times higher (see the fal­lacy on page 613). The calculation of RAID reliability assumes independence between disk failures, but disk failures could be correlated, because such damage due to the environment would likely happen to all the disks in the array. Another concern is that since disk bandwidth is growing more slowly than disk capacity, the time to repair a disk in a RAID system is increasing, which in turn increases the chances of a second failure. For example, a 1000 GB SATA disk could take almost three hours to read sequentially, assuming no interference. Given that the damaged RAID is likely to continue to serve data, reconstruction could be stretched considerably. Besides increasing that time, another concern is that read­ing much more data during reconstruction means increasing the chance of an uncorrectable read media failure, which would result in data loss. Other argu­ments for concern about simultaneous multiple failures are the increasing num­ber of disks in arrays and the use of SATA disks, which are slower and have higher capacity than traditional enterprise disks. Hence, these trends have led to a growing interest in protecting against more than one failure, and so RAID 6 is increasingly being offered as an option and being used in the field. Which of the following are true about RAID levels 1, 3, 4, 5, and 6? 1. RAID systems rely on redundancy to achieve high availability. 2. RAID 1 (mirroring) has the highest check disk overhead. 3. For small writes, RAID 3 (bit-interleaved parity) has the worst throughput. 4. For large writes, RAID 3, 4, and 5 have the same throughput. hot-swapping Replacing a hardware component while the system is running. standby spares Reserve hard­ware resources that can immedi­ately take the place of a failed component. Check Yourself 6.9 Parallelism and I/O: Redundant Arrays of Inexpensive Disks 605
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606 Chapter 6 Storage and Other I/O Topics Elaboration: One issue is how mirroring interacts with striping. Suppose you had, say, four disks’ worth of data to store and eight physical disks to use. Would you create four pairs of disks—each organized as RAID 1—and then stripe data across the four RAID 1 pairs? Alternatively, would you create two sets of four disks—each organized as RAID 0—and then mirror writes to both RAID 0 sets? The RAID terminology has evolved to call the former RAID 1 + 0 or RAID 10 (“striped mirrors”) and the latter RAID 0 + 1 or RAID 01 (“mirrored stripes”). 6.10 Real Stuff: Sun Fire x4150 Server In addition to the revolution in how microprocessors are constructed, we are see­ ing a revolution in how software is delivered. Instead of the traditional model of software sold on a CD or shipped over the Internet to be installed in your com­ puter, the alternative is software as a service. That is, you go over the Internet to do your work on a computer that runs the software you want to use to provide the service that you desire. The most popular example is likely Web searching, but there are services for photo editing and storage, document processing, database storage, virtual worlds, and so on. If you looked hard, you can probably find service ver­sion of almost every program you use on your desktop computer. This shift has led to the construction of large data centers to hold the comput­ ers and disks to run the services used by millions of external users. What should computers look like if they are designed to be placed in these large data centers? They certainly all don’t need displays and keyboards. Clearly, space efficiency and power efficiency will be important if you have 10,000 of them in a datacenter, in addition to the traditional concerns of cost and performance. The related question is what should storage look like in a datacenter? While there are many options, one popular version is to include disks with the processor and memory, and make this whole unit the building block. To overcome concerns about reliability, the application itself makes redundant copies and is responsible for keeping them consistent and recovering from failures. The IT industry has largely agreed to some standards in the physical design of computers for the datacenter, specifically the rack used to hold the computers in the datacenter. The most popular is the 19-inch rack, which is 19 inches wide (482.6 mm). Computers designed for the rack are labeled, naturally enough, rack mount, but are also called a subrack or simply a shelf. Because the traditional placement of holes in which to attach the shelves is 1.75 inches (44.45 mm) apart, this distance is commonly called a rack unit or simply unit (U). The most popular 19-inch rack is 42 U high, which is 42 x 1.75 or 73.5 inches high. The depth of the shelf varies.
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FIGURE 6.15 A standard 19-inch rack populated with 42 1U servers. This rack has 42 1U “pizza box” servers. Source: http://gchelpdesk.ual­berta.ca/news/07mar06/cbhd_news_07mar06.php. Hence, the smallest rack mount computer is 19 inches wide and 1.75 inches tall, often called 1U computers or 1U servers. Because of their dimensions, they have earned the nickname pizza boxes. Figure 6.15 shows an example of a standard rack populated with 42 1U servers. 6.10 Real Stuff: Sun Fire x4150 Server 607
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608 Chapter 6 Storage and Other I/O Topics Figure 6.16 shows the Sun Fire x4150, an example of a 1U server. Maximally configured, this 1U box contains: ■ ■8 2.66 GHz processors, spread across two sockets (2 Intel Xeon 5345) ■ ■64 GB of DDR2-667 DRAM, spread across 16 4GB FBDIMMs ■ ■8 15,000 RPM 73 GB SAS 2.5-inch disk drives ■ ■1 RAID controller (Supporting RAID 0, RAID 1, RAID 5, and RAID 6) ■ ■4 10/100/1000 Ethernet ports ■ ■3 PCI Express x8 ports ■ ■4 external and 1 internal USB 2.0 ports 3 PCI Express Slots System Status LEDs Video 4 Gigabit NICs 2 USB Ports Management Serial Management NIC 2 Redundant Power Supplies FIGURE 6.16 The front and rear of the Sun Fire x4150 1U server. The dimensions are 1.75 inches high by 19 inches wide. The eight 2.5-inch disks drives can be replaced from the front. In the upper right is a DVD and two USB ports. The picture below labels the items at the rear of the server. It has redundant power supplies and fans to allow the server to continue operating despite failures of one of these ­components.
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Figure 6.17 shows the connectivity and bandwidths of the chips on the mother­ board. Figures 6.9 and 6.10 describe the I/O chip set for the Intel 5345, and Figure 6.5 describes the SAS disks in the Sun Fire x4150. To clarify the advice on designing an I/O system in Section 6.8, let’s per­form a simple performance evaluation to see where the bottlenecks might be for a hypothetical application. I/O System Design Make the following assumptions about the Sun Fire x4150: ■ ■The user program uses 200,000 instructions per I/O operation ■ ■The operating system averages 100,000 instructions per I/O operation EXAMPLE A2 A3 A1 A0 B2 B3 B1 B0 D1 D0 D2 D3 C1 C0 C2 C3 Intel Xeon 5100/5300 Intel Xeon 5100/5300 FSB 1333 MT/s FSB 1333 MT/s 10.5 GB/s 10.5 GB/s Dual FSB to MCH XEON TM Channel A 5.3 GB/s Channel B 5.3 GB/s Channel C 5.3 GB/s Channel D 5.3 GB/s PCIe x16 - 2 PCIe x16 - 1 PCIe x16 - 0 PCIe x8 PCIe x8 PCIe x8 8x SAS HDDs MCH Blackford 5000P 2x USB PCI 32-bit 33 MHz PCIe x4 2x Rear USB 2.0 1x Internal USB 2.0 CD/DVD 2x Front USB 2.0 2x 1GB Ethernet 2 & 3 2x 1GB Ethernet 0 & 1 Serial RJ-45 Management 10/100 Ethernet VGA Video USB to IDE USB Hub IOH ESB-2 USB IDE PCIe ESI (PCIe) PCI-E SAS/RAID Controller DIMMs DIMMs DIMMs DIMMs XEON TM AST2000 Q62611.1 GP 0608 TAN A2 FIGURE 6.17 Logical connections and bandwidths of components in the Sun Fire x4150. The three PCIe connectors allow x16 boards to be plugged in, but it only provides eight lanes of bandwidth to the MCH. Source: Figure 5 of “SUN FIRE™ X4150 AND X4450. SERVER ARCHITECTURE” (see www.sun.com/servers/x64/x4150/). 6.10 Real Stuff: Sun Fire x4150 Server 609
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610 Chapter 6 Storage and Other I/O Topics ■ ■The workload consists of 64 KB reads ■ ■Each processor sustains 1 billion instructions per second Find the maximum sustainable I/O rate for a fully loaded Sun Fire x4150 for random reads and sequential reads. Assume that the reads can always be done on an idle disk if one exists (i.e., ignore disk conflicts) and that the RAID controller is not the bottleneck. Let’s first find the I/O rate of a single processor. Each I/O takes 200,000 user instructions and 100,000 OS instructions, so Maximum I/O rate of 1 processor = ​ Instruction execution rate  Instructions per I/O ​ = ​ 1 ´ 109  (200 + 100) ´ 103 ​ = 3,333 ​ I/Os  second ​ As a single Intel 5345 socket has four processors, it can perform 13,333 IOPS. Two sockets with eight processors can perform 26,667 IOPS. Let’s determine IOPS per disks for random and sequential reads for the 2.5-inch SAS disk described in Figure 6.5. Rather than use the average seek time from the disk manufacturer, let’s assume that it is only a quarter of that time, as is often the case (see Section 6.3). The time per random read of a single disk: Time per I/O at disk = Seek + rotational time + Transfer time = ​ 2.9  4 ​ ms + 2.0 ms + ​ 64 KB  112 MB/sec ​ = 3.3 ms Thus, each disk can complete 1000 ms/3.3 ms or 303 I/Os per second, and eight disks perform 2424 random reads per second. For sequential reads, it’s just the transfer size divided by the disk bandwidth: ​ 112 MB/sec  64 KB ​ = 1750 IOPS Eight disks can perform 14,000 sequential 64 KB reads. We need to see if the paths from the disks to memory and the processors are a bottleneck. Let’s start with the PCI Express interconnect from the RAID card to the north bridge chip. Each lane of a PCIe is 250 MB/second, so eight lanes can perform 2 GB/second. Max I/O rate of PCIe x8 = ​ PCI bandwidth  Bytes per I/O ​ = ​ 2 ´ 109  64 ´ 103 ​ = 31,250 ​ I/Os  second ​ Even eight disks transferring sequentially use less than half the PCIe x8 link. ANSWER
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Once the data gets to the MCB, it needs to be written into the DRAM. The bandwidth of a DDR2 667 MHz FBDIMM is 5336 MB/second. A single DIMM can perform ​ 5336 MB/sec  64 KB ​ = 83,375 IOPS The memory is not a bottleneck even with one DIMM, and we have 16 in a fully configured Sun Fire x4150. The final link in the chain is the Front Side Bus that connects north bridge hub to the Intel 5345 socket. Its peak bandwidth is 10.6 GB/sec, but Section 7.10 suggests you get no more than half peak. Each I/O transfers 64 KB, so Max I/O rate of FSB = ​ Bus bandwidth  Bytes per I/O ​ = ​ 5.3 ´ 109  64 ´ 103 ​ = 81,540 ​ I/Os  second ​ There is one Front Side Bus per socket, so the dual FSB peak is over 150,000 IOPS, and once again, the FSB is not a bottleneck. Hence, a fully configured Sun Fire x4150 can sustain the peak bandwidth of the eight disks, which is 2424 random reads per second or 14,000 sequential reads per second. Notice the significant number of simplifying assumptions that are needed to do this example. In practice, many of these simplifications might not hold for critical I/O-intensive applications. For this reason, running a realistic workload or rele­vant benchmark is often the only plausible way to evaluate I/O performance. As mention at the beginning of this section, these new datacenters are con­cerned about power and space as well as cost and performance. Figure 6.18 shows the idle and peak power required by a fully configured Sun Fire x4150, with a breakdown by each component. Let’s look at the alternative configurations of the Sun Fire x4150 to conserve power. I/O System Power Evaluation Reconfigure a Sun Fire x4150 to minimize power, assuming that the workload in the example above is the only activity on this 1U server. To achieve the 2424 random 64 KB reads per second from the prior example, we need all eight disks and the PCI RAID controller. From the calculations above, a single DIMM can support over 80,000 IOPS, so we can save power in mem­ory. The Sun Fire x4150 minimum memory is two DIMMs, so we can EXAMPLE ANSWER 6.10 Real Stuff: Sun Fire x4150 Server 611
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612 Chapter 6 Storage and Other I/O Topics save the power (and cost) of 14 4GB DIMMs. A single socket can support 13,333 IOPS, so we can also reduce the number of Intel E5345 sockets by one. Using the numbers in Figure 6.18, the total system power is now: Idle Powerrandom reads = 154 + 2 ´ 10 + 8 ´ 8 + 15 = 253 watts Peak Powerrandom reads = 215 + 2 ´ 11 + 8 ´ 8 + 15 = 316 watts or a reduction in power by a factor of 1.6 to 1.7. The original system can performance 14,000 64 KB sequential reads per second. We still need all the disks and the disk controller, and the same number of DIMMs can handle this higher load. This workload exceeds a processing power of the single Intel E5345 socket, so we need to add a second one. Idle Powersequential reads = 154 + 22 + 2 ´ 10 + 8 ´ 8 + 15 = 275 watts Peak Powersequential reads = 215 + 79 + 2 ´ 11 + 8 ´ 8 + 15 = 395 watts or a reduction in power by a factor of 1.4 to 1.5. Advanced Topics: Networks Networks are growing in popularity over time, and unlike other I/O devices, there are many books and courses on them. For readers who have not taken courses or 6.11 FIGURE 6.18 Idle and peak power of a fully configured Sun Fire x4150. These experiments came while running SPECJBB with 29 dif­ferent configurations, so the peak power could be different when running different applications (source: www.sun.com/servers/x64/ x4150/calc). Components System Item Idle Peak Number Idle Peak Single Intel 2.66 GHz E5345 socket, Intel 5000 MCB/IOH chip set, Ethernet controllers, power supplies, fans, . . . 154 W 215 W 1 154 W 37% 215 W 39% Additional Intel 2.66 GHz E5345 socket 22 W 79 W 1 22 W 5% 79 W 14% 4 GB DDR2-667 5300 FBDIMM 10 W 11 W 16 160 W 39% 176 W 32% 73 GB SAS 15K Disk drives 8 W 8 W 8 64 W 15% 64 W 12% PCIe x8 RAID Disk controller 15 W 15 W 1 15 W 4% 15 W 3% Total — — — 415 W 100% 549 W 100%
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read books on networking, Section 6.11 on the CD gives a quick overview of the topics and terminology, including Internetworking, the OSI model, protocol families such as TCP/IP, long-haul networks such as ATM, local area networks such as Ethernet, and wireless networks such as IEEE 802.11. 6.12 Fallacies and Pitfalls Fallacy: The rated mean time to failure of disks is 1,200,000 hours or almost 140 years, so disks practically never fail. Marketing practices of disk manufacturers have misled users. How is such an MTTF calculated? Early in the process, manufacturers will put thousands of disks in a room, run them for a few months, and count the number that fail. They com­ pute MTTF as the total number of hours that the disks were cumulatively avail­able divided by the number that failed. One problem is that this number far exceeds the lifetime of a disk, which is commonly assumed to be five years or 43,800 hours. For this large MTTF to make some sense, disk manufacturers argue that the calculation corresponds to a user who buys a disk, and then keeps replacing the disk every five years—the planned lifetime of the disk. The claim is that if many customers (and their great-­ grandchildren) did this for the next century, on average they would replace a disk 27 times before a failure, or about 140 years. A more useful measure would be percentage of disks that fail in a year, called annual failure rate (AFR). Assume 1000 disks with a 1,200,000-hour MTTF and that the disks are used 24 hours a day. If you replaced failed disks with a new one having the same reliability characteristics, the number that would fail per year (8,760 hours) is Failed disks = ​ 1000 drives ´ 8760 hours/drive  1,200,000 hours/failure ​ = 7.3 Stated alternatively, the AFR is 0.73%. Disk manufacturers are starting to quote AFR as well as MTTB to give users better intuition about what to expect about their products. Fallacy: Disk failure rates in the field match their specifications. Two recent studies evaluated large collections of disks to check the relationship between results in the field compared to specifications. One study was of almost 100,000 ATA and SCSI disks that had quoted MTTF of 1,000,000 to 1,500,000 hours, or AFR of 0.6% to 0.8%. They found AFRs of 2% to 4% to be common, often three to five times higher than the specified rates [Schroeder and Gibson, 2007]. 6.12 Fallacies and Pitfalls 613
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614 Chapter 6 Storage and Other I/O Topics A sec­ond study of more than 100,000 ATA disks, which had a quoted AFR of about 1.5%, saw failure rates of 1.7% for drives in their first year rise to 8.6% for drives in their third year, or about five to six times the specified rate [Pinheiro, Weber, and Bar­roso, 2007]. Fallacy: A GB/sec interconnect can transfer 1 GB of data in 1 second. First, you generally cannot use 100% of any computer resource. For a bus, you would be fortunate to get 70% to 80% of the peak bandwidth. Time to send the address, time to acknowledge the signals, and stalls while waiting to use a busy bus are among the reasons you cannot use 100% of a bus. Second, the definition of a gigabyte of storage and a gigabyte per second of bandwidth do not agree. As we discussed on page 596, I/O bandwidth measures are usually quoted in base 10 (i.e., 1 GB/sec = 109 bytes/sec), while 1 GB of data is typically a base 2 measure (i.e., 1 GB = 230 bytes). How significant is this distinc­ tion? If we could use 100% of the bus for data transfer, the time to transfer 1 GB of data on a 1 GB/sec interconnect is actually ​ 230  109 ​ = ​ 1,073,741,824  1,000,000,000 ​ = 1.073741824 » 1.07 seconds Pitfall: Trying to provide features only within the network versus end to end. The concern is providing at a lower-level features that can only be accomplished at the highest ­level, thus only partially satisfying the communication demand. Saltzer, Reed, and Clark [1984] give the end-to-end argument, as follows: The function in question can completely and correctly be specified only with the knowledge and help of the application standing at the endpoints of the commu­ nication system. Therefore, providing that questioned function as a feature of the communication system itself is not possible. Their example of the pitfall was a network at MIT that used several gateways, each of which added a checksum from one gateway to the next. The programmers of the application assumed the checksum guaranteed accuracy, incorrectly believ­ ing that the message was protected while stored in the memory of each gateway. One gateway developed a transient failure that swapped one pair of bytes per mil­ lion bytes transferred. Over time the source code of one operating system was repeatedly passed through the gateway, thereby corrupting the code. The only solution was to correct the infected source files by comparing to paper listings and repairing the code by hand! Had the checksums been calculated and checked by the application running on the end systems, safety would have been assured. There is a useful role for intermediate checks, however, provided that end-to-end checking is available. End-to-end checking may show that something is ­bro­ken between
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two nodes, but it doesn’t point to where the problem is. Intermediate checks can discover which component is broken. You need both for repair. Pitfall: Moving functions from the CPU to the I/O processor, expecting to improve performance without a careful analysis. There are many examples of this pitfall trapping people, although I/O processors, when properly used, can certainly enhance performance. A frequent instance of this fallacy is the use of intelligent I/O interfaces, which, because of the higher overhead to set up an I/O request, can turn out to have worse latency than a ­processor-directed I/O activity (although if the processor is freed up sufficiently, system throughput may still increase). Frequently, performance falls when the I/O processor has much lower performance than the main processor. Consequently, a small amount of main processor time is replaced with a larger amount of I/O pro­ cessor time. Workstation designers have seen both these phenomena repeatedly. Myer and Sutherland [1968] wrote a classic paper on the tradeoff of complex­ ity and performance in I/O controllers. Borrowing the religious concept of the “wheel of reincarnation,” they eventually noticed they were caught in a loop of continuously increasing the power of an I/O processor until it needed its own simpler coprocessor: We approached the task by starting with a simple scheme and then adding com­mands and features that we felt would enhance the power of the machine. Gradually the [display] processor became more complex . . . . Finally the display processor came to resemble a full-fledged computer with some special graphics features. And then a strange thing happened. We felt compelled to add to the processor a second, subsidiary processor, which, itself, began to grow in ­com­plexity. It was then that we discovered the disturbing truth. Designing a display processor can become a never-ending cyclical process. In fact, we found the pro­cess so frustrating that we have come to call it the “wheel of reincarnation.” Pitfall: Using magnetic tapes to back up disks. This is both a fallacy and a pitfall. Magnetic tapes have been part of computer sys­tems as long as disks because they use similar technology as disks, and hence his­torically have followed the same density improvements. The historic cost/ performance difference between disks and tapes is based on a sealed, rotating disk having lower access time than sequential tape access; but removable spools of magnetic tape mean many tapes can be used per reader, and they can be very long and so have high capacity. Hence, in the past a single magnetic tape could hold the contents of many disks, and since it was 10 to 100 times cheaper per gigabyte than disks, it was a useful backup medium. The claim was that magnetic tapes must track disks since innovations in disks must help tapes. This claim was important because tapes were a small market and could not afford a separate large research and development effort. One reason the market is small is that desktop owners generally do not back up disks onto tape, 6.12 Fallacies and Pitfalls 615
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616 Chapter 6 Storage and Other I/O Topics and so while desktops are by far the largest market for disks, desktops are a small market for tapes. Alas, the larger market has led disks to improve much more quickly than tapes. Starting in 2000 to 2002, the largest popular disk was larger than the largest popu­lar tape. In that same time frame, the price per gigabyte of ATA disks dropped below that of tapes. Tape advocates claim that tapes have compatibility require­ments that are not imposed on disks; tape readers must read or write the current and previous generation of tapes, and must read the last four generations of tapes. As disks are closed systems, disk heads need only read the platters enclosed with them, and this advantage explains why disks are improving much more rapidly. Today, some organizations have dropped tapes altogether, using networks and remote disks to replicate the data geographically. Indeed, many companies offer­ing software as a service use inexpensive components but replicate data at an applica­ tion level across multiples sites. The sites are picked so that disasters would not take out both sites, enabling instantaneous recovery time. (Long recovery time for site disasters is another serious drawback to the serial nature of magnetic tapes.) Such a solution depends on advances in disk capacity and network band­width to make economic sense, but these two are getting much greater investment and hence have better recent records of accomplishment than tape. Fallacy: Operating systems are the best place to schedule disk accesses. As mentioned in Section 6.3, higher-level interfaces like ATA and SCSI offer logi­cal block addresses to the host operating system. Given this high-level abstraction, the best an OS can do to try to help performance is to sort the logical block addresses into increasing order. However, since the disk knows the actual mapping of the logical addresses onto the physical geometry of sectors, tracks, and surfaces, it can reduce the rotational and seek latencies by rescheduling. For example, suppose the workload is four reads [Anderson, 2003]: Operation Starting LBA Length Read 724 8 Read 100 16 Read 9987 1 Read 26 128 The host might reorder the four reads into logical block order: Operation Starting LBA Length Read 26 128 Read 100 16 Read 724 8 Read 9987 1
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Depending on the relative location of the data on the disk, reordering could make it worse, as Figure 6.19 shows. The disk-scheduled reads complete in three-quarters of a disk revolution, but the OS-scheduled reads take three revolutions. Pitfall: Using the peak transfer rate of a portion of the I/O system to make perfor­ mance projections or performance comparisons. Many of the components of an I/O system, from the devices to the controllers to the buses, are specified using their peak bandwidths. In practice, these peak band­ width measurements are often based on unrealistic assumptions about the system or are unattainable because of other system limitations. For example, in quoting bus performance, the peak transfer rate is sometimes specified using a memory system that is impossible to build. For networked systems, the software overhead of initiating communication is ignored. The 32-bit, 33MHz PCI bus has a peak bandwidth of about 133 MB/sec. In practice, even for long transfers, it is difficult to sustain more than about 80 MB/sec for realistic memory systems. Amdahl’s law also reminds us that the throughput of an I/O system will be limited by the lowest-performance component in the I/O path. 6.13 Concluding Remarks I/O systems are evaluated on several different characteristics: dependability; the va­riety of I/O devices supported; the maximum number of I/O devices; cost; and performance, measured both in latency and in throughput. These goals lead to FIGURE 6.19 Example showing OS versus disk schedule accesses, labeled host-ordered versus drive-ordered. The former takes three revolutions to complete the four reads, while the latter completes them in just three-fourths of a revolution (from Anderson [2003]). Host-ordered queue Drive-ordered queue 724 100 26 9987 6.13 Concluding Remarks 617
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618 Chapter 6 Storage and Other I/O Topics widely varying schemes for interfacing I/O devices. In the low-end and midrange systems, buffered DMA is likely to be the dominant transfer mechanism. In the high-end systems, latency and bandwidth may both be important, and cost may be secondary. Multiple paths to I/O devices with limited buffering often charac­ terize high-end I/O systems. Typically, being able to access the data on an I/O device at any time (high availability) becomes more important as systems grow. As a result, redundancy and error correction mechanisms become more and more prevalent as we enlarge the system. Storage and networking demands are growing at unprecedented rates, in part because of increasing demands for all information to be at your fingertips. One estimate is that the amount of information created in 2002 was 5 exabytes— equivalent to 500,000 copies of the text in the U.S. Library of Congress—and that the total amount of information in the world was doubling every three years [Lyman and Varian, 2003]. Future directions of I/O include expanding the reach of wired and wireless net­ works, with nearly every device potentially having an IP address, and the expanding role of flash memory in storage systems. The performance of an I/O system, whether measured by bandwidth or latency, depends on all the elements in the path between the device and memory, includ­ ing the operating system that generates the I/O commands. The bandwidth of the interconnect, the memory, and the device determine the maximum transfer rate from or to the device. Similarly, the latency depends on the device latency, together with any latency imposed by the memory system or buses. The effective bandwidth and response latency also depend on other I/O requests that may cause contention for some resource in the path. Finally, the operating system is a bottle­neck. In some cases, the OS takes a long time to deliver an I/O request from a user program to an I/O device, leading to high latency. In other cases, the operating system effectively limits the I/O bandwidth because of limitations in the number of concurrent I/O operations it can support. Keep in mind that while performance can help sell an I/O system, users over­ whelmingly demand capacity and dependability from their I/O systems. Historical Perspective and Further Reading The history of I/O systems is a fascinating one. Section 6.14 gives a brief his­tory of magnetic disks, RAID, flash memory, databases, the Internet, the World Wide Web, and how Ethernet continues to triumph over its challengers. Understanding Program Performance 6.14
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6.15 Exercises Contributed by Perry Alexander of the University of Kansas Exercise 6.1 Figure 6.2 describes numerous I/O devices in terms of their behavior, partner, and data rate. However, these classifications often do not provide a complete picture of data flow within a system. Explore device classifications for the following devices. a. Auto Pilot b. Automated Thermostat 6.1.1 [5] <6.1> For the devices listed in the table, identify I/O interfaces and ­classify them in terms of their behavior and partner. 6.1.2 [5] <6.1> For the interfaces identified in the previous problem, estimate their data rate. 6.1.3 [5] <6.1> For the interfaces identified in the previous problem, determine whether data rate or operation rate is the best performance measurement. Exercise 6.2 Mean Time Between Failures (MTBF), Mean Time To Replacement (MTTR), and Mean Time To Failure (MTTF) are useful metrics for evaluating the reliability and availability of a storage resource. Explore these concepts by answering the ques­ tions about devices with the following metrics. MTTF MTTR a. 3 Years 1 Day b. 7 Years 3 Days 6.2.1 [5] <6.1, 6.2> Calculate the MTBF for each of the devices in the table. 6.2.2 [5] <6.1, 6.2> Calculate the availability for each of the devices in the table. 6.2.3 [5] <6.1, 6.2> What happens to availability as the MTTR approaches 0? Is this a realistic situation? 6.2.4 [5] <6.1, 6.2> What happens to availability as the MTTR gets very high, i.e., a device is difficult to repair? Does this imply the device has low availability? 6.15 Exercises 619
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620 Chapter 6 Storage and Other I/O Topics Exercise 6.3 Average and minimum times for reading and writing to storage devices are ­common measurements used to compare devices. Using techniques from Chap­ ter 6, calculate values related to read and write time for disks with the following ­characteristics. Average Seek Time RPM Disk Transfer Rate Controller Transfer Rate a. 10 ms 7500 90 MB/s 100 MB/s b. 7 ms 10,000 40 MB/s 200 MB/s 6.3.1 [10] <6.2, 6.3> Calculate the average time to read or write a 1024-byte ­sector for each disk listed in the table. 6.3.2 [10] <6.2, 6.3> Calculate the minimum time to read or write a 2048-byte sector for each disk listed in the table. 6.3.3 [10] <6.2, 6.3> For each disk in the table, determine the dominant factor for performance. Specifically, if you could make an improvement to any aspect of the disk, what would you choose? If there is no dominant factor, explain why. Exercise 6.4 Ultimately, storage system design requires consideration of usage scenarios as well as disk parameters. Different situations require different metrics. Let’s try to systematically evaluate disk systems. Explore differences in how storage systems should be evaluated by answering the questions about the following applications. a. Aircraft Control System b. Phone Switch 6.4.1 [5] <6.2, 6.3> For each application, would decreasing the sector size during reads and writes improve performance? Explain your answer. 6.4.2 [5] <6.2, 6.3> For each application, would increasing disk rotation speed improve performance? Explain your answer. 6.4.3 [5] <6.2, 6.3> For each application, would increasing disk rotation speed improve system performance given that MTTF is decreased? Explain your answer.
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Exercise 6.5 FLASH memory is one of the first true competitors for traditional disk drives. Explore the implications of FLASH memory by answering questions about the ­following applications. a. Aircraft Control System b. Phone Switch 6.5.1 [5] <6.2, 6.3, 6.4> As we move towards solid state drives constructed from FLASH memory, what will change about disk read times assuming that the data transfer rate stays constant? 6.5.2 [10] <6.2, 6.3, 6.4> Would each application benefit from a solid state FLASH drive given that cost is a design factor? 6.5.3 [10] <6.2, 6.3, 6.4> Would each application be inappropriate for a solid state FLASH drive given that cost is NOT a design factor? Exercise 6.6 Explore the nature of FLASH memory by answering the questions related to per­ formance for FLASH memories with the following characteristics. Data Transfer Rate Controller Transfer Rate a. 120 MB/s 100 MB/s b. 100 MB/s 90 MB/s 6.6.1 [10] <6.2, 6.3, 6.4> Calculate the average time to read or write a 1024-byte sector for each FLASH memory listed in the table. 6.6.2 [10] <6.2, 6.3, 6.4> Calculate the minimum time to read or write a 512-byte sector for each FLASH memory listed in the table. 6.6.3 [5] <6.2, 6.3, 6.4> Figure 6.6 shows that FLASH memory read and write access times increase as FLASH memory gets larger. Is this unexpected? What fac­ tors cause this? 6.15 Exercises 621
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622 Chapter 6 Storage and Other I/O Topics Exercise 6.7 I/O can be performed either synchronously or asynchronously. Explore the differ­ ences by answering performance questions about the following peripherals. a. Printer b. Scanner 6.7.1 [5] <6.5> What would be the most appropriate bus type (synchronous or asynchronous) for handling communications between a CPU and the peripherals listed in the table? 6.7.2 [5] <6.5> What problems would long, synchronous busses cause for con­ nections between a CPU and the peripherals listed in the table? 6.7.3 [5] <6.5> What problems would asynchronous busses cause for connec­ tions between a CPU and the peripherals listed in the table? Exercise 6.8 Among the most common bus types used in practice today are FireWire (IEEE 1394), USB, PCI, and SATA. Although all four are asynchronous, they are imple­ mented in different ways giving them different characteristics. Explore differ­ ent bus structures by answering questions about the busses and the following peripherals. a. Mouse b. Graphics Coprocessor 6.8.1 [5] <6.5> Select an appropriate bus (FireWire, USB, PCI, or SATA) for the peripherals listed in the table. Explain why the bus selected is appropriate. (See Figure 6.8 for key characteristics of each bus.) 6.8.2 [20] <6.5> Use online or library resources and summarize the communica­ tion structure for each bus type. Identify what the bus controller does and where the control physically is. 6.8.3 [15] <6.5> Outline limitations of each of the bus types. Explain why those limitations must be taken into consideration when using the bus. Exercise 6.9 Communicating with I/O devices is achieved using combinations of polling, interrupt handling, memory mapping, and special I/O commands. Answer the
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­questions about communicating with I/O subsystems for the following applica­ tions using combinations of these techniques. a. Auto Pilot b. Automated Thermostat 6.9.1 [5] <6.6> Describe device polling. Would each application in the table be appropriate for communication using polling techniques? Explain. 6.9.2 [5] <6.6> Describe interrupt driven communication. For each application in the table, if polling is inappropriate, explain how interrupt driven techniques could be used. 6.9.3 [10] <6.6> For the applications listed in the table, outline a design for memory mapped communication. Identify reserved memory locations and out­ line their contents. 6.9.4 [10] <6.6> For the applications listed in the table, outline a design for com­ mands implementing command driven communication. Identify commands and their interaction with the device. 6.9.5 [5] <6.6> Does it make sense to define I/O subsystems that use a combi­ nation of memory mapping and command driven communication? Explain your answer. Exercise 6.10 Section 6.6 defines an eight-step process for handling interrupts. The Cause and Status registers together provide information on the cause of the interrupt and the status of the interrupt handling system. Explore interrupt handling by answering the questions about the following combinations of interrupts. a. Ethernet Controller Data Mouse Controller Reboot b. Mouse Controller Power Down Overheat 6.10.1 [5] <6.6> When an interrupt is detected, the Status register is saved and all but the highest priority interrupt is disabled. Why are low-priority interrupts disabled? Why is the status register saved prior to disabling interrupts? 6.10.2 [10] <6.6> Prioritize interrupts from the devices listed in each table row. 6.10.3 [10] <6.6> Outline how an interrupt from each of the devices listed in the table would be handled. 6.15 Exercises 623
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624 Chapter 6 Storage and Other I/O Topics 6.10.4 [5] <6.6> What happens if the interrupt enable bit of the Cause register is not set when handling an interrupt? What value could the interrupt mask value take to accomplish the same thing? 6.10.5 [5] <6.6> Most interrupt handling systems are implemented in the operat­ ing system. What hardware support could be added to make interrupt handling more efficient? Contrast your solution to potential hardware support for function calls. 6.10.6 [5] <6.6> In some interrupt handling implementations, an interrupt causes an immediate jump to an interrupt vector. Instead of a Cause register where each interrupt sets a bit, each interrupt has its own interrupt vector. Can the same priority interrupt system be implemented using this approach? Is there any advan­ tage to this approach? Exercise 6.11 Direct Memory Access (DMA) allows devices to access memory directly rather than working through the CPU. This can dramatically speed up the performance of peripherals, but adds complexity to memory system implementations. Explore DMA implications by answering the questions about the following peripherals. a. Mouse Controller b. Ethernet Controller 6.11.1 [5] <6.6> Does the CPU relinquish control of memory when DMA is active? For example, can a peripheral simply communicate with memory directly, avoiding the CPU completely? 6.11.2 [10] <6.6> Of the peripherals listed in the table, which would benefit from DMA? What criteria determine if DMA is appropriate? 6.11.3 [10] <6.6> Of the peripherals listed in the table, which could cause coher­ ency problems with cache contents? What criteria determine if coherency issues must be addressed? 6.11.4 [5] <6.6> Describe what problems could occur when mixing DMA and virtual memory. Which of the peripherals in the table could introduce such prob­ lems? How can they be avoided? Exercise 6.12 Metrics for I/O performance may vary dramatically from application to applica­ tion. Where the number of transactions processed dominates performance in some
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situations, data throughput dominates in others. Explore I/O performance evalua­ tion by answering the questions for the following applications. a. Mathematical Computations b. Online Chat 6.12.1 [10] <6.7> For each application in the table, does I/O performance domi­ nate system performance? 6.12.2 [10] <6.7> For each application in the table, is I/O performance best mea­ sured using raw data throughput? 6.12.3 [5] <6.7> For each application in the table, is I/O performance best mea­ sured using the number of transactions processed? 6.12.4 [5] <6.7> Is there a relationship between the performance measures from the previous two problems and choosing whether to use polling or interrupt driven communication? What about the choice of using memory mapped or command driven I/O? Exercise 6.13 Benchmarks play an important role in evaluating and selecting peripheral devices. For benchmarks to be useful, they must exhibit properties similar to those experi­ enced by a device under normal use. Explore benchmarks and device selection by answering questions about the following applications. a. Mathematical Computations b. Online Chat 6.13.1 [5] <6.7> For each application in the table, define characteristics that a set of benchmarks should exhibit when evaluating an I/O subsystem. 6.13.2 [15] <6.7> Using online or library resources, identify a set of standard benchmarks for applications in the table. Why do standard benchmarks help? 6.13.3 [5] <6.7> Does it make sense to evaluate an I/O subsystem outside the larger system it is a part of? How about evaluating a CPU? Exercise 6.14 RAID is among the most popular approaches to parallelism and redundancy in storage systems. The name Redundant Arrays of Inexpensive Disks implies ­several 6.15 Exercises 625
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626 Chapter 6 Storage and Other I/O Topics things about RAID arrays that we will explore in the context of the following ­activities. a. High-Performance Mathematical Computations b. Online Video Services 6.14.1 [10] <6.9> RAID 0 uses striping to force parallel access among many disks. Why does striping improve disk performance? For each of the activities listed in the table, will striping help better achieve their goals? 6.14.2 [5] <6.9> RAID 1 mirrors data among several disks. Assuming that inex­ pensive disks have lower MTBF than expensive disks, how can redundancy using inexpensive disks result in a system with lower MTBF? Use the mathematical defi­ nition of MTBF to explain your answer. For each of the activities listed in the table, will RAID 1 help better achieve their goals? 6.14.3 [5] <6.9> Like RAID 1, RAID 3 provides higher data availability. Explain the trade-off between RAID 1 and RAID 3. Would each of the applications listed in the table benefit from RAID 3 over RAID 1? Exercise 6.15 RAID 3, RAID 4, and RAID 5 all use parity system to protect blocks of data. ­Specifically, a parity block is associated with a collection of data blocks. Each row in the following table shows the values of the data and parity blocks, as described in Figure 6.13. New D0 D0 D1 D2 D3 P a. 7453 AB9C AABB 0098 549C 2FFF b. F245 7453 DD25 AABB FEFE FEFF 6.15.1 [10] <6.9> Calculate the new RAID 3 parity value P’ for data in lines a and b in the table. 6.15.2 [10] <6.9> Calculate the new RAID 4 parity value P’ for data in lines a and b in the table. 6.15.3 [5] <6.9> Is RAID 3 or RAID 4 more efficient? Are there reasons why RAID 3 would be preferable to RAID 4? 6.15.4 [5] <6.9> RAID 4 and RAID 5 use roughly the same mechanism to calcu­ late and store parity for data blocks. How does RAID 5 differ from RAID 4 and for what applications would RAID 5 be more efficient?
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6.15.5 [5] <6.9> RAID 4 and RAID 5 speed improvements grow with respect to RAID 3 as the size of the protected block grows. Why is this the case? Is there a situ­ ation where RAID 4 and RAID 5 would be no more efficient than RAID 3? Exercise 6.16 The emergence of web servers for ecommerce, online storage, and communication has made disk servers critical applications. Availability and speed are well-known metrics for disk servers, but power consumption is becoming increasingly impor­ tant. Answer the questions about configuration and evaluation of disk servers with the following parameters. Program Instructions/ I/O Operation OS Instructions/ I/O Operation Workload (KB reads) Processor Speed (Instructions/ Second) a. 100,000 150,000 64 2 Billion b. 200,000 200,000 128 3 Billion 6.16.1 [10] <6.8, 6.10> Find the maximum sustained I/O rate for random reads and writes. Ignore disk conflicts and assume the RAID controller is not the bottleneck. Follow the same approach as outlined in Section 6.10 making similar assumptions where necessary. 6.16.2 [10] <6.8, 6.10> Assume we are configuring a Sun Fire x4150 server as described in Section 6.10. Determine if a configuration of 8 disks presents an I/O bottleneck. Repeat for configurations of 16, 4, and 2 disks. 6.16.3 [10] <6.8, 6.10> Determine if the PCI bus, DIMM, or the Front Side Bus presents an I/O bottleneck. Use the same parameters and assumptions used in Section 6.10. 6.16.4 [5] <6.8, 6.10> Explain why real systems tend to use benchmarks or real applications to assess actual performance. Exercise 6.17 Determining the performance of a single server with relatively complete data is an easy task. However, when comparing servers from different vendors providing dif­ ferent data, choosing among alternatives can be difficult. Explore the process of find­ ing and evaluating servers by answering questions about the following application. Database Server 6.17.1 [15] <6.8, 6.10> For the application listed above, identify runtime charac­ teristics for an operational system. Choose characteristics that will support evalua­ tion similar to that performed for Exercise 6.16. 6.15 Exercises 627
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628 Chapter 6 Storage and Other I/O Topics 6.17.2 [15] <6.8, 6.10> For the application listed above, find a server available in the marketplace that you feel would be appropriate for running the application. Before evaluating the server, identify reasons why it was selected. 6.17.3 [20] <6.8, 6.10> Using metrics similar to those used in Chapter 6 and Exercise 6.16, assess the server you identified in 6.17.2 in comparison to the Sun Fire x4150 server evaluated in Exercise 6.16. Which would you choose? Did the results of your analysis surprise you? Specifically, would you choose differently? 6.17.4 [15] <6.8, 6.10> Identify a standard benchmark set that would be useful for comparing the server you identified in 6.17.2 with the Sun Fire x4150. Exercise 6.18 Measurements and statistics provided by storage vendors must be carefully inter­ preted to gain meaningful predictions about their system behavior. The following table provides data for various disk drives. # of Drives Hours/Drive Hours/Failure a. 1000 10,512 1,200,000 b. 1250 8760 1,200,000 6.18.1 [10] <6.12> Calculate annual failure rate (AFR) for disks in the table. 6.18.2 [10] <6.12> Assume that annual failure rate varies over the lifetime of disks in the previous table. Specifically, assume that AFR is three times as high in the 1st month of operation and doubles every year starting in the 5th year. How many disks would be replaced after 7 years of operation? What about 10 years? 6.18.3 [10] <6.12> Assume that disks with lower failure rates are more expen­ sive. Specifically, disks are available at a higher cost that will start doubling their failure rate in year 8 rather than year 5. How much more would you pay for disks if your intent is to keep them for 7 years? What about 10 years? Exercise 6.19 For disks in the table in Exercise 6.18, assume that your vendor offers a RAID 0 configuration that will increase storage system throughput by 70% and a RAID 1 configuration that will drop AFR of disk pairs by 2. Assume that the cost of each solution is 1.6 times the original solution cost. 6.19.1 [5] <6.9, 6.12> Given only the original problem parameters, would you recommend upgrading to either RAID 0 or RAID 1 assuming individual disk parameters remain the same in the previous table?
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6.19.2 [5] <6.9, 6.12> Given that your company operates a global search engine with a large disk farm, does upgrading to either RAID 0 or RAID 1 make economic sense given that your income model is based on the number of advertisements served? 6.19.3 [5] <6.9, 6.12> Repeat 6.19.2 for a large disk farm operated by an online backup company. Does upgrading to either RAID 0 or RAID 1 make economic sense given that your income model is based on the availability of your server? Exercise 6.20 Day-to-day evaluation and maintenance of operational computer systems involves many of the concepts discussed in Chapter 6. Explore the intricacies of evaluating systems by exploring the following questions. 6.20.1 [20] <6.10, 6.12> Configure the Sun Fire x4150 to provide 10 terabytes of storage for a processor array of 1000 processors running bioinformatics simula­ tions. Your configuration should minimize power consumption while addressing throughput and availability concerns for the disk array. Make sure you consider the properties of large simulations when performing your configuration. 6.20.2 [20] <6.10, 6.12> Recommend a backup and data archiving system for the disk array from 6.20.1. Compare and contrast disk, tape, and online backup capa­ bilities. Use Internet and library resources to identify potential servers. Assess cost and suitability for the application using parameters described in Chapter 6. Select parameters for comparison using properties of the application as well as specified requirements. 6.20.3 [15] <6.10, 6.12> Competing vendors for the systems you identified in 6.20.2 have offered to allow you to evaluate their systems on site. Identify the benchmarks you will use to determine which system is best for your applica­ tion. Determine how long it will take you to gather enough data to make your determination. §6.2, page 575: 2 and 3 are true. §6.3, page 579: 3 and 4 are true. §6.4, page 582: All are true (assuming 40 MB/s is comparable to100 MB/s). §6.5, page 585: 1 is true. §6.6, page 594: 1 and 2. §6.7, page 598: 1 and 2. 3 is false, since most TPC benchmarks include cost. §6.9, page 605: All are true. Answers to Check Yourself 6.15 Exercises 629
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7 There are finer fish in the sea than have ever been caught. Irish proverb Multicores, Multiprocessors, and Clusters 7.1 Introduction 632 7.2 The Difficulty of Creating Parallel Processing Programs 634 7.3 Shared Memory Multiprocessors 638 7.4 Clusters and Other Message-Passing Multiprocessors 641 7.5 Hardware Multithreading 645 Computer Organization and Design. DOI: 10.1016/B978-0-12-374750-1.00007-4 © 2012 Elsevier, Inc. All rights reserved.
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7.6 SISD, MIMD, SIMD, SPMD, and Vector 648 7.7 Introduction to Graphics Processing Units 654 7.8 Introduction to Multiprocessor Network Topologies 660 7.9 Multiprocessor Benchmarks 664 7.10 Roofline: A Simple Performance Model 667 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 675 7.12 Fallacies and Pitfalls 684 7.13 Concluding Remarks 686 7.14 Historical Perspective and Further Reading 688 7.15 Exercises 688 Multiprocessor or Cluster Organization Computer Computer Computer Computer Network
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632 Chapter 7 Multicores, Multiprocessors, and Clusters 7.1 Introduction Computer architects have long sought the El Dorado of computer design: to create power­ful computers simply by connecting many existing smaller ones. This golden vision is the fountainhead of multiprocessors. Ideally, customers order as many processors as they can afford and receive a commensurate amount of per­formance. Thus, multiprocessor software must be designed to work with a variable number of processors. As mentioned in Chapter 1, power has become the overrid­ing issue for both datacenters and microprocessors. Replacing large inefficient processors with many smaller, efficient processors can deliver better performance per watt or per joule both in the large and in the small, if software can efficiently use them. Thus, improved power efficiency joins scalable performance in the case for multi­ processors. Since multiprocessor software must scale, some designs support operation in the presence of broken hardware; that is, if a single processor fails in a multipro­ cessor with n processors, these system would continue to provide service with n - 1 processors. Hence, multiprocessors can also improve availability (see Chapter 6). High performance can mean high throughput for independent jobs, called job- level parallelism or process-level parallelism. These parallel jobs are independent appli­cations, and they are an important and popular use of parallel computers. This approach is in contrast to running a single job on multiple processors. We use the term parallel processing program to refer to a single program that runs on multi­ ple processors simultaneously. There have long been scientific problems that have needed much faster com­ puters, and this class of problems has been used to justify many novel parallel computers over the past decades. We will cover several of them in this chapter. Some of these problems can be handled simply, using a cluster composed of microprocessors housed in many independent servers or PCs. In addition, clus­ ters can serve equally demanding applications outside the sciences, such as search engines, Web servers, email servers, and databases. As described in Chapter 1, multiprocessors have been shoved into the spot­ light because the power problem means that future increases in performance will apparently come from more processors per chip rather than higher clock rates and improved CPI. They are called multicore microprocessors instead of multipro­cessor microprocessors, presumably to avoid redundancy in ­naming. Hence, pro­cessors are often called cores in a multicore chip. The number of cores is expected to double every two years. Thus, programmers who care about performance must become parallel programmers, for sequential programs mean slow programs. multiprocessor A computer system with at least two proces­sors. This is in contrast to a uni­processor, which has one. job-level parallelism or process-level parallelism Utilizing multiple processors by running independent programs simultaneously. parallel processing program A single program that runs on multiple processors simultaneously. cluster A set of computers connected over a local area network (LAN) that functions as a single large multiprocessor. multicore microprocessor ­ A microprocessor containing mul­tiple processors (“cores”) in a single integrated circuit. “Over the Mountains Of the Moon, Down the Valley of the Shadow, Ride, boldly ride” The shade replied,— “If you seek for El Dorado!” Edgar Allan Poe, “El Dorado,” stanza 4, 1849
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7.1 Introduction 633 The tall challenge facing the industry is to create hardware and software that will make it easy to write correct parallel processing programs that will execute efficiently in performance and power as the number of cores per chip scales geo­metrically. This sudden shift in microprocessor design has caught many off guard, so there is a great deal of confusion about the terminology and what it means. Figure 7.1 tries to clarify the terms serial, parallel, sequential, and concurrent. The columns of this figure represent the software, which is either inherently sequential or concur­rent. The rows of the figure represent the hardware, which is either serial or paral­lel. For example, the programmers of compilers think of them as sequential programs: the steps are lexical analysis, parsing, code generation, optimization, and so on. In contrast, the programmers of operating systems normally think of them as concurrent programs: cooperating processes handling I/O events due to independent jobs running on a computer. Software Sequential Concurrent Hardware Serial Matrix Multiply written in MatLab running on an Intel Pentium 4 Windows Vista Operating System running on an Intel Pentium 4 Parallel Matrix Multiply written in MATLAB running on an Intel Xeon e5345 (Clovertown) Windows Vista Operating System running on an Intel Xeon e5345 (Clovertown) FIGURE 7.1 Hardware/software categorization and examples of application perspective on concurrency versus hardware perspective on parallelism. The point of these two axes of Figure 7.1 is that concurrent software can run on serial hardware, such as operating systems for the Intel Pentium 4 uniprocessor, or on parallel hardware, such as an OS on the more recent Intel Xeon e5345 (Clovertown). The same is true for sequential software. For example, the MATLAB pro­grammer writes a matrix multiply thinking about it sequentially, but it could run serially on Pentium 4 hardware or in parallel on Xeon e5345 hardware. You might guess that the only challenge of the parallel revolution is figuring out how to make naturally sequential software have high performance on parallel hardware, but it is also to make concurrent programs have high performance on multiprocessors as the number of processors increases. With this distinction made, in the rest of this chapter we will use parallel processing program or parallel software to mean either sequential or concurrent software running on parallel hardware. The next section describes why it is hard to create efficient parallel processing programs. Sections 7.3 and 7.4 describe the two alternatives of a fundamental par­allel hardware characteristic, which is whether or not all the processors in the sys­tems rely upon a single physical address. The two popular versions of these alternatives are called shared memory multiprocessors and clusters. Section 7.5 then
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634 Chapter 7 Multicores, Multiprocessors, and Clusters describes multithreading, a term often confused with multiprocessing, in part because it relies upon similar concurrency in programs. Section 7.6 describes an older classification scheme than in Figure 7.1. In addition, it describes two styles of instruction set architectures that support running of sequential applications on parallel hardware, namely SIMD and vector. Section 7.7 describes a relatively new style of computer from the graphics hardware community, called a graphics pro­ cessing unit (GPU). Appendix A describes GPUs in more detail. We next discuss the diffi­culty of finding parallel benchmarks in Section 7.9. This section is followed by a description of a new, simple, yet insightful performance model that helps in the design of applications as well as architectures. We use this model in Section 7.11 to evaluate four recent multicore computers on two application kernels. We close with fallacies and pitfalls and our conclusions for parallelism. Before proceeding further down the path to parallelism, don’t forget our initial incursions from the prior chapters: ■ ■Chapter 2, Section 2.11: Parallelism and Instructions: Synchronization ■ ■Chapter 3, Section 3.6: Parallelism and Computer Arithmetic: Associativity ■ ■Chapter 4, Section 4.10: Parallelism and Advanced Instruction-Level Parallelism ■ ■Chapter 5, Section 5.8: Parallelism and Memory Hierarchies: Cache Coherence ■ ■Chapter 6, Section 6.9: Parallelism and I/O: Redundant Arrays of Inexpensive Disks True or false: To benefit from a multiprocessor, an application must be concur­rent. 7.2 The Difficulty of Creating Parallel Processing Programs The difficulty with parallelism is not the hardware; it is that too few important application programs have been rewritten to complete tasks sooner on multi­ processors. It is difficult to write software that uses multiple processors to complete one task faster, and the problem gets worse as the number of processors increases. Why has this been so? Why have parallel processing programs been so much harder to develop than sequential programs? The first reason is that you must get better performance and efficiency from a parallel processing program on a multiprocessor; otherwise, you would just use a sequential program on a uni­processor, as programming is easier. In fact, uniprocessor design techniques such as superscalar and out-of-order execution take advantage of instruction-level parallelism (see Chapter 4), normally without the involvement of the programmer. Such innovations reduced the demand for rewriting programs for multiprocessors, since programmers could do nothing and yet their sequential programs would run faster on new computers. Check Yourself
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Why is it difficult to write parallel processing programs that are fast, especially as the number of processors increases? In Chapter 1, we used the analogy of eight reporters trying to write a single story in hopes of doing the work eight times faster. To succeed, the task must be broken into eight equal-sized pieces, because otherwise some reporters would be idle while waiting for the ones with larger pieces to finish. Another per­formance danger would be that the reporters would spend too much time communicat­ing with each other instead of writing their pieces of the story. For both this analogy and parallel programming, the challenges include scheduling, load bal­ancing, time for synchronization, and overhead for communication between the parties. The challenge is stiffer with the more reporters for a newspaper story and the more processors for parallel programming. Our discussion in Chapter 1 reveals another obstacle, namely Amdahl’s law. It reminds us that even small parts of a program must be parallelized if the program is to make good use of many cores. Speed-up Challenge Suppose you want to achieve a speed-up of 90 times faster with 100 processors. What per­centage of the original computation can be sequential? Amdahl’s law (Chapter 1) says Execution time after improvement = ​ Execution time affected by improvement  Amount of improvement ​ + Execution time unaffected We can reformulate Amdahl’s in terms of speed-up versus the original execu­ tion time: EXAMPLE ANSWER Speed-up = ​ Execution time before ________________________________________________________________ (Execution time before - Execution time affected) + ​ Execution time affected  100 ​ ​ This formula is usually rewritten assuming that the execution time before is 1 for some unit of time, and the execution time affected by improvement is considered the fraction of the original execution time: Speed-up = ​ 1 __________________________________________ (1 − Fraction time affected) + ​ Fraction time affected __________________ 100 ​ ​ 7.2 The Difficulty of Creating Parallel Processing Programs 635
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636 Chapter 7 Multicores, Multiprocessors, and Clusters Substituting for the goal of a speed-up of 90 into the formula above: 90 = ​ 1 _____________________________________ (1 − Fraction time affected) + ​ Fraction time affected  100 ​ ​ Then simplifying the formula and solving for fraction time affected: 90 × (1 – 0.99 × Fraction time affected) = 1 90 - (90 × 0.99 × Fraction time affected) = 1 90 - 1 = 90 × 0.99 × Fraction time affected Fraction time affected = 89/89.1 = 0.999 Thus, to achieve a speed-up of 90 from 100 processors, the sequential percent­ age can only be 0.1%. Yet, there are applications with substantial parallelism. Speed-up Challenge: Bigger Problem Suppose you want to perform two sums: one is a sum of 10 scalar variables, and one is a matrix sum of a pair of two-dimensional arrays, with dimensions 10 by 10. What speed-up do you get with 10 versus 100 processors? Next, cal­ culate the speed-ups assuming the matrices grow to 100 by 100. If we assume performance is a function of the time for an addition, t, then there are 10 additions that do not benefit from parallel processors and 100 ad­ditions that do. If the time for a single processor is 110 t, the execution time for 10 processors is Execution time after improvement = ​ Execution time affected by improvement _________________________________ Amount of improvement ​ + Execution time unaffected Execution time affected improvement = ​ 100t ____ 10 ​ + 10t = 20t so the speed-up with 10 processors is 110t/20t = 5.5. The execution time for 100 processors is Execution time after improvement = ​ 100t ____ 100 ​ + 10t = 11t so the speed-up with 100 processors is 110t/11t = 10. EXAMPLE ANSWER
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Thus, for this problem size, we get about 55% of the potential speed-up with 10 processors, but only 10% with 100. Look what happens when we increase the matrix. The sequential program now takes 10t + 10,000t = 10,010t. The execution time for 10 processors is Execution time after improvement = ​ 10,000t _______ 10 ​ + 10t = 1010t so the speed-up with 10 processors is 10,010t/1010t = 9.9. The execution time for 100 processors is Execution time after improvement = ​ 10,000t _______ 100 ​ + 10t = 110t so the speed-up with 100 processors is 10,010t/110t = 91. Thus, for this larger problem size, we get about 99% of the potential speed-up with 10 proces­sors and more than 90% with 100. These examples show that getting good speed-up on a multiprocessor while keeping the problem size fixed is harder than getting good speed-up by increasing the size of the problem. This allows us to introduce two terms that describe ways to scale up. Strong scaling means measuring speed-up while keeping the problem size fixed. Weak scaling means that the program size grows proportionally to the increase in the number of processors. Let’s assume that the size of the problem, M, is the working set in main memory, and we have P processors. Then the memory per pro­cessor for strong scaling is approximately M/P, and for weak scaling, it is approxi­mately M. Depending on the application, you can argue for either scaling approach. For example, the TPC-C debit-credit database benchmark (Chapter 6) requires that you scale up the number of customer accounts to achieve higher transactions per minute. The argument is that it’s nonsensical to think that a given customer base is sud­denly going to start using ATMs 100 times a day just because the bank gets a faster computer. Instead, if you’re going to demonstrate a system that can perform 100 times the numbers of transactions per minute, you should run the experiment with 100 times as many customers. This final example shows the importance of load balancing. Speed-up Challenge: Balancing Load To achieve the speed-up of 91 on the previous larger problem with 100 proces­ sors, we assumed the load was perfectly balanced. That is, each of the 100 processors had 1% of the work to do. Instead, show the impact on speed-up if one processor’s load is higher than all the rest. Calculate at 2% and 5%. strong scaling Speed-up achieved on a multi­ processor without increasing the size of the problem. weak scaling Speed-up achieved on a multi­ processor while increasing the size of the problem proportionally to the increase in the number of pro­cessors. EXAMPLE 7.2 The Difficulty of Creating Parallel Processing Programs 637
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638 Chapter 7 Multicores, Multiprocessors, and Clusters If one processor has 2% of the parallel load, then it must do 2% × 10,000 or 200 additions, and the other 99 will share the remaining 9800. Since they are operating simultaneously, we can just calculate the execution time as a maxi­mum Execution time after improvement = Max ​( ​ 9800t _____ 99 ​,​ 200t ____ 1 ​ )​ + 10t = 210t The speed-up drops to 10,010t/210t = 48. If one processor has 5% of the load, it must perform 500 additions: Execution time after improvement = Max ​( ​ 9500t _____ 99 ​,​ 500t ____ 1 ​ )​ + 10t = 510t The speed-up drops even further to 10,010t/510t = 20. This example dem­ onstrates the value of balancing load, for just a single processor with twice the load of the others cuts speed-up almost in half, and five times the load on one processor reduces the speed-up by almost a factor of five. True or false: Strong scaling is not bound by Amdahl’s law. 7.3 Shared Memory Multiprocessors Given the difficulty of rewriting old programs to run well on parallel hardware, a natural question is what computer designers can do to simplify the task. One answer was to provide a single physical address space that all processors can share, so that programs need not concern themselves with where they are run, merely that they may be executed in parallel. In this approach, all variables of a program can be made available at any time to any processor. The alternative is to have a separate address space per processor that requires that sharing must be explicit; we’ll describe this option in the next section. When the physical address space is common—which is usually the case for multicore chips—then the hardware typ­ically provides cache coherence to give a consistent view of the shared memory (see Section 5.8 of Chapter 5). A shared memory multiprocessor (SMP) is one that offers the programmer a single physical address space across all processors, although a more accurate term would have been shared-address multiprocessor. Note that such systems can still run independent jobs in their own virtual address spaces, even if they all share a physical address space. Processors communicate through shared variables in memory, with all processors capable of accessing any memory location via loads and stores. Figure 7.2 shows the classic organization of an SMP. Single address space multiprocessors come in two styles. The first takes about the same time to access main memory no matter which processor requests it and no matter which word is requested. Such machines are called uniform memory access (UMA) multiprocessors. In the second style, some memory accesses are ANSWER Check Yourself shared memory multiproces­sor (SMP) A parallel processor with a single address space, implying implicit communica­tion with loads and stores. uniform memory access (UMA) A multiprocessor in which accesses to main memory take about the same amount of time no matter which processor requests the access and no mat­ter which word is asked.
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much faster than others, depending on which ­processor asks for which word. Such machines are called nonuniform memory access ­(NUMA) multiprocessors. As you might expect, the programming chal­lenges are harder for a NUMA multi­processor than for a UMA multiprocessor, but NUMA machines can scale to larger sizes and NUMAs can have lower latency to nearby memory. As processors operating in parallel will normally share data, they also need to coordinate when operating on shared data; otherwise, one processor could start working on data before another is finished with it. This coordination is called syn­chronization. When sharing is supported with a single address space, there must be a separate mechanism for synchronization. One approach uses a lock for a shared variable. Only one processor at a time can acquire the lock, and other pro­cessors interested in shared data must wait until the original processor unlocks the variable. Section 2.11 of Chapter 2 describes the instructions for locking in MIPS. A Simple Parallel Processing Program for a Shared Address Space Suppose we want to sum 100,000 numbers on a shared memory multipro­ cessor computer with uniform memory access time. Let’s assume we have 100 processors. The first step again would be to split the set of numbers into subsets of the same size. We do not allocate the subsets to a different memory space, since there is a single memory space for this ma­chine; we just give different starting addresses to each processor. Pn is the number that identifies the processor, between 0 and 99. All processors start the pro­gram by running a loop that sums their subset of numbers: EXAMPLE ANSWER Processor Memory I/O Processor Processor Cache Cache Cache Interconnection Network . . . . . . FIGURE 7.2 Classic organization of a shared memory multiprocessor. nonuniform memory access (NUMA) A type of single address space multiprocessor in which some mem­ory accesses are much faster than others depending on which processor asks for which word. synchronization The process of coordinating the behavior of two or more processes, which may be running on different processors. lock A synchronization device that allows access to data to only one processor at a time. 7.3 Shared Memory Multiprocessors 639
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640 Chapter 7 Multicores, Multiprocessors, and Clusters sum[Pn] = 0; for (i = 1000*Pn; i < 1000*(Pn+1); i = i + 1) sum[Pn] = sum[Pn] + A[i]; /* sum the assigned areas*/ The next step is to add these many partial sums. This step is called a reduction. We divide to conquer. Half of the processors add pairs of partial sums, and then a quarter add pairs of the new partial sums, and so on until we have the single, final sum. Figure 7.3 illustrates the hierarchi­cal nature of this reduction. In this example, the two processors must synchronize before the ­“consumer” processor tries to read the result from the memory location written by the “producer” processor; otherwise, the consumer may read the old value of the data. We want each processor to have its own version of the loop counter variable i, so we must indicate that it is a “private” variable. Here is the code (half is private also): half = 100; /* 100 processors in multiprocessor*/ repeat synch(); /* wait for partial sum completion*/ if (half%2 != 0 && Pn == 0) sum[0] = sum[0] + sum[half-1]; /* Conditional sum needed when half is odd; Processor0 gets missing element */ half = half/2; /* dividing line on who sums */ if (Pn < half) sum[Pn] = sum[Pn] + sum[Pn+half]; until (half == 1); /* exit with final sum in Sum[0] */ True or false: Shared memory multiprocessors cannot take advantage of job- level parallelism. reduction A function that pro­cesses a data structure and returns a single value. Check Yourself 0 0 1 0 1 2 3 0 1 2 3 4 5 6 7 (half = 1) (half = 2) (half = 4) FIGURE 7.3 The last four levels of a reduction that sums results from each processor, from bottom to top. For all processors whose number i is less than half, add the sum produced by processor number (i + half) to its sum. Elaboration: An alternative to sharing the physical address space would be to have separate physical address spaces but share a common virtual address space, leaving it up to the operating system to handle communication. This approach has been tried, but it has too high an overhead to offer a practical shared memory abstraction to the programmer.
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7.4 Clusters and Other Message-Passing Multiprocessors The alternative approach to sharing an address space is for the processors to each have their own private physical address space. Figure 7.4 shows the classic organi­ zation of a multiprocessor with multiple private address spaces. This alternative multiprocessor must communicate via explicit message passing, which tradition­ ally is the name of such style of computers. Provided the system has routines to send and receive messages, coordination is built in with message passing, since one processor knows when a message is sent, and the receiving processor knows when a message arrives. If the sender needs confirmation that the message has arrived, the receiving processor can then send an acknowledgment message back to the sender. FIGURE 7.4 Classic organization of a multiprocessor with multiple private address spaces, traditionally called a message-passing multiprocessor. Note that unlike the SMP in Figure 7.2, the interconnection network is not between the caches and memory but is instead between pro­cessor-memory nodes. Cache Cache Cache Memory Memory Memory Interconnection Network . . . . . . Processor Processor Processor . . . Some concurrent applications run well on parallel hardware, independent of whether it offers shared addresses or message passing. In particular, job-level par­ allelism and applications with little communication—like Web search, mail serv­ ers, and file servers—do not require shared addressing to run well. There were several attempts to build high-performance computers based on high- performance message-passing networks, and they did offer better absolute commu­ nication performance than clusters built using local area networks. The problem was that they were much more expensive. Few applications could justify the higher communication performance, given the much higher costs. Hence, clusters have become the most widespread example today of the message-passing parallel com­ puter. Clusters are generally collections of commodity computers that are connected to each other over their I/O interconnect via standard network switches and cables. Each runs a distinct copy of the operating system. Virtually every Internet service relies on clusters of commodity servers and switches. message passing Communicating between ­multiple processors by explic­itly sending and receiving ­information. send message routine A routine used by a processor in machines with private memories to pass to another processor. receive message routine A routine used by a processor in machines with private memories to accept a message from another processor. clusters Collections of computers con­nected via I/O over standard network switches to form a mes­sage-passing multiprocessor. 7.4 Clusters and Other Message-Passing Multiprocessors 641
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642 Chapter 7 Multicores, Multiprocessors, and Clusters One drawback of clusters has been that the cost of administering a cluster of n machines is about the same as the cost of administering n independent machines, while the cost of administering a shared memory multiprocessor with n proces­sors is about the same as administering a single machine. This weakness is one of the reasons for the popularity of virtual machines (Chapter 5), since VMs make clusters easier to administer. For example, VMs make it possible to stop or start programs atomically, which simplifies software upgrades. VMs can even migrate a program from one computer in a cluster to another without stopping the program, allowing a program to migrate from fail­ing hardware. Another drawback to clusters is that the processors in a cluster are usually connected using the I/O interconnect of each computer, whereas the cores in a multiproces­sor are usually connected on the memory interconnect of the computer. The memory interconnect has higher bandwidth and lower latency, allowing much better communication performance. A final weakness is the overhead in the division of memory: a cluster of n machi­ nes has n independent memories and n copies of the operating system, but a shared memory multiprocessor allows a single program to use almost all the memory in the computer, and it only needs a single copy of the OS. Memory Efficiency Suppose a single shared memory processor has 20 GB of main memory, five clustered computers each have 4 GB, and the OS occupies 1 GB. How much more space is there for users with shared memory? The ratio of memory available for user programs on the shared memory computer versus the cluster would be ​ 20 − 1 _________ 5 × (4 − 1) ​ = ​ 19 ___ 15 ​ ≈ 1.25 so shared memory computers have about 25% more space. Let’s redo the summing example from the prior section to see the impact of multiple private memories and explicit communication. A Simple Parallel Processing Program for Message Passing Suppose we want to sum 100,000 numbers in a message-passing multi­processor with 100 processors, each with multiple private memories. EXAMPLE ANSWER EXAMPLE
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Since this computer has multiple address spaces, the first step is distributing the 100 subsets to each of the local memories. The processor containing the 100,000 numbers sends the subsets to each of the 100 processor-­memory nodes. The next step is to get the sum of each subset. This step is simply a loop that every processor follows: read a word from local memory and add it to a local variable: sum = 0; for (i = 0; i<1000; i = i + 1) /* loop over each array */ sum = sum + AN[i]; /* sum the local arrays */ The last step is the reduction that adds these 100 partial sums. The hard part is that each partial sum is located in a different processor. Hence, we must use the interconnection network to send partial sums to accumulate the final sum. Rather than sending all the partial sums to a single processor, which would result in sequentially adding the partial sums, we again divide to con­quer. First, half of the processors send their partial sums to the other half of the processors, where two partial sums are added together. Then one-quarter of the processors (half of the half) send this new partial sum to the other quarter of the processors (the remaining half of the half) for the next round of sums. This halving, sending, and receiving continue until there is a single sum of all numbers. Let Pn represent the number of the processor, send(x,y) be a rou­ tine that sends over the interconnection network to processor number x the value y, and ­receive() be a function that accepts a value from the network for this processor. Here is the code: limit = 100; half = 100;/* 100 processors */ repeat half = (half+1)/2; /* send vs. receive dividing line*/ if (Pn >= half && Pn < limit) send(Pn - half, sum); if (Pn < (limit/2)) sum = sum + receive(); limit = half; /* upper limit of senders */ until (half == 1); /* exit with final sum */ This code divides all processors into senders or receivers, and each ­receiving processor gets only one message, so we can presume that a ­receiving processor will stall until it receives a message. Thus, send and receive can be used as primitives for synchronization as well as for communication, as the processors are aware of the transmission of data. If there is an odd number of nodes, the middle node does not participate in send/receive. The limit is then set so that this node is the highest node in the next iteration. ANSWER 7.4 Clusters and Other Message-Passing Multiprocessors 643
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644 Chapter 7 Multicores, Multiprocessors, and Clusters Elaboration: This example assumes implicitly that message passing is about as fast as addi­tion. In reality, message sending and receiving is much slower. An optimization to better bal­ance computation and communication might be to have fewer nodes receive many sums from other processors. Computers that rely on message passing for communication rather than cache- coherent shared memory are much easier for hardware designers (see Section 5.8 of Chapter 5). The advantage for programmers is that communication is explicit, which means there are fewer performance surprises than with the implicit com­ munication in cache-coherent shared memory computers. The downside for pro­ grammers is that it’s harder to port a sequential program to a message-passing computer, since every communication must be identified in advance or the pro­ gram doesn’t work. Cache-coherent shared memory allows the hardware to figure out what data needs to be communicated, which makes porting easier. There are differences of opinion as to which is the shortest path to high performance, given the pros and cons of implicit communication. A weakness of separate memories for user memory turns into a strength in sys­tem availability. Since a cluster consists of independent computers connected through a local area network, it is much easier to replace a machine without bringing down the system in a cluster than in an SMP. Fundamentally, the shared address means that it is difficult to isolate a processor and replace a processor without heroic work by the operating system. Since the cluster software is a layer that runs on top of local operating ­systems running on each computer, it is much easier to disconnect and replace a broken machine. Given that clusters are constructed from whole computers and independent, scalable networks, this isolation also makes it easier to expand the system without bringing down the application that runs on top of the cluster. Lower cost, high availability, improved power efficiency, and rapid, incremen­tal expandability make clusters attractive to service providers for the World Wide Web. The search engines that millions of us use every day depend upon this tech­nology. eBay, Google, Microsoft, Yahoo, and others all have multiple datacenters each with clusters of tens of thousands of processors. Clearly, the use of multiple processors in Internet service companies has been hugely successful. Elaboration: Another form of large scale computing is grid computing, where the comput­ ers are spread across large areas, and then the programs that run across them must communicate via long haul networks. The most popular and unique form of grid computing was pioneered by the SETI@home project. It was observed that millions of PCs are idle at any one time doing nothing useful, and they could be harvested and put to good uses Hardware/ Software Interface
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if someone developed software that could run on those computers and then gave each PC an independent piece of the problem to work on. The first example was the Search for ExtraTerrestrial Intelligence (SETI). Over 5 million computer users in more than 200 countries have signed up for SETI@home and have collectively contributed over 19 billion hours of computer processing time. By the end of 2006, the SETI@home grid operated at 257 TeraFLOPS. 1. True or false: Like SMPs, message-passing computers rely on locks for synchronization. 2. True or false: Unlike SMPs, message-passing computers need multiple copies of the parallel processing program and the operating system. 7.5 Hardware Multithreading Hardware multithreading allows multiple threads to share the functional units of a single processor in an overlapping fashion. To permit this sharing, the processor must duplicate the independent state of each thread. For example, each thread would have a separate copy of the register file and the PC. The memory itself can be shared through the virtual memory mechanisms, which already support multi­ programming. In addition, the hardware must support the ability to change to a different thread relatively quickly. In particular, a thread switch should be much more efficient than a process switch, which typically requires hundreds to thou­ sands of processor cycles while a thread switch can be instantaneous. There are two main approaches to hardware multithreading. Fine-grained ­multithreading switches between threads on each instruction, resulting in inter­ leaved execution of multiple threads. This interleaving is often done in a round- robin fashion, skipping any threads that are stalled at that time. To make fine-grained multithreading practical, the processor must be able to switch threads on every clock cycle. One key advantage of fine-grained multithreading is that it can hide the throughput losses that arise from both short and long stalls, since instructions from other threads can be executed when one thread stalls. The primary disadvan­ tage of fine-grained multithreading is that it slows down the execu­tion of the indi­ vidual threads, since a thread that is ready to execute without stalls will be delayed by instructions from other threads. Coarse-grained multithreading was invented as an alternative to fine-grained multithreading. Coarse-grained multithreading switches threads only on costly stalls, such as second-level cache misses. This change relieves the need to have thread switching be essentially free and is much less likely to slow down the execu­ tion of an individual thread, since instructions from other threads will only be issued when a thread encounters a costly stall. Coarse-grained multithreading suf­fers, however, from a major drawback: it is limited in its ability to overcome Check Yourself hardware multithreading Increasing utilization of a pro­cessor by switching to another thread when one thread is stalled. fine-grained multithreading A version of hardware multi­threading that suggests switch­ing between threads after every instruction. coarse-grained multithread­ing A version of hardware multi­threading that suggests switch­ing between threads only after significant events, such as a cache miss. 7.5 Hardware Multithreading 645
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646 Chapter 7 Multicores, Multiprocessors, and Clusters throughput losses, especially from shorter stalls. This limitation arises from the pipeline start-up costs of coarse-grained multithreading. Because a processor with coarse-grained multithreading issues instructions from a single thread, when a stall occurs, the pipeline must be emptied or frozen. The new thread that begins executing after the stall must fill the pipeline before instructions will be able to complete. Due to this start-up overhead, coarse-grained multithreading is much more useful for reducing the penalty of high-cost stalls, where pipeline refill is negligible compared to the stall time. Simultaneous multithreading (SMT) is a variation on hardware multithread­ ing that uses the resources of a multiple-issue, dynamically scheduled processor to exploit thread-level parallelism at the same time it exploits instruction-level paral­lelism. The key insight that motivates SMT is that multiple-issue processors often have more functional unit parallelism available than a single thread can effec­ tively use. Furthermore, with register renaming and dynamic scheduling, multiple instructions from independent threads can be issued without regard to the depen­ dences among them; the resolution of the dependences can be handled by the dynamic scheduling capability. Since you are relying on the existing dynamic mechanisms, SMT does not switch resources every cycle. Instead, SMT is always executing instructions from multiple threads, leaving it up to the hardware to associate instruction slots and renamed registers with their proper threads. Figure 7.5 conceptually illustrates the differences in a processor’s ability to exploit superscalar resources for the following processor configurations. The top portion shows how four threads would execute independently on a superscalar with no multithreading support. The bottom portion shows how the four threads could be combined to execute on the processor more efficiently using three multi­ threading options: ■ ■A superscalar with coarse-grained multithreading ■ ■A superscalar with fine-grained multithreading ■ ■A superscalar with simultaneous multithreading In the superscalar without hardware multithreading support, the use of issue slots is limited by a lack of instruction-level parallelism. In addition, a major stall, such as an instruction cache miss, can leave the entire processor idle. In the coarse-grained multithreaded superscalar, the long stalls are partially hidden by switching to another thread that uses the resources of the processor. Although this reduces the number of completely idle clock cycles, the pipeline start-up overhead still leads to idle cycles, and limitations to ILP means all issue slots will not be used. In the fine-grained case, the interleaving of threads mostly eliminates fully empty slots. Because only a single thread issues instructions in a given clock cycle, however, limitations in instruction-level parallelism still lead to idle slots within some clock cycles. simultaneous multithreading (SMT) A version of multi­ threading that lowers the cost of multithreading by utilizing the resources needed for multiple issue, dynamically schedule microarchitecture.
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In the SMT case, thread-level parallelism and instruction-level parallelism are both exploited, with multiple threads using the issue slots in a single clock cycle. Ideally, the issue slot usage is limited by imbalances in the resource needs and resource availability over multiple threads. In practice, other factors can restrict how many slots are used. Although Figure 7.5 greatly simplifies the real operation of these processors, it does illustrate the potential performance advantages of multithreading in general and SMT in particular. For example, the recent Intel Nehalem multicore supports SMT with two threads to improve core utilization. Let us conclude with three observations. First, from Chapter 1, we know that the power wall is forcing a design toward simpler and more power-efficient pro­cessors on a chip. It may well be that the under-utilized resources of out-of-order processors may be reduced, and so simpler forms of multithreading will be used. For example, the Sun UltraSPARC T2 (Niagara 2) microprocessor in Section 7.11 is an example of a return to simpler microarchitectures and hence the use of fine-grained multithreading. Issue slots Thread C Thread D Thread A Thread B Time Time SMT Coarse MT Fine MT Issue slots FIGURE 7.5 How four threads use the issue slots of a superscalar processor in different approaches. The four threads at the top show how each would execute running alone on a standard superscalar processor without multithreading support. The three examples at the bottom show how they would execute running together in three multithreading options. The horizontal dimension represents the instruction issue capability in each clock cycle. The vertical dimension represents a sequence of clock cycles. An empty (white) box indicates that the corresponding issue slot is unused in that clock cycle. The shades of gray and color correspond to four different threads in the multithreading processors. The additional pipe­line start-up effects for coarse multithreading, which are not illustrated in this figure, would lead to further loss in throughput for coarse multithreading. 7.5 Hardware Multithreading 647
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648 Chapter 7 Multicores, Multiprocessors, and Clusters Second, a key performance challenge is tolerating latency due to cache misses. Fine-grained computers like the UltraSPARC T2 switch to another thread on a miss, which is probably more effective in hiding memory latency than trying to fill unused issue slots as in SMT. A third observation is that the goal of hardware multithreading is to use hard­ware more efficiently by sharing components between different tasks. Multicore designs share resources as well. For example, two processors might share a ­float­ing-point unit or an L3 cache. Such sharing reduces some of the benefits of multi­threading compared with providing more non-multithreaded cores. 1. True or false: Both multithreading and multicore rely on parallelism to get more efficiency from a chip. 2. True or false: Simultaneous multithreading uses threads to improve resource utilization of a dynamically scheduled, out-of-order processor. 7.6 SISD, MIMD, SIMD, SPMD, and Vector Another categorization of parallel hardware proposed in the 1960s is still used today. It was based on the number of instruction streams and the number of data streams. Figure 7.6 shows the categories. Thus, a conventional uniprocessor has a single instruction stream and single data stream, and a conventional multiproces­ sor has multiple instruction streams and multiple data streams. These two cate­ gories are abbreviated SISD and MIMD, respectively. Data Streams Single Multiple Instruction Streams Single SISD: Intel Pentium 4 SIMD: SSE instructions of x86 Multiple MISD: No examples today MIMD: Intel Xeon e5345 (Clovertown) FIGURE 7.6 Hardware categorization and examples based on number of instruction streams and data streams: SISD, SIMD, MISD, and MIMD. While it is possible to write separate programs that run on different processors on a MIMD computer and yet work together for a grander, coordinated goal, pro­ grammers normally write a single program that runs on all processors of an MIMD computer, relying on conditional statements when different processors should execute different sections of code. This style is called Single Program Mul­tiple Data (SPMD), but it is just the normal way to program a MIMD computer. Check Yourself SISD or Single Instruction stream, Single Data stream. A uniprocessor. MIMD or Multiple Instruction streams, Multiple Data streams. A multiprocessor. SPMD Single Program, Multi­ple Data streams. The conven­tional MIMD programming model, where a single program runs across all processors.
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While it is hard to provide examples of useful computers that would be classi­fied as multiple instruction streams and single data stream (MISD), the inverse makes much more sense. SIMD computers operate on vectors of data. For exam­ple, a single SIMD instruction might add 64 numbers by sending 64 data streams to 64 ALUs to form 64 sums within a single clock cycle. The virtues of SIMD are that all the parallel execution units are synchronized and they all respond to a single instruction that emanates from a single program counter (PC). From a programmer’s perspective, this is close to the already famil­ iar SISD. Although every unit will be executing the same instruction, each execu­ tion unit has its own address registers, and so each unit can have different data addresses. Thus, in terms of Figure 7.1, a sequential application might be compiled to run on serial hardware organized as a SISD or in parallel hardware that was organized as an SIMD. The original motivation behind SIMD was to amortize the cost of the control unit over dozens of execution units. Another advantage is the reduced size of pro­ gram memory—SIMD needs only one copy of the code that is being simulta­neously executed, while message-passing MIMDs may need a copy in every processor, and shared memory MIMD will need multiple instruction caches. SIMD works best when dealing with arrays in for loops. Hence, for parallel­ ism to work in SIMD, there must be a great deal of identically structured data, which is called data-level parallelism. SIMD is at its weakest in case or switch state­ ments, where each execution unit must perform a different operation on its data, de­pending on what data it has. Execution units with the wrong data are disabled so that units with proper data may continue. Such sit­uations essentially run at 1/nth performance, where n is the num­ber of cases. The so-called array processors that inspired the SIMD category faded into his­ tory (see Section 7.14 on the CD), but two current interpretations of SIMD remain active today. SIMD in x86: Multimedia Extensions The most widely used variation of SIMD is found in almost every microproces­ sor today, and is the basis of the hundreds of MMX and SSE instructions of the x86 microprocessor (see Chapter 2). They were added to improve performance of multimedia programs. These instructions allow the hardware to have many ALUs operate simultaneously or, equivalently, to partition a single, wide ALU into many parallel smaller ALUs that operate simultaneously. For example, you could con­ sider a single hardware component to be one 64-bit ALU or two 32-bit ALUs or four 16-bit ALUs or eight 8-bit ALUs. Loads and stores are simply as wide as the widest ALU, so the programmer can think of the same data transfer instruction as transferring either a single 64-bit data element or two 32-bit data elements or four 16-bit data elements or eight 8-bit data elements. SIMD or Single Instruction stream, Multiple Data streams. A multiprocessor. The same instruction is applied to many data streams, as in a vector pro­ cessor or array processor. data-level parallelism Paral­lelism achieved by operating on independent data. 7.6 SISD, MIMD, SIMD, SPMD, and Vector 649
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650 Chapter 7 Multicores, Multiprocessors, and Clusters This very low cost parallelism for narrow integer data was the original inspira­tion of the MMX instructions of the x86. As Moore’s law continued, more hard­ware was added to these multimedia extensions, and now SSE2 supports the simultaneous execution of a pair of 64-bit floating-point numbers. The width of the operation and the registers is encoded in the opcode of these multimedia instructions. As the data width of the registers and operations grew, the number of opcodes for multimedia instructions exploded, and now there are hundreds of SSE instructions to perform the useful combinations (see Chapter 2). Vector An older and more elegant interpretation of SIMD is called a vector architec­ture, which has been closely identified with Cray Computers. It is again a great match to problems with lots of data-level parallelism. Rather than having 64 ALUs perform 64 additions simultaneously, like the old array processors, the vector architectures pipelined the ALU to get good performance at lower cost. The basic philosophy of vector architecture is to collect data elements from memory, put them in order into a large set of registers, operate on them sequentially in regis­ters, and then write the results back to memory. A key feature of vector architec­tures is a set of vector registers. Thus, a vector architecture might have 32 vector registers, each with 64 64-bit elements. Comparing Vector to Conventional Code Suppose we extend the MIPS instruction set architecture with vector instruc­ tions and vector registers. Vector operations use the same names as MIPS op­erations, but with the letter “V” appended. For example, addv.d adds two double-precision vectors. The vector instructions take as their input either a pair of vector registers (addv.d) or a vector register and a scalar register (addvs.d). In the latter case, the value in the scalar register is used as the in­put for all operations—the operation addvs.d will add the contents of a sca­lar register to each element in a vector register. The names lv and sv denote vector load and vector store, and they load or store an entire vector of dou­ble-precision data. One operand is the vector register to be loaded or stored; the other operand, which is a MIPS general-purpose register, is the starting address of the vector in memory. Given this short description, show the con­ventional MIPS code versus the vector MIPS code for Y = a × X + Y where X and Y are vectors of 64 double precision floating-point numbers, ini­tially resident in memory, and a is a scalar double precision variable. (This example is the so-called DAXPY loop that forms the inner loop of the Lin­pack benchmark; DAXPY stands for double precision a × X plus Y.). Assume that the starting addresses of X and Y are in $s0 and $s1, respectively. EXAMPLE
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Here is the conventional MIPS code for DAXPY: l.d $f0,a($sp) ;load scalar a addiu r4,$s0,#512 ;upper bound of what to load loop: l.d $f2,0($s0) ;load x(i) mul.d $f2,$f2,$f0 ;a × x(i) l.d $f4,0($s1) ;load y(i) add.d $f4,$f4,$f2 ;a × x(i) + y(i) s.d $f4,0($s1) ;store into y(i) addiu $s0,$s0,#8 ;increment index to x addiu $s1,$s1,#8 ;increment index to y subu $t0,r4,$s0 ;compute bound bne $t0,$zero,loop ;check if done Here is the vector MIPS code for DAXPY: l.d $f0,a($sp) ;load scalar a lv $v1,0($s0) ;load vector x mulvs.d $v2,$v1,$f0 ;vector-scalar multiply lv $v3,0($s1) ;load vector y addv.d $v4,$v2,$v3 ;add y to product sv $v4,0($s1) ;store the result There are some interesting comparisons between the two code segments in this example. The most dramatic is that the vector processor greatly reduces the dynamic instruction bandwidth, executing only six instructions versus almost 600 for MIPS. This reduction occurs both because the vector operations work on 64 elements and because the overhead instructions that constitute nearly half the loop on MIPS are not present in the vector code. As you might expect, this reduc­tion in instructions fetched and executed saves power. Another important difference is the frequency of pipeline hazards (Chapter 4). In the straightforward MIPS code, every add.d must wait for a mul.d, and every s.d must wait for the add.d. On the vector processor, each vector instruction will only stall for the first element in each vector, and then subsequent elements will flow smoothly down the pipeline. Thus, pipeline stalls are required only once per vector operation, rather than once per vector element. In this example, the pipeline stall frequency on MIPS will be about 64 times higher than it is on VMIPS. The pipeline stalls can be reduced on MIPS by using loop-unrolling (see Chapter 4). However, the large difference in instruction bandwidth cannot be reduced. ANSWER 7.6 SISD, MIMD, SIMD, SPMD, and Vector 651
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652 Chapter 7 Multicores, Multiprocessors, and Clusters Elaboration: The loop in the example above exactly matched the vector length. When loops are shorter, vector architectures use a register that reduces the length of vector operations. When loops are larger, we add bookkeeping code to iterate full-length vector operations and to handle the leftovers. This latter process is called strip mining. Vector versus Scalar Vector instructions have several important properties compared to conven­tional instruction set architectures, which are called scalar architectures in this context: ■ ■A single vector instruction specifies a great deal of work—it is equivalent to executing an entire loop. The instruction fetch and decode bandwidth needed is dramatically reduced. ■ ■By using a vector instruction, the compiler or programmer indicates that the computation of each result in the vector is independent of the computation of other results in the same vector, so hardware does not have to check for data hazards within a vector instruction. ■ ■Vector architectures and compilers have a reputation of making it much eas­ ier than MIMD multiprocessors to write efficient applications when they contain data-level parallelism. ■ ■Hardware need only check for data hazards between two vector ­instructions once per vector operand, not once for every element within the vectors. Reduced checking can save power as well. ■ ■Vector instructions that access memory have a known access pattern. If the vector’s elements are all adjacent, then fetching the vector from a set of heavily interleaved memory banks works very well. Thus, the cost of the latency to main memory is seen only once for the entire vector, rather than once for each word of the vector. ■ ■Because an entire loop is replaced by a vector instruction whose behavior is predetermined, control hazards that would normally arise from the loop branch are nonexistent. ■ ■The savings in instruction bandwidth and hazard checking plus the efficient use of memory bandwidth give vector architectures advantages in power and energy versus scalar architectures. For these reasons, vector operations can be made faster than a sequence of sca­ lar operations on the same number of data items, and designers are motivated to include vector units if the application domain can use them frequently.
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Vector versus Multimedia Extensions Like multimedia extensions found in the x86 SSE instructions, a vector instruc­tion specifies multiple operations. However, multimedia extensions typically specify a few operations while vector specifies dozens of operations. Unlike multi­media extensions, the number of elements in a vector operation is not in the opcode but in a separate register. This means different versions of the vector archi­tecture can be implemented with a different number of elements just by changing the contents of that register and hence retain binary compatibility. In contrast, a new large set of opcodes is added each time the “vector” length changes in the multimedia exten­ sion architecture of the x86. Also unlike multimedia extensions, the data transfers need not be contiguous. Vectors support both strided accesses, where the hardware loads every nth data element in memory, and indexed accesses, where hardware finds the addresses of the items to be loaded in a vector register. Like multimedia extensions, vector easily captures the flexibility in data widths, so it is easy to make an operation work on 32 64-bit data elements or 64 32-bit data elements or 128 16-bit data elements or 256 8-bit data elements. Generally, vector architectures are a very efficient way to execute data parallel processing programs; they are better matches to compiler technology than multi­ media extensions; and they are easier to evolve over time than the multimedia extensions to the x86 architecture. True or false: As exemplified in the x86, multimedia extensions can be thought of as a vector architecture with short vectors that supports only sequential vector data transfers. Elaboration: Given the advantages of vector, why aren’t they more popular outside high- performance computing? There were concerns about the larger state for vector registers increas­ing context switch time and the difficulty of handling page faults in vector loads and stores, and SIMD instructions achieved some of the benefits of vector instructions. However, recent announcements from Intel suggest that vectors will play a bigger role. Intel’s Advanced Vector Instructions (AVI), to arrive in 2010, will expand the width of the SSE registers from 128 bits to 256 bits immediately and allow eventual expansion to 1024 bits. This latter width is equivalent to 16 double-precision floating-point numbers. Whether there will be vector load and store instructions are unclear. In addition, Intel’s entry into the discrete GPU mar­ket for 2010—code named “Larrabee”—is reputed to have vector instructions. Elaboration: Another advantage of vector and multimedia extensions is that it is relatively easy to extend a scalar instruction set architecture with these instructions to improve perfor­mance of data parallel operations. Check Yourself 7.6 SISD, MIMD, SIMD, SPMD, and Vector 653
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654 Chapter 7 Multicores, Multiprocessors, and Clusters 7.7 Introduction to Graphics Processing Units A major justification for adding SIMD instructions to existing architectures was that many microprocessors were connected to graphics displays in PCs and work­ stations, so an increasing fraction of processing time was used for graphics. Hence, as Moore’s law increased the number of transistors available to micropro­cessors, it made sense to improve graphics processing. Just as Moore’s law allowed the CPU to improve graphics processing, it also enabled video graphics controller chips to add functions to accelerate 2D and 3D graphics. Moreover, at the very high end were expensive graphics cards typically from Silicon Graphics, that could be added to workstations, to enable the creation of photographic quality images. These high-end graphics cards were popular for creating computer-generated images that later found their way into television advertisements and then into movies. Thus, video graphics controllers had a target to shoot for as processing resources increased, much as supercomput­ers provided a rich resource of ideas for microprocessors to borrow in the quest for greater performance. A major driving force for improving graphics processing was the computer game industry, both on PCs and in dedicated game consoles such as the Sony PlayStation. The rapidly growing game market encouraged many companies to make increasing investments in developing faster graphics hardware, and this pos­itive feedback led graphics processing to improve at a faster rate than general-purpose processing in mainstream microprocessors. Given that the graphics and game community had different goals than the micro­processor development community, it evolved its own style of processing and terminology. As the graphics processors increased in power, they earned the name Graphics Processing Units or GPUs to distinguish themselves from CPUs. Here are some of the key characteristics as to how GPUs vary from CPUs: ■ ■GPUs are accelerators that supplement a CPU, so they do not need be able to perform all the tasks of a CPU. This role allows them to dedicate all their resources to graphics. It’s fine for GPUs to perform some tasks poorly or not at all, given that in a system with both a CPU and a GPU, the CPU can do them if needed. Thus, the CPU-GPU combination is one example of hetero­ geneous multiprocessing, where not all the processors are identical. (Another example is the IBM Cell architecture in Section 7.11, which was also designed to accelerate 2D and 3D graphics.) ■ ■The programming interfaces to GPUs are high-level application pro­ gramming interfaces (APIs), such as OpenGL and Microsoft’s DirectX, ­coupled with high-level graphics shading languages, such as NVIDIA’s C for ­Graphics (Cg) and Microsoft’s High Level Shader Language (HLSL).
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The language ­compilers target industry-standard intermediate languages instead of machine instructions. GPU driver software generates optimized GPU-­spe­cific machine instructions. While these APIs and languages evolve rapidly to embrace new GPU resources enabled by Moore’s law, the freedom from backward binary instruction compatibility enables GPU designers to explore new architectures without the fear that they will be saddled with implementing failed experiments forever. This environment leads to more rapid innovation in GPUs than in CPUs. ■ ■Graphics processing involves drawing vertices of 3D geometry primitives such as lines and triangles and shading or rendering pixel fragments of geo­ metric primitives. Video games, for example, draw 20 to 30 times as many pixels as vertices. ■ ■Each vertex can be drawn independently, and each pixel fragment can be rendered independently. To render millions of pixels per frame rapidly, the GPU evolved to execute many threads from vertex and pixel shader pro­grams in parallel. ■ ■The graphics data types are vertices, consisting of (x, y, z, w) coordinates, and pixels, consisting of (red, green, blue, alpha) color components. (See Appendix A to learn more about vertices and pixels.) GPUs represent each vertex component as a 32-bit floating-point number. Each of the four pixel components was originally an 8-bit unsigned integer, but recent GPUs now represent each component as single-precision floating-point number between 0.0 and 1.0. ■ ■The working set can be hundreds of megabytes, and it does not show the same temporal locality as data does in mainstream applications. Moreover, there is a great deal of data-level parallelism in these tasks. These differences led to different styles of architecture: ■ ■Perhaps the biggest difference is that GPUs do not rely on multilevel caches to overcome the long latency to memory, as do CPUs. Instead, GPUs rely on having enough threads to hide the latency to memory. That is, between the time of a memory request and the time that data arrives, the GPU executes hundreds or thousands of threads that are independent of that request. ■ ■GPUs rely on extensive parallelism to obtain high performance, implement­ ing many parallel processors and many concurrent threads. ■ ■The GPU main memory is thus oriented toward bandwidth rather than latency. There are even separate DRAM chips for GPUs that are wider and have higher bandwidth than DRAM chips for CPUs. In addition, GPU memories have traditionally had smaller main memories than conventional microprocessors. In 2008, GPUs typically have 1 GB or less, while CPUs have 7.7 Introduction to Graphics Processing Units 655
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656 Chapter 7 Multicores, Multiprocessors, and Clusters 2 to 32 GB. Finally, keep in mind that for general-purpose compu­tation, you must include the time to transfer the data between CPU memory and GPU memory, since the GPU is a coprocessor. ■ ■Given the reliance on many threads to deliver good memory bandwidth, GPUs can accommodate many parallel processors as well as many threads. Hence, each GPU processor is highly multithreaded. ■ ■In the past, GPUs relied on heterogeneous special purpose processors to deliver the performance needed for graphics applications. Recent GPUs are heading toward identical general-purpose processors to give more flexibil­ ity in programming, making them more like the multicore designs found in mainstream computing. ■ ■Given the four-element nature of the graphics data types, GPUs historically have SIMD instructions, like CPUs. However, recent GPUs are focusing more on scalar instructions to improve programmability and efficiency. ■ ■Unlike CPUs, there has been no support for double precision floating-point arithmetic, since there has been no need for it in the graphics applications. In 2008, the first GPUs to support double precision in hardware were announced. Nevertheless, single precision operations will still be eight to ten times faster than double precision, even on these new GPUs, while the differ­ ence in performance for CPUs is limited to benefits in transferring fewer bytes in the memory system due to using narrow data. Although GPUs were designed for a narrower set of applications, some pro­ grammers wondered if they could specify their applications in a form that would let them tap the high potential performance of GPUs. To distinguish this style of using GPUs, some called it General Purpose GPUs or GPGPUs. After tiring of try­ ing to specify their problems using the graphics APIs and graphics shading lan­ guages, they developed C-inspired programming languages to allow them to write programs directly for the GPUs. An example is Brook, a streaming language for GPUs. The next step in programmability of both the hardware and the program­ ming language is NVIDIA’s CUDA (Compute Unified Device Architecture), which enables the programmer to write C programs to execute on GPUs, albeit with some restrictions. The use of GPUs for parallel computing is growing with their increasing programmability. An Introduction to the NVIDIA GPU Architecture Appendix A goes into much more depth on GPUs and presents in detail the most recent NVIDIA GPU architecture, called Tesla. Since GPUs evolved in their own environment, they not only have different architectures, as suggested above, but they also have a different set of terms. Once you learn the GPU terms, you will
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see the similarities to approaches presented in prior sections, such as fine-grained multithreading and vectors. To help you with that transition to the new vocabulary, we present a quick introduction to the terms and ideas in the Tesla GPU architecture and the CUDA programming environment. A discrete GPU chip sits on a separate card that plugs into a standard PC over the PCI-Express interconnect. So-called motherboard GPUs are integrated into the motherboard chip set, such as a north bridge or a south bridge (Chapter 6). GPUs are generally offered as a family of chips at different price performance points, with all being software compatible. Tesla-based GPUs chips are offered with between 1 and 16 nodes, which NVIDIA calls multiprocessors. In early 2008, the largest version is called the GeForce 8800 GTX, which has 16 multiprocessors and a clock rate of 1.35 GHz. Each multiprocessor contains eight multithreaded sin­gle-precision floating- point units and integer processing units, which NVIDIA calls streaming processors. Since the architecture includes a single-precision floating-point multiply-add instruction, the peak single precision multiply-add performance of the 8800 GTX chip is: 16 MPs × ​ 8 SPs _____ MP ​ × ​ 2 FLOPs/instr ____________ SP ​ × ​ 1 instr ______ clock ​ × ​ 1.35 × 109 clocks ______________ second ​ = ​ 16 × 8 × 2 × 1.35 GFLOPs _____________________ second ​ = ​ 345.6 GFLOPs ____________ second ​ Each of the 16 multiprocessors of the GeForce 8800 GTX has a software-man­aged local store with a capacity of 16 KB plus 8192 32-bit registers. The memory system of the 8800 GTX consists of six partitions of 900 MHz Graphics DDR3 DRAM, each 8 bytes wide and with 128 MB of capacity. The total memory size is thus 768 MB. The peak GDDR3 memory bandwidth is 6 × ​ 8 Bytes _______ transfer ​ × ​ 2 transfers _________ clock ​ × ​ 0.9 × 109 clocks _____________ second ​ = ​ 6 × 8 × 2 × 0.9GB _______________ second ​ = ​ 86.4 GB _______ second ​ To hide memory latency, each streaming processor has hardware-supported threads. Each group of 32 threads is called a warp. A warp is the unit of schedul­ ing, and the active threads in a warp—up to 32—execute in parallel in SIMD fash­ ion. The multithreaded architecture copes with conditions, however, by allowing threads to take different branch paths. When threads of a warp take diverging paths, the warp sequentially ­executes both code paths with some inactive threads, which makes the active threads run more slowly. The hardware joins the threads back into a fully active warp as soon as the conditional paths are completed. To get the best performance, all 32 threads of a warp need to ­execute together in parallel. In simi­ lar style, the hardware also looks at the ­address streams coming from the dif­ferent threads to try to merge the individual ­requests into fewer but larger mem­ory block transfers to increase memory performance. 7.7 Introduction to Graphics Processing Units 657
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658 Chapter 7 Multicores, Multiprocessors, and Clusters Figure 7.7 combines all these features together and compares a Tesla multiprocessor to a Sun UltraSPARC T2 core, which is described in Sections 7.5 and 7.11. Both are hardware multithreaded by scheduling threads over time, shown on the vertical axis. Each Tesla multiprocessor consists of eight streaming processors, which execute eight parallel threads per clock showing horizontally. As mentioned above, the best performance comes when all 32 threads of a warp execute together in a SIMD-like fashion, which the Tesla architecture calls single-instruc­tion multiple-thread (SIMT). SIMT dynamically discovers which threads of a warp can execute the same instruction together, and which independent threads are idle that cycle. The T2 core contains just a single mul­tithreaded processor. Each cycle it executes one instruction for one thread. The Tesla multiprocessor uses fine-grained hardware multithreading to sched­ ule 24 warps over time, which are shown vertically in blocks of four clock cycles. Similarly, the UltraSPARC T2 schedules eight hardware-sup­ported threads over time, one thread per cycle, shown vertically. Thus, just as the T2 hardware switches between threads to keep the T2 core busy, the Tesla hardware switches between warps to keep the Tesla multiprocessor busy. The major difference is that the T2 core has one processor that can switch threads every clock cycle, while the minimum unit of switching warps in the Tesla microprocessor is two clock cycles across eight streaming cores. Since Tesla is aimed at programs with a great deal of data-level parallelism, the designers believed there is little perfor­mance difference between FIGURE 7.7 Comparing single core of a Sun UltraSPARC T2 (Niagara 2) to a single Tesla multi- processor. The T2 core is a single processor and uses hardware multithreading with eight threads (although there are some restrictions scheduling threads to pipelines). The Tesla multiprocessor contains eight streaming proces­ sors and uses hardware-supported ­multithreading with 24 warps of 32 threads (eight processors times four clock cycles). The T2 can switch every clock cycle, while the Tesla can switch only every two or four clock cycles. One way to compare the two is that the T2 can only multithread the processor over time, while Tesla can multithread over time and over space; that is, across the eight streaming processors as well as segments of four clock cycles. Processors UltraSPARC T2 ... Hardware Supported Threads Thread0 Thread1 Thread2 Thread3 Thread4 Thread5 Thread6 Thread7 Tesla Multiprocessor Warp0 Warp1 Warp23
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switching every two or four clock cycles versus every clock cycle, and the hardware was much simpler by restricting the frequency of switching. The CUDA programming environment has its own terminology as well. A CUDA program is a unified C/C++ program for a heterogeneous CPU and GPU system. It executes on the CPU and dispatches parallel work to the GPU. This work consists of a data transfer from main memory and a thread dispatch. A thread is a piece of the program for the GPU. Programmers specify the number of threads in a thread block, and the number of thread blocks they wish to start exe­cuting on the GPU. The reason the programmers care about thread blocks is that all the threads in the thread block are scheduled to run on the same multiprocessor so they all share the same local memory. Thus, they can communicate via loads and stores instead of messages. The CUDA compiler allocates registers to each thread, under the constraint that the registers per thread times threads per thread block does not exceed the 8192 registers per multiprocessor. A thread block can be up to 512 threads. Each group of 32 threads in a thread block is packed into warps. Large thread blocks have better efficiency than small ones, and they can be as small as a single thread. As mentioned above, thread blocks and warps with fewer than 32 threads operate less efficiently than full ones. A hardware scheduler tries to schedule multiple thread blocks per multiproces­ sor when possible. If it does, the scheduler also partitions the 16 KB local store dynamically between the different thread blocks. Putting GPUs into Perspective GPUs like the NVIDIA Tesla architecture do not fit neatly into prior classifications of computers, such Figure 7.6 on page 648. Clearly, the GeForce 8800 GTX, with 16 Tesla multiprocessors, is an MIMD. The question is how to classify each of the Tesla multiprocessors and the eight streaming processors that make up a Tesla multiproces­sor. Recall that we earlier said that SIMD was at its best with for loops and was at its weakest in case and switch statements. Tesla aims at the high performance for data- level parallelism while making it easy for programmers to deal with independent thread-level parallel cases. Tesla allows the programmer to think the multiprocessor is a multithreaded MIMD of eight streaming processors, but the hardware tries to gang together the eight stream­ing processors to act in SIMT fashion when multi­ ple threads of the same warp can execute together. When the threads do operate independently and follow an independent execution path, they execute more slowly than in SIMT fashion, for all 32 threads of a warp share a single instruction fetch unit. If all 32 threads of a warp were executing independent instructions, each thread would operate at 1/16th the peak perfor­mance of a full warp of 32 threads executing on eight streaming processors over four clocks. Thus, each independent thread has its own effective PC, so programmers can think of the Tesla multiproces­sor as MIMD, but programmers need to take care to write control flow statements that allow the SIMT hardware to execute CUDA programs in SIMD fashion to deliver the desired performance. 7.7 Introduction to Graphics Processing Units 659
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660 Chapter 7 Multicores, Multiprocessors, and Clusters In contrast to vector architectures, which rely on a vectorizing compiler to recognize data-level parallelism at compile time and generate vector instructions, hardware implementations of Tesla architecture discovers data-level parallelism among threads at runtime. Thus, Tesla GPUs do not need vectorizing compilers, and they make it easier for the programmer to handle the portions of the program that do not have data-level parallelism. To put this unique approach into perspective, Figure 7.8 places GPUs in a classification that looks at instruction-level parallelism versus data-level parallelism and whether it is discovered at compile time or runtime. This categori­zation is one indication that the Tesla GPU is breaking new ground in computer architecture. Static: Discovered at Compile Time Dynamic: Discovered at Runtime Instruction­Level Parallelism VLIW Superscalar Data­Level Parallelism SIMD or Vector Tesla Multiprocessor FIGURE 7.8 Hardware categorization of processor architectures and examples based on static versus dynamic and ILP versus DLP. True or false: GPUs rely on graphics DRAM chips to reduce memory latency and thereby increase performance on graphics applications. 7.8 Introduction to Multiprocessor Network Topologies Multicore chips require networks on chips to connect cores together. This sec­tion reviews the pros and cons of different multiprocessor networks. Network costs include the number of switches, the number of links on a switch to connect to the network, the width (number of bits) per link, and length of the links when the network is mapped into chip. For example, some cores may be adjacent and others may be on the other side of the chip. Network performance is multifaceted as well. It includes the latency on an unloaded net­work to send and receive a message, the throughput in terms of the maximum number of messages that can be transmitted in a given time period, delays caused by contention for a portion of the network, and variable performance depending on the pattern of communication. Another obligation of the network may be fault tolerance, since systems may be required to operate in the presence of broken components. Finally, in this era of power-limited chips, the power efficiency of different organizations may trump other concerns. Networks are normally drawn as graphs, with each arc of the graph represent­ing a link of the communication network. The processor-memory node is shown as a Check Yourself
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black square, and the switch is shown as a colored circle. In this section, all links are bidirectional; that is, information can flow in either direction. All net­works consist of switches whose links go to processor-memory nodes and to other switches. The first improvement over a bus is a network that connects a sequence of nodes together: This topology is called a ring. Since some nodes are not directly connected, some messages will have to hop along intermediate nodes until they arrive at the final destination. Unlike a bus, a ring is capable of many simultaneous transfers. Because there are numerous topologies to choose from, performance metrics are needed to dis­ tinguish these designs. Two are popular. The first is total network bandwidth, which is the bandwidth of each link multiplied by the number of links. This repre­ sents the very best case. For the ring network above, with P processors, the total network bandwidth would be P times the bandwidth of one link; the total net­work bandwidth of a bus is just the bandwidth of that bus, or two times the band­width of that link. To balance this best case, we include another metric that is closer to the worst case: the bisection bandwidth. This is calculated by dividing the machine into two parts, each with half the nodes. Then you sum the bandwidth of the links that cross that imaginary dividing line. The bisection bandwidth of a ring is two times the link bandwidth, and it is one times the link bandwidth for the bus. If a single link is as fast as the bus, the ring is only twice as fast as a bus in the worst case, but it is P times faster in the best case. Since some network topologies are not symmetric, the question arises of where to draw the imaginary line when bisecting the machine. This is a worst-case met­ ric, so the answer is to choose the division that yields the most pessimistic net­work performance. Stated alternatively, calculate all possible bisection bandwidths and pick the smallest. We take this pessimistic view because parallel programs are often limited by the weakest link in the communication chain. At the other extreme from a ring is a fully connected network, where every processor has a bidirectional link to every other processor. For fully connected networks, the total network bandwidth is P × (P - 1)/2, and the bisection band­ width is (P/2)2. The tremendous improvement in performance of fully connected networks is offset by the tremendous increase in cost. This inspires engineers to invent new topologies that are between the cost of rings and the performance of fully con­ nected networks. The evaluation of success depends in large part on the nature of the communication in the workload of parallel programs run on the machine. The number of different topologies that have been discussed in publications would be difficult to count, but only a handful have been used in commercial parallel processors. Figure 7.9 illustrates two of the popular topologies. Real machines bisection bandwidth The bandwidth between two equal parts of a multiprocessor. This measure is for a worst case split of the multiprocessor. fully connected network A network that connects ­processor-memory nodes by supplying a dedicated commu­nication link between every node. 7.8 Introduction to Multiprocessor Network Topologies 661 network bandwidth Infor­mally, the peak transfer rate of a network; can refer to the speed of a single link or the collective transfer rate of all links in the network.
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662 Chapter 7 Multicores, Multiprocessors, and Clusters frequently add extra links to these simple topologies to improve performance and reliability. An alternative to placing a processor at every node in a network is to leave only the switch at some of these nodes. The switches are smaller than processor­- ­memory-switch nodes, and thus may be packed more densely, thereby lessening distance and increasing performance. Such networks are frequently called multi­stage networks to reflect the multiple steps that a message may travel. Types of multistage networks are as numerous as single-stage networks; Figure 7.10 illustrates two of the popular multistage organizations. A fully connected or crossbar network allows any node to communicate with any other node in one pass through the network. An Omega network uses less hardware than the crossbar net­work (2n log2 n versus n2 switches), but contention can occur between messages, depending on the pattern of communication. For example, the Omega network in Figure 7.10 cannot send a message from P0 to P6 at the same time that it sends a mes­sage from P1 to P7. Implementing Network Topologies This simple analysis of all the networks in this section ignores important practical considerations in the construction of a network. The distance of each link affects the cost of communicating at a high clock rate—generally, the longer the distance, the more expensive it is to run at a high clock rate. Shorter distances also make multistage network A network that supplies a small switch at each node. fully connected network A network that connects ­processor-memory nodes by supplying a dedicated commu­nication link between every node. crossbar network A network that allows any node to commu­nicate with any other node in one pass through the network. FIGURE 7.9 Network topologies that have appeared in commercial parallel proces­sors. The colored circles represent switches and the black squares represent processor-memory nodes. Even though a switch has many links, generally only one goes to the processor. The Boolean n-cube topology is an n-dimensional interconnect with 2n nodes, requiring n links per switch (plus one for the processor) and thus n nearest-neighbor nodes. Frequently, these basic topologies have been supplemented with extra arcs to improve performance and reliability. a. 2-D grid or mesh of 16 nodes b. n-cube tree of 8 nodes (8 = 23 so n = 3)
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it easier to assign more wires to the link, as the power to drive many wires from a chip is less if the wires are short. Shorter wires are also cheaper than longer wires. Another practical limitation is that the three-dimensional drawings must be mapped onto chips that are essentially two-dimensional media. The final concern is power. Power concerns may force multicore chips to rely on simple grid topolo­gies, for example. The bottom line is that topologies that appear elegant when sketched on the blackboard may be impractical when constructed in silicon. FIGURE 7.10 Popular multistage network topologies for eight nodes. The switches in these drawings are simpler than in earlier drawings because the links are unidirectional; data comes in at the ­ bot­tom and exits out the right link. The switch box in c can pass A to C and B to D or B to C and A to D. The crossbar uses n2 switches, where n is the number of processors, while the Omega network uses 2n log2n of the large switch boxes, each of which is logically composed of four of the smaller switches. In this case, the crossbar uses 64 switches versus 12 switch boxes, or 48 switches, in the Omega network. The crossbar, how­ever, can support any combination of messages between processors, while the Omega network cannot. a. Crossbar b. Omega network c. Omega network switch box C D A B P0 P1 P2 P3 P4 P5 P6 P7 P0 P1 P2 P3 P4 P5 P6 P7 7.8 Introduction to Multiprocessor Network Topologies 663
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664 Chapter 7 Multicores, Multiprocessors, and Clusters 7.9 Multiprocessor Benchmarks As we saw in Chapter 1, benchmarking systems is always a sensitive topic, because it is a highly visible way to try to determine which system is better. The results affect not only the sales of commercial systems, but also the reputation of the designers of those systems. Hence, the participants want to win the competition, but they also want to be sure that if someone else wins, they deserve to win because they have a genuinely better system. This desire leads to rules to ensure that the benchmark results are not simply engineering tricks for that benchmark, but are instead advances that improve performance of real applications. To avoid possible tricks, a typical rule is that you can’t change the benchmark. The source code and data sets are fixed, and there is a single proper answer. Any deviation from those rules makes the results invalid. Many multiprocessor benchmarks follow these traditions. A common excep­tion is to be able to increase the size of the problem so that you can run the benchmark on systems with a widely different number of processors. That is, many bench­ marks allow weak scaling rather than require strong scaling, even though you must take care when comparing results for programs running different prob­lem sizes. Figure 7.11 is a summary of several parallel benchmarks, also described below: ■ ■Linpack is a collection of linear algebra routines, and the routines for per­ forming Gaussian elimination constitute what is known as the Linpack benchmark. The DAXPY routine in the example on page 650 represents a small fraction of the source code of the Linpack benchmark, but it accounts for most of the execution time for the benchmark. It allows weak scaling, letting the user pick any size problem. Moreover, it allows the user to rewrite Linpack in any form and in any language, as long as it computes the proper result. Twice a year, the 500 computers with the fastest Linpack performance are published at www.top500.org. The first on this list is considered by the press to be the world’s fastest computer. ■ ■SPECrate is a throughput metric based on the SPEC CPU benchmarks, such as SPEC CPU 2006 (see Chapter 1). Rather than report performance of the individual programs, SPECrate runs many copies of the program simulta­ neously. Thus, it measures job-level parallelism, as there is no communica­ tion between the jobs. You can run as many copies of the programs as you want, so this is again a form of weak scaling. ■ ■SPLASH and SPLASH 2 (Stanford Parallel Applications for Shared Memory) were efforts by researchers at Stanford University in the 1990s to put together
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Benchmark Scaling? Reprogram? Description Linpack Weak Yes Dense matrix linear algebra [Dongarra, 1979] SPECrate Weak No Independent job parallelism [Henning, 2007] Stanford Parallel Applications for Shared Memory SPLASH 2 [Woo et al., 1995] Strong (although offers two problem sizes) No Complex 1D FFT Blocked LU Decomposition Blocked Sparse Cholesky Factorization Integer Radix Sort Barnes­Hut Adaptive Fast Multipole Ocean Simulation Hierarchical Radiosity Ray Tracer Volume Renderer Water Simulation with Spatial Data Structure Water Simulation without Spatial Data Structure NAS Parallel Benchmarks [Bailey et al., 1991] Weak Yes (C or Fortran only) EP: embarrassingly parallel MG: simplified multigrid CG: unstructured grid for a conjugate gradient method FT: 3­D partial differential equation solution using FFTs IS: large integer sort PARSEC Benchmark Suite [Bienia et al., 2008] Weak No Blackscholes—Option pricing with Black­Scholes PDE Bodytrack—Body tracking of a person Canneal—Simulated cache­aware annealing to optimize routing Dedup—Next­generation compression with data deduplication Facesim—Simulates the motions of a human face Ferret—Content similarity search server Fluidanimate—Fluid dynamics for animation with SPH method Freqmine—Frequent itemset mining Streamcluster—Online clustering of an input stream Swaptions—Pricing of a portfolio of swaptions Vips—Image processing x264—H.264 video encoding Berkeley Design Patterns [Asanovic et al., 2006] Strong or Weak Yes Finite­State Machine Combinational Logic Graph Traversal Structured Grid Dense Matrix Sparse Matrix Spectral Methods (FFT) Dynamic Programming N­Body MapReduce Backtrack/Branch and Bound Graphical Model Inference Unstructured Grid 7.9 Multiprocessor Benchmarks 665 FIGURE 7.11 Examples of parallel benchmarks.
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666 Chapter 7 Multicores, Multiprocessors, and Clusters a parallel benchmark suite similar in goals to the SPEC CPU benchmark suite. It includes both kernels and applications, including many from the high-performance computing community. This benchmark requires strong scaling, although it comes with two data sets. ■ ■The NAS (NASA Advanced Supercomputing) parallel benchmarks were another attempt from the 1990s to benchmark multiprocessors. Taken from computational fluid dynamics, they consist of five kernels. They allow weak scaling by defining a few data sets. Like Linpack, these benchmarks can be rewritten, but the rules require that the programming language can only be C or Fortran. ■ ■The recent PARSEC (Princeton Application Repository for Shared Memory Computers) benchmark suite consists of multithreaded programs that use Pthreads (POSIX threads) and OpenMP (Open MultiProcessing). They focus on emerging markets and consist of nine applications and three ker­ nels. Eight rely on data parallelism, three rely on pipelined parallelism, and one on unstructured parallelism. The downside of such traditional restrictions to benchmarks is that innovation is chiefly limited to the architecture and compiler. Better data structures, algo­ rithms, programming languages, and so on often can not be used, since that would give a misleading result. The system could win because of, say, the algo­rithm, and not because of the hardware or the compiler. While these guidelines are understandable when the foundations of computing are relatively stable—as they were in the 1990s and the first half of this decade— they are undesirable at the beginning of a revolution. For this revolution to succeed, we need to encourage innovation at all levels. One recent approach has been advocated by researchers at the University of California at Berkeley. They have identified 13 design patterns that they claim will be part of applications of the future. These design patterns are implemented by frameworks or kernels. Examples are sparse matrices, structured grid, finite-state machines, map reduce, and graph traversal. By keeping the definitions at a high level, they hope to encourage innovations at any level of the system. Thus, the system with the fastest sparse matrix solver is welcome to use any data structure, algorithm, and pro­gramming language, in addition to novel architectures and compilers. We’ll see examples of such benchmarks in Section 7.11. True or false: The main drawback with conventional approaches to bench­ marks for parallel computers is that the rules that ensure fairness also suppress innovation. Pthreads A UNIX API for cre­ating and manipulating threads. It comes with a library. OpenMP An API for shared memory multiprocessing in C, C++, or Fortran that runs on UNIX and Microsoft platforms. It includes compiler directives, a library, and runtime directives. Check Yourself
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7.10 Roofline: A Simple Performance Model This section is based on a paper by Williams and Patterson [2008]. In the recent past, conventional wisdom in computer architecture led to similar microproces­ sor designs. Nearly every desktop and server computer used caches, pipelining, superscalar instruction issue, branch prediction, and out-of-order execution. The instruction sets varied, but the microprocessors were all from the same school of design. The switch to multicore likely means that microprocessors will become more diverse, since there is no conventional wisdom as to which architecture will make it easiest to write correct parallel processing programs that run efficiently and scale as the number of cores increases over time. Moreover, as the number of cores per chip does increase, a single manufacturer will likely offer different numbers of cores per chip at different price points at the same time. Given the increasing diversity, it would be especially helpful if we had a simple model that offered insights into the performance of different designs. It need not be perfect, just insightful. The 3Cs model from Chapter 5 is an analogy. It is not a perfect model, since it ignores potentially important factors like block size, block allocation policy, and block replacement policy. Moreover, it has quirks. For example, a miss can be ascribed due to capacity in one design and to a conflict miss in another cache of the same size. Yet 3Cs model has been popular for 20 years, because it offers insight into the behavior of programs, helping both architects and programmers improve their creations based on insights from that model. To find such a model, let’s start with the 13 Berkeley design patterns in Figure 7.9. The idea of the design patterns is that the performance of a given application is really the weighted sum of several kernels that implement those design patterns. We’ll evaluate individual kernels here, but keep in mind that real applications are combinations of many kernels. While there are versions with different data types, floating point is popular in several implementations. Hence, peak floating-point performance is a limit on the speed of such kernels on a given computer. For multicore chips, peak floating- point performance is the collective peak performance of all the cores on the chip. If there were multiple microprocessors in the system, you would multiply the peak per chip by the total number of chips. The demands on the memory system can be estimated by dividing this peak floating-point performance by the average number of floating-point operations per byte accessed: ​ Floating-Point Operations/Sec  Floating-Point Operations/Byte ​ = Bytes/Sec 7.10 Roofline: A Simple Performance Model 667
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668 Chapter 7 Multicores, Multiprocessors, and Clusters The ratio of floating-point operations per byte of memory accessed is called the arithmetic intensity. It can be calculated by taking the total number of floating- point operations for a program divided by the total number of data bytes transferred to main memory during program execution. Figure 7.12 shows the arithmetic intensity of several of the Berkeley design patterns from Figure 7.11. arithmetic intensity ­ The ratio of floating-point operations in a program to the number of data bytes accessed by a program from main memory. FIGURE 7.12 Arithmetic intensity, specified as the number of float-point operations to run the program divided by the num­ber of bytes accessed in main memory [Williams, Patterson, 2008]. Some kernels have an arithmetic intensity that scales with problem size, such as Dense Matrix, but there are many kernels with arithmetic intensities independent of problem size. For kernels in this former case, weak scaling can lead to different results, since it puts much less demand on the memory system. A r i t h m e t i c I n t e n s i t y O(N) O(log(N)) O(1) Sparse Matrix (SpMV) Structured Grids (Stencils, PDEs) Structured Grids (Lattice Methods) Spectral Methods (FFTs) Dense Matrix (BLAS3) N-body (Particle Methods) The Roofline Model The proposed simple model ties floating-point performance, arithmetic intensity, and memory performance together in a two-dimensional graph [Will­iams, Patterson, 2008]. Peak floating-point performance can be found using the hardware specifications mentioned above. The working set of the kernels we consider here do not fit in on-chip caches, so peak memory performance may be defined by the memory system behind the caches. One way to find the peak memory perfor­mance is the Stream benchmark. (See the Elaboration on page 473 in Chapter 5). Figure 7.13 shows the model, which is done once for a computer, not for each kernel. The vertical Y-axis is achievable floating-point performance from 0.5 to 64.0 GFLOPs/second. The horizontal X-axis is arithmetic intensity, varying from 1/8 FLOPs/DRAM byte accessed to 16 FLOPs/DRAM byte accessed. Note that the graph is a log-log scale. For a given kernel, we can find a point on the X-axis based on its arithmetic intensity. If we drew a vertical line through that point, the performance of the ker­ nel on that computer must lie somewhere along that line. We can plot a horizontal line showing peak floating-point performance of the computer. Obviously, the
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actual floating-point performance can be no higher than the horizontal line, since that is a hardware limit. How could we plot the peak memory performance? Since X-axis is FLOPs/ byte and the Y-axis is FLOPs/second, bytes/second is just a diagonal line at a 45-degree angle in this figure. Hence, we can plot a third line that gives the maximum floating-point performance that the memory system of that computer can support for a given arithmetic intensity. We can express the limits as a formula to plot the line in the graph in Figure 7.13: Attainable GFLOPs/sec = Min (Peak Memory BW × Arithmetic Intensity, Peak Floating-Point Performance) The horizontal and diagonal lines give this simple model its name and indicates its value. The “roofline” sets an upper bound on performance of a kernel depend­ ing on its arithmetic intensity. If we think of arithmetic intensity as a pole that hits the roof, either it hits the flat part of the roof, which means performance is com­putationally limited, or it hits the slanted part of the roof, which means perfor­ mance is ultimately limited by memory bandwidth. In Figure 7.13, kernel 2 is an example of the former and kernel 1 is an example of the latter. Given a roofline of a computer, you can apply it repeatedly, since it doesn’t vary by kernel. FIGURE 7.13 Roofline Model [Williams, Patterson, 2008]. This example has a peak floating-point performance of 16 GFLOPS/sec and a peak memory bandwidth of 16 GB/sec from the Stream benchmark. (Since stream is actually four measurements, this line is the average of the four.) The dotted vertical line in color on the left represents Kernel 1, which has an arithmetic intensity of 0.5 FLOPs/byte. It is limited by memory bandwidth to no more than 8 GFLOPS/sec on this Opteron X2. The dotted vertical line to the right repre­sents Kernel 2, which has an arithmetic intensity of 4 FLOPs/byte. It is limited only computationally to 16 GFLOPS/s. (This data is based on the AMD Opteron X2 (Revision F) using dual cores running at 2 GHz in a dual socket system.) Arithmetic Intensity: FLOPs/Byte Ratio Attainable GFLOPs/second 0.5 1.0 2.0 4.0 8.0 16.0 32.0 64.0 1/8 1/4 1/2 1 2 4 8 16 peak floating-point performance peak memory BW (stream) Kernel 1 (Memory Bandwidth limited) Kernel 2 (Computation limited) 7.10 Roofline: A Simple Performance Model 669
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670 Chapter 7 Multicores, Multiprocessors, and Clusters Note that the “ridge point,” where the diagonal and horizontal roofs meet, offers an interesting insight into the computer. If it is far to the right, then only kernels with very high arithmetic intensity can achieve the maximum perfor­mance of that computer. If it is far to the left, then almost any kernel can poten­tially hit the maximum performance. We’ll see examples of both shortly. Comparing Two Generations of Opterons The AMD Opteron X4 (Barcelona) with four cores is the successor to the Opteron X2 with two cores. To simplify board design, they use the same socket. Hence, they have the same DRAM channels and thus the same peak memory bandwidth. In addition to doubling the number of cores, the Opteron X4 also has twice the peak floating-point performance per core: Opteron X4 cores can issue two floating-point SSE2 instructions per clock cycle, while Opteron X2 cores issue at most one. As the two systems we’re comparing have similar clock rates—2.2 GHz for Opteron X2 versus 2.3 GHz for Opteron X4—the Opteron X4 has more than four times the peak floating-point performance of the Opteron X2 with the same DRAM bandwidth. The Opteron X4 also has a 2MB L3 cache, which is not found in the Opteron X2. Figure 7.14 compares the roofline models for both systems. As we would expect, the ridge point moves from 1 in the Opteron X2 to 5 in the Opteron X4. Hence, to see a performance gain in the next generation, kernels need an arith­metic intensity higher than 1 or their working sets must fit in the caches of the Opteron X4. FIGURE 7.14 Roofline models of two generations of Opterons. The Opteron X2 roofline, which is the same as Figure 7.11, is in black, and the Opteron X4 roofline is in color. The bigger ridge point of Opteron X4 means that kernels that where computationally bound on the Opteron X2 could be memory- performance bound on the Opteron X4. Actual FLOPbyte ratio Attainable GFLOP/s 128.0 64.0 32.0 16.0 8.0 4.0 2.0 1.0 0.5 1/8 1/4 1/2 16 8 4 2 1 Opteron X4 (Barcelona) Opteron X2
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The roofline model gives an upper bound to performance. Suppose your program is far below that bound. What optimizations should you perform, and in what order? To reduce computational bottlenecks, the following two optimizations can help almost any kernel: 1. Floating-point operation mix. Peak floating-point performance for a com­ puter typically requires an equal number of nearly simultaneous additions and multiplications. That balance is necessary either because the computer supports a fused multiply-add instruction (see the Elaboration on page 268 in Chapter 3) or because the floating-point unit has an equal number of floating-point adders and floating-point multipliers. The best performance also requires that a significant fraction of the instruction mix is floating- point operations and not integer instructions. 2. Improve instruction-level parallelism and apply SIMD. For superscalar archi­ tectures, the highest performance comes when fetching, executing, and committing three to four instructions per clock cycle (see Chapter 4). The goal here is to improve the code from the compiler to increase ILP. One way is by unrolling loops. For the x86 architectures, a single SIMD instruction can operate on pairs of double precision operands, so they should be used whenever possible. To reduce memory bottlenecks, the following two optimizations can help: 1. Software prefetching. Usually the highest performance requires keeping many memory operations in flight, which is easier to do by performing software prefetch instructions rather than waiting until the data is required by the computation. 2. Memory affinity. Most microprocessors today include a memory controller on the same chip with the microprocessor. If the system has multiple chips, this means that some addresses go to the DRAM that is local to one chip, and the rest require accesses over the chip interconnect to access the DRAM that is local to another chip. The latter case lowers performance. This optimiza­ tion tries to allocate data and the threads tasked to operate on that data to the same memory-processor pair, so that the processors rarely have to access the memory of the other chips. The roofline model can help decide which of these optimizations to perform and the order in which to perform them. We can think of each of these optimizations as a “ceiling” below the appropriate roofline, meaning that you cannot break through a ceiling without performing the associated optimization. 7.10 Roofline: A Simple Performance Model 671
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672 Chapter 7 Multicores, Multiprocessors, and Clusters FIGURE 7.15 Roofline model with ceilings. The top graph shows the computational “ceilings” of 8 GFLOPs/sec if the floating-point operation mix is imbalanced and 2 GFLOPs/sec if the optimizations to increase ILP and SIMD are also missing. The bottom graph shows the memory bandwidth ceilings of 11 GB/sec without software prefetching and 4.8 GB/sec if memory affinity optimizations are also miss­ing. 0.5 1.0 2.0 4.0 8.0 16.0 32.0 64.0 1/8 1/4 1/2 1 2 4 8 16 peak floating-point performance 1. Fl. Pt. imbalance 2. Without ILP or SIMD AMD Opteron peak memory BW (stream) Arithmetic Intensity: FLOPs/Byte Ratio Attainable GFLOPs/second 0.5 1.0 2.0 4.0 8.0 16.0 32.0 64.0 1/8 1/4 1/2 1 2 4 8 16 AMD Opteron peak memory BW (stream) Arithmetic Intensity: FLOPs/Byte Ratio Attainable GFLOPs/second 3. w/out SW prefetching 4. w/out Memory Affinity peak floating-point performance
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The computational roofline can be found from the manuals, and the memory roofline can be found from running the stream benchmark. The computational ceilings, such as floating-point balance, also come from the manuals for that com­ puter. The memory ceiling requires running experiments on each computer to determine the gap between them. The good news is that this process only need be done once per computer, for once someone characterizes a computer’s ceilings, everyone can use the results to prioritize their optimizations for that computer. Figure 7.15 adds ceilings to the roofline model in Figure 7.13, showing the computational ceilings in the top graph and the memory bandwidth ceilings on the bottom graph. Although the higher ceilings are not labeled with both opti­ mizations, that is implied in this figure; to break through the highest ceiling, you need to have already broken through all the ones below. The thickness of the gap between the ceiling and the next higher limit is the reward for trying that optimization. Thus, Figure 7.15 suggests that optimization 2, which improves ILP, has a large benefit for improving computation on that computer, and optimization 4, which improves memory affinity, has a large bene­fit for improving memory bandwidth on that computer. Figure 7.16 combines the ceilings of Figure 7.15 into a single graph. The arith­ metic intensity of a kernel determines the optimization region, which in turn sug­ gests which optimizations to try. Note that the computational optimizations and the memory bandwidth optimizations overlap for much of the arithmetic inten­ sity. Three regions are shaded differently in Figure 7.16 to indicate the different optimization strategies. For example, Kernel 2 falls in the blue trapezoid on the right, which suggests working only on the computational optimizations. Kernel 1 falls in the blue-gray parallelogram in the middle, which suggests trying both types of optimizations. Moreover, it suggests starting with optimizations 2 and 4. Note that the Kernel 1 vertical lines fall below the floating-point imbalance opti­mization, so optimization 1 may be unnecessary. If a kernel fell in the gray trian­gle on the lower left, it would suggest trying just memory optimizations. Thus far, we have been assuming that the arithmetic intensity is fixed, but that is not really the case. First, there are kernels where the arithmetic intensity increases with problem size, such as for Dense Matrix and N-body problems (see Figure 7.12). Indeed, this can be a reason that programmers have more success with weak scaling than with strong scaling. Second, caches affect the number of accesses that go to memory, so optimizations that improve cache performance also improve arithmetic intensity. One example is improving temporal locality by unrolling loops and then grouping together statements with similar addresses. Many computers have special cache instructions that allocate data in a cache but do not first fill the data from memory at that address, since it will soon be over­written. Both these optimizations reduce memory traffic, thereby moving the arithmetic intensity pole to the right by a factor of, say, 1.5. This shift right could put the kernel in a different optimization region. 7.10 Roofline: A Simple Performance Model 673
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674 Chapter 7 Multicores, Multiprocessors, and Clusters The next section uses the roofline model to demonstrate the difference for four recent multicore microprocessors for two real application kernels. While the examples above show how to help programmers improve performance, the model can also be used by architects to decide where they optimize hardware to improve performance of the kernels that they think will be important. Elaboration: The ceilings are ordered so that lower ceilings are easier to optimize. Clearly, a programmer can optimize in any order, but following this sequence reduces the chances of wasting effort on an optimization that has no benefit due to other constraints. Like the 3Cs model, as long as the roofline model delivers on insights, a model can have quirks. For example, it assumes the program is load balanced between all processors. FIGURE 7.16 Roofline model with ceilings, overlapping areas shaded, and the two ker­ nels from Figure 7.13. Kernels whose arithmetic intensity land in the blue trapezoid on the right should focus on computation optimizations, and kernels whose arithmetic intensity land in the gray triangle in the lower left should focus on memory bandwidth optimizations. Those that land in the blue-gray parallelo­gram in the middle need to worry about both. As Kernel 1 falls in the parallelogram in the middle, try opti­mizing ILP and SIMD, memory affinity, and software prefetching. Kernel 2 falls in the trapezoid on the right, so try optimizing ILP and SIMD and the balance of floating-point operations. 0.5 1.0 2.0 4.0 8.0 16.0 32.0 64.0 1 2 4 8 16 peak memory BW (stream) Arithmetic Intensity: FLOPs/Byte Ratio Attainable GFLOPs/second Kernel 1 Kernel 2 2. Without ILP or SIMD 4. w/out Memory Affinity 1. Fl. Pt. imbalance 3. w/out SW prefetching peak floating-point performance 1/8 1/4 1/2
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Elaboration: An alternative to the Stream benchmark is to use the raw DRAM bandwidth as the roofline. While the DRAMs definitely set a hard bound, actual memory performance is often so far from that boundary that it’s not that useful as an upper bound. That is, no program can go close to that bound. The downside to using Stream is that very careful programming may exceed the Stream results, so the memory roofline may not be as hard a limit as the computa­tional roofline. We stick with Stream because few programmers will be able to deliver more memory bandwidth than Stream discovers. Elaboration: The two axes used above were floating-point operations per second and arith­metic intensity of accesses to main memory. The roofline model could be used for other kernels and computers where the performance was a function of different performance metrics. For example, if the working set fits in the L2 cache of the computer, the bandwidth plotted on the diagonal roofline could be L2 cache bandwidth instead of main memory bandwidth, and the arithmetic intensity on the X-axis would be based on FLOPs per L2 cache byte accessed. The diagonal L2 performance line would move up, and the ridge point would likely move to the left. As a second example, if the kernel was sort, records sorted per second could replace floating-point operations per instruction on the Y-axis and arithmetic intensity would become records per DRAM byte accessed. The roofline model could even work for an I/O intensive kernel. The Y-axis would be I/O operations per second, the X-axis would be the average number of instructions per I/O opera­tion, and the roofline would show peak I/O bandwidth. Elaboration: Although the roofline model shown is for multicore processors, it clearly would work for a uniprocessor as well. 7.11  Real Stuff: Benchmarking Four Multicores Using the Roofline Model Given the uncertainty about the best way to proceed in this parallel revolution, it’s not surprising that we see as many different designs as there are multicore chips. In this section, we’ll examine four multicore systems for two kernels of the design patterns in Figure 7.11: sparse matrix and structured grid. (The information in this section is from [Williams, Oliker, et al., 2007], [Williams, Carter, et al., 2008], [Williams and Patterson, 2008].) 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 675
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676 Chapter 7 Multicores, Multiprocessors, and Clusters Four Multicore Systems Figure 7.17 shows the basic organization of the four systems, and Figure 7.18 lists the key characteristics of the examples of this section. These are all dual socket systems. Figure 7.19 shows the roofline performance model for each system. 667 MHz FBDIMMs Chipset (4x64 b controllers) 10.66 GB/s(write) 21.33 GB/s(read) 10.66 GB/s Core FSB Core Core Core 10.66 GB/s Core FSB Core Core Core 4 MB Shared L2 4 MB Shared L2 4 MB Shared L2 4 MB Shared L2 667 MHz FBDIMMs 4MB Shared L2 (16 way) (address interleaving via 8x64 B banks) 179 GB/s (fill) 90 GB/s (writethru) 21.33 GB/s (read) 10.66 GB/s (write) 8x6.4 GB/s (1 per hub per direction) 4 Coherency Hubs (2 banks each) 2x128 b memory controllers (4 banks each) 21.33 GB/s (read) 10.66 GB/s (write) Crossbar Switch (16 Byte reads 8 Byte writes) MT sparc MT sparc MT sparc MT sparc MT sparc MT sparc MT sparc MT sparc 8K L1 8K L1 8K L1 8K L1 8K L1 8K L1 8K L1 8K L1 667 MHz FBDIMMs 4MB Shared L2 (16 way) (address interleaving via 8x64 B banks) 4 Coherency Hubs (2 banks each) 2x128 b memory controllers (4 banks each) MT sparc MT sparc MT sparc MT sparc MT sparc MT sparc 8K L1 8K L1 8K L1 8K L1 8K L1 8K L1 179 GB/s (fill) 90 GB/s (writethru) MT sparc MT sparc 8K L1 8K L1 Crossbar Switch (16 Byte reads 8 Byte writes) (c) Sun UltraSPARC T2 5140 (Niagara 2) (a) Intel Xeon e5345 (Clovertown) FIGURE 7.17 Four recent multiprocessors, each using two sockets for the processors. Starting from the upper left hand corner, the computers are: (a) Intel Xeon e5345 (Clovertown), (b) AMD Opteron X4 2356 (Barcelona), (c) Sun UltraSPARC T2 5140 (Niagara 2), and (d) IBM Cell QS20. Note that the Intel Xeon e5345 (Clovertown) has a separate north bridge chip not found in the other microprocessors. (d) IBM Cell QS20 667 MHz DDR2 DIMMs 10.66 GB/s 2x64 b memory controllers HyperTransport Opteron Opteron Opteron 667 MHz DDR2 DIMMs 10.66 GB/s 2x64 b memory controllers 512 KB victim 2 MB Shared quasi-victim (32 way) SRI/crossbar 2 MB Shared quasi-victim (32 way) SRI/crossbar HyperTransport 4 GB/s (each direction) 512 KB victim 512 KB victim 512 KB victim 512 KB victim 512 KB victim 512 KB victim 512 KB victim Opteron Opteron Opteron Opteron Opteron <32 GB 800 MHz DDR2 DIMMs 25.6 GB/s EIB (Ring Network) SPE 256 K MFC SPE 256 K MFC SPE 256 K MFC SPE 256 K MFC MFC MFC MFC MFC 256 K 256 K 256 K 256 K SPE SPE SPE SPE 4x64b controllers BIF VMT PPE 512 KB L2 <32 GB 800 MHz DDR2 DIMMs 25.6 GB/s EIB (Ring Network) BIF VMT PPE 512 KB L2 SPE 256 K MFC SPE 256 K MFC SPE 256 K MFC SPE 256 K MFC <20 GB/s (each direction) MFC MFC MFC MFC 256 K 256 K 256 K 256 K SPE SPE SPE SPE 4x64b controllers (b) AMD Opteron X4 2356 (Barcelona)
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The Intel Xeon e5345 (code-named “Clovertown”) contains four cores per socket by packaging two dual core chips into a single socket. These two chips share a front side bus that is attached to a separate north bridge chip set (see Chapter 6). This north bridge chip set supports two front side buses and hence two sockets. It includes the memory controller for the 667 MHz Fully Buffered DRAM DIMMs (FBDIMMs). This dual-socket system uses a processor clock rate of 2.33 GHz and has the highest peak performance of the four examples: 75 GFLOPS. However, the roofline model in Figure 7.19 shows that this can be achieved only with arithmetic intensities of 8 and above. The reason is that the dual front side buses interfere with each other, yielding relatively low memory bandwidth to programs. The AMD Opteron X4 2356 (Barcelona) contains four cores per chip, and each socket has a single chip. Each chip has a memory controller on board and its own path to 667 MHz DDR2 DRAM. These two sockets communicate over separate, dedicated Hypertransport links, which makes it possible to build a “glueless” multichip system. This dual-socket system uses a processor clock rate of 2.30 GHz and has a peak performance of about 74 GFLOPS. Figure 7.19 shows that the ridge point in the roofline model is to the left of the Xeon e5345 (Clover­town), at an arithmetic intensity of about 5 FLOPS per byte. The Sun UltraSPARC T2 5140 (code named “Niagara 2”) is quite different from the two x86 microarchitectures. It uses eight relatively simple cores per chip with a much lower clock rate. It also provides fine-grained multithreading with eight threads per core. A single chip has four memory controllers that could drive four sets of 667 MHz FBDIMMs. To join two UltraSPARC T2 chips together, two of the four memory channels are connected, leaving two memory channels per chip. This dual-socket system has a peak performance of about 22 GFLOPS, and the ridge point is an amazingly low arithmetic intensity of just 1/3 FLOPS per byte. FIGURE 7.18 Characteristics of the four recent multicores. Although the Xeon e5345 and Opteron X4 have the same speed DRAMs, the Stream benchmark shows a higher practical memory bandwidth due to the inefficiencies of the front side bus on the Xeon e5345. MPU Type ISA Number Threads Number Cores Number Sockets Clock GHz Peak GFLOP/s DRAM: Peak GB/s, Clock Rate, Type Intel Xeon e5345 (Clovertown) x86/64 8 8 2 2.33 75 FSB: 2 x 10.6 667 MHz FBDIMM AMD Opteron X4 2356 (Barcelona) x86/64 8 8 2 2.30 74 2 x 10.6 667 MHz DDR2 Sun UltraSPARC T2 5140 (Niagara 2) Sparc 128 16 2 1.17 22 2 x 21.3 (read) 2 x 10.6 (write) 667 MHz FBDIMM IBM Cell QS20 Cell 16 16 2 3.20 29 2 x 25.6 XDR 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 677
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678 Chapter 7 Multicores, Multiprocessors, and Clusters FIGURE 7.19 Roofline model for multicore multiprocessors in Figure 7.15. The ceilings are the same as in Figure 7.13. Starting from the upper left hand corner, the computers are: (a) Intel Xeon e5345 (Clovertown), (b) AMD Opteron X4 2356 (Barcelona), (c) Sun UltraSPARC T2 5140 (Niagara 2), and (d) IBM Cell QS20. Note the ridge points for the four microprocessors intersect the X-axis at the arithmetic intensities of 6, 4, 1/3, and 3/4, respectively. The dashed vertical lines are for the two kernels of this section and the stars mark the performance achieved for these kernels after all the optimizations. SpMV is the pair of dashed vertical lines on the left. It has two lines because its arithmetic intensity improved from 0.166 to 0.255 based on register blocking optimizations. LBHMD is the dashed vertical lines on the right. It has a pair of lines in (a) and (b) because a cache optimization skips filling the cache block on a miss when the processor would write new data into the entire block. That optimization increases the arithmetic inten­sity from 0.70 to 1.07. It’s a single line in (c) at 0.70 because UltraSPARC T2 does not offer the cache optimization. It is a single line at 1.07 in (d) because Cell has local store loaded by DMA, so the program doesn’t fetch unnecessary data as do caches. Attainable GFLOP/s Actual FLOPbyte ratio 1/8 1/4 1/2 1 2 4 8 16 Peak DP mul/add imbalance w/out SIMD w/out ILP 0.5 1.0 2.0 4.0 8.0 16.0 32.0 64.0 128.0 1.0 a. Intel Xeon e5345 (Clovertown) Attainable GFLOP/s Actual FLOPbyte ratio b. AMD Opteron X4 2356 (Barcelona) 1/8 1/4 1/2 1 2 4 8 16 Peak DP mul/add imbalance w/out SIMD w/out ILP 0.5 1.0 2.0 4.0 8.0 16.0 32.0 64.0 128.0 1.0 Actual FLOPbyte ratio Attainable GFLOP/s Attainable GFLOP/s d. IBM Cell QS20 Peak DP w/out FMA w/out SIMD w/out ILP 1/8 1/4 1/2 1 2 4 8 16 0.5 1.0 2.0 4.0 8.0 16.0 32.0 64.0 128.0 1.0 Actual FLOPbyte ratio c. Sun UltraSPARC T2 5140 (Niagara 2) 25% issued = FP Peak DP 1/8 1/4 1/2 1 2 4 8 16 0.5 1.0 2.0 4.0 8.0 16.0 32.0 64.0 128.0 1.0
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The IBM Cell QS20 is again different from the two x86 microarchitectures and from UltraSPARC T2. It is a heterogeneous design, with a relatively simple PowerPC core and with eight SPEs (Synergistic Processing Elements) that have their own unique SIMD-style instruction set. Each SPE also has its own local memory instead of a cache. An SPE must transfer data from main memory into the local memory to operate on it and then back to main memory when it is completed. It uses DMA, which has some similarity to software prefetching. The two sockets are connected via links dedicated to multichip communications. The clock rate of this system is highest of the four multicores at 3.2 GHz, and it uses XDR DRAM chips, which are typically found in game consoles. They have high bandwidth but low capacity. Given that the Cell’s main application was graphics, it has much higher single precision performance than double precision performance. The peak double precision performance of the SPEs in the dual socket system is 29 GFLOPS, and the ridge point of arithmetic intensity is 0.75 FLOPs per byte. While the two x86 architectures have many fewer cores per chip than the IBM and Sun offerings in early 2008, that is just where they are today. As the number of cores is expected to double every technology generation, it will be interesting to see whether the x86 architectures will close the “core gap” or if IBM and Sun can sustain a larger number of cores, given that their primary focus is on servers versus the desktop. Note that these machines take very different approaches to the memory system. The Xeon e5345 uses a conventional private L1 cache and then pairs of processors each share an L2 cache. These are connected through an off-chip memory controller to a common memory over two buses. In contrast, Opteron X4 has a separate memory controller and memory per chip, and each core has private L1 and L2 caches. UltraSPARC T2 has the memory controller on-chip and four separate DRAM channels per chip, and the cores all share the L2 cache, which has four banks to improve bandwidth. Its fine-grained multithreading on top of its multicore design allows it to keep many memory accesses in flight. The most radical is the Cell. It has local private memories per SPE and uses DMA to transfer data between the DRAM attached to each chip and local memory. It sustains many memory accesses in flight by having many cores and then many DMA transfers per core. Let’s see how these four contrasting multicores perform on two kernels. Sparse Matrix The first example kernel of the Sparse Matrix computational design pattern is Sparse Matrix-Vector multiply (SpMV). SpMV is popular in scientific computing, economic modeling, and information retrieval. Alas, conventional implementa­ tions often run at less than 10% of peak performance of uniprocessors. One rea­son is the irregular access to memory, which you might expect from a kernel working with sparse matrices. The computation is 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 679
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680 Chapter 7 Multicores, Multiprocessors, and Clusters y = A × x where A is a sparse matrix and x and y are dense vectors. Fourteen sparse matrices taken from a variety of real applications were used to evaluate SpMV perfor­mance, but only the median performance is reported here. The arithmetic inten­sity varies from 0.166 before a register blocking optimization to 0.250 FLOPS per byte afterward. The code was first parallelized to utilize all the cores. Given that the low arithmetic intensity of SpMV was below the ridge point of all four multicores in Figure 7.19, most of the optimizations involved the memory system: ■ ■Prefetching. To get the most out of the memory systems, both software and hardware prefetching were used. ■ ■Memory Affinity. This optimization reduces accesses to the DRAM memory connected to the other socket in the three systems that have local DRAM memory. ■ ■Compressing Data Structures. Since memory bandwidth likely limits per­ formance, this optimization uses smaller data structures to increase ­performance—for example, using a 16-bit index instead of a 32-bit index, and using more space efficient representations of the nonzeros in the rows of a sparse matrix. Figure 7.20 shows the performance on SpMV for the four systems versus the number of cores. (The same results are found in Figure 7.19, but it’s hard to com­pare performance when on a log scale.) Note that despite having the highest peak performance in Figure 7.18 and the highest single core performance, the Intel Xeon e5345 has the lowest delivered performance of the four multi­cores. Opteron X4 doubles its performance. The Xeon e5345 bottle­neck is the dual front side buses. Despite the lowest clock rate, the larger number of simple cores of the Sun UltraSPARC T2 outperforms the two x86 processors. The IBM Cell has the highest performance of the four. Note that all but the Xeon e5345 scale well with the number of cores, although the Opteron X4 scales more slowly with four or more cores. Structured Grid The second kernel is an example of the structured grid design pattern. Lattice- Boltzmann Magneto-Hydrodynamics (LBMHD) is popular for computational fluid dynamics; it is a structured grid code with a series of time steps.
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Each point involves reading and writing about 75 double precision floating- point numbers and about 1300 floating-point operations. Like SpMV, LBMHD tends to get a small fraction of peak performance on uniprocessors because of the complexity of the data structures and the irregularity of memory access patterns. The FLOPS to byte ratio is a much higher 0.70 versus less than 0.25 in SpMV. By not filling the cache block from memory on a write miss when the program is going to overwrite the whole block, the intensity rises to 1.07. All multicores but UltraSPARC T2 (Niagara 2) offer this cache optimization. Figure 7.19 shows that the arithmetic intensity of LBMHD is high enough that both computational and memory bandwidth optimizations make sense on all multicores but UltraSPARC T2, whose roofline ridge point is below that of LBMHD. UltraSPARC T2 can reach the roofline using only the computational optimizations. In addition to parallelizing the code so that it could use all the cores, the following optimizations were used for LBMHD: ■ ■Memory Affinity: This optimization is again useful for the same reasons mentioned above. ■ ■TLB Miss Minimization: To reduce TLB misses significantly in LBMHD, use a structure of arrays and combine some loops together rather than the con­ ventional approach of using an array of structures. FIGURE 7.20 Performance of SpMV on the four multicores. 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Cores GFLOPs/sec Opteron X4 2356 Cell QS20 UltraSPARC T2 Xeon e5346 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 681
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682 Chapter 7 Multicores, Multiprocessors, and Clusters ■ ■Loop Unrolling and Reordering: To expose sufficient parallelism and improve cache utilization, the loops were unrolled and then reordered to group state­ ments with similar addresses. ■ ■“SIMD-ize”: The compilers of the two x86 systems could not generate good SSE code, so these had to be written by hand in assembly language. Figure 7.21 shows the performance for the four systems versus the number of cores for LBMHD. Like the SpMV, the Intel Xeon e5345 has the worst scalability. This time the more powerful cores of Opteron X4 outperform the simple cores of UltraSPARC T2 despite having half the number of cores. Once again, the IBM Cell is the fastest system. All but Xeon e5345 scale with the number of cores, although T2 and Cell scale more smoothly than the Opteron X4. FIGURE 7.21 Performance of LBMHD on the four multicores. 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Cores GFLOPs/sec Opteron X4 2356 Cell QS20 UltraSPARC T2 Xeon e5345 Productivity In addition to performance, another important issue for the parallel computing revolution is productivity, or the programming difficulty of achieving perfor­ mance. To illustrate the differences, Figure 7.22 compares naïve performance to fully optimized performance for the four cores on the two kernels.
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FIGURE 7.22 Base versus fully optimized performance of the four cores on the two ker­nels. Note the high fraction of fully optimized performance delivered by the Sun UltraSPARC T2 (Niagara 2). There is no base performance column for the IBM Cell because there is no way to port the code to the SPEs without caches. While you could run the code on the Power core, it has an order of magnitude lower performance than the SPES, so we ignore it in this figure. MPU Type Kernel Base GFLOPs/s Optimized GFLOPs/s Naïve % of Optimized Intel Xeon e5345 (Clovertown) SpMV LBMHD 1.0 4.6 1.5 5.6 64% 82% AMD Opteron X4 2356 (Barcelona) SpMV LBMHD 1.4 7.1 3.6 14.1 38% 50% Sun UltraSPARC T2 (Niagara 2) SpMV LBMHD 3.5 9.7 4.1 10.5 86% 93% IBM Cell QS20 SpMV LBMHD ­ ­ 6.4 16.7 0% 0% The easiest was UltraSPARC T2, due to its large memory band­width and its easy-to-understand cores. The advice for these two kernels in UltraSPARC T2 is simply to try to get good performing code from the compiler and then use as many threads as possible. The one caution for other kernels is that UltraS­PARC T2 can come afoul of the pitfall about making sure set associativity matches the number of hardware threads (see page 545 of Chapter 5). Each chip supports 64 hardware threads, while the L2 cache is four-way set associative. This mismatch can require restructuring loops to reduce conflict misses. The Xeon e5346 was difficult because it was hard to understand the memory behavior of the dual front side buses, it was hard to understand how hard­ware prefetching worked, and it was difficult to get good SIMD code from the compiler. The C code for it and for the Opteron X4 are liberally sprinkled with intrinsic statements involving SIMD instructions to get good performance. The Opteron X4 benefited from the most types of optimizations, so it needed more effort than the Xeon e5345, although the memory behavior of the Opteron X4 was easier to understand than that of the Xeon e5345. Cell provided two types of challenges. First, the SIMD instructions of the SPE were awkward to compile for, so at times you needed to help the compiler by inserting intrinsic statements with assembly language instructions into the C code. Second, the memory system was more interesting. Since each SPE has local memory in a separate address space, you could not simply port the code and start 7.11 Real Stuff: Benchmarking Four Multicores Using the Roofline Model 683
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684 Chapter 7 Multicores, Multiprocessors, and Clusters running on the SPE. Hence, there is no base code column for the IBM Cell in Figure 7.22, and you needed to change the program to issue DMA commands to transfer data back and forth between local store and memory. The good news is that DMA played the role of software prefetch in caches, and DMA is much easier to use and achieve good memory performance. Cell was able to deliver almost 90% of the memory bandwidth “roofline” to these kernels, compared to 50% or less for the other multicores. 7.12 Fallacies and Pitfalls The many assaults on parallel processing have uncovered numerous fallacies and pitfalls. We cover three here. Fallacy: Amdahl’s law doesn’t apply to parallel computers. In 1987, the head of a research organization claimed that Amdahl’s law had been broken by a multiprocessor machine. To try to understand the basis of the media reports, let’s see the quote that gave us Amdahl’s law [1967, p. 483]: A fairly obvious conclusion which can be drawn at this point is that the effort ­expended on achieving high parallel processing rates is wasted unless it is ac­companied by achievements in sequential processing rates of very nearly the same ­magnitude. This statement must still be true; the neglected portion of the program must limit performance. One interpretation of the law leads to the following lemma: por­ tions of every program must be sequential, so there must be an economic upper bound to the number of processors—say, 100. By showing linear speed-up with 1000 processors, this lemma is disproved; hence the claim that Amdahl’s law was broken. The approach of the researchers was to use weak scaling: rather than going 1000 times faster on the same data set, they computed 1000 times more work in comparable time. For their algorithm, the sequential portion of the program was constant, independent of the size of the input, and the rest was fully parallel— hence, linear speed-up with 1000 processors. Amdahl’s law obviously applies to parallel processors. What this research does point out is that one of the main uses of faster computers is to run larger prob­lems, but to beware how the algorithm scales as you increase problem size. Fallacy: Peak performance tracks observed performance. For example, Section 7.11 shows that the Intel Xeon e5345, the microprocessor with the highest peak performance, was the slowest of the four multicore micro­ processors for two kernels. For over a decade prophets have voiced the contention that the organization of a single computer has reached its limits and that truly sig­nificant advances can be made only by interconnec­ tion of a multiplicity of com­puters in such a manner as to ­permit cooperative solu­tion. . . . Demonstration is made of the continued valid­ity of the single processor approach . . . Gene Amdahl, “Validity of the single processor approach to achieving large scale com­puting capabilities,” Spring Joint Computer ­Conference, 1967
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The supercomputer industry used this metric in marketing, and the fallacy is exacerbated with parallel machines. Not only are marketers using the nearly unat­tainable peak performance of a uniprocessor node, but also they are then multi­plying it by the total number of processors, assuming perfect speed-up! Amdahl’s law ­suggests how difficult it is to reach either peak; multiplying the two together multiplies the sins. The roofline model helps put peak performance in perspective. Pitfall: Not developing the software to take advantage of, or optimize for, a multi­ processor architecture. There is a long history of software lagging behind on parallel processors, possibly because the software problems are much harder. We give one example to show the subtlety of the issues, but there are many examples we could choose! One frequently encountered problem occurs when software designed for a uni­processor is adapted to a multiprocessor environment. For example, the SGI ­oper­ating system originally protected the page table with a single lock, assum­ ing that page allocation is infrequent. In a uniprocessor, this does not represent a perfor­mance problem. In a multiprocessor, it can become a major performance bottle­neck for some programs. Consider a program that uses a large number of pages that are initialized at start-up, which UNIX does for statically allocated pages. Suppose the program is parallelized so that multiple processes allocate the pages. Because page allocation requires the use of the page table, which is locked when­ ever it is in use, even an OS kernel that allows multiple threads in the OS will be serialized if the processes all try to allocate their pages at once (which is exactly what we might expect at initialization time!). This page table serialization eliminates parallelism in initialization and has sig­nificant impact on overall parallel performance. This performance bottleneck persists even for job-level parallelism. For example, suppose we split the parallel processing program apart into separate jobs and run them, one job per processor, so that there is no sharing between the jobs. (This is exactly what one user did, since he reasonably believed that the performance problem was due to unin­tended sharing or interference in his application.) Unfortunately, the lock still serializes all the jobs—so even the independent job performance is poor. This pitfall indicates the kind of subtle but significant performance bugs that can arise when software runs on multiprocessors. Like many other key software components, the OS algorithms and data structures must be rethought in a multi­ processor context. Placing locks on smaller portions of the page table effectively eliminates the problem. 7.12 Fallacies and Pitfalls 685
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686 Chapter 7 Multicores, Multiprocessors, and Clusters 7.13 Concluding Remarks The dream of building computers by simply aggregating processors has been around since the earliest days of computing. Progress in building and using effec­ tive and efficient parallel processors, however, has been slow. This rate of progress has been limited by difficult software problems as well as by a long process of evolv­ ing the architecture of multiprocessors to enhance usability and improve effi­ciency. We have discussed many of the software challenges in this chapter, includ­ing the difficulty of writing programs that obtain good speed-up due to Amdahl’s law. The wide variety of different architectural approaches and the limited success and short life of many of the parallel architectures of the past have compounded the software difficulties. We discuss the history of the development of these multi­processors in Section 7.14 on the CD. As we said in Chapter 1, despite this long and checkered past, the information technology industry has now tied its future to parallel computing. Although it is easy to make the case that this effort will fail like many in the past, there are rea­sons to be hopeful: ■ ■Clearly, software as a service is growing in importance, and clusters have proven to be a very successful way to deliver such services. By providing redun­ dancy at a higher-level, including geographically distributed ­datacenters, such services have delivered 24 × 7 × 365 availability for customers around the world. It’s hard not to imagine that both the number of servers per ­datacenter and the number of datacenters will continue to grow. Certainly, such ­datacenters will embrace multicore designs, since they can already use thou­sands of processors in their applications. ■ ■The use of parallel processing in domains such as scientific and engineering computation is popular. This application domain has an almost limitless thirst for more computation. It also has many applications that have lots of natural concurrency. Once again, clusters dominate this application area. For example, using the 2007 Linpack report, clusters represent more than 80% of the 500 fastest computers. Nonetheless, it has not been easy: programming parallel processors even for these applications remains challenging. Yet this group too will surely embrace multicore chips, since again they have experience with hundreds to thousand of processors. ■ ■All desktop and server microprocessor manufacturers are building multi­ processors to achieve higher performance, so unlike the past, there is no easy We are dedicating all of our future product development to multicore designs. We believe this is a key inflection point for the industry. ... This is not a race. This is a sea change in computing...” Paul Otellini, Intel President, Intel Developers Forum, 2004. software as a service Rather than selling software that is installed and run on customers own computers, software is run at a remote site and made avail­able over the Internet typically via a Web interface to custom­ers. Customers are charged based on use.
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path to higher performance for sequential applications. Hence, ­program­mers who need higher performance must parallelize their codes or write new ­parallel processing programs. ■ ■Multiple processors on the same chip allow a very different speed of commu­ nication than multiple chip designs, offering both much lower latency and much higher bandwidth. These improvements may make it easier to deliver good performance. ■ ■In the past, microprocessors and multiprocessors were subject to different definitions of success. When scaling uniprocessor performance, micropro­ cessor architects were happy if single thread performance went up by the square root of the increased silicon area. Thus, they were happy with sublin­ ear performance in terms of resources. Multiprocessor success used to be defined as linear speed-up as a function of the number of processors, assum­ ing that the cost of purchase or cost of administration of n processors was n times as much as one processor. Now that parallelism is happening on-chip via multicore, we can use the traditional microprocessor of being suc­cessful with sublinear performance improvement. ■ ■The success of just-in-time runtime compilation makes it feasible to think of software adapting itself to take advance of the increasing number of cores per chip, which provides flexibility that is not available when limited to static compilers. ■ ■Unlike in the past, the open source movement has become a critical portion of the software industry. This movement is a meritocracy, where better engi­ neering solutions can win the mind share of the developers over legacy con­cerns. It also embraces innovation, inviting change to old software and welcoming new languages and software products. Such an open culture could be extremely helpful in this time of rapid change. This revolution in the hardware/software interface is perhaps the greatest chal­ lenge facing the field in the last 50 years. It will provide many new research and business opportunities inside and outside the IT field, and the companies that dominate the multicore era may not be the same ones that dominated the unipro­ cessor era. Perhaps you will be one of the innovators who will seize the opportunities that are sure to appear in the uncertain times ahead. 7.13 Concluding Remarks 687
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688 Chapter 7 Multicores, Multiprocessors, and Clusters 7.14  Historical Perspective and Further Reading This section on the CD gives the rich and often disastrous history of multiproces­ sors over the last 50 years. 7.15 Exercises Contributed by David Kaeli of Northeastern University Exercise 7.1 First, write down a list of your daily activities that you typically do on a weekday. For instance, you might get out of bed, take a shower, get dressed, eat breakfast, dry your hair, brush your teeth, etc. Make sure to break down your list so you have a minimum of 10 activities. 7.1.1 [5] <7.2> Now consider which of these activities is already exploiting some form of parallelism (e.g., brushing multiple teeth at the same time, versus one at a time, carrying one book at a time to school, versus loading them all into your backpack and then carry them “in parallel”). For each of your activities, discuss if they are already working in parallel, but if not, why they are not. 7.1.2 [5] <7.2> Next, consider which of the activities could be carried out con­ currently (e.g., eating breakfast and listening to the news). For each of your activi­ ties, describe which other activity could be paired with this activity. 7.1.3 [5] <7.2> For 7.1.2, what could we change about current systems (e.g., showers, clothes, TVs, cars) so that we could perform more tasks in parallel? 7.1.4 [5] <7.2> Estimate how much shorter time it would take to carry out these activities if you tried to carry out as many tasks in parallel as possible. Exercise 7.2 Many computer applications involve searching through a set of data and sorting the data. A number of efficient searching and sorting algorithms have been devised in order to reduce the runtime of these tedious tasks. In this problem we will consider how best to parallelize these tasks.
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7.2.1 [10] <7.2> Consider the following binary search algorithm (a classic divide and conquer algorithm) that searches for a value X in an sorted N-element array A and returns the index of matched entry: BinarySearch(A[0..N-1], X) { low = 0 high = N - 1 while (low <= high) { mid = (low + high) / 2 if (A[mid] > X) high = mid - 1 else if (A[mid] < X) low = mid + 1 else return mid // found } return -1 // not found } Assume that you have Y cores on a multi-core processor to run BinarySearch. Assuming that Y is much smaller than N, express the speedup factor you might expect to obtain for values of Y and N. Plot these on a graph. 7.2.2 [5] <7.2> Next, assume that Y is equal to N. How would this affect your conclusions in your previous answer? If you were tasked with obtaining the best speedup factor possible (i.e., strong scaling), explain how you might change this code to obtain it. Exercise 7.3 Consider the following piece of C code: for (j=2;j<1000;j++) D[j] = D[j-1]+D[j-2]; The MIPS code corresponding to the above fragment is: DADDIU r2,r2,999 loop: L.D f1, -16(f1) L.D f2, -8(f1) ADD.D f3, f1, f2 S.D f3, 0(r1) DADDIU r1, r1, 8 BNE r1, r2, loop 7.15 Exercises 689
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690 Chapter 7 Multicores, Multiprocessors, and Clusters Instructions have the following associated latencies (in cycles): ADD.D L.D S.D DADDIU 4 6 1 2 7.3.1 [10] <7.2> How many cycles does it take for all instructions in a single iteration of the above loop to execute? 7.3.2 [10] <7.2> When an instruction in a later iteration of a loop depends upon a data value produced in an earlier iteration of the same loop, we say that there is a loop carried dependence between iterations of the loop. Identify the loop-­carried dependences in the above code. Identify the dependent program variable and assembly-level registers. You can ignore the loop induction variable j. 7.3.3 [10] <7.2> Loop unrolling was described in Chapter 4. Apply loop unroll­ ing to this loop and then consider running this code on a 2-node distributed mem­ ory message passing system. Assume that we are going to use message passing as described in Section 7.4, where we introduce a new operation send (x, y) that sends to node x the value y, and an operation receive( ) that waits for the value being sent to it. Assume that send operations take a cycle to issue (i.e., later instructions on the same node can proceed on the next cycle), but take 10 cycles be received on the receiving node. Receive instructions stall execution on the node where they are executed until they receive a message. Produce a schedule for the two nodes assuming an unroll factor of 4 for the loop body (i.e., the loop body will appear 4 times). Compute the number of cycles it will take for the loop to run on the message passing system. 7.3.4 [10] <7.2> The latency of the interconnect network plays a large role in the efficiency of message passing systems. How fast does the interconnect need to be in order to obtain any speedup from using the distributed system described in 7.3.3? Exercise 7.4 Consider the following recursive mergesort algorithm (another classic divide and conquer algorithm). Mergesort was first described by John Von Neumann in 1945. The basic idea is to divide an unsorted list x of m elements into two sublists of about half the size of the original list. Repeat this operation on each sublist, and continue until we have lists of size 1 in length. Then starting with sublists of length 1, “merge” the two sublists into a single sorted list. Mergesort(m) var list left, right, result if length(m) ≤ 1 return m
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else var middle = length(m) / 2 for each x in m up to middle add x to left for each x in m after middle add x to right left = Mergesort(left) right = Mergesort(right) result = Merge(left, right) return result The merge step is carried out by the following code: Merge(left,right) var list result while length(left) > 0 and length(right) > 0 if first(left) ≤ first(right) append first(left) to result left = rest(left) else append first(right) to result right = rest(right) if length(left) > 0 append rest(left) to result if length(right) > 0 append rest(right) to result return result 7.4.1 [10] <7.2> Assume that you have Y cores on a multi-core processor to run MergeSort. Assuming that Y is much smaller than length(m), express the speedup factor you might expect to obtain for values of Y and length(m). Plot these on a graph. 7.4.2 [10] <7.2> Next, assume that Y is equal to length(m). How would this affect your conclusions your previous answer? If you were tasked with obtaining the best speedup factor possible (i.e., strong scaling), explain how you might change this code to obtain it. Exercise 7.5 You are trying to bake 3 blueberry pound cakes. Cake ingredients are as follows: 1 cup butter, softened 1 cup sugar 7.15 Exercises 691
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692 Chapter 7 Multicores, Multiprocessors, and Clusters 4 large eggs 1 teaspoon vanilla extract 1/2 teaspoon salt 1/4 teaspoon nutmeg 1 1/2 cups flour 1 cup blueberries The recipe for a single cake is as follows: Step 1: Preheat oven to 325°F (160°C). Grease and flour your cake pan. Step 2: In large bowl, beat together with a mixer butter and sugar at medium speed until light and fluffy. Add eggs, vanilla, salt and nutmeg. Beat until thoroughly blended. Reduce mixer speed to low and add flour, 1/2 cup at a time, beating just until blended. Step 3: Gently fold in blueberries. Spread evenly in prepared baking pan. Bake for 60 minutes. 7.5.1 [5] <7.2> Your job is to cook 3 cakes as efficiently as possible. Assuming that you only have one oven large enough to hold one cake, one large bowl, one cake pan, and one mixer, come up with a schedule to make three cakes as quickly as possible. Identify the bottlenecks in completing this task. 7.5.2 [5] <7.2> Assume now that you have three bowls, 3 cake pans and 3 mixers. How much faster is the process now that you have additional resources? 7.5.3 [5] <7.2> Assume now that you have two friends that will help you cook, and that you have a large oven that can accommodate all three cakes. How will this change the schedule you arrived at in 7.5.1 above? 7.5.4 [5] <7.2> Compare the cake-making task to computing 3 iterations of a loop on a parallel computer. Identify data-level parallelism and task-level ­parallelism in the cake-making loop. Exercise 7.6 Matrix multiplication plays an important role in a number of applications. Two matrices can only be multiplied if the number of columns of the first matrix is equal to the number of rows in the second. Let’s assume we have an m × n matrix A and we want to multiply it by an n × p matrix B. We can express their product as an m × p matrix denoted by AB (or A · B). If we assign C = AB, and ci,j denotes the entry in C at position (i, j), then ci,j = ​ r = 1 ​ n ​ai, rbr,j = ai, 1b1,j + ai,2b2,j + … + ai,nbn,j​
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for each element i and j with 1 ≤ i ≤ m and 1 ≤ j ≤ p. Now we want to see if we can parallelize the computation of C. Assume that matrices are laid out in memory sequentially as follows: a1,1, a2,1, a3,1, a4,1, …, etc.. 7.6.1 [10] <7.3> Assume that we are going to compute C on both a single core shared memory machine and a 4-core shared-memory machine. Compute the speedup we would expect to obtain on the 4-core machine, ignoring any memory issues. 7.6.2 [10] <7.3> Repeat 7.6.1, assuming that updates to C incur a cache miss due to false sharing when consecutive elements are in a row (i.e., index i) are updated. 7.6.3 [10] <7.3> How would you fix the false sharing issue that can occur? Exercise 7.7 Consider the following portions of two different programs running at the same time on four processors in a symmetric multi-core processor (SMP). Assume that before this code is run, both x and y are 0. Core 1: x = 2; Core 2: y = 2; Core 3: w = x + y + 1; Core 4: z = x + y; 7.7.1 [10] <7.3> What are all the possible resulting values of w, x, y, and z? For each possible outcome, explain how we might arrive at those values. You will need to examine all possible interleavings of instructions. 7.7.2 [5] <7.3> How could you make the execution more deterministic so that only one set of values is possible? Exercise 7.8 In a CC-NUMA shared memory system, CPUs and physical memory are divided across compute nodes. Each CPU has local caches. To maintain the coherency of memory, we can add status bits into each cache block, or we can introduce dedi­ cated memory directories. Using directories, each node provides a dedicated hard­ ware table for managing the status of every block of memory that is “local” to that node. The size of each directory is a function of the size of the CC-NUMA shared space (an entry is provided for each block of memory local to a node). If we store coherency information in the cache, we add this information to every cache in every system (i.e., the amount of storage space is a function of the number of cache lines available in all caches). 7.15 Exercises 693
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694 Chapter 7 Multicores, Multiprocessors, and Clusters In the following proplems, assume that all nodes have the same number of CPUs and the same amount memory (i.e., CPUs and memory are evenly divided between the nodes of the CC-NUMA machine). 7.8.1 [15] <7.3> If we have P CPU in the system, with T nodes in the CC- NUMA system, with each CPU having C memory blocks stored in it, and we maintain a byte of coherency information in each cache line, provide an equation that expresses the amount of memory that will be present in the caches in a single node of the system to maintain coherency. Do not include the actual data storage space consumed in this equation, only account for space used to store coherency information. 7.8.2 [15] <7.3>If each directory entry maintains a byte of information for each CPU, if our CC-NUMA system has S memory blocks, and the system has T nodes, provide an equation that expresses the amount of memory that will be present in each directory. Exercise 7.9 Considering the CC-NUMA system described in the Exercise 7.8, assume that the system has 4 nodes, each with a single-core CPU (each CPU has its own L1 data cache and L2 data cache). The L1 data cache is store-through, though the L2 data cache is write-back. Assume that system has a workload where one CPU writes to an address, and the other CPUs all read that data that is written. Also assume that the address written to is initially only in memory and not in any local cache. Also, after the write, assume that the updated block is only present in the L1 cache of the core performing the write. 7.9.1 [10] <7.3> �For a system that maintains coherency using cache-based block status, describe the inter-node traffic that will be generated as each of the 4 cores writes to a unique address, after which each address written to is read from by each of the remaining 3 cores. 7.9.2 [10] <7.3> �For a directory-based coherency mechanism, describe the inter- node traffic generated when executing the same code pattern. � 7.9.3 [20] <7.3> Repeat 7.9.1 and 7.9.2 assuming that each CPU is now a multi- core CPU, with 4 cores per CPU, each maintaining an L1 data cache, but provided with a shared L2 data cache across the 4 cores. Each core will perform the write, followed by reads by each of the 15 other cores. 7.9.4 [10] <7.3> Consider the system described in 7.9.3, now assuming that each core writes to byte stored in the same cache block. How does this impact bus ­traffic? Explain.
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Exercise 7.10 On a CC-NUMA system, the cost of accessing non-local memory can limit our ability to utilize multiprocessing effectively. The following table shows the costs associated with access data in local memory versus non-local memory and the locality of our application expresses as the proportion of access that are local. Local load/store (cycle) Non-local load/store (cycles) % local accesses 25 200 20 Answer the following questions. Assume that memory accesses are evenly distrib­ uted through the application. Also, assume that only a single memory operation can be active during any cycle. State all assumptions about the ordering of local versus non-local memory operations. 7.10.1 [10] <7.3> If on average we need to access memory once every 75 cycles, what is impact on our application? 7.10.2 [10] <7.3> If on average we need to access memory once every 50 cycles, what is impact on our application? 7.10.3 [10] <7.3> If on average we need to access memory once every 100 cycles, what is impact on our application? Exercise 7.11 The dining philosopher’s problem is a classic problem of synchronization and con­ currency. The general problem is stated as philosophers sitting at a round table doing one of two things: eating or thinking. When they are eating, they are not thinking, and when they are thinking, they are not eating. There is a bowl of pasta in the center. A fork is placed in between each philosopher. The result is that each philosopher has one fork to her left and one fork to her right. Given the nature of eating pasta, the philosopher needs two forks to eat, and can only use the forks on her immediate left and right. The philosophers do not speak to one another. 7.11.1 [10] <7.4> Describe the scenario where none of philosophers ever eats (i.e., starvation). What is the sequence of events that happen that lead up to this problem? 7.11.2 [10] <7.4> Describe how we can solve this problem by introducing the concept of a priority? But can we guarantee that we will treat all the philosophers fairly? Explain. Now assume we hire a waiter who is in charge of assigning forks to philosophers. Nobody can pick up a fork until the waiter says they can. The waiter has global 7.15 Exercises 695
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696 Chapter 7 Multicores, Multiprocessors, and Clusters knowledge of all forks. Further, if we impose the policy that philosophers will always request to pick up their left fork before requesting to pick up their right fork, then we can guarantee to avoid deadlock. 7.11.3 [10] <7.4> �We can implement requests to the waiter as either a queue of requests or as a periodic retry of a request. With a queue, requests are handled in the order they are received. The problem with using the queue is that we may not always be able to service the philosopher whose request is at the head of the queue (due to the unavailability of resources). Describe a scenario with 5 philosophers where a queue is provided, but service is not granted even though there are forks available for another philosopher (whose request is deeper in the queue) to eat. 7.11.4 [10] <7.4> If we implement requests to the waiter by periodically repeat­ ing our request until the resources become available, will this solve the problem described in 7.11.3? Explain. Exercise 7.12 Consider the following three CPU organizations: CPU SS: A 2-core superscalar microprocessor that provides out-of-order issue capabilities on 2 function units (FUs). Only a single thread can run on each core at a time. CPU MT: A fine-grained multithreaded processor that allows instructions from 2 threads to be run concurrently (i.e., there are two functional units), though only instructions from a single thread can be issued on any cycle. CPU SMT: An SMT processor that allows instructions from 2 threads to be run concurrently (i.e., there are two functional units), and instructions from either or both threads can be issued to run on any cycle. Assume we have two threads X and Y to run on these CPUs that include the ­following operations: Thread X Thread Y A1 – takes 3 cycles to execute A2 – no dependencies A3 – conflicts for a functional unit with A1 A4 – depends on the result of A3 B1 – take 2 cycles to execute B2 – conflicts for a functional unit with B1 B3 – depends on the result of B2 B4 – no dependencies and takes 2 cycles to execute Assume all instructions take a single cycle to execute unless noted otherwise or they encounter a hazard. 7.12.1 [10] <7.5> Assume that you have 1 SS CPU. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards?
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7.12.2 [10] <7.5> Now assume you have 2 SS CPUs. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards? 7.12.3 [10] <7.5> Assume that you have 1 MT CPU. How many cycles will it take to execute these two threads? How many issue slots are wasted due to hazards? Exercise 7.13 Virtualization software is being aggressively deployed to reduce the costs of man­ aging today’s high performance servers. Companies like VMWare, Microsoft and IBM have all developed a range of virtualization products. The general concept, described in Chapter 5, is that a hypervisor layer can be introduced between the hardware and the operating system to allow multiple operating systems to share the same physical hardware. The hypervisor layer is then responsible for allocating CPU and memory resources, as well as handling services typically handled by the operating system (e.g., I/O). Virtualization provides an abstract view of the underlying hardware to the hosted operating system and application software. This will require us to rethink how multi-core and multiprocessor systems will be designed in the future to support the sharing of CPUs and memories by a number of operating systems concurrently. 7.13.1 [30] <7.5> Select two hypervisors on the market today, and compare and contrast how they virtualize and manage the underlying hardware (CPUs and memory). 7.13.2 [15] <7.5> Discuss what changes may be necessary in future multi-core CPU platforms in order to better match the resource demands placed on these systems. For instance, can multi-threading play an effective role in alleviating the competition for computing resources? Exercise 7.14 We would like to execute the loop below as efficiently as possible. We have two dif­ ferent machines, a MIMD machine and a SIMD machine. for (i=0; i < 2000; i++) for (j=0; j<3000; j++) X_array[i][j] = Y_array[j][i] + 200; 7.14.1 [10] <7.6> For a 4 CPU MIMD machine, show the sequence of MIPS instructions that you would execute on each CPU. What is the speedup for this MIMD machine? 7.15 Exercises 697
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698 Chapter 7 Multicores, Multiprocessors, and Clusters 7.14.2 [20] <7.6> For an 8-wide SIMD machine (i.e., 8 parallel SIMD functional units), write an assembly program in using your own SIMD extensions to MIPS to execute the loop. Compare the number of instructions executed on the SIMD machine to the MIMD machine. Exercise 7.15 A systolic array is an example of an MISD machine. A systolic array is a pipeline network or “wavefront” of data processing elements. Each of these elements does not need a program counter since execution is triggered by the arrival of data. Clocked systolic arrays compute in “lock-step” with each processor undertaking alternate compute and communication phases. 7.15.1 [10] <7.6> Consider proposed implementations of a systolic array (you can find these in on the Internet or in technical publications). Then attempt to program the loop provided in Exercise 7.14 using this MISD model. Discuss any difficulties you encounter. 7.15.2 [10] <7.6> Discuss the similarities and differences between an MISD and SIMD machine. Answer this question in terms of data-level parallelism. Exercise 7.16 Assume we want to execute the DAXP loop show on page 651 in MIPS assembly on the NVIDIA 8800 GTX GPU described in this Chapter. In this problem, we will assume that all math operations are performed on single-precision floating-point numbers (we will rename the loop SAXP). Assume that instructions take the fol­ lowing number of cycles to execute. Loads Stores Add.S Mult.S 5 2 3 4 7.16.1 [20] <7.7> Describe how you will constructs warps for the SAXP loop to exploit the 8 cores provided in a single multiprocessor. Exercise 7.17 Download the CUDA Toolkit and SDK from http://www.nvidia.com/object/cuda_ get.html. Make sure to use the “emurelease” (Emulation Mode) version of the code (you will not need actual NVIDIA hardware for this assignment). Build the exam­ ple programs provided in the SDK, and confirm that they run on the emulator.
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7.17.1 [90] <7.7> Using the “template” SDK sample as a starting point, write a CUDA program to perform the following vector operations: 1) a − b (vector-vector subtraction) 2) a · b (vector dot product) The dot product of two vectors a = [a1, a2, … , an] and b = [b1, b2, … , bn] is defined as: a · b = ​ i = 1 ​ n ​aibi = a1b1 + a2b2 + … + anbn​ Submit code for each program that demonstrates each operation and verifies the correctness of the results. 7.17.2 [90] <7.7> If you have GPU hardware available, complete a performance analysis your program, examining the computation time for the GPU and a CPU version of your program for a range of vector sizes. Explain any results you see. Exercise 7.18 AMD has recently announced that they will be integrating a graphics processing unit with their X86 cores in a single package, though with different clocks for each of the cores. This is an example of a heterogeneous multiprocessor system which we expect to see produced commericially in the near future. One of the key design points will be to allow for fast data communication between the CPU and the GPU. Presently communications must be performed between discrete CPU and GPU chips. But this is changing in AMDs Fusion architecture. Presently the plan is to use multiple (at least 16) PCI express channels for facilitate intercommunication. Intel is also jumping into this arena with their Larrabee chip. Intel is considering to use their QuickPath interconnect technology. 7.18.1 [25] <7.7> Compare the bandwidth and latency associated with these two interconnect technologies. Exercise 7.19 Refer to Figure 7.7b that shows an n-cube interconnect topology of order 3 that interconnects 8 nodes. One attractive feature of an n-cube interconnection net­ work topology is its ability to sustain broken links and still provide connectivity. 7.19.1 [10] <7.8> Develop an equation that computes how many links in the n-cube (where n is the order of the cube) can fail and we can still guarantee an unbroken link will exist to connect any node in the n-cube. 7.15 Exercises 699
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700 Chapter 7 Multicores, Multiprocessors, and Clusters 7.19.2 [10] <7.8> Compare the resiliency to failure of n-cube to a fully-­connected interconnection network. Plot a comparison of reliability as a function of the added number of links for the two topologies. Exercise 7.20 Benchmarking is field of study that involves identifying representative workloads to run on specific computing platforms in order to be able to objectively compare performance of one system to another. In this exercise we will compare two classes of benchmarks: the Whetstone CPU benchmark and the PARSEC Benchmark suite. Select one program from PARSEC. All programs should be freely available on the Internet. Consider running multiple copies of Whetstone versus running the PARSEC Benchmark on any of systems described in Section 7.11. 7.20.1 [60] <7.9> What is inherently different between these two classes of work­ load when run on these multi-core systems? 7.20.2 [60] <7.9, 7.10> In terms of the Roofline Model, how dependent will the results you obtain when running these benchmarks be on the amount of sharing and synchronization present in the workload used? Exercise 7.21 When performing computations on sparse matrices, latency in the memory hierar­ chy becomes much more of a factor. Sparse matrices lack the spatial locality in the data stream typically found in matrix operations. As a result, new matrix represen­ tations have been proposed. One the earliest sparse matrix representations is the Yale Sparse Matrix Format. It stores an initial sparse m×n matrix, M in row form using three one-dimensional arrays. Let R be the number of nonzero entries in M. We construct an array A of length R that contains all nonzero entries of M (in left-to-right top-to-bottom order). We also construct a second array IA of length m + 1 (i.e., one entry per row, plus one). IA(i) contains the index in A of the first nonzero element of row i. Row i of the original matrix extends from A(IA(i)) to A(IA(i+1)–1). The third array, JA, contains the column index of each element of A, so it also is of length R. 7.21.1 [15] <7.9> Consider the sparse matrix X below and write C code that would store this code in Yale Sparse Matrix Format. Row 1 [1, 2, 0, 0, 0, 0] Row 2 [0, 0, 1, 1, 0, 0] Row 3 [0, 0, 0, 0, 9, 0] Row 4 [2, 0, 0, 0, 0, 2] Row 5 [0, 0, 3, 3, 0, 7] Row 6 [1, 3, 0, 0, 0, 1]
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7.21.2 [10] <7.9> In terms of storage space, assuming that each element in matrix X is single precision floating point, compute the amount of storage used to store the Matrix above in Yale Sparse Matrix Format. 7.21.3 [15] <7.9> Perform matrix multiplication of Matrix X by Matrix Y shown below. [2, 4, 1, 99, 7, 2] Put this computation in a loop, and time its execution. Make sure to increase the number of times this loop is executed to get good resolution in your timing mea­ surement. Compare the runtime of using a naïve representation of the matrix, and the Yale Sparse Matrix Format. 7.21.4 [15] <7.9> Can you find a more efficient sparse matrix representation (in terms of space and computational overhead)? Exercise 7.22 In future systems, we expect to see heterogeneous computing platforms con­ structed out of heterogeneous CPUs. We have begun to see some appear in the embedded processing market in systems that contain both floating point DSPs and a microcontroller CPUs in a multichip module package. Assume that you have three classes of CPU: CPU A—A moderate speed multi-core CPU (with a floating point unit) that can execute multiple instructions per cycle. CPU B—A fast single-core integer CPU (i.e., no floating point unit) that can exe­ cute a single instruction per cycle. CPU C—A slow vector CPU (with floating point capability) that can execute mul­ tiple copies of the same instruction per cycle. Assume that our processors run at the following frequencies: CPU A CPU B CPU C 1 GHz 3 GHz 250 MHz CPU A can execute 2 instructions per cycle, CPU B can execute 1 instruction per cycle, and CPU C can execute 8 instructions (though the same instruction) per cycle. Assume all operations can complete execution in a single cycle of latency without any hazards. 7.15 Exercises 701
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702 Chapter 7 Multicores, Multiprocessors, and Clusters All three CPUs have the ability to perform integer arithmetic, though CPU B can­ not perform floating point arithmetic. CPU A and B have an instruction set similar to a MIPS processor. CPU C can only perform floating point add and subtract operations, as well as memory loads and stores. Assume all CPUs have access to shared memory and that synchronization has zero cost. The task at hand is to compare two matrices X and Y that each contain 1024 × 1024 floating point elements. The output should be a count of the number indices where the value in X was larger or equal to the value in Y. 7.22.1 [10] <7.11> Describe how you would partition the problem on the 3 dif­ ferent CPUs to obtain the best performance. 7.22.2 [10] <7.11> What kind of instruction would you add to the vector CPU C to obtain better performance? Exercise 7.23 Assume a quad-core computer system can process database queries at a steady state rate of requests per second. Also assume that each transaction takes, on average, a fixed amount of time to process. The following table shows pairs of transaction latency and processing rate. Average Transaction Latency Maximum transaction processing rate 1 ms 5000/sec 2 ms 5000/sec 1 ms 10,000/sec 2 ms 10,000/sec For each of the pairs in the table, answer the following questions: 7.23.1 [10] <7.11> On average, how many requests are being processed at any given instant? 7.23.2 [10] <7.11> If move to an 8-core system, ideally, what will happen to the system throughput (i.e., how many queries/second will the computer process)? 7.22.3 [10] <7.11> Discuss why we rarely obtain this kind of speedup by simply increasing the number of cores.
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