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§7.1, page 634: False. Job-level parallelism can help sequential applications and sequential applications can be made to run on parallel hardware, although it is more challenging. §7.2, page 638: False. Weak scaling can compensate for a serial portion of the program that would otherwise limit scalability. §7.3, page 64... | Hennesey_Page_701_Chunk701 |
A Imagination is more important than knowledge. Albert Einstein On Science, 1930s Graphics and Computing GPUs John Nickolls Director of Architecture NVIDIA David Kirk Chief Scientist NVIDIA A P P E N D I X | Hennesey_Page_702_Chunk702 |
A.1 Introduction A-3 A.2 GPU System Architectures A-7 A.3 Programming GPUs A-12 A.4 Multithreaded Multiprocessor Architecture A-25 A.5 Parallel Memory System A-36 A.6 Floating-point Arithmetic A-41 A.7 Real Stuff: The NVIDIA GeForce 8800 A-46 A.8 Real Stuff: Mapping Applications to GPUs A-55 A.9 Fallacies and Pitfalls... | Hennesey_Page_703_Chunk703 |
hardware for triangle setup and rasterization (dicing triangles into individual pixels) and texture mapping and shading (applying “decals” or patterns to pixels and blending colors). In 2000, the single chip graphics processor incorporated almost every detail of the traditional high-end workstation graphics pipeline an... | Hennesey_Page_704_Chunk704 |
soon to be manycore, is a complementary, primarily serial processor companion to the massively parallel manycore GPU. Together, these two types of processors comprise a heterogeneous multiprocessor system. The best performance for many applications comes from using both the CPU and the GPU. This appendix will help you ... | Hennesey_Page_705_Chunk705 |
GPU Unifies Graphics and Computing With the addition of CUDA and GPU computing to the capabilities of the GPU, it is now possible to use the GPU as both a graphics processor and a computing processor at the same time, and to combine these uses in visual computing applications. The underlying processor architecture of t... | Hennesey_Page_706_Chunk706 |
that is desired. So, all applications are now possible, which will stimulate new visual computing approaches. A.2 GPU System Architectures In this section, we survey GPU system architectures in common use today. We discuss system configurations, GPU functions and services, standard programming interfaces, and a basic G... | Hennesey_Page_707_Chunk707 |
A-8 Appendix A Graphics and Computing GPUs as a VGA (video graphics array) which was attached to the PCI bus. Graphics subsystems with built-in processing elements (GPUs) did not exist in the PC landscape of 1990. Figure A.2.2 illustrates two configurations in common use today. These are characterized by a separate GPU... | Hennesey_Page_708_Chunk708 |
is attached to the chipset, also via PCI-Express with the same available bandwidth. In both cases, the GPUs and CPUs may access each other’s memory, albeit with less available bandwidth than their access to the more directly attached memories. In the case of the AMD system, the north bridge or memory controller is inte... | Hennesey_Page_709_Chunk709 |
A-10 Appendix A Graphics and Computing GPUs Graphics Logical Pipeline The graphics logical pipeline is described in Section A.3. Figure A.2.3 illustrates the major processing stages, and highlights the important programmable stages (vertex, geometry, and pixel shader stages). FIGURE A.2.3 Graphics logical pipeline. Pro... | Hennesey_Page_710_Chunk710 |
processor cores. By using many simpler cores and optimizing for data-parallel behavior among groups of threads, more of the per-chip transistor budget is devoted to computation, and less to on-chip caches and overhead. Processor Array A unified GPU processor array contains many processor cores, typically organized into... | Hennesey_Page_711_Chunk711 |
A-12 Appendix A Graphics and Computing GPUs The processor array architecture is scalable to smaller and larger GPU configu rations by scaling the number of multiprocessors and the number of memory partitions. Figure A.2.5 shows seven clusters of two SMs sharing a texture unit and a texture L1 cache. The texture unit d... | Hennesey_Page_712_Chunk712 |
vertex or one pixel. It has remained an effective paradigm as GPUs have rapidly increased their parallelism and performance since the late 1990s. This section briefly describes programming GPUs for real-time graphics applications using graphics APIs and programming languages. It then describes programming GPUs for visu... | Hennesey_Page_713_Chunk713 |
A-14 Appendix A Graphics and Computing GPUs including transforming the vertex 3D position into a screen position and lighting the vertex to determine its color. The geometry shader program executes per-primitive processing and can add or drop primitives. The setup and rasterizer unit generates pixel fragments (fragment... | Hennesey_Page_714_Chunk714 |
access, pointers, file I/O, and recursion. HLSL and Cg assume that programs live within a logical graphics pipeline, and thus I/O is implicit. For example, a pixel fragment shader may expect the geometric normal and multiple texture coordinates to have been interpolated from vertex values by upstream fixed-function sta... | Hennesey_Page_715_Chunk715 |
A-16 Appendix A Graphics and Computing GPUs Although this shader program is only three lines long, it activates a lot of GPU hardware. For each texture fetch, the GPU texture subsystem makes multiple memory accesses to sample image colors in the vicinity of the sampling coordinates, and then interpolates the final resu... | Hennesey_Page_716_Chunk716 |
The compiled Cg shader executes 1400 instructions to compute the color of one skin pixel. As GPUs have evolved superior floating-point performance and very high streaming memory bandwidth for real-time graphics, they have attracted highly parallel applications beyond traditional graphics. At first, access to this power... | Hennesey_Page_717_Chunk717 |
A-18 Appendix A Graphics and Computing GPUs that many sophisticated programs can be readily expressed with a few easily understood abstractions. Since NVIDIA released CUDA in 2007, developers have rapidly developed scalable parallel programs for a wide range of applications, including seismic data processing, computati... | Hennesey_Page_718_Chunk718 |
A.3 Programming GPUs A-19 The CUDA Paradigm CUDA is a minimal extension of the C and C++ programming languages. The programmer writes a serial program that calls parallel kernels, which may be simple functions or full programs. A kernel executes in parallel across a set of parallel threads. The programmer organizes the... | Hennesey_Page_719_Chunk719 |
A-20 Appendix A Graphics and Computing GPUs Parallel execution and thread management is automatic. All thread creation, scheduling, and termination is handled for the programmer by the underlying sys- tem. Indeed, a Tesla architecture GPU performs all thread management directly in hardware. The threads of a block execu... | Hennesey_Page_720_Chunk720 |
into threads and thread blocks allows intuitive problem decompositions, as the number of blocks can be dictated by the size of the data being processed rather than by the number of processors in the system. It also allows the same CUDA program to scale to widely varying numbers of processor cores. To manage this proce... | Hennesey_Page_721_Chunk721 |
A-22 Appendix A Graphics and Computing GPUs The CUDA programming model is similar in style to the familiar single-program multiple data (SPMD) model—it expresses parallelism explicitly, and each kernel executes on a fixed number of threads. However, CUDA is more flexible than most realizations of SPMD, because each ke... | Hennesey_Page_722_Chunk722 |
coarse-grained data parallelism. Independent grids express coarse-grained task parallelism. A kernel is simply C code for one thread of the hierarchy. Restrictions For efficiency, and to simplify its implementation, the CUDA programming model has some restrictions. Threads and thread blocks may only be created by invok... | Hennesey_Page_723_Chunk723 |
A-24 Appendix A Graphics and Computing GPUs with a simple scheduler that introduces minimal runtime overhead. In fact, the Tesla GPU architecture implements hardware management and scheduling of threads and thread blocks. Task parallelism can be expressed at the thread block level but is difficult to express within a t... | Hennesey_Page_724_Chunk724 |
A.4 Multithreaded Multiprocessor Architecture To address different market segments, GPUs implement scalable numbers of multiprocessors—in fact, GPUs are multiprocessors composed of multiprocessors. Furthermore, each multiprocessor is highly multithreaded to execute many fine- grained vertex and pixel shader threads e... | Hennesey_Page_725_Chunk725 |
A-26 Appendix A Graphics and Computing GPUs A graphics vertex or pixel shader program is a program for a single thread that processes a vertex or a pixel. Similarly, a CUDA program is a C program for a single thread that computes a result. Graphics and computing programs instantiate many parallel threads to render comp... | Hennesey_Page_726_Chunk726 |
The pipelined SFUs execute thread instructions that compute special functions and interpolate pixel attributes from primitive vertex attributes. These instructions can execute concurrently with instructions on the SPs. The SFU is described later. The multiprocessor executes texture fetch instructions on the texture uni... | Hennesey_Page_727_Chunk727 |
A-28 Appendix A Graphics and Computing GPUs SP cores over four clocks. The Tesla SM multiprocessor described in Section A.7 also uses a warp size of 32 parallel threads, executing four threads per SP core for efficiency on plentiful pixel threads and computing threads. Thread blocks consist of one or more warps. This e... | Hennesey_Page_728_Chunk728 |
to multiple data lanes. An instruction for a SIMD processor controls a vector of multiple data lanes together, whereas an instruction for a SIMT processor controls an individual thread, and the SIMT instruction unit issues an instruction to a warp of independent parallel threads for efficiency. The SIMT processor finds... | Hennesey_Page_729_Chunk729 |
programmer can ignore the pipeline latency. For this multiprocessor, a round-robin schedule of eight warps has a period of 32 cycles between successive instructions for the same warp. If the program can keep 256 threads active per multiprocessor, instruction latencies up to 32 cycles can be hidden from an individual se... | Hennesey_Page_730_Chunk730 |
generally compute (x, y, z, w) position vectors, while pixel shader programs compute (red, green, blue, alpha) color vectors. However, shader programs are becoming longer and more scalar, and it is increasingly difficult to fully occupy even two components of a legacy GPU four-component vector architecture. In effect, ... | Hennesey_Page_731_Chunk731 |
A-32 Appendix A Graphics and Computing GPUs Basic PTX GPU Thread Instructions Group Instruction Example Meaning Comments Arithmetic arithmetic .type = .s32, .u32, .f32, .s64, .u64, .f64 add.type add.f32 d, a, b d = a + b; sub.type sub.f32 d, a, b d = a – b; mul.type mul.f32 d, a, b d = a * b; mad.type mad.f32 d, a, b, ... | Hennesey_Page_732_Chunk732 |
Source operands are scalar 32-bit or 64-bit values in registers, an immediate value, or a constant; predicate operands are 1-bit Boolean values. Destinations are registers, except for store to memory. Instructions are predicated by prefixing them with @p or @!p, where p is a predicate register. Memory and texture instr... | Hennesey_Page_733_Chunk733 |
A-34 Appendix A Graphics and Computing GPUs To improve memory bandwidth and reduce overhead, the local and global load/ store instructions coalesce individual parallel thread requests from the same SIMT warp together into a single memory block request when the addresses fall in the same block and meet alignment criteri... | Hennesey_Page_734_Chunk734 |
Special Function Unit (SFU) Certain thread instructions can execute on the SFUs, concurrently with other thread instructions executing on the SPs. The SFU implements the special function instructions of Figure A.4.3, which compute 32-bit floating-point approximations to reciprocal, reciprocal square root, and key trans... | Hennesey_Page_735_Chunk735 |
Coupling eight streaming processor cores together closely into a multiprocessor and then implementing a scalable number of such multiprocessors makes a two- level multiprocessor composed of multiprocessors. The CUDA programming model exploits the two-level hierarchy by providing individual threads for fine-grained para... | Hennesey_Page_736_Chunk736 |
To supply these requirements, GPU memory systems have the following characteristics: ■ ■They are wide, meaning there are a large number of pins to convey data between the GPU and its memory devices, and the memory array itself comprises many DRAM chips to provide the full total data bus width. ■ ■They are fast, meaning... | Hennesey_Page_737_Chunk737 |
different DRAM banks, and wait until enough traffic for a particular DRAM row is pending before activating that row and transferring all the traffic at once. Note that accumulating pending requests, while good for DRAM row locality and thus efficient use of the data bus, leads to longer average latency as seen by the r... | Hennesey_Page_738_Chunk738 |
translation; hardware reads the page tables from local memory to respond to misses on behalf of a hierarchy of translation lookaside buffers spread out among the processors and rendering engines. In addition to physical page bits, GPU page table entries specify the compression algorithm for each page. Page sizes range ... | Hennesey_Page_739_Chunk739 |
A-40 Appendix A Graphics and Computing GPUs Each streaming multiprocessor contains eight physical thread processors. During one shared memory clock cycle, each thread processor can process two threads’ worth of instructions, so 16 threads’ worth of shared memory requests must be handled in each clock. Because each thre... | Hennesey_Page_740_Chunk740 |
Surfaces Surface is a generic term for a one-dimensional, two-dimensional, or three- dimensional array of pixel values and an associated format. A variety of formats are defined; for example, a pixel may be defined as four 8-bit RGBA integer components, or four 16-bit floating-point components. A program kernel does no... | Hennesey_Page_741_Chunk741 |
Some fixed-function logic within a GPU, such as texture-filtering hardware, continues to use proprietary numeric formats. Recent GPUs also provide IEEE 754 compatible double precision 64-bit floating-point instructions. Supported Formats The IEEE 754 standard for floating-point arithmetic [2008] specifies basic and st... | Hennesey_Page_742_Chunk742 |
sine, binary exponential, binary logarithm, reciprocal, and reciprocal square root. Attribute interpolation instructions provide efficient generation of pixel attributes, derived from plane equation evaluation. The special function unit (SFU) introduced in Section A.4 computes special functions and interpolates planar ... | Hennesey_Page_743_Chunk743 |
A-44 Appendix A Graphics and Computing GPUs values of the attributes at each pixel location. The value of a given attribute U in an (x,y) plane can be expressed using plane equations of the form: U(x,y) = Aux + Buy + Cu where A, B, and C are interpolation parameters associated with each attribute U. The interpolation p... | Hennesey_Page_744_Chunk744 |
Double precision Newer GPUs such as the Tesla T10P also support IEEE 754 64-bit double precision operations in hardware. Standard floating-point arithmetic operations in double precision include addition, multiplication, and conversions between different floating-point and integer formats. The 2008 IEEE 754 floating-p... | Hennesey_Page_745_Chunk745 |
A-46 Appendix A Graphics and Computing GPUs precision FMA unit enables full-speed denormalized number support on both inputs and outputs. Figure A.6.2 shows a block diagram of an FMA unit. As shown in Figure A.6.2, the significands of A and B are multiplied to form a 106-bit product, with the results left in carry-save... | Hennesey_Page_746_Chunk746 |
Texture/Processor Cluster (TPC) Each TPC contains a geometry controller, an SM controller (SMC), two streaming multiprocessors (SMs), and a texture unit as shown in Figure A.7. 2. The geometry controller maps the logical graphics vertex pipeline into recir- culation on the physical SMs by directing all primitive and ve... | Hennesey_Page_747_Chunk747 |
A-48 Appendix A Graphics and Computing GPUs contains a streaming cache to capture filtering locality, it streams hits mixed with misses without stalling. Streaming Multiprocessor (SM) The SM is a unified graphics and computing multiprocessor that executes vertex, geometry, and pixel-fragment shader programs and paralle... | Hennesey_Page_748_Chunk748 |
To efficiently execute hundreds of parallel threads while running several different programs, the SM is hardware multithreaded. It manages and executes up to 768 concurrent threads in hardware with zero scheduling overhead. Each thread has its own thread execution state and can execute an independent code path. A warp ... | Hennesey_Page_749_Chunk749 |
add and multiply operations are compatible with the IEEE 754 standard for single precision FP numbers, including not-a-number (NaN) and infinity. The add and multiply operations use IEEE round-to-nearest-even as the default rounding mode. The SP core also implements all of the 32-bit and 64-bit integer arithmetic, comp... | Hennesey_Page_750_Chunk750 |
Antialiasing support includes up to 16× multisampling and supersampling. The coverage-sampling antialiasing (CSAA) algorithm computes and stores Boolean coverage at up to 16 samples and compresses redundant color, depth, and stencil information into the memory footprint and a bandwidth of four or eight samples for impr... | Hennesey_Page_751_Chunk751 |
FIGURE A.7.3 SGEMM dense matrix-matrix multiplication performance rates. The graph shows single precision GFLOPS rates achieved in multiplying square N×N matrices (solid lines) and thin N×64 and 64×N matrices (dashed lines). Adapted from Figure 6 of Volkov and Demmel [2008]. The black lines are a 1.35 GHz GeForce 8800 ... | Hennesey_Page_752_Chunk752 |
problem becomes large enough that SGEMM can leverage the GPU parallelism and overcome the CPU–GPU system and copy overhead. Volkov’s SGEMM matrix- matrix multiply achieves 206 GFLOPS, about 60% of the GeForce 8800 GTX peak multiply-add rate, while the QR factorization reached 192 GFLOPS, about 4.3 times the quad-core C... | Hennesey_Page_753_Chunk753 |
Sorting Performance In contrast to the applications just discussed, sort requires far more substantial coordination among parallel threads, and parallel scaling is correspondingly harder to obtain. Nevertheless, a variety of well-known sorting algorithms can be efficiently parallelized to run well on the GPU. Satish, e... | Hennesey_Page_754_Chunk754 |
from this graph that the GPU radix sort achieved the highest sorting rate for all sequences of 8K-elements and larger. In this range, it is on average 2.6 times faster than the quicksort-based routine and roughly 2 times faster than the radix sort rou- tines, all of which were using the eight available CPU cores. The ... | Hennesey_Page_755_Chunk755 |
Given a matrix A in CSR form and a vector x, we can compute a single row of the product y = Ax using the multiply_row() procedure shown in Figure A.8.2. Computing the full product is then simply a matter of looping over all rows and computing the result for that row using multiply_row(), as in the serial C code shown i... | Hennesey_Page_756_Chunk756 |
void csrmul_serial(unsigned int *Ap, unsigned int *Aj, float *Av, unsigned int num_rows, float *x, float *y) { for(unsigned int row=0; row<num_rows; ++row) { unsigned int row_begin = Ap[row]; unsigned int row_end = Ap[row+1]; y[row] = multiply_row(row_end-row_begin, Aj+row_begin, Av+row_begin, x); } } FIGURE A.8.3 Seri... | Hennesey_Page_757_Chunk757 |
A-58 Appendix A Graphics and Computing GPUs The pattern that we see here is a very common one. The original serial algorithm is a loop whose iterations are independent of each other. Such loops can be parallelized quite easily by simply assigning one or more iterations of the loop to each parallel thread. The programmi... | Hennesey_Page_758_Chunk758 |
__global__ void csrmul_cached(unsigned int *Ap, unsigned int *Aj, float *Av, unsigned int num_rows, const float *x, float *y) { // Cache the rows of x[] corresponding to this block. __shared__ float cache[blocksize]; unsigned int block_begin = blockIdx.x * blockDim.x; unsigned int block_end = block_begin + blockDim.x; ... | Hennesey_Page_759_Chunk759 |
These are fairly simple kernels whose purpose is to illustrate basic techniques in writing CUDA programs, rather than how to achieve maximal performance. Numerous possible avenues for optimization are available, several of which are explored by Williams, et al. [2007] on a handful of different multicore architectures. ... | Hennesey_Page_760_Chunk760 |
because addition is associative, we are free to change the order in which elements are added together. For instance, we can imagine adding pairs of consecutive elements in parallel, and then adding these partial sums, and so on. One simple scheme for doing this is from Hillis and Steele [1989]. An implementation of the... | Hennesey_Page_761_Chunk761 |
A-62 Appendix A Graphics and Computing GPUs While simple, this algorithm is not as efficient as we would like. Examining the serial implementation, we see that it performs O(n) additions. The parallel implementation, in contrast, performs O(n log n) additions. For this reason, it is not work efficient, since it does mo... | Hennesey_Page_762_Chunk762 |
__global__ void plus_reduce(int *input, unsigned int N, int *total) { unsigned int tid = threadIdx.x; unsigned int i = blockIdx.x*blockDim.x + threadIdx.x; // Each block loads its elements into shared memory, padding // with 0 if N is not a multiple of blocksize __shared__ int x[blocksize]; x[tid] = (i<N) ? input[i] : ... | Hennesey_Page_763_Chunk763 |
A-64 Appendix A Graphics and Computing GPUs all values with a 0 in the designated bit will come before all values with a 1 in that bit. To produce the correct output, this partitioning must be stable. Implementing the partitioning procedure is a simple application of scan. Thread i holds the value xi and must calculate... | Hennesey_Page_764_Chunk764 |
A similar strategy can be applied for implementing a radix sort kernel that sorts an array of large length, rather than just a one-block array. The fundamental step remains the scan procedure, although when the computation is partitioned across multiple kernels, we must double-buffer the array of values rather than doi... | Hennesey_Page_765_Chunk765 |
void accel_on_all_bodies() { int i, j; float3 acc(0.0f, 0.0f, 0.0f); for (i = 0; i < N; i++) { for (j = 0; j < N; j++) { acc = body_body_interaction(acc, body[i], body[j]); } accel[i] = acc; } } FIGURE A.8.12 Serial code to compute all pair-wise forces on N bodies. __global__ void accel_on_one_body() { int i = threadId... | Hennesey_Page_766_Chunk766 |
The outer loop is replaced by a CUDA kernel grid that launches N threads, one for each body. Optimization for GPU Execution The CUDA code shown is functionally correct, but is not efficient, as it ignores key architectural features. Better performance can be achieved with three main optimizations. First, shared memory ... | Hennesey_Page_767_Chunk767 |
The loop that formerly iterated over all bodies now jumps by the block dimension p. Each iteration of the outer loop loads p successive positions into shared memory (one position per thread). The threads synchronize, and then p force calculations are computed by each thread. A second synchronization is required to ensu... | Hennesey_Page_768_Chunk768 |
done, the q partial results can be collected and summed to compute the final result. Using two or four threads per body leads to large improvements for small N. As an example, the performance on the 8800 GTX jumps by 110% when N = 1024 (one thread achieves 90 GFLOPS, where four achieve 190 GFLOPS). Performance degrades... | Hennesey_Page_769_Chunk769 |
The graph also shows the results of compiling the CUDA version of the code for a CPU, where the performance improves by 24%. CUDA, as a programming language, exposes parallelism, allowing the compiler to make better use of the SSE vector unit on a single core. The CUDA version of the N-body code naturally maps to multi... | Hennesey_Page_770_Chunk770 |
On a GeForce 8800, the all-pairs N-body algorithm delivers more than 240 GFLOPS of performance, compared to less than 2 GFLOPS on recent sequential processors. Compiling and executing the CUDA version of the code on a CPU demonstrates that the problem scales well to multicore CPUs, but is still significantly slower tha... | Hennesey_Page_771_Chunk771 |
spherical shell of bodies rotating about the z-axis. One phenomenon of interest to astrophysicists is the clustering that occurs, along with the merging of galaxies over time. For the interested reader, the CUDA code for this application is available in the CUDA SDK from www.nvidia.com/CUDA. A.9 Fallacies and Pitfalls... | Hennesey_Page_772_Chunk772 |
exponentially. Put another way, given a constant manufacturing cost, the number of transistors will increase exponentially. Gordon Moore [1965] predicted that this progression would provide roughly two times the number of transistors for the same manufacturing cost every year, and later revised it to doubling every two... | Hennesey_Page_773_Chunk773 |
However, there is nothing preventing GPU architects from exposing the parallel processor cores to programmers without the graphics API or the arcane graphics languages. In fact, the Tesla architecture family of GPUs exposes the processors through a software environment known as CUDA, which allows programmers to develop... | Hennesey_Page_774_Chunk774 |
without stalling. Memory latency is long, so it is avoided by striving to run in the cache. At some point, program working set demands may be larger than any cache. Some CPUs have used multithreading to tolerate latency, but the number of threads per core has generally been limited to a small number. The GPU strategy i... | Hennesey_Page_775_Chunk775 |
A.10 Concluding Remarks GPUs are massively parallel processors and have become widely used, not only for 3D graphics, but also for many other applications. This wide application was made possible by the evolution of graphics devices into programmable processors. The graphics application programming model for GPUs is us... | Hennesey_Page_776_Chunk776 |
Historical Perspective and Further Reading This section, which appears on the CD, surveys the history of programmable real- time graphics processing units (GPUs) from the early 1980s through today as they declined in price by two orders of magnitude and increased in performance by two orders of magnitude. It traces th... | Hennesey_Page_777_Chunk777 |
B Fear of serious injury cannot alone justify suppression of free speech and assembly. Louis Brandeis Whitney v. California, 1927 Assemblers, Linkers, and the SPIM Simulator James R. Larus Microsoft Research Microsoft A P P E N D I X | Hennesey_Page_778_Chunk778 |
B.1 Introduction B-3 B.2 Assemblers B-10 B.3 Linkers B-18 B.4 Loading B-19 B.5 Memory Usage B-20 B.6 Procedure Call Convention B-22 B.7 Exceptions and Interrupts B-33 B.8 Input and Output B-38 B.9 SPIM B-40 B.10 MIPS R2000 Assembly Language B-45 B.11 Concluding Remarks B-81 B.12 Exercises B-82 B.1 Introduction Encoding... | Hennesey_Page_779_Chunk779 |
B-4 Appendix B Assemblers, Linkers, and the SPIM Simulator FIGURE B.1.1 The process that produces an executable file. An assembler translates a file of assembly language into an object file, which is linked with other files and libraries into an executable file. Object file Source file Assembler Linker Assembler Assemb... | Hennesey_Page_780_Chunk780 |
B.1 Introduction B-5 easier to read, because operations and operands are written with symbols rather than with bit patterns. However, this assembly language is still difficult to follow, because memory locations are named by their address rather than by a symbolic label. Figure B.1.4 shows assembly language that labels... | Hennesey_Page_781_Chunk781 |
B-6 Appendix B Assemblers, Linkers, and the SPIM Simulator high-level language (such as C or Pascal) into an equivalent program in machine or assembly language. The high-level language is called the source language, and the compiler’s output is its target language. Assembly language’s other role is as a language in wh... | Hennesey_Page_782_Chunk782 |
B.1 Introduction B-7 When to Use Assembly Language The primary reason to program in assembly language, as opposed to an available high-level language, is because the speed or size of a program is critically important. For example, consider a computer that controls a piece of machinery, such as a car’s brakes. A compute... | Hennesey_Page_783_Chunk783 |
B-8 Appendix B Assemblers, Linkers, and the SPIM Simulator uncertainty about the time cost of operations, programmers may find it difficult to ensure that a high-level language program responds within a definite time interval—say, 1 millisecond after a sensor detects that a tire is skidding. An assembly language progra... | Hennesey_Page_784_Chunk784 |
B.1 Introduction B-9 This improvement is not necessarily an indication that the high-level language’s compiler has failed. Compilers typically are better than programmers at produc- ing uniformly high-quality machine code across an entire program. Programmers, however, understand a program’s algorithms and behavior a... | Hennesey_Page_785_Chunk785 |
B-10 Appendix B Assemblers, Linkers, and the SPIM Simulator To compound the problem, longer programs are more difficult to read and understand, and they contain more bugs. Assembly language exacerbates the prob lem because of its complete lack of structure. Common programming idioms, such as if-then statements and loo... | Hennesey_Page_786_Chunk786 |
be referenced from files other than the one in which it is defined. A label is local if the object can be used only within the file in which it is defined. In most assem blers, labels are local by default and must be explicitly declared global. Subroutines and global variables require external labels since they are r... | Hennesey_Page_787_Chunk787 |
B-12 Appendix B Assemblers, Linkers, and the SPIM Simulator An assembler’s first pass reads each line of an assembly file and breaks it into its component pieces. These pieces, which are called lexemes, are individual words, numbers, and punctuation characters. For example, the line ble $t0, 100, loop contains six lexe... | Hennesey_Page_788_Chunk788 |
Elaboration: If an assembler’s speed is important, this two-step process can be done in one pass over the assembly file with a technique known as backpatching. In its pass over the file, the assembler builds a (possibly incomplete) binary representation of every instruction. If the instruction references a label that h... | Hennesey_Page_789_Chunk789 |
B-14 Appendix B Assemblers, Linkers, and the SPIM Simulator This relocation information is necessary because the assembler does not know which memory locations a procedure or piece of data will occupy after it is linked with the rest of the program. Procedures and data from a file are stored in a con- tiguous piece of ... | Hennesey_Page_790_Chunk790 |
specify data in a human-readable form that the assembler translates to binary. Other layout directives are described in Section B.10. String Directive Define the sequence of bytes produced by this directive: .asciiz “The quick brown fox jumps over the lazy dog” .byte 84, 104, 101, 32, 113, 117, 105, 99 .byte 107, 32, 9... | Hennesey_Page_791_Chunk791 |
B-16 Appendix B Assemblers, Linkers, and the SPIM Simulator mov $a1, $7 # Load value into # second arg jal printf # Call the printf routine The .data directive tells the assembler to store the string in the program’s data segment, and the .text directive tells the assembler to store the instruc tions in its text segme... | Hennesey_Page_792_Chunk792 |
la $a0, int_str mov $a1, $a0 jal printf This example illustrates a drawback of macros. A programmer who uses this macro must be aware that print_int uses register $a0 and so cannot correctly print the value in that register. Some assemblers also implement pseudoinstructions, which are instructions pro vided by an asse... | Hennesey_Page_793_Chunk793 |
B-18 Appendix B Assemblers, Linkers, and the SPIM Simulator B.3 Linkers Separate compilation permits a program to be split into pieces that are stored in different files. Each file contains a logically related collection of subroutines and data structures that form a module in a larger program. A file can be compiled a... | Hennesey_Page_794_Chunk794 |
the assembler could not know where a module’s instructions or data would be placed relative to other modules. When the linker places a module in memory, all absolute references must be relocated to reflect its true location. Since the linker has relocation information that identifies all relocatable references, it can... | Hennesey_Page_795_Chunk795 |
B-20 Appendix B Assemblers, Linkers, and the SPIM Simulator system kernel brings a program into memory and starts it running. To start a program, the operating system performs the following steps: 1. It reads the executable file’s header to determine the size of the text and data segments. 2. It creates a new address s... | Hennesey_Page_796_Chunk796 |
FIGURE B.5.1 Layout of memory. Dynamic data Static data Reserved Stack segment Data segment Text segment 7fff fffchex 10000000hex 400000hex Because the data segment begins far above the program at address 10000000hex, load and store instructions cannot directly reference data objects with their 16-bit offset fields (se... | Hennesey_Page_797_Chunk797 |
B-22 Appendix B Assemblers, Linkers, and the SPIM Simulator finds and returns a new block of memory. Since a compiler cannot predict how much memory a program will allocate, the operating system expands the dynamic data area to meet demand. As the upward arrow in the figure indicates, malloc expands the dynamic area wi... | Hennesey_Page_798_Chunk798 |
■ ■Registers $t0–$t9 (8–15, 24, 25) are caller-saved registers that are used to hold temporary quantities that need not be preserved across calls (see Section 2.8 in Chapter 2). ■ ■Registers $s0–$s7 (16–23) are callee-saved registers that hold long-lived values that should be preserved across calls. ■ ■Register $gp (28... | Hennesey_Page_799_Chunk799 |
B-24 Appendix B Assemblers, Linkers, and the SPIM Simulator stack pointer. The executing procedure uses the frame pointer to quickly access values in its stack frame. For example, an argument in the stack frame can be loaded into register $v0 with the instruction lw $v0, 0($fp) Register name Number Usage $zero 0 consta... | Hennesey_Page_800_Chunk800 |
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