system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ void MD5Transform( unsigned long *s, unsigned long *d );
__constant__ unsigned int nPassword[32];
__constant__ unsigned int nPasswordLen;
__constant__ unsigned int cCharset[256];
__constant__ unsigned int nCharsetLen;
__constant__ unsigned long bHash[4];
__global__ void MD5_Brute_GPU( unsigned long *pdwResul... | .file "tmpxft_00083396_00000000-6_MD5_RFC1321_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ void MD5Transform( unsigned long *s, unsigned long *d );
__constant__ unsigned int nPassword[32];
__constant__ unsigned int nPasswordLen;
__constant__ unsigned int cCharset[256];
__constant__ unsigned int nCharsetLen;
__constant__ unsigned long bHash[4];
__global__ void MD5_Brute_GPU( unsigned long *pdwResul... | #include <hip/hip_runtime.h>
__device__ void MD5Transform( unsigned long *s, unsigned long *d );
__constant__ unsigned int nPassword[32];
__constant__ unsigned int nPasswordLen;
__constant__ unsigned int cCharset[256];
__constant__ unsigned int nCharsetLen;
__constant__ unsigned long bHash[4];
__global__ void MD5_Brute... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ void MD5Transform( unsigned long *s, unsigned long *d );
__constant__ unsigned int nPassword[32];
__constant__ unsigned int nPasswordLen;
__constant__ unsigned int cCharset[256];
__constant__ unsigned int nCharsetLen;
__constant__ unsigned long bHash[4];
__global__ void MD5_Brute... | .text
.file "MD5_RFC1321_GPU.hip"
.globl _Z28__device_stub__MD5_Brute_GPUPm # -- Begin function _Z28__device_stub__MD5_Brute_GPUPm
.p2align 4, 0x90
.type _Z28__device_stub__MD5_Brute_GPUPm,@function
_Z28__device_stub__MD5_Brute_GPUPm: # @_Z28__device_stub__MD5_Brute_GPUPm
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00083396_00000000-6_MD5_RFC1321_GPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... | .text
.file "MD5_RFC1321_GPU.hip"
.globl _Z28__device_stub__MD5_Brute_GPUPm # -- Begin function _Z28__device_stub__MD5_Brute_GPUPm
.p2align 4, 0x90
.type _Z28__device_stub__MD5_Brute_GPUPm,@function
_Z28__device_stub__MD5_Brute_GPUPm: # @_Z28__device_stub__MD5_Brute_GPUPm
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <device_launch_parameters.h>
#define LIST_SIZE 100000
extern "C" __device__ long long instCountList[LIST_SIZE];
void bambooLogRecordOff(){
}
void bambooLogKernelBegin(int i... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <device_launch_parameters.h>
#define LIST_SIZE 100000
extern "C" __device__ long long instCountList[LIST_SIZE];
void bambooLogRecordOff(){
}
void bambooLogKernelBegin(int i... | .file "tmpxft_000761e4_00000000-6_record_data.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <device_launch_parameters.h>
#define LIST_SIZE 100000
extern "C" __device__ long long instCountList[LIST_SIZE];
void bambooLogRecordOff(){
}
void bambooLogKernelBegin(int i... | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define LIST_SIZE 100000
extern "C" __device__ long long instCountList[LIST_SIZE];
void bambooLogRecordOff(){
}
void bambooLogKernelBegin(int i) {
}
void bambooLogKernelEnd() {
#ifdef KERNELTRACE
hipDeviceSynchroni... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define LIST_SIZE 100000
extern "C" __device__ long long instCountList[LIST_SIZE];
void bambooLogRecordOff(){
}
void bambooLogKernelBegin(int i) {
}
void bambooLogKernelEnd() {
#ifdef KERNELTRACE
hipDeviceSynchroni... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define LIST_SIZE 100000
extern "C" __device__ long long instCountList[LIST_SIZE];
void bambooLogRecordOff(){
}
void bambooLogKernelBegin(int i) {
}
void bambooLogKernelEnd() {
#ifdef KERNELTRACE
hipDeviceSynchroni... | .text
.file "record_data.hip"
.globl _Z18bambooLogRecordOffv # -- Begin function _Z18bambooLogRecordOffv
.p2align 4, 0x90
.type _Z18bambooLogRecordOffv,@function
_Z18bambooLogRecordOffv: # @_Z18bambooLogRecordOffv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z18bambooLogRecordOffv, .Lfunc_end... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000761e4_00000000-6_record_data.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... | .text
.file "record_data.hip"
.globl _Z18bambooLogRecordOffv # -- Begin function _Z18bambooLogRecordOffv
.p2align 4, 0x90
.type _Z18bambooLogRecordOffv,@function
_Z18bambooLogRecordOffv: # @_Z18bambooLogRecordOffv
.cfi_startproc
# %bb.0:
retq
.Lfunc_end0:
.size _Z18bambooLogRecordOffv, .Lfunc_end... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int glb_hist[COLORS]; __global__ void calc_histogram(unsigned char * img_in, int offset_start, int offset_end){
int ix = blockIdx.x * blockDim.x + threadIdx.x;;
const int gridW = gridDim.x * blockDim.x;
int Row, pos;
__shared__ int hist[COLORS];
if (threadIdx.x < COLORS) {
hist[threadId... | code for sm_80
Function : _Z14calc_histogramPiPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int glb_hist[COLORS]; __global__ void calc_histogram(unsigned char * img_in, int offset_start, int offset_end){
int ix = blockIdx.x * blockDim.x + threadIdx.x;;
const int gridW = gridDim.x * blockDim.x;
int Row, pos;
__shared__ int hist[COLORS];
if (threadIdx.x < COLORS) {
hist[threadId... | .file "tmpxft_000139b2_00000000-6_calc_histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int glb_hist[COLORS]; __global__ void calc_histogram(unsigned char * img_in, int offset_start, int offset_end){
int ix = blockIdx.x * blockDim.x + threadIdx.x;;
const int gridW = gridDim.x * blockDim.x;
int Row, pos;
__shared__ int hist[COLORS];
if (threadIdx.x < COLORS) {
hist[threadId... | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int glb_hist[COLORS]; __global__ void calc_histogram(unsigned char * img_in, int offset_start, int offset_end){
int ix = blockIdx.x * blockDim.x + threadIdx.x;;
const int gridW = gridDim.x * blockDim.x;
int Row, pos;
__shared__ int hist[COLORS];
if (threadId... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int glb_hist[COLORS]; __global__ void calc_histogram(unsigned char * img_in, int offset_start, int offset_end){
int ix = blockIdx.x * blockDim.x + threadIdx.x;;
const int gridW = gridDim.x * blockDim.x;
int Row, pos;
__shared__ int hist[COLORS];
if (threadId... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14calc_histogramPhii
.globl _Z14calc_histogramPhii
.p2align 8
.type _Z14calc_histogramPhii,@function
_Z14calc_histogramPhii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x1c
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_and_sav... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int glb_hist[COLORS]; __global__ void calc_histogram(unsigned char * img_in, int offset_start, int offset_end){
int ix = blockIdx.x * blockDim.x + threadIdx.x;;
const int gridW = gridDim.x * blockDim.x;
int Row, pos;
__shared__ int hist[COLORS];
if (threadId... | .text
.file "calc_histogram.hip"
.globl _Z29__device_stub__calc_histogramPhii # -- Begin function _Z29__device_stub__calc_histogramPhii
.p2align 4, 0x90
.type _Z29__device_stub__calc_histogramPhii,@function
_Z29__device_stub__calc_histogramPhii: # @_Z29__device_stub__calc_histogramPhii
.cfi_startproc
# %bb.0:
subq $88... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14calc_histogramPiPhii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14calc_histogramPhii
.globl _Z14calc_histogramPhii
.p2align 8
.type _Z14calc_histogramPhii,@function
_Z14calc_histogramPhii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b32 s3, s[0:1], 0x1c
v_cmp_gt_u32_e32 vcc_lo, 0x100, v0
s_and_sav... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000139b2_00000000-6_calc_histogram.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... | .text
.file "calc_histogram.hip"
.globl _Z29__device_stub__calc_histogramPhii # -- Begin function _Z29__device_stub__calc_histogramPhii
.p2align 4, 0x90
.type _Z29__device_stub__calc_histogramPhii,@function
_Z29__device_stub__calc_histogramPhii: # @_Z29__device_stub__calc_histogramPhii
.cfi_startproc
# %bb.0:
subq $88... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<iostream>
#include<cuda.h>
using namespace std;
//Catch Cuda errors
void catchCudaError(cudaError_t error){
if(error!=cudaSuccess) {
printf("\n====== Cuda Error Code %i ======\n %s\n",error,cudaGetErrorString(error));
exit(-1);
}
}
//=========================================================... | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<iostream>
#include<cuda.h>
using namespace std;
//Catch Cuda errors
void catchCudaError(cudaError_t error){
if(error!=cudaSuccess) {
printf("\n====== Cuda Error Code %i ======\n %s\n",error,cudaGetErrorString(error));
exit(-1);
}
}
//=========================================================... | .file "tmpxft_00032fae_00000000-6_vector-add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cud... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<iostream>
#include<cuda.h>
using namespace std;
//Catch Cuda errors
void catchCudaError(cudaError_t error){
if(error!=cudaSuccess) {
printf("\n====== Cuda Error Code %i ======\n %s\n",error,cudaGetErrorString(error));
exit(-1);
}
}
//=========================================================... | #include<stdio.h>
#include<iostream>
#include<hip/hip_runtime.h>
using namespace std;
//Catch Cuda errors
void catchCudaError(hipError_t error){
if(error!=hipSuccess) {
printf("\n====== Cuda Error Code %i ======\n %s\n",error,hipGetErrorString(error));
exit(-1);
}
}
//=================================================... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<iostream>
#include<hip/hip_runtime.h>
using namespace std;
//Catch Cuda errors
void catchCudaError(hipError_t error){
if(error!=hipSuccess) {
printf("\n====== Cuda Error Code %i ======\n %s\n",error,hipGetErrorString(error));
exit(-1);
}
}
//=================================================... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | inst... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<iostream>
#include<hip/hip_runtime.h>
using namespace std;
//Catch Cuda errors
void catchCudaError(hipError_t error){
if(error!=hipSuccess) {
printf("\n====== Cuda Error Code %i ======\n %s\n",error,hipGetErrorString(error));
exit(-1);
}
}
//=================================================... | .text
.file "vector-add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14catchCudaError10hipError_t # -- Begin function _Z14catchCudaError10hipError_t
.p2align 4, 0... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | inst... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00032fae_00000000-6_vector-add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cud... | .text
.file "vector-add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14catchCudaError10hipError_t # -- Begin function _Z14catchCudaError10hipError_t
.p2align 4, 0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void rho(float *x, int size, float lambda)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
x[id] = 1 - exp(-x[id] / lambda);
}
} | code for sm_80
Function : _Z3rhoPfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void rho(float *x, int size, float lambda)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
x[id] = 1 - exp(-x[id] / lambda);
}
} | .file "tmpxft_001b5f32_00000000-6_rho.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void rho(float *x, int size, float lambda)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
x[id] = 1 - exp(-x[id] / lambda);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void rho(float *x, int size, float lambda)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
x[id] = 1 - exp(-x[id] / lambda);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void rho(float *x, int size, float lambda)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
x[id] = 1 - exp(-x[id] / lambda);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3rhoPfif
.globl _Z3rhoPfif
.p2align 8
.type _Z3rhoPfif,@function
_Z3rhoPfif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SAL... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define TB 128
#define DISP_MAX 256
__global__ void rho(float *x, int size, float lambda)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
x[id] = 1 - exp(-x[id] / lambda);
}
} | .text
.file "rho.hip"
.globl _Z18__device_stub__rhoPfif # -- Begin function _Z18__device_stub__rhoPfif
.p2align 4, 0x90
.type _Z18__device_stub__rhoPfif,@function
_Z18__device_stub__rhoPfif: # @_Z18__device_stub__rhoPfif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3rhoPfif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3rhoPfif
.globl _Z3rhoPfif
.p2align 8
.type _Z3rhoPfif,@function
_Z3rhoPfif:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SAL... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b5f32_00000000-6_rho.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi... | .text
.file "rho.hip"
.globl _Z18__device_stub__rhoPfif # -- Begin function _Z18__device_stub__rhoPfif
.p2align 4, 0x90
.type _Z18__device_stub__rhoPfif,@function
_Z18__device_stub__rhoPfif: # @_Z18__device_stub__rhoPfif
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateSimple(float *sum, float step, int threads, int blocks)
{
int idx = threadIdx.x + blockI... | code for sm_80
Function : _Z15integrateSimplePffii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateSimple(float *sum, float step, int threads, int blocks)
{
int idx = threadIdx.x + blockI... | .file "tmpxft_0014faf4_00000000-6_integrateSimple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateSimple(float *sum, float step, int threads, int blocks)
{
int idx = threadIdx.x + blockI... | #include <hip/hip_runtime.h>
#include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateSimple(float *sum, float step, int threads, int blocks)
{
i... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateSimple(float *sum, float step, int threads, int blocks)
{
i... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15integrateSimplePffii
.globl _Z15integrateSimplePffii
.p2align 8
.type _Z15integrateSimplePffii,@function
_Z15integrateSimplePffii:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define INTERVALS 1000000
// Max number of threads per block
#define THREADS 512
#define BLOCKS 64
double calculatePiCPU();
// Synchronous error checking call. Enable with nvcc -DDEBUG
__global__ void integrateSimple(float *sum, float step, int threads, int blocks)
{
i... | .text
.file "integrateSimple.hip"
.globl _Z30__device_stub__integrateSimplePffii # -- Begin function _Z30__device_stub__integrateSimplePffii
.p2align 4, 0x90
.type _Z30__device_stub__integrateSimplePffii,@function
_Z30__device_stub__integrateSimplePffii: # @_Z30__device_stub__integrateSimplePffii
.cfi_startproc
# %bb.0... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15integrateSimplePffii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15integrateSimplePffii
.globl _Z15integrateSimplePffii
.p2align 8
.type _Z15integrateSimplePffii,@function
_Z15integrateSimplePffii:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014faf4_00000000-6_integrateSimple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... | .text
.file "integrateSimple.hip"
.globl _Z30__device_stub__integrateSimplePffii # -- Begin function _Z30__device_stub__integrateSimplePffii
.p2align 4, 0x90
.type _Z30__device_stub__integrateSimplePffii,@function
_Z30__device_stub__integrateSimplePffii: # @_Z30__device_stub__integrateSimplePffii
.cfi_startproc
# %bb.0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <cuda.h>
#include "cuda_runtime.h"
#define NUMBLOCK 1
#define BLOCKWIDTH 16
#define NUMTHREAD 10000
#define ASIZE 10000
void printArray(int * image){
int i,j;
for (i = 0; i < ASIZE; ++i)
{
for (j = 0; j < ASIZE; ++j)
{
printf("%d\t", image[i * ASIZE + j... | .file "tmpxft_00184440_00000000-6_integralGlobalV2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <cuda.h>
#include "cuda_runtime.h"
#define NUMBLOCK 1
#define BLOCKWIDTH 16
#define NUMTHREAD 10000
#define ASIZE 10000
void printArray(int * image){
int i,j;
for (i = 0; i < ASIZE; ++i)
{
for (j = 0; j < ASIZE; ++j)
{
printf("%d\t", image[i * ASIZE + j... | #include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define NUMBLOCK 1
#define BLOCKWIDTH 16
#define NUMTHREAD 10000
#define ASIZE 10000
void printArray(int * image){
int i,j;
for (i = 0; i < ASIZE; ++i)
{
for (j = 0; j < ASIZE; ++j)
{
printf("%d\t", image[i * ASIZE + j]);
}
printf("\... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define NUMBLOCK 1
#define BLOCKWIDTH 16
#define NUMTHREAD 10000
#define ASIZE 10000
void printArray(int * image){
int i,j;
for (i = 0; i < ASIZE; ++i)
{
for (j = 0; j < ASIZE; ++j)
{
printf("%d\t", image[i * ASIZE + j]);
}
printf("\... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9prefixSumPiS_
.globl _Z9prefixSumPiS_
.p2align 8
.type _Z9prefixSumPiS_,@function
_Z9prefixSumPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <time.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define NUMBLOCK 1
#define BLOCKWIDTH 16
#define NUMTHREAD 10000
#define ASIZE 10000
void printArray(int * image){
int i,j;
for (i = 0; i < ASIZE; ++i)
{
for (j = 0; j < ASIZE; ++j)
{
printf("%d\t", image[i * ASIZE + j]);
}
printf("\... | .text
.file "integralGlobalV2.hip"
.globl _Z10printArrayPi # -- Begin function _Z10printArrayPi
.p2align 4, 0x90
.type _Z10printArrayPi,@function
_Z10printArrayPi: # @_Z10printArrayPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00184440_00000000-6_integralGlobalV2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... | .text
.file "integralGlobalV2.hip"
.globl _Z10printArrayPi # -- Begin function _Z10printArrayPi
.p2align 4, 0x90
.type _Z10printArrayPi,@function
_Z10printArrayPi: # @_Z10printArrayPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 512
typedef struct Data {
double* a;
double* b;
double* c;
} Data;
__global__ void add( Data data, int vector_size ) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x*blockDim.x + threadIdx.x;
// This if s... | code for sm_80
Function : _Z3add4Datai
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 512
typedef struct Data {
double* a;
double* b;
double* c;
} Data;
__global__ void add( Data data, int vector_size ) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x*blockDim.x + threadIdx.x;
// This if s... | .file "tmpxft_0006d1b1_00000000-6_vadd_coalesced.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 512
typedef struct Data {
double* a;
double* b;
double* c;
} Data;
__global__ void add( Data data, int vector_size ) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x*blockDim.x + threadIdx.x;
// This if s... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 512
typedef struct Data {
double* a;
double* b;
double* c;
} Data;
__global__ void add( Data data, int vector_size ) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x*blockDim.x... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 512
typedef struct Data {
double* a;
double* b;
double* c;
} Data;
__global__ void add( Data data, int vector_size ) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x*blockDim.x... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3add4Datai
.globl _Z3add4Datai
.p2align 8
.type _Z3add4Datai,@function
_Z3add4Datai:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 512
typedef struct Data {
double* a;
double* b;
double* c;
} Data;
__global__ void add( Data data, int vector_size ) {
// Calculate the index in the vector for the thread using the internal variables
int tid = blockIdx.x*blockDim.x... | .text
.file "vadd_coalesced.hip"
.globl _Z18__device_stub__add4Datai # -- Begin function _Z18__device_stub__add4Datai
.p2align 4, 0x90
.type _Z18__device_stub__add4Datai,@function
_Z18__device_stub__add4Datai: # @_Z18__device_stub__add4Datai
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
mov... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3add4Datai
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3add4Datai
.globl _Z3add4Datai
.p2align 8
.type _Z3add4Datai,@function
_Z3add4Datai:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006d1b1_00000000-6_vadd_coalesced.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... | .text
.file "vadd_coalesced.hip"
.globl _Z18__device_stub__add4Datai # -- Begin function _Z18__device_stub__add4Datai
.p2align 4, 0x90
.type _Z18__device_stub__add4Datai,@function
_Z18__device_stub__add4Datai: # @_Z18__device_stub__add4Datai
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
mov... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
namespace chainer_trt {
namespace plugin {
__global__ void transpose_kernel(const float* d_src, float* d_dst,
int* d_indexes, int in_size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < in_size)
d_dst[blockIdx.y * in_size + d_indexes[... | .file "tmpxft_0019d1cd_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
namespace chainer_trt {
namespace plugin {
__global__ void transpose_kernel(const float* d_src, float* d_dst,
int* d_indexes, int in_size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < in_size)
d_dst[blockIdx.y * in_size + d_indexes[... | #include <hip/hip_runtime.h>
/*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
namespace chainer_trt {
namespace plugin {
__global__ void transpose_kernel(const float* d_src, float* d_dst,
int* d_indexes, int in_size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < in_size)
d_dst[bloc... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
namespace chainer_trt {
namespace plugin {
__global__ void transpose_kernel(const float* d_src, float* d_dst,
int* d_indexes, int in_size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < in_size)
d_dst[bloc... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _ZN11chainer_trt6plugin16transpose_kernelEPKfPfPii
.globl _ZN11chainer_trt6plugin16transpose_kernelEPKfPfPii
.p2align 8
.type _ZN11chainer_trt6plugin16transpose_kernelEPKfPfPii,@function
_ZN11chainer_trt6plugin16transpose_kernelEPKfPfPii:
s_clause 0x1
s_loa... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* Copyright (c) 2018 Preferred Networks, Inc. All rights reserved.
*/
namespace chainer_trt {
namespace plugin {
__global__ void transpose_kernel(const float* d_src, float* d_dst,
int* d_indexes, int in_size) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx < in_size)
d_dst[bloc... | .text
.file "transpose.hip"
.globl _ZN11chainer_trt6plugin31__device_stub__transpose_kernelEPKfPfPii # -- Begin function _ZN11chainer_trt6plugin31__device_stub__transpose_kernelEPKfPfPii
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin31__device_stub__transpose_kernelEPKfPfPii,@function
_ZN11chainer_trt6plugin31__device_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019d1cd_00000000-6_transpose.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... | .text
.file "transpose.hip"
.globl _ZN11chainer_trt6plugin31__device_stub__transpose_kernelEPKfPfPii # -- Begin function _ZN11chainer_trt6plugin31__device_stub__transpose_kernelEPKfPfPii
.p2align 4, 0x90
.type _ZN11chainer_trt6plugin31__device_stub__transpose_kernelEPKfPfPii,@function
_ZN11chainer_trt6plugin31__device_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published b... | code for sm_80
Function : _Z8set_carrffPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published b... | .file "tmpxft_000b56e8_00000000-6_set_carr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published b... | #include <hip/hip_runtime.h>
#include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8set_carrffPfm
.globl _Z8set_carrffPfm
.p2align 8
.type _Z8set_carrffPfm,@function
_Z8set_carrffPfm:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_m... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/************************* CudaMat ******************************************
* Copyright (C) 2008-2009 by Rainer Heintzmann *
* heintzmann@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General ... | .text
.file "set_carr.hip"
.globl _Z23__device_stub__set_carrffPfm # -- Begin function _Z23__device_stub__set_carrffPfm
.p2align 4, 0x90
.type _Z23__device_stub__set_carrffPfm,@function
_Z23__device_stub__set_carrffPfm: # @_Z23__device_stub__set_carrffPfm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offse... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8set_carrffPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8set_carrffPfm
.globl _Z8set_carrffPfm
.p2align 8
.type _Z8set_carrffPfm,@function
_Z8set_carrffPfm:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_m... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b56e8_00000000-6_set_carr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... | .text
.file "set_carr.hip"
.globl _Z23__device_stub__set_carrffPfm # -- Begin function _Z23__device_stub__set_carrffPfm
.p2align 4, 0x90
.type _Z23__device_stub__set_carrffPfm,@function
_Z23__device_stub__set_carrffPfm: # @_Z23__device_stub__set_carrffPfm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offse... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Andrew Miller <amiller@dappervision.com>
*
* Cuda 512*512*512*4bytes test
*
* According to the KinectFusion UIST 2011 paper, it's possible
* to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
*
* This code is a simple benchmark accessing 512^3 voxels. Each
* voxel has two 16-bit components. In this... | code for sm_80
Function : _Z9incr_tsdfP5VoxelS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Andrew Miller <amiller@dappervision.com>
*
* Cuda 512*512*512*4bytes test
*
* According to the KinectFusion UIST 2011 paper, it's possible
* to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
*
* This code is a simple benchmark accessing 512^3 voxels. Each
* voxel has two 16-bit components. In this... | .file "tmpxft_000c9859_00000000-6_cuda_512_512_512_4_bytes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@P... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Andrew Miller <amiller@dappervision.com>
*
* Cuda 512*512*512*4bytes test
*
* According to the KinectFusion UIST 2011 paper, it's possible
* to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
*
* This code is a simple benchmark accessing 512^3 voxels. Each
* voxel has two 16-bit components. In this... | /* Andrew Miller <amiller@dappervision.com>
*
* Cuda 512*512*512*4bytes test
*
* According to the KinectFusion UIST 2011 paper, it's possible
* to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
*
* This code is a simple benchmark accessing 512^3 voxels. Each
* voxel has two 16-bit components. In this... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Andrew Miller <amiller@dappervision.com>
*
* Cuda 512*512*512*4bytes test
*
* According to the KinectFusion UIST 2011 paper, it's possible
* to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
*
* This code is a simple benchmark accessing 512^3 voxels. Each
* voxel has two 16-bit components. In this... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9incr_tsdfP5VoxelS0_
.globl _Z9incr_tsdfP5VoxelS0_
.p2align 8
.type _Z9incr_tsdfP5VoxelS0_,@function
_Z9incr_tsdfP5VoxelS0_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Andrew Miller <amiller@dappervision.com>
*
* Cuda 512*512*512*4bytes test
*
* According to the KinectFusion UIST 2011 paper, it's possible
* to do a sweep of 512^3 voxels, 32-bits each, in ~2ms on a GTX470.
*
* This code is a simple benchmark accessing 512^3 voxels. Each
* voxel has two 16-bit components. In this... | .text
.file "cuda_512_512_512_4_bytes.hip"
.globl _Z24__device_stub__incr_tsdfP5VoxelS0_ # -- Begin function _Z24__device_stub__incr_tsdfP5VoxelS0_
.p2align 4, 0x90
.type _Z24__device_stub__incr_tsdfP5VoxelS0_,@function
_Z24__device_stub__incr_tsdfP5VoxelS0_: # @_Z24__device_stub__incr_tsdfP5VoxelS0_
.cfi_startproc
# %... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9incr_tsdfP5VoxelS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9incr_tsdfP5VoxelS0_
.globl _Z9incr_tsdfP5VoxelS0_
.p2align 8
.type _Z9incr_tsdfP5VoxelS0_,@function
_Z9incr_tsdfP5VoxelS0_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c9859_00000000-6_cuda_512_512_512_4_bytes.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@P... | .text
.file "cuda_512_512_512_4_bytes.hip"
.globl _Z24__device_stub__incr_tsdfP5VoxelS0_ # -- Begin function _Z24__device_stub__incr_tsdfP5VoxelS0_
.p2align 4, 0x90
.type _Z24__device_stub__incr_tsdfP5VoxelS0_,@function
_Z24__device_stub__incr_tsdfP5VoxelS0_: # @_Z24__device_stub__incr_tsdfP5VoxelS0_
.cfi_startproc
# %... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void copy( float *v4, const float *v3, const int n ) {
for(int i=blockIdx.x*blockDim.x+threadIdx.x;i<n;i+=blockDim.x*gridDim.x) {
v4[i*8+0] = v3[i*6+0];
v4[i*8+1] = v3[i*6+1];
v4[i*8+2] = v3[i*6+2];
v4[i*8+4] = v3[i*6+3];
v4[i*8+5] = v3[i*6+4];
v4[i*8+6] = v3[i*6+5];
}
} | code for sm_80
Function : _Z4copyPfPKfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void copy( float *v4, const float *v3, const int n ) {
for(int i=blockIdx.x*blockDim.x+threadIdx.x;i<n;i+=blockDim.x*gridDim.x) {
v4[i*8+0] = v3[i*6+0];
v4[i*8+1] = v3[i*6+1];
v4[i*8+2] = v3[i*6+2];
v4[i*8+4] = v3[i*6+3];
v4[i*8+5] = v3[i*6+4];
v4[i*8+6] = v3[i*6+5];
}
} | .file "tmpxft_0008b2c0_00000000-6_copy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void copy( float *v4, const float *v3, const int n ) {
for(int i=blockIdx.x*blockDim.x+threadIdx.x;i<n;i+=blockDim.x*gridDim.x) {
v4[i*8+0] = v3[i*6+0];
v4[i*8+1] = v3[i*6+1];
v4[i*8+2] = v3[i*6+2];
v4[i*8+4] = v3[i*6+3];
v4[i*8+5] = v3[i*6+4];
v4[i*8+6] = v3[i*6+5];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copy( float *v4, const float *v3, const int n ) {
for(int i=blockIdx.x*blockDim.x+threadIdx.x;i<n;i+=blockDim.x*gridDim.x) {
v4[i*8+0] = v3[i*6+0];
v4[i*8+1] = v3[i*6+1];
v4[i*8+2] = v3[i*6+2];
v4[i*8+4] = v3[i*6+3];
v4[i*8+5] = v3[i*6+4];
v4[i*8+6] = v... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copy( float *v4, const float *v3, const int n ) {
for(int i=blockIdx.x*blockDim.x+threadIdx.x;i<n;i+=blockDim.x*gridDim.x) {
v4[i*8+0] = v3[i*6+0];
v4[i*8+1] = v3[i*6+1];
v4[i*8+2] = v3[i*6+2];
v4[i*8+4] = v3[i*6+3];
v4[i*8+5] = v3[i*6+4];
v4[i*8+6] = v... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPfPKfi
.globl _Z4copyPfPKfi
.p2align 8
.type _Z4copyPfPKfi,@function
_Z4copyPfPKfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void copy( float *v4, const float *v3, const int n ) {
for(int i=blockIdx.x*blockDim.x+threadIdx.x;i<n;i+=blockDim.x*gridDim.x) {
v4[i*8+0] = v3[i*6+0];
v4[i*8+1] = v3[i*6+1];
v4[i*8+2] = v3[i*6+2];
v4[i*8+4] = v3[i*6+3];
v4[i*8+5] = v3[i*6+4];
v4[i*8+6] = v... | .text
.file "copy.hip"
.globl _Z19__device_stub__copyPfPKfi # -- Begin function _Z19__device_stub__copyPfPKfi
.p2align 4, 0x90
.type _Z19__device_stub__copyPfPKfi,@function
_Z19__device_stub__copyPfPKfi: # @_Z19__device_stub__copyPfPKfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rd... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4copyPfPKfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPfPKfi
.globl _Z4copyPfPKfi
.p2align 8
.type _Z4copyPfPKfi,@function
_Z4copyPfPKfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008b2c0_00000000-6_copy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "copy.hip"
.globl _Z19__device_stub__copyPfPKfi # -- Begin function _Z19__device_stub__copyPfPKfi
.p2align 4, 0x90
.type _Z19__device_stub__copyPfPKfi,@function
_Z19__device_stub__copyPfPKfi: # @_Z19__device_stub__copyPfPKfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rd... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
__host__ __device__ double2 d2add(double2 a, double2 b) {
/*
* Arguments: two 2d vectors
* Returns: the vector addition of the two vectors
*/
double2 ret;
ret.x=a.x+b.x;
ret.y=a.y+b.y;
return ret;
}
__host__ __device__ double2 d2sub(double2 a, double2 b) {
/*
* A... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
__host__ __device__ double2 d2add(double2 a, double2 b) {
/*
* Arguments: two 2d vectors
* Returns: the vector addition of the two vectors
*/
double2 ret;
ret.x=a.x+b.x;
ret.y=a.y+b.y;
return ret;
}
__host__ __device__ double2 d2sub(double2 a, double2 b) {
/*
* A... | .file "tmpxft_0001a61b_00000000-6_d2func.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <stdlib.h>
__host__ __device__ double2 d2add(double2 a, double2 b) {
/*
* Arguments: two 2d vectors
* Returns: the vector addition of the two vectors
*/
double2 ret;
ret.x=a.x+b.x;
ret.y=a.y+b.y;
return ret;
}
__host__ __device__ double2 d2sub(double2 a, double2 b) {
/*
* A... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
__host__ __device__ double2 d2add(double2 a, double2 b) {
/*
* Arguments: two 2d vectors
* Returns: the vector addition of the two vectors
*/
double2 ret;
ret.x=a.x+b.x;
ret.y=a.y+b.y;
return ret;
}
__host__ __device__ double2 d2sub(d... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
__host__ __device__ double2 d2add(double2 a, double2 b) {
/*
* Arguments: two 2d vectors
* Returns: the vector addition of the two vectors
*/
double2 ret;
ret.x=a.x+b.x;
ret.y=a.y+b.y;
return ret;
}
__host__ __device__ double2 d2sub(d... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <stdlib.h>
__host__ __device__ double2 d2add(double2 a, double2 b) {
/*
* Arguments: two 2d vectors
* Returns: the vector addition of the two vectors
*/
double2 ret;
ret.x=a.x+b.x;
ret.y=a.y+b.y;
return ret;
}
__host__ __device__ double2 d2sub(d... | .text
.file "d2func.hip"
.globl _Z5d2add15HIP_vector_typeIdLj2EES0_ # -- Begin function _Z5d2add15HIP_vector_typeIdLj2EES0_
.p2align 4, 0x90
.type _Z5d2add15HIP_vector_typeIdLj2EES0_,@function
_Z5d2add15HIP_vector_typeIdLj2EES0_: # @_Z5d2add15HIP_vector_typeIdLj2EES0_
.cfi_startproc
# %bb.0:
addsd %xmm2, %xmm0
addsd... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001a61b_00000000-6_d2func.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "d2func.hip"
.globl _Z5d2add15HIP_vector_typeIdLj2EES0_ # -- Begin function _Z5d2add15HIP_vector_typeIdLj2EES0_
.p2align 4, 0x90
.type _Z5d2add15HIP_vector_typeIdLj2EES0_,@function
_Z5d2add15HIP_vector_typeIdLj2EES0_: # @_Z5d2add15HIP_vector_typeIdLj2EES0_
.cfi_startproc
# %bb.0:
addsd %xmm2, %xmm0
addsd... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define... | code for sm_80
Function : _Z9image_velPfiifffiiS_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e22000000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define... | .file "tmpxft_000eebc1_00000000-6_image_vel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d_Lambda[(x)*(nz)+(z)]
#define... | #include <hip/hip_runtime.h>
#define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9image_velPfiifffiiS_S_S_S_S_
.globl _Z9image_velPfiifffiiS_S_S_S_S_
.p2align 8
.type _Z9image_velPfiifffiiS_S_S_S_S_,@function
_Z9image_velPfiifffiiS_S_S_S_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x5c
s_load_b32 s4, s[0:1], 0x1c
v_and_b32_e32 v3, ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define d_vx(z,x) d_vx[(x)*(nz)+(z)]
#define d_vy(z,x) d_vy[(x)*(nz)+(z)]
#define d_vz(z,x) d_vz[(x)*(nz)+(z)]
#define d_szz(z,x) d_szz[(x)*(nz)+(z)] // Pressure
#define d_mem_dvz_dz(z,x) d_mem_dvz_dz[(x)*(nz)+(z)]
#define d_mem_dvx_dx(z,x) d_mem_dvx_dx[(x)*(nz)+(z)]
#define d_Lambda(z,x) d... | .text
.file "image_vel.hip"
.globl _Z24__device_stub__image_velPfiifffiiS_S_S_S_S_ # -- Begin function _Z24__device_stub__image_velPfiifffiiS_S_S_S_S_
.p2align 4, 0x90
.type _Z24__device_stub__image_velPfiifffiiS_S_S_S_S_,@function
_Z24__device_stub__image_velPfiifffiiS_S_S_S_S_: # @_Z24__device_stub__image_velPfiifffi... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9image_velPfiifffiiS_S_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e22000000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9image_velPfiifffiiS_S_S_S_S_
.globl _Z9image_velPfiifffiiS_S_S_S_S_
.p2align 8
.type _Z9image_velPfiifffiiS_S_S_S_S_,@function
_Z9image_velPfiifffiiS_S_S_S_S_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x5c
s_load_b32 s4, s[0:1], 0x1c
v_and_b32_e32 v3, ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eebc1_00000000-6_image_vel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rs... | .text
.file "image_vel.hip"
.globl _Z24__device_stub__image_velPfiifffiiS_S_S_S_S_ # -- Begin function _Z24__device_stub__image_velPfiifffiiS_S_S_S_S_
.p2align 4, 0x90
.type _Z24__device_stub__image_velPfiifffiiS_S_S_S_S_,@function
_Z24__device_stub__image_velPfiifffiiS_S_S_S_S_: # @_Z24__device_stub__image_velPfiifffi... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void PolynomialFunctionKernel_Double(float a3, float a2, float a1, float a0, double* input, double* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if (id < size)
{
double x = input[id];
output[id] = a3 * x * x * x + a2 * x * x +... | code for sm_80
Function : _Z31PolynomialFunctionKernel_DoubleffffPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void PolynomialFunctionKernel_Double(float a3, float a2, float a1, float a0, double* input, double* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if (id < size)
{
double x = input[id];
output[id] = a3 * x * x * x + a2 * x * x +... | .file "tmpxft_001299d4_00000000-6_PolynomialFunctionKernel_Double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatB... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void PolynomialFunctionKernel_Double(float a3, float a2, float a1, float a0, double* input, double* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if (id < size)
{
double x = input[id];
output[id] = a3 * x * x * x + a2 * x * x +... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PolynomialFunctionKernel_Double(float a3, float a2, float a1, float a0, double* input, double* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if (id < size)
{
double x = input[id];
output[id] = ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PolynomialFunctionKernel_Double(float a3, float a2, float a1, float a0, double* input, double* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if (id < size)
{
double x = input[id];
output[id] = ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31PolynomialFunctionKernel_DoubleffffPdS_i
.globl _Z31PolynomialFunctionKernel_DoubleffffPdS_i
.p2align 8
.type _Z31PolynomialFunctionKernel_DoubleffffPdS_i,@function
_Z31PolynomialFunctionKernel_DoubleffffPdS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void PolynomialFunctionKernel_Double(float a3, float a2, float a1, float a0, double* input, double* output, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
if (id < size)
{
double x = input[id];
output[id] = ... | .text
.file "PolynomialFunctionKernel_Double.hip"
.globl _Z46__device_stub__PolynomialFunctionKernel_DoubleffffPdS_i # -- Begin function _Z46__device_stub__PolynomialFunctionKernel_DoubleffffPdS_i
.p2align 4, 0x90
.type _Z46__device_stub__PolynomialFunctionKernel_DoubleffffPdS_i,@function
_Z46__device_stub__PolynomialF... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z31PolynomialFunctionKernel_DoubleffffPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31PolynomialFunctionKernel_DoubleffffPdS_i
.globl _Z31PolynomialFunctionKernel_DoubleffffPdS_i
.p2align 8
.type _Z31PolynomialFunctionKernel_DoubleffffPdS_i,@function
_Z31PolynomialFunctionKernel_DoubleffffPdS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x28
s... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001299d4_00000000-6_PolynomialFunctionKernel_Double.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatB... | .text
.file "PolynomialFunctionKernel_Double.hip"
.globl _Z46__device_stub__PolynomialFunctionKernel_DoubleffffPdS_i # -- Begin function _Z46__device_stub__PolynomialFunctionKernel_DoubleffffPdS_i
.p2align 4, 0x90
.type _Z46__device_stub__PolynomialFunctionKernel_DoubleffffPdS_i,@function
_Z46__device_stub__PolynomialF... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <complex>
#include <math.h>
#include <thrust/complex.h>
#include <sys/time.h>
#include <cassert>
using namespace std;
__constant__ const int block_1 = 16;
__constant__ const int block_2 = 8;
void checkError(){
cudaError_t errSync = cudaGetLastError();
cudaError_t errAsync = cudaDeviceSynchr... | .file "tmpxft_000ab88c_00000000-6_cooley-tukey-parallel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5980:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <complex>
#include <math.h>
#include <thrust/complex.h>
#include <sys/time.h>
#include <cassert>
using namespace std;
__constant__ const int block_1 = 16;
__constant__ const int block_2 = 8;
void checkError(){
cudaError_t errSync = cudaGetLastError();
cudaError_t errAsync = cudaDeviceSynchr... | #include <hip/hip_runtime.h>
#include <iostream>
#include <complex>
#include <math.h>
#include <thrust/complex.h>
#include <sys/time.h>
#include <cassert>
using namespace std;
__constant__ const int block_1 = 16;
__constant__ const int block_2 = 8;
void checkError(){
hipError_t errSync = hipGetLastError();
hipError_t e... |
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