system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <algorithm>
#include <fstream>
#include <iostream>
#include <sstream>
#include <vector>
#define THREADS 64
// Error check-----
#define gpuErrchk(ans) \
{ gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line,
bool abort = true) {
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11deviceDFSk5PiS_S_S_
.globl _Z11deviceDFSk5PiS_S_S_
.p2align 8
.type _Z11deviceDFSk5PiS_S_S_,@function
_Z11deviceDFSk5PiS_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
// Kernel function to add the elements of two arrays
#include <curand_kernel.h>
//#include <pycuda-complex.hpp>
#include <stdio.h>
#include <fstream>
#include <iostream>
#include <ctime>
#define X_MIN -1.5f
#define X_MAX 1.5f
#define Y_MIN -3.2f
#define Y_MAX 2.0f
#define X_DIM 1440... | .file "tmpxft_00021cdb_00000000-6_cuda_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4021:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cuda... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
// Kernel function to add the elements of two arrays
#include <curand_kernel.h>
//#include <pycuda-complex.hpp>
#include <stdio.h>
#include <fstream>
#include <iostream>
#include <ctime>
#define X_MIN -1.5f
#define X_MAX 1.5f
#define Y_MIN -3.2f
#define Y_MAX 2.0f
#define X_DIM 1440... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
// Kernel function to add the elements of two arrays
#include <hiprand/hiprand_kernel.h>
//#include <pycuda-complex.hpp>
#include <stdio.h>
#include <fstream>
#include <iostream>
#include <ctime>
#define X_MIN -1.5f
#define X_MAX 1.5f
#define Y_MIN -3.2f... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
// Kernel function to add the elements of two arrays
#include <hiprand/hiprand_kernel.h>
//#include <pycuda-complex.hpp>
#include <stdio.h>
#include <fstream>
#include <iostream>
#include <ctime>
#define X_MIN -1.5f
#define X_MAX 1.5f
#define Y_MIN -3.2f... | .text
.file "cuda_test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__init_kerneli # -- Begin function _Z26__device_stub__init_kerneli
.p2align 4, 0... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00021cdb_00000000-6_cuda_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4021:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cuda... | .text
.file "cuda_test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__init_kerneli # -- Begin function _Z26__device_stub__init_kerneli
.p2align 4, 0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Demo code of Cuda programming lecture
*
* This programme illustrates how warp divergence may influence the performance of CUDA programme
*
*
*/
#include <cstdio>
#include <cstdlib>
#include <sys/time.h>
#define HALF_BLOCK_SIZE 512
#define BLOCK_SIZE 1024
#define LOOP_NUM 1024
//Kernel1 (has warp divergence)
__gl... | code for sm_80
Function : _Z7kernel2PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e2200000021... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Demo code of Cuda programming lecture
*
* This programme illustrates how warp divergence may influence the performance of CUDA programme
*
*
*/
#include <cstdio>
#include <cstdlib>
#include <sys/time.h>
#define HALF_BLOCK_SIZE 512
#define BLOCK_SIZE 1024
#define LOOP_NUM 1024
//Kernel1 (has warp divergence)
__gl... | .file "tmpxft_00092a66_00000000-6_warp_example.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Demo code of Cuda programming lecture
*
* This programme illustrates how warp divergence may influence the performance of CUDA programme
*
*
*/
#include <cstdio>
#include <cstdlib>
#include <sys/time.h>
#define HALF_BLOCK_SIZE 512
#define BLOCK_SIZE 1024
#define LOOP_NUM 1024
//Kernel1 (has warp divergence)
__gl... | /**
* Demo code of Cuda programming lecture
*
* This programme illustrates how warp divergence may influence the performance of CUDA programme
*
*
*/
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <sys/time.h>
#define HALF_BLOCK_SIZE 512
#define BLOCK_SIZE 1024
#define LOOP_NUM 1024
//Kerne... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Demo code of Cuda programming lecture
*
* This programme illustrates how warp divergence may influence the performance of CUDA programme
*
*
*/
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <sys/time.h>
#define HALF_BLOCK_SIZE 512
#define BLOCK_SIZE 1024
#define LOOP_NUM 1024
//Kerne... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PiS_
.globl _Z7kernel1PiS_
.p2align 8
.type _Z7kernel1PiS_,@function
_Z7kernel1PiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_al... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Demo code of Cuda programming lecture
*
* This programme illustrates how warp divergence may influence the performance of CUDA programme
*
*
*/
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <sys/time.h>
#define HALF_BLOCK_SIZE 512
#define BLOCK_SIZE 1024
#define LOOP_NUM 1024
//Kerne... | .text
.file "warp_example.hip"
.globl _Z22__device_stub__kernel1PiS_ # -- Begin function _Z22__device_stub__kernel1PiS_
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PiS_,@function
_Z22__device_stub__kernel1PiS_: # @_Z22__device_stub__kernel1PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7kernel2PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e2200000021... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1PiS_
.globl _Z7kernel1PiS_
.p2align 8
.type _Z7kernel1PiS_,@function
_Z7kernel1PiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_al... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00092a66_00000000-6_warp_example.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, ... | .text
.file "warp_example.hip"
.globl _Z22__device_stub__kernel1PiS_ # -- Begin function _Z22__device_stub__kernel1PiS_
.p2align 4, 0x90
.type _Z22__device_stub__kernel1PiS_,@function
_Z22__device_stub__kernel1PiS_: # @_Z22__device_stub__kernel1PiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
constexpr int BLOCK_SIZE = 1024;
//KERNEL implementation 1
__global__ void scan1(int *data_out, int *data_in, int *max, int N) {
__shared__ int partial[BLOCK_SIZE * 2];
int buf_output = 0;
int buf... | code for sm_80
Function : _Z5scan3PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
constexpr int BLOCK_SIZE = 1024;
//KERNEL implementation 1
__global__ void scan1(int *data_out, int *data_in, int *max, int N) {
__shared__ int partial[BLOCK_SIZE * 2];
int buf_output = 0;
int buf... | .file "tmpxft_00065ea6_00000000-6_scan.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4145:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
constexpr int BLOCK_SIZE = 1024;
//KERNEL implementation 1
__global__ void scan1(int *data_out, int *data_in, int *max, int N) {
__shared__ int partial[BLOCK_SIZE * 2];
int buf_output = 0;
int buf... | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
constexpr int BLOCK_SIZE = 1024;
//KERNEL implementation 1
__global__ void scan1(int *data_out, int *data_in, int *max, int N) {
__shared__ int partial[BLOCK_SIZE * 2... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
constexpr int BLOCK_SIZE = 1024;
//KERNEL implementation 1
__global__ void scan1(int *data_out, int *data_in, int *max, int N) {
__shared__ int partial[BLOCK_SIZE * 2... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5scan1PiS_S_i
.globl _Z5scan1PiS_S_i
.p2align 8
.type _Z5scan1PiS_S_i,@function
_Z5scan1PiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_mov_b32 s4, s15
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <cassert>
#include <cstdio>
#include <cstdlib>
#include <cmath>
#include <random>
constexpr int BLOCK_SIZE = 1024;
//KERNEL implementation 1
__global__ void scan1(int *data_out, int *data_in, int *max, int N) {
__shared__ int partial[BLOCK_SIZE * 2... | .text
.file "scan.hip"
.globl _Z20__device_stub__scan1PiS_S_i # -- Begin function _Z20__device_stub__scan1PiS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__scan1PiS_S_i,@function
_Z20__device_stub__scan1PiS_S_i: # @_Z20__device_stub__scan1PiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
mo... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
@Author: 3sne ( Mukur Panchani )
@FileName: q4MatAddAndMul2D.cu
@Task: CUDA program that calculates multiplication and addition of two matrices using 2D Grid & 2D Block.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <cuda_runtime.h>
__device__ int getTid() {
int blockSkip = (blockIdx.y * gr... | code for sm_80
Function : _Z19MatMulElementThreadPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R10, c[0x0][0x17c] ; /* 0x00005f00000a7a13 */
/* 0x000fe20... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
@Author: 3sne ( Mukur Panchani )
@FileName: q4MatAddAndMul2D.cu
@Task: CUDA program that calculates multiplication and addition of two matrices using 2D Grid & 2D Block.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <cuda_runtime.h>
__device__ int getTid() {
int blockSkip = (blockIdx.y * gr... | .file "tmpxft_00167afb_00000000-6_q4MatAddAndMul2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
@Author: 3sne ( Mukur Panchani )
@FileName: q4MatAddAndMul2D.cu
@Task: CUDA program that calculates multiplication and addition of two matrices using 2D Grid & 2D Block.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <cuda_runtime.h>
__device__ int getTid() {
int blockSkip = (blockIdx.y * gr... | /*
@Author: 3sne ( Mukur Panchani )
@FileName: q4MatAddAndMul2D.cu
@Task: CUDA program that calculates multiplication and addition of two matrices using 2D Grid & 2D Block.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
__device__ int getTid() {
int blockSkip = (blockIdx.y *... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
@Author: 3sne ( Mukur Panchani )
@FileName: q4MatAddAndMul2D.cu
@Task: CUDA program that calculates multiplication and addition of two matrices using 2D Grid & 2D Block.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
__device__ int getTid() {
int blockSkip = (blockIdx.y *... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19MatAddElementThreadPiS_S_
.globl _Z19MatAddElementThreadPiS_S_
.p2align 8
.type _Z19MatAddElementThreadPiS_S_,@function
_Z19MatAddElementThreadPiS_S_:
s_load_b32 s4, s[0:1], 0x18
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_load_b32 s5, s[0:1], ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
@Author: 3sne ( Mukur Panchani )
@FileName: q4MatAddAndMul2D.cu
@Task: CUDA program that calculates multiplication and addition of two matrices using 2D Grid & 2D Block.
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <hip/hip_runtime.h>
__device__ int getTid() {
int blockSkip = (blockIdx.y *... | .text
.file "q4MatAddAndMul2D.hip"
.globl _Z34__device_stub__MatAddElementThreadPiS_S_ # -- Begin function _Z34__device_stub__MatAddElementThreadPiS_S_
.p2align 4, 0x90
.type _Z34__device_stub__MatAddElementThreadPiS_S_,@function
_Z34__device_stub__MatAddElementThreadPiS_S_: # @_Z34__device_stub__MatAddElementThreadPiS... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00167afb_00000000-6_q4MatAddAndMul2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... | .text
.file "q4MatAddAndMul2D.hip"
.globl _Z34__device_stub__MatAddElementThreadPiS_S_ # -- Begin function _Z34__device_stub__MatAddElementThreadPiS_S_
.p2align 4, 0x90
.type _Z34__device_stub__MatAddElementThreadPiS_S_,@function
_Z34__device_stub__MatAddElementThreadPiS_S_: # @_Z34__device_stub__MatAddElementThreadPiS... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void _bcnn_backward_depthwise_conv_weight_kernel( int nthreads, float *dst_grad, float *src_data, int batch_size, const int channels, int dst_h, int dst_w, const int src_h, const int src_w, int kernel_sz, int stride, int pad, float *weight_diff) {
int i, n, c, h, w, kw, kh, h_out_s, w_o... | .file "tmpxft_00130caa_00000000-6__bcnn_backward_depthwise_conv_weight_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUn... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void _bcnn_backward_depthwise_conv_weight_kernel( int nthreads, float *dst_grad, float *src_data, int batch_size, const int channels, int dst_h, int dst_w, const int src_h, const int src_w, int kernel_sz, int stride, int pad, float *weight_diff) {
int i, n, c, h, w, kw, kh, h_out_s, w_o... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _bcnn_backward_depthwise_conv_weight_kernel( int nthreads, float *dst_grad, float *src_data, int batch_size, const int channels, int dst_h, int dst_w, const int src_h, const int src_w, int kernel_sz, int stride, int pad, float *weight_diff) {
int i, n, ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _bcnn_backward_depthwise_conv_weight_kernel( int nthreads, float *dst_grad, float *src_data, int batch_size, const int channels, int dst_h, int dst_w, const int src_h, const int src_w, int kernel_sz, int stride, int pad, float *weight_diff) {
int i, n, ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z43_bcnn_backward_depthwise_conv_weight_kerneliPfS_iiiiiiiiiS_
.globl _Z43_bcnn_backward_depthwise_conv_weight_kerneliPfS_iiiiiiiiiS_
.p2align 8
.type _Z43_bcnn_backward_depthwise_conv_weight_kerneliPfS_iiiiiiiiiS_,@function
_Z43_bcnn_backward_depthwise_con... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _bcnn_backward_depthwise_conv_weight_kernel( int nthreads, float *dst_grad, float *src_data, int batch_size, const int channels, int dst_h, int dst_w, const int src_h, const int src_w, int kernel_sz, int stride, int pad, float *weight_diff) {
int i, n, ... | .text
.file "_bcnn_backward_depthwise_conv_weight_kernel.hip"
.globl _Z58__device_stub___bcnn_backward_depthwise_conv_weight_kerneliPfS_iiiiiiiiiS_ # -- Begin function _Z58__device_stub___bcnn_backward_depthwise_conv_weight_kerneliPfS_iiiiiiiiiS_
.p2align 4, 0x90
.type _Z58__device_stub___bcnn_backward_depthwise_conv_w... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00130caa_00000000-6__bcnn_backward_depthwise_conv_weight_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUn... | .text
.file "_bcnn_backward_depthwise_conv_weight_kernel.hip"
.globl _Z58__device_stub___bcnn_backward_depthwise_conv_weight_kerneliPfS_iiiiiiiiiS_ # -- Begin function _Z58__device_stub___bcnn_backward_depthwise_conv_weight_kerneliPfS_iiiiiiiiiS_
.p2align 4, 0x90
.type _Z58__device_stub___bcnn_backward_depthwise_conv_w... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include "StdAfx.h"
#include <iostream>
#include <stdio.h>
#include <cuda_runtime_api.h>
#define MAX_FILE_NAME_CHARS 40
#define MAX_OUTFILE_NAME_CHARS 45
#define FRAMES_PER_ITER 256
#define PROMETHEUS_TESLA_C2075 1
using namespace std;
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafe... | code for sm_80
Function : _Z8cudafuncPcS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e2800000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include "StdAfx.h"
#include <iostream>
#include <stdio.h>
#include <cuda_runtime_api.h>
#define MAX_FILE_NAME_CHARS 40
#define MAX_OUTFILE_NAME_CHARS 45
#define FRAMES_PER_ITER 256
#define PROMETHEUS_TESLA_C2075 1
using namespace std;
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafe... | .file "tmpxft_00033dc2_00000000-6_t_fiprj2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3678:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaU... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include "StdAfx.h"
#include <iostream>
#include <stdio.h>
#include <cuda_runtime_api.h>
#define MAX_FILE_NAME_CHARS 40
#define MAX_OUTFILE_NAME_CHARS 45
#define FRAMES_PER_ITER 256
#define PROMETHEUS_TESLA_C2075 1
using namespace std;
// Define this to turn on error checking
#define CUDA_ERROR_CHECK
#define CudaSafe... | //#include "StdAfx.h"
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#define MAX_FILE_NAME_CHARS 40
#define MAX_OUTFILE_NAME_CHARS 45
#define FRAMES_PER_ITER 256
#define PROMETHEUS_TESLA_C2075 1
using namespace std;
// Define this to turn on error checking
#define C... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //#include "StdAfx.h"
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#define MAX_FILE_NAME_CHARS 40
#define MAX_OUTFILE_NAME_CHARS 45
#define FRAMES_PER_ITER 256
#define PROMETHEUS_TESLA_C2075 1
using namespace std;
// Define this to turn on error checking
#define C... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cudafuncPcS_
.globl _Z8cudafuncPcS_
.p2align 8
.type _Z8cudafuncPcS_,@function
_Z8cudafuncPcS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_mov_b32 s2, exec_lo
s_mul_i32 s15, s15, s4
s_delay_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //#include "StdAfx.h"
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#define MAX_FILE_NAME_CHARS 40
#define MAX_OUTFILE_NAME_CHARS 45
#define FRAMES_PER_ITER 256
#define PROMETHEUS_TESLA_C2075 1
using namespace std;
// Define this to turn on error checking
#define C... | .text
.file "t_fiprj2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__cudafuncPcS_ # -- Begin function _Z23__device_stub__cudafuncPcS_
.p2align 4, 0x... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8cudafuncPcS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e2800000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cudafuncPcS_
.globl _Z8cudafuncPcS_
.p2align 8
.type _Z8cudafuncPcS_,@function
_Z8cudafuncPcS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_mov_b32 s2, exec_lo
s_mul_i32 s15, s15, s4
s_delay_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // From CUDA for Engineering
// dist_v2_cuda_unified/kernel.cu
#include <iostream>
#include <stdio.h>
#include <cuda_runtime.h>
#define N 1000000000
#define TPB 32
#define DEBUG 0
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1)... | code for sm_80
Function : _Z14distanceKernelPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // From CUDA for Engineering
// dist_v2_cuda_unified/kernel.cu
#include <iostream>
#include <stdio.h>
#include <cuda_runtime.h>
#define N 1000000000
#define TPB 32
#define DEBUG 0
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1)... | .file "tmpxft_000fade3_00000000-6_dist_v2_unified.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // From CUDA for Engineering
// dist_v2_cuda_unified/kernel.cu
#include <iostream>
#include <stdio.h>
#include <cuda_runtime.h>
#define N 1000000000
#define TPB 32
#define DEBUG 0
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1)... | // From CUDA for Engineering
// dist_v2_cuda_unified/kernel.cu
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define N 1000000000
#define TPB 32
#define DEBUG 0
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // From CUDA for Engineering
// dist_v2_cuda_unified/kernel.cu
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define N 1000000000
#define TPB 32
#define DEBUG 0
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfS_f
.globl _Z14distanceKernelPfS_f
.p2align 8
.type _Z14distanceKernelPfS_f,@function
_Z14distanceKernelPfS_f:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // From CUDA for Engineering
// dist_v2_cuda_unified/kernel.cu
#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>
#define N 1000000000
#define TPB 32
#define DEBUG 0
float scale(int i, int n) {
return ((float)i) / (n - 1);
}
__device__
float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - ... | .text
.file "dist_v2_unified.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5scaleii # -- Begin function _Z5scaleii
.p2align 4, 0x90
.type _Z5sc... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14distanceKernelPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfS_f
.globl _Z14distanceKernelPfS_f
.p2align 8
.type _Z14distanceKernelPfS_f,@function
_Z14distanceKernelPfS_f:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fade3_00000000-6_dist_v2_unified.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call ... | .text
.file "dist_v2_unified.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z5scaleii # -- Begin function _Z5scaleii
.p2align 4, 0x90
.type _Z5sc... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#define ASCII_CHARS 128
int mod(int a, int b) {
return (a%b+b)%b;
}
void printrow(float *msg_v_list) {
int i;
for (i = 0; i < 16; i++) {
printf("PRINTROW: %f\n", msg_v_list[i]);
}
}
__global__ void mtxEncrypt(float *secretKey, float *... | code for sm_80
Function : _Z10mtxEncryptPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*00... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#define ASCII_CHARS 128
int mod(int a, int b) {
return (a%b+b)%b;
}
void printrow(float *msg_v_list) {
int i;
for (i = 0; i < 16; i++) {
printf("PRINTROW: %f\n", msg_v_list[i]);
}
}
__global__ void mtxEncrypt(float *secretKey, float *... | .file "tmpxft_000d4982_00000000-6_hill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#define ASCII_CHARS 128
int mod(int a, int b) {
return (a%b+b)%b;
}
void printrow(float *msg_v_list) {
int i;
for (i = 0; i < 16; i++) {
printf("PRINTROW: %f\n", msg_v_list[i]);
}
}
__global__ void mtxEncrypt(float *secretKey, float *... | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define ASCII_CHARS 128
int mod(int a, int b) {
return (a%b+b)%b;
}
void printrow(float *msg_v_list) {
int i;
for (i = 0; i < 16; i++) {
printf("PRINTROW: %f\n", msg_v_list[i]);
}
}
__global__ void mtxEncrypt(float *secretKey, floa... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define ASCII_CHARS 128
int mod(int a, int b) {
return (a%b+b)%b;
}
void printrow(float *msg_v_list) {
int i;
for (i = 0; i < 16; i++) {
printf("PRINTROW: %f\n", msg_v_list[i]);
}
}
__global__ void mtxEncrypt(float *secretKey, floa... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mtxEncryptPfS_S_i
.globl _Z10mtxEncryptPfS_S_i
.p2align 8
.type _Z10mtxEncryptPfS_S_i,@function
_Z10mtxEncryptPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define ASCII_CHARS 128
int mod(int a, int b) {
return (a%b+b)%b;
}
void printrow(float *msg_v_list) {
int i;
for (i = 0; i < 16; i++) {
printf("PRINTROW: %f\n", msg_v_list[i]);
}
}
__global__ void mtxEncrypt(float *secretKey, floa... | .text
.file "hill.hip"
.globl _Z3modii # -- Begin function _Z3modii
.p2align 4, 0x90
.type _Z3modii,@function
_Z3modii: # @_Z3modii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
movl %edi, %eax
cltd
idivl %esi
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10mtxEncryptPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*00... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10mtxEncryptPfS_S_i
.globl _Z10mtxEncryptPfS_S_i
.p2align 8
.type _Z10mtxEncryptPfS_S_i,@function
_Z10mtxEncryptPfS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d4982_00000000-6_hill.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "hill.hip"
.globl _Z3modii # -- Begin function _Z3modii
.p2align 4, 0x90
.type _Z3modii,@function
_Z3modii: # @_Z3modii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
movl %edi, %eax
cltd
idivl %esi
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void multMatrixGPU(const float *matrixA, const size_t rowA, const size_t columnA, const float *matrixB, const size_t rowB, const size_t columnB, float *matrixC)
{
__shared__ float ds_A[TILE_SIZE][TILE_SIZE];
__shared__ float ds... | code for sm_80
Function : _Z13multMatrixGPUPKfmmS0_mmPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void multMatrixGPU(const float *matrixA, const size_t rowA, const size_t columnA, const float *matrixB, const size_t rowB, const size_t columnB, float *matrixC)
{
__shared__ float ds_A[TILE_SIZE][TILE_SIZE];
__shared__ float ds... | .file "tmpxft_001231c0_00000000-6_multMatrixGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void multMatrixGPU(const float *matrixA, const size_t rowA, const size_t columnA, const float *matrixB, const size_t rowB, const size_t columnB, float *matrixC)
{
__shared__ float ds_A[TILE_SIZE][TILE_SIZE];
__shared__ float ds... | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void multMatrixGPU(const float *matrixA, const size_t rowA, const size_t columnA, const float *matrixB, const size_t rowB, const size_t columnB, float *matrixC)
{
__shared__ float ds_A[TILE_SIZE][TI... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void multMatrixGPU(const float *matrixA, const size_t rowA, const size_t columnA, const float *matrixB, const size_t rowB, const size_t columnB, float *matrixC)
{
__shared__ float ds_A[TILE_SIZE][TI... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13multMatrixGPUPKfmmS0_mmPf
.globl _Z13multMatrixGPUPKfmmS0_mmPf
.p2align 8
.type _Z13multMatrixGPUPKfmmS0_mmPf,@function
_Z13multMatrixGPUPKfmmS0_mmPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b256 s[4:11], s[0:1], 0x0
v_bfe_u32 v3, v0, 1... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void multMatrixGPU(const float *matrixA, const size_t rowA, const size_t columnA, const float *matrixB, const size_t rowB, const size_t columnB, float *matrixC)
{
__shared__ float ds_A[TILE_SIZE][TI... | .text
.file "multMatrixGPU.hip"
.globl _Z28__device_stub__multMatrixGPUPKfmmS0_mmPf # -- Begin function _Z28__device_stub__multMatrixGPUPKfmmS0_mmPf
.p2align 4, 0x90
.type _Z28__device_stub__multMatrixGPUPKfmmS0_mmPf,@function
_Z28__device_stub__multMatrixGPUPKfmmS0_mmPf: # @_Z28__device_stub__multMatrixGPUPKfmmS0_mmPf... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13multMatrixGPUPKfmmS0_mmPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/*... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13multMatrixGPUPKfmmS0_mmPf
.globl _Z13multMatrixGPUPKfmmS0_mmPf
.p2align 8
.type _Z13multMatrixGPUPKfmmS0_mmPf,@function
_Z13multMatrixGPUPKfmmS0_mmPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x44
s_load_b256 s[4:11], s[0:1], 0x0
v_bfe_u32 v3, v0, 1... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001231c0_00000000-6_multMatrixGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... | .text
.file "multMatrixGPU.hip"
.globl _Z28__device_stub__multMatrixGPUPKfmmS0_mmPf # -- Begin function _Z28__device_stub__multMatrixGPUPKfmmS0_mmPf
.p2align 4, 0x90
.type _Z28__device_stub__multMatrixGPUPKfmmS0_mmPf,@function
_Z28__device_stub__multMatrixGPUPKfmmS0_mmPf: # @_Z28__device_stub__multMatrixGPUPKfmmS0_mmPf... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void histogram_kernel(float* magnitude, float* phase, float* histograms, int input_width, int input_height, int cell_grid_width, int cell_grid_height, int magnitude_step, int phase_step, int histograms_step, int cell_width, int cell_height, int num_bins)
{
//TODO: make the buffer sizes ... | .file "tmpxft_0011a093_00000000-6_histogram_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void histogram_kernel(float* magnitude, float* phase, float* histograms, int input_width, int input_height, int cell_grid_width, int cell_grid_height, int magnitude_step, int phase_step, int histograms_step, int cell_width, int cell_height, int num_bins)
{
//TODO: make the buffer sizes ... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_kernel(float* magnitude, float* phase, float* histograms, int input_width, int input_height, int cell_grid_width, int cell_grid_height, int magnitude_step, int phase_step, int histograms_step, int cell_width, int cell_height, int num_bins)
{
/... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_kernel(float* magnitude, float* phase, float* histograms, int input_width, int input_height, int cell_grid_width, int cell_grid_height, int magnitude_step, int phase_step, int histograms_step, int cell_width, int cell_height, int num_bins)
{
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16histogram_kernelPfS_S_iiiiiiiiii
.globl _Z16histogram_kernelPfS_S_iiiiiiiiii
.p2align 8
.type _Z16histogram_kernelPfS_S_iiiiiiiiii,@function
_Z16histogram_kernelPfS_S_iiiiiiiiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x4c
s_load_b32 s5, s[0:1], 0x18
v_a... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_kernel(float* magnitude, float* phase, float* histograms, int input_width, int input_height, int cell_grid_width, int cell_grid_height, int magnitude_step, int phase_step, int histograms_step, int cell_width, int cell_height, int num_bins)
{
/... | .text
.file "histogram_kernel.hip"
.globl _Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii # -- Begin function _Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii
.p2align 4, 0x90
.type _Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii,@function
_Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii: # @_Z31__device_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011a093_00000000-6_histogram_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... | .text
.file "histogram_kernel.hip"
.globl _Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii # -- Begin function _Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii
.p2align 4, 0x90
.type _Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii,@function
_Z31__device_stub__histogram_kernelPfS_S_iiiiiiiiii: # @_Z31__device_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<cuda.h>
#define BLOCK_DIM 16
__global__ void matrixMultKernel(int *a,int *b,int *c,int width);
int main(){
int curr=2;
int N=BLOCK_DIM*curr;
printf("------------------------------------------\n");
while(N<=BLOCK_DIM*16){
int a[N][N], b[N][N], gpu_mul[N][N],... | code for sm_80
Function : _Z16matrixMultKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000e22000000260... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<cuda.h>
#define BLOCK_DIM 16
__global__ void matrixMultKernel(int *a,int *b,int *c,int width);
int main(){
int curr=2;
int N=BLOCK_DIM*curr;
printf("------------------------------------------\n");
while(N<=BLOCK_DIM*16){
int a[N][N], b[N][N], gpu_mul[N][N],... | .file "tmpxft_0009e8cb_00000000-6_MatMultS.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<cuda.h>
#define BLOCK_DIM 16
__global__ void matrixMultKernel(int *a,int *b,int *c,int width);
int main(){
int curr=2;
int N=BLOCK_DIM*curr;
printf("------------------------------------------\n");
while(N<=BLOCK_DIM*16){
int a[N][N], b[N][N], gpu_mul[N][N],... | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<hip/hip_runtime.h>
#define BLOCK_DIM 16
__global__ void matrixMultKernel(int *a,int *b,int *c,int width);
int main(){
int curr=2;
int N=BLOCK_DIM*curr;
printf("------------------------------------------\n");
while(N<=BLOCK_DIM*16){
int a[N][N], b[N][N], gpu... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<hip/hip_runtime.h>
#define BLOCK_DIM 16
__global__ void matrixMultKernel(int *a,int *b,int *c,int width);
int main(){
int curr=2;
int N=BLOCK_DIM*curr;
printf("------------------------------------------\n");
while(N<=BLOCK_DIM*16){
int a[N][N], b[N][N], gpu... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrixMultKernelPiS_S_i
.globl _Z16matrixMultKernelPiS_S_i
.p2align 8
.type _Z16matrixMultKernelPiS_S_i,@function
_Z16matrixMultKernelPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
v_mov_b32_e32 v1, ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<time.h>
#include<hip/hip_runtime.h>
#define BLOCK_DIM 16
__global__ void matrixMultKernel(int *a,int *b,int *c,int width);
int main(){
int curr=2;
int N=BLOCK_DIM*curr;
printf("------------------------------------------\n");
while(N<=BLOCK_DIM*16){
int a[N][N], b[N][N], gpu... | .text
.file "MatMultS.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.LCPI0_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16matrixMultKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R12, SR_CTAID.Y ; /* 0x00000000000c7919 */
/* 0x000e22000000260... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrixMultKernelPiS_S_i
.globl _Z16matrixMultKernelPiS_S_i
.p2align 8
.type _Z16matrixMultKernelPiS_S_i,@function
_Z16matrixMultKernelPiS_S_i:
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v5, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
v_mov_b32_e32 v1, ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009e8cb_00000000-6_MatMultS.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... | .text
.file "MatMultS.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.LCPI0_1:
.long 0x49742400 # float 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define int8 unsigned char
#include <cstdlib>
#include <iostream>
using std::cout;
inline void gpuAssert(cudaError_t code) {
if (code != cudaSuccess) {
std::cout << cudaGetErrorString(code) << "\n";
}
}
__global__ void adjust_hue_hwc(const int height, const int width,
int8 * const input, int8 * const output) {
// multi... | .file "tmpxft_00010cfb_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnr... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define int8 unsigned char
#include <cstdlib>
#include <iostream>
using std::cout;
inline void gpuAssert(cudaError_t code) {
if (code != cudaSuccess) {
std::cout << cudaGetErrorString(code) << "\n";
}
}
__global__ void adjust_hue_hwc(const int height, const int width,
int8 * const input, int8 * const output) {
// multi... | #define int8 unsigned char
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <iostream>
using std::cout;
inline void gpuAssert(hipError_t code) {
if (code != hipSuccess) {
std::cout << hipGetErrorString(code) << "\n";
}
}
__global__ void adjust_hue_hwc(const int height, const int width,
int8 * const input, int8 ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define int8 unsigned char
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <iostream>
using std::cout;
inline void gpuAssert(hipError_t code) {
if (code != hipSuccess) {
std::cout << hipGetErrorString(code) << "\n";
}
}
__global__ void adjust_hue_hwc(const int height, const int width,
int8 * const input, int8 ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14adjust_hue_hwciiPhS_
.globl _Z14adjust_hue_hwciiPhS_
.p2align 8
.type _Z14adjust_hue_hwciiPhS_,@function
_Z14adjust_hue_hwciiPhS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define int8 unsigned char
#include <hip/hip_runtime.h>
#include <cstdlib>
#include <iostream>
using std::cout;
inline void gpuAssert(hipError_t code) {
if (code != hipSuccess) {
std::cout << hipGetErrorString(code) << "\n";
}
}
__global__ void adjust_hue_hwc(const int height, const int width,
int8 * const input, int8 ... | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__adjust_hue_hwciiPhS_ # -- Begin function _Z29__device_stub__adjust_hue_hwciiPhS_
... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00010cfb_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnr... | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__adjust_hue_hwciiPhS_ # -- Begin function _Z29__device_stub__adjust_hue_hwciiPhS_
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void
mat_add(float *a, float *b, float *c, int limit)
{
const int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < limit)
{
c[i] = a[i] + b[i];
}
} | code for sm_80
Function : _Z7mat_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void
mat_add(float *a, float *b, float *c, int limit)
{
const int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < limit)
{
c[i] = a[i] + b[i];
}
} | .file "tmpxft_0010fc22_00000000-6_mat_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void
mat_add(float *a, float *b, float *c, int limit)
{
const int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < limit)
{
c[i] = a[i] + b[i];
}
} | #include <hip/hip_runtime.h>
__global__ void
mat_add(float *a, float *b, float *c, int limit)
{
const int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < limit)
{
c[i] = a[i] + b[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_add(float *a, float *b, float *c, int limit)
{
const int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < limit)
{
c[i] = a[i] + b[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_i
.globl _Z7mat_addPfS_S_i
.p2align 8
.type _Z7mat_addPfS_S_i,@function
_Z7mat_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_add(float *a, float *b, float *c, int limit)
{
const int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < limit)
{
c[i] = a[i] + b[i];
}
} | .text
.file "mat_add.hip"
.globl _Z22__device_stub__mat_addPfS_S_i # -- Begin function _Z22__device_stub__mat_addPfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__mat_addPfS_S_i,@function
_Z22__device_stub__mat_addPfS_S_i: # @_Z22__device_stub__mat_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_of... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7mat_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7mat_addPfS_S_i
.globl _Z7mat_addPfS_S_i
.p2align 8
.type _Z7mat_addPfS_S_i,@function
_Z7mat_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010fc22_00000000-6_mat_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "mat_add.hip"
.globl _Z22__device_stub__mat_addPfS_S_i # -- Begin function _Z22__device_stub__mat_addPfS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__mat_addPfS_S_i,@function
_Z22__device_stub__mat_addPfS_S_i: # @_Z22__device_stub__mat_addPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_of... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C" {
__host__ __device__ __forceinline__ int
index_strides(const int i, const int j, const int k, const dim3 strides) {
return i * strides.x + j * strides.y + k * strides.z;
}
__global__ void laplace3d_strides(double *d, double *n, int Nx, int Ny, int Nz, int istride, int jstride, int kstride) {
dim3 sizes(Nx,N... | code for sm_80
Function : set_val
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R4, 0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C" {
__host__ __device__ __forceinline__ int
index_strides(const int i, const int j, const int k, const dim3 strides) {
return i * strides.x + j * strides.y + k * strides.z;
}
__global__ void laplace3d_strides(double *d, double *n, int Nx, int Ny, int Nz, int istride, int jstride, int kstride) {
dim3 sizes(Nx,N... | .file "tmpxft_00178a7b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C" {
__host__ __device__ __forceinline__ int
index_strides(const int i, const int j, const int k, const dim3 strides) {
return i * strides.x + j * strides.y + k * strides.z;
}
__global__ void laplace3d_strides(double *d, double *n, int Nx, int Ny, int Nz, int istride, int jstride, int kstride) {
dim3 sizes(Nx,N... | #include <hip/hip_runtime.h>
extern "C" {
__host__ __device__ __forceinline__ int
index_strides(const int i, const int j, const int k, const dim3 strides) {
return i * strides.x + j * strides.y + k * strides.z;
}
__global__ void laplace3d_strides(double *d, double *n, int Nx, int Ny, int Nz, int istride, int jstride, i... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C" {
__host__ __device__ __forceinline__ int
index_strides(const int i, const int j, const int k, const dim3 strides) {
return i * strides.x + j * strides.y + k * strides.z;
}
__global__ void laplace3d_strides(double *d, double *n, int Nx, int Ny, int Nz, int istride, int jstride, i... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected laplace3d_strides
.globl laplace3d_strides
.p2align 8
.type laplace3d_strides,@function
laplace3d_strides:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x18
v_and_b32_e32 v1, ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C" {
__host__ __device__ __forceinline__ int
index_strides(const int i, const int j, const int k, const dim3 strides) {
return i * strides.x + j * strides.y + k * strides.z;
}
__global__ void laplace3d_strides(double *d, double *n, int Nx, int Ny, int Nz, int istride, int jstride, i... | .text
.file "kernel.hip"
.globl __device_stub__laplace3d_strides # -- Begin function __device_stub__laplace3d_strides
.p2align 4, 0x90
.type __device_stub__laplace3d_strides,@function
__device_stub__laplace3d_strides: # @__device_stub__laplace3d_strides
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : set_val
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R4, 0... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected laplace3d_strides
.globl laplace3d_strides
.p2align 8
.type laplace3d_strides,@function
laplace3d_strides:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s6, s[0:1], 0x18
v_and_b32_e32 v1, ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00178a7b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "kernel.hip"
.globl __device_stub__laplace3d_strides # -- Begin function __device_stub__laplace3d_strides
.p2align 4, 0x90
.type __device_stub__laplace3d_strides,@function
__device_stub__laplace3d_strides: # @__device_stub__laplace3d_strides
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#include "RoomFusionDLL.cuh"
// ªì©l¤ÆCUDA¡A¦ý¨ä¹ê³oÓ¨ç¼Æ¤]¥i¥H¤£©I¥s¡A¨Ï¥ÎCUDAªº¹w³]È´NOK
bool InitCUDA()
{
int count;
cudaGetDeviceCount(&count);
if (count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for (i = 0; i < count; i++) {
cudaDeviceProp prop;
if (cudaGetDevice... | .file "tmpxft_0019c5de_00000000-6_RoomFusionDLL.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#include "RoomFusionDLL.cuh"
// ªì©l¤ÆCUDA¡A¦ý¨ä¹ê³oÓ¨ç¼Æ¤]¥i¥H¤£©I¥s¡A¨Ï¥ÎCUDAªº¹w³]È´NOK
bool InitCUDA()
{
int count;
cudaGetDeviceCount(&count);
if (count == 0) {
fprintf(stderr, "There is no device.\n");
return false;
}
int i;
for (i = 0; i < count; i++) {
cudaDeviceProp prop;
if (cudaGetDevice... | #include <hip/hip_runtime.h>
// ¥Î¥HÀˬd¨âÓ¯BÂI¼Æ¬O§_¤Q¤À±µªñ
#define nearlyEqual(a,b) ( a - b < 0.005f && a - b > -0.005f )
bool InitCUDA();
void runGPUApplyDepth(unsigned char* image, float* depth, int imageWidth, int imageHeight, float threshold);
void runGPUApplyCorrection(float* depth, int imageWidth, int imageHe... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// ¥Î¥HÀˬd¨âÓ¯BÂI¼Æ¬O§_¤Q¤À±µªñ
#define nearlyEqual(a,b) ( a - b < 0.005f && a - b > -0.005f )
bool InitCUDA();
void runGPUApplyDepth(unsigned char* image, float* depth, int imageWidth, int imageHeight, float threshold);
void runGPUApplyCorrection(float* depth, int imageWidth, int imageHe... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// ¥Î¥HÀˬd¨âÓ¯BÂI¼Æ¬O§_¤Q¤À±µªñ
#define nearlyEqual(a,b) ( a - b < 0.005f && a - b > -0.005f )
bool InitCUDA();
void runGPUApplyDepth(unsigned char* image, float* depth, int imageWidth, int imageHeight, float threshold);
void runGPUApplyCorrection(float* depth, int imageWidth, int imageHe... | .text
.file "RoomFusionDLL.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-pr... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18gpuApplyCorrectionPfiiffffffffffffffffffffffff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x000... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019c5de_00000000-6_RoomFusionDLL.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... | .text
.file "RoomFusionDLL.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-pr... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* compute 0 + 1 + 2 + ... + 1023 using cuda - in a bad way
*/
#include <stdlib.h>
#include <stdio.h>
__global__ void sum(int *result) {
*result = *result + threadIdx.x;
}
int main() {
int h_result = 0;
void *d_result;
cudaMalloc(&d_result,sizeof(int));
cudaMemcpy(d_result,&h_result,sizeof(int),cudaMemcpyHostToDevice... | code for sm_80
Function : _Z3sumPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* compute 0 + 1 + 2 + ... + 1023 using cuda - in a bad way
*/
#include <stdlib.h>
#include <stdio.h>
__global__ void sum(int *result) {
*result = *result + threadIdx.x;
}
int main() {
int h_result = 0;
void *d_result;
cudaMalloc(&d_result,sizeof(int));
cudaMemcpy(d_result,&h_result,sizeof(int),cudaMemcpyHostToDevice... | .file "tmpxft_0013f1ca_00000000-6_no-sync-cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* compute 0 + 1 + 2 + ... + 1023 using cuda - in a bad way
*/
#include <stdlib.h>
#include <stdio.h>
__global__ void sum(int *result) {
*result = *result + threadIdx.x;
}
int main() {
int h_result = 0;
void *d_result;
cudaMalloc(&d_result,sizeof(int));
cudaMemcpy(d_result,&h_result,sizeof(int),cudaMemcpyHostToDevice... | /*
* compute 0 + 1 + 2 + ... + 1023 using cuda - in a bad way
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void sum(int *result) {
*result = *result + threadIdx.x;
}
int main() {
int h_result = 0;
void *d_result;
hipMalloc(&d_result,sizeof(int));
hipMemcpy(d_result,&h_result,sizeof(... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* compute 0 + 1 + 2 + ... + 1023 using cuda - in a bad way
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void sum(int *result) {
*result = *result + threadIdx.x;
}
int main() {
int h_result = 0;
void *d_result;
hipMalloc(&d_result,sizeof(int));
hipMemcpy(d_result,&h_result,sizeof(... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPi
.globl _Z3sumPi
.p2align 8
.type _Z3sumPi,@function
_Z3sumPi:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* compute 0 + 1 + 2 + ... + 1023 using cuda - in a bad way
*/
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void sum(int *result) {
*result = *result + threadIdx.x;
}
int main() {
int h_result = 0;
void *d_result;
hipMalloc(&d_result,sizeof(int));
hipMemcpy(d_result,&h_result,sizeof(... | .text
.file "no-sync-cuda.hip"
.globl _Z18__device_stub__sumPi # -- Begin function _Z18__device_stub__sumPi
.p2align 4, 0x90
.type _Z18__device_stub__sumPi,@function
_Z18__device_stub__sumPi: # @_Z18__device_stub__sumPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rs... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPi
.globl _Z3sumPi
.p2align 8
.type _Z3sumPi,@function
_Z3sumPi:
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013f1ca_00000000-6_no-sync-cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, ... | .text
.file "no-sync-cuda.hip"
.globl _Z18__device_stub__sumPi # -- Begin function _Z18__device_stub__sumPi
.p2align 4, 0x90
.type _Z18__device_stub__sumPi,@function
_Z18__device_stub__sumPi: # @_Z18__device_stub__sumPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rs... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void CutSubImageKernel_SingleParams(float *input, float *output, float subImageX, float subImageY, float subImageDiameter, bool safeBounds, int inputWidth, int inputHeight, int outputWidth, int outputHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ thre... | code for sm_80
Function : _Z30CutSubImageKernel_SingleParamsPfS_fffbiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x00000... |
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