system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
__global__ void print_gpu(void) {
printf("Houston, we have a problem in section [%d,%d] \
From Apollo 13\n", threadIdx.x,blockIdx.x);
}
int main(void) {
printf("This is Houston. Say again, please. \
From Base\n");
print_gpu<<<2,2>>>();
hipDeviceSynchroni... | .text
.file "hello_houston.hip"
.globl _Z24__device_stub__print_gpuv # -- Begin function _Z24__device_stub__print_gpuv
.p2align 4, 0x90
.type _Z24__device_stub__print_gpuv,@function
_Z24__device_stub__print_gpuv: # @_Z24__device_stub__print_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
l... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011f001_00000000-6_hello_houston.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... | .text
.file "hello_houston.hip"
.globl _Z24__device_stub__print_gpuv # -- Begin function _Z24__device_stub__print_gpuv
.p2align 4, 0x90
.type _Z24__device_stub__print_gpuv,@function
_Z24__device_stub__print_gpuv: # @_Z24__device_stub__print_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
l... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 30
//typedef long long int ll;
__global__ void align(char *key , char *s , int *scores , int n , int num)
{
int GP = -1 , MR = 1;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < num)
{
int i , j , k , tmp;
int nm[N + 1][N + 1];
char r1[2*N+2] , r2[2*N+2];
... | .file "tmpxft_0000efaa_00000000-6_nm_align.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 30
//typedef long long int ll;
__global__ void align(char *key , char *s , int *scores , int n , int num)
{
int GP = -1 , MR = 1;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < num)
{
int i , j , k , tmp;
int nm[N + 1][N + 1];
char r1[2*N+2] , r2[2*N+2];
... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 30
//typedef long long int ll;
__global__ void align(char *key , char *s , int *scores , int n , int num)
{
int GP = -1 , MR = 1;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < num)
{
int i , j , k , tmp;
int nm[N + 1][N + 1];
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 30
//typedef long long int ll;
__global__ void align(char *key , char *s , int *scores , int n , int num)
{
int GP = -1 , MR = 1;
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < num)
{
int i , j , k , tmp;
int nm[N + 1][N + 1];
... | .text
.file "nm_align.hip"
.globl _Z20__device_stub__alignPcS_Piii # -- Begin function _Z20__device_stub__alignPcS_Piii
.p2align 4, 0x90
.type _Z20__device_stub__alignPcS_Piii,@function
_Z20__device_stub__alignPcS_Piii: # @_Z20__device_stub__alignPcS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offse... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000efaa_00000000-6_nm_align.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp... | .text
.file "nm_align.hip"
.globl _Z20__device_stub__alignPcS_Piii # -- Begin function _Z20__device_stub__alignPcS_Piii
.p2align 4, 0x90
.type _Z20__device_stub__alignPcS_Piii,@function
_Z20__device_stub__alignPcS_Piii: # @_Z20__device_stub__alignPcS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offse... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,int var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float* var_13,float* var... | .file "tmpxft_000dee7b_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,int var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float* var_13,float* var... | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,int var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float va... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,float var_2,float var_3,float var_4,int var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float va... | .text
.file "test.hip"
.globl _Z22__device_stub__computefifffifffffffPfS_S_fffffffffff # -- Begin function _Z22__device_stub__computefifffifffffffPfS_S_fffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifffifffffffPfS_S_fffffffffff,@function
_Z22__device_stub__computefifffifffffffPfS_S_fffffffffff: # @_Z22_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dee7b_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "test.hip"
.globl _Z22__device_stub__computefifffifffffffPfS_S_fffffffffff # -- Begin function _Z22__device_stub__computefifffifffffffPfS_S_fffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefifffifffffffPfS_S_fffffffffff,@function
_Z22__device_stub__computefifffifffffffPfS_S_fffffffffff: # @_Z22_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
__global__ void foo(int *p) {
p[threadIdx.x] = threadIdx.x;
} | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MM... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
__global__ void foo(int *p) {
p[threadIdx.x] = threadIdx.x;
} | .file "tmpxft_0018f435_00000000-6_inter-group.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
__global__ void foo(int *p) {
p[threadIdx.x] = threadIdx.x;
} | #include <hip/hip_runtime.h>
__global__ void foo(int *p) {
p[threadIdx.x] = threadIdx.x;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void foo(int *p) {
p[threadIdx.x] = threadIdx.x;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void foo(int *p) {
p[threadIdx.x] = threadIdx.x;
} | .text
.file "inter-group.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MM... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018f435_00000000-6_inter-group.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... | .text
.file "inter-group.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // 1D convolution example using CUDA C++
// Each block takes in a bunch of elements and computes a 1D convolution using multiple threads
#include <iostream>
// Global parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function and macro to handle CUDA erro... | code for sm_80
Function : _Z6conv1dPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ HF... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // 1D convolution example using CUDA C++
// Each block takes in a bunch of elements and computes a 1D convolution using multiple threads
#include <iostream>
// Global parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function and macro to handle CUDA erro... | .file "tmpxft_000055f7_00000000-6_conv1d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " at line "
#NO_APP
.text
.type _ZL11handleError9cudaErrorPKci, @function
_ZL11handleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi,... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // 1D convolution example using CUDA C++
// Each block takes in a bunch of elements and computes a 1D convolution using multiple threads
#include <iostream>
// Global parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function and macro to handle CUDA erro... | // 1D convolution example using CUDA C++
// Each block takes in a bunch of elements and computes a 1D convolution using multiple threads
#include <hip/hip_runtime.h>
#include <iostream>
// Global parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // 1D convolution example using CUDA C++
// Each block takes in a bunch of elements and computes a 1D convolution using multiple threads
#include <hip/hip_runtime.h>
#include <iostream>
// Global parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6conv1dPfS_
.globl _Z6conv1dPfS_
.p2align 8
.type _Z6conv1dPfS_,@function
_Z6conv1dPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s4, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // 1D convolution example using CUDA C++
// Each block takes in a bunch of elements and computes a 1D convolution using multiple threads
#include <hip/hip_runtime.h>
#include <iostream>
// Global parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function ... | .text
.file "conv1d.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__conv1dPfS_ # -- Begin function _Z21__device_stub__conv1dPfS_
.p2align 4, 0x90
.... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6conv1dPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ HF... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6conv1dPfS_
.globl _Z6conv1dPfS_
.p2align 8
.type _Z6conv1dPfS_,@function
_Z6conv1dPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s4, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000055f7_00000000-6_conv1d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " at line "
#NO_APP
.text
.type _ZL11handleError9cudaErrorPKci, @function
_ZL11handleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi,... | .text
.file "conv1d.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__conv1dPfS_ # -- Begin function _Z21__device_stub__conv1dPfS_
.p2align 4, 0x90
.... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void NmDistanceKernel(int b,int n,const float * xyz,int m,const float * xyz2,float * result,int * result_i){
const int batch=512;
__shared__ float buf[batch*2];
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int k2=0;k2<m;k2+=batch){
int end_k=min(m,k2+batch)-k2;
for (int j=threadIdx.x;j... | .file "tmpxft_000041d8_00000000-6_NmDistanceKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void NmDistanceKernel(int b,int n,const float * xyz,int m,const float * xyz2,float * result,int * result_i){
const int batch=512;
__shared__ float buf[batch*2];
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int k2=0;k2<m;k2+=batch){
int end_k=min(m,k2+batch)-k2;
for (int j=threadIdx.x;j... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NmDistanceKernel(int b,int n,const float * xyz,int m,const float * xyz2,float * result,int * result_i){
const int batch=512;
__shared__ float buf[batch*2];
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int k2=0;k2<m;k2+=batch){
int end_k=min(m,k2+batch)... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NmDistanceKernel(int b,int n,const float * xyz,int m,const float * xyz2,float * result,int * result_i){
const int batch=512;
__shared__ float buf[batch*2];
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int k2=0;k2<m;k2+=batch){
int end_k=min(m,k2+batch)... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16NmDistanceKerneliiPKfiS0_PfPi
.globl _Z16NmDistanceKerneliiPKfiS0_PfPi
.p2align 8
.type _Z16NmDistanceKerneliiPKfiS0_PfPi,@function
_Z16NmDistanceKerneliiPKfiS0_PfPi:
s_load_b32 s12, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s14, s12
s_cbranch_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void NmDistanceKernel(int b,int n,const float * xyz,int m,const float * xyz2,float * result,int * result_i){
const int batch=512;
__shared__ float buf[batch*2];
for (int i=blockIdx.x;i<b;i+=gridDim.x){
for (int k2=0;k2<m;k2+=batch){
int end_k=min(m,k2+batch)... | .text
.file "NmDistanceKernel.hip"
.globl _Z31__device_stub__NmDistanceKerneliiPKfiS0_PfPi # -- Begin function _Z31__device_stub__NmDistanceKerneliiPKfiS0_PfPi
.p2align 4, 0x90
.type _Z31__device_stub__NmDistanceKerneliiPKfiS0_PfPi,@function
_Z31__device_stub__NmDistanceKerneliiPKfiS0_PfPi: # @_Z31__device_stub__NmDist... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000041d8_00000000-6_NmDistanceKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... | .text
.file "NmDistanceKernel.hip"
.globl _Z31__device_stub__NmDistanceKerneliiPKfiS0_PfPi # -- Begin function _Z31__device_stub__NmDistanceKerneliiPKfiS0_PfPi
.p2align 4, 0x90
.type _Z31__device_stub__NmDistanceKerneliiPKfiS0_PfPi,@function
_Z31__device_stub__NmDistanceKerneliiPKfiS0_PfPi: # @_Z31__device_stub__NmDist... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<random>
#include<iostream>
size_t n_blocks = 20;
size_t n_threads = 20;
size_t vec_size = n_blocks * n_threads;
void fill_random(double* a, size_t vec_size)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<double> dis(0.0, 1000.0);
for(size_t k = 0; k < vec_size; ++k) {
*a++ = di... | code for sm_80
Function : _Z8add_elemPdS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<random>
#include<iostream>
size_t n_blocks = 20;
size_t n_threads = 20;
size_t vec_size = n_blocks * n_threads;
void fill_random(double* a, size_t vec_size)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<double> dis(0.0, 1000.0);
for(size_t k = 0; k < vec_size; ++k) {
*a++ = di... | .file "tmpxft_000b3d99_00000000-6_vector_add_scratch.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4757:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
ca... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<random>
#include<iostream>
size_t n_blocks = 20;
size_t n_threads = 20;
size_t vec_size = n_blocks * n_threads;
void fill_random(double* a, size_t vec_size)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<double> dis(0.0, 1000.0);
for(size_t k = 0; k < vec_size; ++k) {
*a++ = di... | #include <hip/hip_runtime.h>
#include<random>
#include<iostream>
size_t n_blocks = 20;
size_t n_threads = 20;
size_t vec_size = n_blocks * n_threads;
void fill_random(double* a, size_t vec_size)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<double> dis(0.0, 1000.0);
for(size_t k = 0; k... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<random>
#include<iostream>
size_t n_blocks = 20;
size_t n_threads = 20;
size_t vec_size = n_blocks * n_threads;
void fill_random(double* a, size_t vec_size)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<double> dis(0.0, 1000.0);
for(size_t k = 0; k... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8add_elemPdS_S_m
.globl _Z8add_elemPdS_S_m
.p2align 8
.type _Z8add_elemPdS_S_m,@function
_Z8add_elemPdS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<random>
#include<iostream>
size_t n_blocks = 20;
size_t n_threads = 20;
size_t vec_size = n_blocks * n_threads;
void fill_random(double* a, size_t vec_size)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<double> dis(0.0, 1000.0);
for(size_t k = 0; k... | .text
.file "vector_add_scratch.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin func... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8add_elemPdS_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8add_elemPdS_S_m
.globl _Z8add_elemPdS_S_m
.p2align 8
.type _Z8add_elemPdS_S_m,@function
_Z8add_elemPdS_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b3d99_00000000-6_vector_add_scratch.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4757:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
ca... | .text
.file "vector_add_scratch.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin func... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include "intermediateVelocity.h"
/**
* \namespace kernels
* \brief Con... | code for sm_80
Function : _ZN7kernels13update_rhs1_yEPdS0_S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x00000000000079... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include "intermediateVelocity.h"
/**
* \namespace kernels
* \brief Con... | .file "tmpxft_000a9144_00000000-6_intermediateVelocity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
a... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include "intermediateVelocity.h"
/**
* \namespace kernels
* \brief Con... | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include <hip/hip_runtime.h>
#include "intermediateVelocity.h"
/**
* \n... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include <hip/hip_runtime.h>
#include "intermediateVelocity.h"
/**
* \n... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _ZN7kernels9size_LHS1EPiS0_S0_S0_iiii
.globl _ZN7kernels9size_LHS1EPiS0_S0_S0_iiii
.p2align 8
.type _ZN7kernels9size_LHS1EPiS0_S0_S0_iiii,@function
_ZN7kernels9size_LHS1EPiS0_S0_S0_iiii:
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[12:13], s[... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /***************************************************************************//**
* \file intermediateVelocity.cu
* \author Christopher Minar (minarc@oregonstate.edu)
* \brief kernels to generate the right hand side for the initial velocity solve
*/
#include <hip/hip_runtime.h>
#include "intermediateVelocity.h"
/**
* \n... | .text
.file "intermediateVelocity.hip"
.globl _ZN7kernels24__device_stub__size_LHS1EPiS0_S0_S0_iiii # -- Begin function _ZN7kernels24__device_stub__size_LHS1EPiS0_S0_S0_iiii
.p2align 4, 0x90
.type _ZN7kernels24__device_stub__size_LHS1EPiS0_S0_S0_iiii,@function
_ZN7kernels24__device_stub__size_LHS1EPiS0_S0_S0_iiii: # @_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a9144_00000000-6_intermediateVelocity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
a... | .text
.file "intermediateVelocity.hip"
.globl _ZN7kernels24__device_stub__size_LHS1EPiS0_S0_S0_iiii # -- Begin function _ZN7kernels24__device_stub__size_LHS1EPiS0_S0_S0_iiii
.p2align 4, 0x90
.type _ZN7kernels24__device_stub__size_LHS1EPiS0_S0_S0_iiii,@function
_ZN7kernels24__device_stub__size_LHS1EPiS0_S0_S0_iiii: # @_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void clock_block(clock_t *d, clock_t clock_count) {
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count) {
clock_offset = clock64() - start_clock;
}
if (d) {
*d = clock_offset;
}
} | code for sm_80
Function : _Z11clock_blockPll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x000fca0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void clock_block(clock_t *d, clock_t clock_count) {
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count) {
clock_offset = clock64() - start_clock;
}
if (d) {
*d = clock_offset;
}
} | .file "tmpxft_0010e6b2_00000000-6_clock_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void clock_block(clock_t *d, clock_t clock_count) {
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count) {
clock_offset = clock64() - start_clock;
}
if (d) {
*d = clock_offset;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void clock_block(clock_t *d, clock_t clock_count) {
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count) {
clock_offset = clock64() - start_clock;
}
if (d) {
*d = clock_offset;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void clock_block(clock_t *d, clock_t clock_count) {
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count) {
clock_offset = clock64() - start_clock;
}
if (d) {
*d = clock_offset;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11clock_blockPll
.globl _Z11clock_blockPll
.p2align 8
.type _Z11clock_blockPll,@function
_Z11clock_blockPll:
s_load_b64 s[4:5], s[0:1], 0x8
s_getreg_b32 s6, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void clock_block(clock_t *d, clock_t clock_count) {
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count) {
clock_offset = clock64() - start_clock;
}
if (d) {
*d = clock_offset;
}
} | .text
.file "clock_block.hip"
.globl _Z26__device_stub__clock_blockPll # -- Begin function _Z26__device_stub__clock_blockPll
.p2align 4, 0x90
.type _Z26__device_stub__clock_blockPll,@function
_Z26__device_stub__clock_blockPll: # @_Z26__device_stub__clock_blockPll
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11clock_blockPll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x000fca0... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11clock_blockPll
.globl _Z11clock_blockPll
.p2align 8
.type _Z11clock_blockPll,@function
_Z11clock_blockPll:
s_load_b64 s[4:5], s[0:1], 0x8
s_getreg_b32 s6, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_waitcnt lgkmcnt(0)
v_cmp_lt_i64_e64 ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010e6b2_00000000-6_clock_block.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... | .text
.file "clock_block.hip"
.globl _Z26__device_stub__clock_blockPll # -- Begin function _Z26__device_stub__clock_blockPll
.p2align 4, 0x90
.type _Z26__device_stub__clock_blockPll,@function
_Z26__device_stub__clock_blockPll: # @_Z26__device_stub__clock_blockPll
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_hardswish(const float *input_, float *output_, int n_data_size_)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= n_data_size_)return;
if (input_[i] >= 3.0f)
{
output_[i] = input_[i];
}
else if (input_[i] <= -3.0f)
{
output_[i] = 0.0f;
}
else
{
output_[i] = input_[i... | code for sm_80
Function : _Z16kernel_hardswishPKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_hardswish(const float *input_, float *output_, int n_data_size_)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= n_data_size_)return;
if (input_[i] >= 3.0f)
{
output_[i] = input_[i];
}
else if (input_[i] <= -3.0f)
{
output_[i] = 0.0f;
}
else
{
output_[i] = input_[i... | .file "tmpxft_00039d8a_00000000-6_kernel_hardswish.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_hardswish(const float *input_, float *output_, int n_data_size_)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= n_data_size_)return;
if (input_[i] >= 3.0f)
{
output_[i] = input_[i];
}
else if (input_[i] <= -3.0f)
{
output_[i] = 0.0f;
}
else
{
output_[i] = input_[i... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_hardswish(const float *input_, float *output_, int n_data_size_)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= n_data_size_)return;
if (input_[i] >= 3.0f)
{
output_[i] = input_[i];
}
else if (input_[i] <= -3.0f)
{
output_[i] = 0.0f;
}... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_hardswish(const float *input_, float *output_, int n_data_size_)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= n_data_size_)return;
if (input_[i] >= 3.0f)
{
output_[i] = input_[i];
}
else if (input_[i] <= -3.0f)
{
output_[i] = 0.0f;
}... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kernel_hardswishPKfPfi
.globl _Z16kernel_hardswishPKfPfi
.p2align 8
.type _Z16kernel_hardswishPKfPfi,@function
_Z16kernel_hardswishPKfPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_hardswish(const float *input_, float *output_, int n_data_size_)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i >= n_data_size_)return;
if (input_[i] >= 3.0f)
{
output_[i] = input_[i];
}
else if (input_[i] <= -3.0f)
{
output_[i] = 0.0f;
}... | .text
.file "kernel_hardswish.hip"
.globl _Z31__device_stub__kernel_hardswishPKfPfi # -- Begin function _Z31__device_stub__kernel_hardswishPKfPfi
.p2align 4, 0x90
.type _Z31__device_stub__kernel_hardswishPKfPfi,@function
_Z31__device_stub__kernel_hardswishPKfPfi: # @_Z31__device_stub__kernel_hardswishPKfPfi
.cfi_startp... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16kernel_hardswishPKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16kernel_hardswishPKfPfi
.globl _Z16kernel_hardswishPKfPfi
.p2align 8
.type _Z16kernel_hardswishPKfPfi,@function
_Z16kernel_hardswishPKfPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00039d8a_00000000-6_kernel_hardswish.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... | .text
.file "kernel_hardswish.hip"
.globl _Z31__device_stub__kernel_hardswishPKfPfi # -- Begin function _Z31__device_stub__kernel_hardswishPKfPfi
.p2align 4, 0x90
.type _Z31__device_stub__kernel_hardswishPKfPfi,@function
_Z31__device_stub__kernel_hardswishPKfPfi: # @_Z31__device_stub__kernel_hardswishPKfPfi
.cfi_startp... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* compile with:
nvcc -fatbin -O2
-gencode=arch=compute_20,code=sm_20
-gencode=arch=compute_30,code=sm_30
-gencode=arch=compute_35,code=sm_35
-gencode=arch=compute_50,code=sm_50
-gencode=arch=compute_52,code=sm_52
-gencode=arch=compute_60,code=sm_60
-gencode=arch=compute_61,code=sm_61
-gencode=arch=compute_62,code=sm_6... | .file "tmpxft_0004683f_00000000-6_forcefield.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* compile with:
nvcc -fatbin -O2
-gencode=arch=compute_20,code=sm_20
-gencode=arch=compute_30,code=sm_30
-gencode=arch=compute_35,code=sm_35
-gencode=arch=compute_50,code=sm_50
-gencode=arch=compute_52,code=sm_52
-gencode=arch=compute_60,code=sm_60
-gencode=arch=compute_61,code=sm_61
-gencode=arch=compute_62,code=sm_6... | #include <hip/hip_runtime.h>
/* compile with:
nvcc -fatbin -O2
-gencode=arch=compute_20,code=sm_20
-gencode=arch=compute_30,code=sm_30
-gencode=arch=compute_35,code=sm_35
-gencode=arch=compute_50,code=sm_50
-gencode=arch=compute_52,code=sm_52
-gencode=arch=compute_60,code=sm_60
-gencode=arch=compute_61,code=sm_61
-genc... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/* compile with:
nvcc -fatbin -O2
-gencode=arch=compute_20,code=sm_20
-gencode=arch=compute_30,code=sm_30
-gencode=arch=compute_35,code=sm_35
-gencode=arch=compute_50,code=sm_50
-gencode=arch=compute_52,code=sm_52
-gencode=arch=compute_60,code=sm_60
-gencode=arch=compute_61,code=sm_61
-genc... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected calc
.globl calc
.p2align 8
.type calc,@function
calc:
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x3c
s_mov_b32 s8, s15
v_mov_b32_e32 v3, 0
s_mov_b32 s24, exec_lo
v_mov_b32_e32... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/* compile with:
nvcc -fatbin -O2
-gencode=arch=compute_20,code=sm_20
-gencode=arch=compute_30,code=sm_30
-gencode=arch=compute_35,code=sm_35
-gencode=arch=compute_50,code=sm_50
-gencode=arch=compute_52,code=sm_52
-gencode=arch=compute_60,code=sm_60
-gencode=arch=compute_61,code=sm_61
-genc... | .text
.file "forcefield.hip"
.globl __device_stub__calc # -- Begin function __device_stub__calc
.p2align 4, 0x90
.type __device_stub__calc,@function
__device_stub__calc: # @__device_stub__calc
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 8... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004683f_00000000-6_forcefield.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "forcefield.hip"
.globl __device_stub__calc # -- Begin function __device_stub__calc
.p2align 4, 0x90
.type __device_stub__calc,@function
__device_stub__calc: # @__device_stub__calc
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 8... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(Hand... | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFM... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(Hand... | .file "tmpxft_001053eb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " line "
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3800:
.cfi_startproc
testl %edi, %edi... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err)(Hand... | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#def... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#def... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
v_cvt_f32_i32_e32 v0, s14
v_cvt_f32_i32_e32 v1, s15
s_load_b32 s3, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | insti... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <iostream>
#include <string>
#include <fstream>
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString( err ) << " in " << file << " line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#def... | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFM... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPi
.globl _Z6kernelPi
.p2align 8
.type _Z6kernelPi,@function
_Z6kernelPi:
v_cvt_f32_i32_e32 v0, s14
v_cvt_f32_i32_e32 v1, s15
s_load_b32 s3, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | insti... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001053eb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " line "
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3800:
.cfi_startproc
testl %edi, %edi... | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPi # -- Begin function _Z21__device_stub__kernelPi
.p2align 4, 0x90
.type... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void iota(int const size, int *data, int const value)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
data[idx] = idx + value;
} | code for sm_80
Function : _Z4iotaiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void iota(int const size, int *data, int const value)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
data[idx] = idx + value;
} | .file "tmpxft_000d9dbb_00000000-6_iota.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void iota(int const size, int *data, int const value)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
data[idx] = idx + value;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void iota(int const size, int *data, int const value)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
data[idx] = idx + value;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void iota(int const size, int *data, int const value)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
data[idx] = idx + value;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4iotaiPii
.globl _Z4iotaiPii
.p2align 8
.type _Z4iotaiPii,@function
_Z4iotaiPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(S... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void iota(int const size, int *data, int const value)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
data[idx] = idx + value;
} | .text
.file "iota.hip"
.globl _Z19__device_stub__iotaiPii # -- Begin function _Z19__device_stub__iotaiPii
.p2align 4, 0x90
.type _Z19__device_stub__iotaiPii,@function
_Z19__device_stub__iotaiPii: # @_Z19__device_stub__iotaiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rs... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4iotaiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4iotaiPii
.globl _Z4iotaiPii
.p2align 8
.type _Z4iotaiPii,@function
_Z4iotaiPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(S... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d9dbb_00000000-6_iota.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "iota.hip"
.globl _Z19__device_stub__iotaiPii # -- Begin function _Z19__device_stub__iotaiPii
.p2align 4, 0x90
.type _Z19__device_stub__iotaiPii,@function
_Z19__device_stub__iotaiPii: # @_Z19__device_stub__iotaiPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rs... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_image2D1C_ConvolveColumn(float* img, int n_x, int n_y, short k, float *kernel, float* out)
{
// Find index of current thread
int idx_x = blockIdx.x * blockDim.x + threadIdx.x;
int idx_y = blockIdx.y * blockDim.y + threadIdx.y;
if (idx_x>=n_x) return;
if (idx_y>=n_y) return;
... | code for sm_80
Function : _Z31kernel_image2D1C_ConvolveColumnPfiisS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_image2D1C_ConvolveColumn(float* img, int n_x, int n_y, short k, float *kernel, float* out)
{
// Find index of current thread
int idx_x = blockIdx.x * blockDim.x + threadIdx.x;
int idx_y = blockIdx.y * blockDim.y + threadIdx.y;
if (idx_x>=n_x) return;
if (idx_y>=n_y) return;
... | .file "tmpxft_00129092_00000000-6_kernel_image2D1C_ConvolveColumn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatB... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_image2D1C_ConvolveColumn(float* img, int n_x, int n_y, short k, float *kernel, float* out)
{
// Find index of current thread
int idx_x = blockIdx.x * blockDim.x + threadIdx.x;
int idx_y = blockIdx.y * blockDim.y + threadIdx.y;
if (idx_x>=n_x) return;
if (idx_y>=n_y) return;
... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_image2D1C_ConvolveColumn(float* img, int n_x, int n_y, short k, float *kernel, float* out)
{
// Find index of current thread
int idx_x = blockIdx.x * blockDim.x + threadIdx.x;
int idx_y = blockIdx.y * blockDim.y + threadIdx.y;
if (idx_x>=n_x) ret... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_image2D1C_ConvolveColumn(float* img, int n_x, int n_y, short k, float *kernel, float* out)
{
// Find index of current thread
int idx_x = blockIdx.x * blockDim.x + threadIdx.x;
int idx_y = blockIdx.y * blockDim.y + threadIdx.y;
if (idx_x>=n_x) ret... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31kernel_image2D1C_ConvolveColumnPfiisS_S_
.globl _Z31kernel_image2D1C_ConvolveColumnPfiisS_S_
.p2align 8
.type _Z31kernel_image2D1C_ConvolveColumnPfiisS_S_,@function
_Z31kernel_image2D1C_ConvolveColumnPfiisS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_image2D1C_ConvolveColumn(float* img, int n_x, int n_y, short k, float *kernel, float* out)
{
// Find index of current thread
int idx_x = blockIdx.x * blockDim.x + threadIdx.x;
int idx_y = blockIdx.y * blockDim.y + threadIdx.y;
if (idx_x>=n_x) ret... | .text
.file "kernel_image2D1C_ConvolveColumn.hip"
.globl _Z46__device_stub__kernel_image2D1C_ConvolveColumnPfiisS_S_ # -- Begin function _Z46__device_stub__kernel_image2D1C_ConvolveColumnPfiisS_S_
.p2align 4, 0x90
.type _Z46__device_stub__kernel_image2D1C_ConvolveColumnPfiisS_S_,@function
_Z46__device_stub__kernel_imag... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z31kernel_image2D1C_ConvolveColumnPfiisS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.Y ; /* 0x0000000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31kernel_image2D1C_ConvolveColumnPfiisS_S_
.globl _Z31kernel_image2D1C_ConvolveColumnPfiisS_S_
.p2align 8
.type _Z31kernel_image2D1C_ConvolveColumnPfiisS_S_,@function
_Z31kernel_image2D1C_ConvolveColumnPfiisS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00129092_00000000-6_kernel_image2D1C_ConvolveColumn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatB... | .text
.file "kernel_image2D1C_ConvolveColumn.hip"
.globl _Z46__device_stub__kernel_image2D1C_ConvolveColumnPfiisS_S_ # -- Begin function _Z46__device_stub__kernel_image2D1C_ConvolveColumnPfiisS_S_
.p2align 4, 0x90
.type _Z46__device_stub__kernel_image2D1C_ConvolveColumnPfiisS_S_,@function
_Z46__device_stub__kernel_imag... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<time.h>
#include<stdio.h>
typedef unsigned long long Dtype;
__global__ void VecAdd(Dtype** A, int* N, unsigned long long* d_time, Dtype* xj, Dtype* xi)
{
Dtype *j = *A;
unsigned int start_t, end_t;
//for (int it=0; it < *N; it++)
j=*(Dtype **)j;
*xi=*j;
start_t = clock();
//for (int it=0; it < *N*5; it+... | code for sm_80
Function : _Z6VecAddPPyPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<time.h>
#include<stdio.h>
typedef unsigned long long Dtype;
__global__ void VecAdd(Dtype** A, int* N, unsigned long long* d_time, Dtype* xj, Dtype* xi)
{
Dtype *j = *A;
unsigned int start_t, end_t;
//for (int it=0; it < *N; it++)
j=*(Dtype **)j;
*xi=*j;
start_t = clock();
//for (int it=0; it < *N*5; it+... | .file "tmpxft_0005d8f4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<time.h>
#include<stdio.h>
typedef unsigned long long Dtype;
__global__ void VecAdd(Dtype** A, int* N, unsigned long long* d_time, Dtype* xj, Dtype* xi)
{
Dtype *j = *A;
unsigned int start_t, end_t;
//for (int it=0; it < *N; it++)
j=*(Dtype **)j;
*xi=*j;
start_t = clock();
//for (int it=0; it < *N*5; it+... | #include <hip/hip_runtime.h>
#include<time.h>
#include<stdio.h>
typedef unsigned long long Dtype;
__global__ void VecAdd(Dtype** A, int* N, unsigned long long* d_time, Dtype* xj, Dtype* xi)
{
Dtype *j = *A;
unsigned int start_t, end_t;
//for (int it=0; it < *N; it++)
j=*(Dtype **)j;
*xi=*j;
start_t = clock();
//... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<time.h>
#include<stdio.h>
typedef unsigned long long Dtype;
__global__ void VecAdd(Dtype** A, int* N, unsigned long long* d_time, Dtype* xj, Dtype* xi)
{
Dtype *j = *A;
unsigned int start_t, end_t;
//for (int it=0; it < *N; it++)
j=*(Dtype **)j;
*xi=*j;
start_t = clock();
//... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPPyPiS_S_S_
.globl _Z6VecAddPPyPiS_S_S_
.p2align 8
.type _Z6VecAddPPyPiS_S_S_,@function
_Z6VecAddPPyPiS_S_S_:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<time.h>
#include<stdio.h>
typedef unsigned long long Dtype;
__global__ void VecAdd(Dtype** A, int* N, unsigned long long* d_time, Dtype* xj, Dtype* xi)
{
Dtype *j = *A;
unsigned int start_t, end_t;
//for (int it=0; it < *N; it++)
j=*(Dtype **)j;
*xi=*j;
start_t = clock();
//... | .text
.file "kernel.hip"
.globl _Z21__device_stub__VecAddPPyPiS_S_S_ # -- Begin function _Z21__device_stub__VecAddPPyPiS_S_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPPyPiS_S_S_,@function
_Z21__device_stub__VecAddPPyPiS_S_S_: # @_Z21__device_stub__VecAddPPyPiS_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPPyPiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff0... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPPyPiS_S_S_
.globl _Z6VecAddPPyPiS_S_S_
.p2align 8
.type _Z6VecAddPPyPiS_S_S_,@function
_Z6VecAddPPyPiS_S_S_:
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
v_mov_b32_e32 v4, 0
s_waitcnt lgkmcnt(0... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005d8f4_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "kernel.hip"
.globl _Z21__device_stub__VecAddPPyPiS_S_S_ # -- Begin function _Z21__device_stub__VecAddPPyPiS_S_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPPyPiS_S_S_,@function
_Z21__device_stub__VecAddPPyPiS_S_S_: # @_Z21__device_stub__VecAddPPyPiS_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <vector>
#include <iostream>
#define cudaErrCheck(code) if (code != cudaSuccess) throw CudaException{code, __FILE__, __LINE__}
struct CudaException
{
cudaError_t code;
const char * file;
int line;
const char * what() const noexcept { return cudaGetErrorString(code); }
};
__global__ void kernel(int * x, size_t... | code for sm_80
Function : _Z6kernelPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e2800000025... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <vector>
#include <iostream>
#define cudaErrCheck(code) if (code != cudaSuccess) throw CudaException{code, __FILE__, __LINE__}
struct CudaException
{
cudaError_t code;
const char * file;
int line;
const char * what() const noexcept { return cudaGetErrorString(code); }
};
__global__ void kernel(int * x, size_t... | .file "tmpxft_0017e91e_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnreg... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <vector>
#include <iostream>
#define cudaErrCheck(code) if (code != cudaSuccess) throw CudaException{code, __FILE__, __LINE__}
struct CudaException
{
cudaError_t code;
const char * file;
int line;
const char * what() const noexcept { return cudaGetErrorString(code); }
};
__global__ void kernel(int * x, size_t... | #include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#define cudaErrCheck(code) if (code != hipSuccess) throw CudaException{code, __FILE__, __LINE__}
struct CudaException
{
hipError_t code;
const char * file;
int line;
const char * what() const noexcept { return hipGetErrorString(code); }
};
__global__ v... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#define cudaErrCheck(code) if (code != hipSuccess) throw CudaException{code, __FILE__, __LINE__}
struct CudaException
{
hipError_t code;
const char * file;
int line;
const char * what() const noexcept { return hipGetErrorString(code); }
};
__global__ v... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPim
.globl _Z6kernelPim
.p2align 8
.type _Z6kernelPim,@function
_Z6kernelPim:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu ins... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <iostream>
#define cudaErrCheck(code) if (code != hipSuccess) throw CudaException{code, __FILE__, __LINE__}
struct CudaException
{
hipError_t code;
const char * file;
int line;
const char * what() const noexcept { return hipGetErrorString(code); }
};
__global__ v... | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPim # -- Begin function _Z21__device_stub__kernelPim
.p2align 4, 0x90
.typ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e2800000025... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPim
.globl _Z6kernelPim
.p2align 8
.type _Z6kernelPim,@function
_Z6kernelPim:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu ins... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017e91e_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4036:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnreg... | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPim # -- Begin function _Z21__device_stub__kernelPim
.p2align 4, 0x90
.typ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
using namespace std;
__global__ void vec_add(float *A, float *B, float *C, int n_array){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<n_array){
C[idx] = A[idx] + B[idx];
}
}
int main(){
int ngpus=2;
cudaGetDeviceCount(&ngpus);
printf("Number of GPUs: %i\n", ngpus);
floa... | code for sm_80
Function : _Z7vec_addPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
using namespace std;
__global__ void vec_add(float *A, float *B, float *C, int n_array){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<n_array){
C[idx] = A[idx] + B[idx];
}
}
int main(){
int ngpus=2;
cudaGetDeviceCount(&ngpus);
printf("Number of GPUs: %i\n", ngpus);
floa... | .file "tmpxft_001940c3_00000000-6_vec_add_multi_gpus.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
ca... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
using namespace std;
__global__ void vec_add(float *A, float *B, float *C, int n_array){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<n_array){
C[idx] = A[idx] + B[idx];
}
}
int main(){
int ngpus=2;
cudaGetDeviceCount(&ngpus);
printf("Number of GPUs: %i\n", ngpus);
floa... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
__global__ void vec_add(float *A, float *B, float *C, int n_array){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<n_array){
C[idx] = A[idx] + B[idx];
}
}
int main(){
int ngpus=2;
hipGetDeviceCount(&ngpus);
printf("Number ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
using namespace std;
__global__ void vec_add(float *A, float *B, float *C, int n_array){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if(idx<n_array){
C[idx] = A[idx] + B[idx];
}
}
int main(){
int ngpus=2;
hipGetDeviceCount(&ngpus);
printf("Number ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7vec_addPfS_S_i
.globl _Z7vec_addPfS_S_i
.p2align 8
.type _Z7vec_addPfS_S_i,@function
_Z7vec_addPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_... |
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